Skip to content

02-Protocol.md

Latest commit

 

History

History
147 lines (99 loc) · 5.53 KB

02-Protocol.md

File metadata and controls

147 lines (99 loc) · 5.53 KB

📝 Chapter 2: Protocol Details and Modes

If we've handled the physical connections (wires), let's look at how data flows over these wires.

SPI is less of a "communication" protocol and more of a "Data Exchange" protocol. The Master and Slave are like two players putting their cards on the table at the same time.

2.1 Shift Register Logic (Data Exchange) 🔄

At the heart of SPI lies the Shift Register. The Master and Slave virtually form a single circular loop.

  1. The Loop: While the Master sends 1 bit (via MOSI), the Slave simultaneously sends 1 bit to the Master (via MISO).
  2. Clock Pulse: Data shifts one step with each SCK pulse.
  3. Result: At the end of 8 Clock Pulses, the data in the Master has moved to the Slave, and the data in the Slave has moved to the Master.

⚠️ Field Note (Critical): There is no such thing as "Read Only" in SPI! If you want to read data from a Slave, you must send something to it (usually a blank "Dummy Byte" like 0x00 or 0xFF). Because the Master generates the clock; if the Master doesn't send data (doesn't generate clock), the Slave cannot respond.

graph LR
    subgraph MASTER
    MR[Shift Register]
    end
    
    subgraph SLAVE
    SR[Shift Register]
    end

    MR -- MOSI (Send Bit) --> SR
    SR -- MISO (Send Bit) --> MR
    
    style MASTER fill:#e3f2fd,stroke:#1565c0
    style SLAVE fill:#fff3e0,stroke:#e65100
Loading

2.2 SPI Modes: The CPOL and CPHA Nightmare 😱

In I2C, the standard is singular. In SPI, there are 4 different variations (Modes). If Master and Slave do not speak in the same mode, the data will be garbage.

These modes are determined by two parameters:

1. CPOL (Clock Polarity) - Idle State of Clock

  • CPOL = 0: The clock signal is LOW (0V) when idle. It goes High for the pulse.
  • CPOL = 1: The clock signal is HIGH (3.3V) when idle. It goes Low for the pulse.

2. CPHA (Clock Phase) - Sampling Time

  • CPHA = 0: Data is sampled on the Leading Edge (First Edge) of the clock.
  • CPHA = 1: Data is sampled on the Trailing Edge (Second Edge) of the clock.

4 SPI Modes Table

SPI Mode CPOL CPHA Description
Mode 0 0 0 Most Common. Clock waits Low, reads on rise (leading edge).
Mode 1 0 1 Clock waits Low, reads on fall (trailing edge).
Mode 2 1 0 Clock waits High, reads on fall (leading edge).
Mode 3 1 1 Second Most Common. Clock waits High, reads on rise (trailing edge).

How do I know? Look at the "Timing Diagram" section in the sensor's datasheet. If the clock line starts up high, it's CPOL=1; if it starts low, it's CPOL=0.

SPI Modes Timing Diagram

2.3 Daisy Chain 🔗

What if we run out of pins on the Master device? In standard connection, a separate CS pin was required for each Slave. With Daisy Chain, we can drive dozens of devices using a single CS pin.

Connection Logic:

  • Master MOSI -> Slave 1 MOSI
  • Slave 1 MISO -> Slave 2 MOSI
  • Slave 2 MISO -> Master MISO
  • All SCK and CS pins are connected in parallel.

Data Transfer (Train Wagon Logic): Imagine you have 3 separate 8-bit LED drivers. A giant 24-bit Shift Register is formed in total.

  • The first byte sent by the Master goes to the device at the very end of the chain.
  • Just like a water pipe; water entering first comes out at the very end of the pipe.
graph LR
    subgraph M [Master]
    M_MOSI[MOSI]
    M_MISO[MISO]
    end

    subgraph S1 [Slave 1]
    S1_IN[DIN]
    S1_OUT[DOUT]
    end

    subgraph S2 [Slave 2]
    S2_IN[DIN]
    S2_OUT[DOUT]
    end
    
    M_MOSI --> S1_IN
    S1_OUT --> S2_IN
    S2_OUT --> M_MISO

    style M fill:#e3f2fd
    style S1 fill:#fff9c4
    style S2 fill:#fff9c4
Loading

Disadvantage: If one device fails, the chain breaks. Also, managing the protocol in software is more complex. Not every device supports Daisy Chain!

2.4 Protocol Overhead and Blind Communication

The biggest difference between SPI and I2C is the lack of a "Feedback" (Acknowledgement) mechanism.

  • I2C: Master sends a byte, Slave says "ACK" (Received). Master knows the Slave is there.
  • SPI: Master sends the data, but does not know if the Slave received it, or even if the Slave is there at all.
  • Result: SPI is "Blind" communication. If the Slave is broken or the cable is cut, the Master constantly reads 0x00 or 0xFF but receives no error code.

✅ Summary

  1. Dummy Byte: You must send blank data (0x00) to receive data from the Slave.
  2. Mode Mismatch: Master and Slave CPOL/CPHA settings must be exactly the same. (Read the Datasheet!).
  3. Error Checking: Since there is no hardware ACK, checking data integrity via software (CRC or specific start bytes) is a good practice.
Chapter 1: Physical Layer Back to Menu Chapter 3: ESP32 Integration