ALICE 3 TRK: add simplified-realistic OT barrel layout

New kSimplifiedRealistic layoutMLOT option (TRKOTLayerRealistic): detailed
OT module stack (chips, FPC, cold plate, ZIF connector, SMD capacitors,
brackets, cooling pipe), two-row staves with active overlap, and a barrel
built in four parts (two eta half-barrels, each split azimuthally). The
ML layers and the original kSegmented OT are kept as comparison baselines.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Author: bulukutlu

Detectors/Upgrades/ALICE3/TRK/README.md

@@ -15,7 +15,7 @@ Configurables for various sub-detectors are presented in the following Table:
 | Subsystem          | Available options                                       | Comments                                                         |
 | ------------------ | ------------------------------------------------------- | ---------------------------------------------------------------- |
 | `TRKBase.layoutVD` | `kIRIS4` (default), `kIRISFullCyl`, `kIRIS5`, `kIRIS4a` | [link to definitions](./base/include/TRKBase/TRKBaseParam.h) |
-| `TRKBase.layoutMLOT` | `kCylindrical`, `kSegmented` (default)     | `kSegmented` produces a Turbo layout for ML and a Staggered layout for OT                                                                 |
+| `TRKBase.layoutMLOT` | `kCylindrical`, `kSegmented` (default), `kSimplifiedRealistic` | `kCylindrical`: simple silicon tubes. `kSegmented`: Turbo ML + solid-module OT. `kSimplifiedRealistic`: same ML as `kSegmented`, but a detailed OT barrel (see below) |
 | `TRKBase.layoutSRV` | `kPeacockv1` (default), `kLOISymm` | `kLOISymm` produces radially symmetric service volumes, as used in the LoI |
 
 For example, a geometry with fully cylindrical tracker barrel (for all layers in VD, ML and OT) can be obtained by
@@ -26,7 +26,7 @@ o2-sim-serial-run5 -n 1 -g pythia8hi -m A3IP TRK FT3 TF3 \
 
 ## Custom Geometry Configuration
 
-The geometry of the ML and OT layers can be overridden by providing a custom plain-text configuration file via `TRKBase.configFile=filename.txt`. The parser interprets the file differently depending on the active `TRKBase.layoutMLOT` setting (`kCylindrical` or `kSegmented`).
+The geometry of the ML and OT layers can be overridden by providing a custom plain-text configuration file via `TRKBase.configFile=filename.txt`. The parser interprets the file differently depending on the active `TRKBase.layoutMLOT` setting (`kCylindrical`, or `kSegmented`/`kSimplifiedRealistic` which share the same syntax).
 
 ### General Syntax Rules
 * **Separators:** All columns **must** be separated by a single TAB (`\t`). Using spaces will result in a parsing error.
@@ -55,9 +55,9 @@ When `TRKBase.layoutMLOT=kCylindrical` is used, each layer requires a minimum of
 80.0	255.9	0.1
 ```
 
-### 2. Segmented Layout (`kSegmented`)
+### 2. Segmented / Simplified-Realistic Layout (`kSegmented`, `kSimplifiedRealistic`)
 
-When `TRKBase.layoutMLOT=kSegmented` is used, each layer requires a minimum of 5 base parameters to define the geometry. The parser distinguishes between Middle Layers (ML) and Outer Layers (OT) based on the sequential layer index.
+Both layouts use the same configuration-file syntax (only the OT geometry implementation differs). Each layer requires a minimum of 5 base parameters to define the geometry. The parser distinguishes between Middle Layers (ML) and Outer Layers (OT) based on the sequential layer index.
 
 * *(Note: The 5 base parameters map directly to: Inner Radius (`rInn`), Thickness (`thick`), Tilt Angle (`tiltAngle`), Number of Staves (`nStaves`), and Number of Modules per stave (`nMods`)).*
 
@@ -66,8 +66,9 @@ The first 5 valid lines are parsed as `TRKMLLayer` objects. These layers **requi
 * **Format:** `rInn` \t `thick` \t `tiltAngle` \t `nStaves` \t `nMods` \t `stagOffset` \t `[optional_mode]`
 
 **Outer Layers (OT) - Indices 5 and above**
-From the 6th valid line onwards, lines are parsed as `TRKOTLayer` objects. These layers do **not** have a staggering offset. The optional mode parameter shifts to the 6th column.
+From the 6th valid line onwards, lines are parsed as OT layer objects (`TRKOTLayer` for `kSegmented`, `TRKOTLayerRealistic` for `kSimplifiedRealistic`). These layers do **not** have a staggering offset. The optional mode parameter shifts to the 6th column.
 * **Format:** `rInn` \t `thick` \t `tiltAngle` \t `nStaves` \t `nMods` \t `[optional_mode]`
+* *(Note: for `kSimplifiedRealistic`, `nStaves` is recomputed internally from the average radius and stave width to guarantee the neighbour overlap; the value in the file is ignored for the OT.)*
 
 **Example for `kSegmented`:**
 
@@ -89,5 +90,17 @@ From the 6th valid line onwards, lines are parsed as `TRKOTLayer` objects. These
 80.0	0.01	0.0	56	22	1
 ```
 
+## Simplified-Realistic OT geometry (`kSimplifiedRealistic`)
+
+`kSimplifiedRealistic` keeps the ML layers identical to `kSegmented` but replaces the solid-silicon OT modules with a more detailed, but still simplified, description (`TRKOTLayerRealistic`). All tunable dimensions live in [`Specs.h`](./base/include/TRKBase/Specs.h) (`constants::OT`); values that depend on others are computed in the source.
+
+**Module** — a flush stack about the chip mid-plane: cold plate (carbon fibre), 8 pure-silicon chips (2 in φ × 4 in z, dead zones facing the outer module edges), FPC (Kapton+Cu), one ZIF connector centred on a short edge, SMD capacitors over the chip footprints (skipping any under the connector), and two mounting brackets on the cold plate.
+
+**Stave** — two module rows overlapping in φ (so each row's dead zone is covered by the other row's sensor) and offset in r, plus a cooling pipe between them.
+
+**Barrel** — each layer is built in **four parts**: two z-half-barrels (±η), each split azimuthally into two 180° halves cut on **perpendicular planes** (one horizontal, one vertical, matching the Peacock services). Neighbouring staves overlap (≥ 1 mm active double-coverage); the two azimuthal halves meet at a ~1 mm gap instead. The stave count is fixed (the gap is absorbed into a slightly larger internal overlap). The cooling pipe faces the larger radius on the inner two OT layers (R = 45, 60 cm) and the smaller radius on the flipped outer layer (R = 80 cm).
+
+The OT services (cables/cooling bundles, cold plates) are built by `TRKServices` for all layouts via `TRKBase.layoutSRV`.
+
 <!-- doxy
 /doxy -->

Detectors/Upgrades/ALICE3/TRK/base/include/TRKBase/Specs.h

@@ -71,7 +71,7 @@ namespace moduleMLOT /// same for ML and OT for the moment
 {                    /// TODO: account for different modules in case of changes
 namespace silicon
 {
-constexpr double thickness{100 * mu}; // thickness of the silicon (should be 10 um epitaxial layer + 90 um substrate)?
+constexpr double thickness{100 * mu}; // thickness of the silicon sensor (per OT spec §2.1; previously 50 um)
 } // namespace silicon
 namespace metalstack
 {
@@ -114,17 +114,66 @@ namespace OT
 {
 namespace halfstave
 {
-constexpr double width{moduleMLOT::width * 1}; // width of the half stave
-// constexpr double length{moduleMLOT::length * 20};                         // length of the halfstave
-constexpr double length{258 * cm};                                        // length of the halfstave, hardcoded to fit the implemented geometry
+constexpr double width{moduleMLOT::width * 1}; // width of the half stave (= one row width = FPC width = 52.2 mm)
+constexpr double length{258 * cm};             // legacy constant, not used directly in geometry assembly
 constexpr int nRows{static_cast<int>(width / moduleMLOT::chip::pitchX)};  // number of rows in the halfstave
 constexpr int nCols{static_cast<int>(length / moduleMLOT::chip::pitchZ)}; // number of columns in the halfstave
 } // namespace halfstave
 constexpr int nLayers{3};                                                 // number of layers in the OT
-constexpr double width{halfstave::width * 2};                             // width of the stave
+constexpr double width{halfstave::width * 2};                             // width of the stave (two rows)
 constexpr double length{halfstave::length};                               // length of the stave
 constexpr int nRows{static_cast<int>(width / moduleMLOT::chip::pitchX)};  // number of rows in the stave
 constexpr int nCols{static_cast<int>(length / moduleMLOT::chip::pitchZ)}; // number of columns in the stave
+constexpr int nModulesPerRow{11};                                         // modules along z in one row (spec §4.1)
+constexpr double interModuleGap{0.2 * mm};                                // z-gap between consecutive module FPCs (spec §4.2)
+
+// Detailed component dimensions (spec §2 and §7)
+namespace fpc
+{
+constexpr double length{116.8 * mm};    // z-extent (4 chips + gaps + edges)
+constexpr double width{52.2 * mm};     // phi-extent (2 chips + gap + edges)
+constexpr double thickness{0.200 * mm}; // r-extent; Kapton+Cu stack (spec §2.2)
+} // namespace fpc
+namespace coldPlate
+{
+constexpr double length{116.8 * mm};    // z-extent, same as FPC
+constexpr double width{47.2 * mm};     // phi-extent, narrower than FPC (chip active region only)
+constexpr double thickness{0.4 * mm};  // r-extent (spec §2.5)
+} // namespace coldPlate
+namespace connector
+{
+constexpr double width{25.0 * mm};     // phi-extent (long axis of ZIF connector)
+constexpr double length{10.0 * mm};     // z-extent
+constexpr double thickness{2.0 * mm};  // r-extent (spec §2.3)
+} // namespace connector
+namespace capacitor
+{
+constexpr double width{1.0 * mm};      // phi-extent
+constexpr double length{0.5 * mm};     // z-extent
+constexpr double thickness{0.3 * mm};  // r-extent (spec §2.4, unified size for 0201 and 0402)
+constexpr int perChip{5};              // 5 per chip → 40 per module
+} // namespace capacitor
+namespace bracket
+{
+constexpr double length{10.0 * mm};    // z-extent (spec §2.6)
+constexpr double width{5.0 * mm};      // phi-extent
+constexpr double thickness{8.0 * mm};  // r-extent, stand-off toward cooling pipe
+} // namespace bracket
+namespace coolingPipe
+{
+constexpr double rInner{0.4 * cm};       // inner radius: 4 mm
+constexpr double rOuter{0.5 * cm};       // outer radius: 5 mm (wall = 1 mm carbon fibre)
+constexpr double rLocalOffset{3.5 * cm}; // chip mid-plane → pipe axis, along local r
+} // namespace coolingPipe
+
+// Assembly parameters for the simplified-realistic OT (tunable)
+constexpr double sensorThickness{moduleMLOT::silicon::thickness}; // 100 um pure-silicon chip (no metal stack)
+constexpr double interChipGap{0.2 * mm};                          // gap between chips within a module
+constexpr double rowActiveOverlap{1.0 * mm};                      // active double-coverage between the two rows of a stave
+constexpr double halfBarrelChipGap{1.0 * mm};                     // chip-edge gap between the two azimuthal half-barrels
+constexpr double connectorZDepth{3.0 * cm};                       // connector centre, inset from the module short edge in z
+constexpr double bracketZDepth{3.0 * cm};                         // bracket centre, inset from the cold-plate short edge in z
+constexpr double barrelHalvesZGap{0.8 * cm};                      // z-gap between the two eta half-barrels
 } // namespace OT
 
 namespace apts /// parameters for the APTS response

Detectors/Upgrades/ALICE3/TRK/base/include/TRKBase/TRKBaseParam.h

@@ -30,6 +30,7 @@ enum eVDLayout {
 enum eMLOTLayout {
   kCylindrical = 0,
   kSegmented,
+  kSimplifiedRealistic,
 };
 
 enum eSrvLayout {

Detectors/Upgrades/ALICE3/TRK/simulation/include/TRKSimulation/TRKLayer.h

@@ -13,7 +13,6 @@
 #define ALICEO2_TRK_LAYER_H
 
 #include "TRKBase/Specs.h"
-#include "TRKBase/TRKBaseParam.h"
 #include <TGeoManager.h>
 
 #include <Rtypes.h>
@@ -77,8 +76,8 @@ class TRKSegmentedLayer : public TRKCylindricalLayer
   TGeoVolume* createSensor() override;
   TGeoVolume* createDeadzone();
   TGeoVolume* createMetalStack() override;
-  TGeoVolume* createChip();
-  TGeoVolume* createModule();
+  virtual TGeoVolume* createChip();
+  virtual TGeoVolume* createModule();
   virtual TGeoVolume* createStave() = 0;
   void createLayer(TGeoVolume* motherVolume) override = 0;
 
@@ -88,7 +87,6 @@ class TRKSegmentedLayer : public TRKCylindricalLayer
   int mNumberOfStaves;
   bool mIsFlipped = false;
 
-  // Fixed parameters for the layer, to be set based on the specifications of the chip and module
   static constexpr double sChipWidth = constants::moduleMLOT::chip::width;
   static constexpr double sChipLength = constants::moduleMLOT::chip::length;
   static constexpr double sDeadzoneWidth = constants::moduleMLOT::chip::passiveEdgeReadOut;
@@ -99,10 +97,8 @@ class TRKSegmentedLayer : public TRKCylindricalLayer
   // TGeo objects outside logical volumes can cause errors
   static constexpr float sLogicalVolumeThickness = 1.3;
 
-  // For the segmented layers, because of tilting and staggering the bounding radii can be different
-  // from the inner radius and inner radius + thickness.
-  // This function calculates the bounding radii based on the geometry of the stave and the tilt angle,
-  // to ensure that the layer volume is large enough to contain all the staves without overlaps.
+  // Bounding radii accounting for tilt/staggering, so the layer volume contains
+  // all staves without extrusions.
   virtual std::pair<float, float> getBoundingRadii(double staveWidth) const;
 
   ClassDefOverride(TRKSegmentedLayer, 0);
@@ -130,6 +126,7 @@ class TRKMLLayer : public TRKSegmentedLayer
   ClassDefOverride(TRKMLLayer, 0);
 };
 
+// Original (simplified) OT barrel: solid-silicon modules, cylindrically paved.
 class TRKOTLayer : public TRKSegmentedLayer
 {
  public:
@@ -146,15 +143,46 @@ class TRKOTLayer : public TRKSegmentedLayer
 
  private:
   static constexpr double sHalfStaveWidth = constants::OT::halfstave::width;
-  static constexpr double sInStaveOverlap = constants::moduleMLOT::gaps::outerEdgeLongSide + constants::moduleMLOT::chip::passiveEdgeReadOut + 0.1; // 1.5mm outer-edge + 1mm deadzone + 1mm (true) overlap
+  static constexpr double sInStaveOverlap = constants::moduleMLOT::gaps::outerEdgeLongSide + constants::moduleMLOT::chip::passiveEdgeReadOut + 0.1;
   static constexpr double sStaveWidth = constants::OT::width - sInStaveOverlap;
 
-  // Override to account for the staggering offset present in OT layers
   std::pair<float, float> getBoundingRadii(double staveWidth) const override;
 
   ClassDefOverride(TRKOTLayer, 0);
 };
 
+// Simplified-realistic OT barrel: detailed module stack (FPC, cold plate, ZIF
+// connector, SMD capacitors, mounting brackets, cooling pipe), two-row staves
+// with active overlap, and a barrel paved in four parts (two eta half-barrels,
+// each split azimuthally into two halves cut on perpendicular planes).
+// All tunable dimensions live in constants::OT; everything derived is computed
+// in the source.
+class TRKOTLayerRealistic : public TRKSegmentedLayer
+{
+ public:
+  TRKOTLayerRealistic() = default;
+  TRKOTLayerRealistic(int layerNumber, std::string layerName, float rInn, float tiltAngle, int numberOfStaves, int numberOfModules, float thickOrX2X0, MatBudgetParamMode mode);
+  ~TRKOTLayerRealistic() override = default;
+
+  TGeoVolume* createChip() override;
+  TGeoVolume* createModule() override;
+  TGeoVolume* createStave() override;
+  TGeoVolume* createHalfStave();
+  void createLayer(TGeoVolume* motherVolume) override;
+
+ private:
+  TGeoVolume* createFPC();
+  TGeoVolume* createColdPlate();
+  TGeoVolume* createCoolingPipe();
+  void addConnector(TGeoVolume* moduleVol, double rMid);
+  void addCapacitors(TGeoVolume* moduleVol, double rMid);
+  void addBrackets(TGeoVolume* moduleVol, double rMid);
+
+  std::pair<float, float> getBoundingRadii(double staveWidth) const override;
+
+  ClassDefOverride(TRKOTLayerRealistic, 0);
+};
+
 } // namespace trk
 } // namespace o2
 #endif // ALICEO2_TRK_LAYER_H