Some issues with the RISC-V backend

[emoon]

Hi,
I found some issues when using the RISC-V backend (tested with latest code on next branch)

Change the RISCV_CODE32 example code to
#define RISCV_CODE32 "\x33\x03\xf0\x41"

Platform: riscv32
Code:0x33 0x03 0xf0 0x41 
Disasm:
0x1000:	neg	t1, $� $�t6
	op_count: 2
		operands[0].type: REG = t1
		operands[1].type: REG = t6

notice the bad op_str above

	uint16_t regs_read[16]; ///< list of implicit registers read by this insn
	uint8_t regs_read_count; ///< number of implicit registers read by this insn

	uint16_t regs_write[20]; ///< list of implicit registers modified by this insn
	uint8_t regs_write_count; ///< number of implicit registers modified by this insn

Is not updated correctly by the backend (all values are zero) but using the details directly

	cs_riscv* riscv;
	cs_detail* detail;

	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
	if (ins->detail == NULL)
		return;

	riscv = &(ins->detail->riscv);
	detail = ins->detail;
	if (riscv->op_count)
		printf("\top_count: %u\n", riscv->op_count);

	for (i = 0; i < riscv->op_count; i++) {
           ...

Works as expected

[aquynh]

@fanfuqiang do you have any comments?

[emoon]

any update on this?

[Rot127]

Fixed with #2756

cstool -d riscv32 "\x33\x03\xf0\x41"
 0  33 03 f0 41  neg	t1, t6
	ID: 265 (sub)
	op_count: 2
		operands[0].type: REG = t1
		operands[0].access: WRITE
		operands[1].type: REG = t6
		operands[1].access: READ