SoC.out

#! /usr/bin/vvp
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x55e6e6cfaca0 .scope module, "SD_SPI_TB" "SD_SPI_TB" 2 5;
 .timescale -9 -12;
v0x55e6e6d1cb80_0 .net "DataClockRegister", 0 0, L_0x55e6e6d2d220;  1 drivers
v0x55e6e6d1cc40_0 .var "OuputDataRegister", 7 0;
v0x55e6e6d1cd00_0 .var "SPI_EnableRegister", 0 0;
v0x55e6e6d1ce20_0 .var *"_s8", 0 0; Local signal
v0x55e6e6d1cec0_0 .var "clk", 0 0;
E_0x55e6e6ce6d20 .event negedge, v0x55e6e6d1a8a0_0;
S_0x55e6e6cfae20 .scope begin, "TEST_CASE" "TEST_CASE" 2 31, 2 31 0, S_0x55e6e6cfaca0;
 .timescale -9 -12;
S_0x55e6e6cfafa0 .scope module, "uut" "SD" 2 9, 3 1 0, S_0x55e6e6cfaca0;
 .timescale -9 -12;
    .port_info 0 /INPUT 1 "MasterCLK"
    .port_info 1 /INPUT 1 "Reset"
    .port_info 2 /INPUT 1 "SPI_MISO"
    .port_info 3 /OUTPUT 1 "SPI_MOSI"
    .port_info 4 /OUTPUT 1 "SPI_CLK"
    .port_info 5 /OUTPUT 1 "SPI_CS"
    .port_info 6 /OUTPUT 1 "DataClockRegister"
    .port_info 7 /OUTPUT 8 "InputDataRegister"
    .port_info 8 /INPUT 8 "OuputDataRegister"
    .port_info 9 /INPUT 1 "SPI_EnableRegister"
    .port_info 10 /INPUT 1 "SPI_EnableCSRegister"
v0x55e6e6d1c170_0 .net "DataClockRegister", 0 0, L_0x55e6e6d2d220;  alias, 1 drivers
v0x55e6e6d1c230_0 .net "InputData", 7 0, v0x55e6e6d1aa20_0;  1 drivers
v0x55e6e6d1c2d0_0 .var "InputDataRegister", 7 0;
v0x55e6e6d1c370_0 .net "MasterCLK", 0 0, v0x55e6e6d1cec0_0;  1 drivers
v0x55e6e6d1c410_0 .net "OuputDataRegister", 7 0, v0x55e6e6d1cc40_0;  1 drivers
v0x55e6e6d1c4d0_0 .var "OutputData", 7 0;
L_0x7fcbed2ce1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1c590_0 .net "Reset", 0 0, L_0x7fcbed2ce1c8;  1 drivers
v0x55e6e6d1c630_0 .net "SPI_CLK", 0 0, L_0x55e6e6d2db30;  1 drivers
v0x55e6e6d1c6d0_0 .net "SPI_CS", 0 0, v0x55e6e6d1adb0_0;  1 drivers
L_0x7fcbed2ce258 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1c7a0_0 .net "SPI_EnableCSRegister", 0 0, L_0x7fcbed2ce258;  1 drivers
v0x55e6e6d1c870_0 .net "SPI_EnableRegister", 0 0, v0x55e6e6d1cd00_0;  1 drivers
L_0x7fcbed2ce210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1c940_0 .net "SPI_MISO", 0 0, L_0x7fcbed2ce210;  1 drivers
v0x55e6e6d1ca10_0 .net "SPI_MOSI", 0 0, L_0x55e6e6d2d730;  1 drivers
S_0x55e6e6cfb120 .scope module, "spi" "FullSPI" 3 22, 4 1 0, S_0x55e6e6cfafa0;
 .timescale -9 -12;
    .port_info 0 /OUTPUT 8 "InputData"
    .port_info 1 /OUTPUT 1 "DataClk"
    .port_info 2 /OUTPUT 1 "SPI_MOSI"
    .port_info 3 /OUTPUT 1 "SPI_CLK"
    .port_info 4 /OUTPUT 1 "SPI_CS"
    .port_info 5 /INPUT 8 "OutputData"
    .port_info 6 /INPUT 1 "SPI_MISO"
    .port_info 7 /INPUT 1 "MasterCLK"
    .port_info 8 /INPUT 1 "SPI_Enable"
    .port_info 9 /INPUT 1 "SPI_EnableCS"
L_0x55e6e6d2d220 .functor BUFZ 1, v0x55e6e6cf8170_0, C4<0>, C4<0>, C4<0>;
v0x55e6e6cf8170_0 .var "DataCLK", 0 0;
v0x55e6e6d1a8a0_0 .net "DataClk", 0 0, L_0x55e6e6d2d220;  alias, 1 drivers
v0x55e6e6d1a960_0 .var "InData", 7 0;
v0x55e6e6d1aa20_0 .var "InputData", 7 0;
v0x55e6e6d1ab00_0 .net "MasterCLK", 0 0, v0x55e6e6d1cec0_0;  alias, 1 drivers
v0x55e6e6d1ac10_0 .net "OutputData", 7 0, v0x55e6e6d1c4d0_0;  1 drivers
v0x55e6e6d1acf0_0 .net "SPI_CLK", 0 0, L_0x55e6e6d2db30;  alias, 1 drivers
v0x55e6e6d1adb0_0 .var "SPI_CS", 0 0;
v0x55e6e6d1ae70_0 .net "SPI_Enable", 0 0, v0x55e6e6d1cd00_0;  alias, 1 drivers
v0x55e6e6d1af30_0 .net "SPI_EnableCS", 0 0, L_0x7fcbed2ce258;  alias, 1 drivers
v0x55e6e6d1aff0_0 .var "SPI_InputCLK", 0 0;
v0x55e6e6d1b0b0_0 .net "SPI_MISO", 0 0, L_0x7fcbed2ce210;  alias, 1 drivers
v0x55e6e6d1b170_0 .net "SPI_MOSI", 0 0, L_0x55e6e6d2d730;  alias, 1 drivers
L_0x7fcbed2ce018 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1b230_0 .net/2u *"_s0", 31 0, L_0x7fcbed2ce018;  1 drivers
v0x55e6e6d1b310_0 .net *"_s10", 1 0, L_0x55e6e6d2d420;  1 drivers
L_0x7fcbed2ce0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1b3f0_0 .net *"_s13", 0 0, L_0x7fcbed2ce0a8;  1 drivers
L_0x7fcbed2ce0f0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1b4d0_0 .net/2u *"_s14", 1 0, L_0x7fcbed2ce0f0;  1 drivers
v0x55e6e6d1b5b0_0 .net *"_s16", 1 0, L_0x55e6e6d2d5c0;  1 drivers
v0x55e6e6d1b690_0 .net *"_s2", 31 0, L_0x55e6e6d2d010;  1 drivers
v0x55e6e6d1b770_0 .net *"_s20", 1 0, L_0x55e6e6d2d8b0;  1 drivers
L_0x7fcbed2ce138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1b850_0 .net *"_s23", 0 0, L_0x7fcbed2ce138;  1 drivers
L_0x7fcbed2ce180 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1b930_0 .net/2u *"_s24", 1 0, L_0x7fcbed2ce180;  1 drivers
v0x55e6e6d1ba10_0 .net *"_s26", 1 0, L_0x55e6e6d2d9f0;  1 drivers
L_0x7fcbed2ce060 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x55e6e6d1baf0_0 .net *"_s5", 28 0, L_0x7fcbed2ce060;  1 drivers
v0x55e6e6d1bbd0_0 .net *"_s6", 31 0, L_0x55e6e6d2d180;  1 drivers
v0x55e6e6d1bcb0_0 .net *"_s9", 0 0, L_0x55e6e6d2d330;  1 drivers
v0x55e6e6d1bd90_0 .var "count", 2 0;
v0x55e6e6d1be70_0 .var "outData", 7 0;
v0x55e6e6d1bf50_0 .var "spiCount", 7 0;
E_0x55e6e6ce62d0 .event posedge, v0x55e6e6d1aff0_0;
E_0x55e6e6ce7910 .event negedge, v0x55e6e6d1aff0_0;
E_0x55e6e6ce7ef0 .event posedge, v0x55e6e6d1ab00_0;
L_0x55e6e6d2d010 .concat [ 3 29 0 0], v0x55e6e6d1bd90_0, L_0x7fcbed2ce060;
L_0x55e6e6d2d180 .arith/sub 32, L_0x7fcbed2ce018, L_0x55e6e6d2d010;
L_0x55e6e6d2d330 .part/v v0x55e6e6d1be70_0, L_0x55e6e6d2d180, 1;
L_0x55e6e6d2d420 .concat [ 1 1 0 0], L_0x55e6e6d2d330, L_0x7fcbed2ce0a8;
L_0x55e6e6d2d5c0 .functor MUXZ 2, L_0x7fcbed2ce0f0, L_0x55e6e6d2d420, v0x55e6e6d1cd00_0, C4<>;
L_0x55e6e6d2d730 .part L_0x55e6e6d2d5c0, 0, 1;
L_0x55e6e6d2d8b0 .concat [ 1 1 0 0], v0x55e6e6d1aff0_0, L_0x7fcbed2ce138;
L_0x55e6e6d2d9f0 .functor MUXZ 2, L_0x7fcbed2ce180, L_0x55e6e6d2d8b0, v0x55e6e6d1cd00_0, C4<>;
L_0x55e6e6d2db30 .part L_0x55e6e6d2d9f0, 0, 1;
    .scope S_0x55e6e6cfb120;
T_0 ;
    %pushi/vec4 7, 0, 3;
    %store/vec4 v0x55e6e6d1bd90_0, 0, 3;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v0x55e6e6d1bf50_0, 0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x55e6e6d1aff0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x55e6e6cf8170_0, 0, 1;
    %end;
    .thread T_0;
    .scope S_0x55e6e6cfb120;
T_1 ;
    %wait E_0x55e6e6ce7ef0;
    %load/vec4 v0x55e6e6d1bf50_0;
    %pad/u 32;
    %cmpi/u 124, 0, 32;
    %jmp/0xz  T_1.0, 5;
    %load/vec4 v0x55e6e6d1bf50_0;
    %addi 1, 0, 8;
    %assign/vec4 v0x55e6e6d1bf50_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x55e6e6d1aff0_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %load/vec4 v0x55e6e6d1bf50_0;
    %pad/u 32;
    %cmpi/u 249, 0, 32;
    %jmp/0xz  T_1.2, 5;
    %load/vec4 v0x55e6e6d1bf50_0;
    %addi 1, 0, 8;
    %assign/vec4 v0x55e6e6d1bf50_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x55e6e6d1aff0_0, 0;
    %jmp T_1.3;
T_1.2 ;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x55e6e6d1bf50_0, 0;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x55e6e6d1aff0_0, 0;
T_1.3 ;
T_1.1 ;
    %jmp T_1;
    .thread T_1;
    .scope S_0x55e6e6cfb120;
T_2 ;
    %wait E_0x55e6e6ce7910;
    %load/vec4 v0x55e6e6d1bd90_0;
    %pad/u 32;
    %cmpi/e 7, 0, 32;
    %jmp/0xz  T_2.0, 4;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x55e6e6cf8170_0, 0;
    %load/vec4 v0x55e6e6d1a960_0;
    %assign/vec4 v0x55e6e6d1aa20_0, 0;
    %load/vec4 v0x55e6e6d1ac10_0;
    %assign/vec4 v0x55e6e6d1be70_0, 0;
    %load/vec4 v0x55e6e6d1af30_0;
    %load/vec4 v0x55e6e6d1ae70_0;
    %and;
    %flag_set/vec4 8;
    %jmp/0 T_2.2, 8;
    %pushi/vec4 0, 0, 1;
    %jmp/1 T_2.3, 8;
T_2.2 ; End of true expr.
    %pushi/vec4 1, 0, 1;
    %jmp/0 T_2.3, 8;
 ; End of false expr.
    %blend;
T_2.3;
    %assign/vec4 v0x55e6e6d1adb0_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %load/vec4 v0x55e6e6d1bd90_0;
    %pad/u 32;
    %cmpi/e 3, 0, 32;
    %jmp/0xz  T_2.4, 4;
    %pushi/vec4 0, 0, 1;
    %assign/vec4 v0x55e6e6cf8170_0, 0;
T_2.4 ;
T_2.1 ;
    %load/vec4 v0x55e6e6d1bd90_0;
    %addi 1, 0, 3;
    %assign/vec4 v0x55e6e6d1bd90_0, 0;
    %jmp T_2;
    .thread T_2;
    .scope S_0x55e6e6cfb120;
T_3 ;
    %wait E_0x55e6e6ce62d0;
    %load/vec4 v0x55e6e6d1b0b0_0;
    %ix/load 5, 0, 0;
    %pushi/vec4 7, 0, 32;
    %load/vec4 v0x55e6e6d1bd90_0;
    %pad/u 32;
    %sub;
    %ix/vec4 4;
    %assign/vec4/off/d v0x55e6e6d1a960_0, 4, 5;
    %jmp T_3;
    .thread T_3;
    .scope S_0x55e6e6cfafa0;
T_4 ;
    %wait E_0x55e6e6ce7ef0;
    %load/vec4 v0x55e6e6d1c870_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.0, 8;
    %load/vec4 v0x55e6e6d1c230_0;
    %assign/vec4 v0x55e6e6d1c2d0_0, 0;
    %load/vec4 v0x55e6e6d1c410_0;
    %assign/vec4 v0x55e6e6d1c4d0_0, 0;
T_4.0 ;
    %jmp T_4;
    .thread T_4;
    .scope S_0x55e6e6cfaca0;
T_5 ;
    %wait E_0x55e6e6ce6d20;
    %load/vec4 v0x55e6e6d1cc40_0;
    %addi 1, 0, 8;
    %assign/vec4 v0x55e6e6d1cc40_0, 0;
    %pushi/vec4 1, 0, 1;
    %assign/vec4 v0x55e6e6d1cd00_0, 0;
    %jmp T_5;
    .thread T_5;
    .scope S_0x55e6e6cfaca0;
T_6 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x55e6e6d1cec0_0, 0, 1;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v0x55e6e6d1cc40_0, 0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x55e6e6d1cd00_0, 0, 1;
    %end;
    .thread T_6;
    .scope S_0x55e6e6cfaca0;
T_7 ;
    %load/vec4 v0x55e6e6d1cec0_0;
    %inv;
    %store/vec4 v0x55e6e6d1ce20_0, 0, 1;
    %pushi/vec4 1000, 0, 64;
    %ix/vec4 4;
    %delayx 4;
    %load/vec4 v0x55e6e6d1ce20_0;
    %store/vec4 v0x55e6e6d1cec0_0, 0, 1;
    %jmp T_7;
    .thread T_7;
    .scope S_0x55e6e6cfaca0;
T_8 ;
    %fork t_1, S_0x55e6e6cfae20;
    %jmp t_0;
    .scope S_0x55e6e6cfae20;
t_1 ;
    %vpi_call 2 32 "$dumpfile", "SoC.vcd" {0 0 0};
    %vpi_call 2 33 "$dumpvars", 32'sb11111111111111111111111111111111, S_0x55e6e6cfafa0 {0 0 0};
    %delay 800000000, 0;
    %vpi_call 2 34 "$finish" {0 0 0};
    %end;
    .scope S_0x55e6e6cfaca0;
t_0 %join;
    %end;
    .thread T_8;
# The file index is used to find the file name in the following table.
:file_names 5;
    "N/A";
    "<interactive>";
    "Hardware/Peripheral_SD/SD_TB.v";
    "Hardware/Peripheral_SD/SD.v";
    "Hardware/Peripheral_SD/FullSPI.v";