In cloudFPGA (cF), the user application is referred to as a ROLE and is integrated along with a SHELL that abstracts the hardware components of the FPGA module.
The current role implements a set of functions that were developed as IP cores to support the test and the bring-up of the TCP, UDP and DDR4 components of the cF module FMKU2595 when equipped with a Xilinx FPGA XCKU060. This role is typically paired with the shell Kale.
A block diagram of the ROLE is depicted in Figure 1. It features:
- a UDP Shell Interface (USIF) core that handles the control flow interface between the SHELL and the ROLE. The main purpose of the USIF is to provide a placeholder for the opening of one or multiple port(s).
- a UDP Application Flash (UAF) core that implements a set of UDP-oriented tests.
- a TCP Shell Interface (TSIF) core that handles the control flow interface between the SHELL and the ROLE. The main purpose of the TSIF is to open port(s) for listening and for connecting to remote host(s).
- a TCP Application Flash (TAF) core that implements a set of TCP-oriented tests.
- a Memory Test Application (MTA) core that implements a memory test for the DDR4.
Figure-1: Block diagram of Bring-up Role
| Acronym | Description | File |
|---|---|---|
| SHELL | Interface to shell Kale. | Shell |
| Acronym | Description | File |
|---|---|---|
| TSIF | TCP Shell InterFace | tcp_shell_if |
| USIF | UDP Shell InterFace | udp_shell_if |
| TAF | TCP Application Flash | tcp_app_flash |
| UAF | UDP Application Flash | udp_app_flash |
| MTA | Memory Test Application | FIXME-TODO |