Trace CPU is a simulation mode of Gem5, which generates a trace based on the OoO core model. Instead of recording the absolute timestamp of individual instructions as in other normal trace format, the Trace CPU generate a elastic trace recording the dependence of instructions along with the execution order of the instruction. This would later allow a replay with a cache model to produce an accurate timing performance with the actual latency from memory.
It would be great if we can support this trace. Ask Gem5 to generate a trace and feed this trace to FlexiCAS, in order to evaluate speed performance for different cache architectures.
references:
Trace CPU is a simulation mode of Gem5, which generates a trace based on the OoO core model. Instead of recording the absolute timestamp of individual instructions as in other normal trace format, the Trace CPU generate a elastic trace recording the dependence of instructions along with the execution order of the instruction. This would later allow a replay with a cache model to produce an accurate timing performance with the actual latency from memory.
It would be great if we can support this trace. Ask Gem5 to generate a trace and feed this trace to FlexiCAS, in order to evaluate speed performance for different cache architectures.
references: