chore(ci): fix fmt, lockfile and clippy warnings

Signed-off-by: Zewei Yang <yangzewei@loongson.cn>

Author: yzewei

Cargo.lock

@@ -1,22 +1,20 @@
+use log::debug;
+use std::sync::atomic::{AtomicU64, Ordering};
 /// LoongArch IOCSR Mailbox and Control Registers
 ///
 /// This module provides emulation for LoongArch IOCSR (I/O Control and Status Register)
 /// mailbox system used for inter-processor communication.
-
 use std::sync::Arc;
-use std::sync::atomic::{AtomicU64, Ordering};
-use log::debug;
 
 /// Maximum Number of LoongArch vCpus supported
-const MAX_LOONGARCH_VCPUS:  usize = 16;
+const MAX_LOONGARCH_VCPUS: usize = 16;
 
 /// IOCSR Mailbox addresses (each 8 bytes apart)
 pub const LOONGARCH_IOCSR_MBUF0: u64 = 0x1020;
 pub const LOONGARCH_IOCSR_MBUF1: u64 = 0x1028;
 pub const LOONGARCH_IOCSR_MBUF2: u64 = 0x1030;
 pub const LOONGARCH_IOCSR_MBUF3: u64 = 0x1038;
 
-
 /// IOCSR Mailbox send command register
 pub const LOONGARCH_IOCSR_MBUF_SEND: u64 = 0x1048;
 
@@ -61,12 +59,14 @@ impl LoongArchIocsrState {
         Self {
             misc_func: AtomicU64::new(0),
             mailboxes: (0..count)
-                .map(|_| [
-                    AtomicU64::new(0),
-                    AtomicU64::new(0),
-                    AtomicU64::new(0),
-                    AtomicU64::new(0),
-                ])
+                .map(|_| {
+                    [
+                        AtomicU64::new(0),
+                        AtomicU64::new(0),
+                        AtomicU64::new(0),
+                        AtomicU64::new(0),
+                    ]
+                })
                 .collect(),
         }
     }
@@ -100,6 +100,7 @@ impl LoongArchIocsrState {
     /// Process a mailbox send command
     ///
     /// This function parses the MBUF_SEND register value and updates the target CPU's mailbox.
+    /// Currently used only for SMP support, which is disabled in single-vCPU mode.
     ///
     /// # Arguments
     /// * `value` - The 64-bit value written to MBUF_SEND register
@@ -113,13 +114,21 @@ impl LoongArchIocsrState {
     pub fn process_mbuf_send(&self, value: u64) -> Result<(), String> {
         // Extract fields from the value
         let target_cpu = ((value >> IOCSR_MBUF_SEND_CPU_SHIFT) & 0x3FFF) as usize;
-        let box_hi = ((value >> 3) & 1) != 0;
-        let box_lo = ((value >> 2) & 1) != 0;
-        let box_num = (box_lo as u32) ^ (box_hi as u32);
+        // Linux encodes mailbox selector as:
+        //   (IOCSR_MBUF_SEND_BOX_{LO,HI}(box) << IOCSR_MBUF_SEND_BOX_SHIFT)
+        // where BOX_LO(box)=(box<<1), BOX_HI(box)=((box<<1)+1).
+        // So the packed field is 3 bits: [box_num(2b), hi_low(1b)].
+        let box_sel = ((value >> IOCSR_MBUF_SEND_BOX_SHIFT) & 0x7) as u32;
+        let box_hi = (box_sel & 0x1) != 0;
+        let box_num = (box_sel >> 1) as usize;
         let data32 = ((value >> IOCSR_MBUF_SEND_BUF_SHIFT) & 0xFFFFFFFF) as u32;
         // Validate target CPU
         if target_cpu >= self.mailboxes.len() {
-            return Err(format!("Invalid target CPU: {} (max: {})", target_cpu, self.mailboxes.len() - 1));
+            return Err(format!(
+                "Invalid target CPU: {} (max: {})",
+                target_cpu,
+                self.mailboxes.len() - 1
+            ));
         }
         // Validate mailbox number
         if box_num >= 4 {
@@ -128,14 +137,14 @@ impl LoongArchIocsrState {
         // Update the target mailbox
         if box_hi {
             // Write high 32 bits
-            let current = self.read_mailbox(target_cpu, box_num as usize);
+            let current = self.read_mailbox(target_cpu, box_num);
             let new_val = (current & 0xFFFFFFFF) | ((data32 as u64) << 32);
-            self.write_mailbox(target_cpu, box_num as usize, new_val);
+            self.write_mailbox(target_cpu, box_num, new_val);
         } else {
             // Write low 32 bits
-            let current = self.read_mailbox(target_cpu, box_num as usize);
+            let current = self.read_mailbox(target_cpu, box_num);
             let new_val = (current & 0xFFFFFFFF00000000) | (data32 as u64);
-            self.write_mailbox(target_cpu, box_num as usize, new_val);
+            self.write_mailbox(target_cpu, box_num, new_val);
         }
         Ok(())
     }
@@ -168,7 +177,8 @@ pub fn process_iocsr_read(
     addr: u64,
     data: &mut [u8],
     iocsr_state: &Arc<LoongArchIocsrState>,
-    cpu_id: u8) -> IocsrReadResult {
+    cpu_id: u8,
+) -> IocsrReadResult {
     match (addr, data.len()) {
         (LOONGARCH_IOCSR_FEATURES, 4) => {
             // Feature flags: EXTIOI, CSRIPI, VM support
@@ -208,7 +218,8 @@ pub fn process_iocsr_write(
     addr: u64,
     data: &[u8],
     iocsr_state: &Arc<LoongArchIocsrState>,
-    cpu_id: u8) -> IocsrWriteResult {
+    cpu_id: u8,
+) -> IocsrWriteResult {
     match (addr, data.len()) {
         (LOONGARCH_IOCSR_MISC_FUNC, 8) => {
             // Miscellaneous function register

src/arch/src/loongarch64/linux/iocsr.rs

@@ -1,3 +1,3 @@
 pub mod efi;
+pub mod iocsr;
 pub mod regs;
-pub mod iocsr;

src/arch/src/loongarch64/linux/mod.rs

@@ -31,7 +31,7 @@ const CPUCFG3_KVM_CONSERVATIVE_MASK: u64 = 0x0000_fcff;
 const CPUCFG4_KVM_MASK: u64 = 0xffff_ffff;
 const CPUCFG5_KVM_MASK: u64 = 0xffff_ffff;
 
-const CPUCFG16_CACHE_CONFIG: u64 = 0xF;  // L1I, L1D, L2, L3 present
+const CPUCFG16_CACHE_CONFIG: u64 = 0xF; // L1I, L1D, L2, L3 present
 const CPUCFG17_L1I_MASK: u64 = ((5u64) << 24) | ((8u64) << 16) | ((4u64 - 1) << 0);
 const CPUCFG18_L1D_MASK: u64 = ((5u64) << 24) | ((8u64) << 16) | ((4u64 - 1) << 0);
 const CPUCFG19_L2_MASK: u64 = ((6u64) << 24) | ((9u64) << 16) | ((8u64 - 1) << 0);
@@ -94,11 +94,7 @@ pub fn setup_regs(
 
     debug!(
         "loongarch setup_regs: cpu_id={}, pc=0x{:x}, a0={}, a1=0x{:x}, a2=0x{:x}",
-        cpu_id,
-        regs.pc,
-        regs.gpr[4],
-        regs.gpr[5],
-        regs.gpr[6],
+        cpu_id, regs.pc, regs.gpr[4], regs.gpr[5], regs.gpr[6],
     );
     let mut cpucfg0 = [0_u8; 8];
     if vcpu.get_one_reg(CPUCFG0_REG_ID, &mut cpucfg0).is_ok() {

src/arch/src/loongarch64/linux/regs.rs

@@ -143,8 +143,11 @@ fn create_chosen_node<T: DeviceInfoForFDT + Clone + Debug>(
     // Only set stdout-path if we have a Serial device (not when using Virtio Console).
     // When using Virtio Console (hvc0), kernel uses the console= cmdline parameter instead.
     // When using Serial (ttyS0), we point FDT to the serial device node.
-    let has_serial = dev_info.keys().any(|(device_type, _)| device_type == &DeviceType::Serial);
-    let has_virtio_console = dev_info.keys()
+    let has_serial = dev_info
+        .keys()
+        .any(|(device_type, _)| device_type == &DeviceType::Serial);
+    let has_virtio_console = dev_info
+        .keys()
         .any(|(device_type, _)| matches!(device_type, DeviceType::Virtio(3))); // VIRTIO_ID_CONSOLE = 3
 
     if has_serial && !has_virtio_console {
@@ -157,22 +160,22 @@ fn create_chosen_node<T: DeviceInfoForFDT + Clone + Debug>(
         }
     }
     let stdout_path = if has_serial && !has_virtio_console {
-        dev_info.iter().find_map(|((device_type, _device_id), info)| {
-            if device_type == &DeviceType::Serial {
-                Some(format!("/serial@{:x}", info.addr()))
-            } else {
-                None
-            }
-        })
+        dev_info
+            .iter()
+            .find_map(|((device_type, _device_id), info)| {
+                if device_type == &DeviceType::Serial {
+                    Some(format!("/serial@{:x}", info.addr()))
+                } else {
+                    None
+                }
+            })
     } else {
         None
     };
 
     debug!(
         "loongarch chosen: has_serial={}, has_virtio_console={}, stdout_path={:?}",
-        has_serial,
-        has_virtio_console,
-        stdout_path,
+        has_serial, has_virtio_console, stdout_path,
     );
 
     if let Some(path) = &stdout_path {

src/devices/src/fdt/loongarch64.rs

@@ -11,7 +11,12 @@ use utils::eventfd::EventFd;
 use vmm_sys_util::ioctl::ioctl_with_ref;
 use vmm_sys_util::ioctl_iow_nr;
 
-ioctl_iow_nr!(KVM_INTERRUPT_LOONGARCH, kvm_bindings::KVMIO, 0x86, kvm_interrupt);
+ioctl_iow_nr!(
+    KVM_INTERRUPT_LOONGARCH,
+    kvm_bindings::KVMIO,
+    0x86,
+    kvm_interrupt
+);
 
 pub struct KvmLoongArchIrqChip {
     _ipi_fd: DeviceFd,
@@ -96,23 +101,17 @@ impl IrqChipT for KvmLoongArchIrqChip {
 
     fn set_irq(
         &self,
-        _irq_line: Option<u32>,
+        irq_line: Option<u32>,
         interrupt_evt: Option<&EventFd>,
     ) -> Result<(), DeviceError> {
-        //debug!("loongarch irqchip set_irq irq_line={:?}", _irq_line);
-        if let Some(interrupt_evt) = interrupt_evt {
-            if let Err(e) = interrupt_evt.write(1) {
-                error!("Failed to signal used queue: {e:?}");
-                return Err(DeviceError::FailedSignalingUsedQueue(e));
-            }
-            //debug!("loongarch irqchip eventfd write ok");
-        } else {
-            error!("EventFd not set up for irq line");
-            return Err(DeviceError::FailedSignalingUsedQueue(io::Error::new(
-                io::ErrorKind::NotFound,
-                "EventFd not set up for irq line".to_string(),
-            )));
+        //debug!("loongarch irqchip set_irq_state irq_line={:?}", irq_line);
+        // LoongArch mmio/serial path does not rely on irqfd registration.
+        // Inject via KVM_INTERRUPT (assert).
+        if let Err(e) = self.set_irq_state(irq_line, interrupt_evt, true) {
+            error!("Failed to set irq state: {e:?}");
+            return Err(e);
         }
+        //debug!("loongarch irqchip eventfd write ok");
         Ok(())
     }
 
@@ -132,11 +131,7 @@ impl IrqChipT for KvmLoongArchIrqChip {
             }
         };
 
-        let signed_irq = if active {
-            irq as i32
-        } else {
-            -(irq as i32)
-        };
+        let signed_irq = if active { irq as i32 } else { -(irq as i32) };
         let interrupt = kvm_interrupt {
             // KVM uapi exposes `irq` as u32, but LoongArch KVM casts it back to `int`
             // and uses the sign to distinguish assert vs deassert.

src/devices/src/legacy/kvmloongarchirqchip.rs

@@ -159,7 +159,11 @@ impl Serial {
         if let Some(intc) = &self.intc {
             intc.lock()
                 .unwrap()
-                .set_irq_state(self.irq_line, Some(&self.interrupt_evt), self.interrupt_active())
+                .set_irq_state(
+                    self.irq_line,
+                    Some(&self.interrupt_evt),
+                    self.interrupt_active(),
+                )
                 .map_err(|e| io::Error::new(io::ErrorKind::Other, format!("{e:?}")))?;
             return Ok(());
         }

src/devices/src/legacy/loongarch64/serial.rs

@@ -140,10 +140,11 @@ impl InterruptTransport {
             let _irq_sync = self.0.irq_sync.lock().unwrap();
             let old = self.status().fetch_or(status as usize, Ordering::SeqCst);
             if old == 0 {
-                self.intc()
-                    .lock()
-                    .unwrap()
-                    .set_irq_state(self.0.irq_line, Some(&self.0.event), true)?;
+                self.intc().lock().unwrap().set_irq_state(
+                    self.0.irq_line,
+                    Some(&self.0.event),
+                    true,
+                )?;
             }
             return Ok(());
         }
@@ -511,12 +512,12 @@ impl BusDevice for MmioTransport {
                                     .fetch_and(!(v as usize), Ordering::SeqCst);
                                 let new = old & !(v as usize);
                                 if old != 0 && new == 0 {
-                                    if let Err(e) = self
-                                        .interrupt
-                                        .intc()
-                                        .lock()
-                                        .unwrap()
-                                        .set_irq_state(self.interrupt.0.irq_line, Some(&self.interrupt.0.event), false)
+                                    if let Err(e) =
+                                        self.interrupt.intc().lock().unwrap().set_irq_state(
+                                            self.interrupt.0.irq_line,
+                                            Some(&self.interrupt.0.event),
+                                            false,
+                                        )
                                     {
                                         warn!(target: &self.interrupt.0.log_target, "Failed to deassert irq: {e:?}");
                                     }