From f3df335d51e6a1d92d24e8d869ecd97819a1c847 Mon Sep 17 00:00:00 2001
From: dinoplays <dinoplays21@gmail.com>
Date: Tue, 29 Oct 2024 16:23:31 +1100
Subject: [PATCH 1/5] Initial commit

---
 .../FFT_files/FFT_stream.out.sdc              |    0
 .../FFT_files/FFT_stream.qpf                  |    0
 .../FFT_files/README.md                       |    0
 .../FFT_files/async_fifo.qip                  |    0
 .../FFT_files/async_fifo.v                    |    0
 .../FFT_files/async_fifo_bb.v                 |    0
 .../FFT_files/display.sv                      |    0
 .../FFT_files/dstream.sv                      |    0
 .../FFT_files/fft_find_peak.sv                |    0
 .../FFT_files/fft_input_buffer.sv             |    0
 .../FFT_files/fft_mag_sq.sv                   |    0
 .../FFT_files/fft_pitch_detect.sv             |    0
 .../FFT_files/fft_pitch_detect_tb.sv          |    0
 .../FFT_files/impulse_plotter.py              |    0
 .../FFT_files/low_pass_conv.sv                |    0
 .../FFT_files/mic/adc_pll.ppf                 |    0
 .../FFT_files/mic/adc_pll.qip                 |    0
 .../FFT_files/mic/adc_pll.v                   |    0
 .../FFT_files/mic/adc_pll_bb.v                |    0
 .../FFT_files/mic/i2c_master.sv               |    0
 .../FFT_files/mic/i2c_pll.ppf                 |    0
 .../FFT_files/mic/i2c_pll.qip                 |    0
 .../FFT_files/mic/i2c_pll.v                   |    0
 .../FFT_files/mic/i2c_pll_bb.v                |    0
 .../FFT_files/mic/mic_load.sv                 |    0
 .../FFT_files/mic/set_audio_encoder.sv        |    0
 .../FFT_files/mic/top_level.sv                |    0
 .../FFT_files/r22sdf/Butterfly.v              |    0
 .../FFT_files/r22sdf/DelayBuffer.v            |    0
 .../FFT_files/r22sdf/FFT.v                    |    0
 .../FFT_files/r22sdf/Multiply.v               |    0
 .../FFT_files/r22sdf/SdfUnit2.v               |    0
 .../FFT_files/r22sdf/SdfUnit_TC.v             |    0
 .../FFT_files/r22sdf/Twiddle.v                |    0
 .../FFT_files/r22sdf/TwiddleConvert4.v        |    0
 .../FFT_files/r22sdf/TwiddleConvert8.v        |    0
 .../FFT_files/r22sdf/twiddle_gen.pl           |    0
 .../FFT_files/record_audio.py                 |    0
 .../FFT_files/seven_seg.sv                    |    0
 .../FFT_files/top_level.sv                    |    0
 .../FFT_top_level.sv                          |    0
 .../README.md                                 |    0
 .../backwards.sv                              |    0
 .../continuous_motor_control.sv               |    0
 .../debounce.sv                               |    0
 .../direction_fsm.sv                          |    0
 .../display.sv                                |    0
 .../display_2digit.sv                         |    0
 .../drive_motor.sv                            |    0
 .../edge_detect.sv                            |    0
 .../forward.sv                                |    0
 .../json_command_sender.sv                    |    0
 .../json_command_sender_tb.sv                 |    0
 .../lcd_inst_pkg.sv                           |    0
 .../motors.qpf                                |    0
 .../nbit_synchroniser.sv                      |    0
 .../pinAssignments.csv                        |    0
 .../reset_pulser.sv                           |    0
 .../sensor_driver.sv                          |    0
 .../seven_seg.sv                              |    0
 .../speed_control_mapping.sv                  |    0
 .../speed_fsm.sv                              |    0
 .../stop.sv                                   |    0
 .../synchroniser.sv                           |    0
 .../top_level_distance_sensor.sv              |    0
 .../top_level_motor_driver.qsf                |    0
 .../top_level_motor_driver.sv                 |    0
 .../uart_tx.sv                                |    0
 .../uart_tx_tb.sv                             |    0
 .../debounce.sv                               |    0
 .../sensor_driver.sv                          |    0
 .../stp1.stp                                  |    0
 .../top_level.qsf                             |    0
 .../top_level.sv                              |    0
 .../top_level_distance_sensor.sv              |    0
 .../ultrasonic.qpf                            |    0
 .../address_generator.sv                      |    0
 .../camera_enable.qsf                         |    0
 .../camera_generation_top.sv                  |    0
 .../char_display.sopcinfo                     |    0
 .../clock_domain_fifo.qip                     |    0
 .../clock_domain_fifo.v                       |    0
 .../clock_domain_fifo_bb.v                    |    0
 .../colour_detect.sv                          |    0
 .../data_expander.sv                          |    0
 .../data_expander_hw.tcl                      |    0
 .../filter_fsm.sv                             |    0
 .../filter_select.sv                          |    0
 .../frame_buffer.v                            |    0
 .../i2c_sender.v                              |    0
 .../my_altpll.v                               |    0
 .../my_frame_buffer_15to0.v                   |    0
 .../ov7670_capture.v                          |    0
 .../ov7670_controller.v                       |    0
 .../ov7670_registers.v                        |    0
 .../state_machine_with_display.sv             |    0
 .../static_data_initialisation.sv             |    0
 .../synchroniser.sv                           |    0
 .../top_level.out.sdc                         |    0
 .../top_level.qpf                             |    0
 .../top_level.qsf                             |    0
 .../top_level.sdc                             |    0
 .../top_level.sv                              |    0
 .../FFT_files/FFT_stream.out.sdc              |    0
 .../FFT_files/FFT_stream.qpf                  |    0
 .../FFT_files/README.md                       |    0
 .../FFT_files/async_fifo.qip                  |    0
 .../FFT_files/async_fifo.v                    |    0
 .../FFT_files/async_fifo_bb.v                 |    0
 .../FFT_files/display.sv                      |    0
 .../FFT_files/dstream.sv                      |    0
 .../FFT_files/fft_find_peak.sv                |    0
 .../FFT_files/fft_input_buffer.sv             |    0
 .../FFT_files/fft_mag_sq.sv                   |    0
 .../FFT_files/fft_pitch_detect.sv             |    0
 .../FFT_files/fft_pitch_detect_tb.sv          |    0
 .../FFT_files/impulse_plotter.py              |    0
 .../FFT_files/low_pass_conv.sv                |    0
 .../FFT_files/mic/adc_pll.ppf                 |    0
 .../FFT_files/mic/adc_pll.qip                 |    0
 .../FFT_files/mic/adc_pll.v                   |    0
 .../FFT_files/mic/adc_pll_bb.v                |    0
 .../FFT_files/mic/i2c_master.sv               |    0
 .../FFT_files/mic/i2c_pll.ppf                 |    0
 .../FFT_files/mic/i2c_pll.qip                 |    0
 .../FFT_files/mic/i2c_pll.v                   |    0
 .../FFT_files/mic/i2c_pll_bb.v                |    0
 .../FFT_files/mic/mic_load.sv                 |    0
 .../FFT_files/mic/set_audio_encoder.sv        |    0
 .../FFT_files/mic/top_level.sv                |    0
 .../FFT_files/r22sdf/Butterfly.v              |    0
 .../FFT_files/r22sdf/DelayBuffer.v            |    0
 .../FFT_files/r22sdf/FFT.v                    |    0
 .../FFT_files/r22sdf/Multiply.v               |    0
 .../FFT_files/r22sdf/SdfUnit2.v               |    0
 .../FFT_files/r22sdf/SdfUnit_TC.v             |    0
 .../FFT_files/r22sdf/Twiddle.v                |    0
 .../FFT_files/r22sdf/TwiddleConvert4.v        |    0
 .../FFT_files/r22sdf/TwiddleConvert8.v        |    0
 .../FFT_files/r22sdf/twiddle_gen.pl           |    0
 .../FFT_files/record_audio.py                 |    0
 .../FFT_files/seven_seg.sv                    |    0
 .../FFT_files/top_level.sv                    |    0
 .../FFT_top_level.sv                          |    0
 .../address_generator.sv                      |    0
 .../backwards.sv                              |    0
 .../camera_enable.qsf                         |    0
 .../camera_generation_top.sv                  |    0
 .../clock_domain_fifo.qip                     |    0
 .../clock_domain_fifo.v                       |    0
 .../clock_domain_fifo_bb.v                    |    0
 .../colour_detect.sv                          |    0
 .../continuous_motor_control.sv               |    0
 .../debounce.sv                               |    0
 .../direction_fsm.sv                          |    0
 .../display.sv                                |    0
 .../display_2digit.sv                         |    0
 .../drive_motor.sv                            |    0
 .../edge_detect.sv                            |    0
 .../forward.sv                                |    0
 .../frame_buffer.v                            |    0
 .../i2c_sender.v                              |    0
 .../json_command_sender.sv                    |    0
 .../json_command_sender_tb.sv                 |    0
 .../lcd_inst_pkg.sv                           |    0
 .../motors.qpf                                |    0
 .../my_altpll.v                               |    0
 .../my_frame_buffer_15to0.v                   |    0
 .../nbit_synchroniser.sv                      |    0
 .../ov7670_capture.v                          |    0
 .../ov7670_controller.v                       |    0
 .../ov7670_registers.v                        |    0
 .../reset_pulser.sv                           |    0
 .../sensor_driver.sv                          |    0
 .../seven_seg.sv                              |    0
 .../speed_control_mapping.sv                  |    0
 .../speed_fsm.sv                              |    0
 .../stop.sv                                   |    0
 .../synchroniser.sv                           |    0
 .../top_level.sv                              |    0
 .../top_level_distance_sensor.sv              |    0
 .../top_level_motor_driver.qsf                |    0
 .../top_level_motor_driver.sv                 |    0
 .../uart_tx.sv                                |    0
 .../uart_tx_tb.sv                             |    0
 .../FFT_files/FFT_stream.out.sdc              |  114 ++
 .../FFT_files/FFT_stream.qpf                  |   31 +
 src/5_Blur_Integration/FFT_files/README.md    |   10 +
 .../FFT_files/async_fifo.qip                  |    5 +
 src/5_Blur_Integration/FFT_files/async_fifo.v |  180 ++
 .../FFT_files/async_fifo_bb.v                 |  138 ++
 src/5_Blur_Integration/FFT_files/display.sv   |   92 +
 src/5_Blur_Integration/FFT_files/dstream.sv   |   16 +
 .../FFT_files/fft_find_peak.sv                |   72 +
 .../FFT_files/fft_input_buffer.sv             |   62 +
 .../FFT_files/fft_mag_sq.sv                   |   41 +
 .../FFT_files/fft_pitch_detect.sv             |   86 +
 .../FFT_files/fft_pitch_detect_tb.sv          |   65 +
 .../FFT_files/impulse_plotter.py              |   27 +
 .../FFT_files/low_pass_conv.sv                |   72 +
 .../FFT_files/mic/adc_pll.ppf                 |   11 +
 .../FFT_files/mic/adc_pll.qip                 |    6 +
 .../FFT_files/mic/adc_pll.v                   |  321 +++
 .../FFT_files/mic/adc_pll_bb.v                |  211 ++
 .../FFT_files/mic/i2c_master.sv               |  110 ++
 .../FFT_files/mic/i2c_pll.ppf                 |   11 +
 .../FFT_files/mic/i2c_pll.qip                 |    6 +
 .../FFT_files/mic/i2c_pll.v                   |  321 +++
 .../FFT_files/mic/i2c_pll_bb.v                |  211 ++
 .../FFT_files/mic/mic_load.sv                 |   51 +
 .../FFT_files/mic/set_audio_encoder.sv        |   59 +
 .../FFT_files/mic/top_level.sv                |   33 +
 .../FFT_files/r22sdf/Butterfly.v              |   32 +
 .../FFT_files/r22sdf/DelayBuffer.v            |   32 +
 src/5_Blur_Integration/FFT_files/r22sdf/FFT.v |   89 +
 .../FFT_files/r22sdf/Multiply.v               |   35 +
 .../FFT_files/r22sdf/SdfUnit2.v               |   94 +
 .../FFT_files/r22sdf/SdfUnit_TC.v             |  344 ++++
 .../FFT_files/r22sdf/Twiddle.v                | 1063 ++++++++++
 .../FFT_files/r22sdf/TwiddleConvert4.v        |   61 +
 .../FFT_files/r22sdf/TwiddleConvert8.v        |   70 +
 .../FFT_files/r22sdf/twiddle_gen.pl           |   44 +
 .../FFT_files/record_audio.py                 |   67 +
 src/5_Blur_Integration/FFT_files/seven_seg.sv |   22 +
 src/5_Blur_Integration/FFT_files/top_level.sv |   47 +
 src/5_Blur_Integration/FFT_top_level.sv       |   56 +
 src/5_Blur_Integration/address_generator.sv   |   57 +
 src/5_Blur_Integration/backwards.sv           |  115 ++
 src/5_Blur_Integration/camera_enable.qsf      | 1176 +++++++++++
 .../camera_generation_top.sv                  |   90 +
 src/5_Blur_Integration/clock_domain_fifo.qip  |    5 +
 src/5_Blur_Integration/clock_domain_fifo.v    |  168 ++
 src/5_Blur_Integration/clock_domain_fifo_bb.v |  126 ++
 src/5_Blur_Integration/colour_detect.sv       |   60 +
 .../continuous_motor_control.sv               |   54 +
 src/5_Blur_Integration/debounce.sv            |   59 +
 src/5_Blur_Integration/direction_fsm.sv       |  131 ++
 src/5_Blur_Integration/display.sv             |   92 +
 src/5_Blur_Integration/display_2digit.sv      |   88 +
 src/5_Blur_Integration/drive_motor.sv         |   65 +
 src/5_Blur_Integration/edge_detect.sv         |   21 +
 src/5_Blur_Integration/forward.sv             |  112 ++
 src/5_Blur_Integration/frame_buffer.v         |  104 +
 src/5_Blur_Integration/i2c_sender.v           |  197 ++
 src/5_Blur_Integration/json_command_sender.sv |  112 ++
 .../json_command_sender_tb.sv                 |   62 +
 src/5_Blur_Integration/lcd_inst_pkg.sv        |  146 ++
 src/5_Blur_Integration/motors.qpf             |   31 +
 src/5_Blur_Integration/my_altpll.v            |  317 +++
 .../my_frame_buffer_15to0.v                   |  201 ++
 src/5_Blur_Integration/nbit_synchroniser.sv   |   17 +
 src/5_Blur_Integration/ov7670_capture.v       |  118 ++
 src/5_Blur_Integration/ov7670_controller.v    |   77 +
 src/5_Blur_Integration/ov7670_registers.v     |  278 +++
 src/5_Blur_Integration/reset_pulser.sv        |   22 +
 src/5_Blur_Integration/sensor_driver.sv       |  135 ++
 src/5_Blur_Integration/seven_seg.sv           |   22 +
 .../speed_control_mapping.sv                  |   27 +
 src/5_Blur_Integration/speed_fsm.sv           |   50 +
 src/5_Blur_Integration/stop.sv                |   98 +
 src/5_Blur_Integration/synchroniser.sv        |    9 +
 .../top_level_distance_sensor.sv              |   45 +
 .../top_level_motor_driver.qsf                | 1758 +++++++++++++++++
 .../top_level_motor_driver.sv                 |  304 +++
 src/5_Blur_Integration/uart_tx.sv             |   79 +
 src/5_Blur_Integration/uart_tx_tb.sv          |   96 +
 266 files changed, 11142 insertions(+)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/FFT_stream.out.sdc (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/FFT_stream.qpf (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/README.md (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/async_fifo.qip (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/async_fifo.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/async_fifo_bb.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/display.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/dstream.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/fft_find_peak.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/fft_input_buffer.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/fft_mag_sq.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/fft_pitch_detect.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/fft_pitch_detect_tb.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/impulse_plotter.py (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/low_pass_conv.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/adc_pll.ppf (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/adc_pll.qip (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/adc_pll.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/adc_pll_bb.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/i2c_master.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/i2c_pll.ppf (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/i2c_pll.qip (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/i2c_pll.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/i2c_pll_bb.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/mic_load.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/set_audio_encoder.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/mic/top_level.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/Butterfly.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/DelayBuffer.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/FFT.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/Multiply.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/SdfUnit2.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/SdfUnit_TC.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/Twiddle.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/TwiddleConvert4.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/TwiddleConvert8.v (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/r22sdf/twiddle_gen.pl (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/record_audio.py (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/seven_seg.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_files/top_level.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/FFT_top_level.sv (100%)
 rename src/{FFT_Motor_Integration => 1_FFT_Motor_Integration}/README.md (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/backwards.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/continuous_motor_control.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/debounce.sv (100%)
 rename src/{FFT_Motor_Integration => 1_FFT_Motor_Integration}/direction_fsm.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/display.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/display_2digit.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/drive_motor.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/edge_detect.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/forward.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/json_command_sender.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/json_command_sender_tb.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/lcd_inst_pkg.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/motors.qpf (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/nbit_synchroniser.sv (100%)
 rename src/{FFT_Motor_Integration => 1_FFT_Motor_Integration}/pinAssignments.csv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/reset_pulser.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/sensor_driver.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/seven_seg.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/speed_control_mapping.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/speed_fsm.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/stop.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/synchroniser.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/top_level_distance_sensor.sv (100%)
 rename src/{FFT_Motor_Integration => 1_FFT_Motor_Integration}/top_level_motor_driver.qsf (100%)
 rename src/{FFT_Motor_Integration => 1_FFT_Motor_Integration}/top_level_motor_driver.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/uart_tx.sv (100%)
 rename src/{Camera_FFT_Motor_Integration => 1_FFT_Motor_Integration}/uart_tx_tb.sv (100%)
 rename src/{ProximityCode => 2_ProximityCode}/debounce.sv (100%)
 rename src/{FFT_Motor_Integration => 2_ProximityCode}/sensor_driver.sv (100%)
 rename src/{ProximityCode => 2_ProximityCode}/stp1.stp (100%)
 rename src/{ProximityCode => 2_ProximityCode}/top_level.qsf (100%)
 rename src/{ProximityCode => 2_ProximityCode}/top_level.sv (100%)
 rename src/{ProximityCode => 2_ProximityCode}/top_level_distance_sensor.sv (100%)
 rename src/{ProximityCode => 2_ProximityCode}/ultrasonic.qpf (100%)
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 create mode 100644 src/5_Blur_Integration/lcd_inst_pkg.sv
 create mode 100644 src/5_Blur_Integration/motors.qpf
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 create mode 100644 src/5_Blur_Integration/ov7670_capture.v
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diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/FFT_stream.out.sdc b/src/1_FFT_Motor_Integration/FFT_files/FFT_stream.out.sdc
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/FFT_stream.out.sdc
rename to src/1_FFT_Motor_Integration/FFT_files/FFT_stream.out.sdc
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/FFT_stream.qpf b/src/1_FFT_Motor_Integration/FFT_files/FFT_stream.qpf
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/FFT_stream.qpf
rename to src/1_FFT_Motor_Integration/FFT_files/FFT_stream.qpf
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/README.md b/src/1_FFT_Motor_Integration/FFT_files/README.md
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/README.md
rename to src/1_FFT_Motor_Integration/FFT_files/README.md
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/async_fifo.qip b/src/1_FFT_Motor_Integration/FFT_files/async_fifo.qip
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/async_fifo.qip
rename to src/1_FFT_Motor_Integration/FFT_files/async_fifo.qip
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/async_fifo.v b/src/1_FFT_Motor_Integration/FFT_files/async_fifo.v
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/async_fifo.v
rename to src/1_FFT_Motor_Integration/FFT_files/async_fifo.v
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/async_fifo_bb.v b/src/1_FFT_Motor_Integration/FFT_files/async_fifo_bb.v
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/async_fifo_bb.v
rename to src/1_FFT_Motor_Integration/FFT_files/async_fifo_bb.v
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/display.sv b/src/1_FFT_Motor_Integration/FFT_files/display.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/display.sv
rename to src/1_FFT_Motor_Integration/FFT_files/display.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/dstream.sv b/src/1_FFT_Motor_Integration/FFT_files/dstream.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/dstream.sv
rename to src/1_FFT_Motor_Integration/FFT_files/dstream.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/fft_find_peak.sv b/src/1_FFT_Motor_Integration/FFT_files/fft_find_peak.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/fft_find_peak.sv
rename to src/1_FFT_Motor_Integration/FFT_files/fft_find_peak.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/fft_input_buffer.sv b/src/1_FFT_Motor_Integration/FFT_files/fft_input_buffer.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/fft_input_buffer.sv
rename to src/1_FFT_Motor_Integration/FFT_files/fft_input_buffer.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/fft_mag_sq.sv b/src/1_FFT_Motor_Integration/FFT_files/fft_mag_sq.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/fft_mag_sq.sv
rename to src/1_FFT_Motor_Integration/FFT_files/fft_mag_sq.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/fft_pitch_detect.sv b/src/1_FFT_Motor_Integration/FFT_files/fft_pitch_detect.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/fft_pitch_detect.sv
rename to src/1_FFT_Motor_Integration/FFT_files/fft_pitch_detect.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/fft_pitch_detect_tb.sv b/src/1_FFT_Motor_Integration/FFT_files/fft_pitch_detect_tb.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/fft_pitch_detect_tb.sv
rename to src/1_FFT_Motor_Integration/FFT_files/fft_pitch_detect_tb.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/impulse_plotter.py b/src/1_FFT_Motor_Integration/FFT_files/impulse_plotter.py
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/impulse_plotter.py
rename to src/1_FFT_Motor_Integration/FFT_files/impulse_plotter.py
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/low_pass_conv.sv b/src/1_FFT_Motor_Integration/FFT_files/low_pass_conv.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/low_pass_conv.sv
rename to src/1_FFT_Motor_Integration/FFT_files/low_pass_conv.sv
diff --git a/src/Camera_FFT_Motor_Integration/FFT_files/mic/adc_pll.ppf b/src/1_FFT_Motor_Integration/FFT_files/mic/adc_pll.ppf
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/FFT_files/mic/adc_pll.ppf
rename to src/1_FFT_Motor_Integration/FFT_files/mic/adc_pll.ppf
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rename to src/4_Camera_FFT_Motor_Integration/frame_buffer.v
diff --git a/src/ColourDetection/i2c_sender.v b/src/4_Camera_FFT_Motor_Integration/i2c_sender.v
similarity index 100%
rename from src/ColourDetection/i2c_sender.v
rename to src/4_Camera_FFT_Motor_Integration/i2c_sender.v
diff --git a/src/FFT_Motor_Integration/json_command_sender.sv b/src/4_Camera_FFT_Motor_Integration/json_command_sender.sv
similarity index 100%
rename from src/FFT_Motor_Integration/json_command_sender.sv
rename to src/4_Camera_FFT_Motor_Integration/json_command_sender.sv
diff --git a/src/FFT_Motor_Integration/json_command_sender_tb.sv b/src/4_Camera_FFT_Motor_Integration/json_command_sender_tb.sv
similarity index 100%
rename from src/FFT_Motor_Integration/json_command_sender_tb.sv
rename to src/4_Camera_FFT_Motor_Integration/json_command_sender_tb.sv
diff --git a/src/FFT_Motor_Integration/lcd_inst_pkg.sv b/src/4_Camera_FFT_Motor_Integration/lcd_inst_pkg.sv
similarity index 100%
rename from src/FFT_Motor_Integration/lcd_inst_pkg.sv
rename to src/4_Camera_FFT_Motor_Integration/lcd_inst_pkg.sv
diff --git a/src/FFT_Motor_Integration/motors.qpf b/src/4_Camera_FFT_Motor_Integration/motors.qpf
similarity index 100%
rename from src/FFT_Motor_Integration/motors.qpf
rename to src/4_Camera_FFT_Motor_Integration/motors.qpf
diff --git a/src/ColourDetection/my_altpll.v b/src/4_Camera_FFT_Motor_Integration/my_altpll.v
similarity index 100%
rename from src/ColourDetection/my_altpll.v
rename to src/4_Camera_FFT_Motor_Integration/my_altpll.v
diff --git a/src/ColourDetection/my_frame_buffer_15to0.v b/src/4_Camera_FFT_Motor_Integration/my_frame_buffer_15to0.v
similarity index 100%
rename from src/ColourDetection/my_frame_buffer_15to0.v
rename to src/4_Camera_FFT_Motor_Integration/my_frame_buffer_15to0.v
diff --git a/src/FFT_Motor_Integration/nbit_synchroniser.sv b/src/4_Camera_FFT_Motor_Integration/nbit_synchroniser.sv
similarity index 100%
rename from src/FFT_Motor_Integration/nbit_synchroniser.sv
rename to src/4_Camera_FFT_Motor_Integration/nbit_synchroniser.sv
diff --git a/src/ColourDetection/ov7670_capture.v b/src/4_Camera_FFT_Motor_Integration/ov7670_capture.v
similarity index 100%
rename from src/ColourDetection/ov7670_capture.v
rename to src/4_Camera_FFT_Motor_Integration/ov7670_capture.v
diff --git a/src/ColourDetection/ov7670_controller.v b/src/4_Camera_FFT_Motor_Integration/ov7670_controller.v
similarity index 100%
rename from src/ColourDetection/ov7670_controller.v
rename to src/4_Camera_FFT_Motor_Integration/ov7670_controller.v
diff --git a/src/ColourDetection/ov7670_registers.v b/src/4_Camera_FFT_Motor_Integration/ov7670_registers.v
similarity index 100%
rename from src/ColourDetection/ov7670_registers.v
rename to src/4_Camera_FFT_Motor_Integration/ov7670_registers.v
diff --git a/src/FFT_Motor_Integration/reset_pulser.sv b/src/4_Camera_FFT_Motor_Integration/reset_pulser.sv
similarity index 100%
rename from src/FFT_Motor_Integration/reset_pulser.sv
rename to src/4_Camera_FFT_Motor_Integration/reset_pulser.sv
diff --git a/src/ProximityCode/sensor_driver.sv b/src/4_Camera_FFT_Motor_Integration/sensor_driver.sv
similarity index 100%
rename from src/ProximityCode/sensor_driver.sv
rename to src/4_Camera_FFT_Motor_Integration/sensor_driver.sv
diff --git a/src/FFT_Motor_Integration/seven_seg.sv b/src/4_Camera_FFT_Motor_Integration/seven_seg.sv
similarity index 100%
rename from src/FFT_Motor_Integration/seven_seg.sv
rename to src/4_Camera_FFT_Motor_Integration/seven_seg.sv
diff --git a/src/FFT_Motor_Integration/speed_control_mapping.sv b/src/4_Camera_FFT_Motor_Integration/speed_control_mapping.sv
similarity index 100%
rename from src/FFT_Motor_Integration/speed_control_mapping.sv
rename to src/4_Camera_FFT_Motor_Integration/speed_control_mapping.sv
diff --git a/src/FFT_Motor_Integration/speed_fsm.sv b/src/4_Camera_FFT_Motor_Integration/speed_fsm.sv
similarity index 100%
rename from src/FFT_Motor_Integration/speed_fsm.sv
rename to src/4_Camera_FFT_Motor_Integration/speed_fsm.sv
diff --git a/src/FFT_Motor_Integration/stop.sv b/src/4_Camera_FFT_Motor_Integration/stop.sv
similarity index 100%
rename from src/FFT_Motor_Integration/stop.sv
rename to src/4_Camera_FFT_Motor_Integration/stop.sv
diff --git a/src/FFT_Motor_Integration/synchroniser.sv b/src/4_Camera_FFT_Motor_Integration/synchroniser.sv
similarity index 100%
rename from src/FFT_Motor_Integration/synchroniser.sv
rename to src/4_Camera_FFT_Motor_Integration/synchroniser.sv
diff --git a/src/Camera_FFT_Motor_Integration/top_level.sv b/src/4_Camera_FFT_Motor_Integration/top_level.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/top_level.sv
rename to src/4_Camera_FFT_Motor_Integration/top_level.sv
diff --git a/src/FFT_Motor_Integration/top_level_distance_sensor.sv b/src/4_Camera_FFT_Motor_Integration/top_level_distance_sensor.sv
similarity index 100%
rename from src/FFT_Motor_Integration/top_level_distance_sensor.sv
rename to src/4_Camera_FFT_Motor_Integration/top_level_distance_sensor.sv
diff --git a/src/Camera_FFT_Motor_Integration/top_level_motor_driver.qsf b/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.qsf
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/top_level_motor_driver.qsf
rename to src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.qsf
diff --git a/src/Camera_FFT_Motor_Integration/top_level_motor_driver.sv b/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv
similarity index 100%
rename from src/Camera_FFT_Motor_Integration/top_level_motor_driver.sv
rename to src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv
diff --git a/src/FFT_Motor_Integration/uart_tx.sv b/src/4_Camera_FFT_Motor_Integration/uart_tx.sv
similarity index 100%
rename from src/FFT_Motor_Integration/uart_tx.sv
rename to src/4_Camera_FFT_Motor_Integration/uart_tx.sv
diff --git a/src/FFT_Motor_Integration/uart_tx_tb.sv b/src/4_Camera_FFT_Motor_Integration/uart_tx_tb.sv
similarity index 100%
rename from src/FFT_Motor_Integration/uart_tx_tb.sv
rename to src/4_Camera_FFT_Motor_Integration/uart_tx_tb.sv
diff --git a/src/5_Blur_Integration/FFT_files/FFT_stream.out.sdc b/src/5_Blur_Integration/FFT_files/FFT_stream.out.sdc
new file mode 100644
index 0000000..cc2dbad
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/FFT_stream.out.sdc
@@ -0,0 +1,114 @@
+## Generated SDC file "FFT_stream.out.sdc"
+
+## Copyright (C) 2020  Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions 
+## and other software and tools, and any partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Intel Program License 
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors.  Please
+## refer to the applicable agreement for further details, at
+## https://fpgasoftware.intel.com/eula.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition"
+
+## DATE    "Thu Sep 12 03:00:43 2024"
+
+##
+## DEVICE  "EP4CE115F29C7"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
+create_clock -name {AUD_BCLK} -period 325.520 -waveform { 0.000 162.760 } [get_ports {AUD_BCLK}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+create_generated_clock -name {i2c_pll_u|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {i2c_pll_u|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2500 -master_clock {CLOCK_50} [get_pins {i2c_pll_u|altpll_component|auto_generated|pll1|clk[0]}] 
+create_generated_clock -name {adc_pll_u|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {adc_pll_u|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50/1 -multiply_by 80 -divide_by 217 -master_clock {CLOCK_50} [get_pins {adc_pll_u|altpll_component|auto_generated|pll1|clk[0]}] 
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe15|dffe16a*}]
+set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qe9:dffpipe12|dffe13a*}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
diff --git a/src/5_Blur_Integration/FFT_files/FFT_stream.qpf b/src/5_Blur_Integration/FFT_files/FFT_stream.qpf
new file mode 100644
index 0000000..8efcc2b
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/FFT_stream.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 23:18:53  September 08, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "23:18:53  September 08, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "FFT_stream"
diff --git a/src/5_Blur_Integration/FFT_files/README.md b/src/5_Blur_Integration/FFT_files/README.md
new file mode 100644
index 0000000..ac18b36
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/README.md
@@ -0,0 +1,10 @@
+### How to setup.
+
+
+Import everything in the folders
+/mic
+/r22sdf
+
+Don't include the top level present in mic.
+
+Make sure to only include the .qip files not the .v files as well
diff --git a/src/5_Blur_Integration/FFT_files/async_fifo.qip b/src/5_Blur_Integration/FFT_files/async_fifo.qip
new file mode 100644
index 0000000..624f76a
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/async_fifo.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "async_fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "async_fifo_bb.v"]
diff --git a/src/5_Blur_Integration/FFT_files/async_fifo.v b/src/5_Blur_Integration/FFT_files/async_fifo.v
new file mode 100644
index 0000000..1012e18
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/async_fifo.v
@@ -0,0 +1,180 @@
+// Copy & Paste your code from task 1.3 here!// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: async_fifo.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module async_fifo (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdfull,
+	wrfull);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdfull;
+	output	  wrfull;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [15:0] sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire [15:0] q = sub_wire0[15:0];
+	wire  rdfull = sub_wire1;
+	wire  wrfull = sub_wire2;
+
+	dcfifo	dcfifo_component (
+				.aclr (aclr),
+				.data (data),
+				.rdclk (rdclk),
+				.rdreq (rdreq),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.q (sub_wire0),
+				.rdfull (sub_wire1),
+				.wrfull (sub_wire2),
+				.eccstatus (),
+				.rdempty (),
+				.rdusedw (),
+				.wrempty (),
+				.wrusedw ());
+	defparam
+		dcfifo_component.intended_device_family = "Cyclone IV E",
+		dcfifo_component.lpm_numwords = 1024,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 10,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.rdsync_delaypipe = 4,
+		dcfifo_component.read_aclr_synch = "OFF",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON",
+		dcfifo_component.write_aclr_synch = "OFF",
+		dcfifo_component.wrsync_delaypipe = 4;
+
+
+endmodule
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/src/5_Blur_Integration/FFT_files/async_fifo_bb.v b/src/5_Blur_Integration/FFT_files/async_fifo_bb.v
new file mode 100644
index 0000000..f4790ee
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/async_fifo_bb.v
@@ -0,0 +1,138 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: async_fifo.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module async_fifo (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdfull,
+	wrfull);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdfull;
+	output	  wrfull;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL async_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/src/5_Blur_Integration/FFT_files/display.sv b/src/5_Blur_Integration/FFT_files/display.sv
new file mode 100644
index 0000000..d3c7d85
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/display.sv
@@ -0,0 +1,92 @@
+module display (
+    input         clk,
+    input  [10:0] value,
+    output [6:0]  display0,
+    output [6:0]  display1,
+    output [6:0]  display2,
+    output [6:0]  display3
+);
+    /*** FSM Controller Code: ***/
+    enum { Initialise, Add3, Shift, Result } next_state, current_state = Initialise; // FSM states.
+    
+    logic init, add, done; // FSM outputs.
+
+    logic [3:0] count = 0; // Use this to count the 11 loop iterations.
+
+    /*** DO NOT MODIFY THE CODE ABOVE ***/
+
+
+
+    always_comb begin : double_dabble_fsm_next_state_logic
+        case (current_state)
+            Initialise: next_state = Add3;
+            Add3:       next_state = Shift;
+            Shift:      next_state = count == 10 ? Result : Add3;
+            Result:     next_state = Initialise;
+            default:    next_state = Initialise;
+        endcase
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_fsm_ff
+        current_state <= next_state;
+        if (current_state == Shift) begin
+            count <= count == 10 ? 0 : count + 1;
+        end
+    end
+
+    always_comb begin : double_dabble_fsm_output
+        init = 1'b0;
+        add = 1'b0;
+        done = 1'b0;
+        case (current_state) // Moore FSM
+            Initialise: init = 1'b1;
+            Add3:       add = 1'b1;
+            Result:     done = 1'b1;
+        endcase
+    end
+    
+
+
+    /*** DO NOT MODIFY THE CODE BELOW ***/
+    logic [3:0] digit0, digit1, digit2, digit3;
+
+    //// Seven-Segment Displays
+    seven_seg u_digit0 (.bcd(digit0), .segments(display0));
+    seven_seg u_digit1 (.bcd(digit1), .segments(display1));
+    seven_seg u_digit2 (.bcd(digit2), .segments(display2));
+    seven_seg u_digit3 (.bcd(digit3), .segments(display3));
+
+    // Algorithm RTL:  (completed no changes required - see dd_rtl.png for a representation of the code below but for 2 BCD digits.)
+    // essentially a 27-bit long, 1-bit wide shift-register, starting from the 11 input bits through to the 4 bits of each BCD digit (4*4=16, 16+11=27).
+    // We shift in the Shift state, add 3 to BCD digits greater than 4 in the Add3 state, and initialise the shift-register values in the Initialise state.
+    logic [3:0]  bcd0, bcd1, bcd2, bcd3; // Do NOT change.
+    logic [10:0] temp_value; // Do NOT change.
+
+    always_ff @(posedge clk) begin : double_dabble_shiftreg
+        if (init) begin // Initialise: set bcd values to 0 and temp_value to value.
+            {bcd3, bcd2, bcd1, bcd0, temp_value} <= {16'b0, value}; // A nice usage of the concat operator on both LHS and RHS!
+        end
+        else begin
+            if (add) begin // Add3: 3 is added to each bcd value greater than 4.
+                bcd0 <= bcd0 > 4 ? bcd0 + 3 : bcd0;  // Conditional operator.
+                bcd1 <= bcd1 > 4 ? bcd1 + 3 : bcd1;
+                bcd2 <= bcd2 > 4 ? bcd2 + 3 : bcd2;
+                bcd3 <= bcd3 > 4 ? bcd3 + 3 : bcd3;
+            end
+            else begin // Shift: essentially everything becomes a shift-register
+                {bcd3, bcd2, bcd1, bcd0, temp_value} <= {bcd3, bcd2, bcd1, bcd0, temp_value} << 1; // Concat operator makes this easy!
+            end
+        end
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_ff_output
+        // Need to 'flop' bcd values at the output so that intermediate calculations are not seen at the output.
+        if (done) begin  // Only take bcd values when the algorithm is done!
+            digit0 <= bcd0;
+            digit1 <= bcd1;
+            digit2 <= bcd2;
+            digit3 <= bcd3;
+        end
+    end
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/dstream.sv b/src/5_Blur_Integration/FFT_files/dstream.sv
new file mode 100644
index 0000000..c56a684
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/dstream.sv
@@ -0,0 +1,16 @@
+interface dstream #(parameter N);  // Data stream interface. Parameter N is the bit width of the data.
+	logic valid; // We use a handshake protocol just like in AXI-Stream
+	logic ready;
+	logic [N-1:0] data;
+	
+	modport in( // Module that takes the data as input.
+		input  valid,
+		output ready,
+		input  data
+	);
+	modport out( // Module that outputs the data.
+		output valid,
+		input  ready,
+		output data
+	);
+endinterface
diff --git a/src/5_Blur_Integration/FFT_files/fft_find_peak.sv b/src/5_Blur_Integration/FFT_files/fft_find_peak.sv
new file mode 100644
index 0000000..b2d2cb3
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/fft_find_peak.sv
@@ -0,0 +1,72 @@
+module fft_find_peak #(
+    parameter NSamples = 1024, // 1024 N-points
+    parameter W        = 33,   // For 16x2 + 1
+	parameter NBits    = $clog2(NSamples)
+
+) (
+    input                        clk,
+    input                        reset,
+    input  [W-1:0]               mag,
+    input                        mag_valid,
+    output logic [W-1:0]         peak = 0,
+    output logic [NBits-1:0]     peak_k = 0,
+    output logic                 peak_valid
+);
+    logic [NBits-1:0] i = 0, k;
+	always_comb for (integer j=0; j<NBits; j=j+1) k[j] = i[NBits-1-j]; // bit-reversed index
+    // determine if the peak is valid;
+
+    logic [W-1:0]         peak_temp   = 0;
+    logic [NBits-1:0]     peak_k_temp = 0;
+
+    always_ff @(posedge clk) begin : find_peak
+        //TODO Find the peak (maximum) value out of a window of 1024 streamed samples, streamed in one at a time.
+        // Store the corresponding k-index representing that value in peak_k. Set peak_valid to 1 for 1 clock cycle once all 1024 values have been streamed through.
+        // Use the counter i to count from 0 to 1023. Reset all registers after the 1024th value of i, in preparation for the next FFT window.
+        // The FFT k-index is represented by bit-reversing i.
+
+        // check if we are resetting. Then reset all of the values
+        if(reset) begin
+            peak_k_temp <= 0;
+            peak_temp <= 0;
+            peak_valid <=0;
+            i <= 0;
+        end
+        // if we've reached theend of the packet then set peak_valid correctly
+        else if(i == NSamples - 1) begin
+
+            // set the output variables
+            peak_k <= peak_k_temp;
+            peak <= peak_temp;
+
+            // set valid to 1 and reset the maximum peak detected
+            peak_valid <= 1;
+            peak_temp <= 0;
+            peak_k_temp <= 0;
+            i <= 0;
+
+        end
+        // check if the magnitue provided is valid
+        else if(mag_valid) begin
+            
+            // increment the index if the mag is bigger than the peak
+            if(mag > peak_temp) begin
+                if(k[NBits - 1] != 1'b1) begin
+                    peak_temp <= mag;
+                    peak_k_temp <= k;
+                end
+            end
+
+            i <= i + 1;
+            peak_valid <= 0;
+        end
+        else begin
+
+            // reset registers in mag not valid
+            peak_k_temp <= 0;
+            peak_temp <= 0;
+            peak_valid <=0;
+            i <= 0;
+        end
+    end
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/fft_input_buffer.sv b/src/5_Blur_Integration/FFT_files/fft_input_buffer.sv
new file mode 100644
index 0000000..ef5e7fd
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/fft_input_buffer.sv
@@ -0,0 +1,62 @@
+module fft_input_buffer #(
+    parameter W = 16,
+    parameter NSamples = 1024
+) (
+    input                clk,
+     input                reset,
+     input                audio_clk,
+    dstream.in           audio_input,
+     output logic [W-1:0] fft_input,
+     output logic         fft_input_valid
+);
+    logic fft_read = 0;
+    logic [$clog2(NSamples):0] n = 0;
+
+    logic full, wr_full;
+    async_fifo u_fifo (.aclr(reset),
+                        .data(audio_input.data),
+                        .wrclk(audio_clk),
+                        .wrreq(audio_input.valid),
+                        .wrfull(wr_full),
+                        .q(fft_input),          
+                        .rdclk(clk),      
+                        .rdreq(fft_read),         
+                        .rdfull(full));
+    assign audio_input.ready = !wr_full;
+
+    assign fft_input_valid = fft_read; // The Async FIFO is set such that valid data is read out whenever the rdreq flag is high.
+    
+    //TODO implement a counter n to set fft_read to 1 when the FIFO becomes full (use full, not wr_full).
+    // Then, keep fft_read set to 1 until 1024 (NSamples) samples in total have been read out from the FIFO.
+
+    logic start_count;
+
+    always_ff @(posedge clk) begin
+
+        if(full || start_count) begin
+            n <= n + 1;
+        end
+        else begin
+            n <= 0;
+        end
+    end
+
+    always_comb begin
+
+        //  check to see that the counting has begun
+        if(n > 0 && n < NSamples) begin
+            start_count = 1;
+        end
+        else begin
+            start_count = 0;
+        end
+
+        if(full || start_count) begin
+            fft_read = 1;
+        end
+        else begin
+            fft_read = 0;
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/FFT_files/fft_mag_sq.sv b/src/5_Blur_Integration/FFT_files/fft_mag_sq.sv
new file mode 100644
index 0000000..1beaed0
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/fft_mag_sq.sv
@@ -0,0 +1,41 @@
+module fft_mag_sq #(
+    parameter W = 16
+) (
+    input                clk,
+    input                reset,
+    input                fft_valid,
+    input        [W-1:0] fft_imag,
+    input        [W-1:0] fft_real,
+    output logic [W*2:0] mag_sq,
+    output logic         mag_valid
+);
+
+    logic signed [W*2-1:0] multiply_stage_real, multiply_stage_imag;
+    logic signed [W*2:0]   add_stage;
+    
+    always_ff @(posedge clk) begin
+       //TODO Your code here!
+
+       multiply_stage_real <= signed'(fft_real) * signed'(fft_real);
+       multiply_stage_imag <= signed'(fft_imag) * signed'(fft_imag);
+
+       add_stage <= multiply_stage_real + multiply_stage_imag;
+       // We want to implement the 2 pipeline stages, similar to task 1.2.
+       // When multiplying, make sure to use the signed function, e.g: signed'(fft_real)*signed'(fft_real);
+       // Remember to usereset.
+
+    end
+
+    // Flip flop to create the 2 clock cycle delay 
+    logic [1:0] shiftRegister;
+    always_ff @(posedge clk) begin
+        shiftRegister[1] <= shiftRegister[0];
+        shiftRegister[0] <= fft_valid;
+    end
+
+    assign mag_sq = add_stage;
+    assign mag_valid = shiftRegister[1];//TODO set to `1` when mag_sq valid **this should be 2 cycles after valid input!**
+    // Hint: you can use a shift register to implement valid.
+
+    // make a shift register with two flip flops. The input to the shift register is fft valid and the output is magvalid
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/FFT_files/fft_pitch_detect.sv b/src/5_Blur_Integration/FFT_files/fft_pitch_detect.sv
new file mode 100644
index 0000000..18ca5b1
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/fft_pitch_detect.sv
@@ -0,0 +1,86 @@
+module fft_pitch_detect (
+    input clk,
+    input audio_clk,
+    input reset,
+    dstream.in  audio_input,
+    dstream.out pitch_output
+);
+    parameter W        = 16;   //NOTE: To change this, you must also change the Twiddle factor initialisations in r22sdf/Twiddle.v. You can use r22sdf/twiddle_gen.pl.
+    parameter NSamples = 1024; //NOTE: To change this, you must also change the SdfUnit instantiations in r22sdf/FFT.v accordingly.
+
+    logic           di_en;  //  Input Data Enable
+    logic   [W-1:0] di_re;  //  Input Data (Real)
+    logic   [W-1:0] di_im;  //  Input Data (Imag)
+
+    logic           do_en;  //  Output Data Enable
+    logic   [W-1:0] do_re;  //  Output Data (Real)
+    logic   [W-1:0] do_im;  //  Output Data (Imag)
+
+    assign  di_im = 0; // No imaginary parts (audio signal is purely real).
+
+    logic           mag_valid;
+    logic   [W*2:0] mag_sq;
+	 
+
+    /*
+    SECTION TO HANDLE DOWNSAMPLING AND FILTERING
+    */
+    integer decimate_counter = 0;
+    dstream #(.N(2*W))    conv_input   ();
+    dstream #(.N(2*W))    conv_output  ();
+    dstream #(.N(W))      pitch_input  ();
+
+	assign conv_input.valid = audio_input.valid;
+	assign conv_input.data  = {audio_input.data, 16'b0}; // Make audio samples the integer part (32 bits, 16 bit fraction).
+	assign audio_input.ready = conv_input.ready;
+	low_pass_conv #(.W(2*W), .W_FRAC(W)) u_anti_alias_filter ( // Use 32 bits, 16 bit fraction.
+		.clk(audio_clk),
+		.x(conv_input),
+		.y(conv_output)
+	);
+	always_ff @(posedge audio_clk) if (conv_output.valid) decimate_counter <= decimate_counter==3? 0 : decimate_counter+1; // Count from 0 to 3.
+    assign pitch_input.data  = conv_output.data[31:16]; // Retrieve the 16 bit integer part for our audio samples.
+    assign pitch_input.valid = conv_output.valid && decimate_counter == 0; // Down-sample! Only use every 4th sample.
+    assign conv_output.ready = 1; // The input buffer will never need to assert back-pressure given 48 kHz << 18.432 MHz.
+	 
+    fft_input_buffer #(.W(W), .NSamples(NSamples)) u_fft_input_buffer (
+          .clk(clk), 
+          .reset(reset), 
+          .audio_clk(audio_clk), 
+          .audio_input(pitch_input), 
+          .fft_input(di_re), 
+          .fft_input_valid(di_en)
+    );
+	 
+    FFT #(.WIDTH(W)) u_fft_ip (
+        .clock(clk), 
+        .reset(reset), 
+        .di_en(di_en), 
+        .di_re(di_re), 
+        .di_im(di_im), 
+        .do_en(do_en), 
+        .do_re(do_re), 
+        .do_im(do_im)
+    );
+	 
+    fft_mag_sq #(.W(W)) u_fft_mag_sq (
+        .clk(clk), 
+        .reset(reset), 
+        .fft_valid(do_en), 
+        .fft_imag(do_im), 
+        .fft_real(do_re), 
+        .mag_sq(mag_sq), 
+        .mag_valid(mag_valid)
+    );
+	 
+    fft_find_peak #(.W(W*2+1),.NSamples(NSamples)) u_fft_find_peak (
+        .clk(clk), 
+        .reset(reset), 
+        .mag(mag_sq), 
+        .mag_valid(mag_valid), 
+        .peak(), 
+        .peak_k(pitch_output.data), 
+        .peak_valid(pitch_output.valid)
+    );
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/fft_pitch_detect_tb.sv b/src/5_Blur_Integration/FFT_files/fft_pitch_detect_tb.sv
new file mode 100644
index 0000000..26165cd
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/fft_pitch_detect_tb.sv
@@ -0,0 +1,65 @@
+`timescale 1 ns / 1 ns
+module fft_pitch_detect_tb;
+
+    localparam NSamples = 1024;
+    localparam W        = 16;
+
+    localparam TCLK  = 50;  // 20 MHz.
+    localparam TBCLK = 300; // x6 slower
+
+    logic clk = 0, bclk = 0;    //  Master Clock
+    
+    always #(TCLK/2) clk = ~clk;
+    always #(TBCLK/2) bclk = ~bclk;
+	 
+    logic reset = 1'b1;
+    
+    dstream #(.N(W)) audio_input ();
+    dstream #(.N($clog2(NSamples))) pitch_output ();
+
+    fft_pitch_detect DUT (.clk(clk), .audio_clk(bclk), .reset(reset), .audio_input(audio_input), .pitch_output(pitch_output));
+
+    logic [W-1:0] input_signal [NSamples];
+    initial $readmemh("test_waveform.hex", input_signal);
+
+
+    logic start = 1'b0; // Use a start flag.
+    initial begin : test_procedure
+        $dumpfile("waveform.vcd");
+        $dumpvars();
+        reset = 1'b1;
+        #(TCLK*5);
+        reset = 1'b0;
+        #(TCLK*5);
+        start = 1'b1;
+        repeat (3) @(negedge pitch_output.valid);
+        #(TCLK*100);
+        $finish();
+    end
+
+    // Input Driver
+    integer i = 0, next_i;
+    assign next_i = i < NSamples-1 ? i + 1 : 0;
+    always_ff @(posedge bclk) begin : driver
+        audio_input.valid <= 1'b0;
+        audio_input.data <= input_signal[i];
+        if (start) begin
+            audio_input.valid <= 1'b1;
+            if (audio_input.valid && audio_input.ready) begin
+                audio_input.data <= input_signal[next_i];
+                i <= next_i;
+            end
+        end
+    end
+
+    logic [2*W:0] output_check, expected_output;
+    integer output_i = 0;
+    always_ff @(posedge clk) begin : monitor
+        if (pitch_output.valid) begin
+            output_check <= pitch_output.data;
+            output_i     <= output_i < NSamples-1 ? output_i + 1 : 0;
+        end
+    end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/impulse_plotter.py b/src/5_Blur_Integration/FFT_files/impulse_plotter.py
new file mode 100644
index 0000000..b9ebc6d
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/impulse_plotter.py
@@ -0,0 +1,27 @@
+import pandas as pd
+import matplotlib.pyplot as plt
+
+hex_values = [
+    0x00000000, 0x00000014, 0x0000003f, 0x00000050, 0x00000000, 0xffffff0b, 0xfffffd56, 0xfffffb08,
+    0xfffff8a1, 0xfffff6ee, 0xfffff6f3, 0xfffff9b5, 0x00000000, 0x00000a2d, 0x000017f4, 0x00002860,
+    0x000039e3, 0x00004a8b, 0x0000584b, 0x0000615d, 0x00006488, 0x0000615d, 0x0000584b, 0x00004a8b,
+    0x000039e3, 0x00002860, 0x000017f4, 0x00000a2d, 0x00000000, 0xfffff9b5, 0xfffff6f3, 0xfffff6ee,
+    0xfffff8a1, 0xfffffb08, 0xfffffd56, 0xffffff0b, 0x00000000, 0x00000050, 0x0000003f, 0x00000014,
+    0x00000000
+]
+
+def hex_to_decimal(hex_value):
+    # Convert hex to signed 32-bit integer
+    if hex_value & 0x80000000:
+        hex_value -= 0x100000000
+    # Convert to fixed-point with 16 fractional bits
+    return hex_value / 2**16
+
+decimal_values = [hex_to_decimal(value) for value in hex_values]
+df = pd.DataFrame()
+df['Impulse Response'] = decimal_values
+fig, ax = plt.subplots()
+df.plot(ax=ax)
+ax.set_xlabel('Sample Index')
+ax.set_ylabel('Impulse Response')
+plt.show()
diff --git a/src/5_Blur_Integration/FFT_files/low_pass_conv.sv b/src/5_Blur_Integration/FFT_files/low_pass_conv.sv
new file mode 100644
index 0000000..55b7491
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/low_pass_conv.sv
@@ -0,0 +1,72 @@
+module low_pass_conv #(parameter W, W_FRAC) (
+    input clk,
+    dstream.in x,
+    dstream.out y
+);
+
+    // 1. Assign x.ready: we are ready for data if the module we output to (y.ready) is ready (this module does not exert backpressure).
+    assign x.ready = y.ready;
+
+    // Impulse response h[n]: (32-bit, 16-bit frac, 2's complement)
+    localparam N = 41;
+    logic signed [W-1:0] h [0:N-1] = '{32'h00000000, 32'h00000014, 32'h0000003f, 32'h00000050, 32'h00000000, 32'hffffff0b, 32'hfffffd56, 32'hfffffb08, 32'hfffff8a1, 32'hfffff6ee, 32'hfffff6f3, 32'hfffff9b5, 32'h00000000, 32'h00000a2d, 32'h000017f4, 32'h00002860, 32'h000039e3, 32'h00004a8b, 32'h0000584b, 32'h0000615d, 32'h00006488, 32'h0000615d, 32'h0000584b, 32'h00004a8b, 32'h000039e3, 32'h00002860, 32'h000017f4, 32'h00000a2d, 32'h00000000, 32'hfffff9b5, 32'hfffff6f3, 32'hfffff6ee, 32'hfffff8a1, 32'hfffffb08, 32'hfffffd56, 32'hffffff0b, 32'h00000000, 32'h00000050, 32'h0000003f, 32'h00000014, 32'h00000000};
+
+    // 2. Make a shift register of depth = impulse response size. Feed x.data into this shift register when x.valid=1 and x.ready=1 (and shift all other data in the shift reg).
+    logic signed [W-1:0] shift_reg [0:N-1];
+    always_ff @(posedge clk) begin : h_shift_register
+
+        // On a handshake (x.valid & x.ready), shift signed'(x.data) into shift_reg and shift everything.
+        // Hint: use a for loop.
+
+        //check that we are valid and ready for shift
+        if(x.valid && x.ready) begin
+
+            // for each register shift it along by one
+            for(int i = N - 1; i > 0; i--) begin
+                shift_reg[i] <= shift_reg[i - 1];
+            end
+            // set the newest element to be the new data
+            shift_reg[0] <= signed'(x.data);
+        end
+
+    end
+
+    // 3. Multiply each register in the shift register by its repsective h[n] value, for n = 0 to N.
+    logic signed [2*W-1:0] mult_result [0:N-1];  // 2*W as the multiply doubles width
+    always_comb begin : h_multiply
+        // Set mult_result for each n value.
+        // Hint: use a for loop.
+        for(int i=0; i < N; ++i) begin
+            // multiply each register value by the h value
+            mult_result[i] = shift_reg[i] * h[i];
+        end
+
+    end
+
+    // 4. Add all of the multiplication results together and shift the result into the output buffer.
+    logic signed [$clog2(N)+2*W:0] macc; // $clog2(N)+1 to accomodate for overflows over the 41 additions.
+    always_comb begin : MAC
+        macc = 0;
+        // Set macc to be the sum of all elements in mult_result.
+        // Hint: use a for loop.
+        for(int i=0; i<N; ++i) begin
+            macc = macc + mult_result[i];
+        end
+    end
+
+    // 5. Output reg: use y.data as a register, load the result of the MACC into y.data if x.valid and x.ready are high (i.e. data is moving).
+    // y.valid should be set as a register here too.
+    logic overflow; // Optional (not marked): detect for overflow.
+    logic x_valid_q = 1'b0; // Delay x.valid by 1 clock cycle
+    always_ff @(posedge clk) begin : output_reg
+        y.valid <= 1'b0; /*FIX*/
+        if (x.valid & x.ready) begin
+            y.data <= macc[$clog2(N) + 2*W - 1: W_FRAC]; // Take one less bit to truncate and then go to only the integer part
+            overflow <= (macc < 0) ? 1 : 0;
+
+            x_valid_q <= 1'b1;    // Delay x.valid by 1 clock cycle
+            y.valid <= x_valid_q; // 2 clock cycles for valid data to get from x to y
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/FFT_files/mic/adc_pll.ppf b/src/5_Blur_Integration/FFT_files/mic/adc_pll.ppf
new file mode 100644
index 0000000..c2127d2
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/adc_pll.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="adc_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/src/5_Blur_Integration/FFT_files/mic/adc_pll.qip b/src/5_Blur_Integration/FFT_files/mic/adc_pll.qip
new file mode 100644
index 0000000..63d8308
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/adc_pll.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "adc_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "adc_pll_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "adc_pll.ppf"]
diff --git a/src/5_Blur_Integration/FFT_files/mic/adc_pll.v b/src/5_Blur_Integration/FFT_files/mic/adc_pll.v
new file mode 100644
index 0000000..9435835
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/adc_pll.v
@@ -0,0 +1,321 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: adc_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module adc_pll (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire2 = 1'h0;
+	wire [4:0] sub_wire3;
+	wire  sub_wire5;
+	wire  sub_wire0 = inclk0;
+	wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
+	wire [0:0] sub_wire4 = sub_wire3[0:0];
+	wire  c0 = sub_wire4;
+	wire  locked = sub_wire5;
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire1),
+				.clk (sub_wire3),
+				.locked (sub_wire5),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 3125,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1152,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=adc_pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.431999"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.43200000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "adc_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1152"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/5_Blur_Integration/FFT_files/mic/adc_pll_bb.v b/src/5_Blur_Integration/FFT_files/mic/adc_pll_bb.v
new file mode 100644
index 0000000..e8639fb
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/adc_pll_bb.v
@@ -0,0 +1,211 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: adc_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module adc_pll (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.431999"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.43200000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "adc_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1152"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL adc_pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/5_Blur_Integration/FFT_files/mic/i2c_master.sv b/src/5_Blur_Integration/FFT_files/mic/i2c_master.sv
new file mode 100644
index 0000000..e1b1730
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/i2c_master.sv
@@ -0,0 +1,110 @@
+module i2c_master (
+    input  clk,      // 20 kHz input clock. Assume this is the correct frequency for the I2C transfer.
+
+    output i2c_scl,  // I2C clock
+    inout  i2c_sda,  // I2C DATA
+
+    input  [6:0] slav_addr,
+    input  read_not_write,
+    input  [7:0] reg_addr,
+
+    input  [7:0] write_data,
+    input  write_valid,
+    output logic write_ready,
+
+    output logic [7:0] read_data,
+    output logic read_valid,
+    input  read_ready,
+
+    output logic error
+);
+
+    logic sda_set;  // sda_set=1 means use high impedance on the I2C data line, so the line is undriven by the master. sda_set=0 means pull-down the I2C data line to a 0 (master drives the line).
+    logic scl_idle; // This indicates when the I2C clock should be idle (=1).
+    
+    enum logic [3:0] {INIT, START, SLAVE_ADDR, READ_OR_WRITE, ACK1, REG_ADDR, ACK2, DATA, ACK3, STOP0, STOP1, STOP2} state = INIT, next_state;
+        
+    assign i2c_scl = scl_idle | ~clk;     // The SCL is 1 if idle, else it is the inverted i2c clock (this is a trick so that the positive edge of SCL is always inbetween SDA transitions!).
+    assign i2c_sda = sda_set ? 1'bz : 0 ; // I2C: set the data line to the high-impedance Z state when sending a `1`, else set to `0`.
+
+    logic ack_1, ack_2, ack_3;            // Acknowledgement status bits for each separate ACK : 1.After slave address, 2.After register address and 3.After data.
+    assign error = ack_1 | ack_2 | ack_3; // If any of the acknowledgements from the receiver are high (NACK), then an error has occured (acknowledge is active-low).
+    
+    logic [2:0] counter = 0; // Use this to count bits.
+    
+    localparam slave_address_length = 7;
+    localparam slave_register_address = 8;
+    localparam slave_data_length = 8;
+    //TODO Complete the FSM next-state table. Most states automatically transistion to the next (these are listed in order):
+    always_comb begin : fsm_next_state
+        next_state = INIT;
+        case(state)
+            INIT:          next_state = (write_valid && write_ready) ? START : INIT; // Remember to check for a handshake (valid & ready). Move to the START state once a 'write_valid' signal has been received.
+            START:         next_state = SLAVE_ADDR;
+            SLAVE_ADDR:    next_state = (counter == slave_address_length - 1) ? READ_OR_WRITE : SLAVE_ADDR; // Send slave address to the device by incrementing the bit counter.
+            READ_OR_WRITE: next_state = ACK1;
+            ACK1:          next_state = REG_ADDR;
+            REG_ADDR:      next_state = (counter == slave_register_address - 1) ? ACK2 : REG_ADDR;  // Send the register address to the device by incrementing the bit counter.
+            ACK2:          next_state = DATA;
+            DATA:          next_state = (counter == slave_data_length - 1) ? ACK3 : DATA;  // Send the data to the device by incrementing the bit counter.
+            ACK3:          next_state = STOP0;
+            STOP0:         next_state = STOP1;  // Here, we use 3 STOP states to deal with the SCL and SDA stop symbol timings.
+            STOP1:         next_state = STOP2;
+            STOP2:         next_state = INIT;
+        endcase
+    end    
+
+    logic  [6:0] slav_addr_temp;
+    logic  [7:0] write_data_temp;
+    logic  [7:0] reg_addr_temp;
+    logic        read_not_write_temp;
+
+    always_ff @(posedge clk) begin : registers
+        state <= next_state;
+        // Register the acknowledgements (should all be zero):
+        case (state)
+            INIT:   begin ack_1 <= 0 ; ack_2 <= 0 ; ack_3 <= 0; end // Reset ACK registers.
+            ACK1:         ack_1 <= i2c_sda;
+            ACK2:         ack_2 <= i2c_sda;
+            ACK3:         ack_3 <= i2c_sda;
+        endcase
+        // Bit counter (only counts in the sending states).
+        if (state == SLAVE_ADDR || state == REG_ADDR || state == DATA) begin
+            counter <= counter + 1; // Only count bits in these states (i.e. when we are actually sending information)
+        end
+        else counter <= 0;
+        // Store the data transferred on the handshake:
+        if (write_ready && write_valid) begin
+            slav_addr_temp      <= slav_addr;
+            write_data_temp     <= write_data;
+            reg_addr_temp       <= reg_addr;
+            read_not_write_temp <= read_not_write;
+        end
+    end
+
+    //TODO Complete the following FSM output table:
+    always_comb begin : fsm_output
+        sda_set = 1;      // Default : SDA line is high (undriven).
+        scl_idle = 0;     // Default : The clock is idle (high). You can change this if you think it's easier.
+        write_ready = 0;  // Default : We are not ready to send a write transaction.
+        case (state)
+            INIT:          begin write_ready = 1'b1;
+                                 scl_idle = 1'b1; end // Reset registers. Indicate that we are *ready* for a write transaction.
+            START:         begin scl_idle = 1; sda_set = 0; end // Pull SDA down for start condition (sda_set).
+            SLAVE_ADDR:    begin sda_set = slav_addr_temp[6 - counter]; end // SLAVE ADDR: The address of the slave we wish to write to. Set sda_set accordingly.
+            READ_OR_WRITE: begin sda_set = read_not_write_temp; end
+            ACK1:          begin sda_set = 1'b1; end
+            REG_ADDR:      begin sda_set = reg_addr_temp[7 - counter]; end // REG ADDR: The address of the register we wish to write to. Set sda_set accordingly.
+            ACK2:          begin sda_set = 1'b1; end
+            DATA:          begin sda_set = write_data_temp[7 - counter]; end // DATA: The data we wish to write. Set sda_set accordingly.
+            ACK3:          begin sda_set = 1'b1; end
+            STOP0:         begin sda_set = 1'b0; end // Here, we use 3 STOP states to deal with the SCL and SDA stop symbol timings.
+            STOP1:         begin scl_idle = 1'b1; sda_set = 1'b0; end //   For each of these 3 STOP states, set sda_set and scl_idle appropriately.
+            STOP2:         begin sda_set = 1'b1; scl_idle = 1'b1; end
+        endcase
+    end
+
+
+    always if (read_not_write) $error("I2C read transaction not implemented!");
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/mic/i2c_pll.ppf b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.ppf
new file mode 100644
index 0000000..7269dee
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="i2c_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/src/5_Blur_Integration/FFT_files/mic/i2c_pll.qip b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.qip
new file mode 100644
index 0000000..aa8c95b
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "i2c_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "i2c_pll_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "i2c_pll.ppf"]
diff --git a/src/5_Blur_Integration/FFT_files/mic/i2c_pll.v b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.v
new file mode 100644
index 0000000..ec06a71
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/i2c_pll.v
@@ -0,0 +1,321 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: i2c_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module i2c_pll (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2500,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=i2c_pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "i2c_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/5_Blur_Integration/FFT_files/mic/i2c_pll_bb.v b/src/5_Blur_Integration/FFT_files/mic/i2c_pll_bb.v
new file mode 100644
index 0000000..ecee61b
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/i2c_pll_bb.v
@@ -0,0 +1,211 @@
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: i2c_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module i2c_pll (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "i2c_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL i2c_pll_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/src/5_Blur_Integration/FFT_files/mic/mic_load.sv b/src/5_Blur_Integration/FFT_files/mic/mic_load.sv
new file mode 100644
index 0000000..ef94416
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/mic_load.sv
@@ -0,0 +1,51 @@
+`timescale 1ps/1ps
+module mic_load #(parameter N=16) (
+	input bclk, // Assume a 18.432 MHz clock
+    input adclrc,
+	input adcdat,
+    // No ready signal nor handshake: as this module streams live audio data, it cannot be stalled, therefore we only have the valid signal.
+    output logic valid,
+    output logic [N-1:0] sample_data
+);
+    // Assume that i2c has already configured the CODEC for LJ data, MSB-first and N-bit samples.
+
+    // Rising edge detect on ADCLRC to sense left channel
+    logic redge_adclrc, adclrc_q; 
+    always_ff @(posedge  bclk) begin : adclrc_rising_edge_ff
+        adclrc_q <= adclrc;
+    end
+    assign redge_adclrc = ~adclrc_q & adclrc; // rising edge detected!
+
+    /*
+     * Implement the Timing diagram.
+     * -----------------------------
+     * You should use a temporary N-bit RX register to store the ADCDAT bitstream from MSB to LSB.
+     * Remember that MSB is first, LSB is last.
+     * Use `temp_rx_data[(N-1)-bit_index] <= adcdat;`
+     * BCLK rising is your trigger to sample the value of ADCDAT into the register at the appropriate bit index.
+     * ADCLRC rising (see `redge_adclrc`) signals that the MSB should be sampled on the next rising edge of BCLK.
+     * With the above, think about when and how you would reset your bit_index counter.
+     */
+
+     logic [N - 1:0] temp_rx_data;
+     integer bit_index = 0;
+     // flip flop to set clock
+     always_ff @(posedge bclk) begin
+        if (redge_adclrc) begin
+            temp_rx_data[N - 1] <= adcdat;
+            bit_index <= 1;
+            valid <= 0;
+        end
+        else if (bit_index <=  N - 1) begin
+            temp_rx_data[(N - 1) - bit_index] <= adcdat;
+            bit_index <= bit_index + 1;
+            valid <= 0;
+        end
+        else begin
+            valid <= 1;
+        end
+     end
+
+    assign sample_data = temp_rx_data;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/mic/set_audio_encoder.sv b/src/5_Blur_Integration/FFT_files/mic/set_audio_encoder.sv
new file mode 100644
index 0000000..e0bca4b
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/set_audio_encoder.sv
@@ -0,0 +1,59 @@
+module set_audio_encoder (
+    input      i2c_clk, // Assuming a 20 kHz clock is input (for testbench)
+    output     I2C_SCLK,
+    inout      I2C_SDAT
+);
+    logic [23:0] data;       
+    logic valid, ready;
+    logic error;
+
+    // Instantiate I2C master module
+    i2c_master u1 (.clk(i2c_clk), .i2c_scl(I2C_SCLK), .i2c_sda(I2C_SDAT), .slav_addr(data[23-:7]), .read_not_write(data[16]), .reg_addr(data[15-:8]), .write_data(data[7:0]), .write_ready(ready), .write_valid(valid), .error(error));
+
+    // Now, let's use a FSM to control the I2C master module.
+    // We will feed the I2C module a set of instructions that determine the registers to set and values to set them to (see always_comb block at the bottom).
+    enum logic [1:0] {LOAD, WAIT, NEXT} state = LOAD, next_state;            
+
+    localparam INIT_CMDS_N = 11;
+    logic [3:0] initialise_index = 0;
+    
+    always_comb begin : fsm_next_state
+        next_state = LOAD;
+        case (state)
+            LOAD : next_state = initialise_index < INIT_CMDS_N ? WAIT : LOAD; // Stop sending to the audio encoder chip after we step through all initialisation commands.
+            WAIT : next_state = ready ? (error === 1 ? LOAD : NEXT) : WAIT;  // Wait until the I2C module is finished sending bits. If it finished but there was an error, try again by restarting from the LOAD state.
+            NEXT : next_state = LOAD; 
+        endcase
+    end
+                                                        
+    logic [15:0]    reg_and_data;
+    logic done;
+    assign done = (initialise_index >= INIT_CMDS_N && ready);
+                            
+    always_ff @(posedge i2c_clk) begin : fsm_ff
+        state <= next_state;
+        case(state)
+            LOAD: data <= {7'h1A,1'b0,reg_and_data};      // 0x1A is the 7-bit address of the Audio Encoder chip. The 1-bit is R/W=0 for writing. Now, reg_and_data is 7bits reg address and 9bits data to write into that register.
+            NEXT: initialise_index <= initialise_index+1; // Increment the initialise index to read the next initialisation command from the sequence.
+        endcase
+    end
+    assign valid = (state == WAIT); // Assert valid to get the I2C module to start sending.
+
+    // The following is a ROM that contains all initialisation commands to setup the audio codec, in order.
+    always_comb begin : config_data_cmds
+        case(initialise_index)
+            //    Audio Config Data  // Format: {7 bits for reg, 9 bits for value}
+            1:        reg_and_data    <=    {7'h00, 9'hFF}; // Set SET_LIN_L:     +12dB left channel line input volume, enable mute to ADC, disable simultaneous load.
+            2:        reg_and_data    <=    {7'h01, 9'hFF}; // Set SET_LIN_R:     +12dB right channel line input volume, enable mute to ADC, disable simultaneous load.
+            3:        reg_and_data    <=    {7'h02, 9'hFD}; // Set SET_HEAD_L:    +4dB left channel headphone output volume, zero cross detect enabled, disable simultaneous load.
+            4:        reg_and_data    <=    {7'h03, 9'hFD}; // Set SET_HEAD_R:    +4dB right channel headphone output volume, zero cross detect enabled, disable simultaneous load.
+            5:        reg_and_data    <=    {7'h04, 9'h3D}; // Set A_PATH_CTRL:   Microphone boost enabled, disable mic mute to ADC, mic line select to ADC, enable bypass, select DAC, enable side tone, -6dB side tone attenuation
+            6:        reg_and_data    <=    {7'h05, 9'h00}; // Set D_PATH_CTRL:   Enable high pass filter, disable de-emphasis, disable soft-mute, clear DC offset when high pass filter disabled.
+            7:        reg_and_data    <=    {7'h06, 9'h00}; // POWER_DOWN_CTRL:   Disable all power down options.       
+            8:        reg_and_data    <=    {7'h07, 9'h41}; // SET_FORMAT:        MSB-first Left-Justified audio data format, 16 bit audio data length, right-channel DAC data when DACLRC is low, right channel DAC data right, enable MASTER mode, don't invert BCLK.
+            9:        reg_and_data    <=    {7'h08, 9'h02}; // SAMPLE_CTRL:       Normal mode (256/384fs), Base Over-Sampling Ratio = 384fs, ADC and DAC sample rate control = 0, core clock is MCLK, CLOCKOUT is core clock.
+            10:       reg_and_data    <=    {7'h09, 9'h01}; // SET_ACTIVE:        Bit-0: Set interface to Active.
+            default : reg_and_data    <=    16'd0 ;
+        endcase
+    end
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/mic/top_level.sv b/src/5_Blur_Integration/FFT_files/mic/top_level.sv
new file mode 100644
index 0000000..1c9443a
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/mic/top_level.sv
@@ -0,0 +1,33 @@
+module top_level (
+	input CLOCK_50,
+	output	I2C_SCLK,
+	inout		I2C_SDAT,
+	input		AUD_ADCDAT,
+	input   AUD_BCLK,
+	output   AUD_XCK,
+	input    AUD_ADCLRCK,
+	output  logic [17:0] LEDR
+);
+
+	logic adc_clk; adc_pll adc_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(adc_clk)); // generate 18.432 MHz clock
+	logic i2c_clk; i2c_pll i2c_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(i2c_clk)); // generate 20 kHz clock
+
+	set_audio_encoder set_codec_u (.i2c_clk(i2c_clk), .I2C_SCLK(I2C_SCLK), .I2C_SDAT(I2C_SDAT));
+		
+	logic [15:0] data;
+		
+	mic_load #(.N(16)) u_mic_load (
+    .adclrc(AUD_ADCLRCK),
+	 .bclk(AUD_BCLK),
+	 .adcdat(AUD_ADCDAT),
+    .sample_data(data)
+   );
+	
+	assign AUD_XCK = adc_clk;
+		
+	always_comb begin
+		if (data[15]) LEDR[15:0] <= (~data[15:0]+1); // magnitude of a negative number (2's complement)
+		else LEDR[15:0] <= data[15:0];
+	end
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/Butterfly.v b/src/5_Blur_Integration/FFT_files/r22sdf/Butterfly.v
new file mode 100644
index 0000000..61df798
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/Butterfly.v
@@ -0,0 +1,32 @@
+//----------------------------------------------------------------------
+//  Butterfly: Add/Sub and Scaling
+//----------------------------------------------------------------------
+module Butterfly #(
+    parameter   WIDTH = 16,
+    parameter   RH = 0  //  Round Half Up
+)(
+    input   signed  [WIDTH-1:0] x0_re,  //  Input Data #0 (Real)
+    input   signed  [WIDTH-1:0] x0_im,  //  Input Data #0 (Imag)
+    input   signed  [WIDTH-1:0] x1_re,  //  Input Data #1 (Real)
+    input   signed  [WIDTH-1:0] x1_im,  //  Input Data #1 (Imag)
+    output  signed  [WIDTH-1:0] y0_re,  //  Output Data #0 (Real)
+    output  signed  [WIDTH-1:0] y0_im,  //  Output Data #0 (Imag)
+    output  signed  [WIDTH-1:0] y1_re,  //  Output Data #1 (Real)
+    output  signed  [WIDTH-1:0] y1_im   //  Output Data #1 (Imag)
+);
+
+wire signed [WIDTH:0]   add_re, add_im, sub_re, sub_im;
+
+//  Add/Sub
+assign  add_re = x0_re + x1_re;
+assign  add_im = x0_im + x1_im;
+assign  sub_re = x0_re - x1_re;
+assign  sub_im = x0_im - x1_im;
+
+//  Scaling
+assign  y0_re = (add_re + RH) >>> 1;
+assign  y0_im = (add_im + RH) >>> 1;
+assign  y1_re = (sub_re + RH) >>> 1;
+assign  y1_im = (sub_im + RH) >>> 1;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/DelayBuffer.v b/src/5_Blur_Integration/FFT_files/r22sdf/DelayBuffer.v
new file mode 100644
index 0000000..19bff72
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/DelayBuffer.v
@@ -0,0 +1,32 @@
+//----------------------------------------------------------------------
+//  DelayBuffer: Generate Constant Delay
+//----------------------------------------------------------------------
+module DelayBuffer #(
+    parameter   DEPTH = 32,
+    parameter   WIDTH = 16
+)(
+    input               clock,  //  Master Clock
+    input   [WIDTH-1:0] di_re,  //  Data Input (Real)
+    input   [WIDTH-1:0] di_im,  //  Data Input (Imag)
+    output  [WIDTH-1:0] do_re,  //  Data Output (Real)
+    output  [WIDTH-1:0] do_im   //  Data Output (Imag)
+);
+
+reg [WIDTH-1:0] buf_re[0:DEPTH-1];
+reg [WIDTH-1:0] buf_im[0:DEPTH-1];
+integer n;
+
+//  Shift Buffer
+always @(posedge clock) begin
+    for (n = DEPTH-1; n > 0; n = n - 1) begin
+        buf_re[n] <= buf_re[n-1];
+        buf_im[n] <= buf_im[n-1];
+    end
+    buf_re[0] <= di_re;
+    buf_im[0] <= di_im;
+end
+
+assign  do_re = buf_re[DEPTH-1];
+assign  do_im = buf_im[DEPTH-1];
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/FFT.v b/src/5_Blur_Integration/FFT_files/r22sdf/FFT.v
new file mode 100644
index 0000000..2875ebc
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/FFT.v
@@ -0,0 +1,89 @@
+//----------------------------------------------------------------------
+//  FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback
+//----------------------------------------------------------------------
+module FFT #(
+    parameter   WIDTH = 32
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+//----------------------------------------------------------------------
+//  Data must be input consecutively in natural order.
+//  The result is scaled to 1/N and output in bit-reversed order.
+//----------------------------------------------------------------------
+
+wire            su1_do_en;
+wire[WIDTH-1:0] su1_do_re;
+wire[WIDTH-1:0] su1_do_im;
+wire            su2_do_en;
+wire[WIDTH-1:0] su2_do_re;
+wire[WIDTH-1:0] su2_do_im;
+wire            su3_do_en;
+wire[WIDTH-1:0] su3_do_re;
+wire[WIDTH-1:0] su3_do_im;
+wire            su4_do_en;
+wire[WIDTH-1:0] su4_do_re;
+wire[WIDTH-1:0] su4_do_im;
+
+SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (di_en      ),  //  i
+    .di_re  (di_re      ),  //  i
+    .di_im  (di_im      ),  //  i
+    .do_en  (su1_do_en  ),  //  o
+    .do_re  (su1_do_re  ),  //  o
+    .do_im  (su1_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su1_do_en  ),  //  i
+    .di_re  (su1_do_re  ),  //  i
+    .di_im  (su1_do_im  ),  //  i
+    .do_en  (su2_do_en  ),  //  o
+    .do_re  (su2_do_re  ),  //  o
+    .do_im  (su2_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su2_do_en  ),  //  i
+    .di_re  (su2_do_re  ),  //  i
+    .di_im  (su2_do_im  ),  //  i
+    .do_en  (su3_do_en  ),  //  o
+    .do_re  (su3_do_re  ),  //  o
+    .do_im  (su3_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su3_do_en  ),  //  i
+    .di_re  (su3_do_re  ),  //  i
+    .di_im  (su3_do_im  ),  //  i
+    .do_en  (su4_do_en  ),  //  o
+    .do_re  (su4_do_re  ),  //  o
+    .do_im  (su4_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su4_do_en  ),  //  i
+    .di_re  (su4_do_re  ),  //  i
+    .di_im  (su4_do_im  ),  //  i
+    .do_en  (do_en      ),  //  o
+    .do_re  (do_re      ),  //  o
+    .do_im  (do_im      )   //  o
+);
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/Multiply.v b/src/5_Blur_Integration/FFT_files/r22sdf/Multiply.v
new file mode 100644
index 0000000..6172571
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/Multiply.v
@@ -0,0 +1,35 @@
+//----------------------------------------------------------------------
+//  Multiply: Complex Multiplier
+//----------------------------------------------------------------------
+module Multiply #(
+    parameter   WIDTH = 16
+)(
+    input   signed  [WIDTH-1:0] a_re,
+    input   signed  [WIDTH-1:0] a_im,
+    input   signed  [WIDTH-1:0] b_re,
+    input   signed  [WIDTH-1:0] b_im,
+    output  signed  [WIDTH-1:0] m_re,
+    output  signed  [WIDTH-1:0] m_im
+);
+
+wire signed [WIDTH*2-1:0]   arbr, arbi, aibr, aibi;
+wire signed [WIDTH-1:0]     sc_arbr, sc_arbi, sc_aibr, sc_aibi;
+
+//  Signed Multiplication
+assign  arbr = a_re * b_re;
+assign  arbi = a_re * b_im;
+assign  aibr = a_im * b_re;
+assign  aibi = a_im * b_im;
+
+//  Scaling
+assign  sc_arbr = arbr >>> (WIDTH-1);
+assign  sc_arbi = arbi >>> (WIDTH-1);
+assign  sc_aibr = aibr >>> (WIDTH-1);
+assign  sc_aibi = aibi >>> (WIDTH-1);
+
+//  Sub/Add
+//  These sub/add may overflow if unnormalized data is input.
+assign  m_re = sc_arbr - sc_aibi;
+assign  m_im = sc_arbi + sc_aibr;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit2.v b/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit2.v
new file mode 100644
index 0000000..13bcf5a
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit2.v
@@ -0,0 +1,94 @@
+//----------------------------------------------------------------------
+//  SdfUnit2: Radix-2 SDF Dedicated for Twiddle Resolution M = 2
+//----------------------------------------------------------------------
+module SdfUnit2 #(
+    parameter   WIDTH = 16, //  Data Bit Length
+    parameter   BF_RH = 0   //  Butterfly Round Half Up
+)(
+    input                   clock,  //  Master Clock
+    input                   reset,  //  Active High Asynchronous Reset
+    input                   di_en,  //  Input Data Enable
+    input       [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input       [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output  reg             do_en,  //  Output Data Enable
+    output  reg [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  reg [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+
+//----------------------------------------------------------------------
+//  Internal Regs and Nets
+//----------------------------------------------------------------------
+reg             bf_en;      //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] x0_re;      //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] x0_im;      //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] x1_re;      //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] x1_im;      //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] y0_re;      //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] y0_im;      //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] y1_re;      //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] y1_im;      //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db_di_re;   //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db_di_im;   //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db_do_re;   //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db_do_im;   //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf_sp_re;   //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf_sp_im;   //  Single-Path Data Output (Imag)
+reg             bf_sp_en;   //  Single-Path Data Enable
+
+//----------------------------------------------------------------------
+//  Butterfly Add/Sub
+//----------------------------------------------------------------------
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf_en <= 1'b0;
+    end else begin
+        bf_en <= di_en ? ~bf_en : 1'b0;
+    end
+end
+
+//  Set unknown value x for verification
+assign  x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
+assign  x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
+assign  x1_re = bf_en ? di_re : {WIDTH{1'bx}};
+assign  x1_im = bf_en ? di_im : {WIDTH{1'bx}};
+
+Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
+    .x0_re  (x0_re  ),  //  i
+    .x0_im  (x0_im  ),  //  i
+    .x1_re  (x1_re  ),  //  i
+    .x1_im  (x1_im  ),  //  i
+    .y0_re  (y0_re  ),  //  o
+    .y0_im  (y0_im  ),  //  o
+    .y1_re  (y1_re  ),  //  o
+    .y1_im  (y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
+    .clock  (clock      ),  //  i
+    .di_re  (db_di_re   ),  //  i
+    .di_im  (db_di_im   ),  //  i
+    .do_re  (db_do_re   ),  //  o
+    .do_im  (db_do_im   )   //  o
+);
+
+assign  db_di_re = bf_en ? y1_re : di_re;
+assign  db_di_im = bf_en ? y1_im : di_im;
+assign  bf_sp_re = bf_en ? y0_re : db_do_re;
+assign  bf_sp_im = bf_en ? y0_im : db_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf_sp_en <= 1'b0;
+        do_en <= 1'b0;
+    end else begin
+        bf_sp_en <= di_en;
+        do_en <= bf_sp_en;
+    end
+end
+
+always @(posedge clock) begin
+    do_re <= bf_sp_re;
+    do_im <= bf_sp_im;
+end
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit_TC.v b/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit_TC.v
new file mode 100644
index 0000000..6fdf6f8
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/SdfUnit_TC.v
@@ -0,0 +1,344 @@
+//----------------------------------------------------------------------
+//  SdfUnit: Radix-2^2 SDF Unit with Twiddle Conversion
+//----------------------------------------------------------------------
+module SdfUnit #(
+    parameter   N = 64,     //  Number of FFT Point
+    parameter   M = 64,     //  Twiddle Resolution
+    parameter   WIDTH = 16, //  Data Bit Length
+    parameter   T4_EN = 0,  //  Use TwiddleConvert4
+    parameter   T8_EN = 1,  //  Use TwiddleConvert8
+    parameter   TW_FF = 1,  //  Use Twiddle Output Register
+    parameter   TC_FF = 1,  //  Use TwiddleConvert Output Register
+    parameter   B1_RH = 0,  //  1st Butterfly Round Half Up
+    parameter   B2_RH = 1,  //  2nd Butterfly Round Half Up
+    parameter   LP = 0      //  Power Saving
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+
+//  log2 constant function
+function integer log2;
+    input integer x;
+    integer value;
+    begin
+        value = x-1;
+        for (log2=0; value>0; log2=log2+1)
+            value = value>>1;
+    end
+endfunction
+
+localparam  LOG_N = log2(N);    //  Bit Length of N
+localparam  LOG_M = log2(M);    //  Bit Length of M
+
+//  When using Twiddle Conversion, start counting 1T earlier
+localparam  TC_EN = T4_EN | T8_EN;
+localparam  EARLY = TC_EN & TW_FF & TC_FF;
+
+//----------------------------------------------------------------------
+//  Internal Regs and Nets
+//----------------------------------------------------------------------
+//  1st Butterfly
+reg [LOG_N-1:0] di_count;   //  Input Data Count
+wire            bf1_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf1_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db1_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db1_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db1_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db1_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf1_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf1_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf1_sp_en;  //  Single-Path Data Enable
+reg [LOG_N-1:0] bf1_count;  //  Single-Path Data Count
+wire            bf1_start;  //  Single-Path Output Trigger
+wire            bf1_end;    //  End of Single-Path Data
+wire            bf1_mj;     //  Twiddle (-j) Enable
+reg [WIDTH-1:0] bf1_do_re;  //  1st Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf1_do_im;  //  1st Butterfly Output Data (Imag)
+
+//  2nd Butterfly
+reg             bf2_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf2_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db2_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db2_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db2_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db2_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf2_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf2_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf2_ct_en;  //  Single-Path Data Count Enable
+reg [LOG_N-1:0] bf2_count;  //  Single-Path Data Count
+wire            bf2_start_0t;// Single-Path Output Trigger
+reg             bf2_start_1t;// Single-Path Output Trigger
+wire            bf2_start;  //  Single-Path Output Trigger
+wire            bf2_end;    //  End of Single-Path Data
+reg             bf2_ct_en_1d;// Single-Path Data Enable When Using TC
+wire            bf2_sp_en;  //  Single-Path Data Enable
+reg [WIDTH-1:0] bf2_do_re;  //  2nd Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf2_do_im;  //  2nd Butterfly Output Data (Imag)
+reg             bf2_do_en;  //  2nd Butterfly Output Data Enable
+
+//  Multiplication
+wire[1:0]       tw_sel;     //  Twiddle Select (2n/n/3n)
+wire[LOG_N-3:0] tw_num;     //  Twiddle Number (n)
+wire[LOG_N-1:0] tw_addr;    //  Twiddle Table Address
+wire[LOG_N-1:0] tc_addr;    //  Twiddle Address from TwiddleConvert
+wire[LOG_N-1:0] tw_addr_tc; //  Twiddle Address after TC_EN Switch
+wire[WIDTH-1:0] tw_re;      //  Twiddle Data from Table (Real)
+wire[WIDTH-1:0] tw_im;      //  Twiddle Data from Table (Imag)
+wire[WIDTH-1:0] tc_re;      //  Twiddle Data from TwiddleConvert (Real)
+wire[WIDTH-1:0] tc_im;      //  Twiddle Data from TwiddleConvert (Imag)
+reg             tw_nz;      //  Multiplication Enable
+reg             tw_nz_1d;   //  Multiplication Enable
+wire            mu_en;      //  Multiplication Enable
+wire[WIDTH-1:0] mu_a_re;    //  Multiplier Input (Real)
+wire[WIDTH-1:0] mu_a_im;    //  Multiplier Input (Imag)
+wire[WIDTH-1:0] mu_b_re;    //  Twiddle Data to Multiplier (Real)
+wire[WIDTH-1:0] mu_b_im;    //  Twiddle Data to Multiplier (Imag)
+wire[WIDTH-1:0] mu_m_re;    //  Multiplier Output (Real)
+wire[WIDTH-1:0] mu_m_im;    //  Multiplier Output (Imag)
+reg [WIDTH-1:0] mu_do_re;   //  Multiplication Output Data (Real)
+reg [WIDTH-1:0] mu_do_im;   //  Multiplication Output Data (Imag)
+reg             mu_do_en;   //  Multiplication Output Data Enable
+
+//----------------------------------------------------------------------
+//  1st Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        di_count <= {LOG_N{1'b0}};
+    end else begin
+        di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_bf = di_count[LOG_M-1];
+
+//  Reducing signal changes may reduce power consumption
+//  Set unknown value x for verification
+assign  bf1_x0_re = bf1_bf ? db1_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf1_x0_im = bf1_bf ? db1_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf1_x1_re = bf1_bf ? di_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf1_x1_im = bf1_bf ? di_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+
+Butterfly #(.WIDTH(WIDTH),.RH(B1_RH)) BF1 (
+    .x0_re  (bf1_x0_re  ),  //  i
+    .x0_im  (bf1_x0_im  ),  //  i
+    .x1_re  (bf1_x1_re  ),  //  i
+    .x1_im  (bf1_x1_im  ),  //  i
+    .y0_re  (bf1_y0_re  ),  //  o
+    .y0_im  (bf1_y0_im  ),  //  o
+    .y1_re  (bf1_y1_re  ),  //  o
+    .y1_im  (bf1_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
+    .clock  (clock      ),  //  i
+    .di_re  (db1_di_re  ),  //  i
+    .di_im  (db1_di_im  ),  //  i
+    .do_re  (db1_do_re  ),  //  o
+    .do_im  (db1_do_im  )   //  o
+);
+
+assign  db1_di_re = bf1_bf ? bf1_y1_re : di_re;
+assign  db1_di_im = bf1_bf ? bf1_y1_im : di_im;
+assign  bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ?  db1_do_im : db1_do_re;
+assign  bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf1_sp_en <= 1'b0;
+        bf1_count <= {LOG_N{1'b0}};
+    end else begin
+        bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
+        bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_start = (di_count == (2**(LOG_M-1)-1));
+assign  bf1_end = (bf1_count == (2**LOG_N-1));
+assign  bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
+
+always @(posedge clock) begin
+    bf1_do_re <= bf1_sp_re;
+    bf1_do_im <= bf1_sp_im;
+end
+
+//----------------------------------------------------------------------
+//  2nd Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock) begin
+    bf2_bf <= bf1_count[LOG_M-2];
+end
+
+//  Reducing signal changes may reduce power consumption
+//  Set unknown value x for verification
+assign  bf2_x0_re = bf2_bf ? db2_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf2_x0_im = bf2_bf ? db2_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf2_x1_re = bf2_bf ? bf1_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+assign  bf2_x1_im = bf2_bf ? bf1_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
+
+//  Negative bias occurs when RH=0 and positive bias occurs when RH=1.
+//  Using both alternately reduces the overall rounding error.
+Butterfly #(.WIDTH(WIDTH),.RH(B2_RH)) BF2 (
+    .x0_re  (bf2_x0_re  ),  //  i
+    .x0_im  (bf2_x0_im  ),  //  i
+    .x1_re  (bf2_x1_re  ),  //  i
+    .x1_im  (bf2_x1_im  ),  //  i
+    .y0_re  (bf2_y0_re  ),  //  o
+    .y0_im  (bf2_y0_im  ),  //  o
+    .y1_re  (bf2_y1_re  ),  //  o
+    .y1_im  (bf2_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
+    .clock  (clock      ),  //  i
+    .di_re  (db2_di_re  ),  //  i
+    .di_im  (db2_di_im  ),  //  i
+    .do_re  (db2_do_re  ),  //  o
+    .do_im  (db2_do_im  )   //  o
+);
+
+assign  db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
+assign  db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
+assign  bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
+assign  bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_ct_en <= 1'b0;
+        bf2_count <= {LOG_N{1'b0}};
+    end else begin
+        bf2_ct_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_ct_en;
+        bf2_count <= bf2_ct_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+
+//  When using Twiddle Conversion, start counting 1T earlier
+assign  bf2_start_0t = (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
+always @(posedge clock) begin
+    bf2_start_1t <= bf2_start_0t;
+end
+assign  bf2_start = EARLY ? bf2_start_0t : bf2_start_1t;
+assign  bf2_end = (bf2_count == (2**LOG_N-1));
+
+always @(posedge clock) begin
+    bf2_ct_en_1d <= bf2_ct_en;
+end
+assign  bf2_sp_en = EARLY ? bf2_ct_en_1d : bf2_ct_en;
+
+always @(posedge clock) begin
+    bf2_do_re <= bf2_sp_re;
+    bf2_do_im <= bf2_sp_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_do_en <= 1'b0;
+    end else begin
+        bf2_do_en <= bf2_sp_en;
+    end
+end
+
+//----------------------------------------------------------------------
+//  Multiplication
+//----------------------------------------------------------------------
+assign  tw_sel[1] = bf2_count[LOG_M-2];
+assign  tw_sel[0] = bf2_count[LOG_M-1];
+assign  tw_num = bf2_count << (LOG_N-LOG_M);
+assign  tw_addr = tw_num * tw_sel;
+
+Twiddle #(.TW_FF(TW_FF)) TW (
+    .clock  (clock      ),  //  i
+    .addr   (tw_addr_tc ),  //  i
+    .tw_re  (tw_re      ),  //  o
+    .tw_im  (tw_im      )   //  o
+);
+
+generate if (T4_EN) begin
+    TwiddleConvert4 #(.LOG_N(LOG_N),.WIDTH(WIDTH),.TW_FF(TW_FF),.TC_FF(TC_FF)) TC (
+        .clock      (clock  ),  //  i
+        .tw_addr    (tw_addr),  //  i
+        .tw_re      (tw_re  ),  //  i
+        .tw_im      (tw_im  ),  //  i
+        .tc_addr    (tc_addr),  //  o
+        .tc_re      (tc_re  ),  //  o
+        .tc_im      (tc_im  )   //  o
+    );
+end else if (T8_EN) begin
+    TwiddleConvert8 #(.LOG_N(LOG_N),.WIDTH(WIDTH),.TW_FF(TW_FF),.TC_FF(TC_FF)) TC (
+        .clock      (clock  ),  //  i
+        .tw_addr    (tw_addr),  //  i
+        .tw_re      (tw_re  ),  //  i
+        .tw_im      (tw_im  ),  //  i
+        .tc_addr    (tc_addr),  //  o
+        .tc_re      (tc_re  ),  //  o
+        .tc_im      (tc_im  )   //  o
+    );
+end else begin
+    assign  tc_addr = {LOG_N{1'bx}};
+    assign  tc_re = {WIDTH{1'bx}};
+    assign  tc_im = {WIDTH{1'bx}};
+end endgenerate
+
+assign  tw_addr_tc = TC_EN ? tc_addr : tw_addr;
+assign  mu_b_re = TC_EN ? tc_re : tw_re;
+assign  mu_b_im = TC_EN ? tc_im : tw_im;
+
+//  Multiplication is bypassed when twiddle address is 0.
+always @(posedge clock) begin
+    tw_nz <= (tw_addr != {LOG_N{1'b0}});
+    tw_nz_1d <= tw_nz;
+end
+//  When using Twiddle Conversion, address generated 1T Earlier
+assign  mu_en = EARLY ? tw_nz_1d : tw_nz;
+
+//  Set unknown value x for verification
+assign  mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
+assign  mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
+
+Multiply #(.WIDTH(WIDTH)) MU (
+    .a_re   (mu_a_re),  //  i
+    .a_im   (mu_a_im),  //  i
+    .b_re   (mu_b_re),  //  i
+    .b_im   (mu_b_im),  //  i
+    .m_re   (mu_m_re),  //  o
+    .m_im   (mu_m_im)   //  o
+);
+
+always @(posedge clock) begin
+    mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
+    mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        mu_do_en <= 1'b0;
+    end else begin
+        mu_do_en <= bf2_do_en;
+    end
+end
+
+//  No multiplication required at final stage
+assign  do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
+assign  do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
+assign  do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/Twiddle.v b/src/5_Blur_Integration/FFT_files/r22sdf/Twiddle.v
new file mode 100644
index 0000000..96e2220
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/Twiddle.v
@@ -0,0 +1,1063 @@
+//----------------------------------------------------------------------
+//  Twiddle: 1024-Point Twiddle Table for Radix-2^2 Butterfly
+//----------------------------------------------------------------------
+module Twiddle #(
+    parameter   TW_FF = 1   //  Use Output Register
+)(
+    input           clock,  //  Master Clock
+    input   [9:0]   addr,   //  Twiddle Factor Number
+    output  [15:0]  tw_re,  //  Twiddle Factor (Real)
+    output  [15:0]  tw_im   //  Twiddle Factor (Imag)
+);
+
+wire[15:0]  wn_re[0:1023];  //  Twiddle Table (Real)
+wire[15:0]  wn_im[0:1023];  //  Twiddle Table (Imag)
+wire[15:0]  mx_re;          //  Multiplexer output (Real)
+wire[15:0]  mx_im;          //  Multiplexer output (Imag)
+reg [15:0]  ff_re;          //  Register output (Real)
+reg [15:0]  ff_im;          //  Register output (Imag)
+
+assign  mx_re = wn_re[addr];
+assign  mx_im = wn_im[addr];
+
+always @(posedge clock) begin
+    ff_re <= mx_re;
+    ff_im <= mx_im;
+end
+
+assign  tw_re = TW_FF ? ff_re : mx_re;
+assign  tw_im = TW_FF ? ff_im : mx_im;
+
+//----------------------------------------------------------------------
+//  Twiddle Factor Value
+//----------------------------------------------------------------------
+//  Multiplication is bypassed when twiddle address is 0.
+//  Setting wn_re[0] = 0 and wn_im[0] = 0 makes it easier to check the waveform.
+//  It may also reduce power consumption slightly.
+//
+//      wn_re = cos(-2pi*n/1024)          wn_im = sin(-2pi*n/1024)
+assign  wn_re[ 0] = 16'h0000;   assign  wn_im[ 0] = 16'h0000;   //  0  1.000 -0.000
+assign  wn_re[ 1] = 16'h7FFF;   assign  wn_im[ 1] = 16'hFF37;   //  1  1.000 -0.006
+assign  wn_re[ 2] = 16'h7FFE;   assign  wn_im[ 2] = 16'hFE6E;   //  2  1.000 -0.012
+assign  wn_re[ 3] = 16'h7FFA;   assign  wn_im[ 3] = 16'hFDA5;   //  3  1.000 -0.018
+assign  wn_re[ 4] = 16'h7FF6;   assign  wn_im[ 4] = 16'hFCDC;   //  4  1.000 -0.025
+assign  wn_re[ 5] = 16'h7FF1;   assign  wn_im[ 5] = 16'hFC13;   //  5  1.000 -0.031
+assign  wn_re[ 6] = 16'h7FEA;   assign  wn_im[ 6] = 16'hFB4A;   //  6  0.999 -0.037
+assign  wn_re[ 7] = 16'h7FE2;   assign  wn_im[ 7] = 16'hFA81;   //  7  0.999 -0.043
+assign  wn_re[ 8] = 16'h7FD9;   assign  wn_im[ 8] = 16'hF9B8;   //  8  0.999 -0.049
+assign  wn_re[ 9] = 16'h7FCE;   assign  wn_im[ 9] = 16'hF8EF;   //  9  0.998 -0.055
+assign  wn_re[10] = 16'h7FC2;   assign  wn_im[10] = 16'hF827;   // 10  0.998 -0.061
+assign  wn_re[11] = 16'h7FB5;   assign  wn_im[11] = 16'hF75E;   // 11  0.998 -0.067
+assign  wn_re[12] = 16'h7FA7;   assign  wn_im[12] = 16'hF695;   // 12  0.997 -0.074
+assign  wn_re[13] = 16'h7F98;   assign  wn_im[13] = 16'hF5CD;   // 13  0.997 -0.080
+assign  wn_re[14] = 16'h7F87;   assign  wn_im[14] = 16'hF505;   // 14  0.996 -0.086
+assign  wn_re[15] = 16'h7F75;   assign  wn_im[15] = 16'hF43C;   // 15  0.996 -0.092
+assign  wn_re[16] = 16'h7F62;   assign  wn_im[16] = 16'hF374;   // 16  0.995 -0.098
+assign  wn_re[17] = 16'h7F4E;   assign  wn_im[17] = 16'hF2AC;   // 17  0.995 -0.104
+assign  wn_re[18] = 16'h7F38;   assign  wn_im[18] = 16'hF1E4;   // 18  0.994 -0.110
+assign  wn_re[19] = 16'h7F22;   assign  wn_im[19] = 16'hF11C;   // 19  0.993 -0.116
+assign  wn_re[20] = 16'h7F0A;   assign  wn_im[20] = 16'hF055;   // 20  0.992 -0.122
+assign  wn_re[21] = 16'h7EF0;   assign  wn_im[21] = 16'hEF8D;   // 21  0.992 -0.128
+assign  wn_re[22] = 16'h7ED6;   assign  wn_im[22] = 16'hEEC6;   // 22  0.991 -0.135
+assign  wn_re[23] = 16'h7EBA;   assign  wn_im[23] = 16'hEDFF;   // 23  0.990 -0.141
+assign  wn_re[24] = 16'h7E9D;   assign  wn_im[24] = 16'hED38;   // 24  0.989 -0.147
+assign  wn_re[25] = 16'h7E7F;   assign  wn_im[25] = 16'hEC71;   // 25  0.988 -0.153
+assign  wn_re[26] = 16'h7E60;   assign  wn_im[26] = 16'hEBAB;   // 26  0.987 -0.159
+assign  wn_re[27] = 16'h7E3F;   assign  wn_im[27] = 16'hEAE4;   // 27  0.986 -0.165
+assign  wn_re[28] = 16'h7E1E;   assign  wn_im[28] = 16'hEA1E;   // 28  0.985 -0.171
+assign  wn_re[29] = 16'h7DFB;   assign  wn_im[29] = 16'hE958;   // 29  0.984 -0.177
+assign  wn_re[30] = 16'h7DD6;   assign  wn_im[30] = 16'hE892;   // 30  0.983 -0.183
+assign  wn_re[31] = 16'h7DB1;   assign  wn_im[31] = 16'hE7CD;   // 31  0.982 -0.189
+assign  wn_re[32] = 16'h7D8A;   assign  wn_im[32] = 16'hE707;   // 32  0.981 -0.195
+assign  wn_re[33] = 16'h7D63;   assign  wn_im[33] = 16'hE642;   // 33  0.980 -0.201
+assign  wn_re[34] = 16'h7D3A;   assign  wn_im[34] = 16'hE57D;   // 34  0.978 -0.207
+assign  wn_re[35] = 16'h7D0F;   assign  wn_im[35] = 16'hE4B9;   // 35  0.977 -0.213
+assign  wn_re[36] = 16'h7CE4;   assign  wn_im[36] = 16'hE3F4;   // 36  0.976 -0.219
+assign  wn_re[37] = 16'h7CB7;   assign  wn_im[37] = 16'hE330;   // 37  0.974 -0.225
+assign  wn_re[38] = 16'h7C89;   assign  wn_im[38] = 16'hE26D;   // 38  0.973 -0.231
+assign  wn_re[39] = 16'h7C5A;   assign  wn_im[39] = 16'hE1A9;   // 39  0.972 -0.237
+assign  wn_re[40] = 16'h7C2A;   assign  wn_im[40] = 16'hE0E6;   // 40  0.970 -0.243
+assign  wn_re[41] = 16'h7BF9;   assign  wn_im[41] = 16'hE023;   // 41  0.969 -0.249
+assign  wn_re[42] = 16'h7BC6;   assign  wn_im[42] = 16'hDF61;   // 42  0.967 -0.255
+assign  wn_re[43] = 16'h7B92;   assign  wn_im[43] = 16'hDE9E;   // 43  0.965 -0.261
+assign  wn_re[44] = 16'h7B5D;   assign  wn_im[44] = 16'hDDDC;   // 44  0.964 -0.267
+assign  wn_re[45] = 16'h7B27;   assign  wn_im[45] = 16'hDD1B;   // 45  0.962 -0.273
+assign  wn_re[46] = 16'h7AEF;   assign  wn_im[46] = 16'hDC59;   // 46  0.960 -0.279
+assign  wn_re[47] = 16'h7AB7;   assign  wn_im[47] = 16'hDB99;   // 47  0.959 -0.284
+assign  wn_re[48] = 16'h7A7D;   assign  wn_im[48] = 16'hDAD8;   // 48  0.957 -0.290
+assign  wn_re[49] = 16'h7A42;   assign  wn_im[49] = 16'hDA18;   // 49  0.955 -0.296
+assign  wn_re[50] = 16'h7A06;   assign  wn_im[50] = 16'hD958;   // 50  0.953 -0.302
+assign  wn_re[51] = 16'h79C9;   assign  wn_im[51] = 16'hD898;   // 51  0.951 -0.308
+assign  wn_re[52] = 16'h798A;   assign  wn_im[52] = 16'hD7D9;   // 52  0.950 -0.314
+assign  wn_re[53] = 16'h794A;   assign  wn_im[53] = 16'hD71B;   // 53  0.948 -0.320
+assign  wn_re[54] = 16'h790A;   assign  wn_im[54] = 16'hD65C;   // 54  0.946 -0.325
+assign  wn_re[55] = 16'h78C8;   assign  wn_im[55] = 16'hD59E;   // 55  0.944 -0.331
+assign  wn_re[56] = 16'h7885;   assign  wn_im[56] = 16'hD4E1;   // 56  0.942 -0.337
+assign  wn_re[57] = 16'h7840;   assign  wn_im[57] = 16'hD424;   // 57  0.939 -0.343
+assign  wn_re[58] = 16'h77FB;   assign  wn_im[58] = 16'hD367;   // 58  0.937 -0.348
+assign  wn_re[59] = 16'h77B4;   assign  wn_im[59] = 16'hD2AB;   // 59  0.935 -0.354
+assign  wn_re[60] = 16'h776C;   assign  wn_im[60] = 16'hD1EF;   // 60  0.933 -0.360
+assign  wn_re[61] = 16'h7723;   assign  wn_im[61] = 16'hD134;   // 61  0.931 -0.366
+assign  wn_re[62] = 16'h76D9;   assign  wn_im[62] = 16'hD079;   // 62  0.929 -0.371
+assign  wn_re[63] = 16'h768E;   assign  wn_im[63] = 16'hCFBE;   // 63  0.926 -0.377
+assign  wn_re[64] = 16'h7642;   assign  wn_im[64] = 16'hCF04;   // 64  0.924 -0.383
+assign  wn_re[65] = 16'h75F4;   assign  wn_im[65] = 16'hCE4B;   // 65  0.922 -0.388
+assign  wn_re[66] = 16'h75A6;   assign  wn_im[66] = 16'hCD92;   // 66  0.919 -0.394
+assign  wn_re[67] = 16'h7556;   assign  wn_im[67] = 16'hCCD9;   // 67  0.917 -0.400
+assign  wn_re[68] = 16'h7505;   assign  wn_im[68] = 16'hCC21;   // 68  0.914 -0.405
+assign  wn_re[69] = 16'h74B3;   assign  wn_im[69] = 16'hCB69;   // 69  0.912 -0.411
+assign  wn_re[70] = 16'h7460;   assign  wn_im[70] = 16'hCAB2;   // 70  0.909 -0.416
+assign  wn_re[71] = 16'h740B;   assign  wn_im[71] = 16'hC9FC;   // 71  0.907 -0.422
+assign  wn_re[72] = 16'h73B6;   assign  wn_im[72] = 16'hC946;   // 72  0.904 -0.428
+assign  wn_re[73] = 16'h735F;   assign  wn_im[73] = 16'hC890;   // 73  0.901 -0.433
+assign  wn_re[74] = 16'h7308;   assign  wn_im[74] = 16'hC7DB;   // 74  0.899 -0.439
+assign  wn_re[75] = 16'h72AF;   assign  wn_im[75] = 16'hC727;   // 75  0.896 -0.444
+assign  wn_re[76] = 16'h7255;   assign  wn_im[76] = 16'hC673;   // 76  0.893 -0.450
+assign  wn_re[77] = 16'h71FA;   assign  wn_im[77] = 16'hC5C0;   // 77  0.890 -0.455
+assign  wn_re[78] = 16'h719E;   assign  wn_im[78] = 16'hC50D;   // 78  0.888 -0.461
+assign  wn_re[79] = 16'h7141;   assign  wn_im[79] = 16'hC45B;   // 79  0.885 -0.466
+assign  wn_re[80] = 16'h70E3;   assign  wn_im[80] = 16'hC3A9;   // 80  0.882 -0.471
+assign  wn_re[81] = 16'h7083;   assign  wn_im[81] = 16'hC2F8;   // 81  0.879 -0.477
+assign  wn_re[82] = 16'h7023;   assign  wn_im[82] = 16'hC248;   // 82  0.876 -0.482
+assign  wn_re[83] = 16'h6FC2;   assign  wn_im[83] = 16'hC198;   // 83  0.873 -0.488
+assign  wn_re[84] = 16'h6F5F;   assign  wn_im[84] = 16'hC0E9;   // 84  0.870 -0.493
+assign  wn_re[85] = 16'h6EFB;   assign  wn_im[85] = 16'hC03A;   // 85  0.867 -0.498
+assign  wn_re[86] = 16'h6E97;   assign  wn_im[86] = 16'hBF8C;   // 86  0.864 -0.504
+assign  wn_re[87] = 16'h6E31;   assign  wn_im[87] = 16'hBEDF;   // 87  0.861 -0.509
+assign  wn_re[88] = 16'h6DCA;   assign  wn_im[88] = 16'hBE32;   // 88  0.858 -0.514
+assign  wn_re[89] = 16'h6D62;   assign  wn_im[89] = 16'hBD86;   // 89  0.855 -0.519
+assign  wn_re[90] = 16'h6CF9;   assign  wn_im[90] = 16'hBCDA;   // 90  0.851 -0.525
+assign  wn_re[91] = 16'h6C8F;   assign  wn_im[91] = 16'hBC2F;   // 91  0.848 -0.530
+assign  wn_re[92] = 16'h6C24;   assign  wn_im[92] = 16'hBB85;   // 92  0.845 -0.535
+assign  wn_re[93] = 16'h6BB8;   assign  wn_im[93] = 16'hBADC;   // 93  0.842 -0.540
+assign  wn_re[94] = 16'h6B4B;   assign  wn_im[94] = 16'hBA33;   // 94  0.838 -0.545
+assign  wn_re[95] = 16'h6ADD;   assign  wn_im[95] = 16'hB98B;   // 95  0.835 -0.550
+assign  wn_re[96] = 16'h6A6E;   assign  wn_im[96] = 16'hB8E3;   // 96  0.831 -0.556
+assign  wn_re[97] = 16'h69FD;   assign  wn_im[97] = 16'hB83C;   // 97  0.828 -0.561
+assign  wn_re[98] = 16'h698C;   assign  wn_im[98] = 16'hB796;   // 98  0.825 -0.566
+assign  wn_re[99] = 16'h691A;   assign  wn_im[99] = 16'hB6F1;   // 99  0.821 -0.571
+assign  wn_re[100] = 16'h68A7;   assign  wn_im[100] = 16'hB64C;   // 100  0.818 -0.576
+assign  wn_re[101] = 16'h6832;   assign  wn_im[101] = 16'hB5A8;   // 101  0.814 -0.581
+assign  wn_re[102] = 16'h67BD;   assign  wn_im[102] = 16'hB505;   // 102  0.810 -0.586
+assign  wn_re[103] = 16'h6747;   assign  wn_im[103] = 16'hB462;   // 103  0.807 -0.591
+assign  wn_re[104] = 16'h66D0;   assign  wn_im[104] = 16'hB3C0;   // 104  0.803 -0.596
+assign  wn_re[105] = 16'h6657;   assign  wn_im[105] = 16'hB31F;   // 105  0.800 -0.601
+assign  wn_re[106] = 16'h65DE;   assign  wn_im[106] = 16'hB27F;   // 106  0.796 -0.606
+assign  wn_re[107] = 16'h6564;   assign  wn_im[107] = 16'hB1DF;   // 107  0.792 -0.610
+assign  wn_re[108] = 16'h64E9;   assign  wn_im[108] = 16'hB140;   // 108  0.788 -0.615
+assign  wn_re[109] = 16'h646C;   assign  wn_im[109] = 16'hB0A2;   // 109  0.785 -0.620
+assign  wn_re[110] = 16'h63EF;   assign  wn_im[110] = 16'hB005;   // 110  0.781 -0.625
+assign  wn_re[111] = 16'h6371;   assign  wn_im[111] = 16'hAF68;   // 111  0.777 -0.630
+assign  wn_re[112] = 16'h62F2;   assign  wn_im[112] = 16'hAECC;   // 112  0.773 -0.634
+assign  wn_re[113] = 16'h6272;   assign  wn_im[113] = 16'hAE31;   // 113  0.769 -0.639
+assign  wn_re[114] = 16'h61F1;   assign  wn_im[114] = 16'hAD97;   // 114  0.765 -0.644
+assign  wn_re[115] = 16'h616F;   assign  wn_im[115] = 16'hACFD;   // 115  0.761 -0.649
+assign  wn_re[116] = 16'h60EC;   assign  wn_im[116] = 16'hAC65;   // 116  0.757 -0.653
+assign  wn_re[117] = 16'h6068;   assign  wn_im[117] = 16'hABCD;   // 117  0.753 -0.658
+assign  wn_re[118] = 16'h5FE4;   assign  wn_im[118] = 16'hAB36;   // 118  0.749 -0.662
+assign  wn_re[119] = 16'h5F5E;   assign  wn_im[119] = 16'hAAA0;   // 119  0.745 -0.667
+assign  wn_re[120] = 16'h5ED7;   assign  wn_im[120] = 16'hAA0A;   // 120  0.741 -0.672
+assign  wn_re[121] = 16'h5E50;   assign  wn_im[121] = 16'hA976;   // 121  0.737 -0.676
+assign  wn_re[122] = 16'h5DC8;   assign  wn_im[122] = 16'hA8E2;   // 122  0.733 -0.681
+assign  wn_re[123] = 16'h5D3E;   assign  wn_im[123] = 16'hA84F;   // 123  0.728 -0.685
+assign  wn_re[124] = 16'h5CB4;   assign  wn_im[124] = 16'hA7BD;   // 124  0.724 -0.690
+assign  wn_re[125] = 16'h5C29;   assign  wn_im[125] = 16'hA72C;   // 125  0.720 -0.694
+assign  wn_re[126] = 16'h5B9D;   assign  wn_im[126] = 16'hA69C;   // 126  0.716 -0.698
+assign  wn_re[127] = 16'h5B10;   assign  wn_im[127] = 16'hA60C;   // 127  0.711 -0.703
+assign  wn_re[128] = 16'h5A82;   assign  wn_im[128] = 16'hA57E;   // 128  0.707 -0.707
+assign  wn_re[129] = 16'h59F4;   assign  wn_im[129] = 16'hA4F0;   // 129  0.703 -0.711
+assign  wn_re[130] = 16'h5964;   assign  wn_im[130] = 16'hA463;   // 130  0.698 -0.716
+assign  wn_re[131] = 16'h58D4;   assign  wn_im[131] = 16'hA3D7;   // 131  0.694 -0.720
+assign  wn_re[132] = 16'h5843;   assign  wn_im[132] = 16'hA34C;   // 132  0.690 -0.724
+assign  wn_re[133] = 16'h57B1;   assign  wn_im[133] = 16'hA2C2;   // 133  0.685 -0.728
+assign  wn_re[134] = 16'h571E;   assign  wn_im[134] = 16'hA238;   // 134  0.681 -0.733
+assign  wn_re[135] = 16'h568A;   assign  wn_im[135] = 16'hA1B0;   // 135  0.676 -0.737
+assign  wn_re[136] = 16'h55F6;   assign  wn_im[136] = 16'hA129;   // 136  0.672 -0.741
+assign  wn_re[137] = 16'h5560;   assign  wn_im[137] = 16'hA0A2;   // 137  0.667 -0.745
+assign  wn_re[138] = 16'h54CA;   assign  wn_im[138] = 16'hA01C;   // 138  0.662 -0.749
+assign  wn_re[139] = 16'h5433;   assign  wn_im[139] = 16'h9F98;   // 139  0.658 -0.753
+assign  wn_re[140] = 16'h539B;   assign  wn_im[140] = 16'h9F14;   // 140  0.653 -0.757
+assign  wn_re[141] = 16'h5303;   assign  wn_im[141] = 16'h9E91;   // 141  0.649 -0.761
+assign  wn_re[142] = 16'h5269;   assign  wn_im[142] = 16'h9E0F;   // 142  0.644 -0.765
+assign  wn_re[143] = 16'h51CF;   assign  wn_im[143] = 16'h9D8E;   // 143  0.639 -0.769
+assign  wn_re[144] = 16'h5134;   assign  wn_im[144] = 16'h9D0E;   // 144  0.634 -0.773
+assign  wn_re[145] = 16'h5098;   assign  wn_im[145] = 16'h9C8F;   // 145  0.630 -0.777
+assign  wn_re[146] = 16'h4FFB;   assign  wn_im[146] = 16'h9C11;   // 146  0.625 -0.781
+assign  wn_re[147] = 16'h4F5E;   assign  wn_im[147] = 16'h9B94;   // 147  0.620 -0.785
+assign  wn_re[148] = 16'h4EC0;   assign  wn_im[148] = 16'h9B17;   // 148  0.615 -0.788
+assign  wn_re[149] = 16'h4E21;   assign  wn_im[149] = 16'h9A9C;   // 149  0.610 -0.792
+assign  wn_re[150] = 16'h4D81;   assign  wn_im[150] = 16'h9A22;   // 150  0.606 -0.796
+assign  wn_re[151] = 16'h4CE1;   assign  wn_im[151] = 16'h99A9;   // 151  0.601 -0.800
+assign  wn_re[152] = 16'h4C40;   assign  wn_im[152] = 16'h9930;   // 152  0.596 -0.803
+assign  wn_re[153] = 16'h4B9E;   assign  wn_im[153] = 16'h98B9;   // 153  0.591 -0.807
+assign  wn_re[154] = 16'h4AFB;   assign  wn_im[154] = 16'h9843;   // 154  0.586 -0.810
+assign  wn_re[155] = 16'h4A58;   assign  wn_im[155] = 16'h97CE;   // 155  0.581 -0.814
+assign  wn_re[156] = 16'h49B4;   assign  wn_im[156] = 16'h9759;   // 156  0.576 -0.818
+assign  wn_re[157] = 16'h490F;   assign  wn_im[157] = 16'h96E6;   // 157  0.571 -0.821
+assign  wn_re[158] = 16'h486A;   assign  wn_im[158] = 16'h9674;   // 158  0.566 -0.825
+assign  wn_re[159] = 16'h47C4;   assign  wn_im[159] = 16'h9603;   // 159  0.561 -0.828
+assign  wn_re[160] = 16'h471D;   assign  wn_im[160] = 16'h9592;   // 160  0.556 -0.831
+assign  wn_re[161] = 16'h4675;   assign  wn_im[161] = 16'h9523;   // 161  0.550 -0.835
+assign  wn_re[162] = 16'h45CD;   assign  wn_im[162] = 16'h94B5;   // 162  0.545 -0.838
+assign  wn_re[163] = 16'h4524;   assign  wn_im[163] = 16'h9448;   // 163  0.540 -0.842
+assign  wn_re[164] = 16'h447B;   assign  wn_im[164] = 16'h93DC;   // 164  0.535 -0.845
+assign  wn_re[165] = 16'h43D1;   assign  wn_im[165] = 16'h9371;   // 165  0.530 -0.848
+assign  wn_re[166] = 16'h4326;   assign  wn_im[166] = 16'h9307;   // 166  0.525 -0.851
+assign  wn_re[167] = 16'h427A;   assign  wn_im[167] = 16'h929E;   // 167  0.519 -0.855
+assign  wn_re[168] = 16'h41CE;   assign  wn_im[168] = 16'h9236;   // 168  0.514 -0.858
+assign  wn_re[169] = 16'h4121;   assign  wn_im[169] = 16'h91CF;   // 169  0.509 -0.861
+assign  wn_re[170] = 16'h4074;   assign  wn_im[170] = 16'h9169;   // 170  0.504 -0.864
+assign  wn_re[171] = 16'h3FC6;   assign  wn_im[171] = 16'h9105;   // 171  0.498 -0.867
+assign  wn_re[172] = 16'h3F17;   assign  wn_im[172] = 16'h90A1;   // 172  0.493 -0.870
+assign  wn_re[173] = 16'h3E68;   assign  wn_im[173] = 16'h903E;   // 173  0.488 -0.873
+assign  wn_re[174] = 16'h3DB8;   assign  wn_im[174] = 16'h8FDD;   // 174  0.482 -0.876
+assign  wn_re[175] = 16'h3D08;   assign  wn_im[175] = 16'h8F7D;   // 175  0.477 -0.879
+assign  wn_re[176] = 16'h3C57;   assign  wn_im[176] = 16'h8F1D;   // 176  0.471 -0.882
+assign  wn_re[177] = 16'h3BA5;   assign  wn_im[177] = 16'h8EBF;   // 177  0.466 -0.885
+assign  wn_re[178] = 16'h3AF3;   assign  wn_im[178] = 16'h8E62;   // 178  0.461 -0.888
+assign  wn_re[179] = 16'h3A40;   assign  wn_im[179] = 16'h8E06;   // 179  0.455 -0.890
+assign  wn_re[180] = 16'h398D;   assign  wn_im[180] = 16'h8DAB;   // 180  0.450 -0.893
+assign  wn_re[181] = 16'h38D9;   assign  wn_im[181] = 16'h8D51;   // 181  0.444 -0.896
+assign  wn_re[182] = 16'h3825;   assign  wn_im[182] = 16'h8CF8;   // 182  0.439 -0.899
+assign  wn_re[183] = 16'h3770;   assign  wn_im[183] = 16'h8CA1;   // 183  0.433 -0.901
+assign  wn_re[184] = 16'h36BA;   assign  wn_im[184] = 16'h8C4A;   // 184  0.428 -0.904
+assign  wn_re[185] = 16'h3604;   assign  wn_im[185] = 16'h8BF5;   // 185  0.422 -0.907
+assign  wn_re[186] = 16'h354E;   assign  wn_im[186] = 16'h8BA0;   // 186  0.416 -0.909
+assign  wn_re[187] = 16'h3497;   assign  wn_im[187] = 16'h8B4D;   // 187  0.411 -0.912
+assign  wn_re[188] = 16'h33DF;   assign  wn_im[188] = 16'h8AFB;   // 188  0.405 -0.914
+assign  wn_re[189] = 16'h3327;   assign  wn_im[189] = 16'h8AAA;   // 189  0.400 -0.917
+assign  wn_re[190] = 16'h326E;   assign  wn_im[190] = 16'h8A5A;   // 190  0.394 -0.919
+assign  wn_re[191] = 16'h31B5;   assign  wn_im[191] = 16'h8A0C;   // 191  0.388 -0.922
+assign  wn_re[192] = 16'h30FC;   assign  wn_im[192] = 16'h89BE;   // 192  0.383 -0.924
+assign  wn_re[193] = 16'h3042;   assign  wn_im[193] = 16'h8972;   // 193  0.377 -0.926
+assign  wn_re[194] = 16'h2F87;   assign  wn_im[194] = 16'h8927;   // 194  0.371 -0.929
+assign  wn_re[195] = 16'h2ECC;   assign  wn_im[195] = 16'h88DD;   // 195  0.366 -0.931
+assign  wn_re[196] = 16'h2E11;   assign  wn_im[196] = 16'h8894;   // 196  0.360 -0.933
+assign  wn_re[197] = 16'h2D55;   assign  wn_im[197] = 16'h884C;   // 197  0.354 -0.935
+assign  wn_re[198] = 16'h2C99;   assign  wn_im[198] = 16'h8805;   // 198  0.348 -0.937
+assign  wn_re[199] = 16'h2BDC;   assign  wn_im[199] = 16'h87C0;   // 199  0.343 -0.939
+assign  wn_re[200] = 16'h2B1F;   assign  wn_im[200] = 16'h877B;   // 200  0.337 -0.942
+assign  wn_re[201] = 16'h2A62;   assign  wn_im[201] = 16'h8738;   // 201  0.331 -0.944
+assign  wn_re[202] = 16'h29A4;   assign  wn_im[202] = 16'h86F6;   // 202  0.325 -0.946
+assign  wn_re[203] = 16'h28E5;   assign  wn_im[203] = 16'h86B6;   // 203  0.320 -0.948
+assign  wn_re[204] = 16'h2827;   assign  wn_im[204] = 16'h8676;   // 204  0.314 -0.950
+assign  wn_re[205] = 16'h2768;   assign  wn_im[205] = 16'h8637;   // 205  0.308 -0.951
+assign  wn_re[206] = 16'h26A8;   assign  wn_im[206] = 16'h85FA;   // 206  0.302 -0.953
+assign  wn_re[207] = 16'h25E8;   assign  wn_im[207] = 16'h85BE;   // 207  0.296 -0.955
+assign  wn_re[208] = 16'h2528;   assign  wn_im[208] = 16'h8583;   // 208  0.290 -0.957
+assign  wn_re[209] = 16'h2467;   assign  wn_im[209] = 16'h8549;   // 209  0.284 -0.959
+assign  wn_re[210] = 16'h23A7;   assign  wn_im[210] = 16'h8511;   // 210  0.279 -0.960
+assign  wn_re[211] = 16'h22E5;   assign  wn_im[211] = 16'h84D9;   // 211  0.273 -0.962
+assign  wn_re[212] = 16'h2224;   assign  wn_im[212] = 16'h84A3;   // 212  0.267 -0.964
+assign  wn_re[213] = 16'h2162;   assign  wn_im[213] = 16'h846E;   // 213  0.261 -0.965
+assign  wn_re[214] = 16'h209F;   assign  wn_im[214] = 16'h843A;   // 214  0.255 -0.967
+assign  wn_re[215] = 16'h1FDD;   assign  wn_im[215] = 16'h8407;   // 215  0.249 -0.969
+assign  wn_re[216] = 16'h1F1A;   assign  wn_im[216] = 16'h83D6;   // 216  0.243 -0.970
+assign  wn_re[217] = 16'h1E57;   assign  wn_im[217] = 16'h83A6;   // 217  0.237 -0.972
+assign  wn_re[218] = 16'h1D93;   assign  wn_im[218] = 16'h8377;   // 218  0.231 -0.973
+assign  wn_re[219] = 16'h1CD0;   assign  wn_im[219] = 16'h8349;   // 219  0.225 -0.974
+assign  wn_re[220] = 16'h1C0C;   assign  wn_im[220] = 16'h831C;   // 220  0.219 -0.976
+assign  wn_re[221] = 16'h1B47;   assign  wn_im[221] = 16'h82F1;   // 221  0.213 -0.977
+assign  wn_re[222] = 16'h1A83;   assign  wn_im[222] = 16'h82C6;   // 222  0.207 -0.978
+assign  wn_re[223] = 16'h19BE;   assign  wn_im[223] = 16'h829D;   // 223  0.201 -0.980
+assign  wn_re[224] = 16'h18F9;   assign  wn_im[224] = 16'h8276;   // 224  0.195 -0.981
+assign  wn_re[225] = 16'h1833;   assign  wn_im[225] = 16'h824F;   // 225  0.189 -0.982
+assign  wn_re[226] = 16'h176E;   assign  wn_im[226] = 16'h822A;   // 226  0.183 -0.983
+assign  wn_re[227] = 16'h16A8;   assign  wn_im[227] = 16'h8205;   // 227  0.177 -0.984
+assign  wn_re[228] = 16'h15E2;   assign  wn_im[228] = 16'h81E2;   // 228  0.171 -0.985
+assign  wn_re[229] = 16'h151C;   assign  wn_im[229] = 16'h81C1;   // 229  0.165 -0.986
+assign  wn_re[230] = 16'h1455;   assign  wn_im[230] = 16'h81A0;   // 230  0.159 -0.987
+assign  wn_re[231] = 16'h138F;   assign  wn_im[231] = 16'h8181;   // 231  0.153 -0.988
+assign  wn_re[232] = 16'h12C8;   assign  wn_im[232] = 16'h8163;   // 232  0.147 -0.989
+assign  wn_re[233] = 16'h1201;   assign  wn_im[233] = 16'h8146;   // 233  0.141 -0.990
+assign  wn_re[234] = 16'h113A;   assign  wn_im[234] = 16'h812A;   // 234  0.135 -0.991
+assign  wn_re[235] = 16'h1073;   assign  wn_im[235] = 16'h8110;   // 235  0.128 -0.992
+assign  wn_re[236] = 16'h0FAB;   assign  wn_im[236] = 16'h80F6;   // 236  0.122 -0.992
+assign  wn_re[237] = 16'h0EE4;   assign  wn_im[237] = 16'h80DE;   // 237  0.116 -0.993
+assign  wn_re[238] = 16'h0E1C;   assign  wn_im[238] = 16'h80C8;   // 238  0.110 -0.994
+assign  wn_re[239] = 16'h0D54;   assign  wn_im[239] = 16'h80B2;   // 239  0.104 -0.995
+assign  wn_re[240] = 16'h0C8C;   assign  wn_im[240] = 16'h809E;   // 240  0.098 -0.995
+assign  wn_re[241] = 16'h0BC4;   assign  wn_im[241] = 16'h808B;   // 241  0.092 -0.996
+assign  wn_re[242] = 16'h0AFB;   assign  wn_im[242] = 16'h8079;   // 242  0.086 -0.996
+assign  wn_re[243] = 16'h0A33;   assign  wn_im[243] = 16'h8068;   // 243  0.080 -0.997
+assign  wn_re[244] = 16'h096B;   assign  wn_im[244] = 16'h8059;   // 244  0.074 -0.997
+assign  wn_re[245] = 16'h08A2;   assign  wn_im[245] = 16'h804B;   // 245  0.067 -0.998
+assign  wn_re[246] = 16'h07D9;   assign  wn_im[246] = 16'h803E;   // 246  0.061 -0.998
+assign  wn_re[247] = 16'h0711;   assign  wn_im[247] = 16'h8032;   // 247  0.055 -0.998
+assign  wn_re[248] = 16'h0648;   assign  wn_im[248] = 16'h8027;   // 248  0.049 -0.999
+assign  wn_re[249] = 16'h057F;   assign  wn_im[249] = 16'h801E;   // 249  0.043 -0.999
+assign  wn_re[250] = 16'h04B6;   assign  wn_im[250] = 16'h8016;   // 250  0.037 -0.999
+assign  wn_re[251] = 16'h03ED;   assign  wn_im[251] = 16'h800F;   // 251  0.031 -1.000
+assign  wn_re[252] = 16'h0324;   assign  wn_im[252] = 16'h800A;   // 252  0.025 -1.000
+assign  wn_re[253] = 16'h025B;   assign  wn_im[253] = 16'h8006;   // 253  0.018 -1.000
+assign  wn_re[254] = 16'h0192;   assign  wn_im[254] = 16'h8002;   // 254  0.012 -1.000
+assign  wn_re[255] = 16'h00C9;   assign  wn_im[255] = 16'h8001;   // 255  0.006 -1.000
+assign  wn_re[256] = 16'h0000;   assign  wn_im[256] = 16'h8000;   // 256  0.000 -1.000
+assign  wn_re[257] = 16'hxxxx;   assign  wn_im[257] = 16'hxxxx;   // 257 -0.006 -1.000
+assign  wn_re[258] = 16'hFE6E;   assign  wn_im[258] = 16'h8002;   // 258 -0.012 -1.000
+assign  wn_re[259] = 16'hxxxx;   assign  wn_im[259] = 16'hxxxx;   // 259 -0.018 -1.000
+assign  wn_re[260] = 16'hFCDC;   assign  wn_im[260] = 16'h800A;   // 260 -0.025 -1.000
+assign  wn_re[261] = 16'hFC13;   assign  wn_im[261] = 16'h800F;   // 261 -0.031 -1.000
+assign  wn_re[262] = 16'hFB4A;   assign  wn_im[262] = 16'h8016;   // 262 -0.037 -0.999
+assign  wn_re[263] = 16'hxxxx;   assign  wn_im[263] = 16'hxxxx;   // 263 -0.043 -0.999
+assign  wn_re[264] = 16'hF9B8;   assign  wn_im[264] = 16'h8027;   // 264 -0.049 -0.999
+assign  wn_re[265] = 16'hxxxx;   assign  wn_im[265] = 16'hxxxx;   // 265 -0.055 -0.998
+assign  wn_re[266] = 16'hF827;   assign  wn_im[266] = 16'h803E;   // 266 -0.061 -0.998
+assign  wn_re[267] = 16'hF75E;   assign  wn_im[267] = 16'h804B;   // 267 -0.067 -0.998
+assign  wn_re[268] = 16'hF695;   assign  wn_im[268] = 16'h8059;   // 268 -0.074 -0.997
+assign  wn_re[269] = 16'hxxxx;   assign  wn_im[269] = 16'hxxxx;   // 269 -0.080 -0.997
+assign  wn_re[270] = 16'hF505;   assign  wn_im[270] = 16'h8079;   // 270 -0.086 -0.996
+assign  wn_re[271] = 16'hxxxx;   assign  wn_im[271] = 16'hxxxx;   // 271 -0.092 -0.996
+assign  wn_re[272] = 16'hF374;   assign  wn_im[272] = 16'h809E;   // 272 -0.098 -0.995
+assign  wn_re[273] = 16'hF2AC;   assign  wn_im[273] = 16'h80B2;   // 273 -0.104 -0.995
+assign  wn_re[274] = 16'hF1E4;   assign  wn_im[274] = 16'h80C8;   // 274 -0.110 -0.994
+assign  wn_re[275] = 16'hxxxx;   assign  wn_im[275] = 16'hxxxx;   // 275 -0.116 -0.993
+assign  wn_re[276] = 16'hF055;   assign  wn_im[276] = 16'h80F6;   // 276 -0.122 -0.992
+assign  wn_re[277] = 16'hxxxx;   assign  wn_im[277] = 16'hxxxx;   // 277 -0.128 -0.992
+assign  wn_re[278] = 16'hEEC6;   assign  wn_im[278] = 16'h812A;   // 278 -0.135 -0.991
+assign  wn_re[279] = 16'hEDFF;   assign  wn_im[279] = 16'h8146;   // 279 -0.141 -0.990
+assign  wn_re[280] = 16'hED38;   assign  wn_im[280] = 16'h8163;   // 280 -0.147 -0.989
+assign  wn_re[281] = 16'hxxxx;   assign  wn_im[281] = 16'hxxxx;   // 281 -0.153 -0.988
+assign  wn_re[282] = 16'hEBAB;   assign  wn_im[282] = 16'h81A0;   // 282 -0.159 -0.987
+assign  wn_re[283] = 16'hxxxx;   assign  wn_im[283] = 16'hxxxx;   // 283 -0.165 -0.986
+assign  wn_re[284] = 16'hEA1E;   assign  wn_im[284] = 16'h81E2;   // 284 -0.171 -0.985
+assign  wn_re[285] = 16'hE958;   assign  wn_im[285] = 16'h8205;   // 285 -0.177 -0.984
+assign  wn_re[286] = 16'hE892;   assign  wn_im[286] = 16'h822A;   // 286 -0.183 -0.983
+assign  wn_re[287] = 16'hxxxx;   assign  wn_im[287] = 16'hxxxx;   // 287 -0.189 -0.982
+assign  wn_re[288] = 16'hE707;   assign  wn_im[288] = 16'h8276;   // 288 -0.195 -0.981
+assign  wn_re[289] = 16'hxxxx;   assign  wn_im[289] = 16'hxxxx;   // 289 -0.201 -0.980
+assign  wn_re[290] = 16'hE57D;   assign  wn_im[290] = 16'h82C6;   // 290 -0.207 -0.978
+assign  wn_re[291] = 16'hE4B9;   assign  wn_im[291] = 16'h82F1;   // 291 -0.213 -0.977
+assign  wn_re[292] = 16'hE3F4;   assign  wn_im[292] = 16'h831C;   // 292 -0.219 -0.976
+assign  wn_re[293] = 16'hxxxx;   assign  wn_im[293] = 16'hxxxx;   // 293 -0.225 -0.974
+assign  wn_re[294] = 16'hE26D;   assign  wn_im[294] = 16'h8377;   // 294 -0.231 -0.973
+assign  wn_re[295] = 16'hxxxx;   assign  wn_im[295] = 16'hxxxx;   // 295 -0.237 -0.972
+assign  wn_re[296] = 16'hE0E6;   assign  wn_im[296] = 16'h83D6;   // 296 -0.243 -0.970
+assign  wn_re[297] = 16'hE023;   assign  wn_im[297] = 16'h8407;   // 297 -0.249 -0.969
+assign  wn_re[298] = 16'hDF61;   assign  wn_im[298] = 16'h843A;   // 298 -0.255 -0.967
+assign  wn_re[299] = 16'hxxxx;   assign  wn_im[299] = 16'hxxxx;   // 299 -0.261 -0.965
+assign  wn_re[300] = 16'hDDDC;   assign  wn_im[300] = 16'h84A3;   // 300 -0.267 -0.964
+assign  wn_re[301] = 16'hxxxx;   assign  wn_im[301] = 16'hxxxx;   // 301 -0.273 -0.962
+assign  wn_re[302] = 16'hDC59;   assign  wn_im[302] = 16'h8511;   // 302 -0.279 -0.960
+assign  wn_re[303] = 16'hDB99;   assign  wn_im[303] = 16'h8549;   // 303 -0.284 -0.959
+assign  wn_re[304] = 16'hDAD8;   assign  wn_im[304] = 16'h8583;   // 304 -0.290 -0.957
+assign  wn_re[305] = 16'hxxxx;   assign  wn_im[305] = 16'hxxxx;   // 305 -0.296 -0.955
+assign  wn_re[306] = 16'hD958;   assign  wn_im[306] = 16'h85FA;   // 306 -0.302 -0.953
+assign  wn_re[307] = 16'hxxxx;   assign  wn_im[307] = 16'hxxxx;   // 307 -0.308 -0.951
+assign  wn_re[308] = 16'hD7D9;   assign  wn_im[308] = 16'h8676;   // 308 -0.314 -0.950
+assign  wn_re[309] = 16'hD71B;   assign  wn_im[309] = 16'h86B6;   // 309 -0.320 -0.948
+assign  wn_re[310] = 16'hD65C;   assign  wn_im[310] = 16'h86F6;   // 310 -0.325 -0.946
+assign  wn_re[311] = 16'hxxxx;   assign  wn_im[311] = 16'hxxxx;   // 311 -0.331 -0.944
+assign  wn_re[312] = 16'hD4E1;   assign  wn_im[312] = 16'h877B;   // 312 -0.337 -0.942
+assign  wn_re[313] = 16'hxxxx;   assign  wn_im[313] = 16'hxxxx;   // 313 -0.343 -0.939
+assign  wn_re[314] = 16'hD367;   assign  wn_im[314] = 16'h8805;   // 314 -0.348 -0.937
+assign  wn_re[315] = 16'hD2AB;   assign  wn_im[315] = 16'h884C;   // 315 -0.354 -0.935
+assign  wn_re[316] = 16'hD1EF;   assign  wn_im[316] = 16'h8894;   // 316 -0.360 -0.933
+assign  wn_re[317] = 16'hxxxx;   assign  wn_im[317] = 16'hxxxx;   // 317 -0.366 -0.931
+assign  wn_re[318] = 16'hD079;   assign  wn_im[318] = 16'h8927;   // 318 -0.371 -0.929
+assign  wn_re[319] = 16'hxxxx;   assign  wn_im[319] = 16'hxxxx;   // 319 -0.377 -0.926
+assign  wn_re[320] = 16'hCF04;   assign  wn_im[320] = 16'h89BE;   // 320 -0.383 -0.924
+assign  wn_re[321] = 16'hCE4B;   assign  wn_im[321] = 16'h8A0C;   // 321 -0.388 -0.922
+assign  wn_re[322] = 16'hCD92;   assign  wn_im[322] = 16'h8A5A;   // 322 -0.394 -0.919
+assign  wn_re[323] = 16'hxxxx;   assign  wn_im[323] = 16'hxxxx;   // 323 -0.400 -0.917
+assign  wn_re[324] = 16'hCC21;   assign  wn_im[324] = 16'h8AFB;   // 324 -0.405 -0.914
+assign  wn_re[325] = 16'hxxxx;   assign  wn_im[325] = 16'hxxxx;   // 325 -0.411 -0.912
+assign  wn_re[326] = 16'hCAB2;   assign  wn_im[326] = 16'h8BA0;   // 326 -0.416 -0.909
+assign  wn_re[327] = 16'hC9FC;   assign  wn_im[327] = 16'h8BF5;   // 327 -0.422 -0.907
+assign  wn_re[328] = 16'hC946;   assign  wn_im[328] = 16'h8C4A;   // 328 -0.428 -0.904
+assign  wn_re[329] = 16'hxxxx;   assign  wn_im[329] = 16'hxxxx;   // 329 -0.433 -0.901
+assign  wn_re[330] = 16'hC7DB;   assign  wn_im[330] = 16'h8CF8;   // 330 -0.439 -0.899
+assign  wn_re[331] = 16'hxxxx;   assign  wn_im[331] = 16'hxxxx;   // 331 -0.444 -0.896
+assign  wn_re[332] = 16'hC673;   assign  wn_im[332] = 16'h8DAB;   // 332 -0.450 -0.893
+assign  wn_re[333] = 16'hC5C0;   assign  wn_im[333] = 16'h8E06;   // 333 -0.455 -0.890
+assign  wn_re[334] = 16'hC50D;   assign  wn_im[334] = 16'h8E62;   // 334 -0.461 -0.888
+assign  wn_re[335] = 16'hxxxx;   assign  wn_im[335] = 16'hxxxx;   // 335 -0.466 -0.885
+assign  wn_re[336] = 16'hC3A9;   assign  wn_im[336] = 16'h8F1D;   // 336 -0.471 -0.882
+assign  wn_re[337] = 16'hxxxx;   assign  wn_im[337] = 16'hxxxx;   // 337 -0.477 -0.879
+assign  wn_re[338] = 16'hC248;   assign  wn_im[338] = 16'h8FDD;   // 338 -0.482 -0.876
+assign  wn_re[339] = 16'hC198;   assign  wn_im[339] = 16'h903E;   // 339 -0.488 -0.873
+assign  wn_re[340] = 16'hC0E9;   assign  wn_im[340] = 16'h90A1;   // 340 -0.493 -0.870
+assign  wn_re[341] = 16'hxxxx;   assign  wn_im[341] = 16'hxxxx;   // 341 -0.498 -0.867
+assign  wn_re[342] = 16'hBF8C;   assign  wn_im[342] = 16'h9169;   // 342 -0.504 -0.864
+assign  wn_re[343] = 16'hxxxx;   assign  wn_im[343] = 16'hxxxx;   // 343 -0.509 -0.861
+assign  wn_re[344] = 16'hBE32;   assign  wn_im[344] = 16'h9236;   // 344 -0.514 -0.858
+assign  wn_re[345] = 16'hBD86;   assign  wn_im[345] = 16'h929E;   // 345 -0.519 -0.855
+assign  wn_re[346] = 16'hBCDA;   assign  wn_im[346] = 16'h9307;   // 346 -0.525 -0.851
+assign  wn_re[347] = 16'hxxxx;   assign  wn_im[347] = 16'hxxxx;   // 347 -0.530 -0.848
+assign  wn_re[348] = 16'hBB85;   assign  wn_im[348] = 16'h93DC;   // 348 -0.535 -0.845
+assign  wn_re[349] = 16'hxxxx;   assign  wn_im[349] = 16'hxxxx;   // 349 -0.540 -0.842
+assign  wn_re[350] = 16'hBA33;   assign  wn_im[350] = 16'h94B5;   // 350 -0.545 -0.838
+assign  wn_re[351] = 16'hB98B;   assign  wn_im[351] = 16'h9523;   // 351 -0.550 -0.835
+assign  wn_re[352] = 16'hB8E3;   assign  wn_im[352] = 16'h9592;   // 352 -0.556 -0.831
+assign  wn_re[353] = 16'hxxxx;   assign  wn_im[353] = 16'hxxxx;   // 353 -0.561 -0.828
+assign  wn_re[354] = 16'hB796;   assign  wn_im[354] = 16'h9674;   // 354 -0.566 -0.825
+assign  wn_re[355] = 16'hxxxx;   assign  wn_im[355] = 16'hxxxx;   // 355 -0.571 -0.821
+assign  wn_re[356] = 16'hB64C;   assign  wn_im[356] = 16'h9759;   // 356 -0.576 -0.818
+assign  wn_re[357] = 16'hB5A8;   assign  wn_im[357] = 16'h97CE;   // 357 -0.581 -0.814
+assign  wn_re[358] = 16'hB505;   assign  wn_im[358] = 16'h9843;   // 358 -0.586 -0.810
+assign  wn_re[359] = 16'hxxxx;   assign  wn_im[359] = 16'hxxxx;   // 359 -0.591 -0.807
+assign  wn_re[360] = 16'hB3C0;   assign  wn_im[360] = 16'h9930;   // 360 -0.596 -0.803
+assign  wn_re[361] = 16'hxxxx;   assign  wn_im[361] = 16'hxxxx;   // 361 -0.601 -0.800
+assign  wn_re[362] = 16'hB27F;   assign  wn_im[362] = 16'h9A22;   // 362 -0.606 -0.796
+assign  wn_re[363] = 16'hB1DF;   assign  wn_im[363] = 16'h9A9C;   // 363 -0.610 -0.792
+assign  wn_re[364] = 16'hB140;   assign  wn_im[364] = 16'h9B17;   // 364 -0.615 -0.788
+assign  wn_re[365] = 16'hxxxx;   assign  wn_im[365] = 16'hxxxx;   // 365 -0.620 -0.785
+assign  wn_re[366] = 16'hB005;   assign  wn_im[366] = 16'h9C11;   // 366 -0.625 -0.781
+assign  wn_re[367] = 16'hxxxx;   assign  wn_im[367] = 16'hxxxx;   // 367 -0.630 -0.777
+assign  wn_re[368] = 16'hAECC;   assign  wn_im[368] = 16'h9D0E;   // 368 -0.634 -0.773
+assign  wn_re[369] = 16'hAE31;   assign  wn_im[369] = 16'h9D8E;   // 369 -0.639 -0.769
+assign  wn_re[370] = 16'hAD97;   assign  wn_im[370] = 16'h9E0F;   // 370 -0.644 -0.765
+assign  wn_re[371] = 16'hxxxx;   assign  wn_im[371] = 16'hxxxx;   // 371 -0.649 -0.761
+assign  wn_re[372] = 16'hAC65;   assign  wn_im[372] = 16'h9F14;   // 372 -0.653 -0.757
+assign  wn_re[373] = 16'hxxxx;   assign  wn_im[373] = 16'hxxxx;   // 373 -0.658 -0.753
+assign  wn_re[374] = 16'hAB36;   assign  wn_im[374] = 16'hA01C;   // 374 -0.662 -0.749
+assign  wn_re[375] = 16'hAAA0;   assign  wn_im[375] = 16'hA0A2;   // 375 -0.667 -0.745
+assign  wn_re[376] = 16'hAA0A;   assign  wn_im[376] = 16'hA129;   // 376 -0.672 -0.741
+assign  wn_re[377] = 16'hxxxx;   assign  wn_im[377] = 16'hxxxx;   // 377 -0.676 -0.737
+assign  wn_re[378] = 16'hA8E2;   assign  wn_im[378] = 16'hA238;   // 378 -0.681 -0.733
+assign  wn_re[379] = 16'hxxxx;   assign  wn_im[379] = 16'hxxxx;   // 379 -0.685 -0.728
+assign  wn_re[380] = 16'hA7BD;   assign  wn_im[380] = 16'hA34C;   // 380 -0.690 -0.724
+assign  wn_re[381] = 16'hA72C;   assign  wn_im[381] = 16'hA3D7;   // 381 -0.694 -0.720
+assign  wn_re[382] = 16'hA69C;   assign  wn_im[382] = 16'hA463;   // 382 -0.698 -0.716
+assign  wn_re[383] = 16'hxxxx;   assign  wn_im[383] = 16'hxxxx;   // 383 -0.703 -0.711
+assign  wn_re[384] = 16'hA57E;   assign  wn_im[384] = 16'hA57E;   // 384 -0.707 -0.707
+assign  wn_re[385] = 16'hxxxx;   assign  wn_im[385] = 16'hxxxx;   // 385 -0.711 -0.703
+assign  wn_re[386] = 16'hA463;   assign  wn_im[386] = 16'hA69C;   // 386 -0.716 -0.698
+assign  wn_re[387] = 16'hA3D7;   assign  wn_im[387] = 16'hA72C;   // 387 -0.720 -0.694
+assign  wn_re[388] = 16'hA34C;   assign  wn_im[388] = 16'hA7BD;   // 388 -0.724 -0.690
+assign  wn_re[389] = 16'hxxxx;   assign  wn_im[389] = 16'hxxxx;   // 389 -0.728 -0.685
+assign  wn_re[390] = 16'hA238;   assign  wn_im[390] = 16'hA8E2;   // 390 -0.733 -0.681
+assign  wn_re[391] = 16'hxxxx;   assign  wn_im[391] = 16'hxxxx;   // 391 -0.737 -0.676
+assign  wn_re[392] = 16'hA129;   assign  wn_im[392] = 16'hAA0A;   // 392 -0.741 -0.672
+assign  wn_re[393] = 16'hA0A2;   assign  wn_im[393] = 16'hAAA0;   // 393 -0.745 -0.667
+assign  wn_re[394] = 16'hA01C;   assign  wn_im[394] = 16'hAB36;   // 394 -0.749 -0.662
+assign  wn_re[395] = 16'hxxxx;   assign  wn_im[395] = 16'hxxxx;   // 395 -0.753 -0.658
+assign  wn_re[396] = 16'h9F14;   assign  wn_im[396] = 16'hAC65;   // 396 -0.757 -0.653
+assign  wn_re[397] = 16'hxxxx;   assign  wn_im[397] = 16'hxxxx;   // 397 -0.761 -0.649
+assign  wn_re[398] = 16'h9E0F;   assign  wn_im[398] = 16'hAD97;   // 398 -0.765 -0.644
+assign  wn_re[399] = 16'h9D8E;   assign  wn_im[399] = 16'hAE31;   // 399 -0.769 -0.639
+assign  wn_re[400] = 16'h9D0E;   assign  wn_im[400] = 16'hAECC;   // 400 -0.773 -0.634
+assign  wn_re[401] = 16'hxxxx;   assign  wn_im[401] = 16'hxxxx;   // 401 -0.777 -0.630
+assign  wn_re[402] = 16'h9C11;   assign  wn_im[402] = 16'hB005;   // 402 -0.781 -0.625
+assign  wn_re[403] = 16'hxxxx;   assign  wn_im[403] = 16'hxxxx;   // 403 -0.785 -0.620
+assign  wn_re[404] = 16'h9B17;   assign  wn_im[404] = 16'hB140;   // 404 -0.788 -0.615
+assign  wn_re[405] = 16'h9A9C;   assign  wn_im[405] = 16'hB1DF;   // 405 -0.792 -0.610
+assign  wn_re[406] = 16'h9A22;   assign  wn_im[406] = 16'hB27F;   // 406 -0.796 -0.606
+assign  wn_re[407] = 16'hxxxx;   assign  wn_im[407] = 16'hxxxx;   // 407 -0.800 -0.601
+assign  wn_re[408] = 16'h9930;   assign  wn_im[408] = 16'hB3C0;   // 408 -0.803 -0.596
+assign  wn_re[409] = 16'hxxxx;   assign  wn_im[409] = 16'hxxxx;   // 409 -0.807 -0.591
+assign  wn_re[410] = 16'h9843;   assign  wn_im[410] = 16'hB505;   // 410 -0.810 -0.586
+assign  wn_re[411] = 16'h97CE;   assign  wn_im[411] = 16'hB5A8;   // 411 -0.814 -0.581
+assign  wn_re[412] = 16'h9759;   assign  wn_im[412] = 16'hB64C;   // 412 -0.818 -0.576
+assign  wn_re[413] = 16'hxxxx;   assign  wn_im[413] = 16'hxxxx;   // 413 -0.821 -0.571
+assign  wn_re[414] = 16'h9674;   assign  wn_im[414] = 16'hB796;   // 414 -0.825 -0.566
+assign  wn_re[415] = 16'hxxxx;   assign  wn_im[415] = 16'hxxxx;   // 415 -0.828 -0.561
+assign  wn_re[416] = 16'h9592;   assign  wn_im[416] = 16'hB8E3;   // 416 -0.831 -0.556
+assign  wn_re[417] = 16'h9523;   assign  wn_im[417] = 16'hB98B;   // 417 -0.835 -0.550
+assign  wn_re[418] = 16'h94B5;   assign  wn_im[418] = 16'hBA33;   // 418 -0.838 -0.545
+assign  wn_re[419] = 16'hxxxx;   assign  wn_im[419] = 16'hxxxx;   // 419 -0.842 -0.540
+assign  wn_re[420] = 16'h93DC;   assign  wn_im[420] = 16'hBB85;   // 420 -0.845 -0.535
+assign  wn_re[421] = 16'hxxxx;   assign  wn_im[421] = 16'hxxxx;   // 421 -0.848 -0.530
+assign  wn_re[422] = 16'h9307;   assign  wn_im[422] = 16'hBCDA;   // 422 -0.851 -0.525
+assign  wn_re[423] = 16'h929E;   assign  wn_im[423] = 16'hBD86;   // 423 -0.855 -0.519
+assign  wn_re[424] = 16'h9236;   assign  wn_im[424] = 16'hBE32;   // 424 -0.858 -0.514
+assign  wn_re[425] = 16'hxxxx;   assign  wn_im[425] = 16'hxxxx;   // 425 -0.861 -0.509
+assign  wn_re[426] = 16'h9169;   assign  wn_im[426] = 16'hBF8C;   // 426 -0.864 -0.504
+assign  wn_re[427] = 16'hxxxx;   assign  wn_im[427] = 16'hxxxx;   // 427 -0.867 -0.498
+assign  wn_re[428] = 16'h90A1;   assign  wn_im[428] = 16'hC0E9;   // 428 -0.870 -0.493
+assign  wn_re[429] = 16'h903E;   assign  wn_im[429] = 16'hC198;   // 429 -0.873 -0.488
+assign  wn_re[430] = 16'h8FDD;   assign  wn_im[430] = 16'hC248;   // 430 -0.876 -0.482
+assign  wn_re[431] = 16'hxxxx;   assign  wn_im[431] = 16'hxxxx;   // 431 -0.879 -0.477
+assign  wn_re[432] = 16'h8F1D;   assign  wn_im[432] = 16'hC3A9;   // 432 -0.882 -0.471
+assign  wn_re[433] = 16'hxxxx;   assign  wn_im[433] = 16'hxxxx;   // 433 -0.885 -0.466
+assign  wn_re[434] = 16'h8E62;   assign  wn_im[434] = 16'hC50D;   // 434 -0.888 -0.461
+assign  wn_re[435] = 16'h8E06;   assign  wn_im[435] = 16'hC5C0;   // 435 -0.890 -0.455
+assign  wn_re[436] = 16'h8DAB;   assign  wn_im[436] = 16'hC673;   // 436 -0.893 -0.450
+assign  wn_re[437] = 16'hxxxx;   assign  wn_im[437] = 16'hxxxx;   // 437 -0.896 -0.444
+assign  wn_re[438] = 16'h8CF8;   assign  wn_im[438] = 16'hC7DB;   // 438 -0.899 -0.439
+assign  wn_re[439] = 16'hxxxx;   assign  wn_im[439] = 16'hxxxx;   // 439 -0.901 -0.433
+assign  wn_re[440] = 16'h8C4A;   assign  wn_im[440] = 16'hC946;   // 440 -0.904 -0.428
+assign  wn_re[441] = 16'h8BF5;   assign  wn_im[441] = 16'hC9FC;   // 441 -0.907 -0.422
+assign  wn_re[442] = 16'h8BA0;   assign  wn_im[442] = 16'hCAB2;   // 442 -0.909 -0.416
+assign  wn_re[443] = 16'hxxxx;   assign  wn_im[443] = 16'hxxxx;   // 443 -0.912 -0.411
+assign  wn_re[444] = 16'h8AFB;   assign  wn_im[444] = 16'hCC21;   // 444 -0.914 -0.405
+assign  wn_re[445] = 16'hxxxx;   assign  wn_im[445] = 16'hxxxx;   // 445 -0.917 -0.400
+assign  wn_re[446] = 16'h8A5A;   assign  wn_im[446] = 16'hCD92;   // 446 -0.919 -0.394
+assign  wn_re[447] = 16'h8A0C;   assign  wn_im[447] = 16'hCE4B;   // 447 -0.922 -0.388
+assign  wn_re[448] = 16'h89BE;   assign  wn_im[448] = 16'hCF04;   // 448 -0.924 -0.383
+assign  wn_re[449] = 16'hxxxx;   assign  wn_im[449] = 16'hxxxx;   // 449 -0.926 -0.377
+assign  wn_re[450] = 16'h8927;   assign  wn_im[450] = 16'hD079;   // 450 -0.929 -0.371
+assign  wn_re[451] = 16'hxxxx;   assign  wn_im[451] = 16'hxxxx;   // 451 -0.931 -0.366
+assign  wn_re[452] = 16'h8894;   assign  wn_im[452] = 16'hD1EF;   // 452 -0.933 -0.360
+assign  wn_re[453] = 16'h884C;   assign  wn_im[453] = 16'hD2AB;   // 453 -0.935 -0.354
+assign  wn_re[454] = 16'h8805;   assign  wn_im[454] = 16'hD367;   // 454 -0.937 -0.348
+assign  wn_re[455] = 16'hxxxx;   assign  wn_im[455] = 16'hxxxx;   // 455 -0.939 -0.343
+assign  wn_re[456] = 16'h877B;   assign  wn_im[456] = 16'hD4E1;   // 456 -0.942 -0.337
+assign  wn_re[457] = 16'hxxxx;   assign  wn_im[457] = 16'hxxxx;   // 457 -0.944 -0.331
+assign  wn_re[458] = 16'h86F6;   assign  wn_im[458] = 16'hD65C;   // 458 -0.946 -0.325
+assign  wn_re[459] = 16'h86B6;   assign  wn_im[459] = 16'hD71B;   // 459 -0.948 -0.320
+assign  wn_re[460] = 16'h8676;   assign  wn_im[460] = 16'hD7D9;   // 460 -0.950 -0.314
+assign  wn_re[461] = 16'hxxxx;   assign  wn_im[461] = 16'hxxxx;   // 461 -0.951 -0.308
+assign  wn_re[462] = 16'h85FA;   assign  wn_im[462] = 16'hD958;   // 462 -0.953 -0.302
+assign  wn_re[463] = 16'hxxxx;   assign  wn_im[463] = 16'hxxxx;   // 463 -0.955 -0.296
+assign  wn_re[464] = 16'h8583;   assign  wn_im[464] = 16'hDAD8;   // 464 -0.957 -0.290
+assign  wn_re[465] = 16'h8549;   assign  wn_im[465] = 16'hDB99;   // 465 -0.959 -0.284
+assign  wn_re[466] = 16'h8511;   assign  wn_im[466] = 16'hDC59;   // 466 -0.960 -0.279
+assign  wn_re[467] = 16'hxxxx;   assign  wn_im[467] = 16'hxxxx;   // 467 -0.962 -0.273
+assign  wn_re[468] = 16'h84A3;   assign  wn_im[468] = 16'hDDDC;   // 468 -0.964 -0.267
+assign  wn_re[469] = 16'hxxxx;   assign  wn_im[469] = 16'hxxxx;   // 469 -0.965 -0.261
+assign  wn_re[470] = 16'h843A;   assign  wn_im[470] = 16'hDF61;   // 470 -0.967 -0.255
+assign  wn_re[471] = 16'h8407;   assign  wn_im[471] = 16'hE023;   // 471 -0.969 -0.249
+assign  wn_re[472] = 16'h83D6;   assign  wn_im[472] = 16'hE0E6;   // 472 -0.970 -0.243
+assign  wn_re[473] = 16'hxxxx;   assign  wn_im[473] = 16'hxxxx;   // 473 -0.972 -0.237
+assign  wn_re[474] = 16'h8377;   assign  wn_im[474] = 16'hE26D;   // 474 -0.973 -0.231
+assign  wn_re[475] = 16'hxxxx;   assign  wn_im[475] = 16'hxxxx;   // 475 -0.974 -0.225
+assign  wn_re[476] = 16'h831C;   assign  wn_im[476] = 16'hE3F4;   // 476 -0.976 -0.219
+assign  wn_re[477] = 16'h82F1;   assign  wn_im[477] = 16'hE4B9;   // 477 -0.977 -0.213
+assign  wn_re[478] = 16'h82C6;   assign  wn_im[478] = 16'hE57D;   // 478 -0.978 -0.207
+assign  wn_re[479] = 16'hxxxx;   assign  wn_im[479] = 16'hxxxx;   // 479 -0.980 -0.201
+assign  wn_re[480] = 16'h8276;   assign  wn_im[480] = 16'hE707;   // 480 -0.981 -0.195
+assign  wn_re[481] = 16'hxxxx;   assign  wn_im[481] = 16'hxxxx;   // 481 -0.982 -0.189
+assign  wn_re[482] = 16'h822A;   assign  wn_im[482] = 16'hE892;   // 482 -0.983 -0.183
+assign  wn_re[483] = 16'h8205;   assign  wn_im[483] = 16'hE958;   // 483 -0.984 -0.177
+assign  wn_re[484] = 16'h81E2;   assign  wn_im[484] = 16'hEA1E;   // 484 -0.985 -0.171
+assign  wn_re[485] = 16'hxxxx;   assign  wn_im[485] = 16'hxxxx;   // 485 -0.986 -0.165
+assign  wn_re[486] = 16'h81A0;   assign  wn_im[486] = 16'hEBAB;   // 486 -0.987 -0.159
+assign  wn_re[487] = 16'hxxxx;   assign  wn_im[487] = 16'hxxxx;   // 487 -0.988 -0.153
+assign  wn_re[488] = 16'h8163;   assign  wn_im[488] = 16'hED38;   // 488 -0.989 -0.147
+assign  wn_re[489] = 16'h8146;   assign  wn_im[489] = 16'hEDFF;   // 489 -0.990 -0.141
+assign  wn_re[490] = 16'h812A;   assign  wn_im[490] = 16'hEEC6;   // 490 -0.991 -0.135
+assign  wn_re[491] = 16'hxxxx;   assign  wn_im[491] = 16'hxxxx;   // 491 -0.992 -0.128
+assign  wn_re[492] = 16'h80F6;   assign  wn_im[492] = 16'hF055;   // 492 -0.992 -0.122
+assign  wn_re[493] = 16'hxxxx;   assign  wn_im[493] = 16'hxxxx;   // 493 -0.993 -0.116
+assign  wn_re[494] = 16'h80C8;   assign  wn_im[494] = 16'hF1E4;   // 494 -0.994 -0.110
+assign  wn_re[495] = 16'h80B2;   assign  wn_im[495] = 16'hF2AC;   // 495 -0.995 -0.104
+assign  wn_re[496] = 16'h809E;   assign  wn_im[496] = 16'hF374;   // 496 -0.995 -0.098
+assign  wn_re[497] = 16'hxxxx;   assign  wn_im[497] = 16'hxxxx;   // 497 -0.996 -0.092
+assign  wn_re[498] = 16'h8079;   assign  wn_im[498] = 16'hF505;   // 498 -0.996 -0.086
+assign  wn_re[499] = 16'hxxxx;   assign  wn_im[499] = 16'hxxxx;   // 499 -0.997 -0.080
+assign  wn_re[500] = 16'h8059;   assign  wn_im[500] = 16'hF695;   // 500 -0.997 -0.074
+assign  wn_re[501] = 16'h804B;   assign  wn_im[501] = 16'hF75E;   // 501 -0.998 -0.067
+assign  wn_re[502] = 16'h803E;   assign  wn_im[502] = 16'hF827;   // 502 -0.998 -0.061
+assign  wn_re[503] = 16'hxxxx;   assign  wn_im[503] = 16'hxxxx;   // 503 -0.998 -0.055
+assign  wn_re[504] = 16'h8027;   assign  wn_im[504] = 16'hF9B8;   // 504 -0.999 -0.049
+assign  wn_re[505] = 16'hxxxx;   assign  wn_im[505] = 16'hxxxx;   // 505 -0.999 -0.043
+assign  wn_re[506] = 16'h8016;   assign  wn_im[506] = 16'hFB4A;   // 506 -0.999 -0.037
+assign  wn_re[507] = 16'h800F;   assign  wn_im[507] = 16'hFC13;   // 507 -1.000 -0.031
+assign  wn_re[508] = 16'h800A;   assign  wn_im[508] = 16'hFCDC;   // 508 -1.000 -0.025
+assign  wn_re[509] = 16'hxxxx;   assign  wn_im[509] = 16'hxxxx;   // 509 -1.000 -0.018
+assign  wn_re[510] = 16'h8002;   assign  wn_im[510] = 16'hFE6E;   // 510 -1.000 -0.012
+assign  wn_re[511] = 16'hxxxx;   assign  wn_im[511] = 16'hxxxx;   // 511 -1.000 -0.006
+assign  wn_re[512] = 16'hxxxx;   assign  wn_im[512] = 16'hxxxx;   // 512 -1.000 -0.000
+assign  wn_re[513] = 16'h8001;   assign  wn_im[513] = 16'h00C9;   // 513 -1.000  0.006
+assign  wn_re[514] = 16'hxxxx;   assign  wn_im[514] = 16'hxxxx;   // 514 -1.000  0.012
+assign  wn_re[515] = 16'hxxxx;   assign  wn_im[515] = 16'hxxxx;   // 515 -1.000  0.018
+assign  wn_re[516] = 16'h800A;   assign  wn_im[516] = 16'h0324;   // 516 -1.000  0.025
+assign  wn_re[517] = 16'hxxxx;   assign  wn_im[517] = 16'hxxxx;   // 517 -1.000  0.031
+assign  wn_re[518] = 16'hxxxx;   assign  wn_im[518] = 16'hxxxx;   // 518 -0.999  0.037
+assign  wn_re[519] = 16'h801E;   assign  wn_im[519] = 16'h057F;   // 519 -0.999  0.043
+assign  wn_re[520] = 16'hxxxx;   assign  wn_im[520] = 16'hxxxx;   // 520 -0.999  0.049
+assign  wn_re[521] = 16'hxxxx;   assign  wn_im[521] = 16'hxxxx;   // 521 -0.998  0.055
+assign  wn_re[522] = 16'h803E;   assign  wn_im[522] = 16'h07D9;   // 522 -0.998  0.061
+assign  wn_re[523] = 16'hxxxx;   assign  wn_im[523] = 16'hxxxx;   // 523 -0.998  0.067
+assign  wn_re[524] = 16'hxxxx;   assign  wn_im[524] = 16'hxxxx;   // 524 -0.997  0.074
+assign  wn_re[525] = 16'h8068;   assign  wn_im[525] = 16'h0A33;   // 525 -0.997  0.080
+assign  wn_re[526] = 16'hxxxx;   assign  wn_im[526] = 16'hxxxx;   // 526 -0.996  0.086
+assign  wn_re[527] = 16'hxxxx;   assign  wn_im[527] = 16'hxxxx;   // 527 -0.996  0.092
+assign  wn_re[528] = 16'h809E;   assign  wn_im[528] = 16'h0C8C;   // 528 -0.995  0.098
+assign  wn_re[529] = 16'hxxxx;   assign  wn_im[529] = 16'hxxxx;   // 529 -0.995  0.104
+assign  wn_re[530] = 16'hxxxx;   assign  wn_im[530] = 16'hxxxx;   // 530 -0.994  0.110
+assign  wn_re[531] = 16'h80DE;   assign  wn_im[531] = 16'h0EE4;   // 531 -0.993  0.116
+assign  wn_re[532] = 16'hxxxx;   assign  wn_im[532] = 16'hxxxx;   // 532 -0.992  0.122
+assign  wn_re[533] = 16'hxxxx;   assign  wn_im[533] = 16'hxxxx;   // 533 -0.992  0.128
+assign  wn_re[534] = 16'h812A;   assign  wn_im[534] = 16'h113A;   // 534 -0.991  0.135
+assign  wn_re[535] = 16'hxxxx;   assign  wn_im[535] = 16'hxxxx;   // 535 -0.990  0.141
+assign  wn_re[536] = 16'hxxxx;   assign  wn_im[536] = 16'hxxxx;   // 536 -0.989  0.147
+assign  wn_re[537] = 16'h8181;   assign  wn_im[537] = 16'h138F;   // 537 -0.988  0.153
+assign  wn_re[538] = 16'hxxxx;   assign  wn_im[538] = 16'hxxxx;   // 538 -0.987  0.159
+assign  wn_re[539] = 16'hxxxx;   assign  wn_im[539] = 16'hxxxx;   // 539 -0.986  0.165
+assign  wn_re[540] = 16'h81E2;   assign  wn_im[540] = 16'h15E2;   // 540 -0.985  0.171
+assign  wn_re[541] = 16'hxxxx;   assign  wn_im[541] = 16'hxxxx;   // 541 -0.984  0.177
+assign  wn_re[542] = 16'hxxxx;   assign  wn_im[542] = 16'hxxxx;   // 542 -0.983  0.183
+assign  wn_re[543] = 16'h824F;   assign  wn_im[543] = 16'h1833;   // 543 -0.982  0.189
+assign  wn_re[544] = 16'hxxxx;   assign  wn_im[544] = 16'hxxxx;   // 544 -0.981  0.195
+assign  wn_re[545] = 16'hxxxx;   assign  wn_im[545] = 16'hxxxx;   // 545 -0.980  0.201
+assign  wn_re[546] = 16'h82C6;   assign  wn_im[546] = 16'h1A83;   // 546 -0.978  0.207
+assign  wn_re[547] = 16'hxxxx;   assign  wn_im[547] = 16'hxxxx;   // 547 -0.977  0.213
+assign  wn_re[548] = 16'hxxxx;   assign  wn_im[548] = 16'hxxxx;   // 548 -0.976  0.219
+assign  wn_re[549] = 16'h8349;   assign  wn_im[549] = 16'h1CD0;   // 549 -0.974  0.225
+assign  wn_re[550] = 16'hxxxx;   assign  wn_im[550] = 16'hxxxx;   // 550 -0.973  0.231
+assign  wn_re[551] = 16'hxxxx;   assign  wn_im[551] = 16'hxxxx;   // 551 -0.972  0.237
+assign  wn_re[552] = 16'h83D6;   assign  wn_im[552] = 16'h1F1A;   // 552 -0.970  0.243
+assign  wn_re[553] = 16'hxxxx;   assign  wn_im[553] = 16'hxxxx;   // 553 -0.969  0.249
+assign  wn_re[554] = 16'hxxxx;   assign  wn_im[554] = 16'hxxxx;   // 554 -0.967  0.255
+assign  wn_re[555] = 16'h846E;   assign  wn_im[555] = 16'h2162;   // 555 -0.965  0.261
+assign  wn_re[556] = 16'hxxxx;   assign  wn_im[556] = 16'hxxxx;   // 556 -0.964  0.267
+assign  wn_re[557] = 16'hxxxx;   assign  wn_im[557] = 16'hxxxx;   // 557 -0.962  0.273
+assign  wn_re[558] = 16'h8511;   assign  wn_im[558] = 16'h23A7;   // 558 -0.960  0.279
+assign  wn_re[559] = 16'hxxxx;   assign  wn_im[559] = 16'hxxxx;   // 559 -0.959  0.284
+assign  wn_re[560] = 16'hxxxx;   assign  wn_im[560] = 16'hxxxx;   // 560 -0.957  0.290
+assign  wn_re[561] = 16'h85BE;   assign  wn_im[561] = 16'h25E8;   // 561 -0.955  0.296
+assign  wn_re[562] = 16'hxxxx;   assign  wn_im[562] = 16'hxxxx;   // 562 -0.953  0.302
+assign  wn_re[563] = 16'hxxxx;   assign  wn_im[563] = 16'hxxxx;   // 563 -0.951  0.308
+assign  wn_re[564] = 16'h8676;   assign  wn_im[564] = 16'h2827;   // 564 -0.950  0.314
+assign  wn_re[565] = 16'hxxxx;   assign  wn_im[565] = 16'hxxxx;   // 565 -0.948  0.320
+assign  wn_re[566] = 16'hxxxx;   assign  wn_im[566] = 16'hxxxx;   // 566 -0.946  0.325
+assign  wn_re[567] = 16'h8738;   assign  wn_im[567] = 16'h2A62;   // 567 -0.944  0.331
+assign  wn_re[568] = 16'hxxxx;   assign  wn_im[568] = 16'hxxxx;   // 568 -0.942  0.337
+assign  wn_re[569] = 16'hxxxx;   assign  wn_im[569] = 16'hxxxx;   // 569 -0.939  0.343
+assign  wn_re[570] = 16'h8805;   assign  wn_im[570] = 16'h2C99;   // 570 -0.937  0.348
+assign  wn_re[571] = 16'hxxxx;   assign  wn_im[571] = 16'hxxxx;   // 571 -0.935  0.354
+assign  wn_re[572] = 16'hxxxx;   assign  wn_im[572] = 16'hxxxx;   // 572 -0.933  0.360
+assign  wn_re[573] = 16'h88DD;   assign  wn_im[573] = 16'h2ECC;   // 573 -0.931  0.366
+assign  wn_re[574] = 16'hxxxx;   assign  wn_im[574] = 16'hxxxx;   // 574 -0.929  0.371
+assign  wn_re[575] = 16'hxxxx;   assign  wn_im[575] = 16'hxxxx;   // 575 -0.926  0.377
+assign  wn_re[576] = 16'h89BE;   assign  wn_im[576] = 16'h30FC;   // 576 -0.924  0.383
+assign  wn_re[577] = 16'hxxxx;   assign  wn_im[577] = 16'hxxxx;   // 577 -0.922  0.388
+assign  wn_re[578] = 16'hxxxx;   assign  wn_im[578] = 16'hxxxx;   // 578 -0.919  0.394
+assign  wn_re[579] = 16'h8AAA;   assign  wn_im[579] = 16'h3327;   // 579 -0.917  0.400
+assign  wn_re[580] = 16'hxxxx;   assign  wn_im[580] = 16'hxxxx;   // 580 -0.914  0.405
+assign  wn_re[581] = 16'hxxxx;   assign  wn_im[581] = 16'hxxxx;   // 581 -0.912  0.411
+assign  wn_re[582] = 16'h8BA0;   assign  wn_im[582] = 16'h354E;   // 582 -0.909  0.416
+assign  wn_re[583] = 16'hxxxx;   assign  wn_im[583] = 16'hxxxx;   // 583 -0.907  0.422
+assign  wn_re[584] = 16'hxxxx;   assign  wn_im[584] = 16'hxxxx;   // 584 -0.904  0.428
+assign  wn_re[585] = 16'h8CA1;   assign  wn_im[585] = 16'h3770;   // 585 -0.901  0.433
+assign  wn_re[586] = 16'hxxxx;   assign  wn_im[586] = 16'hxxxx;   // 586 -0.899  0.439
+assign  wn_re[587] = 16'hxxxx;   assign  wn_im[587] = 16'hxxxx;   // 587 -0.896  0.444
+assign  wn_re[588] = 16'h8DAB;   assign  wn_im[588] = 16'h398D;   // 588 -0.893  0.450
+assign  wn_re[589] = 16'hxxxx;   assign  wn_im[589] = 16'hxxxx;   // 589 -0.890  0.455
+assign  wn_re[590] = 16'hxxxx;   assign  wn_im[590] = 16'hxxxx;   // 590 -0.888  0.461
+assign  wn_re[591] = 16'h8EBF;   assign  wn_im[591] = 16'h3BA5;   // 591 -0.885  0.466
+assign  wn_re[592] = 16'hxxxx;   assign  wn_im[592] = 16'hxxxx;   // 592 -0.882  0.471
+assign  wn_re[593] = 16'hxxxx;   assign  wn_im[593] = 16'hxxxx;   // 593 -0.879  0.477
+assign  wn_re[594] = 16'h8FDD;   assign  wn_im[594] = 16'h3DB8;   // 594 -0.876  0.482
+assign  wn_re[595] = 16'hxxxx;   assign  wn_im[595] = 16'hxxxx;   // 595 -0.873  0.488
+assign  wn_re[596] = 16'hxxxx;   assign  wn_im[596] = 16'hxxxx;   // 596 -0.870  0.493
+assign  wn_re[597] = 16'h9105;   assign  wn_im[597] = 16'h3FC6;   // 597 -0.867  0.498
+assign  wn_re[598] = 16'hxxxx;   assign  wn_im[598] = 16'hxxxx;   // 598 -0.864  0.504
+assign  wn_re[599] = 16'hxxxx;   assign  wn_im[599] = 16'hxxxx;   // 599 -0.861  0.509
+assign  wn_re[600] = 16'h9236;   assign  wn_im[600] = 16'h41CE;   // 600 -0.858  0.514
+assign  wn_re[601] = 16'hxxxx;   assign  wn_im[601] = 16'hxxxx;   // 601 -0.855  0.519
+assign  wn_re[602] = 16'hxxxx;   assign  wn_im[602] = 16'hxxxx;   // 602 -0.851  0.525
+assign  wn_re[603] = 16'h9371;   assign  wn_im[603] = 16'h43D1;   // 603 -0.848  0.530
+assign  wn_re[604] = 16'hxxxx;   assign  wn_im[604] = 16'hxxxx;   // 604 -0.845  0.535
+assign  wn_re[605] = 16'hxxxx;   assign  wn_im[605] = 16'hxxxx;   // 605 -0.842  0.540
+assign  wn_re[606] = 16'h94B5;   assign  wn_im[606] = 16'h45CD;   // 606 -0.838  0.545
+assign  wn_re[607] = 16'hxxxx;   assign  wn_im[607] = 16'hxxxx;   // 607 -0.835  0.550
+assign  wn_re[608] = 16'hxxxx;   assign  wn_im[608] = 16'hxxxx;   // 608 -0.831  0.556
+assign  wn_re[609] = 16'h9603;   assign  wn_im[609] = 16'h47C4;   // 609 -0.828  0.561
+assign  wn_re[610] = 16'hxxxx;   assign  wn_im[610] = 16'hxxxx;   // 610 -0.825  0.566
+assign  wn_re[611] = 16'hxxxx;   assign  wn_im[611] = 16'hxxxx;   // 611 -0.821  0.571
+assign  wn_re[612] = 16'h9759;   assign  wn_im[612] = 16'h49B4;   // 612 -0.818  0.576
+assign  wn_re[613] = 16'hxxxx;   assign  wn_im[613] = 16'hxxxx;   // 613 -0.814  0.581
+assign  wn_re[614] = 16'hxxxx;   assign  wn_im[614] = 16'hxxxx;   // 614 -0.810  0.586
+assign  wn_re[615] = 16'h98B9;   assign  wn_im[615] = 16'h4B9E;   // 615 -0.807  0.591
+assign  wn_re[616] = 16'hxxxx;   assign  wn_im[616] = 16'hxxxx;   // 616 -0.803  0.596
+assign  wn_re[617] = 16'hxxxx;   assign  wn_im[617] = 16'hxxxx;   // 617 -0.800  0.601
+assign  wn_re[618] = 16'h9A22;   assign  wn_im[618] = 16'h4D81;   // 618 -0.796  0.606
+assign  wn_re[619] = 16'hxxxx;   assign  wn_im[619] = 16'hxxxx;   // 619 -0.792  0.610
+assign  wn_re[620] = 16'hxxxx;   assign  wn_im[620] = 16'hxxxx;   // 620 -0.788  0.615
+assign  wn_re[621] = 16'h9B94;   assign  wn_im[621] = 16'h4F5E;   // 621 -0.785  0.620
+assign  wn_re[622] = 16'hxxxx;   assign  wn_im[622] = 16'hxxxx;   // 622 -0.781  0.625
+assign  wn_re[623] = 16'hxxxx;   assign  wn_im[623] = 16'hxxxx;   // 623 -0.777  0.630
+assign  wn_re[624] = 16'h9D0E;   assign  wn_im[624] = 16'h5134;   // 624 -0.773  0.634
+assign  wn_re[625] = 16'hxxxx;   assign  wn_im[625] = 16'hxxxx;   // 625 -0.769  0.639
+assign  wn_re[626] = 16'hxxxx;   assign  wn_im[626] = 16'hxxxx;   // 626 -0.765  0.644
+assign  wn_re[627] = 16'h9E91;   assign  wn_im[627] = 16'h5303;   // 627 -0.761  0.649
+assign  wn_re[628] = 16'hxxxx;   assign  wn_im[628] = 16'hxxxx;   // 628 -0.757  0.653
+assign  wn_re[629] = 16'hxxxx;   assign  wn_im[629] = 16'hxxxx;   // 629 -0.753  0.658
+assign  wn_re[630] = 16'hA01C;   assign  wn_im[630] = 16'h54CA;   // 630 -0.749  0.662
+assign  wn_re[631] = 16'hxxxx;   assign  wn_im[631] = 16'hxxxx;   // 631 -0.745  0.667
+assign  wn_re[632] = 16'hxxxx;   assign  wn_im[632] = 16'hxxxx;   // 632 -0.741  0.672
+assign  wn_re[633] = 16'hA1B0;   assign  wn_im[633] = 16'h568A;   // 633 -0.737  0.676
+assign  wn_re[634] = 16'hxxxx;   assign  wn_im[634] = 16'hxxxx;   // 634 -0.733  0.681
+assign  wn_re[635] = 16'hxxxx;   assign  wn_im[635] = 16'hxxxx;   // 635 -0.728  0.685
+assign  wn_re[636] = 16'hA34C;   assign  wn_im[636] = 16'h5843;   // 636 -0.724  0.690
+assign  wn_re[637] = 16'hxxxx;   assign  wn_im[637] = 16'hxxxx;   // 637 -0.720  0.694
+assign  wn_re[638] = 16'hxxxx;   assign  wn_im[638] = 16'hxxxx;   // 638 -0.716  0.698
+assign  wn_re[639] = 16'hA4F0;   assign  wn_im[639] = 16'h59F4;   // 639 -0.711  0.703
+assign  wn_re[640] = 16'hxxxx;   assign  wn_im[640] = 16'hxxxx;   // 640 -0.707  0.707
+assign  wn_re[641] = 16'hxxxx;   assign  wn_im[641] = 16'hxxxx;   // 641 -0.703  0.711
+assign  wn_re[642] = 16'hA69C;   assign  wn_im[642] = 16'h5B9D;   // 642 -0.698  0.716
+assign  wn_re[643] = 16'hxxxx;   assign  wn_im[643] = 16'hxxxx;   // 643 -0.694  0.720
+assign  wn_re[644] = 16'hxxxx;   assign  wn_im[644] = 16'hxxxx;   // 644 -0.690  0.724
+assign  wn_re[645] = 16'hA84F;   assign  wn_im[645] = 16'h5D3E;   // 645 -0.685  0.728
+assign  wn_re[646] = 16'hxxxx;   assign  wn_im[646] = 16'hxxxx;   // 646 -0.681  0.733
+assign  wn_re[647] = 16'hxxxx;   assign  wn_im[647] = 16'hxxxx;   // 647 -0.676  0.737
+assign  wn_re[648] = 16'hAA0A;   assign  wn_im[648] = 16'h5ED7;   // 648 -0.672  0.741
+assign  wn_re[649] = 16'hxxxx;   assign  wn_im[649] = 16'hxxxx;   // 649 -0.667  0.745
+assign  wn_re[650] = 16'hxxxx;   assign  wn_im[650] = 16'hxxxx;   // 650 -0.662  0.749
+assign  wn_re[651] = 16'hABCD;   assign  wn_im[651] = 16'h6068;   // 651 -0.658  0.753
+assign  wn_re[652] = 16'hxxxx;   assign  wn_im[652] = 16'hxxxx;   // 652 -0.653  0.757
+assign  wn_re[653] = 16'hxxxx;   assign  wn_im[653] = 16'hxxxx;   // 653 -0.649  0.761
+assign  wn_re[654] = 16'hAD97;   assign  wn_im[654] = 16'h61F1;   // 654 -0.644  0.765
+assign  wn_re[655] = 16'hxxxx;   assign  wn_im[655] = 16'hxxxx;   // 655 -0.639  0.769
+assign  wn_re[656] = 16'hxxxx;   assign  wn_im[656] = 16'hxxxx;   // 656 -0.634  0.773
+assign  wn_re[657] = 16'hAF68;   assign  wn_im[657] = 16'h6371;   // 657 -0.630  0.777
+assign  wn_re[658] = 16'hxxxx;   assign  wn_im[658] = 16'hxxxx;   // 658 -0.625  0.781
+assign  wn_re[659] = 16'hxxxx;   assign  wn_im[659] = 16'hxxxx;   // 659 -0.620  0.785
+assign  wn_re[660] = 16'hB140;   assign  wn_im[660] = 16'h64E9;   // 660 -0.615  0.788
+assign  wn_re[661] = 16'hxxxx;   assign  wn_im[661] = 16'hxxxx;   // 661 -0.610  0.792
+assign  wn_re[662] = 16'hxxxx;   assign  wn_im[662] = 16'hxxxx;   // 662 -0.606  0.796
+assign  wn_re[663] = 16'hB31F;   assign  wn_im[663] = 16'h6657;   // 663 -0.601  0.800
+assign  wn_re[664] = 16'hxxxx;   assign  wn_im[664] = 16'hxxxx;   // 664 -0.596  0.803
+assign  wn_re[665] = 16'hxxxx;   assign  wn_im[665] = 16'hxxxx;   // 665 -0.591  0.807
+assign  wn_re[666] = 16'hB505;   assign  wn_im[666] = 16'h67BD;   // 666 -0.586  0.810
+assign  wn_re[667] = 16'hxxxx;   assign  wn_im[667] = 16'hxxxx;   // 667 -0.581  0.814
+assign  wn_re[668] = 16'hxxxx;   assign  wn_im[668] = 16'hxxxx;   // 668 -0.576  0.818
+assign  wn_re[669] = 16'hB6F1;   assign  wn_im[669] = 16'h691A;   // 669 -0.571  0.821
+assign  wn_re[670] = 16'hxxxx;   assign  wn_im[670] = 16'hxxxx;   // 670 -0.566  0.825
+assign  wn_re[671] = 16'hxxxx;   assign  wn_im[671] = 16'hxxxx;   // 671 -0.561  0.828
+assign  wn_re[672] = 16'hB8E3;   assign  wn_im[672] = 16'h6A6E;   // 672 -0.556  0.831
+assign  wn_re[673] = 16'hxxxx;   assign  wn_im[673] = 16'hxxxx;   // 673 -0.550  0.835
+assign  wn_re[674] = 16'hxxxx;   assign  wn_im[674] = 16'hxxxx;   // 674 -0.545  0.838
+assign  wn_re[675] = 16'hBADC;   assign  wn_im[675] = 16'h6BB8;   // 675 -0.540  0.842
+assign  wn_re[676] = 16'hxxxx;   assign  wn_im[676] = 16'hxxxx;   // 676 -0.535  0.845
+assign  wn_re[677] = 16'hxxxx;   assign  wn_im[677] = 16'hxxxx;   // 677 -0.530  0.848
+assign  wn_re[678] = 16'hBCDA;   assign  wn_im[678] = 16'h6CF9;   // 678 -0.525  0.851
+assign  wn_re[679] = 16'hxxxx;   assign  wn_im[679] = 16'hxxxx;   // 679 -0.519  0.855
+assign  wn_re[680] = 16'hxxxx;   assign  wn_im[680] = 16'hxxxx;   // 680 -0.514  0.858
+assign  wn_re[681] = 16'hBEDF;   assign  wn_im[681] = 16'h6E31;   // 681 -0.509  0.861
+assign  wn_re[682] = 16'hxxxx;   assign  wn_im[682] = 16'hxxxx;   // 682 -0.504  0.864
+assign  wn_re[683] = 16'hxxxx;   assign  wn_im[683] = 16'hxxxx;   // 683 -0.498  0.867
+assign  wn_re[684] = 16'hC0E9;   assign  wn_im[684] = 16'h6F5F;   // 684 -0.493  0.870
+assign  wn_re[685] = 16'hxxxx;   assign  wn_im[685] = 16'hxxxx;   // 685 -0.488  0.873
+assign  wn_re[686] = 16'hxxxx;   assign  wn_im[686] = 16'hxxxx;   // 686 -0.482  0.876
+assign  wn_re[687] = 16'hC2F8;   assign  wn_im[687] = 16'h7083;   // 687 -0.477  0.879
+assign  wn_re[688] = 16'hxxxx;   assign  wn_im[688] = 16'hxxxx;   // 688 -0.471  0.882
+assign  wn_re[689] = 16'hxxxx;   assign  wn_im[689] = 16'hxxxx;   // 689 -0.466  0.885
+assign  wn_re[690] = 16'hC50D;   assign  wn_im[690] = 16'h719E;   // 690 -0.461  0.888
+assign  wn_re[691] = 16'hxxxx;   assign  wn_im[691] = 16'hxxxx;   // 691 -0.455  0.890
+assign  wn_re[692] = 16'hxxxx;   assign  wn_im[692] = 16'hxxxx;   // 692 -0.450  0.893
+assign  wn_re[693] = 16'hC727;   assign  wn_im[693] = 16'h72AF;   // 693 -0.444  0.896
+assign  wn_re[694] = 16'hxxxx;   assign  wn_im[694] = 16'hxxxx;   // 694 -0.439  0.899
+assign  wn_re[695] = 16'hxxxx;   assign  wn_im[695] = 16'hxxxx;   // 695 -0.433  0.901
+assign  wn_re[696] = 16'hC946;   assign  wn_im[696] = 16'h73B6;   // 696 -0.428  0.904
+assign  wn_re[697] = 16'hxxxx;   assign  wn_im[697] = 16'hxxxx;   // 697 -0.422  0.907
+assign  wn_re[698] = 16'hxxxx;   assign  wn_im[698] = 16'hxxxx;   // 698 -0.416  0.909
+assign  wn_re[699] = 16'hCB69;   assign  wn_im[699] = 16'h74B3;   // 699 -0.411  0.912
+assign  wn_re[700] = 16'hxxxx;   assign  wn_im[700] = 16'hxxxx;   // 700 -0.405  0.914
+assign  wn_re[701] = 16'hxxxx;   assign  wn_im[701] = 16'hxxxx;   // 701 -0.400  0.917
+assign  wn_re[702] = 16'hCD92;   assign  wn_im[702] = 16'h75A6;   // 702 -0.394  0.919
+assign  wn_re[703] = 16'hxxxx;   assign  wn_im[703] = 16'hxxxx;   // 703 -0.388  0.922
+assign  wn_re[704] = 16'hxxxx;   assign  wn_im[704] = 16'hxxxx;   // 704 -0.383  0.924
+assign  wn_re[705] = 16'hCFBE;   assign  wn_im[705] = 16'h768E;   // 705 -0.377  0.926
+assign  wn_re[706] = 16'hxxxx;   assign  wn_im[706] = 16'hxxxx;   // 706 -0.371  0.929
+assign  wn_re[707] = 16'hxxxx;   assign  wn_im[707] = 16'hxxxx;   // 707 -0.366  0.931
+assign  wn_re[708] = 16'hD1EF;   assign  wn_im[708] = 16'h776C;   // 708 -0.360  0.933
+assign  wn_re[709] = 16'hxxxx;   assign  wn_im[709] = 16'hxxxx;   // 709 -0.354  0.935
+assign  wn_re[710] = 16'hxxxx;   assign  wn_im[710] = 16'hxxxx;   // 710 -0.348  0.937
+assign  wn_re[711] = 16'hD424;   assign  wn_im[711] = 16'h7840;   // 711 -0.343  0.939
+assign  wn_re[712] = 16'hxxxx;   assign  wn_im[712] = 16'hxxxx;   // 712 -0.337  0.942
+assign  wn_re[713] = 16'hxxxx;   assign  wn_im[713] = 16'hxxxx;   // 713 -0.331  0.944
+assign  wn_re[714] = 16'hD65C;   assign  wn_im[714] = 16'h790A;   // 714 -0.325  0.946
+assign  wn_re[715] = 16'hxxxx;   assign  wn_im[715] = 16'hxxxx;   // 715 -0.320  0.948
+assign  wn_re[716] = 16'hxxxx;   assign  wn_im[716] = 16'hxxxx;   // 716 -0.314  0.950
+assign  wn_re[717] = 16'hD898;   assign  wn_im[717] = 16'h79C9;   // 717 -0.308  0.951
+assign  wn_re[718] = 16'hxxxx;   assign  wn_im[718] = 16'hxxxx;   // 718 -0.302  0.953
+assign  wn_re[719] = 16'hxxxx;   assign  wn_im[719] = 16'hxxxx;   // 719 -0.296  0.955
+assign  wn_re[720] = 16'hDAD8;   assign  wn_im[720] = 16'h7A7D;   // 720 -0.290  0.957
+assign  wn_re[721] = 16'hxxxx;   assign  wn_im[721] = 16'hxxxx;   // 721 -0.284  0.959
+assign  wn_re[722] = 16'hxxxx;   assign  wn_im[722] = 16'hxxxx;   // 722 -0.279  0.960
+assign  wn_re[723] = 16'hDD1B;   assign  wn_im[723] = 16'h7B27;   // 723 -0.273  0.962
+assign  wn_re[724] = 16'hxxxx;   assign  wn_im[724] = 16'hxxxx;   // 724 -0.267  0.964
+assign  wn_re[725] = 16'hxxxx;   assign  wn_im[725] = 16'hxxxx;   // 725 -0.261  0.965
+assign  wn_re[726] = 16'hDF61;   assign  wn_im[726] = 16'h7BC6;   // 726 -0.255  0.967
+assign  wn_re[727] = 16'hxxxx;   assign  wn_im[727] = 16'hxxxx;   // 727 -0.249  0.969
+assign  wn_re[728] = 16'hxxxx;   assign  wn_im[728] = 16'hxxxx;   // 728 -0.243  0.970
+assign  wn_re[729] = 16'hE1A9;   assign  wn_im[729] = 16'h7C5A;   // 729 -0.237  0.972
+assign  wn_re[730] = 16'hxxxx;   assign  wn_im[730] = 16'hxxxx;   // 730 -0.231  0.973
+assign  wn_re[731] = 16'hxxxx;   assign  wn_im[731] = 16'hxxxx;   // 731 -0.225  0.974
+assign  wn_re[732] = 16'hE3F4;   assign  wn_im[732] = 16'h7CE4;   // 732 -0.219  0.976
+assign  wn_re[733] = 16'hxxxx;   assign  wn_im[733] = 16'hxxxx;   // 733 -0.213  0.977
+assign  wn_re[734] = 16'hxxxx;   assign  wn_im[734] = 16'hxxxx;   // 734 -0.207  0.978
+assign  wn_re[735] = 16'hE642;   assign  wn_im[735] = 16'h7D63;   // 735 -0.201  0.980
+assign  wn_re[736] = 16'hxxxx;   assign  wn_im[736] = 16'hxxxx;   // 736 -0.195  0.981
+assign  wn_re[737] = 16'hxxxx;   assign  wn_im[737] = 16'hxxxx;   // 737 -0.189  0.982
+assign  wn_re[738] = 16'hE892;   assign  wn_im[738] = 16'h7DD6;   // 738 -0.183  0.983
+assign  wn_re[739] = 16'hxxxx;   assign  wn_im[739] = 16'hxxxx;   // 739 -0.177  0.984
+assign  wn_re[740] = 16'hxxxx;   assign  wn_im[740] = 16'hxxxx;   // 740 -0.171  0.985
+assign  wn_re[741] = 16'hEAE4;   assign  wn_im[741] = 16'h7E3F;   // 741 -0.165  0.986
+assign  wn_re[742] = 16'hxxxx;   assign  wn_im[742] = 16'hxxxx;   // 742 -0.159  0.987
+assign  wn_re[743] = 16'hxxxx;   assign  wn_im[743] = 16'hxxxx;   // 743 -0.153  0.988
+assign  wn_re[744] = 16'hED38;   assign  wn_im[744] = 16'h7E9D;   // 744 -0.147  0.989
+assign  wn_re[745] = 16'hxxxx;   assign  wn_im[745] = 16'hxxxx;   // 745 -0.141  0.990
+assign  wn_re[746] = 16'hxxxx;   assign  wn_im[746] = 16'hxxxx;   // 746 -0.135  0.991
+assign  wn_re[747] = 16'hEF8D;   assign  wn_im[747] = 16'h7EF0;   // 747 -0.128  0.992
+assign  wn_re[748] = 16'hxxxx;   assign  wn_im[748] = 16'hxxxx;   // 748 -0.122  0.992
+assign  wn_re[749] = 16'hxxxx;   assign  wn_im[749] = 16'hxxxx;   // 749 -0.116  0.993
+assign  wn_re[750] = 16'hF1E4;   assign  wn_im[750] = 16'h7F38;   // 750 -0.110  0.994
+assign  wn_re[751] = 16'hxxxx;   assign  wn_im[751] = 16'hxxxx;   // 751 -0.104  0.995
+assign  wn_re[752] = 16'hxxxx;   assign  wn_im[752] = 16'hxxxx;   // 752 -0.098  0.995
+assign  wn_re[753] = 16'hF43C;   assign  wn_im[753] = 16'h7F75;   // 753 -0.092  0.996
+assign  wn_re[754] = 16'hxxxx;   assign  wn_im[754] = 16'hxxxx;   // 754 -0.086  0.996
+assign  wn_re[755] = 16'hxxxx;   assign  wn_im[755] = 16'hxxxx;   // 755 -0.080  0.997
+assign  wn_re[756] = 16'hF695;   assign  wn_im[756] = 16'h7FA7;   // 756 -0.074  0.997
+assign  wn_re[757] = 16'hxxxx;   assign  wn_im[757] = 16'hxxxx;   // 757 -0.067  0.998
+assign  wn_re[758] = 16'hxxxx;   assign  wn_im[758] = 16'hxxxx;   // 758 -0.061  0.998
+assign  wn_re[759] = 16'hF8EF;   assign  wn_im[759] = 16'h7FCE;   // 759 -0.055  0.998
+assign  wn_re[760] = 16'hxxxx;   assign  wn_im[760] = 16'hxxxx;   // 760 -0.049  0.999
+assign  wn_re[761] = 16'hxxxx;   assign  wn_im[761] = 16'hxxxx;   // 761 -0.043  0.999
+assign  wn_re[762] = 16'hFB4A;   assign  wn_im[762] = 16'h7FEA;   // 762 -0.037  0.999
+assign  wn_re[763] = 16'hxxxx;   assign  wn_im[763] = 16'hxxxx;   // 763 -0.031  1.000
+assign  wn_re[764] = 16'hxxxx;   assign  wn_im[764] = 16'hxxxx;   // 764 -0.025  1.000
+assign  wn_re[765] = 16'hFDA5;   assign  wn_im[765] = 16'h7FFA;   // 765 -0.018  1.000
+assign  wn_re[766] = 16'hxxxx;   assign  wn_im[766] = 16'hxxxx;   // 766 -0.012  1.000
+assign  wn_re[767] = 16'hxxxx;   assign  wn_im[767] = 16'hxxxx;   // 767 -0.006  1.000
+assign  wn_re[768] = 16'hxxxx;   assign  wn_im[768] = 16'hxxxx;   // 768 -0.000  1.000
+assign  wn_re[769] = 16'hxxxx;   assign  wn_im[769] = 16'hxxxx;   // 769  0.006  1.000
+assign  wn_re[770] = 16'hxxxx;   assign  wn_im[770] = 16'hxxxx;   // 770  0.012  1.000
+assign  wn_re[771] = 16'hxxxx;   assign  wn_im[771] = 16'hxxxx;   // 771  0.018  1.000
+assign  wn_re[772] = 16'hxxxx;   assign  wn_im[772] = 16'hxxxx;   // 772  0.025  1.000
+assign  wn_re[773] = 16'hxxxx;   assign  wn_im[773] = 16'hxxxx;   // 773  0.031  1.000
+assign  wn_re[774] = 16'hxxxx;   assign  wn_im[774] = 16'hxxxx;   // 774  0.037  0.999
+assign  wn_re[775] = 16'hxxxx;   assign  wn_im[775] = 16'hxxxx;   // 775  0.043  0.999
+assign  wn_re[776] = 16'hxxxx;   assign  wn_im[776] = 16'hxxxx;   // 776  0.049  0.999
+assign  wn_re[777] = 16'hxxxx;   assign  wn_im[777] = 16'hxxxx;   // 777  0.055  0.998
+assign  wn_re[778] = 16'hxxxx;   assign  wn_im[778] = 16'hxxxx;   // 778  0.061  0.998
+assign  wn_re[779] = 16'hxxxx;   assign  wn_im[779] = 16'hxxxx;   // 779  0.067  0.998
+assign  wn_re[780] = 16'hxxxx;   assign  wn_im[780] = 16'hxxxx;   // 780  0.074  0.997
+assign  wn_re[781] = 16'hxxxx;   assign  wn_im[781] = 16'hxxxx;   // 781  0.080  0.997
+assign  wn_re[782] = 16'hxxxx;   assign  wn_im[782] = 16'hxxxx;   // 782  0.086  0.996
+assign  wn_re[783] = 16'hxxxx;   assign  wn_im[783] = 16'hxxxx;   // 783  0.092  0.996
+assign  wn_re[784] = 16'hxxxx;   assign  wn_im[784] = 16'hxxxx;   // 784  0.098  0.995
+assign  wn_re[785] = 16'hxxxx;   assign  wn_im[785] = 16'hxxxx;   // 785  0.104  0.995
+assign  wn_re[786] = 16'hxxxx;   assign  wn_im[786] = 16'hxxxx;   // 786  0.110  0.994
+assign  wn_re[787] = 16'hxxxx;   assign  wn_im[787] = 16'hxxxx;   // 787  0.116  0.993
+assign  wn_re[788] = 16'hxxxx;   assign  wn_im[788] = 16'hxxxx;   // 788  0.122  0.992
+assign  wn_re[789] = 16'hxxxx;   assign  wn_im[789] = 16'hxxxx;   // 789  0.128  0.992
+assign  wn_re[790] = 16'hxxxx;   assign  wn_im[790] = 16'hxxxx;   // 790  0.135  0.991
+assign  wn_re[791] = 16'hxxxx;   assign  wn_im[791] = 16'hxxxx;   // 791  0.141  0.990
+assign  wn_re[792] = 16'hxxxx;   assign  wn_im[792] = 16'hxxxx;   // 792  0.147  0.989
+assign  wn_re[793] = 16'hxxxx;   assign  wn_im[793] = 16'hxxxx;   // 793  0.153  0.988
+assign  wn_re[794] = 16'hxxxx;   assign  wn_im[794] = 16'hxxxx;   // 794  0.159  0.987
+assign  wn_re[795] = 16'hxxxx;   assign  wn_im[795] = 16'hxxxx;   // 795  0.165  0.986
+assign  wn_re[796] = 16'hxxxx;   assign  wn_im[796] = 16'hxxxx;   // 796  0.171  0.985
+assign  wn_re[797] = 16'hxxxx;   assign  wn_im[797] = 16'hxxxx;   // 797  0.177  0.984
+assign  wn_re[798] = 16'hxxxx;   assign  wn_im[798] = 16'hxxxx;   // 798  0.183  0.983
+assign  wn_re[799] = 16'hxxxx;   assign  wn_im[799] = 16'hxxxx;   // 799  0.189  0.982
+assign  wn_re[800] = 16'hxxxx;   assign  wn_im[800] = 16'hxxxx;   // 800  0.195  0.981
+assign  wn_re[801] = 16'hxxxx;   assign  wn_im[801] = 16'hxxxx;   // 801  0.201  0.980
+assign  wn_re[802] = 16'hxxxx;   assign  wn_im[802] = 16'hxxxx;   // 802  0.207  0.978
+assign  wn_re[803] = 16'hxxxx;   assign  wn_im[803] = 16'hxxxx;   // 803  0.213  0.977
+assign  wn_re[804] = 16'hxxxx;   assign  wn_im[804] = 16'hxxxx;   // 804  0.219  0.976
+assign  wn_re[805] = 16'hxxxx;   assign  wn_im[805] = 16'hxxxx;   // 805  0.225  0.974
+assign  wn_re[806] = 16'hxxxx;   assign  wn_im[806] = 16'hxxxx;   // 806  0.231  0.973
+assign  wn_re[807] = 16'hxxxx;   assign  wn_im[807] = 16'hxxxx;   // 807  0.237  0.972
+assign  wn_re[808] = 16'hxxxx;   assign  wn_im[808] = 16'hxxxx;   // 808  0.243  0.970
+assign  wn_re[809] = 16'hxxxx;   assign  wn_im[809] = 16'hxxxx;   // 809  0.249  0.969
+assign  wn_re[810] = 16'hxxxx;   assign  wn_im[810] = 16'hxxxx;   // 810  0.255  0.967
+assign  wn_re[811] = 16'hxxxx;   assign  wn_im[811] = 16'hxxxx;   // 811  0.261  0.965
+assign  wn_re[812] = 16'hxxxx;   assign  wn_im[812] = 16'hxxxx;   // 812  0.267  0.964
+assign  wn_re[813] = 16'hxxxx;   assign  wn_im[813] = 16'hxxxx;   // 813  0.273  0.962
+assign  wn_re[814] = 16'hxxxx;   assign  wn_im[814] = 16'hxxxx;   // 814  0.279  0.960
+assign  wn_re[815] = 16'hxxxx;   assign  wn_im[815] = 16'hxxxx;   // 815  0.284  0.959
+assign  wn_re[816] = 16'hxxxx;   assign  wn_im[816] = 16'hxxxx;   // 816  0.290  0.957
+assign  wn_re[817] = 16'hxxxx;   assign  wn_im[817] = 16'hxxxx;   // 817  0.296  0.955
+assign  wn_re[818] = 16'hxxxx;   assign  wn_im[818] = 16'hxxxx;   // 818  0.302  0.953
+assign  wn_re[819] = 16'hxxxx;   assign  wn_im[819] = 16'hxxxx;   // 819  0.308  0.951
+assign  wn_re[820] = 16'hxxxx;   assign  wn_im[820] = 16'hxxxx;   // 820  0.314  0.950
+assign  wn_re[821] = 16'hxxxx;   assign  wn_im[821] = 16'hxxxx;   // 821  0.320  0.948
+assign  wn_re[822] = 16'hxxxx;   assign  wn_im[822] = 16'hxxxx;   // 822  0.325  0.946
+assign  wn_re[823] = 16'hxxxx;   assign  wn_im[823] = 16'hxxxx;   // 823  0.331  0.944
+assign  wn_re[824] = 16'hxxxx;   assign  wn_im[824] = 16'hxxxx;   // 824  0.337  0.942
+assign  wn_re[825] = 16'hxxxx;   assign  wn_im[825] = 16'hxxxx;   // 825  0.343  0.939
+assign  wn_re[826] = 16'hxxxx;   assign  wn_im[826] = 16'hxxxx;   // 826  0.348  0.937
+assign  wn_re[827] = 16'hxxxx;   assign  wn_im[827] = 16'hxxxx;   // 827  0.354  0.935
+assign  wn_re[828] = 16'hxxxx;   assign  wn_im[828] = 16'hxxxx;   // 828  0.360  0.933
+assign  wn_re[829] = 16'hxxxx;   assign  wn_im[829] = 16'hxxxx;   // 829  0.366  0.931
+assign  wn_re[830] = 16'hxxxx;   assign  wn_im[830] = 16'hxxxx;   // 830  0.371  0.929
+assign  wn_re[831] = 16'hxxxx;   assign  wn_im[831] = 16'hxxxx;   // 831  0.377  0.926
+assign  wn_re[832] = 16'hxxxx;   assign  wn_im[832] = 16'hxxxx;   // 832  0.383  0.924
+assign  wn_re[833] = 16'hxxxx;   assign  wn_im[833] = 16'hxxxx;   // 833  0.388  0.922
+assign  wn_re[834] = 16'hxxxx;   assign  wn_im[834] = 16'hxxxx;   // 834  0.394  0.919
+assign  wn_re[835] = 16'hxxxx;   assign  wn_im[835] = 16'hxxxx;   // 835  0.400  0.917
+assign  wn_re[836] = 16'hxxxx;   assign  wn_im[836] = 16'hxxxx;   // 836  0.405  0.914
+assign  wn_re[837] = 16'hxxxx;   assign  wn_im[837] = 16'hxxxx;   // 837  0.411  0.912
+assign  wn_re[838] = 16'hxxxx;   assign  wn_im[838] = 16'hxxxx;   // 838  0.416  0.909
+assign  wn_re[839] = 16'hxxxx;   assign  wn_im[839] = 16'hxxxx;   // 839  0.422  0.907
+assign  wn_re[840] = 16'hxxxx;   assign  wn_im[840] = 16'hxxxx;   // 840  0.428  0.904
+assign  wn_re[841] = 16'hxxxx;   assign  wn_im[841] = 16'hxxxx;   // 841  0.433  0.901
+assign  wn_re[842] = 16'hxxxx;   assign  wn_im[842] = 16'hxxxx;   // 842  0.439  0.899
+assign  wn_re[843] = 16'hxxxx;   assign  wn_im[843] = 16'hxxxx;   // 843  0.444  0.896
+assign  wn_re[844] = 16'hxxxx;   assign  wn_im[844] = 16'hxxxx;   // 844  0.450  0.893
+assign  wn_re[845] = 16'hxxxx;   assign  wn_im[845] = 16'hxxxx;   // 845  0.455  0.890
+assign  wn_re[846] = 16'hxxxx;   assign  wn_im[846] = 16'hxxxx;   // 846  0.461  0.888
+assign  wn_re[847] = 16'hxxxx;   assign  wn_im[847] = 16'hxxxx;   // 847  0.466  0.885
+assign  wn_re[848] = 16'hxxxx;   assign  wn_im[848] = 16'hxxxx;   // 848  0.471  0.882
+assign  wn_re[849] = 16'hxxxx;   assign  wn_im[849] = 16'hxxxx;   // 849  0.477  0.879
+assign  wn_re[850] = 16'hxxxx;   assign  wn_im[850] = 16'hxxxx;   // 850  0.482  0.876
+assign  wn_re[851] = 16'hxxxx;   assign  wn_im[851] = 16'hxxxx;   // 851  0.488  0.873
+assign  wn_re[852] = 16'hxxxx;   assign  wn_im[852] = 16'hxxxx;   // 852  0.493  0.870
+assign  wn_re[853] = 16'hxxxx;   assign  wn_im[853] = 16'hxxxx;   // 853  0.498  0.867
+assign  wn_re[854] = 16'hxxxx;   assign  wn_im[854] = 16'hxxxx;   // 854  0.504  0.864
+assign  wn_re[855] = 16'hxxxx;   assign  wn_im[855] = 16'hxxxx;   // 855  0.509  0.861
+assign  wn_re[856] = 16'hxxxx;   assign  wn_im[856] = 16'hxxxx;   // 856  0.514  0.858
+assign  wn_re[857] = 16'hxxxx;   assign  wn_im[857] = 16'hxxxx;   // 857  0.519  0.855
+assign  wn_re[858] = 16'hxxxx;   assign  wn_im[858] = 16'hxxxx;   // 858  0.525  0.851
+assign  wn_re[859] = 16'hxxxx;   assign  wn_im[859] = 16'hxxxx;   // 859  0.530  0.848
+assign  wn_re[860] = 16'hxxxx;   assign  wn_im[860] = 16'hxxxx;   // 860  0.535  0.845
+assign  wn_re[861] = 16'hxxxx;   assign  wn_im[861] = 16'hxxxx;   // 861  0.540  0.842
+assign  wn_re[862] = 16'hxxxx;   assign  wn_im[862] = 16'hxxxx;   // 862  0.545  0.838
+assign  wn_re[863] = 16'hxxxx;   assign  wn_im[863] = 16'hxxxx;   // 863  0.550  0.835
+assign  wn_re[864] = 16'hxxxx;   assign  wn_im[864] = 16'hxxxx;   // 864  0.556  0.831
+assign  wn_re[865] = 16'hxxxx;   assign  wn_im[865] = 16'hxxxx;   // 865  0.561  0.828
+assign  wn_re[866] = 16'hxxxx;   assign  wn_im[866] = 16'hxxxx;   // 866  0.566  0.825
+assign  wn_re[867] = 16'hxxxx;   assign  wn_im[867] = 16'hxxxx;   // 867  0.571  0.821
+assign  wn_re[868] = 16'hxxxx;   assign  wn_im[868] = 16'hxxxx;   // 868  0.576  0.818
+assign  wn_re[869] = 16'hxxxx;   assign  wn_im[869] = 16'hxxxx;   // 869  0.581  0.814
+assign  wn_re[870] = 16'hxxxx;   assign  wn_im[870] = 16'hxxxx;   // 870  0.586  0.810
+assign  wn_re[871] = 16'hxxxx;   assign  wn_im[871] = 16'hxxxx;   // 871  0.591  0.807
+assign  wn_re[872] = 16'hxxxx;   assign  wn_im[872] = 16'hxxxx;   // 872  0.596  0.803
+assign  wn_re[873] = 16'hxxxx;   assign  wn_im[873] = 16'hxxxx;   // 873  0.601  0.800
+assign  wn_re[874] = 16'hxxxx;   assign  wn_im[874] = 16'hxxxx;   // 874  0.606  0.796
+assign  wn_re[875] = 16'hxxxx;   assign  wn_im[875] = 16'hxxxx;   // 875  0.610  0.792
+assign  wn_re[876] = 16'hxxxx;   assign  wn_im[876] = 16'hxxxx;   // 876  0.615  0.788
+assign  wn_re[877] = 16'hxxxx;   assign  wn_im[877] = 16'hxxxx;   // 877  0.620  0.785
+assign  wn_re[878] = 16'hxxxx;   assign  wn_im[878] = 16'hxxxx;   // 878  0.625  0.781
+assign  wn_re[879] = 16'hxxxx;   assign  wn_im[879] = 16'hxxxx;   // 879  0.630  0.777
+assign  wn_re[880] = 16'hxxxx;   assign  wn_im[880] = 16'hxxxx;   // 880  0.634  0.773
+assign  wn_re[881] = 16'hxxxx;   assign  wn_im[881] = 16'hxxxx;   // 881  0.639  0.769
+assign  wn_re[882] = 16'hxxxx;   assign  wn_im[882] = 16'hxxxx;   // 882  0.644  0.765
+assign  wn_re[883] = 16'hxxxx;   assign  wn_im[883] = 16'hxxxx;   // 883  0.649  0.761
+assign  wn_re[884] = 16'hxxxx;   assign  wn_im[884] = 16'hxxxx;   // 884  0.653  0.757
+assign  wn_re[885] = 16'hxxxx;   assign  wn_im[885] = 16'hxxxx;   // 885  0.658  0.753
+assign  wn_re[886] = 16'hxxxx;   assign  wn_im[886] = 16'hxxxx;   // 886  0.662  0.749
+assign  wn_re[887] = 16'hxxxx;   assign  wn_im[887] = 16'hxxxx;   // 887  0.667  0.745
+assign  wn_re[888] = 16'hxxxx;   assign  wn_im[888] = 16'hxxxx;   // 888  0.672  0.741
+assign  wn_re[889] = 16'hxxxx;   assign  wn_im[889] = 16'hxxxx;   // 889  0.676  0.737
+assign  wn_re[890] = 16'hxxxx;   assign  wn_im[890] = 16'hxxxx;   // 890  0.681  0.733
+assign  wn_re[891] = 16'hxxxx;   assign  wn_im[891] = 16'hxxxx;   // 891  0.685  0.728
+assign  wn_re[892] = 16'hxxxx;   assign  wn_im[892] = 16'hxxxx;   // 892  0.690  0.724
+assign  wn_re[893] = 16'hxxxx;   assign  wn_im[893] = 16'hxxxx;   // 893  0.694  0.720
+assign  wn_re[894] = 16'hxxxx;   assign  wn_im[894] = 16'hxxxx;   // 894  0.698  0.716
+assign  wn_re[895] = 16'hxxxx;   assign  wn_im[895] = 16'hxxxx;   // 895  0.703  0.711
+assign  wn_re[896] = 16'hxxxx;   assign  wn_im[896] = 16'hxxxx;   // 896  0.707  0.707
+assign  wn_re[897] = 16'hxxxx;   assign  wn_im[897] = 16'hxxxx;   // 897  0.711  0.703
+assign  wn_re[898] = 16'hxxxx;   assign  wn_im[898] = 16'hxxxx;   // 898  0.716  0.698
+assign  wn_re[899] = 16'hxxxx;   assign  wn_im[899] = 16'hxxxx;   // 899  0.720  0.694
+assign  wn_re[900] = 16'hxxxx;   assign  wn_im[900] = 16'hxxxx;   // 900  0.724  0.690
+assign  wn_re[901] = 16'hxxxx;   assign  wn_im[901] = 16'hxxxx;   // 901  0.728  0.685
+assign  wn_re[902] = 16'hxxxx;   assign  wn_im[902] = 16'hxxxx;   // 902  0.733  0.681
+assign  wn_re[903] = 16'hxxxx;   assign  wn_im[903] = 16'hxxxx;   // 903  0.737  0.676
+assign  wn_re[904] = 16'hxxxx;   assign  wn_im[904] = 16'hxxxx;   // 904  0.741  0.672
+assign  wn_re[905] = 16'hxxxx;   assign  wn_im[905] = 16'hxxxx;   // 905  0.745  0.667
+assign  wn_re[906] = 16'hxxxx;   assign  wn_im[906] = 16'hxxxx;   // 906  0.749  0.662
+assign  wn_re[907] = 16'hxxxx;   assign  wn_im[907] = 16'hxxxx;   // 907  0.753  0.658
+assign  wn_re[908] = 16'hxxxx;   assign  wn_im[908] = 16'hxxxx;   // 908  0.757  0.653
+assign  wn_re[909] = 16'hxxxx;   assign  wn_im[909] = 16'hxxxx;   // 909  0.761  0.649
+assign  wn_re[910] = 16'hxxxx;   assign  wn_im[910] = 16'hxxxx;   // 910  0.765  0.644
+assign  wn_re[911] = 16'hxxxx;   assign  wn_im[911] = 16'hxxxx;   // 911  0.769  0.639
+assign  wn_re[912] = 16'hxxxx;   assign  wn_im[912] = 16'hxxxx;   // 912  0.773  0.634
+assign  wn_re[913] = 16'hxxxx;   assign  wn_im[913] = 16'hxxxx;   // 913  0.777  0.630
+assign  wn_re[914] = 16'hxxxx;   assign  wn_im[914] = 16'hxxxx;   // 914  0.781  0.625
+assign  wn_re[915] = 16'hxxxx;   assign  wn_im[915] = 16'hxxxx;   // 915  0.785  0.620
+assign  wn_re[916] = 16'hxxxx;   assign  wn_im[916] = 16'hxxxx;   // 916  0.788  0.615
+assign  wn_re[917] = 16'hxxxx;   assign  wn_im[917] = 16'hxxxx;   // 917  0.792  0.610
+assign  wn_re[918] = 16'hxxxx;   assign  wn_im[918] = 16'hxxxx;   // 918  0.796  0.606
+assign  wn_re[919] = 16'hxxxx;   assign  wn_im[919] = 16'hxxxx;   // 919  0.800  0.601
+assign  wn_re[920] = 16'hxxxx;   assign  wn_im[920] = 16'hxxxx;   // 920  0.803  0.596
+assign  wn_re[921] = 16'hxxxx;   assign  wn_im[921] = 16'hxxxx;   // 921  0.807  0.591
+assign  wn_re[922] = 16'hxxxx;   assign  wn_im[922] = 16'hxxxx;   // 922  0.810  0.586
+assign  wn_re[923] = 16'hxxxx;   assign  wn_im[923] = 16'hxxxx;   // 923  0.814  0.581
+assign  wn_re[924] = 16'hxxxx;   assign  wn_im[924] = 16'hxxxx;   // 924  0.818  0.576
+assign  wn_re[925] = 16'hxxxx;   assign  wn_im[925] = 16'hxxxx;   // 925  0.821  0.571
+assign  wn_re[926] = 16'hxxxx;   assign  wn_im[926] = 16'hxxxx;   // 926  0.825  0.566
+assign  wn_re[927] = 16'hxxxx;   assign  wn_im[927] = 16'hxxxx;   // 927  0.828  0.561
+assign  wn_re[928] = 16'hxxxx;   assign  wn_im[928] = 16'hxxxx;   // 928  0.831  0.556
+assign  wn_re[929] = 16'hxxxx;   assign  wn_im[929] = 16'hxxxx;   // 929  0.835  0.550
+assign  wn_re[930] = 16'hxxxx;   assign  wn_im[930] = 16'hxxxx;   // 930  0.838  0.545
+assign  wn_re[931] = 16'hxxxx;   assign  wn_im[931] = 16'hxxxx;   // 931  0.842  0.540
+assign  wn_re[932] = 16'hxxxx;   assign  wn_im[932] = 16'hxxxx;   // 932  0.845  0.535
+assign  wn_re[933] = 16'hxxxx;   assign  wn_im[933] = 16'hxxxx;   // 933  0.848  0.530
+assign  wn_re[934] = 16'hxxxx;   assign  wn_im[934] = 16'hxxxx;   // 934  0.851  0.525
+assign  wn_re[935] = 16'hxxxx;   assign  wn_im[935] = 16'hxxxx;   // 935  0.855  0.519
+assign  wn_re[936] = 16'hxxxx;   assign  wn_im[936] = 16'hxxxx;   // 936  0.858  0.514
+assign  wn_re[937] = 16'hxxxx;   assign  wn_im[937] = 16'hxxxx;   // 937  0.861  0.509
+assign  wn_re[938] = 16'hxxxx;   assign  wn_im[938] = 16'hxxxx;   // 938  0.864  0.504
+assign  wn_re[939] = 16'hxxxx;   assign  wn_im[939] = 16'hxxxx;   // 939  0.867  0.498
+assign  wn_re[940] = 16'hxxxx;   assign  wn_im[940] = 16'hxxxx;   // 940  0.870  0.493
+assign  wn_re[941] = 16'hxxxx;   assign  wn_im[941] = 16'hxxxx;   // 941  0.873  0.488
+assign  wn_re[942] = 16'hxxxx;   assign  wn_im[942] = 16'hxxxx;   // 942  0.876  0.482
+assign  wn_re[943] = 16'hxxxx;   assign  wn_im[943] = 16'hxxxx;   // 943  0.879  0.477
+assign  wn_re[944] = 16'hxxxx;   assign  wn_im[944] = 16'hxxxx;   // 944  0.882  0.471
+assign  wn_re[945] = 16'hxxxx;   assign  wn_im[945] = 16'hxxxx;   // 945  0.885  0.466
+assign  wn_re[946] = 16'hxxxx;   assign  wn_im[946] = 16'hxxxx;   // 946  0.888  0.461
+assign  wn_re[947] = 16'hxxxx;   assign  wn_im[947] = 16'hxxxx;   // 947  0.890  0.455
+assign  wn_re[948] = 16'hxxxx;   assign  wn_im[948] = 16'hxxxx;   // 948  0.893  0.450
+assign  wn_re[949] = 16'hxxxx;   assign  wn_im[949] = 16'hxxxx;   // 949  0.896  0.444
+assign  wn_re[950] = 16'hxxxx;   assign  wn_im[950] = 16'hxxxx;   // 950  0.899  0.439
+assign  wn_re[951] = 16'hxxxx;   assign  wn_im[951] = 16'hxxxx;   // 951  0.901  0.433
+assign  wn_re[952] = 16'hxxxx;   assign  wn_im[952] = 16'hxxxx;   // 952  0.904  0.428
+assign  wn_re[953] = 16'hxxxx;   assign  wn_im[953] = 16'hxxxx;   // 953  0.907  0.422
+assign  wn_re[954] = 16'hxxxx;   assign  wn_im[954] = 16'hxxxx;   // 954  0.909  0.416
+assign  wn_re[955] = 16'hxxxx;   assign  wn_im[955] = 16'hxxxx;   // 955  0.912  0.411
+assign  wn_re[956] = 16'hxxxx;   assign  wn_im[956] = 16'hxxxx;   // 956  0.914  0.405
+assign  wn_re[957] = 16'hxxxx;   assign  wn_im[957] = 16'hxxxx;   // 957  0.917  0.400
+assign  wn_re[958] = 16'hxxxx;   assign  wn_im[958] = 16'hxxxx;   // 958  0.919  0.394
+assign  wn_re[959] = 16'hxxxx;   assign  wn_im[959] = 16'hxxxx;   // 959  0.922  0.388
+assign  wn_re[960] = 16'hxxxx;   assign  wn_im[960] = 16'hxxxx;   // 960  0.924  0.383
+assign  wn_re[961] = 16'hxxxx;   assign  wn_im[961] = 16'hxxxx;   // 961  0.926  0.377
+assign  wn_re[962] = 16'hxxxx;   assign  wn_im[962] = 16'hxxxx;   // 962  0.929  0.371
+assign  wn_re[963] = 16'hxxxx;   assign  wn_im[963] = 16'hxxxx;   // 963  0.931  0.366
+assign  wn_re[964] = 16'hxxxx;   assign  wn_im[964] = 16'hxxxx;   // 964  0.933  0.360
+assign  wn_re[965] = 16'hxxxx;   assign  wn_im[965] = 16'hxxxx;   // 965  0.935  0.354
+assign  wn_re[966] = 16'hxxxx;   assign  wn_im[966] = 16'hxxxx;   // 966  0.937  0.348
+assign  wn_re[967] = 16'hxxxx;   assign  wn_im[967] = 16'hxxxx;   // 967  0.939  0.343
+assign  wn_re[968] = 16'hxxxx;   assign  wn_im[968] = 16'hxxxx;   // 968  0.942  0.337
+assign  wn_re[969] = 16'hxxxx;   assign  wn_im[969] = 16'hxxxx;   // 969  0.944  0.331
+assign  wn_re[970] = 16'hxxxx;   assign  wn_im[970] = 16'hxxxx;   // 970  0.946  0.325
+assign  wn_re[971] = 16'hxxxx;   assign  wn_im[971] = 16'hxxxx;   // 971  0.948  0.320
+assign  wn_re[972] = 16'hxxxx;   assign  wn_im[972] = 16'hxxxx;   // 972  0.950  0.314
+assign  wn_re[973] = 16'hxxxx;   assign  wn_im[973] = 16'hxxxx;   // 973  0.951  0.308
+assign  wn_re[974] = 16'hxxxx;   assign  wn_im[974] = 16'hxxxx;   // 974  0.953  0.302
+assign  wn_re[975] = 16'hxxxx;   assign  wn_im[975] = 16'hxxxx;   // 975  0.955  0.296
+assign  wn_re[976] = 16'hxxxx;   assign  wn_im[976] = 16'hxxxx;   // 976  0.957  0.290
+assign  wn_re[977] = 16'hxxxx;   assign  wn_im[977] = 16'hxxxx;   // 977  0.959  0.284
+assign  wn_re[978] = 16'hxxxx;   assign  wn_im[978] = 16'hxxxx;   // 978  0.960  0.279
+assign  wn_re[979] = 16'hxxxx;   assign  wn_im[979] = 16'hxxxx;   // 979  0.962  0.273
+assign  wn_re[980] = 16'hxxxx;   assign  wn_im[980] = 16'hxxxx;   // 980  0.964  0.267
+assign  wn_re[981] = 16'hxxxx;   assign  wn_im[981] = 16'hxxxx;   // 981  0.965  0.261
+assign  wn_re[982] = 16'hxxxx;   assign  wn_im[982] = 16'hxxxx;   // 982  0.967  0.255
+assign  wn_re[983] = 16'hxxxx;   assign  wn_im[983] = 16'hxxxx;   // 983  0.969  0.249
+assign  wn_re[984] = 16'hxxxx;   assign  wn_im[984] = 16'hxxxx;   // 984  0.970  0.243
+assign  wn_re[985] = 16'hxxxx;   assign  wn_im[985] = 16'hxxxx;   // 985  0.972  0.237
+assign  wn_re[986] = 16'hxxxx;   assign  wn_im[986] = 16'hxxxx;   // 986  0.973  0.231
+assign  wn_re[987] = 16'hxxxx;   assign  wn_im[987] = 16'hxxxx;   // 987  0.974  0.225
+assign  wn_re[988] = 16'hxxxx;   assign  wn_im[988] = 16'hxxxx;   // 988  0.976  0.219
+assign  wn_re[989] = 16'hxxxx;   assign  wn_im[989] = 16'hxxxx;   // 989  0.977  0.213
+assign  wn_re[990] = 16'hxxxx;   assign  wn_im[990] = 16'hxxxx;   // 990  0.978  0.207
+assign  wn_re[991] = 16'hxxxx;   assign  wn_im[991] = 16'hxxxx;   // 991  0.980  0.201
+assign  wn_re[992] = 16'hxxxx;   assign  wn_im[992] = 16'hxxxx;   // 992  0.981  0.195
+assign  wn_re[993] = 16'hxxxx;   assign  wn_im[993] = 16'hxxxx;   // 993  0.982  0.189
+assign  wn_re[994] = 16'hxxxx;   assign  wn_im[994] = 16'hxxxx;   // 994  0.983  0.183
+assign  wn_re[995] = 16'hxxxx;   assign  wn_im[995] = 16'hxxxx;   // 995  0.984  0.177
+assign  wn_re[996] = 16'hxxxx;   assign  wn_im[996] = 16'hxxxx;   // 996  0.985  0.171
+assign  wn_re[997] = 16'hxxxx;   assign  wn_im[997] = 16'hxxxx;   // 997  0.986  0.165
+assign  wn_re[998] = 16'hxxxx;   assign  wn_im[998] = 16'hxxxx;   // 998  0.987  0.159
+assign  wn_re[999] = 16'hxxxx;   assign  wn_im[999] = 16'hxxxx;   // 999  0.988  0.153
+assign  wn_re[1000] = 16'hxxxx;   assign  wn_im[1000] = 16'hxxxx;   // 1000  0.989  0.147
+assign  wn_re[1001] = 16'hxxxx;   assign  wn_im[1001] = 16'hxxxx;   // 1001  0.990  0.141
+assign  wn_re[1002] = 16'hxxxx;   assign  wn_im[1002] = 16'hxxxx;   // 1002  0.991  0.135
+assign  wn_re[1003] = 16'hxxxx;   assign  wn_im[1003] = 16'hxxxx;   // 1003  0.992  0.128
+assign  wn_re[1004] = 16'hxxxx;   assign  wn_im[1004] = 16'hxxxx;   // 1004  0.992  0.122
+assign  wn_re[1005] = 16'hxxxx;   assign  wn_im[1005] = 16'hxxxx;   // 1005  0.993  0.116
+assign  wn_re[1006] = 16'hxxxx;   assign  wn_im[1006] = 16'hxxxx;   // 1006  0.994  0.110
+assign  wn_re[1007] = 16'hxxxx;   assign  wn_im[1007] = 16'hxxxx;   // 1007  0.995  0.104
+assign  wn_re[1008] = 16'hxxxx;   assign  wn_im[1008] = 16'hxxxx;   // 1008  0.995  0.098
+assign  wn_re[1009] = 16'hxxxx;   assign  wn_im[1009] = 16'hxxxx;   // 1009  0.996  0.092
+assign  wn_re[1010] = 16'hxxxx;   assign  wn_im[1010] = 16'hxxxx;   // 1010  0.996  0.086
+assign  wn_re[1011] = 16'hxxxx;   assign  wn_im[1011] = 16'hxxxx;   // 1011  0.997  0.080
+assign  wn_re[1012] = 16'hxxxx;   assign  wn_im[1012] = 16'hxxxx;   // 1012  0.997  0.074
+assign  wn_re[1013] = 16'hxxxx;   assign  wn_im[1013] = 16'hxxxx;   // 1013  0.998  0.067
+assign  wn_re[1014] = 16'hxxxx;   assign  wn_im[1014] = 16'hxxxx;   // 1014  0.998  0.061
+assign  wn_re[1015] = 16'hxxxx;   assign  wn_im[1015] = 16'hxxxx;   // 1015  0.998  0.055
+assign  wn_re[1016] = 16'hxxxx;   assign  wn_im[1016] = 16'hxxxx;   // 1016  0.999  0.049
+assign  wn_re[1017] = 16'hxxxx;   assign  wn_im[1017] = 16'hxxxx;   // 1017  0.999  0.043
+assign  wn_re[1018] = 16'hxxxx;   assign  wn_im[1018] = 16'hxxxx;   // 1018  0.999  0.037
+assign  wn_re[1019] = 16'hxxxx;   assign  wn_im[1019] = 16'hxxxx;   // 1019  1.000  0.031
+assign  wn_re[1020] = 16'hxxxx;   assign  wn_im[1020] = 16'hxxxx;   // 1020  1.000  0.025
+assign  wn_re[1021] = 16'hxxxx;   assign  wn_im[1021] = 16'hxxxx;   // 1021  1.000  0.018
+assign  wn_re[1022] = 16'hxxxx;   assign  wn_im[1022] = 16'hxxxx;   // 1022  1.000  0.012
+assign  wn_re[1023] = 16'hxxxx;   assign  wn_im[1023] = 16'hxxxx;   // 1023  1.000  0.006
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert4.v b/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert4.v
new file mode 100644
index 0000000..d93502f
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert4.v
@@ -0,0 +1,61 @@
+//----------------------------------------------------------------------
+//  TwiddleConvert4: Convert Twiddle Value to Reduce Table Size to 1/4
+//----------------------------------------------------------------------
+module TwiddleConvert4 #(
+    parameter   LOG_N = 6,      //  Address Bit Length
+    parameter   WIDTH = 16,     //  Data Bit Length
+    parameter   TW_FF = 1,      //  Use Twiddle Output Register
+    parameter   TC_FF = 1       //  Use Output Register
+)(
+    input               clock,      //  Master Clock
+    input   [LOG_N-1:0] tw_addr,    //  Twiddle Number
+    input   [WIDTH-1:0] tw_re,      //  Twiddle Value (Real)
+    input   [WIDTH-1:0] tw_im,      //  Twiddle Value (Imag)
+    output  [LOG_N-1:0] tc_addr,    //  Converted Twiddle Number
+    output  [WIDTH-1:0] tc_re,      //  Converted Twiddle Value (Real)
+    output  [WIDTH-1:0] tc_im       //  Converted Twiddle Value (Imag)
+);
+
+//  Internal Nets
+reg [LOG_N-1:0] ff_addr;
+wire[LOG_N-1:0] sel_addr;
+reg [WIDTH-1:0] mx_re;
+reg [WIDTH-1:0] mx_im;
+reg [WIDTH-1:0] ff_re;
+reg [WIDTH-1:0] ff_im;
+
+//  Convert Twiddle Number
+assign  tc_addr[LOG_N-1:LOG_N-2] = 2'd0;
+assign  tc_addr[LOG_N-3:0] = tw_addr[LOG_N-3:0];
+
+//  Convert Twiddle Value
+always @(posedge clock) begin
+    ff_addr <= tw_addr;
+end
+assign  sel_addr = TW_FF ? ff_addr : tw_addr;
+
+always @* begin
+    if (sel_addr[LOG_N-3:0] == {LOG_N-2{1'b0}}) begin
+        case (sel_addr[LOG_N-1:LOG_N-2])
+        2'd0    : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
+        2'd1    : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {1'b1,{WIDTH-1{1'b0}}}};
+        default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
+        endcase
+    end else begin
+        case (sel_addr[LOG_N-1:LOG_N-2])
+        2'd0    : {mx_re, mx_im} <= { tw_re,  tw_im};
+        2'd1    : {mx_re, mx_im} <= { tw_im, -tw_re};
+        2'd2    : {mx_re, mx_im} <= {-tw_re, -tw_im};
+        default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
+        endcase
+    end
+end
+always @(posedge clock) begin
+    ff_re <= mx_re;
+    ff_im <= mx_im;
+end
+
+assign  tc_re = TC_FF ? ff_re : mx_re;
+assign  tc_im = TC_FF ? ff_im : mx_im;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert8.v b/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert8.v
new file mode 100644
index 0000000..801be86
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/TwiddleConvert8.v
@@ -0,0 +1,70 @@
+//----------------------------------------------------------------------
+//  TwiddleConvert8: Convert Twiddle Value to Reduce Table Size to 1/8
+//----------------------------------------------------------------------
+module TwiddleConvert8 #(
+    parameter   LOG_N = 6,      //  Address Bit Length
+    parameter   WIDTH = 16,     //  Data Bit Length
+    parameter   TW_FF = 1,      //  Use Twiddle Output Register
+    parameter   TC_FF = 1       //  Use Output Register
+)(
+    input               clock,      //  Master Clock
+    input   [LOG_N-1:0] tw_addr,    //  Twiddle Number
+    input   [WIDTH-1:0] tw_re,      //  Twiddle Value (Real)
+    input   [WIDTH-1:0] tw_im,      //  Twiddle Value (Imag)
+    output  [LOG_N-1:0] tc_addr,    //  Converted Twiddle Number
+    output  [WIDTH-1:0] tc_re,      //  Converted Twiddle Value (Real)
+    output  [WIDTH-1:0] tc_im       //  Converted Twiddle Value (Imag)
+);
+
+//  Define Constants
+localparam[WIDTH-1:0] COSMQ = (((32'h5A82799A<<1) >> (32-WIDTH)) + 1)>>1; // cos(-pi/4)
+localparam[WIDTH-1:0] SINMH = 32'h80000000 >> (32-WIDTH); // sin(-pi/2)
+
+//  Internal Nets
+reg [LOG_N-1:0] ff_addr;
+wire[LOG_N-1:0] sel_addr;
+reg [WIDTH-1:0] mx_re;
+reg [WIDTH-1:0] mx_im;
+reg [WIDTH-1:0] ff_re;
+reg [WIDTH-1:0] ff_im;
+
+//  Convert Twiddle Number
+assign  tc_addr[LOG_N-1:LOG_N-3] = 3'd0;
+assign  tc_addr[LOG_N-4:0] = tw_addr[LOG_N-3] ? -tw_addr[LOG_N-4:0] : tw_addr[LOG_N-4:0];
+
+//  Convert Twiddle Value
+always @(posedge clock) begin
+    ff_addr <= tw_addr;
+end
+assign  sel_addr = TW_FF ? ff_addr : tw_addr;
+
+always @* begin
+    if (sel_addr[LOG_N-4:0] == {LOG_N-3{1'b0}}) begin
+        case (sel_addr[LOG_N-1:LOG_N-3])
+        3'd0    : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
+        3'd1    : {mx_re, mx_im} <= { COSMQ       , -COSMQ       };
+        3'd2    : {mx_re, mx_im} <= {{WIDTH{1'b0}},  SINMH       };
+        3'd3    : {mx_re, mx_im} <= {-COSMQ       , -COSMQ       };
+        default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
+        endcase
+    end else begin
+        case (sel_addr[LOG_N-1:LOG_N-3])
+        3'd0    : {mx_re, mx_im} <= { tw_re,  tw_im};
+        3'd1    : {mx_re, mx_im} <= {-tw_im, -tw_re};
+        3'd2    : {mx_re, mx_im} <= { tw_im, -tw_re};
+        3'd3    : {mx_re, mx_im} <= {-tw_re,  tw_im};
+        3'd4    : {mx_re, mx_im} <= {-tw_re, -tw_im};
+        3'd5    : {mx_re, mx_im} <= { tw_im,  tw_re};
+        default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
+        endcase
+    end
+end
+always @(posedge clock) begin
+    ff_re <= mx_re;
+    ff_im <= mx_im;
+end
+
+assign  tc_re = TC_FF ? ff_re : mx_re;
+assign  tc_im = TC_FF ? ff_im : mx_im;
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/r22sdf/twiddle_gen.pl b/src/5_Blur_Integration/FFT_files/r22sdf/twiddle_gen.pl
new file mode 100644
index 0000000..ee33c45
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/r22sdf/twiddle_gen.pl
@@ -0,0 +1,44 @@
+#!/usr/bin/perl
+
+use strict;
+use warnings;
+use POSIX 'floor';
+
+my $pi = atan2(1, 1) * 4;
+
+my $N = 1024;	# Number of FFT Points
+my $NB = 32;	# Number of Twiddle Data Bits
+
+my $ND = int(log(2**($NB-1))/log(10)) + 2;	# Number of Decimal Digits
+my $NX = int(($NB + 3) / 4);	# Number of Hexadecimal Digits
+
+my $XX = "x" x $NX;	# Hexadecimal Unknown Value String
+
+printf("//      wn_re = cos(-2pi*n/%2d)  ", $N);
+printf("        wn_im = sin(-2pi*n/%2d)\n", $N);
+
+for (my $n = 0; $n < $N; ++$n) {
+	my $wr = cos(-2 * $pi * $n / $N);
+	my $wi = sin(-2 * $pi * $n / $N);
+
+	my $wr_d = floor($wr * 2**($NB-1) + 0.5);	$wr_d -= 1 if ($wr_d == 2**($NB-1));
+	my $wi_d = floor($wi * 2**($NB-1) + 0.5);	$wi_d -= 1 if ($wi_d == 2**($NB-1));
+	my $wr_u = ($wr_d < 0) ? ($wr_d + 2**$NB) : $wr_d;
+	my $wi_u = ($wi_d < 0) ? ($wi_d + 2**$NB) : $wi_d;
+
+#	printf("%${ND}d  %${ND}d  ", $wr_d, $wi_d);
+#	printf("%0${NB}b  %0${NB}b  ", $wr_u, $wi_u);
+#	printf("%0${NX}X  %0${NX}X  ", $wr_u, $wi_u);
+	my $dontcare = 1;
+	$dontcare = 0 if ($n < $N/4);
+	$dontcare = 0 if (($n < 2*$N/4) && ($n % 2 == 0));
+	$dontcare = 0 if (($n < 3*$N/4) && ($n % 3 == 0));
+	$wr_u = 0 if ($n == 0);
+	my $wr_s = ($dontcare) ? $XX : sprintf("%0${NX}X", $wr_u);
+	my $wi_s = ($dontcare) ? $XX : sprintf("%0${NX}X", $wi_u);
+	printf("assign  wn_re[%2d] = ${NB}'h$wr_s;   ", $n);
+	printf("assign  wn_im[%2d] = ${NB}'h$wi_s;   ", $n);
+	printf("// %2d", $n);
+	printf(" % .3f % .3f", $wr, $wi);
+	print "\n";
+}
diff --git a/src/5_Blur_Integration/FFT_files/record_audio.py b/src/5_Blur_Integration/FFT_files/record_audio.py
new file mode 100644
index 0000000..4f636c2
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/record_audio.py
@@ -0,0 +1,67 @@
+import pyaudio # pip install pyaudio
+import matplotlib.pyplot as plt
+import numpy as np
+ 
+FORMAT = pyaudio.paInt16
+CHANNELS = 1
+RATE = 48000
+CHUNK = 512
+RECORD_SECONDS = 1
+WAVE_OUTPUT_FILENAME = "recordedFile.wav"
+device_index = 2
+audio = pyaudio.PyAudio()
+
+print("----------------------record device list---------------------")
+info = audio.get_host_api_info_by_index(0)
+numdevices = info.get('deviceCount')
+for i in range(0, numdevices):
+        if (audio.get_device_info_by_host_api_device_index(0, i).get('maxInputChannels')) > 0:
+            print("Input Device id ", i, " - ", audio.get_device_info_by_host_api_device_index(0, i).get('name'))
+
+print("-------------------------------------------------------------")
+index = int(input()) # Can comment the above code out after you know this!
+
+print("recording via index "+str(index))
+
+stream = audio.open(format=FORMAT, channels=CHANNELS,
+                rate=RATE, input=True,input_device_index = index,
+                frames_per_buffer=CHUNK)
+print ("recording started")
+Recordframes = []
+ 
+for i in range(0, 64): # 64x512 = 32768 samples (682.67ms)
+    data = stream.read(CHUNK)
+    Recordframes.append(data)
+print ("recording stopped")
+ 
+stream.stop_stream()
+stream.close()
+audio.terminate()
+
+signal = []
+
+for frame in Recordframes:
+    for i in range(0,len(frame),2):
+         signal.append(int.from_bytes(frame[i:i+2],byteorder="little", signed=True))
+
+# Write whole recording to file
+hexRecording = open("hex_recording.hex",'w')
+for n in signal:
+    hexRecording.write(f"{n&0xFFFF:04x}\n") # 16-bit
+
+# Decimate (skip samples to increase resolution - SHOULD use low-pass filter!)
+decimation = 1 # Change up to 32
+decimated_sig = signal[-1024*decimation::decimation]
+
+plt.plot(decimated_sig)
+plt.show()
+
+H = np.fft.fft(decimated_sig, 1024) # H[k] DFT of h[n]
+mag = np.abs(H[:512])
+freq = np.arange(0,512)/1024 * (48000/decimation)
+plt.title("Frequency Response: 1024-point DFT $H[k]$")
+plt.ylabel("Magnitude")
+plt.xlabel("Frequency (Hz)")
+plt.stem(freq, mag)
+plt.grid()
+plt.show()
\ No newline at end of file
diff --git a/src/5_Blur_Integration/FFT_files/seven_seg.sv b/src/5_Blur_Integration/FFT_files/seven_seg.sv
new file mode 100644
index 0000000..f30c561
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/seven_seg.sv
@@ -0,0 +1,22 @@
+module seven_seg(
+    input      [3:0]  bcd,
+    output reg [6:0]  segments // Must be reg to set in always block!!
+);
+  
+  always @(*) begin
+    case(bcd)
+        0:       segments = 7'b1000000;
+        1:       segments = 7'b1111001;
+        2:       segments = 7'b0100100;
+        3:       segments = 7'b0110000;
+        4:       segments = 7'b0011001;
+        5:       segments = 7'b0010010;
+        6:       segments = 7'b0000010;
+        7:       segments = 7'b1111000;
+        8:       segments = 7'b0000000;
+        9:       segments = 7'b0010000;
+        default: segments = 7'b1111111;  // Default: All segments turned off.
+    endcase
+  end
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_files/top_level.sv b/src/5_Blur_Integration/FFT_files/top_level.sv
new file mode 100644
index 0000000..bc75971
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_files/top_level.sv
@@ -0,0 +1,47 @@
+module top_level (
+	input    CLOCK_50,
+	output	I2C_SCLK,
+	inout		I2C_SDAT,
+	output [6:0] HEX0,
+	output [6:0] HEX1,
+	output [6:0] HEX2,
+	output [6:0] HEX3,
+	input  [3:0] KEY,
+	input		AUD_ADCDAT,
+	input    AUD_BCLK,
+	output   AUD_XCK,
+	input    AUD_ADCLRCK,
+	output logic [17:0] LEDR
+);
+   localparam W        = 16;   //NOTE: To change this, you must also change the Twiddle factor initialisations in r22sdf/Twiddle.v. You can use r22sdf/twiddle_gen.pl.
+   localparam NSamples = 1024; //NOTE: To change this, you must also change the SdfUnit instantiations in r22sdf/FFT.v accordingly.
+
+	logic adc_clk; adc_pll adc_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(adc_clk)); // generate 18.432 MHz clock
+	logic i2c_clk; i2c_pll i2c_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(i2c_clk)); // generate 20 kHz clock
+
+	set_audio_encoder set_codec_u (.i2c_clk(i2c_clk), .I2C_SCLK(I2C_SCLK), .I2C_SDAT(I2C_SDAT));
+
+	dstream #(.N(W))                audio_input ();
+   dstream #(.N($clog2(NSamples))) pitch_output ();
+	 
+	mic_load #(.N(W)) u_mic_load (
+    .adclrc(AUD_ADCLRCK),
+	 .bclk(AUD_BCLK),
+	 .adcdat(AUD_ADCDAT),
+    .sample_data(audio_input.data),
+	 .valid(audio_input.valid)
+   );
+			
+	assign AUD_XCK = adc_clk;
+	
+   fft_pitch_detect #(.W(W), .NSamples(NSamples)) DUT (
+	    .clk(adc_clk),
+		 .audio_clk(AUD_BCLK),
+		 .reset(~KEY[0]),
+		 .audio_input(audio_input),
+		 .pitch_output(pitch_output)
+    );
+	
+	display u_display (.clk(adc_clk),.value(pitch_output.data),.display0(HEX0),.display1(HEX1),.display2(HEX2),.display3(HEX3));
+
+endmodule
diff --git a/src/5_Blur_Integration/FFT_top_level.sv b/src/5_Blur_Integration/FFT_top_level.sv
new file mode 100644
index 0000000..34bdda2
--- /dev/null
+++ b/src/5_Blur_Integration/FFT_top_level.sv
@@ -0,0 +1,56 @@
+module FFT_top_level(
+	
+	input CLOCK_50,
+	input reset,
+	
+	// Microphone inputs and outputs
+	output	     I2C_SCLK,
+	inout		 I2C_SDAT,
+	input		 AUD_ADCDAT,
+	input    	 AUD_BCLK,
+	output   	 AUD_XCK,
+	input    	 AUD_ADCLRCK,
+	
+	output [9:0] mic_freq
+
+);
+
+	localparam W        = 16;   //NOTE: To change this, you must also change the Twiddle factor initialisations in r22sdf/Twiddle.v. You can use r22sdf/twiddle_gen.pl.
+		
+	localparam NSamples = 1024; //NOTE: To change this, you must also change the SdfUnit instantiations in r22sdf/FFT.v accordingly.
+
+	logic adc_clk; adc_pll adc_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(adc_clk)); // generate 18.432 MHz clock
+	logic i2c_clk; i2c_pll i2c_pll_u (.areset(1'b0),.inclk0(CLOCK_50),.c0(i2c_clk)); // generate 20 kHz clock
+
+	set_audio_encoder set_codec_u (.i2c_clk(i2c_clk), .I2C_SCLK(I2C_SCLK), .I2C_SDAT(I2C_SDAT));
+
+	dstream #(.N(W)) audio_input ();
+	dstream #(.N($clog2(NSamples))) pitch_output ();
+	 
+	mic_load #(.N(W)) u_mic_load (
+	 .adclrc(AUD_ADCLRCK),
+	 .bclk(AUD_BCLK),
+	 .adcdat(AUD_ADCDAT),
+	 .sample_data(audio_input.data),
+	 .valid(audio_input.valid)
+	);
+			
+	assign AUD_XCK = adc_clk;
+
+	fft_pitch_detect #(.W(W), .NSamples(NSamples)) DUT (
+		 .clk(adc_clk),
+		 .audio_clk(AUD_BCLK),
+		 .reset(reset),
+		 .audio_input(audio_input),
+		 .pitch_output(pitch_output)
+	);
+
+	
+	// Use a synchroniser to avoid metastable regions in clock domain crossing
+	nbit_synchroniser #(.N($clog2(NSamples))) nbs1(.clk(CLOCK_50),
+									.x_valid(pitch_output.valid),
+									.x(pitch_output.data),
+									.y(mic_freq));
+
+									
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/address_generator.sv b/src/5_Blur_Integration/address_generator.sv
new file mode 100644
index 0000000..a93c259
--- /dev/null
+++ b/src/5_Blur_Integration/address_generator.sv
@@ -0,0 +1,57 @@
+module address_generator(
+    input clk_25_vga,
+    input logic vga_ready,
+    input logic resend,
+    output logic vga_start_out,
+    output logic vga_end_out,
+    output logic [16:0] rdaddress
+);
+
+// create counter with back pressure
+  integer row = 0, col = 0;
+  integer row_old = 0, col_old = 0;
+  reg vga_start, vga_end;
+  logic [16:0] address;
+
+  always_ff @(posedge clk_25_vga) begin
+    
+    if(resend)
+      begin
+        col = 0; row= 0;
+      end
+    else if(vga_ready) begin
+      if(col >= 319) begin
+        col<= 0;
+        if(row >= 239) row <= 0;
+        else row <= row + 1;
+      end
+      else col <= col + 1;
+
+      row_old <= row;
+      col_old <= col;
+    end
+	
+  end
+  
+  // Set VGA start and end
+  always @(*) begin
+
+    // set start of packet
+		if(col_old == 0 && row_old == 0) begin
+			vga_start = 1;
+		end
+		else vga_start = 0;
+		
+    // set end of packet
+		if(col_old == 319 && row_old == 239) vga_end = 1;
+		else vga_end = 0;
+
+    // use the current row and column because there will be a 1 cycle delay
+    address = row * 320 + col;
+  end
+
+  assign vga_start_out = vga_start;
+  assign vga_end_out = vga_end;
+  assign rdaddress = address;
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/backwards.sv b/src/5_Blur_Integration/backwards.sv
new file mode 100644
index 0000000..87233aa
--- /dev/null
+++ b/src/5_Blur_Integration/backwards.sv
@@ -0,0 +1,115 @@
+import lcd_inst_pkg::*;
+
+module backwards #(
+    parameter CLKS_PER_BIT = 50_000_000/115_200,
+    parameter BITS_N = 8,
+    parameter NUM_BYTES = 27
+    )(
+    input clk,
+    input rst,
+    input [2:0] speed,
+    output logic uart_out,
+    output logic ready         // Signal indicating the system is ready for a new command
+);
+    logic [4:0] byte_index = 0;
+    logic [4:0] next_byte_index = 0;
+
+    logic uart_valid;
+    logic [BITS_N-1:0] current_byte = 8'b0;
+
+    logic uart_ready;
+
+    // UART transmitter instance
+    uart_tx #(
+        .CLKS_PER_BIT(CLKS_PER_BIT),
+        .BITS_N(BITS_N)
+    ) uart (
+        .clk(clk),
+        .rst(rst),
+        .data_tx(current_byte),
+        .uart_out(uart_out),
+        .valid(uart_valid),
+        .ready(uart_ready)
+    );
+
+    // Hard-coded 25-byte JSON message: {"T":11,"L":164,"R":164}\n
+    logic [0:NUM_BYTES-1][7:0] json_data;
+    initial begin
+        json_data[0] = _OPEN_BRACE;
+        json_data[1] =_DOUBLE_QUOTE;
+        json_data[2] =_T;
+        json_data[3] =_DOUBLE_QUOTE;
+        json_data[4] =_COLON;
+        json_data[5] =_1;
+        json_data[6] =_COMMA;
+        json_data[7] =_DOUBLE_QUOTE;
+        json_data[8] =_L;
+        json_data[9] =_DOUBLE_QUOTE;
+        json_data[10] =_COLON;
+        json_data[11] = _MINUS;
+        json_data[12] =_0;
+        json_data[13] =_PERIOD;
+        json_data[14] =_5;
+        json_data[15] =_COMMA;
+        json_data[16] =_DOUBLE_QUOTE;
+        json_data[17] =_R;
+        json_data[18] =_DOUBLE_QUOTE;
+        json_data[19] =_COLON;
+        json_data[20] = _MINUS;
+        json_data[21] =_0;
+        json_data[22] =_PERIOD;
+        json_data[23] =_5;
+        json_data[24] =_CLOSE_BRACE;
+        json_data[25] =8'h0A;
+		json_data[26] =8'h0A; // new line character
+    end
+    
+    // map the speed control correctly
+    logic [7:0] ascii_speed;
+    speed_control_mapping scm (
+        .speed(speed),
+        .ascii_speed(ascii_speed)
+    );
+
+
+    localparam speed_index_0 = 14;
+    localparam speed_index_1 = 23;
+    // current byte based on byte index
+    always_comb begin
+
+        current_byte = json_data[byte_index];
+
+        // adjust the speed by the speed signal
+        if(byte_index == speed_index_0 || byte_index == speed_index_1) begin
+            current_byte = ascii_speed;
+        end
+
+    end
+	 
+    // Control logic to send the JSON string byte by byte
+    always_ff @(posedge clk) begin
+        if (rst)
+        begin
+            byte_index <= 0;
+            next_byte_index <= 0;
+            uart_valid <= 1'b0;
+        end 
+		else if (next_byte_index == NUM_BYTES) 
+			  begin
+				uart_valid <= 1'b0; //  we've reached the end so set valid low
+			  end
+        else if (uart_ready)
+        begin
+            if(next_byte_index < NUM_BYTES)
+					begin
+						 byte_index <= next_byte_index;
+						 uart_valid <= 1'b1;
+						 next_byte_index <= next_byte_index + 1;
+					end
+        end 
+    end
+
+    // Ready signal when all bytes have been sent, including the newline
+    assign ready = (byte_index == NUM_BYTES) && uart_ready && (!uart_valid);  // Only ready after the last byte is fully sent
+
+endmodule
diff --git a/src/5_Blur_Integration/camera_enable.qsf b/src/5_Blur_Integration/camera_enable.qsf
new file mode 100644
index 0000000..9a7e052
--- /dev/null
+++ b/src/5_Blur_Integration/camera_enable.qsf
@@ -0,0 +1,1176 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 06:24:53  September 24, 2024
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		camera_enable_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY top_level
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:24:53  SEPTEMBER 24, 2024"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE top_level.sv
+set_global_assignment -name QIP_FILE vga_interface/synthesis/vga_interface.qip
+set_global_assignment -name SYSTEMVERILOG_FILE data_expander.sv
+set_global_assignment -name VERILOG_FILE ov7670_registers.v
+set_global_assignment -name VERILOG_FILE ov7670_controller.v
+set_global_assignment -name VERILOG_FILE ov7670_capture.v
+set_global_assignment -name VERILOG_FILE my_frame_buffer_15to0.v
+set_global_assignment -name VERILOG_FILE my_altpll.v
+set_global_assignment -name VERILOG_FILE i2c_sender.v
+set_global_assignment -name VERILOG_FILE frame_buffer.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_D2 -to AUD_ADCDAT
+set_location_assignment PIN_C2 -to AUD_ADCLRCK
+set_location_assignment PIN_F2 -to AUD_BCLK
+set_location_assignment PIN_D1 -to AUD_DACDAT
+set_location_assignment PIN_E3 -to AUD_DACLRCK
+set_location_assignment PIN_E1 -to AUD_XCK
+set_location_assignment PIN_AG14 -to CLOCK2_50
+set_location_assignment PIN_AG15 -to CLOCK3_50
+set_location_assignment PIN_Y2 -to CLOCK_50
+set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
+set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
+set_location_assignment PIN_R5 -to DRAM_ADDR[10]
+set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
+set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
+set_location_assignment PIN_W7 -to DRAM_ADDR[6]
+set_location_assignment PIN_W8 -to DRAM_ADDR[5]
+set_location_assignment PIN_V5 -to DRAM_ADDR[4]
+set_location_assignment PIN_P1 -to DRAM_ADDR[3]
+set_location_assignment PIN_U8 -to DRAM_ADDR[2]
+set_location_assignment PIN_V8 -to DRAM_ADDR[1]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_location_assignment PIN_R4 -to DRAM_BA[1]
+set_location_assignment PIN_U7 -to DRAM_BA[0]
+set_location_assignment PIN_V7 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AE5 -to DRAM_CLK
+set_location_assignment PIN_T4 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[31]
+set_location_assignment PIN_U4 -to DRAM_DQ[30]
+set_location_assignment PIN_T3 -to DRAM_DQ[29]
+set_location_assignment PIN_R3 -to DRAM_DQ[28]
+set_location_assignment PIN_R2 -to DRAM_DQ[27]
+set_location_assignment PIN_R1 -to DRAM_DQ[26]
+set_location_assignment PIN_R7 -to DRAM_DQ[25]
+set_location_assignment PIN_U5 -to DRAM_DQ[24]
+set_location_assignment PIN_L7 -to DRAM_DQ[23]
+set_location_assignment PIN_M7 -to DRAM_DQ[22]
+set_location_assignment PIN_M4 -to DRAM_DQ[21]
+set_location_assignment PIN_N4 -to DRAM_DQ[20]
+set_location_assignment PIN_N3 -to DRAM_DQ[19]
+set_location_assignment PIN_P2 -to DRAM_DQ[18]
+set_location_assignment PIN_L8 -to DRAM_DQ[17]
+set_location_assignment PIN_M8 -to DRAM_DQ[16]
+set_location_assignment PIN_AC2 -to DRAM_DQ[15]
+set_location_assignment PIN_AB3 -to DRAM_DQ[14]
+set_location_assignment PIN_AC1 -to DRAM_DQ[13]
+set_location_assignment PIN_AB2 -to DRAM_DQ[12]
+set_location_assignment PIN_AA3 -to DRAM_DQ[11]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_Y4 -to DRAM_DQ[9]
+set_location_assignment PIN_Y3 -to DRAM_DQ[8]
+set_location_assignment PIN_U3 -to DRAM_DQ[7]
+set_location_assignment PIN_V1 -to DRAM_DQ[6]
+set_location_assignment PIN_V2 -to DRAM_DQ[5]
+set_location_assignment PIN_V3 -to DRAM_DQ[4]
+set_location_assignment PIN_W1 -to DRAM_DQ[3]
+set_location_assignment PIN_V4 -to DRAM_DQ[2]
+set_location_assignment PIN_W2 -to DRAM_DQ[1]
+set_location_assignment PIN_W3 -to DRAM_DQ[0]
+set_location_assignment PIN_N8 -to DRAM_DQM[3]
+set_location_assignment PIN_K8 -to DRAM_DQM[2]
+set_location_assignment PIN_W4 -to DRAM_DQM[1]
+set_location_assignment PIN_U2 -to DRAM_DQM[0]
+set_location_assignment PIN_U6 -to DRAM_RAS_N
+set_location_assignment PIN_V6 -to DRAM_WE_N
+set_location_assignment PIN_D14 -to EEP_I2C_SCLK
+set_location_assignment PIN_E14 -to EEP_I2C_SDAT
+set_location_assignment PIN_A17 -to ENET0_GTX_CLK
+set_location_assignment PIN_A21 -to ENET0_INT_N
+set_location_assignment PIN_C14 -to ENET0_LINK100
+set_location_assignment PIN_C20 -to ENET0_MDC
+set_location_assignment PIN_B21 -to ENET0_MDIO
+set_location_assignment PIN_C19 -to ENET0_RST_N
+set_location_assignment PIN_A15 -to ENET0_RX_CLK
+set_location_assignment PIN_E15 -to ENET0_RX_COL
+set_location_assignment PIN_D15 -to ENET0_RX_CRS
+set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
+set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
+set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
+set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
+set_location_assignment PIN_C17 -to ENET0_RX_DV
+set_location_assignment PIN_D18 -to ENET0_RX_ER
+set_location_assignment PIN_B17 -to ENET0_TX_CLK
+set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
+set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
+set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
+set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
+set_location_assignment PIN_A18 -to ENET0_TX_EN
+set_location_assignment PIN_B18 -to ENET0_TX_ER
+set_location_assignment PIN_C23 -to ENET1_GTX_CLK
+set_location_assignment PIN_D24 -to ENET1_INT_N
+set_location_assignment PIN_D13 -to ENET1_LINK100
+set_location_assignment PIN_D23 -to ENET1_MDC
+set_location_assignment PIN_D25 -to ENET1_MDIO
+set_location_assignment PIN_D22 -to ENET1_RST_N
+set_location_assignment PIN_B15 -to ENET1_RX_CLK
+set_location_assignment PIN_B22 -to ENET1_RX_COL
+set_location_assignment PIN_D20 -to ENET1_RX_CRS
+set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
+set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
+set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
+set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
+set_location_assignment PIN_A22 -to ENET1_RX_DV
+set_location_assignment PIN_C24 -to ENET1_RX_ER
+set_location_assignment PIN_C22 -to ENET1_TX_CLK
+set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
+set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
+set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
+set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
+set_location_assignment PIN_B25 -to ENET1_TX_EN
+set_location_assignment PIN_A25 -to ENET1_TX_ER
+set_location_assignment PIN_A14 -to ENETCLK_25
+set_location_assignment PIN_D9 -to EX_IO[6]
+set_location_assignment PIN_E10 -to EX_IO[5]
+set_location_assignment PIN_F14 -to EX_IO[4]
+set_location_assignment PIN_H14 -to EX_IO[3]
+set_location_assignment PIN_H13 -to EX_IO[2]
+set_location_assignment PIN_J14 -to EX_IO[1]
+set_location_assignment PIN_J10 -to EX_IO[0]
+set_location_assignment PIN_AD11 -to FL_ADDR[22]
+set_location_assignment PIN_AD10 -to FL_ADDR[21]
+set_location_assignment PIN_AE10 -to FL_ADDR[20]
+set_location_assignment PIN_AD12 -to FL_ADDR[19]
+set_location_assignment PIN_AC12 -to FL_ADDR[18]
+set_location_assignment PIN_AH12 -to FL_ADDR[17]
+set_location_assignment PIN_AA8 -to FL_ADDR[16]
+set_location_assignment PIN_Y10 -to FL_ADDR[15]
+set_location_assignment PIN_AC8 -to FL_ADDR[14]
+set_location_assignment PIN_AD8 -to FL_ADDR[13]
+set_location_assignment PIN_AA10 -to FL_ADDR[12]
+set_location_assignment PIN_AF9 -to FL_ADDR[11]
+set_location_assignment PIN_AE9 -to FL_ADDR[10]
+set_location_assignment PIN_AB10 -to FL_ADDR[9]
+set_location_assignment PIN_AB12 -to FL_ADDR[8]
+set_location_assignment PIN_AB13 -to FL_ADDR[7]
+set_location_assignment PIN_AA12 -to FL_ADDR[6]
+set_location_assignment PIN_AA13 -to FL_ADDR[5]
+set_location_assignment PIN_Y12 -to FL_ADDR[4]
+set_location_assignment PIN_Y14 -to FL_ADDR[3]
+set_location_assignment PIN_Y13 -to FL_ADDR[2]
+set_location_assignment PIN_AH7 -to FL_ADDR[1]
+set_location_assignment PIN_AG12 -to FL_ADDR[0]
+set_location_assignment PIN_AG7 -to FL_CE_N
+set_location_assignment PIN_AF12 -to FL_DQ[7]
+set_location_assignment PIN_AH11 -to FL_DQ[6]
+set_location_assignment PIN_AG11 -to FL_DQ[5]
+set_location_assignment PIN_AF11 -to FL_DQ[4]
+set_location_assignment PIN_AH10 -to FL_DQ[3]
+set_location_assignment PIN_AG10 -to FL_DQ[2]
+set_location_assignment PIN_AF10 -to FL_DQ[1]
+set_location_assignment PIN_AH8 -to FL_DQ[0]
+set_location_assignment PIN_AG8 -to FL_OE_N
+set_location_assignment PIN_AE11 -to FL_RST_N
+set_location_assignment PIN_Y1 -to FL_RY
+set_location_assignment PIN_AC10 -to FL_WE_N
+set_location_assignment PIN_AE12 -to FL_WP_N
+set_location_assignment PIN_AG26 -to GPIO[35]
+set_location_assignment PIN_AH23 -to GPIO[34]
+set_location_assignment PIN_AH26 -to GPIO[33]
+set_location_assignment PIN_AF20 -to GPIO[32]
+set_location_assignment PIN_AG23 -to GPIO[31]
+set_location_assignment PIN_AE20 -to GPIO[30]
+set_location_assignment PIN_AF26 -to GPIO[29]
+set_location_assignment PIN_AH22 -to GPIO[28]
+set_location_assignment PIN_AE24 -to GPIO[27]
+set_location_assignment PIN_AG22 -to GPIO[26]
+set_location_assignment PIN_AE25 -to GPIO[25]
+set_location_assignment PIN_AH25 -to GPIO[24]
+set_location_assignment PIN_AD25 -to GPIO[23]
+set_location_assignment PIN_AG25 -to GPIO[22]
+set_location_assignment PIN_AD22 -to GPIO[21]
+set_location_assignment PIN_AF22 -to GPIO[20]
+set_location_assignment PIN_AF21 -to GPIO[19]
+set_location_assignment PIN_AE22 -to GPIO[18]
+set_location_assignment PIN_AC22 -to GPIO[17]
+set_location_assignment PIN_AF25 -to GPIO[16]
+set_location_assignment PIN_AE21 -to GPIO[15]
+set_location_assignment PIN_AF24 -to GPIO[14]
+set_location_assignment PIN_AF15 -to GPIO[13]
+set_location_assignment PIN_AD19 -to GPIO[12]
+set_location_assignment PIN_AF16 -to GPIO[11]
+set_location_assignment PIN_AC19 -to GPIO[10]
+set_location_assignment PIN_AE15 -to GPIO[9]
+set_location_assignment PIN_AD15 -to GPIO[8]
+set_location_assignment PIN_AE16 -to GPIO[7]
+set_location_assignment PIN_AD21 -to GPIO[6]
+set_location_assignment PIN_Y16 -to GPIO[5]
+set_location_assignment PIN_AC21 -to GPIO[4]
+set_location_assignment PIN_Y17 -to GPIO[3]
+set_location_assignment PIN_AB21 -to GPIO[2]
+set_location_assignment PIN_AC15 -to GPIO[1]
+set_location_assignment PIN_AB22 -to GPIO[0]
+set_location_assignment PIN_H22 -to HEX0[6]
+set_location_assignment PIN_J22 -to HEX0[5]
+set_location_assignment PIN_L25 -to HEX0[4]
+set_location_assignment PIN_L26 -to HEX0[3]
+set_location_assignment PIN_E17 -to HEX0[2]
+set_location_assignment PIN_F22 -to HEX0[1]
+set_location_assignment PIN_G18 -to HEX0[0]
+set_location_assignment PIN_U24 -to HEX1[6]
+set_location_assignment PIN_U23 -to HEX1[5]
+set_location_assignment PIN_W25 -to HEX1[4]
+set_location_assignment PIN_W22 -to HEX1[3]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[1]
+set_location_assignment PIN_M24 -to HEX1[0]
+set_location_assignment PIN_W28 -to HEX2[6]
+set_location_assignment PIN_W27 -to HEX2[5]
+set_location_assignment PIN_Y26 -to HEX2[4]
+set_location_assignment PIN_W26 -to HEX2[3]
+set_location_assignment PIN_Y25 -to HEX2[2]
+set_location_assignment PIN_AA26 -to HEX2[1]
+set_location_assignment PIN_AA25 -to HEX2[0]
+set_location_assignment PIN_Y19 -to HEX3[6]
+set_location_assignment PIN_AF23 -to HEX3[5]
+set_location_assignment PIN_AD24 -to HEX3[4]
+set_location_assignment PIN_AA21 -to HEX3[3]
+set_location_assignment PIN_AB20 -to HEX3[2]
+set_location_assignment PIN_U21 -to HEX3[1]
+set_location_assignment PIN_V21 -to HEX3[0]
+set_location_assignment PIN_AE18 -to HEX4[6]
+set_location_assignment PIN_AF19 -to HEX4[5]
+set_location_assignment PIN_AE19 -to HEX4[4]
+set_location_assignment PIN_AH21 -to HEX4[3]
+set_location_assignment PIN_AG21 -to HEX4[2]
+set_location_assignment PIN_AA19 -to HEX4[1]
+set_location_assignment PIN_AB19 -to HEX4[0]
+set_location_assignment PIN_AH18 -to HEX5[6]
+set_location_assignment PIN_AF18 -to HEX5[5]
+set_location_assignment PIN_AG19 -to HEX5[4]
+set_location_assignment PIN_AH19 -to HEX5[3]
+set_location_assignment PIN_AB18 -to HEX5[2]
+set_location_assignment PIN_AC18 -to HEX5[1]
+set_location_assignment PIN_AD18 -to HEX5[0]
+set_location_assignment PIN_AC17 -to HEX6[6]
+set_location_assignment PIN_AA15 -to HEX6[5]
+set_location_assignment PIN_AB15 -to HEX6[4]
+set_location_assignment PIN_AB17 -to HEX6[3]
+set_location_assignment PIN_AA16 -to HEX6[2]
+set_location_assignment PIN_AB16 -to HEX6[1]
+set_location_assignment PIN_AA17 -to HEX6[0]
+set_location_assignment PIN_AA14 -to HEX7[6]
+set_location_assignment PIN_AG18 -to HEX7[5]
+set_location_assignment PIN_AF17 -to HEX7[4]
+set_location_assignment PIN_AH17 -to HEX7[3]
+set_location_assignment PIN_AG17 -to HEX7[2]
+set_location_assignment PIN_AE17 -to HEX7[1]
+set_location_assignment PIN_AD17 -to HEX7[0]
+set_location_assignment PIN_AH15 -to HSMC_CLKIN0
+set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
+set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
+set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
+set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
+set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
+set_location_assignment PIN_AF27 -to HSMC_D[3]
+set_location_assignment PIN_AE27 -to HSMC_D[2]
+set_location_assignment PIN_AE28 -to HSMC_D[1]
+set_location_assignment PIN_AE26 -to HSMC_D[0]
+set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
+set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
+set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
+set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
+set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
+set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
+set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
+set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
+set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
+set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
+set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
+set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
+set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
+set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
+set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
+set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
+set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
+set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
+set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
+set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
+set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
+set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
+set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
+set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
+set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
+set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
+set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
+set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
+set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
+set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
+set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
+set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
+set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
+set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
+set_location_assignment PIN_B7 -to I2C_SCLK
+set_location_assignment PIN_A8 -to I2C_SDAT
+set_location_assignment PIN_Y15 -to IRDA_RXD
+set_location_assignment PIN_R24 -to KEY[3]
+set_location_assignment PIN_N21 -to KEY[2]
+set_location_assignment PIN_M21 -to KEY[1]
+set_location_assignment PIN_M23 -to KEY[0]
+set_location_assignment PIN_L6 -to LCD_BLON
+set_location_assignment PIN_M5 -to LCD_DATA[7]
+set_location_assignment PIN_M3 -to LCD_DATA[6]
+set_location_assignment PIN_K2 -to LCD_DATA[5]
+set_location_assignment PIN_K1 -to LCD_DATA[4]
+set_location_assignment PIN_K7 -to LCD_DATA[3]
+set_location_assignment PIN_L2 -to LCD_DATA[2]
+set_location_assignment PIN_L1 -to LCD_DATA[1]
+set_location_assignment PIN_L3 -to LCD_DATA[0]
+set_location_assignment PIN_L4 -to LCD_EN
+set_location_assignment PIN_L5 -to LCD_ON
+set_location_assignment PIN_M2 -to LCD_RS
+set_location_assignment PIN_M1 -to LCD_RW
+set_location_assignment PIN_F17 -to LEDG[8]
+set_location_assignment PIN_G21 -to LEDG[7]
+set_location_assignment PIN_G22 -to LEDG[6]
+set_location_assignment PIN_G20 -to LEDG[5]
+set_location_assignment PIN_H21 -to LEDG[4]
+set_location_assignment PIN_E24 -to LEDG[3]
+set_location_assignment PIN_E25 -to LEDG[2]
+set_location_assignment PIN_E22 -to LEDG[1]
+set_location_assignment PIN_E21 -to LEDG[0]
+set_location_assignment PIN_H15 -to LEDR[17]
+set_location_assignment PIN_G16 -to LEDR[16]
+set_location_assignment PIN_G15 -to LEDR[15]
+set_location_assignment PIN_F15 -to LEDR[14]
+set_location_assignment PIN_H17 -to LEDR[13]
+set_location_assignment PIN_J16 -to LEDR[12]
+set_location_assignment PIN_H16 -to LEDR[11]
+set_location_assignment PIN_J15 -to LEDR[10]
+set_location_assignment PIN_G17 -to LEDR[9]
+set_location_assignment PIN_J17 -to LEDR[8]
+set_location_assignment PIN_H19 -to LEDR[7]
+set_location_assignment PIN_J19 -to LEDR[6]
+set_location_assignment PIN_E18 -to LEDR[5]
+set_location_assignment PIN_F18 -to LEDR[4]
+set_location_assignment PIN_F21 -to LEDR[3]
+set_location_assignment PIN_E19 -to LEDR[2]
+set_location_assignment PIN_F19 -to LEDR[1]
+set_location_assignment PIN_G19 -to LEDR[0]
+set_location_assignment PIN_C3 -to OTG_ADDR[1]
+set_location_assignment PIN_H7 -to OTG_ADDR[0]
+set_location_assignment PIN_A3 -to OTG_CS_N
+set_location_assignment PIN_D4 -to OTG_DACK_N[1]
+set_location_assignment PIN_C4 -to OTG_DACK_N[0]
+set_location_assignment PIN_G4 -to OTG_DATA[15]
+set_location_assignment PIN_F3 -to OTG_DATA[14]
+set_location_assignment PIN_F1 -to OTG_DATA[13]
+set_location_assignment PIN_G3 -to OTG_DATA[12]
+set_location_assignment PIN_G2 -to OTG_DATA[11]
+set_location_assignment PIN_G1 -to OTG_DATA[10]
+set_location_assignment PIN_H4 -to OTG_DATA[9]
+set_location_assignment PIN_H3 -to OTG_DATA[8]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_J3 -to OTG_DATA[5]
+set_location_assignment PIN_J4 -to OTG_DATA[4]
+set_location_assignment PIN_K3 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[2]
+set_location_assignment PIN_K4 -to OTG_DATA[1]
+set_location_assignment PIN_J6 -to OTG_DATA[0]
+set_location_assignment PIN_B4 -to OTG_DREQ[1]
+set_location_assignment PIN_J1 -to OTG_DREQ[0]
+set_location_assignment PIN_C6 -to OTG_FSPEED
+set_location_assignment PIN_D5 -to OTG_INT[1]
+set_location_assignment PIN_A6 -to OTG_INT[0]
+set_location_assignment PIN_B6 -to OTG_LSPEED
+set_location_assignment PIN_B3 -to OTG_RD_N
+set_location_assignment PIN_C5 -to OTG_RST_N
+set_location_assignment PIN_A4 -to OTG_WR_N
+set_location_assignment PIN_G6 -to PS2_CLK
+set_location_assignment PIN_G5 -to PS2_CLK2
+set_location_assignment PIN_H5 -to PS2_DAT
+set_location_assignment PIN_F5 -to PS2_DAT2
+set_location_assignment PIN_AE13 -to SD_CLK
+set_location_assignment PIN_AD14 -to SD_CMD
+set_location_assignment PIN_AC14 -to SD_DAT[3]
+set_location_assignment PIN_AB14 -to SD_DAT[2]
+set_location_assignment PIN_AF13 -to SD_DAT[1]
+set_location_assignment PIN_AE14 -to SD_DAT[0]
+set_location_assignment PIN_AF14 -to SD_WP_N
+set_location_assignment PIN_AH14 -to SMA_CLKIN
+set_location_assignment PIN_AE23 -to SMA_CLKOUT
+set_location_assignment PIN_T8 -to SRAM_ADDR[19]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
+set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
+set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
+set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
+set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
+set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
+set_location_assignment PIN_T7 -to SRAM_ADDR[9]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
+set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
+set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
+set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF8 -to SRAM_CE_N
+set_location_assignment PIN_AG3 -to SRAM_DQ[15]
+set_location_assignment PIN_AF3 -to SRAM_DQ[14]
+set_location_assignment PIN_AE4 -to SRAM_DQ[13]
+set_location_assignment PIN_AE3 -to SRAM_DQ[12]
+set_location_assignment PIN_AE1 -to SRAM_DQ[11]
+set_location_assignment PIN_AE2 -to SRAM_DQ[10]
+set_location_assignment PIN_AD2 -to SRAM_DQ[9]
+set_location_assignment PIN_AD1 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[7]
+set_location_assignment PIN_AH6 -to SRAM_DQ[6]
+set_location_assignment PIN_AG6 -to SRAM_DQ[5]
+set_location_assignment PIN_AF6 -to SRAM_DQ[4]
+set_location_assignment PIN_AH4 -to SRAM_DQ[3]
+set_location_assignment PIN_AG4 -to SRAM_DQ[2]
+set_location_assignment PIN_AF4 -to SRAM_DQ[1]
+set_location_assignment PIN_AH3 -to SRAM_DQ[0]
+set_location_assignment PIN_AD4 -to SRAM_LB_N
+set_location_assignment PIN_AD5 -to SRAM_OE_N
+set_location_assignment PIN_AC4 -to SRAM_UB_N
+set_location_assignment PIN_AE8 -to SRAM_WE_N
+set_location_assignment PIN_Y23 -to SW[17]
+set_location_assignment PIN_Y24 -to SW[16]
+set_location_assignment PIN_AA22 -to SW[15]
+set_location_assignment PIN_AA23 -to SW[14]
+set_location_assignment PIN_AA24 -to SW[13]
+set_location_assignment PIN_AB23 -to SW[12]
+set_location_assignment PIN_AB24 -to SW[11]
+set_location_assignment PIN_AC24 -to SW[10]
+set_location_assignment PIN_AB25 -to SW[9]
+set_location_assignment PIN_AC25 -to SW[8]
+set_location_assignment PIN_AB26 -to SW[7]
+set_location_assignment PIN_AD26 -to SW[6]
+set_location_assignment PIN_AC26 -to SW[5]
+set_location_assignment PIN_AB27 -to SW[4]
+set_location_assignment PIN_AD27 -to SW[3]
+set_location_assignment PIN_AC27 -to SW[2]
+set_location_assignment PIN_AC28 -to SW[1]
+set_location_assignment PIN_AB28 -to SW[0]
+set_location_assignment PIN_B14 -to TD_CLK27
+set_location_assignment PIN_F7 -to TD_DATA[7]
+set_location_assignment PIN_E7 -to TD_DATA[6]
+set_location_assignment PIN_D6 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[4]
+set_location_assignment PIN_C7 -to TD_DATA[3]
+set_location_assignment PIN_D8 -to TD_DATA[2]
+set_location_assignment PIN_A7 -to TD_DATA[1]
+set_location_assignment PIN_E8 -to TD_DATA[0]
+set_location_assignment PIN_E5 -to TD_HS
+set_location_assignment PIN_G7 -to TD_RESET_N
+set_location_assignment PIN_E4 -to TD_VS
+set_location_assignment PIN_G14 -to UART_CTS
+set_location_assignment PIN_J13 -to UART_RTS
+set_location_assignment PIN_G12 -to UART_RXD
+set_location_assignment PIN_G9 -to UART_TXD
+set_location_assignment PIN_D12 -to VGA_B[7]
+set_location_assignment PIN_D11 -to VGA_B[6]
+set_location_assignment PIN_C12 -to VGA_B[5]
+set_location_assignment PIN_A11 -to VGA_B[4]
+set_location_assignment PIN_B11 -to VGA_B[3]
+set_location_assignment PIN_C11 -to VGA_B[2]
+set_location_assignment PIN_A10 -to VGA_B[1]
+set_location_assignment PIN_B10 -to VGA_B[0]
+set_location_assignment PIN_F11 -to VGA_BLANK_N
+set_location_assignment PIN_A12 -to VGA_CLK
+set_location_assignment PIN_C9 -to VGA_G[7]
+set_location_assignment PIN_F10 -to VGA_G[6]
+set_location_assignment PIN_B8 -to VGA_G[5]
+set_location_assignment PIN_C8 -to VGA_G[4]
+set_location_assignment PIN_H12 -to VGA_G[3]
+set_location_assignment PIN_F8 -to VGA_G[2]
+set_location_assignment PIN_G11 -to VGA_G[1]
+set_location_assignment PIN_G8 -to VGA_G[0]
+set_location_assignment PIN_G13 -to VGA_HS
+set_location_assignment PIN_H10 -to VGA_R[7]
+set_location_assignment PIN_H8 -to VGA_R[6]
+set_location_assignment PIN_J12 -to VGA_R[5]
+set_location_assignment PIN_G10 -to VGA_R[4]
+set_location_assignment PIN_F12 -to VGA_R[3]
+set_location_assignment PIN_D10 -to VGA_R[2]
+set_location_assignment PIN_E11 -to VGA_R[1]
+set_location_assignment PIN_E12 -to VGA_R[0]
+set_location_assignment PIN_C10 -to VGA_SYNC_N
+set_location_assignment PIN_C13 -to VGA_VS
+set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
+set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
+set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
+set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
+set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
+set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
+set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
+set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
+set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
+set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
+set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
+set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
+set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
+set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
+set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
+set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
+set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
+set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
+set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
+set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
+set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
+set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
+set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
+set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
+set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
+set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
+set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
+set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
+set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
+set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
+set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
+set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
+set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
+set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
+set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
+set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
+set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
+set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity digital_cam_impl1 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity digital_cam_impl1 -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -entity digital_cam_impl1 -section_id Top
+set_location_assignment PIN_M23 -to btn_resend
+set_location_assignment PIN_Y2 -to clk_50
+set_location_assignment PIN_E21 -to led_config_finished
+set_location_assignment PIN_E22 -to config_start
+set_location_assignment PIN_AE22 -to ov7670_data[6]
+set_location_assignment PIN_AF21 -to ov7670_data[7]
+set_location_assignment PIN_AF25 -to ov7670_data[4]
+set_location_assignment PIN_AC22 -to ov7670_data[5]
+set_location_assignment PIN_AF24 -to ov7670_data[2]
+set_location_assignment PIN_AE21 -to ov7670_data[3]
+set_location_assignment PIN_AD19 -to ov7670_data[0]
+set_location_assignment PIN_AF15 -to ov7670_data[1]
+set_location_assignment PIN_AG25 -to ov7670_href
+set_location_assignment PIN_AD25 -to ov7670_vsync
+set_location_assignment PIN_AF16 -to ov7670_reset
+set_location_assignment PIN_AC19 -to ov7670_pwdn
+set_location_assignment PIN_AD22 -to ov7670_pclk
+set_location_assignment PIN_AF22 -to ov7670_xclk
+set_location_assignment PIN_AH25 -to ov7670_siod
+set_location_assignment PIN_AE25 -to ov7670_sioc
+set_location_assignment PIN_D12 -to vga_b[7]
+set_location_assignment PIN_D11 -to vga_b[6]
+set_location_assignment PIN_C12 -to vga_b[5]
+set_location_assignment PIN_A11 -to vga_b[4]
+set_location_assignment PIN_B11 -to vga_b[3]
+set_location_assignment PIN_C11 -to vga_b[2]
+set_location_assignment PIN_A10 -to vga_b[1]
+set_location_assignment PIN_B10 -to vga_b[0]
+set_location_assignment PIN_A12 -to vga_CLK
+set_location_assignment PIN_C10 -to vga_sync_N
+set_location_assignment PIN_F11 -to vga_blank_N
+set_location_assignment PIN_G13 -to vga_hsync
+set_location_assignment PIN_C13 -to vga_vsync
+set_location_assignment PIN_C9 -to vga_g[7]
+set_location_assignment PIN_F10 -to vga_g[6]
+set_location_assignment PIN_B8 -to vga_g[5]
+set_location_assignment PIN_C8 -to vga_g[4]
+set_location_assignment PIN_H12 -to vga_g[3]
+set_location_assignment PIN_F8 -to vga_g[2]
+set_location_assignment PIN_G11 -to vga_g[1]
+set_location_assignment PIN_G8 -to vga_g[0]
+set_location_assignment PIN_H10 -to vga_r[7]
+set_location_assignment PIN_H8 -to vga_r[6]
+set_location_assignment PIN_J12 -to vga_r[5]
+set_location_assignment PIN_G10 -to vga_r[4]
+set_location_assignment PIN_F12 -to vga_r[3]
+set_location_assignment PIN_D10 -to vga_r[2]
+set_location_assignment PIN_E11 -to vga_r[1]
+set_location_assignment PIN_E12 -to vga_r[0]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity digital_cam_impl1 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/src/5_Blur_Integration/camera_generation_top.sv b/src/5_Blur_Integration/camera_generation_top.sv
new file mode 100644
index 0000000..d8b378e
--- /dev/null
+++ b/src/5_Blur_Integration/camera_generation_top.sv
@@ -0,0 +1,90 @@
+module camera_generation_top (
+	
+	// Camera Inputs and Outputs
+	input wire ov7670_pclk,
+	output wire ov7670_xclk,
+	input wire ov7670_vsync,
+	input wire ov7670_href,
+	input wire [7:0] ov7670_data,
+	output wire ov7670_sioc,
+	inout wire ov7670_siod,
+	output wire ov7670_pwdn,
+	output wire ov7670_reset,
+	
+	input clk_50,
+	input [17:0] SW,	// switches taken as inputs	
+	input ready, // ready comes from vga or its high - create selection
+	output sop,
+	output eop,
+	output [11:0] pixel,
+	output [16:0] address,
+	output clk_25_vga
+);
+
+
+	wire btn_resend;
+	assign btn_resend = SW[0];
+	
+	wire clk_50_camera;
+	wire wren;
+	wire resend;
+	wire nBlank;
+	wire vSync;
+	wire [16:0] wraddress;
+	wire [11:0] wrdata;
+	logic [16:0] rdaddress;
+	wire [11:0] rddata;
+  	logic [11:0] vga_data;
+	wire [7:0] red; wire [7:0] green; wire [7:0] blue;
+	wire activeArea;
+
+  my_altpll Inst_vga_pll(
+      .inclk0(clk_50),
+    .c0(clk_50_camera),
+    .c1(clk_25_vga));
+
+  assign resend =  ~btn_resend;
+
+  ov7670_controller Inst_ov7670_controller(
+      .clk(clk_50_camera),
+    .resend(resend),
+    .config_finished(led_config_finished),
+    .sioc(ov7670_sioc),
+    .siod(ov7670_siod),
+    .reset(ov7670_reset),
+    .pwdn(ov7670_pwdn),
+    .xclk(ov7670_xclk));
+
+  ov7670_capture Inst_ov7670_capture(
+      .pclk(ov7670_pclk),
+    .vsync(ov7670_vsync),
+    .href(ov7670_href),
+    .d(ov7670_data),
+    .addr(wraddress),
+    .dout(wrdata),
+    .we(wren));
+	
+  frame_buffer Inst_frame_buffer(
+    .rdaddress(rdaddress),
+    .rdclock(clk_25_vga),
+    .q(rddata),
+    .wrclock(ov7670_pclk),
+    .wraddress(wraddress[16:0]),
+    .data(wrdata),
+    .wren(wren));
+
+
+  // create address generator
+  address_generator ag0(
+    .clk_25_vga(clk_25_vga),
+    .resend(resend),
+    .vga_ready(ready),
+    .vga_start_out(sop),
+    .vga_end_out(eop),
+    .rdaddress(rdaddress)
+  );
+  
+  assign pixel = rddata;
+  assign address = rdaddress;
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/clock_domain_fifo.qip b/src/5_Blur_Integration/clock_domain_fifo.qip
new file mode 100644
index 0000000..e9d0993
--- /dev/null
+++ b/src/5_Blur_Integration/clock_domain_fifo.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock_domain_fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_domain_fifo_bb.v"]
diff --git a/src/5_Blur_Integration/clock_domain_fifo.v b/src/5_Blur_Integration/clock_domain_fifo.v
new file mode 100644
index 0000000..98c27d8
--- /dev/null
+++ b/src/5_Blur_Integration/clock_domain_fifo.v
@@ -0,0 +1,168 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: clock_domain_fifo.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module clock_domain_fifo (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	wrfull);
+
+	input	[1:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[1:0]  q;
+	output	  rdempty;
+	output	  wrfull;
+
+	wire [1:0] sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire [1:0] q = sub_wire0[1:0];
+	wire  rdempty = sub_wire1;
+	wire  wrfull = sub_wire2;
+
+	dcfifo	dcfifo_component (
+				.data (data),
+				.rdclk (rdclk),
+				.rdreq (rdreq),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.q (sub_wire0),
+				.rdempty (sub_wire1),
+				.wrfull (sub_wire2),
+				.aclr (),
+				.eccstatus (),
+				.rdfull (),
+				.rdusedw (),
+				.wrempty (),
+				.wrusedw ());
+	defparam
+		dcfifo_component.intended_device_family = "Cyclone IV E",
+		dcfifo_component.lpm_hint = "MAXIMUM_DEPTH=128",
+		dcfifo_component.lpm_numwords = 128,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 2,
+		dcfifo_component.lpm_widthu = 7,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.rdsync_delaypipe = 4,
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON",
+		dcfifo_component.wrsync_delaypipe = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "2"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "2"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMUM_DEPTH=128"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
+// Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 2 0 data 0 0 2 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/src/5_Blur_Integration/clock_domain_fifo_bb.v b/src/5_Blur_Integration/clock_domain_fifo_bb.v
new file mode 100644
index 0000000..c3b0b9e
--- /dev/null
+++ b/src/5_Blur_Integration/clock_domain_fifo_bb.v
@@ -0,0 +1,126 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: clock_domain_fifo.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module clock_domain_fifo (
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	wrfull);
+
+	input	[1:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[1:0]  q;
+	output	  rdempty;
+	output	  wrfull;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "2"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "2"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMUM_DEPTH=128"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
+// Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
+// Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @data 0 0 2 0 data 0 0 2 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clock_domain_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/src/5_Blur_Integration/colour_detect.sv b/src/5_Blur_Integration/colour_detect.sv
new file mode 100644
index 0000000..567e33d
--- /dev/null
+++ b/src/5_Blur_Integration/colour_detect.sv
@@ -0,0 +1,60 @@
+module colour_detect(
+	input clk,
+	input [11:0] data_in,
+	input [3:0] upper_thresh,
+	input [16:0] address,
+	input sop,
+	output [11:0] data_out,
+	output [16:0] red_pixels
+	
+);
+
+	logic [3:0] r;
+	logic [3:0] g;
+	logic [3:0] b;
+	
+	assign r = data_in[11:8];
+	assign g = data_in[7:4];
+	assign b = data_in[3:0];
+	
+	
+	// Prototype a counter
+	logic [16:0] prev_address;
+	logic [16:0] red_pixel_count;
+	
+	// create an appropriate counter for red pixels
+	always_ff @(posedge clk) begin
+		prev_address <= address;
+		
+		if(sop) begin
+			red_pixel_count <= 0;
+		end
+		else if(prev_address != address) begin
+			
+			// increment red pixel count
+			if(is_red) begin
+				red_pixel_count <= red_pixel_count + 1;
+			end
+		end
+	end
+	
+	// signals based on thresholding
+	logic is_red;
+	assign is_red = (r > g) & (r > b) & (r >= upper_thresh);
+
+	// determine output based on colours
+	always_comb begin
+		// determine if r is dominant
+		if(is_red) begin
+			data_out = {4'b1111, 8'b00000000};
+		end	
+		else begin
+			data_out = 12'b000000000000;
+		end
+	end
+	
+	
+	assign red_pixels = red_pixel_count;
+	
+	
+endmodule
diff --git a/src/5_Blur_Integration/continuous_motor_control.sv b/src/5_Blur_Integration/continuous_motor_control.sv
new file mode 100644
index 0000000..7c7d5e7
--- /dev/null
+++ b/src/5_Blur_Integration/continuous_motor_control.sv
@@ -0,0 +1,54 @@
+/*
+This code allows for continuous commands to be send outwards
+as opposed to temporary commands.
+
+It will pulse reset for the activated controller
+*/
+
+
+module continous_motor_control
+(
+    input clk,
+    input [2:0] direction, // should be a 3 bit state
+    output forward_rst,
+    output reverse_rst,
+    output stop_rst
+);
+
+    // create a counter to wait approx every 83.886 ms
+    // assume a 50 Mhz clock
+    integer i = 0;
+    always_ff @(posedge clk) begin
+        i <= i + 1;
+    end
+
+    // signals to determine frequency of reset pulsing
+    logic [22:0] clks_per_100ms;
+    assign clks_per_100ms = 1 << 22;
+
+    always_comb begin
+        
+        forward_rst = 0;
+        reverse_rst = 0;
+        stop_rst = 0;
+
+        case (direction) 
+            3'b001 : begin 
+                forward_rst = (i%clks_per_100ms == 0) ? 1 : 0;
+            end
+            3'b011 : begin
+                reverse_rst = (i%clks_per_100ms == 0) ? 1 : 0;
+            end
+				3'b010 : begin
+					 stop_rst = (i%clks_per_100ms == 0) ? 1 : 0;
+				end
+				3'b000 : begin
+					stop_rst = (i%clks_per_100ms == 0) ? 1 : 0;
+				end
+            default : begin
+                stop_rst = (i%clks_per_100ms == 0) ? 1 : 0;
+            end
+        endcase
+    end
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/debounce.sv b/src/5_Blur_Integration/debounce.sv
new file mode 100644
index 0000000..00e27d0
--- /dev/null
+++ b/src/5_Blur_Integration/debounce.sv
@@ -0,0 +1,59 @@
+/*
+Debounce module debounces a given input.
+Delay is set to 50 us (based on a 50 MHz clock)
+*/
+
+module debounce #(
+  parameter DELAY_COUNTS = 2500     // For a 50MHz clock this is 50us and stuff
+) (
+    input clk, button,
+    output reg button_pressed
+);
+
+  initial button_pressed = 0;
+
+  // Use a synchronizer to synchronize `button`.
+  wire button_sync; // Output of the synchronizer. Input to your debounce logic.
+  synchroniser button_synchroniser (.clk(clk), .x(button), .y(button_sync));
+
+  // Note: Use the synchronized `button_sync` wire as the input signal to the debounce logic.
+  
+  // Create a register for the delay counts
+  reg [$clog2(DELAY_COUNTS):0] count = 0;
+  reg prev_button = 0;
+
+  // Set the count flip-flop:
+  always @(posedge clk) begin
+      if (button_sync != prev_button) begin
+        count <= 0;
+      end
+      else if (count == DELAY_COUNTS) begin
+        count <= count;
+      end
+      else begin
+        count <= count + 1; 
+      end
+  end
+
+  // Set the prev_button flip-flop:
+  always @(posedge clk) begin
+    if (button_sync != prev_button) begin
+      prev_button <= button_sync;
+    end
+    else begin
+      prev_button <= prev_button;
+    end
+  end
+
+  // Set the button_pressed flip-flop:
+  always @(posedge clk) begin
+    if (button_sync == prev_button && count == DELAY_COUNTS) begin
+      button_pressed <= prev_button;
+    end
+    else begin
+      button_pressed <= button_pressed; 
+    end
+  end
+
+endmodule
+
diff --git a/src/5_Blur_Integration/direction_fsm.sv b/src/5_Blur_Integration/direction_fsm.sv
new file mode 100644
index 0000000..85aa0c0
--- /dev/null
+++ b/src/5_Blur_Integration/direction_fsm.sv
@@ -0,0 +1,131 @@
+module direction_fsm #(
+    parameter FREQUENCY = 13,
+	 parameter TOO_CLOSE = 8'd30
+)(
+    input           		  clk,
+	 input logic [9:0] frequency_input, // frequency input
+	 input logic [4:0] threshold_frequency,
+	
+    input logic [7:0] distance, // ultrasonic input
+	 input logic [16:0] red_pixels,
+	 input logic [16:0] threshold_pixels,
+	 
+    output [2:0] direction
+);
+	
+	 logic red_stop_signal;
+	 assign red_stop_signal = (red_pixels > threshold_pixels);
+	 
+	 // add a delay to the distance calculation
+	 
+	// create a distance shift register
+	logic [7:0] distances [1:0];
+	
+	logic too_close;
+	always_ff @(posedge clk) begin
+		
+		// process through shift register
+		if(distance != distances[0]) begin
+			distances[1] <= distances[0];
+			distances[0] <= distance;
+		end
+
+	end
+	
+	// set a signal based on the data incoming
+	always_comb begin
+		if(distances[0] <= TOO_CLOSE && distances[1] <= TOO_CLOSE) begin
+			too_close = 1'b1;
+		end
+		else begin
+			too_close = 1'b0;
+		end
+	end
+	
+	
+	// create a shift register for the different microphone input values
+	logic [9:0] mic_inputs [3:0];
+	logic threshold_reached;
+	
+	// shift the values through the register
+	always_ff @(posedge clk) begin
+		if(frequency_input != frequency_input[0]) begin
+			mic_inputs[3] <= mic_inputs[2];
+			mic_inputs[2] <= mic_inputs[1];
+			mic_inputs[1] <= mic_inputs[0];
+			mic_inputs[0] <= frequency_input;
+		end
+	end
+	
+	// determine the thresholding reached status
+	always_comb begin
+		
+		threshold_reached = (mic_inputs[0] >= threshold_frequency) &
+								  (mic_inputs[1] >= threshold_frequency) &
+								  (mic_inputs[2] >= threshold_frequency) &
+								  (mic_inputs[3] >= threshold_frequency);
+	end
+	
+
+    // State typedef enum used here
+	 // Note that we specify the exact encoding that we want to use for each state
+    typedef enum logic [2:0] {
+        IDLE_BASE = 3'b000,
+        FORWARDS = 3'b001,
+        IDLE_TABLE = 3'b010,
+        BACKWARDS = 3'b011,
+        STOP = 3'b100
+    } state_type;
+
+    // create a 1 second delay that can be used to prevent the robot 
+    // from  instantly changing directions
+    integer i = 0;
+    localparam TIME_FOR_1s = 50000000;
+    always_ff @(posedge clk) begin
+        if(current_state != FORWARDS && current_state != BACKWARDS) begin
+            i <= 0;
+        end
+        else if (i < TIME_FOR_1s) begin 
+            i <= i + 1;
+        end
+    end
+
+    state_type current_state = IDLE_BASE, next_state;
+
+    // always_comb block for next state logic
+    always_comb begin
+        next_state = current_state;
+			
+		  case(current_state)
+            IDLE_BASE : begin
+                if(threshold_reached) begin
+                    next_state = FORWARDS;
+                end
+            end
+            IDLE_TABLE : begin
+                if(threshold_reached) begin
+                    next_state = BACKWARDS;
+                end
+            end
+            FORWARDS : begin
+                if((too_close && i >= TIME_FOR_1s) || (red_stop_signal)) begin // corresponds to two seconds at 50MHz
+                    next_state = IDLE_TABLE;
+                end
+            end
+            BACKWARDS : begin
+                if(too_close && i >= TIME_FOR_1s) begin
+                    next_state = IDLE_BASE;
+                end
+            end
+		  endcase
+    end
+
+    // always_ff for FSM state variable flip_flops
+    always_ff @(posedge clk) begin
+        current_state <= next_state;
+    end
+
+    // outputs
+    assign direction = current_state;
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/display.sv b/src/5_Blur_Integration/display.sv
new file mode 100644
index 0000000..d3c7d85
--- /dev/null
+++ b/src/5_Blur_Integration/display.sv
@@ -0,0 +1,92 @@
+module display (
+    input         clk,
+    input  [10:0] value,
+    output [6:0]  display0,
+    output [6:0]  display1,
+    output [6:0]  display2,
+    output [6:0]  display3
+);
+    /*** FSM Controller Code: ***/
+    enum { Initialise, Add3, Shift, Result } next_state, current_state = Initialise; // FSM states.
+    
+    logic init, add, done; // FSM outputs.
+
+    logic [3:0] count = 0; // Use this to count the 11 loop iterations.
+
+    /*** DO NOT MODIFY THE CODE ABOVE ***/
+
+
+
+    always_comb begin : double_dabble_fsm_next_state_logic
+        case (current_state)
+            Initialise: next_state = Add3;
+            Add3:       next_state = Shift;
+            Shift:      next_state = count == 10 ? Result : Add3;
+            Result:     next_state = Initialise;
+            default:    next_state = Initialise;
+        endcase
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_fsm_ff
+        current_state <= next_state;
+        if (current_state == Shift) begin
+            count <= count == 10 ? 0 : count + 1;
+        end
+    end
+
+    always_comb begin : double_dabble_fsm_output
+        init = 1'b0;
+        add = 1'b0;
+        done = 1'b0;
+        case (current_state) // Moore FSM
+            Initialise: init = 1'b1;
+            Add3:       add = 1'b1;
+            Result:     done = 1'b1;
+        endcase
+    end
+    
+
+
+    /*** DO NOT MODIFY THE CODE BELOW ***/
+    logic [3:0] digit0, digit1, digit2, digit3;
+
+    //// Seven-Segment Displays
+    seven_seg u_digit0 (.bcd(digit0), .segments(display0));
+    seven_seg u_digit1 (.bcd(digit1), .segments(display1));
+    seven_seg u_digit2 (.bcd(digit2), .segments(display2));
+    seven_seg u_digit3 (.bcd(digit3), .segments(display3));
+
+    // Algorithm RTL:  (completed no changes required - see dd_rtl.png for a representation of the code below but for 2 BCD digits.)
+    // essentially a 27-bit long, 1-bit wide shift-register, starting from the 11 input bits through to the 4 bits of each BCD digit (4*4=16, 16+11=27).
+    // We shift in the Shift state, add 3 to BCD digits greater than 4 in the Add3 state, and initialise the shift-register values in the Initialise state.
+    logic [3:0]  bcd0, bcd1, bcd2, bcd3; // Do NOT change.
+    logic [10:0] temp_value; // Do NOT change.
+
+    always_ff @(posedge clk) begin : double_dabble_shiftreg
+        if (init) begin // Initialise: set bcd values to 0 and temp_value to value.
+            {bcd3, bcd2, bcd1, bcd0, temp_value} <= {16'b0, value}; // A nice usage of the concat operator on both LHS and RHS!
+        end
+        else begin
+            if (add) begin // Add3: 3 is added to each bcd value greater than 4.
+                bcd0 <= bcd0 > 4 ? bcd0 + 3 : bcd0;  // Conditional operator.
+                bcd1 <= bcd1 > 4 ? bcd1 + 3 : bcd1;
+                bcd2 <= bcd2 > 4 ? bcd2 + 3 : bcd2;
+                bcd3 <= bcd3 > 4 ? bcd3 + 3 : bcd3;
+            end
+            else begin // Shift: essentially everything becomes a shift-register
+                {bcd3, bcd2, bcd1, bcd0, temp_value} <= {bcd3, bcd2, bcd1, bcd0, temp_value} << 1; // Concat operator makes this easy!
+            end
+        end
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_ff_output
+        // Need to 'flop' bcd values at the output so that intermediate calculations are not seen at the output.
+        if (done) begin  // Only take bcd values when the algorithm is done!
+            digit0 <= bcd0;
+            digit1 <= bcd1;
+            digit2 <= bcd2;
+            digit3 <= bcd3;
+        end
+    end
+
+endmodule
diff --git a/src/5_Blur_Integration/display_2digit.sv b/src/5_Blur_Integration/display_2digit.sv
new file mode 100644
index 0000000..6d8c370
--- /dev/null
+++ b/src/5_Blur_Integration/display_2digit.sv
@@ -0,0 +1,88 @@
+module display_2digit (
+    input         clk,
+    input  [10:0] value,
+    output [6:0]  display0,
+    output [6:0]  display1
+);
+    /*** FSM Controller Code: ***/
+    enum { Initialise, Add3, Shift, Result } next_state, current_state = Initialise; // FSM states.
+    
+    logic init, add, done; // FSM outputs.
+
+    logic [3:0] count = 0; // Use this to count the 11 loop iterations.
+
+    /*** DO NOT MODIFY THE CODE ABOVE ***/
+
+
+
+    always_comb begin : double_dabble_fsm_next_state_logic
+        case (current_state)
+            Initialise: next_state = Add3;
+            Add3:       next_state = Shift;
+            Shift:      next_state = count == 10 ? Result : Add3;
+            Result:     next_state = Initialise;
+            default:    next_state = Initialise;
+        endcase
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_fsm_ff
+        current_state <= next_state;
+        if (current_state == Shift) begin
+            count <= count == 10 ? 0 : count + 1;
+        end
+    end
+
+    always_comb begin : double_dabble_fsm_output
+        init = 1'b0;
+        add = 1'b0;
+        done = 1'b0;
+        case (current_state) // Moore FSM
+            Initialise: init = 1'b1;
+            Add3:       add = 1'b1;
+            Result:     done = 1'b1;
+        endcase
+    end
+    
+
+
+    /*** DO NOT MODIFY THE CODE BELOW ***/
+    logic [3:0] digit0, digit1, digit2, digit3;
+
+    //// Seven-Segment Displays
+    seven_seg u_digit0 (.bcd(digit0), .segments(display0));
+    seven_seg u_digit1 (.bcd(digit1), .segments(display1));
+
+    // Algorithm RTL:  (completed no changes required - see dd_rtl.png for a representation of the code below but for 2 BCD digits.)
+    // essentially a 27-bit long, 1-bit wide shift-register, starting from the 11 input bits through to the 4 bits of each BCD digit (4*4=16, 16+11=27).
+    // We shift in the Shift state, add 3 to BCD digits greater than 4 in the Add3 state, and initialise the shift-register values in the Initialise state.
+    logic [3:0]  bcd0, bcd1, bcd2, bcd3; // Do NOT change.
+    logic [10:0] temp_value; // Do NOT change.
+
+    always_ff @(posedge clk) begin : double_dabble_shiftreg
+        if (init) begin // Initialise: set bcd values to 0 and temp_value to value.
+            {bcd3, bcd2, bcd1, bcd0, temp_value} <= {16'b0, value}; // A nice usage of the concat operator on both LHS and RHS!
+        end
+        else begin
+            if (add) begin // Add3: 3 is added to each bcd value greater than 4.
+                bcd0 <= bcd0 > 4 ? bcd0 + 3 : bcd0;  // Conditional operator.
+                bcd1 <= bcd1 > 4 ? bcd1 + 3 : bcd1;
+                bcd2 <= bcd2 > 4 ? bcd2 + 3 : bcd2;
+                bcd3 <= bcd3 > 4 ? bcd3 + 3 : bcd3;
+            end
+            else begin // Shift: essentially everything becomes a shift-register
+                {bcd3, bcd2, bcd1, bcd0, temp_value} <= {bcd3, bcd2, bcd1, bcd0, temp_value} << 1; // Concat operator makes this easy!
+            end
+        end
+    end
+
+    always_ff @(posedge clk) begin : double_dabble_ff_output
+        // Need to 'flop' bcd values at the output so that intermediate calculations are not seen at the output.
+        if (done) begin  // Only take bcd values when the algorithm is done!
+            digit0 <= bcd0;
+            digit1 <= bcd1;
+            digit2 <= bcd2;
+            digit3 <= bcd3;
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/drive_motor.sv b/src/5_Blur_Integration/drive_motor.sv
new file mode 100644
index 0000000..11b9982
--- /dev/null
+++ b/src/5_Blur_Integration/drive_motor.sv
@@ -0,0 +1,65 @@
+module drive_motor(
+	
+	input CLOCK_50,
+	input [2:0] direction, // should be the state
+	input [2:0] speed,
+	output uart_out 		  // uart output
+);
+	
+	// each uart out module stored separately
+	logic back_uart_out;
+	logic forward_uart_out;
+	logic stop_uart_out;
+
+	// create reset signals
+	logic f_rst, b_rst, s_rst;
+	
+	continous_motor_control cmc (
+		.clk(CLOCK_50),
+		.direction(direction),
+		.forward_rst(f_rst),
+		.reverse_rst(b_rst),
+		.stop_rst(s_rst)
+	);
+	
+	forward fward (
+		 .clk(CLOCK_50),
+		 .rst(f_rst),
+		 .speed(speed),
+		 .uart_out(forward_uart_out),
+		 .ready()
+	);
+	
+	backwards back (
+		 .clk(CLOCK_50),
+		 .speed(speed),
+		 .rst(b_rst),
+		 .uart_out(back_uart_out),
+		 .ready()
+	);
+	
+	stop stop_sequence (
+		.clk(CLOCK_50),
+		.rst(s_rst),
+		.uart_out(stop_uart_out),
+		.ready()
+	);
+	
+	// always comb block to select what direction we want the robot to go
+	always_comb begin
+		
+		if(direction == 3'b001) 
+			begin
+				uart_out = forward_uart_out;
+			end
+		else if (direction == 3'b011)
+			begin
+				uart_out = back_uart_out;
+			end
+		else
+			begin
+				uart_out = stop_uart_out;
+			end
+	end	
+	
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/edge_detect.sv b/src/5_Blur_Integration/edge_detect.sv
new file mode 100644
index 0000000..34dd3d3
--- /dev/null
+++ b/src/5_Blur_Integration/edge_detect.sv
@@ -0,0 +1,21 @@
+/*
+Module acts a a positive edge detection.
+It will take in an input signal and will output a logic
+value corresponding to whether or not there was a positive
+edge change in the last clock cycle.
+*/
+
+module edge_detect(
+    input           		  clk,
+    input           		  button,
+    output                button_edge
+);
+
+    // Rising edge detection block here!
+    logic button_q0 = 0;
+    always_ff @(posedge clk) begin : edge_detect
+        button_q0 <= button;
+    end : edge_detect
+    assign button_edge = (button > button_q0);
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/forward.sv b/src/5_Blur_Integration/forward.sv
new file mode 100644
index 0000000..29ffa19
--- /dev/null
+++ b/src/5_Blur_Integration/forward.sv
@@ -0,0 +1,112 @@
+import lcd_inst_pkg::*;
+
+module forward #(
+    parameter CLKS_PER_BIT = 50_000_000/115_200,
+    parameter BITS_N = 8,
+    parameter NUM_BYTES = 25
+    )(
+    input clk,
+    input rst,
+    input [2:0] speed,
+    output logic uart_out,
+    output logic ready         // Signal indicating the system is ready for a new command
+);
+    logic [4:0] byte_index = 0;
+    logic [4:0] next_byte_index = 0;
+
+    logic uart_valid;
+    logic [BITS_N-1:0] current_byte = 8'b0;
+
+    logic uart_ready;
+
+    // UART transmitter instance
+    uart_tx #(
+        .CLKS_PER_BIT(CLKS_PER_BIT),
+        .BITS_N(BITS_N)
+    ) uart (
+        .clk(clk),
+        .rst(rst),
+        .data_tx(current_byte),
+        .uart_out(uart_out),
+        .valid(uart_valid),
+        .ready(uart_ready)
+    );
+
+    // Hard-coded 25-byte JSON message: {"T":11,"L":164,"R":164}\n
+    logic [0:NUM_BYTES-1][7:0] json_data;
+    initial begin
+        json_data[0] = _OPEN_BRACE;
+        json_data[1] =_DOUBLE_QUOTE;
+        json_data[2] =_T;
+        json_data[3] =_DOUBLE_QUOTE;
+        json_data[4] =_COLON;
+        json_data[5] =_1;
+        json_data[6] =_COMMA;
+        json_data[7] =_DOUBLE_QUOTE;
+        json_data[8] =_L;
+        json_data[9] =_DOUBLE_QUOTE;
+        json_data[10] =_COLON;
+        json_data[11] =_0;
+        json_data[12] =_PERIOD;
+        json_data[13] =_5;
+        json_data[14] =_COMMA;
+        json_data[15] =_DOUBLE_QUOTE;
+        json_data[16] =_R;
+        json_data[17] =_DOUBLE_QUOTE;
+        json_data[18] =_COLON;
+        json_data[19] =_0;
+        json_data[20] =_PERIOD;
+        json_data[21] =_5;
+        json_data[22] =_CLOSE_BRACE;
+        json_data[23] =8'h0A;
+		json_data[24] =8'h0A; // new line character
+    end
+    
+    // map the speed control correctly
+    logic [7:0] ascii_speed;
+    speed_control_mapping scm (
+        .speed(speed),
+        .ascii_speed(ascii_speed)
+    );
+
+    localparam speed_index_0 = 13;
+    localparam speed_index_1 = 21;
+    // current byte based on byte index
+    always_comb begin
+
+        current_byte = json_data[byte_index];
+
+        // adjust the speed by the speed signal
+        if(byte_index == speed_index_0 || byte_index == speed_index_1) begin
+            current_byte = ascii_speed;
+        end
+
+    end
+	 
+    // Control logic to send the JSON string byte by byte
+    always_ff @(posedge clk) begin
+        if (rst)
+        begin
+            byte_index <= 0;
+            next_byte_index <= 0;
+            uart_valid <= 1'b0;
+        end 
+		else if (next_byte_index == NUM_BYTES) 
+			  begin
+				uart_valid <= 1'b0; //  we've reached the end so set valid low
+			  end
+        else if (uart_ready)
+        begin
+            if(next_byte_index < NUM_BYTES)
+					begin
+						 byte_index <= next_byte_index;
+						 uart_valid <= 1'b1;
+						 next_byte_index <= next_byte_index + 1;
+					end
+        end 
+    end
+
+    // Ready signal when all bytes have been sent, including the newline
+    assign ready = (byte_index == NUM_BYTES) && uart_ready && (!uart_valid);  // Only ready after the last byte is fully sent
+
+endmodule
diff --git a/src/5_Blur_Integration/frame_buffer.v b/src/5_Blur_Integration/frame_buffer.v
new file mode 100644
index 0000000..f4157b2
--- /dev/null
+++ b/src/5_Blur_Integration/frame_buffer.v
@@ -0,0 +1,104 @@
+// File digital_cam_impl1/frame_buffer.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// create a buffer to store pixels data for a frame of 320x240 pixels;
+// data for each pixel is 12 bits;
+// that is 76800 pixels; hence, address is represented on 17 bits 
+// (2^17 = 131072 > 76800);
+// Notes: 
+// 1) If we wanted to work with 640x480 pixels, that would require
+// an amount of embedded RAM that is not available on the Cyclone IV E of DE2-115;
+// 2) We create the buffer with 76800 by stacking-up two blocks
+// of 2^16 = 65536 addresses; 
+// no timescale needed
+
+module frame_buffer(
+input wire [11:0] data,
+input wire [16:0] rdaddress,
+input wire rdclock,
+input wire [16:0] wraddress,
+input wire wrclock,
+input wire wren,
+output reg [11:0] q
+);
+
+
+
+
+// read signals
+wire [11:0] q_top;
+wire [11:0] q_bottom;
+// write signals
+reg wren_top;
+reg wren_bottom;
+
+  my_frame_buffer_15to0 Inst_buffer_top(
+      .data(data[11:0]),
+    .rdaddress(rdaddress[15:0]),
+    .rdclock(rdclock),
+    .wraddress(wraddress[15:0]),
+    .wrclock(wrclock),
+    .wren(wren_top),
+    .q(q_top));
+
+  my_frame_buffer_15to0 Inst_buffer_bottom(
+      .data(data[11:0]),
+    .rdaddress(rdaddress[15:0]),
+    .rdclock(rdclock),
+    .wraddress(wraddress[15:0]),
+    .wrclock(wrclock),
+    .wren(wren_bottom),
+    .q(q_bottom));
+
+  always @(wraddress[16], wren) begin
+    case(wraddress[16])
+    1'b0 : begin
+      wren_top <= wren;
+      wren_bottom <= 1'b0;
+    end
+    1'b1 : begin
+      wren_top <= 1'b0;
+      wren_bottom <= wren;
+    end
+    default : begin
+      wren_top <= 1'b0;
+      wren_bottom <= 1'b0;
+    end
+    endcase
+  end
+
+  always @(rdaddress[16], q_top, q_bottom) begin
+    case(rdaddress[16])
+    1'b0 : begin
+      q <= q_top;
+    end
+    1'b1 : begin
+      q <= q_bottom;
+    end
+    default : begin
+      q <= 12'b000000000000;
+    end
+    endcase
+  end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/i2c_sender.v b/src/5_Blur_Integration/i2c_sender.v
new file mode 100644
index 0000000..cae8272
--- /dev/null
+++ b/src/5_Blur_Integration/i2c_sender.v
@@ -0,0 +1,197 @@
+// File digital_cam_impl1/i2c_sender.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// this is an entity used to sSend the commands to the OV7670 camera module
+// over an I2C-like interface
+// no timescale needed
+
+module i2c_sender(
+input wire clk,
+inout reg siod,
+output reg sioc,
+output reg taken,
+input wire send,
+input wire [7:0] id,
+input wire [7:0] reg_,
+input wire [7:0] value
+);
+
+
+
+
+reg [7:0] divider = 8'b00000001;  // this value gives a 254 cycle pause before the initial frame is sent
+reg [31:0] busy_sr = 1'b0;
+reg [31:0] data_sr = 1'b1;
+
+  always @(busy_sr, data_sr[31]) begin
+    if(busy_sr[11:10] == 2'b10 || busy_sr[20:19] == 2'b10 || busy_sr[29:28] == 2'b10) begin
+      siod <= 1'bZ;
+    end
+    else begin
+      siod <= data_sr[31];
+    end
+  end
+
+  always @(posedge clk) begin
+    taken <= 1'b0;
+    if(busy_sr[31] == 1'b0) begin
+      sioc <= 1'b1;
+      if(send == 1'b1) begin
+        if(divider == 8'b00000000) begin
+          data_sr <= {3'b100,id,1'b0,reg_,1'b0,value,1'b0,2'b01};
+          busy_sr <= {3'b111,9'b111111111,9'b111111111,9'b111111111,2'b11};
+          taken <= 1'b1;
+        end
+        else begin
+          divider <= divider + 1;
+          // this only happens on powerup
+        end
+      end
+    end
+    else begin
+      case({busy_sr[32 - 1:32 - 3],busy_sr[2:0]})
+      {3'b111,3'b111} : begin // start seq #1
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b1;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b1;
+        end
+        endcase
+      end
+      {3'b111,3'b110} : begin // start seq #2
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b1;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b1;
+        end
+        endcase
+      end
+      {3'b111,3'b100} : begin // start seq #3
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b0;
+        end
+        2'b01 : begin
+          sioc <= 1'b0;
+        end
+        2'b10 : begin
+          sioc <= 1'b0;
+        end
+        default : begin
+          sioc <= 1'b0;
+        end
+        endcase
+      end
+      {3'b110,3'b000} : begin // end seq #1
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b0;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b1;
+        end
+        endcase
+      end
+      {3'b100,3'b000} : begin // end seq #2
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b1;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b1;
+        end
+        endcase
+      end
+      {3'b000,3'b000} : begin // Idle
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b1;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b1;
+        end
+        endcase
+      end
+      default : begin
+        case(divider[7:6])
+        2'b00 : begin
+          sioc <= 1'b0;
+        end
+        2'b01 : begin
+          sioc <= 1'b1;
+        end
+        2'b10 : begin
+          sioc <= 1'b1;
+        end
+        default : begin
+          sioc <= 1'b0;
+        end
+        endcase
+      end
+      endcase
+      if(divider == 8'b11111111) begin
+        busy_sr <= {busy_sr[32 - 2:0],1'b0};
+        data_sr <= {data_sr[32 - 2:0],1'b1};
+        divider <= {8{1'b0}};
+      end
+      else begin
+        divider <= divider + 1;
+      end
+    end
+  end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/json_command_sender.sv b/src/5_Blur_Integration/json_command_sender.sv
new file mode 100644
index 0000000..f319c5d
--- /dev/null
+++ b/src/5_Blur_Integration/json_command_sender.sv
@@ -0,0 +1,112 @@
+import lcd_inst_pkg::*;
+
+module json_command_sender #(
+    parameter CLKS_PER_BIT = 50_000_000/115_200,
+    parameter BITS_N = 8,
+    parameter NUM_BYTES = 25
+    )(
+    input clk,
+    input rst,
+    input logic [3:0] speed,
+    output logic uart_out,
+    output logic ready         // Signal indicating the system is ready for a new command
+);
+    logic [4:0] byte_index = 0;
+    logic [4:0] next_byte_index = 0;
+
+    logic uart_valid;
+    logic [BITS_N-1:0] current_byte = 8'b0;
+
+    logic uart_ready;
+
+    // UART transmitter instance
+    uart_tx #(
+        .CLKS_PER_BIT(CLKS_PER_BIT),
+        .BITS_N(BITS_N)
+    ) uart (
+        .clk(clk),
+        .rst(rst),
+        .data_tx(current_byte),
+        .uart_out(uart_out),
+        .valid(uart_valid),
+        .ready(uart_ready)
+    );
+
+    // Hard-coded 25-byte JSON message: {"T":11,"L":164,"R":164}\n
+    logic [0:NUM_BYTES-1][7:0] json_data;
+    initial begin
+        json_data[0] = _OPEN_BRACE;
+        json_data[1] =_DOUBLE_QUOTE;
+        json_data[2] =_T;
+        json_data[3] =_DOUBLE_QUOTE;
+        json_data[4] =_COLON;
+        json_data[5] =_1;
+        json_data[6] =_COMMA;
+        json_data[7] =_DOUBLE_QUOTE;
+        json_data[8] =_L;
+        json_data[9] =_DOUBLE_QUOTE;
+        json_data[10] =_COLON;
+        json_data[11] =_0;
+        json_data[12] =_PERIOD;
+        json_data[13] =_5;
+        json_data[14] =_COMMA;
+        json_data[15] =_DOUBLE_QUOTE;
+        json_data[16] =_R;
+        json_data[17] =_DOUBLE_QUOTE;
+        json_data[18] =_COLON;
+        json_data[19] =_0;
+        json_data[20] =_PERIOD;
+        json_data[21] =_5;
+        json_data[22] =_CLOSE_BRACE;
+        json_data[23] =8'h0A;
+		json_data[24] =8'h0A; // new line character
+    end
+
+    // map the speed control correctly
+    logic [7:0] ascii_speed;
+    speed_control_mapping scm (
+        .speed(speed),
+        .ascii_speed(ascii_speed)
+    );
+
+    localparam speed_index_0 = 13;
+    localparam speed_index_1 = 21;
+    // current byte based on byte index
+    always_comb begin
+
+        current_byte = json_data[byte_index];
+
+        // adjust the speed by the speed signal
+        if(byte_index == speed_index_0 || byte_index == speed_index_1) begin
+            current_byte = ascii_speed;
+        end
+
+    end
+	 
+    // Control logic to send the JSON string byte by byte
+    always_ff @(posedge clk) begin
+        if (rst)
+        begin
+            byte_index <= 0;
+            next_byte_index <= 0;
+            uart_valid <= 1'b0;
+        end 
+		else if (next_byte_index == NUM_BYTES) 
+			  begin
+				uart_valid <= 1'b0; //  we've reached the end so set valid low
+			  end
+        else if (uart_ready)
+        begin
+            if(next_byte_index < NUM_BYTES)
+					begin
+						 byte_index <= next_byte_index;
+						 uart_valid <= 1'b1;
+						 next_byte_index <= next_byte_index + 1;
+					end
+        end 
+    end
+
+    // Ready signal when all bytes have been sent, including the newline
+    assign ready = (byte_index == NUM_BYTES) && uart_ready && (!uart_valid);  // Only ready after the last byte is fully sent
+
+endmodule
diff --git a/src/5_Blur_Integration/json_command_sender_tb.sv b/src/5_Blur_Integration/json_command_sender_tb.sv
new file mode 100644
index 0000000..88234d1
--- /dev/null
+++ b/src/5_Blur_Integration/json_command_sender_tb.sv
@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+
+module json_command_sender_tb;
+
+    localparam CLKS_PER_BIT = 50_000_000/115_200;
+    localparam BITS_N = 8;
+
+    // Clock and reset signals
+    logic clk;
+    logic rst;
+    logic uart_out;
+    logic ready;
+
+    // Instantiate the DUT (Device Under Test)
+    json_command_sender #(
+    .CLKS_PER_BIT(CLKS_PER_BIT),
+    .BITS_N(BITS_N),
+    .NUM_BYTES(25)
+    ) uut (
+        .clk(clk),
+        .rst(rst),
+        .uart_out(uart_out),
+        .ready(ready)
+    );
+
+    // Clock generation
+    initial clk = 0;
+    always #10 clk = ~clk; // 50 MHz clock (20 ns period)
+
+    // Simulation procedure
+    initial begin
+
+        // Apply reset
+        rst = 1;
+        #50;
+        rst = 0;
+		  
+        // End of simulation
+        wait(ready) begin
+				#1000;
+				rst = 1;
+				#50;
+				rst = 0;
+        end
+		  
+		  wait (ready) begin
+				#50;
+				$display("Transmission complete.");
+            $finish;
+		  end
+    end
+	 
+	 
+
+    // Monitor the UART output
+    always @(posedge clk) begin
+        if (!rst) begin
+            $display("Sending byte: %h at time %t", uut.current_byte, $time);
+        end
+    end
+
+endmodule
diff --git a/src/5_Blur_Integration/lcd_inst_pkg.sv b/src/5_Blur_Integration/lcd_inst_pkg.sv
new file mode 100644
index 0000000..af6ff15
--- /dev/null
+++ b/src/5_Blur_Integration/lcd_inst_pkg.sv
@@ -0,0 +1,146 @@
+/*
+ *  Commands for the LCD controller.
+ *    Format: bit-8 is the Memory Address for LCD controller (this is also = RS).
+ *         bits 7:0 ASCII charater code (RS=1) or control code (RS=0). 
+ */
+package lcd_inst_pkg;
+    // verilator lint_off UNUSEDPARAM
+    /** Control Commands **/
+
+    // Clear Display
+    localparam logic [8:0] CLEAR_DISPLAY        = (9'h001);
+    // Return Home
+    localparam logic [8:0] RETURN_HOME          = (9'h002);
+    //Entry Mode 
+    localparam logic [8:0] ENTRY_DIR_RIGHT      = (9'h006);
+    localparam logic [8:0] ENTRY_DIR_LEFT       = (9'h004);
+    localparam logic [8:0] ENTRY_SHIFT_ENABLE   = (9'h005);
+    localparam logic [8:0] ENTRY_SHIFT_DISABLE  = (9'h004);
+
+    // Display ON/OFF Control
+    localparam logic [8:0] DISPLAY_ON           = (9'h00C);
+    localparam logic [8:0] CURSOR_ON            = (9'h00E);
+    localparam logic [8:0] CURSOR_BLINK_ON      = (9'h00F);
+
+    localparam logic [8:0] DISPLAY_OFF          = (9'h008);
+
+    localparam logic [8:0] CURSOR_OFF           = (9'h00C); //equivalent to DISPLAY_ON
+    localparam logic [8:0] CURSOR_BLINK_OFF     = (9'h00E); //equivalent to CURSOR_ON
+
+    // Cursor/Display Shift
+    // cause the entire display to move to left or right (the origin of the display is also changed)
+    localparam logic [8:0] DISPLAY_SHIFT_RIGHT  = (9'h01C);
+    localparam logic [8:0] DISPLAY_SHIFT_LEFT   = (9'h018);
+    // move the cursor to left or right
+    localparam logic [8:0] CURSOR_SHIFT_RIGHT   = (9'h014);
+    localparam logic [8:0] CURSOR_SHIFT_LEFT    = (9'h010);
+
+    /** Commands to Write ASCII Characters **/
+
+    // Numeric characters (0-9)
+    localparam logic [7:0] _0 = {8'd48};
+    localparam logic [7:0] _1 = {8'd49};
+    localparam logic [7:0] _2 = {8'd50};
+    localparam logic [7:0] _3 = {8'd51};
+    localparam logic [7:0] _4 = {8'd52};
+    localparam logic [7:0] _5 = {8'd53};
+    localparam logic [7:0] _6 = {8'd54};
+    localparam logic [7:0] _7 = {8'd55};
+    localparam logic [7:0] _8 = {8'd56};
+    localparam logic [7:0] _9 = {8'd57};
+
+    // Uppercase alphabetic characters (A-Z)
+    localparam logic [7:0] _A = {8'd65};
+    localparam logic [7:0] _B = {8'd66};
+    localparam logic [7:0] _C = {8'd67};
+    localparam logic [7:0] _D = {8'd68};
+    localparam logic [7:0] _E = {8'd69};
+    localparam logic [7:0] _F = {8'd70};
+    localparam logic [7:0] _G = {8'd71};
+    localparam logic [7:0] _H = {8'd72};
+    localparam logic [7:0] _I = {8'd73};
+    localparam logic [7:0] _J = {8'd74};
+    localparam logic [7:0] _K = {8'd75};
+    localparam logic [7:0] _L = {8'd76};
+    localparam logic [7:0] _M = {8'd77};
+    localparam logic [7:0] _N = {8'd78};
+    localparam logic [7:0] _O = {8'd79};
+    localparam logic [7:0] _P = {8'd80};
+    localparam logic [7:0] _Q = {8'd81};
+    localparam logic [7:0] _R = {8'd82};
+    localparam logic [7:0] _S = {8'd83};
+    localparam logic [7:0] _T = {8'd84};
+    localparam logic [7:0] _U = {8'd85};
+    localparam logic [7:0] _V = {8'd86};
+    localparam logic [7:0] _W = {8'd87};
+    localparam logic [7:0] _X = {8'd88};
+    localparam logic [7:0] _Y = {8'd89};
+    localparam logic [7:0] _Z = {8'd90};
+
+    // Lowercase alphabetic characters (a-z)
+    localparam logic [7:0] _a = {8'd97};
+    localparam logic [7:0] _b = {8'd98};
+    localparam logic [7:0] _c = {8'd99};
+    localparam logic [7:0] _d = {8'd100};
+    localparam logic [7:0] _e = {8'd101};
+    localparam logic [7:0] _f = {8'd102};
+    localparam logic [7:0] _g = {8'd103};
+    localparam logic [7:0] _h = {8'd104};
+    localparam logic [7:0] _i = {8'd105};
+    localparam logic [7:0] _j = {8'd106};
+    localparam logic [7:0] _k = {8'd107};
+    localparam logic [7:0] _l = {8'd108};
+    localparam logic [7:0] _m = {8'd109};
+    localparam logic [7:0] _n = {8'd110};
+    localparam logic [7:0] _o = {8'd111};
+    localparam logic [7:0] _p = {8'd112};
+    localparam logic [7:0] _q = {8'd113};
+    localparam logic [7:0] _r = {8'd114};
+    localparam logic [7:0] _s = {8'd115};
+    localparam logic [7:0] _t = {8'd116};
+    localparam logic [7:0] _u = {8'd117};
+    localparam logic [7:0] _v = {8'd118};
+    localparam logic [7:0] _w = {8'd119};
+    localparam logic [7:0] _x = {8'd120};
+    localparam logic [7:0] _y = {8'd121};
+    localparam logic [7:0] _z = {8'd122};
+
+    // Special characters
+    localparam logic [7:0] _SPACE         = { 8'd32};
+    localparam logic [7:0] _EXCLAMATION   = { 8'd33}; // !
+    localparam logic [7:0] _DOUBLE_QUOTE  = { 8'd34}; // "
+    localparam logic [7:0] _HASH          = { 8'd35}; // #
+    localparam logic [7:0] _DOLLAR        = { 8'd36}; // $
+    localparam logic [7:0] _PERCENT       = { 8'd37}; // %
+    localparam logic [7:0] _AMPERSAND     = { 8'd38}; // &
+    localparam logic [7:0] _SINGLE_QUOTE  = { 8'd39}; // '
+    localparam logic [7:0] _OPEN_PAREN    = { 8'd40}; // (
+    localparam logic [7:0] _CLOSE_PAREN   = { 8'd41}; // )
+    localparam logic [7:0] _ASTERISK      = { 8'd42}; // *
+    localparam logic [7:0] _PLUS          = { 8'd43}; // +
+    localparam logic [7:0] _COMMA         = { 8'd44}; // ,
+    localparam logic [7:0] _MINUS         = { 8'd45}; // -
+    localparam logic [7:0] _PERIOD        = { 8'd46}; // .
+    localparam logic [7:0] _SLASH         = { 8'd47}; // /
+    localparam logic [7:0] _COLON         = { 8'd58}; // :
+    localparam logic [7:0] _SEMICOLON     = { 8'd59}; // ;
+    localparam logic [7:0] _LESS_THAN     = { 8'd60}; // <
+    localparam logic [7:0] _EQUALS        = { 8'd61}; // =
+    localparam logic [7:0] _GREATER_THAN  = { 8'd62}; // >
+    localparam logic [7:0] _QUESTION      = { 8'd63}; // ?
+    localparam logic [7:0] _AT            = { 8'd64}; // @
+    localparam logic [7:0] _OPEN_BRACKET  = { 8'd91}; // [
+    localparam logic [7:0] _BACKSLASH     = { 8'd92}; // \
+    localparam logic [7:0] _CLOSE_BRACKET = { 8'd93}; // ]
+    localparam logic [7:0] _CARET         = { 8'd94}; // ^
+    localparam logic [7:0] _UNDERSCORE    = { 8'd95}; // _
+    localparam logic [7:0] _BACKTICK      = { 8'd96}; // `
+    localparam logic [7:0] _OPEN_BRACE    = { 8'd123}; // {
+    localparam logic [7:0] _PIPE          = { 8'd124}; // |
+    localparam logic [7:0] _CLOSE_BRACE   = { 8'd125}; // }
+    localparam logic [7:0] _TILDE         = { 8'd126}; // ~
+
+    // verilator lint_on UNUSEDPARAM
+
+endpackage
+
diff --git a/src/5_Blur_Integration/motors.qpf b/src/5_Blur_Integration/motors.qpf
new file mode 100644
index 0000000..705896b
--- /dev/null
+++ b/src/5_Blur_Integration/motors.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 08:01:25  October 15, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "08:01:25  October 15, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "top_level_motor_driver"
diff --git a/src/5_Blur_Integration/my_altpll.v b/src/5_Blur_Integration/my_altpll.v
new file mode 100644
index 0000000..f9aea22
--- /dev/null
+++ b/src/5_Blur_Integration/my_altpll.v
@@ -0,0 +1,317 @@
+// File digital_cam_impl1/my_altpll.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+// ============================================================
+// File Name: my_altpll.vhd
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+// no timescale needed
+
+module my_altpll(
+input wire inclk0,
+output wire c0,
+output wire c1
+);
+
+
+
+
+wire [4:0] sub_wire0;
+wire sub_wire1;
+wire sub_wire2;
+wire sub_wire3;
+wire [1:0] sub_wire4;
+wire [0:0] sub_wire5_bv;
+wire [0:0] sub_wire5;
+
+  assign sub_wire5_bv[0:0] = 1'b0;
+  assign sub_wire5 = sub_wire5_bv;
+  assign sub_wire2 = sub_wire0[1];
+  assign sub_wire1 = sub_wire0[0];
+  assign c0 = sub_wire1;
+  assign c1 = sub_wire2;
+  assign sub_wire3 = inclk0;
+  assign sub_wire4 = {sub_wire5[0:0],sub_wire3};
+  altpll altpll_component(
+      .inclk(sub_wire4),
+      .clk(sub_wire0));
+
+  defparam
+    altpll_component.bandwidth_type = "AUTO",
+    altpll_component.clk0_divide_by = 1,
+    altpll_component.clk0_duty_cycle = 50,
+    altpll_component.clk0_multiply_by = 1,
+    altpll_component.clk0_phase_shift = "0",
+    altpll_component.clk1_divide_by = 2,
+    altpll_component.clk1_duty_cycle = 50,
+    altpll_component.clk1_multiply_by = 1,
+    altpll_component.clk1_phase_shift = 0,
+    altpll_component.compensate_clock = "CLK0",
+    altpll_component.inclk0_input_frequency = 20000,
+    altpll_component.intended_device_family = "Cyclone IV E",
+    altpll_component.lpm_hint = "CBX_MODULE_PREFIX=my_altpll",
+    altpll_component.lpm_type = "altpll",
+    altpll_component.operation_mode = "NORMAL",
+    altpll_component.pll_type = "AUTO",
+    altpll_component.port_activeclock = "PORT_UNUSED",
+    altpll_component.port_areset = "PORT_UNUSED",
+    altpll_component.port_clkbad0 = "PORT_UNUSED",
+    altpll_component.port_clkbad1 = "PORT_UNUSED",
+    altpll_component.port_clkloss = "PORT_UNUSED",
+    altpll_component.port_clkswitch = "PORT_UNUSED",
+    altpll_component.port_configupdate = "PORT_UNUSED",
+    altpll_component.port_fbin = "PORT_UNUSED",
+    altpll_component.port_inclk0 = "PORT_USED",
+    altpll_component.port_inclk1 = "PORT_UNUSED",
+    altpll_component.port_locked = "PORT_UNUSED",
+    altpll_component.port_pfdena = "PORT_UNUSED",
+    altpll_component.port_phasecounterselect = "PORT_UNUSED",
+    altpll_component.port_phasedone = "PORT_UNUSED",
+    altpll_component.port_phasestep = "PORT_UNUSED",
+    altpll_component.port_phaseupdown = "PORT_UNUSED",
+    altpll_component.port_pllena = "PORT_UNUSED",
+    altpll_component.port_scanaclr = "PORT_UNUSED",
+    altpll_component.port_scanclk = "PORT_UNUSED",
+    altpll_component.port_scanclkena = "PORT_UNUSED",
+    altpll_component.port_scandata = "PORT_UNUSED",
+    altpll_component.port_scandataout = "PORT_UNUSED",
+    altpll_component.port_scandone = "PORT_UNUSED",
+    altpll_component.port_scanread = "PORT_UNUSED",
+    altpll_component.port_scanwrite = "PORT_UNUSED",
+    altpll_component.port_clk0 = "PORT_USED",
+    altpll_component.port_clk1 = "PORT_USED",
+    altpll_component.port_clk2 = "PORT_UNUSED",
+    altpll_component.port_clk3 = "PORT_UNUSED",
+    altpll_component.port_clk4 = "PORT_UNUSED",
+    altpll_component.port_clk5 = "PORT_UNUSED",
+    altpll_component.port_clkena0 = "PORT_UNUSED",
+    altpll_component.port_clkena1 = "PORT_UNUSED",
+    altpll_component.port_clkena2 = "PORT_UNUSED",
+    altpll_component.port_clkena3 = "PORT_UNUSED",
+    altpll_component.port_clkena4 = "PORT_UNUSED",
+    altpll_component.port_clkena5 = "PORT_UNUSED",
+    altpll_component.port_extclk0 = "PORT_UNUSED",
+    altpll_component.port_extclk1 = "PORT_UNUSED",
+    altpll_component.port_extclk2 = "PORT_UNUSED",
+    altpll_component.port_extclk3 = "PORT_UNUSED",
+    altpll_component.width_clock = 5;
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "my_altpll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll.vhd TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_altpll_inst.vhd FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
+
+endmodule
diff --git a/src/5_Blur_Integration/my_frame_buffer_15to0.v b/src/5_Blur_Integration/my_frame_buffer_15to0.v
new file mode 100644
index 0000000..1d2a5b9
--- /dev/null
+++ b/src/5_Blur_Integration/my_frame_buffer_15to0.v
@@ -0,0 +1,201 @@
+// File digital_cam_impl1/my_frame_buffer_15to0.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+// ============================================================
+// File Name: my_frame_buffer_15to0.vhd
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+// no timescale needed
+
+module my_frame_buffer_15to0(
+input wire [11:0] data,
+input wire [15:0] rdaddress,
+input wire rdclock,
+input wire [15:0] wraddress,
+input wire wrclock,
+input wire wren,
+output wire [11:0] q
+);
+
+
+
+
+wire [11:0] sub_wire0;
+
+  assign q = sub_wire0[11:0];
+  altsyncram altsyncram_component(
+      .address_a(wraddress),
+    .clock0(wrclock),
+    .data_a(data),
+    .wren_a(wren),
+    .address_b(rdaddress),
+    .clock1(rdclock),
+    .q_b(sub_wire0));
+
+    defparam
+      altsyncram_component.address_aclr_b ="NONE",
+      altsyncram_component.address_reg_b ="CLOCK1",
+      altsyncram_component.clock_enable_input_a ="BYPASS",
+      altsyncram_component.clock_enable_input_b ="BYPASS",
+      altsyncram_component.clock_enable_output_b ="BYPASS",
+      altsyncram_component.intended_device_family = "Cyclone IV E",
+      altsyncram_component.lpm_type = "altsyncram",
+      altsyncram_component.numwords_a = 65536,
+      altsyncram_component.numwords_b = 65536,
+      altsyncram_component.operation_mode = "DUAL_PORT",
+      altsyncram_component.outdata_aclr_b = "NONE",
+      altsyncram_component.outdata_reg_b = "UNREGISTERED",
+      altsyncram_component.power_up_uninitialized = "FALSE",
+      altsyncram_component.widthad_a = 16,
+      altsyncram_component.widthad_b = 16,
+      altsyncram_component.width_a = 12,
+      altsyncram_component.width_b = 12,
+      altsyncram_component.width_byteena_a = 1;
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "1"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "786432"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "12"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "12"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "12"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "12"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "65536"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "12"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
+// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 16 0 INPUT NODEFVAL "rdaddress[15..0]"
+// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+// Retrieval info: USED_PORT: wraddress 0 0 16 0 INPUT NODEFVAL "wraddress[15..0]"
+// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 16 0 wraddress 0 0 16 0
+// Retrieval info: CONNECT: @address_b 0 0 16 0 rdaddress 0 0 16 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 12 0 data 0 0 12 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 12 0 @q_b 0 0 12 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_frame_buffer_15to0.vhd TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_frame_buffer_15to0.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_frame_buffer_15to0.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_frame_buffer_15to0.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL my_frame_buffer_15to0_inst.vhd FALSE
+// Retrieval info: LIB_FILE: altera_mf
+
+endmodule
diff --git a/src/5_Blur_Integration/nbit_synchroniser.sv b/src/5_Blur_Integration/nbit_synchroniser.sv
new file mode 100644
index 0000000..4440e11
--- /dev/null
+++ b/src/5_Blur_Integration/nbit_synchroniser.sv
@@ -0,0 +1,17 @@
+module nbit_synchroniser #(
+	parameter N = 2)(
+	input clk,
+    input x_valid,
+	input [N - 1:0]x,
+	output [N - 1:0] y);
+
+    reg [N - 1:0] x_q0, x_q1;
+    always @(posedge clk)
+    begin
+        if(x_valid) begin
+            x_q0 <= x;    // Flip-flop #1
+        end
+        x_q1 <= x_q0; // Flip-flop #2
+    end
+    assign y = x_q1;
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/ov7670_capture.v b/src/5_Blur_Integration/ov7670_capture.v
new file mode 100644
index 0000000..e0b344d
--- /dev/null
+++ b/src/5_Blur_Integration/ov7670_capture.v
@@ -0,0 +1,118 @@
+// File digital_cam_impl1/ov7670_capture.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// Captures the pixels data of each frame coming from the OV7670 camera and 
+// Stores them in block RAM
+// The length of href controls how often pixels are captive - (2 downto 0) stores
+// one pixel every 4 cycles.
+// "line" is used to control how often data is captured. In this case every forth 
+// line
+// no timescale needed
+
+module ov7670_capture(
+input wire pclk,
+input wire vsync,
+input wire href,
+input wire [7:0] d,
+output wire [16:0] addr,
+output wire [11:0] dout,
+output wire we
+);
+
+
+
+
+reg [15:0] d_latch = 1'b0;
+reg [16:0] address = 1'b0;
+reg [1:0] line = 1'b0;
+reg [6:0] href_last = 1'b0;
+reg we_reg = 1'b0;
+reg href_hold = 1'b0;
+reg latched_vsync = 1'b0;
+reg latched_href = 1'b0;
+reg [7:0] latched_d = 1'b0;
+
+  assign addr = address;
+  assign we = we_reg;
+  assign dout = {d_latch[15:12],d_latch[10:7],d_latch[4:1]};
+  always @(posedge pclk) begin
+    if(we_reg == 1'b1) begin
+      address <= (address) + 1;
+    end
+    // This is a bit tricky href starts a pixel transfer that takes 3 cycles
+    //        Input   | state after clock tick   
+    //         href   | wr_hold    d_latch           dout                we address  address_next
+    // cycle -1  x    |    xx      xxxxxxxxxxxxxxxx  xxxxxxxxxxxx  x   xxxx     xxxx
+    // cycle 0   1    |    x1      xxxxxxxxRRRRRGGG  xxxxxxxxxxxx  x   xxxx     addr
+    // cycle 1   0    |    10      RRRRRGGGGGGBBBBB  xxxxxxxxxxxx  x   addr     addr
+    // cycle 2   x    |    0x      GGGBBBBBxxxxxxxx  RRRRGGGGBBBB  1   addr     addr+1
+    // detect the rising edge on href - the start of the scan line
+    if(href_hold == 1'b0 && latched_href == 1'b1) begin
+      case(line)
+      2'b00 : begin
+        line <= 2'b01;
+      end
+      2'b01 : begin
+        line <= 2'b10;
+      end
+      2'b10 : begin
+        line <= 2'b11;
+      end
+      default : begin
+        line <= 2'b00;
+      end
+      endcase
+    end
+    href_hold <= latched_href;
+    // capturing the data from the camera, 12-bit RGB
+    if(latched_href == 1'b1) begin
+      d_latch <= {d_latch[7:0],latched_d};
+    end
+    we_reg <= 1'b0;
+    // Is a new screen about to start (i.e. we have to restart capturing
+    if(latched_vsync == 1'b1) begin
+      address <= {17{1'b0}};
+      href_last <= {7{1'b0}};
+      line <= {2{1'b0}};
+    end
+    else begin
+      // If not, set the write enable whenever we need to capture a pixel
+      if(href_last[2] == 1'b1) begin
+        if(line[1] == 1'b1) begin
+          we_reg <= 1'b1;
+        end
+        href_last <= {7{1'b0}};
+      end
+      else begin
+        href_last <= {href_last[((6)) - 1:0],latched_href};
+      end
+    end
+  end
+
+  always @(negedge pclk) begin
+    latched_d <= d;
+    latched_href <= href;
+    latched_vsync <= vsync;
+  end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/ov7670_controller.v b/src/5_Blur_Integration/ov7670_controller.v
new file mode 100644
index 0000000..358d19f
--- /dev/null
+++ b/src/5_Blur_Integration/ov7670_controller.v
@@ -0,0 +1,77 @@
+// File digital_cam_impl1/ov7670_controller.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// Controller for the OV760 camera - transferes registers to the 
+// camera over an I2C like bus
+// no timescale needed
+
+module ov7670_controller(
+input wire clk,
+input wire resend,
+output wire config_finished,
+output wire sioc,
+inout wire siod,
+output wire reset,
+output wire pwdn,
+output wire xclk
+);
+
+
+
+
+reg sys_clk = 1'b0;
+wire [15:0] command;
+wire finished;
+wire taken;
+wire send;  // device write ID; see datasheet of camera module;
+parameter camera_address = 8'h42;
+
+  assign config_finished = finished;
+  assign send =  ~finished;
+  i2c_sender Inst_i2c_sender(
+      .clk(clk),
+    .taken(taken),
+    .siod(siod),
+    .sioc(sioc),
+    .send(send),
+    .id(camera_address),
+    .reg_(command[15:8]),
+    .value(command[7:0]));
+
+  assign reset = 1'b1;
+  // Normal mode
+  assign pwdn = 1'b0;
+  // Power device up
+  assign xclk = sys_clk;
+  ov7670_registers Inst_ov7670_registers(
+      .clk(clk),
+    .advance(taken),
+    .command(command),
+    .finished(finished),
+    .resend(resend));
+
+  always @(posedge clk) begin
+    sys_clk <=  ~sys_clk;
+  end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/ov7670_registers.v b/src/5_Blur_Integration/ov7670_registers.v
new file mode 100644
index 0000000..b3a92ec
--- /dev/null
+++ b/src/5_Blur_Integration/ov7670_registers.v
@@ -0,0 +1,278 @@
+// File digital_cam_impl1/ov7670_registers.vhd translated with vhd2vl v3.0 VHDL to Verilog RTL translator
+// vhd2vl settings:
+//  * Verilog Module Declaration Style: 2001
+
+// vhd2vl is Free (libre) Software:
+//   Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
+//     http://www.ocean-logic.com
+//   Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
+//   Modifications (C) 2010 Shankar Giri
+//   Modifications Copyright (C) 2002-2017 Larry Doolittle
+//     http://doolittle.icarus.com/~larry/vhd2vl/
+//   Modifications (C) 2017 Rodrigo A. Melo
+//
+//   vhd2vl comes with ABSOLUTELY NO WARRANTY.  Always check the resulting
+//   Verilog for correctness, ideally with a formal verification tool.
+//
+//   You are welcome to redistribute vhd2vl under certain conditions.
+//   See the license (GPLv2) file included with the source for details.
+
+// The result of translation follows.  Its copyright status should be
+// considered unchanged from the original VHDL.
+
+// register settings for the OV7670 camera (partially from OV7670.c
+// in the Linux Kernel)
+//
+// this is tricky; based on my experience, using an OV7670 camera module
+// has a LOT to do with how we set/program the camera's registers;
+// it seems that the register values here get it right; thanks to the guys
+// who managed to dig this up (consequence of the rather poor datasheet
+// from OmniVision): Mike Field, Christopher Wilson;
+// 
+// Notes:
+// 1) Regarding the WITH SELECT Statement:
+//      WITH sreg(sel) SELECT
+//           finished <= '1' when x"FFFF",
+//                       '0' when others;
+// This means the transfer is finished the first time sreg ends up as "FFFF",  
+// i.e. Need Sequential Addresses in the below case statements 
+// no timescale needed
+
+module ov7670_registers(
+input wire clk,
+input wire resend,
+input wire advance,
+output wire [15:0] command,
+output reg finished
+);
+
+
+
+
+reg [15:0] sreg;
+reg [7:0] address = 1'b0;
+
+  assign command = sreg;
+  always @(*) begin
+    case(sreg)
+      16'hFFFF : finished <= 1'b1;
+      default : finished <= 1'b0;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    if(resend == 1'b1) begin
+      address <= {8{1'b0}};
+    end
+    else if(advance == 1'b1) begin
+      address <= (address) + 1;
+    end
+    case(address)
+    8'h00 : begin
+      sreg <= 16'h1280;
+      // COM7   Reset
+    end
+    8'h01 : begin
+      sreg <= 16'h1280;
+      // COM7   Reset
+    end
+    8'h02 : begin
+      sreg <= 16'h1204;
+      // COM7   Size & RGB output
+    end
+    8'h03 : begin
+      sreg <= 16'h1100;
+      // CLKRC  Prescaler - Fin/(1+1)
+    end
+    8'h04 : begin
+      sreg <= 16'h0C00;
+      // COM3   Lots of stuff, enable scaling, all others off
+    end
+    8'h05 : begin
+      sreg <= 16'h3E00;
+      // COM14  PCLK scaling off
+    end
+    8'h06 : begin
+      sreg <= 16'h8C00;
+      // RGB444 Set RGB format
+    end
+    8'h07 : begin
+      sreg <= 16'h0400;
+      // COM1   no CCIR601
+    end
+    8'h08 : begin
+      sreg <= 16'h4010;
+      // COM15  Full 0-255 output, RGB 565
+    end
+    8'h09 : begin
+      sreg <= 16'h3a04;
+      // TSLB   Set UV ordering,  do not auto-reset window
+    end
+    8'h0A : begin
+      sreg <= 16'h1438;
+      // COM9  - AGC Celling
+    end
+    8'h0B : begin
+      sreg <= 16'h4f40;
+      //x"4fb3"; -- MTX1  - colour conversion matrix
+    end
+    8'h0C : begin
+      sreg <= 16'h5034;
+      //x"50b3"; -- MTX2  - colour conversion matrix
+    end
+    8'h0D : begin
+      sreg <= 16'h510C;
+      //x"5100"; -- MTX3  - colour conversion matrix
+    end
+    8'h0E : begin
+      sreg <= 16'h5217;
+      //x"523d"; -- MTX4  - colour conversion matrix
+    end
+    8'h0F : begin
+      sreg <= 16'h5329;
+      //x"53a7"; -- MTX5  - colour conversion matrix
+    end
+    8'h10 : begin
+      sreg <= 16'h5440;
+      //x"54e4"; -- MTX6  - colour conversion matrix
+    end
+    8'h11 : begin
+      sreg <= 16'h581e;
+      //x"589e"; -- MTXS  - Matrix sign and auto contrast
+    end
+    8'h12 : begin
+      sreg <= 16'h3dc0;
+      // COM13 - Turn on GAMMA and UV Auto adjust
+    end
+    8'h13 : begin
+      sreg <= 16'h1100;
+      // CLKRC  Prescaler - Fin/(1+1)
+    end
+    8'h14 : begin
+      sreg <= 16'h1711;
+      // HSTART HREF start (high 8 bits)
+    end
+    8'h15 : begin
+      sreg <= 16'h1861;
+      // HSTOP  HREF stop (high 8 bits)
+    end
+    8'h16 : begin
+      sreg <= 16'h32A4;
+      // HREF   Edge offset and low 3 bits of HSTART and HSTOP
+    end
+    8'h17 : begin
+      sreg <= 16'h1903;
+      // VSTART VSYNC start (high 8 bits)
+    end
+    8'h18 : begin
+      sreg <= 16'h1A7b;
+      // VSTOP  VSYNC stop (high 8 bits) 
+    end
+    8'h19 : begin
+      sreg <= 16'h030a;
+      // VREF   VSYNC low two bits
+    end
+    8'h1A : begin
+      sreg <= 16'h0e61;
+      // COM5(0x0E) 0x61
+    end
+    8'h1B : begin
+      sreg <= 16'h0f4b;
+      // COM6(0x0F) 0x4B 
+    end
+    8'h1C : begin
+      sreg <= 16'h1602;
+      //
+    end
+    8'h1D : begin
+      sreg <= 16'h1e37;
+      // MVFP (0x1E) 0x07  -- FLIP AND MIRROR IMAGE 0x3x
+    end
+    8'h1E : begin
+      sreg <= 16'h2102;
+    end
+    8'h1F : begin
+      sreg <= 16'h2291;
+    end
+    8'h20 : begin
+      sreg <= 16'h2907;
+    end
+    8'h21 : begin
+      sreg <= 16'h330b;
+    end
+    8'h22 : begin
+      sreg <= 16'h350b;
+    end
+    8'h23 : begin
+      sreg <= 16'h371d;
+    end
+    8'h24 : begin
+      sreg <= 16'h3871;
+    end
+    8'h25 : begin
+      sreg <= 16'h392a;
+    end
+    8'h26 : begin
+      sreg <= 16'h3c78;
+      // COM12 (0x3C) 0x78
+    end
+    8'h27 : begin
+      sreg <= 16'h4d40;
+    end
+    8'h28 : begin
+      sreg <= 16'h4e20;
+    end
+    8'h29 : begin
+      sreg <= 16'h6900;
+      // GFIX (0x69) 0x00
+    end
+    8'h2A : begin
+      sreg <= 16'h6b4a;
+    end
+    8'h2B : begin
+      sreg <= 16'h7410;
+    end
+    8'h2C : begin
+      sreg <= 16'h8d4f;
+    end
+    8'h2D : begin
+      sreg <= 16'h8e00;
+    end
+    8'h2E : begin
+      sreg <= 16'h8f00;
+    end
+    8'h2F : begin
+      sreg <= 16'h9000;
+    end
+    8'h30 : begin
+      sreg <= 16'h9100;
+    end
+    8'h31 : begin
+      sreg <= 16'h9600;
+    end
+    8'h32 : begin
+      sreg <= 16'h9a00;
+    end
+    8'h33 : begin
+      sreg <= 16'hb084;
+    end
+    8'h34 : begin
+      sreg <= 16'hb10c;
+    end
+    8'h35 : begin
+      sreg <= 16'hb20e;
+    end
+    8'h36 : begin
+      sreg <= 16'hb382;
+    end
+    8'h37 : begin
+      sreg <= 16'hb80a;
+    end
+    default : begin
+      sreg <= 16'hffff;
+    end
+    endcase
+  end
+
+
+endmodule
diff --git a/src/5_Blur_Integration/reset_pulser.sv b/src/5_Blur_Integration/reset_pulser.sv
new file mode 100644
index 0000000..1e6b77a
--- /dev/null
+++ b/src/5_Blur_Integration/reset_pulser.sv
@@ -0,0 +1,22 @@
+/*
+	
+	Pulses an output value every 
+*/
+
+module reset_pulser(
+
+	input clock_50,
+	output rst
+);
+
+	
+	// counts up to 2^27 - 1
+	// should take about 2.68 seconds
+	logic [26:0]i;
+	always_ff @(posedge clock_50) begin
+		i <= i + 1;		
+	end
+	
+	assign rst = (i == 0);
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/sensor_driver.sv b/src/5_Blur_Integration/sensor_driver.sv
new file mode 100644
index 0000000..e8313c9
--- /dev/null
+++ b/src/5_Blur_Integration/sensor_driver.sv
@@ -0,0 +1,135 @@
+// sensor_driver based on timing diagram:
+// user sends a trigger signal which lasts 10us, and expects an echo signal back to the module
+// The Echo is a distance object that is pulse width and the range in proportion.
+// You can calculate the range through the time interval between sending trigger signal and receiving echo signal
+
+module sensor_driver#(parameter ten_us = 10'd500)(
+  input clk,
+  input rst,
+  input measure,
+  input echo,
+  output trig,
+  output [7:0] distance);
+  
+  localparam IDLE = 3'b000,
+          TRIGGER = 3'b010,
+             WAIT = 3'b011,
+        COUNTECHO = 3'b100,
+		  DISPLAY_DISTANCE = 3'b101;
+		  
+  wire inIDLE, inTRIGGER, inWAIT, inCOUNTECHO, inDISPLAY;
+  reg [9:0] counter;
+  reg [21:0] distanceRAW = 0; // cycles in COUNTECHO
+  reg [31:0] distanceRAW_in_cm = 0;
+  wire trigcountDONE, counterDONE;
+  
+  logic [2:0] state;
+  logic ready;   
+
+  //Ready
+  assign ready = inIDLE;
+  
+  //Decode states
+  assign inIDLE = (state == IDLE);
+  assign inTRIGGER = (state == TRIGGER);
+  assign inWAIT = (state == WAIT);
+  assign inCOUNTECHO = (state == COUNTECHO);
+  assign inDISPLAY = (state == DISPLAY_DISTANCE);
+
+  //State transactions
+  always@(posedge clk or posedge rst)
+    begin
+      if(rst)
+        begin
+          state <= IDLE;
+        end
+      else
+        begin
+          case(state)
+            IDLE:
+              begin
+                state <= (measure & ready) ? TRIGGER : state;
+              end
+            TRIGGER:
+              begin
+                state <= (trigcountDONE) ? WAIT : state;
+              end
+            WAIT:
+              begin
+                state <= (echo) ? COUNTECHO : state;
+              end
+            COUNTECHO:
+              begin
+                state <= (echo) ? state : DISPLAY_DISTANCE;
+              end
+				DISPLAY_DISTANCE:
+					begin
+						state <= IDLE;
+					end
+          endcase
+          
+        end
+    end
+  
+  //Trigger
+  assign trig = inTRIGGER;
+  
+  //Counter
+  always@(posedge clk)
+    begin
+      if(inIDLE)
+        begin
+          counter <= 10'd0;
+        end
+      else
+        begin
+          counter <= counter + {9'd0, (|counter | inTRIGGER)};
+        end
+    end
+  assign trigcountDONE = (counter == ten_us);
+
+  //Get distance
+  always@(posedge clk)
+    begin
+      if(inWAIT) begin
+        distanceRAW <= 22'd0;
+      end else
+        distanceRAW <= distanceRAW + {21'd0, inCOUNTECHO};
+		  
+    end
+
+  // to calculate distance in cm
+  // range = high level time * velocity (340M/S) / 2
+  // 340m/s = 0.000034cm/ns = 0.00068cm/cycle
+  // range = 0.00068/2 = 0.00034cm/cycle
+  // using fixedpoint python library we can convert 0.000034 to fixed point binary with 8 int and 24 frac bits by writing the code below
+  // import fixedpoint
+  // print(fixedpoint.FixedPoint(0.00034, signed=True, m=8, n=24)) # Signed with 8 integer bits and 24 fractional bits
+	 
+	always @(posedge clk) begin
+		if(inDISPLAY) begin
+			distanceRAW_in_cm <= distanceRAW * 32'h1648;
+		end
+	end
+	
+	assign distance = distanceRAW_in_cm[31:24];
+
+endmodule
+
+// timer used to measure distance at 250ms intervals - not used in top level
+module refresher250ms(
+  input clk,
+  input en,
+  output measure);
+  reg [24:0] counter;
+
+  assign measure = (counter == 25'd1);
+
+  always@(posedge clk)
+    begin
+      if(~en | (counter == 25'd12_500_000))
+        counter <= 25'd0;
+      else
+        counter <= 25'd1 + counter;
+    end
+endmodule
diff --git a/src/5_Blur_Integration/seven_seg.sv b/src/5_Blur_Integration/seven_seg.sv
new file mode 100644
index 0000000..f30c561
--- /dev/null
+++ b/src/5_Blur_Integration/seven_seg.sv
@@ -0,0 +1,22 @@
+module seven_seg(
+    input      [3:0]  bcd,
+    output reg [6:0]  segments // Must be reg to set in always block!!
+);
+  
+  always @(*) begin
+    case(bcd)
+        0:       segments = 7'b1000000;
+        1:       segments = 7'b1111001;
+        2:       segments = 7'b0100100;
+        3:       segments = 7'b0110000;
+        4:       segments = 7'b0011001;
+        5:       segments = 7'b0010010;
+        6:       segments = 7'b0000010;
+        7:       segments = 7'b1111000;
+        8:       segments = 7'b0000000;
+        9:       segments = 7'b0010000;
+        default: segments = 7'b1111111;  // Default: All segments turned off.
+    endcase
+  end
+
+endmodule
diff --git a/src/5_Blur_Integration/speed_control_mapping.sv b/src/5_Blur_Integration/speed_control_mapping.sv
new file mode 100644
index 0000000..9096c37
--- /dev/null
+++ b/src/5_Blur_Integration/speed_control_mapping.sv
@@ -0,0 +1,27 @@
+/*
+Module maps logic integers up to 7 to their corresponding 
+ascii characters
+*/
+
+import lcd_inst_pkg::*;
+
+module speed_control_mapping
+(
+    input logic [3:0] speed,
+    output logic [7:0] ascii_speed
+);
+
+    always_comb begin
+        ascii_speed = {8'd53};
+        case(speed)
+
+            3'b000 : ascii_speed = _0;
+            3'b001 : ascii_speed = _1;
+            3'b010 : ascii_speed = _2;
+            3'b011 : ascii_speed = _3;
+            3'b100 : ascii_speed = _4;
+            3'b101 : ascii_speed = _5;
+            default ascii_speed = _5;
+        endcase
+    end
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/speed_fsm.sv b/src/5_Blur_Integration/speed_fsm.sv
new file mode 100644
index 0000000..d4453ed
--- /dev/null
+++ b/src/5_Blur_Integration/speed_fsm.sv
@@ -0,0 +1,50 @@
+module speed_fsm(
+
+	input CLOCK_50,
+	input [2:0] direction, // current state
+	input [9:0] mic_freq,
+	input [4:0] threshold_frequency,
+	output [2:0] speed
+);
+
+	logic rst;
+	
+	// determine if we are in reset mode or not
+	always_comb begin
+		if(direction == 3'b001 || direction == 3'b011) begin
+			rst = 0;
+		end
+		else begin
+			rst = 1;
+		end
+	end
+	
+	logic [2:0] speed_temp = 0;
+	
+	// increment the temp speed if we are at the correct value
+	always_ff @(posedge CLOCK_50) begin
+		if(rst) begin
+			speed_temp <= 0;
+		end
+		else if(mic_freq > threshold_frequency) begin
+			speed_temp <= (speed_temp < 6) ? speed_temp + 1 : speed_temp;
+		end
+		else begin
+			speed_temp <= speed_temp;
+		end
+	end
+	
+	
+	always_comb begin
+		
+		// handle speeds out of control
+		if(speed_temp >= 5) begin
+			speed = 3;					// change this
+		end
+		else begin
+			speed = speed_temp + 1;
+		end
+	
+	end
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/stop.sv b/src/5_Blur_Integration/stop.sv
new file mode 100644
index 0000000..018b0e7
--- /dev/null
+++ b/src/5_Blur_Integration/stop.sv
@@ -0,0 +1,98 @@
+import lcd_inst_pkg::*;
+
+module stop #(
+    parameter CLKS_PER_BIT = 50_000_000/115_200,
+    parameter BITS_N = 8,
+    parameter NUM_BYTES = 25
+    )(
+    input clk,
+    input rst,
+    output logic uart_out,
+    output logic ready         // Signal indicating the system is ready for a new command
+);
+    logic [4:0] byte_index = 0;
+    logic [4:0] next_byte_index = 0;
+
+    logic uart_valid;
+    logic [BITS_N-1:0] current_byte = 8'b0;
+
+    logic uart_ready;
+
+    // UART transmitter instance
+    uart_tx #(
+        .CLKS_PER_BIT(CLKS_PER_BIT),
+        .BITS_N(BITS_N)
+    ) uart (
+        .clk(clk),
+        .rst(rst),
+        .data_tx(current_byte),
+        .uart_out(uart_out),
+        .valid(uart_valid),
+        .ready(uart_ready)
+    );
+
+    // Hard-coded 25-byte JSON message: {"T":11,"L":164,"R":164}\n
+    logic [0:NUM_BYTES-1][7:0] json_data;
+    initial begin
+        json_data[0] = _OPEN_BRACE;
+        json_data[1] =_DOUBLE_QUOTE;
+        json_data[2] =_T;
+        json_data[3] =_DOUBLE_QUOTE;
+        json_data[4] =_COLON;
+        json_data[5] =_1;
+        json_data[6] =_COMMA;
+        json_data[7] =_DOUBLE_QUOTE;
+        json_data[8] =_L;
+        json_data[9] =_DOUBLE_QUOTE;
+        json_data[10] =_COLON;
+        json_data[11] =_0;
+        json_data[12] =_PERIOD;
+        json_data[13] =_0;
+        json_data[14] =_COMMA;
+        json_data[15] =_DOUBLE_QUOTE;
+        json_data[16] =_R;
+        json_data[17] =_DOUBLE_QUOTE;
+        json_data[18] =_COLON;
+        json_data[19] =_0;
+        json_data[20] =_PERIOD;
+        json_data[21] =_0;
+        json_data[22] =_CLOSE_BRACE;
+        json_data[23] =8'h0A;
+		json_data[24] =8'h0A; // new line character
+    end
+
+    // current byte based on byte index
+    always_comb begin
+        current_byte = json_data[byte_index];
+    end
+	 
+    // Control logic to send the JSON string byte by byte
+    always_ff @(posedge clk) begin
+        if (rst)
+        begin
+            byte_index <= 0;
+            next_byte_index <= 0;
+            uart_valid <= 1'b0;
+        end 
+		else if (next_byte_index == NUM_BYTES) 
+			  begin
+				uart_valid <= 1'b0; //  we've reached the end so set valid low
+			  end
+        else if (uart_ready)
+        begin
+            if(next_byte_index < NUM_BYTES)
+					begin
+						 byte_index <= next_byte_index;
+						 uart_valid <= 1'b1;
+						 next_byte_index <= next_byte_index + 1;
+					end
+        end 
+    end
+
+    // Ready signal when all bytes have been sent, including the newline
+
+    // add a delay before we output a ready flag
+    
+    assign ready = (byte_index == NUM_BYTES) && uart_ready && (!uart_valid);  // Only ready after the last byte is fully sent
+
+endmodule
diff --git a/src/5_Blur_Integration/synchroniser.sv b/src/5_Blur_Integration/synchroniser.sv
new file mode 100644
index 0000000..748e085
--- /dev/null
+++ b/src/5_Blur_Integration/synchroniser.sv
@@ -0,0 +1,9 @@
+module synchroniser (input clk, x, output y);
+    reg x_q0, x_q1;
+    always @(posedge clk)
+    begin
+        x_q0 <= x;    // Flip-flop #1
+        x_q1 <= x_q0; // Flip-flop #2
+    end
+    assign y = x_q1;
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/top_level_distance_sensor.sv b/src/5_Blur_Integration/top_level_distance_sensor.sv
new file mode 100644
index 0000000..d424960
--- /dev/null
+++ b/src/5_Blur_Integration/top_level_distance_sensor.sv
@@ -0,0 +1,45 @@
+module top_level_distance_sensor(
+	input CLOCK_50,
+	inout [35:0] GPIO,
+   input enable,
+	input reset,
+	output [7:0] ultrasonic_distance,
+	output [6:0] HEX4,
+	output [6:0] HEX5
+);
+
+logic start;
+logic echo, trigger;
+
+assign echo = GPIO[34];
+assign GPIO[35] = trigger;
+
+// Measure the distance every 250ms
+refresher250ms refresher_250ms (
+  .clk(CLOCK_50),
+  .en(enable),
+  .measure(start)
+);
+
+logic [7:0] distance;
+// Sends trigger and reads distance
+sensor_driver u0(
+  .clk(CLOCK_50),
+  .rst(reset),
+  .measure(start),
+  .echo(echo),
+  .trig(trigger), 
+  .distance(distance)
+);
+
+ 
+ display_2digit  d2d(
+    .clk(CLOCK_50),
+    .value(distance),
+    .display0(HEX4),
+    .display1(HEX5)
+	);
+
+ assign ultrasonic_distance = distance;
+ 
+endmodule
diff --git a/src/5_Blur_Integration/top_level_motor_driver.qsf b/src/5_Blur_Integration/top_level_motor_driver.qsf
new file mode 100644
index 0000000..d161b2b
--- /dev/null
+++ b/src/5_Blur_Integration/top_level_motor_driver.qsf
@@ -0,0 +1,1758 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 08:01:26  October 15, 2024
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		top_level_motor_driver_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY top_level_motor_driver
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:01:25  OCTOBER 15, 2024"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_location_assignment PIN_D2 -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_location_assignment PIN_C2 -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_location_assignment PIN_F2 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+set_location_assignment PIN_D1 -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_location_assignment PIN_E3 -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_location_assignment PIN_E1 -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+set_location_assignment PIN_AG14 -to CLOCK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
+set_location_assignment PIN_AG15 -to CLOCK3_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+set_location_assignment PIN_Y2 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_location_assignment PIN_R5 -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_location_assignment PIN_W7 -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_location_assignment PIN_W8 -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_location_assignment PIN_V5 -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_location_assignment PIN_P1 -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_location_assignment PIN_U8 -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_location_assignment PIN_V8 -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_location_assignment PIN_R4 -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_location_assignment PIN_U7 -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_location_assignment PIN_V7 -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_location_assignment PIN_AE5 -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_location_assignment PIN_T4 -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
+set_location_assignment PIN_U4 -to DRAM_DQ[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
+set_location_assignment PIN_T3 -to DRAM_DQ[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
+set_location_assignment PIN_R3 -to DRAM_DQ[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
+set_location_assignment PIN_R2 -to DRAM_DQ[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
+set_location_assignment PIN_R1 -to DRAM_DQ[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
+set_location_assignment PIN_R7 -to DRAM_DQ[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
+set_location_assignment PIN_U5 -to DRAM_DQ[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
+set_location_assignment PIN_L7 -to DRAM_DQ[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
+set_location_assignment PIN_M7 -to DRAM_DQ[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
+set_location_assignment PIN_M4 -to DRAM_DQ[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
+set_location_assignment PIN_N4 -to DRAM_DQ[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
+set_location_assignment PIN_N3 -to DRAM_DQ[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
+set_location_assignment PIN_P2 -to DRAM_DQ[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
+set_location_assignment PIN_L8 -to DRAM_DQ[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
+set_location_assignment PIN_M8 -to DRAM_DQ[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
+set_location_assignment PIN_AC2 -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_location_assignment PIN_AB3 -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_location_assignment PIN_AC1 -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_location_assignment PIN_AB2 -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_location_assignment PIN_AA3 -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_location_assignment PIN_Y4 -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_location_assignment PIN_Y3 -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_location_assignment PIN_U3 -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_location_assignment PIN_V1 -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_location_assignment PIN_V2 -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_location_assignment PIN_V3 -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_location_assignment PIN_W1 -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_location_assignment PIN_V4 -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_location_assignment PIN_W2 -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_location_assignment PIN_W3 -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_location_assignment PIN_N8 -to DRAM_DQM[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
+set_location_assignment PIN_K8 -to DRAM_DQM[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
+set_location_assignment PIN_W4 -to DRAM_DQM[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
+set_location_assignment PIN_U2 -to DRAM_DQM[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
+set_location_assignment PIN_U6 -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_location_assignment PIN_V6 -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_location_assignment PIN_D14 -to EEP_I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
+set_location_assignment PIN_E14 -to EEP_I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
+set_location_assignment PIN_A17 -to ENET0_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
+set_location_assignment PIN_A21 -to ENET0_INT_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
+set_location_assignment PIN_C14 -to ENET0_LINK100
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
+set_location_assignment PIN_C20 -to ENET0_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
+set_location_assignment PIN_B21 -to ENET0_MDIO
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
+set_location_assignment PIN_C19 -to ENET0_RST_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N
+set_location_assignment PIN_A15 -to ENET0_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
+set_location_assignment PIN_E15 -to ENET0_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
+set_location_assignment PIN_D15 -to ENET0_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
+set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
+set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
+set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
+set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
+set_location_assignment PIN_C17 -to ENET0_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
+set_location_assignment PIN_D18 -to ENET0_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
+set_location_assignment PIN_B17 -to ENET0_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
+set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
+set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
+set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
+set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
+set_location_assignment PIN_A18 -to ENET0_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
+set_location_assignment PIN_B18 -to ENET0_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
+set_location_assignment PIN_C23 -to ENET1_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
+set_location_assignment PIN_D24 -to ENET1_INT_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
+set_location_assignment PIN_D13 -to ENET1_LINK100
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
+set_location_assignment PIN_D23 -to ENET1_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
+set_location_assignment PIN_D25 -to ENET1_MDIO
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
+set_location_assignment PIN_D22 -to ENET1_RST_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N
+set_location_assignment PIN_B15 -to ENET1_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
+set_location_assignment PIN_B22 -to ENET1_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
+set_location_assignment PIN_D20 -to ENET1_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
+set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
+set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
+set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
+set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
+set_location_assignment PIN_A22 -to ENET1_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
+set_location_assignment PIN_C24 -to ENET1_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
+set_location_assignment PIN_C22 -to ENET1_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
+set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
+set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
+set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
+set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
+set_location_assignment PIN_B25 -to ENET1_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
+set_location_assignment PIN_A25 -to ENET1_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
+set_location_assignment PIN_A14 -to ENETCLK_25
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
+set_location_assignment PIN_D9 -to EX_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6]
+set_location_assignment PIN_E10 -to EX_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5]
+set_location_assignment PIN_F14 -to EX_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4]
+set_location_assignment PIN_H14 -to EX_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3]
+set_location_assignment PIN_H13 -to EX_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2]
+set_location_assignment PIN_J14 -to EX_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1]
+set_location_assignment PIN_J10 -to EX_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0]
+set_location_assignment PIN_AD11 -to FL_ADDR[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
+set_location_assignment PIN_AD10 -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_location_assignment PIN_AE10 -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_location_assignment PIN_AD12 -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_location_assignment PIN_AC12 -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_location_assignment PIN_AH12 -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_location_assignment PIN_AA8 -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_location_assignment PIN_Y10 -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_location_assignment PIN_AC8 -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_location_assignment PIN_AD8 -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_location_assignment PIN_AA10 -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_location_assignment PIN_AF9 -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_location_assignment PIN_AE9 -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_location_assignment PIN_AB10 -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_location_assignment PIN_AB12 -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_location_assignment PIN_AB13 -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_location_assignment PIN_AA12 -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_location_assignment PIN_AA13 -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_location_assignment PIN_Y12 -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_location_assignment PIN_Y14 -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_location_assignment PIN_Y13 -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_location_assignment PIN_AH7 -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_location_assignment PIN_AG12 -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_location_assignment PIN_AG7 -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_location_assignment PIN_AF12 -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_location_assignment PIN_AH11 -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_location_assignment PIN_AG11 -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_location_assignment PIN_AF11 -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_location_assignment PIN_AH10 -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_location_assignment PIN_AG10 -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_location_assignment PIN_AF10 -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_location_assignment PIN_AH8 -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_location_assignment PIN_AG8 -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_location_assignment PIN_AE11 -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_location_assignment PIN_Y1 -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_location_assignment PIN_AC10 -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_location_assignment PIN_AE12 -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_location_assignment PIN_AG26 -to GPIO[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
+set_location_assignment PIN_AH23 -to GPIO[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
+set_location_assignment PIN_AH26 -to GPIO[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
+set_location_assignment PIN_AF20 -to GPIO[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
+set_location_assignment PIN_AG23 -to GPIO[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
+set_location_assignment PIN_AE20 -to GPIO[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
+set_location_assignment PIN_AF26 -to GPIO[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
+set_location_assignment PIN_AH22 -to GPIO[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
+set_location_assignment PIN_AE24 -to GPIO[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
+set_location_assignment PIN_AG22 -to GPIO[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
+set_location_assignment PIN_AE25 -to GPIO[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
+set_location_assignment PIN_AH25 -to GPIO[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
+set_location_assignment PIN_AD25 -to GPIO[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
+set_location_assignment PIN_AG25 -to GPIO[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
+set_location_assignment PIN_AD22 -to GPIO[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
+set_location_assignment PIN_AF22 -to GPIO[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
+set_location_assignment PIN_AF21 -to GPIO[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
+set_location_assignment PIN_AE22 -to GPIO[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
+set_location_assignment PIN_AC22 -to GPIO[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
+set_location_assignment PIN_AF25 -to GPIO[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
+set_location_assignment PIN_AE21 -to GPIO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
+set_location_assignment PIN_AF24 -to GPIO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
+set_location_assignment PIN_AF15 -to GPIO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
+set_location_assignment PIN_AD19 -to GPIO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
+set_location_assignment PIN_AF16 -to GPIO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
+set_location_assignment PIN_AC19 -to GPIO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
+set_location_assignment PIN_AE15 -to GPIO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
+set_location_assignment PIN_AD15 -to GPIO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
+set_location_assignment PIN_AE16 -to GPIO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
+set_location_assignment PIN_AD21 -to GPIO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
+set_location_assignment PIN_Y16 -to GPIO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
+set_location_assignment PIN_AC21 -to GPIO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
+set_location_assignment PIN_Y17 -to GPIO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
+set_location_assignment PIN_AB21 -to GPIO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
+set_location_assignment PIN_AC15 -to GPIO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
+set_location_assignment PIN_AB22 -to GPIO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
+set_location_assignment PIN_H22 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
+set_location_assignment PIN_J22 -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
+set_location_assignment PIN_L25 -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
+set_location_assignment PIN_L26 -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
+set_location_assignment PIN_E17 -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
+set_location_assignment PIN_F22 -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
+set_location_assignment PIN_G18 -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
+set_location_assignment PIN_U24 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
+set_location_assignment PIN_U23 -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
+set_location_assignment PIN_W25 -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
+set_location_assignment PIN_W22 -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
+set_location_assignment PIN_M24 -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
+set_location_assignment PIN_W28 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
+set_location_assignment PIN_W27 -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
+set_location_assignment PIN_Y26 -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
+set_location_assignment PIN_W26 -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
+set_location_assignment PIN_Y25 -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
+set_location_assignment PIN_AA26 -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
+set_location_assignment PIN_AA25 -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
+set_location_assignment PIN_Y19 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_location_assignment PIN_AF23 -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_location_assignment PIN_AD24 -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_location_assignment PIN_AA21 -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_location_assignment PIN_AB20 -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_location_assignment PIN_U21 -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
+set_location_assignment PIN_V21 -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
+set_location_assignment PIN_AE18 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_location_assignment PIN_AF19 -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_location_assignment PIN_AE19 -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_location_assignment PIN_AH21 -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_location_assignment PIN_AG21 -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_location_assignment PIN_AA19 -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_location_assignment PIN_AB19 -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_location_assignment PIN_AH18 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_location_assignment PIN_AF18 -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_location_assignment PIN_AG19 -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_location_assignment PIN_AH19 -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_location_assignment PIN_AB18 -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_location_assignment PIN_AC18 -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_location_assignment PIN_AD18 -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_location_assignment PIN_AC17 -to HEX6[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
+set_location_assignment PIN_AA15 -to HEX6[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
+set_location_assignment PIN_AB15 -to HEX6[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
+set_location_assignment PIN_AB17 -to HEX6[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
+set_location_assignment PIN_AA16 -to HEX6[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
+set_location_assignment PIN_AB16 -to HEX6[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
+set_location_assignment PIN_AA17 -to HEX6[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
+set_location_assignment PIN_AA14 -to HEX7[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
+set_location_assignment PIN_AG18 -to HEX7[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
+set_location_assignment PIN_AF17 -to HEX7[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
+set_location_assignment PIN_AH17 -to HEX7[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
+set_location_assignment PIN_AG17 -to HEX7[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
+set_location_assignment PIN_AE17 -to HEX7[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
+set_location_assignment PIN_AD17 -to HEX7[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
+set_location_assignment PIN_AH15 -to HSMC_CLKIN0
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0
+set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
+set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
+set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
+set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
+set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
+set_location_assignment PIN_AF27 -to HSMC_D[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
+set_location_assignment PIN_AE27 -to HSMC_D[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
+set_location_assignment PIN_AE28 -to HSMC_D[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
+set_location_assignment PIN_AE26 -to HSMC_D[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
+set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
+set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
+set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
+set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
+set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
+set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
+set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
+set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
+set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
+set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
+set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
+set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
+set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
+set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
+set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
+set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
+set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
+set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
+set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
+set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
+set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
+set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
+set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
+set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
+set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
+set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
+set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
+set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
+set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
+set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
+set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
+set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
+set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
+set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
+set_location_assignment PIN_B7 -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+set_location_assignment PIN_A8 -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+set_location_assignment PIN_Y15 -to IRDA_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
+set_location_assignment PIN_R24 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
+set_location_assignment PIN_N21 -to KEY[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
+set_location_assignment PIN_M21 -to KEY[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
+set_location_assignment PIN_M23 -to KEY[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
+set_location_assignment PIN_L6 -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_location_assignment PIN_M5 -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_location_assignment PIN_M3 -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_location_assignment PIN_K2 -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_location_assignment PIN_K1 -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_location_assignment PIN_K7 -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_location_assignment PIN_L2 -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_location_assignment PIN_L1 -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_location_assignment PIN_L3 -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_location_assignment PIN_L4 -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_location_assignment PIN_L5 -to LCD_ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
+set_location_assignment PIN_M2 -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_location_assignment PIN_M1 -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_location_assignment PIN_F17 -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
+set_location_assignment PIN_G21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
+set_location_assignment PIN_G22 -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
+set_location_assignment PIN_G20 -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
+set_location_assignment PIN_H21 -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
+set_location_assignment PIN_E24 -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
+set_location_assignment PIN_E25 -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
+set_location_assignment PIN_E22 -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
+set_location_assignment PIN_E21 -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
+set_location_assignment PIN_H15 -to LEDR[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
+set_location_assignment PIN_G16 -to LEDR[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
+set_location_assignment PIN_G15 -to LEDR[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
+set_location_assignment PIN_F15 -to LEDR[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
+set_location_assignment PIN_H17 -to LEDR[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
+set_location_assignment PIN_J16 -to LEDR[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
+set_location_assignment PIN_H16 -to LEDR[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
+set_location_assignment PIN_J15 -to LEDR[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
+set_location_assignment PIN_G17 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
+set_location_assignment PIN_J17 -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
+set_location_assignment PIN_H19 -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
+set_location_assignment PIN_J19 -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
+set_location_assignment PIN_E18 -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
+set_location_assignment PIN_F18 -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
+set_location_assignment PIN_F21 -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
+set_location_assignment PIN_E19 -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
+set_location_assignment PIN_F19 -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
+set_location_assignment PIN_G19 -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
+set_location_assignment PIN_C3 -to OTG_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
+set_location_assignment PIN_H7 -to OTG_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
+set_location_assignment PIN_A3 -to OTG_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
+set_location_assignment PIN_D4 -to OTG_DACK_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1]
+set_location_assignment PIN_C4 -to OTG_DACK_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0]
+set_location_assignment PIN_G4 -to OTG_DATA[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
+set_location_assignment PIN_F3 -to OTG_DATA[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
+set_location_assignment PIN_F1 -to OTG_DATA[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
+set_location_assignment PIN_G3 -to OTG_DATA[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
+set_location_assignment PIN_G2 -to OTG_DATA[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
+set_location_assignment PIN_G1 -to OTG_DATA[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
+set_location_assignment PIN_H4 -to OTG_DATA[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
+set_location_assignment PIN_H3 -to OTG_DATA[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
+set_location_assignment PIN_J3 -to OTG_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
+set_location_assignment PIN_J4 -to OTG_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
+set_location_assignment PIN_K3 -to OTG_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
+set_location_assignment PIN_K4 -to OTG_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
+set_location_assignment PIN_J6 -to OTG_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
+set_location_assignment PIN_B4 -to OTG_DREQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1]
+set_location_assignment PIN_J1 -to OTG_DREQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
+set_location_assignment PIN_C6 -to OTG_FSPEED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED
+set_location_assignment PIN_D5 -to OTG_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1]
+set_location_assignment PIN_A6 -to OTG_INT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0]
+set_location_assignment PIN_B6 -to OTG_LSPEED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED
+set_location_assignment PIN_B3 -to OTG_RD_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N
+set_location_assignment PIN_C5 -to OTG_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
+set_location_assignment PIN_A4 -to OTG_WR_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N
+set_location_assignment PIN_G6 -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_location_assignment PIN_G5 -to PS2_CLK2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
+set_location_assignment PIN_H5 -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_location_assignment PIN_F5 -to PS2_DAT2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
+set_location_assignment PIN_AE13 -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_location_assignment PIN_AD14 -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_location_assignment PIN_AC14 -to SD_DAT[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
+set_location_assignment PIN_AB14 -to SD_DAT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
+set_location_assignment PIN_AF13 -to SD_DAT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
+set_location_assignment PIN_AE14 -to SD_DAT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
+set_location_assignment PIN_AF14 -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_location_assignment PIN_AH14 -to SMA_CLKIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
+set_location_assignment PIN_AE23 -to SMA_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
+set_location_assignment PIN_T8 -to SRAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
+set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
+set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
+set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
+set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
+set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
+set_location_assignment PIN_T7 -to SRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
+set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
+set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
+set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
+set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
+set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
+set_location_assignment PIN_AF8 -to SRAM_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
+set_location_assignment PIN_AG3 -to SRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
+set_location_assignment PIN_AF3 -to SRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
+set_location_assignment PIN_AE4 -to SRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
+set_location_assignment PIN_AE3 -to SRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
+set_location_assignment PIN_AE1 -to SRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
+set_location_assignment PIN_AE2 -to SRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
+set_location_assignment PIN_AD2 -to SRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
+set_location_assignment PIN_AD1 -to SRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
+set_location_assignment PIN_AH6 -to SRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
+set_location_assignment PIN_AG6 -to SRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
+set_location_assignment PIN_AF6 -to SRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
+set_location_assignment PIN_AH4 -to SRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
+set_location_assignment PIN_AG4 -to SRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
+set_location_assignment PIN_AF4 -to SRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
+set_location_assignment PIN_AH3 -to SRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
+set_location_assignment PIN_AD4 -to SRAM_LB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
+set_location_assignment PIN_AD5 -to SRAM_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
+set_location_assignment PIN_AC4 -to SRAM_UB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
+set_location_assignment PIN_AE8 -to SRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
+set_location_assignment PIN_Y23 -to SW[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
+set_location_assignment PIN_Y24 -to SW[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
+set_location_assignment PIN_AA22 -to SW[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
+set_location_assignment PIN_AA23 -to SW[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
+set_location_assignment PIN_AA24 -to SW[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
+set_location_assignment PIN_AB23 -to SW[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
+set_location_assignment PIN_AB24 -to SW[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
+set_location_assignment PIN_AC24 -to SW[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
+set_location_assignment PIN_AB25 -to SW[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
+set_location_assignment PIN_AC25 -to SW[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
+set_location_assignment PIN_AB26 -to SW[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
+set_location_assignment PIN_AD26 -to SW[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
+set_location_assignment PIN_AC26 -to SW[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
+set_location_assignment PIN_AB27 -to SW[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
+set_location_assignment PIN_AD27 -to SW[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
+set_location_assignment PIN_AC27 -to SW[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
+set_location_assignment PIN_AC28 -to SW[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
+set_location_assignment PIN_AB28 -to SW[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
+set_location_assignment PIN_B14 -to TD_CLK27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
+set_location_assignment PIN_F7 -to TD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
+set_location_assignment PIN_E7 -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
+set_location_assignment PIN_D6 -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
+set_location_assignment PIN_C7 -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
+set_location_assignment PIN_D8 -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
+set_location_assignment PIN_A7 -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
+set_location_assignment PIN_E8 -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
+set_location_assignment PIN_E5 -to TD_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
+set_location_assignment PIN_G7 -to TD_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
+set_location_assignment PIN_E4 -to TD_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
+set_location_assignment PIN_G14 -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_location_assignment PIN_J13 -to UART_RTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_location_assignment PIN_G12 -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_location_assignment PIN_G9 -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_location_assignment PIN_D12 -to VGA_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+set_location_assignment PIN_D11 -to VGA_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
+set_location_assignment PIN_C12 -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_location_assignment PIN_A11 -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_location_assignment PIN_B11 -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_location_assignment PIN_C11 -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_location_assignment PIN_A10 -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_location_assignment PIN_B10 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_location_assignment PIN_F11 -to VGA_BLANK_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
+set_location_assignment PIN_A12 -to VGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
+set_location_assignment PIN_C9 -to VGA_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
+set_location_assignment PIN_F10 -to VGA_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
+set_location_assignment PIN_B8 -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_location_assignment PIN_C8 -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_location_assignment PIN_H12 -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_location_assignment PIN_F8 -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_location_assignment PIN_G11 -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_location_assignment PIN_G8 -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_location_assignment PIN_G13 -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_location_assignment PIN_H10 -to VGA_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
+set_location_assignment PIN_H8 -to VGA_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
+set_location_assignment PIN_J12 -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_location_assignment PIN_G10 -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_location_assignment PIN_F12 -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_location_assignment PIN_D10 -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_location_assignment PIN_E11 -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_location_assignment PIN_E12 -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_location_assignment PIN_C10 -to VGA_SYNC_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
+set_location_assignment PIN_C13 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
+set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
+set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
+set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
+set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
+set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
+set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
+set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
+set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
+set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
+set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
+set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
+set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
+set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
+set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
+set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
+set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
+set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
+set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
+set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
+set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
+set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
+set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
+set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
+set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
+set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
+set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
+set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
+set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
+set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
+set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
+set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
+set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
+set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
+set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
+set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
+set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
+set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH json_command_sender_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME json_command_sender_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id json_command_sender_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME json_command_sender_tb -section_id json_command_sender_tb
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT json_command_sender_tb.sv -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_FILE json_command_sender_tb.sv -section_id json_command_sender_tb
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity top_level -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity top_level -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -entity top_level -section_id Top
+set_location_assignment PIN_M23 -to btn_resend
+set_location_assignment PIN_Y2 -to clk_50
+set_location_assignment PIN_E22 -to config_start
+set_location_assignment PIN_E21 -to led_config_finished
+set_location_assignment PIN_AD19 -to ov7670_data[0]
+set_location_assignment PIN_AF15 -to ov7670_data[1]
+set_location_assignment PIN_AF24 -to ov7670_data[2]
+set_location_assignment PIN_AE21 -to ov7670_data[3]
+set_location_assignment PIN_AF25 -to ov7670_data[4]
+set_location_assignment PIN_AC22 -to ov7670_data[5]
+set_location_assignment PIN_AE22 -to ov7670_data[6]
+set_location_assignment PIN_AF21 -to ov7670_data[7]
+set_location_assignment PIN_AG25 -to ov7670_href
+set_location_assignment PIN_AD22 -to ov7670_pclk
+set_location_assignment PIN_AC19 -to ov7670_pwdn
+set_location_assignment PIN_AF16 -to ov7670_reset
+set_location_assignment PIN_AE25 -to ov7670_sioc
+set_location_assignment PIN_AH25 -to ov7670_siod
+set_location_assignment PIN_AD25 -to ov7670_vsync
+set_location_assignment PIN_AF22 -to ov7670_xclk
+set_location_assignment PIN_A12 -to vga_CLK
+set_location_assignment PIN_B10 -to vga_b[0]
+set_location_assignment PIN_A10 -to vga_b[1]
+set_location_assignment PIN_C11 -to vga_b[2]
+set_location_assignment PIN_B11 -to vga_b[3]
+set_location_assignment PIN_A11 -to vga_b[4]
+set_location_assignment PIN_C12 -to vga_b[5]
+set_location_assignment PIN_D11 -to vga_b[6]
+set_location_assignment PIN_D12 -to vga_b[7]
+set_location_assignment PIN_F11 -to vga_blank_N
+set_location_assignment PIN_G8 -to vga_g[0]
+set_location_assignment PIN_G11 -to vga_g[1]
+set_location_assignment PIN_F8 -to vga_g[2]
+set_location_assignment PIN_H12 -to vga_g[3]
+set_location_assignment PIN_C8 -to vga_g[4]
+set_location_assignment PIN_B8 -to vga_g[5]
+set_location_assignment PIN_F10 -to vga_g[6]
+set_location_assignment PIN_C9 -to vga_g[7]
+set_location_assignment PIN_G13 -to vga_hsync
+set_location_assignment PIN_E12 -to vga_r[0]
+set_location_assignment PIN_E11 -to vga_r[1]
+set_location_assignment PIN_D10 -to vga_r[2]
+set_location_assignment PIN_F12 -to vga_r[3]
+set_location_assignment PIN_G10 -to vga_r[4]
+set_location_assignment PIN_J12 -to vga_r[5]
+set_location_assignment PIN_H8 -to vga_r[6]
+set_location_assignment PIN_H10 -to vga_r[7]
+set_location_assignment PIN_C10 -to vga_sync_N
+set_location_assignment PIN_C13 -to vga_vsync
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity digital_cam_impl1 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity digital_cam_impl1 -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -entity digital_cam_impl1 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity digital_cam_impl1 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity top_level -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N -entity top_level
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 -entity top_level
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 -entity top_level
+set_global_assignment -name QIP_FILE ../vga_interface/synthesis/vga_interface.qip
+set_global_assignment -name VERILOG_FILE i2c_sender.v
+set_global_assignment -name SYSTEMVERILOG_FILE camera_generation_top.sv
+set_global_assignment -name VERILOG_FILE ov7670_registers.v
+set_global_assignment -name VERILOG_FILE ov7670_controller.v
+set_global_assignment -name VERILOG_FILE ov7670_capture.v
+set_global_assignment -name VERILOG_FILE my_frame_buffer_15to0.v
+set_global_assignment -name VERILOG_FILE my_altpll.v
+set_global_assignment -name VERILOG_FILE frame_buffer.v
+set_global_assignment -name SYSTEMVERILOG_FILE address_generator.sv
+set_global_assignment -name SYSTEMVERILOG_FILE top_level_distance_sensor.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sensor_driver.sv
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/TwiddleConvert8.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/TwiddleConvert4.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/Twiddle.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/SdfUnit2.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/SdfUnit_TC.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/Multiply.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/FFT.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/DelayBuffer.v
+set_global_assignment -name VERILOG_FILE FFT_files/r22sdf/Butterfly.v
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/mic/set_audio_encoder.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/mic/mic_load.sv
+set_global_assignment -name QIP_FILE FFT_files/mic/i2c_pll.qip
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/mic/i2c_master.sv
+set_global_assignment -name QIP_FILE FFT_files/mic/adc_pll.qip
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/low_pass_conv.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/fft_pitch_detect.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/fft_mag_sq.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/fft_input_buffer.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/fft_find_peak.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/dstream.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_files/display.sv
+set_global_assignment -name QIP_FILE FFT_files/async_fifo.qip
+set_global_assignment -name SYSTEMVERILOG_FILE nbit_synchroniser.sv
+set_global_assignment -name SYSTEMVERILOG_FILE continuous_motor_control.sv
+set_global_assignment -name SYSTEMVERILOG_FILE speed_control_mapping.sv
+set_global_assignment -name SYSTEMVERILOG_FILE stop.sv
+set_global_assignment -name SYSTEMVERILOG_FILE direction_fsm.sv
+set_global_assignment -name SYSTEMVERILOG_FILE forward.sv
+set_global_assignment -name SYSTEMVERILOG_FILE backwards.sv
+set_global_assignment -name SYSTEMVERILOG_FILE synchroniser.sv
+set_global_assignment -name SYSTEMVERILOG_FILE lcd_inst_pkg.sv
+set_global_assignment -name SYSTEMVERILOG_FILE edge_detect.sv
+set_global_assignment -name SYSTEMVERILOG_FILE debounce.sv
+set_global_assignment -name SYSTEMVERILOG_FILE uart_tx_tb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE top_level_motor_driver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE json_command_sender_tb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE json_command_sender.sv
+set_global_assignment -name SYSTEMVERILOG_FILE FFT_top_level.sv
+set_global_assignment -name SYSTEMVERILOG_FILE drive_motor.sv
+set_global_assignment -name SYSTEMVERILOG_FILE reset_pulser.sv
+set_global_assignment -name SYSTEMVERILOG_FILE speed_fsm.sv
+set_global_assignment -name SYSTEMVERILOG_FILE display_2digit.sv
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/src/5_Blur_Integration/top_level_motor_driver.sv b/src/5_Blur_Integration/top_level_motor_driver.sv
new file mode 100644
index 0000000..dcd0ba6
--- /dev/null
+++ b/src/5_Blur_Integration/top_level_motor_driver.sv
@@ -0,0 +1,304 @@
+module top_level_motor_driver (
+    input wire CLOCK_50,
+    output [17:0] LEDR,
+    input wire [17:0]SW,
+    input wire [3:0]KEY,
+    inout wire [35:0]GPIO, // GPIO5
+
+	// 7seg outputs
+
+	output [6:0] HEX0,
+	output [6:0] HEX1,
+	output [6:0] HEX2,
+	output [6:0] HEX3,
+	output [6:0] HEX4,
+	output [6:0] HEX5,
+	output [6:0] HEX6,
+	output [6:0] HEX7,
+
+	// Microphone inputs and outputs
+	output	     I2C_SCLK,
+	inout		 I2C_SDAT,
+	input		 AUD_ADCDAT,
+	input    	 AUD_BCLK,
+	output   	 AUD_XCK,
+	input    	 AUD_ADCLRCK,
+	
+	// vga  outputs
+	output wire VGA_HS,
+	output wire VGA_VS,
+	output wire [7:0] VGA_R,
+	output wire [7:0] VGA_G,
+	output wire [7:0] VGA_B,
+	output wire VGA_BLANK_N,
+	output wire VGA_SYNC_N,
+	output wire VGA_CLK
+
+);
+	// Camera Inputs and Outputs
+	wire ov7670_pclk; assign ov7670_pclk  = GPIO[21];
+	wire ov7670_xclk; assign GPIO[20]     = ov7670_xclk;
+	wire ov7670_vsync;assign ov7670_vsync = GPIO[23];
+	wire ov7670_href; assign ov7670_href  = GPIO[22];
+	wire [7:0] ov7670_data; assign ov7670_data  = GPIO[19:12];
+	wire ov7670_sioc; assign GPIO[25]     = ov7670_sioc;
+	wire ov7670_siod; assign GPIO[24]     = ov7670_siod;
+	wire ov7670_pwdn; assign GPIO[10]     = ov7670_pwdn;
+	wire ov7670_reset;assign GPIO[11]     = ov7670_reset;
+
+	// vga outputs
+	wire vga_hsync; assign VGA_HS 	      = vga_hsync;
+	wire vga_vsync; assign VGA_VS 	      = vga_vsync;
+	wire [7:0] vga_r; assign VGA_R		  = vga_r;
+	wire [7:0] vga_g; assign VGA_G 		  = vga_g;
+	wire [7:0] vga_b; assign VGA_B 		  = vga_b;
+	wire vga_blank_N; assign VGA_BLANK_N  = vga_blank_N;
+	wire vga_sync_N; assign VGA_SYNC_N	  = vga_sync_N;
+	wire vga_CLK; assign VGA_CLK		  = vga_CLK;
+
+	logic [3:0] debounced_keys;
+	logic [3:0] edge_detect_keys;
+	
+	// debounce key
+	genvar i;
+	generate
+		for(i = 0; i < 4; ++i) begin : debouncing_time
+			debounce #(.DELAY_COUNTS(2500)) d_0 (
+		   			  .clk(CLOCK_50),
+						  .button(KEY[i]),
+						  .button_pressed(debounced_keys[i])); 
+		end : debouncing_time
+	endgenerate
+	
+	
+	// edging time
+	
+	genvar j;
+	generate
+		for(j = 0; j < 4; ++j) begin : edge_time
+			edge_detect e0 (
+					.clk(CLOCK_50),
+					.button(~debounced_keys[j]),
+					.button_edge(edge_detect_keys[j])
+				);
+		end : edge_time
+	endgenerate  
+
+	// 
+	//
+	//
+	// FFT STUFF IS PRESENTED BELOW
+	//
+	//
+	//
+	
+	logic [9:0] mic_freq;
+	logic fft_reset;
+	assign fft_reset = ~SW[1];
+	FFT_top_level FFT_TL(
+		.CLOCK_50(CLOCK_50),
+		.reset(fft_reset),
+		.I2C_SCLK(I2C_SCLK),
+		.I2C_SDAT(I2C_SDAT),
+		.AUD_ADCDAT(AUD_ADCDAT),
+		.AUD_BCLK(AUD_BCLK),
+		.AUD_XCK(AUD_XCK),
+		.AUD_ADCLRCK(AUD_ADCLRCK),
+		.mic_freq(mic_freq)
+	);
+	
+	// display threshold values on hex6 and hex7
+	display_2digit  d2d(
+    .clk(CLOCK_50),
+    .value(tval),
+    .display0(HEX6),
+    .display1(HEX7)
+	);
+
+	// visualise pitch output
+	display u_display (.clk(CLOCK_50),.value(mic_freq),.display0(HEX0),.display1(HEX1),.display2(HEX2),.display3(HEX3));
+
+	
+	//------------------------
+	// MOTOR CONTROLCODE BELOW
+	//------------------------
+	
+	
+	// create a reset pulser
+	logic reset_ultra;
+	reset_pulser rp0 (
+		.clock_50(CLOCK_50),
+		.rst(reset_ultra)
+	);
+	
+	// create sensor data
+	// print sensor data on the hexs 4 and 5
+	logic [7:0] distance;
+	top_level_distance_sensor tlds (
+		.CLOCK_50(CLOCK_50),
+		.GPIO(GPIO),
+		.enable(1'b1),
+		.reset(reset_ultra),
+		.ultrasonic_distance(distance),
+		.HEX4(HEX4),
+		.HEX5(HEX5)
+	);
+	
+	// variables for handling drive control commands
+	logic [2:0] direction;
+	
+	
+	// THRESHOLD FREQUENCY ON SW[8:4]
+	// display the current threshold value
+	logic [4:0] tval;
+	assign tval = SW[17:13];
+	
+	
+	// DISPLAY THE THRESHOLDED FREQUENCY
+
+
+	// start up the directional state machine
+	
+	// state machine for high level logic
+	logic [16:0] red_pixel_threshold;
+	assign red_pixel_threshold = 17'b01000000000000000;
+	direction_fsm #(.TOO_CLOSE(8'd20)) dfsm (
+		.clk(CLOCK_50),
+		.frequency_input(mic_freq),
+		.distance(distance),
+		.threshold_frequency(tval),
+		.direction(direction),
+		.red_pixels(red_pixels),
+		.threshold_pixels(red_pixel_threshold)
+	);
+	
+	
+	// speed control
+	logic [2:0] speed;
+	speed_fsm sfsm (
+		.CLOCK_50(CLOCK_50),
+		.direction(direction),
+		.mic_freq(mic_freq),
+		.threshold_frequency(tval),
+		.speed(speed)
+	);
+
+	
+	// actual motor control
+	logic uart_out;
+	drive_motor dm (
+		.CLOCK_50(CLOCK_50),
+		.direction(direction),
+		.speed(speed),
+		.uart_out(uart_out)
+	);
+	
+	assign GPIO[5] = uart_out;
+	
+	
+	/*
+	--------------------------------
+	--------------------------------
+	--------------------------------
+	
+	THE SECITON BELOW IS FOR THE CAMERA,
+	BUFFER, ADDRESS GENERATOR AND VGA 
+	INTERFACING 
+	
+	--------------------------------
+	--------------------------------
+	--------------------------------
+	*/
+	
+	
+	logic vga_ready, sop, eop;
+	logic [16:0] rdaddress;
+	logic [11:0] rddata;
+	wire clk_25_vga;
+	
+	camera_generation_top cgt0 (
+	
+	// Camera Inputs and Outputs
+	.ov7670_pclk(ov7670_pclk),
+	.ov7670_xclk(ov7670_xclk),
+	.ov7670_vsync(ov7670_vsync),
+	.ov7670_href(ov7670_href),
+	.ov7670_data(ov7670_data),
+	.ov7670_sioc(ov7670_sioc),
+	.ov7670_siod(ov7670_siod),
+	.ov7670_pwdn(ov7670_pwdn),
+	.ov7670_reset(ov7670_reset),
+	
+	.clk_50(CLOCK_50),
+	.SW(SW),	// switches taken as inputs	
+	.ready(vga_ready), // ready comes from vga or its high - create selection
+	.sop(sop),
+	.eop(eop),
+	.pixel(rddata),
+	.address(rdaddress),
+	.clk_25_vga(clk_25_vga)
+);
+	 
+
+  logic [11:0] colour_data;
+  logic [3:0] upper_thresh;
+  logic [16:0] red_pixels;
+  
+  assign upper_thresh = 4'b1000; // can be changed to SW[5:2] for calibration
+ 
+ // detects and outputs predominantly red pixels.
+ // saves the number of pixels in red_pixels variable
+  colour_detect cd0(
+	.clk(clk_25_vga),
+	.data_in(rddata),
+	.upper_thresh(upper_thresh),
+	.address(rdaddress),
+	.data_out(colour_data),
+	.red_pixels(red_pixels),
+	.sop(sop));
+
+ // detects and outputs predominantly red pixels.
+ // saves the number of pixels in red_pixels variable
+  blurring_filter blurring_filter(
+	.clk(CLOCK_50),
+	.ready_in(ready_in),
+	.valid_in(valid_in),
+	.startofpacket_in(startofpacket_in),
+	.endofpacket_in(endofpacket_in),
+	.data_in(data_in),
+	.ready_in(ready_out),
+	.valid_in(valid_out),
+	.startofpacket_in(startofpacket_out),
+	.endofpacket_in(endofpacket_out),
+	.data_out(data_out));
+	
+  assign LEDR[16:0] = red_pixels;
+
+  // choose what data we are using
+  logic decision;
+  assign decision = SW[2];
+  logic [11:0] display_data;
+  
+  assign display_data = (decision) ? colour_data : rddata;
+  
+  // in case we want to interface with the vga
+  vga_interface vgai0 (
+			 .clk_clk(clk_25_vga),                                         //                                       clk.clk
+			 .reset_reset_n(1'b1),                                   //                                     reset.reset_n
+			 .video_scaler_0_avalon_scaler_sink_startofpacket(sop), //         video_scaler_0_avalon_scaler_sink.startofpacket
+			 .video_scaler_0_avalon_scaler_sink_endofpacket(eop),   //                                          .endofpacket
+			 .video_scaler_0_avalon_scaler_sink_valid(1'b1),         //                                          .valid
+			.video_scaler_0_avalon_scaler_sink_ready(vga_ready),         //                                          .ready
+		   .video_scaler_0_avalon_scaler_sink_data(display_data),          //                                          .data
+			.video_vga_controller_0_external_interface_CLK(vga_CLK),   // video_vga_controller_0_external_interface.CLK
+			.video_vga_controller_0_external_interface_HS(vga_hsync),    //                                          .HS
+			.video_vga_controller_0_external_interface_VS(vga_vsync),    //                                          .VS
+			.video_vga_controller_0_external_interface_BLANK(vga_blank_N), //                                          .BLANK
+			.video_vga_controller_0_external_interface_SYNC(vga_sync_N),  //                                          .SYNC
+		   .video_vga_controller_0_external_interface_R(vga_r),     //                                          .R
+		   .video_vga_controller_0_external_interface_G(vga_g),     //                                          .G
+		   .video_vga_controller_0_external_interface_B(vga_b)      //                                          .B
+	);
+
+
+endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/uart_tx.sv b/src/5_Blur_Integration/uart_tx.sv
new file mode 100644
index 0000000..a4e84ed
--- /dev/null
+++ b/src/5_Blur_Integration/uart_tx.sv
@@ -0,0 +1,79 @@
+`timescale 1ns / 1ps
+
+module uart_tx #(
+      parameter CLKS_PER_BIT = (50_000_000/115_200), // E.g. Baud_rate = 115200 with FPGA clk = 50MHz
+      parameter BITS_N       = 8  // Number of data bits per UART frame
+) (
+      input clk,
+      input rst,
+      input [BITS_N-1:0] data_tx,
+      output logic uart_out,
+      
+      input valid,            // Handshake protocol: valid (when `data_tx` is valid to be sent onto the UART).
+      output logic ready      // Handshake protocol: ready (when this UART module is ready to send data).
+ );
+
+   logic [BITS_N-1:0] data_tx_temp;
+   logic [2:0]        bit_n;
+
+   enum {IDLE, START_BIT, DATA_BITS, STOP_BIT} current_state, next_state;
+
+   logic baud_trigger;
+   integer cycle_counter;
+
+   assign baud_trigger = (cycle_counter == CLKS_PER_BIT - 1);
+
+   always_comb begin : fsm_next_state
+         case (current_state)
+            IDLE:        next_state = valid ? START_BIT : IDLE; // Handshake protocol: Only start sending data when valid data comes through.
+            START_BIT:   next_state = baud_trigger ? DATA_BITS : START_BIT;
+            DATA_BITS:   next_state = (baud_trigger && bit_n == BITS_N - 1) ? STOP_BIT : DATA_BITS; // Send all `BITS_N` bits.
+            STOP_BIT:    next_state = baud_trigger ? IDLE : STOP_BIT;
+            default:     next_state = IDLE;
+         endcase
+   end
+   
+   always_ff @( posedge clk ) begin : fsm_ff
+      if (rst) begin
+         current_state <= IDLE;
+         data_tx_temp <= 0;
+         bit_n <= 0;
+         cycle_counter <= 0;
+      end
+      else begin
+         current_state <= next_state;
+         cycle_counter <= baud_trigger ? 0 : cycle_counter + 1;
+         case (current_state)
+            IDLE: begin // Idle -- register the data to send (in case it gets corrupted by an external module). Reset counters.
+               data_tx_temp <= data_tx;
+               bit_n <= 0;
+            end
+            DATA_BITS: begin // Data transfer -- Count up the bit-index to send.
+               if (baud_trigger) bit_n <= bit_n + 1'b1;
+            end
+         endcase
+      end
+      
+   end
+
+   always_comb begin : fsm_output
+         uart_out = 1'b1; // Default: The UART line is high.
+         ready = 1'b0;    // Default: This UART module is only ready for new data when in the IDLE state.
+         case (current_state)
+            IDLE:   begin
+               ready = 1'b1;  // Handshake protocol: This UART module is ready for new data to send.
+            end
+            START_BIT:    begin
+               uart_out = 1'b0; // The start condition is a zero.
+            end
+            DATA_BITS:    begin
+               uart_out = data_tx_temp[bit_n]; // Set the UART TX line to the current bit being sent.
+            end
+            STOP_BIT:     begin
+               uart_out = 1'b1;
+            end
+            
+         endcase
+   end
+
+ endmodule
\ No newline at end of file
diff --git a/src/5_Blur_Integration/uart_tx_tb.sv b/src/5_Blur_Integration/uart_tx_tb.sv
new file mode 100644
index 0000000..9f04e95
--- /dev/null
+++ b/src/5_Blur_Integration/uart_tx_tb.sv
@@ -0,0 +1,96 @@
+`timescale 1ns / 1ps
+
+module uart_tx_tb;
+
+   // Parameters
+   parameter CLKS_PER_BIT = (50_000_000/115_200);
+   parameter BITS_N       = 8;
+
+   // Inputs
+   reg clk;
+   reg rst;
+   reg [BITS_N-1:0] data_tx;
+   reg valid;
+
+   // Outputs
+   wire uart_out;
+   wire ready;
+
+   // Clock generation (50MHz)
+   initial clk = 0;
+   always #10 clk = ~clk; // 50MHz clock (20ns period)
+
+   // Instantiate the UART TX module
+   uart_tx #(
+      .CLKS_PER_BIT(CLKS_PER_BIT),
+      .BITS_N(BITS_N)
+   ) uut (
+      .clk(clk),
+      .rst(rst),
+      .data_tx(data_tx),
+      .uart_out(uart_out),
+      .valid(valid),
+      .ready(ready)
+   );
+
+   // Test procedure
+   initial begin
+      // Initialize inputs
+      rst = 1;
+      valid = 0;
+      data_tx = 8'b0;
+
+      // Reset the design
+      #100;
+      rst = 0;
+
+      // Wait for the UART module to be ready
+      wait(ready == 1);
+      
+      // Test case 1: Transmit a byte (0x55)
+      data_tx = 8'b01010101; // 0x55
+      valid = 1;
+      #40; // Wait for one clock cycle
+      valid = 0;
+
+      // Wait for the transmission to complete (stop bit and back to IDLE)
+      wait(ready == 1);
+      
+      // Test case 2: Transmit another byte (0xA3)
+      #80;
+      wait(ready == 1);
+      data_tx = 8'b10100011; // 0xA3
+      valid = 1;
+      #40; // Wait for one clock cycle
+      valid = 0;
+
+      // Wait for the transmission to complete
+      wait(ready == 1);
+
+      // Test case 3: Check for the edge cases
+      // Transmit all 1s (0xFF)
+      data_tx = 8'b11111111;
+      valid = 1;
+      #40;
+      valid = 0;
+      wait(ready == 1);
+
+      // Transmit all 0s (0x00)
+      #80;
+      wait(ready == 1);
+      data_tx = 8'b00000000;
+      valid = 1;
+      #40;
+      valid = 0;
+      wait(ready == 1);
+
+      // Finish the simulation
+      $finish;
+   end
+
+   // Monitor the UART output
+   initial begin
+      $monitor("Time: %0t | uart_out: %b | ready: %b | data_tx: %h", $time, uart_out, ready, data_tx);
+   end
+
+endmodule
\ No newline at end of file

From aea99830755626d45a938c4127ed3f63650a863d Mon Sep 17 00:00:00 2001
From: dinoplays <166807132+dinoplays@users.noreply.github.com>
Date: Tue, 29 Oct 2024 18:34:09 +1100
Subject: [PATCH 2/5] Update top_level_motor_driver.sv

---
 .../top_level_motor_driver.sv                 | 32 +++++++++----------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/5_Blur_Integration/top_level_motor_driver.sv b/src/5_Blur_Integration/top_level_motor_driver.sv
index dcd0ba6..f23788a 100644
--- a/src/5_Blur_Integration/top_level_motor_driver.sv
+++ b/src/5_Blur_Integration/top_level_motor_driver.sv
@@ -256,21 +256,21 @@ module top_level_motor_driver (
 	.data_out(colour_data),
 	.red_pixels(red_pixels),
 	.sop(sop));
+	
+	logic valid;
+   logic [11:0] blur_data;
+	
+	assign valid = 1'b1;
 
- // detects and outputs predominantly red pixels.
- // saves the number of pixels in red_pixels variable
-  blurring_filter blurring_filter(
-	.clk(CLOCK_50),
-	.ready_in(ready_in),
-	.valid_in(valid_in),
-	.startofpacket_in(startofpacket_in),
-	.endofpacket_in(endofpacket_in),
-	.data_in(data_in),
-	.ready_in(ready_out),
-	.valid_in(valid_out),
-	.startofpacket_in(startofpacket_out),
-	.endofpacket_in(endofpacket_out),
-	.data_out(data_out));
+ // blurs only the face
+  blurring_filter blurring_face(
+	.clk(clk_25_vga),
+	.ready(vga_ready),
+	.valid(valid),
+	.startofpacket_in(sop),
+	.endofpacket_in(eop),
+	.data_in(rddata),
+	.data_out(blur_data));
 	
   assign LEDR[16:0] = red_pixels;
 
@@ -279,7 +279,7 @@ module top_level_motor_driver (
   assign decision = SW[2];
   logic [11:0] display_data;
   
-  assign display_data = (decision) ? colour_data : rddata;
+  assign display_data = (decision) ? blur_data : rddata;
   
   // in case we want to interface with the vga
   vga_interface vgai0 (
@@ -301,4 +301,4 @@ module top_level_motor_driver (
 	);
 
 
-endmodule
\ No newline at end of file
+endmodule

From 65c8969460fbd27dac3bdbbcbfce7f44eb40f9b1 Mon Sep 17 00:00:00 2001
From: dinoplays <166807132+dinoplays@users.noreply.github.com>
Date: Tue, 29 Oct 2024 18:35:10 +1100
Subject: [PATCH 3/5] Create blurring_filter.sv

---
 src/5_Blur_Integration/blurring_filter.sv | 432 ++++++++++++++++++++++
 1 file changed, 432 insertions(+)
 create mode 100644 src/5_Blur_Integration/blurring_filter.sv

diff --git a/src/5_Blur_Integration/blurring_filter.sv b/src/5_Blur_Integration/blurring_filter.sv
new file mode 100644
index 0000000..3e37c1d
--- /dev/null
+++ b/src/5_Blur_Integration/blurring_filter.sv
@@ -0,0 +1,432 @@
+`timescale 1ns / 1ps
+
+module blurring_filter (
+    input logic clk,
+    input logic ready,
+    input logic valid,
+    input logic startofpacket_in,
+    input logic endofpacket_in,
+    input logic [12-1:0] data_in,
+    output logic [12-1:0] data_out
+);
+    // Extract RGB components from input data
+    logic [3:0] red_in, green_in, blue_in;
+
+    assign red_in   = data_in[11:8];  // Bits 11-8 for red
+    assign green_in = data_in[7:4];   // Bits 7-4 for green
+    assign blue_in  = data_in[3:0];   // Bits 3-0 for blue
+
+    // 320x240 image
+    localparam image_width = 9'b101000000;
+    localparam image_length = 8'b11110000;
+
+    logic [9:0] col_count;
+    logic [8:0] row_count;
+
+    logic head_detected;
+    logic finish_blur;
+    logic blur_pixels;
+    logic face_ending;
+    logic [9:0] blur_start, blur_end, temp_blur_start, temp_blur_end;
+
+    // Image buffer for RGB components
+    logic [3:0] red_buffer [0:(image_width*4 + 6)];
+    logic [3:0] green_buffer [0:(image_width*4 + 6)];
+    logic [3:0] blue_buffer [0:(image_width*4 + 6)];
+
+    logic [9:0] conv_result_r, conv_result_g, conv_result_b;  // Final convolution results for RGB
+    logic signed [9:0] TtoB_edge_result_r, TtoB_edge_result_g, TtoB_edge_result_b, 
+        LtoR_edge_result_r, LtoR_edge_result_g, LtoR_edge_result_b; // Intermediray edge detection results
+
+    logic signed [16:0] TtoB_grey_result, LtoR_grey_result;
+
+    // Define the bitshift kernel_blur
+    logic [3:0] kernel_blur [0:34];
+    
+    // Define the edge kernels
+    logic [5:0] kernel_TtoB [0:24];
+    logic [5:0] kernel_LtoR [0:24];
+
+    always_comb begin
+    // Blur
+        kernel_blur[0] = 15;
+        kernel_blur[1] = 0;
+        kernel_blur[2] = 0;
+        kernel_blur[3] = 0;
+        kernel_blur[4] = 1;
+        kernel_blur[5] = 1;
+        kernel_blur[6] = 1;
+
+        kernel_blur[7] = 15;
+        kernel_blur[8] = 0;
+        kernel_blur[9] = 0;
+        kernel_blur[10] = 1;
+        kernel_blur[11] = 1;
+        kernel_blur[12] = 1;
+        kernel_blur[13] = 1;
+
+        kernel_blur[14] = 0;
+        kernel_blur[15] = 0;
+        kernel_blur[16] = 1;
+        kernel_blur[17] = 1;
+        kernel_blur[18] = 1;
+        kernel_blur[19] = 1;
+        kernel_blur[20] = 1;
+
+        kernel_blur[21] = 0;
+        kernel_blur[22] = 1;
+        kernel_blur[23] = 1;
+        kernel_blur[24] = 1;
+        kernel_blur[25] = 1;
+        kernel_blur[26] = 1;
+        kernel_blur[27] = 2;
+
+        kernel_blur[28] = 1;
+        kernel_blur[29] = 1;
+        kernel_blur[30] = 1;
+        kernel_blur[31] = 1;
+        kernel_blur[32] = 1;
+        kernel_blur[33] = 2;
+        kernel_blur[34] = 2;
+
+        /*
+        Sum is 64
+        Weights
+        0 1 1 1 2 2 2
+        0 1 1 2 2 2 2
+        1 1 2 2 2 2 2
+        1 2 2 2 2 2 4
+        2 2 2 2 2 4 4
+        */
+
+    // Kernel for top to bottom edge detection
+        kernel_TtoB[0] = 0;
+        kernel_TtoB[1] = 0;
+        kernel_TtoB[2] = 1;
+        kernel_TtoB[3] = 1;
+        kernel_TtoB[4] = 2;
+
+        kernel_TtoB[5] = 0;
+        kernel_TtoB[6] = 0;
+        kernel_TtoB[7] = 1;
+        kernel_TtoB[8] = 1;
+        kernel_TtoB[9] = 1;
+
+        kernel_TtoB[10] = 15;
+        kernel_TtoB[11] = 15;
+        kernel_TtoB[12] = 15;
+        kernel_TtoB[13] = 15;
+        kernel_TtoB[14] = 15;
+
+        kernel_TtoB[15] = 1;
+        kernel_TtoB[16] = 1;
+        kernel_TtoB[17] = 1;
+        kernel_TtoB[18] = 1;
+        kernel_TtoB[19] = 1;
+
+        kernel_TtoB[20] = 1;
+        kernel_TtoB[21] = 1;
+        kernel_TtoB[22] = 1;
+        kernel_TtoB[23] = 1;
+        kernel_TtoB[24] = 2;
+
+        /*
+        1  1  2  2  4
+        1  1  2  2  2
+        0  0  0  0  0
+       -2 -2 -2 -2 -2
+       -2 -2 -2 -2 -4
+        */
+
+    // Kernel for left to right edge detection
+        kernel_LtoR[0] = 0;
+        kernel_LtoR[1] = 0;
+        kernel_LtoR[2] = 15;
+        kernel_LtoR[3] = 1;
+        kernel_LtoR[4] = 1;
+
+        kernel_LtoR[5] = 0;
+        kernel_LtoR[6] = 0;
+        kernel_LtoR[7] = 15;
+        kernel_LtoR[8] = 1;
+        kernel_LtoR[9] = 1;
+
+        kernel_LtoR[10] = 1;
+        kernel_LtoR[11] = 1;
+        kernel_LtoR[12] = 15;
+        kernel_LtoR[13] = 1;
+        kernel_LtoR[14] = 1;
+
+        kernel_LtoR[15] = 1;
+        kernel_LtoR[16] = 1;
+        kernel_LtoR[17] = 15;
+        kernel_LtoR[18] = 1;
+        kernel_LtoR[19] = 1;
+
+        kernel_LtoR[20] = 2;
+        kernel_LtoR[21] = 1;
+        kernel_LtoR[22] = 15;
+        kernel_LtoR[23] = 1;
+        kernel_LtoR[24] = 2;
+
+       /*
+        1  1  0 -2 -2
+        1  1  0 -2 -2
+        2  2  0 -2 -2
+        2  2  0 -2 -2
+        4  2  0 -2 -4
+        */
+
+    end
+
+    // Shift incoming data into separate RGB buffers
+    always_ff @(posedge clk) begin : Image_buffer
+        if (startofpacket_in) begin
+            row_count <= 0;
+            col_count <= 0;
+
+            for (int i = 0; i < (image_width*4 + 6); i++) begin
+                red_buffer[i] <= 0;
+                green_buffer[i] <= 0;
+                blue_buffer[i] <= 0;
+            end
+        end
+		  
+		  if (ready && valid) begin
+            // Shift the buffers left for red, green, and blue
+            for (int i = 0; i < (image_width*4 + 6); i++) begin
+                red_buffer[i] <= red_buffer[i+1];
+                green_buffer[i] <= green_buffer[i+1];
+                blue_buffer[i] <= blue_buffer[i+1];
+            end
+            // Insert new data for each color component
+            red_buffer[(image_width*4 + 6)] <= red_in;
+            green_buffer[(image_width*4 + 6)] <= green_in;
+            blue_buffer[(image_width*4 + 6)] <= blue_in;
+
+            if (col_count == 319) begin
+                col_count <= 0;
+                row_count <= row_count + 1;
+            end
+
+            else begin
+                col_count <= col_count + 1;
+            end
+        end
+    end
+
+    // Blur images and detect edges
+    always_ff @(posedge clk) begin : Convolution
+        // Reset variables for every pixel
+        conv_result_r = 0;
+        conv_result_g = 0;
+        conv_result_b = 0;
+        
+        TtoB_edge_result_r = 0;
+        TtoB_edge_result_g = 0;
+        TtoB_edge_result_b = 0;
+        LtoR_edge_result_r = 0;
+        LtoR_edge_result_g = 0;
+        LtoR_edge_result_b = 0;
+
+        TtoB_grey_result = 0;
+        LtoR_grey_result = 0;
+
+        // Reset variables at the start of a new image
+        if ((row_count == 0) && (col_count == 0)) begin
+            blur_start <= 9'b0010100010;
+            blur_end <= 9'b0010100010;
+            head_detected <= 0;
+            finish_blur <= 0;
+            temp_blur_start <= 0;
+            temp_blur_end <= 0;
+            blur_pixels = 0;
+            face_ending <= 0;
+        end
+
+        // Convolute RGB
+        for (int i = 0; i < 5; i++) begin
+            for (int j = 0; j < 7; j++) begin
+                conv_result_r = conv_result_r + (red_buffer[(i * image_width) + j] << kernel_blur[((7 * i) + j)]);
+                conv_result_g = conv_result_g + (green_buffer[(i * image_width) + j] << kernel_blur[((7 * i) + j)]);
+                conv_result_b = conv_result_b + (blue_buffer[(i * image_width) + j] << kernel_blur[((7 * i) + j)]);
+            end
+        end
+
+        // Apply edge detection to RGB
+        for (int i = 0; i < 5; i++) begin
+            for (int j = 0; j < 5; j++) begin
+                // Top to bottom edge filter
+                if (i < 3) begin
+                    TtoB_edge_result_r = TtoB_edge_result_r + (red_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                    TtoB_edge_result_g = TtoB_edge_result_g + (green_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                    TtoB_edge_result_b = TtoB_edge_result_b + (blue_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                end
+                else begin
+                    TtoB_edge_result_r = TtoB_edge_result_r - (red_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                    TtoB_edge_result_g = TtoB_edge_result_g - (green_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                    TtoB_edge_result_b = TtoB_edge_result_b - (blue_buffer[(i * image_width) + j] << kernel_TtoB[((5 * i) + j)]);
+                end
+
+                // Left to right edge filter
+                if (j < 3) begin
+                    LtoR_edge_result_r = LtoR_edge_result_r + (red_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                    LtoR_edge_result_g = LtoR_edge_result_g + (green_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                    LtoR_edge_result_b = LtoR_edge_result_b + (blue_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                end
+                else begin
+                    LtoR_edge_result_r = LtoR_edge_result_r - (red_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                    LtoR_edge_result_g = LtoR_edge_result_g - (green_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                    LtoR_edge_result_b = LtoR_edge_result_b - (blue_buffer[(i * image_width) + j] << kernel_LtoR[((5 * i) + j)]);
+                end
+            end
+        end
+
+        // Convert edge data from RGB to greyscale
+        TtoB_grey_result = (TtoB_edge_result_r << 5) // Multiply by 32
+                            + (TtoB_edge_result_g << 6) // Multiply by 64
+                            + (TtoB_edge_result_b << 4); // Multiply by 16
+        
+        LtoR_grey_result = (LtoR_edge_result_r << 5) // Multiply by 32
+                            + (LtoR_edge_result_g << 6) // Multiply by 64
+                            + (LtoR_edge_result_b << 4); // Multiply by 16
+
+        if (ready && valid) begin
+				 // Reset variables at th start of a new line
+				 if (col_count == 319) begin
+					  if ((temp_blur_start != 0) && (temp_blur_end != 0)) begin
+							blur_start <= temp_blur_start;
+							blur_end <= temp_blur_end;
+					  end
+
+					  if ((head_detected) && (!face_ending))begin
+							blur_start <= temp_blur_start - 5;
+					  end
+
+					  temp_blur_start <= 0;
+					  temp_blur_end <= 0;
+				 end
+
+				 // If the top of the head is detected at the middle of the image, raise a flag (must be past row 5 for valid convolution)
+				 if (!head_detected) begin
+					  if (((TtoB_grey_result > 0) || (LtoR_grey_result > 0)) && ((col_count >= blur_start - 30) && (col_count <= blur_start + 30)) && (row_count > 5)) begin
+							head_detected <= 1;
+							blur_pixels = 1;
+							temp_blur_start <= col_count;
+							temp_blur_end <= col_count;
+					  end
+
+					  // For no blur, pass through the data
+					  data_out <= data_in;
+				 end
+
+				 // Check if blurring is finished or if pixels are within blurring bounds
+				 else begin
+					  if (finish_blur) begin
+							// For no blur, pass through the data
+							data_out <= data_in;
+					  end
+
+					  else begin
+							// Check if pixel is not within dynamic blurring boundary (must be past column 5 for valid convolution)
+							if ((col_count < blur_start - 5) || (col_count > (blur_end + 5)) || (col_count < 7)) begin
+								 // For no blur, pass through the data
+								 data_out <= data_in;
+								 blur_pixels = 0;
+							end
+
+							// Blur face and check for edges on face
+							else begin
+								 // Check that pixel is edge
+								 if ((TtoB_grey_result > 0) || (LtoR_grey_result > 0)) begin
+									  // Continuously check for the last edge in the image
+									  if (blur_pixels) begin
+											temp_blur_end <= col_count;
+
+											// If the face start pixel begins to move to the right
+											if (temp_blur_start > (blur_start + 5)) begin
+												 face_ending <= 1;
+											end
+									  end
+
+									  // For first edge pixel on left side, raise a flag and set temp_blur_start
+									  else begin
+											temp_blur_start <= col_count;
+											temp_blur_end <= col_count;
+											blur_pixels = 1;
+									  end
+								 end
+
+								 // Where face edge not detected properly, assume face broadens out at 22.5 degrees
+								 if (!face_ending) begin
+									  if ((col_count > (blur_start + 10)) && (temp_blur_start == 0)) begin
+											if (col_count % 2 == 0) begin
+												 temp_blur_start <= blur_start - 1;
+												 blur_pixels = 1;
+											end
+											else begin
+												 temp_blur_start <= blur_start;
+												 blur_pixels = 1;
+											end
+									  end
+
+									  if ((col_count > (blur_end + 10)) && (temp_blur_end == 0)) begin
+											if (col_count % 2 == 0) begin
+												 temp_blur_end <= blur_end + 1;
+												 blur_pixels = 0;
+											end
+											else begin
+												 temp_blur_end <= blur_end;
+												 blur_pixels = 0;
+											end
+									  end
+								 end
+
+								 // If the face is ending, where face edge not detected properly, slowly narrow down until face is finished
+								 if (face_ending) begin
+									  if (temp_blur_start < blur_start) begin
+											if (col_count % 2 == 0) begin
+												 temp_blur_start <= blur_start + 1;
+											end
+											else begin
+												 temp_blur_start <= blur_start;
+											end
+									  end
+
+									  if ((temp_blur_end > blur_end) || (temp_blur_end < blur_end - 10)) begin
+											if (col_count % 2 == 0) begin
+												 temp_blur_end <= blur_end - 1;
+											end
+											else begin
+												 temp_blur_end <= blur_end;
+											end
+									  end
+
+									  if (blur_end - blur_start <= 5) begin
+											finish_blur <= 1;
+									  end
+								 end
+							end
+					  end
+				 end
+				 
+				 // Blur the pixels
+				 if (blur_pixels) begin
+						if ((conv_result_r[9:6] > 10) && (conv_result_g[9:6] > 10) && (conv_result_b[9:6] > 10)) begin
+							conv_result_r[9:6] = (conv_result_r[9:6]+red_in) >> 1;
+							conv_result_g[9:6] = (conv_result_g[9:6]+green_in) >> 1;
+							conv_result_b[9:6] = (conv_result_b[9:6]+blue_in) >> 1;
+						end
+					  // Combine the normalized results for each color component
+					  data_out <= {conv_result_r[9:6], conv_result_g[9:6], conv_result_b[9:6]};
+				 end
+				 
+				 // Output the input pixel
+				 else begin
+					  // For no blur, pass through the data
+					  data_out <= data_in;
+				 end
+        end
+    end
+
+endmodule

From 18d041a14bb8a2c914e3c900b205c8a3ef2583ac Mon Sep 17 00:00:00 2001
From: RossGazis <rgaz8196@uni.sydney.edu.au>
Date: Thu, 31 Oct 2024 00:03:26 +1100
Subject: [PATCH 4/5] hopefully this lets me pull request

---
 src/FPGA_TO_NANO/image_sending.qpf      | 31 +++++++++++++++++++++++++
 src/image_send_select/image_sending.qpf | 31 +++++++++++++++++++++++++
 2 files changed, 62 insertions(+)
 create mode 100644 src/FPGA_TO_NANO/image_sending.qpf
 create mode 100644 src/image_send_select/image_sending.qpf

diff --git a/src/FPGA_TO_NANO/image_sending.qpf b/src/FPGA_TO_NANO/image_sending.qpf
new file mode 100644
index 0000000..42057a9
--- /dev/null
+++ b/src/FPGA_TO_NANO/image_sending.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 00:00:23  October 31, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "00:00:23  October 31, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "top_level"
diff --git a/src/image_send_select/image_sending.qpf b/src/image_send_select/image_sending.qpf
new file mode 100644
index 0000000..bcf19c4
--- /dev/null
+++ b/src/image_send_select/image_sending.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 00:00:20  October 31, 2024
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "00:00:20  October 31, 2024"
+
+# Revisions
+
+PROJECT_REVISION = "top_level"

From 1fbc88ea43e59f90bd6ac6bee89e248bcb31d69e Mon Sep 17 00:00:00 2001
From: RossGazis <rgaz8196@uni.sydney.edu.au>
Date: Thu, 31 Oct 2024 00:26:16 +1100
Subject: [PATCH 5/5] Update top_level_motor_driver.sv

---
 .../top_level_motor_driver.sv                 | 34 +++++++++++++++++--
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv b/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv
index 2054ff7..dc26266 100644
--- a/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv
+++ b/src/4_Camera_FFT_Motor_Integration/top_level_motor_driver.sv
@@ -257,15 +257,43 @@ module top_level_motor_driver (
 	.red_pixels(red_pixels),
 	.sop(sop));
 	
-	assign LEDR[16:0] = red_pixels;
-
   // choose what data we are using
   logic decision;
   assign decision = SW[2];
   logic [11:0] display_data;
+
+  assign display_data = (decision) ? image_send_select_fsm_output : rddata;
   
-  assign display_data = (decision) ? colour_data : rddata;
+  // 10 sec delay
+  localparam TEN_SEC_DELAY = 500_000_000;
+  logic [28:0] delay_counter;
+  logic image_ready;
+  always_ff @(posedge CLOCK_50) begin
+        delay_counter <= delay_counter + 1;
+        if (delay_counter == TEN_SEC_DELAY) begin
+                image_ready = 1'b1;
+        end
+        else begin
+                image_ready = 1'b0;
+        end
+  end
+  logic [11:0] image_send_select_fsm_output;
   
+  localparam TABLE_STATE = 4'b0100;
+  localparam ONE_SECOND_DELAY = 50_000_000;
+  image_send_select #(
+        .WAIT_TIME(ONE_SECOND_DELAY),
+        .RESET_TIME(ONE_SECOND_DELAY),
+        .TABLE_STATE(TABLE_STATE)
+  ) iamge_send (
+        .clk(CLOCK_50),
+        .norm_in(rddata),
+        .blur_in(12'b0000_1111_0000),
+        .state(4'b0100),
+        .image_ready(image_ready),
+        .reset_signal(LEDR[17]),
+        .data_out(image_send_select_fsm_output)
+  );
   // in case we want to interface with the vga
   vga_interface vgai0 (
 			 .clk_clk(clk_25_vga),                                         //                                       clk.clk