ControlFPGA/Controller.out.sdc at master · dariosol/ControlFPGA · GitHub

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## Generated SDC file "Controller.out.sdc"

## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors.  Please refer to the
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Full Version"

## DATE    "Tue Mar 11 16:18:12 2014"

##
## DEVICE  "EP4SGX530KH40C2"
##


#**************************************************************
# Time Information
#**************************************************************

#set_time_format -unit ns -decimal_places 3


#**************************************************************
# Create Clock
#**************************************************************

#create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
#create_clock -name {OSCILL_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSCILL_50}]


#**************************************************************
# Create Generated Clock
#**************************************************************

#create_generated_clock -name {PLL_INST|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {PLL_INST|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -divide_by 5 -master_clock {OSCILL_50} [get_pins {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]


############################################################

set_time_format -unit ns -decimal_places 3


#
#
# Input clocks (free running)
#
#
create_clock -name {OSCILL_50} -period 20 [get_ports {OSCILL_50}]
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]

# Note: input_clock_125 generated by pll
#create_generated_clock -name {input_clock_125} -multiply_by 5 -divide_by 2 -source [get_pins {ethlink_inst|PLL|altpll_refclk2_inst|altpll_component|auto_generated|pll1|inclk[0]}] [get_pins {ethlink_inst|PLL|altpll_refclk2_inst|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {input_clock_125} -source [get_pins {ethlink_inst|PLL|altpll_refclk2_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 5 -divide_by 2 -master_clock {OSCILL_50}  [get_pins {ethlink_inst|PLL|altpll_refclk2_inst|altpll_component|auto_generated|pll1|clk[0]}]
# Note: input_clock_40 generated by pll
create_generated_clock -name {PLL_INST|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {PLL_INST|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -divide_by 5 -master_clock {OSCILL_50} [get_pins {PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]

#
# Set false paths to remove irrelevant setup and hold analysis
#
set_false_path -from [get_clocks {OSCILL_50}] -to [get_clocks {input_clock_125}]


#**************************************************************
# Set Clock Latency
#**************************************************************


#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {OSCILL_50}] -rise_to [get_clocks {OSCILL_50}]  0.020
set_clock_uncertainty -rise_from [get_clocks {OSCILL_50}] -fall_to [get_clocks {OSCILL_50}]  0.020
set_clock_uncertainty -fall_from [get_clocks {OSCILL_50}] -rise_to [get_clocks {OSCILL_50}]  0.020
set_clock_uncertainty -fall_from [get_clocks {OSCILL_50}] -fall_to [get_clocks {OSCILL_50}]  0.020
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020


#**************************************************************
# Set Input Delay
#**************************************************************


#**************************************************************
# Set Output Delay
#**************************************************************


#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]


#**************************************************************
# Set False Path
#**************************************************************


#**************************************************************
# Set Multicycle Path
#**************************************************************


#**************************************************************
# Set Maximum Delay
#**************************************************************


#**************************************************************
# Set Minimum Delay
#**************************************************************


#**************************************************************
# Set Input Transition
#**************************************************************