function_static.v

// The design module - Static Function Example
module stat_func(clk, rst_n, result);
    input  wire clk;
    input  wire rst_n;
    output reg  [7:0] result;
	
    reg [7:0] x = 0; 

    function [7:0] fstat(input [7:0] in);
        begin
            x = x + in;
            fstat = x;
        end
    endfunction

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            result <= 8'd0;
        else
            result <= fstat(8'd1);
    end

endmodule

//The testbench - Static Function Example
module tb;

    reg clk;
    reg rst_n;
    wire [7:0] result;

    stat_func dut (.*);

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst_n = 0;
        #12 rst_n = 1;
    end

    initial begin
        repeat(10) begin
            @(posedge clk);
            $display("time=%0t result=%0d", $time, result);
        end
        $finish;
    end

endmodule

// Run Script to execute the above design in Modelsim

/*

vlib work
vlog function_static.v
vsim tb
add wave -position insertpoint sim:/tb/*
run -all

*/