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<!DOCTYPE html>
<html lang="en">
<head>
<!-- Basic Page Needs
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<title>Dionysios Diamantopoulos</title>
<meta name="description" content="Personal web site of Dionysios Diamantopoulos. Thanks to Robert Berki and Jenn Pereira">
<meta name="keywords" content="Many-accelerator Energy/Performance Efficient Architectures, Hardware/Software co-Design, DSP Architectures for Telecom Applications, RTL-to-GDSII, Multi-clock domain crossing, Multi-voltage islands crossing, FPGA-in-the-loop Virtual Prototyping, Hihg-Level-Synthesis, Multi-processor System-on-Chip, 2-D/3-D Network-on-Chip, Jitter-free clock-tree synthesis, 3-D chip stacking, Low-power/Thermal-aware VLSI Design, Real-time Debugging, FPGAs: Xilinx (ISE,Vivado,Vivado HLS, Coregen, Chipscope, EDK, SDK), Altera (Quartus), Actel (Libero), Synopsys (Synplify), ASICs: Synopsys (Design Compiler, Primetime), Cadence (IUS, SOC Encounter, Virtuoso)">
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<a class="navbar-brand" href="index.html">Dionysios Diamantopoulos, PhD</a>
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<li><a href="#tf-about" class="page-scroll">About</a></li>
<li><a href="#tf-team" class="page-scroll">Portfolio</a></li>
<li><a href="#tf-services" class="page-scroll">Specialties</a></li>
<li><a href="#tf-works" class="page-scroll">Publications</a></li>
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<h1>Welcome on <strong><span class="color">board</span></strong></h1>
<p class="lead">"If one does not know to which port one is sailing, no wind is <strong>favorable</strong>", Lucius Annaeus Seneca<br>
"It is not the ship so much as the <strong>skillful sailing</strong> that assures the <strong>prosperous voyage"</strong>, George William Curtis<br>
"What can we gain by sailing to the moon if we are not able to cross the <strong>abyss</strong> that separates <strong>us from ourselves</strong>?", Thomas Merton</p>
<a href="#tf-about" class="fa fa-angle-down page-scroll"></a>
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<!-- About Us Page
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<p><a href="./cv/diamantopoulos_cv.pdf"> <img src="img/cv.jpg" class="img-responsive"> </a></p>
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<div class="col-md-8">
<div class="about-text">
<div class="section-title">
<p class="lead">
<strong>Disclaimer:</strong> The postings on this site are my own and don't necessarily represent IBM's positions, strategies, or opinions.<br><br>
</p>
"Is there a single greater thing you can teach an 8, 9, or 10-year old than to sail solo? Name me another activity that teaches geometry, mechanics, and physics while showing a small child that the mind always matters more than brute strength, and that size and gender are irrelevant to success. A sport where the playing field of wind and water mutates with every race to remind them that nature is ever-dynamic – yet enforces rules of right-of-way, sportsmanship, and marine safety. Lessons that train them to assemble complex sails and rigging, wash their own clothes, and not panic when capsizing. Lessons that teach them to trust their judgement, take responsibility for their decisions and not to blame anyone/anything else other than themselves. A lifestyle that begins with a love for the water, and ends with a wizard-like ability to read its secret language of waves, clouds, currents and the predictable movement of a boat. Sailing is a way of seeing the world -- without a digital screen" - Wesley Hsu <br><br>
root@me ~ $ whoami
<h2>Some words <strong>about me</strong></h2>
<hr>
</div>
<p class="intro" align="justify">Developing innovative digital systems & design tools by following a multi-facet approach is my core belief in the last years of my work experience. A strong research background gives me the analytical framework for simplifying complexity. As a hands-on senior engineer I design efficient architectures that support real-world computing platforms. In the past years I have actively participated in several leading multi-national projects delivering world-class digital systems with highly acknowledged contribution in the realization of reconfigurable and application specific computing. Being passionate about all things to do with silicon bring-up, I am constantly looking to deploy my expertise in world-class engineering challenges. Currently, I am a <a href="https://researcher.watson.ibm.com/researcher/view.php?person=zurich-DID">Reasearch Scientist</a> at the <a href="https://www.zurich.ibm.com/cci/">Cloud and AI Systems Research Department</a> of <a href="https://www.zurich.ibm.com">IBM Research Europe - Zurich Laboratory</a>. Previously I was a Post-Doc Reasearcher at the Heterogeneous Cognitive Computing Systems Group of the same department, researching novel architectures for energy-efficient FPGA accelerators, towards HPC, Big Data, and IoT applications (project <a href="http://oprecomp.eu/"> FET-H2020 Open transPREcision COMPuting</a>). Before joining IBM Research, I was a PhD researcher at <a href="http://www.microlab.ntua.gr"> Microlab-NTUA</a> and a research associate at <a href="http://www.iccs.gr/eng/">ICCS</a>.</p>
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<strong>Insight</strong> - <em>Passionate about all things to do with silicon bring-up.</em>
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<span class="fa fa-dot-circle-o"></span>
<strong>Skills</strong> - <em>Multi-disciplinary engineering profile & collaborative research focus.</em>
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<h2>Selected <strong>Work Samples</strong></h2>
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<img src="img/work/1.jpg" alt="..." class="img-rounded team-img">
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<h3>Project SPARTAN</h3>
<p>Principal Investigator</p>
<p>Speeding-up computer vision algorithms (up to 1.111x) with customized FPGA accelerators, for autonomous space rover navigation.</p>
</div>
</div>
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<div class="item">
<div class="thumbnail">
<img src="img/work/2.jpg" alt="..." class="img-rounded team-img">
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<h3>Project Plug&Chip</h3>
<p>PhD Researcher</p>
<p>Accelerating image feature extraction on a car's ECU, targeting automotive industry. A novel virtualization framewrok supports the early design prototyping.</p>
</div>
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<div class="item">
<div class="thumbnail">
<img src="img/work/3.jpg" alt="..." class="img-rounded team-img">
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<h3>Project MemLuv</h3>
<p>PhD Researcher</p>
<p>Extending High Level Synthesis tools with Dynamic Memory Management, on Many-Accelerator systems. The novel technique delivers gains in FPGA's accelerators density (3.8x) and throughput (21.4x).</p>
</div>
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<div class="item">
<div class="thumbnail">
<img src="img/work/4.jpg" alt="..." class="img-rounded team-img">
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<h3>Project NexGenMiliwave</h3>
<p>Senior Digital DSP Designer</p>
<p>Developing and implementing onto FPGA, VHDL IP cores of baseband OFDM transceiver, targeting 1Gbps wireless link on LTE/WiMAX backbone networks.</p>
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<img src="img/work/5.jpg" alt="..." class="img-rounded team-img">
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<h3>Project 3Dnow!</h3>
<p>PhD Researcher</p>
<p>Framework for performing rapid evaluation of three-dimensional (3D) chip stacking SoCs. Experimentation with DSP kernels showed average power savings of 20% on a 2-tiers Leon3 processor.</p>
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<div class="item">
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<img src="img/work/6.jpg" alt="..." class="img-rounded team-img">
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<h3>Project GENESIS</h3>
<p>PhD Researcher</p>
<p>Developing a genetic algorithm-based FPGA placer. The novel placer exhibits inherent parallelism and achieves average reduction of execution run-time and application's delay by 67x and 16%, respectively.</p>
</div>
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<div class="item">
<div class="thumbnail">
<img src="img/work/7.jpg" alt="..." class="img-rounded team-img">
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<h3>Project 3DNocNoc</h3>
<p>PhD Researcher</p>
<p>Experimenting with irregular Network-on-Chip topologies. The proposed heterogeneous 3-D routers lead to 25% higher maximum operation frequency and 39% lower power consumption, as compared to the uniform 3-D NoCs.</p>
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<div class="thumbnail">
<img src="img/work/8.jpg" alt="..." class="img-rounded team-img">
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<h3>Project Safari</h3>
<p>PhD Researcher</p>
<p>Thermal-aware exploration at the micro-architecture level for temperature hotspots elimination. The novel design tool leads to temperature reduction of 17 Kelvin degrees and aging phenomena improvement up to 14%.</p>
</div>
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<h2>Take a look at <strong>my specialties.</strong></h2>
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<small><em>"Skill is the unified force of experience, intellect and passion in their operation", John Ruskin </em></small>
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<div class="col-md-3 col-sm-6 service">
<img src="img/specialties/1.png" alt="..." class="img-circle services-img">
<h4><strong>FPGAs</strong></h4>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Many-accelerator Energy/Performance Efficient Architectures.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> HW/SW co-Design with soft/hard IPs.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Word-length Optimization.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Real-time Debugging.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Ethernet, Wishbone, AMBA, I<sup>2</sup>C, UART IPs.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Constraints-driven Design & Verification.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Families: Xilinx Spartan, Kintex, Virtex, Altera Stratix, Arria.</em><br></div>
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<div class="col-md-3 col-sm-6 service">
<img src="img/specialties/2.png" alt="..." class="img-circle services-img">
<h4><strong>ASICs</strong></h4>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> RTL-to-GDSII hands-on flow.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Multi-clock domain crossing.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Multi-voltage islands crossing.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Jitter-free clock-tree synthesis.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> 3-D chip stacking.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Low-power/Thermal-aware VLSI Design.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Formal Verification.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Static Timing Analysis with NLDM, CCS.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Libraries: Artisan TSMC 180, 130, 90, 65, 45. Faraday UMC 180, 90, FlexASIC 90, Nangate 45, SAED 90.</em><br></div>
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<div class="col-md-3 col-sm-6 service">
<img src="img/specialties/3.png" alt="..." class="img-circle services-img">
<h4><strong>Archit/res - Design Flows</strong></h4>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> FPGA-in-the-loop Virtual Prototyping.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Hihg-Level-Synthesis C, C++, OpenCL.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Multi-processor System-on-Chip.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> 2-D/3-D Network-on-Chip.</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Micro-architecture Exploitation.</em><br></div>
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<h4><strong>EDA Tools</strong></h4>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> FPGAs: Xilinx (ISE,Vivado,Vivado HLS, Coregen, Chipscope, EDK, SDK), Altera (Quartus), Actel (Libero), Synopsys (Synplify).</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> ASICs: Synopsys (Design Compiler, Primetime, Formality), Cadence (IUS-Ncsim, SOC Encounter, Virtuoso)</em><br></div>
<div align="left"><span class="fa fa-dot-circle-o"></span><em> Other/Common: Mentor (Modelsim, Catapult), Cadence OrCAD, SPICE, Simulink</em><br></div>
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<h2>Some of <strong>the Projects/Organisations</strong> I've collaborated</h2>
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<a href="http://www.esa.int">European Space Agency<img src="img/client/01.png"> </a>
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<a href="http://proteas.microlab.ntua.gr/spartan">SPARTAN, ESA-funded<img src="img/client/02.png"> </a>
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<a href="http://http://www.hipeac.net">HiPEAC<img src="img/client/05.png"> </a>
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<a href="http://www.nexgenmiliwave.eu">NexGenMiliwave, ESPA-funded<img src="img/client/04.png"> </a>
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<a href="http://www.corallia.org">Corallia<img src="img/client/10.png"> </a>
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<a href="http://si-cluster.gr/en">CIDCIP, Helenic Space Technologies and Applications Cluster<img src="img/client/06.png"> </a>
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<a href="http://si-cluster.gr/en">MENELAOS, Helenic Space Technologies and Applications Cluster<img src="img/client/07.png"> </a>
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<a href="http://www.2parma.eu">2PARMA, EU-funded<img src="img/client/08.png"> </a>
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<a href="http://www.daad.gr/gr/26028/index.html">TEAChER, EU-funded<img src="img/client/09.png"> </a>
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<a href="https://zenon.microlab.ntua.gr:8000/sextant">SEXTANT, ESA-funded<img src="img/client/03.png"> </a>
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<h2>Take a look at <strong>my publications</strong></h2>
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<i class="fa fa-quote-left fa-lg fa-pull-left fa-border"></i><small><em> The moment a man sets his thoughts down on paper, however secretly, he is in a sense writing for publication, Raymond Chandler</em></small>
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<h5><a href="https://dblp.org/pers/d/Diamantopoulos:Dionysios.html">Up-to-date list on dblp</a></h5>
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<strong>A1 (English).</strong> PhD Dissertation, D. Diamantopoulos "Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Platforms", 237 pages, July 2015.
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<strong>A1 (Greek).</strong> PhD Dissertation, D. Diamantopoulos "Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Platforms", 280 pages, July 2015.
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<strong>J9.</strong>I. Koutras, K. Maragos, D. Diamantopoulos, K. Siozios, D. Soudris, "On supporting rapid prototyping of embedded systems with reconfigurable architectures," Integr. 58: 91-100, doi: 10.1016/j.vlsi.2017.02.007, March 2017.
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<strong>J8.</strong>C. Kachris, D. Diamantopoulos, G. Ch. Sirakoulis, D. Soudris, "An FPGA-based Integrated MapReduce Accelerator Platform," J. Signal Process. Syst. 87(3): 357-369, doi: 10.1007/s11265-016-1108-7, June 2017.
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<strong>J7.</strong> D. Diamantopoulos, S. Xydis, K. Siozios, D. Soudris, "Mitigating Memory-induced Dark Silicon in Many-Accelerator Architectures," IEEE Computer Architecture Letters ,vol.PP, no.99, pp.1,1 doi: 10.1109/LCA.2015.2410791, March 2015.
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<strong>J6.</strong> D. Diamantopoulos, K. Siozios, S. Xydis, D. Soudris. "GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management)." ACM Transactions on Embedded Computing Systems (TECS) vol.14, no. 1: 18, doi: 10.1145/2629651, January 2015.
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<strong>J5.</strong> Kostavelis, L. Nalpantidis, E. Boukas, M. Aviles Rodrigalvarez, I. Stamoulias, G.Lentaris, D. Diamantopoulos, K. Siozios, D. Soudris, A. Gasteratos. "SPARTAN:Developing a vision system for future autonomous space exploration robots." Journal of Field Robotics vol. 31, no. 1, pp.107-140. doi:10.1002/rob.21484, 2014.
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<strong>J4.</strong> E. Sotiriou-Xanthopoulos, D. Diamantopoulos, K. Siozios, G. Economakos, D. Soudris."A framework for rapid evaluation of heterogeneous 3-D NoC architectures." Elsevier Microprocessors and Microsystems vol. 38, no. 4, pp. 292-303, doi:10.1016/j.micpro.2013.09.003, June 2014.
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<strong>J3.</strong> D. Diamantopoulos, E. Sotiriou-Xanthopoulos, K. Siozios, G. Economakos, D. Soudris."Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs". ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no.5s, Article 168, pp. 1-25, 25 pages, doi:10.1145/2661634, December 2014.
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<strong>J2.</strong> D. Diamantopoulos, K. Siozios and D. Soudris, A Framework for Performing Rapid Evaluation of 3-D SoCs, IET Electronics Letters, pp. 679 - 681, June 2012.
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<strong>J1.</strong> D. Diamantopoulos, K. Siozios, S. Xydis and D. Soudris, A Systematic Methodology for Reliability Improvements on SoC-based Software Defined Radio Systems, VLSI Design, Vol. 2012, Article ID 784945.
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<strong>C16.</strong> D. Diamantopoulos, C. Kachris. "High-level Synthesizable Dataflow MapRe-duce Accelerator for FPGA-coupled Data Centers", Embedded Computer Systems (SAMOS), 2015 International Conference on.
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<strong>C15.</strong> D. Diamantopoulos, S. Xydis, K. Siozios, D. Soudris. "Dynamic memory management in Vivado-hls for scalable many-accelerator architectures." In Applied Reconfigurable Computing (ARC), pp. 117-128. Springer International Publishing, March 2015.
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<strong>C14.</strong> E. Sotiriou-Xanthopoulos, D. Diamantopoulos, G. Economakos. "Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures." In Applied Reconfigurable Computing (ARC), pp. 321-330. Springer International Publishing, March 2015.
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<strong>C13.</strong> K. Siozios, P. Figuli, H. Sidiropoulos, C. Tradowsky, D. Diamantopoulos, K. Maragos, S. Percy Delicia, D. Soudris, J. Becker. "TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools." In Applied Reconfigu-rable Computing (ARC), pp. 103-114. Springer International Publishing, March 2015.
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<strong>C12.</strong> G. Lentaris, I. Stamoulias, D. Diamantopoulos, K. Maragos, K. Siozios, D. Soudris, M. Aviles Rodrigalvarez, M. Lourakis, X. Zabulis, I. Kostavelis, L. Nalpantidis, E. Boukas, A. Gasteratos, "SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms." In Applied Reconfigurable Computing (ARC), pp. 475-486. Springer International Publi-shing, March 2015.
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<strong>C11.</strong> D. Diamantopoulos, G. Economakos, D. Reisis, "Using high-level synthesis to build memory and datapath optimized DSP accelerators," Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on, pp.714,717, doi: 10.1109/ICECS.2014.7050085, December 2014.
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<strong>C10.</strong> D. Diamantopoulos, C. Economakos, D. Soudris, G. Economakos, "A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs," Signal Processing and Information Technology (ISSPIT), 2013 IEEE International Symposium on, pp.000404,000409, 12-15, doi: 10.1109/ISSPIT.2013.6781915, December 2013.
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<strong>C9.</strong> D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos, D. Soudris, "HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips," Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International, pp.2194,2199, 20-24, doi: 10.1109/IPDPSW.2013.202, May 2013.
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<strong>C8.</strong> G. Lentaris, D. Diamantopoulos, G. Stamoulias, K. Siozios, D. Soudris, M.A. Rodrigalvarez, "FPGA-based path-planning of high mobility rover for future planetary missions," Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on, pp.85,88, doi: 10.1109/ICECS.2012.6463793, December 2012.
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<strong>C7.</strong> D. Diamantopoulos, K. Siozios, G. Lentaris, D. Soudris, M.A. Rodrigalvarez, "SPARTAN project: On profiling computer vision algorithms for rover naviga-tion," Adaptive Hardware and Systems (AHS), 2012 NASA/ESA Conference on, pp.174,181, doi: 10.1109/AHS.2012.6268647, June 2012.
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<strong>C6.</strong> G. Lentaris, D. Diamantopoulos, K. Siozios, D. Soudris, M.A. Rodrigalvarez, "Hardware implementation of stereo correspondence algorithm for the Exo-Mars mission," Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on , pp.667,670, doi: 10.1109/FPL.2012.6339173, August 2012.
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<strong>C5.</strong> D. Diamantopoulos, P. Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis, D. Soudris, "Configurable baseband digital transceiver for Gbps wireless 60 GHz communications," Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on, pp.192,195, doi: 10.1109/ICECS.2011.6122246, December 2011.
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<strong>C4.</strong> E. Sotiriou-Xanthopoulos, D. Diamantopoulos, G. Economakos, D. Soudris, "Design and experimentation with low-power morphable multipliers," Elec-tronics, Circuits and Systems (ICECS), 2011 18th IEEE International Confe-rence on , vol., no., pp.752,755, doi: 10.1109/ICECS.2011.6122383, December 2011.
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<strong>C3.</strong> K. Siozios, D. Diamantopoulos, I. Kostavelis, E. Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, M. Aviles, I. Anagnostopoulos, SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications, in Proceedings of the 6th Internatio-nal Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), doi: 10.1109/ReCoSoC.2011.5981524, pp.1,9, June 2011.
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<strong>C2.</strong> D. Diamantopoulos, K. Siozios, S. Xydis, D. Soudris, "Thermal optimization for micro-architectures through selective block replication," Embedded Computer Systems (SAMOS), 2011 International Conference on, pp.59,66,doi: 10.1109/SAMOS.2011.6045445, July 2011.
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<strong>C1.</strong> D. Diamantopoulos, K. Siozios, D. Bekiaris, D. Soudris, "A novel methodology for architecture-level exploration of 3D SoCs," Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on, pp.1,6, doi: 10.1109/DTIS.2011.5941425, April 2011.
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<strong>W15.</strong> D. Diamantopoulos, C. Kachris and D. Soudris, "MapReduce FPGA Acceleration for High Performance Computing Machines", Workshop on Reconfigurable Computing for HPC and HPDA (ReC4P), London, UK, August 31, 2015.
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<strong>W14.</strong> D. Diamantopoulos, I. Galanis, K. Siozios, G. Economakos, and D. Soudris, "A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms", Workshop on Reconfigurable Computing (WRC), 2015.
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<strong>W13.</strong> D. Diamantopoulos, I. Galanis, K. Siozios, G. Economakos, and D. Soudris, "A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms", Workshop on Reconfigurable Computing (WRC), 2015.
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<strong>W12.</strong> D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos and D. Soudris, HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips, Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES), May 20-24th, 2013. <div class="clearfix"></div>
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<strong>W11.</strong> D. Diamantopoulos, P. Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis and D. Soudris, A Reconfigurable Baseband Architecture for Gbps Wireless 60 GHz Communications, Fifth Friday Workshop on Designing for Embedded Parallel Computing Platforms (DEPCP), March 22, 2013, Grenoble, France.
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<a href="http://proteas.microlab.ntua.gr/ksiop/short_description/short_wrc_2013_spartan.html">
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<strong>W10.</strong> G. Lentaris, D. Diamantopoulos, K. Siozios, I. Stamoulias, I. Kostavelis, E. Boukas, L. Nalpantidis, D. Soudris, A. Gasteratos, and M. Aviles, SPARTAN: Efficient Implementation of Computer Vision Algorithms for Autonomous Rover Navigation, Workshop on Reconfigurable Computing (WRC), Jan. 2013, Germany.
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<a href="https://www.researchgate.net/publication/255926863_An_FPGA_implementation_of_the_SURF_algorithm_for_the_ExoMars_programme">
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<strong>W9.</strong> G. Lentaris, I. Stamoulias, D. Diamantopoulos, K. Siozios, and D. Soudris, An FPGA implementation of the SURF algorithm for the ExoMars programme, Workshop on Reconfigurable Computing (WRC), Jan. 2013, Germany.
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<a href="http://proteas.microlab.ntua.gr/ksiop/short_description/short_wrc_2013_genetic.html">
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<strong>W8.</strong> D. Diamantopoulos, K. Siozios, and D. Soudris, A Framework for Performing Fault-Tolerant Placement Based on Genetic Algorithm, Workshop on Recon-figurable Computing (WRC), Jan. 2013, Germany.
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<strong>W7.</strong> D. Diamantopoulos, K. Siozios, S. Xydis and D. Soudris, A genetic algorithm-based FPGA placer for multi-core processors, Fifth Friday Workshop on Designing for Embedded Parallel Computing Platforms (DEPCP), March 22, 2013, Grenoble, France <div class="clearfix"></div>
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<a href="https://www.researchgate.net/publication/255924168_Towards_Accelerating_Computer_Vision_Algorithms_Targeting_to_Space_Applications_with_a_Heterogeneous_Platform">
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<strong>W6.</strong> D. Diamantopoulos, K. Siozios, I. Stamoulias, G. Lentaris, D. Soudris and M. Aviles, Towards Computer Vision FPGA Acceleration, DATE Friday Workshop on Reconfigurable Computing (Configcomp), March 22, 2013, Grenoble, France.
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<strong>W5.</strong> D. Diamantopoulos, K. Siozios, S. Xydis and D. Soudris, A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms, Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures (PARMA), Jan. 2013.
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<a href="https://www.researchgate.net/publication/255910810_ON_DESIGNING_SELF-AWARE_RECONFIGURABLE_PLATFORMS">
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<strong>W4.</strong> K. Siozios, H. Sidiropoulos, D. Diamantopoulos, P. Figuli, D. Soudris, M. Hubner and J. Becker, On Designing Self-Aware Reconfigurable Platforms, Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), pp. 14-17, Norway, 2012.
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<strong>W3.</strong> D. Diamantopoulos, G. Lentaris, K. Siozios, D. Soudris and M. Aviles, Towards Accelarating Computer Vision Algorithms Targeting to Space Applications with a Heterogeneous Platform, Friday Workshop on Designing for Embed-ded Parallel Computing Platforms: Architectures, Design Tools, and Applications at DATE 2012, Germany, 2012.
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<strong>W2.</strong> K. Siozios, D. Diamantopoulos, H. Sidiropoulos, A. Papanikolaou, and D. Soudris, Rapid Evaluation of 3-D Interconnection Schemes , DATE 2011 3D Integration Workshop, Grenoble, 2011, France.
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<a href="https://www.researchgate.net/publication/255920505_A_Co-design_Methodology_for_Implementing_Computer_Vision_Algorithms_for_Rover_Navigation_onto_Reconfigurable_Hardware">
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<strong>W1.</strong> M. Aviles, K. Siozios, D. Diamantopoulos, L. Nalpantidis, I. Kostavelis, E. Boukas, D. Soudris and A. Gasteratos, A Co-design Methodology for Imple-menting Computer Vision Algorithms for Rover Navigation onto Reconfigu-rable Hardware,Workshop on Computer Vision on Low-Power Reconfigurable Architectures, International Conferenceon Field Programmable Logic and Applications, Sept. 2011, Chania, Greece.
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<h5>2nd award Cadence Design Systems, Inc.</h5>
<p>Many thanks @ Cadence Design Systems, Inc. for the prize of <strong><a href="http://www.cadence.com/cadence/events/Pages/designcontest2012.aspx"> Automotive Embedded System contest</a></strong>. CDNLive EMEA 2013 was not only an outstanding event but also a great opportunity for Cadence to attribute add-on value for every word of the motto "connect-share-inspire", justifying why is the No1 EDA company worldwide. Also many thanks to Dr. Kostas Siozios, Prof. George Economakos and Prof. Dimitrios Soudris for their guidance and support throughout this project.</p>
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<p><strong><a href="http://www.arte.tv/fr/7750486.html">Greece: the gods of technology.</a></strong> Since 2011 Greece tries to organize its industry in "clusters". After the information technology sector, today is the aerospace industry, which is trying to win contracts from the European Space Agency but also among Americans, Israelis and Chinese. The story in Athens from Adéa Guillot.</p>
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<p>HiPEAC student Dionysios Diamantopoulos from NTU Athens visits Cadence’s office in Munich as a finalist of their sponsored thesis contest for automotive embedded systems.<strong><a href="https://www.hipeac.net/assets/public/publications/newsletter/hipeacinfo33.pdf"> Report in HiPEACinfo 33, pages 18-19</a>.</strong></p>
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<p>A complete hands-on tutorial on Robotic Operating System (ROS). Only in Greek. <strong><a href="http://www.e-compupress.gr/magazines/preview/lf/8/#/14/"> Report in Linux Inside, Issue 8, pages 68-69</a>.</strong></p>
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<p>A cover story for projects SPARTAN-SEXTANT funded from ESA. Only in Greek. <strong><a href="http://www.epikaira.gr"> Report in Epikaira, Issue 116, pages 102-103</a>.</strong></p>
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<p>An article covering aspects of the projects SPARTAN-SEXTANT funded from ESA. Only in Greek. <strong><a href="http://www.e-typos.com"> Report in Eleytheros Typos, Issue Monday 1 October 2012, page 51</a>.</strong></p>
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Cloud FPGAs & Tape Group,<br>
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