Hello!
We love your bot in the MiSTer FPGA discord. I have noticed a possible issue recently. Case statements in vhdl do not apparently get syntax highlighting
https://github.com/MiSTer-devel/GBA_MiSTer/blob/master/rtl/gba_sound.vhd#L422-L425
https://github.com/MiSTer-devel/GBA_MiSTer/blob/master/rtl/gba_sound_ch1.vhd#L265-L271
It looks like the vhdl markdown tag doesn't get applied for some reason. I made sure to test that it wasn't the linter/parser (which I assumed might be shared between this project and discord).

Thank you!