diff --git a/Firmware/.vs/BMSLadder/v14/.atsuo b/Firmware/.vs/BMSLadder/v14/.atsuo new file mode 100644 index 0000000..abe4feb Binary files /dev/null and b/Firmware/.vs/BMSLadder/v14/.atsuo differ diff --git a/Firmware/CellManagement.c b/Firmware/CellManagement.c index aafae27..80b0236 100644 --- a/Firmware/CellManagement.c +++ b/Firmware/CellManagement.c @@ -5,7 +5,7 @@ #include "HardwareDefines.h" #define OVERVOLTAGE_THRESHOLD_MILLIVOLTS 4150 -#define BALANCE_THRESHOLD_MILLIVOLTS 4050 +#define BALANCE_THRESHOLD_MILLIVOLTS 4100 #define UNDERVOLTAGE_THRESHOLD_MILLIVOLTS 2800 /* @@ -13,12 +13,13 @@ Under Voltage @ 2.6V -> 2uA Average Running @ 3V -> 2.5uA Average Running @ 4V -> 2.6uA Average - Balancing @ 4.1V -> Approximately 700mA with current settings - Over voltage @ 4.3V -> Approximately 700mA with current settings + Balancing @ 4.1V -> Approximately 120mA with current settings + Over voltage @ 4.15V -> Approximately 700mA with current settings */ inline void BalanceOn(bool highCurrent) { + TCA0_SINGLE_CMP0 = 128; //12.5% duty cycle on the balance FET, period around 80ms if (highCurrent) { TCA0_SINGLE_CMP0 = 768; //75% duty cycle on the balance FET, period around 80ms diff --git a/Firmware/Debug/BMSLadder.elf b/Firmware/Debug/BMSLadder.elf index 6836253..6f43825 100644 Binary files a/Firmware/Debug/BMSLadder.elf and b/Firmware/Debug/BMSLadder.elf differ diff --git a/Firmware/Debug/BMSLadder.hex b/Firmware/Debug/BMSLadder.hex index b4e685c..87390d3 100644 --- a/Firmware/Debug/BMSLadder.hex +++ b/Firmware/Debug/BMSLadder.hex @@ -2,7 +2,7 @@ :1000100019C018C017C016C015C014C013C012C034 :1000200011C010C00FC00EC00DC00CC00BC00AC064 :1000300009C008C011241FBECFEFCDBFDFE3DEBF74 -:10004000DFD04DC1DDCFE0E0F6E081E5828381E0E5 +:10004000E9D05BC1DDCFE0E0F6E081E5828381E0CD :1000500080830895E0EAF0E080E1808382E081839C :100060000895E0E0F6E08081816080830895E0E01B :10007000F6E080818E7F80830895E0E0F6E086835D @@ -11,38 +11,39 @@ :1000A000F6DFE0E0F6E02385216023870895CF9214 :1000B000DF92EF92FF92CEDFC6DFD3DF8DE1ECDF80 :1000C0008DE1EADF9C0140E050E060E070E381E117 -:1000D00090E0C7D069017A01CADFC701B601FF907D +:1000D00090E0D5D069017A01CADFC701B601FF906F :1000E000EF90DF90CF900895CF93DF93EC01DFDFA7 :1000F000688379838A839B83663320E17207810555 -:10010000910568F080E093E08093280A9093290A93 -:10011000E0E0FAE080818160808383E01FC0623D7F -:100120007F408105910538F0E0E0FAE08081816050 -:10013000808382E013C0E0E0FAE080818E7F8083DC -:100140001092020A88819981AA81BB81803F9A40DE -:10015000A105B10510F081E001C080E0DF91CF91F1 -:10016000089584E08093100488E48093000480E480 -:1001700080930504089580E094E08093260A90938C -:10018000270A80E890E08093280A9093290A83E167 -:100190008093010A8CE08093000A1092020A08956D -:1001A00085E0809350008895089581E08093500009 -:1001B000889508958091400083FF03C084E0809378 -:1001C0000104089518C0A89580E480930604EFE127 -:1001D000F3E03197F1F700C0000080930504992304 -:1001E00049F0FFEF21EE34E0F15020403040E1F7DC -:1001F00000C00000892F9FEF980F8111E4CF089570 -:10020000CF93DF9300D000D0CDB7DEB7A895A9DF9C -:10021000B2DFD0DFCE01019667DF823069F0833034 -:1002200019F08130A9F40FC084E08093050480E4C4 -:1002300080930604BADF0CC084E08093050482E05A -:10024000C1DFB3DF05C084E08093060481E0BADF3C -:10025000A7DF80E090E02496CDBFDEBFDF91CF9195 -:100260000895052E97FB16F400940FD057FD05D086 -:1002700014D007FC02D046F408C050954095309544 -:1002800021953F4F4F4F5F4F089590958095709502 -:1002900061957F4F8F4F9F4F0895A1E21A2EAA1BA1 -:1002A000BB1BFD010DC0AA1FBB1FEE1FFF1FA21726 -:1002B000B307E407F50720F0A21BB30BE40BF50B23 -:1002C000661F771F881F991F1A9469F760957095AC -:1002D000809590959B01AC01BD01CF010895F894E4 -:0202E000FFCF4E +:10010000910588F0E8E2FAE080E890E0808391834E +:1001100080E093E080839183E0E0FAE08081816079 +:10012000808383E025C0643070418105910568F0CB +:1001300080E890E08093280A9093290AE0E0FAE0B2 +:1001400080818160808382E013C0E0E0FAE08081FA +:100150008E7F80831092020A88819981AA81BB8157 +:10016000803F9A40A105B10510F081E001C080E018 +:10017000DF91CF91089584E08093100488E4809308 +:10018000000480E480930504089580E094E0809367 +:10019000260A9093270A80E890E08093280A90939B +:1001A000290A83E18093010A8CE08093000A10926F +:1001B000020A089585E0809350008895089581E0B3 +:1001C00080935000889508958091400083FF03C07C +:1001D00084E080930104089518C0A89580E480937A +:1001E0000604EFE1F3E03197F1F700C000008093DF +:1001F0000504992349F0FFEF21EE34E0F15020404F +:100200003040E1F700C00000892F9FEF980F811167 +:10021000E4CF0895CF93DF9300D000D0CDB7DEB701 +:10022000A895A9DFB2DFD0DFCE0101965DDF813076 +:10023000A1F0C8F0823051F08330C1F484E08093A3 +:10024000050480E480930604BADF10C084E0809344 +:10025000060482E0C1DFB3DF09C084E080930604B6 +:1002600081E0BADF03C084E080930504A3DF80E06F +:1002700090E02496CDBFDEBFDF91CF910895052E8B +:1002800097FB16F400940FD057FD05D014D007FC4F +:1002900002D046F408C050954095309521953F4FC7 +:1002A0004F4F5F4F089590958095709561957F4F62 +:1002B0008F4F9F4F0895A1E21A2EAA1BBB1BFD0171 +:1002C0000DC0AA1FBB1FEE1FFF1FA217B307E40735 +:1002D000F50720F0A21BB30BE40BF50B661F771F8D +:1002E000881F991F1A9469F760957095809590956D +:0E02F0009B01AC01BD01CF010895F894FFCF32 :00000001FF diff --git a/Firmware/Debug/BMSLadder.lss b/Firmware/Debug/BMSLadder.lss index d5c1950..6b2b95f 100644 --- a/Firmware/Debug/BMSLadder.lss +++ b/Firmware/Debug/BMSLadder.lss @@ -3,29 +3,29 @@ BMSLadder.elf: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn - 0 .data 00000000 00803f80 00803f80 00000336 2**0 + 0 .data 00000000 00803f80 00803f80 00000352 2**0 CONTENTS, ALLOC, LOAD, DATA - 1 .text 000002e2 00000000 00000000 00000054 2**1 + 1 .text 000002fe 00000000 00000000 00000054 2**1 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .comment 00000030 00000000 00000000 00000336 2**0 + 2 .comment 00000030 00000000 00000000 00000352 2**0 CONTENTS, READONLY - 3 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 00000368 2**2 + 3 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 00000384 2**2 CONTENTS, READONLY - 4 .debug_aranges 000000d0 00000000 00000000 000003a4 2**0 + 4 .debug_aranges 000000d0 00000000 00000000 000003c0 2**0 CONTENTS, READONLY, DEBUGGING - 5 .debug_info 00001e0c 00000000 00000000 00000474 2**0 + 5 .debug_info 00001e1b 00000000 00000000 00000490 2**0 CONTENTS, READONLY, DEBUGGING - 6 .debug_abbrev 00001593 00000000 00000000 00002280 2**0 + 6 .debug_abbrev 00001593 00000000 00000000 000022ab 2**0 CONTENTS, READONLY, DEBUGGING - 7 .debug_line 000007a3 00000000 00000000 00003813 2**0 + 7 .debug_line 000007bc 00000000 00000000 0000383e 2**0 CONTENTS, READONLY, DEBUGGING - 8 .debug_frame 0000017c 00000000 00000000 00003fb8 2**2 + 8 .debug_frame 0000017c 00000000 00000000 00003ffc 2**2 CONTENTS, READONLY, DEBUGGING - 9 .debug_str 000011ec 00000000 00000000 00004134 2**0 + 9 .debug_str 00001211 00000000 00000000 00004178 2**0 CONTENTS, READONLY, DEBUGGING - 10 .debug_loc 000002b3 00000000 00000000 00005320 2**0 + 10 .debug_loc 000002be 00000000 00000000 00005389 2**0 CONTENTS, READONLY, DEBUGGING - 11 .debug_ranges 000000a0 00000000 00000000 000055d3 2**0 + 11 .debug_ranges 000000a0 00000000 00000000 00005647 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: @@ -65,54 +65,31 @@ Disassembly of section .text: 3a: cd bf out 0x3d, r28 ; 61 3c: df e3 ldi r29, 0x3F ; 63 3e: de bf out 0x3e, r29 ; 62 - 40: df d0 rcall .+446 ; 0x200
- 42: 4d c1 rjmp .+666 ; 0x2de <_exit> + 40: e9 d0 rcall .+466 ; 0x214
+ 42: 5b c1 rjmp .+694 ; 0x2fa <_exit> 00000044 <__bad_interrupt>: 44: dd cf rjmp .-70 ; 0x0 <__vectors> 00000046 : -#include "adc.h" - -void ADC0Init() -{ - - ADC0.CTRLC = ADC_PRESC_DIV4_gc /* CLK_PER divided by 4 */ 46: e0 e0 ldi r30, 0x00 ; 0 48: f6 e0 ldi r31, 0x06 ; 6 4a: 81 e5 ldi r24, 0x51 ; 81 4c: 82 83 std Z+2, r24 ; 0x02 - | ADC_REFSEL_VDDREF_gc /* VDD Reference */ - | (1 << ADC_SAMPCAP_bp); /* Sample Capacitance Selection: enabled for reference higher than 1V */ - - - ADC0.CTRLA = 1 << ADC_ENABLE_bp /* ADC Enable: enabled */ 4e: 81 e0 ldi r24, 0x01 ; 1 50: 80 83 st Z, r24 52: 08 95 ret 00000054 : - | 0 << ADC_RUNSTBY_bp; /* Run standby mode: disabled */ -} - -void InternalReferenceInit() -{ - VREF.CTRLA = VREF_ADC0REFSEL_1V1_gc; 54: e0 ea ldi r30, 0xA0 ; 160 56: f0 e0 ldi r31, 0x00 ; 0 58: 80 e1 ldi r24, 0x10 ; 16 5a: 80 83 st Z, r24 - VREF.CTRLB = VREF_ADC0REFEN_bm; //Enable reference, even if nothing is requesting it. 5c: 82 e0 ldi r24, 0x02 ; 2 5e: 81 83 std Z+1, r24 ; 0x01 60: 08 95 ret 00000062 : -} - -void ADC0Enable() -{ - ADC0.CTRLA |= ADC_ENABLE_bm; 62: e0 e0 ldi r30, 0x00 ; 0 64: f6 e0 ldi r31, 0x06 ; 6 66: 80 81 ld r24, Z @@ -121,11 +98,6 @@ void ADC0Enable() 6c: 08 95 ret 0000006e : -} - -void ADC0Disable() -{ - ADC0.CTRLA &= ~ADC_ENABLE_bm; 6e: e0 e0 ldi r30, 0x00 ; 0 70: f6 e0 ldi r31, 0x06 ; 6 72: 80 81 ld r24, Z @@ -134,64 +106,34 @@ void ADC0Disable() 78: 08 95 ret 0000007a : -} - -void ADC0StartConversion(adc_0_channel_t channel) -{ - ADC0.MUXPOS = channel; 7a: e0 e0 ldi r30, 0x00 ; 0 7c: f6 e0 ldi r31, 0x06 ; 6 7e: 86 83 std Z+6, r24 ; 0x06 - ADC0.COMMAND = ADC_STCONV_bm; 80: 81 e0 ldi r24, 0x01 ; 1 82: 80 87 std Z+8, r24 ; 0x08 84: 08 95 ret 00000086 : -} - -bool ADC0ConversionDone() -{ - return (ADC0.INTFLAGS & ADC_RESRDY_bm); 86: 80 91 0b 06 lds r24, 0x060B ; 0x80060b <__RODATA_PM_OFFSET__+0x7f860b> -} 8a: 81 70 andi r24, 0x01 ; 1 8c: 08 95 ret 0000008e : - -adc_result_t ADC0GetConversionResult(void) -{ - return (ADC0.RES); 8e: 80 91 10 06 lds r24, 0x0610 ; 0x800610 <__RODATA_PM_OFFSET__+0x7f8610> 92: 90 91 11 06 lds r25, 0x0611 ; 0x800611 <__RODATA_PM_OFFSET__+0x7f8611> -} 96: 08 95 ret 00000098 : - -adc_result_t ADC0GetConversion(adc_0_channel_t channel) -{ - adc_result_t res; - - ADC0StartConversion(channel); 98: f0 df rcall .-32 ; 0x7a - while (!ADC0ConversionDone()) 9a: f5 df rcall .-22 ; 0x86 9c: 88 23 and r24, r24 9e: e9 f3 breq .-6 ; 0x9a - { - } - res = ADC0GetConversionResult(); a0: f6 df rcall .-20 ; 0x8e - ADC0.INTFLAGS |= ADC_RESRDY_bm; a2: e0 e0 ldi r30, 0x00 ; 0 a4: f6 e0 ldi r31, 0x06 ; 6 a6: 23 85 ldd r18, Z+11 ; 0x0b a8: 21 60 ori r18, 0x01 ; 1 aa: 23 87 std Z+11, r18 ; 0x0b - return res; -} ac: 08 95 ret 000000ae : @@ -229,7 +171,7 @@ uint32_t CellVoltage(void) cc: 70 e3 ldi r23, 0x30 ; 48 ce: 81 e1 ldi r24, 0x11 ; 17 d0: 90 e0 ldi r25, 0x00 ; 0 - d2: c7 d0 rcall .+398 ; 0x262 <__divmodsi4> + d2: d5 d0 rcall .+426 ; 0x27e <__divmodsi4> d4: 69 01 movw r12, r18 d6: 7a 01 movw r14, r20 ADC0Disable(); @@ -264,463 +206,491 @@ cellStatus_t ManageCell(uint32_t* cellVoltage) fc: 72 07 cpc r23, r18 fe: 81 05 cpc r24, r1 100: 91 05 cpc r25, r1 - 102: 68 f0 brcs .+26 ; 0x11e + 102: 88 f0 brcs .+34 ; 0x126 + Over voltage @ 4.15V -> Approximately 700mA with current settings +*/ inline void BalanceOn(bool highCurrent) { + TCA0_SINGLE_CMP0 = 128; //12.5% duty cycle on the balance FET, period around 80ms + 104: e8 e2 ldi r30, 0x28 ; 40 + 106: fa e0 ldi r31, 0x0A ; 10 + 108: 80 e8 ldi r24, 0x80 ; 128 + 10a: 90 e0 ldi r25, 0x00 ; 0 + 10c: 80 83 st Z, r24 + 10e: 91 83 std Z+1, r25 ; 0x01 if (highCurrent) { TCA0_SINGLE_CMP0 = 768; //75% duty cycle on the balance FET, period around 80ms - 104: 80 e0 ldi r24, 0x00 ; 0 - 106: 93 e0 ldi r25, 0x03 ; 3 - 108: 80 93 28 0a sts 0x0A28, r24 ; 0x800a28 <__RODATA_PM_OFFSET__+0x7f8a28> - 10c: 90 93 29 0a sts 0x0A29, r25 ; 0x800a29 <__RODATA_PM_OFFSET__+0x7f8a29> + 110: 80 e0 ldi r24, 0x00 ; 0 + 112: 93 e0 ldi r25, 0x03 ; 3 + 114: 80 83 st Z, r24 + 116: 91 83 std Z+1, r25 ; 0x01 } TCA0_SINGLE_CTRLA |= TCA_SINGLE_ENABLE_bm; - 110: e0 e0 ldi r30, 0x00 ; 0 - 112: fa e0 ldi r31, 0x0A ; 10 - 114: 80 81 ld r24, Z - 116: 81 60 ori r24, 0x01 ; 1 - 118: 80 83 st Z, r24 + 118: e0 e0 ldi r30, 0x00 ; 0 + 11a: fa e0 ldi r31, 0x0A ; 10 + 11c: 80 81 ld r24, Z + 11e: 81 60 ori r24, 0x01 ; 1 + 120: 80 83 st Z, r24 if (*cellVoltage >= OVERVOLTAGE_THRESHOLD_MILLIVOLTS) { bool highCurrentBalance = true; BalanceOn(highCurrentBalance); return CellStatusOverVoltage; - 11a: 83 e0 ldi r24, 0x03 ; 3 - 11c: 1f c0 rjmp .+62 ; 0x15c + 122: 83 e0 ldi r24, 0x03 ; 3 + 124: 25 c0 rjmp .+74 ; 0x170 } if (*cellVoltage >= BALANCE_THRESHOLD_MILLIVOLTS) - 11e: 62 3d cpi r22, 0xD2 ; 210 - 120: 7f 40 sbci r23, 0x0F ; 15 - 122: 81 05 cpc r24, r1 - 124: 91 05 cpc r25, r1 - 126: 38 f0 brcs .+14 ; 0x136 + 126: 64 30 cpi r22, 0x04 ; 4 + 128: 70 41 sbci r23, 0x10 ; 16 + 12a: 81 05 cpc r24, r1 + 12c: 91 05 cpc r25, r1 + 12e: 68 f0 brcs .+26 ; 0x14a + Over voltage @ 4.15V -> Approximately 700mA with current settings +*/ + +inline void BalanceOn(bool highCurrent) { + TCA0_SINGLE_CMP0 = 128; //12.5% duty cycle on the balance FET, period around 80ms + 130: 80 e8 ldi r24, 0x80 ; 128 + 132: 90 e0 ldi r25, 0x00 ; 0 + 134: 80 93 28 0a sts 0x0A28, r24 ; 0x800a28 <__RODATA_PM_OFFSET__+0x7f8a28> + 138: 90 93 29 0a sts 0x0A29, r25 ; 0x800a29 <__RODATA_PM_OFFSET__+0x7f8a29> if (highCurrent) { TCA0_SINGLE_CMP0 = 768; //75% duty cycle on the balance FET, period around 80ms } TCA0_SINGLE_CTRLA |= TCA_SINGLE_ENABLE_bm; - 128: e0 e0 ldi r30, 0x00 ; 0 - 12a: fa e0 ldi r31, 0x0A ; 10 - 12c: 80 81 ld r24, Z - 12e: 81 60 ori r24, 0x01 ; 1 - 130: 80 83 st Z, r24 + 13c: e0 e0 ldi r30, 0x00 ; 0 + 13e: fa e0 ldi r31, 0x0A ; 10 + 140: 80 81 ld r24, Z + 142: 81 60 ori r24, 0x01 ; 1 + 144: 80 83 st Z, r24 if (*cellVoltage >= BALANCE_THRESHOLD_MILLIVOLTS) { bool highCurrentBalance = false; BalanceOn(highCurrentBalance); return CellStatusBalancing; - 132: 82 e0 ldi r24, 0x02 ; 2 - 134: 13 c0 rjmp .+38 ; 0x15c + 146: 82 e0 ldi r24, 0x02 ; 2 + 148: 13 c0 rjmp .+38 ; 0x170 TCA0_SINGLE_CTRLA |= TCA_SINGLE_ENABLE_bm; } inline void BalanceOff(void) { TCA0_SINGLE_CTRLA &= ~TCA_SINGLE_ENABLE_bm; - 136: e0 e0 ldi r30, 0x00 ; 0 - 138: fa e0 ldi r31, 0x0A ; 10 - 13a: 80 81 ld r24, Z - 13c: 8e 7f andi r24, 0xFE ; 254 - 13e: 80 83 st Z, r24 + 14a: e0 e0 ldi r30, 0x00 ; 0 + 14c: fa e0 ldi r31, 0x0A ; 10 + 14e: 80 81 ld r24, Z + 150: 8e 7f andi r24, 0xFE ; 254 + 152: 80 83 st Z, r24 TCA0_SINGLE_CTRLC = 0; - 140: 10 92 02 0a sts 0x0A02, r1 ; 0x800a02 <__RODATA_PM_OFFSET__+0x7f8a02> + 154: 10 92 02 0a sts 0x0A02, r1 ; 0x800a02 <__RODATA_PM_OFFSET__+0x7f8a02> return CellStatusBalancing; } BalanceOff(); if (*cellVoltage >= UNDERVOLTAGE_THRESHOLD_MILLIVOLTS) - 144: 88 81 ld r24, Y - 146: 99 81 ldd r25, Y+1 ; 0x01 - 148: aa 81 ldd r26, Y+2 ; 0x02 - 14a: bb 81 ldd r27, Y+3 ; 0x03 - 14c: 80 3f cpi r24, 0xF0 ; 240 - 14e: 9a 40 sbci r25, 0x0A ; 10 - 150: a1 05 cpc r26, r1 - 152: b1 05 cpc r27, r1 - 154: 10 f0 brcs .+4 ; 0x15a + 158: 88 81 ld r24, Y + 15a: 99 81 ldd r25, Y+1 ; 0x01 + 15c: aa 81 ldd r26, Y+2 ; 0x02 + 15e: bb 81 ldd r27, Y+3 ; 0x03 + 160: 80 3f cpi r24, 0xF0 ; 240 + 162: 9a 40 sbci r25, 0x0A ; 10 + 164: a1 05 cpc r26, r1 + 166: b1 05 cpc r27, r1 + 168: 10 f0 brcs .+4 ; 0x16e { return CellStatusNormal; - 156: 81 e0 ldi r24, 0x01 ; 1 - 158: 01 c0 rjmp .+2 ; 0x15c + 16a: 81 e0 ldi r24, 0x01 ; 1 + 16c: 01 c0 rjmp .+2 ; 0x170 } return CellStatusUnderVoltage; - 15a: 80 e0 ldi r24, 0x00 ; 0 + 16e: 80 e0 ldi r24, 0x00 ; 0 } - 15c: df 91 pop r29 - 15e: cf 91 pop r28 - 160: 08 95 ret + 170: df 91 pop r29 + 172: cf 91 pop r28 + 174: 08 95 ret -00000162 : +00000176 : #define F_CPU 3200000UL #include "util/delay.h" void InitializeIO(void) { PORTA_PIN0CTRL = PORT_ISC_INPUT_DISABLE_gc; - 162: 84 e0 ldi r24, 0x04 ; 4 - 164: 80 93 10 04 sts 0x0410, r24 ; 0x800410 <__RODATA_PM_OFFSET__+0x7f8410> + 176: 84 e0 ldi r24, 0x04 ; 4 + 178: 80 93 10 04 sts 0x0410, r24 ; 0x800410 <__RODATA_PM_OFFSET__+0x7f8410> PORTA_DIR = BALANCE_PIN_MASK | TX_LED_PIN_MASK; - 168: 88 e4 ldi r24, 0x48 ; 72 - 16a: 80 93 00 04 sts 0x0400, r24 ; 0x800400 <__RODATA_PM_OFFSET__+0x7f8400> + 17c: 88 e4 ldi r24, 0x48 ; 72 + 17e: 80 93 00 04 sts 0x0400, r24 ; 0x800400 <__RODATA_PM_OFFSET__+0x7f8400> PORTA_OUTSET = TX_LED_PIN_MASK; //Default LED state is off - 16e: 80 e4 ldi r24, 0x40 ; 64 - 170: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> - 174: 08 95 ret + 182: 80 e4 ldi r24, 0x40 ; 64 + 184: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> + 188: 08 95 ret -00000176 : +0000018a : } void InitializeBalancePWM() { TCA0_SINGLE_PER = 1024; - 176: 80 e0 ldi r24, 0x00 ; 0 - 178: 94 e0 ldi r25, 0x04 ; 4 - 17a: 80 93 26 0a sts 0x0A26, r24 ; 0x800a26 <__RODATA_PM_OFFSET__+0x7f8a26> - 17e: 90 93 27 0a sts 0x0A27, r25 ; 0x800a27 <__RODATA_PM_OFFSET__+0x7f8a27> + 18a: 80 e0 ldi r24, 0x00 ; 0 + 18c: 94 e0 ldi r25, 0x04 ; 4 + 18e: 80 93 26 0a sts 0x0A26, r24 ; 0x800a26 <__RODATA_PM_OFFSET__+0x7f8a26> + 192: 90 93 27 0a sts 0x0A27, r25 ; 0x800a27 <__RODATA_PM_OFFSET__+0x7f8a27> TCA0_SINGLE_CMP0 = 128; //12.5% duty cycle on the balance FET, period around 80ms - 182: 80 e8 ldi r24, 0x80 ; 128 - 184: 90 e0 ldi r25, 0x00 ; 0 - 186: 80 93 28 0a sts 0x0A28, r24 ; 0x800a28 <__RODATA_PM_OFFSET__+0x7f8a28> - 18a: 90 93 29 0a sts 0x0A29, r25 ; 0x800a29 <__RODATA_PM_OFFSET__+0x7f8a29> + 196: 80 e8 ldi r24, 0x80 ; 128 + 198: 90 e0 ldi r25, 0x00 ; 0 + 19a: 80 93 28 0a sts 0x0A28, r24 ; 0x800a28 <__RODATA_PM_OFFSET__+0x7f8a28> + 19e: 90 93 29 0a sts 0x0A29, r25 ; 0x800a29 <__RODATA_PM_OFFSET__+0x7f8a29> TCA0_SINGLE_CTRLB = TCA_SINGLE_CMP0EN_bm | TCA_SINGLE_WGMODE_SINGLESLOPE_gc; - 18e: 83 e1 ldi r24, 0x13 ; 19 - 190: 80 93 01 0a sts 0x0A01, r24 ; 0x800a01 <__RODATA_PM_OFFSET__+0x7f8a01> + 1a2: 83 e1 ldi r24, 0x13 ; 19 + 1a4: 80 93 01 0a sts 0x0A01, r24 ; 0x800a01 <__RODATA_PM_OFFSET__+0x7f8a01> TCA0_SINGLE_CTRLA = TCA_SINGLE_CLKSEL_DIV256_gc; - 194: 8c e0 ldi r24, 0x0C ; 12 - 196: 80 93 00 0a sts 0x0A00, r24 ; 0x800a00 <__RODATA_PM_OFFSET__+0x7f8a00> + 1a8: 8c e0 ldi r24, 0x0C ; 12 + 1aa: 80 93 00 0a sts 0x0A00, r24 ; 0x800a00 <__RODATA_PM_OFFSET__+0x7f8a00> TCA0_SINGLE_CTRLC = 0; - 19a: 10 92 02 0a sts 0x0A02, r1 ; 0x800a02 <__RODATA_PM_OFFSET__+0x7f8a02> - 19e: 08 95 ret + 1ae: 10 92 02 0a sts 0x0A02, r1 ; 0x800a02 <__RODATA_PM_OFFSET__+0x7f8a02> + 1b2: 08 95 ret -000001a0 : +000001b4 : ); } void SleepDeep(void) { SLPCTRL_CTRLA = SLPCTRL_SMODE_PDOWN_gc | SLPCTRL_SEN_bm; - 1a0: 85 e0 ldi r24, 0x05 ; 5 - 1a2: 80 93 50 00 sts 0x0050, r24 ; 0x800050 <__RODATA_PM_OFFSET__+0x7f8050> + 1b4: 85 e0 ldi r24, 0x05 ; 5 + 1b6: 80 93 50 00 sts 0x0050, r24 ; 0x800050 <__RODATA_PM_OFFSET__+0x7f8050> asm volatile( - 1a6: 88 95 sleep - 1a8: 08 95 ret + 1ba: 88 95 sleep + 1bc: 08 95 ret -000001aa : +000001be : ); } void SleepIdle(void) { SLPCTRL_CTRLA = SLPCTRL_SMODE_IDLE_gc | SLPCTRL_SEN_bm; - 1aa: 81 e0 ldi r24, 0x01 ; 1 - 1ac: 80 93 50 00 sts 0x0050, r24 ; 0x800050 <__RODATA_PM_OFFSET__+0x7f8050> + 1be: 81 e0 ldi r24, 0x01 ; 1 + 1c0: 80 93 50 00 sts 0x0050, r24 ; 0x800050 <__RODATA_PM_OFFSET__+0x7f8050> asm volatile( - 1b0: 88 95 sleep - 1b2: 08 95 ret + 1c4: 88 95 sleep + 1c6: 08 95 ret -000001b4 : +000001c8 : void ConfigureFaultOutput(void) { //Check the reset source, if it was a WDT, configure the Fault pin as GPIO output, if it was a POR we don't want to do this. //This gives us 8 seconds after connecting power to the board to be able to reprogram the device. if (RSTCTRL_RSTFR & RSTCTRL_WDRF_bm) - 1b4: 80 91 40 00 lds r24, 0x0040 ; 0x800040 <__RODATA_PM_OFFSET__+0x7f8040> - 1b8: 83 ff sbrs r24, 3 - 1ba: 03 c0 rjmp .+6 ; 0x1c2 + 1c8: 80 91 40 00 lds r24, 0x0040 ; 0x800040 <__RODATA_PM_OFFSET__+0x7f8040> + 1cc: 83 ff sbrs r24, 3 + 1ce: 03 c0 rjmp .+6 ; 0x1d6 { PORTA_DIRSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; - 1bc: 84 e0 ldi r24, 0x04 ; 4 - 1be: 80 93 01 04 sts 0x0401, r24 ; 0x800401 <__RODATA_PM_OFFSET__+0x7f8401> - 1c2: 08 95 ret + 1d0: 84 e0 ldi r24, 0x04 ; 4 + 1d2: 80 93 01 04 sts 0x0401, r24 ; 0x800401 <__RODATA_PM_OFFSET__+0x7f8401> + 1d6: 08 95 ret -000001c4 : +000001d8 : } } void FlashLed(uint8_t numFlashes) { while (numFlashes--) - 1c4: 18 c0 rjmp .+48 ; 0x1f6 + 1d8: 18 c0 rjmp .+48 ; 0x20a PORTA_OUTSET = TX_LED_PIN_MASK; } inline void ResetWatchdog(void) { asm volatile( - 1c6: a8 95 wdr + 1da: a8 95 wdr PORTA_OUTCLR = REF2V5_ENABLE_REPURPOSED_AS_FAULT; } inline void LedOn(void) { PORTA_OUTCLR = TX_LED_PIN_MASK; - 1c8: 80 e4 ldi r24, 0x40 ; 64 - 1ca: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> + 1dc: 80 e4 ldi r24, 0x40 ; 64 + 1de: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> #else //round up by default __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); #endif __builtin_avr_delay_cycles(__ticks_dc); - 1ce: ef e1 ldi r30, 0x1F ; 31 - 1d0: f3 e0 ldi r31, 0x03 ; 3 - 1d2: 31 97 sbiw r30, 0x01 ; 1 - 1d4: f1 f7 brne .-4 ; 0x1d2 - 1d6: 00 c0 rjmp .+0 ; 0x1d8 - 1d8: 00 00 nop + 1e2: ef e1 ldi r30, 0x1F ; 31 + 1e4: f3 e0 ldi r31, 0x03 ; 3 + 1e6: 31 97 sbiw r30, 0x01 ; 1 + 1e8: f1 f7 brne .-4 ; 0x1e6 + 1ea: 00 c0 rjmp .+0 ; 0x1ec + 1ec: 00 00 nop } inline void LedOff(void) { PORTA_OUTSET = TX_LED_PIN_MASK; - 1da: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> + 1ee: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> { ResetWatchdog(); LedOn(); _delay_ms(1); LedOff(); if (numFlashes) - 1de: 99 23 and r25, r25 - 1e0: 49 f0 breq .+18 ; 0x1f4 - 1e2: ff ef ldi r31, 0xFF ; 255 - 1e4: 21 ee ldi r18, 0xE1 ; 225 - 1e6: 34 e0 ldi r19, 0x04 ; 4 - 1e8: f1 50 subi r31, 0x01 ; 1 - 1ea: 20 40 sbci r18, 0x00 ; 0 - 1ec: 30 40 sbci r19, 0x00 ; 0 - 1ee: e1 f7 brne .-8 ; 0x1e8 - 1f0: 00 c0 rjmp .+0 ; 0x1f2 - 1f2: 00 00 nop - 1f4: 89 2f mov r24, r25 + 1f2: 99 23 and r25, r25 + 1f4: 49 f0 breq .+18 ; 0x208 + 1f6: ff ef ldi r31, 0xFF ; 255 + 1f8: 21 ee ldi r18, 0xE1 ; 225 + 1fa: 34 e0 ldi r19, 0x04 ; 4 + 1fc: f1 50 subi r31, 0x01 ; 1 + 1fe: 20 40 sbci r18, 0x00 ; 0 + 200: 30 40 sbci r19, 0x00 ; 0 + 202: e1 f7 brne .-8 ; 0x1fc + 204: 00 c0 rjmp .+0 ; 0x206 + 206: 00 00 nop + 208: 89 2f mov r24, r25 } } void FlashLed(uint8_t numFlashes) { while (numFlashes--) - 1f6: 9f ef ldi r25, 0xFF ; 255 - 1f8: 98 0f add r25, r24 - 1fa: 81 11 cpse r24, r1 - 1fc: e4 cf rjmp .-56 ; 0x1c6 + 20a: 9f ef ldi r25, 0xFF ; 255 + 20c: 98 0f add r25, r24 + 20e: 81 11 cpse r24, r1 + 210: e4 cf rjmp .-56 ; 0x1da if (numFlashes) { _delay_ms(500); } } } - 1fe: 08 95 ret + 212: 08 95 ret -00000200
: +00000214
: //_delay_ms(2000); //FlashLed(remainder); //} int main(void) { - 200: cf 93 push r28 - 202: df 93 push r29 - 204: 00 d0 rcall .+0 ; 0x206 - 206: 00 d0 rcall .+0 ; 0x208 - 208: cd b7 in r28, 0x3d ; 61 - 20a: de b7 in r29, 0x3e ; 62 + 214: cf 93 push r28 + 216: df 93 push r29 + 218: 00 d0 rcall .+0 ; 0x21a + 21a: 00 d0 rcall .+0 ; 0x21c + 21c: cd b7 in r28, 0x3d ; 61 + 21e: de b7 in r29, 0x3e ; 62 PORTA_OUTSET = TX_LED_PIN_MASK; } inline void ResetWatchdog(void) { asm volatile( - 20c: a8 95 wdr + 220: a8 95 wdr //} int main(void) { ResetWatchdog(); InitializeIO(); - 20e: a9 df rcall .-174 ; 0x162 + 222: a9 df rcall .-174 ; 0x176 InitializeBalancePWM(); - 210: b2 df rcall .-156 ; 0x176 + 224: b2 df rcall .-156 ; 0x18a ConfigureFaultOutput(); - 212: d0 df rcall .-96 ; 0x1b4 + 226: d0 df rcall .-96 ; 0x1c8 uint32_t cellVoltage; cellStatus_t cellStatus = ManageCell(&cellVoltage); - 214: ce 01 movw r24, r28 - 216: 01 96 adiw r24, 0x01 ; 1 - 218: 67 df rcall .-306 ; 0xe8 + 228: ce 01 movw r24, r28 + 22a: 01 96 adiw r24, 0x01 ; 1 + 22c: 5d df rcall .-326 ; 0xe8 switch (cellStatus) - 21a: 82 30 cpi r24, 0x02 ; 2 - 21c: 69 f0 breq .+26 ; 0x238 - 21e: 83 30 cpi r24, 0x03 ; 3 - 220: 19 f0 breq .+6 ; 0x228 - 222: 81 30 cpi r24, 0x01 ; 1 - 224: a9 f4 brne .+42 ; 0x250 - 226: 0f c0 rjmp .+30 ; 0x246 + 22e: 81 30 cpi r24, 0x01 ; 1 + 230: a1 f0 breq .+40 ; 0x25a + 232: c8 f0 brcs .+50 ; 0x266 + 234: 82 30 cpi r24, 0x02 ; 2 + 236: 51 f0 breq .+20 ; 0x24c + 238: 83 30 cpi r24, 0x03 ; 3 + 23a: c1 f4 brne .+48 ; 0x26c TCA0_SINGLE_CTRLC = 0; } inline void IndicateFault(void) { PORTA_OUTSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; - 228: 84 e0 ldi r24, 0x04 ; 4 - 22a: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> + 23c: 84 e0 ldi r24, 0x04 ; 4 + 23e: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> PORTA_OUTCLR = REF2V5_ENABLE_REPURPOSED_AS_FAULT; } inline void LedOn(void) { PORTA_OUTCLR = TX_LED_PIN_MASK; - 22e: 80 e4 ldi r24, 0x40 ; 64 - 230: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> + 242: 80 e4 ldi r24, 0x40 ; 64 + 244: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> switch (cellStatus) { case CellStatusOverVoltage: IndicateFault(); LedOn(); SleepIdle(); - 234: ba df rcall .-140 ; 0x1aa + 248: ba df rcall .-140 ; 0x1be break; - 236: 0c c0 rjmp .+24 ; 0x250 - TCA0_SINGLE_CTRLC = 0; + 24a: 10 c0 rjmp .+32 ; 0x26c + PORTA_OUTSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; } -inline void IndicateFault(void) +inline void IndicateNoFault(void) { - PORTA_OUTSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; - 238: 84 e0 ldi r24, 0x04 ; 4 - 23a: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> + PORTA_OUTCLR = REF2V5_ENABLE_REPURPOSED_AS_FAULT; + 24c: 84 e0 ldi r24, 0x04 ; 4 + 24e: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> + LedOn(); SleepIdle(); break; case CellStatusBalancing: - //IndicateNoFault(); - IndicateFault(); //Fault output is going to be used to switch from CC to CV charge, so we want it high as soon as the first cell starts balancing + IndicateNoFault(); FlashLed(2); - 23e: 82 e0 ldi r24, 0x02 ; 2 - 240: c1 df rcall .-126 ; 0x1c4 + 252: 82 e0 ldi r24, 0x02 ; 2 + 254: c1 df rcall .-126 ; 0x1d8 SleepIdle(); - 242: b3 df rcall .-154 ; 0x1aa + 256: b3 df rcall .-154 ; 0x1be break; - 244: 05 c0 rjmp .+10 ; 0x250 + 258: 09 c0 rjmp .+18 ; 0x26c PORTA_OUTSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; } inline void IndicateNoFault(void) { PORTA_OUTCLR = REF2V5_ENABLE_REPURPOSED_AS_FAULT; - 246: 84 e0 ldi r24, 0x04 ; 4 - 248: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> + 25a: 84 e0 ldi r24, 0x04 ; 4 + 25c: 80 93 06 04 sts 0x0406, r24 ; 0x800406 <__RODATA_PM_OFFSET__+0x7f8406> FlashLed(2); SleepIdle(); break; case CellStatusNormal: IndicateNoFault(); FlashLed(1); - 24c: 81 e0 ldi r24, 0x01 ; 1 - 24e: ba df rcall .-140 ; 0x1c4 + 260: 81 e0 ldi r24, 0x01 ; 1 + 262: ba df rcall .-140 ; 0x1d8 + break; + 264: 03 c0 rjmp .+6 ; 0x26c + TCA0_SINGLE_CTRLC = 0; +} + +inline void IndicateFault(void) +{ + PORTA_OUTSET = REF2V5_ENABLE_REPURPOSED_AS_FAULT; + 266: 84 e0 ldi r24, 0x04 ; 4 + 268: 80 93 05 04 sts 0x0405, r24 ; 0x800405 <__RODATA_PM_OFFSET__+0x7f8405> case CellStatusUnderVoltage: - //IndicateFault(); //Fault output is going to be used as a "overcharge indicator", so don't output fault condition for lower limit + IndicateFault(); break; } SleepDeep(); - 250: a7 df rcall .-178 ; 0x1a0 + 26c: a3 df rcall .-186 ; 0x1b4 } - 252: 80 e0 ldi r24, 0x00 ; 0 - 254: 90 e0 ldi r25, 0x00 ; 0 - 256: 24 96 adiw r28, 0x04 ; 4 - 258: cd bf out 0x3d, r28 ; 61 - 25a: de bf out 0x3e, r29 ; 62 - 25c: df 91 pop r29 - 25e: cf 91 pop r28 - 260: 08 95 ret - -00000262 <__divmodsi4>: - 262: 05 2e mov r0, r21 - 264: 97 fb bst r25, 7 - 266: 16 f4 brtc .+4 ; 0x26c <__divmodsi4+0xa> - 268: 00 94 com r0 - 26a: 0f d0 rcall .+30 ; 0x28a <__negsi2> - 26c: 57 fd sbrc r21, 7 - 26e: 05 d0 rcall .+10 ; 0x27a <__divmodsi4_neg2> - 270: 14 d0 rcall .+40 ; 0x29a <__udivmodsi4> - 272: 07 fc sbrc r0, 7 - 274: 02 d0 rcall .+4 ; 0x27a <__divmodsi4_neg2> - 276: 46 f4 brtc .+16 ; 0x288 <__divmodsi4_exit> - 278: 08 c0 rjmp .+16 ; 0x28a <__negsi2> - -0000027a <__divmodsi4_neg2>: - 27a: 50 95 com r21 - 27c: 40 95 com r20 - 27e: 30 95 com r19 - 280: 21 95 neg r18 - 282: 3f 4f sbci r19, 0xFF ; 255 - 284: 4f 4f sbci r20, 0xFF ; 255 - 286: 5f 4f sbci r21, 0xFF ; 255 - -00000288 <__divmodsi4_exit>: - 288: 08 95 ret - -0000028a <__negsi2>: - 28a: 90 95 com r25 - 28c: 80 95 com r24 - 28e: 70 95 com r23 - 290: 61 95 neg r22 - 292: 7f 4f sbci r23, 0xFF ; 255 - 294: 8f 4f sbci r24, 0xFF ; 255 - 296: 9f 4f sbci r25, 0xFF ; 255 - 298: 08 95 ret - -0000029a <__udivmodsi4>: - 29a: a1 e2 ldi r26, 0x21 ; 33 - 29c: 1a 2e mov r1, r26 - 29e: aa 1b sub r26, r26 - 2a0: bb 1b sub r27, r27 - 2a2: fd 01 movw r30, r26 - 2a4: 0d c0 rjmp .+26 ; 0x2c0 <__udivmodsi4_ep> - -000002a6 <__udivmodsi4_loop>: - 2a6: aa 1f adc r26, r26 - 2a8: bb 1f adc r27, r27 - 2aa: ee 1f adc r30, r30 - 2ac: ff 1f adc r31, r31 - 2ae: a2 17 cp r26, r18 - 2b0: b3 07 cpc r27, r19 - 2b2: e4 07 cpc r30, r20 - 2b4: f5 07 cpc r31, r21 - 2b6: 20 f0 brcs .+8 ; 0x2c0 <__udivmodsi4_ep> - 2b8: a2 1b sub r26, r18 - 2ba: b3 0b sbc r27, r19 - 2bc: e4 0b sbc r30, r20 - 2be: f5 0b sbc r31, r21 - -000002c0 <__udivmodsi4_ep>: - 2c0: 66 1f adc r22, r22 - 2c2: 77 1f adc r23, r23 - 2c4: 88 1f adc r24, r24 - 2c6: 99 1f adc r25, r25 - 2c8: 1a 94 dec r1 - 2ca: 69 f7 brne .-38 ; 0x2a6 <__udivmodsi4_loop> - 2cc: 60 95 com r22 - 2ce: 70 95 com r23 - 2d0: 80 95 com r24 - 2d2: 90 95 com r25 - 2d4: 9b 01 movw r18, r22 - 2d6: ac 01 movw r20, r24 - 2d8: bd 01 movw r22, r26 - 2da: cf 01 movw r24, r30 - 2dc: 08 95 ret - -000002de <_exit>: - 2de: f8 94 cli - -000002e0 <__stop_program>: - 2e0: ff cf rjmp .-2 ; 0x2e0 <__stop_program> + 26e: 80 e0 ldi r24, 0x00 ; 0 + 270: 90 e0 ldi r25, 0x00 ; 0 + 272: 24 96 adiw r28, 0x04 ; 4 + 274: cd bf out 0x3d, r28 ; 61 + 276: de bf out 0x3e, r29 ; 62 + 278: df 91 pop r29 + 27a: cf 91 pop r28 + 27c: 08 95 ret + +0000027e <__divmodsi4>: + 27e: 05 2e mov r0, r21 + 280: 97 fb bst r25, 7 + 282: 16 f4 brtc .+4 ; 0x288 <__divmodsi4+0xa> + 284: 00 94 com r0 + 286: 0f d0 rcall .+30 ; 0x2a6 <__negsi2> + 288: 57 fd sbrc r21, 7 + 28a: 05 d0 rcall .+10 ; 0x296 <__divmodsi4_neg2> + 28c: 14 d0 rcall .+40 ; 0x2b6 <__udivmodsi4> + 28e: 07 fc sbrc r0, 7 + 290: 02 d0 rcall .+4 ; 0x296 <__divmodsi4_neg2> + 292: 46 f4 brtc .+16 ; 0x2a4 <__divmodsi4_exit> + 294: 08 c0 rjmp .+16 ; 0x2a6 <__negsi2> + +00000296 <__divmodsi4_neg2>: + 296: 50 95 com r21 + 298: 40 95 com r20 + 29a: 30 95 com r19 + 29c: 21 95 neg r18 + 29e: 3f 4f sbci r19, 0xFF ; 255 + 2a0: 4f 4f sbci r20, 0xFF ; 255 + 2a2: 5f 4f sbci r21, 0xFF ; 255 + +000002a4 <__divmodsi4_exit>: + 2a4: 08 95 ret + +000002a6 <__negsi2>: + 2a6: 90 95 com r25 + 2a8: 80 95 com r24 + 2aa: 70 95 com r23 + 2ac: 61 95 neg r22 + 2ae: 7f 4f sbci r23, 0xFF ; 255 + 2b0: 8f 4f sbci r24, 0xFF ; 255 + 2b2: 9f 4f sbci r25, 0xFF ; 255 + 2b4: 08 95 ret + +000002b6 <__udivmodsi4>: + 2b6: a1 e2 ldi r26, 0x21 ; 33 + 2b8: 1a 2e mov r1, r26 + 2ba: aa 1b sub r26, r26 + 2bc: bb 1b sub r27, r27 + 2be: fd 01 movw r30, r26 + 2c0: 0d c0 rjmp .+26 ; 0x2dc <__udivmodsi4_ep> + +000002c2 <__udivmodsi4_loop>: + 2c2: aa 1f adc r26, r26 + 2c4: bb 1f adc r27, r27 + 2c6: ee 1f adc r30, r30 + 2c8: ff 1f adc r31, r31 + 2ca: a2 17 cp r26, r18 + 2cc: b3 07 cpc r27, r19 + 2ce: e4 07 cpc r30, r20 + 2d0: f5 07 cpc r31, r21 + 2d2: 20 f0 brcs .+8 ; 0x2dc <__udivmodsi4_ep> + 2d4: a2 1b sub r26, r18 + 2d6: b3 0b sbc r27, r19 + 2d8: e4 0b sbc r30, r20 + 2da: f5 0b sbc r31, r21 + +000002dc <__udivmodsi4_ep>: + 2dc: 66 1f adc r22, r22 + 2de: 77 1f adc r23, r23 + 2e0: 88 1f adc r24, r24 + 2e2: 99 1f adc r25, r25 + 2e4: 1a 94 dec r1 + 2e6: 69 f7 brne .-38 ; 0x2c2 <__udivmodsi4_loop> + 2e8: 60 95 com r22 + 2ea: 70 95 com r23 + 2ec: 80 95 com r24 + 2ee: 90 95 com r25 + 2f0: 9b 01 movw r18, r22 + 2f2: ac 01 movw r20, r24 + 2f4: bd 01 movw r22, r26 + 2f6: cf 01 movw r24, r30 + 2f8: 08 95 ret + +000002fa <_exit>: + 2fa: f8 94 cli + +000002fc <__stop_program>: + 2fc: ff cf rjmp .-2 ; 0x2fc <__stop_program> diff --git a/Firmware/Debug/BMSLadder.map b/Firmware/Debug/BMSLadder.map index 7ae6e35..6d0785b 100644 --- a/Firmware/Debug/BMSLadder.map +++ b/Firmware/Debug/BMSLadder.map @@ -211,7 +211,7 @@ END GROUP .rela.plt *(.rela.plt) -.text 0x00000000 0x2e2 +.text 0x00000000 0x2fe *(.vectors) .vectors 0x00000000 0x34 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.8.332/gcc/dev/attiny202/avrxmega3/short-calls/crtattiny202.o 0x00000000 __vector_default @@ -322,42 +322,42 @@ END GROUP 0x000000ae 0x3a CellManagement.o 0x000000ae CellVoltage .text.ManageCell - 0x000000e8 0x7a CellManagement.o + 0x000000e8 0x8e CellManagement.o 0x000000e8 ManageCell .text.InitializeIO - 0x00000162 0x14 main.o - 0x00000162 InitializeIO + 0x00000176 0x14 main.o + 0x00000176 InitializeIO .text.InitializeBalancePWM - 0x00000176 0x2a main.o - 0x00000176 InitializeBalancePWM + 0x0000018a 0x2a main.o + 0x0000018a InitializeBalancePWM .text.SleepDeep - 0x000001a0 0xa main.o - 0x000001a0 SleepDeep + 0x000001b4 0xa main.o + 0x000001b4 SleepDeep .text.SleepIdle - 0x000001aa 0xa main.o - 0x000001aa SleepIdle + 0x000001be 0xa main.o + 0x000001be SleepIdle .text.ConfigureFaultOutput - 0x000001b4 0x10 main.o - 0x000001b4 ConfigureFaultOutput + 0x000001c8 0x10 main.o + 0x000001c8 ConfigureFaultOutput .text.FlashLed - 0x000001c4 0x3c main.o - 0x000001c4 FlashLed - .text.main 0x00000200 0x62 main.o - 0x00000200 main + 0x000001d8 0x3c main.o + 0x000001d8 FlashLed + .text.main 0x00000214 0x6a main.o + 0x00000214 main .text.libgcc.div - 0x00000262 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_divmodsi4.o) - 0x00000262 __divmodsi4 + 0x0000027e 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_divmodsi4.o) + 0x0000027e __divmodsi4 .text.libgcc.div - 0x0000028a 0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_negsi2.o) - 0x0000028a __negsi2 + 0x000002a6 0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_negsi2.o) + 0x000002a6 __negsi2 .text.libgcc.div - 0x0000029a 0x44 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_udivmodsi4.o) - 0x0000029a __udivmodsi4 - 0x000002de . = ALIGN (0x2) + 0x000002b6 0x44 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_udivmodsi4.o) + 0x000002b6 __udivmodsi4 + 0x000002fa . = ALIGN (0x2) *(.fini9) - .fini9 0x000002de 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o) - 0x000002de _exit - 0x000002de exit + .fini9 0x000002fa 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o) + 0x000002fa _exit + 0x000002fa exit *(.fini9) *(.fini8) *(.fini8) @@ -376,16 +376,16 @@ END GROUP *(.fini1) *(.fini1) *(.fini0) - .fini0 0x000002de 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o) + .fini0 0x000002fa 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/5.4.0/avrxmega3/short-calls\libgcc.a(_exit.o) *(.fini0) - 0x000002e2 _etext = . + 0x000002fe _etext = . .rodata *(.rodata) *(.rodata*) *(.gnu.linkonce.r*) -.data 0x00803f80 0x0 load address 0x000002e2 +.data 0x00803f80 0x0 load address 0x000002fe [!provide] PROVIDE (__data_start, .) *(.data) *(.data*) @@ -400,8 +400,8 @@ END GROUP *(.bss*) *(COMMON) [!provide] PROVIDE (__bss_end, .) - 0x000002e2 __data_load_start = LOADADDR (.data) - 0x000002e2 __data_load_end = (__data_load_start + SIZEOF (.data)) + 0x000002fe __data_load_start = LOADADDR (.data) + 0x000002fe __data_load_end = (__data_load_start + SIZEOF (.data)) .noinit 0x00803f80 0x0 [!provide] PROVIDE (__noinit_start, .) @@ -486,12 +486,12 @@ END GROUP .debug_pubnames *(.debug_pubnames) -.debug_info 0x00000000 0x1e0c +.debug_info 0x00000000 0x1e1b *(.debug_info .gnu.linkonce.wi.*) .debug_info 0x00000000 0x11d6 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.8.332/gcc/dev/attiny202/avrxmega3/short-calls/crtattiny202.o .debug_info 0x000011d6 0x536 adc.o .debug_info 0x0000170c 0x2c7 CellManagement.o - .debug_info 0x000019d3 0x439 main.o + .debug_info 0x000019d3 0x448 main.o .debug_abbrev 0x00000000 0x1593 *(.debug_abbrev) @@ -500,12 +500,12 @@ END GROUP .debug_abbrev 0x000012a6 0x13e CellManagement.o .debug_abbrev 0x000013e4 0x1af main.o -.debug_line 0x00000000 0x7a3 +.debug_line 0x00000000 0x7bc *(.debug_line .debug_line.* .debug_line_end) .debug_line 0x00000000 0x136 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.8.332/gcc/dev/attiny202/avrxmega3/short-calls/crtattiny202.o .debug_line 0x00000136 0x1db adc.o - .debug_line 0x00000311 0x1b0 CellManagement.o - .debug_line 0x000004c1 0x2e2 main.o + .debug_line 0x00000311 0x1bc CellManagement.o + .debug_line 0x000004cd 0x2ef main.o .debug_frame 0x00000000 0x17c *(.debug_frame) @@ -513,21 +513,21 @@ END GROUP .debug_frame 0x00000094 0x54 CellManagement.o .debug_frame 0x000000e8 0x94 main.o -.debug_str 0x00000000 0x11ec +.debug_str 0x00000000 0x1211 *(.debug_str) .debug_str 0x00000000 0x7a9 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/ATtiny_DFP/1.8.332/gcc/dev/attiny202/avrxmega3/short-calls/crtattiny202.o .debug_str 0x000007a9 0x5d5 adc.o 0x609 (size before relaxing) - .debug_str 0x00000d7e 0xe3 CellManagement.o - 0x3de (size before relaxing) - .debug_str 0x00000e61 0x38b main.o - 0x56f (size before relaxing) + .debug_str 0x00000d7e 0x108 CellManagement.o + 0x3dd (size before relaxing) + .debug_str 0x00000e86 0x38b main.o + 0x56e (size before relaxing) -.debug_loc 0x00000000 0x2b3 +.debug_loc 0x00000000 0x2be *(.debug_loc) .debug_loc 0x00000000 0x4e adc.o .debug_loc 0x0000004e 0x132 CellManagement.o - .debug_loc 0x00000180 0x133 main.o + .debug_loc 0x00000180 0x13e main.o .debug_macinfo *(.debug_macinfo) diff --git a/Firmware/Debug/BMSLadder.srec b/Firmware/Debug/BMSLadder.srec index cbe649a..8467290 100644 --- a/Firmware/Debug/BMSLadder.srec +++ b/Firmware/Debug/BMSLadder.srec @@ -3,7 +3,7 @@ S113000019C020C01FC01EC01DC01CC01BC01AC008 S113001019C018C017C016C015C014C013C012C030 S113002011C010C00FC00EC00DC00CC00BC00AC060 S113003009C008C011241FBECFEFCDBFDFE3DEBF70 -S1130040DFD04DC1DDCFE0E0F6E081E5828381E0E1 +S1130040E9D05BC1DDCFE0E0F6E081E5828381E0C9 S113005080830895E0EAF0E080E1808382E0818398 S11300600895E0E0F6E08081816080830895E0E017 S1130070F6E080818E7F80830895E0E0F6E0868359 @@ -12,38 +12,39 @@ S11300901006909111060895F0DFF5DF8823E9F347 S11300A0F6DFE0E0F6E02385216023870895CF9210 S11300B0DF92EF92FF92CEDFC6DFD3DF8DE1ECDF7C S11300C08DE1EADF9C0140E050E060E070E381E113 -S11300D090E0C7D069017A01CADFC701B601FF9079 +S11300D090E0D5D069017A01CADFC701B601FF906B S11300E0EF90DF90CF900895CF93DF93EC01DFDFA3 S11300F0688379838A839B83663320E17207810551 -S1130100910568F080E093E08093280A9093290A8F -S1130110E0E0FAE080818160808383E01FC0623D7B -S11301207F408105910538F0E0E0FAE0808181604C -S1130130808382E013C0E0E0FAE080818E7F8083D8 -S11301401092020A88819981AA81BB81803F9A40DA -S1130150A105B10510F081E001C080E0DF91CF91ED -S1130160089584E08093100488E48093000480E47C -S113017080930504089580E094E08093260A909388 -S1130180270A80E890E08093280A9093290A83E163 -S11301908093010A8CE08093000A1092020A089569 -S11301A085E0809350008895089581E08093500005 -S11301B0889508958091400083FF03C084E0809374 -S11301C00104089518C0A89580E480930604EFE123 -S11301D0F3E03197F1F700C0000080930504992300 -S11301E049F0FFEF21EE34E0F15020403040E1F7D8 -S11301F000C00000892F9FEF980F8111E4CF08956C -S1130200CF93DF9300D000D0CDB7DEB7A895A9DF98 -S1130210B2DFD0DFCE01019667DF823069F0833030 -S113022019F08130A9F40FC084E08093050480E4C0 -S113023080930604BADF0CC084E08093050482E056 -S1130240C1DFB3DF05C084E08093060481E0BADF38 -S1130250A7DF80E090E02496CDBFDEBFDF91CF9191 -S11302600895052E97FB16F400940FD057FD05D082 -S113027014D007FC02D046F408C050954095309540 -S113028021953F4F4F4F5F4F0895909580957095FE -S113029061957F4F8F4F9F4F0895A1E21A2EAA1B9D -S11302A0BB1BFD010DC0AA1FBB1FEE1FFF1FA21722 -S11302B0B307E407F50720F0A21BB30BE40BF50B1F -S11302C0661F771F881F991F1A9469F760957095A8 -S11302D0809590959B01AC01BD01CF010895F894E0 -S10502E0FFCF4A +S1130100910588F0E8E2FAE080E890E0808391834A +S113011080E093E080839183E0E0FAE08081816075 +S1130120808383E025C0643070418105910568F0C7 +S113013080E890E08093280A9093290AE0E0FAE0AE +S113014080818160808382E013C0E0E0FAE08081F6 +S11301508E7F80831092020A88819981AA81BB8153 +S1130160803F9A40A105B10510F081E001C080E014 +S1130170DF91CF91089584E08093100488E4809304 +S1130180000480E480930504089580E094E0809363 +S1130190260A9093270A80E890E08093280A909397 +S11301A0290A83E18093010A8CE08093000A10926B +S11301B0020A089585E0809350008895089581E0AF +S11301C080935000889508958091400083FF03C078 +S11301D084E080930104089518C0A89580E4809376 +S11301E00604EFE1F3E03197F1F700C000008093DB +S11301F00504992349F0FFEF21EE34E0F15020404B +S11302003040E1F700C00000892F9FEF980F811163 +S1130210E4CF0895CF93DF9300D000D0CDB7DEB7FD +S1130220A895A9DFB2DFD0DFCE0101965DDF813072 +S1130230A1F0C8F0823051F08330C1F484E080939F +S1130240050480E480930604BADF10C084E0809340 +S1130250060482E0C1DFB3DF09C084E080930604B2 +S113026081E0BADF03C084E080930504A3DF80E06B +S113027090E02496CDBFDEBFDF91CF910895052E87 +S113028097FB16F400940FD057FD05D014D007FC4B +S113029002D046F408C050954095309521953F4FC3 +S11302A04F4F5F4F089590958095709561957F4F5E +S11302B08F4F9F4F0895A1E21A2EAA1BBB1BFD016D +S11302C00DC0AA1FBB1FEE1FFF1FA217B307E40731 +S11302D0F50720F0A21BB30BE40BF50B661F771F89 +S11302E0881F991F1A9469F7609570958095909569 +S11102F09B01AC01BD01CF010895F894FFCF2E S9030000FC diff --git a/Firmware/Debug/CellManagement.o b/Firmware/Debug/CellManagement.o index 490994c..3edfba6 100644 Binary files a/Firmware/Debug/CellManagement.o and b/Firmware/Debug/CellManagement.o differ diff --git a/Firmware/Debug/main.o b/Firmware/Debug/main.o index d95a188..7ba03f2 100644 Binary files a/Firmware/Debug/main.o and b/Firmware/Debug/main.o differ diff --git a/Firmware/main.c b/Firmware/main.c index 4208fb7..02f7ab1 100644 --- a/Firmware/main.c +++ b/Firmware/main.c @@ -5,7 +5,6 @@ Fuse Configuration: BOD - Disabled, when in brown out, the power consumption goes to 100uA vs < 1uA in shutdown sleep mode. - Reset Pin - Configured for GPIO mode (Note, this makes the chip no longer reprogrammable without getting hold of a 12V pulse programmer Watchdog - 8k cycles, 8.2 seconds, this code always runs, then sleeps and waits for the watchdog to trigger a reset, there is no "main loop" for power consumption optimization. Startup Time - 16ms */ @@ -130,8 +129,7 @@ int main(void) SleepIdle(); break; case CellStatusBalancing: - //IndicateNoFault(); - IndicateFault(); //Fault output is going to be used to switch from CC to CV charge, so we want it high as soon as the first cell starts balancing + IndicateNoFault(); FlashLed(2); SleepIdle(); break; @@ -140,7 +138,7 @@ int main(void) FlashLed(1); break; case CellStatusUnderVoltage: - //IndicateFault(); //Fault output is going to be used as a "overcharge indicator", so don't output fault condition for lower limit + IndicateFault(); break; }