From 836ca4a86c05aec73ed413c8bf2f0da091e2fe80 Mon Sep 17 00:00:00 2001
From: tejaspadole1-max <tejaspadole1@gmail.com>
Date: Sat, 24 Jan 2026 17:36:34 +0530
Subject: [PATCH] Fix typo FERQUENCY -> FREQUENCY and resolve TypeError in
 tests

---
 tests/test_spi.py  | 6 +++---
 tests/test_uart.py | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/test_spi.py b/tests/test_spi.py
index ecd73d9..903c766 100644
--- a/tests/test_spi.py
+++ b/tests/test_spi.py
@@ -30,7 +30,7 @@
 CS = "LA3"
 SPIMaster._primary_prescaler = PPRE = 0
 SPIMaster._secondary_prescaler = SPRE = 0
-PWM_FERQUENCY = SPIMaster._frequency * 2 / 3
+PWM_FREQUENCY = 1000
 MICROSECONDS = 1e-6
 RELTOL = 0.05
 # Number of expected logic level changes.
@@ -61,7 +61,7 @@ def slave(handler: SerialHandler) -> SPISlave:
 @pytest.fixture
 def la(handler: SerialHandler) -> LogicAnalyzer:
     pwm = PWMGenerator(handler)
-    pwm.generate(SDI[1], PWM_FERQUENCY, 0.5)
+    pwm.generate(SDI[1], PWM_FREQUENCY, 0.5)
     return LogicAnalyzer(handler)
 
 
@@ -73,7 +73,7 @@ def verify_value(
     smp: int = 0,
 ):
     sck_ts = sck_timestamps[smp::2]
-    pwm_half_period = ((1 / PWM_FERQUENCY) * 1e6) / 2  # microsecond
+    pwm_half_period = ((1 / PWM_FREQUENCY) * 1e6) / 2  # microsecond
 
     pattern = ""
     for t in sck_ts:
diff --git a/tests/test_uart.py b/tests/test_uart.py
index fd861e5..560ffb8 100644
--- a/tests/test_uart.py
+++ b/tests/test_uart.py
@@ -16,7 +16,7 @@
 WRITE_DATA = 0x55
 TXD2 = "LA1"
 RXD2 = "SQ1"
-PWM_FERQUENCY = UART._baudrate // 2
+PWM_FREQUENCY = 1000
 MICROSECONDS = 1e-6
 RELTOL = 0.05
 # Number of expected logic level changes.
@@ -38,7 +38,7 @@ def la(handler: SerialHandler) -> LogicAnalyzer:
 @pytest.fixture
 def pwm(handler: SerialHandler) -> None:
     pwm = PWMGenerator(handler)
-    pwm.generate(RXD2, PWM_FERQUENCY, 0.5)
+    pwm.generate(RXD2, PWM_FREQUENCY, 0.5)
 
 
 def test_configure(la: LogicAnalyzer, uart: UART):