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clk_ mt7988-infra: convert invalid GATE to MUX
1 parent aad2a0b commit 1900cb6

1 file changed

Lines changed: 38 additions & 38 deletions

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‎drivers/clk/mediatek/clk-mt7988-infracfg.c‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -56,49 +56,49 @@ static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
5656

5757
static const struct mtk_mux infra_muxes[] = {
5858
/* MODULE_CLK_SEL_0 */
59-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
60-
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
61-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
62-
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
63-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
64-
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
65-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
66-
0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
67-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
68-
0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
69-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
70-
0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
71-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72-
0x0010, 0x0014, 14, 2, -1, -1, -1),
73-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
74-
0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
75-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
76-
0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
77-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
78-
0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
79-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
80-
0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
81-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
82-
0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
83-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
84-
0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
85-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
86-
0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
87-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
88-
0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
59+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
60+
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1),
61+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
62+
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1),
63+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
64+
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1),
65+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
66+
0x0018, 0x0010, 0x0014, 4, 1, -1, -1),
67+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
68+
0x0018, 0x0010, 0x0014, 5, 1, -1, -1),
69+
MUX_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
70+
0x0018, 0x0010, 0x0014, 6, 1, -1, -1),
71+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
72+
0x0010, 0x0014, 14, 2, -1, -1),
73+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
74+
0x0018, 0x0010, 0x0014, 16, 2, -1, -1),
75+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
76+
0x0018, 0x0010, 0x0014, 18, 2, -1, -1),
77+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
78+
0x0018, 0x0010, 0x0014, 20, 2, -1, -1),
79+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
80+
0x0018, 0x0010, 0x0014, 22, 2, -1, -1),
81+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
82+
0x0018, 0x0010, 0x0014, 24, 2, -1, -1),
83+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
84+
0x0018, 0x0010, 0x0014, 26, 2, -1, -1),
85+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
86+
0x0018, 0x0010, 0x0014, 28, 2, -1, -1),
87+
MUX_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
88+
0x0018, 0x0010, 0x0014, 30, 2, -1, -1),
8989
/* MODULE_CLK_SEL_1 */
90-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
90+
MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
9191
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
92-
-1, -1),
93-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
92+
-1),
93+
MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
9494
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
95-
-1, -1),
96-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
95+
-1),
96+
MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
9797
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
98-
-1, -1),
99-
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
98+
-1),
99+
MUX_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
100100
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
101-
-1, -1),
101+
-1),
102102
};
103103

104104
static const struct mtk_gate_regs infra0_cg_regs = {

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