P5 INTERCONNECT + JTAG · L4 IO+ECDSA+DSLogic · pre: P4

[gHashTag]

P5 — INTERCONNECT + JTAG (TRI NET integration phase 5/6)

Parent EPIC: #61 · ONE SHOT: #79 · Predecessor: P4

Layer: L4 Interconnect (TRI NET physical)
Window: Days 14-15
Pre-condition: P4 ✅ green.

Goal

Chip responds to external world: 24-pin TT IO operational at ≤66 MHz ext clk, JTAG self-test passes via DSLogic, on-die ECDSA signs 8-die super-root, host verifies signature.

Includes

• G-135 — BitNet ↔ GF16 software-side adapter
• G-139 — JTAG self-test (resolves DSLogic blocker t27#590)
• ECDSA-on-die gates ×5 (carry v15) — sign super-root with on-die private key

CI workflow

interconnect-jtag.yml — runs JTAG session against DSLogic emulator + ECDSA signature roundtrip.

Acceptance

• JTAG IDCODE responds correctly via DSLogic
• ECDSA signature on Merkle super-root verifies on host
• BitNet↔GF16 adapter passes round-trip test
• 24-pin IO meets TT timing constraints

Risk

Low — well-understood IP.

Linked upstream

• t27#590 (DSLogic JTAG blocker)
• trios#807 (JEPA-T ingest)

Anchor

TRI NET physical · TRINITY · NEVER STOP