[Meta] CROWN-ASIC architecture roadmap (P0 / P1 / P2)

[gHashTag]

Meta: CROWN-ASIC architecture roadmap (P0 / P1 / P2)

Anchor: φ²+φ⁻²=3 · Defense 2026-06-15 · Throne: gHashTag/trios#264
Target submission stack: TTSKY26c → TTIHP27a → TSMC 28 / GF 22FDX
Skill: trinity-silicon-tapeout (AGI Driver, L-DPC3 → silicon → AGI)

This is the dispatch hub for upgrading CROWN-ASIC architecture without violating any of R-SI-1..R-SI-10.

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P0 — first PR (separate issue)

ID	Change	Effect	Tracking
A	LUT instead of * in gf16_mul.v:30	R-SI-1 absolute	P0 issue
C	Wallace-tree popcount in gf16_dot4.v	+60 % f_max	P0 issue
N	Yosys EQY: t27c-RTL ↔ hand-written src/*.v	closes Coq→silicon gap	P0 issue

P1 — second wave (one issue each)

ID	Change	Effect	Cost
D	Torus 4×4 router with XY-routing (replaces single-hop 2×2 crossbar)	4× tile count on same die	+1 hop latency, +~200 cells/router
E	2 virtual channels (receipt vs payload)	guaranteed receipt forward-progress	~100 cells/router
F	Credit-based flow control	~1 pkt/cycle/link throughput	counters per port
G	On-die Poseidon hash for TRN_RCPT_*	real DePIN proof-of-compute	~500 cells
H	Merkle accumulator for batched receipts	O(log N) host verification	small
I	Per-tile monotonic counter (replay protection)	DePIN replay defense	~50 cells
K	eFPGA patch tile (1 of 16)	post-silicon FSM patching	~3000 cells
L	Finalize trinity_mesh_adapter_stub.v as UART/serial; radio offloaded to ESP32-S3	unblocks G3	spec-only
M	SVA-assertions in each module	runtime invariant proof	$0 area
O	UVM/cocotb testbench (replace hand-rolled tb.v)	coverage-driven verification	tool-only

P2 — strategic (PhD Glava 35)

ID	Change	Effect	Cost
J	USB-3 → PCIe Gen2 ×1 on TTIHP27a	~500 MB/s vs ~80 MB/s	IHP node only
P	Hardware zero-skip for sparse GF16 activations	5–10× LLM throughput	medium
Q	In-memory compute via OpenRAM SRAM macro for LUTs	frees logic cells for more tiles	layout work
R	Coq-extracted scheduler in trinity_master_fsm.v	fairness/liveness/deadlock-freedom proved	XL, hero claim

Hard "do not" list

• ❌ RISC-V/ARM soft-core (violates R-SI-7 CPU-less FSM)
• ❌ Proprietary IP (AMBA, DesignWare) — violates R-SI-5 Apache-2.0
• ❌ Float/fixed-point ALU — violates R-SI-2 ternary only
• ❌ > 950 cells/tile — violates R-SI-3 TT DPL-0036 budget
• ❌ New * operators in src/ (R-SI-1)

Gate status (2026-05-13)

Gate	Status	Notes
G0	✅ done	PR #2, commit cfc234e
G1	✅ GREEN sim	100/100 0x47C0
G2	✅ GREEN sim	100/100 in host/g2_receipts.jsonl
G3	🟡 spec frozen, HW HOLD	unblocked by P1-L
G4	✅ GREEN	7/7 unit + 100/100
G5	🟡 schematic frozen	needs PCB layout

Operator next moves

1. Re-target L-DPC3 to TTSKY26c (TTSKY26a deadline missed 2026-05-11)
2. Land P0 PR (A+C+N) — see linked issue
3. Run OpenLane2 on current 2x2 to baseline DRC/LVS
4. Open one issue per P1 ID (D..O) as work begins
5. Slot P2-R (Coq-extracted scheduler) as the PhD Glava 35 hero claim

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φ²+φ⁻²=3 · CROWN-ASIC · TRINITY · R5-HONEST · Defense 2026-06-15

[gHashTag]

P0 tracking: #4 (A+C+N first PR plan)

[gHashTag]

🔗 Linked to MASTER-EPIC trinity-fpga#61 — TRI-1 Max Squeeze v3 Unified Hub (S-1..S-20, 13 falsification gates, TTSKY26b deadline 2026-05-18). RTL work in this repo (tt-trinity-gf16) tracks back to the unified hub there.