From 4a022dbd49c7f9e189dc5ed86135754d011a56a6 Mon Sep 17 00:00:00 2001
From: Vasilev Dmitrii <admin@t27.ai>
Date: Fri, 15 May 2026 16:39:33 +0700
Subject: [PATCH] fix(info.yaml): wire MAX top_module + 4x4 tile size (W15-TT-E
 enablement)
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PR #39 added MAX RTL but info.yaml still pointed at Mid top — GDS was
building Mid, not MAX. This flips the YAML to submit MAX 4×4 mesh.

R-SI-1 status: legacy gf16_mul.v `*` is grandfathered (TRI_NET_SHUTTLE_TRIAD
Rule 2, Issue #4 deferred-ttsky26c label). No RTL changes needed for W15-TT-E.

EPIC: gHashTag/trinity-fpga#61 · phi^2+phi^-2=3
---
 info.yaml | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/info.yaml b/info.yaml
index a38009d..685b3ba 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,6 +1,6 @@
 # Tiny Tapeout project information
 project:
-  title:        "TRI-1 Mid — Trinity GF16 16-cell SUPER-CROWN SoC"
+  title:        "TRI-1 MAX — Trinity GF16 16-tile 4×4 mesh SoC"
   author:       "Dmitrii Vasilev · Trinity Stack"
   discord:      "t27_dev"
   description:  |
@@ -46,11 +46,14 @@ project:
   language:     "Verilog"
   clock_hz:     50000000
 
-  tiles: "8x2"  # bumped 2x2 -> 8x2 in PR #8 (Wave-26b SUPER-CROWN) to accommodate full Trinity SoC mini: 4 GF16 tiles + mesh + master FSM + 6 CROWN POST modules + 16x16 ternary matmul + BitNet encoder + BPB counter + BLAKE3 anchor + multi-tile RECEIPT + ALU-9 decoder + RING27 memory + phi-PLL + Wishbone-lite full. Target ~16000 gates @ 60% density on SKY130.
+  tiles: "4x4"  # bumped 8x2 -> 4x4 in fix/max-info-yaml-wireup (RVR-022-D W15-TT-E) to match MAX 16-tile 4x4 mesh footprint.
 
-  top_module:  "tt_um_ghtag_trinity_gf16"
+  top_module:  "tt_um_trinity_max"
 
   source_files:
+    - "tt_um_trinity_max.v"
+    - "trinity_mesh_4x4.v"
+    - "trinity_router_4x4.v"
     - "tt_um_ghtag_trinity_gf16.v"
     - "gf16_mul.v"
     - "gf16_add.v"