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display.qsf
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101 lines (98 loc) · 5.03 KB
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2023 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
# Date created = 17:23:18 February 20, 2025
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# display_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY display
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:23:18 FEBRUARY 20, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_location_assignment PIN_12 -to clk_50mhz
set_location_assignment PIN_50 -to reset_button
set_location_assignment PIN_75 -to disp_u[6]
set_location_assignment PIN_76 -to disp_u[5]
set_location_assignment PIN_73 -to disp_u[4]
set_location_assignment PIN_74 -to disp_u[3]
set_location_assignment PIN_71 -to disp_u[2]
set_location_assignment PIN_72 -to disp_u[1]
set_location_assignment PIN_69 -to disp_u[0]
set_location_assignment PIN_70 -to DP2
set_location_assignment PIN_33 -to disp_d[6]
set_location_assignment PIN_30 -to disp_d[5]
set_location_assignment PIN_35 -to disp_d[4]
set_location_assignment PIN_34 -to disp_d[3]
set_location_assignment PIN_37 -to disp_d[2]
set_location_assignment PIN_36 -to disp_d[1]
set_location_assignment PIN_39 -to disp_d[0]
set_location_assignment PIN_38 -to DP1
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_instance_assignment -name RESERVE_PIN AS_OUTPUT_DRIVING_GROUND -to DP1
set_instance_assignment -name RESERVE_PIN AS_OUTPUT_DRIVING_GROUND -to DP2
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to reset_button
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to reset_button
set_global_assignment -name VHDL_FILE display.vhd
set_global_assignment -name VHDL_FILE chain_clk_div.vhd
set_global_assignment -name VHDL_FILE debounce.vhd
set_global_assignment -name VHDL_FILE ula.vhd
set_global_assignment -name VHDL_FILE state_machine.vhd
set_global_assignment -name VHDL_FILE rom_tb.vhd
set_global_assignment -name VHDL_FILE rom.vhd
set_global_assignment -name VHDL_FILE reg_instr.vhd
set_global_assignment -name VHDL_FILE reg_flags.vhd
set_global_assignment -name VHDL_FILE reg_bank.vhd
set_global_assignment -name VHDL_FILE reg_addr.vhd
set_global_assignment -name VHDL_FILE reg_16bits.vhd
set_global_assignment -name VHDL_FILE ram.vhd
set_global_assignment -name VHDL_FILE processor.vhd
set_global_assignment -name VHDL_FILE pc.vhd
set_global_assignment -name VHDL_FILE ctrl_unit.vhd
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top