From 3a17bba7bbc42954021cbb53363126e85c106f63 Mon Sep 17 00:00:00 2001 From: Anton Kesy Date: Thu, 8 Jan 2026 20:54:42 +0100 Subject: [PATCH 1/3] Fix typos --- doc/tutorials/chapter_1/01_setup_installation.md | 6 +++--- doc/tutorials/chapter_3/00_unit_test.md | 2 +- doc/tutorials/chapter_4/00_basic_generation.md | 2 +- doc/tutorials/chapter_5/00_basic_modules.md | 2 +- .../chapter_6/00_combinational_logic.md | 2 +- doc/tutorials/chapter_7/00_sequential_logic.md | 2 +- doc/tutorials/chapter_8/01_interface.md | 4 ++-- .../chapter_8/02_finite_state_machine.md | 6 +++--- .../_docs/A07-bus-ranges-and-swizzling.md | 2 +- .../_docs/A12-non-synthesizable-signal.md | 4 ++-- doc/user_guide/_docs/A16-simulator.md | 2 +- doc/user_guide/_get-started/02-installation.md | 2 +- example/example.dart | 2 +- example/logic_array.dart | 2 +- lib/src/collections/traverseable_collection.dart | 2 +- lib/src/exceptions/logic/put_exception.dart | 2 +- .../exceptions/logic/unassignable_exception.dart | 2 +- lib/src/modules/conditionals/case.dart | 2 +- lib/src/modules/conditionals/if.dart | 8 ++++---- lib/src/modules/conditionals/sequential.dart | 2 +- lib/src/modules/gates.dart | 16 ++++++++-------- lib/src/modules/pipeline.dart | 2 +- lib/src/signals/logic.dart | 2 +- lib/src/signals/wire.dart | 2 +- lib/src/simulator.dart | 2 +- lib/src/synthesizers/utilities/synth_logic.dart | 2 +- lib/src/utilities/synchronous_propagator.dart | 2 +- test/async_reset_test.dart | 2 +- test/logic_value_test.dart | 2 +- test/simulator_test.dart | 2 +- 30 files changed, 46 insertions(+), 46 deletions(-) diff --git a/doc/tutorials/chapter_1/01_setup_installation.md b/doc/tutorials/chapter_1/01_setup_installation.md index af19a4028..a8a416cbd 100644 --- a/doc/tutorials/chapter_1/01_setup_installation.md +++ b/doc/tutorials/chapter_1/01_setup_installation.md @@ -16,7 +16,7 @@ To access the Codespaces feature on the reposito Please note that Codespaces are free for all users with a personal GitHub account that have either a Free or Pro plan. However, there is a monthly usage limit. To learn more about this feature, visit the official GitHub Codespaces Overview page at . -> All personal GitHub.com accounts have a monthly quota of free use of GitHub Codespaces included in the Free or Pro plan. You can get started using GitHub Codespaces on your personal account without changing any settings or providing payment details. You can create and use a codespaces for any repository you can clone. You can also use a template to create codespaces that are not initially associated with a repository. If you create a codespaces from an organization-owned repository, use of the codespaces will either be charged to the organization (if the organization is configured for this), or to your personal account. Codespaces created from templates are always charged to your personal account. You can continue using GitHub Codespaces beyond your monthly included storage and compute usage by providing payment details and setting a spending limit. For more information, see "About billing for GitHub Codespaces. +> All personal GitHub.com accounts have a monthly quota of free use of GitHub Codespaces included in the Free or Pro plan. You can get started using GitHub Codespaces on your personal account without changing any settings or providing payment details. You can create and use a codespaces for any repository you can clone. You can also use a template to create codespaces that are not initially associated with a repository. If you create a codespaces from an organization-owned repository, use of the Codespaces will either be charged to the organization (if the organization is configured for this), or to your personal account. Codespaces created from templates are always charged to your personal account. You can continue using GitHub Codespaces beyond your monthly included storage and compute usage by providing payment details and setting a spending limit. For more information, see "About billing for GitHub Codespaces. ![step 1](assets/codespaces_setup/step_1.png) @@ -48,7 +48,7 @@ If you can see SystemVerilog code pop up on the terminal. Well, you have success ### Step 6: Delete the CodeSpaces (Optional) -To delete the codespaces, go back to and click on codespaces just like step 1. But this time, you will see more options. Click on the `delete` option to delete codespaces. +To delete the Codespaces, go back to and click on Codespaces just like step 1. But this time, you will see more options. Click on the `delete` option to delete Codespaces. ![step 6](assets/codespaces_setup/step_6.png) @@ -248,7 +248,7 @@ If you can see SystemVerilog code pop up on the terminal. Congratulation, you ar ## Docker Container Setup -There are another options which is to setup on lcoal docker environment. Firstly, you must install docker in your PC. +There are another options which is to setup on local docker environment. Firstly, you must install docker in your PC. Pre-requisites: diff --git a/doc/tutorials/chapter_3/00_unit_test.md b/doc/tutorials/chapter_3/00_unit_test.md index 1f94a7d72..c35666df1 100644 --- a/doc/tutorials/chapter_3/00_unit_test.md +++ b/doc/tutorials/chapter_3/00_unit_test.md @@ -47,7 +47,7 @@ import 'package:rohd/rohd.dart'; import 'package:test/test.dart'; void main() { - // your rohd implmentation here! + // your rohd implementation here! } ``` diff --git a/doc/tutorials/chapter_4/00_basic_generation.md b/doc/tutorials/chapter_4/00_basic_generation.md index c32e59a36..ffb9a2663 100644 --- a/doc/tutorials/chapter_4/00_basic_generation.md +++ b/doc/tutorials/chapter_4/00_basic_generation.md @@ -9,7 +9,7 @@ In this chapter: -- You learn how to create an n-bit adder by utilizing dart function and class. You will start by writting unit test and slowly implement the function of the n-bit adder. +- You learn how to create an n-bit adder by utilizing dart function and class. You will start by writing unit test and slowly implement the function of the n-bit adder. ## What is n-bit adder? diff --git a/doc/tutorials/chapter_5/00_basic_modules.md b/doc/tutorials/chapter_5/00_basic_modules.md index 52556e68d..65ab303fc 100644 --- a/doc/tutorials/chapter_5/00_basic_modules.md +++ b/doc/tutorials/chapter_5/00_basic_modules.md @@ -49,7 +49,7 @@ In ROHD, `Module` has inputs and outputs that connects them. However, there are } ``` -3. Logic must be defined *before* the call to `super.build()`, which always must be called **at the end of the `build()` method** if it is overidden. +3. Logic must be defined *before* the call to `super.build()`, which always must be called **at the end of the `build()` method** if it is overridden. The `Module` base class has an optional String argument 'name' which is an instance name. diff --git a/doc/tutorials/chapter_6/00_combinational_logic.md b/doc/tutorials/chapter_6/00_combinational_logic.md index 2b6cbf8f5..618f78f99 100644 --- a/doc/tutorials/chapter_6/00_combinational_logic.md +++ b/doc/tutorials/chapter_6/00_combinational_logic.md @@ -69,7 +69,7 @@ The most important part that you have to notice here is the assignment operator Alright, now we know how the operator in ROHD. we can dive into the `If...Else` in ROHD. In dart, `if...else` is used as a conditional for hardware generation, we can think of it as `if` condition A filled, then generate this pieces of hardware `else` generate that pieces of hardware. While in ROHD, `If...Else` is conditionally assignment which assign signal to a port, which we can think something like `If` Logic signal `A` is high, `Then` assign output port `B` to `A`. -In today tutorial, we will review how to assign value to PORT using ROHD `If...Else` conditionals. Let start by understanding ROHD `If...Else` conditionals. There are several ways of using `If...Else` in ROHD, but the most prefferable way is using `If.block` which is more readable and clean. +In today tutorial, we will review how to assign value to PORT using ROHD `If...Else` conditionals. Let start by understanding ROHD `If...Else` conditionals. There are several ways of using `If...Else` in ROHD, but the most preferable way is using `If.block` which is more readable and clean. *Note: `If...Else` and `Case` in ROHD is written with the first letter capitalized to differentiate from the built-in dart keywords and functionality.* diff --git a/doc/tutorials/chapter_7/00_sequential_logic.md b/doc/tutorials/chapter_7/00_sequential_logic.md index ca721907a..ecb2daa25 100644 --- a/doc/tutorials/chapter_7/00_sequential_logic.md +++ b/doc/tutorials/chapter_7/00_sequential_logic.md @@ -281,7 +281,7 @@ expect( Well, that its for unit test in Sequential Logic. After you finish the `Simulation`, you can use `Simulator.endSimulation()` to end the Simulator and await for `Simulator.simulationEnded`. -There is another method of writting unit test using which is using `Simulator.registerAction()`. But we will dive into that in the next chapter. +There is another method of writing unit test using which is using `Simulator.registerAction()`. But we will dive into that in the next chapter. You can find the executable version of code at [shift_register.dart](shift_register.dart). diff --git a/doc/tutorials/chapter_8/01_interface.md b/doc/tutorials/chapter_8/01_interface.md index 87f9e1386..ccd44fd62 100644 --- a/doc/tutorials/chapter_8/01_interface.md +++ b/doc/tutorials/chapter_8/01_interface.md @@ -79,7 +79,7 @@ class Counter extends Module { ## Counter Module Interface -Let us see how we can change the `ROHD` module to `Counter` interface. First, we can create a enum `CounterDirection` that have tags of `inward`, `outward` and `misc`. You can think of this as what is the category you want to group your ports. This category can be reuse between modules. `inward` port group all inputs port, `outward` group all output ports, and `misc` group all miscellanous ports such as `clk`. +Let us see how we can change the `ROHD` module to `Counter` interface. First, we can create a enum `CounterDirection` that have tags of `inward`, `outward` and `misc`. You can think of this as what is the category you want to group your ports. This category can be reuse between modules. `inward` port group all inputs port, `outward` group all output ports, and `misc` group all miscellaneous ports such as `clk`. Then, we can create our interface `CounterInterface` that extends from parents `Interface`. The `TagType` is the enum that we create earlier. Let create the getters to all ports for `Counter` to allows us to send signals to the interface. @@ -183,7 +183,7 @@ Future main() async { } ``` -Thats it for the ROHD interface. By using interface, you code can be a lot cleaner and readable. Hope you enjoy the tutorials. You can find the executable version of code at [counter_interface.dart](./counter_interface.dart). +That's it for the ROHD interface. By using interface, you code can be a lot cleaner and readable. Hope you enjoy the tutorials. You can find the executable version of code at [counter_interface.dart](./counter_interface.dart). ## Exercise diff --git a/doc/tutorials/chapter_8/02_finite_state_machine.md b/doc/tutorials/chapter_8/02_finite_state_machine.md index b3d99e5c5..dead94976 100644 --- a/doc/tutorials/chapter_8/02_finite_state_machine.md +++ b/doc/tutorials/chapter_8/02_finite_state_machine.md @@ -35,7 +35,7 @@ Transitions between states would be triggered by events such as button presses o ## ROHD FSM -In ROHD, there are abstraction level of writting FSM. Yes, you can definitely wrote the code using Sequential and Combinational like previous chapter. But, today we want to see how we can leverage the abstraction layer provided in ROHD to quickly create the Oven FSM above. +In ROHD, there are abstraction level of writing FSM. Yes, you can definitely write the code using Sequential and Combinational like previous chapter. But, today we want to see how we can leverage the abstraction layer provided in ROHD to quickly create the Oven FSM above. First, we want to import the ROHD package and also `counter` module. We can use the counter interface we created last session. @@ -64,7 +64,7 @@ class OvenModule extends Module { In ROHD, we can use `FiniteStateMachine` API library. The `FiniteStateMachine` constructs a simple FSM, using the `clk` and `reset` signals. Also accepts the `reset` state to transition to `resetState` along with the List of _states of the FSM. Later, we will also need to create a List of `state` and send to the `FiniteStateMachine`. -Let start by intitialize a variable called `_oven` that is `FiniteStateMachine` with `StateIdentifier` as `OvenState`. +Let's start by initializing a variable called `_oven` that is a `FiniteStateMachine` with `StateIdentifier` as `OvenState`. Besides, we can use a simple hashmap to map over the button and LED value to integer. @@ -124,7 +124,7 @@ class OvenModule extends Module { Let start creating the FSM `State`. FSM `State` represent a state named `identifier` with a definition of `events` and `actions` associated with that state. -- `identifier`: Identifer or name of the state. +- `identifier`: Identifier or name of the state. - `events`: A map of the possible conditions that might be true and the next state that the FSM needs to transition to in each of those cases. - `actions`: Actions to perform while the FSM is in this state. diff --git a/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md b/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md index 3b89edb3f..0f6a1a68d 100644 --- a/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md +++ b/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md @@ -6,7 +6,7 @@ last_modified_at: 2022-12-06 toc: true --- -Multi-bit busses can be accessed by single bits and ranges or composed from multiple other signals. Slicing, swizzling, etc. are also accessible on `LogicValue`s. +Multi-bit buses can be accessed by single bits and ranges or composed from multiple other signals. Slicing, swizzling, etc. are also accessible on `LogicValue`s. ```dart var a = Logic(width:8), diff --git a/doc/user_guide/_docs/A12-non-synthesizable-signal.md b/doc/user_guide/_docs/A12-non-synthesizable-signal.md index 97f7a1353..f1f030e14 100644 --- a/doc/user_guide/_docs/A12-non-synthesizable-signal.md +++ b/doc/user_guide/_docs/A12-non-synthesizable-signal.md @@ -6,7 +6,7 @@ last_modified_at: 2022-12-06 toc: true --- -For testbench code or other non-synthesizable code, you can use `put` or `inject` on any `Logic` to deposit a value on the signal. The two functions have similar behavior, but `inject` is shorthand for calling `put` inside of `Simulator.injectAction`, which allows the deposited change to propogate within the same `Simulator` tick. Generally, you will want to use `inject` for testbench interaction with a design if it has any sequential elements. +For testbench code or other non-synthesizable code, you can use `put` or `inject` on any `Logic` to deposit a value on the signal. The two functions have similar behavior, but `inject` is shorthand for calling `put` inside of `Simulator.injectAction`, which allows the deposited change to propagate within the same `Simulator` tick. Generally, you will want to use `inject` for testbench interaction with a design if it has any sequential elements. ```dart var a = Logic(), b = Logic(width:4); @@ -19,4 +19,4 @@ b.inject(0xf); a.inject(LogicValue.x); ``` -Note: changing a value directly with `put()` will propogate the value, but it will not trigger flip-flop edge detection or cosim interaction. +Note: changing a value directly with `put()` will propagate the value, but it will not trigger flip-flop edge detection or cosim interaction. diff --git a/doc/user_guide/_docs/A16-simulator.md b/doc/user_guide/_docs/A16-simulator.md index add69710a..c9f65e213 100644 --- a/doc/user_guide/_docs/A16-simulator.md +++ b/doc/user_guide/_docs/A16-simulator.md @@ -6,7 +6,7 @@ last_modified_at: 2022-12-06 toc: true --- -The ROHD simulator is a static class accessible as [`Simulator`](https://intel.github.io/rohd/rohd/Simulator-class.html) which implements a simple event-based simulator. All `Logic`s in Dart have `glitch` events which propogate values to connected `Logic`s downstream. In this way, ROHD propogates values across the entire graph representation of the hardware (without any `Simulator` involvement required). The simulator has a concept of (unitless) time, and arbitrary Dart functions can be registered to occur at arbitraty times in the simulator. Asking the simulator to run causes it to iterate through all registered timestamps and execute the functions in chronological order. When these functions deposit signals on `Logic`s, it propogates values across the hardware. The simulator has a number of events surrounding execution of a timestamp tick so that things like `FlipFlop`s can know when clocks and signals are glitch-free. +The ROHD simulator is a static class accessible as [`Simulator`](https://intel.github.io/rohd/rohd/Simulator-class.html) which implements a simple event-based simulator. All `Logic`s in Dart have `glitch` events which propagate values to connected `Logic`s downstream. In this way, ROHD propagates values across the entire graph representation of the hardware (without any `Simulator` involvement required). The simulator has a concept of (unitless) time, and arbitrary Dart functions can be registered to occur at arbitraty times in the simulator. Asking the simulator to run causes it to iterate through all registered timestamps and execute the functions in chronological order. When these functions deposit signals on `Logic`s, it propagates values across the hardware. The simulator has a number of events surrounding execution of a timestamp tick so that things like `FlipFlop`s can know when clocks and signals are glitch-free. - To register a function at an arbitraty timestamp, use `Simulator.registerAction` - To set a maximum simulation time, use `Simulator.setMaxSimTime` diff --git a/doc/user_guide/_get-started/02-installation.md b/doc/user_guide/_get-started/02-installation.md index f8e2ba708..4597146e7 100644 --- a/doc/user_guide/_get-started/02-installation.md +++ b/doc/user_guide/_get-started/02-installation.md @@ -30,7 +30,7 @@ Be sure to note the minimum Dart version required for ROHD specified in pubspec. ## Package Managers for Hardware -In the Dart ecosystem, you can use a package manager to define all package dependencies. A package manager allows you to define constrainted subsets of versions of all your *direct* dependencies, and then the tool will solve for a coherent set of all (direct and indirect) dependencies required to build your project. There's no need to manually figure out tool versions, build flags and options, environment setup, etc. because it is all guaranteed to work. Integration of other packages (whether a tool or a hardware IP) become as simple as an `import` statment. Compare that to SystemVerilog IP integration! +In the Dart ecosystem, you can use a package manager to define all package dependencies. A package manager allows you to define constrained subsets of versions of all your *direct* dependencies, and then the tool will solve for a coherent set of all (direct and indirect) dependencies required to build your project. There's no need to manually figure out tool versions, build flags and options, environment setup, etc. because it is all guaranteed to work. Integration of other packages (whether a tool or a hardware IP) become as simple as an `import` statement. Compare that to SystemVerilog IP integration! Read more about package managers here: diff --git a/example/example.dart b/example/example.dart index a58aaaf61..7199ecffa 100644 --- a/example/example.dart +++ b/example/example.dart @@ -11,7 +11,7 @@ // allow `print` messages (disable lint): // ignore_for_file: avoid_print -// Import necessary dart pacakges for this file. +// Import necessary dart packages for this file. import 'dart:async'; // Import the ROHD package. diff --git a/example/logic_array.dart b/example/logic_array.dart index bd5d8d6a3..69439650f 100644 --- a/example/logic_array.dart +++ b/example/logic_array.dart @@ -12,7 +12,7 @@ // allow `print` messages (disable lint): // ignore_for_file: avoid_print -// Import necessary dart pacakges for this file. +// Import necessary dart packages for this file. import 'dart:async'; // Import the ROHD package. diff --git a/lib/src/collections/traverseable_collection.dart b/lib/src/collections/traverseable_collection.dart index 1ba286252..43bf298ee 100644 --- a/lib/src/collections/traverseable_collection.dart +++ b/lib/src/collections/traverseable_collection.dart @@ -19,7 +19,7 @@ import 'dart:collection'; /// /// In situations where it is necessary to iterate through and frequently access /// elements by index, but also check whether a certain element is contained -/// wihin it, and there are many elements, this implementation is substantially +/// within it, and there are many elements, this implementation is substantially /// faster than using either a [Set] or a [List]. class TraverseableCollection with IterableMixin { /// The underlying [Set] that stores the data. diff --git a/lib/src/exceptions/logic/put_exception.dart b/lib/src/exceptions/logic/put_exception.dart index d227a1c95..7d7c8ead0 100644 --- a/lib/src/exceptions/logic/put_exception.dart +++ b/lib/src/exceptions/logic/put_exception.dart @@ -2,7 +2,7 @@ // SPDX-License-Identifier: BSD-3-Clause // // put_exception.dart -// An exception that thrown when a signal failes to `put`. +// An exception that thrown when a signal fails to `put`. // // 2023 January 5 // Author: Max Korbel diff --git a/lib/src/exceptions/logic/unassignable_exception.dart b/lib/src/exceptions/logic/unassignable_exception.dart index 529e86f7d..93468f177 100644 --- a/lib/src/exceptions/logic/unassignable_exception.dart +++ b/lib/src/exceptions/logic/unassignable_exception.dart @@ -2,7 +2,7 @@ // SPDX-License-Identifier: BSD-3-Clause // // unassignable_exception.dart -// An exception that thrown when a signal failes to `put`. +// An exception that thrown when a signal fails to `put`. // // 2024 October 24 // Author: Max Korbel diff --git a/lib/src/modules/conditionals/case.dart b/lib/src/modules/conditionals/case.dart index 34e39a24f..4538b2322 100644 --- a/lib/src/modules/conditionals/case.dart +++ b/lib/src/modules/conditionals/case.dart @@ -158,7 +158,7 @@ class Case extends Conditional { } if (!expression.value.isValid) { - // if expression has X or Z, then propogate X's! + // if expression has X or Z, then propagate X's! driveX(drivenSignals); return; } diff --git a/lib/src/modules/conditionals/if.dart b/lib/src/modules/conditionals/if.dart index 4d0776982..57ae30057 100644 --- a/lib/src/modules/conditionals/if.dart +++ b/lib/src/modules/conditionals/if.dart @@ -12,7 +12,7 @@ import 'package:meta/meta.dart'; import 'package:rohd/rohd.dart'; import 'package:rohd/src/modules/conditionals/ssa.dart'; -/// A conditional block to execute only if [condition] is satisified. +/// A conditional block to execute only if [condition] is satisfied. /// /// Intended for use with [If.block]. class ElseIf { @@ -35,12 +35,12 @@ class ElseIf { ElseIf.s(Logic condition, Conditional then) : this(condition, [then]); } -/// A conditional block to execute only if `condition` is satisified. +/// A conditional block to execute only if `condition` is satisfied. /// /// Intended for use with [If.block]. typedef Iff = ElseIf; -/// A conditional block to execute only if [condition] is satisified. +/// A conditional block to execute only if [condition] is satisfied. /// /// This should come last in [If.block]. class Else extends Iff { @@ -88,7 +88,7 @@ class If extends Conditional { if (orElse != null) Else(orElse), ]); - /// If [condition] is high, then [then] is excutes, + /// If [condition] is high, then [then] is executes, /// otherwise [orElse] is executed. /// /// Use this constructor when you only have a single [then] condition. diff --git a/lib/src/modules/conditionals/sequential.dart b/lib/src/modules/conditionals/sequential.dart index 9ba125ebe..f2e5a0afe 100644 --- a/lib/src/modules/conditionals/sequential.dart +++ b/lib/src/modules/conditionals/sequential.dart @@ -107,7 +107,7 @@ class _SequentialTriggerRaceTracker { _preNonTriggerClearAction = action; } - /// Whether a post-tick has been registered alreayd for this timestep. + /// Whether a post-tick has been registered already for this timestep. bool _registeredPostTick = false; /// Registers a post-tick event to clear the flags. diff --git a/lib/src/modules/gates.dart b/lib/src/modules/gates.dart index eda65c92e..0f16be2f6 100644 --- a/lib/src/modules/gates.dart +++ b/lib/src/modules/gates.dart @@ -83,7 +83,7 @@ class _OneInputUnaryGate extends Module with InlineSystemVerilog { final LogicValue Function(LogicValue a) _op; final String _opStr; - /// Constructs a unary gate for an abitrary custom functional implementation. + /// Constructs a unary gate for an arbitrary custom functional implementation. /// /// The function [_op] is executed as the custom functional behavior. When /// this [Module] is in-lined as SystemVerilog, it will use [_opStr] as the @@ -171,7 +171,7 @@ abstract class _TwoInputBitwiseGate extends Module with InlineSystemVerilog { /// expression to behave as a self-determined width. final bool _makeSelfDetermined; - /// Constructs a two-input bitwise gate for an abitrary custom functional + /// Constructs a two-input bitwise gate for an arbitrary custom functional /// implementation. /// /// The function [_op] is executed as the custom functional behavior. When @@ -269,7 +269,7 @@ abstract class _TwoInputComparisonGate extends Module with InlineSystemVerilog { /// The `String` representing the operation to perform in generated code. final String _opStr; - /// Constructs a two-input comparison gate for an abitrary custom functional + /// Constructs a two-input comparison gate for an arbitrary custom functional /// implementation. /// /// The function [_op] is executed as the custom functional behavior. When @@ -376,7 +376,7 @@ abstract class _ShiftGate extends Module with InlineSystemVerilog { /// If the shift amount is a constant, this will be set to that constant. late final LogicValue? _shiftAmountConstant; - /// Constructs a two-input shift gate for an abitrary custom functional + /// Constructs a two-input shift gate for an arbitrary custom functional /// implementation. /// /// The function [_op] is executed as the custom functional behavior. When @@ -641,7 +641,7 @@ class Multiply extends _TwoInputBitwiseGate { name: name, makeSelfDetermined: true); } -/// A two-input divison module. +/// A two-input division module. class Divide extends _TwoInputBitwiseGate { /// Calculates [in0] divided by [in1]. /// @@ -837,10 +837,10 @@ class Mux extends Module with InlineSystemVerilog { /// The control signal for this [Mux]. late final Logic _control = input(_controlName); - /// [Mux] input propogated when [out] is `0`. + /// [Mux] input propagated when [out] is `0`. late final Logic _d0 = input(_d0Name); - /// [Mux] input propogated when [out] is `1`. + /// [Mux] input propagated when [out] is `1`. late final Logic _d1 = input(_d1Name); /// Output port of the [Mux]. @@ -930,7 +930,7 @@ class IndexGate extends Module with InlineSystemVerilog { /// The output of this gate. late final Logic selection = output(_selectionName); - /// Constructs a two-input bit index gate for an abitrary custom functional + /// Constructs a two-input bit index gate for an arbitrary custom functional /// implementation. /// /// The signal will be indexed by [index] as an output. diff --git a/lib/src/modules/pipeline.dart b/lib/src/modules/pipeline.dart index 4dcfdadcb..c90088ee1 100644 --- a/lib/src/modules/pipeline.dart +++ b/lib/src/modules/pipeline.dart @@ -329,7 +329,7 @@ class Pipeline { /// A pipeline that implements Ready/Valid protocol at each stage. class ReadyValidPipeline extends Pipeline { - /// Indicates that valid contents are ready to be recieved + /// Indicates that valid contents are ready to be received /// at the output of the pipeline. late final Logic validPipeOut; diff --git a/lib/src/signals/logic.dart b/lib/src/signals/logic.dart index 3c117e85e..6e5afe009 100644 --- a/lib/src/signals/logic.dart +++ b/lib/src/signals/logic.dart @@ -361,7 +361,7 @@ class Logic { /// /// The type of [val] should be an `int`, [BigInt], `bool`, or [LogicValue]. /// - /// This function is used for propogating glitches through connected signals. + /// This function is used for propagating glitches through connected signals. /// Use this function for custom definitions of [Module] behavior. /// /// If [fill] is set, all bits of the signal gets set to [val], similar diff --git a/lib/src/signals/wire.dart b/lib/src/signals/wire.dart index 32241f169..854de7638 100644 --- a/lib/src/signals/wire.dart +++ b/lib/src/signals/wire.dart @@ -230,7 +230,7 @@ class _Wire { /// The type of [val] and usage of [fill] should be supported by /// [LogicValue.of]. /// - /// This function is used for propogating glitches through connected signals. + /// This function is used for propagating glitches through connected signals. /// Use this function for custom definitions of [Module] behavior. void put(dynamic val, {required String signalName, bool fill = false}) { var newValue = LogicValue.of(val, fill: fill, width: width); diff --git a/lib/src/simulator.dart b/lib/src/simulator.dart index d631df1f3..8012c4384 100644 --- a/lib/src/simulator.dart +++ b/lib/src/simulator.dart @@ -194,7 +194,7 @@ abstract class Simulator { _maxSimTime = newMaxSimTime; } - /// Registers an abritrary [action] to be executed at [timestamp] time. + /// Registers an arbitrary [action] to be executed at [timestamp] time. /// /// The [action], if it returns a [Future], will be `await`ed. static void registerAction(int timestamp, dynamic Function() action) { diff --git a/lib/src/synthesizers/utilities/synth_logic.dart b/lib/src/synthesizers/utilities/synth_logic.dart index 5dec7300c..65928b3b2 100644 --- a/lib/src/synthesizers/utilities/synth_logic.dart +++ b/lib/src/synthesizers/utilities/synth_logic.dart @@ -214,7 +214,7 @@ class SynthLogic { } else { assert( logics.length > 1, - 'If there is a consant, but the const name is not allowed, ' + 'If there is a constant, but the const name is not allowed, ' 'there needs to be another option'); } } diff --git a/lib/src/utilities/synchronous_propagator.dart b/lib/src/utilities/synchronous_propagator.dart index 411c397f2..fc767e30f 100644 --- a/lib/src/utilities/synchronous_propagator.dart +++ b/lib/src/utilities/synchronous_propagator.dart @@ -2,7 +2,7 @@ // SPDX-License-Identifier: BSD-3-Clause // // synchronous_propogator.dart -// Ultra light-weight events for signal propogation +// Ultra light-weight events for signal propagation // // 2021 August 3 // Author: Max Korbel diff --git a/test/async_reset_test.dart b/test/async_reset_test.dart index 6f0ff4657..099acb420 100644 --- a/test/async_reset_test.dart +++ b/test/async_reset_test.dart @@ -15,7 +15,7 @@ import 'package:test/test.dart'; class NonIdenticalTriggerSeq extends Module { /// If [triggerAfterSampledUpdate] is `true`, then the trigger for the - /// sequential block happens *afer* the signal being sampled updates. If + /// sequential block happens *after* the signal being sampled updates. If /// [triggerAfterSampledUpdate] is `false`, then the trigger for the /// sequential block happens *before* the signal being sampled updates. NonIdenticalTriggerSeq( diff --git a/test/logic_value_test.dart b/test/logic_value_test.dart index 6fe17d4b9..fb9753014 100644 --- a/test/logic_value_test.dart +++ b/test/logic_value_test.dart @@ -14,7 +14,7 @@ import 'package:rohd/src/exceptions/logic_value/invalid_random_logic_value_excep import 'package:rohd/src/utilities/web.dart'; import 'package:test/test.dart'; -// All logicvalues to support trying all possiblities +// All logicvalues to support trying all possibilities const List allLv = [ LogicValue.zero, LogicValue.one, diff --git a/test/simulator_test.dart b/test/simulator_test.dart index dfd652594..2ab79d366 100644 --- a/test/simulator_test.dart +++ b/test/simulator_test.dart @@ -28,7 +28,7 @@ void main() { expect(actionTaken, equals(true)); }); - test('simulator supports cancelation of previously scheduled actions', + test('simulator supports cancellation of previously scheduled actions', () async { var actionCount = 0; From 43ac0bd1a23efc526e831563f9497f677be0dd0a Mon Sep 17 00:00:00 2001 From: Anton Kesy Date: Fri, 9 Jan 2026 11:00:34 +0100 Subject: [PATCH 2/3] Update last_modified_at --- doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md | 2 +- doc/user_guide/_docs/A12-non-synthesizable-signal.md | 2 +- doc/user_guide/_docs/A16-simulator.md | 2 +- doc/user_guide/_get-started/02-installation.md | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md b/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md index 0f6a1a68d..f4a21d4fd 100644 --- a/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md +++ b/doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md @@ -2,7 +2,7 @@ title: "Bus ranges and swizzling" permalink: /docs/bus-range-swizzling/ excerpt: "Bus ranges and swizzling" -last_modified_at: 2022-12-06 +last_modified_at: 2026-01-09 toc: true --- diff --git a/doc/user_guide/_docs/A12-non-synthesizable-signal.md b/doc/user_guide/_docs/A12-non-synthesizable-signal.md index f1f030e14..2d5ccdc86 100644 --- a/doc/user_guide/_docs/A12-non-synthesizable-signal.md +++ b/doc/user_guide/_docs/A12-non-synthesizable-signal.md @@ -2,7 +2,7 @@ title: "Non-synthesizable signal deposition" permalink: /docs/non-synthesizable-signal/ excerpt: "Non-synthesizable signal deposition" -last_modified_at: 2022-12-06 +last_modified_at: 2026-01-09 toc: true --- diff --git a/doc/user_guide/_docs/A16-simulator.md b/doc/user_guide/_docs/A16-simulator.md index c9f65e213..da8dcfbb3 100644 --- a/doc/user_guide/_docs/A16-simulator.md +++ b/doc/user_guide/_docs/A16-simulator.md @@ -2,7 +2,7 @@ title: "ROHD Simulator" permalink: /docs/simulator/ excerpt: "ROHD Simulator" -last_modified_at: 2022-12-06 +last_modified_at: 2026-01-09 toc: true --- diff --git a/doc/user_guide/_get-started/02-installation.md b/doc/user_guide/_get-started/02-installation.md index 4597146e7..204ce4af9 100644 --- a/doc/user_guide/_get-started/02-installation.md +++ b/doc/user_guide/_get-started/02-installation.md @@ -2,7 +2,7 @@ title: "Setup & Install" permalink: /get-started/setup/ excerpt: "Instructions for installing the theme for new and existing Jekyll based sites." -last_modified_at: 2023-01-03 +last_modified_at: 2026-01-09 toc: true --- From 60371abc644d742d859f0ea2fa68b720daf22b5c Mon Sep 17 00:00:00 2001 From: Anton Kesy Date: Fri, 9 Jan 2026 11:01:28 +0100 Subject: [PATCH 3/3] Update copyright date --- doc/tutorials/chapter_1/01_setup_installation.md | 2 +- example/example.dart | 2 +- example/logic_array.dart | 2 +- lib/src/collections/traverseable_collection.dart | 2 +- lib/src/exceptions/logic/put_exception.dart | 2 +- lib/src/exceptions/logic/unassignable_exception.dart | 2 +- lib/src/modules/conditionals/case.dart | 2 +- lib/src/modules/conditionals/if.dart | 2 +- lib/src/modules/conditionals/sequential.dart | 2 +- lib/src/modules/gates.dart | 2 +- lib/src/modules/pipeline.dart | 2 +- lib/src/signals/logic.dart | 2 +- lib/src/signals/wire.dart | 2 +- lib/src/simulator.dart | 2 +- lib/src/synthesizers/utilities/synth_logic.dart | 2 +- lib/src/utilities/synchronous_propagator.dart | 2 +- test/async_reset_test.dart | 2 +- test/logic_value_test.dart | 2 +- test/simulator_test.dart | 2 +- 19 files changed, 19 insertions(+), 19 deletions(-) diff --git a/doc/tutorials/chapter_1/01_setup_installation.md b/doc/tutorials/chapter_1/01_setup_installation.md index a8a416cbd..7f7bb00a9 100644 --- a/doc/tutorials/chapter_1/01_setup_installation.md +++ b/doc/tutorials/chapter_1/01_setup_installation.md @@ -291,5 +291,5 @@ If you can see SystemVerilog code pop up on the terminal. Congratulation, you ar 2023 February 13 Author: Yao Jing Quek <> -Copyright (C) 2021-2023 Intel Corporation +Copyright (C) 2021-2026 Intel Corporation SPDX-License-Identifier: BSD-3-Clause diff --git a/example/example.dart b/example/example.dart index 7199ecffa..2ddbfc738 100644 --- a/example/example.dart +++ b/example/example.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2023 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // example.dart diff --git a/example/logic_array.dart b/example/logic_array.dart index 69439650f..f772c4929 100644 --- a/example/logic_array.dart +++ b/example/logic_array.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2025 Intel Corporation +// Copyright (C) 2025-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // logic_array.dart diff --git a/lib/src/collections/traverseable_collection.dart b/lib/src/collections/traverseable_collection.dart index 43bf298ee..fd5bdfe5f 100644 --- a/lib/src/collections/traverseable_collection.dart +++ b/lib/src/collections/traverseable_collection.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2024 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // traverseable_collection.dart diff --git a/lib/src/exceptions/logic/put_exception.dart b/lib/src/exceptions/logic/put_exception.dart index 7d7c8ead0..36d8f8015 100644 --- a/lib/src/exceptions/logic/put_exception.dart +++ b/lib/src/exceptions/logic/put_exception.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2023 Intel Corporation +// Copyright (C) 2023-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // put_exception.dart diff --git a/lib/src/exceptions/logic/unassignable_exception.dart b/lib/src/exceptions/logic/unassignable_exception.dart index 93468f177..9fe239d17 100644 --- a/lib/src/exceptions/logic/unassignable_exception.dart +++ b/lib/src/exceptions/logic/unassignable_exception.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2024 Intel Corporation +// Copyright (C) 2024-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // unassignable_exception.dart diff --git a/lib/src/modules/conditionals/case.dart b/lib/src/modules/conditionals/case.dart index 4538b2322..61b90fff3 100644 --- a/lib/src/modules/conditionals/case.dart +++ b/lib/src/modules/conditionals/case.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // case.dart diff --git a/lib/src/modules/conditionals/if.dart b/lib/src/modules/conditionals/if.dart index 57ae30057..f406abcef 100644 --- a/lib/src/modules/conditionals/if.dart +++ b/lib/src/modules/conditionals/if.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // if.dart diff --git a/lib/src/modules/conditionals/sequential.dart b/lib/src/modules/conditionals/sequential.dart index f2e5a0afe..62a7c1129 100644 --- a/lib/src/modules/conditionals/sequential.dart +++ b/lib/src/modules/conditionals/sequential.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // sequential.dart diff --git a/lib/src/modules/gates.dart b/lib/src/modules/gates.dart index 0f16be2f6..2780cde9d 100644 --- a/lib/src/modules/gates.dart +++ b/lib/src/modules/gates.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // gates.dart diff --git a/lib/src/modules/pipeline.dart b/lib/src/modules/pipeline.dart index c90088ee1..47dae1a2f 100644 --- a/lib/src/modules/pipeline.dart +++ b/lib/src/modules/pipeline.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2024 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // pipeline.dart diff --git a/lib/src/signals/logic.dart b/lib/src/signals/logic.dart index 6e5afe009..88afba0d6 100644 --- a/lib/src/signals/logic.dart +++ b/lib/src/signals/logic.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // logic.dart diff --git a/lib/src/signals/wire.dart b/lib/src/signals/wire.dart index 854de7638..883e3eaf0 100644 --- a/lib/src/signals/wire.dart +++ b/lib/src/signals/wire.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2023 Intel Corporation +// Copyright (C) 2023-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // wire.dart diff --git a/lib/src/simulator.dart b/lib/src/simulator.dart index 8012c4384..eeb51564b 100644 --- a/lib/src/simulator.dart +++ b/lib/src/simulator.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // Copyright (C) 2024 Adam Rose // SPDX-License-Identifier: BSD-3-Clause // diff --git a/lib/src/synthesizers/utilities/synth_logic.dart b/lib/src/synthesizers/utilities/synth_logic.dart index 65928b3b2..709487a88 100644 --- a/lib/src/synthesizers/utilities/synth_logic.dart +++ b/lib/src/synthesizers/utilities/synth_logic.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // synth_logic.dart diff --git a/lib/src/utilities/synchronous_propagator.dart b/lib/src/utilities/synchronous_propagator.dart index fc767e30f..317c19409 100644 --- a/lib/src/utilities/synchronous_propagator.dart +++ b/lib/src/utilities/synchronous_propagator.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // synchronous_propogator.dart diff --git a/test/async_reset_test.dart b/test/async_reset_test.dart index 099acb420..82e1dbcdf 100644 --- a/test/async_reset_test.dart +++ b/test/async_reset_test.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2024-2025 Intel Corporation +// Copyright (C) 2024-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // async_reset_test.dart diff --git a/test/logic_value_test.dart b/test/logic_value_test.dart index fb9753014..d3753df8d 100644 --- a/test/logic_value_test.dart +++ b/test/logic_value_test.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause // // logic_value_test.dart diff --git a/test/simulator_test.dart b/test/simulator_test.dart index 2ab79d366..e22a4e054 100644 --- a/test/simulator_test.dart +++ b/test/simulator_test.dart @@ -1,4 +1,4 @@ -// Copyright (C) 2021-2025 Intel Corporation +// Copyright (C) 2021-2026 Intel Corporation // Copyright (C) 2024 Adam Rose // SPDX-License-Identifier: BSD-3-Clause //