diff --git a/README.md b/README.md index a55f7b3c9..8b3b5b27e 100644 --- a/README.md +++ b/README.md @@ -52,6 +52,8 @@ SSA snapshots of the test fixtures. The optimized binaries will run on any moder ARM64 processor, and on x86_64 processors not older than Intel Haswell and AMD Zen (circa 2013, the optimizer uses FMA3 instructions). +Here are the links the the perf run in CI: TODO + `badc` emits position-independent code and the real native binaries (macOS Mach-O, Linux ELF, or Windows PE32+), on any of five targets, from any host: diff --git a/demos/chibicc/smoke.py b/demos/chibicc/smoke.py index 7349c44db..84c248aa6 100644 --- a/demos/chibicc/smoke.py +++ b/demos/chibicc/smoke.py @@ -73,6 +73,7 @@ def compile_one(badc: Path, src: Path, out: Path) -> tuple[bool, str]: proc = subprocess.run( [ str(badc), + "-O", "-I", str(CHIBICC_DIR), "-c", @@ -160,7 +161,7 @@ def main() -> int: src_files = [str(CHIBICC_DIR / name) for name in TU_STATE] out_path = work / ("chibicc.exe" if WIN else "chibicc") proc = subprocess.run( - [str(badc), "-I", str(CHIBICC_DIR), "-o", str(out_path), *src_files], + [str(badc), "-O", "-I", str(CHIBICC_DIR), "-o", str(out_path), *src_files], capture_output=True, text=True, check=False, diff --git a/demos/gui_hello/smoke.py b/demos/gui_hello/smoke.py index 8b2e071ff..09cc37f47 100755 --- a/demos/gui_hello/smoke.py +++ b/demos/gui_hello/smoke.py @@ -78,7 +78,7 @@ def main() -> int: for target, source, suffix in BUILDS: src = GUI_DIR / source out = work / f"hello-{target}{suffix}" - cmd = [str(badc), f"--target={target}", str(src), "-o", str(out)] + cmd = [str(badc), "-O", f"--target={target}", str(src), "-o", str(out)] if target.startswith("windows"): cmd.extend(["-include", "msvc_compat.h"]) proc = subprocess.run(cmd, capture_output=True, text=True) diff --git a/demos/nt_loader/smoke.py b/demos/nt_loader/smoke.py index 52f1f5bd5..dd42cf372 100644 --- a/demos/nt_loader/smoke.py +++ b/demos/nt_loader/smoke.py @@ -70,7 +70,7 @@ def pe_subsystem(path: Path) -> int: def build_pe(badc: Path, target: str, source: Path, out: Path) -> None: - cmd = [str(badc), f"--target={target}", str(source), "-o", str(out)] + cmd = [str(badc), "-O", f"--target={target}", str(source), "-o", str(out)] proc = subprocess.run(cmd, capture_output=True, text=True) if proc.returncode != 0: print( diff --git a/demos/python/build.py b/demos/python/build.py index f991d37d6..6e574967c 100644 --- a/demos/python/build.py +++ b/demos/python/build.py @@ -299,6 +299,21 @@ def _fix_winsock_fd_gates() -> None: sys.exit("build: select() fd-range gate not found in selectmodule.c") +def _widen_stack_margin() -> None: + """badc's register allocator does not yet split live ranges, so + _PyEval_EvalFrameDefault's frame is several times larger than the + reference compilers'. CPython requires the recursion-check margin to + exceed one eval frame (pycore_pythonrun.h); raise it from 2^11 to + 2^13 words until the allocator work shrinks the frame.""" + pythonrun = SRC / "Include/internal/pycore_pythonrun.h" + text = pythonrun.read_text() + needle = "# define _PyOS_LOG2_STACK_MARGIN 11" + if needle in text: + pythonrun.write_text(text.replace(needle, "# define _PyOS_LOG2_STACK_MARGIN 13", 1)) + elif "# define _PyOS_LOG2_STACK_MARGIN 13" not in text: + sys.exit("build: _PyOS_LOG2_STACK_MARGIN not found in pycore_pythonrun.h") + + def _check_frozen() -> None: missing = [ h for h in re.findall(r'frozen_modules/[\w.]+\.h', (SRC / "Python/frozen.c").read_text()) @@ -316,6 +331,7 @@ def ensure_inputs(target: str, log) -> None: sys.stderr.write(r.stdout + r.stderr) sys.exit("build: setup.py failed") cfg = TARGETS[target] + _widen_stack_margin() if cfg.get("windows"): # Windows derives its config from the in-tree PC/ files rather than a # committed manifest: disable mimalloc, wire the extra builtins into the @@ -446,7 +462,7 @@ def build(target: str, do_link: bool, log) -> Path | None: out = PY_DIR / ".cache" / f"obj-{target}" out.mkdir(parents=True, exist_ok=True) dbg = ["-g"] if os.environ.get("BADC_PY_G") else [] - opt = ["-O"] if os.environ.get("BADC_PY_O") else [] + opt = ["-O"] entries = _entries(target) jobs = [(badc, target, src, defs, incs, dbg, opt, str(out), str(SRC)) for src, defs, incs in entries] @@ -473,7 +489,7 @@ def build(target: str, do_link: bool, log) -> Path | None: # the core defines (no CPython includes needed). for helper in _WIN_HELPERS: hobj = out / (helper[:-2] + ".o") - hcmd = [badc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", *dbg, + hcmd = [badc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", *dbg, *opt, *[f"-D{d}" for d in _WIN_DEFINES], str(PY_DIR / helper), "-o", str(hobj)] r = run(hcmd, timeout=120) if r.returncode != 0: @@ -738,7 +754,10 @@ def run_tests(target: str, py: Path, log, tier2: bool = False) -> int: r = run([str(exe), "-m", "test", "-q", "-w", *ignore, *slice_], cwd=str(cwd), env=env, timeout=1800) print(f"build: test slice {' '.join(slice_)} exit={r.returncode}") if r.returncode != 0: - sys.stderr.write((r.stdout + r.stderr)[-3000:]) + # Keep the head too: a fatal-error dump puts the message and the + # aborting frame above hundreds of repeated traceback lines. + blob = r.stdout + r.stderr + sys.stderr.write(blob[:3000] + ("\n...\n" + blob[-3000:] if len(blob) > 3000 else "")) return 1 return 0 diff --git a/demos/python/compare_compilers.py b/demos/python/compare_compilers.py index 960965e12..60478e221 100644 --- a/demos/python/compare_compilers.py +++ b/demos/python/compare_compilers.py @@ -1,6 +1,7 @@ #!/usr/bin/env python3 """Build CPython from the same recipe with badc and the platform reference -compiler (clang on POSIX, cl on Windows), at -O and without, and report +compiler (clang on POSIX, cl on Windows), at -O and without (badc -O +implies NDEBUG; the clang/cl -O legs define it explicitly), and report per-binary section sizes plus a runtime microbenchmark. The recipe -- the per-TU source list, defines, and includes -- comes from @@ -75,7 +76,7 @@ def _compile_cmd(cc_kind, cc, target, src, defs, incs, obj, opt, reenable): return [cc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", '-DCOMPILER="[badc]"', *o, *defs, *incs, src, "-o", obj] if cc_kind == "clang": - o = ["-O2"] if opt else ["-O0"] + o = ["-O2", "-DNDEBUG"] if opt else ["-O0"] redef = [f"-D{m}=1" for m in reenable] # Force the same no-__int128 path badc takes, so the bigint code is # identical and the comparison isolates the compiler, not the dialect. diff --git a/demos/python/smoke.py b/demos/python/smoke.py index e09867b40..3abba19da 100644 --- a/demos/python/smoke.py +++ b/demos/python/smoke.py @@ -183,13 +183,10 @@ def compile_and_link(badc: str, trace: Path, out: Path, log) -> Path: src, flags = compiles[obj] dst = out / (obj.replace("/", "_")) dbg = ["-g"] if os.environ.get("BADC_PY_G") else [] - # BADC_PY_O builds each TU with the optimizer, for a benchmarkable - # interpreter and to exercise the optimization passes across the - # whole source. The host build trace's own -O flags are dropped by + # Each TU builds with the optimizer (badc -O also implies NDEBUG). + # The host build trace's own -O flags are dropped by # parse_commands, so this is the only optimization control. - do_opt = bool(os.environ.get("BADC_PY_O")) - if do_opt and opt_only is not None: - do_opt = os.path.basename(src) in opt_only + do_opt = opt_only is None or os.path.basename(src) in opt_only opt = ["-O"] if do_opt else [] # `--gnu` mirrors the reference clang build: __GNUC__ makes the # struct layouts (packed tracemalloc) match the clang-built diff --git a/demos/python/targets/linux-aarch64/pyconfig.h b/demos/python/targets/linux-aarch64/pyconfig.h index 943f7caf6..2f75deb8b 100644 --- a/demos/python/targets/linux-aarch64/pyconfig.h +++ b/demos/python/targets/linux-aarch64/pyconfig.h @@ -1003,6 +1003,12 @@ /* Define to 1 if you have the 'pthread_getattr_np' function. */ #define HAVE_PTHREAD_GETATTR_NP 1 +/* badc links the GNU C library on these targets; CPython gates the + pthread_getattr_np stack-bounds path on the glibc macro. */ +#ifndef __GLIBC__ +#define __GLIBC__ 2 +#define __GLIBC_MINOR__ 17 +#endif /* Define to 1 if you have the 'pthread_getcpuclockid' function. */ #define HAVE_PTHREAD_GETCPUCLOCKID 1 diff --git a/demos/python/targets/linux-x64/pyconfig.h b/demos/python/targets/linux-x64/pyconfig.h index 940ac6bb5..4ea17feb8 100644 --- a/demos/python/targets/linux-x64/pyconfig.h +++ b/demos/python/targets/linux-x64/pyconfig.h @@ -1003,6 +1003,12 @@ /* Define to 1 if you have the 'pthread_getattr_np' function. */ #define HAVE_PTHREAD_GETATTR_NP 1 +/* badc links the GNU C library on these targets; CPython gates the + pthread_getattr_np stack-bounds path on the glibc macro. */ +#ifndef __GLIBC__ +#define __GLIBC__ 2 +#define __GLIBC_MINOR__ 17 +#endif /* Define to 1 if you have the 'pthread_getcpuclockid' function. */ #define HAVE_PTHREAD_GETCPUCLOCKID 1 diff --git a/demos/quickjs/smoke.py b/demos/quickjs/smoke.py index d29b242f8..5f5664266 100644 --- a/demos/quickjs/smoke.py +++ b/demos/quickjs/smoke.py @@ -97,7 +97,7 @@ def main() -> int: # `--export-all` puts the engine's API in the executable's dynamic # symbol table so a dlopen'd native module resolves its references to # the host (JS_NewObject, JS_ToIndex, ...) from the global scope. - cmd = [str(badc), "--export-all"] + cmd = [str(badc), "-O", "--export-all"] for d in DEFINES: cmd += ["-D", d] cmd += ["-I", str(QJS_DIR)] @@ -158,7 +158,7 @@ def main() -> int: ) module_passed = 0 for src, so, test, cwd in modules: - build = [str(badc), "--export-all", "--shared"] + build = [str(badc), "-O", "--export-all", "--shared"] for d in DEFINES: build += ["-D", d] build += ["-D", "JS_SHARED_LIBRARY", "-I", str(QJS_DIR), str(src), "-o", str(so)] diff --git a/demos/raylib/smoke.py b/demos/raylib/smoke.py index d0a1af36b..3c7ef8149 100644 --- a/demos/raylib/smoke.py +++ b/demos/raylib/smoke.py @@ -166,7 +166,7 @@ def platform_build(badc: Path, work: Path) -> bool: objs = [] for mod in modules: obj = work / f"{mod}.o" - cmd = [str(badc), "-c", *defines] + cmd = [str(badc), "-O", "-c", *defines] if mod == "rcore": cmd += rcore_extra if mod == "raudio": @@ -183,7 +183,7 @@ def platform_build(badc: Path, work: Path) -> bool: return False logic_obj = work / "loderunner_logic.o" - if run([str(badc), "-c", "-I", str(RAYLIB_DIR), + if run([str(badc), "-O", "-c", "-I", str(RAYLIB_DIR), "-o", str(logic_obj), str(RAYLIB_DIR / "loderunner_logic.c")]).returncode != 0: return False @@ -192,7 +192,7 @@ def platform_build(badc: Path, work: Path) -> bool: # `#pragma subsystem(windows)` drives the PE subsystem (a pragma in a # separately-compiled object is not visible at link). loderunner_logic.c # is still separately compiled to exercise the multi-object link. - if run([str(badc), *defines, "-I", str(inc), "-I", str(src), + if run([str(badc), "-O", *defines, "-I", str(inc), "-I", str(src), str(RAYLIB_DIR / "loderunner.c"), str(logic_obj), str(archive), "-o", str(game)]).returncode != 0: print("smoke FAIL: standalone link", file=sys.stderr) @@ -283,7 +283,7 @@ def _validate_win_imports(badc: Path, game: Path, work: Path) -> bool: lines.append("return miss?1:0;}") src.write_text("\n".join(lines) + "\n") exe = work / f"import_probe{EXE}" - if run([str(badc), str(src), "-o", str(exe)]).returncode != 0: + if run([str(badc), "-O", str(src), "-o", str(exe)]).returncode != 0: print("smoke FAIL: could not build the import probe", file=sys.stderr) return False p = run([str(exe)], capture_output=True, text=True) diff --git a/demos/tcl/smoke.py b/demos/tcl/smoke.py index 04df77777..be41dd699 100644 --- a/demos/tcl/smoke.py +++ b/demos/tcl/smoke.py @@ -114,7 +114,7 @@ def compile_units(badc: str, unix: Path, generic: Path, out: Path, log) -> list[ objs, fails = [], [] for src, obj, flags in cmds: objp = out / f"{obj}.o" - cmd = [badc, "-c", "-UHAVE_CPUID", *extra, *flags, *includes, src, "-o", str(objp)] + cmd = [badc, "-O", "-c", "-UHAVE_CPUID", *extra, *flags, *includes, src, "-o", str(objp)] r = run(cmd, timeout=180) if r.returncode != 0: msg = (r.stderr.strip().splitlines() or [f"rc{r.returncode}"])[-1] @@ -127,7 +127,7 @@ def compile_units(badc: str, unix: Path, generic: Path, out: Path, log) -> list[ zflags = ["-DHAVE_ZLIB=1", "-DBUILD_tcl", "-DSTDC", "-I" + str(zdir)] for name in ZLIB_UNITS: objp = out / f"Z{name}.o" - r = run([badc, "-c", *zflags, str(zdir / f"{name}.c"), "-o", str(objp)], timeout=180) + r = run([badc, "-O", "-c", *zflags, str(zdir / f"{name}.c"), "-o", str(objp)], timeout=180) if r.returncode != 0: fails.append((f"zlib {name}", (r.stderr.strip().splitlines() or ["rc"])[-1][:160])) else: diff --git a/demos/tinycc/smoke.py b/demos/tinycc/smoke.py index 657fec13d..0275aec52 100644 --- a/demos/tinycc/smoke.py +++ b/demos/tinycc/smoke.py @@ -252,7 +252,7 @@ def compile_one( target: str | None, ) -> tuple[bool, str]: """Run badc -c against `src`. Returns (ok, captured_stderr_head).""" - cmd = [str(badc), "-q", "-I", str(TINYCC_DIR)] + cmd = [str(badc), "-q", "-O", "-I", str(TINYCC_DIR)] if target is not None: cmd.append(f"--target={target}") for d in cpp_defs: @@ -373,7 +373,7 @@ def main() -> int: src_files = [str(TINYCC_DIR / name) for name in active] link_target_is_win = key[0] == "Windows" out_path = work / ("tcc.exe" if link_target_is_win else "tcc") - cmd = [str(badc), "-q", "-I", str(TINYCC_DIR)] + cmd = [str(badc), "-q", "-O", "-I", str(TINYCC_DIR)] if target is not None: cmd.append(f"--target={target}") for d in cpp_defs: diff --git a/headers/include/pthread.h b/headers/include/pthread.h index 7ac027eb0..84f9078d4 100644 --- a/headers/include/pthread.h +++ b/headers/include/pthread.h @@ -58,6 +58,8 @@ #pragma binding(libc::pthread_cond_broadcast, "_pthread_cond_broadcast") #pragma binding(libc::pthread_attr_init, "_pthread_attr_init") #pragma binding(libc::pthread_attr_destroy, "_pthread_attr_destroy") +#pragma binding(libc::pthread_attr_getguardsize, "_pthread_attr_getguardsize") +#pragma binding(libc::pthread_attr_getstack, "_pthread_attr_getstack") #pragma binding(libc::pthread_attr_setdetachstate, "_pthread_attr_setdetachstate") #pragma binding(libc::pthread_attr_setstacksize, "_pthread_attr_setstacksize") #pragma binding(libc::pthread_attr_setscope, "_pthread_attr_setscope") @@ -128,6 +130,9 @@ #pragma binding(libc::pthread_attr_setschedparam, "pthread_attr_setschedparam") #pragma binding(libc::pthread_attr_getschedparam, "pthread_attr_getschedparam") #pragma binding(libc::pthread_attr_setinheritsched, "pthread_attr_setinheritsched") +#pragma binding(libc::pthread_attr_getguardsize, "pthread_attr_getguardsize") +#pragma binding(libc::pthread_attr_getstack, "pthread_attr_getstack") +#pragma binding(libc::pthread_getattr_np, "pthread_getattr_np") // The Linux C library's pthread_atfork lives in libc_nonshared.a (a static stub), // not as a dynamic export of libc.so.6 -- x86_64 keeps a weak legacy // alias but aarch64 does not, so a dynamic import resolves on one and @@ -314,6 +319,13 @@ int pthread_attr_setscope(char *attr, int scope); int pthread_attr_setschedpolicy(char *attr, int policy); int pthread_attr_setschedparam(char *attr, const struct sched_param *param); int pthread_attr_getschedparam(const char *attr, struct sched_param *param); +int pthread_attr_getguardsize(const char *attr, unsigned long *guardsize); +int pthread_attr_getstack(const char *attr, void **stackaddr, unsigned long *stacksize); +#if defined(__linux__) +// GNU extension: the running thread's attributes, including the real +// stack bounds (the portable route is pthread_attr_getstack on these). +int pthread_getattr_np(unsigned long thread, char *attr); +#endif int pthread_attr_setinheritsched(char *attr, int inheritsched); #ifdef __linux__ // Linux names the calling-convention pair (pthread_t, name). diff --git a/src/c5/ast/walk.rs b/src/c5/ast/walk.rs index 9e470cd89..6cd05a805 100644 --- a/src/c5/ast/walk.rs +++ b/src/c5/ast/walk.rs @@ -1091,7 +1091,9 @@ impl<'a> Walker<'a> { sorted.sort_by_key(|p| p.0); } let lt_op = if disc_unsigned { BinOp::Ult } else { BinOp::Lt }; - self.emit_switch_search(b, disc_val, &sorted, lt_op, deflt); + if !self.emit_switch_table(b, disc_val, &sorted, deflt) { + self.emit_switch_search(b, disc_val, &sorted, lt_op, deflt); + } // Walk the body linearly. The opening block is reachable // only by a goto into the switch ahead of the first case @@ -1335,11 +1337,62 @@ impl<'a> Walker<'a> { blk } - /// Reserve a block for every `case` value and for `default` in a - /// switch body, descending into nested statements but not into a - /// nested switch (whose labels belong to it, C99 6.8.4.2). A - /// duplicate case value keeps the first block; the parser already - /// rejects duplicates. + /// Emit a jump-table dispatcher for a dense case list: a bias + /// subtract, an unsigned bounds check branching to `deflt`, and a + /// `Terminator::JumpTable` indexed by the biased discriminant. + /// Returns false (leaving the cursor untouched) when the case set + /// is too small or too sparse; the caller falls back to the + /// compare tree. `cases` is sorted with values already converted + /// to the promoted controlling type, so consecutive entries differ + /// by their true unsigned distance regardless of signedness. + fn emit_switch_table( + &mut self, + b: &mut super::super::codegen::ssa::build::SsaBuilder, + disc: super::super::ir::ValueId, + cases: &[(i64, super::super::ir::BlockId)], + deflt: super::super::ir::BlockId, + ) -> bool { + const MIN_CASES: usize = 8; + if cases.len() < MIN_CASES { + return false; + } + let lo = cases[0].0; + let hi = cases[cases.len() - 1].0; + // Exact unsigned span; wrapping covers the full i64 label + // domain (hi >= lo in the sort order, so the difference is + // < 2^64 and the wrapped subtraction is exact). + let span = (hi as u64).wrapping_sub(lo as u64); + // Density gate: at least half the table slots hold a real + // case. The bound also caps the table at 2 * cases entries. + if span >= 2 * cases.len() as u64 { + return false; + } + let mut targets = alloc::vec![deflt; span as usize + 1]; + for &(v, blk) in cases { + let slot = &mut targets[(v as u64).wrapping_sub(lo as u64) as usize]; + // First case wins on a converted-value collision, matching + // the compare tree's first-match order. + if *slot == deflt { + *slot = blk; + } + } + // idx = disc - lo; the wrapped 64-bit subtraction with the + // unsigned bound accepts exactly disc in [lo, hi] for every + // promoted width (the discriminant is already sign- or + // zero-extended to the same domain as the labels). + let idx = if lo != 0 { + b.binop_imm(BinOp::Sub, disc, lo) + } else { + disc + }; + let inb = b.binop_imm(BinOp::Ult, idx, span as i64 + 1); + let dispatch = b.new_block(); + b.branch_zero(inb, deflt, dispatch); + b.switch_to(dispatch); + b.jump_table(idx, targets); + true + } + /// Emit a balanced binary search over a sorted, distinct case list /// as the switch dispatcher. The cursor is at an open block on entry /// and the block is closed on return. Internal nodes branch on @@ -1374,6 +1427,11 @@ impl<'a> Walker<'a> { } } + /// Reserve a block for every `case` value and for `default` in a + /// switch body, descending into nested statements but not into a + /// nested switch (whose labels belong to it, C99 6.8.4.2). A + /// duplicate case value keeps the first block; the parser already + /// rejects duplicates. fn collect_switch_cases( &mut self, b: &mut super::super::codegen::ssa::build::SsaBuilder, @@ -1447,9 +1505,7 @@ impl<'a> Walker<'a> { // f64 bits untagged. if is_float_ty(*ty) { let f32_bits = f64::from_bits(*bits) as f32; - let imm = f32_bits.to_bits() as i64; - let v = b.imm(imm); - return Ok(b.mark_f32(v)); + return Ok(b.imm_f32(f32_bits.to_bits())); } Ok(b.imm(*bits as i64)) } @@ -2392,6 +2448,12 @@ impl<'a> Walker<'a> { return Ok(call); } if *class == Token::Sys as i64 { + // A returns-twice callee (setjmp family / + // vfork) disables spill-slot sharing in this + // function; see FunctionSsa::has_returns_twice_call. + if crate::c5::ir::returns_twice_fn_name(&self.symbols[*sym as usize].name) { + b.mark_returns_twice(); + } // The Ident's `val` is the binding's // flat index across all `#pragma // binding(...)` directives -- exactly @@ -2993,7 +3055,7 @@ impl<'a> Walker<'a> { let load_kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lhs); - let place = self.rmw_place(b, *lhs, store_kind)?; + let place = self.rmw_place(b, *lhs)?; let old = place.load(b, load_kind, vol); // Constant-rhs short-circuit (mirror of the // `Expr::Binary` path): an integer-literal rhs @@ -3112,7 +3174,7 @@ impl<'a> Walker<'a> { let kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lvalue); - let place = self.rmw_place(b, *lvalue, store_kind)?; + let place = self.rmw_place(b, *lvalue)?; let old = place.load(b, kind, vol); let stepped = self.increment_value(b, old, *by, *ty); place.store(b, stepped, store_kind, vol); @@ -3139,7 +3201,7 @@ impl<'a> Walker<'a> { let kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lvalue); - let place = self.rmw_place(b, *lvalue, store_kind)?; + let place = self.rmw_place(b, *lvalue)?; let old = place.load(b, kind, vol); let stepped = self.increment_value(b, old, *by, *ty); place.store(b, stepped, store_kind, vol); @@ -3508,18 +3570,15 @@ impl<'a> Walker<'a> { } /// Resolve where a read-modify-write operator targets its lvalue. A - /// non-thread-local `Token::Loc` Ident of integer-class storage width - /// keeps its frame slot so mem2reg can promote it; the float-stored - /// case (`StoreKind::F32`, which the fused `StoreLocal` does not - /// lower) and every non-local lvalue materialize an address through - /// `walk_expr_lvalue`. Mirrors the `Expr::Assign` local-target - /// shortcut so `i++` / `i += k` keep the counter register-resident, - /// not just `i = i + k`. + /// non-thread-local `Token::Loc` Ident keeps its frame slot so + /// mem2reg can promote it; every non-local lvalue materializes an + /// address through `walk_expr_lvalue`. Mirrors the `Expr::Assign` + /// local-target shortcut so `i++` / `i += k` keep the counter + /// register-resident, not just `i = i + k`. fn rmw_place( &mut self, b: &mut super::super::codegen::ssa::build::SsaBuilder, lvalue: ExprId, - store_kind: StoreKind, ) -> Result { // A bitfield member: compute the storage unit's address once so // the read and the write target the same unit (the object is @@ -3542,13 +3601,12 @@ impl<'a> Walker<'a> { }; return Ok(RmwPlace::Bitfield { addr, bf }); } - if !matches!(store_kind, StoreKind::F32) - && let Expr::Ident { - class, - val, - is_thread_local: false, - .. - } = self.ast.expr(lvalue) + if let Expr::Ident { + class, + val, + is_thread_local: false, + .. + } = self.ast.expr(lvalue) && *class == Token::Loc as i64 { return Ok(RmwPlace::Slot(*val)); diff --git a/src/c5/codegen/aarch64/emit.rs b/src/c5/codegen/aarch64/emit.rs index e2398e072..b245bc9bf 100644 --- a/src/c5/codegen/aarch64/emit.rs +++ b/src/c5/codegen/aarch64/emit.rs @@ -54,12 +54,13 @@ use super::encode::{ enc_br, enc_cbnz, enc_cbz, enc_cinc, enc_cmp_reg, enc_cset, enc_eor_reg, enc_fadd_d, enc_fcmp_d, enc_fcmp_s, enc_fcvt_d_s, enc_fcvt_s_d, enc_fcvtzs_x_d, enc_fcvtzu_x_d, enc_fdiv_d, enc_fmov_d_to_x, enc_fmov_w_to_s, enc_fmov_x_to_d, enc_fmul_d, enc_fneg_d, enc_fsub_d, - enc_ldaxr, enc_ldp_post, enc_ldr_d_imm, enc_ldr_imm, enc_ldr_post, enc_ldr_s_imm, - enc_ldr32_imm, enc_ldrb_imm, enc_ldrh_imm, enc_ldrsb_imm, enc_ldrsh_imm, enc_ldrsw_imm, - enc_lslv, enc_lsrv, enc_movz, enc_msub, enc_mul, enc_orr_reg, enc_ret, enc_scvtf_d_x, enc_sdiv, - enc_stlxr, enc_stp_pre, enc_str_d_imm, enc_str_imm, enc_str_pre, enc_str_s_imm, enc_str32_imm, - enc_strb_imm, enc_strh_imm, enc_sub_imm, enc_sub_reg, enc_subs_imm, enc_ucvtf_d_x, enc_udiv, - load_imm64, + enc_ldaxr, enc_ldp_d_off, enc_ldp_d_post, enc_ldp_off, enc_ldp_post, enc_ldr_d_imm, + enc_ldr_d_post, enc_ldr_imm, enc_ldr_post, enc_ldr_s_imm, enc_ldr32_imm, enc_ldrb_imm, + enc_ldrh_imm, enc_ldrsb_imm, enc_ldrsh_imm, enc_ldrsw_imm, enc_ldrsw_reg_lsl2, enc_lslv, + enc_lsrv, enc_movz, enc_msub, enc_mul, enc_orr_reg, enc_ret, enc_scvtf_d_x, enc_sdiv, + enc_stlxr, enc_stp_d_off, enc_stp_d_pre, enc_stp_off, enc_stp_pre, enc_str_d_imm, + enc_str_d_pre, enc_str_imm, enc_str_pre, enc_str_s_imm, enc_str32_imm, enc_strb_imm, + enc_strh_imm, enc_sub_imm, enc_sub_reg, enc_subs_imm, enc_ucvtf_d_x, enc_udiv, load_imm64, }; use super::ssa::emit_common::{build_arg_aggs, place_same_loc}; use super::ssa::reg_alloc::{Allocation, Place}; @@ -667,11 +668,15 @@ pub(crate) fn emit_function( moves.push((Place::IntReg(src), dst)); vids.push(vid); homes.push(dst); - // Sign-extend on entry only when a consumer reads the - // parameter's upper bits; otherwise the low word already - // holds the C99 6.5.2.2p4-converted value. - if matches!(kind, LoadKind::I8 | LoadKind::I16 | LoadKind::I32) - && alloc.high_observed.get(vid).copied().unwrap_or(true) + // The caller passes the raw 64-bit value; the callee + // performs the C99 6.5.2.2p4 conversion. An I8/I16 extend + // rewrites bits 8..63 / 16..63 and is always required; an + // I32 extend touches only bits 32..63 and is skipped when + // no consumer reads them (`high_observed` tracks exactly + // that range). + if matches!(kind, LoadKind::I8 | LoadKind::I16) + || (matches!(kind, LoadKind::I32) + && alloc.high_observed.get(vid).copied().unwrap_or(true)) { exts.push((dst, *kind)); } @@ -764,6 +769,10 @@ pub(crate) fn emit_function( // placeholder; `(site, target_block, rd)` is resolved against the // final `block_offsets` once every block has been laid out. let mut block_addr_fixups: Vec<(usize, BlockId, Reg)> = Vec::new(); + // Text-embedded jump tables: `(table_start, table_idx)` per + // `Terminator::JumpTable`. Each 32-bit entry is patched to + // `block_offset - table_start` once every block is laid out. + let mut jump_table_fixups: Vec<(usize, u32)> = Vec::new(); // Per-function alloca bookkeeping. Set by `Inst::AllocaInit` // and read by `Inst::Intrinsic { kind: Alloca }`; zero // means the function doesn't use alloca. @@ -1121,6 +1130,45 @@ pub(crate) fn emit_function( }; emit(code, enc_br(rt)); } + Terminator::JumpTable { idx, table } => { + // Table dispatch: `adr` the table base (embedded right + // after the `br`, so the +/-1 MiB reach is trivially + // met), load the 32-bit table-relative entry, add, and + // branch. The bounds check preceding this terminator + // proves the index in range. + let iplace = alloc + .places + .get(idx as usize) + .copied() + .unwrap_or(Place::None); + let rt = match materialize_int(code, iplace, scratch.primary, frame) { + Some(r) => r, + None => { + bail("JumpTable: idx Place not int", idx, iplace); + code.truncate(snapshot); + fixups.truncate(fixups_snapshot); + plt_call_fixups.truncate(plt_call_fixups_snapshot); + data_fixups.truncate(data_fixups_snapshot); + user_extern_data_refs.truncate(user_extern_data_refs_snapshot); + pending_func_fixups.truncate(pending_func_fixups_snapshot); + tls_index_fixups.truncate(tls_index_fixups_snapshot); + elf_tpoff_fixups.truncate(elf_tpoff_snapshot); + macho_tlv_fixups.truncate(macho_tlv_fixups_snapshot); + macho_tlv_descriptors.truncate(macho_tlv_descriptors_snapshot); + return false; + } + }; + // rt is an allocated register or scratch.primary, never + // scratch.secondary, so the table base cannot alias it. + let tbl = scratch.secondary; + emit(code, enc_adr(tbl, 16)); + emit(code, enc_ldrsw_reg_lsl2(scratch.primary, tbl, rt)); + emit(code, enc_add_reg(tbl, tbl, scratch.primary)); + emit(code, enc_br(tbl)); + jump_table_fixups.push((code.len(), table)); + let entries = func.jump_tables[table as usize].len(); + code.resize(code.len() + entries * 4, 0); + } Terminator::TailExt(binding_idx) => { // Tail-jump through the GOT-patched trampoline: // `adrp x16, _ ; ldr x16, [x16, _] ; br x16`. @@ -1169,6 +1217,19 @@ pub(crate) fn emit_function( let word = enc_adr(*rd, rel as i32); code[*site..*site + 4].copy_from_slice(&word.to_le_bytes()); } + // Patch each jump table's entries with the target block's offset + // relative to the table base. + for (table_start, table) in &jump_table_fixups { + for (i, &t) in func.jump_tables[*table as usize].iter().enumerate() { + let rel = block_offsets[t as usize] as i64 - *table_start as i64; + debug_assert!( + i32::try_from(rel).is_ok(), + "JumpTable: entry offset out of i32 range" + ); + let site = table_start + i * 4; + code[site..site + 4].copy_from_slice(&(rel as i32).to_le_bytes()); + } + } // Patch the recorded branches. for fx in &branch_fixups { let target_off = block_offsets[fx.target as usize]; @@ -1367,14 +1428,9 @@ fn emit_prologue( emit(code, enc_str_imm(Reg(r), Reg(31), off)); } // Standard frame below the gr-save area. A variadic callee is - // never a full leaf (`param_spill_bytes != 0`), so the - // stp / mov-fp pair always follows. - emit(code, enc_stp_pre(Reg(29), Reg(30), Reg(31), -16)); - emit(code, enc_add_imm(Reg(29), Reg(31), 0)); - if frame.frame_bytes > 0 { - emit_stack_alloc(code, frame.frame_bytes, abi, Reg(16)); - } - emit_prologue_saved_regs(code, alloc, frame); + // never a full leaf (`param_spill_bytes != 0`), so the frame + // record always follows. + emit_frame_and_saves(code, alloc, frame, abi); return; } // AAPCS64 variadic register save area (AAPCS64 Appendix B). Reserve @@ -1410,12 +1466,7 @@ fn emit_prologue( enc_str_d_imm(i as u8, Reg(31), AARCH64_GR_SAVE_BYTES + i * 16), ); } - emit(code, enc_stp_pre(Reg(29), Reg(30), Reg(31), -16)); - emit(code, enc_add_imm(Reg(29), Reg(31), 0)); - if frame.frame_bytes > 0 { - emit_stack_alloc(code, frame.frame_bytes, abi, Reg(16)); - } - emit_prologue_saved_regs(code, alloc, frame); + emit_frame_and_saves(code, alloc, frame, abi); return; } // Host-arg-reg spill for non-variadic functions: spill each @@ -1527,13 +1578,9 @@ fn emit_prologue( if is_full_leaf(func, frame, alloc) { return; } - // Standard frame: stp fp/lr; mov fp, sp; sub sp, sp, frame_bytes. - emit(code, enc_stp_pre(Reg(29), Reg(30), Reg(31), -16)); - emit(code, enc_add_imm(Reg(29), Reg(31), 0)); - if frame.frame_bytes > 0 { - emit_stack_alloc(code, frame.frame_bytes, abi, Reg(16)); - } - emit_prologue_saved_regs(code, alloc, frame); + // Standard frame: frame record, fp, frame allocation, callee + // saves (folded into one pre-indexed group when the frame fits). + emit_frame_and_saves(code, alloc, frame, abi); emit_struct_param_scatter(code, func, abi, frame); if func.indirect_result_slot != 0 { // AAPCS64 6.9: save the caller-supplied x8 indirect-result @@ -1693,29 +1740,200 @@ fn emit_struct_param_scatter( /// Save the allocator-reported callee-saved GPRs + FP regs at the /// bottom of the frame. The saved-reg region sits just above sp; its -/// offsets are one slot per saved register, so the 12-bit scaled -/// immediate (range 0..32760 in multiples of 8) always covers them. The -/// allocator spill region, by contrast, can exceed that reach and is -/// addressed through the range-checked SP helpers. Using `stur` off fp -/// would silently truncate the 9-bit immediate for frames larger than -/// ~256 bytes. x19 is saved just past the allocator-saved gprs, but only -/// when the function clobbers it; the slot is reserved either way so the -/// surrounding offsets stay fixed. -fn emit_prologue_saved_regs(code: &mut Vec, alloc: &Allocation, frame: Frame) { - for (i, &r) in alloc.fp_used.iter().enumerate() { - let off = (i as u32) * 8; - emit(code, enc_str_d_imm(r, Reg(31), off)); +/// offsets are one slot per saved register, so the pair imm7 (scaled by +/// 8, range -512..504) and the 12-bit scaled immediate always cover +/// them. The allocator spill region, by contrast, can exceed that reach +/// and is addressed through the range-checked SP helpers. x19 is saved +/// just past the allocator-saved gprs, but only when the function +/// clobbers it; the slot is reserved either way so the surrounding +/// offsets stay fixed. Adjacent slots within each region save as +/// stp / ldp pairs; a region's odd tail saves alone. +/// +/// When `fold != 0` (see [`frame_fold_bytes`]) the first save carries +/// the whole allocation -- frame plus the fp/lr slot pair -- as a +/// pre-indexed store of `-fold` bytes, replacing the prologue's +/// `stp x29, x30, [sp, #-16]!` / `sub sp` pair; the first save always +/// targets offset 0, so every other offset is unchanged. +fn emit_prologue_saved_regs(code: &mut Vec, alloc: &Allocation, frame: Frame, fold: u32) { + let mut alloc_pending = fold != 0; + let fp = &alloc.fp_used; + let mut i = 0usize; + while i + 1 < fp.len() { + if core::mem::take(&mut alloc_pending) { + emit( + code, + enc_stp_d_pre(fp[i], fp[i + 1], Reg(31), -(fold as i32)), + ); + } else { + emit( + code, + enc_stp_d_off(fp[i], fp[i + 1], Reg(31), (i as i32) * 8), + ); + } + i += 2; + } + if i < fp.len() { + if core::mem::take(&mut alloc_pending) { + emit(code, enc_str_d_pre(fp[i], Reg(31), -(fold as i32))); + } else { + emit(code, enc_str_d_imm(fp[i], Reg(31), (i as u32) * 8)); + } + } + let saved_fpr_bytes = super::ssa::emit_common::slots16(fp.len() as u32); + let gpr = &alloc.gpr_used; + let mut i = 0usize; + while i + 1 < gpr.len() { + let off = (saved_fpr_bytes + (i as u32) * 8) as i32; + if core::mem::take(&mut alloc_pending) { + emit( + code, + enc_stp_pre(Reg(gpr[i]), Reg(gpr[i + 1]), Reg(31), -(fold as i32)), + ); + } else { + emit( + code, + enc_stp_off(Reg(gpr[i]), Reg(gpr[i + 1]), Reg(31), off), + ); + } + i += 2; + } + if i < gpr.len() { + if core::mem::take(&mut alloc_pending) { + emit(code, enc_str_pre(Reg(gpr[i]), Reg(31), -(fold as i32))); + } else { + let off = saved_fpr_bytes + (i as u32) * 8; + emit(code, enc_str_imm(Reg(gpr[i]), Reg(31), off)); + } } + if frame.uses_x19 { + if core::mem::take(&mut alloc_pending) { + emit(code, enc_str_pre(Reg(19), Reg(31), -(fold as i32))); + } else { + let saved_gpr_bytes = super::ssa::emit_common::slots16(gpr.len() as u32); + emit( + code, + enc_str_imm(Reg(19), Reg(31), saved_fpr_bytes + saved_gpr_bytes), + ); + } + } + debug_assert!(!alloc_pending, "frame fold requested with no callee save"); +} + +/// Restore what [`emit_prologue_saved_regs`] saved, in mirror order +/// (x19, gprs descending, fp regs descending) so the offset-0 access +/// comes last and, when `fold != 0`, tears the frame down as a +/// post-indexed load of `fold` bytes, replacing the epilogue's +/// `add sp` and the fp/lr `ldp`. `fold` is the total writeback +/// (frame plus the fp/lr pair), or 0 for the unfolded shape. +fn emit_epilogue_restore_regs(code: &mut Vec, alloc: &Allocation, frame: Frame, fold: u32) { let saved_fpr_bytes = super::ssa::emit_common::slots16(alloc.fp_used.len() as u32); - for (i, &r) in alloc.gpr_used.iter().enumerate() { + let gpr = &alloc.gpr_used; + if frame.uses_x19 { + let saved_gpr_bytes = super::ssa::emit_common::slots16(gpr.len() as u32); + let off = saved_fpr_bytes + saved_gpr_bytes; + if off == 0 && fold != 0 { + emit(code, enc_ldr_post(Reg(19), Reg(31), fold as i32)); + } else { + emit(code, enc_ldr_imm(Reg(19), Reg(31), off)); + } + } + let mut i = gpr.len(); + if i % 2 == 1 { + i -= 1; let off = saved_fpr_bytes + (i as u32) * 8; - emit(code, enc_str_imm(Reg(r), Reg(31), off)); + if off == 0 && fold != 0 { + emit(code, enc_ldr_post(Reg(gpr[i]), Reg(31), fold as i32)); + } else { + emit(code, enc_ldr_imm(Reg(gpr[i]), Reg(31), off)); + } } - if frame.uses_x19 { - let saved_gpr_bytes = super::ssa::emit_common::slots16(alloc.gpr_used.len() as u32); - let x19_save_off = saved_fpr_bytes + saved_gpr_bytes; - emit(code, enc_str_imm(Reg(19), Reg(31), x19_save_off)); + while i >= 2 { + i -= 2; + let off = (saved_fpr_bytes + (i as u32) * 8) as i32; + if off == 0 && fold != 0 { + emit( + code, + enc_ldp_post(Reg(gpr[i]), Reg(gpr[i + 1]), Reg(31), fold as i32), + ); + } else { + emit( + code, + enc_ldp_off(Reg(gpr[i]), Reg(gpr[i + 1]), Reg(31), off), + ); + } + } + let fp = &alloc.fp_used; + let mut i = fp.len(); + if i % 2 == 1 { + i -= 1; + if i == 0 && fold != 0 { + emit(code, enc_ldr_d_post(fp[i], Reg(31), fold as i32)); + } else { + emit(code, enc_ldr_d_imm(fp[i], Reg(31), (i as u32) * 8)); + } + } + while i >= 2 { + i -= 2; + if i == 0 && fold != 0 { + emit(code, enc_ldp_d_post(fp[i], fp[i + 1], Reg(31), fold as i32)); + } else { + emit( + code, + enc_ldp_d_off(fp[i], fp[i + 1], Reg(31), (i as i32) * 8), + ); + } + } +} + +/// Frame bytes the folded prologue / epilogue shape can carry, or 0 +/// when the fold does not apply. The folded shape extends the frame by +/// the 16-byte fp/lr slot pair at its top: the first callee save +/// pre-indexes `-(frame_bytes + 16)`, fp/lr store / load through the +/// signed-offset pair form at `[sp, #frame_bytes]`, and the last +/// restore post-indexes the whole amount back. All three must fit +/// their immediates: the scaled imm7 pair forms reach +-504/512, so a +/// pair-first frame folds up to 488 (16-aligned: 480); a single-register +/// bottom save uses the unscaled imm9 (+-255) and folds up to 224. +/// Both sides compute the fold from the same inputs so they agree. +fn frame_fold_bytes(alloc: &Allocation, frame: Frame) -> u32 { + let n_bottom = if !alloc.fp_used.is_empty() { + alloc.fp_used.len() + } else if !alloc.gpr_used.is_empty() { + alloc.gpr_used.len() + } else if frame.uses_x19 { + 1 + } else { + return 0; + }; + debug_assert!(frame.frame_bytes >= 16, "saves imply a non-empty frame"); + let limit = if n_bottom >= 2 { 480 } else { 224 }; + if frame.frame_bytes <= limit { + frame.frame_bytes + } else { + 0 + } +} + +/// Establish the frame record and fp, allocate the frame, and save the +/// callee-saved registers. The folded shape allocates everything with +/// the first callee save's pre-index and keeps fp and every offset +/// identical to the unfolded `stp fp/lr; mov fp, sp; sub sp` shape; +/// fp/lr restore first in the epilogue, so the `ret`-feeding lr load +/// issues off an address that depends on no other restore. +fn emit_frame_and_saves(code: &mut Vec, alloc: &Allocation, frame: Frame, abi: super::Abi) { + let fold = frame_fold_bytes(alloc, frame); + if fold != 0 { + emit_prologue_saved_regs(code, alloc, frame, fold + 16); + emit(code, enc_stp_off(Reg(29), Reg(30), Reg(31), fold as i32)); + emit(code, enc_add_imm(Reg(29), Reg(31), fold)); + return; + } + emit(code, enc_stp_pre(Reg(29), Reg(30), Reg(31), -16)); + emit(code, enc_add_imm(Reg(29), Reg(31), 0)); + if frame.frame_bytes > 0 { + emit_stack_alloc(code, frame.frame_bytes, abi, Reg(16)); } + emit_prologue_saved_regs(code, alloc, frame, 0); } /// Byte offset (positive) from fp to the start of the saved-reg @@ -1912,16 +2130,16 @@ fn emit_inst( }; // The encoding to write `dst <- sign-extend(arg_reg)`. // For full-width kinds (I64), it is a plain mov. The - // sign-extension is skipped when no consumer reads the - // parameter's upper bits. + // caller passes the raw 64-bit value, so an I8/I16 + // conversion always runs; an I32 extend touches only + // bits 32..63 and is skipped when no consumer reads them. let high_dead = !alloc.high_observed.get(v as usize).copied().unwrap_or(true); let sign_extend = |code: &mut Vec, rd: Reg| { let rn = Reg(arg_reg); match kind { - _ if high_dead => emit_mov_reg(code, rd, rn), LoadKind::I8 => emit(code, super::encode::enc_sxtb(rd, rn)), LoadKind::I16 => emit(code, super::encode::enc_sxth(rd, rn)), - LoadKind::I32 => emit(code, super::encode::enc_sxtw(rd, rn)), + LoadKind::I32 if !high_dead => emit(code, super::encode::enc_sxtw(rd, rn)), _ => emit_mov_reg(code, rd, rn), } }; @@ -3864,13 +4082,10 @@ fn move_call_result(code: &mut Vec, dst: Place, frame: Frame, fp_return: boo } } -/// Indirect call through a function-pointer value. Mirrors the -/// pool path's indirect-call lowering: marshal args per the host -/// ABI, capture the target into a callee-overwritable scratch -/// register that arg marshalling won't clobber, `blr`, recover -/// the return value. -/// FP args and variadic indirect callees aren't part of the thin -/// slice; either case returns false. +/// Indirect call through a function-pointer value: marshal args per +/// the host ABI, capture the target into a callee-overwritable +/// scratch register that arg marshalling won't clobber, `blr`, +/// recover the return value. #[allow(clippy::too_many_arguments)] fn emit_call_indirect( code: &mut Vec, @@ -3922,173 +4137,84 @@ fn emit_call_indirect( .copied() .find(|r| !arg_source_regs.contains(r)) .map(Reg); - if (callee_variadic - && (abi.variadic_on_stack || abi.variadic_int_only || abi.aarch64_host_variadic())) - || !aggs.is_empty() - || ret_agg.is_some() - { - // Host ABI through a function pointer, taken for a host - // variadic callee or any call passing an aggregate by value - // (aggregates are placed by `marshal_args`, which the - // c5-stack push path below does not handle): the named - // arguments follow AAPCS64 (int / FP bank) and the variadic tail - // rides the host stack at 8-byte stride (macOS, - // `variadic_on_stack`), the integer register bank then the - // stack (Windows arm64, `variadic_int_only`), or both banks then - // the stack (Linux aarch64, `aarch64_host_variadic`) -- the same - // placement `emit_call` uses for a direct variadic call. The - // target pointer rides a non-arg-passing scratch that - // `marshal_args` will not clobber, or a reserved stack cell - // above the argument slots when no such scratch is free. - let mut plan = - super::plan_call_args_aggs(args.len(), fixed_args, fp_arg_mask, abi, &aggs, false); - let staged_off = match free_target_reg { - Some(_) => None, - None => { - // One 16-byte cell keeps SP 16-aligned; the argument - // slots stay below the original scratch_bytes. - plan.scratch_bytes += 16; - Some(plan.scratch_bytes - 16) - } - }; - let target_r = match materialize_int(code, target_place, scratch.primary, frame) { - Some(r) => r, - None => return false, - }; - let target_reg = match free_target_reg { - Some(r) => { - if target_r.0 != r.0 { - emit_mov_reg(code, r, target_r); - } - r - } - None => { - if target_r.0 != scratch.primary.0 { - emit_mov_reg(code, scratch.primary, target_r); - } - scratch.primary - } - }; - emit_sub_sp_imm(code, plan.scratch_bytes); - if let Some(off) = staged_off { - emit_sp_str_x_auto(code, target_reg, off); - } - if !marshal_args( - code, &plan, args, alloc, scratch, frame, arg_aggs, agg_descs, - ) { - return false; + // Host ABI through a function pointer, for variadic and + // non-variadic callees alike: `marshal_args` places the named + // arguments per AAPCS64 (int / FP bank, overflow on the host + // stack) and a variadic tail per the target's host variadic + // placement (`variadic_on_stack` on macOS, `variadic_int_only` + // on Windows arm64, both banks then the stack on Linux + // aarch64) -- the same placement `emit_call` uses for a direct + // call. A non-variadic call plans every argument as fixed, + // mirroring the direct path; the walker lowers an unrecoverable + // prototype as all-fixed non-variadic, which this placement + // serves. The target pointer rides a non-arg-passing scratch + // that `marshal_args` will not clobber, or a reserved stack + // cell above the argument slots when no such scratch is free. + let plan_fixed = if callee_variadic { + fixed_args + } else { + args.len() + }; + let mut plan = + super::plan_call_args_aggs(args.len(), plan_fixed, fp_arg_mask, abi, &aggs, false); + let staged_off = match free_target_reg { + Some(_) => None, + None => { + // One 16-byte cell keeps SP 16-aligned; the argument + // slots stay below the original scratch_bytes. + plan.scratch_bytes += 16; + Some(plan.scratch_bytes - 16) } - setup_indirect_result(code, ret_agg, ret_slot_off, agg_descs, frame); - // The marshal consumed every argument source, so x9 is free - // to carry the staged pointer to the blr. - let call_reg = match staged_off { - Some(off) => { - emit_sp_ldr_x(code, Reg(9), off); - Reg(9) - } - None => target_reg, - }; - emit(code, enc_blr(call_reg)); - emit_add_sp_imm(code, plan.scratch_bytes); - finish_call_result( - code, - ret_agg, - ret_slot_off, - agg_descs, - dst, - frame, - scratch, - fp_return, - ); - return true; - } - // Indirect calls keep the c5-stack push shape regardless of - // whether the callee is variadic. Variadic c5 callees read - // their args off the 16-byte-stride stack (their prologue - // skips the host-arg-reg spill); non-variadic callees pull - // their args from x0..x7 + host stack overflow, ignoring the - // c5 stack pushes. Mirroring the pool path's indirect-call - // shape -- push every arg first, then load the prefix into - // host arg regs, then blr -- handles both at the indirect - // call site without needing the callee's variadic flag. - // `fp_arg_mask` is supplied by the caller from the argument types; - // the reload loop below routes each masked argument into its - // d-register per the plan. - for (i, &arg_id) in args.iter().rev().enumerate() { - let arg_place = alloc - .places - .get(arg_id as usize) - .copied() - .unwrap_or(Place::None); - let sp_shift = (i as u32) * 16; - let src = if let Place::FpReg(_) = arg_place { - // FP value: load into d-reg, then move bit pattern - // into x16 for the 16-byte stride push. - let dn = match materialize_fp_shifted(code, arg_place, 0, frame, sp_shift) { - Some(r) => r, - None => return false, - }; - emit(code, enc_fmov_d_to_x(scratch.primary, dn)); - scratch.primary - } else { - match materialize_int_shifted(code, arg_place, scratch.primary, frame, sp_shift) { - Some(r) => r, - None => return false, - } - }; - emit(code, enc_str_pre(src, Reg(31), -16)); - } - let pushed_bytes = (args.len() as u32) * 16; - // The pushes consumed every argument source, so x9 holds no live - // value; capture the pointer here, with SP shifted by the pushes. - let target_reg = Reg(9); - let target_r = - match materialize_int_shifted(code, target_place, target_reg, frame, pushed_bytes) { - Some(r) => r, - None => return false, - }; - if target_r.0 != target_reg.0 { - emit_mov_reg(code, target_reg, target_r); - } - // Load the prefix into host arg regs from the c5-stride - // stack we just laid down. Non-variadic callees expect this - // shape; variadic callees ignore the host arg regs but read - // the same slots through the address-of-local path. Stack - // overflow (args - // past 8) stays on the c5 stack at `[sp + i*16]`, which the - // callee prologue's overflow restripe loop also reads from. - let plan = super::plan_call_args_aggs(args.len(), args.len(), fp_arg_mask, abi, &aggs, false); - emit_sub_sp_imm(code, plan.scratch_bytes); - for (i, &placement) in plan.placements.iter().enumerate() { - match placement { - super::ArgPlacement::IntReg(r) => { - let src_off = plan.scratch_bytes + (i as u32) * 16; - emit(code, enc_ldr_imm(Reg(r), Reg(31), src_off)); - } - super::ArgPlacement::FpReg(r) => { - let src_off = plan.scratch_bytes + (i as u32) * 16; - emit(code, enc_ldr_d_imm(r, Reg(31), src_off)); - } - super::ArgPlacement::Stack(off) => { - let src_off = plan.scratch_bytes + (i as u32) * 16; - emit(code, enc_ldr_imm(scratch.primary, Reg(31), src_off)); - emit(code, enc_str_imm(scratch.primary, Reg(31), off)); + }; + let target_r = match materialize_int(code, target_place, scratch.primary, frame) { + Some(r) => r, + None => return false, + }; + let target_reg = match free_target_reg { + Some(r) => { + if target_r.0 != r.0 { + emit_mov_reg(code, r, target_r); } - // This path plans with the scalar `plan_call_args`, so - // aggregate placements never occur here. - super::ArgPlacement::StructRegs { .. } - | super::ArgPlacement::StructByRefReg(_) - | super::ArgPlacement::StructByRefStack(_) - | super::ArgPlacement::StructStack { .. } => { - unreachable!("aggregate arg placement on the scalar indirect path") + r + } + None => { + if target_r.0 != scratch.primary.0 { + emit_mov_reg(code, scratch.primary, target_r); } + scratch.primary } + }; + emit_sub_sp_imm(code, plan.scratch_bytes); + if let Some(off) = staged_off { + emit_sp_str_x_auto(code, target_reg, off); } - emit(code, enc_blr(target_reg)); + if !marshal_args( + code, &plan, args, alloc, scratch, frame, arg_aggs, agg_descs, + ) { + return false; + } + setup_indirect_result(code, ret_agg, ret_slot_off, agg_descs, frame); + // The marshal consumed every argument source, so x9 is free + // to carry the staged pointer to the blr. + let call_reg = match staged_off { + Some(off) => { + emit_sp_ldr_x(code, Reg(9), off); + Reg(9) + } + None => target_reg, + }; + emit(code, enc_blr(call_reg)); emit_add_sp_imm(code, plan.scratch_bytes); - // Drop the 16-byte-stride argument pushes. - emit_add_sp_imm(code, pushed_bytes); - move_call_result(code, dst, frame, fp_return); + finish_call_result( + code, + ret_agg, + ret_slot_off, + agg_descs, + dst, + frame, + scratch, + fp_return, + ); true } @@ -6565,28 +6691,6 @@ fn emit_return( emit_mov_reg(code, Reg(0), src); } } - // Restore saved callee-saved GPRs + FP regs (mirror of - // prologue). Addressing through sp uses `enc_ldr_imm`'s - // 12-bit scaled immediate (range 0..32760 in multiples of - // 8); the matching prologue uses `enc_str_imm` at the same - // offsets. - let saved_fpr_bytes = super::ssa::emit_common::slots16(alloc.fp_used.len() as u32); - for (i, &r) in alloc.gpr_used.iter().enumerate() { - let off = saved_fpr_bytes + (i as u32) * 8; - emit(code, enc_ldr_imm(Reg(r), Reg(31), off)); - } - for (i, &r) in alloc.fp_used.iter().enumerate() { - let off = (i as u32) * 8; - emit(code, enc_ldr_d_imm(r, Reg(31), off)); - } - // Restore x19 from the dedicated slot above the allocator saves; - // mirror of the prologue's save, emitted only when the function - // clobbers x19. - if frame.uses_x19 { - let saved_gpr_bytes = super::ssa::emit_common::slots16(alloc.gpr_used.len() as u32); - let x19_save_off = saved_fpr_bytes + saved_gpr_bytes; - emit(code, enc_ldr_imm(Reg(19), Reg(31), x19_save_off)); - } // Leaf-function elision: prologue emitted no save, so the // epilogue emits no matching restore -- the function body is // bracketed only by the return-value materialization and the @@ -6596,11 +6700,22 @@ fn emit_return( emit(code, enc_ret(Reg(30))); return; } - // Tear down the frame. - if frame.frame_bytes > 0 { - emit_add_sp_imm(code, frame.frame_bytes); + // Restore fp/lr first in the folded shape (the lr load feeds `ret`, + // so it issues off sp before the writeback chain), then x19 and the + // callee-saved GPRs / FP regs in mirror order of the prologue's + // saves; the final restore's post-index tears the frame down. The + // unfolded shape keeps the restore / `add sp` / fp-lr `ldp` order. + let fold = frame_fold_bytes(alloc, frame); + if fold != 0 { + emit(code, enc_ldp_off(Reg(29), Reg(30), Reg(31), fold as i32)); + emit_epilogue_restore_regs(code, alloc, frame, fold + 16); + } else { + emit_epilogue_restore_regs(code, alloc, frame, 0); + if frame.frame_bytes > 0 { + emit_add_sp_imm(code, frame.frame_bytes); + } + emit(code, enc_ldp_post(Reg(29), Reg(30), Reg(31), 16)); } - emit(code, enc_ldp_post(Reg(29), Reg(30), Reg(31), 16)); // Drop whatever bytes the prologue allocated above the saved // fp/lr for c5 cdecl parameter slots. The single source of // truth is `prologue_param_spill_bytes`, recorded on diff --git a/src/c5/codegen/aarch64/encode.rs b/src/c5/codegen/aarch64/encode.rs index 89e478f14..e1ccccfda 100644 --- a/src/c5/codegen/aarch64/encode.rs +++ b/src/c5/codegen/aarch64/encode.rs @@ -204,6 +204,66 @@ pub(crate) fn enc_ldp_off(rt: Reg, rt2: Reg, rn: Reg, imm: i32) -> u32 { | (rt.0 as u32) } +/// Shared field packer for the LDP / STP (SIMD&FP, 64-bit) forms below. +/// `imm` scales by 8 into the imm7 field, same as the X-register forms. +fn enc_ldst_pair_d(base: u32, dt: u8, dt2: u8, rn: Reg, imm: i32) -> u32 { + debug_assert!(dt < 32 && dt2 < 32); + debug_assert!(imm % 8 == 0, "ldp/stp d: imm must be 8-byte aligned"); + let imm7 = imm / 8; + debug_assert!( + (-64..64).contains(&imm7), + "ldp/stp d: offset {imm} (scaled {imm7}) out of range" + ); + base | (((imm7 as u32) & 0x7F) << 15) + | ((dt2 as u32) << 10) + | ((rn.0 as u32) << 5) + | (dt as u32) +} + +/// `STP , , [, #imm]` -- store-pair, signed offset. +pub(crate) fn enc_stp_d_off(dt: u8, dt2: u8, rn: Reg, imm: i32) -> u32 { + enc_ldst_pair_d(0x6D00_0000, dt, dt2, rn, imm) +} + +/// `LDP , , [, #imm]` -- load-pair, signed offset. +pub(crate) fn enc_ldp_d_off(dt: u8, dt2: u8, rn: Reg, imm: i32) -> u32 { + enc_ldst_pair_d(0x6D40_0000, dt, dt2, rn, imm) +} + +/// `STP , , [, #imm]!` -- store-pair, pre-indexed. +pub(crate) fn enc_stp_d_pre(dt: u8, dt2: u8, rn: Reg, imm: i32) -> u32 { + enc_ldst_pair_d(0x6D80_0000, dt, dt2, rn, imm) +} + +/// `LDP , , [], #imm` -- load-pair, post-indexed. +pub(crate) fn enc_ldp_d_post(dt: u8, dt2: u8, rn: Reg, imm: i32) -> u32 { + enc_ldst_pair_d(0x6CC0_0000, dt, dt2, rn, imm) +} + +/// `STR
, [, #imm]!` -- pre-indexed store with writeback +/// (unscaled imm9). D-register mirror of [`enc_str_pre`]. +pub(crate) fn enc_str_d_pre(dt: u8, rn: Reg, imm: i32) -> u32 { + debug_assert!(dt < 32); + debug_assert!( + (-256..256).contains(&imm), + "str-d-pre imm: {imm} out of range" + ); + let imm9 = (imm as u32) & 0x1FF; + 0xFC00_0C00 | (imm9 << 12) | ((rn.0 as u32) << 5) | (dt as u32) +} + +/// `LDR
, [], #imm` -- post-indexed load with writeback +/// (unscaled imm9). D-register mirror of [`enc_ldr_post`]. +pub(crate) fn enc_ldr_d_post(dt: u8, rn: Reg, imm: i32) -> u32 { + debug_assert!(dt < 32); + debug_assert!( + (-256..256).contains(&imm), + "ldr-d-post imm: {imm} out of range" + ); + let imm9 = (imm as u32) & 0x1FF; + 0xFC40_0400 | (imm9 << 12) | ((rn.0 as u32) << 5) | (dt as u32) +} + /// `MOV , ` -- alias for `ORR , XZR, `. Note that ARM /// uses two distinct mov forms: this one (register-to-register, where /// `Rn` field 31 means XZR) and `add xd, sp, #0` (which is what you @@ -1517,6 +1577,12 @@ pub(crate) fn lower( } } }); + // Unroll constant-trip loops before the inliner so a helper + // whose body was a short loop becomes a single-block inline + // candidate; see x86_64.rs's matching block for the rationale. + super::ssa::emit_common::time_pass("passes::unroll::run (aarch64)", || { + crate::c5::codegen::passes::unroll::run(&mut ssa_funcs); + }); // Inline after mem2reg; see x86_64.rs's matching block for // the ordering rationale. super::ssa::emit_common::time_pass("passes::inline::run (aarch64)", || { @@ -1531,6 +1597,29 @@ pub(crate) fn lower( super::ssa::emit_common::time_pass("passes::struct_return_reg::run (aarch64)", || { crate::c5::codegen::passes::struct_return_reg::run(&mut ssa_funcs); }); + // Constant folding over the post-inline tape; see x86_64.rs's + // matching block for the rationale. + super::ssa::emit_common::time_pass("passes::constfold::run (aarch64)", || { + crate::c5::codegen::passes::constfold::run(&mut ssa_funcs); + }); + // Split constant-index local arrays that unrolling exposed into + // per-element slots and re-run mem2reg to promote them to SSA + // values. Gated to functions the unroll pass expanded so the + // mem2reg rebuild is confined; see x86_64.rs's matching block. + super::ssa::emit_common::time_pass("passes::sroa::run (aarch64)", || { + let usable_gpr = super::ssa::reg_alloc::usable_gpr_count(target); + for f in &mut ssa_funcs { + if f.did_unroll { + let promoted = crate::c5::codegen::passes::sroa::run(f, usable_gpr); + if !promoted.is_empty() { + promoted_local_slots + .entry(f.ent_pc) + .or_default() + .extend(promoted); + } + } + } + }); super::ssa::emit_common::time_pass("passes::rotate::run (aarch64)", || { crate::c5::codegen::passes::rotate::run(&mut ssa_funcs); }); @@ -1567,6 +1656,13 @@ pub(crate) fn lower( super::ssa::emit_common::time_pass("passes::store_forward::run (aarch64)", || { crate::c5::codegen::passes::store_forward::run(&mut ssa_funcs); }); + // Block layout: fallthrough chains, loop rotation to + // bottom-test, branch inversion. Reorders blocks and remaps + // block ids only, so it runs last; the emit elides jumps to + // the next block in the new order. + super::ssa::emit_common::time_pass("passes::layout::run (aarch64)", || { + crate::c5::codegen::passes::layout::run(&mut ssa_funcs); + }); } // Upper bound on ent_pcs the lowering will reference. The // walker stamps `ent_pc` / `end_pc` against the ent_pc diff --git a/src/c5/codegen/passes/constfold.rs b/src/c5/codegen/passes/constfold.rs new file mode 100644 index 000000000..6eb8273cc --- /dev/null +++ b/src/c5/codegen/passes/constfold.rs @@ -0,0 +1,566 @@ +//! Post-inline constant folding. The inliner substitutes call-site +//! immediates into callee bodies and materialises callee-narrows +//! extends on them (`splice_param_ref`), leaving `Extend(Imm)` / +//! `Binop(Imm, Imm)` / `BinopI(Imm, k)` chains no earlier stage +//! re-folds. Folding them lets the downstream matchers (`rotate`'s +//! constant-count arm, `constfold_branch`, the immediate-form +//! encoders) see plain `Inst::Imm` / `Inst::BinopI` shapes. +//! +//! Rewrites, in-place to a bounded fixed point: +//! * `Extend { Imm }` -> `Imm` (sign-extended per kind); +//! * `BinopI { int op, Imm lhs, k }` -> `Imm`; +//! * `Binop { int op, Imm, Imm }` -> `Imm`; +//! * `Binop { rhs = Imm }` -> `BinopI` for [`binopi_safe`] ops when +//! the immediate encodes without a per-use scratch +//! materialisation or the `Imm` def has no other use; +//! * `Binop { lhs = Imm }` -> the rhs-imm form via commutation or +//! compare mirroring, then the rule above. +//! +//! Only a plain integer `Inst::Imm` whose `f32_values` flag is clear +//! participates: `ImmData` / `ImmCode` / `ImmExtCode` / `BlockAddr` / +//! `TlsAddr` / `LocalAddr` resolve to addresses at emit time, and an +//! f32 `Imm` carries the low-32 bit pattern in the IR while the +//! evaluator's register convention is f64-widened. Division the +//! evaluator computes but native code traps on (`/ 0`, +//! `i64::MIN / -1`) is refused by `eval::fold_binop`, so folding +//! never changes runtime behavior. +//! +//! Blocks and terminators are untouched and every rewrite is +//! in-place, so `inst_src` / `f32_values` stay parallel. Operand +//! `Imm`s made dead are reaped by the emit's use-count DCE. + +use crate::c5::codegen::ssa::reg_alloc::for_each_operand; +use crate::c5::ir::{BinOp, FunctionSsa, Inst, NO_VALUE, Terminator, ValueId}; +use crate::c5::vm::eval; +use alloc::vec; +use alloc::vec::Vec; + +pub(crate) fn run(funcs: &mut [FunctionSsa]) { + for func in funcs { + run_one(func); + } +} + +/// Bound on fold rounds. A round resolves every chain whose defs +/// precede their uses on the inst tape; further rounds only pick up +/// cross-block back-references, which converge in practice within +/// two. +const MAX_ROUNDS: usize = 4; + +fn run_one(func: &mut FunctionSsa) { + for _ in 0..MAX_ROUNDS { + if !fold_round(func) { + return; + } + } +} + +/// Ops both per-arch emitters lower in `BinopI` form. The x86_64 +/// `emit_binop_imm` panics on Div / Divu / Mod / Modu; the aarch64 +/// one bails on Mod / Modu (no third scratch register). FP ops keep +/// register operands. Everything else has an immediate-form arm in +/// both emitters. +fn binopi_safe(op: BinOp) -> bool { + matches!( + op, + BinOp::Add + | BinOp::Sub + | BinOp::Mul + | BinOp::And + | BinOp::Or + | BinOp::Xor + | BinOp::Shl + | BinOp::Shr + | BinOp::Shru + | BinOp::Ror + | BinOp::Eq + | BinOp::Ne + | BinOp::Lt + | BinOp::Gt + | BinOp::Le + | BinOp::Ge + | BinOp::Ult + | BinOp::Ugt + | BinOp::Ule + | BinOp::Uge + ) +} + +/// Whether `op` with immediate `imm` encodes in both per-arch +/// emitters without a per-use scratch materialisation of the +/// immediate. Derived from the two `emit_binop_imm` peephole sets: +/// shifts embed a 6-bit count, add/sub take imm12 (aarch64) / imm32 +/// (x86_64), compares cmp-imm12 / cmp-imm32, mul lowers to a +/// shift-by-log2; `And 0xffffffff` and `Xor -1` have dedicated +/// single-instruction forms. Anything else loads the immediate into +/// a scratch register at every use, so rewriting a shared immediate +/// operand would duplicate its materialisation. +fn imm_encodes_free(op: BinOp, imm: i64) -> bool { + match op { + BinOp::Shl | BinOp::Shr | BinOp::Shru | BinOp::Ror => (0..64).contains(&imm), + BinOp::Add | BinOp::Sub => imm.unsigned_abs() < 4096, + BinOp::Mul => imm > 0 && (imm as u64).is_power_of_two(), + BinOp::And => imm == 0xffff_ffff, + BinOp::Xor => imm == -1, + BinOp::Eq + | BinOp::Ne + | BinOp::Lt + | BinOp::Gt + | BinOp::Le + | BinOp::Ge + | BinOp::Ult + | BinOp::Ugt + | BinOp::Ule + | BinOp::Uge => (0..4096).contains(&imm), + _ => false, + } +} + +/// `imm OP x` recast as `x OP' imm`: the op itself for commutative +/// ops, the mirrored comparison for ordered compares. `None` for the +/// non-commutative rest (Sub, shifts, division, FP). +fn mirror(op: BinOp) -> Option { + Some(match op { + BinOp::Add | BinOp::Mul | BinOp::And | BinOp::Or | BinOp::Xor | BinOp::Eq | BinOp::Ne => op, + BinOp::Lt => BinOp::Gt, + BinOp::Gt => BinOp::Lt, + BinOp::Le => BinOp::Ge, + BinOp::Ge => BinOp::Le, + BinOp::Ult => BinOp::Ugt, + BinOp::Ugt => BinOp::Ult, + BinOp::Ule => BinOp::Uge, + BinOp::Uge => BinOp::Ule, + _ => return None, + }) +} + +/// Resolve `v` to its integer constant when its def is a plain +/// `Inst::Imm` not flagged f32. Out-of-range ids (`NO_VALUE`) and +/// address-bearing immediates resolve to `None`. +fn imm_of(func: &FunctionSsa, v: ValueId) -> Option { + let i = v as usize; + match func.insts.get(i)? { + Inst::Imm(k) if !matches!(func.f32_values.get(i), Some(true)) => Some(*k), + _ => None, + } +} + +/// Operand-reference counts, including terminator conditions and the +/// per-block `exit_acc`. Counts taken at round start over-approximate +/// after in-round rewrites drop references, which only defers a +/// single-use rewrite to the next round. +fn count_uses(func: &FunctionSsa) -> Vec { + let n = func.insts.len(); + let mut counts = vec![0u32; n]; + let bump = |counts: &mut Vec, v: ValueId| { + if v != NO_VALUE && (v as usize) < n { + counts[v as usize] += 1; + } + }; + for inst in &func.insts { + for_each_operand(inst, |op| bump(&mut counts, op)); + if let Inst::CallIndirect { target, .. } = inst { + bump(&mut counts, *target); + } + } + for block in &func.blocks { + match block.terminator { + Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => bump(&mut counts, cond), + Terminator::Return(v) => bump(&mut counts, v), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + bump(&mut counts, target) + } + _ => {} + } + bump(&mut counts, block.exit_acc); + } + counts +} + +fn fold_round(func: &mut FunctionSsa) -> bool { + let uses = count_uses(func); + // A shared immediate operand only moves into the instruction when + // the encoding is materialisation-free; a sole use may always + // move (the per-use materialisation replaces the def's). + let to_imm_form = |op: BinOp, value_id: ValueId, imm: i64| -> bool { + binopi_safe(op) + && (imm_encodes_free(op, imm) || uses.get(value_id as usize).copied().unwrap_or(0) == 1) + }; + let mut changed = false; + for idx in 0..func.insts.len() { + if matches!(func.f32_values.get(idx), Some(true)) { + continue; + } + let new_inst = match &func.insts[idx] { + Inst::Extend { value, kind } => { + imm_of(func, *value).map(|k| Inst::Imm(eval::eval_extend(k, *kind))) + } + Inst::BinopI { op, lhs, rhs_imm } => imm_of(func, *lhs) + .and_then(|l| eval::fold_binop(*op, l, *rhs_imm)) + .map(Inst::Imm), + Inst::Binop { op, lhs, rhs } => match (imm_of(func, *lhs), imm_of(func, *rhs)) { + (Some(l), Some(r)) => eval::fold_binop(*op, l, r).map(Inst::Imm), + (None, Some(r)) if to_imm_form(*op, *rhs, r) => Some(Inst::BinopI { + op: *op, + lhs: *lhs, + rhs_imm: r, + }), + (Some(l), None) => { + mirror(*op) + .filter(|m| to_imm_form(*m, *lhs, l)) + .map(|m| Inst::BinopI { + op: m, + lhs: *rhs, + rhs_imm: l, + }) + } + _ => None, + }, + _ => None, + }; + if let Some(inst) = new_inst { + func.insts[idx] = inst; + changed = true; + } + } + changed +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::c5::ir::{Block, LoadKind, Terminator}; + use alloc::vec; + use alloc::vec::Vec; + + fn fresh(insts: Vec) -> FunctionSsa { + let n = insts.len(); + FunctionSsa { + name: alloc::string::String::new(), + ent_pc: 0, + end_pc: 0, + locals: 0, + has_returns_twice_call: false, + did_unroll: false, + n_params: 0, + is_variadic: false, + is_inline: false, + inst_src: vec![(0, 0); n], + f32_values: vec![false; n], + param_fp_mask: 0, + agg_descs: Vec::new(), + param_aggs: Vec::new(), + param_local_slots: Vec::new(), + ret_agg: None, + ret_is_fp: false, + indirect_result_slot: 0, + computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), + synthetic_base: 0, + multi_cell_slots: Vec::new(), + insts, + blocks: vec![Block { + start_pc: 0, + inst_range: 0..n as u32, + terminator: Terminator::Return(crate::c5::ir::NO_VALUE), + exit_acc: 0, + }], + extern_call_refs: Vec::new(), + extern_imm_code_refs: Vec::new(), + extern_imm_data_refs: Vec::new(), + extern_tls_refs: Vec::new(), + } + } + + #[test] + fn binop_of_two_imms_folds() { + let mut f = fresh(vec![ + Inst::Imm(2), + Inst::Imm(3), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Imm(5))); + } + + #[test] + fn chain_through_extend_folds_in_one_run() { + // Post-inline shape: Imm -> callee-narrows Extend -> shift. + let mut f = fresh(vec![ + Inst::Imm(0xff), + Inst::Extend { + value: 0, + kind: LoadKind::I8, + }, + Inst::BinopI { + op: BinOp::Mul, + lhs: 1, + rhs_imm: 2, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[1], Inst::Imm(-1))); + assert!(matches!(f.insts[2], Inst::Imm(-2))); + } + + #[test] + fn div_mod_by_zero_is_refused() { + for op in [BinOp::Div, BinOp::Mod, BinOp::Divu, BinOp::Modu] { + let mut f = fresh(vec![ + Inst::Imm(7), + Inst::Imm(0), + Inst::Binop { op, lhs: 0, rhs: 1 }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Binop { .. }), "{op:?}"); + } + } + + #[test] + fn min_over_minus_one_is_refused() { + for op in [BinOp::Div, BinOp::Mod] { + let mut f = fresh(vec![ + Inst::Imm(i64::MIN), + Inst::Imm(-1), + Inst::Binop { op, lhs: 0, rhs: 1 }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Binop { .. }), "{op:?}"); + } + } + + #[test] + fn rhs_imm_rewrites_to_binopi_for_safe_ops() { + let mut f = fresh(vec![ + Inst::LocalAddr(0), + Inst::Imm(9), + Inst::Binop { + op: BinOp::Shru, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!( + f.insts[2], + Inst::BinopI { + op: BinOp::Shru, + lhs: 0, + rhs_imm: 9, + } + )); + } + + #[test] + fn div_mod_never_rewrite_to_binopi() { + // Pins BINOPI_SAFE to the emitters' coverage: the x86_64 + // BinopI arm panics on Div / Divu / Mod / Modu and the + // aarch64 arm bails on Mod / Modu. + for op in [BinOp::Div, BinOp::Divu, BinOp::Mod, BinOp::Modu] { + assert!(!binopi_safe(op), "{op:?}"); + let mut f = fresh(vec![ + Inst::LocalAddr(0), + Inst::Imm(2), + Inst::Binop { op, lhs: 0, rhs: 1 }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Binop { .. }), "{op:?}"); + } + for op in [ + BinOp::Fadd, + BinOp::Fsub, + BinOp::Fmul, + BinOp::Fdiv, + BinOp::Feq, + BinOp::Fne, + BinOp::Flt, + BinOp::Fgt, + BinOp::Fle, + BinOp::Fge, + ] { + assert!(!binopi_safe(op), "{op:?}"); + } + for op in [ + BinOp::Add, + BinOp::Sub, + BinOp::Mul, + BinOp::And, + BinOp::Or, + BinOp::Xor, + BinOp::Shl, + BinOp::Shr, + BinOp::Shru, + BinOp::Ror, + BinOp::Eq, + BinOp::Ne, + BinOp::Lt, + BinOp::Gt, + BinOp::Le, + BinOp::Ge, + BinOp::Ult, + BinOp::Ugt, + BinOp::Ule, + BinOp::Uge, + ] { + assert!(binopi_safe(op), "{op:?}"); + } + } + + #[test] + fn lhs_imm_commutes_and_mirrors() { + // 5 + x -> x + 5. + let mut f = fresh(vec![ + Inst::Imm(5), + Inst::LocalAddr(0), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!( + f.insts[2], + Inst::BinopI { + op: BinOp::Add, + lhs: 1, + rhs_imm: 5, + } + )); + // 5 < x -> x > 5. + let mut f = fresh(vec![ + Inst::Imm(5), + Inst::LocalAddr(0), + Inst::Binop { + op: BinOp::Lt, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!( + f.insts[2], + Inst::BinopI { + op: BinOp::Gt, + lhs: 1, + rhs_imm: 5, + } + )); + // 5 - x has no rhs-imm form; it must stay put. + let mut f = fresh(vec![ + Inst::Imm(5), + Inst::LocalAddr(0), + Inst::Binop { + op: BinOp::Sub, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Binop { op: BinOp::Sub, .. })); + } + + #[test] + fn f32_flagged_imm_does_not_fold() { + // An f32 Imm carries the low-32 bit pattern; folding it with + // the f64-widened evaluator convention would corrupt it. + let mut f = fresh(vec![ + Inst::Imm(0x3f80_0000), + Inst::Extend { + value: 0, + kind: LoadKind::I32, + }, + ]); + f.f32_values[0] = true; + run_one(&mut f); + assert!(matches!(f.insts[1], Inst::Extend { .. })); + } + + #[test] + fn address_imms_do_not_fold() { + // ImmData is a data-segment offset patched at write time, not + // an integer constant; it must survive as the BinopI operand. + let mut f = fresh(vec![ + Inst::ImmData(64), + Inst::Imm(8), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[0], Inst::ImmData(64))); + assert!(matches!( + f.insts[2], + Inst::BinopI { + op: BinOp::Add, + lhs: 0, + rhs_imm: 8, + } + )); + } + + #[test] + fn shared_wide_imm_keeps_register_form() { + // A scratch-materialised immediate (Xor with a wide constant) + // shared by two ops must stay a register operand: rewriting + // both would duplicate the constant materialisation per use. + let mut f = fresh(vec![ + Inst::LocalAddr(0), + Inst::Imm(0x0123_4567_89ab_cdef), + Inst::Binop { + op: BinOp::Xor, + lhs: 0, + rhs: 1, + }, + Inst::Binop { + op: BinOp::Xor, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[2], Inst::Binop { .. })); + assert!(matches!(f.insts[3], Inst::Binop { .. })); + } + + #[test] + fn single_use_wide_imm_rewrites() { + let mut f = fresh(vec![ + Inst::LocalAddr(0), + Inst::Imm(0x0123_4567_89ab_cdef), + Inst::Binop { + op: BinOp::Xor, + lhs: 0, + rhs: 1, + }, + ]); + run_one(&mut f); + assert!(matches!( + f.insts[2], + Inst::BinopI { + op: BinOp::Xor, + lhs: 0, + rhs_imm: 0x0123_4567_89ab_cdef, + } + )); + } + + #[test] + fn extend_of_imm_folds_per_kind() { + let mut f = fresh(vec![ + Inst::Imm(0x1_8000), + Inst::Extend { + value: 0, + kind: LoadKind::I16, + }, + ]); + run_one(&mut f); + assert!(matches!(f.insts[1], Inst::Imm(-32768))); + } +} diff --git a/src/c5/codegen/passes/constfold_branch.rs b/src/c5/codegen/passes/constfold_branch.rs index 862e55f66..331b4f8d0 100644 --- a/src/c5/codegen/passes/constfold_branch.rs +++ b/src/c5/codegen/passes/constfold_branch.rs @@ -46,6 +46,16 @@ fn run_one(func: &mut FunctionSsa) { fall_through, } => fold(func.insts.as_slice(), cond) .map(|k| Terminator::Jmp(if k != 0 { target } else { fall_through })), + // A constant in-range index selects one table entry; out of + // range the terminator is unreachable (the lowering's bounds + // check precedes it) and is left alone. + Terminator::JumpTable { idx, table } => fold(func.insts.as_slice(), idx) + .and_then(|k| { + func.jump_tables[table as usize] + .get(k as u64 as usize) + .copied() + }) + .map(Terminator::Jmp), _ => None, }; if let Some(t) = new_term { @@ -92,8 +102,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/passes/dedup_imm.rs b/src/c5/codegen/passes/dedup_imm.rs index c3edafacf..e2f6c756e 100644 --- a/src/c5/codegen/passes/dedup_imm.rs +++ b/src/c5/codegen/passes/dedup_imm.rs @@ -136,6 +136,9 @@ fn run_one(func: &mut FunctionSsa) { Terminator::Return(v) if *v != NO_VALUE => { *v = resolve(&redirect, *v); } + Terminator::JumpTable { idx, .. } => { + *idx = resolve(&redirect, *idx); + } _ => {} } } @@ -246,8 +249,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/passes/drop_redundant_extend.rs b/src/c5/codegen/passes/drop_redundant_extend.rs index d50336a44..7d2d01d17 100644 --- a/src/c5/codegen/passes/drop_redundant_extend.rs +++ b/src/c5/codegen/passes/drop_redundant_extend.rs @@ -15,6 +15,19 @@ //! per-op renormalization left over from a chain of low-word //! integer arithmetic. //! +//! A third case works across blocks: two `Extend`s of the same SSA +//! value with the same `kind` compute the same result, so an occurrence +//! at a position dominated by another redirects to the dominating one +//! (`dedup_dominated_extends`). Extends of a value round-tripped +//! through a spill slot are not tracked: proving the slot was stored +//! extended needs a per-slot reaching-store analysis, so those stay. +//! +//! Finally, `drop_call_arg_reextends` removes the caller-side +//! re-extension of an argument to a direct internal call whose callee +//! re-derives the parameter from the low bits of the incoming register +//! anyway (its every read of the parameter is a `ParamRef` of a narrow +//! signed kind, which the per-arch entry lowering sign-extends). +//! //! The dead Extend is left in place; the allocator's dead-pure DCE and //! the per-arch emit's `is_dead_pure` skip drop it. `resolve` walks //! redirect chains so stacked extends collapse. @@ -23,9 +36,10 @@ use crate::c5::ir::{BinOp, FunctionSsa, Inst, LoadKind, NO_VALUE, StoreKind, Ter use alloc::vec::Vec; pub(crate) fn run(funcs: &mut [FunctionSsa]) { - for func in funcs { + for func in funcs.iter_mut() { run_one(func); } + drop_call_arg_reextends(funcs); } /// Mark `v`'s upper bits as observed and enqueue it for propagation. @@ -167,7 +181,9 @@ pub(crate) fn compute_high_observed(func: &FunctionSsa) -> Vec { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => { observe(&mut hi, &mut work, *cond); } - Terminator::GotoIndirect { target } => observe(&mut hi, &mut work, *target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + observe(&mut hi, &mut work, *target) + } Terminator::Return(v) if *v != NO_VALUE => observe(&mut hi, &mut work, *v), _ => {} } @@ -213,6 +229,371 @@ pub(crate) fn compute_high_observed(func: &FunctionSsa) -> Vec { hi } +// Resolve through chains: Extend(Extend(load)) becomes load. +fn resolve(redirect: &[Option], mut v: ValueId) -> ValueId { + let mut guard = 0u32; + while v != NO_VALUE && (v as usize) < redirect.len() { + match redirect[v as usize] { + Some(t) if t != v => { + v = t; + guard += 1; + if guard > redirect.len() as u32 { + break; + } + } + _ => break, + } + } + v +} + +/// Redirect an `Extend { value, kind }` to an earlier `Extend` of the +/// same `(value, kind)` at a dominating position: same block at a lower +/// index, or a block that strictly dominates. SSA values are immutable, +/// so the two extends compute the same result, and the dominating +/// definition reaches every consumer of the dominated one. Sources are +/// resolved through the already-collected redirects so extends of a +/// value and of its dropped re-extension land in one group. +/// +/// An extend that feeds a call argument or the return value is not +/// redirected: the emit computes it directly into the argument / +/// return register at its own position, whereas redirecting stretches +/// the dominating extend's live range to the call and trades the one +/// extend for parallel-copy moves and a saved register. +/// +/// A redirect whose live range would cross a call is also skipped +/// (`call_between`): the allocator has no rematerialization, so the +/// value would occupy a callee-saved register (or a spill slot) across +/// the call, costing save/restore traffic that outweighs the one +/// recomputed extend. +fn dedup_dominated_extends(func: &FunctionSsa, redirect: &mut [Option]) { + use hashbrown::HashMap; + let mut inst_block = alloc::vec![u32::MAX; func.insts.len()]; + for (bid, block) in func.blocks.iter().enumerate() { + for idx in block.inst_range.clone() { + if let Some(slot) = inst_block.get_mut(idx as usize) { + *slot = bid as u32; + } + } + } + let mut placed = alloc::vec![false; func.insts.len()]; + let mark = |placed: &mut [bool], v: ValueId| { + if let Some(slot) = placed.get_mut(v as usize) { + *slot = true; + } + }; + for inst in &func.insts { + match inst { + Inst::Call { args, .. } | Inst::CallExt { args, .. } | Inst::Intrinsic { args, .. } => { + for a in args { + mark(&mut placed, *a); + } + } + Inst::CallIndirect { args, .. } => { + for a in args { + mark(&mut placed, *a); + } + } + _ => {} + } + } + for block in &func.blocks { + if let Terminator::Return(v) = block.terminator + && v != NO_VALUE + { + mark(&mut placed, v); + } + } + let idom = crate::c5::codegen::ssa::mem2reg::dominators(func); + // Dominator-tree depth per block; unreachable blocks get MAX. + let mut depth = alloc::vec![u32::MAX; func.blocks.len()]; + for b in 0..func.blocks.len() { + if idom[b] == u32::MAX { + continue; + } + let (mut d, mut cur) = (0u32, b as u32); + while cur != 0 && idom[cur as usize] != u32::MAX { + cur = idom[cur as usize]; + d += 1; + } + depth[b] = d; + } + let mut groups: HashMap<(ValueId, LoadKind), Vec> = HashMap::new(); + for (idx, inst) in func.insts.iter().enumerate() { + let Inst::Extend { value, kind } = inst else { + continue; + }; + if redirect[idx].is_some() { + continue; + } + let blk = inst_block[idx]; + if blk == u32::MAX || depth.get(blk as usize).copied() == Some(u32::MAX) { + continue; + } + groups + .entry((resolve(redirect, *value), *kind)) + .or_default() + .push(idx as ValueId); + } + let dominates = |c_blk: u32, e_blk: u32| -> bool { + let mut b = e_blk; + while b != 0 { + b = idom[b as usize]; + if b == u32::MAX { + return false; + } + if b == c_blk { + return true; + } + } + false + }; + let is_call = |inst: &Inst| { + matches!( + inst, + Inst::Call { .. } | Inst::CallExt { .. } | Inst::CallIndirect { .. } + ) + }; + let block_has_call: Vec = func + .blocks + .iter() + .map(|b| { + b.inst_range + .clone() + .any(|idx| is_call(&func.insts[idx as usize])) + }) + .collect(); + // Whether a call sits at a position in `range` of `blk`'s insts. + let call_in = |blk: u32, range: core::ops::Range| -> bool { + let br = func.blocks[blk as usize].inst_range.clone(); + (range.start.max(br.start)..range.end.min(br.end)) + .any(|idx| is_call(&func.insts[idx as usize])) + }; + let succs = |b: u32| { + crate::c5::codegen::ssa::mem2reg::successors( + &func.blocks[b as usize].terminator, + &func.computed_goto_targets, + &func.jump_tables, + ) + }; + // Whether some path from `c` (exclusive) to `e` (exclusive) passes a + // call: the straight-line segment when both sit in one block, else a + // forward search over successor edges carrying a seen-a-call state. + // The start block contributes its calls after `c`, the target block + // its calls before `e`, and any block in between its calls + // wholesale (a cyclic revisit of the start / target block too). + let call_between = |c: ValueId, e: ValueId| -> bool { + let c_blk = inst_block[c as usize]; + let e_blk = inst_block[e as usize]; + if c_blk == e_blk && c < e && call_in(c_blk, c + 1..e) { + return true; + } + let n = func.blocks.len(); + let mut seen = alloc::vec![[false; 2]; n]; + let mut work: Vec<(u32, bool)> = Vec::new(); + let start_flag = call_in(c_blk, c + 1..u32::MAX); + for s in succs(c_blk) { + if !seen[s as usize][start_flag as usize] { + seen[s as usize][start_flag as usize] = true; + work.push((s, start_flag)); + } + } + while let Some((b, f)) = work.pop() { + if b == e_blk && (f || call_in(b, 0..e)) { + return true; + } + let f2 = f || block_has_call[b as usize]; + for s in succs(b) { + if !seen[s as usize][f2 as usize] { + seen[s as usize][f2 as usize] = true; + work.push((s, f2)); + } + } + } + false + }; + for mut members in groups.into_values() { + if members.len() < 2 { + continue; + } + // Sorting by (depth, idx) means a member can only be dominated + // by an earlier one, so redirects always point backward. + members.sort_by_key(|&v| (depth[inst_block[v as usize] as usize], v)); + for i in 1..members.len() { + let e = members[i]; + if placed[e as usize] { + continue; + } + let e_blk = inst_block[e as usize]; + for &c in &members[..i] { + let c_blk = inst_block[c as usize]; + if ((c_blk == e_blk && c < e) || dominates(c_blk, e_blk)) && !call_between(c, e) { + redirect[e as usize] = Some(c); + break; + } + } + } + } +} + +/// Bit width of a narrow signed extend kind; `None` otherwise. +fn narrow_kind_bits(kind: LoadKind) -> Option { + match kind { + LoadKind::I8 => Some(8), + LoadKind::I16 => Some(16), + LoadKind::I32 => Some(32), + _ => None, + } +} + +/// Per-parameter re-extension proof for `func`: `Some(kind)` when every +/// read of parameter `i` is a `ParamRef { idx: i, kind }` of one narrow +/// signed kind, so the callee derives the parameter from the low +/// `kind`-width bits of the incoming register (the per-arch entry +/// lowering sign-extends them; an elided I32 extension means no +/// consumer reads higher bits). The parameter's c5 cdecl cell must not +/// leak the raw incoming register: the prologue spills it unextended +/// when the cell survives, so any address take or live 8-byte read of +/// the cell disqualifies. Reads of 4 bytes or fewer see only the low +/// word, which the caller-side drop preserves. +fn param_reextend_kinds(func: &FunctionSsa) -> Vec> { + let n = func.n_params; + let mut kinds: Vec> = alloc::vec![None; n]; + if n == 0 || func.is_variadic || func.indirect_result_slot != 0 { + return kinds; + } + let mut use_counts = alloc::vec![0u32; func.insts.len()]; + let bump = |counts: &mut [u32], v: ValueId| { + if let Some(slot) = counts.get_mut(v as usize) { + *slot += 1; + } + }; + for inst in &func.insts { + crate::c5::codegen::ssa::reg_alloc::for_each_operand(inst, |v| bump(&mut use_counts, v)); + } + for block in &func.blocks { + if block.exit_acc != NO_VALUE { + bump(&mut use_counts, block.exit_acc); + } + match block.terminator { + Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => { + bump(&mut use_counts, cond) + } + Terminator::GotoIndirect { target } => bump(&mut use_counts, target), + Terminator::Return(v) if v != NO_VALUE => bump(&mut use_counts, v), + _ => {} + } + } + for (i, kind) in kinds.iter_mut().enumerate() { + let slot = i as i64 + 2; + if func + .multi_cell_slots + .iter() + .any(|&(base, cells)| slot >= base && slot < base + cells) + { + continue; + } + let mut seen: Option = None; + let mut ok = true; + for (idx, inst) in func.insts.iter().enumerate() { + match inst { + Inst::ParamRef { idx: p, kind: k } if *p as usize == i => { + if narrow_kind_bits(*k).is_none() || seen.is_some_and(|s| s != *k) { + ok = false; + break; + } + seen = Some(*k); + } + Inst::LocalAddr(off) if *off == slot => { + ok = false; + break; + } + Inst::LoadLocal { + off, + kind: k, + volatile, + } if *off == slot + && matches!(k, LoadKind::I64 | LoadKind::F64 | LoadKind::F32) + && (*volatile || use_counts[idx] > 0) => + { + ok = false; + break; + } + _ => {} + } + } + if ok { + *kind = seen; + } + } + kinds +} + +/// For each direct internal call, replace an `Extend { value, kind }` +/// argument with `value` when the callee's parameter re-extends from a +/// width no wider than `kind` (see [`param_reextend_kinds`]). The bits +/// the drop changes are above the extend's width, and the callee reads +/// none of them. Restricted to `Inst::Call`: an external or indirect +/// callee's entry behavior is unknown, so those keep the canonical +/// C99 6.5.2.2p4-converted argument value. +fn drop_call_arg_reextends(funcs: &mut [FunctionSsa]) { + use hashbrown::HashMap; + let mut by_ent: HashMap>> = HashMap::new(); + for func in funcs.iter() { + if func + .insts + .iter() + .any(|i| matches!(i, Inst::ParamRef { .. })) + { + by_ent.insert(func.ent_pc, param_reextend_kinds(func)); + } + } + if by_ent.is_empty() { + return; + } + for func in funcs.iter_mut() { + for idx in 0..func.insts.len() { + let Inst::Call { + target_pc, + args, + arg_aggs, + .. + } = &func.insts[idx] + else { + continue; + }; + let Some(params) = by_ent.get(target_pc) else { + continue; + }; + let mut rewrites: Vec<(usize, ValueId)> = Vec::new(); + for (k, &a) in args.iter().enumerate() { + if arg_aggs.get(k).copied().flatten().is_some() { + continue; + } + let Some(Inst::Extend { value, kind }) = func.insts.get(a as usize) else { + continue; + }; + let (Some(ext_bits), Some(param_kind)) = + (narrow_kind_bits(*kind), params.get(k).copied().flatten()) + else { + continue; + }; + if narrow_kind_bits(param_kind).is_some_and(|pb| pb <= ext_bits) { + rewrites.push((k, *value)); + } + } + if rewrites.is_empty() { + continue; + } + if let Inst::Call { args, .. } = &mut func.insts[idx] { + for (k, v) in rewrites { + args[k] = v; + } + } + } + } +} + fn is_signed_load(insts: &[Inst], v: ValueId) -> Option { if v == NO_VALUE { return None; @@ -255,26 +636,10 @@ fn run_one(func: &mut FunctionSsa) { redirect[idx] = Some(*value); } } + dedup_dominated_extends(func, &mut redirect); if redirect.iter().all(|r| r.is_none()) { return; } - // Resolve through chains: Extend(Extend(load)) becomes load. - fn resolve(redirect: &[Option], mut v: ValueId) -> ValueId { - let mut guard = 0u32; - while v != NO_VALUE { - match redirect[v as usize] { - Some(t) if t != v => { - v = t; - guard += 1; - if guard > redirect.len() as u32 { - break; - } - } - _ => break, - } - } - v - } // Rewrite every operand, terminator value, and block accumulator. for inst in func.insts.iter_mut() { // The redirect-from list (the dead Extends) reads the load @@ -408,8 +773,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), @@ -588,6 +956,364 @@ mod tests { ); } + /// b0: v0 Imm; v1 Add(v0,v0); v2 Extend(v1, k0); Bz v2 -> b2 / b1 + /// b1: v3 Extend(v1, k1); v4 Add(v3, 1); Return(v4) + /// b2: v5 Extend(v1, k0); v6 Add(v5, 1); Return(v6) + /// I8/I16 kinds keep case 1/2 out of the way so the cross-block + /// dedup is the only redirect source; the adds consume the extends + /// away from the call-argument / return positions dedup skips. + fn diamond_extends(k0: LoadKind, k1: LoadKind) -> FunctionSsa { + fresh( + vec![ + Inst::Imm(300), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 0, + }, + Inst::Extend { value: 1, kind: k0 }, + Inst::Extend { value: 1, kind: k1 }, + Inst::BinopI { + op: BinOp::Add, + lhs: 3, + rhs_imm: 1, + }, + Inst::Extend { value: 1, kind: k0 }, + Inst::BinopI { + op: BinOp::Add, + lhs: 5, + rhs_imm: 1, + }, + ], + vec![ + Block { + start_pc: 0, + inst_range: 0..3, + terminator: Terminator::Bz { + cond: 2, + target: 2, + fall_through: 1, + }, + exit_acc: 2, + }, + Block { + start_pc: 0, + inst_range: 3..5, + terminator: Terminator::Return(4), + exit_acc: 4, + }, + Block { + start_pc: 0, + inst_range: 5..7, + terminator: Terminator::Return(6), + exit_acc: 6, + }, + ], + ) + } + + #[test] + fn dominated_same_kind_extend_redirects_to_dominating_one() { + let mut f = diamond_extends(LoadKind::I8, LoadKind::I8); + run_one(&mut f); + assert!( + matches!(f.insts[4], Inst::BinopI { lhs: 2, .. }), + "b1's extend duplicates the entry-block extend of the same \ + (value, kind) and must redirect to it; got {:?}", + f.insts[4] + ); + assert!(matches!(f.insts[6], Inst::BinopI { lhs: 2, .. })); + } + + #[test] + fn kind_mismatch_blocks_the_dedup() { + let mut f = diamond_extends(LoadKind::I8, LoadKind::I16); + run_one(&mut f); + assert!( + matches!(f.insts[4], Inst::BinopI { lhs: 3, .. }), + "an I16 extend must not redirect to an I8 extend of the same value", + ); + } + + #[test] + fn sibling_branch_extend_is_not_deduped() { + // b0: v0 Imm; v1 Add; Bz -> b2 / b1 + // b1: v2 Extend(v1, I8); v3 Add(v2, 1); Return(v3) + // b2: v4 Extend(v1, I8); v5 Add(v4, 1); Return(v5) + // Neither branch dominates the other; both extends stay. + let mut f = fresh( + vec![ + Inst::Imm(300), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 0, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I8, + }, + Inst::BinopI { + op: BinOp::Add, + lhs: 2, + rhs_imm: 1, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I8, + }, + Inst::BinopI { + op: BinOp::Add, + lhs: 4, + rhs_imm: 1, + }, + ], + vec![ + Block { + start_pc: 0, + inst_range: 0..2, + terminator: Terminator::Bz { + cond: 1, + target: 2, + fall_through: 1, + }, + exit_acc: 1, + }, + Block { + start_pc: 0, + inst_range: 2..4, + terminator: Terminator::Return(3), + exit_acc: 3, + }, + Block { + start_pc: 0, + inst_range: 4..6, + terminator: Terminator::Return(5), + exit_acc: 5, + }, + ], + ); + run_one(&mut f); + assert!(matches!(f.insts[3], Inst::BinopI { lhs: 2, .. })); + assert!( + matches!(f.insts[5], Inst::BinopI { lhs: 4, .. }), + "sibling-branch extends have no dominance relation and must both stay", + ); + } + + #[test] + fn call_argument_extend_is_not_dedup_redirected() { + // b0: v0 Imm; v1 Add; v2 Extend(v1, I8); Bz -> b2 / b1 + // b1: v3 Extend(v1, I8); v4 Call(args=[v3]); Return(v4) + // b2: Return(v2) + // The dominated extend feeds a call argument, so it stays: the + // emit materialises it into the argument register in place. + let mut f = fresh( + vec![ + Inst::Imm(300), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 0, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I8, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I8, + }, + Inst::Call { + target_pc: 99, + args: alloc::vec![3], + fixed_args: 1, + fp_return: false, + fp_arg_mask: 0, + arg_aggs: Vec::new(), + ret_agg: None, + ret_slot_local: 0, + }, + ], + vec![ + Block { + start_pc: 0, + inst_range: 0..3, + terminator: Terminator::Bz { + cond: 2, + target: 2, + fall_through: 1, + }, + exit_acc: 2, + }, + Block { + start_pc: 0, + inst_range: 3..5, + terminator: Terminator::Return(4), + exit_acc: 4, + }, + Block { + start_pc: 0, + inst_range: 5..5, + terminator: Terminator::Return(2), + exit_acc: 2, + }, + ], + ); + run_one(&mut f); + let Inst::Call { args, .. } = &f.insts[4] else { + panic!("expected Call at v4"); + }; + assert_eq!( + args[0], 3, + "a call-argument extend keeps its own position; dedup must not \ + stretch the dominating extend's live range to the call", + ); + } + + /// Callee at ent_pc 7: ParamRef(0, I32) returned; caller passes + /// Extend { v, I32 } as the argument of a direct call to it. + fn caller_callee(callee_kind: LoadKind, variadic: bool) -> Vec { + let mut callee = fresh( + vec![Inst::ParamRef { + idx: 0, + kind: callee_kind, + }], + vec![Block { + start_pc: 0, + inst_range: 0..1, + terminator: Terminator::Return(0), + exit_acc: 0, + }], + ); + callee.ent_pc = 7; + callee.n_params = 1; + callee.is_variadic = variadic; + let mut caller = fresh( + vec![ + Inst::Imm(300), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 0, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I32, + }, + Inst::Call { + target_pc: 7, + args: alloc::vec![2], + fixed_args: 1, + fp_return: false, + fp_arg_mask: 0, + arg_aggs: Vec::new(), + ret_agg: None, + ret_slot_local: 0, + }, + ], + vec![Block { + start_pc: 0, + inst_range: 0..4, + terminator: Terminator::Return(3), + exit_acc: 3, + }], + ); + caller.ent_pc = 9; + alloc::vec![callee, caller] + } + + fn call_arg(funcs: &[FunctionSsa]) -> u32 { + let Inst::Call { args, .. } = &funcs[1].insts[3] else { + panic!("expected Call at v3"); + }; + args[0] + } + + #[test] + fn call_arg_extend_drops_when_callee_reextends() { + let mut funcs = caller_callee(LoadKind::I32, false); + run(&mut funcs); + assert_eq!( + call_arg(&funcs), + 1, + "the callee's ParamRef(I32) re-extends, so the caller passes the raw add", + ); + } + + #[test] + fn call_arg_extend_stays_for_wider_param_kind() { + // Callee reads 8 bytes of the incoming register (ParamRef I64): + // dropping the caller's I32 extend would expose raw high bits. + let mut funcs = caller_callee(LoadKind::I64, false); + run(&mut funcs); + assert_eq!(call_arg(&funcs), 2); + } + + #[test] + fn call_arg_extend_stays_for_variadic_callee() { + let mut funcs = caller_callee(LoadKind::I32, true); + run(&mut funcs); + assert_eq!(call_arg(&funcs), 2); + } + + #[test] + fn call_arg_extend_stays_when_param_cell_escapes() { + let mut funcs = caller_callee(LoadKind::I32, false); + // Take the address of the parameter's c5 cdecl cell: the raw + // incoming register is spilled there and may be read wide. + funcs[0].insts.push(Inst::LocalAddr(2)); + funcs[0].blocks[0].inst_range = 0..2; + run(&mut funcs); + assert_eq!(call_arg(&funcs), 2); + } + + #[test] + fn call_arg_extend_stays_for_external_callee() { + // The argument feeds an external call (CallExt), whose entry + // behavior is unknown, so the caller-side extend must stay: the + // rewrite pass only touches direct internal `Inst::Call`. + let mut caller = fresh( + vec![ + Inst::Imm(300), + Inst::Binop { + op: BinOp::Add, + lhs: 0, + rhs: 0, + }, + Inst::Extend { + value: 1, + kind: LoadKind::I32, + }, + Inst::CallExt { + binding_idx: 0, + args: alloc::vec![2], + fp_arg_mask: 0, + fp_return: false, + arg_aggs: Vec::new(), + ret_agg: None, + ret_slot_local: 0, + }, + ], + vec![Block { + start_pc: 0, + inst_range: 0..4, + terminator: Terminator::Return(3), + exit_acc: 3, + }], + ); + caller.ent_pc = 9; + let mut funcs = alloc::vec![caller]; + run(&mut funcs); + let Inst::CallExt { args, .. } = &funcs[0].insts[3] else { + panic!("expected CallExt at v3"); + }; + assert_eq!( + args[0], 2, + "an external callee's entry behavior is unknown; the extend stays", + ); + } + #[test] fn extend_feeding_signed_compare_is_kept() { // v3 Extend(v2) feeds a signed `Lt` compare, which reads the diff --git a/src/c5/codegen/passes/fma.rs b/src/c5/codegen/passes/fma.rs index 15cf43c7e..799a68808 100644 --- a/src/c5/codegen/passes/fma.rs +++ b/src/c5/codegen/passes/fma.rs @@ -61,7 +61,9 @@ fn use_counts(func: &FunctionSsa) -> Vec { for block in &func.blocks { match block.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => bump(cond), - Terminator::GotoIndirect { target } => bump(target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + bump(target) + } Terminator::Return(v) => bump(v), Terminator::Jmp(_) | Terminator::TailExt(_) | Terminator::FallThrough(_) => {} } diff --git a/src/c5/codegen/passes/index_fold.rs b/src/c5/codegen/passes/index_fold.rs index 358367735..3993b90e1 100644 --- a/src/c5/codegen/passes/index_fold.rs +++ b/src/c5/codegen/passes/index_fold.rs @@ -90,7 +90,9 @@ fn use_counts(func: &FunctionSsa) -> Vec { for block in &func.blocks { match block.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => bump(cond, &mut counts), - Terminator::GotoIndirect { target } => bump(target, &mut counts), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + bump(target, &mut counts) + } Terminator::Return(v) => bump(v, &mut counts), Terminator::Jmp(_) | Terminator::TailExt(_) | Terminator::FallThrough(_) => {} } diff --git a/src/c5/codegen/passes/inline.rs b/src/c5/codegen/passes/inline.rs index 440cadfe3..b47c2a26d 100644 --- a/src/c5/codegen/passes/inline.rs +++ b/src/c5/codegen/passes/inline.rs @@ -108,6 +108,13 @@ fn is_inline_candidate(func: &FunctionSsa, cap: u32, abi: Abi) -> bool { say("variadic"); return false; } + // A body calling a returns-twice function (setjmp family / vfork) + // stays out of line: splicing it would silently drop the caller's + // no-slot-share discipline (`FunctionSsa::has_returns_twice_call`). + if func.has_returns_twice_call { + say("calls a returns-twice function"); + return false; + } // Host-ABI aggregates are admitted only in the shapes the splice can // reproduce: a by-value parameter passed in a single integer register // (it arrives as the address of the caller's copy in one argument, and @@ -170,6 +177,13 @@ fn is_inline_candidate(func: &FunctionSsa, cap: u32, abi: Abi) -> bool { say("GotoIndirect terminator"); return false; } + Terminator::JumpTable { .. } => { + // Splicing shifts the callee's block ids, which the + // caller-side jump_tables clone would have to remap; a + // table dispatcher is far past the size cap anyway. + say("JumpTable terminator"); + return false; + } Terminator::Jmp(_) | Terminator::FallThrough(_) | Terminator::Bz { .. } @@ -426,7 +440,7 @@ fn is_inline_candidate(func: &FunctionSsa, cap: u32, abi: Abi) -> bool { /// Map a single operand `v` through `remap`. `NO_VALUE` stays. #[inline] -fn map_v(v: ValueId, remap: &[ValueId]) -> ValueId { +pub(super) fn map_v(v: ValueId, remap: &[ValueId]) -> ValueId { if v == NO_VALUE || (v as usize) >= remap.len() { v } else { @@ -436,7 +450,7 @@ fn map_v(v: ValueId, remap: &[ValueId]) -> ValueId { /// Apply the caller's value remap to every operand in `inst`. The /// caller hands us a fresh clone; we mutate in place. -fn remap_caller_inst(inst: &mut Inst, remap: &[ValueId]) { +pub(super) fn remap_caller_inst(inst: &mut Inst, remap: &[ValueId]) { match inst { Inst::Imm(_) | Inst::ImmData(_) @@ -586,7 +600,7 @@ fn rewrite_callee_inst(inst: &Inst, args: &[ValueId], callee_remap: &[ValueId]) } /// Rewrite block terminators through the caller's value remap. -fn remap_terminator(term: &mut Terminator, remap: &[ValueId]) { +pub(super) fn remap_terminator(term: &mut Terminator, remap: &[ValueId]) { match term { Terminator::Jmp(_) | Terminator::FallThrough(_) | Terminator::TailExt(_) => {} Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => { @@ -595,6 +609,9 @@ fn remap_terminator(term: &mut Terminator, remap: &[ValueId]) { Terminator::GotoIndirect { target } => { *target = map_v(*target, remap); } + Terminator::JumpTable { idx, .. } => { + *idx = map_v(*idx, remap); + } Terminator::Return(v) => { *v = map_v(*v, remap); } @@ -668,6 +685,12 @@ fn splice_multi_block( Terminator::GotoIndirect { target } => Terminator::GotoIndirect { target: map_v(target, remap), }, + // Multi-block splicing is skipped for jump-table callers + // (block_id_shift_unsafe); the table entries would need the + // same shift. TODO: remap via the shared BlockId utility. + Terminator::JumpTable { .. } => { + unreachable!("multi-block splice skips jump-table callers") + } } }; @@ -884,6 +907,9 @@ fn splice_multi_block( Terminator::GotoIndirect { .. } => { unreachable!("filter rejects GotoIndirect") } + Terminator::JumpTable { .. } => { + unreachable!("filter rejects JumpTable") + } }; let exit_acc = if cblock.exit_acc != NO_VALUE { map_v(cblock.exit_acc, &callee_remap) @@ -988,8 +1014,16 @@ fn splice_multi_block( ret_is_fp: original.ret_is_fp, indirect_result_slot: original.indirect_result_slot, computed_goto_targets: original.computed_goto_targets, + // Multi-block splicing is skipped for jump-table callers and + // the filter rejects jump-table callees, so both lists are + // empty here. + jump_tables: original.jump_tables, synthetic_base: original.synthetic_base, multi_cell_slots: original.multi_cell_slots, + // The candidate filter rejects returns-twice callees, so only + // the caller's own flag can be set here. + has_returns_twice_call: original.has_returns_twice_call, + did_unroll: original.did_unroll, }; } @@ -1356,6 +1390,7 @@ fn inline_caller(caller: &mut FunctionSsa, callees: &BTreeMap body, body -> post, +//! post -> header. This pass only reorders `func.blocks` and remaps +//! block ids (instructions never move between blocks), letting the +//! emitters' next-block jump elision collapse the reordered chains: +//! +//! * an edge into a chain of empty `Jmp` blocks is retargeted to the +//! chain's end, stopping one hop short of a phi-carrying block +//! (that hop holds the edge's phi moves); +//! * blocks are placed depth-first from the entry with every natural +//! loop's body contiguous; +//! * a loop whose header conditionally exits the loop is rotated to +//! bottom-test form: the header moves to the end of the loop's +//! chain, and an unconditional latch is placed directly before it +//! so the back edge falls through; +//! * a conditional whose taken target is the next block in layout is +//! inverted (`Bz` <-> `Bnz`, arms swapped); the successor set is +//! unchanged, so no critical edge appears after +//! `split_crit_edges`. +//! +//! Functions with a computed goto (`BlockAddr` pins label blocks and +//! the flow can be irreducible) and functions with an irreducible +//! loop (a retreating edge whose target does not dominate its +//! source) keep their source order. + +use alloc::collections::{BTreeMap, BTreeSet}; +use alloc::vec::Vec; + +use super::super::ssa::mem2reg::{dominators, predecessors, successors}; +use crate::c5::ir::{BlockId, FunctionSsa, Inst, Terminator}; + +/// Sentinel matching `mem2reg`'s undefined immediate dominator. +const NO_BLOCK: BlockId = BlockId::MAX; + +pub(crate) fn run(funcs: &mut [FunctionSsa]) { + for func in funcs.iter_mut() { + run_one(func); + } +} + +fn run_one(func: &mut FunctionSsa) { + if !func.computed_goto_targets.is_empty() || func.blocks.len() < 2 { + return; + } + thread_jumps(func); + let rpo = rpo_numbers(func); + let idom = dominators(func); + if is_irreducible(func, &idom, &rpo) { + return; + } + let preds = predecessors(func); + let loops = natural_loops(func, &idom, &preds, &rpo); + let forest = LoopForest::build(func.blocks.len(), &loops); + let order = layout_order(func, &loops, &forest); + debug_assert_eq!(order.first(), Some(&0), "entry block must stay first"); + if order.first() != Some(&0) { + return; + } + super::remap_blocks::permute_blocks(func, &order); + invert_branches(func); +} + +/// The unconditional target of a terminator, if any. +fn uncond_target(term: &Terminator) -> Option { + match term { + Terminator::Jmp(t) | Terminator::FallThrough(t) => Some(*t), + _ => None, + } +} + +fn block_is_empty(func: &FunctionSsa, b: BlockId) -> bool { + let r = &func.blocks[b as usize].inst_range; + r.start >= r.end +} + +fn block_has_phis(func: &FunctionSsa, b: BlockId) -> bool { + let r = func.blocks[b as usize].inst_range.clone(); + r.into_iter() + .any(|i| matches!(func.insts[i as usize], Inst::Phi { .. })) +} + +/// Follow the chain of empty unconditionally-branching blocks from +/// `start` and return the block an edge into `start` may target +/// instead. The final block must carry no phis (its incomings key +/// predecessor ids that a retarget would falsify); when it does, the +/// chain stops one hop short, at the empty block that holds the +/// edge's phi moves. A chain longer than the block count is a jump +/// cycle and is left alone. +fn thread_target(func: &FunctionSsa, start: BlockId) -> BlockId { + let mut prev = start; + let mut cur = start; + let mut steps = 0usize; + while steps <= func.blocks.len() { + if !block_is_empty(func, cur) { + break; + } + let Some(t) = uncond_target(&func.blocks[cur as usize].terminator) else { + break; + }; + if t == cur { + break; + } + prev = cur; + cur = t; + steps += 1; + } + if steps > func.blocks.len() { + return start; + } + if block_has_phis(func, cur) { prev } else { cur } +} + +/// Retarget every terminator edge through [`thread_target`]. Bypassed +/// blocks keep their own edges; any that become unreachable are +/// placed after the reachable code by the layout order. +fn thread_jumps(func: &mut FunctionSsa) { + for i in 0..func.blocks.len() { + let term = func.blocks[i].terminator; + let new_term = match term { + Terminator::Jmp(t) => Terminator::Jmp(thread_target(func, t)), + Terminator::FallThrough(t) => Terminator::FallThrough(thread_target(func, t)), + Terminator::Bz { + cond, + target, + fall_through, + } => Terminator::Bz { + cond, + target: thread_target(func, target), + fall_through: thread_target(func, fall_through), + }, + Terminator::Bnz { + cond, + target, + fall_through, + } => Terminator::Bnz { + cond, + target: thread_target(func, target), + fall_through: thread_target(func, fall_through), + }, + other => other, + }; + func.blocks[i].terminator = new_term; + } +} + +/// Reverse-postorder number per block from a depth-first search at +/// the entry; `usize::MAX` for blocks unreachable from the entry. +pub(super) fn rpo_numbers(func: &FunctionSsa) -> Vec { + let n = func.blocks.len(); + let mut po: Vec = Vec::with_capacity(n); + let mut visited = alloc::vec![false; n]; + let mut stack: Vec<(BlockId, usize)> = Vec::new(); + visited[0] = true; + stack.push((0, 0)); + while let Some(&(b, si)) = stack.last() { + let succ = successors(&func.blocks[b as usize].terminator, &[], &func.jump_tables); + if si < succ.len() { + stack.last_mut().unwrap().1 += 1; + let s = succ[si]; + if !visited[s as usize] { + visited[s as usize] = true; + stack.push((s, 0)); + } + } else { + po.push(b); + stack.pop(); + } + } + let mut rpo = alloc::vec![usize::MAX; n]; + for (i, &b) in po.iter().enumerate() { + rpo[b as usize] = po.len() - 1 - i; + } + rpo +} + +/// Whether `a` dominates `b`, walking `b` up the immediate-dominator +/// tree to the entry. +fn dominates(a: BlockId, b: BlockId, idom: &[BlockId]) -> bool { + if a == b { + return true; + } + let mut x = b; + while x != 0 { + let up = idom[x as usize]; + if up == NO_BLOCK || up == x { + break; + } + if up == a { + return true; + } + x = up; + } + a == 0 && idom[b as usize] != NO_BLOCK +} + +/// A retreating edge (target at or before the source in RPO) whose +/// target does not dominate its source enters a loop past its +/// header; such a multiple-entry loop has no rotation-safe header. +fn is_irreducible(func: &FunctionSsa, idom: &[BlockId], rpo: &[usize]) -> bool { + for (b, block) in func.blocks.iter().enumerate() { + if rpo[b] == usize::MAX { + continue; + } + for s in successors(&block.terminator, &[], &func.jump_tables) { + if rpo[s as usize] <= rpo[b] && !dominates(s, b as BlockId, idom) { + return true; + } + } + } + false +} + +/// A natural loop: the header plus every block that can reach a back +/// edge's source without passing through the header. +pub(super) struct NaturalLoop { + pub(super) header: BlockId, + pub(super) body: BTreeSet, +} + +/// Natural loops keyed by header, merging the bodies of multiple back +/// edges that target the same header. Back edges from unreachable +/// blocks are ignored. +pub(super) fn natural_loops( + func: &FunctionSsa, + idom: &[BlockId], + preds: &[Vec], + rpo: &[usize], +) -> Vec { + let mut bodies: BTreeMap> = BTreeMap::new(); + for (b, block) in func.blocks.iter().enumerate() { + if rpo[b] == usize::MAX { + continue; + } + let b = b as BlockId; + for s in successors(&block.terminator, &[], &func.jump_tables) { + // `b -> s` is a back edge iff the header `s` dominates `b`. + if dominates(s, b, idom) { + let body = bodies.entry(s).or_default(); + collect_loop_body(s, b, preds, body); + } + } + } + bodies + .into_iter() + .map(|(header, body)| NaturalLoop { header, body }) + .collect() +} + +/// Add the header and every block reaching `back_src` without passing +/// through the header to `body`. +fn collect_loop_body( + header: BlockId, + back_src: BlockId, + preds: &[Vec], + body: &mut BTreeSet, +) { + body.insert(header); + if body.insert(back_src) { + let mut stack = alloc::vec![back_src]; + while let Some(n) = stack.pop() { + for &p in &preds[n as usize] { + if body.insert(p) { + stack.push(p); + } + } + } + } +} + +/// Loop nesting derived from body containment. Two distinct natural +/// loops of a reducible CFG are disjoint or strictly nested (loops +/// sharing a header were merged), so the smallest containing body is +/// unique. +struct LoopForest { + /// Innermost loop containing each block, if any. + innermost: Vec>, + /// Innermost loop strictly containing each loop, if any. + parent: Vec>, +} + +impl LoopForest { + fn build(n_blocks: usize, loops: &[NaturalLoop]) -> LoopForest { + let smallest_containing = |b: BlockId, exclude: Option| -> Option { + let mut best: Option = None; + for (li, l) in loops.iter().enumerate() { + if Some(li) == exclude || !l.body.contains(&b) { + continue; + } + if best.is_none_or(|bi| l.body.len() < loops[bi].body.len()) { + best = Some(li); + } + } + best + }; + let innermost = (0..n_blocks) + .map(|b| smallest_containing(b as BlockId, None)) + .collect(); + let parent = loops + .iter() + .enumerate() + .map(|(li, l)| smallest_containing(l.header, Some(li))) + .collect(); + LoopForest { innermost, parent } + } + + /// The outermost loop containing `b` that is strictly inside + /// `level`, or `None` when `b` belongs to `level` directly. + fn unit_loop(&self, b: BlockId, level: Option) -> Option { + let mut li = self.innermost[b as usize]?; + if Some(li) == level { + return None; + } + while self.parent[li] != level { + li = self.parent[li]?; + } + Some(li) + } +} + +/// Whether the loop can rotate to bottom-test form: the header's +/// conditional has exactly one arm leaving the loop, and the header +/// is not the function entry (which must stay first). +fn rotatable(func: &FunctionSsa, l: &NaturalLoop) -> bool { + if l.header == 0 { + return false; + } + match func.blocks[l.header as usize].terminator { + Terminator::Bz { + target, + fall_through, + .. + } + | Terminator::Bnz { + target, + fall_through, + .. + } => l.body.contains(&target) != l.body.contains(&fall_through), + _ => false, + } +} + +/// Depth-first placement over the blocks of `level` (a loop's body, +/// or the whole function for `None`) starting at `entry`. Each inner +/// loop is laid out recursively and treated as one unit. Within a +/// rotated loop the header chunk moves to the end and an +/// unconditional latch is placed directly before it. Appends the +/// placed blocks to `out`. +fn lay_out( + func: &FunctionSsa, + loops: &[NaturalLoop], + forest: &LoopForest, + level: Option, + entry: BlockId, + placed: &mut [bool], + out: &mut Vec, +) { + let in_level = |b: BlockId| level.is_none_or(|li| loops[li].body.contains(&b)); + // Chunks in placement order: a single block, or a whole inner + // loop. Kept separate so rotation and the latch move reorder + // units without breaking a unit's internal fallthroughs. + let mut chunks: Vec> = Vec::new(); + let mut stack: Vec = alloc::vec![entry]; + while let Some(b) = stack.pop() { + if placed[b as usize] || !in_level(b) { + continue; + } + let mut chunk: Vec = Vec::new(); + match forest.unit_loop(b, level) { + None => { + placed[b as usize] = true; + chunk.push(b); + // Push the conditional's taken target first so the + // fall-through arm pops first and chains. + match func.blocks[b as usize].terminator { + Terminator::Jmp(t) | Terminator::FallThrough(t) => stack.push(t), + Terminator::Bz { + target, + fall_through, + .. + } + | Terminator::Bnz { + target, + fall_through, + .. + } => { + stack.push(target); + stack.push(fall_through); + } + Terminator::Return(_) + | Terminator::TailExt(_) + | Terminator::GotoIndirect { .. } => {} + // Case blocks chain in table order; the entries are + // remapped with the rest of the id surface. + Terminator::JumpTable { table, .. } => { + for &t in func.jump_tables[table as usize].iter().rev() { + stack.push(t); + } + } + } + } + Some(li) => { + lay_out( + func, + loops, + forest, + Some(li), + loops[li].header, + placed, + &mut chunk, + ); + // Exit successors, collected tail-first so the last + // block's exit (the rotated header's) continues the + // chain. + let mut exits: Vec = Vec::new(); + for &cb in chunk.iter().rev() { + for s in + successors(&func.blocks[cb as usize].terminator, &[], &func.jump_tables) + { + if !loops[li].body.contains(&s) && !exits.contains(&s) { + exits.push(s); + } + } + } + for &e in exits.iter().rev() { + stack.push(e); + } + } + } + chunks.push(chunk); + } + if let Some(li) = level { + let l = &loops[li]; + let header_first = chunks.first().map(|c| c.as_slice()) == Some(&[l.header][..]); + debug_assert!(header_first, "loop chain must start at its header"); + if header_first && chunks.len() >= 2 && rotatable(func, l) { + let header_chunk = chunks.remove(0); + chunks.push(header_chunk); + move_latch_before_header(func, l.header, &mut chunks); + } + } + for chunk in chunks { + out.extend(chunk); + } +} + +/// Place an unconditional latch (a single-block chunk ending in +/// `Jmp(header)`) directly before the header chunk of a rotated loop +/// so the back edge falls through. Skipped when the chunk already +/// preceding the header reaches it by fallthrough. +fn move_latch_before_header(func: &FunctionSsa, header: BlockId, chunks: &mut Vec>) { + let hpos = chunks.len() - 1; + debug_assert_eq!(chunks[hpos].as_slice(), &[header]); + if hpos == 0 { + return; + } + let reaches_header = |b: BlockId| match func.blocks[b as usize].terminator { + Terminator::Jmp(t) | Terminator::FallThrough(t) => t == header, + Terminator::Bz { fall_through, .. } | Terminator::Bnz { fall_through, .. } => { + fall_through == header + } + _ => false, + }; + if chunks[hpos - 1].last().is_some_and(|&b| reaches_header(b)) { + return; + } + let latch = chunks[..hpos].iter().rposition(|c| { + c.len() == 1 + && matches!( + func.blocks[c[0] as usize].terminator, + Terminator::Jmp(t) | Terminator::FallThrough(t) if t == header + ) + }); + if let Some(lp) = latch { + let chunk = chunks.remove(lp); + chunks.insert(chunks.len() - 1, chunk); + } +} + +/// Layout order for the whole function: old block ids in the new +/// emission order. Blocks unreachable from the entry keep their +/// relative order at the tail. +fn layout_order(func: &FunctionSsa, loops: &[NaturalLoop], forest: &LoopForest) -> Vec { + let n = func.blocks.len(); + let mut placed = alloc::vec![false; n]; + let mut order: Vec = Vec::with_capacity(n); + lay_out(func, loops, forest, None, 0, &mut placed, &mut order); + for (b, done) in placed.iter().enumerate() { + if !done { + order.push(b as BlockId); + } + } + order +} + +/// Invert a conditional whose taken target is the next block in +/// layout so the emitters' next-block elision applies. The successor +/// set is unchanged. +fn invert_branches(func: &mut FunctionSsa) { + for i in 0..func.blocks.len() { + let next = (i + 1) as BlockId; + let term = &mut func.blocks[i].terminator; + match *term { + Terminator::Bz { + cond, + target, + fall_through, + } if target == next && fall_through != next => { + *term = Terminator::Bnz { + cond, + target: fall_through, + fall_through: target, + }; + } + Terminator::Bnz { + cond, + target, + fall_through, + } if target == next && fall_through != next => { + *term = Terminator::Bz { + cond, + target: fall_through, + fall_through: target, + }; + } + _ => {} + } + } +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::c5::ir::{Block, LoadKind, NO_VALUE}; + use alloc::vec; + + fn func_with(insts: Vec, blocks: Vec) -> FunctionSsa { + FunctionSsa { + inst_src: vec![(0, 0); insts.len()], + f32_values: vec![false; insts.len()], + insts, + blocks, + ..FunctionSsa::default() + } + } + + fn block(range: core::ops::Range, terminator: Terminator) -> Block { + Block { + start_pc: 0, + inst_range: range, + terminator, + exit_acc: NO_VALUE, + } + } + + /// Maximum number of emitted (non-elided) unconditional branches + /// on any unconditional chain inside a loop that ends at the + /// loop's header. + fn max_backedge_uncond_branches(func: &FunctionSsa) -> usize { + let rpo = rpo_numbers(func); + let idom = dominators(func); + let preds = predecessors(func); + let loops = natural_loops(func, &idom, &preds, &rpo); + let mut worst = 0; + for l in &loops { + for &b in &l.body { + let mut cur = b; + let mut count = 0usize; + let mut steps = 0usize; + while steps <= func.blocks.len() { + let Some(t) = uncond_target(&func.blocks[cur as usize].terminator) else { + break; + }; + if t != cur + 1 { + count += 1; + } + cur = t; + steps += 1; + if cur == l.header { + worst = worst.max(count); + break; + } + if !l.body.contains(&cur) { + break; + } + } + } + } + worst + } + + /// The walker's for-loop shape: entry(0) -> header(1) with + /// `Bz(after=4, body=3)`, post(2) -> header, body(3) -> post, + /// after(4) returns. One instruction per block so nothing is + /// empty except where noted. + fn for_loop_shape() -> FunctionSsa { + func_with( + vec![ + Inst::Imm(0), + Inst::Imm(1), + Inst::Imm(2), + Inst::Imm(3), + Inst::Imm(4), + ], + vec![ + block(0..1, Terminator::Jmp(1)), + block( + 1..2, + Terminator::Bz { + cond: 1, + target: 4, + fall_through: 3, + }, + ), + block(2..3, Terminator::Jmp(1)), + block(3..4, Terminator::Jmp(2)), + block(4..5, Terminator::Return(4)), + ], + ) + } + + #[test] + fn for_loop_rotates_to_bottom_test() { + let mut f = for_loop_shape(); + run_one(&mut f); + // Layout: entry, body, post, header, after. Old ids: 0 3 2 1 4. + assert_eq!(f.blocks.len(), 5); + // Entry branches to the rotated header at the loop bottom. + assert!(matches!(f.blocks[0].terminator, Terminator::Jmp(3))); + // body falls into post, post falls into the header. + assert!(matches!(f.blocks[1].terminator, Terminator::Jmp(2))); + assert!(matches!(f.blocks[2].terminator, Terminator::Jmp(3))); + // The rotated header inverted Bz -> Bnz: the back edge is the + // taken conditional, the exit falls through. + assert!(matches!( + f.blocks[3].terminator, + Terminator::Bnz { + target: 1, + fall_through: 4, + .. + } + )); + assert!(matches!(f.blocks[4].terminator, Terminator::Return(_))); + assert_eq!(max_backedge_uncond_branches(&f), 0); + } + + #[test] + fn rotated_loop_keeps_instructions_in_their_blocks() { + let mut f = for_loop_shape(); + run_one(&mut f); + // Each block kept its inst_range: old header's single Imm(1) + // now sits in layout block 3. + assert_eq!(f.blocks[3].inst_range, 1..2); + assert!(matches!(f.insts[1], Inst::Imm(1))); + } + + #[test] + fn phi_incoming_ids_follow_the_permutation() { + let mut f = for_loop_shape(); + // Give the post block a phi whose incoming names the body + // block (old id 3, which the layout renumbers to 1). + f.insts[2] = Inst::Phi { + incoming: vec![(3, 3)], + kind: LoadKind::I64, + }; + run_one(&mut f); + // Layout: entry, body, post, header, after (old 0 3 2 1 4); + // the post block keeps id 2, its incoming now names body = 1. + let Inst::Phi { incoming, .. } = &f.insts[2] else { + panic!("expected phi"); + }; + assert_eq!(incoming[0].0, 1); + } + + #[test] + fn empty_jump_chain_is_threaded() { + // b0 -Jmp-> b1(empty) -Jmp-> b2(empty) -Jmp-> b3(ret). + let mut f = func_with( + vec![Inst::Imm(0), Inst::Imm(3)], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..1, Terminator::Jmp(2)), + block(1..1, Terminator::Jmp(3)), + block(1..2, Terminator::Return(1)), + ], + ); + thread_jumps(&mut f); + assert!(matches!(f.blocks[0].terminator, Terminator::Jmp(3))); + } + + #[test] + fn threading_stops_before_a_phi_carrying_target() { + // b0 -Jmp-> b1(empty) -Jmp-> b2(phi). The edge may skip to b1 + // at most: b1 holds the phi moves for the b1 -> b2 edge. + let mut f = func_with( + vec![ + Inst::Imm(0), + Inst::Phi { + incoming: vec![(1, 0)], + kind: LoadKind::I64, + }, + ], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..1, Terminator::Jmp(2)), + block(1..2, Terminator::Return(1)), + ], + ); + thread_jumps(&mut f); + assert!(matches!(f.blocks[0].terminator, Terminator::Jmp(1))); + } + + #[test] + fn computed_goto_function_is_untouched() { + let mut f = for_loop_shape(); + f.computed_goto_targets = vec![1]; + let before: Vec<_> = f + .blocks + .iter() + .map(|b| alloc::format!("{:?}", b.terminator)) + .collect(); + run_one(&mut f); + let after: Vec<_> = f + .blocks + .iter() + .map(|b| alloc::format!("{:?}", b.terminator)) + .collect(); + assert_eq!(before, after); + } + + #[test] + fn irreducible_loop_is_left_in_source_order() { + // b0 branches into both b1 and b2, which branch to each other: + // a two-entry loop with no dominating header. + let mut f = func_with( + vec![Inst::Imm(0), Inst::Imm(1), Inst::Imm(2), Inst::Imm(3)], + vec![ + block( + 0..1, + Terminator::Bz { + cond: 0, + target: 2, + fall_through: 1, + }, + ), + block( + 1..2, + Terminator::Bz { + cond: 1, + target: 3, + fall_through: 2, + }, + ), + block( + 2..3, + Terminator::Bz { + cond: 2, + target: 3, + fall_through: 1, + }, + ), + block(3..4, Terminator::Return(3)), + ], + ); + let before: Vec<_> = f + .blocks + .iter() + .map(|b| alloc::format!("{:?}", b.terminator)) + .collect(); + run_one(&mut f); + let after: Vec<_> = f + .blocks + .iter() + .map(|b| alloc::format!("{:?}", b.terminator)) + .collect(); + assert_eq!(before, after); + } + + #[test] + fn do_while_shape_is_not_rotated() { + // entry(0) -> body(1) -> cond(2) -Bnz-> body, fall after(3). + // Already bottom-test; the header (body) must stay on top. + let mut f = func_with( + vec![Inst::Imm(0), Inst::Imm(1), Inst::Imm(2), Inst::Imm(3)], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..2, Terminator::Jmp(2)), + block( + 2..3, + Terminator::Bnz { + cond: 2, + target: 1, + fall_through: 3, + }, + ), + block(3..4, Terminator::Return(3)), + ], + ); + run_one(&mut f); + assert!(matches!(f.blocks[0].terminator, Terminator::Jmp(1))); + assert!(matches!(f.blocks[1].terminator, Terminator::Jmp(2))); + assert!(matches!( + f.blocks[2].terminator, + Terminator::Bnz { + target: 1, + fall_through: 3, + .. + } + )); + assert_eq!(max_backedge_uncond_branches(&f), 0); + } + + #[test] + fn two_continue_paths_carry_at_most_one_uncond_branch() { + // for-loop whose body splits twice, both arms jumping to the + // shared post block: entry(0) -> header(1) Bz(after=7, body=2); + // body(2) Bz(c1=3, c2=4); c1(3) -Jmp-> post(5); c2(4) -Jmp-> + // post(5); post(5) -Jmp-> header; unused(6); after(7). + let mut f = func_with( + (0..8i64).map(Inst::Imm).collect(), + vec![ + block(0..1, Terminator::Jmp(1)), + block( + 1..2, + Terminator::Bz { + cond: 1, + target: 7, + fall_through: 2, + }, + ), + block( + 2..3, + Terminator::Bz { + cond: 2, + target: 3, + fall_through: 4, + }, + ), + block(3..4, Terminator::Jmp(5)), + block(4..5, Terminator::Jmp(5)), + block(5..6, Terminator::Jmp(1)), + block(6..7, Terminator::Return(6)), + block(7..8, Terminator::Return(7)), + ], + ); + run_one(&mut f); + assert!(max_backedge_uncond_branches(&f) <= 1); + } + + #[test] + fn nested_loop_bodies_stay_contiguous() { + // outer: header(1) Bz(after=6, body=2); inner loop inside the + // outer body: header(2) Bz(back-to-outer=5, body=3); inner + // body(3) -> inner post(4) -> inner header; outer post(5) -> + // outer header; after(6). + let mut f = func_with( + (0..7i64).map(Inst::Imm).collect(), + vec![ + block(0..1, Terminator::Jmp(1)), + block( + 1..2, + Terminator::Bz { + cond: 1, + target: 6, + fall_through: 2, + }, + ), + block( + 2..3, + Terminator::Bz { + cond: 2, + target: 5, + fall_through: 3, + }, + ), + block(3..4, Terminator::Jmp(4)), + block(4..5, Terminator::Jmp(2)), + block(5..6, Terminator::Jmp(1)), + block(6..7, Terminator::Return(6)), + ], + ); + run_one(&mut f); + assert_eq!(max_backedge_uncond_branches(&f), 0); + // Recover the inner loop on the permuted function and check + // its blocks are adjacent in layout. + let rpo = rpo_numbers(&f); + let idom = dominators(&f); + let preds = predecessors(&f); + let loops = natural_loops(&f, &idom, &preds, &rpo); + assert_eq!(loops.len(), 2); + let inner = loops.iter().min_by_key(|l| l.body.len()).unwrap(); + let ids: Vec = inner.body.iter().copied().collect(); + let span = *ids.last().unwrap() - ids[0] + 1; + assert_eq!(span as usize, ids.len(), "inner loop must be contiguous"); + } + + #[test] + fn block_addr_remap_covered_by_permutation_utility() { + // The layout pass skips computed-goto functions; the shared + // permutation utility still remaps `BlockAddr` for callers + // that reorder such functions (see remap_blocks tests). + let mut f = func_with( + vec![Inst::BlockAddr(1), Inst::Imm(1)], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..2, Terminator::Return(1)), + ], + ); + super::super::remap_blocks::permute_blocks(&mut f, &[1, 0]); + assert!(matches!(f.insts[0], Inst::BlockAddr(0))); + } +} diff --git a/src/c5/codegen/passes/mod.rs b/src/c5/codegen/passes/mod.rs index c6c8dcd80..70a0b5598 100644 --- a/src/c5/codegen/passes/mod.rs +++ b/src/c5/codegen/passes/mod.rs @@ -2,13 +2,18 @@ //! `FunctionSsa` in place and is target-neutral; the per-target lowering //! drivers run a selection of them before instruction selection. +pub(crate) mod constfold; pub(crate) mod constfold_branch; pub(crate) mod dedup_imm; pub(crate) mod drop_redundant_extend; pub(crate) mod fma; pub(crate) mod index_fold; pub(crate) mod inline; +pub(crate) mod layout; +pub(crate) mod remap_blocks; pub(crate) mod rotate; pub(crate) mod split_crit_edges; +pub(crate) mod sroa; pub(crate) mod store_forward; pub(crate) mod struct_return_reg; +pub(crate) mod unroll; diff --git a/src/c5/codegen/passes/remap_blocks.rs b/src/c5/codegen/passes/remap_blocks.rs new file mode 100644 index 000000000..48257252e --- /dev/null +++ b/src/c5/codegen/passes/remap_blocks.rs @@ -0,0 +1,202 @@ +//! Block permutation and block-id remapping. +//! +//! [`permute_blocks`] reorders `func.blocks` and rewrites every +//! block-id reference to the new numbering. Instructions never move +//! between blocks: each block keeps its `inst_range` slice of the +//! flat `insts` array, so value ids, liveness, and the allocator's +//! input are unaffected. The complete block-id reference surface is +//! the terminators' targets (`Jmp`, `Bz`, `Bnz`, `FallThrough`), +//! `Phi::incoming` predecessor ids, `Inst::BlockAddr`, +//! `FunctionSsa::computed_goto_targets`, and the +//! `FunctionSsa::jump_tables` target lists (`Terminator::JumpTable` +//! itself carries only the table index). + +use alloc::vec::Vec; + +use crate::c5::ir::{BlockId, FunctionSsa, Inst, Terminator}; + +/// Reorder `func.blocks` so old block `order[i]` becomes block `i`, +/// remapping every block-id reference. `order` must be a permutation +/// of `0..func.blocks.len()`. +pub(crate) fn permute_blocks(func: &mut FunctionSsa, order: &[BlockId]) { + let n = func.blocks.len(); + assert_eq!(order.len(), n, "order must cover every block"); + let mut new_id: Vec = alloc::vec![BlockId::MAX; n]; + for (new_idx, &old) in order.iter().enumerate() { + assert!( + (old as usize) < n && new_id[old as usize] == BlockId::MAX, + "order must be a permutation of the block ids" + ); + new_id[old as usize] = new_idx as BlockId; + } + func.blocks = order + .iter() + .map(|&old| func.blocks[old as usize].clone()) + .collect(); + remap_block_ids(func, &new_id); +} + +/// Rewrite every block-id reference through `new_id` (indexed by the +/// old id). The caller has already reordered `func.blocks` to match. +pub(crate) fn remap_block_ids(func: &mut FunctionSsa, new_id: &[BlockId]) { + for block in func.blocks.iter_mut() { + match &mut block.terminator { + Terminator::Jmp(t) | Terminator::FallThrough(t) => *t = new_id[*t as usize], + Terminator::Bz { + target, + fall_through, + .. + } + | Terminator::Bnz { + target, + fall_through, + .. + } => { + *target = new_id[*target as usize]; + *fall_through = new_id[*fall_through as usize]; + } + Terminator::Return(_) + | Terminator::TailExt(_) + | Terminator::GotoIndirect { .. } + | Terminator::JumpTable { .. } => {} + } + } + for inst in func.insts.iter_mut() { + match inst { + Inst::BlockAddr(b) => *b = new_id[*b as usize], + Inst::Phi { incoming, .. } => { + for (b, _) in incoming.iter_mut() { + *b = new_id[*b as usize]; + } + } + _ => {} + } + } + for table in func.jump_tables.iter_mut() { + for t in table.iter_mut() { + *t = new_id[*t as usize]; + } + } + for t in func.computed_goto_targets.iter_mut() { + *t = new_id[*t as usize]; + } +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::c5::ir::{Block, LoadKind, NO_VALUE}; + use alloc::vec; + + fn func_with(insts: Vec, blocks: Vec) -> FunctionSsa { + FunctionSsa { + inst_src: vec![(0, 0); insts.len()], + f32_values: vec![false; insts.len()], + insts, + blocks, + ..FunctionSsa::default() + } + } + + fn block(range: core::ops::Range, terminator: Terminator) -> Block { + Block { + start_pc: 0, + inst_range: range, + terminator, + exit_acc: NO_VALUE, + } + } + + #[test] + fn permutation_remaps_jump_table_targets() { + let mut f = func_with( + vec![Inst::Imm(0)], + vec![ + block(0..1, Terminator::JumpTable { idx: 0, table: 0 }), + block(1..1, Terminator::Return(NO_VALUE)), + block(1..1, Terminator::Return(NO_VALUE)), + ], + ); + f.jump_tables = vec![vec![1, 2, 1]]; + permute_blocks(&mut f, &[0, 2, 1]); + assert_eq!(f.jump_tables[0], vec![2, 1, 2]); + assert!(matches!( + f.blocks[0].terminator, + Terminator::JumpTable { table: 0, .. } + )); + } + + #[test] + fn permutation_remaps_terminators_phis_block_addrs_and_goto_targets() { + // b0 -> b1 -> b2(ret); b1 holds a phi from b0 and a BlockAddr(2). + let mut f = func_with( + vec![ + Inst::Imm(1), + Inst::Phi { + incoming: vec![(0, 0)], + kind: LoadKind::I64, + }, + Inst::BlockAddr(2), + ], + vec![ + block(0..1, Terminator::Jmp(1)), + block( + 1..3, + Terminator::Bz { + cond: 1, + target: 2, + fall_through: 1, + }, + ), + block(3..3, Terminator::Return(NO_VALUE)), + ], + ); + f.computed_goto_targets = vec![2]; + // New order: [0, 2, 1] -- old b2 becomes b1, old b1 becomes b2. + permute_blocks(&mut f, &[0, 2, 1]); + assert!(matches!(f.blocks[0].terminator, Terminator::Jmp(2))); + assert!(matches!(f.blocks[1].terminator, Terminator::Return(_))); + assert!(matches!( + f.blocks[2].terminator, + Terminator::Bz { + target: 1, + fall_through: 2, + .. + } + )); + let Inst::Phi { incoming, .. } = &f.insts[1] else { + panic!("expected phi"); + }; + assert_eq!(incoming[0].0, 0); + assert!(matches!(f.insts[2], Inst::BlockAddr(1))); + assert_eq!(f.computed_goto_targets, vec![1]); + // Instructions did not move: block ranges follow their blocks. + assert_eq!(f.blocks[2].inst_range, 1..3); + } + + #[test] + #[should_panic(expected = "permutation")] + fn duplicate_entry_in_order_panics() { + let mut f = func_with( + vec![Inst::Imm(0)], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..1, Terminator::Return(NO_VALUE)), + ], + ); + permute_blocks(&mut f, &[0, 0]); + } + + #[test] + #[should_panic(expected = "cover every block")] + fn short_order_panics() { + let mut f = func_with( + vec![Inst::Imm(0)], + vec![ + block(0..1, Terminator::Jmp(1)), + block(1..1, Terminator::Return(NO_VALUE)), + ], + ); + permute_blocks(&mut f, &[0]); + } +} diff --git a/src/c5/codegen/passes/split_crit_edges.rs b/src/c5/codegen/passes/split_crit_edges.rs index 68a5d6f68..13d86dd43 100644 --- a/src/c5/codegen/passes/split_crit_edges.rs +++ b/src/c5/codegen/passes/split_crit_edges.rs @@ -39,13 +39,18 @@ fn run_one(func: &mut FunctionSsa) { // block ids, which `Inst::BlockAddr` and computed_goto_targets // reference directly. Such functions carry no phis (mem2reg is // skipped for them), so there are no critical edges to split. + // Jump-table functions are NOT skipped: split blocks are appended + // (existing ids stay stable) and table entries are retargetable, + // so an edge from the dispatcher to a phi-carrying case block is + // split like any other -- without it, `emit_phi_predecessor_moves` + // would emit every case block's moves at the dispatcher exit. if !func.computed_goto_targets.is_empty() { return; } // Count predecessors per block. Walking terminators is enough. let mut pred_count: Vec = alloc::vec![0; n_original]; for block in &func.blocks { - for succ in successors(&block.terminator) { + for succ in successors(&block.terminator, &func.jump_tables) { if (succ as usize) < n_original { pred_count[succ as usize] += 1; } @@ -55,7 +60,7 @@ fn run_one(func: &mut FunctionSsa) { // while we walk it. Each entry is `(pred, original_succ)`. let mut splits: Vec<(BlockId, BlockId)> = Vec::new(); for (idx, block) in func.blocks.iter().enumerate().take(n_original) { - let succs = successors(&block.terminator); + let succs = successors(&block.terminator, &func.jump_tables); if succs.len() < 2 { continue; } @@ -137,6 +142,17 @@ fn run_one(func: &mut FunctionSsa) { fall_through }, }, + // Retarget every table entry naming the split successor; + // repeated entries (case-value holes on the default block) + // all route through the one synthetic block. + Terminator::JumpTable { table, .. } => { + for t in func.jump_tables[table as usize].iter_mut() { + if *t == original_succ { + *t = new_id; + } + } + term + } other => other, }; func.blocks[pred as usize].terminator = new_term; @@ -160,7 +176,7 @@ fn run_one(func: &mut FunctionSsa) { } } -fn successors(term: &Terminator) -> Vec { +fn successors(term: &Terminator, jump_tables: &[Vec]) -> Vec { match term { Terminator::Jmp(b) | Terminator::FallThrough(b) => alloc::vec![*b], Terminator::Bz { @@ -173,6 +189,17 @@ fn successors(term: &Terminator) -> Vec { fall_through, .. } => alloc::vec![*target, *fall_through], + // Distinct targets only, so a table's repeated entries yield + // one split per (pred, succ) edge. + Terminator::JumpTable { table, .. } => { + let mut out: Vec = Vec::new(); + for &t in &jump_tables[*table as usize] { + if !out.contains(&t) { + out.push(t); + } + } + out + } // This pass is skipped for functions with a computed goto (its // run() guards on computed_goto_targets), so an indirect branch // never reaches here; its successors live on the function, not @@ -208,8 +235,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), @@ -383,4 +413,67 @@ mod tests { run_one(&mut f); assert_eq!(f.blocks[3].exit_acc, NO_VALUE); } + + #[test] + fn jump_table_entries_retargeted_to_trampoline() { + // b0 -[JumpTable [1, 2, 1]]-> b1 (phi), b2 (no phi) + // b3 -[Jmp]-> b1 + // b1 has two predecessors and a phi, so both table entries + // naming it must retarget to one synthetic trampoline; the + // phi's b0 incoming renames to the trampoline. b2 has a + // single predecessor and stays a direct entry. + let mut f = fresh( + vec![ + Inst::Imm(0), + Inst::Phi { + incoming: alloc::vec![(0, 0), (3, 3)], + kind: LoadKind::I64, + }, + Inst::Imm(2), + Inst::Imm(3), + ], + vec![ + Block { + start_pc: 0, + inst_range: 0..1, + terminator: Terminator::JumpTable { idx: 0, table: 0 }, + exit_acc: 0, + }, + Block { + start_pc: 0, + inst_range: 1..2, + terminator: Terminator::Return(1), + exit_acc: 1, + }, + Block { + start_pc: 0, + inst_range: 2..3, + terminator: Terminator::Return(2), + exit_acc: 2, + }, + Block { + start_pc: 0, + inst_range: 3..4, + terminator: Terminator::Jmp(1), + exit_acc: 3, + }, + ], + ); + f.jump_tables = alloc::vec![alloc::vec![1, 2, 1]]; + run_one(&mut f); + assert_eq!(f.blocks.len(), 5); + assert!(matches!( + f.blocks[0].terminator, + Terminator::JumpTable { idx: 0, table: 0 } + )); + assert_eq!(f.jump_tables[0], alloc::vec![4, 2, 4]); + assert!(matches!(f.blocks[4].terminator, Terminator::Jmp(1))); + assert_eq!(f.blocks[4].inst_range.len(), 0); + let Inst::Phi { incoming, .. } = &f.insts[1] else { + panic!("expected phi"); + }; + assert!(incoming.iter().any(|(b, _)| *b == 4)); + assert!(incoming.iter().any(|(b, _)| *b == 3)); + assert!(!incoming.iter().any(|(b, _)| *b == 0)); + } } diff --git a/src/c5/codegen/passes/sroa.rs b/src/c5/codegen/passes/sroa.rs new file mode 100644 index 000000000..afc79776e --- /dev/null +++ b/src/c5/codegen/passes/sroa.rs @@ -0,0 +1,549 @@ +//! Scalar promotion of constant-index local arrays (SROA-lite). +//! +//! Runs under `-O` after the constant folder, on functions the unroll +//! pass expanded (`FunctionSsa::did_unroll`). Full unrolling of a +//! constant-trip loop turns each array subscript `a[j]` into a constant +//! byte offset from the array's base slot, so the frame round-trip that +//! kept the array memory-resident is removable. mem2reg leaves such an +//! array in memory because its base address is taken (`LocalAddr`), so +//! this pass rewrites every constant-offset, full-width access into a +//! per-element `LoadLocal` / `StoreLocal` against the element's own +//! frame slot and re-runs mem2reg, which promotes the now address-free +//! element slots to SSA values (and inserts phis across any surrounding +//! loop). +//! +//! A local aggregate is split only when every access through its base +//! address is a non-volatile, full-width (8-byte), 8-byte-aligned, +//! in-bounds constant offset and the address never otherwise escapes (to +//! a call, a stored pointer, an `Mcpy`, a comparison, or a runtime-index +//! computation). An 8-byte element at byte offset `k*8` from base slot +//! `S` occupies frame slot `S + k` (locals sit at `off * 8` bytes from +//! the frame pointer, `emit_common::c5_slot_to_fp_offset`), so the +//! rewrite reuses storage the frame already reserved -- no new slot is +//! allocated. The now-dead base-address instructions are neutralised to +//! `Imm(0)` so mem2reg's address-taken scan no longer pins the base slot. + +use alloc::collections::{BTreeMap, BTreeSet}; +use alloc::vec::Vec; + +use crate::c5::codegen::ssa::reg_alloc::for_each_operand; +use crate::c5::ir::{BinOp, FunctionSsa, Inst, LoadKind, NO_VALUE, StoreKind, Terminator, ValueId}; + +/// Split constant-index local arrays into per-element scalar slots and +/// re-run mem2reg to promote them. Returns the base slots of arrays that +/// were fully promoted (every element lifted to a register), for the +/// debug-info emitter to drop their now-stale frame location. +pub(crate) fn run(func: &mut FunctionSsa, usable_gpr: usize) -> Vec { + // mem2reg leaves computed-goto functions unpromoted; keep this pass + // consistent so its split can never strand a slot the re-run refuses + // to lift. + if !func.computed_goto_targets.is_empty() { + return Vec::new(); + } + let split = split_arrays(func, usable_gpr); + if split.is_empty() { + return Vec::new(); + } + // The split produced address-free element slots; the mem2reg re-run + // promotes them (a full pruned-SSA rebuild, confined to this function + // by the did_unroll gate at the call site). + let promoted: BTreeSet = crate::c5::codegen::ssa::mem2reg::run(func) + .into_iter() + .collect(); + // Report an array base as promoted only when every element slot was + // lifted; a partially promoted array keeps a live frame location the + // debug info must still point at. + let mut fully: Vec = Vec::new(); + for (base, cells) in split { + if (0..cells).all(|k| promoted.contains(&(base + k))) { + fully.push(base); + } + } + fully +} + +/// A constant-offset, full-width access to split, resolved to its +/// per-element frame slot. +struct Access { + id: u32, + base: i64, + slot: i64, + store: bool, +} + +/// Rewrite every splittable array's accesses to per-element LoadLocal / +/// StoreLocal and neutralise the dead base-address instructions. Returns +/// `(base_slot, cells)` for each array actually split. Splits nothing +/// when the total element count would exceed `budget` (the target's +/// usable GPR file), since the mem2reg re-run would then spill the +/// loop-carried phis back to the frame at a net loss. +fn split_arrays(func: &mut FunctionSsa, budget: usize) -> Vec<(i64, i64)> { + // Candidate array bases: declared / synthetic multi-cell locals. The + // parser records each as `(base, cells)` with `base` the lowest cell. + // A base repeated across disjoint scopes takes the smallest cell count + // so an access is bounds-checked against every occupant. + let mut cells_of: BTreeMap = BTreeMap::new(); + for &(base, cells) in &func.multi_cell_slots { + if base < 0 && cells >= 1 { + cells_of + .entry(base) + .and_modify(|c| *c = (*c).min(cells)) + .or_insert(cells); + } + } + if cells_of.is_empty() { + return Vec::new(); + } + + // Resolve every value to its (base_slot, byte_offset) when it is an + // address expression rooted at a `LocalAddr` through constant Add / + // Sub chains; None otherwise. Memoised with an in-progress guard + // against the cyclic references the unordered SSA tape may carry. + let n = func.insts.len(); + let mut state: Vec = alloc::vec![0u8; n]; + let mut resolved: Vec> = alloc::vec![None; n]; + for v in 0..n { + resolve_addr(&func.insts, v as ValueId, &mut state, &mut resolved); + } + let base_of = |v: ValueId| -> Option { + resolved + .get(v as usize) + .copied() + .flatten() + .map(|(b, _)| b) + .filter(|b| cells_of.contains_key(b)) + }; + + // A base drops out the moment any access or use fails a condition. + let mut unsafe_base: BTreeSet = BTreeSet::new(); + let mut accesses: Vec = Vec::new(); + + for (i, inst) in func.insts.iter().enumerate() { + match inst { + // An address expression built by a constant Add / Sub is a + // safe intermediate: its address operand is skipped here and + // its result is validated through the uses of `i`. + Inst::BinopI { + op: BinOp::Add | BinOp::Sub, + .. + } + | Inst::Binop { + op: BinOp::Add | BinOp::Sub, + .. + } if resolved[i].is_some() => {} + Inst::Load { + addr, + disp, + kind, + volatile, + } => { + if let Some((base, off)) = resolved.get(*addr as usize).copied().flatten() + && cells_of.contains_key(&base) + { + match check_access(base, off + *disp as i64, load_is_word(*kind), &cells_of) { + Some(slot) if !*volatile => accesses.push(Access { + id: i as u32, + base, + slot, + store: false, + }), + _ => { + unsafe_base.insert(base); + } + } + } + } + Inst::Store { + addr, + disp, + value, + kind, + volatile, + } => { + if let Some((base, off)) = resolved.get(*addr as usize).copied().flatten() + && cells_of.contains_key(&base) + { + match check_access(base, off + *disp as i64, store_is_word(*kind), &cells_of) { + Some(slot) if !*volatile => accesses.push(Access { + id: i as u32, + base, + slot, + store: true, + }), + _ => { + unsafe_base.insert(base); + } + } + } + // The stored value being an address escapes that base. + if let Some(base) = base_of(*value) { + unsafe_base.insert(base); + } + } + other => { + for_each_operand(other, |v| { + if let Some(base) = base_of(v) { + unsafe_base.insert(base); + } + }); + } + } + } + // A base address reaching a terminator or block accumulator escapes. + for block in &func.blocks { + let v = match &block.terminator { + Terminator::Return(v) + | Terminator::Bz { cond: v, .. } + | Terminator::Bnz { cond: v, .. } + | Terminator::GotoIndirect { target: v } + | Terminator::JumpTable { idx: v, .. } => *v, + _ => NO_VALUE, + }; + if let Some(base) = base_of(v) { + unsafe_base.insert(base); + } + if let Some(base) = base_of(block.exit_acc) { + unsafe_base.insert(base); + } + } + + // Bases that survived every check and carry at least one access. + let mut split: BTreeMap = BTreeMap::new(); + for a in &accesses { + if !unsafe_base.contains(&a.base) { + split.insert(a.base, cells_of[&a.base]); + } + } + if split.is_empty() { + return Vec::new(); + } + // Register-budget gate: promoting more element slots than the target's + // GPR file holds spills the loop-carried phis back to the frame at a + // net loss, so leave the arrays memory-resident when the split would + // overflow the budget. Nothing is mutated on this path. + let total: i64 = split.values().copied().sum(); + if total > budget as i64 { + return Vec::new(); + } + // Commit: rewrite each surviving access to its per-element slot. + for a in &accesses { + if !split.contains_key(&a.base) { + continue; + } + let inst = &mut func.insts[a.id as usize]; + if a.store { + if let Inst::Store { value, kind, .. } = *inst { + *inst = Inst::StoreLocal { + off: a.slot, + value, + kind, + volatile: false, + }; + } + } else if let Inst::Load { kind, .. } = *inst { + *inst = Inst::LoadLocal { + off: a.slot, + kind, + volatile: false, + }; + } + } + // Neutralise the now-dead base-address expressions of every split + // base: every consumer was a rewritten access or another address + // expression, so the value has no live use. + for (v, r) in resolved.iter().enumerate() { + if let Some((base, _)) = r + && split.contains_key(base) + { + func.insts[v] = Inst::Imm(0); + } + } + split.into_iter().collect() +} + +/// The frame slot an 8-byte access at `total_off` bytes from base slot +/// `base` maps to, when the access is full-width, 8-byte-aligned, and in +/// bounds. `None` otherwise. +fn check_access( + base: i64, + total_off: i64, + is_word: bool, + cells_of: &BTreeMap, +) -> Option { + if !is_word || total_off < 0 || total_off % 8 != 0 { + return None; + } + let k = total_off / 8; + let cells = *cells_of.get(&base)?; + if k >= cells { + return None; + } + Some(base + k) +} + +fn load_is_word(k: LoadKind) -> bool { + matches!(k, LoadKind::I64 | LoadKind::F64) +} + +fn store_is_word(k: StoreKind) -> bool { + matches!(k, StoreKind::I64 | StoreKind::F64) +} + +/// Resolve `v` to `(base_slot, byte_offset)` when it is a `LocalAddr` +/// plus a chain of constant Add / Sub, else `None`. Memoised; `state` +/// holds 0 (unvisited), 1 (in progress -- a cycle, treated as None), or +/// 2 (done). +fn resolve_addr( + insts: &[Inst], + v: ValueId, + state: &mut [u8], + resolved: &mut [Option<(i64, i64)>], +) -> Option<(i64, i64)> { + let vi = v as usize; + if vi >= insts.len() { + return None; + } + match state[vi] { + 1 => return None, + 2 => return resolved[vi], + _ => {} + } + state[vi] = 1; + let imm = |id: ValueId| -> Option { + match insts.get(id as usize) { + Some(Inst::Imm(k)) => Some(*k), + _ => None, + } + }; + let r = match &insts[vi] { + Inst::LocalAddr(s) => Some((*s, 0)), + Inst::BinopI { + op: BinOp::Add, + lhs, + rhs_imm, + } => resolve_addr(insts, *lhs, state, resolved).map(|(s, o)| (s, o + *rhs_imm)), + Inst::BinopI { + op: BinOp::Sub, + lhs, + rhs_imm, + } => resolve_addr(insts, *lhs, state, resolved).map(|(s, o)| (s, o - *rhs_imm)), + Inst::Binop { + op: BinOp::Add, + lhs, + rhs, + } => { + if let Some(c) = imm(*rhs) { + resolve_addr(insts, *lhs, state, resolved).map(|(s, o)| (s, o + c)) + } else if let Some(c) = imm(*lhs) { + resolve_addr(insts, *rhs, state, resolved).map(|(s, o)| (s, o + c)) + } else { + None + } + } + Inst::Binop { + op: BinOp::Sub, + lhs, + rhs, + } => { + if let Some(c) = imm(*rhs) { + resolve_addr(insts, *lhs, state, resolved).map(|(s, o)| (s, o - c)) + } else { + None + } + } + _ => None, + }; + state[vi] = 2; + resolved[vi] = r; + r +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::c5::ir::{Block, Terminator}; + + fn func(insts: Vec, term: Terminator, multi_cell: Vec<(i64, i64)>) -> FunctionSsa { + let n = insts.len() as u32; + FunctionSsa { + inst_src: alloc::vec![(0, 0); insts.len()], + f32_values: alloc::vec![false; insts.len()], + insts, + blocks: alloc::vec![Block { + start_pc: 0, + inst_range: 0..n, + terminator: term, + exit_acc: NO_VALUE, + }], + multi_cell_slots: multi_cell, + ..FunctionSsa::default() + } + } + + fn store(addr: ValueId, value: ValueId) -> Inst { + Inst::Store { + addr, + disp: 0, + value, + kind: StoreKind::I64, + volatile: false, + } + } + fn load(addr: ValueId) -> Inst { + Inst::Load { + addr, + disp: 0, + kind: LoadKind::I64, + volatile: false, + } + } + fn add_imm(lhs: ValueId, k: i64) -> Inst { + Inst::BinopI { + op: BinOp::Add, + lhs, + rhs_imm: k, + } + } + + /// Two-element local array `a` at base slot -2: a[0]=v0 via + /// LocalAddr(-2), a[1]=v3 via LocalAddr(-2)+8, then read back. + fn two_elem_array() -> FunctionSsa { + let insts = alloc::vec![ + Inst::Imm(5), // v0 + Inst::LocalAddr(-2), // v1 + store(1, 0), // v2 a[0] = 5 + Inst::Imm(7), // v3 + Inst::LocalAddr(-2), // v4 + add_imm(4, 8), // v5 &a[1] + store(5, 3), // v6 a[1] = 7 + Inst::LocalAddr(-2), // v7 + load(7), // v8 a[0] + Inst::LocalAddr(-2), // v9 + add_imm(9, 8), // v10 &a[1] + load(10), // v11 a[1] + Inst::Binop { + op: BinOp::Add, + lhs: 8, + rhs: 11, + }, // v12 a[0] + a[1] + ]; + func(insts, Terminator::Return(12), alloc::vec![(-2, 2)]) + } + + #[test] + fn const_index_array_splits_and_promotes() { + let mut f = two_elem_array(); + let promoted = run(&mut f, 64); + assert_eq!(promoted, alloc::vec![-2], "the array's base slot promotes"); + // No frame access to the array survives after promotion. + for inst in &f.insts { + assert!( + !matches!( + inst, + Inst::LoadLocal { off: -2 | -1, .. } | Inst::StoreLocal { off: -2 | -1, .. } + ) || matches!(inst, Inst::LoadLocal { .. }), + "no live StoreLocal to the array may remain" + ); + } + assert!( + !f.insts + .iter() + .any(|i| matches!(i, Inst::StoreLocal { off: -2 | -1, .. })), + "promoted stores are neutralised" + ); + } + + #[test] + fn dead_local_addr_neutralised() { + let mut f = two_elem_array(); + let split = split_arrays(&mut f, 64); + assert_eq!(split, alloc::vec![(-2, 2)]); + // Store/Load rewritten to per-element slots (-2 for a[0], -1 for a[1]). + assert!(matches!(f.insts[2], Inst::StoreLocal { off: -2, .. })); + assert!(matches!(f.insts[6], Inst::StoreLocal { off: -1, .. })); + assert!(matches!(f.insts[8], Inst::LoadLocal { off: -2, .. })); + assert!(matches!(f.insts[11], Inst::LoadLocal { off: -1, .. })); + // Base-address instructions (LocalAddr + Add) neutralised. + for id in [1usize, 4, 5, 7, 9, 10] { + assert!( + matches!(f.insts[id], Inst::Imm(0)), + "address expr v{id} must be neutralised, got {:?}", + f.insts[id] + ); + } + } + + #[test] + fn over_budget_array_not_split() { + // The two-element array needs 2 register slots; a budget of 1 + // leaves it memory-resident (the re-run would spill it back). + let mut f = two_elem_array(); + let before = alloc::format!("{:?}", f.insts); + let split = split_arrays(&mut f, 1); + assert!(split.is_empty(), "over-budget array must not split"); + assert_eq!(before, alloc::format!("{:?}", f.insts), "tape unchanged"); + } + + #[test] + fn runtime_index_array_not_split() { + // a[0]=v0 (constant), then a load at a runtime offset. + let insts = alloc::vec![ + Inst::Imm(5), // v0 + Inst::LocalAddr(-2), // v1 + store(1, 0), // v2 a[0]=5 + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64, + }, // v3 runtime k + Inst::LocalAddr(-2), // v4 + Inst::Binop { + op: BinOp::Add, + lhs: 4, + rhs: 3, + }, // v5 &a[k] (runtime) + load(5), // v6 + ]; + let mut f = func(insts, Terminator::Return(6), alloc::vec![(-2, 2)]); + let before = alloc::format!("{:?}", f.insts); + let split = split_arrays(&mut f, 64); + assert!(split.is_empty(), "runtime-index array must not split"); + assert_eq!(before, alloc::format!("{:?}", f.insts), "tape unchanged"); + } + + #[test] + fn escaped_address_array_not_split() { + // Const-index stores plus the base address escaping through the + // terminator: the whole array must stay memory-resident. + let insts = alloc::vec![ + Inst::Imm(5), // v0 + Inst::LocalAddr(-2), // v1 + store(1, 0), // v2 a[0]=5 + Inst::LocalAddr(-2), // v3 escapes below + ]; + let mut f = func(insts, Terminator::Return(3), alloc::vec![(-2, 2)]); + let before = alloc::format!("{:?}", f.insts); + let split = split_arrays(&mut f, 64); + assert!(split.is_empty(), "escaped-address array must not split"); + assert_eq!(before, alloc::format!("{:?}", f.insts), "tape unchanged"); + } + + #[test] + fn function_without_candidate_arrays_untouched() { + // No multi-cell locals: nothing to scalarize, and the mem2reg + // re-run never fires (mirrors a function the unroll pass left with + // no constant-index array). + let insts = alloc::vec![ + Inst::Imm(1), + Inst::LoadLocal { + off: 2, + kind: LoadKind::I64, + volatile: false, + }, + ]; + let mut f = func(insts, Terminator::Return(1), alloc::vec![]); + let before = alloc::format!("{:?}", f.insts); + let promoted = run(&mut f, 64); + assert!(promoted.is_empty()); + assert_eq!(before, alloc::format!("{:?}", f.insts), "tape unchanged"); + } +} diff --git a/src/c5/codegen/passes/store_forward.rs b/src/c5/codegen/passes/store_forward.rs index 05865988f..8410eb820 100644 --- a/src/c5/codegen/passes/store_forward.rs +++ b/src/c5/codegen/passes/store_forward.rs @@ -38,8 +38,21 @@ //! would be unsound. //! A load forwards from an earlier load only when the load kinds match //! exactly, so the extension already applied is the one wanted. +//! +//! Frame slots (`StoreLocal` / `LoadLocal`) are tracked in a second +//! table keyed by slot index, with the same width, volatile, and +//! distance discipline. A slot participates only when nothing but +//! `LoadLocal` / `StoreLocal` can reach it: no `LocalAddr`, no volatile +//! access (`mem2reg::promotable_slots`), and no write through a +//! `FunctionSsa` field or call result slot. Such a slot's address is +//! never a value, so no `Store`, `Mcpy`, or atomic can write it; its +//! entries survive those instructions and die at another `StoreLocal` +//! to the same slot, at a call (a reload after the call is cheaper +//! than keeping the value live across it), or at the block boundary. +use crate::c5::codegen::ssa::mem2reg::promotable_slots; use crate::c5::ir::{FunctionSsa, Inst, LoadKind, NO_VALUE, StoreKind, Terminator, ValueId}; +use alloc::collections::BTreeSet; use alloc::vec::Vec; /// Access width in bytes for a load kind. @@ -100,6 +113,55 @@ struct Entry { load_kind: Option, } +/// A known-available frame-slot value within the current block. Slots +/// are 8-byte cells and every `LoadLocal` / `StoreLocal` accesses a +/// slot from its base, so entries for distinct slots are disjoint and +/// any two accesses of one slot overlap. +#[derive(Clone, Copy)] +struct SlotEntry { + off: i64, + width: u8, + value: ValueId, + src_idx: u32, + /// As [`Entry::load_kind`]. + load_kind: Option, +} + +/// Slots whose store -> load pairs may forward: reachable only through +/// `LoadLocal` / `StoreLocal`, so every write is visible in the SSA. +/// Starts from `mem2reg::promotable_slots` (no `LocalAddr`, no volatile +/// access, no alloca-arena slot) and removes the slots the emit writes +/// through `FunctionSsa` fields or call metadata rather than an +/// instruction. A function with a runtime-growing frame is skipped +/// entirely, as in mem2reg. +fn forwardable_slots(func: &FunctionSsa) -> BTreeSet { + if func + .insts + .iter() + .any(|i| matches!(i, Inst::AllocaInit(s) if *s != 0)) + { + return BTreeSet::new(); + } + let mut slots = promotable_slots(func); + slots.remove(&func.indirect_result_slot); + for s in &func.param_local_slots { + slots.remove(s); + } + for inst in &func.insts { + match inst { + Inst::Call { ret_slot_local, .. } + | Inst::CallIndirect { ret_slot_local, .. } + | Inst::CallExt { ret_slot_local, .. } + if *ret_slot_local != 0 => + { + slots.remove(ret_slot_local); + } + _ => {} + } + } + slots +} + /// Byte ranges `[a, a+aw)` and `[b, b+bw)` overlap. fn overlaps(a: i32, aw: u8, b: i32, bw: u8) -> bool { let a_end = a as i64 + aw as i64; @@ -124,9 +186,11 @@ fn run_one(func: &mut FunctionSsa) { // Loads replaced in place by an `Extend` of the stored value. let mut rewrites: Vec<(usize, Inst)> = Vec::new(); let mut any = false; + let slots = forwardable_slots(func); for block in &func.blocks { let mut table: Vec = Vec::new(); + let mut slot_table: Vec = Vec::new(); for idx in block.inst_range.clone() { let i = idx as usize; if i >= func.insts.len() { @@ -237,10 +301,92 @@ fn run_one(func: &mut FunctionSsa) { }); } } + // A volatile slot access is never tracked; its slot is + // outside `forwardable_slots`. A volatile load reads + // only, so existing entries stay valid. + Inst::LoadLocal { volatile: true, .. } => {} + Inst::LoadLocal { + off, + kind, + volatile: false, + } => { + let off = *off; + let kind = *kind; + if !slots.contains(&off) { + continue; + } + let w = load_width(kind); + let hit = slot_table + .iter() + .find(|e| e.off == off && e.width == w) + .copied() + .filter(|e| (i as u32).saturating_sub(e.src_idx) <= MAX_FORWARD_DISTANCE); + if let Some(e) = hit { + match e.load_kind { + None => match kind { + LoadKind::I64 => { + redirect[i] = Some(e.value); + any = true; + } + LoadKind::I8 | LoadKind::I16 | LoadKind::I32 => { + rewrites.push(( + i, + Inst::Extend { + value: e.value, + kind, + }, + )); + } + // Unsigned sub-width and floating: not + // forwarded (see the module note). + _ => {} + }, + Some(k) if k == kind => { + redirect[i] = Some(e.value); + any = true; + } + Some(_) => {} + } + } + if !slot_table.iter().any(|e| e.off == off && e.width == w) { + let value = redirect[i].unwrap_or(i as ValueId); + slot_table.push(SlotEntry { + off, + width: w, + value, + src_idx: idx, + load_kind: Some(kind), + }); + } + } + Inst::StoreLocal { + off, + value, + kind, + volatile, + } => { + let off = *off; + let value = *value; + let kind = *kind; + let volatile = *volatile; + // A frame write can alias a tracked pointer entry + // (the pointer can be a `LocalAddr` of this slot), + // so the pointer table clears as before. + table.clear(); + slot_table.retain(|e| e.off != off); + if slots.contains(&off) && is_int_store(kind) && !volatile { + slot_table.push(SlotEntry { + off, + width: store_width(kind), + value, + src_idx: idx, + load_kind: None, + }); + } + } // Reads and pure computes the pass does not model: no // clobber, no entry. - Inst::LoadLocal { .. } - | Inst::LoadIndexed { .. } + Inst::LoadIndexed { .. } | Inst::Imm(_) | Inst::ImmData(_) | Inst::ImmCode(_) @@ -256,20 +402,29 @@ fn run_one(func: &mut FunctionSsa) { | Inst::FpCast { .. } | Inst::ParamRef { .. } | Inst::Phi { .. } => {} - // Anything that can write through a pointer the pass does - // not track clears the whole table. - Inst::StoreLocal { .. } - | Inst::StoreIndexed { .. } + // Anything that can write through a pointer the pass + // does not track clears the pointer table. Slot entries + // survive: a forwardable slot's address is never a + // value, so none of these can write it. + Inst::StoreIndexed { .. } | Inst::Mcpy { .. } | Inst::AtomicRmw { .. } | Inst::AtomicCas { .. } - | Inst::AllocaInit(_) - | Inst::Call { .. } + | Inst::AllocaInit(_) => { + table.clear(); + } + // A call cannot write a forwardable slot either, but + // forwarding across one would hold the value in a + // register (or a spill slot) over the call, which costs + // more than the frame reload it removes. Both tables + // clear. + Inst::Call { .. } | Inst::CallIndirect { .. } | Inst::CallExt { .. } | Inst::Intrinsic { .. } | Inst::TailExt(_) => { table.clear(); + slot_table.clear(); } } } @@ -310,6 +465,12 @@ fn run_one(func: &mut FunctionSsa) { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => { *cond = resolve(&redirect, *cond); } + Terminator::GotoIndirect { target } => { + *target = resolve(&redirect, *target); + } + Terminator::JumpTable { idx, .. } => { + *idx = resolve(&redirect, *idx); + } Terminator::Return(v) if *v != NO_VALUE => { *v = resolve(&redirect, *v); } @@ -424,8 +585,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks: alloc::vec![Block { start_pc: 0, @@ -703,6 +867,276 @@ mod tests { ); } + /// `slot = s; return slot;` forwards the I64 slot reload to the + /// stored value. + #[test] + fn store_local_then_load_local_redirects() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(2), + 2, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(0)), + "the slot reload should redirect to the stored value v0", + ); + } + + /// A call between the slot store and the reload blocks the forward: + /// not for aliasing (the callee cannot reach the slot) but because + /// forwarding would keep the value live across the call. + #[test] + fn store_local_does_not_forward_across_call() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::Call { + target_pc: 0, + args: Vec::new(), + fixed_args: 0, + fp_return: false, + fp_arg_mask: 0, + arg_aggs: Vec::new(), + ret_agg: None, + ret_slot_local: 0, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(3), + 3, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(3)), + "a reload after a call must stay a reload", + ); + } + + /// A slot whose address is taken anywhere in the function never + /// forwards: a store through the pointer could sit between the + /// slot store and the reload. + #[test] + fn address_taken_slot_does_not_forward() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::LocalAddr(-1), + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::Store { + addr: 1, + disp: 0, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(4), + 4, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(4)), + "an address-taken slot must not forward", + ); + } + + /// A volatile slot store pins the slot: neither it nor any access + /// of the slot forwards (C99 6.7.3p6). + #[test] + fn volatile_store_local_does_not_forward() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I64, + volatile: true, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(2), + 2, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(2)), + "a volatile-stored slot must not forward", + ); + } + + /// A second store to the slot replaces the tracked value: the + /// reload forwards to the newer store, not the older one. + #[test] + fn second_store_local_replaces_entry() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::ParamRef { + idx: 1, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::StoreLocal { + off: -1, + value: 1, + kind: StoreKind::I64, + volatile: false, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(4), + 4, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(1)), + "the reload should forward to the second store's value", + ); + } + + /// A signed sub-width slot reload becomes an `Extend` of the + /// stored value, as for the pointer path. + #[test] + fn signed_subwidth_slot_reload_becomes_extend() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -1, + value: 0, + kind: StoreKind::I32, + volatile: false, + }, + Inst::LoadLocal { + off: -1, + kind: LoadKind::I32, + volatile: false, + }, + ], + Terminator::Return(2), + 2, + ); + run_one(&mut f); + assert!( + matches!( + f.insts[2], + Inst::Extend { + value: 0, + kind: LoadKind::I32 + } + ), + "an I32 slot reload of an I32 store should become Extend(stored, I32)", + ); + } + + /// A call's aggregate-return slot is written by the call itself, so + /// it never forwards even without a `LocalAddr`. + #[test] + fn call_ret_slot_does_not_forward() { + let mut f = fresh( + alloc::vec![ + Inst::ParamRef { + idx: 0, + kind: LoadKind::I64 + }, + Inst::StoreLocal { + off: -2, + value: 0, + kind: StoreKind::I64, + volatile: false, + }, + Inst::Call { + target_pc: 0, + args: Vec::new(), + fixed_args: 0, + fp_return: false, + fp_arg_mask: 0, + arg_aggs: Vec::new(), + ret_agg: Some(0), + ret_slot_local: -2, + }, + Inst::LoadLocal { + off: -2, + kind: LoadKind::I64, + volatile: false, + }, + ], + Terminator::Return(3), + 3, + ); + run_one(&mut f); + assert!( + matches!(f.blocks[0].terminator, Terminator::Return(3)), + "a call result slot must not forward across the call", + ); + } + /// Two loads of the same location with no write between: the second /// forwards to the first. #[test] diff --git a/src/c5/codegen/passes/struct_return_reg.rs b/src/c5/codegen/passes/struct_return_reg.rs index 435f9c6ff..a7e473573 100644 --- a/src/c5/codegen/passes/struct_return_reg.rs +++ b/src/c5/codegen/passes/struct_return_reg.rs @@ -171,7 +171,8 @@ fn promote_once(func: &mut FunctionSsa) -> bool { Terminator::Return(v) | Terminator::Bz { cond: v, .. } | Terminator::Bnz { cond: v, .. } - | Terminator::GotoIndirect { target: v } => refs.push(*v), + | Terminator::GotoIndirect { target: v } + | Terminator::JumpTable { idx: v, .. } => refs.push(*v), _ => {} } if block.exit_acc != NO_VALUE { @@ -298,7 +299,8 @@ fn promote_once(func: &mut FunctionSsa) -> bool { Terminator::Return(v) | Terminator::Bz { cond: v, .. } | Terminator::Bnz { cond: v, .. } - | Terminator::GotoIndirect { target: v } => { + | Terminator::GotoIndirect { target: v } + | Terminator::JumpTable { idx: v, .. } => { if let Some(&s) = la_slot.get(v) { mark_disq(&mut slots, s); } @@ -440,6 +442,9 @@ fn promote_once(func: &mut FunctionSsa) -> bool { Terminator::GotoIndirect { target } => { *target = resolve(&redirect, *target); } + Terminator::JumpTable { idx, .. } => { + *idx = resolve(&redirect, *idx); + } Terminator::Return(v) if *v != NO_VALUE => { *v = resolve(&redirect, *v); } diff --git a/src/c5/codegen/passes/unroll.rs b/src/c5/codegen/passes/unroll.rs new file mode 100644 index 000000000..a87953d43 --- /dev/null +++ b/src/c5/codegen/passes/unroll.rs @@ -0,0 +1,918 @@ +//! Full unrolling of constant-trip loops. +//! +//! Runs under `-O` after `ssa_mem2reg` (loop-carried values are header +//! phis by then) and before the inliner, so a helper whose body was a +//! short counted loop becomes a single-block inline candidate and the +//! cloned call sites join the inliner's worklist. The post-inline +//! constant folder collapses the per-copy `Extend(Imm)` / `BinopI` +//! index chains the clones leave behind. +//! +//! The transform treats the loop body as a pseudo-callee spliced once +//! per iteration, reusing the inliner's remap primitives: its +//! "parameters" are the header's phis (`phi_i = Phi{(preheader, +//! init_i), (latch, r_i)}`) and its "returns" are the latch back-edge +//! operands `r_i`. Copy 0 binds each phi to `init_i`; copy k binds it +//! to copy k-1's remapped `r_i`. A final header-only clone binds the +//! phis to the exit-iteration values so every header-defined value +//! visible past the loop (including the header's `exit_acc`) resolves; +//! SSA dominance guarantees no value defined in the body or latch is +//! used outside the loop (the zero-trip path skips them). The loop's +//! blocks collapse into one straight-line block; all later block-id +//! references rewrite through `remap_blocks::remap_block_ids`. +//! +//! Eligible loops are the walker's canonical counted shape: +//! +//! * a natural loop whose header conditionally exits (`Bz` / `Bnz` +//! with one successor in the loop, one out) and whose remaining +//! blocks form a single-successor chain back to the header -- one +//! body block, optionally followed by the walker's increment block +//! as the latch; +//! * every header phi merges exactly the preheader and latch values; +//! * no volatile access (C99 6.7.3p6 forbids duplicating the access), +//! `Mcpy`, atomic, intrinsic, `AllocaInit`, or `TailExt` in the +//! loop; calls are cloned per copy; +//! * the trip count evaluates to a constant `<= MAX_TRIP` by abstract +//! interpretation of the header condition and latch step over the +//! shared VM evaluator (`vm::eval`), starting from constant phi +//! inits; +//! * the loop is at most `MAX_LOOP_INSTS` instructions and the +//! expansion at most `MAX_REGION_INSTS`. +//! +//! Functions with a computed goto or a `BlockAddr` (block ids shift), +//! or a returns-twice call (cloned call sites would multiply the +//! setjmp return points), keep their loops rolled. + +use alloc::collections::{BTreeMap, BTreeSet}; +use alloc::vec; +use alloc::vec::Vec; + +use super::super::ssa::mem2reg::{dominators, predecessors}; +use super::inline::{map_v, remap_caller_inst, remap_terminator}; +use super::layout::{natural_loops, rpo_numbers}; +use crate::c5::ir::{Block, BlockId, FunctionSsa, Inst, NO_VALUE, Terminator, ValueId}; +use crate::c5::vm::eval; + +/// Largest constant trip count that unrolls. +const MAX_TRIP: usize = 16; +/// Iteration bound while counting trips; a condition still true past +/// this is treated as unknown. +const COUNT_CAP: usize = 64; +/// Largest loop (header + chain instructions) that unrolls. +const MAX_LOOP_INSTS: usize = 40; +/// Cap on the expanded region: `(trip + 1) * loop_insts`. +const MAX_REGION_INSTS: usize = 600; +/// Per-function bounds: loops expanded, and the instruction count +/// past which no further loop is attempted. +const MAX_LOOPS_PER_FUNC: usize = 16; +const MAX_FUNC_INSTS: usize = 4096; + +pub(crate) fn run(funcs: &mut [FunctionSsa]) { + for func in funcs.iter_mut() { + run_one(func); + } +} + +fn run_one(func: &mut FunctionSsa) { + // Block ids shift when the loop's blocks merge: a computed goto's + // label set and any `BlockAddr` would need retargeting through a + // block that no longer exists once its clones are inlined into the + // merged region. A returns-twice call site must stay unique per + // source occurrence (C99 7.13.2.1p3). + if !func.computed_goto_targets.is_empty() + || func.has_returns_twice_call + || func.insts.iter().any(|i| matches!(i, Inst::BlockAddr(_))) + { + return; + } + for _ in 0..MAX_LOOPS_PER_FUNC { + if func.insts.len() > MAX_FUNC_INSTS { + return; + } + let Some(shape) = find_unrollable(func) else { + return; + }; + #[cfg(feature = "codegen_test")] + if std::env::var("BADC_LOG_UNROLL").is_ok() { + eprintln!( + "[unroll] {n}: header=b{h} chain={c:?} trip={t} loop_insts={i}", + n = func.name, + h = shape.header, + c = shape.chain, + t = shape.trip, + i = shape_inst_count(func, &shape) + ); + } + expand(func, &shape); + // Record that a loop was expanded: the post-inline scalar + // promotion re-runs mem2reg only on functions where unrolling + // turned an array subscript into a constant offset. + func.did_unroll = true; + } +} + +/// A loop that passed every gate. `chain` is the loop's non-header +/// blocks in execution order; the last entry is the latch. +struct LoopShape { + header: BlockId, + chain: Vec, + exit: BlockId, + /// One entry per header phi: `(phi id, preheader init operand, + /// latch back-edge operand)`. + phis: Vec<(ValueId, ValueId, ValueId)>, + trip: usize, +} + +fn find_unrollable(func: &FunctionSsa) -> Option { + if func.blocks.len() < 3 { + return None; + } + let preds = predecessors(func); + let idom = dominators(func); + let rpo = rpo_numbers(func); + let loops = natural_loops(func, &idom, &preds, &rpo); + loops.iter().find_map(|l| { + try_shape(func, l.header, &l.body, &preds).filter(|s| { + s.trip <= MAX_TRIP && { + let loop_insts = shape_inst_count(func, s); + loop_insts <= MAX_LOOP_INSTS && (s.trip + 1) * loop_insts <= MAX_REGION_INSTS + } + }) + }) +} + +fn shape_inst_count(func: &FunctionSsa, s: &LoopShape) -> usize { + core::iter::once(&s.header) + .chain(s.chain.iter()) + .map(|&b| { + let r = &func.blocks[b as usize].inst_range; + (r.end - r.start) as usize + }) + .sum() +} + +fn try_shape( + func: &FunctionSsa, + header: BlockId, + body: &BTreeSet, + preds: &[Vec], +) -> Option { + let h = header; + // Entry block 0 has the function's implicit entry edge; a loop + // block there has an extra predecessor the phi gate cannot see. + if h == 0 || body.len() < 2 || body.len() > 3 { + return None; + } + // The header conditionally exits: one successor in the loop, one out. + let (cond, s1, s2, is_bz) = match func.blocks[h as usize].terminator { + Terminator::Bz { + cond, + target, + fall_through, + } => (cond, target, fall_through, true), + Terminator::Bnz { + cond, + target, + fall_through, + } => (cond, target, fall_through, false), + _ => return None, + }; + let (enter, exit) = match (body.contains(&s1), body.contains(&s2)) { + (true, false) => (s1, s2), + (false, true) => (s2, s1), + _ => return None, + }; + // The non-header blocks form a single-successor chain back to the + // header; anything else is a multi-block body and stays rolled. + let mut chain: Vec = Vec::new(); + let mut cur = enter; + while cur != h { + if cur == 0 || chain.contains(&cur) || chain.len() >= body.len() { + return None; + } + chain.push(cur); + cur = match func.blocks[cur as usize].terminator { + Terminator::Jmp(t) | Terminator::FallThrough(t) => t, + _ => return None, + }; + } + if chain.len() + 1 != body.len() || chain.iter().any(|b| !body.contains(b)) { + return None; + } + let latch = *chain.last()?; + // Exactly two header predecessors: the latch and one preheader + // outside the loop. More entries mean a side entry the phi + // rewrite cannot express. + let hp = &preds[h as usize]; + if hp.len() != 2 { + return None; + } + let pre = match (hp[0] == latch, hp[1] == latch) { + (true, false) => hp[1], + (false, true) => hp[0], + _ => return None, + }; + if body.contains(&pre) { + return None; + } + let mut phis: Vec<(ValueId, ValueId, ValueId)> = Vec::new(); + for &b in core::iter::once(&h).chain(chain.iter()) { + for pc in func.blocks[b as usize].inst_range.clone() { + match &func.insts[pc as usize] { + Inst::Phi { incoming, .. } => { + if b != h || incoming.len() != 2 { + return None; + } + let (mut init, mut back) = (None, None); + for &(pb, v) in incoming { + if pb == latch { + back = Some(v); + } else if pb == pre { + init = Some(v); + } else { + return None; + } + } + let (init, back) = (init?, back?); + if init == NO_VALUE || back == NO_VALUE { + return None; + } + phis.push((pc, init, back)); + } + // A volatile access is performed strictly per the + // abstract machine (C99 5.1.2.3p2 / 6.7.3p6); cloning + // duplicates it. + Inst::Load { volatile: true, .. } + | Inst::Store { volatile: true, .. } + | Inst::LoadLocal { volatile: true, .. } + | Inst::StoreLocal { volatile: true, .. } => return None, + Inst::Mcpy { .. } + | Inst::AtomicRmw { .. } + | Inst::AtomicCas { .. } + | Inst::Intrinsic { .. } + | Inst::AllocaInit(_) + | Inst::TailExt(_) + | Inst::BlockAddr(_) => return None, + _ => {} + } + } + } + if phis.is_empty() { + return None; + } + // Each init must be defined outside the loop so copy 0 can + // reference it directly. + let in_loop = |v: ValueId| { + core::iter::once(&h) + .chain(chain.iter()) + .any(|&b| func.blocks[b as usize].inst_range.contains(&v)) + }; + if phis.iter().any(|&(_, init, _)| in_loop(init)) { + return None; + } + let trip = count_trips(func, cond, s1, exit, is_bz, &phis)?; + Some(LoopShape { + header: h, + chain, + exit, + phis, + trip, + }) +} + +/// Constant evaluation of `v` under phi bindings `state`, over the +/// shared VM operator semantics. Values outside the binding set that +/// are not constant-computable (loads, calls, other phis, address +/// immediates, f32 patterns) are unknown. +fn eval_value( + func: &FunctionSsa, + v: ValueId, + state: &BTreeMap>, + cache: &mut BTreeMap>, + depth: usize, +) -> Option { + if v == NO_VALUE || depth > 64 { + return None; + } + if let Some(&s) = state.get(&v) { + return s; + } + if let Some(&c) = cache.get(&v) { + return c; + } + if func.f32_values.get(v as usize).copied().unwrap_or(false) { + return None; + } + let r = match func.insts.get(v as usize)? { + Inst::Imm(k) => Some(*k), + Inst::Extend { value, kind } => { + eval_value(func, *value, state, cache, depth + 1).map(|x| eval::eval_extend(x, *kind)) + } + Inst::BinopI { op, lhs, rhs_imm } => eval_value(func, *lhs, state, cache, depth + 1) + .and_then(|l| eval::fold_binop(*op, l, *rhs_imm)), + Inst::Binop { op, lhs, rhs } => eval_value(func, *lhs, state, cache, depth + 1) + .zip(eval_value(func, *rhs, state, cache, depth + 1)) + .and_then(|(l, r)| eval::fold_binop(*op, l, r)), + _ => None, + }; + cache.insert(v, r); + r +} + +/// Count iterations by abstract interpretation: bind each phi to its +/// constant init, evaluate the header condition, and step every phi +/// through its latch operand. A phi whose value stops being constant +/// carries `None` and poisons only what reads it. Unknown condition +/// or more than `COUNT_CAP` iterations means no constant trip. +fn count_trips( + func: &FunctionSsa, + cond: ValueId, + target: BlockId, + exit: BlockId, + is_bz: bool, + phis: &[(ValueId, ValueId, ValueId)], +) -> Option { + let mut state: BTreeMap> = BTreeMap::new(); + { + let empty = BTreeMap::new(); + let mut cache = BTreeMap::new(); + for &(phi, init, _) in phis { + let v = eval_value(func, init, &empty, &mut cache, 0); + state.insert(phi, v); + } + } + for k in 0..=COUNT_CAP { + let mut cache = BTreeMap::new(); + let c = eval_value(func, cond, &state, &mut cache, 0)?; + // The branch takes `target` when the condition fires (`Bz`: + // cond == 0; `Bnz`: cond != 0) and the fall-through arm + // otherwise; the loop exits when that successor is `exit`. + let fired = if is_bz { c == 0 } else { c != 0 }; + if fired == (target == exit) { + return Some(k); + } + if k == COUNT_CAP { + return None; + } + let next: Vec<(ValueId, Option)> = phis + .iter() + .map(|&(phi, _, back)| (phi, eval_value(func, back, &state, &mut cache, 0))) + .collect(); + for (phi, v) in next { + state.insert(phi, v); + } + } + None +} + +/// Rebuild `func` with the loop's blocks replaced by one straight-line +/// block holding `trip` body copies plus the final header clone. +fn expand(func: &mut FunctionSsa, shape: &LoopShape) { + let h = shape.header as usize; + let trip = shape.trip; + let copies = trip + 1; + let n_old = func.insts.len(); + let n_blocks = func.blocks.len(); + let chain_set: BTreeSet = shape.chain.iter().copied().collect(); + + // Dense position of each loop instruction, for the per-copy clone + // table the extern-ref carry reads. + let mut loop_pos: Vec = vec![u32::MAX; n_old]; + let mut loop_len = 0u32; + for &b in core::iter::once(&shape.header).chain(shape.chain.iter()) { + for pc in func.blocks[b as usize].inst_range.clone() { + loop_pos[pc as usize] = loop_len; + loop_len += 1; + } + } + let mut clone_ids: Vec> = vec![vec![NO_VALUE; loop_len as usize]; copies]; + + // Old -> new block ids: the chain blocks disappear; later ids + // shift down. The removed ids alias the merged block so the map + // is total; nothing references them after the expansion. + let mut new_bid: Vec = Vec::with_capacity(n_blocks); + let mut removed = 0u32; + for b in 0..n_blocks as u32 { + if chain_set.contains(&b) { + removed += 1; + new_bid.push(BlockId::MAX); + } else { + new_bid.push(b - removed); + } + } + for &c in &chain_set { + new_bid[c as usize] = new_bid[h]; + } + + let mut new_insts: Vec = Vec::new(); + let mut new_inst_src: Vec<(u32, u32)> = Vec::new(); + let mut new_f32: Vec = Vec::new(); + // (old block id, start offset in `new_insts`) per surviving block. + let mut new_block_starts: Vec<(usize, u32)> = Vec::new(); + // Running value remap. Loop instructions are overwritten per copy, + // so between copies the entry holds the previous copy's clone -- + // exactly the back-edge view the next copy's phi bindings read. + // After the merged block the header entries hold the final clone, + // the view every outside use requires (only header values dominate + // the exit). The block array is not ordered definitions-before- + // uses, so emission runs to a fixed point as the inliner's splice + // does: ids are structurally stable across passes and each pass + // resolves one forward-reference level. + let mut cur: Vec = vec![NO_VALUE; n_old]; + let mut guard = n_old + 2; + loop { + new_insts.clear(); + new_inst_src.clear(); + new_f32.clear(); + new_block_starts.clear(); + let before = cur.clone(); + for ob in 0..n_blocks { + if chain_set.contains(&(ob as BlockId)) { + continue; + } + new_block_starts.push((ob, new_insts.len() as u32)); + let mut emit = |pc: u32, + copy: Option, + cur: &mut Vec, + new_insts: &mut Vec, + new_inst_src: &mut Vec<(u32, u32)>, + new_f32: &mut Vec| { + let mut inst = func.insts[pc as usize].clone(); + remap_caller_inst(&mut inst, cur); + let id = new_insts.len() as u32; + cur[pc as usize] = id; + if let Some(k) = copy { + clone_ids[k][loop_pos[pc as usize] as usize] = id; + } + new_insts.push(inst); + new_inst_src.push(func.inst_src.get(pc as usize).copied().unwrap_or((0, 0))); + new_f32.push(func.f32_values.get(pc as usize).copied().unwrap_or(false)); + }; + if ob == h { + for k in 0..copies { + // Parallel phi binding: read every source before + // writing, so one phi's new binding cannot feed + // another's within the same copy. + let binds: Vec<(ValueId, ValueId)> = shape + .phis + .iter() + .map(|&(phi, init, back)| { + let src = if k == 0 { init } else { back }; + (phi, map_v(src, &cur)) + }) + .collect(); + for (phi, b) in binds { + cur[phi as usize] = b; + } + for pc in func.blocks[h].inst_range.clone() { + if matches!(func.insts[pc as usize], Inst::Phi { .. }) { + continue; + } + emit( + pc, + Some(k), + &mut cur, + &mut new_insts, + &mut new_inst_src, + &mut new_f32, + ); + } + // The final clone is header-only: it materialises + // the exit-visible header values. + if k < trip { + for &cb in &shape.chain { + for pc in func.blocks[cb as usize].inst_range.clone() { + emit( + pc, + Some(k), + &mut cur, + &mut new_insts, + &mut new_inst_src, + &mut new_f32, + ); + } + } + } + } + } else { + for pc in func.blocks[ob].inst_range.clone() { + emit( + pc, + None, + &mut cur, + &mut new_insts, + &mut new_inst_src, + &mut new_f32, + ); + } + } + } + if cur == before { + break; + } + guard -= 1; + if guard == 0 { + break; + } + } + + // Blocks: surviving blocks keep their terminators (values through + // the final remap; block ids stay old until `remap_block_ids`). + // The merged block jumps straight to the exit -- the trip count + // proved the final header clone's condition takes that edge. + let mut new_blocks: Vec = Vec::with_capacity(new_block_starts.len()); + for (i, &(ob, start)) in new_block_starts.iter().enumerate() { + let end = new_block_starts + .get(i + 1) + .map(|&(_, s)| s) + .unwrap_or(new_insts.len() as u32); + let old = &func.blocks[ob]; + let terminator = if ob == h { + Terminator::Jmp(shape.exit) + } else { + let mut t = old.terminator; + remap_terminator(&mut t, &cur); + t + }; + new_blocks.push(Block { + start_pc: old.start_pc, + inst_range: start..end, + terminator, + exit_acc: map_v(old.exit_acc, &cur), + }); + } + + // Extern-ref carry: a reference on a loop instruction lands on + // every clone (each cloned `Call` / `ImmData` / `ImmCode` / + // `TlsAddr` still names the cross-TU symbol); a reference outside + // retargets through the final remap. + let retarget = |refs: &[(u32, u32)]| -> Vec<(u32, u32)> { + let mut out = Vec::new(); + for &(idx, sym) in refs { + let pos = loop_pos.get(idx as usize).copied().unwrap_or(u32::MAX); + if pos != u32::MAX { + for ids in clone_ids.iter() { + let nv = ids[pos as usize]; + if nv != NO_VALUE { + out.push((nv, sym)); + } + } + } else { + let nv = map_v(idx, &cur); + if nv != NO_VALUE { + out.push((nv, sym)); + } + } + } + out + }; + func.extern_call_refs = retarget(&func.extern_call_refs); + func.extern_imm_code_refs = retarget(&func.extern_imm_code_refs); + func.extern_imm_data_refs = retarget(&func.extern_imm_data_refs); + func.extern_tls_refs = retarget(&func.extern_tls_refs); + + func.insts = new_insts; + func.inst_src = new_inst_src; + func.f32_values = new_f32; + func.blocks = new_blocks; + super::remap_blocks::remap_block_ids(func, &new_bid); +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::c5::codegen::ssa::reg_alloc::for_each_operand; + use crate::c5::ir::{BinOp, LoadKind, StoreKind}; + + fn func_with(insts: Vec, blocks: Vec) -> FunctionSsa { + FunctionSsa { + inst_src: vec![(0, 0); insts.len()], + f32_values: vec![false; insts.len()], + insts, + blocks, + ..FunctionSsa::default() + } + } + + fn block(range: core::ops::Range, terminator: Terminator) -> Block { + Block { + start_pc: 0, + inst_range: range, + terminator, + exit_acc: NO_VALUE, + } + } + + /// The walker's counted-loop shape with two loop-carried phis: + /// + /// b0 entry: v0 = Imm(init_i), v1 = Imm(42); Jmp b1 + /// b1 header: v2 = phi_i{(b0, v0), (b3, v6)}, + /// v3 = phi_s{(b0, v1), (b3, v5)}, + /// v4 = Lt(v2, bound); Bz -> b4 (exit) / b2 (body) + /// b2 body: v5 = Add(v3, v2); Jmp b3 + /// b3 latch: v6 = Add(v2, 1); Jmp b1 + /// b4 exit: v7 = Add(v2, 100); Return(v3) + /// + /// The exit uses both the phi (v3) and a header-computed value + /// through the phi (v7's operand v2), covering exit-value + /// resolution through the final header clone. + fn two_phi_loop(init_i: i64, bound: i64) -> FunctionSsa { + func_with( + vec![ + Inst::Imm(init_i), + Inst::Imm(42), + Inst::Phi { + incoming: vec![(0, 0), (3, 6)], + kind: LoadKind::I64, + }, + Inst::Phi { + incoming: vec![(0, 1), (3, 5)], + kind: LoadKind::I64, + }, + Inst::BinopI { + op: BinOp::Lt, + lhs: 2, + rhs_imm: bound, + }, + Inst::Binop { + op: BinOp::Add, + lhs: 3, + rhs: 2, + }, + Inst::BinopI { + op: BinOp::Add, + lhs: 2, + rhs_imm: 1, + }, + Inst::BinopI { + op: BinOp::Add, + lhs: 2, + rhs_imm: 100, + }, + ], + vec![ + block(0..2, Terminator::Jmp(1)), + block( + 2..5, + Terminator::Bz { + cond: 4, + target: 4, + fall_through: 2, + }, + ), + block(5..6, Terminator::Jmp(3)), + block(6..7, Terminator::Jmp(1)), + block(7..8, Terminator::Return(3)), + ], + ) + } + + /// Structural integrity: block ranges partition the tape in order + /// and every operand of every instruction resolves to a defined id. + fn assert_well_formed(f: &FunctionSsa) { + let mut expect = 0u32; + for b in &f.blocks { + assert_eq!(b.inst_range.start, expect, "ranges must be contiguous"); + assert!(b.inst_range.end >= b.inst_range.start); + expect = b.inst_range.end; + match b.terminator { + Terminator::Jmp(t) | Terminator::FallThrough(t) => { + assert!((t as usize) < f.blocks.len()) + } + Terminator::Bz { + target, + fall_through, + .. + } + | Terminator::Bnz { + target, + fall_through, + .. + } => { + assert!((target as usize) < f.blocks.len()); + assert!((fall_through as usize) < f.blocks.len()); + } + _ => {} + } + } + assert_eq!(expect as usize, f.insts.len(), "ranges must cover the tape"); + assert_eq!(f.inst_src.len(), f.insts.len()); + assert_eq!(f.f32_values.len(), f.insts.len()); + for inst in &f.insts { + for_each_operand(inst, |v| { + assert!( + v != NO_VALUE && (v as usize) < f.insts.len(), + "operand {v} out of range in {inst:?}" + ); + }); + } + } + + fn returned_imm(f: &FunctionSsa) -> Option { + for b in &f.blocks { + if let Terminator::Return(v) = b.terminator + && let Some(Inst::Imm(k)) = f.insts.get(v as usize) + { + return Some(*k); + } + } + None + } + + #[test] + fn two_phi_loop_unrolls_to_constant() { + let mut f = two_phi_loop(0, 3); + run_one(&mut f); + assert_eq!(f.blocks.len(), 3, "header + chain collapse to one block"); + assert!(!f.insts.iter().any(|i| matches!(i, Inst::Phi { .. }))); + assert!( + !f.blocks + .iter() + .any(|b| matches!(b.terminator, Terminator::Bz { .. } | Terminator::Bnz { .. })) + ); + assert_well_formed(&f); + // 42 + (0 + 1 + 2) folds through the copies' Binop chain. + super::super::constfold::run(core::slice::from_mut(&mut f)); + assert_eq!(returned_imm(&f), Some(45)); + } + + #[test] + fn exit_values_resolve_through_final_header_clone() { + let mut f = two_phi_loop(0, 3); + // Return the header-computed v7 = phi_i + 100 instead of phi_s. + f.blocks[4].terminator = Terminator::Return(7); + run_one(&mut f); + assert_well_formed(&f); + super::super::constfold::run(core::slice::from_mut(&mut f)); + // At the exit the induction phi holds the bound. + assert_eq!(returned_imm(&f), Some(103)); + } + + #[test] + fn trip_zero_passes_preheader_values_through() { + let mut f = two_phi_loop(5, 3); + run_one(&mut f); + assert_well_formed(&f); + // Merged block holds only the final header clone: the cond + // BinopI and the exit-visible v7 clone; no body/latch copies. + assert!(!f.insts.iter().any(|i| matches!(i, Inst::Phi { .. }))); + let Terminator::Return(v) = f.blocks.last().unwrap().terminator else { + panic!("expected Return"); + }; + assert!( + matches!(f.insts[v as usize], Inst::Imm(42)), + "zero-trip exit reads the preheader init, got {:?}", + f.insts[v as usize] + ); + } + + #[test] + fn trip_one_unrolls_single_copy() { + let mut f = two_phi_loop(0, 1); + run_one(&mut f); + assert_well_formed(&f); + // One body copy: exactly one body Add(v_s, v_i) clone (counted + // before constfold collapses it to an Imm). + let body_adds = f + .insts + .iter() + .filter(|i| matches!(i, Inst::Binop { op: BinOp::Add, .. })) + .count(); + assert_eq!(body_adds, 1); + super::super::constfold::run(core::slice::from_mut(&mut f)); + assert_eq!(returned_imm(&f), Some(42)); + } + + #[test] + fn trip_above_cap_bails() { + for bound in [17, 100] { + let mut f = two_phi_loop(0, bound); + let before = alloc::format!("{:?}", f.insts); + run_one(&mut f); + assert_eq!( + before, + alloc::format!("{:?}", f.insts), + "trip {bound} must stay rolled" + ); + assert_eq!(f.blocks.len(), 5); + } + } + + #[test] + fn unknown_trip_bails() { + // The condition reads a load, not a constant chain. + let mut f = two_phi_loop(0, 3); + f.insts[4] = Inst::Load { + addr: 2, + disp: 0, + kind: LoadKind::I64, + volatile: false, + }; + run_one(&mut f); + assert_eq!(f.blocks.len(), 5); + } + + #[test] + fn volatile_access_bails() { + let mut f = two_phi_loop(0, 3); + // Body add becomes a volatile store of the phi. + f.insts[5] = Inst::Store { + addr: 2, + disp: 0, + value: 3, + kind: StoreKind::I64, + volatile: true, + }; + run_one(&mut f); + assert_eq!(f.blocks.len(), 5); + } + + #[test] + fn computed_goto_function_bails() { + let mut f = two_phi_loop(0, 3); + f.computed_goto_targets = vec![2]; + run_one(&mut f); + assert_eq!(f.blocks.len(), 5); + } + + #[test] + fn clone_counts_match_copy_structure() { + let mut f = two_phi_loop(0, 3); + let trip = 3usize; + run_one(&mut f); + assert_well_formed(&f); + // Outside insts appear once; header non-phi insts trip + 1 + // times; body / latch insts trip times. Phis vanish. + let outside = 3; // v0, v1, v7 + let header_nonphi = 1; // v4 + let chain = 2; // v5, v6 + assert_eq!( + f.insts.len(), + outside + header_nonphi * (trip + 1) + chain * trip + ); + } + + #[test] + fn extern_refs_carry_onto_every_clone() { + // Body carries a cross-TU call and a data-address immediate. + let mut f = func_with( + vec![ + Inst::Imm(0), + Inst::Phi { + incoming: vec![(0, 0), (2, 5)], + kind: LoadKind::I64, + }, + Inst::BinopI { + op: BinOp::Lt, + lhs: 1, + rhs_imm: 2, + }, + Inst::ImmData(64), + Inst::Call { + target_pc: 900, + args: vec![3], + fixed_args: 1, + fp_return: false, + fp_arg_mask: 0, + arg_aggs: Vec::new(), + ret_agg: None, + ret_slot_local: 0, + }, + Inst::BinopI { + op: BinOp::Add, + lhs: 1, + rhs_imm: 1, + }, + ], + vec![ + block(0..1, Terminator::Jmp(1)), + block( + 1..3, + Terminator::Bz { + cond: 2, + target: 3, + fall_through: 2, + }, + ), + block(3..6, Terminator::Jmp(1)), + block(6..6, Terminator::Return(NO_VALUE)), + ], + ); + f.extern_call_refs = vec![(4, 11)]; + f.extern_imm_data_refs = vec![(3, 12)]; + run_one(&mut f); + assert_well_formed(&f); + assert_eq!(f.extern_call_refs.len(), 2, "one call ref per copy"); + assert_eq!(f.extern_imm_data_refs.len(), 2); + for &(idx, sym) in &f.extern_call_refs { + assert_eq!(sym, 11); + assert!(matches!( + f.insts[idx as usize], + Inst::Call { target_pc: 900, .. } + )); + } + for &(idx, sym) in &f.extern_imm_data_refs { + assert_eq!(sym, 12); + assert!(matches!(f.insts[idx as usize], Inst::ImmData(64))); + } + } +} diff --git a/src/c5/codegen/ssa/build.rs b/src/c5/codegen/ssa/build.rs index 9884bd595..b5593c9de 100644 --- a/src/c5/codegen/ssa/build.rs +++ b/src/c5/codegen/ssa/build.rs @@ -64,6 +64,11 @@ struct LocalCacheEntry { #[derive(Clone, Copy, PartialEq, Eq, Hash)] enum PureKey { Imm(i64), + /// `Inst::Imm` holding an f32 bit pattern, tagged f32. Kept apart + /// from [`PureKey::Imm`]: the f32 mark changes the value's + /// materialisation, so an integer imm with an equal payload must + /// not unify with it. + ImmF32(i64), ImmData(i64), ImmCode(usize), TlsAddr(i64), @@ -166,8 +171,11 @@ impl SsaBuilder { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, }; let mut b = Self { func, @@ -408,6 +416,19 @@ impl SsaBuilder { id } + /// `Inst::Imm` carrying an f32 bit pattern, tagged f32 (a `float` + /// constant, C99 6.4.4.2p4). Cached under its own key so it never + /// unifies with an integer imm of equal payload. + pub(crate) fn imm_f32(&mut self, f32_bits: u32) -> ValueId { + let v = f32_bits as i64; + if let Some(cached) = self.lookup_pure(PureKey::ImmF32(v)) { + return cached; + } + let id = self.push(Inst::Imm(v)); + self.pure_cache.insert(PureKey::ImmF32(v), id); + self.mark_f32(id) + } + /// `Inst::ImmData` (data-segment offset). Same CSE shape as /// `imm`. Externally-resolved data offsets use /// `imm_data_extern`, which records a per-site reloc entry @@ -461,6 +482,16 @@ impl SsaBuilder { self.close(Terminator::GotoIndirect { target }, target); } + /// Close the current block with `Terminator::JumpTable`: + /// control transfers to `targets[idx]`. The caller must have + /// proven `idx` in `0..targets.len()` (an unsigned bounds + /// check branching to the default block). + pub(crate) fn jump_table(&mut self, idx: ValueId, targets: alloc::vec::Vec) { + let table = self.func.jump_tables.len() as u32; + self.func.jump_tables.push(targets); + self.close(Terminator::JumpTable { idx, table }, idx); + } + /// `Inst::ImmCode(0)` whose target lives in another TU. /// Records the parser-symbol index for later linker /// resolution. @@ -1129,7 +1160,18 @@ impl SsaBuilder { /// block, va_start / va_arg may write through caller buffers. pub(crate) fn intrinsic(&mut self, kind: i64, args: Vec) -> ValueId { self.local_cache.clear(); - self.push(Inst::Intrinsic { kind, args }) + let id = self.push(Inst::Intrinsic { kind, args }); + if super::reg_alloc::is_setjmp_barrier(&self.func.insts[id as usize]) { + self.func.has_returns_twice_call = true; + } + id + } + + /// Record that the function calls a returns-twice function (the + /// setjmp family / vfork). See + /// [`FunctionSsa::has_returns_twice_call`]. + pub(crate) fn mark_returns_twice(&mut self) { + self.func.has_returns_twice_call = true; } /// Reserve a fresh per-function 8-byte stack slot for the diff --git a/src/c5/codegen/ssa/dump.rs b/src/c5/codegen/ssa/dump.rs index 1d1bfcb57..335091a40 100644 --- a/src/c5/codegen/ssa/dump.rs +++ b/src/c5/codegen/ssa/dump.rs @@ -71,6 +71,13 @@ pub(crate) fn dump_function(func: &FunctionSsa, alloc: &Allocation) -> String { " terminator {}", fmt_terminator(block.terminator), )); + if let Terminator::JumpTable { table, .. } = block.terminator { + let targets: alloc::vec::Vec = func.jump_tables[table as usize] + .iter() + .map(|b| format!("b{b}")) + .collect(); + out.push_str(&format!(" [{}]", targets.join(", "))); + } if block.exit_acc != NO_VALUE { out.push_str(&format!(" (exit_acc=v{})", block.exit_acc)); } @@ -279,6 +286,9 @@ fn fmt_terminator(t: Terminator) -> String { Terminator::TailExt(b) => format!("TailExt({b})"), Terminator::FallThrough(b) => format!("FallThrough(b{b})"), Terminator::GotoIndirect { target } => format!("GotoIndirect(v{target})"), + Terminator::JumpTable { idx, table } => { + format!("JumpTable {{ idx=v{idx}, table={table} }}") + } } } diff --git a/src/c5/codegen/ssa/emit_common.rs b/src/c5/codegen/ssa/emit_common.rs index ab7375724..5ab43aff6 100644 --- a/src/c5/codegen/ssa/emit_common.rs +++ b/src/c5/codegen/ssa/emit_common.rs @@ -47,28 +47,53 @@ pub(crate) fn slots16(n_slots: u32) -> u32 { align16(n_slots * 8) } +/// True when the emitted form of `inst` addresses the locals region +/// (negative slot offset): slot loads / stores / address-takes, the +/// alloca-arena bookkeeping store, and a call gathering an aggregate +/// return into its result-temp slot. Purely structural; whether the +/// instruction is emitted at all is `is_dead_pure`'s decision, and the +/// frame gate below combines the two so it cannot disagree with the +/// per-inst emit skip. +fn inst_addresses_local(inst: &super::super::ir::Inst) -> bool { + use super::super::ir::Inst; + match inst { + Inst::LoadLocal { off, .. } | Inst::StoreLocal { off, .. } | Inst::LocalAddr(off) => { + *off < 0 + } + Inst::AllocaInit(slot) => *slot != 0, + Inst::Call { ret_slot_local, .. } + | Inst::CallIndirect { ret_slot_local, .. } + | Inst::CallExt { ret_slot_local, .. } => *ret_slot_local < 0, + _ => false, + } +} + /// The frame regions both targets size identically: the locals region, the /// allocator spill region, and the saved callee-GPR region, each a 16-byte -/// aligned byte count. The locals region is zero when no surviving instruction +/// aligned byte count. The locals region is zero when no emitted instruction /// references a user local (negative `off`); after mem2reg and dead-store /// elimination such an object is never observed and needs no storage -/// (C99 6.2.4p2). Param cells use non-negative `off` and are sized separately. +/// (C99 6.2.4p2). An instruction the per-inst dispatch skips as dead pure +/// (`is_dead_pure`) produces no machine code and therefore no access; the +/// same predicate gates both decisions. Param cells use non-negative `off` +/// and are sized separately. pub(crate) fn compute_frame_base( func: &super::super::ir::FunctionSsa, alloc: &super::reg_alloc::Allocation, ) -> (u32, u32, u32) { - use super::super::ir::Inst; let declared_locals_bytes = slots16(func.locals.max(0) as u32); - // A function returning an aggregate larger than 16 bytes saves the - // caller-supplied indirect-result pointer into its `indirect_result_slot` - // in the prologue and reads it on return; that slot is reached through a - // FunctionSsa field rather than an instruction, so it counts as a local - // access even when no LoadLocal / StoreLocal / LocalAddr references it. + // Two prologue paths reach the locals region through FunctionSsa fields + // rather than instructions and count as accesses on their own: saving + // the caller-supplied indirect-result pointer into `indirect_result_slot`, + // and scattering a by-value aggregate parameter into its body local. let any_local_access = func.indirect_result_slot < 0 - || func.insts.iter().any(|i| match i { - Inst::LoadLocal { off, .. } | Inst::StoreLocal { off, .. } => *off < 0, - Inst::LocalAddr(off) => *off < 0, - _ => false, + || func + .param_aggs + .iter() + .zip(func.param_local_slots.iter()) + .any(|(agg, slot)| agg.is_some() && *slot < 0) + || func.insts.iter().enumerate().any(|(idx, i)| { + inst_addresses_local(i) && !is_dead_pure(i, idx as super::super::ir::ValueId, alloc) }); let locals_bytes = if any_local_access { declared_locals_bytes @@ -425,6 +450,18 @@ pub(crate) fn emit_phi_predecessor_moves( .. } => alloc::vec![target, fall_through], Terminator::GotoIndirect { .. } => func.computed_goto_targets.clone(), + Terminator::JumpTable { table, .. } => { + // Distinct targets only: entries repeat (holes point at + // the default block) but each CFG edge's phi moves are + // emitted once. + let mut out: alloc::vec::Vec = alloc::vec::Vec::new(); + for &t in &func.jump_tables[table as usize] { + if !out.contains(&t) { + out.push(t); + } + } + out + } Terminator::Return(_) | Terminator::TailExt(_) => alloc::vec![], }; for succ in succs { diff --git a/src/c5/codegen/ssa/liveness.rs b/src/c5/codegen/ssa/liveness.rs index efd0c1797..e9c69279e 100644 --- a/src/c5/codegen/ssa/liveness.rs +++ b/src/c5/codegen/ssa/liveness.rs @@ -71,7 +71,9 @@ impl Liveness { }; match &blk.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => term_use(*cond), - Terminator::GotoIndirect { target } => term_use(*target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + term_use(*target) + } Terminator::Return(v) => term_use(*v), Terminator::Jmp(_) | Terminator::TailExt(_) | Terminator::FallThrough(_) => {} } @@ -124,7 +126,11 @@ impl Liveness { } match &blk.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => mark(*cond), - Terminator::GotoIndirect { target } if *target != NO_VALUE => mark(*target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if *target != NO_VALUE => + { + mark(*target) + } Terminator::Return(v) if *v != NO_VALUE => mark(*v), _ => {} } @@ -142,6 +148,7 @@ impl Liveness { for s in super::mem2reg::successors( &func.blocks[b].terminator, &func.computed_goto_targets, + &func.jump_tables, ) { let sb = s as usize * words; for w in 0..words { @@ -248,7 +255,9 @@ impl Liveness { } match &blk.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => *cond == x, - Terminator::GotoIndirect { target } => *target == x, + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + *target == x + } Terminator::Return(v) => *v == x, _ => false, } @@ -313,7 +322,9 @@ impl Liveness { live.insert(*cond); } } - Terminator::GotoIndirect { target } if (*target as usize) < n => { + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if (*target as usize) < n => + { live.insert(*target); } Terminator::Return(v) if *v != NO_VALUE && (*v as usize) < n => { @@ -390,7 +401,9 @@ impl Liveness { live.insert(*cond); } } - Terminator::GotoIndirect { target } if (*target as usize) < n => { + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if (*target as usize) < n => + { live.insert(*target); } Terminator::Return(v) if *v != NO_VALUE && (*v as usize) < n => { @@ -488,8 +501,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/ssa/mem2reg.rs b/src/c5/codegen/ssa/mem2reg.rs index 5754cac7b..a2435c8ed 100644 --- a/src/c5/codegen/ssa/mem2reg.rs +++ b/src/c5/codegen/ssa/mem2reg.rs @@ -66,8 +66,15 @@ pub(crate) fn promotable_slots(func: &FunctionSsa) -> BTreeSet { /// Successor block ids of a terminator, in branch order. For /// `GotoIndirect` the successors are the function's address-taken /// label blocks (`cg_targets`, from `FunctionSsa::computed_goto_targets`); -/// pass an empty slice for functions with no computed goto. -pub(crate) fn successors(term: &Terminator, cg_targets: &[BlockId]) -> Vec { +/// for `JumpTable` they are the distinct blocks of the terminator's +/// entry in `jump_tables` (entries repeat; the CFG edge set does +/// not). Pass empty slices for functions without either shape. +/// TODO: fold into the shared BlockId remap utility once it lands. +pub(crate) fn successors( + term: &Terminator, + cg_targets: &[BlockId], + jump_tables: &[Vec], +) -> Vec { match term { Terminator::Jmp(b) | Terminator::FallThrough(b) => alloc::vec![*b], Terminator::Bz { @@ -81,6 +88,15 @@ pub(crate) fn successors(term: &Terminator, cg_targets: &[BlockId]) -> Vec alloc::vec![*target, *fall_through], Terminator::GotoIndirect { .. } => cg_targets.to_vec(), + Terminator::JumpTable { table, .. } => { + let mut out: Vec = Vec::new(); + for &t in &jump_tables[*table as usize] { + if !out.contains(&t) { + out.push(t); + } + } + out + } Terminator::Return(_) | Terminator::TailExt(_) => Vec::new(), } } @@ -90,7 +106,11 @@ pub(crate) fn successors(term: &Terminator, cg_targets: &[BlockId]) -> Vec Vec> { let mut preds: Vec> = alloc::vec![Vec::new(); func.blocks.len()]; for (idx, block) in func.blocks.iter().enumerate() { - for succ in successors(&block.terminator, &func.computed_goto_targets) { + for succ in successors( + &block.terminator, + &func.computed_goto_targets, + &func.jump_tables, + ) { preds[succ as usize].push(idx as BlockId); } } @@ -118,6 +138,7 @@ fn postorder(func: &FunctionSsa) -> Vec { let succ = successors( &func.blocks[b as usize].terminator, &func.computed_goto_targets, + &func.jump_tables, ); if si < succ.len() { stack.last_mut().unwrap().1 += 1; @@ -303,7 +324,11 @@ fn slot_live_in_sets(func: &FunctionSsa, promotable: &BTreeSet) -> Vec = BTreeSet::new(); - for s in successors(&func.blocks[b].terminator, &func.computed_goto_targets) { + for s in successors( + &func.blocks[b].terminator, + &func.computed_goto_targets, + &func.jump_tables, + ) { live_out.extend(live_in[s as usize].iter().copied()); } let mut ni = gen_set[b].clone(); @@ -422,6 +447,7 @@ pub(crate) fn insert_phis( match &mut block.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => remap(cond), Terminator::GotoIndirect { target } => remap(target), + Terminator::JumpTable { idx, .. } => remap(idx), Terminator::Return(v) => { if *v != NO_VALUE { remap(v); @@ -1105,7 +1131,7 @@ pub(crate) fn run(func: &mut FunctionSsa) -> Vec { // phi's place. Order matches the dom-tree walk; the // BlockId tag makes lookup positional-independent. let term = func.blocks[b as usize].terminator; - for succ in successors(&term, &func.computed_goto_targets) { + for succ in successors(&term, &func.computed_goto_targets, &func.jump_tables) { for (slot, phi_id) in &phis_at[succ as usize].clone() { if let Some(&val) = current.get(slot) { if let Inst::Phi { incoming, .. } = &mut func.insts[*phi_id as usize] { @@ -1215,6 +1241,9 @@ pub(crate) fn run(func: &mut FunctionSsa) -> Vec { Terminator::GotoIndirect { target } => { *target = resolve(&redirect, *target); } + Terminator::JumpTable { idx, .. } => { + *idx = resolve(&redirect, *idx); + } Terminator::Return(v) => { if *v != NO_VALUE { *v = resolve(&redirect, *v); @@ -1275,8 +1304,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/ssa/native.rs b/src/c5/codegen/ssa/native.rs index 1c8339b59..fe1f814a9 100644 --- a/src/c5/codegen/ssa/native.rs +++ b/src/c5/codegen/ssa/native.rs @@ -206,18 +206,26 @@ mod tests { assert!(!bytes.is_empty(), "sum3 produced zero bytes"); // emit_prologue runs three c5 param-spill stores (one per // declared int param), then the AAPCS64 frame setup: - // `stp x29, x30, [sp, #-0x10]!` = 0xa9bf7bfd. Verify the - // sentinel appears in the first 32 bytes so the prologue - // is recognisable without pinning every byte. + // an `stp x29, x30` in pre-indexed or signed-offset form (the + // locals allocation may fold into the pre-index, and under + // register pressure the pair lands at a signed offset into an + // already-adjusted frame). Match with the imm7 field masked. let preamble_words = bytes.len().min(32) / 4; let found_stp = (0..preamble_words).any(|w| { let off = w * 4; - u32::from_le_bytes([bytes[off], bytes[off + 1], bytes[off + 2], bytes[off + 3]]) - == 0xa9bf7bfd + let word = + u32::from_le_bytes([bytes[off], bytes[off + 1], bytes[off + 2], bytes[off + 3]]); + word & 0xffc0_7fff == 0xa980_7bfd || word & 0xffc0_7fff == 0xa900_7bfd }); + let preamble: alloc::vec::Vec = (0..preamble_words) + .map(|w| { + let off = w * 4; + u32::from_le_bytes([bytes[off], bytes[off + 1], bytes[off + 2], bytes[off + 3]]) + }) + .collect(); assert!( found_stp, - "sum3 prologue: stp x29/x30 not found in first 32 bytes" + "sum3 prologue: stp x29/x30 not found in first 32 bytes: {preamble:08x?}" ); } diff --git a/src/c5/codegen/ssa/phi_class.rs b/src/c5/codegen/ssa/phi_class.rs index f88bc8abe..6a3f9e913 100644 --- a/src/c5/codegen/ssa/phi_class.rs +++ b/src/c5/codegen/ssa/phi_class.rs @@ -162,8 +162,11 @@ mod tests { ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/ssa/reg_alloc.rs b/src/c5/codegen/ssa/reg_alloc.rs index 7378265df..87b83fd3a 100644 --- a/src/c5/codegen/ssa/reg_alloc.rs +++ b/src/c5/codegen/ssa/reg_alloc.rs @@ -107,10 +107,8 @@ pub(crate) struct Allocation { /// Highest PC index that names each value as an operand, raised /// across back edges by `extend_last_use_across_blocks`. A value /// defined at PC `i` is live throughout `[i, last_use[i]]`. The - /// allocator's interval tests read it: `class_last_use` feeds - /// `promote_calls_after_def_to_classes` so a value whose range - /// spans a call takes a callee-saved home, and the coalescing - /// hints avoid a caller-saved register such a call would clobber. + /// coalescing hints read it to avoid sending a value that outlives + /// a call into a caller-saved register the call would clobber. pub last_use: Vec, /// For `BinopI(Shr, X, K)` insts the allocator recognised as /// the upper half of a sign-narrow `Shl K; Shr K` pair (K in @@ -263,6 +261,19 @@ impl RegBanks { } } +/// General-purpose registers the allocator may use for `target`, after +/// the codegen-test bank caps (`BADC_MAX_GPR` / the per-thread override). +/// The scalar-promotion pass (`passes::sroa`) uses this as the ceiling on +/// how many array element slots it lifts to registers: promoting more +/// loop-carried values than the file holds spills them back to the frame +/// at a net loss, so an array whose element count would overflow the file +/// stays memory-resident. +pub(crate) fn usable_gpr_count(target: Target) -> usize { + let banks = RegBanks::for_target(target); + let (max_gpr, _) = pool_size_limits(); + (banks.caller_gprs.len() + banks.callee_gprs.len()).min(max_gpr) +} + /// Allocate physical placements for every value in `func`. See /// the module docs for the algorithm. /// Callee-saved registers the emit pass reserves as fixed scratch and @@ -386,29 +397,11 @@ pub(crate) fn allocate(func: &FunctionSsa, target: Target) -> Allocation { // until every member of its class is dead. let liveness = super::liveness::Liveness::compute(func); let mut classes = super::phi_class::PhiClasses::build(func, &liveness); - let class_last_use: Vec = { - let n = func.insts.len(); - let mut cl = alloc::vec![0u32; n]; - for (v, &lu) in last_use.iter().enumerate().take(n) { - let c = classes.find(v as ValueId) as usize; - if lu > cl[c] { - cl[c] = lu; - } - } - cl - }; let mut calls_after_def = compute_calls_after_def(func, &liveness, target); - // Promote per-value `calls_after_def` to the class's combined - // live range. Without this, a class member whose own last use - // does not cross a call but whose class root lives past one - // would be placed in a caller-saved register and clobbered. - promote_calls_after_def_to_classes( - &mut classes, - func, - &class_last_use, - target, - &mut calls_after_def, - ); + // Promote per-value `calls_after_def` to the class: members share + // one register, so a member whose own range does not cross a call + // still needs a callee-saved home when another member's does. + promote_calls_after_def_to_classes(&mut classes, &mut calls_after_def); // Call-argument coalescing hints. Run after `last_use` and // `calls_after_def` so the per-value safety guards can read them. // The prior unconditional ABI-hint pass was reverted in commit @@ -427,7 +420,6 @@ pub(crate) fn allocate(func: &FunctionSsa, target: Target) -> Allocation { // in its bank spills. Unlike a pc-interval linear scan this models // a value live across a back-edge passthrough block, whose live // range wraps the pc axis. - let _ = &class_last_use; let node_of: Vec = (0..func.insts.len() as ValueId) .map(|v| classes.find(v)) .collect(); @@ -460,6 +452,7 @@ pub(crate) fn allocate(func: &FunctionSsa, target: Target) -> Allocation { &banks, max_gpr, max_fpr, + func.has_returns_twice_call, ); places = coloring.places; let spill_count = coloring.spill_count; @@ -872,7 +865,9 @@ fn verify_allocation( Terminator::Return(v) if (*v as usize) < used.len() => { used[*v as usize] = true; } - Terminator::GotoIndirect { target } if (*target as usize) < used.len() => { + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if (*target as usize) < used.len() => + { used[*target as usize] = true; } _ => {} @@ -1035,6 +1030,7 @@ pub(crate) fn color_graph( banks: &RegBanks, max_gpr: usize, max_fpr: usize, + no_slot_share: bool, ) -> Coloring { let n = node_of.len(); let mut color: Vec = vec![Place::None; n]; @@ -1115,13 +1111,24 @@ pub(crate) fn color_graph( // later-coloured value that interferes excludes this // slot, preserving distinct storage for live ranges that // overlap. - let slot = (0..spill_count) - .find(|&s| slot_used[s as usize] != stamp) - .unwrap_or_else(|| { - let s = spill_count; - spill_count += 1; - s - }); + // + // `no_slot_share` (the caller invokes a returns-twice + // function): liveness no longer bounds slot lifetime. A + // value dead on the first-return path is still read + // after the second return -- C99 7.13.2.1p3 for setjmp, + // and under vfork the child's writes land on the + // parent's shared stack -- so every value gets a + // dedicated slot. + let slot = if no_slot_share { + None + } else { + (0..spill_count).find(|&s| slot_used[s as usize] != stamp) + } + .unwrap_or_else(|| { + let s = spill_count; + spill_count += 1; + s + }); Place::Spill(slot) } }; @@ -1184,7 +1191,10 @@ fn compute_use_counts(func: &FunctionSsa) -> Vec { super::super::ir::Terminator::Bz { cond, .. } => bump_into(&mut counts, cond), super::super::ir::Terminator::Bnz { cond, .. } => bump_into(&mut counts, cond), super::super::ir::Terminator::Return(v) => bump_into(&mut counts, v), - super::super::ir::Terminator::GotoIndirect { target } => bump_into(&mut counts, target), + super::super::ir::Terminator::GotoIndirect { target } + | super::super::ir::Terminator::JumpTable { idx: target, .. } => { + bump_into(&mut counts, target) + } _ => {} } } @@ -1726,7 +1736,9 @@ fn compute_param_incoming_forbid(func: &FunctionSsa, target: Target) -> Vec } } Terminator::Return(v) if (*v as usize) < used.len() => used[*v as usize] = true, - Terminator::GotoIndirect { target } if (*target as usize) < used.len() => { + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if (*target as usize) < used.len() => + { used[*target as usize] = true; } _ => {} @@ -1934,10 +1946,9 @@ fn compute_last_use(func: &FunctionSsa) -> Vec { // such carrier to `end_pc` so a value defined inside the block // but read only by the terminator (the common Return-value case) // has its interval cover any intervening call. Without this the - // forward scan leaves `last_use[v]` at v's own def PC, the - // `compute_calls_after_def` interval test then misses the - // intervening call, and a downstream coalescing hint can place - // `v` in a caller-saved register that the call clobbers. + // forward scan leaves `last_use[v]` at v's own def PC and a + // downstream coalescing hint, which guards on `last_use`, can + // place `v` in a caller-saved register that the call clobbers. for b in &func.blocks { let end_pc = b.inst_range.end; let mut bump = |v: ValueId| { @@ -1952,7 +1963,9 @@ fn compute_last_use(func: &FunctionSsa) -> Vec { match &b.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => bump(*cond), Terminator::Return(v) => bump(*v), - Terminator::GotoIndirect { target } => bump(*target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } => { + bump(*target) + } _ => {} } } @@ -2017,7 +2030,11 @@ fn extend_last_use_across_blocks(func: &FunctionSsa, last_use: &mut [u32]) { match &blk.terminator { Terminator::Bz { cond, .. } | Terminator::Bnz { cond, .. } => mark(*cond), Terminator::Return(v) if *v != NO_VALUE => mark(*v), - Terminator::GotoIndirect { target } if *target != NO_VALUE => mark(*target), + Terminator::GotoIndirect { target } | Terminator::JumpTable { idx: target, .. } + if *target != NO_VALUE => + { + mark(*target) + } _ => {} } } @@ -2033,9 +2050,11 @@ fn extend_last_use_across_blocks(func: &FunctionSsa, last_use: &mut [u32]) { for b in (0..nblocks).rev() { let base = b * words; scratch.iter_mut().for_each(|w| *w = 0); - for s in - super::mem2reg::successors(&func.blocks[b].terminator, &func.computed_goto_targets) - { + for s in super::mem2reg::successors( + &func.blocks[b].terminator, + &func.computed_goto_targets, + &func.jump_tables, + ) { let sb = s as usize * words; for w in 0..words { scratch[w] |= live_in[sb + w]; @@ -2099,53 +2118,24 @@ fn compute_calls_after_def( } /// Promote each phi class's `calls_after_def` flag so every member -/// inherits the class's combined call-crossing status. Without this, -/// `compute_calls_after_def` reads per-value `last_use[v]` -- a class -/// member whose own last use does not cross any call but whose -/// *class root* lives past a call would be placed in a caller-saved -/// register and clobbered by that call. +/// inherits the class's combined call-crossing status: the class flag +/// is the OR of the members' CFG-precise per-value flags. Class +/// members share one register, so if any member is live across a call +/// the shared register must be callee-saved. Where no member is live +/// the shared register holds nothing a call could clobber, so the +/// class stays eligible for a caller-saved home. fn promote_calls_after_def_to_classes( classes: &mut super::phi_class::PhiClasses, - func: &FunctionSsa, - class_last_use: &[u32], - target: Target, calls_after_def: &mut [bool], ) { - let tls_addr_is_call = matches!(target, Target::MacOSAarch64); - let n = func.insts.len(); - let mut call_pcs: Vec = Vec::new(); - for (idx, inst) in func.insts.iter().enumerate() { - let is_call = matches!( - inst, - Inst::Call { .. } | Inst::CallIndirect { .. } | Inst::CallExt { .. } - ) || (tls_addr_is_call && matches!(inst, Inst::TlsAddr(_))) - || is_setjmp_barrier(inst); - if is_call { - call_pcs.push(idx as u32); - } - } - call_pcs.sort_unstable(); - // For every value, check whether any call sits between the - // class's first definition (= class root's PC) and the class's - // combined last use. If so, every member of the class needs a - // callee-saved placement. let mut class_must_callee: alloc::collections::BTreeMap = alloc::collections::BTreeMap::new(); - for v in 0..n { + for (v, &crosses) in calls_after_def.iter().enumerate() { let root = classes.find(v as ValueId); - if class_must_callee.contains_key(&root) { - continue; - } - let lo = call_pcs.binary_search(&(root + 1)).unwrap_or_else(|i| i); - let crosses_call = call_pcs - .get(lo) - .map(|&first| first < class_last_use[root as usize]) - .unwrap_or(false); - class_must_callee.insert(root, crosses_call); + *class_must_callee.entry(root).or_insert(false) |= crosses; } - for (v, entry) in calls_after_def.iter_mut().enumerate().take(n) { - let root = classes.find(v as ValueId); - if class_must_callee[&root] { + for (v, entry) in calls_after_def.iter_mut().enumerate() { + if class_must_callee[&classes.find(v as ValueId)] { *entry = true; } } @@ -2322,7 +2312,15 @@ int main(void) { return 0; } int_node(false, None), int_node(false, None), ]; - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert_eq!(r.spill_count, 0); let regs: Vec = r.places.clone(); assert_ne!(regs[0], regs[1]); @@ -2339,7 +2337,15 @@ int main(void) { return 0; } let g = Interference::from_edges(5, &edges); let node_of = [0u32, 1, 2, 3, 4]; let cons: Vec> = (0..5).map(|_| int_node(false, None)).collect(); - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert_eq!( r.spill_count, 1, "four registers, five live values -> one spill" @@ -2352,6 +2358,47 @@ int main(void) { return 0; } assert_eq!(spilled, 1); } + #[test] + fn returns_twice_caller_never_shares_spill_slots() { + // Nodes 0-3 fill the four registers; 4 and 5 both spill and do + // not interfere with each other, so slot sharing would give + // them one slot. A returns-twice caller (setjmp / vfork) must + // keep the slots distinct: the value dead on the first-return + // path is still read after the second return (C99 7.13.2.1p3). + let mut edges: Vec<(u32, u32)> = (0..4u32) + .flat_map(|a| (a + 1..4u32).map(move |b| (a, b))) + .collect(); + for spilled in [4u32, 5] { + edges.extend((0..4u32).map(|r| (r, spilled))); + } + let g = Interference::from_edges(6, &edges); + let node_of = [0u32, 1, 2, 3, 4, 5]; + let cons: Vec> = (0..6).map(|_| int_node(false, None)).collect(); + let shared = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); + assert_eq!(shared.spill_count, 1, "non-interfering spills share"); + assert_eq!(shared.places[4], shared.places[5]); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + true, + ); + assert_eq!(r.spill_count, 2, "returns-twice: one slot per value"); + assert_eq!(r.places[4], Place::Spill(0)); + assert_eq!(r.places[5], Place::Spill(1)); + } + #[test] fn must_callee_node_avoids_caller_saved() { // A single call-crossing node must land in a callee-saved @@ -2359,7 +2406,15 @@ int main(void) { return 0; } let g = Interference::from_edges(1, &[]); let node_of = [0u32]; let cons = [int_node(true, None)]; - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert!( matches!(r.places[0], Place::IntReg(20) | Place::IntReg(21)), "call-crossing value must take a callee-saved register, got {:?}", @@ -2374,7 +2429,15 @@ int main(void) { return 0; } let g = Interference::from_edges(1, &[]); let node_of = [0u32]; let cons = [int_node(false, None)]; - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert!( matches!(r.places[0], Place::IntReg(0) | Place::IntReg(1)), "non-crossing value should prefer caller-saved, got {:?}", @@ -2387,7 +2450,15 @@ int main(void) { return 0; } let g = Interference::from_edges(2, &[(0, 1)]); let node_of = [0u32, 1]; let cons = [int_node(false, Some(21)), int_node(false, None)]; - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert_eq!( r.places[0], Place::IntReg(21), @@ -2403,7 +2474,15 @@ int main(void) { return 0; } let g = Interference::from_edges(3, &[(0, 2)]); let node_of = [0u32, 0, 2]; let cons = [int_node(false, None), None, int_node(false, None)]; - let r = color_graph(&g, &node_of, &cons, &tiny_banks(), usize::MAX, usize::MAX); + let r = color_graph( + &g, + &node_of, + &cons, + &tiny_banks(), + usize::MAX, + usize::MAX, + false, + ); assert_eq!(r.places[0], r.places[1], "class members share a register"); assert_ne!(r.places[0], r.places[2]); } @@ -2822,8 +2901,11 @@ int main(void) { return 0; } ret_is_fp: false, indirect_result_slot: 0, computed_goto_targets: Vec::new(), + jump_tables: Vec::new(), synthetic_base: 0, multi_cell_slots: Vec::new(), + has_returns_twice_call: false, + did_unroll: false, insts, blocks, extern_call_refs: Vec::new(), diff --git a/src/c5/codegen/ssa/slot_coalesce.rs b/src/c5/codegen/ssa/slot_coalesce.rs index 990e4c35e..cfa10282e 100644 --- a/src/c5/codegen/ssa/slot_coalesce.rs +++ b/src/c5/codegen/ssa/slot_coalesce.rs @@ -54,6 +54,14 @@ pub(crate) fn run(funcs: &mut [FunctionSsa]) -> CoalesceDwarf { } fn coalesce(f: &mut FunctionSsa) -> BTreeMap> { + // A returns-twice call (setjmp family / vfork) re-enters the frame + // after the first-return path ran: live ranges from ordinary + // liveness do not bound slot lifetime (C99 7.13.2.1p3), so every + // slot stays dedicated -- the same rule the register allocator + // applies to spill slots. + if f.has_returns_twice_call { + return BTreeMap::new(); + } // `synthetic_base > 0` marks a walker-built function with declared // locals; hand-built SSA (sys-trampolines, CRT entry) carries 0 and is // left alone -- its slot model is not the walker's. @@ -272,7 +280,7 @@ fn coalesce(f: &mut FunctionSsa) -> BTreeMap> { .blocks .iter() .map(|blk| { - successors(&blk.terminator, &f.computed_goto_targets) + successors(&blk.terminator, &f.computed_goto_targets, &f.jump_tables) .iter() .map(|&b| b as usize) .collect() diff --git a/src/c5/codegen/x86_64/emit.rs b/src/c5/codegen/x86_64/emit.rs index 6061c54ae..0672e2216 100644 --- a/src/c5/codegen/x86_64/emit.rs +++ b/src/c5/codegen/x86_64/emit.rs @@ -1536,11 +1536,15 @@ pub(crate) fn emit_function( moves.push((Place::IntReg(src), dst)); vids.push(vid); homes.push(dst); - // Sign-extend on entry only when a consumer reads the - // parameter's upper bits; otherwise the low word already - // holds the C99 6.5.2.2p4-converted value. - if matches!(kind, LoadKind::I8 | LoadKind::I16 | LoadKind::I32) - && alloc.high_observed.get(vid).copied().unwrap_or(true) + // The caller passes the raw 64-bit value; the callee + // performs the C99 6.5.2.2p4 conversion. An I8/I16 extend + // rewrites bits 8..63 / 16..63 and is always required; an + // I32 extend touches only bits 32..63 and is skipped when + // no consumer reads them (`high_observed` tracks exactly + // that range). + if matches!(kind, LoadKind::I8 | LoadKind::I16) + || (matches!(kind, LoadKind::I32) + && alloc.high_observed.get(vid).copied().unwrap_or(true)) { exts.push((dst, *kind)); } @@ -1585,6 +1589,10 @@ pub(crate) fn emit_function( // final `block_offsets` after the relaxation passes settle (only the // disp32 is patched, so the destination register need not be saved). let mut block_addr_fixups: Vec<(usize, u32)> = Vec::new(); + // Text-embedded jump tables: `(table_start, table_idx)` per + // `Terminator::JumpTable`. Each 32-bit entry is patched to + // `block_offset - table_start` after the relaxation passes settle. + let mut jump_table_fixups: Vec<(usize, u32)> = Vec::new(); // Branch relaxation. The block loop runs once with every local // branch in the rel32 long form (`branch_short` empty), then, when // `relax_branches` finds shortenable branches, once more with the @@ -1611,6 +1619,7 @@ pub(crate) fn emit_function( let mut current_alloca_top: u32 = 0; // Re-collected each relaxation pass; resolved after the loop. block_addr_fixups.clear(); + jump_table_fixups.clear(); for (block_idx, block) in func.blocks.iter().enumerate() { block_offsets[block_idx] = code.len(); @@ -1949,6 +1958,43 @@ pub(crate) fn emit_function( }; super::encode::emit_jmp_r(code, rt); } + Terminator::JumpTable { idx, table } => { + // Table dispatch: `lea` the table base (embedded + // right after the `jmp`), sign-extend the 32-bit + // table-relative entry, add, and branch. The bounds + // check preceding this terminator proves the index + // in range. + let iplace = alloc + .places + .get(idx as usize) + .copied() + .unwrap_or(Place::None); + let Some(rt) = materialize_int(code, iplace, SCRATCH_R10, frame) else { + bail_msg("JumpTable: idx Place not int reg / spill"); + code.truncate(snapshot); + fixups.truncate(fixups_snapshot); + plt_call_fixups.truncate(plt_call_fixups_snapshot); + data_fixups.truncate(data_fixups_snapshot); + user_extern_data_refs.truncate(user_extern_data_refs_snapshot); + pending_func_fixups.truncate(pending_func_fixups_snapshot); + return false; + }; + // rt is an allocated register or SCRATCH_R10, never + // r11, so the table base cannot alias it. The lea's + // disp32 spans a fixed distance to the table, so it + // is patched here rather than post-layout. + let lea_start = code.len(); + super::encode::emit_lea_r_rip32(code, SCRATCH_R11, 0); + super::encode::emit_movsxd_r_sib(code, SCRATCH_R10, SCRATCH_R11, rt, 4); + super::encode::emit_add_rr(code, SCRATCH_R10, SCRATCH_R11); + super::encode::emit_jmp_r(code, SCRATCH_R10); + let table_start = code.len(); + let disp = (table_start - (lea_start + super::encode::LEA_RIP32_LEN)) as i32; + code[lea_start + 3..lea_start + 7].copy_from_slice(&disp.to_le_bytes()); + jump_table_fixups.push((table_start, table)); + let entries = func.jump_tables[table as usize].len(); + code.resize(code.len() + entries * 4, 0); + } Terminator::TailExt(binding_idx) => { // The parser emits `Terminator::TailExt` for the // sys-trampoline bodies: the matching indirect @@ -2040,6 +2086,20 @@ pub(crate) fn emit_function( code[*lea_start + 3..*lea_start + 7].copy_from_slice(&imm.to_le_bytes()); } + // Patch each jump table's entries with the target block's offset + // relative to the table base. + for (table_start, table) in &jump_table_fixups { + for (i, &t) in func.jump_tables[*table as usize].iter().enumerate() { + let rel = block_offsets[t as usize] as i64 - *table_start as i64; + debug_assert!( + i32::try_from(rel).is_ok(), + "JumpTable: entry offset out of i32 range" + ); + let site = table_start + i * 4; + code[site..site + 4].copy_from_slice(&(rel as i32).to_le_bytes()); + } + } + // Patch recorded branches. The displacement is measured from the // byte after the displacement field: `site + 1` for the rel8 short // form, `site + 4` for rel32. `relax_branches` guarantees a short @@ -2796,30 +2856,31 @@ fn emit_inst( return false; } }; - // Skip the entry sign-extension when no consumer reads the - // parameter's upper bits; the low word already holds it. + // The caller passes the raw 64-bit value, so an I8/I16 + // conversion always runs; an I32 extend touches only + // bits 32..63 and is skipped when no consumer reads them. let high_dead = !alloc.high_observed.get(v as usize).copied().unwrap_or(true); let materialize = |code: &mut Vec, rd: Reg| { if from_home { match kind { - _ if high_dead => emit_mov_r_mem(code, rd, Reg::RBP, home_off), LoadKind::I8 => { super::encode::emit_movsx_r_mem8(code, rd, Reg::RBP, home_off) } LoadKind::I16 => { super::encode::emit_movsx_r_mem16(code, rd, Reg::RBP, home_off) } - LoadKind::I32 => { + LoadKind::I32 if !high_dead => { super::encode::emit_movsxd_r_mem(code, rd, Reg::RBP, home_off) } _ => emit_mov_r_mem(code, rd, Reg::RBP, home_off), } } else { match kind { - _ if high_dead => emit_mov_rr(code, rd, arg_reg), LoadKind::I8 => super::encode::emit_movsx_r_r8(code, rd, arg_reg), LoadKind::I16 => super::encode::emit_movsx_r_r16(code, rd, arg_reg), - LoadKind::I32 => super::encode::emit_movsxd_r_r(code, rd, arg_reg), + LoadKind::I32 if !high_dead => { + super::encode::emit_movsxd_r_r(code, rd, arg_reg) + } _ => emit_mov_rr(code, rd, arg_reg), } } diff --git a/src/c5/codegen/x86_64/encode.rs b/src/c5/codegen/x86_64/encode.rs index 70f8ca8de..e9d577027 100644 --- a/src/c5/codegen/x86_64/encode.rs +++ b/src/c5/codegen/x86_64/encode.rs @@ -1965,6 +1965,15 @@ pub(crate) fn lower( } } }); + // Unroll constant-trip loops after mem2reg (the loop-carried + // values are phis by then) and before the inliner, so a helper + // whose body was a short loop becomes a single-block inline + // candidate and the cloned call sites join the inliner's + // worklist. The post-inline constant folder then collapses the + // per-copy `Extend(Imm)` / `BinopI(Imm, k)` index chains. + super::ssa::emit_common::time_pass("passes::unroll::run (x86_64)", || { + crate::c5::codegen::passes::unroll::run(&mut ssa_funcs); + }); // Inline after mem2reg so the candidate filter sees the // promoted form: dead cell loads / stores are gone and the // callee's body reads its parameters via `ParamRef`. @@ -1982,6 +1991,33 @@ pub(crate) fn lower( super::ssa::emit_common::time_pass("passes::struct_return_reg::run (x86_64)", || { crate::c5::codegen::passes::struct_return_reg::run(&mut ssa_funcs); }); + // Constant folding over the post-inline tape: `Extend(Imm)` / + // `Binop(Imm, Imm)` chains left by parameter substitution fold + // to plain `Imm`, and immediate-operand binops take `BinopI` + // form, so the rotate matcher and the branch folder see + // constants. + super::ssa::emit_common::time_pass("passes::constfold::run (x86_64)", || { + crate::c5::codegen::passes::constfold::run(&mut ssa_funcs); + }); + // Split constant-index local arrays that unrolling exposed into + // per-element slots and re-run mem2reg to promote them to SSA + // values. Gated to functions the unroll pass expanded so the + // mem2reg rebuild is confined; the promoted element slots feed + // the same debug-info location drop as the initial mem2reg. + super::ssa::emit_common::time_pass("passes::sroa::run (x86_64)", || { + let usable_gpr = super::ssa::reg_alloc::usable_gpr_count(target); + for f in &mut ssa_funcs { + if f.did_unroll { + let promoted = crate::c5::codegen::passes::sroa::run(f, usable_gpr); + if !promoted.is_empty() { + promoted_local_slots + .entry(f.ent_pc) + .or_default() + .extend(promoted); + } + } + } + }); // Rotate idiom recognition: collapses `(x >> c) | (x << (W - // c))` chains to `BinopI(Ror, x, c)`. Runs after the inliner // so post-inline parameter substitutions expose the constant @@ -2022,6 +2058,13 @@ pub(crate) fn lower( super::ssa::emit_common::time_pass("passes::store_forward::run (x86_64)", || { crate::c5::codegen::passes::store_forward::run(&mut ssa_funcs); }); + // Block layout: fallthrough chains, loop rotation to + // bottom-test, branch inversion. Reorders blocks and remaps + // block ids only, so it runs last; the emit elides jumps to + // the next block in the new order. + super::ssa::emit_common::time_pass("passes::layout::run (x86_64)", || { + crate::c5::codegen::passes::layout::run(&mut ssa_funcs); + }); } // Upper bound on ent_pcs the lowering will reference. The // walker stamps `ent_pc` / `end_pc` against the ent_pc diff --git a/src/c5/compiler/call_fixups.rs b/src/c5/compiler/call_fixups.rs index b161bf373..32ed9a952 100644 --- a/src/c5/compiler/call_fixups.rs +++ b/src/c5/compiler/call_fixups.rs @@ -261,6 +261,9 @@ impl Compiler { // FunctionSsa with a deterministic name so the symbol // table and DWARF subprogram DIEs identify it. sb.set_name(alloc::format!("__c5_sys_{}", self.symbols[sys_idx].name)); + if crate::c5::ir::returns_twice_fn_name(&self.symbols[sys_idx].name) { + sb.mark_returns_twice(); + } let _alloca = sb.alloca_init(0); // Zero-arg and arg-forwarding shapes both flow through // the standard `call_ext + return` pair so the codegen diff --git a/src/c5/compiler/const_expr.rs b/src/c5/compiler/const_expr.rs index 29881569b..fc307d5ed 100644 --- a/src/c5/compiler/const_expr.rs +++ b/src/c5/compiler/const_expr.rs @@ -374,7 +374,7 @@ impl Compiler { /// contributes to the resulting value, matching clang/gcc. /// The `:` arm recurses back into `parse_const_expr_cond_val` so /// `a ? b : c ? d : e` parses right-associatively. - fn parse_const_expr_cond_val(&mut self) -> Result { + pub(super) fn parse_const_expr_cond_val(&mut self) -> Result { let cond = self.parse_const_expr_or_val()?; if self.lex.tk == Token::Cond { self.next()?; @@ -880,6 +880,13 @@ impl Compiler { // the cast clamps it back to integer per C99 6.3.1.4. if self.lex_is_type_start() { let mut target_ty = self.parse_decl_base_type()?; + // The type is consumed as a cast, not bound through a + // declarator; drop the declarator side channels it may set. + self.pending.base_is_function_type = false; + self.pending.bare_function_type_declarator = false; + self.pending.fn_ptr_indirection = None; + self.pending.typedef_fn_proto = None; + self.pending.fn_ptr_param_types = None; while self.lex.tk == Token::MulOp { self.next()?; target_ty += Ty::Ptr as i64; diff --git a/src/c5/compiler/expr.rs b/src/c5/compiler/expr.rs index dc32bba42..5f18968d8 100644 --- a/src/c5/compiler/expr.rs +++ b/src/c5/compiler/expr.rs @@ -448,15 +448,18 @@ impl Compiler { self.ast_emit_int_lit(val, self.ty); self.next()?; } else if self.lex.tk == Token::FloatNum { - // C99 6.4.4.2: floating constant. The lexer parsed - // `1.5` etc. into f64 and stored `f64::to_bits()` cast - // to i64 in `ival`. The byte pattern flows through - // the integer-literal emit unmodified; the codegen - // reads it back via `f64::from_bits` when the - // surrounding `self.ty` marks the value as floating. + // C99 6.4.4.2p4: an unsuffixed floating constant has + // type double, `f`/`F` float, `l`/`L` long double + // (represented as f64 in c5). The lexer stored the + // value -- already rounded to single precision for + // `f`/`F` -- as `f64::to_bits()` cast to i64 in `ival`. let bits = self.lex.ival as u64; self.emit_imm(self.lex.ival); - self.ty = Ty::Double as i64; + self.ty = if self.lex.float_suffix_f32 { + Ty::Float as i64 + } else { + Ty::Double as i64 + }; self.ast_emit_float_lit(bits, self.ty); self.next()?; } else if self.lex.tk == '"' { diff --git a/src/c5/compiler/global_init.rs b/src/c5/compiler/global_init.rs index d01a61ef1..15cd3752c 100644 --- a/src/c5/compiler/global_init.rs +++ b/src/c5/compiler/global_init.rs @@ -26,15 +26,19 @@ use super::types::{ }; impl Compiler { - /// After a leading `(TYPE)` cast in a global initializer, returns - /// true when the cast applies to a relocation-bearing leaf (`&x`, a + /// After a leading `(TYPE)` cast in an initializer, returns true + /// when the cast applies to a relocation-bearing leaf (`&x`, a /// string literal, or a function / global-array name) rather than an /// arithmetic value. Reloc leaves keep the address-folding path; an /// arithmetic cast must instead reach the const-expr evaluator, which /// narrows per C99 6.3.1.3. Entry is positioned just inside the cast /// paren (depth 1); the lexer is restored before returning. - fn post_cast_is_reloc_leaf(&mut self) -> Result { + pub(super) fn post_cast_is_reloc_leaf(&mut self) -> Result { let snap = self.lex.snapshot(); + // The scan may lex a string literal, whose bytes the lexer + // appends to the data segment; the snapshot does not cover + // the data segment, so truncate it back before returning. + let data_snap = self.data.len(); let mut depth: i64 = 1; while depth > 0 && self.lex.tk != 0 { if self.lex.tk == '(' { @@ -48,8 +52,28 @@ impl Compiler { } self.next()?; } - while self.lex.tk == '(' { + // The leaf may sit behind grouping parens and further casts + // (`(T)(((U)(fn)))`); skip both to reach it. + loop { + if self.lex.tk != '(' { + break; + } self.next()?; + if self.lex_is_type_start() { + let mut d: i64 = 1; + while d > 0 && self.lex.tk != 0 { + if self.lex.tk == '(' { + d += 1; + } else if self.lex.tk == ')' { + d -= 1; + if d == 0 { + self.next()?; + break; + } + } + self.next()?; + } + } } let reloc = self.lex.tk == Token::AndOp || self.lex.tk == '"' @@ -61,6 +85,7 @@ impl Compiler { && self.symbols[self.lex.curr_id_idx].array_size != 0) }); self.lex.restore(snap); + self.data.truncate(data_snap); Ok(reloc) } diff --git a/src/c5/compiler/initializer.rs b/src/c5/compiler/initializer.rs index 46ee6fd82..eacf4da95 100644 --- a/src/c5/compiler/initializer.rs +++ b/src/c5/compiler/initializer.rs @@ -955,9 +955,10 @@ impl Compiler { } // `(type)expr` cast or `(expr)` parenthesized constant in a // static initializer. After consuming `(`, peek the next - // token: if it starts a type, treat as a cast and recurse on - // the value (c5's i64-shaped representation makes integer / - // pointer casts no-ops). Otherwise it's a parenthesized + // token: if it starts a type, treat as a cast -- arithmetic + // operands go through the const-expr evaluator (which applies + // the cast's conversion), relocation-bearing leaves recurse + // with the cast dropped. Otherwise it's a parenthesized // constant expression -- evaluate it and expect `)`. if self.lex.tk == '(' { // Cast / float-content detection both need to look @@ -996,6 +997,21 @@ impl Compiler { if self.lex.tk == Token::Brak { return self.parse_array_compound_literal(cast_ty); } + // A cast of an arithmetic operand converts to the target + // type (C99 6.5.4, 6.3.1.3); route the element through the + // constant-expression evaluator, which applies every cast + // in the chain at its own width, so + // `(long)(int)0x92492493` sign-extends through `int`. + // Only a cast of a relocation-bearing leaf keeps the + // skip-and-recurse path below, where the value is the + // leaf's address and the cast merely retypes it. + if !self.post_cast_is_reloc_leaf()? { + self.lex.restore(snap); + return Ok(match self.parse_const_expr_cond_val()? { + ConstVal::Float(f) => (f.to_bits() as i64, InitElemReloc::Float64Bits), + v @ ConstVal::Int { .. } => (v.as_int(), InitElemReloc::None), + }); + } // Optional function-pointer abstract declarator // `(*)(args)` after the base type. Same treatment // as in the expression-level cast handler: scan diff --git a/src/c5/compiler/locals.rs b/src/c5/compiler/locals.rs index 4d775f630..5a5af4a7b 100644 --- a/src/c5/compiler/locals.rs +++ b/src/c5/compiler/locals.rs @@ -496,8 +496,19 @@ impl Compiler { /// element with runtime stores at the declaration point. The data /// image holds zeros; each element is parsed through the expression /// grammar (so `&&label` yields a block-address node) and stored into - /// `arr[i]` via an `Expr::Assign` statement the walker lowers to a - /// global address store. A constant element is stored the same way. + /// `arr[i]` via an `Expr::Assign` the walker lowers to a global + /// address store. A constant element is stored the same way. + /// + /// C99 6.2.4p3: static storage duration means one initialization for + /// the whole program run, so the stores are wrapped in a hidden + /// once-guard: a guard byte placed directly after the array's storage + /// (same data object -- no object start in between -- so data DCE and + /// linker rebase move it with the array). The whole declaration + /// lowers to a single statement `guard ? 0 : (e0, ..., en, guard = 1)` + /// because the enclosing declaration parse captures every pushed + /// stmt id as a top-level block item. + /// TODO: the generic fix resolves `&&label` elements in the data + /// image via label relocations, removing the runtime stores. pub(super) fn emit_static_array_init_runtime( &mut self, loc_idx: usize, @@ -522,12 +533,17 @@ impl Compiler { } c }; + let guard_off = self.data.len() as i64 - self.symbols[loc_idx].val; + for _ in 0..8 { + self.data.push(0); + } debug_assert!(self.lex.tk == '{'); self.next()?; // consume `{` // The array Ident decays to its base address; the index is the // element's byte offset, matching the walker's pre-scaled // `Expr::Index` convention. let arr_ty = ty + Ty::Ptr as i64; + let mut assigns: alloc::vec::Vec = alloc::vec::Vec::new(); let mut i: i64 = 0; while self.lex.tk != '}' { // Optional designator: `[N] = ...` (C99 6.7.8p6) or the GCC @@ -595,14 +611,65 @@ impl Compiler { }, pos, ); - self.ast - .push_stmt(super::super::ast::Stmt::Expr(assign_id), pos); + assigns.push(assign_id); } } i = range_end + 1; self.accept(',')?; } self.next()?; // consume `}` + if let Some(&first) = assigns.first() { + use super::super::ast::Expr; + let g_ty = Ty::Char as i64; + let guard_at = |c: &mut Self| { + let base = c.ast_emit_ident(loc_idx as u32, arr_ty); + let idx = c.ast_emit_int_lit(guard_off, Ty::Int as i64); + let pos = c.ast_src_pos(); + c.ast.push_expr( + Expr::Index { + array: base, + idx, + ty: g_ty, + }, + pos, + ) + }; + let guard_read = guard_at(self); + let guard_lhs = guard_at(self); + let one = self.ast_emit_int_lit(1, Ty::Int as i64); + let pos = self.ast_src_pos(); + let guard_set = self.ast.push_expr( + Expr::Assign { + lhs: guard_lhs, + rhs: one, + ty: g_ty, + }, + pos, + ); + let mut chain = first; + for &e in assigns.iter().skip(1).chain(core::iter::once(&guard_set)) { + chain = self.ast.push_expr( + Expr::Comma { + lhs: chain, + rhs: e, + ty: g_ty, + }, + pos, + ); + } + let zero = self.ast_emit_int_lit(0, Ty::Int as i64); + let guarded = self.ast.push_expr( + Expr::Ternary { + cond: guard_read, + then_e: zero, + else_e: chain, + ty: Ty::Int as i64, + }, + pos, + ); + self.ast + .push_stmt(super::super::ast::Stmt::Expr(guarded), pos); + } self.ast_acc = None; Ok(()) } diff --git a/src/c5/compiler/mod.rs b/src/c5/compiler/mod.rs index df0952b57..31c02e980 100644 --- a/src/c5/compiler/mod.rs +++ b/src/c5/compiler/mod.rs @@ -220,6 +220,10 @@ pub struct CompileOptions { /// for auto-included names another input defines, so the user's /// definition wins over the header's library binding. pub implicit_extern_fns: Vec, + /// `-O` -- predefine `NDEBUG` and `__OPTIMIZE__`, both `1`, so a + /// single flag selects release semantics (optimization passes plus + /// asserts compiled out). Explicit `-D` / `-U` flags override. + pub optimize: bool, } impl CompileOptions { @@ -238,6 +242,11 @@ impl CompileOptions { self.undefines = undefines; self } + /// Enable the `-O` predefines. See [`Self::optimize`]. + pub fn with_optimize(mut self, on: bool) -> Self { + self.optimize = on; + self + } /// Replace the `-I` include-search-path list. pub fn with_include_paths(mut self, include_paths: Vec) -> Self { self.include_paths = include_paths; @@ -1219,6 +1228,12 @@ impl Compiler { for name in &opts.force_includes { pp.add_force_include(name); } + // `-O` predefines, installed before the CLI lists so an explicit + // `-D NDEBUG=` overrides the value and `-U NDEBUG` removes it. + if opts.optimize { + pp.define("NDEBUG", "1"); + pp.define("__OPTIMIZE__", "1"); + } for (name, body) in &opts.defines { pp.define(name, body); } diff --git a/src/c5/ir.rs b/src/c5/ir.rs index 956127439..014e38066 100644 --- a/src/c5/ir.rs +++ b/src/c5/ir.rs @@ -540,6 +540,13 @@ pub(crate) enum Terminator { /// whose address is taken via `&&label`); the CFG treats this as /// a branch to all of them. GotoIndirect { target: ValueId }, + /// Indexed branch through a per-function jump table: control + /// transfers to `jump_tables[table][idx]`. The switch lowering + /// proves `idx` in range with an unsigned bounds check before + /// this terminator, so no entry is out of bounds at runtime. + /// The target list lives in [`FunctionSsa::jump_tables`] + /// because `Terminator` is `Copy`. + JumpTable { idx: ValueId, table: u32 }, /// Synthetic fall-through to a successor block. Preserved /// on the variant for object-file round-trips of SSA bodies /// that already carry it; new IR producers should use the @@ -720,6 +727,12 @@ pub(crate) struct FunctionSsa { /// treat an indirect branch as a branch to all of these. Empty /// for functions with no computed goto. pub computed_goto_targets: Vec, + /// Target-block lists for the function's `Terminator::JumpTable` + /// terminators, keyed by the terminator's `table` index. Entry + /// `i` is the successor for a runtime index of `i`; blocks may + /// repeat (case-value holes point at the default block). Empty + /// for functions with no jump table. + pub jump_tables: Vec>, /// Boundary between the parser's declared local slots and the SSA /// builder's synthetic slots. `set_locals` records the declared- /// plus-alloca count here; every slot reserved afterward by @@ -739,4 +752,32 @@ pub(crate) struct FunctionSsa { /// an interior cell, which is referenced by no instruction. Empty for SSA /// built outside the walker. pub multi_cell_slots: Vec<(i64, i64)>, + /// True when the body calls a function that may return twice into + /// this frame: the setjmp family (C99 7.13) or vfork(2). Ordinary + /// liveness under-approximates storage lifetime here -- a value + /// dead on the first-return path is still read after the second + /// return (C99 7.13.2.1p3), and under vfork the child's writes + /// land on the parent's stack. Spill-slot sharing and frame-slot + /// coalescing are disabled when set, and the inliner keeps such a + /// body out of line. + pub has_returns_twice_call: bool, + /// True once `passes::unroll` fully expanded at least one loop in this + /// function. Set by the unroll pass; read by the post-inline scalar + /// promotion (`passes::sroa`) to gate its mem2reg re-run to functions + /// whose constant-trip loops turned array subscripts into constant + /// offsets. False for every function the unroll pass left unchanged. + pub did_unroll: bool, +} + +/// External functions that may return twice into the caller's frame: +/// the setjmp family (C99 7.13.1.1) plus vfork(2). Matched on the +/// c5-side symbol name; `__c5_msvcrt_setjmp` is the target of the +/// Windows x86_64 `setjmp` macro (headers/include/setjmp.h). The +/// AArch64 inline setjmp is an intrinsic, recognised structurally by +/// `codegen::ssa::reg_alloc::is_setjmp_barrier`. +pub(crate) fn returns_twice_fn_name(name: &str) -> bool { + matches!( + name, + "setjmp" | "_setjmp" | "sigsetjmp" | "__sigsetjmp" | "__c5_msvcrt_setjmp" | "vfork" + ) } diff --git a/src/c5/lexer.rs b/src/c5/lexer.rs index 37c9ee851..eb22b3a64 100644 --- a/src/c5/lexer.rs +++ b/src/c5/lexer.rs @@ -240,6 +240,13 @@ pub(crate) struct Lexer { /// decimal constant with no `u` suffix stays signed. pub int_is_decimal: bool, + /// `true` when the most recent `Token::FloatNum` carried an `f`/`F` + /// suffix (C99 6.4.4.2p4: the constant has type `float`). `ival` + /// then holds the value already rounded to single precision, + /// re-widened to f64 bits. An `l`/`L` suffix keeps the flag false: + /// c5 represents long double as f64. + pub float_suffix_f32: bool, + /// `true` when the most recent `'"'` string-literal token came from /// a wide (`L"..."`) literal. The element width follows /// `wchar_bytes`; the initializer and expression parsers read this @@ -385,6 +392,7 @@ impl Lexer { int_suffix_long: 0, int_suffix_unsigned: false, int_is_decimal: true, + float_suffix_f32: false, str_is_wide: false, wchar_bytes: 4, char_signed: true, @@ -484,10 +492,11 @@ impl Lexer { ))); } let mut exp = if exp_neg { -exp } else { exp }; - // The `f`/`F`/`l`/`L` suffix only selects the type; c5 stores - // every floating constant as f64, so it is consumed and - // discarded. + // C99 6.4.4.2p4: `f`/`F` types the constant `float`, `l`/`L` + // long double (represented as f64 in c5). Record the float + // suffix; the value is rounded to single precision below. if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } // Scale by 2^exp through exact doubling / halving so the @@ -500,6 +509,11 @@ impl Lexer { mant *= 0.5; exp += 1; } + // An `f`-suffixed constant is a value of type float (C99 + // 6.4.4.2p4-5): round to single precision, kept as f64 bits. + if self.float_suffix_f32 { + mant = mant as f32 as f64; + } Ok(mant) } @@ -1000,6 +1014,7 @@ impl Lexer { self.int_suffix_long = 0; self.int_suffix_unsigned = false; self.int_is_decimal = true; + self.float_suffix_f32 = false; loop { if self.pos >= self.src.len() { self.tk = Tok::EOF; @@ -1269,11 +1284,10 @@ impl Lexer { if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { - // Consume the floating-point suffix per C99 - // 6.4.4.2: `f`/`F` is float, `l`/`L` is long - // double. The c5 dialect aliases long double - // to double, so every suffix lands in `f64` - // and the suffix is purely informational. + // Floating-point suffix per C99 6.4.4.2p4: + // `f`/`F` types the constant `float`, `l`/`L` + // long double (represented as f64 in c5). + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } let lit = @@ -1283,12 +1297,18 @@ impl Lexer { self.line ))) })?; - let f: f64 = lit.parse().map_err(|e| { + let mut f: f64 = lit.parse().map_err(|e| { C5Error::Compile(crate::c5::error::fmt_internal_err(&format!( "{}: malformed float literal `{lit}`: {e}", self.line ))) })?; + // An `f`-suffixed constant is a value of type float + // (C99 6.4.4.2p5): round to single precision, kept + // as f64 bits. + if self.float_suffix_f32 { + f = f as f32 as f64; + } self.ival = f.to_bits() as i64; self.tk = Tok(Token::FloatNum as i64); return self.end_number(); @@ -1633,12 +1653,11 @@ impl Lexer { if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { - // Floating-point suffix (C99 6.4.4.2): - // `f`/`F` -> float, `l`/`L` -> long - // double. The c5 dialect aliases long - // double to double, so the suffix is - // informational and the bytes land in - // `f64`. + // Floating-point suffix per C99 + // 6.4.4.2p4: `f`/`F` types the constant + // `float`, `l`/`L` long double + // (represented as f64 in c5). + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } let lit = core::str::from_utf8(&self.src[int_start..body_end]) @@ -1648,12 +1667,18 @@ impl Lexer { self.line ))) })?; - let f: f64 = lit.parse().map_err(|e| { + let mut f: f64 = lit.parse().map_err(|e| { C5Error::Compile(crate::c5::error::fmt_internal_err(&format!( "{}: malformed float literal `{lit}`: {e}", self.line ))) })?; + // An `f`-suffixed constant is a value of + // type float (C99 6.4.4.2p5): round to + // single precision, kept as f64 bits. + if self.float_suffix_f32 { + f = f as f32 as f64; + } self.ival = f.to_bits() as i64; self.tk = Tok(Token::FloatNum as i64); } else { diff --git a/src/c5/tests/codegen.rs b/src/c5/tests/codegen.rs index 8ee583462..2729d8d32 100644 --- a/src/c5/tests/codegen.rs +++ b/src/c5/tests/codegen.rs @@ -917,6 +917,70 @@ fn jmp_to_next_block_falls_through() { ); } +/// Switch lowering: a dense case set (>= 8 cases, span < 2 * cases) +/// dispatches through `Terminator::JumpTable` behind an unsigned +/// bounds check to default; a hole's table slot routes to default. +/// A small or sparse set keeps the balanced compare tree. +#[test] +fn dense_switch_lowers_to_jump_table_sparse_keeps_tree() { + use crate::Target; + use crate::c5::ir::{FunctionSsa, Terminator}; + let program = super::compile_str_bare( + "int dense8(int x) { switch (x) { \ + case 3: return 1; case 4: return 2; case 5: return 3; \ + case 6: return 4; case 8: return 5; case 9: return 6; \ + case 10: return 7; case 11: return 8; default: return 0; } } \ + int dense7(int x) { switch (x) { \ + case 0: return 1; case 1: return 2; case 2: return 3; \ + case 3: return 4; case 4: return 5; case 5: return 6; \ + case 6: return 7; default: return 0; } } \ + int half8(int x) { switch (x) { \ + case 0: return 1; case 2: return 2; case 4: return 3; \ + case 6: return 4; case 8: return 5; case 10: return 6; \ + case 12: return 7; case 14: return 8; default: return 0; } } \ + int sparse8(int x) { switch (x) { \ + case 0: return 1; case 3: return 2; case 6: return 3; \ + case 9: return 4; case 12: return 5; case 15: return 6; \ + case 18: return 7; case 21: return 8; default: return 0; } } \ + int main(void) { return dense8(3) + dense7(0) + half8(0) + sparse8(0); }", + ); + let funcs = crate::c5::codegen::ssa::shadow::produce_ssa_funcs(&program, Target::host()) + .expect("produce_ssa_funcs"); + let table_of = |name: &str| -> Option<(u32, u32)> { + let f: &FunctionSsa = funcs.iter().find(|f| f.name == name).unwrap(); + f.blocks.iter().enumerate().find_map(|(b, blk)| { + if let Terminator::JumpTable { table, .. } = blk.terminator { + Some((b as u32, table)) + } else { + None + } + }) + }; + // dense8: cases 3..11 with a hole at 7 -> a 9-entry table whose + // hole slot names the same block the bounds check defaults to. + let (dispatch, table) = table_of("dense8").expect("dense8 uses a jump table"); + let dense8: &FunctionSsa = funcs.iter().find(|f| f.name == "dense8").unwrap(); + assert_eq!(dense8.jump_tables[table as usize].len(), 9); + let deflt = dense8 + .blocks + .iter() + .find_map(|blk| match blk.terminator { + Terminator::Bz { + target, + fall_through, + .. + } if fall_through == dispatch => Some(target), + _ => None, + }) + .expect("bounds check branches to default ahead of the table"); + assert_eq!(dense8.jump_tables[table as usize][4], deflt); + // half8: span 14 with 8 cases passes the 50% density gate. + assert!(table_of("half8").is_some(), "half-dense set uses a table"); + // dense7 is below the case minimum; sparse8 fails the density gate. + assert!(table_of("dense7").is_none(), "7 cases keep the tree"); + assert!(table_of("sparse8").is_none(), "sparse set keeps the tree"); +} + /// C99 6.3.1.8 + 6.5p5: the post-binop sign-narrow that renormalizes an /// `int` result is built as `Inst::Extend { kind: I32 }`, which the /// aarch64 emit lowers to `SXTW Xd, Wn` (`SBFM Xd, Xn, #0, #31`) and the diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index 487e119ed..36f658802 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1082,6 +1082,9 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("goto.c", 5), ("switch_statement.c", 25), ("switch_binary_search.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("switch_case_label_promoted.c", 0), ("int_literal_boundary_types.c", 0), ("const_expr_unsigned_fold.c", 0), @@ -1100,6 +1103,8 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("return_callee_saved_value.c", 0), ("spill_slot_reuse_disjoint_calls.c", 0), ("rotate_variable_count.c", 0), + ("rotate_inline_const_count.c", 0), + ("constfold_post_inline.c", 0), ("bitwise_not_mvn.c", 0), ("add_three_operand_lea.c", 0), ("add_sub_negative_imm.c", 0), @@ -1130,6 +1135,14 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), + ("sroa_const_index_local_array.c", 0), + ("sroa_runtime_index_stays_memory.c", 0), ("recursion_factorial.c", 120), ("return_value_in_callee_saved.c", 7), ("divmod_preserves_rdx.c", 0), @@ -1194,11 +1207,22 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -1296,6 +1320,9 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ // VM and both codegens implement. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("fp_param_float_before_double.c", 0), ("float_arg_single_precision.c", 0), @@ -1317,6 +1344,8 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -1399,6 +1428,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("inline_struct_return_reg.c", 0), ("inline_two_word_struct_return.c", 0), ("struct_return_reg_computed_goto.c", 0), + ("store_forward_local_slot.c", 0), ("inline_struct_return_escape.c", 0), ("inline_struct_param_mutated.c", 0), ("block_scope_extern.c", 0), @@ -1447,6 +1477,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("libc_pread64_pwrite64.c", 0), @@ -1570,6 +1601,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index decd95767..03954a371 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -378,6 +378,9 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("goto.c", 5), ("switch_statement.c", 25), ("switch_binary_search.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("switch_case_label_promoted.c", 0), ("int_literal_boundary_types.c", 0), ("const_expr_unsigned_fold.c", 0), @@ -404,6 +407,14 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), + ("sroa_const_index_local_array.c", 0), + ("sroa_runtime_index_stays_memory.c", 0), ("recursion_factorial.c", 120), ("pointers.c", 200), ("pointer_arithmetic_scaling.c", 104), // sizeof(int) = 4 @@ -423,6 +434,8 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("struct_param_stack_spill.c", 0), ("struct_stack_arg_then_scalar.c", 0), ("call_sp_adjust_imm12_overflow.c", 0), + ("callee_save_pair_fold.c", 17), + ("callee_save_pair_large_frame.c", 18), ("indirect_call_target_scratch_exhausted.c", 0), ("fp_load_folded_disp.c", 0), ("mixed_struct_gpr_abi.c", 0), @@ -472,11 +485,22 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -506,6 +530,8 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("return_callee_saved_value.c", 0), ("spill_slot_reuse_disjoint_calls.c", 0), ("rotate_variable_count.c", 0), + ("rotate_inline_const_count.c", 0), + ("constfold_post_inline.c", 0), ("bitwise_not_mvn.c", 0), ("add_three_operand_lea.c", 0), ("add_sub_negative_imm.c", 0), @@ -520,6 +546,8 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -595,6 +623,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("inline_struct_return_reg.c", 0), ("inline_two_word_struct_return.c", 0), ("struct_return_reg_computed_goto.c", 0), + ("store_forward_local_slot.c", 0), ("inline_struct_return_escape.c", 0), ("inline_struct_param_mutated.c", 0), ("inline_phi_caller_leaf_helper.c", 0), @@ -645,6 +674,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("libc_pread64_pwrite64.c", 0), @@ -797,6 +827,9 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ // host-platform smoke test for that pipeline. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_unary_intrinsic.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("fp_param_float_before_double.c", 0), @@ -947,6 +980,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index fee4718aa..196c0641c 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -324,6 +324,9 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("goto.c", 5), ("switch_statement.c", 25), ("switch_binary_search.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("branch_relaxation.c", 21), ("float_register_resident.c", 45), ("variadic_struct_arg.c", 18), @@ -337,6 +340,8 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("return_callee_saved_value.c", 0), ("spill_slot_reuse_disjoint_calls.c", 0), ("rotate_variable_count.c", 0), + ("rotate_inline_const_count.c", 0), + ("constfold_post_inline.c", 0), ("bitwise_not_mvn.c", 0), ("add_three_operand_lea.c", 0), ("add_sub_negative_imm.c", 0), @@ -350,6 +355,14 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), + ("sroa_const_index_local_array.c", 0), + ("sroa_runtime_index_stays_memory.c", 0), ("recursion_factorial.c", 120), ("pointers.c", 200), ("pointer_arithmetic_scaling.c", 104), // sizeof(int) = 4 @@ -400,11 +413,22 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -506,6 +530,9 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ // Full FP arithmetic + comparisons + casts. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), @@ -523,6 +550,8 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -638,6 +667,7 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("fts_and_fd_set_headers.c", 0), @@ -720,6 +750,8 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), + ("vfork_shared_stack_slot_reuse.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index 15407c8aa..34376736e 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -284,6 +284,9 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("goto.c", 5), ("switch_statement.c", 25), ("switch_binary_search.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("branch_relaxation.c", 21), ("float_register_resident.c", 45), ("variadic_struct_arg.c", 18), @@ -303,6 +306,14 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), + ("sroa_const_index_local_array.c", 0), + ("sroa_runtime_index_stays_memory.c", 0), ("recursion_factorial.c", 120), ("pointers.c", 200), ("pointer_arithmetic_scaling.c", 104), // sizeof(int) = 4 @@ -353,11 +364,22 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -457,6 +479,9 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ // cvttsd2si). ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), @@ -474,6 +499,8 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -590,6 +617,7 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("fts_and_fd_set_headers.c", 0), @@ -669,6 +697,8 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), + ("vfork_shared_stack_slot_reuse.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index e003473ba..fa1a3de8c 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -634,6 +634,14 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), + ("sroa_const_index_local_array.c", 0), + ("sroa_runtime_index_stays_memory.c", 0), ("goto.c", 5), ("recursion_factorial.c", 120), ("pointers.c", 200), @@ -681,11 +689,22 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -713,6 +732,9 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("fn_ptr_explicit_deref.c", 42), ("fn_ptr_decay_inside_block.c", 0), ("switch_nested_case_in_compound.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("ternary_middle_comma.c", 0), ("local_init_int_to_float.c", 0), ("libc_basic.c", 0), @@ -752,6 +774,9 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ // as the ELF arm64 / macOS arm64 paths. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), @@ -769,6 +794,8 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -869,6 +896,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("addr_of_intrinsic_math_float.c", 0), @@ -929,6 +957,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index eb83de562..f1df1f105 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -647,6 +647,12 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("do_while.c", 5), ("break_continue.c", 4), ("for_loop.c", 10), + ("layout_bottom_test_loop.c", 45), + ("layout_nested_loops.c", 27), + ("layout_goto_block_addr.c", 16), + ("unroll_const_trip_copy.c", 0), + ("unroll_trip_17_stays_rolled.c", 0), + ("unroll_volatile_stays_rolled.c", 0), ("goto.c", 5), ("recursion_factorial.c", 120), ("pointers.c", 200), @@ -694,11 +700,22 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), + ("narrow_param_entry_extend.c", 0), + ("qsort_scan_extend_dedup.c", 0), + ("call_arg_extend_drop.c", 0), + ("indirect_call_narrow_scalar_args.c", 0), + ("indirect_call_ten_scalar_args.c", 0), + ("indirect_call_mixed_fp_int_args.c", 0), + ("float_param_stack_overflow.c", 0), + ("indirect_call_variadic_fp_control.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), @@ -726,6 +743,9 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("fn_ptr_explicit_deref.c", 42), ("fn_ptr_decay_inside_block.c", 0), ("switch_nested_case_in_compound.c", 0), + ("switch_jump_table_dense.c", 0), + ("switch_jump_table_sparse_kept.c", 0), + ("switch_jump_table_phi_join.c", 0), ("ternary_middle_comma.c", 0), ("local_init_int_to_float.c", 0), ("libc_basic.c", 0), @@ -767,6 +787,9 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ // ABI, which this fixture doesn't exercise (no FP libc calls). ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), @@ -784,6 +807,8 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), @@ -884,6 +909,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("addr_of_intrinsic_math_float.c", 0), @@ -947,6 +973,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("block_scope_typedef_variadic_fnptr.c", 0), ("atomic_operand_in_working_regs.c", 0), ("setjmp_value_live_across.c", 0), + ("setjmp_spill_slots_unshared.c", 0), ("mixed_sse_int_aggregate_args.c", 0), ("variadic_agg_return_classes.c", 0), ("va_copy_under_pressure.c", 0), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 2db15108f..f2279a2c4 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -166,6 +166,21 @@ fn label_addr_array_init() { assert_eq!(run_fixture("label_addr_array_init.c"), 0); } +#[test] +fn static_init_once_guard() { + // C99 6.2.4p3: a static-local initialized by runtime stores + // (`&&label` elements) runs its initializer once; later calls + // must not clobber user writes to the table. + assert_eq!(run_fixture("static_init_once_guard.c"), 0); +} + +#[test] +fn computed_goto_static_table() { + // A static `&&label` dispatch table across repeated calls: the + // once-guard skip path must leave correct label addresses. + assert_eq!(run_fixture("computed_goto_static_table.c"), 0); +} + #[test] fn sieve_of_eratosthenes() { // Dense array write/read loop with a multiplicative inner stride; @@ -378,6 +393,30 @@ fn float_increment_decrement() { assert_eq!(run_fixture("float_increment_decrement.c"), 0); } +#[test] +fn compound_assign_float_register_resident() { + // A float lvalue updated via `op=` / `++` / `--` (C99 6.5.16.2, + // 6.5.2.4, 6.5.3.1) stays promotable to an FP register, matching + // the `x = x op k` form. + assert_eq!(run_fixture("compound_assign_float_register_resident.c"), 0); +} + +#[test] +fn float_literal_f_suffix() { + // C99 6.4.4.2p4-5: an `f`/`F`-suffixed floating constant has type + // `float` and its value is rounded to single precision at the + // literal. Covers sizeof, widening, the variadic default argument + // promotion, and hex-float spellings. + assert_eq!(run_fixture("float_literal_f_suffix.c"), 0); +} + +#[test] +fn float_literal_arith_single_precision() { + // C99 6.3.1.8: `float` combined with an `f`-suffixed constant + // computes in single precision with no widen / narrow hop. + assert_eq!(run_fixture("float_literal_arith_single_precision.c"), 0); +} + #[test] fn array_range_designator() { // GCC `[a ... b] = value` fills the inclusive range; covers constant @@ -702,6 +741,14 @@ fn inline_two_word_struct_return() { assert_eq!(run_fixture("inline_two_word_struct_return.c"), 0); } +#[test] +fn store_forward_local_slot() { + // A frame-slot store immediately reloaded in one block forwards to + // the stored value; volatile, address-taken, and cross-block pairs + // reload from memory. + assert_eq!(run_fixture("store_forward_local_slot.c"), 0); +} + #[test] fn struct_return_reg_computed_goto() { // A one-word-struct return that carries a label address is promoted out @@ -750,6 +797,19 @@ fn inline_phi_narrow_param_return() { assert_eq!(run_fixture("inline_phi_narrow_param_return.c"), 0); } +#[test] +fn reg_alloc_callee_bank_call_block_before_loop() { + // A recursive function whose call block is laid out at a lower pc + // than its hot loop: only the values whose CFG live range spans + // the calls need callee-saved homes. A pc-interval class test also + // flagged the loop-local values, overfilled the callee bank, and + // spilled the loop induction variable. + assert_eq!( + run_fixture("reg_alloc_callee_bank_call_block_before_loop.c"), + 0 + ); +} + #[test] fn const_member_address_init() { // C99 6.6: a static initializer may be the constant address of a @@ -1000,6 +1060,9 @@ fn switch_statement() { // a == 2 -> res = 20, falls through to case 3 -> res += 5 -> 25 assert_eq!(run_fixture("switch_statement.c"), 25); assert_eq!(run_fixture("switch_binary_search.c"), 0); + assert_eq!(run_fixture("switch_jump_table_dense.c"), 0); + assert_eq!(run_fixture("switch_jump_table_sparse_kept.c"), 0); + assert_eq!(run_fixture("switch_jump_table_phi_join.c"), 0); assert_eq!(run_fixture("branch_relaxation.c"), 21); assert_eq!(run_fixture("float_register_resident.c"), 45); assert_eq!(run_fixture("variadic_struct_arg.c"), 18); @@ -1098,6 +1161,36 @@ fn for_loop() { assert_eq!(run_fixture("for_loop.c"), 10); } +#[test] +fn layout_bottom_test_loop() { + assert_eq!(run_fixture("layout_bottom_test_loop.c"), 45); +} + +#[test] +fn layout_nested_loops() { + assert_eq!(run_fixture("layout_nested_loops.c"), 27); +} + +#[test] +fn layout_goto_block_addr() { + assert_eq!(run_fixture("layout_goto_block_addr.c"), 16); +} + +#[test] +fn unroll_const_trip_copy() { + assert_eq!(run_fixture("unroll_const_trip_copy.c"), 0); +} + +#[test] +fn unroll_trip_17_stays_rolled() { + assert_eq!(run_fixture("unroll_trip_17_stays_rolled.c"), 0); +} + +#[test] +fn unroll_volatile_stays_rolled() { + assert_eq!(run_fixture("unroll_volatile_stays_rolled.c"), 0); +} + #[test] fn recursion_factorial() { assert_eq!(run_fixture("recursion_factorial.c"), 120); @@ -1704,9 +1797,9 @@ fn adjacent_string_literals_concatenate() { #[test] fn float_long_double_suffix_accepted() { // C99 6.4.4.2: the floating-suffix is one of `f`, `F`, `l`, - // `L`. The dialect stores every floating literal in `f64`, - // so the four spellings of the same value land identical at - // the bit level. The fixture also pins the integer-vs-float + // `L`. 1.0 is exact in every precision, so the four spellings + // of the value land identical at the bit level after conversion + // to double. The fixture also pins the integer-vs-float // disambiguator -- bare `7L` stays a `long` integer because // no `.` / `e` was seen. assert_eq!(run_fixture("float_long_double_suffix.c"), 0); @@ -2041,6 +2134,84 @@ fn global_init_midexpr_cast_narrow() { assert_eq!(run_fixture("global_init_midexpr_cast_narrow.c"), 0); } +#[test] +fn init_brace_intermediate_cast() { + // C99 6.5.4 + 6.7.8p11: a brace-enclosed initializer element applies + // every cast in its chain -- `(long)(int)0x92492493` sign-extends + // through `int` -- in static and automatic storage, for array + // elements and struct members alike. + assert_eq!(run_fixture("init_brace_intermediate_cast.c"), 0); +} + +#[test] +fn dead_local_load_frame_elide() { + // C99 6.2.4p2: a local that is never observed needs no storage. A + // promotion-orphaned slot load with no consumers emits no code and + // must not force a frame; a volatile access (5.1.2.3p2) keeps it. + assert_eq!(run_fixture("dead_local_load_frame_elide.c"), 0); +} + +#[test] +fn narrow_param_entry_extend() { + // C99 6.5.2.2p4 / 6.3.1.3: a register-passed narrow parameter is + // converted on entry; an I8/I16 conversion rewrites bits 8..31, + // so it cannot be skipped on a bits-32..63-only liveness proof. + assert_eq!(run_fixture("narrow_param_entry_extend.c"), 0); +} + +#[test] +fn qsort_scan_extend_dedup() { + // One sign-extension result per (value, kind): re-extensions at + // dominated positions redirect to the dominating one. + assert_eq!(run_fixture("qsort_scan_extend_dedup.c"), 0); +} + +#[test] +fn call_arg_extend_drop() { + // The caller-side re-extension of a direct-call argument drops + // only when the callee re-derives the parameter from the low bits. + assert_eq!(run_fixture("call_arg_extend_drop.c"), 0); +} + +#[test] +fn indirect_call_narrow_scalar_args() { + // C99 6.5.2.2p7: a non-variadic indirect call converts each + // argument to the pointee prototype's parameter type; narrow + // (char/short) parameters read the same values as a direct call. + assert_eq!(run_fixture("indirect_call_narrow_scalar_args.c"), 0); +} + +#[test] +fn indirect_call_ten_scalar_args() { + // Ten integer arguments through a function pointer: args 9 and 10 + // ride the host stack overflow slots; positional weights catch a + // slot permutation or a missed overflow store. + assert_eq!(run_fixture("indirect_call_ten_scalar_args.c"), 0); +} + +#[test] +fn indirect_call_mixed_fp_int_args() { + // Interleaved int/FP scalars through a non-variadic function + // pointer: the banks advance independently per the arg-type mask. + assert_eq!(run_fixture("indirect_call_mixed_fp_int_args.c"), 0); +} + +#[test] +fn float_param_stack_overflow() { + // `float` parameters past the FP argument registers ride the host + // stack at single precision; the argument cell carries the f32 bit + // pattern on both the native and the interpreter paths. + assert_eq!(run_fixture("float_param_stack_overflow.c"), 0); +} + +#[test] +fn indirect_call_variadic_fp_control() { + // A variadic callee through a function pointer keeps the host + // variadic placement; mixed int/double varargs cover both banks + // and the stack tail. + assert_eq!(run_fixture("indirect_call_variadic_fp_control.c"), 0); +} + #[test] fn enum_tag_types() { // `enum Foo { ... };` registers a tag whose constants @@ -2331,3 +2502,25 @@ fn darwin_enotsup_is_distinct_from_eopnotsupp() { && ENOTSUP!=EOPNOTSUPP) ? 0 : 1; }"; assert_eq!(super::run_str(src), 0); } + +#[test] +fn ndebug_optimize_predefine() { + // The library harness never sets the driver's `-O`, so neither + // NDEBUG nor __OPTIMIZE__ is predefined here; the CLI-level + // `-O` semantics are locked by `tests/cli_fixture_smoke.rs`. + assert_eq!(run_fixture("ndebug_optimize_predefine.c"), 100); +} + +#[test] +fn constfold_post_inline_matches_interpreter() { + // The differential companion to the mid-end constant folder: the + // same fixture runs natively unoptimized and with -O via the + // fixture tables, so any fold that disagrees with the + // interpreter's evaluator surfaces as a lane divergence. + assert_eq!(run_fixture("constfold_post_inline.c"), 0); +} + +#[test] +fn rotate_inline_const_count_matches_interpreter() { + assert_eq!(run_fixture("rotate_inline_const_count.c"), 0); +} diff --git a/src/c5/vm/eval.rs b/src/c5/vm/eval.rs new file mode 100644 index 000000000..84402e298 --- /dev/null +++ b/src/c5/vm/eval.rs @@ -0,0 +1,260 @@ +//! Shared SSA constant evaluator: the arithmetic arms of the VM +//! interpreter, factored out so the interpreter and the compile-time +//! constant folder (`codegen::passes::constfold`) share one +//! implementation of the operator semantics. + +use super::super::ir::{BinOp, FpCastKind, LoadKind}; + +/// Integer division / modulo by zero, named for the trapping op. C99 6.5.5p5 leaves the behavior +/// undefined; the evaluator diagnoses it rather than invoking +/// host-level UB. The VM re-wraps `message()` into its runtime error; +/// the fold gate refuses the operands instead. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum EvalTrap { + Div, + Mod, + Divu, + Modu, +} + +impl EvalTrap { + pub(crate) fn message(self) -> &'static str { + match self { + EvalTrap::Div => "vm_ssa: signed integer division by zero", + EvalTrap::Mod => "vm_ssa: signed integer modulo by zero", + EvalTrap::Divu => "vm_ssa: unsigned integer division by zero", + EvalTrap::Modu => "vm_ssa: unsigned integer modulo by zero", + } + } +} + +/// Round a result to single precision when `f32_flag` marks the +/// defining value f32 (C99 6.3.1.8). The register convention keeps an +/// f32 value as the f64 bit pattern of its single-precision value, so +/// the round-trip through `f32` reproduces hardware single-precision +/// arithmetic. A non-f32 (double) value passes through unchanged. The +/// flag is `None` for SSA built outside the walker (no f32 tracking), +/// which also passes through as double. +pub(crate) fn round_if_f32(bits: i64, f32_flag: Option<&bool>) -> i64 { + if matches!(f32_flag, Some(true)) { + (f64::from_bits(bits as u64) as f32 as f64).to_bits() as i64 + } else { + bits + } +} + +/// Binop dispatch. Mirrors `fold_int_binop` in `ast::walk`; +/// the two share C99-driven semantics for arithmetic / bitwise / +/// shift / comparison ops. FP arms (Fadd, Feq, ...) treat each +/// operand as the bit pattern of an `f64` and return a fresh +/// bit pattern (arithmetic) or 0 / 1 (compares). Integer divide +/// by zero surfaces as [`EvalTrap`]. +pub(crate) fn apply_binop(op: BinOp, lhs: i64, rhs: i64) -> Result { + let r = match op { + BinOp::Add => lhs.wrapping_add(rhs), + BinOp::Sub => lhs.wrapping_sub(rhs), + BinOp::Mul => lhs.wrapping_mul(rhs), + BinOp::And => lhs & rhs, + BinOp::Or => lhs | rhs, + BinOp::Xor => lhs ^ rhs, + BinOp::Shl => ((lhs as u64) << (rhs as u32 & 63)) as i64, + BinOp::Shr => lhs >> (rhs as u32 & 63), + BinOp::Shru => ((lhs as u64) >> (rhs as u32 & 63)) as i64, + BinOp::Ror => (lhs as u64).rotate_right(rhs as u32 & 63) as i64, + BinOp::Eq => (lhs == rhs) as i64, + BinOp::Ne => (lhs != rhs) as i64, + BinOp::Lt => (lhs < rhs) as i64, + BinOp::Gt => (lhs > rhs) as i64, + BinOp::Le => (lhs <= rhs) as i64, + BinOp::Ge => (lhs >= rhs) as i64, + BinOp::Ult => ((lhs as u64) < (rhs as u64)) as i64, + BinOp::Ugt => ((lhs as u64) > (rhs as u64)) as i64, + BinOp::Ule => ((lhs as u64) <= (rhs as u64)) as i64, + BinOp::Uge => ((lhs as u64) >= (rhs as u64)) as i64, + BinOp::Div => { + if rhs == 0 { + return Err(EvalTrap::Div); + } + lhs.wrapping_div(rhs) + } + BinOp::Mod => { + if rhs == 0 { + return Err(EvalTrap::Mod); + } + lhs.wrapping_rem(rhs) + } + BinOp::Divu => { + let r = rhs as u64; + if r == 0 { + return Err(EvalTrap::Divu); + } + ((lhs as u64) / r) as i64 + } + BinOp::Modu => { + let r = rhs as u64; + if r == 0 { + return Err(EvalTrap::Modu); + } + ((lhs as u64) % r) as i64 + } + BinOp::Fadd => (f64::from_bits(lhs as u64) + f64::from_bits(rhs as u64)).to_bits() as i64, + BinOp::Fsub => (f64::from_bits(lhs as u64) - f64::from_bits(rhs as u64)).to_bits() as i64, + BinOp::Fmul => (f64::from_bits(lhs as u64) * f64::from_bits(rhs as u64)).to_bits() as i64, + BinOp::Fdiv => (f64::from_bits(lhs as u64) / f64::from_bits(rhs as u64)).to_bits() as i64, + BinOp::Feq => (f64::from_bits(lhs as u64) == f64::from_bits(rhs as u64)) as i64, + BinOp::Fne => (f64::from_bits(lhs as u64) != f64::from_bits(rhs as u64)) as i64, + BinOp::Flt => (f64::from_bits(lhs as u64) < f64::from_bits(rhs as u64)) as i64, + BinOp::Fgt => (f64::from_bits(lhs as u64) > f64::from_bits(rhs as u64)) as i64, + BinOp::Fle => (f64::from_bits(lhs as u64) <= f64::from_bits(rhs as u64)) as i64, + BinOp::Fge => (f64::from_bits(lhs as u64) >= f64::from_bits(rhs as u64)) as i64, + }; + Ok(r) +} + +/// Compile-time fold gate over [`apply_binop`]. Refuses: +/// * FP ops -- the folder handles integer values only (the IR keeps +/// an f32 `Imm` as the low-32 bit pattern while the VM register +/// convention widens to f64, so the bit-level semantics differ); +/// * division / modulo by zero; +/// * `i64::MIN / -1` and `i64::MIN % -1` -- `wrapping_div` folds a +/// value the native `idiv` traps on (#DE), so folding would change +/// the program's runtime behavior. +pub(crate) fn fold_binop(op: BinOp, lhs: i64, rhs: i64) -> Option { + if matches!( + op, + BinOp::Fadd + | BinOp::Fsub + | BinOp::Fmul + | BinOp::Fdiv + | BinOp::Feq + | BinOp::Fne + | BinOp::Flt + | BinOp::Fgt + | BinOp::Fle + | BinOp::Fge + ) { + return None; + } + if matches!(op, BinOp::Div | BinOp::Mod) && lhs == i64::MIN && rhs == -1 { + return None; + } + apply_binop(op, lhs, rhs).ok() +} + +/// `Inst::Extend`: discard the bits above `kind`'s width and +/// replicate the sign bit (C99 6.3.1.3). Kinds outside the signed +/// narrow set pass through unchanged. +pub(crate) fn eval_extend(raw: i64, kind: LoadKind) -> i64 { + match kind { + LoadKind::I8 => raw as i8 as i64, + LoadKind::I16 => raw as i16 as i64, + LoadKind::I32 => raw as i32 as i64, + _ => raw, + } +} + +/// `Inst::FpCast`. A register carrying a single-precision value +/// already holds the f64 bit pattern of that f32 (the F32 load widens +/// on read). Widening to double is therefore a no-op; narrowing +/// rounds the f64 to f32 then re-stores the f32-as-f64 bit pattern +/// (C99 6.3.1.5). +pub(crate) fn eval_fpcast(kind: FpCastKind, raw: i64) -> i64 { + match kind { + FpCastKind::FpToInt => f64::from_bits(raw as u64) as i64, + FpCastKind::UFpToInt => f64::from_bits(raw as u64) as u64 as i64, + FpCastKind::IntToFp => (raw as f64).to_bits() as i64, + FpCastKind::UIntToFp => (raw as u64 as f64).to_bits() as i64, + FpCastKind::F32ToF64 => raw, + FpCastKind::F64ToF32 => (f64::from_bits(raw as u64) as f32 as f64).to_bits() as i64, + } +} + +/// `Inst::Fneg` on an f64 bit pattern. +pub(crate) fn eval_fneg(raw: i64) -> i64 { + (-f64::from_bits(raw as u64)).to_bits() as i64 +} + +/// `Inst::Fma`: single-rounding fused multiply-add (C99 6.5p8). Match +/// the host fmadd / vfmadd: round once, at the result's width. +/// `libm::fma` / `fmaf` give the same single rounding as the native +/// instruction (and, unlike `f64::mul_add`, are available in the +/// no_std build) so the VM reference agrees with native codegen on +/// every target. +pub(crate) fn eval_fma( + a_bits: i64, + b_bits: i64, + c_bits: i64, + neg_product: bool, + neg_addend: bool, + is_f32: bool, +) -> i64 { + let mut av = f64::from_bits(a_bits as u64); + let bv = f64::from_bits(b_bits as u64); + let mut cv = f64::from_bits(c_bits as u64); + if neg_product { + av = -av; + } + if neg_addend { + cv = -cv; + } + let res = if is_f32 { + libm::fmaf(av as f32, bv as f32, cv as f32) as f64 + } else { + libm::fma(av, bv, cv) + }; + res.to_bits() as i64 +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn fold_refuses_div_mod_by_zero() { + for op in [BinOp::Div, BinOp::Mod, BinOp::Divu, BinOp::Modu] { + assert_eq!(fold_binop(op, 7, 0), None); + } + } + + #[test] + fn fold_refuses_min_over_minus_one() { + // Native `idiv` raises #DE on this operand pair; `wrapping_div` + // would fold it to i64::MIN and hide the trap. + assert_eq!(fold_binop(BinOp::Div, i64::MIN, -1), None); + assert_eq!(fold_binop(BinOp::Mod, i64::MIN, -1), None); + // The unsigned forms treat i64::MIN / -1 as ordinary operands. + assert_eq!(fold_binop(BinOp::Divu, i64::MIN, -1), Some(0)); + assert_eq!(fold_binop(BinOp::Modu, i64::MIN, -1), Some(i64::MIN)); + } + + #[test] + fn fold_refuses_fp_ops() { + assert_eq!(fold_binop(BinOp::Fadd, 1, 2), None); + assert_eq!(fold_binop(BinOp::Feq, 1, 1), None); + } + + #[test] + fn fold_matches_interpreter_semantics() { + assert_eq!(fold_binop(BinOp::Add, i64::MAX, 1), Some(i64::MIN)); + assert_eq!(fold_binop(BinOp::Shl, 1, 65), Some(2)); + assert_eq!(fold_binop(BinOp::Shr, -8, 1), Some(-4)); + assert_eq!( + fold_binop(BinOp::Shru, -8, 1), + Some(((-8i64) as u64 >> 1) as i64) + ); + assert_eq!(fold_binop(BinOp::Div, -7, 2), Some(-3)); + assert_eq!(fold_binop(BinOp::Mod, -7, 2), Some(-1)); + assert_eq!(fold_binop(BinOp::Ror, 1, 1), Some(i64::MIN)); + assert_eq!(fold_binop(BinOp::Ult, -1, 1), Some(0)); + assert_eq!(fold_binop(BinOp::Lt, -1, 1), Some(1)); + } + + #[test] + fn extend_sign_replicates_per_kind() { + assert_eq!(eval_extend(0xff, LoadKind::I8), -1); + assert_eq!(eval_extend(0x8000, LoadKind::I16), -32768); + assert_eq!(eval_extend(0xffff_ffff, LoadKind::I32), -1); + assert_eq!(eval_extend(0x7f, LoadKind::I8), 0x7f); + assert_eq!(eval_extend(-1, LoadKind::I64), -1); + } +} diff --git a/src/c5/vm/mod.rs b/src/c5/vm/mod.rs index f5e667b19..af508d895 100644 --- a/src/c5/vm/mod.rs +++ b/src/c5/vm/mod.rs @@ -7,6 +7,7 @@ use super::host::Host; use super::ir::FunctionSsa; use super::program::Program; +pub(crate) mod eval; mod ssa; /// Whether the VM should emit a per-instruction trace to the host's diff --git a/src/c5/vm/ssa.rs b/src/c5/vm/ssa.rs index ae21313be..c0cbe4542 100644 --- a/src/c5/vm/ssa.rs +++ b/src/c5/vm/ssa.rs @@ -15,8 +15,9 @@ use alloc::vec::Vec; use super::super::error::C5Error; use super::super::host::Host; use super::super::ir::{ - AtomicRmwOp, BinOp, FpCastKind, FunctionSsa, Inst, LoadKind, StoreKind, Terminator, ValueId, + AtomicRmwOp, BinOp, FunctionSsa, Inst, LoadKind, StoreKind, Terminator, ValueId, }; +use super::eval::{self, round_if_f32}; /// `Inst::ImmCode` results are tagged with this bit set so /// `Inst::CallIndirect` can distinguish a function pointer from @@ -703,6 +704,22 @@ fn run_func( let tok = frame.regs[target as usize]; frame.block_idx = (tok & !CODE_ADDR_TAG) as usize; } + Terminator::JumpTable { idx, table } => { + // The lowering's bounds check proves the index in + // range; an out-of-range value here is a lowering bug. + let i = frame.regs[idx as usize] as u64 as usize; + let Some(&t) = frame + .func + .jump_tables + .get(table as usize) + .and_then(|tbl| tbl.get(i)) + else { + break Err(C5Error::Runtime(alloc::format!( + "vm_ssa: JumpTable index {i} out of range" + ))); + }; + frame.block_idx = t as usize; + } Terminator::TailExt(_) => { break Err(C5Error::Runtime( "vm_ssa: Terminator::TailExt not implemented".to_string(), @@ -745,6 +762,13 @@ fn finish_agg_return( /// advances by the aggregate's span, reads them contiguously. A fixed /// struct parameter stays its source address; `run_func`'s /// `param_aggs` scatter copies it into the body local. +/// +/// A `float`-typed argument's cell carries the f32 bit pattern: the +/// callee reads it back with `ParamRef { F32 }` / `LoadLocal { F32 }` +/// (native callers store the s-register view the same way). The +/// interpreter's register convention holds every f32 value as the f64 +/// pattern of its single-precision value, so narrow at the cell +/// boundary. fn collect_call_args( frame: &Frame<'_>, mem: &Memory, @@ -766,6 +790,10 @@ fn collect_call_args( } continue; } + if matches!(frame.func.f32_values.get(a as usize), Some(true)) { + out.push((f64::from_bits(val as u64) as f32).to_bits() as i64); + continue; + } out.push(val); } Ok(out) @@ -781,7 +809,16 @@ fn run_inst( let inst = &frame.func.insts[v as usize]; let name = match inst { Inst::Imm(k) => { - frame.regs[v as usize] = *k; + // An f32-marked imm carries the f32 bit pattern (the shape + // the native emit materialises); the interpreter's register + // convention keeps every f32 value as the f64 pattern of + // its single-precision value, so widen at the definition. + frame.regs[v as usize] = if matches!(frame.func.f32_values.get(v as usize), Some(true)) + { + (f32::from_bits(*k as u32) as f64).to_bits() as i64 + } else { + *k + }; return Ok(()); } Inst::ImmData(off) => { @@ -985,7 +1022,7 @@ fn run_inst( } Inst::Fneg(src) => { let raw = frame.regs[*src as usize]; - let neg = (-f64::from_bits(raw as u64)).to_bits() as i64; + let neg = eval::eval_fneg(raw); frame.regs[v as usize] = round_if_f32(neg, frame.func.f32_values.get(v as usize)); return Ok(()); } @@ -996,56 +1033,26 @@ fn run_inst( neg_product, neg_addend, } => { - // Single-rounding fused multiply-add (C99 6.5p8). Match the - // host fmadd / vfmadd: round once, at the result's width. - // `libm::fma` / `fmaf` give the same single rounding as the - // native instruction (and, unlike `f64::mul_add`, are - // available in the no_std build) so the VM reference agrees - // with native codegen on every target. let is_f32 = matches!(frame.func.f32_values.get(v as usize), Some(true)); - let mut av = f64::from_bits(frame.regs[*a as usize] as u64); - let bv = f64::from_bits(frame.regs[*b as usize] as u64); - let mut cv = f64::from_bits(frame.regs[*c as usize] as u64); - if *neg_product { - av = -av; - } - if *neg_addend { - cv = -cv; - } - let res = if is_f32 { - libm::fmaf(av as f32, bv as f32, cv as f32) as f64 - } else { - libm::fma(av, bv, cv) - }; - frame.regs[v as usize] = - round_if_f32(res.to_bits() as i64, frame.func.f32_values.get(v as usize)); + let res = eval::eval_fma( + frame.regs[*a as usize], + frame.regs[*b as usize], + frame.regs[*c as usize], + *neg_product, + *neg_addend, + is_f32, + ); + frame.regs[v as usize] = round_if_f32(res, frame.func.f32_values.get(v as usize)); return Ok(()); } Inst::Extend { value, kind } => { let raw = frame.regs[*value as usize]; - frame.regs[v as usize] = match kind { - LoadKind::I8 => raw as i8 as i64, - LoadKind::I16 => raw as i16 as i64, - LoadKind::I32 => raw as i32 as i64, - _ => raw, - }; + frame.regs[v as usize] = eval::eval_extend(raw, *kind); return Ok(()); } Inst::FpCast { kind, value } => { let raw = frame.regs[*value as usize]; - frame.regs[v as usize] = match kind { - FpCastKind::FpToInt => f64::from_bits(raw as u64) as i64, - FpCastKind::UFpToInt => f64::from_bits(raw as u64) as u64 as i64, - FpCastKind::IntToFp => (raw as f64).to_bits() as i64, - FpCastKind::UIntToFp => (raw as u64 as f64).to_bits() as i64, - // A register carrying a single-precision value already - // holds the f64 bit pattern of that f32 (the F32 load - // widens on read). Widening to double is therefore a - // no-op; narrowing rounds the f64 to f32 then re-stores - // the f32-as-f64 bit pattern (C99 6.3.1.5). - FpCastKind::F32ToF64 => raw, - FpCastKind::F64ToF32 => (f64::from_bits(raw as u64) as f32 as f64).to_bits() as i64, - }; + frame.regs[v as usize] = eval::eval_fpcast(*kind, raw); return Ok(()); } Inst::Call { @@ -1138,17 +1145,35 @@ fn run_inst( // arena get the "not implemented" path below. return Ok(()); } - Inst::ParamRef { idx, .. } => { + Inst::ParamRef { idx, kind } => { // The i-th declared parameter sits at c5 cdecl slot // i+2 (run_func wrote each `args[i]` to // `stack_base + (locals + i) * 8`). Read the 8-byte // value back so the SSA-VM sees the same i64 the - // call site passed. + // call site passed. A `float` parameter's cell holds + // the f32 bit pattern (see `collect_call_args`); the + // F32 read widens it back to the f64-pattern register + // convention. let off = (*idx as i64) + 2; let addr = frame.slot_addr(off).ok_or_else(|| { C5Error::Runtime(format!("vm_ssa: ParamRef({idx}): slot {off} out of range")) })?; - frame.regs[v as usize] = load_from_memory(mem, addr, LoadKind::I64)?; + let read_kind = if matches!(kind, LoadKind::F32) { + LoadKind::F32 + } else { + LoadKind::I64 + }; + let raw = load_from_memory(mem, addr, read_kind)?; + // Mirror the native entry lowering: a narrow signed kind + // sign-extends from its width (C99 6.5.2.2p4 / 6.3.1.3), so + // a caller that passed the value unextended still yields + // the canonical parameter value. + frame.regs[v as usize] = match kind { + LoadKind::I8 => raw as i8 as i64, + LoadKind::I16 => raw as i16 as i64, + LoadKind::I32 => raw as i32 as i64, + _ => raw, + }; return Ok(()); } Inst::Phi { .. } => "Phi", @@ -2240,97 +2265,11 @@ fn narrow_store(value: i64, kind: StoreKind) -> i64 { } } -/// Round a result to single precision when `f32_flag` marks the -/// defining value f32 (C99 6.3.1.8). The register convention keeps an -/// f32 value as the f64 bit pattern of its single-precision value, so -/// the round-trip through `f32` reproduces hardware single-precision -/// arithmetic. A non-f32 (double) value passes through unchanged. The -/// flag is `None` for SSA built outside the walker (no f32 tracking), -/// which also passes through as double. -fn round_if_f32(bits: i64, f32_flag: Option<&bool>) -> i64 { - if matches!(f32_flag, Some(true)) { - (f64::from_bits(bits as u64) as f32 as f64).to_bits() as i64 - } else { - bits - } -} - -/// Binop dispatch. Mirrors `fold_int_binop` in `ast::walk`; -/// the two share C99-driven semantics for arithmetic / bitwise / -/// shift / comparison ops. FP arms (Fadd, Feq, ...) treat each -/// operand as the bit pattern of an `f64` and return a fresh -/// bit pattern (arithmetic) or 0 / 1 (compares). Integer divide -/// by zero surfaces as a runtime error -- C99 6.5.5p5 leaves -/// division-by-zero undefined and we'd rather diagnose it than -/// invoke host-level UB. +/// Binop dispatch, shared with the compile-time constant folder +/// (`super::eval`); a division trap re-wraps as the VM's runtime +/// error. fn apply_binop(op: BinOp, lhs: i64, rhs: i64) -> Result { - let r = match op { - BinOp::Add => lhs.wrapping_add(rhs), - BinOp::Sub => lhs.wrapping_sub(rhs), - BinOp::Mul => lhs.wrapping_mul(rhs), - BinOp::And => lhs & rhs, - BinOp::Or => lhs | rhs, - BinOp::Xor => lhs ^ rhs, - BinOp::Shl => ((lhs as u64) << (rhs as u32 & 63)) as i64, - BinOp::Shr => lhs >> (rhs as u32 & 63), - BinOp::Shru => ((lhs as u64) >> (rhs as u32 & 63)) as i64, - BinOp::Ror => (lhs as u64).rotate_right(rhs as u32 & 63) as i64, - BinOp::Eq => (lhs == rhs) as i64, - BinOp::Ne => (lhs != rhs) as i64, - BinOp::Lt => (lhs < rhs) as i64, - BinOp::Gt => (lhs > rhs) as i64, - BinOp::Le => (lhs <= rhs) as i64, - BinOp::Ge => (lhs >= rhs) as i64, - BinOp::Ult => ((lhs as u64) < (rhs as u64)) as i64, - BinOp::Ugt => ((lhs as u64) > (rhs as u64)) as i64, - BinOp::Ule => ((lhs as u64) <= (rhs as u64)) as i64, - BinOp::Uge => ((lhs as u64) >= (rhs as u64)) as i64, - BinOp::Div => { - if rhs == 0 { - return Err(C5Error::Runtime( - "vm_ssa: signed integer division by zero".to_string(), - )); - } - lhs.wrapping_div(rhs) - } - BinOp::Mod => { - if rhs == 0 { - return Err(C5Error::Runtime( - "vm_ssa: signed integer modulo by zero".to_string(), - )); - } - lhs.wrapping_rem(rhs) - } - BinOp::Divu => { - let r = rhs as u64; - if r == 0 { - return Err(C5Error::Runtime( - "vm_ssa: unsigned integer division by zero".to_string(), - )); - } - ((lhs as u64) / r) as i64 - } - BinOp::Modu => { - let r = rhs as u64; - if r == 0 { - return Err(C5Error::Runtime( - "vm_ssa: unsigned integer modulo by zero".to_string(), - )); - } - ((lhs as u64) % r) as i64 - } - BinOp::Fadd => (f64::from_bits(lhs as u64) + f64::from_bits(rhs as u64)).to_bits() as i64, - BinOp::Fsub => (f64::from_bits(lhs as u64) - f64::from_bits(rhs as u64)).to_bits() as i64, - BinOp::Fmul => (f64::from_bits(lhs as u64) * f64::from_bits(rhs as u64)).to_bits() as i64, - BinOp::Fdiv => (f64::from_bits(lhs as u64) / f64::from_bits(rhs as u64)).to_bits() as i64, - BinOp::Feq => (f64::from_bits(lhs as u64) == f64::from_bits(rhs as u64)) as i64, - BinOp::Fne => (f64::from_bits(lhs as u64) != f64::from_bits(rhs as u64)) as i64, - BinOp::Flt => (f64::from_bits(lhs as u64) < f64::from_bits(rhs as u64)) as i64, - BinOp::Fgt => (f64::from_bits(lhs as u64) > f64::from_bits(rhs as u64)) as i64, - BinOp::Fle => (f64::from_bits(lhs as u64) <= f64::from_bits(rhs as u64)) as i64, - BinOp::Fge => (f64::from_bits(lhs as u64) >= f64::from_bits(rhs as u64)) as i64, - }; - Ok(r) + eval::apply_binop(op, lhs, rhs).map_err(|t| C5Error::Runtime(t.message().to_string())) } #[cfg(test)] diff --git a/src/main.rs b/src/main.rs index 1dced89cd..3cc507f8a 100644 --- a/src/main.rs +++ b/src/main.rs @@ -57,7 +57,9 @@ Multi-TU knobs: Compile knobs: -O, --optimize Run the SSA optimization passes (mem2reg, inlining, rotate and branch const-fold, - immediate dedup). Off by default. The + immediate dedup) and predefine `NDEBUG=1` + and `__OPTIMIZE__=1` (override with `-D` / + `-U`). Off by default. The `-O1`/`-O2`/`-O3`/`-Os`/`-Oz`/`-Ofast`/`-Og` forms all select this single level; `-O0` disables it. @@ -745,6 +747,7 @@ fn run() { }; let copts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(defines.clone()) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -829,6 +832,7 @@ fn run() { }; let opts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(defines.clone()) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -922,6 +926,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_export_all_functions(export_all) .with_implicit_extern_fns(implicit_externs.to_vec()) .with_no_entry_point(true); @@ -967,6 +972,7 @@ fn run() { } let copts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(copts_defines) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -1458,6 +1464,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_no_entry_point(true); let mut compiler = Compiler::with_options(src_bytes, target, copts); if show_includes { @@ -1563,6 +1570,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_no_entry_point(true); let mut compiler = Compiler::with_options(src_bytes, target, copts); if show_includes { diff --git a/tests/cli_fixture_smoke.rs b/tests/cli_fixture_smoke.rs index 345404de6..b25bac009 100644 --- a/tests/cli_fixture_smoke.rs +++ b/tests/cli_fixture_smoke.rs @@ -219,6 +219,64 @@ fn opt_level_flags_map_to_the_single_level() { assert_eq!(os, o, "-Os should match -O"); } +// `-O` predefines `NDEBUG=1` and `__OPTIMIZE__=1` (release semantics). +// The predefines land before the CLI `-D` / `-U` lists, so an explicit +// `-D NDEBUG=` keeps the user's value and `-U NDEBUG` removes the +// implied one, re-enabling `assert`. +#[cfg(any(target_os = "linux", target_os = "macos"))] +#[test] +fn optimize_flag_predefines_ndebug() { + let badc = env!("CARGO_BIN_EXE_badc"); + let manifest = env!("CARGO_MANIFEST_DIR"); + let fixtures = PathBuf::from(manifest) + .join("tests") + .join("fixtures") + .join("c"); + let dir = std::env::temp_dir().join(format!("badc-ndebug-{}", std::process::id())); + let _ = std::fs::remove_dir_all(&dir); + std::fs::create_dir_all(&dir).expect("create temp dir"); + + let run = |tag: &str, flags: &[&str], src: &std::path::Path| -> std::process::ExitStatus { + let exe = dir.join(tag); + let mut cmd = Command::new(badc); + for f in flags { + cmd.arg(f); + } + let out = cmd.arg(src).arg("-o").arg(&exe).output().expect("run badc"); + assert!( + out.status.success(), + "compile {tag} failed: {}", + String::from_utf8_lossy(&out.stderr) + ); + Command::new(&exe).output().expect("run prog").status + }; + + // Exit codes: both predefines -> NDEBUG's value, exactly one -> 101, + // neither -> 100 (see the fixture). + let probe = fixtures.join("ndebug_optimize_predefine.c"); + assert_eq!(run("plain", &[], &probe).code(), Some(100)); + assert_eq!(run("opt", &["-O"], &probe).code(), Some(1)); + assert_eq!( + run("opt-dval", &["-O", "-DNDEBUG=7"], &probe).code(), + Some(7) + ); + assert_eq!( + run("opt-undef", &["-O", "-UNDEBUG"], &probe).code(), + Some(101) + ); + + // Under `-O` the assert(0) is compiled out; `-U NDEBUG` re-enables + // it and the program traps instead of exiting 0. + let trap = fixtures.join("ndebug_undef_reenables_assert.c"); + assert_eq!(run("assert-off", &["-O"], &trap).code(), Some(0)); + let fired = run("assert-on", &["-O", "-UNDEBUG"], &trap); + assert!( + !fired.success(), + "-U NDEBUG under -O must re-enable assert (got {fired:?})" + ); + let _ = std::fs::remove_dir_all(&dir); +} + // `--install ` writes every embedded header under /include // (recreating subdirectories) and the runtime source under /lib. #[test] diff --git a/tests/fixtures/c/call_arg_extend_drop.c b/tests/fixtures/c/call_arg_extend_drop.c new file mode 100644 index 000000000..721a89b67 --- /dev/null +++ b/tests/fixtures/c/call_arg_extend_drop.c @@ -0,0 +1,32 @@ +// A direct internal call whose callee re-extends the parameter on +// entry (its every read is a narrow-kind ParamRef) does not need the +// caller-side re-extension of a computed argument; the callee derives +// the C99 6.5.2.2p4-converted value from the low bits itself. The +// checks pass values whose pre-truncation high bits are nonzero so a +// dropped extension that the callee failed to re-derive is caught. + +static int addv(int a, int b) { return a + b; } + +static int fib(int n) { + if (n < 2) return n; + return fib(n - 1) + fib(n - 2); +} + +// The parameter's cell address escapes: the prologue spills the raw +// incoming register, so the caller-side extension must survive here. +static long cell_escapes(int a) { + int *p = &a; + return (long)*p * 3; +} + +static int narrow(signed char c, short s) { return c * 100 + s; } + +int main(void) { + long big = 0x7fffffff00000005L; + int x = (int)big; + if (addv(x - 1, x + 1) != 10) return 1; + if (fib(x + 15) != 6765) return 2; + if (cell_escapes(x - 12) != -21) return 3; + if (narrow((signed char)(x + 0xEB), (short)(x - 0xFF0)) != -5675) return 4; + return 0; +} diff --git a/tests/fixtures/c/callee_save_pair_fold.c b/tests/fixtures/c/callee_save_pair_fold.c new file mode 100644 index 000000000..512da3c36 --- /dev/null +++ b/tests/fixtures/c/callee_save_pair_fold.c @@ -0,0 +1,21 @@ +// Five values live across a call occupy five callee-saved GPRs, so +// the aarch64 prologue saves them as two stp pairs plus a single str +// tail. The frame fits the pair imm7 reach, so the whole allocation +// (frame plus the fp/lr slot pair) folds into the first pair's +// pre-index, fp/lr store through the signed-offset pair form at +// [sp, #frame], and fp comes from `add x29, sp, #frame`; the epilogue +// restores fp/lr first and tears the frame down with the final +// restore's post-index. x86_64 keeps its mov-to-slot saves. Locked by +// the asm snapshot; the exit code checks the restores read back intact. + +int sink(int x) { + if (x <= 0) return 1; + return x + sink(x - 1); +} + +int quad(int a, int b, int c, int d, int e) { + int t = sink(a); + return t + a + b + c + d + e; +} + +int main(void) { return quad(1, 2, 3, 4, 5); } // 17 diff --git a/tests/fixtures/c/callee_save_pair_large_frame.c b/tests/fixtures/c/callee_save_pair_large_frame.c new file mode 100644 index 000000000..3ff703755 --- /dev/null +++ b/tests/fixtures/c/callee_save_pair_large_frame.c @@ -0,0 +1,22 @@ +// The 800-byte local array pushes the frame past the folded shape's +// pair imm7 reach, so the aarch64 prologue keeps the frame-record +// stp / mov fp / `sub sp` shape and stores the two call-crossing +// values as one stp pair at its signed offset; the epilogue keeps the +// paired ldp, `add sp`, and post-indexed fp/lr ldp. Locked by the asm +// snapshot; the exit code checks the array and the restored registers +// survive the call. + +int sink(int x) { + if (x <= 0) return 1; + return x + sink(x - 1); +} + +int bigframe(int a, int b) { + int buf[200]; + buf[0] = a; + buf[199] = b; + int t = sink(buf[0]); + return t + buf[199] + a + b; +} + +int main(void) { return bigframe(3, 4); } // sink(3)=7; 7+4+3+4 = 18 diff --git a/tests/fixtures/c/compound_assign_float_register_resident.c b/tests/fixtures/c/compound_assign_float_register_resident.c new file mode 100644 index 000000000..de83d02f8 --- /dev/null +++ b/tests/fixtures/c/compound_assign_float_register_resident.c @@ -0,0 +1,31 @@ +// A float lvalue updated through compound assignment (C99 6.5.16.2) +// or `++` / `--` (6.5.2.4, 6.5.3.1) keeps its frame slot eligible for +// register promotion, the same as `x = x op k`: no address is taken, +// and the loop-carried value merges through an F32 phi. Asserted by +// return code. + +int main(void) { + float acc = 100.0f; + float step = 1.0f; + for (int i = 0; i < 8; i++) { + acc -= 2.0f; + acc += step; + step++; + } + // acc = 100 - 8*2 + (1+2+...+8); every value is exact in f32. + if (acc != 120.0f) return 1; + if (step != 9.0f) return 2; + + float post = 0.5f; + post--; + if (post != -0.5f) return 3; + + // Double rhs: the operation runs in double and the result narrows + // back to single precision before the store (C99 6.3.1.5). + float m = 3.0f; + m *= 4.0; + m /= 2.0f; + if (m != 6.0f) return 4; + + return 0; +} diff --git a/tests/fixtures/c/computed_goto_static_table.c b/tests/fixtures/c/computed_goto_static_table.c new file mode 100644 index 000000000..a1a862103 --- /dev/null +++ b/tests/fixtures/c/computed_goto_static_table.c @@ -0,0 +1,34 @@ +// A static `&&label` dispatch table driven across repeated calls: after +// the first call initializes the table, later calls take the once-guard +// skip path and must still dispatch through correct label addresses. +// The interpreter sums operands until halt; a second program re-enters +// the same function. + +static int interp(const unsigned char *code) { + static void *tbl[] = { &&op_add, &&op_sub, &&op_dup, &&op_halt }; + int acc = 0; + int pc = 0; + goto *tbl[code[pc++]]; +op_add: + acc += code[pc++]; + goto *tbl[code[pc++]]; +op_sub: + acc -= code[pc++]; + goto *tbl[code[pc++]]; +op_dup: + acc += acc; + goto *tbl[code[pc++]]; +op_halt: + return acc; +} + +int main(void) { + // ADD 5, DUP, SUB 3, HALT => (5*2)-3 = 7 + static const unsigned char p1[] = { 0, 5, 2, 1, 3, 3 }; + // ADD 9, SUB 4, DUP, HALT => (9-4)*2 = 10 + static const unsigned char p2[] = { 0, 9, 1, 4, 2, 3 }; + if (interp(p1) != 7) return 1; + if (interp(p2) != 10) return 2; + if (interp(p1) != 7) return 3; + return 0; +} diff --git a/tests/fixtures/c/constfold_post_inline.c b/tests/fixtures/c/constfold_post_inline.c new file mode 100644 index 000000000..63706d3a0 --- /dev/null +++ b/tests/fixtures/c/constfold_post_inline.c @@ -0,0 +1,96 @@ +// Post-inline constant folding: constant arguments substituted into +// static helpers leave Extend(Imm) / Binop(Imm, Imm) chains that the +// mid-end folder must evaluate exactly as the interpreter and the +// unoptimized build do. Every folded arm is exercised: wrapping +// unsigned add/mul (C99 6.2.5p9), signed/unsigned shifts including +// counts 64 and 65 (6.5.7p3 leaves those undefined; the +// implementation pins the masked native semantics), the full +// comparison set, unsigned division/modulo extremes, C99 6.5.5p6 +// truncated signed division, callee-narrows extends (6.3.1.3), and +// the rotate idiom. Exit 0 when every computed value matches its +// literal. + +typedef unsigned long long u64; +typedef long long i64; + +static u64 add_u(u64 a, u64 b) { return a + b; } +static u64 mul_u(u64 a, u64 b) { return a * b; } +static i64 sub_i(i64 a, i64 b) { return a - b; } +static u64 shl_u(u64 x, int c) { return x << c; } +static u64 shr_u(u64 x, int c) { return x >> c; } +static i64 shr_i(i64 x, int c) { return x >> c; } +static u64 div_u(u64 a, u64 b) { return a / b; } +static u64 mod_u(u64 a, u64 b) { return a % b; } +static i64 div_i(i64 a, i64 b) { return a / b; } +static i64 mod_i(i64 a, i64 b) { return a % b; } +static u64 ror_u(u64 x, int c) { return (x >> c) | (x << (64 - c)); } +static int lt_i(i64 a, i64 b) { return a < b; } +static int gt_i(i64 a, i64 b) { return a > b; } +static int le_i(i64 a, i64 b) { return a <= b; } +static int ge_i(i64 a, i64 b) { return a >= b; } +static int lt_u(u64 a, u64 b) { return a < b; } +static int gt_u(u64 a, u64 b) { return a > b; } +static int le_u(u64 a, u64 b) { return a <= b; } +static int ge_u(u64 a, u64 b) { return a >= b; } +static int eq_i(i64 a, i64 b) { return a == b; } +static int ne_i(i64 a, i64 b) { return a != b; } +static i64 sext8(signed char v) { return v; } +static i64 sext16(short v) { return v; } +static i64 sext32(int v) { return v; } + +int main(void) { + // Constant-on-constant folds (both operands substituted). + if (add_u(0xffffffffffffffffULL, 2) != 1) return 1; + if (mul_u(0xffffffffffffffffULL, 3) != 0xfffffffffffffffdULL) return 2; + if (sub_i(-5, 9223372036854775807LL) != 9223372036854775804LL) return 3; + if (shl_u(0x0123456789abcdefULL, 4) != 0x123456789abcdef0ULL) return 4; + if (shl_u(0x0123456789abcdefULL, 64) != 0x0123456789abcdefULL) return 5; + if (shl_u(0x0123456789abcdefULL, 65) != 0x02468acf13579bdeULL) return 6; + if (shr_u(0x0123456789abcdefULL, 3) != 0x002468acf13579bdULL) return 7; + if (shr_u(0x8000000000000000ULL, 63) != 1) return 8; + if (shr_i(-8, 1) != -4) return 9; + if (shr_i(-1, 63) != -1) return 10; + if (div_u(0xffffffffffffffffULL, 3) != 0x5555555555555555ULL) return 11; + if (mod_u(0xffffffffffffffffULL, 7) != 1) return 12; + if (div_u(0x8000000000000000ULL, 0xffffffffffffffffULL) != 0) return 13; + if (mod_u(0x8000000000000000ULL, 0xffffffffffffffffULL) != 0x8000000000000000ULL) return 14; + if (div_i(-7, 2) != -3) return 15; + if (mod_i(-7, 2) != -1) return 16; + if (div_i(7, -2) != -3) return 17; + if (mod_i(7, -2) != 1) return 18; + if (ror_u(0x0123456789abcdefULL, 7) != 0xde02468acf13579bULL) return 19; + if (!lt_i(-2, 1) || lt_i(1, -2)) return 20; + if (!gt_i(1, -2) || gt_i(-2, 1)) return 21; + if (!le_i(3, 3) || le_i(4, 3)) return 22; + if (!ge_i(3, 3) || ge_i(3, 4)) return 23; + if (!lt_u(1, 0xffffffffffffffffULL) || lt_u(0xffffffffffffffffULL, 1)) return 24; + if (!gt_u(0xffffffffffffffffULL, 1) || gt_u(1, 0xffffffffffffffffULL)) return 25; + if (!le_u(5, 5) || le_u(6, 5)) return 26; + if (!ge_u(5, 5) || ge_u(5, 6)) return 27; + if (!eq_i(-1, -1) || eq_i(-1, 1)) return 28; + if (!ne_i(-1, 1) || ne_i(-1, -1)) return 29; + // Callee-narrows Extend(Imm) folds, including a truncating + // conversion (6.3.1.3p3, implementation-defined: two's-complement + // wrap). + if (sext8(-100) != -100) return 30; + if (sext8(511) != -1) return 31; + if (sext16(-30000) != -30000) return 32; + if (sext16(0x18000) != -32768) return 33; + if (sext32(-2000000000) != -2000000000) return 34; + if (sext32(0xf80000000LL) != -2147483648LL) return 35; + // Immediate-operand rewrites over a runtime value: rhs-imm form + // and the commuted / mirrored lhs-imm form must agree with the + // literal expectations for the known seed. + volatile u64 seed = 0x0123456789abcdefULL; + u64 x = seed; + if (5 + x != 0x0123456789abcdf4ULL) return 36; + if (x + 5 != 0x0123456789abcdf4ULL) return 37; + if (!(100 < x)) return 38; + if (100 > x) return 39; + if (!(0xffffffffffffffffULL >= x)) return 40; + if (ror_u(x, 7) != 0xde02468acf13579bULL) return 41; + if (shl_u(x, 65) != 0x02468acf13579bdeULL) return 42; + volatile i64 sneg = -8; + if (shr_i(sneg, 1) != -4) return 43; + return 0; +} diff --git a/tests/fixtures/c/dead_local_load_frame_elide.c b/tests/fixtures/c/dead_local_load_frame_elide.c new file mode 100644 index 000000000..2f66b7420 --- /dev/null +++ b/tests/fixtures/c/dead_local_load_frame_elide.c @@ -0,0 +1,29 @@ +// A slot load with no consumers emits no machine code, so it must not +// force a frame: an object that is never observed needs no storage +// (C99 6.2.4p2), and the loop leaf below compiles without a prologue. +// A volatile slot access is itself observable behaviour (5.1.2.3p2 / +// 6.7.3p6), is always emitted, and keeps the frame. + +typedef unsigned char u8; +typedef unsigned long long u64; + +u64 fold(const u8 *x) { + u64 i, u = 0; + for (i = 0; i < 8; i++) u = (u << 8) | x[i]; + return u; +} + +long vol_keep(const u8 *x) { + volatile long u = x[0]; + u; + return 9; +} + +int main(void) { + u8 buf[8]; + u64 i; + for (i = 0; i < 8; i++) buf[i] = (u8)(i + 1); + if (fold(buf) != 0x0102030405060708ULL) return 1; + if (vol_keep(buf) != 9) return 2; + return 0; +} diff --git a/tests/fixtures/c/float_literal_arith_single_precision.c b/tests/fixtures/c/float_literal_arith_single_precision.c new file mode 100644 index 000000000..16a0ab31f --- /dev/null +++ b/tests/fixtures/c/float_literal_arith_single_precision.c @@ -0,0 +1,28 @@ +// C99 6.3.1.8: `float op float-constant` stays in single precision -- +// an `f`-suffixed literal has type float (6.4.4.2p4), so no widen / +// narrow hop brackets the operation. Runtime checks pin the values; +// the SSA snapshot pins the single-precision ops. + +static float step(float x) { + return x - 1.0f; +} + +static float blend(float x, float y) { + return x * 0.5f + y * 0.25f; +} + +int main(void) { + if (step(2.5f) != 1.5f) return 1; + if (blend(3.0f, 8.0f) != 3.5f) return 2; + + // Accumulation where f32 and f64 intermediates diverge: ten + // additions of 0.1f in f32 land at 1.0000001f, not 1.0f. + float sum = 0.0f; + for (int i = 0; i < 10; i++) { + sum = sum + 0.1f; + } + if (sum == 1.0f) return 3; + if (sum != 1.0000001f) return 4; + + return 0; +} diff --git a/tests/fixtures/c/float_literal_f_suffix.c b/tests/fixtures/c/float_literal_f_suffix.c new file mode 100644 index 000000000..4503538ab --- /dev/null +++ b/tests/fixtures/c/float_literal_f_suffix.c @@ -0,0 +1,54 @@ +// C99 6.4.4.2p4: an unsuffixed floating constant has type double, +// `f`/`F` float, `l`/`L` long double (which c5 represents as +// double). p5: the value is converted to the constant's type at +// the literal, so an `f`-suffixed constant carries single-precision +// rounding into any wider context. + +#include + +static double vsum(int n, ...) { + va_list ap; + va_start(ap, n); + double s = 0; + int i; + for (i = 0; i < n; i++) { + s += va_arg(ap, double); + } + va_end(ap); + return s; +} + +int main(void) { + // Constant types observed through sizeof (6.5.3.4). + if (sizeof(1.0f) != 4) return 1; + if (sizeof(1.0F) != 4) return 2; + if (sizeof(1.0) != 8) return 3; + if (sizeof(1.0l) != 8) return 4; + if (sizeof(1.0L) != 8) return 5; + if (sizeof(.5f) != 4) return 6; + if (sizeof(1e2f) != 4) return 7; + if (sizeof(0x1p0f) != 4) return 8; + + // 16777217 is the first integer with no f32 representation: the + // f-suffixed constant rounds to 16777216 at the literal, while + // the double constant holds it exactly. + if (16777217.0f != 16777216.0f) return 9; + if (16777217.0 == 16777216.0) return 10; + + // The f32 rounding survives widening (6.3.1.5): (double)0.1f is + // the exact value of the f32 nearest 0.1, not the double nearest. + if (0.1f == 0.1) return 11; + if (0.1f != 0.10000000149011611938476562500) return 12; + if (-0.1f != -0.10000000149011611938476562500) return 13; + + // Default argument promotion (6.5.2.2p6): an f-suffixed literal + // argument reaches the variadic callee as its exact double + // widening. + if (vsum(2, 1.5f, 0.25f) != 1.75) return 14; + if (vsum(1, 0.1f) != 0.10000000149011611938476562500) return 16; + + // A hex floating constant (6.4.4.2) takes the suffix too. + if (0x1.000002p24f != 16777218.0f) return 15; + + return 0; +} diff --git a/tests/fixtures/c/float_literal_variadic_printf.c b/tests/fixtures/c/float_literal_variadic_printf.c new file mode 100644 index 000000000..e83ccaf55 --- /dev/null +++ b/tests/fixtures/c/float_literal_variadic_printf.c @@ -0,0 +1,14 @@ +// C99 6.5.2.2p6: a `float` argument to a variadic function undergoes +// the default argument promotion to `double`; an `f`-suffixed literal +// (6.4.4.2p4) rides the same path. The formatted text pins the exact +// promoted values, including the single-precision rounding of 0.1f. + +#include +#include + +int main(void) { + char buf[64]; + snprintf(buf, sizeof buf, "%.1f %.8f", 1.5f, 0.1f); + if (strcmp(buf, "1.5 0.10000000") != 0) return 1; + return 0; +} diff --git a/tests/fixtures/c/float_long_double_suffix.c b/tests/fixtures/c/float_long_double_suffix.c index 766e6c744..af5175f8a 100644 --- a/tests/fixtures/c/float_long_double_suffix.c +++ b/tests/fixtures/c/float_long_double_suffix.c @@ -1,8 +1,8 @@ // Locks C99 6.4.4.2 -- the floating-suffix is one of f / F / l / L. -// `f`/`F` mark `float`, `l`/`L` mark `long double`. The c5 dialect -// stores every floating literal in `f64` and treats the suffix as -// informational, so the four spellings of the same value must all -// land at the same bit pattern. +// `f`/`F` type the constant `float`, `l`/`L` `long double` (which c5 +// represents as double). 1.0 is exact in every precision, so the +// four spellings of the value must all land at the same bit pattern +// after conversion to double. // // Returns 0 only when every check passes; each failure path // returns a distinct nonzero code. diff --git a/tests/fixtures/c/float_param_stack_overflow.c b/tests/fixtures/c/float_param_stack_overflow.c new file mode 100644 index 000000000..4e0e74ff8 --- /dev/null +++ b/tests/fixtures/c/float_param_stack_overflow.c @@ -0,0 +1,29 @@ +// A `float` parameter past the FP argument registers rides the host +// stack at single precision (System V AMD64 3.2.3 / AAPCS64 6.4.1); +// Win64 overflows after four positional slots. The callee reads the +// cell back as an f32 bit pattern, so a caller storing a widened +// double there yields 0.0f. Weighted positions catch a dropped or +// permuted overflow slot, direct and through a function pointer. + +static int wsum(float a, float b, float c, float d, float e, + float f, float g, float h, float i, float j) { + return (int)(a * 1.0f + b * 2.0f + c * 4.0f + d * 8.0f + e * 16.0f + + f * 32.0f + g * 64.0f + h * 128.0f + i * 256.0f + j * 512.0f); +} + +typedef int (*wf)(float, float, float, float, float, + float, float, float, float, float); + +volatile float fone = 1.0f; + +int main(void) { + float v = fone; + int d = wsum(v, v, v, v, v, v, v, v, v, v); + /* 1+2+4+8+16+32+64+128+256+512 */ + if (d != 1023) return 1; + wf p = wsum; + int r = p(v, v, v, v, v, v, v, v, 1.5f, 0.5f); + /* 255 + 1.5*256 + 0.5*512 = 255 + 384 + 256 */ + if (r != 895) return 2; + return 0; +} diff --git a/tests/fixtures/c/indirect_call_mixed_fp_int_args.c b/tests/fixtures/c/indirect_call_mixed_fp_int_args.c new file mode 100644 index 000000000..08042bd18 --- /dev/null +++ b/tests/fixtures/c/indirect_call_mixed_fp_int_args.c @@ -0,0 +1,26 @@ +// Mixed integer and floating scalar arguments through a non-variadic +// function pointer: the integer and FP argument banks advance +// independently (AAPCS64 6.4.1 / SysV AMD64 3.2.3), routed at the call +// site by the argument-type mask. Interleaving the banks catches a +// mask that sends an FP argument through the integer bank or the +// reverse. + +static int mixfn(int a, double x, int b, double y, float z, int c) { + return a + (int)(x * 10.0) + b + (int)(y * 100.0) + (int)(z * 2.0f) + c; +} + +typedef int (*mf)(int, double, int, double, float, int); + +volatile int ione = 1; +volatile double dbase = 2.5; + +int main(void) { + mf p = mixfn; + int a = ione; + double x = dbase; + int r = p(a, x, a + 2, 0.25, 1.5f, 7); + /* 1 + 25 + 3 + 25 + 3 + 7 */ + if (r != 64) return 1; + if (r != mixfn(a, x, a + 2, 0.25, 1.5f, 7)) return 2; + return 0; +} diff --git a/tests/fixtures/c/indirect_call_narrow_scalar_args.c b/tests/fixtures/c/indirect_call_narrow_scalar_args.c new file mode 100644 index 000000000..73d927bd2 --- /dev/null +++ b/tests/fixtures/c/indirect_call_narrow_scalar_args.c @@ -0,0 +1,23 @@ +// A non-variadic indirect call marshals its scalar arguments per the +// host ABI, and each argument is converted to the pointee prototype's +// parameter type (C99 6.5.2.2p7). Narrow (char/short) parameters must +// observe the same converted values through the fn-pointer boundary +// as through a direct call. + +static int take(signed char c, short s, int i) { + return (int)c * 100000 + (int)s * 10 + i; +} + +typedef int (*fn3)(signed char, short, int); + +volatile int big = 0x12345; + +int main(void) { + fn3 p = take; + int v = big; /* 74565: char 0x45 = 69, short 0x2345 = 9029 */ + int direct = take(v, v, v); + int indirect = p(v, v, v); + if (direct != indirect) return 1; + if (indirect != 69 * 100000 + 9029 * 10 + 74565) return 2; + return 0; +} diff --git a/tests/fixtures/c/indirect_call_ten_scalar_args.c b/tests/fixtures/c/indirect_call_ten_scalar_args.c new file mode 100644 index 000000000..21de0c850 --- /dev/null +++ b/tests/fixtures/c/indirect_call_ten_scalar_args.c @@ -0,0 +1,24 @@ +// Ten integer arguments through a function pointer: the first eight +// ride the integer argument registers and the ninth and tenth land in +// the host stack overflow slots (AAPCS64 6.4.1 stage C / SysV AMD64 +// 3.2.3). A distinct positional weight per argument makes any slot +// permutation or missed overflow store change the result. + +static long weight10(long a, long b, long c, long d, long e, long f, long g, long h, long i, + long j) { + return a * 1 + b * 2 + c * 3 + d * 4 + e * 5 + f * 6 + g * 7 + h * 8 + i * 9 + j * 10; +} + +typedef long (*w10)(long, long, long, long, long, long, long, long, long, long); + +volatile long base = 1; + +int main(void) { + w10 p = weight10; + long b0 = base; + long r = p(b0, b0 + 1, b0 + 2, b0 + 3, b0 + 4, b0 + 5, b0 + 6, b0 + 7, b0 + 8, b0 + 9); + if (r != 385) return 1; /* sum of k*k, k = 1..10 */ + long d = weight10(b0, b0 + 1, b0 + 2, b0 + 3, b0 + 4, b0 + 5, b0 + 6, b0 + 7, b0 + 8, b0 + 9); + if (r != d) return 2; + return 0; +} diff --git a/tests/fixtures/c/indirect_call_variadic_fp_control.c b/tests/fixtures/c/indirect_call_variadic_fp_control.c new file mode 100644 index 000000000..db8e7255e --- /dev/null +++ b/tests/fixtures/c/indirect_call_variadic_fp_control.c @@ -0,0 +1,31 @@ +// A variadic callee reached through a function pointer keeps the host +// variadic placement (C99 6.5.2.2p7; the pointee prototype's ellipsis +// selects the variadic protocol at the call site). Mixed int/double +// varargs exercise both banks and the stack tail. + +#include + +static double vsum(int n, ...) { + va_list ap; + va_start(ap, n); + double acc = 0.0; + for (int i = 0; i < n; i++) { + if (i % 2 == 0) { + acc += (double)va_arg(ap, int); + } else { + acc += va_arg(ap, double); + } + } + va_end(ap); + return acc; +} + +typedef double (*vf)(int, ...); + +int main(void) { + vf p = vsum; + double r = p(4, 1, 2.5, 3, 4.25); + if (r != 10.75) return 1; + if (r != vsum(4, 1, 2.5, 3, 4.25)) return 2; + return 0; +} diff --git a/tests/fixtures/c/init_brace_intermediate_cast.c b/tests/fixtures/c/init_brace_intermediate_cast.c new file mode 100644 index 000000000..7b1b5ef27 --- /dev/null +++ b/tests/fixtures/c/init_brace_intermediate_cast.c @@ -0,0 +1,77 @@ +// C99 6.5.4: a cast converts the operand to the named type, so an +// intermediate cast narrows before any outer widening. 6.7.8p11: an +// initializer is converted to the object's type as by assignment +// after the expression's own conversions. Brace-enclosed elements +// must apply every cast in the chain, in static and automatic +// storage, for array and struct members alike. + +struct box { + long long l; + unsigned long long ul; + int i; +}; + +long long sa[4] = { + (long long)(int)0x92492493, + (long long)(unsigned)0x1FFFFFFFFLL, + (long long)(short)0xFFFF, + (long long)(signed char)0x1FF, +}; +unsigned long long sua[2] = { (unsigned long long)(short)0xFFFF, (unsigned long long)(int)0x92492493 }; +int sia[2] = { (int)(signed char)200, (int)(short)0x18000 }; +struct box sb = { (long long)(int)0x92492493, (unsigned long long)(short)0xFFFF, (int)(signed char)200 }; + +// Scalar wrapped in the optional brace pair (6.7.8p11). +long long sscal = { (long long)(int)0x92492493 }; + +// The cast binds tighter than a following binary operator (6.5.4). +long long sprec[2] = { (int)0x100000000LL / 2, (int)0xFFFFFFFF >> 4 }; + +// Casts converting between integer and floating values (6.3.1.4). +int sfi[1] = { (int)2.75 }; +double sfd[1] = { (long long)3.9 }; + +int main(void) { + long long aa[4] = { + (long long)(int)0x92492493, + (long long)(unsigned)0x1FFFFFFFFLL, + (long long)(short)0xFFFF, + (long long)(signed char)0x1FF, + }; + unsigned long long aua[2] = { (unsigned long long)(short)0xFFFF, (unsigned long long)(int)0x92492493 }; + int aia[2] = { (int)(signed char)200, (int)(short)0x18000 }; + struct box ab = { (long long)(int)0x92492493, (unsigned long long)(short)0xFFFF, (int)(signed char)200 }; + long long ascal = { (long long)(int)0x92492493 }; + + if (sa[0] != -1840700269LL) return 1; + if (sa[1] != 4294967295LL) return 2; + if (sa[2] != -1LL) return 3; + if (sa[3] != -1LL) return 4; + if (sua[0] != 0xFFFFFFFFFFFFFFFFULL) return 5; + if (sua[1] != 0xFFFFFFFF92492493ULL) return 6; + if (sia[0] != -56) return 7; + if (sia[1] != -32768) return 8; + if (sb.l != -1840700269LL) return 9; + if (sb.ul != 0xFFFFFFFFFFFFFFFFULL) return 10; + if (sb.i != -56) return 11; + if (sscal != -1840700269LL) return 12; + if (sprec[0] != 0LL) return 13; + if (sprec[1] != -1LL) return 14; + if (sfi[0] != 2) return 15; + if (sfd[0] != 3.0) return 16; + + if (aa[0] != -1840700269LL) return 17; + if (aa[1] != 4294967295LL) return 18; + if (aa[2] != -1LL) return 19; + if (aa[3] != -1LL) return 20; + if (aua[0] != 0xFFFFFFFFFFFFFFFFULL) return 21; + if (aua[1] != 0xFFFFFFFF92492493ULL) return 22; + if (aia[0] != -56) return 23; + if (aia[1] != -32768) return 24; + if (ab.l != -1840700269LL) return 25; + if (ab.ul != 0xFFFFFFFFFFFFFFFFULL) return 26; + if (ab.i != -56) return 27; + if (ascal != -1840700269LL) return 28; + + return 0; +} diff --git a/tests/fixtures/c/layout_bottom_test_loop.c b/tests/fixtures/c/layout_bottom_test_loop.c new file mode 100644 index 000000000..d62eaca90 --- /dev/null +++ b/tests/fixtures/c/layout_bottom_test_loop.c @@ -0,0 +1,11 @@ +// A counted loop. The block layout pass rotates it to bottom-test +// form: the body and step fall through in layout order and the back +// edge is a single conditional branch to the loop top. +int main(void) { + int sum = 0; + int i; + for (i = 0; i < 10; i++) { + sum += i; + } + return sum; +} diff --git a/tests/fixtures/c/layout_goto_block_addr.c b/tests/fixtures/c/layout_goto_block_addr.c new file mode 100644 index 000000000..ea86efa8a --- /dev/null +++ b/tests/fixtures/c/layout_goto_block_addr.c @@ -0,0 +1,34 @@ +// Loops built from plain gotos and from GCC labels-as-values. The +// plain-goto loop in main is layout-eligible; dispatch takes label +// addresses (`&&label`), so the layout pass leaves its block order +// untouched and the label table stays valid. +static int dispatch(int n) { + void *labels[2]; + labels[0] = &&even; + labels[1] = &&odd; + int acc = 0; + int i = 0; +next: + if (i >= n) + return acc; + goto *labels[i & 1]; +even: + acc += 2; + i++; + goto next; +odd: + acc += 1; + i++; + goto next; +} + +int main(void) { + int acc = 0; + int i = 0; +again: + acc += dispatch(i); + i++; + if (i < 5) + goto again; + return acc; +} diff --git a/tests/fixtures/c/layout_nested_loops.c b/tests/fixtures/c/layout_nested_loops.c new file mode 100644 index 000000000..a175a96a1 --- /dev/null +++ b/tests/fixtures/c/layout_nested_loops.c @@ -0,0 +1,20 @@ +// Nested counted loops with continue paths that share the inner +// step block. The layout pass keeps each loop's blocks contiguous, +// rotates both loops to bottom-test form, and places the shared +// step block directly before the rotated inner header so the back +// edge falls through. +int main(void) { + int total = 0; + int i, j; + for (i = 0; i < 6; i++) { + for (j = 0; j < i; j++) { + if ((i + j) % 3 == 0) + continue; + if (j == 4) + continue; + total += j; + } + total += i; + } + return total; +} diff --git a/tests/fixtures/c/narrow_param_entry_extend.c b/tests/fixtures/c/narrow_param_entry_extend.c new file mode 100644 index 000000000..e94464b64 --- /dev/null +++ b/tests/fixtures/c/narrow_param_entry_extend.c @@ -0,0 +1,30 @@ +// A register-passed narrow parameter arrives as the caller's raw +// 64-bit value; the callee applies the C99 6.5.2.2p4 / 6.3.1.3 +// conversion on entry. The entry sign-extension used to be skipped +// whenever no consumer read bits 32..63, but an I8/I16 conversion +// also rewrites bits 8..31: a product truncated to int observed the +// unconverted low word. The volatile loop keeps the callees out of +// the inliner so the parameter entry path is what executes. + +volatile int big = 0x12345; + +static int scale(signed char c, short s, int i) { + volatile int pad = 0; + for (int k = 0; k < 3; k++) pad += k; + (void)pad; + return (int)c * 100000 + (int)s * 10 + i; +} + +static unsigned uscale(unsigned char c, unsigned short s) { + volatile int pad = 0; + for (int k = 0; k < 3; k++) pad += k; + (void)pad; + return (unsigned)c * 100000u + (unsigned)s; +} + +int main(void) { + int v = big; /* 74565: char 69, short 9029 */ + if (scale(v, v, v) != 69 * 100000 + 9029 * 10 + 74565) return 1; + if (uscale(v, v) != 69u * 100000u + 9029u) return 2; + return 0; +} diff --git a/tests/fixtures/c/ndebug_optimize_predefine.c b/tests/fixtures/c/ndebug_optimize_predefine.c new file mode 100644 index 000000000..c1f2b9918 --- /dev/null +++ b/tests/fixtures/c/ndebug_optimize_predefine.c @@ -0,0 +1,13 @@ +// `-O` predefines `NDEBUG` and `__OPTIMIZE__` (both 1, following the +// gcc/clang convention for the latter); explicit `-D` / `-U` flags +// override the implied values. The exit code reports what the +// preprocessor saw: both defined -> the NDEBUG value, exactly one +// defined -> 101, neither -> 100. + +#if defined(NDEBUG) && defined(__OPTIMIZE__) +int main(void) { return NDEBUG; } +#elif defined(NDEBUG) || defined(__OPTIMIZE__) +int main(void) { return 101; } +#else +int main(void) { return 100; } +#endif diff --git a/tests/fixtures/c/ndebug_undef_reenables_assert.c b/tests/fixtures/c/ndebug_undef_reenables_assert.c new file mode 100644 index 000000000..3e3b5e158 --- /dev/null +++ b/tests/fixtures/c/ndebug_undef_reenables_assert.c @@ -0,0 +1,10 @@ +// With `-O` the implied `NDEBUG` compiles the assert out and the +// program exits 0; `-U NDEBUG` on top of `-O` removes the predefine, +// so the false assertion fires and the program traps. + +#include + +int main(void) { + assert(0); + return 0; +} diff --git a/tests/fixtures/c/qsort_scan_extend_dedup.c b/tests/fixtures/c/qsort_scan_extend_dedup.c new file mode 100644 index 000000000..1ebf9828a --- /dev/null +++ b/tests/fixtures/c/qsort_scan_extend_dedup.c @@ -0,0 +1,38 @@ +// A partition scan re-derives `(long)i` in the loop header, the +// increment block, and the swap block. The extends are the same +// (value, kind) at dominated positions, so one dominating sxtw / +// movslq per iteration suffices (C99 6.3.1.3 gives one conversion +// result per value). Locks the cross-block extend dedup; the sort +// result checks the deduped index still addresses correctly. + +static void qs(int *a, int lo, int hi) { + if (lo >= hi) return; + int pivot = a[(lo + hi) / 2]; + int i = lo, j = hi; + while (i <= j) { + while (a[i] < pivot) i++; + while (a[j] > pivot) j--; + if (i <= j) { + int t = a[i]; + a[i] = a[j]; + a[j] = t; + i++; + j--; + } + } + qs(a, lo, j); + qs(a, i, hi); +} + +int main(void) { + int a[64]; + unsigned int seed = 12345u; + for (int i = 0; i < 64; i++) { + seed = seed * 1103515245u + 12345u; + a[i] = (int)(seed >> 16) - 0x4000; + } + qs(a, 0, 63); + for (int i = 1; i < 64; i++) + if (a[i] < a[i - 1]) return 1; + return 0; +} diff --git a/tests/fixtures/c/reg_alloc_callee_bank_call_block_before_loop.c b/tests/fixtures/c/reg_alloc_callee_bank_call_block_before_loop.c new file mode 100644 index 000000000..fbe4f75c8 --- /dev/null +++ b/tests/fixtures/c/reg_alloc_callee_bank_call_block_before_loop.c @@ -0,0 +1,42 @@ +// Call-crossing precision for phi classes: in `qs` the recursive-call +// block is laid out at a lower pc than the partition loop, and the +// loop keeps more values live than the callee bank minus one. Only +// the values whose CFG live range spans the calls (a, hi, i) need a +// callee-saved home; a pc-interval test also flagged lo/pivot/j, +// overfilled the callee bank, and spilled the loop induction +// variable. The SSA snapshot locks spill_count=0 for `qs`. +static void qs(int *a, int lo, int hi) { + if (lo >= hi) return; + int pivot = a[(lo + hi) / 2]; + int i = lo, j = hi; + while (i <= j) { + while (a[i] < pivot) i++; + while (a[j] > pivot) j--; + if (i <= j) { + int t = a[i]; + a[i] = a[j]; + a[j] = t; + i++; + j--; + } + } + qs(a, lo, j); + qs(a, i, hi); +} + +int main(void) { + int a[64]; + unsigned int seed = 12345; + int i; + for (i = 0; i < 64; i++) { + seed = seed * 1103515245u + 12345u; + a[i] = (int)(seed & 0x7fffffff); + } + qs(a, 0, 63); + for (i = 1; i < 64; i++) { + if (a[i] < a[i - 1]) { + return 1; + } + } + return 0; +} diff --git a/tests/fixtures/c/rotate_inline_const_count.c b/tests/fixtures/c/rotate_inline_const_count.c new file mode 100644 index 000000000..66c83dd7f --- /dev/null +++ b/tests/fixtures/c/rotate_inline_const_count.c @@ -0,0 +1,17 @@ +// A static rotate helper called with constant counts: after inlining +// the counts are immediates behind a callee-narrows extend, so the +// constant folder plus the rotate pass must produce the +// immediate-form rotate (rorq $n / ror #n, pinned by the asm +// snapshots) rather than the register-count sequence. Exit 0 when +// the mixed value matches the reference. + +typedef unsigned long long u64; + +static u64 R(u64 x, int c) { return (x >> c) | (x << (64 - c)); } +static u64 mix(u64 x) { return R(x, 28) ^ R(x, 34) ^ R(x, 39); } + +int main(void) { + volatile u64 seed = 0x0123456789abcdefULL; + if (mix(seed) != 0xb7c57a100c7ec1abULL) return 1; + return 0; +} diff --git a/tests/fixtures/c/setjmp_spill_slots_unshared.c b/tests/fixtures/c/setjmp_spill_slots_unshared.c new file mode 100644 index 000000000..0360f0183 --- /dev/null +++ b/tests/fixtures/c/setjmp_spill_slots_unshared.c @@ -0,0 +1,69 @@ +// C99 7.13.2.1p3: automatic objects not modified between setjmp and +// longjmp keep their values at the second return. longjmp restores +// registers but not the frame, so first-return-path temporaries must +// not reuse the spill slots of values read only after the second +// return. The eight saved values must survive the longjmp. +#include +#include +#include + +jmp_buf env; +int seed[64]; +int acc; + +int main(void) { + for (int i = 0; i < 64; i++) { + seed[i] = i + 1; + } + int v0 = seed[0] * 3 + 0; + int v1 = seed[1] * 3 + 1; + int v2 = seed[2] * 3 + 2; + int v3 = seed[3] * 3 + 3; + int v4 = seed[4] * 3 + 4; + int v5 = seed[5] * 3 + 5; + int v6 = seed[6] * 3 + 6; + int v7 = seed[7] * 3 + 7; + if (setjmp(env) != 0) { + int mask = 0; + if (v0 != seed[0] * 3 + 0) mask |= 1 << 0; + if (v1 != seed[1] * 3 + 1) mask |= 1 << 1; + if (v2 != seed[2] * 3 + 2) mask |= 1 << 2; + if (v3 != seed[3] * 3 + 3) mask |= 1 << 3; + if (v4 != seed[4] * 3 + 4) mask |= 1 << 4; + if (v5 != seed[5] * 3 + 5) mask |= 1 << 5; + if (v6 != seed[6] * 3 + 6) mask |= 1 << 6; + if (v7 != seed[7] * 3 + 7) mask |= 1 << 7; + if (mask) { + printf("CLOBBERED mask=%x\n", mask); + return 1; + } + printf("ok\n"); + return 0; + } + // First-return path: many simultaneously-live temporaries feeding + // a wide sum, forcing spills, then jump back. + int t0 = seed[16] * 5 + 1; + int t1 = seed[17] * 5 + 2; + int t2 = seed[18] * 5 + 3; + int t3 = seed[19] * 5 + 4; + int t4 = seed[20] * 5 + 5; + int t5 = seed[21] * 5 + 6; + int t6 = seed[22] * 5 + 7; + int t7 = seed[23] * 5 + 8; + int t8 = seed[24] * 5 + 9; + int t9 = seed[25] * 5 + 10; + int t10 = seed[26] * 5 + 11; + int t11 = seed[27] * 5 + 12; + int t12 = seed[28] * 5 + 13; + int t13 = seed[29] * 5 + 14; + int t14 = seed[30] * 5 + 15; + int t15 = seed[31] * 5 + 16; + int t16 = seed[32] * 5 + 17; + int t17 = seed[33] * 5 + 18; + int t18 = seed[34] * 5 + 19; + int t19 = seed[35] * 5 + 20; + acc = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 + t9 + t10 + t11 + + t12 + t13 + t14 + t15 + t16 + t17 + t18 + t19; + longjmp(env, 1); + return 2; +} diff --git a/tests/fixtures/c/sroa_const_index_local_array.c b/tests/fixtures/c/sroa_const_index_local_array.c new file mode 100644 index 000000000..d7a7711d8 --- /dev/null +++ b/tests/fixtures/c/sroa_const_index_local_array.c @@ -0,0 +1,31 @@ +/* A fixed-size local array whose subscripts all become constant once the + * trip loops fully unroll: `passes::sroa` splits the array into + * per-element slots and the mem2reg re-run promotes them to SSA values. + * `a` is carried across the runtime-trip while loop, so the promoted + * elements need header phis (locked by the SSA snapshot -- no LocalAddr + * or Store to the array base survives). The eight-element array stays + * within the usable-GPR budget of both targets, so it promotes on each. + * The rotated shift-and-carry exercises the per-element reaching + * definition across the collapsed inner loop; the computed sum is the + * runtime check. */ +typedef unsigned long long u64; + +u64 rounds(u64 *in, int n) { + u64 a[8]; + for (int i = 0; i < 8; i++) a[i] = in[i]; + while (n-- > 0) { + u64 last = a[7]; + for (int j = 7; j > 0; j--) a[j] = a[j - 1] + (a[j] << 1); + a[0] = last ^ (a[0] << 1); + } + u64 s = 0; + for (int i = 0; i < 8; i++) s += a[i]; + return s; +} + +int main(void) { + u64 in[8]; + for (int i = 0; i < 8; i++) in[i] = (u64)i * 0x1111 + 7; + if (rounds(in, 5) != 21938052ULL) return 1; + return 0; +} diff --git a/tests/fixtures/c/sroa_runtime_index_stays_memory.c b/tests/fixtures/c/sroa_runtime_index_stays_memory.c new file mode 100644 index 000000000..86710173d --- /dev/null +++ b/tests/fixtures/c/sroa_runtime_index_stays_memory.c @@ -0,0 +1,20 @@ +/* A local array with a runtime subscript stays memory-resident: the + * trip-8 fill loop unrolls (so the function is a scalar-promotion + * candidate), but the runtime-indexed reads `a[k & 7]` cannot map to a + * fixed element slot, so `passes::sroa` must leave the whole array in the + * frame (locked by the SSA snapshot -- the array is still addressed + * through its base). The computed value is the runtime check. */ +typedef unsigned long long u64; + +u64 pick(u64 *in, int k) { + u64 a[8]; + for (int i = 0; i < 8; i++) a[i] = in[i] * 3 + 1; + return a[k & 7] + a[(k + 5) & 7]; +} + +int main(void) { + u64 in[8]; + for (int i = 0; i < 8; i++) in[i] = (u64)i; + if (pick(in, 10) != 29ULL) return 1; + return 0; +} diff --git a/tests/fixtures/c/static_init_once_guard.c b/tests/fixtures/c/static_init_once_guard.c new file mode 100644 index 000000000..896e69ec2 --- /dev/null +++ b/tests/fixtures/c/static_init_once_guard.c @@ -0,0 +1,43 @@ +// C99 6.2.4p3: an object with static storage duration is initialized +// exactly once, before program startup semantics apply to its lifetime. +// A static-local array whose initializer carries `&&label` elements is +// filled by runtime stores at the declaration point; those stores must +// not re-run on later calls, or they clobber user writes to the table. + +static void *saved; + +static int step(int n) { + static void *tbl[] = { &&l1, &&l2 }; + if (n == 0) { + // First call: record the original entry, then redirect slot 0. + saved = tbl[0]; + tbl[0] = tbl[1]; + goto *tbl[1]; + } + // Second call: the redirect must have survived the re-entry. + if (tbl[0] != tbl[1]) return 1; + tbl[0] = saved; + goto *tbl[0]; +l1: + return 10; +l2: + return 20; +} + +// A logical AND inside a constant element routes to the same runtime +// path (the initializer scan keys on the `&&` token), so its once +// semantics are locked too. +static int flag_table(int n, int set) { + static int flags[3] = { 1 && 1, 0, 1 }; + if (set) flags[1] = 7; + return flags[n]; +} + +int main(void) { + if (step(0) != 20) return 2; + if (step(1) != 10) return 3; + if (flag_table(1, 1) != 7) return 4; + if (flag_table(1, 0) != 7) return 5; + if (flag_table(0, 0) != 1) return 6; + return 0; +} diff --git a/tests/fixtures/c/store_forward_local_slot.c b/tests/fixtures/c/store_forward_local_slot.c new file mode 100644 index 000000000..3d9ba088f --- /dev/null +++ b/tests/fixtures/c/store_forward_local_slot.c @@ -0,0 +1,61 @@ +/* store_forward on frame slots. mem2reg skips a function containing a + computed goto, so its scalar locals stay as StoreLocal / LoadLocal; + a store immediately reloaded in the same block forwards to the stored + value. Negative controls: a volatile slot performs every access (C99 + 6.7.3p6), an address-taken slot observes a store through its pointer, + and a pair split across a block boundary reloads. */ + +/* acc's store and reloads sit in one block; the reloads forward. */ +static int forwards(int n) { + void *lab = &&out; + int acc; + acc = n * 3; + int r = acc + acc; + goto *lab; +out: + return r; +} + +/* Each access of v is performed: the reload is kept. */ +static int volatile_kept(int n) { + void *lab = &&out; + volatile int v; + v = n; + int r = v; + goto *lab; +out: + return r; +} + +/* x's address is taken; the store through p between x's store and the + reload must be observed, so the reload is kept. */ +static int aliased_kept(int n) { + void *lab = &&out; + int x; + int *p = &x; + x = n; + *p = n + 1; + int r = x; + goto *lab; +out: + return r; +} + +/* The store and the reload sit in different blocks: the reload is kept + (the pass is intra-block). */ +static int cross_block(int n) { + void *lab = &&join; + int acc; + acc = n * 2; + goto *lab; +join: + return acc; +} + +int main(void) { + if (forwards(5) != 30) return 1; + if (volatile_kept(7) != 7) return 2; + if (aliased_kept(9) != 10) return 3; + if (cross_block(6) != 12) return 4; + return 0; +} diff --git a/tests/fixtures/c/switch_jump_table_dense.c b/tests/fixtures/c/switch_jump_table_dense.c new file mode 100644 index 000000000..70c286345 --- /dev/null +++ b/tests/fixtures/c/switch_jump_table_dense.c @@ -0,0 +1,92 @@ +// A dense case set (>= 8 cases, >= 50% dense over the span) lowers to +// a jump table: a bias subtract, an unsigned bounds check to default, +// and an indexed branch through a text-embedded table. Every case must +// route to its block, a hole in the span and any out-of-range value +// (below the bias, above the span, negative) must reach default, and +// an unsigned discriminant biased near UINT_MAX must index correctly. + +static int dense_signed(int x) { + switch (x) { + case 3: return 1; + case 4: return 2; + case 5: return 3; + case 6: return 4; + case 7: return 5; + case 8: return 6; + case 9: return 7; + case 10: return 8; + case 11: return 9; + case 12: return 10; + case 13: return 11; + case 14: return 12; + // 15 is a hole: its table slot routes to default. + case 16: return 13; + case 17: return 14; + case 18: return 15; + case 19: return 16; + default: return -1; + } +} + +static int dense_negative_bias(long long x) { + switch (x) { + case -6: return 1; + case -5: return 2; + case -4: return 3; + case -3: return 4; + case -2: return 5; + case -1: return 6; + case 0: return 7; + case 1: return 8; + case 2: return 9; + default: return -1; + } +} + +static int dense_unsigned_high(unsigned u) { + switch (u) { + case 0xfffffff6u: return 1; + case 0xfffffff7u: return 2; + case 0xfffffff8u: return 3; + case 0xfffffff9u: return 4; + case 0xfffffffau: return 5; + case 0xfffffffbu: return 6; + case 0xfffffffcu: return 7; + case 0xfffffffdu: return 8; + case 0xfffffffeu: return 9; + case 0xffffffffu: return 10; + default: return -1; + } +} + +int main(void) { + // Every real case value routes to its block. + for (int i = 3; i <= 19; i++) { + if (i == 15) continue; + int want = i < 15 ? i - 2 : i - 3; + if (dense_signed(i) != want) return 1; + } + // The hole and both out-of-range sides reach default. + if (dense_signed(15) != -1) return 2; + if (dense_signed(2) != -1) return 3; + if (dense_signed(20) != -1) return 4; + if (dense_signed(-1) != -1) return 5; + if (dense_signed(-2147483647 - 1) != -1) return 6; + if (dense_signed(2147483647) != -1) return 7; + + for (long long i = -6; i <= 2; i++) { + if (dense_negative_bias(i) != (int)(i + 7)) return 8; + } + if (dense_negative_bias(-7) != -1) return 9; + if (dense_negative_bias(3) != -1) return 10; + if (dense_negative_bias(0x100000000ll) != -1) return 11; + if (dense_negative_bias(-0x100000000ll) != -1) return 12; + + for (unsigned i = 0; i < 10; i++) { + if (dense_unsigned_high(0xfffffff6u + i) != (int)(i + 1)) return 13; + } + if (dense_unsigned_high(0xfffffff5u) != -1) return 14; + if (dense_unsigned_high(0u) != -1) return 15; + if (dense_unsigned_high(0x7fffffffu) != -1) return 16; + return 0; +} diff --git a/tests/fixtures/c/switch_jump_table_phi_join.c b/tests/fixtures/c/switch_jump_table_phi_join.c new file mode 100644 index 000000000..1bd030067 --- /dev/null +++ b/tests/fixtures/c/switch_jump_table_phi_join.c @@ -0,0 +1,42 @@ +// Case blocks that fall through into each other so shared blocks +// carry phis under -O: each fall-into block merges the dispatcher's +// table edge with the previous case's fall-through edge. The +// critical-edge splitter must retarget the table entries onto +// trampoline blocks; without the split, the dispatcher exit would +// emit every successor's phi moves and clobber live values on the +// other table edges. + +static long long chain(int op, long long a, long long b) { + long long x = a; + long long y = b; + switch (op) { + case 0: x = a + 1; /* fall through */ + case 1: y = x + 2; /* fall through */ + case 2: x = x + y; /* fall through */ + case 3: y = y * 3; /* fall through */ + case 4: x = x - y; /* fall through */ + case 5: y = y + x; /* fall through */ + case 6: x = x * 2; /* fall through */ + case 7: y = y - 1; /* fall through */ + case 8: x = x + 7; /* fall through */ + case 9: y = y + x; break; + case 10: x = -a; break; + case 11: y = -b; break; + default: x = 13; y = 17; break; + } + return x * 31 + y; +} + +int main(void) { + long long h = 0; + for (int op = -2; op < 14; op++) { + for (long long a = -1; a < 3; a++) { + for (long long b = 0; b < 3; b++) { + h = h * 33 + chain(op, a, b); + } + } + } + // long long keeps 64-bit arithmetic on LLP64 (Windows) too. + // Golden value cross-checked against clang -O2 and -O0. + return h == -3365603682695239840LL ? 0 : 1; +} diff --git a/tests/fixtures/c/switch_jump_table_sparse_kept.c b/tests/fixtures/c/switch_jump_table_sparse_kept.c new file mode 100644 index 000000000..50c5edc8d --- /dev/null +++ b/tests/fixtures/c/switch_jump_table_sparse_kept.c @@ -0,0 +1,31 @@ +// A sparse case set keeps the balanced compare tree: with more than +// half the span made of holes a table would waste text, so the +// lowering's density gate (span < 2 * cases) must reject it. The +// routing semantics are identical either way; the asm snapshots lock +// the absence of the indexed-branch shape. + +static int sparse(int x) { + switch (x) { + case 0: return 1; + case 10: return 2; + case 20: return 3; + case 30: return 4; + case 40: return 5; + case 50: return 6; + case 60: return 7; + case 70: return 8; + case 80: return 9; + case 90: return 10; + default: return -1; + } +} + +int main(void) { + for (int i = 0; i < 10; i++) { + if (sparse(i * 10) != i + 1) return 1; + } + if (sparse(5) != -1) return 2; + if (sparse(-10) != -1) return 3; + if (sparse(100) != -1) return 4; + return 0; +} diff --git a/tests/fixtures/c/unroll_const_trip_copy.c b/tests/fixtures/c/unroll_const_trip_copy.c new file mode 100644 index 000000000..97673c564 --- /dev/null +++ b/tests/fixtures/c/unroll_const_trip_copy.c @@ -0,0 +1,17 @@ +/* Constant-trip loops fully unroll: the trip-8 copy loop and the + * rotated-index accumulation collapse to straight-line code (locked + * by the SSA snapshot); the computed values check the per-copy index + * substitution, including the signed % on the rotated index. */ +long a[8], b[8]; + +int main(void) { + long i, s = 0; + for (i = 0; i < 8; i++) a[i] = i * 3 + 1; + for (i = 0; i < 8; i++) b[i] = a[i]; + for (i = 0; i < 8; i++) s += b[(i + 1) % 8] * (i + 1); + /* sum of a[(i+1)%8] * (i+1) = sum over j of a[j]*w */ + if (s != 4 + 7 * 2 + 10 * 3 + 13 * 4 + 16 * 5 + 19 * 6 + 22 * 7 + 1 * 8) + return 1; + if (i != 8) return 2; + return 0; +} diff --git a/tests/fixtures/c/unroll_trip_17_stays_rolled.c b/tests/fixtures/c/unroll_trip_17_stays_rolled.c new file mode 100644 index 000000000..5472cfae0 --- /dev/null +++ b/tests/fixtures/c/unroll_trip_17_stays_rolled.c @@ -0,0 +1,10 @@ +/* A trip count above the unroll cap keeps the loop rolled: the SSA + * snapshot retains the header phi and back edge. */ +long acc[17]; + +int main(void) { + long i, s = 0; + for (i = 0; i < 17; i++) acc[i] = i; + for (i = 0; i < 17; i++) s += acc[i]; + return !(s == 136 && i == 17); +} diff --git a/tests/fixtures/c/unroll_volatile_stays_rolled.c b/tests/fixtures/c/unroll_volatile_stays_rolled.c new file mode 100644 index 000000000..c5b7fe64d --- /dev/null +++ b/tests/fixtures/c/unroll_volatile_stays_rolled.c @@ -0,0 +1,10 @@ +/* A volatile access is performed strictly per the abstract machine + * (C99 6.7.3p6): the loop must not unroll, and each of the four + * iterations performs one load and one store. */ +volatile long counter; + +int main(void) { + long i; + for (i = 0; i < 4; i++) counter = counter + 1; + return !(counter == 4 && i == 4); +} diff --git a/tests/fixtures/c/vfork_shared_stack_slot_reuse.c b/tests/fixtures/c/vfork_shared_stack_slot_reuse.c new file mode 100644 index 000000000..9fe56b3ba --- /dev/null +++ b/tests/fixtures/c/vfork_shared_stack_slot_reuse.c @@ -0,0 +1,89 @@ +// vfork(2)'s child runs on the parent's stack. Values read only after +// the parent resumes are dead on the child path by ordinary liveness, +// so without a returns-twice guard the child's call-staging +// temporaries reuse their spill slots and the resumed parent reads +// the clobber. The twelve saved values must survive the child. +#include +#include +#include +#include + +int seed[64]; + +int child_exec(int a0, int a1, int a2, int a3, int a4, int a5, int a6, + int a7, int a8, int a9, int a10, int a11, int a12, int a13, + int a14, int a15, int a16, int a17, int a18, int a19) { + return (a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 + a9 + a10 + a11 + + a12 + a13 + a14 + a15 + a16 + a17 + a18 + a19) & 0x7f; +} + +int main(void) { + for (int i = 0; i < 64; i++) { + seed[i] = i + 1; + } + int v0 = seed[0] * 3 + 0; + int v1 = seed[1] * 3 + 1; + int v2 = seed[2] * 3 + 2; + int v3 = seed[3] * 3 + 3; + int v4 = seed[4] * 3 + 4; + int v5 = seed[5] * 3 + 5; + int v6 = seed[6] * 3 + 6; + int v7 = seed[7] * 3 + 7; + int v8 = seed[8] * 3 + 8; + int v9 = seed[9] * 3 + 9; + int v10 = seed[10] * 3 + 10; + int v11 = seed[11] * 3 + 11; + int pid = vfork(); + if (pid < 0) { + printf("vfork failed\n"); + return 2; + } + if (pid != 0) { + int st = 0; + waitpid(pid, &st, 0); + int mask = 0; + if (v0 != seed[0] * 3 + 0) mask |= 1 << 0; + if (v1 != seed[1] * 3 + 1) mask |= 1 << 1; + if (v2 != seed[2] * 3 + 2) mask |= 1 << 2; + if (v3 != seed[3] * 3 + 3) mask |= 1 << 3; + if (v4 != seed[4] * 3 + 4) mask |= 1 << 4; + if (v5 != seed[5] * 3 + 5) mask |= 1 << 5; + if (v6 != seed[6] * 3 + 6) mask |= 1 << 6; + if (v7 != seed[7] * 3 + 7) mask |= 1 << 7; + if (v8 != seed[8] * 3 + 8) mask |= 1 << 8; + if (v9 != seed[9] * 3 + 9) mask |= 1 << 9; + if (v10 != seed[10] * 3 + 10) mask |= 1 << 10; + if (v11 != seed[11] * 3 + 11) mask |= 1 << 11; + if (mask) { + printf("CLOBBERED mask=%x\n", mask); + return 1; + } + printf("ok\n"); + return 0; + } + // Child: many simultaneously-live temporaries feeding a wide call, + // forcing spills into the frame the parent still owns. + int t0 = seed[16] * 5 + 1; + int t1 = seed[17] * 5 + 2; + int t2 = seed[18] * 5 + 3; + int t3 = seed[19] * 5 + 4; + int t4 = seed[20] * 5 + 5; + int t5 = seed[21] * 5 + 6; + int t6 = seed[22] * 5 + 7; + int t7 = seed[23] * 5 + 8; + int t8 = seed[24] * 5 + 9; + int t9 = seed[25] * 5 + 10; + int t10 = seed[26] * 5 + 11; + int t11 = seed[27] * 5 + 12; + int t12 = seed[28] * 5 + 13; + int t13 = seed[29] * 5 + 14; + int t14 = seed[30] * 5 + 15; + int t15 = seed[31] * 5 + 16; + int t16 = seed[32] * 5 + 17; + int t17 = seed[33] * 5 + 18; + int t18 = seed[34] * 5 + 19; + int t19 = seed[35] * 5 + 20; + _exit(child_exec(t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, + t13, t14, t15, t16, t17, t18, t19)); + return 3; +} diff --git a/tests/perf/run.py b/tests/perf/run.py index 13b715689..ba48e4f07 100755 --- a/tests/perf/run.py +++ b/tests/perf/run.py @@ -20,6 +20,9 @@ * cl /Od -- MSVC cl.exe on Windows. * cl /O2 -- MSVC cl.exe on Windows. +badc -O implies NDEBUG; the clang -O2 and cl /O2 rows pass -DNDEBUG +explicitly to match. The unoptimized entries keep asserts live. + Override the badc binary via $BADC; override the tcc binary via $TCC. """ @@ -213,7 +216,7 @@ def probe_compilers() -> list[Compiler]: # libSystem. Without `-lm` clang fails to link quickjs_bench. clang_trailing = ("-lm",) if sys.platform == "linux" else () found.append(Compiler("clang -O0", ["clang", "-O0"], trailing=clang_trailing)) - found.append(Compiler("clang -O2", ["clang", "-O2"], trailing=clang_trailing)) + found.append(Compiler("clang -O2", ["clang", "-O2", "-DNDEBUG"], trailing=clang_trailing)) if WIN and shutil.which("cl"): found.append( @@ -226,7 +229,7 @@ def probe_compilers() -> list[Compiler]: found.append( Compiler( "cl /O2", - ["cl", "/nologo", "/O2"], + ["cl", "/nologo", "/O2", "/DNDEBUG"], output_dash_o=False, ) ) diff --git a/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm b/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm index 30bce799a..14b183ab0 100644 --- a/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm +++ b/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x2, #0x0 // =0 sub x0, x29, #0x20 add x1, x29, #0x10 @@ -52,16 +51,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 str w17, [x16, #0x1c] mov x0, x2 - sxtw x1, w2 - ldursw x3, [x29, #0x10] - cmp x1, x3 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - sub x1, x29, #0x20 - mov x17, x1 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,15 +70,18 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x1, x16 - ldrsw x1, [x1] - add x0, x0, x1 - b + mov x3, x16 + ldrsw x3, [x3] + add x0, x0, x3 + add x2, x1, #0x1 + sxtw x1, w2 + ldursw x3, [x29, #0x10] + cmp x1, x3 + b.lt sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret @@ -108,10 +103,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x2, #0x0 // =0 scvtf d0, x2 sub x0, x29, #0x20 @@ -133,16 +127,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 str w17, [x16, #0x1c] - sxtw x0, w2 - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 b - sub x0, x29, #0x20 - mov x17, x0 + sub x1, x29, #0x20 + mov x17, x1 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x1c] cmp x16, #0x0 @@ -159,14 +146,17 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr d1, [x0] + mov x1, x16 + ldr d1, [x1] fadd d0, d0, d1 - b + add x2, x0, #0x1 + sxtw x0, w2 + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt sub x0, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret @@ -188,10 +178,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x2, #0x0 // =0 scvtf d0, x2 sub x0, x29, #0x20 @@ -213,27 +202,12 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 str w17, [x16, #0x1c] - sxtw x0, w2 - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 b - sxtw x0, w2 mov x17, #0x1 // =1 - and x0, x0, x17 - cbz x0, - b - sub x0, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - add sp, sp, #0xc0 - ret - sub x0, x29, #0x20 - mov x17, x0 + and x1, x0, x17 + cbz x1, + sub x1, x29, #0x20 + mov x17, x1 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x1c] cmp x16, #0x0 @@ -250,12 +224,12 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr d1, [x0] + mov x1, x16 + ldr d1, [x1] fadd d0, d0, d1 b - sub x0, x29, #0x20 - mov x17, x0 + sub x1, x29, #0x20 + mov x17, x1 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -272,11 +246,21 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldrsw x0, [x0] - scvtf d1, x0 + mov x1, x16 + ldrsw x1, [x1] + scvtf d1, x1 fadd d0, d0, d1 b + add x2, x0, #0x1 + sxtw x0, w2 + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt + sub x0, x29, #0x20 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 + add sp, sp, #0xc0 + ret : sub sp, sp, #0xc0 @@ -296,10 +280,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x2, #0x0 // =0 sub x0, x29, #0x20 add x1, x29, #0x10 @@ -333,16 +316,9 @@ Disassembly of section .text: str x9, [x0, #0x18] ldr x9, [sp], #0x10 mov x0, x2 - sxtw x1, w2 - ldursw x3, [x29, #0x10] - cmp x1, x3 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - sub x1, x29, #0x20 - mov x17, x1 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -359,21 +335,18 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x1, x16 - ldrsw x1, [x1] - add x0, x0, x1 - b - mov x2, #0x0 // =0 + mov x3, x16 + ldrsw x3, [x3] + add x0, x0, x3 + add x2, x1, #0x1 sxtw x1, w2 ldursw x3, [x29, #0x10] cmp x1, x3 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 + b.lt + mov x2, #0x0 // =0 b - sub x1, x29, #0x40 - mov x17, x1 + sub x3, x29, #0x40 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -390,16 +363,19 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x1, x16 - ldrsw x1, [x1] - add x0, x0, x1 - b + mov x3, x16 + ldrsw x3, [x3] + add x0, x0, x3 + add x2, x1, #0x1 + sxtw x1, w2 + ldursw x3, [x29, #0x10] + cmp x1, x3 + b.lt sub x1, x29, #0x40 sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret @@ -421,10 +397,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 ldursw x0, [x29, #0x10] ldursw x1, [x29, #0x18] add x0, x0, x1 @@ -525,17 +500,15 @@ Disassembly of section .text: add x0, x0, x1 sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, #0x0 // =0 mov x0, #0x5 // =5 mov x1, #0x1 // =1 @@ -546,8 +519,7 @@ Disassembly of section .text: bl cmp x0, #0xf b.eq - mov x17, #0x1 // =1 - orr x20, x20, x17 + mov x20, #0x1 // =1 mov x0, #0xc // =12 mov x1, #0x1 // =1 mov x2, #0x2 // =2 @@ -674,9 +646,8 @@ Disassembly of section .text: mov x17, #0x40 // =64 orr x20, x20, x17 sxtw x0, w20 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret b b diff --git a/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm b/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm index 51d48992c..d0dae5c80 100644 --- a/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm +++ b/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: leaq -0xe0(%rbp), %r10 movq %r10, 0x10(%rax) movq %rdx, %rax - movslq %edx, %rcx - movslq -0xe0(%rbp), %rsi - cmpq %rsi, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx jmp - leaq -0x18(%rbp), %rcx - movq %rcx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -58,10 +51,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rcx - movslq (%rcx), %rcx - addq %rcx, %rax - jmp + movq %r10, %rsi + movslq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rcx), %rdx + movslq %edx, %rcx + movslq -0xe0(%rbp), %rsi + cmpq %rsi, %rcx + jl leaq -0x18(%rbp), %rcx movslq %eax, %rax addq $0xe0, %rsp @@ -98,16 +95,9 @@ Disassembly of section .text: movq %r10, 0x8(%rax) leaq -0xe0(%rbp), %r10 movq %r10, 0x10(%rax) - movslq %edx, %rax - movslq -0xe0(%rbp), %rcx - cmpq %rcx, %rax - jge jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rcx + movq %rcx, %r11 movl 0x4(%r11), %r10d cmpq $0xb0, %r10 jae @@ -116,10 +106,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movsd (%rax,%riz), %xmm1 + movq %r10, %rcx + movsd (%rcx,%riz), %xmm1 addsd %xmm1, %xmm0 - jmp + leaq 0x1(%rax), %rdx + movslq %edx, %rax + movslq -0xe0(%rbp), %rcx + cmpq %rcx, %rax + jl leaq -0x18(%rbp), %rax addq $0xe0, %rsp popq %rbp @@ -155,25 +149,13 @@ Disassembly of section .text: movq %r10, 0x8(%rax) leaq -0xe0(%rbp), %r10 movq %r10, 0x10(%rax) - movslq %edx, %rax - movslq -0xe0(%rbp), %rcx - cmpq %rcx, %rax - jge jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - movslq %edx, %rax - andq $0x1, %rax - testq %rax, %rax + movq %rax, %rcx + andq $0x1, %rcx + testq %rcx, %rcx je - jmp - leaq -0x18(%rbp), %rax - addq $0xe0, %rsp - popq %rbp - retq - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rcx + movq %rcx, %r11 movl 0x4(%r11), %r10d cmpq $0xb0, %r10 jae @@ -182,12 +164,12 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movsd (%rax,%riz), %xmm1 + movq %r10, %rcx + movsd (%rcx,%riz), %xmm1 addsd %xmm1, %xmm0 jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rcx + movq %rcx, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -196,11 +178,20 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movslq (%rax), %rax - cvtsi2sd %rax, %xmm1 + movq %r10, %rcx + movslq (%rcx), %rcx + cvtsi2sd %rcx, %xmm1 addsd %xmm1, %xmm0 jmp + leaq 0x1(%rax), %rdx + movslq %edx, %rax + movslq -0xe0(%rbp), %rcx + cmpq %rcx, %rax + jl + leaq -0x18(%rbp), %rax + addq $0xe0, %rsp + popq %rbp + retq : pushq %rbp @@ -242,16 +233,9 @@ Disassembly of section .text: movq %rdx, 0x10(%rax) popq %rdx movq %rdx, %rax - movslq %edx, %rcx - movslq -0xf0(%rbp), %rsi - cmpq %rsi, %rcx - jge jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx - jmp - leaq -0x18(%rbp), %rcx - movq %rcx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -260,21 +244,18 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rcx - movslq (%rcx), %rcx - addq %rcx, %rax - jmp - xorq %rdx, %rdx + movq %r10, %rsi + movslq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rcx), %rdx movslq %edx, %rcx movslq -0xf0(%rbp), %rsi cmpq %rsi, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx + jl + xorq %rdx, %rdx jmp - leaq -0x30(%rbp), %rcx - movq %rcx, %r11 + leaq -0x30(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -283,10 +264,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rcx - movslq (%rcx), %rcx - addq %rcx, %rax - jmp + movq %r10, %rsi + movslq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rcx), %rdx + movslq %edx, %rcx + movslq -0xf0(%rbp), %rsi + cmpq %rsi, %rcx + jl leaq -0x30(%rbp), %rcx leaq -0x18(%rbp), %rcx movslq %eax, %rax @@ -389,7 +374,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xb0, %rsp + subq $0x40, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -406,7 +391,7 @@ Disassembly of section .text: callq cmpq $0xf, %rax je - orq $0x1, %rbx + movl $0x1, %ebx movl $0xc, %edi movl $0x1, %esi movl $0x2, %edx @@ -562,7 +547,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xb0, %rsp + addq $0x40, %rsp popq %rbp retq jmp @@ -572,4 +557,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/add_sub_negative_imm.aarch64.asm b/tests/snapshots/asm/add_sub_negative_imm.aarch64.asm index 7c8ae87b8..ec4e3e140 100644 --- a/tests/snapshots/asm/add_sub_negative_imm.aarch64.asm +++ b/tests/snapshots/asm/add_sub_negative_imm.aarch64.asm @@ -93,17 +93,15 @@ Disassembly of section .text: mov x1, #0x0 // =0 mov x0, #0x5 // =5 stur w0, [x29, #-0x20] - ldursw x0, [x29, #-0x20] - cmp x0, #0x0 - b.le b ldursw x0, [x29, #-0x20] + add x1, x1, x0 + ldursw x0, [x29, #-0x20] sub x0, x0, #0x1 stur w0, [x29, #-0x20] - b ldursw x0, [x29, #-0x20] - add x1, x1, x0 - b + cmp x0, #0x0 + b.gt sxtw x0, w1 cmp x0, #0xf b.eq diff --git a/tests/snapshots/asm/add_sub_negative_imm.x64.asm b/tests/snapshots/asm/add_sub_negative_imm.x64.asm index d3ba4d596..53c3b09c2 100644 --- a/tests/snapshots/asm/add_sub_negative_imm.x64.asm +++ b/tests/snapshots/asm/add_sub_negative_imm.x64.asm @@ -82,17 +82,15 @@ Disassembly of section .text: xorq %rcx, %rcx movl $0x5, %eax movl %eax, -0x20(%rbp) - movslq -0x20(%rbp), %rax - testq %rax, %rax - jle jmp movslq -0x20(%rbp), %rax + addq %rax, %rcx + movslq -0x20(%rbp), %rax decq %rax movl %eax, -0x20(%rbp) - jmp movslq -0x20(%rbp), %rax - addq %rax, %rcx - jmp + testq %rax, %rax + jg movslq %ecx, %rax cmpq $0xf, %rax je diff --git a/tests/snapshots/asm/addr_of_intrinsic_math.aarch64.asm b/tests/snapshots/asm/addr_of_intrinsic_math.aarch64.asm index 9c7e1ab0f..c7f179a64 100644 --- a/tests/snapshots/asm/addr_of_intrinsic_math.aarch64.asm +++ b/tests/snapshots/asm/addr_of_intrinsic_math.aarch64.asm @@ -10,15 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0xc0]! + stp x22, x23, [sp, #0x10] str x24, [sp, #0x20] str x19, [sp, #0x30] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 adrp x0, add x0, x0, adrp x20, @@ -32,118 +29,91 @@ Disassembly of section .text: mov x24, #0x400c000000000000 // =4615063718147915776 fmov d16, x24 fneg d0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 fmov d17, x24 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x4030000000000000 // =4625196817309499392 - str x0, [sp, #-0x10]! mov x9, x20 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x999a // =39322 movk x0, #0x9999, lsl #16 movk x0, #0x9999, lsl #32 movk x0, #0x4005, lsl #48 - str x0, [sp, #-0x10]! mov x9, x21 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 mov x0, #0x4000000000000000 // =4611686018427387904 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0xcccd // =52429 movk x0, #0xcccc, lsl #16 movk x0, #0xcccc, lsl #32 movk x0, #0x4000, lsl #48 - str x0, [sp, #-0x10]! mov x9, x22 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 mov x0, #0x4008000000000000 // =4613937818241073152 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x3333 // =13107 movk x0, #0x3333, lsl #16 movk x0, #0x3333, lsl #32 movk x0, #0x4007, lsl #48 - str x0, [sp, #-0x10]! mov x9, x23 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 mov x0, #0x4000000000000000 // =4611686018427387904 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret sub x0, x29, #0x40 adrp x1, @@ -161,49 +131,37 @@ Disassembly of section .text: mov x20, #0x4022000000000000 // =4621256167635550208 fmov d16, x20 fneg d0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 fmov d17, x20 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret sub x0, x29, #0x40 ldr x0, [x0, #0x8] mov x1, #0x400000000000 // =70368744177664 movk x1, #0x4054, lsl #48 - str x1, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 mov x0, #0x4022000000000000 // =4621256167635550208 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret sub x0, x29, #0x40 ldr x0, [x0, #0x10] @@ -211,25 +169,20 @@ Disassembly of section .text: movk x1, #0x9999, lsl #16 movk x1, #0x9999, lsl #32 movk x1, #0x4017, lsl #48 - str x1, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 mov x0, #0x4014000000000000 // =4617315517961601024 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x401c000000000000 // =4619567317775286272 fmov d16, x0 @@ -240,14 +193,11 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x9 // =9 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x800000000000 // =140737488355328 movk x0, #0x4048, lsl #48 @@ -259,24 +209,18 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0xa // =10 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x30] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret <__c5_sys_sqrt>: diff --git a/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm b/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm index aad4e05a0..76e8185f2 100644 --- a/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm +++ b/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm @@ -10,15 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xd0 - str d8, [sp] - str d9, [sp, #0x8] - str x20, [sp, #0x10] - str x21, [sp, #0x18] - str x22, [sp, #0x20] - str x19, [sp, #0x30] + stp x20, x21, [sp, #-0xd0]! + str x22, [sp, #0x10] + str x19, [sp, #0x20] + stp x29, x30, [sp, #0xc0] + add x29, sp, #0xc0 adrp x0, add x0, x0, adrp x20, @@ -27,141 +23,85 @@ Disassembly of section .text: add x21, x21, adrp x22, add x22, x22, - mov x1, #0x4030000000000000 // =4625196817309499392 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x41800000 // =1098907648 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 mov x9, x20 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x4000, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x6666 // =26214 + movk x0, #0x4006, lsl #16 mov x9, x21 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 mov x9, x22 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret adrp x0, add x0, x0, - mov x20, #0x400c000000000000 // =4615063718147915776 - fmov d16, x20 - fneg d0, d16 - fcvt s0, d0 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x20, #0x40600000 // =1080033280 + fmov s16, w20 + fneg s0, s16 mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret sub x0, x29, #0x40 adrp x1, @@ -174,144 +114,104 @@ Disassembly of section .text: ldr x10, [x1, #0x10] str x10, [x0, #0x10] ldr x10, [sp], #0x10 - mov x0, #0x400000000000 // =70368744177664 - movk x0, #0x4054, lsl #48 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4017, lsl #48 - fmov d16, x0 - fcvt s8, d16 + mov x0, #0x42a20000 // =1117913088 + fmov s16, w0 + sub x17, x29, #0x48 + str s16, [x17] mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x4000, lsl #48 - fmov d16, x0 - fcvt s9, d16 + movk x0, #0x40bc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x50 + str s16, [x17] + mov x0, #0x6666 // =26214 + movk x0, #0x4006, lsl #16 + fmov s16, w0 + sub x17, x29, #0x58 + str s16, [x17] sub x0, x29, #0x40 ldr x0, [x0] - fmov x16, d0 - str x16, [sp, #-0x10]! + sub x16, x29, #0x48 + ldr s0, [x16] mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 - mov x0, #0x4022000000000000 // =4621256167635550208 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41100000 // =1091567616 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret sub x0, x29, #0x40 ldr x0, [x0, #0x8] - fmov x16, d8 - str x16, [sp, #-0x10]! + sub x16, x29, #0x50 + ldr s0, [x16] mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret sub x0, x29, #0x40 ldr x0, [x0, #0x10] - fmov x16, d9 - str x16, [sp, #-0x10]! + sub x16, x29, #0x58 + ldr s0, [x16] mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40e00000 // =1088421888 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4048, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x42440000 // =1111752704 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40e00000 // =1088421888 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xa // =10 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xd0 ret <__c5_sys_sqrtf>: diff --git a/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm b/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm index ed602bc38..b79982bd2 100644 --- a/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm +++ b/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xc0, %rsp + subq $0xb0, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -21,14 +21,12 @@ Disassembly of section .text: leaq , %rbx # leaq , %r12 # leaq , %r13 # - movabsq $0x4030000000000000, %rcx # imm = 0x4030000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %edi # imm = 0x41800000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -40,18 +38,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x402ccccd, %edi # imm = 0x402CCCCD movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -63,18 +59,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4000cccccccccccd, %rax # imm = 0x4000CCCCCCCCCCCD - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40066666, %edi # imm = 0x40066666 movq %r12, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -86,18 +80,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x4039999a, %edi # imm = 0x4039999A movq %r13, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,20 +101,18 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq , %rax # - movabsq $0x400c000000000000, %rbx # imm = 0x400C000000000000 + movl $0x40600000, %ebx # imm = 0x40600000 movq %rbx, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 callq *%rax - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -134,7 +124,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax @@ -147,24 +137,22 @@ Disassembly of section .text: movq 0x10(%rcx), %rdx movq %rdx, 0x10(%rax) popq %rdx - movabsq $0x4054400000000000, %rax # imm = 0x4054400000000000 + movl $0x42a20000, %eax # imm = 0x42A20000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x401799999999999a, %rax # imm = 0x401799999999999A + movss %xmm14, -0x48(%rbp,%riz) + movl $0x40bccccd, %eax # imm = 0x40BCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x28(%rsp) - movabsq $0x4000cccccccccccd, %rax # imm = 0x4000CCCCCCCCCCCD + movss %xmm14, -0x50(%rbp,%riz) + movl $0x40066666, %eax # imm = 0x40066666 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x20(%rsp) + movss %xmm14, -0x58(%rbp,%riz) leaq -0x40(%rbp), %rax movq (%rax), %rax + movss -0x48(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4022000000000000, %rax # imm = 0x4022000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41100000, %eax # imm = 0x41100000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -176,17 +164,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax movq 0x8(%rax), %rax - movsd 0x28(%rsp), %xmm0 + movss -0x50(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -198,17 +185,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax movq 0x10(%rax), %rax - movsd 0x20(%rsp), %xmm0 + movss -0x58(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -220,21 +206,19 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -246,17 +230,15 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4048800000000000, %rax # imm = 0x4048800000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x42440000, %eax # imm = 0x42440000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -268,14 +250,14 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq @@ -287,3 +269,4 @@ Disassembly of section .text: <__c5_sys_ceilf>: jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm b/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm index cb1b3934c..60bba8533 100644 --- a/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm +++ b/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm @@ -10,76 +10,53 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, adrp x0, add x0, x0, adrp x1, add x1, x1, - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, adrp x1, add x1, x1, - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.lt mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, adrp x1, add x1, x1, - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.gt mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -92,27 +69,18 @@ Disassembly of section .text: add x0, x0, adrp x1, add x1, x1, - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x21, x0 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm b/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm index c771849c9..309bf34a5 100644 --- a/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm +++ b/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq , %rbx # @@ -27,7 +27,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -40,7 +40,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -53,7 +53,7 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -72,13 +72,13 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/addr_of_libm_import.aarch64.asm b/tests/snapshots/asm/addr_of_libm_import.aarch64.asm index dff444c5b..0ea8cded6 100644 --- a/tests/snapshots/asm/addr_of_libm_import.aarch64.asm +++ b/tests/snapshots/asm/addr_of_libm_import.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x90]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 adrp x0, add x0, x0, adrp x20, @@ -24,63 +22,50 @@ Disassembly of section .text: adrp x21, add x21, x21, mov x22, #0x0 // =0 - str x22, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x22 blr x9 - add sp, sp, #0x10 fmov d17, x22 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret mov x0, #0x0 // =0 - str x0, [sp, #-0x10]! mov x9, x20 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x4024000000000000 // =4621819117588971520 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x21 - ldr d0, [sp] - ldr d1, [sp, #0x10] + fmov d0, x0 + fmov d1, x1 blr x9 - add sp, sp, #0x20 mov x0, #0x4090000000000000 // =4652218415073722368 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret sub x0, x29, #0x28 adrp x1, @@ -94,43 +79,35 @@ Disassembly of section .text: sub x0, x29, #0x28 mov x20, #0x0 // =0 ldr x0, [x0] - str x20, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x20 blr x9 - add sp, sp, #0x10 fmov d17, x20 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret sub x0, x29, #0x28 ldr x0, [x0, #0x8] mov x1, #0x0 // =0 - str x1, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret mov x0, #0x0 // =0 fmov d0, x0 @@ -141,20 +118,16 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret <__c5_sys_sin>: diff --git a/tests/snapshots/asm/adjacent_strings.aarch64.asm b/tests/snapshots/asm/adjacent_strings.aarch64.asm index 87df0b531..4251a03a1 100644 --- a/tests/snapshots/asm/adjacent_strings.aarch64.asm +++ b/tests/snapshots/asm/adjacent_strings.aarch64.asm @@ -10,12 +10,7 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldrb w0, [x0, #0x5] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/adjacent_strings.x64.asm b/tests/snapshots/asm/adjacent_strings.x64.asm index 20941618a..6d70fb491 100644 --- a/tests/snapshots/asm/adjacent_strings.x64.asm +++ b/tests/snapshots/asm/adjacent_strings.x64.asm @@ -11,11 +11,8 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movsbq 0x5(%rax), %rax - addq $0x10, %rsp - popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/alignof_operator.aarch64.asm b/tests/snapshots/asm/alignof_operator.aarch64.asm index 58fa1155e..ad602dd97 100644 --- a/tests/snapshots/asm/alignof_operator.aarch64.asm +++ b/tests/snapshots/asm/alignof_operator.aarch64.asm @@ -17,29 +17,21 @@ Disassembly of section .text: b.eq mov x0, #0x1 // =1 ret - b + mov x0, #0x0 // =0 + ret mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - b mov x0, #0x9 // =9 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/alignof_operator.x64.asm b/tests/snapshots/asm/alignof_operator.x64.asm index 4391419cc..3094a0ddd 100644 --- a/tests/snapshots/asm/alignof_operator.x64.asm +++ b/tests/snapshots/asm/alignof_operator.x64.asm @@ -17,31 +17,23 @@ Disassembly of section .text: je movl $0x1, %eax retq - jmp + xorq %rax, %rax + retq movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - jmp movl $0x9, %eax retq - xorq %rax, %rax - retq addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/alloca_alignment.aarch64.asm b/tests/snapshots/asm/alloca_alignment.aarch64.asm index ca11718ef..fe2615edf 100644 --- a/tests/snapshots/asm/alloca_alignment.aarch64.asm +++ b/tests/snapshots/asm/alloca_alignment.aarch64.asm @@ -171,11 +171,6 @@ Disassembly of section .text: sub x17, x29, #0x2, lsl #12 // =0x2000 sub x17, x17, #0x50 str x0, [x17] - b - mov x0, #0x1 // =1 - sub x17, x29, #0x2, lsl #12 // =0x2000 - sub x17, x17, #0x50 - str x0, [x17] sub x16, x29, #0x2, lsl #12 // =0x2000 sub x16, x16, #0x50 ldr x0, [x16] @@ -184,3 +179,8 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + sub x17, x29, #0x2, lsl #12 // =0x2000 + sub x17, x17, #0x50 + str x0, [x17] + b diff --git a/tests/snapshots/asm/alloca_alignment.x64.asm b/tests/snapshots/asm/alloca_alignment.x64.asm index 7b67088c6..bfebf3e69 100644 --- a/tests/snapshots/asm/alloca_alignment.x64.asm +++ b/tests/snapshots/asm/alloca_alignment.x64.asm @@ -148,11 +148,11 @@ Disassembly of section .text: je xorq %rax, %rax movq %rax, -0x2050(%rbp) - jmp - movl $0x1, %eax - movq %rax, -0x2050(%rbp) movq -0x2050(%rbp), %rax addq $0x2050, %rsp # imm = 0x2050 popq %rbp retq + movl $0x1, %eax + movq %rax, -0x2050(%rbp) + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/alloca_arena_in_bounds.aarch64.asm b/tests/snapshots/asm/alloca_arena_in_bounds.aarch64.asm index afccff1c2..525b53aa6 100644 --- a/tests/snapshots/asm/alloca_arena_in_bounds.aarch64.asm +++ b/tests/snapshots/asm/alloca_arena_in_bounds.aarch64.asm @@ -35,14 +35,6 @@ Disassembly of section .text: mov x0, #0x0 // =0 stur w0, [x29, #-0x10] stur w0, [x29, #-0x18] - ldursw x0, [x29, #-0x18] - mov x17, #0x1f40 // =8000 - cmp x0, x17 - b.ge - b - ldursw x0, [x29, #-0x18] - add x0, x0, #0x1 - stur w0, [x29, #-0x18] b ldursw x0, [x29, #-0x10] ldur x1, [x29, #-0x8] @@ -51,7 +43,13 @@ Disassembly of section .text: ldrb w1, [x1] add x0, x0, x1 stur w0, [x29, #-0x10] - b + ldursw x0, [x29, #-0x18] + add x0, x0, #0x1 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x18] + mov x17, #0x1f40 // =8000 + cmp x0, x17 + b.lt ldursw x0, [x29, #-0x10] mov x17, #0x5dc0 // =24000 cmp x0, x17 @@ -60,11 +58,6 @@ Disassembly of section .text: sub x17, x29, #0x2, lsl #12 // =0x2000 sub x17, x17, #0x30 str x0, [x17] - b - mov x0, #0x1 // =1 - sub x17, x29, #0x2, lsl #12 // =0x2000 - sub x17, x17, #0x30 - str x0, [x17] sub x16, x29, #0x2, lsl #12 // =0x2000 sub x16, x16, #0x30 ldr x0, [x16] @@ -73,3 +66,8 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + sub x17, x29, #0x2, lsl #12 // =0x2000 + sub x17, x17, #0x30 + str x0, [x17] + b diff --git a/tests/snapshots/asm/alloca_arena_in_bounds.x64.asm b/tests/snapshots/asm/alloca_arena_in_bounds.x64.asm index f5bb4ca50..4865f943d 100644 --- a/tests/snapshots/asm/alloca_arena_in_bounds.x64.asm +++ b/tests/snapshots/asm/alloca_arena_in_bounds.x64.asm @@ -36,13 +36,6 @@ Disassembly of section .text: xorq %rax, %rax movl %eax, -0x10(%rbp) movl %eax, -0x18(%rbp) - movslq -0x18(%rbp), %rax - cmpq $0x1f40, %rax # imm = 0x1F40 - jge - jmp - movslq -0x18(%rbp), %rax - incq %rax - movl %eax, -0x18(%rbp) jmp movslq -0x10(%rbp), %rax movq -0x8(%rbp), %rcx @@ -51,17 +44,22 @@ Disassembly of section .text: movzbq (%rcx), %rcx addq %rcx, %rax movl %eax, -0x10(%rbp) - jmp + movslq -0x18(%rbp), %rax + incq %rax + movl %eax, -0x18(%rbp) + movslq -0x18(%rbp), %rax + cmpq $0x1f40, %rax # imm = 0x1F40 + jl movslq -0x10(%rbp), %rax cmpq $0x5dc0, %rax # imm = 0x5DC0 jne xorq %rax, %rax movq %rax, -0x2030(%rbp) - jmp - movl $0x1, %eax - movq %rax, -0x2030(%rbp) movq -0x2030(%rbp), %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp retq + movl $0x1, %eax + movq %rax, -0x2030(%rbp) + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/alloca_basic.aarch64.asm b/tests/snapshots/asm/alloca_basic.aarch64.asm index fd1292ddb..ac3abead4 100644 --- a/tests/snapshots/asm/alloca_basic.aarch64.asm +++ b/tests/snapshots/asm/alloca_basic.aarch64.asm @@ -34,13 +34,6 @@ Disassembly of section .text: bl mov x0, #0x0 // =0 stur w0, [x29, #-0x10] - ldursw x0, [x29, #-0x10] - cmp x0, #0x20 - b.ge - b - ldursw x0, [x29, #-0x10] - add x0, x0, #0x1 - stur w0, [x29, #-0x10] b ldur x0, [x29, #-0x8] ldursw x1, [x29, #-0x10] @@ -50,8 +43,13 @@ Disassembly of section .text: eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - b.eq - b + b.ne + ldursw x0, [x29, #-0x10] + add x0, x0, #0x1 + stur w0, [x29, #-0x10] + ldursw x0, [x29, #-0x10] + cmp x0, #0x20 + b.lt mov x0, #0x0 // =0 ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 @@ -93,14 +91,6 @@ Disassembly of section .text: mov x0, #0x0 // =0 stur w0, [x29, #-0x18] stur w0, [x29, #-0x10] - ldursw x0, [x29, #-0x10] - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x10] - add x0, x0, #0x1 - stur w0, [x29, #-0x10] b ldur x0, [x29, #-0x8] ldursw x1, [x29, #-0x10] @@ -108,16 +98,14 @@ Disassembly of section .text: mul x2, x1, x17 sub x2, x2, #0x3 str w2, [x0, x1, lsl #2] - b - mov x0, #0x0 // =0 + ldursw x0, [x29, #-0x10] + add x0, x0, #0x1 stur w0, [x29, #-0x10] ldursw x0, [x29, #-0x10] ldursw x1, [x29, #0x10] cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x10] - add x0, x0, #0x1 + b.lt + mov x0, #0x0 // =0 stur w0, [x29, #-0x10] b ldursw x0, [x29, #-0x18] @@ -126,7 +114,13 @@ Disassembly of section .text: ldrsw x1, [x1, x2, lsl #2] add x0, x0, x1 stur w0, [x29, #-0x18] - b + ldursw x0, [x29, #-0x10] + add x0, x0, #0x1 + stur w0, [x29, #-0x10] + ldursw x0, [x29, #-0x10] + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt ldursw x0, [x29, #-0x18] ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 @@ -172,8 +166,8 @@ Disassembly of section .text: cmp x0, x1 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 @@ -213,8 +207,8 @@ Disassembly of section .text: ldr x0, [x16] cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 @@ -245,15 +239,15 @@ Disassembly of section .text: ldr x0, [x16] cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 @@ -272,14 +266,6 @@ Disassembly of section .text: mov x0, #0x0 // =0 stur w0, [x29, #-0x8] stur w0, [x29, #-0x10] - ldursw x0, [x29, #-0x10] - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x10] - add x0, x0, #0x1 - stur w0, [x29, #-0x10] b mov x0, #0x8 // =8 add x17, x0, #0xf @@ -301,7 +287,13 @@ Disassembly of section .text: ldr x1, [x1] add x0, x0, x1 stur w0, [x29, #-0x8] - b + ldursw x0, [x29, #-0x10] + add x0, x0, #0x1 + stur w0, [x29, #-0x10] + ldursw x0, [x29, #-0x10] + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt ldursw x0, [x29, #-0x8] ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 @@ -340,13 +332,6 @@ Disassembly of section .text: stur w0, [x29, #-0x10] mov x0, #0x0 // =0 stur w0, [x29, #-0x18] - ldursw x0, [x29, #-0x18] - cmp x0, #0x40 - b.ge - b - ldursw x0, [x29, #-0x18] - add x0, x0, #0x1 - stur w0, [x29, #-0x18] b ldur x0, [x29, #-0x8] ldursw x1, [x29, #-0x18] @@ -356,13 +341,17 @@ Disassembly of section .text: mov x17, #0xff // =255 and x1, x1, x17 cmp x0, x1 - b.eq - b + b.ne + ldursw x0, [x29, #-0x18] + add x0, x0, #0x1 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x18] + cmp x0, #0x40 + b.lt ldursw x0, [x29, #-0x10] cmp x0, #0xbe b.eq - b - mov x0, #0xffff // =65535 + mov x0, #0xfffe // =65534 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 @@ -372,31 +361,30 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret - b - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 + mov x0, #0x0 // =0 ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret + b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 bl cmp x0, #0x0 b.eq @@ -405,10 +393,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0xa // =10 bl @@ -423,10 +410,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl cmp x0, #0x0 @@ -436,10 +422,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x32 // =50 bl @@ -454,10 +439,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x33 // =51 bl @@ -468,14 +452,12 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/alloca_basic.x64.asm b/tests/snapshots/asm/alloca_basic.x64.asm index 216f1c37a..f14c82c12 100644 --- a/tests/snapshots/asm/alloca_basic.x64.asm +++ b/tests/snapshots/asm/alloca_basic.x64.asm @@ -35,21 +35,19 @@ Disassembly of section .text: callq xorq %rax, %rax movl %eax, -0x10(%rbp) - movslq -0x10(%rbp), %rax - cmpq $0x20, %rax - jge - jmp - movslq -0x10(%rbp), %rax - incq %rax - movl %eax, -0x10(%rbp) jmp movq -0x8(%rbp), %rax movslq -0x10(%rbp), %rcx addq %rcx, %rax movsbq (%rax), %rax cmpq $0x55, %rax - je - jmp + jne + movslq -0x10(%rbp), %rax + incq %rax + movl %eax, -0x10(%rbp) + movslq -0x10(%rbp), %rax + cmpq $0x20, %rax + jl xorq %rax, %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp @@ -89,30 +87,20 @@ Disassembly of section .text: xorq %rax, %rax movl %eax, -0x18(%rbp) movl %eax, -0x10(%rbp) - movslq -0x10(%rbp), %rax - movslq 0x10(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq -0x10(%rbp), %rax - incq %rax - movl %eax, -0x10(%rbp) jmp movq -0x8(%rbp), %rax movslq -0x10(%rbp), %rcx imulq $0x7, %rcx, %rdx subq $0x3, %rdx movl %edx, (%rax,%rcx,4) - jmp - xorq %rax, %rax + movslq -0x10(%rbp), %rax + incq %rax movl %eax, -0x10(%rbp) movslq -0x10(%rbp), %rax movslq 0x10(%rbp), %rcx cmpq %rcx, %rax - jge - jmp - movslq -0x10(%rbp), %rax - incq %rax + jl + xorq %rax, %rax movl %eax, -0x10(%rbp) jmp movslq -0x18(%rbp), %rax @@ -121,7 +109,13 @@ Disassembly of section .text: movslq (%rcx,%rdx,4), %rcx addq %rcx, %rax movl %eax, -0x18(%rbp) - jmp + movslq -0x10(%rbp), %rax + incq %rax + movl %eax, -0x10(%rbp) + movslq -0x10(%rbp), %rax + movslq 0x10(%rbp), %rcx + cmpq %rcx, %rax + jl movslq -0x18(%rbp), %rax addq $0x2020, %rsp # imm = 0x2020 popq %rbp @@ -246,14 +240,6 @@ Disassembly of section .text: xorq %rax, %rax movl %eax, -0x8(%rbp) movl %eax, -0x10(%rbp) - movslq -0x10(%rbp), %rax - movslq 0x10(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq -0x10(%rbp), %rax - incq %rax - movl %eax, -0x10(%rbp) jmp movl $0x8, %eax movq %rax, %r10 @@ -276,7 +262,13 @@ Disassembly of section .text: movq (%rcx), %rcx addq %rcx, %rax movl %eax, -0x8(%rbp) - jmp + movslq -0x10(%rbp), %rax + incq %rax + movl %eax, -0x10(%rbp) + movslq -0x10(%rbp), %rax + movslq 0x10(%rbp), %rcx + cmpq %rcx, %rax + jl movslq -0x8(%rbp), %rax addq $0x2020, %rsp # imm = 0x2020 popq %rbp @@ -318,13 +310,6 @@ Disassembly of section .text: movl %eax, -0x10(%rbp) xorq %rax, %rax movl %eax, -0x18(%rbp) - movslq -0x18(%rbp), %rax - cmpq $0x40, %rax - jge - jmp - movslq -0x18(%rbp), %rax - incq %rax - movl %eax, -0x18(%rbp) jmp movq -0x8(%rbp), %rax movslq -0x18(%rbp), %rcx @@ -333,34 +318,38 @@ Disassembly of section .text: movslq 0x10(%rbp), %rcx movsbq %cl, %rcx cmpq %rcx, %rax - je - jmp + jne + movslq -0x18(%rbp), %rax + incq %rax + movl %eax, -0x18(%rbp) + movslq -0x18(%rbp), %rax + cmpq $0x40, %rax + jl movslq -0x10(%rbp), %rax cmpq $0xbe, %rax je - jmp - movabsq $-0x1, %rax + movabsq $-0x2, %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq - jmp - movabsq $-0x2, %rax + xorq %rax, %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq - xorq %rax, %rax + movabsq $-0x1, %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq + jmp
: pushq %rbp @@ -443,3 +432,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/anon_union_braced_init.aarch64.asm b/tests/snapshots/asm/anon_union_braced_init.aarch64.asm index 926d85829..d54740d28 100644 --- a/tests/snapshots/asm/anon_union_braced_init.aarch64.asm +++ b/tests/snapshots/asm/anon_union_braced_init.aarch64.asm @@ -47,19 +47,18 @@ Disassembly of section .text: cset x2, eq cbz x2, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] + str x20, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 mov x0, #0x7 // =7 adrp x20, add x20, x20, @@ -67,9 +66,8 @@ Disassembly of section .text: bl cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret sub x0, x29, #0x20 adrp x1, @@ -109,9 +107,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret sub x0, x29, #0x30 adrp x1, @@ -133,9 +130,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret sub x0, x29, #0x50 adrp x1, @@ -166,14 +162,12 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret b b diff --git a/tests/snapshots/asm/anon_union_braced_init.x64.asm b/tests/snapshots/asm/anon_union_braced_init.x64.asm index 77829ef1b..de402fe1f 100644 --- a/tests/snapshots/asm/anon_union_braced_init.x64.asm +++ b/tests/snapshots/asm/anon_union_braced_init.x64.asm @@ -51,12 +51,12 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp
: diff --git a/tests/snapshots/asm/anon_union_init.aarch64.asm b/tests/snapshots/asm/anon_union_init.aarch64.asm index c6c30f7ae..7eebe97a9 100644 --- a/tests/snapshots/asm/anon_union_init.aarch64.asm +++ b/tests/snapshots/asm/anon_union_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 adrp x0, add x0, x0, ldrsw x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x3 @@ -36,8 +31,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0xc] cmp x1, #0x4 @@ -48,8 +41,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -82,12 +73,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/anon_union_init.x64.asm b/tests/snapshots/asm/anon_union_init.x64.asm index cd9fba5f5..108c5f71b 100644 --- a/tests/snapshots/asm/anon_union_init.x64.asm +++ b/tests/snapshots/asm/anon_union_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x1, %rcx @@ -28,8 +25,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx cmpq $0x3, %rcx @@ -44,8 +39,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0xc(%rax), %rcx cmpq $0x4, %rcx @@ -60,8 +53,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -100,12 +91,8 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp @@ -114,4 +101,3 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/anonymous_aggregates.aarch64.asm b/tests/snapshots/asm/anonymous_aggregates.aarch64.asm index 28e97cff9..fc51d6368 100644 --- a/tests/snapshots/asm/anonymous_aggregates.aarch64.asm +++ b/tests/snapshots/asm/anonymous_aggregates.aarch64.asm @@ -13,11 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x60 - b - mov x0, #0x1 // =1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 mov x1, #0xcdef // =52719 movk x1, #0x90ab, lsl #16 @@ -160,11 +155,6 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x14 // =20 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x30 mov x1, #0xa // =10 str w1, [x0] @@ -255,12 +245,12 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1234 // =4660 - movk x0, #0x5678, lsl #16 - sub x1, x29, #0x40 - ldrsw x1, [x1, #0x4] - mov w1, w1 - cmp x1, x0 + sub x0, x29, #0x40 + ldrsw x0, [x0, #0x4] + mov w0, w0 + mov x17, #0x1234 // =4660 + movk x17, #0x5678, lsl #16 + cmp x0, x17 b.eq mov x0, #0x22 // =34 add sp, sp, #0x60 @@ -358,3 +348,11 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x14 // =20 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/anonymous_aggregates.x64.asm b/tests/snapshots/asm/anonymous_aggregates.x64.asm index 83b4498a3..8331c29b8 100644 --- a/tests/snapshots/asm/anonymous_aggregates.x64.asm +++ b/tests/snapshots/asm/anonymous_aggregates.x64.asm @@ -14,11 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x60, %rsp - jmp - movl $0x1, %eax - addq $0x60, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax movabsq $0x1234567890abcdef, %rcx # imm = 0x1234567890ABCDEF movq %rcx, (%rax) @@ -141,11 +136,6 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - jmp - movl $0x14, %eax - addq $0x60, %rsp - popq %rbp - retq leaq -0x30(%rbp), %rax movl $0xa, %ecx movl %ecx, (%rax) @@ -234,11 +224,10 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x56781234, %eax # imm = 0x56781234 - leaq -0x40(%rbp), %rcx - movslq 0x4(%rcx), %rcx - movl %ecx, %ecx - cmpq %rax, %rcx + leaq -0x40(%rbp), %rax + movslq 0x4(%rax), %rax + movl %eax, %eax + cmpq $0x56781234, %rax # imm = 0x56781234 je movl $0x22, %eax addq $0x60, %rsp @@ -315,4 +304,13 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x14, %eax + addq $0x60, %rsp + popq %rbp + retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/arg_register_cycle.aarch64.asm b/tests/snapshots/asm/arg_register_cycle.aarch64.asm index 0b824de3b..3d4ca2f43 100644 --- a/tests/snapshots/asm/arg_register_cycle.aarch64.asm +++ b/tests/snapshots/asm/arg_register_cycle.aarch64.asm @@ -22,7 +22,6 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x2, x2, #0x1 - sxtw x2, w2 mov x16, x1 mov x1, x0 mov x0, x16 diff --git a/tests/snapshots/asm/arg_register_cycle.x64.asm b/tests/snapshots/asm/arg_register_cycle.x64.asm index 962ca4549..d0b297bfb 100644 --- a/tests/snapshots/asm/arg_register_cycle.x64.asm +++ b/tests/snapshots/asm/arg_register_cycle.x64.asm @@ -23,8 +23,7 @@ Disassembly of section .text: movslq %eax, %rax popq %rbp retq - leaq -0x1(%rdx), %rax - movslq %eax, %rdx + decq %rdx xchgq %rsi, %rdi popq %rbp jmp diff --git a/tests/snapshots/asm/array_2d_struct_init.aarch64.asm b/tests/snapshots/asm/array_2d_struct_init.aarch64.asm index 015cb4dde..0a3a26061 100644 --- a/tests/snapshots/asm/array_2d_struct_init.aarch64.asm +++ b/tests/snapshots/asm/array_2d_struct_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldr d0, [x0] @@ -45,8 +42,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -75,8 +70,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -106,12 +99,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_2d_struct_init.x64.asm b/tests/snapshots/asm/array_2d_struct_init.x64.asm index 8f6592cee..cd4e915ca 100644 --- a/tests/snapshots/asm/array_2d_struct_init.x64.asm +++ b/tests/snapshots/asm/array_2d_struct_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movsd (%rax,%riz), %xmm0 movl $0x1, %esi @@ -67,8 +64,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -110,8 +105,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -154,12 +147,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -168,4 +157,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm b/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm index f88acfae7..fc71ab228 100644 --- a/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm +++ b/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr x1, [x0] @@ -20,8 +17,6 @@ Disassembly of section .text: cmp x1, #0x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0] ldr x1, [x1] @@ -32,16 +27,12 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x8] cmp x1, #0x2aa b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1] @@ -62,16 +53,12 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x18] cmp x1, #0x28b b.eq mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1, #0x10] @@ -82,8 +69,6 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x28] @@ -94,24 +79,18 @@ Disassembly of section .text: cmp x1, x17 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1, #0x20] cmp x1, #0x0 b.eq mov x0, #0x8 // =8 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x10] ldrsw x1, [x1, #0x8] cmp x1, #0x7 b.eq mov x0, #0x9 // =9 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x10] ldrsw x1, [x1, #0x18] @@ -124,20 +103,14 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0xa // =10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x0, [x0, #0x10] ldrsw x0, [x0, #0x28] cmp x0, #0x0 b.eq mov x0, #0xb // =11 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_compound_literal_static_init.x64.asm b/tests/snapshots/asm/array_compound_literal_static_init.x64.asm index 60455cade..69ab257a1 100644 --- a/tests/snapshots/asm/array_compound_literal_static_init.x64.asm +++ b/tests/snapshots/asm/array_compound_literal_static_init.x64.asm @@ -11,17 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movq (%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movq (%rax), %rcx movq (%rcx), %rcx @@ -29,16 +24,12 @@ Disassembly of section .text: cmpq $0x61, %rcx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x2aa, %rcx # imm = 0x2AA je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq (%rcx), %rcx @@ -57,16 +48,12 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x18(%rcx), %rcx cmpq $0x28b, %rcx # imm = 0x28B je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq 0x10(%rcx), %rcx @@ -74,32 +61,24 @@ Disassembly of section .text: cmpq $0x6e, %rcx je movl $0x6, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x28(%rcx), %rcx cmpq $-0x1, %rcx je movl $0x7, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq 0x20(%rcx), %rcx testq %rcx, %rcx je movl $0x8, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x7, %rcx je movl $0x9, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rcx movslq 0x18(%rcx), %rcx @@ -116,22 +95,15 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0xa, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rax movslq 0x28(%rax), %rax testq %rax, %rax je movl $0xb, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_initializers.aarch64.asm b/tests/snapshots/asm/array_initializers.aarch64.asm index 0fb037794..6e9f2aad2 100644 --- a/tests/snapshots/asm/array_initializers.aarch64.asm +++ b/tests/snapshots/asm/array_initializers.aarch64.asm @@ -98,11 +98,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x1, [x0] @@ -121,11 +116,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrb w0, [x0] @@ -168,11 +158,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xb // =11 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x0, [x0] @@ -278,11 +263,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x16 // =22 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x18 ldrsw x0, [x0] sub x1, x29, #0x18 @@ -298,11 +278,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x18 // =24 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x20 ldrb w0, [x0] mov x17, #0x6f // =111 @@ -385,3 +360,23 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x4 // =4 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x16 // =22 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x18 // =24 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/array_initializers.x64.asm b/tests/snapshots/asm/array_initializers.x64.asm index 9bc388b57..9801c1158 100644 --- a/tests/snapshots/asm/array_initializers.x64.asm +++ b/tests/snapshots/asm/array_initializers.x64.asm @@ -88,11 +88,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - jmp - movl $0x4, %eax - addq $0x40, %rsp - popq %rbp - retq leaq , %rax movslq (%rax), %rcx movslq 0x4(%rax), %rdx @@ -110,11 +105,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - jmp - movl $0x6, %eax - addq $0x40, %rsp - popq %rbp - retq leaq , %rax movsbq (%rax), %rax cmpq $0x68, %rax @@ -147,11 +137,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - jmp - movl $0xb, %eax - addq $0x40, %rsp - popq %rbp - retq leaq , %rax movslq (%rax), %rax cmpq $0x1, %rax @@ -235,11 +220,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - jmp - movl $0x16, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax movslq (%rax), %rax leaq -0x18(%rbp), %rcx @@ -255,11 +235,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - jmp - movl $0x18, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x20(%rbp), %rax movsbq (%rax), %rax cmpq $0x6f, %rax @@ -336,4 +311,25 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq + movl $0x4, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0xb, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x16, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x18, %eax + addq $0x40, %rsp + popq %rbp + retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm b/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm index 73c59c3fe..26ba82fc4 100644 --- a/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm +++ b/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldr x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -58,8 +53,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -92,12 +85,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm b/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm index 97bad7a6a..ee0e0b1bf 100644 --- a/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm +++ b/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movq (%rax), %rcx cmpq $0x1, %rcx @@ -28,8 +25,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -68,8 +63,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -108,12 +101,8 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -122,4 +111,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_range_designator.aarch64.asm b/tests/snapshots/asm/array_range_designator.aarch64.asm index fbd50faaf..1c058b9f8 100644 --- a/tests/snapshots/asm/array_range_designator.aarch64.asm +++ b/tests/snapshots/asm/array_range_designator.aarch64.asm @@ -10,31 +10,22 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 adrp x0, add x0, x0, ldrsw x1, [x0] cmp x1, #0x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x4] cmp x1, #0x2 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x10] cmp x1, #0x7 @@ -45,8 +36,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0xc] cmp x1, #0x0 @@ -57,8 +46,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x30] cmp x1, #0x9 @@ -69,12 +56,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b @@ -84,9 +67,15 @@ Disassembly of section .text: str x0, [sp, #-0x10]! stp x29, x30, [sp, #-0x10]! mov x29, sp + sub sp, sp, #0x10 stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x40] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x8] + b adr x1, str x1, [x0] adr x1, @@ -103,18 +92,24 @@ Disassembly of section .text: str x1, [x0, #0x30] adr x1, str x1, [x0, #0x38] + mov x1, #0x1 // =1 + strb w1, [x0, #0x40] + stur x1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] br x0 mov x0, #0x64 // =100 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret mov x0, #0xc8 // =200 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret mov x0, #0x3e7 // =999 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret diff --git a/tests/snapshots/asm/array_range_designator.x64.asm b/tests/snapshots/asm/array_range_designator.x64.asm index f65c82e32..3d3ca38f7 100644 --- a/tests/snapshots/asm/array_range_designator.x64.asm +++ b/tests/snapshots/asm/array_range_designator.x64.asm @@ -11,30 +11,21 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x4(%rax), %rcx cmpq $0x2, %rcx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx testq %rcx, %rcx je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x10(%rax), %rcx cmpq $0x7, %rcx @@ -49,8 +40,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0xc(%rax), %rcx testq %rcx, %rcx @@ -65,8 +54,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x30(%rax), %rcx cmpq $0x9, %rcx @@ -81,12 +68,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp @@ -99,8 +82,15 @@ Disassembly of section .text: pushq %r10 pushq %rbp movq %rsp, %rbp + subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x40(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x8(%rbp) + jmp leaq , %rcx # movq %rcx, (%rax) leaq , %rcx # @@ -117,22 +107,28 @@ Disassembly of section .text: movq %rcx, 0x30(%rax) leaq , %rcx # movq %rcx, 0x38(%rax) + movl $0x1, %ecx + movb %cl, 0x40(%rax) + movq %rcx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movl $0x64, %eax + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq movl $0xc8, %eax + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq movl $0x3e7, %eax # imm = 0x3E7 + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp @@ -187,3 +183,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/array_typedef_dimensions_propagate.aarch64.asm b/tests/snapshots/asm/array_typedef_dimensions_propagate.aarch64.asm index 4bafda373..240518d90 100644 --- a/tests/snapshots/asm/array_typedef_dimensions_propagate.aarch64.asm +++ b/tests/snapshots/asm/array_typedef_dimensions_propagate.aarch64.asm @@ -10,17 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/array_typedef_dimensions_propagate.x64.asm b/tests/snapshots/asm/array_typedef_dimensions_propagate.x64.asm index 107080586..2821b2e1e 100644 --- a/tests/snapshots/asm/array_typedef_dimensions_propagate.x64.asm +++ b/tests/snapshots/asm/array_typedef_dimensions_propagate.x64.asm @@ -11,17 +11,13 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/arrays_basic.aarch64.asm b/tests/snapshots/asm/arrays_basic.aarch64.asm index 9d5604e95..353c7657e 100644 --- a/tests/snapshots/asm/arrays_basic.aarch64.asm +++ b/tests/snapshots/asm/arrays_basic.aarch64.asm @@ -13,15 +13,14 @@ Disassembly of section .text: sxtw x1, w1 mov x3, #0x0 // =0 mov x2, x3 + b + ldrsw x3, [x0, x4, lsl #2] + add x2, x2, x3 + add x3, x4, #0x1 + sxtw x3, w3 sxtw x4, w3 cmp x4, x1 - b.ge - sxtw x3, w3 - ldrsw x4, [x0, x3, lsl #2] - add x2, x2, x4 - add x3, x3, #0x1 - sxtw x3, w3 - b + b.lt sxtw x0, w2 ret @@ -29,17 +28,22 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x80 - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x5 - b.ge sub x0, x29, #0x18 - sxtw x2, w1 - add x3, x2, #0x1 - str w3, [x0, x2, lsl #2] - add x0, x1, #0x1 - sxtw x1, w0 - b + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str w1, [x0] + sub x0, x29, #0x18 + mov x1, #0x2 // =2 + str w1, [x0, #0x4] + sub x0, x29, #0x18 + mov x1, #0x3 // =3 + str w1, [x0, #0x8] + sub x0, x29, #0x18 + mov x1, #0x4 // =4 + str w1, [x0, #0xc] + sub x0, x29, #0x18 + mov x1, #0x5 // =5 + str w1, [x0, #0x10] sub x0, x29, #0x18 mov x1, #0x5 // =5 bl @@ -49,24 +53,27 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret + adrp x0, + add x0, x0, + add x0, x0, #0x0 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x5 - b.ge + str w1, [x0] adrp x0, add x0, x0, - sxtw x2, w1 - mov x17, #0xa // =10 - mul x3, x2, x17 - str w3, [x0, x2, lsl #2] - add x0, x1, #0x1 - sxtw x1, w0 - b + mov x1, #0xa // =10 + str w1, [x0, #0x4] + adrp x0, + add x0, x0, + mov x1, #0x14 // =20 + str w1, [x0, #0x8] + adrp x0, + add x0, x0, + mov x1, #0x1e // =30 + str w1, [x0, #0xc] + adrp x0, + add x0, x0, + mov x1, #0x28 // =40 + str w1, [x0, #0x10] adrp x0, add x0, x0, ldrsw x1, [x0] @@ -85,16 +92,6 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, mov x1, #0x0 // =0 @@ -134,25 +131,28 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x3 - b.ge sub x0, x29, #0x40 - sxtw x2, w1 - lsl x2, x2, #3 - add x0, x0, x2 + mov x1, #0x0 // =0 + add x0, x0, #0x0 str w1, [x0] sub x0, x29, #0x40 - sxtw x2, w1 - lsl x3, x2, #3 - add x0, x0, x3 - mov x17, #0x64 // =100 - mul x2, x2, x17 - str w2, [x0, #0x4] - add x0, x1, #0x1 - sxtw x1, w0 - b + add x0, x0, #0x0 + mov x1, #0x0 // =0 + str w1, [x0, #0x4] + sub x0, x29, #0x40 + mov x1, #0x1 // =1 + str w1, [x0, #0x8] + sub x0, x29, #0x40 + add x0, x0, #0x8 + mov x1, #0x64 // =100 + str w1, [x0, #0x4] + sub x0, x29, #0x40 + mov x1, #0x2 // =2 + str w1, [x0, #0x10] + sub x0, x29, #0x40 + add x0, x0, #0x10 + mov x1, #0xc8 // =200 + str w1, [x0, #0x4] sub x0, x29, #0x40 ldrsw x0, [x0] cmp x0, #0x0 @@ -177,32 +177,91 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xc // =12 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x68 mov x1, #0x0 // =0 str w1, [x0, #0x20] - sxtw x0, w1 - cmp x0, #0x8 - b.ge sub x0, x29, #0x68 - sxtw x2, w1 - add x3, x2, #0x1 - str w3, [x0, x2, lsl #2] + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str w1, [x0] sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] sub x2, x29, #0x68 - ldrsw x2, [x2, #0x20] - sub x3, x29, #0x68 - sxtw x4, w1 - ldrsw x3, [x3, x4, lsl #2] - add x2, x2, x3 - str w2, [x0, #0x20] - add x0, x1, #0x1 - sxtw x1, w0 - b + add x2, x2, #0x0 + ldrsw x2, [x2] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x2 // =2 + str w1, [x0, #0x4] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x4] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x3 // =3 + str w1, [x0, #0x8] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x8] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x4 // =4 + str w1, [x0, #0xc] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0xc] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x5 // =5 + str w1, [x0, #0x10] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x10] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x6 // =6 + str w1, [x0, #0x14] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x14] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x7 // =7 + str w1, [x0, #0x18] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x18] + add x1, x1, x2 + str w1, [x0, #0x20] + sub x0, x29, #0x68 + mov x1, #0x8 // =8 + str w1, [x0, #0x1c] + sub x0, x29, #0x68 + sub x1, x29, #0x68 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x68 + ldrsw x2, [x2, #0x1c] + add x1, x1, x2 + str w1, [x0, #0x20] sub x0, x29, #0x68 ldrsw x0, [x0, #0x20] cmp x0, #0x24 @@ -211,18 +270,31 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x8 - b.ge sub x0, x29, #0x70 - sxtw x2, w1 - add x0, x0, x2 - add x2, x2, #0x41 - strb w2, [x0] - add x0, x1, #0x1 - sxtw x1, w0 - b + add x0, x0, #0x0 + mov x1, #0x41 // =65 + strb w1, [x0] + sub x0, x29, #0x70 + mov x1, #0x42 // =66 + strb w1, [x0, #0x1] + sub x0, x29, #0x70 + mov x1, #0x43 // =67 + strb w1, [x0, #0x2] + sub x0, x29, #0x70 + mov x1, #0x44 // =68 + strb w1, [x0, #0x3] + sub x0, x29, #0x70 + mov x1, #0x45 // =69 + strb w1, [x0, #0x4] + sub x0, x29, #0x70 + mov x1, #0x46 // =70 + strb w1, [x0, #0x5] + sub x0, x29, #0x70 + mov x1, #0x47 // =71 + strb w1, [x0, #0x6] + sub x0, x29, #0x70 + mov x1, #0x48 // =72 + strb w1, [x0, #0x7] sub x0, x29, #0x70 ldrb w0, [x0] mov x17, #0x41 // =65 @@ -263,3 +335,19 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x2 // =2 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/arrays_basic.x64.asm b/tests/snapshots/asm/arrays_basic.x64.asm index aff639261..4bfe6fed0 100644 --- a/tests/snapshots/asm/arrays_basic.x64.asm +++ b/tests/snapshots/asm/arrays_basic.x64.asm @@ -14,15 +14,14 @@ Disassembly of section .text: movslq %esi, %rsi xorq %rcx, %rcx movq %rcx, %rax + jmp + movslq (%rdi,%rdx,4), %rcx + addq %rcx, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rcx movslq %ecx, %rdx cmpq %rsi, %rdx - jge - movslq %ecx, %rcx - movslq (%rdi,%rcx,4), %rdx - addq %rdx, %rax - incq %rcx - movslq %ecx, %rcx - jmp + jl movslq %eax, %rax retq @@ -30,17 +29,22 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x80, %rsp - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x5, %rax - jge leaq -0x18(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movl %esi, (%rax,%rdx,4) - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp + addq $0x0, %rax + movl $0x1, %ecx + movl %ecx, (%rax) + leaq -0x18(%rbp), %rax + movl $0x2, %ecx + movl %ecx, 0x4(%rax) + leaq -0x18(%rbp), %rax + movl $0x3, %ecx + movl %ecx, 0x8(%rax) + leaq -0x18(%rbp), %rax + movl $0x4, %ecx + movl %ecx, 0xc(%rax) + leaq -0x18(%rbp), %rax + movl $0x5, %ecx + movl %ecx, 0x10(%rax) leaq -0x18(%rbp), %rdi movl $0x5, %esi callq @@ -50,22 +54,22 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - jmp - movl $0x2, %eax - addq $0x80, %rsp - popq %rbp - retq + leaq , %rax + addq $0x0, %rax xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x5, %rax - jge + movl %ecx, (%rax) leaq , %rax - movslq %ecx, %rdx - imulq $0xa, %rdx, %rsi - movl %esi, (%rax,%rdx,4) - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp + movl $0xa, %ecx + movl %ecx, 0x4(%rax) + leaq , %rax + movl $0x14, %ecx + movl %ecx, 0x8(%rax) + leaq , %rax + movl $0x1e, %ecx + movl %ecx, 0xc(%rax) + leaq , %rax + movl $0x28, %ecx + movl %ecx, 0x10(%rax) leaq , %rax movslq (%rax), %rcx movslq 0x4(%rax), %rdx @@ -83,16 +87,6 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - jmp - movl $0x4, %eax - addq $0x80, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x80, %rsp - popq %rbp - retq leaq , %rax xorq %rcx, %rcx movl $0x68, %edx @@ -123,25 +117,28 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x3, %rax - jge leaq -0x40(%rbp), %rax - movslq %ecx, %rdx - shlq $0x3, %rdx - addq %rdx, %rax + xorq %rcx, %rcx + addq $0x0, %rax movl %ecx, (%rax) leaq -0x40(%rbp), %rax - movslq %ecx, %rdx - movq %rdx, %rsi - shlq $0x3, %rsi - addq %rsi, %rax - imulq $0x64, %rdx, %rdx - movl %edx, 0x4(%rax) - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp + addq $0x0, %rax + xorq %rcx, %rcx + movl %ecx, 0x4(%rax) + leaq -0x40(%rbp), %rax + movl $0x1, %ecx + movl %ecx, 0x8(%rax) + leaq -0x40(%rbp), %rax + addq $0x8, %rax + movl $0x64, %ecx + movl %ecx, 0x4(%rax) + leaq -0x40(%rbp), %rax + movl $0x2, %ecx + movl %ecx, 0x10(%rax) + leaq -0x40(%rbp), %rax + addq $0x10, %rax + movl $0xc8, %ecx + movl %ecx, 0x4(%rax) leaq -0x40(%rbp), %rax movslq (%rax), %rax testq %rax, %rax @@ -166,32 +163,91 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - jmp - movl $0xc, %eax - addq $0x80, %rsp - popq %rbp - retq leaq -0x68(%rbp), %rax xorq %rcx, %rcx movl %ecx, 0x20(%rax) - movslq %ecx, %rax - cmpq $0x8, %rax - jge leaq -0x68(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movl %esi, (%rax,%rdx,4) + addq $0x0, %rax + movl $0x1, %ecx + movl %ecx, (%rax) leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx leaq -0x68(%rbp), %rdx - movslq 0x20(%rdx), %rdx - leaq -0x68(%rbp), %rsi - movslq %ecx, %rdi - movslq (%rsi,%rdi,4), %rsi - addq %rsi, %rdx - movl %edx, 0x20(%rax) - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp + addq $0x0, %rdx + movslq (%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x2, %ecx + movl %ecx, 0x4(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x4(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x3, %ecx + movl %ecx, 0x8(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x8(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x4, %ecx + movl %ecx, 0xc(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0xc(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x5, %ecx + movl %ecx, 0x10(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x10(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x6, %ecx + movl %ecx, 0x14(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x14(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x7, %ecx + movl %ecx, 0x18(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x18(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) + leaq -0x68(%rbp), %rax + movl $0x8, %ecx + movl %ecx, 0x1c(%rax) + leaq -0x68(%rbp), %rax + leaq -0x68(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x68(%rbp), %rdx + movslq 0x1c(%rdx), %rdx + addq %rdx, %rcx + movl %ecx, 0x20(%rax) leaq -0x68(%rbp), %rax movslq 0x20(%rax), %rax cmpq $0x24, %rax @@ -200,18 +256,31 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge leaq -0x70(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - addq $0x41, %rdx - movb %dl, (%rax) - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp + addq $0x0, %rax + movl $0x41, %ecx + movb %cl, (%rax) + leaq -0x70(%rbp), %rax + movl $0x42, %ecx + movb %cl, 0x1(%rax) + leaq -0x70(%rbp), %rax + movl $0x43, %ecx + movb %cl, 0x2(%rax) + leaq -0x70(%rbp), %rax + movl $0x44, %ecx + movb %cl, 0x3(%rax) + leaq -0x70(%rbp), %rax + movl $0x45, %ecx + movb %cl, 0x4(%rax) + leaq -0x70(%rbp), %rax + movl $0x46, %ecx + movb %cl, 0x5(%rax) + leaq -0x70(%rbp), %rax + movl $0x47, %ecx + movb %cl, 0x6(%rax) + leaq -0x70(%rbp), %rax + movl $0x48, %ecx + movb %cl, 0x7(%rax) leaq -0x70(%rbp), %rax movsbq (%rax), %rax cmpq $0x41, %rax @@ -246,4 +315,21 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq + movl $0x2, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xc, %eax + addq $0x80, %rsp + popq %rbp + retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm b/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm index cdaf0b437..f02995716 100644 --- a/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm +++ b/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm @@ -10,51 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0x3 // =3 - cmp x0, #0x3 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xabcd // =43981 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov w0, w0 - mov x17, #0xabcd // =43981 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfd // =253 - cmp x0, #0xfd - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7788 // =30600 - movk x0, #0x5566, lsl #16 - movk x0, #0x3344, lsl #32 - movk x0, #0x1122, lsl #48 - sxth x0, w0 - mov x17, #0xff // =255 - and x0, x0, x17 - mov w0, w0 - cmp x0, #0x88 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm b/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm index f80411e61..88108b579 100644 --- a/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm +++ b/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm @@ -11,44 +11,13 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0x3, %eax - cmpq $0x3, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x5433, %rax # imm = 0xABCD - movl %eax, %eax - movl $0xffffabcd, %r11d # imm = 0xFFFFABCD - cmpq %r11, %rax - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0xfd, %eax - cmpq $0xfd, %rax - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $0x1122334455667788, %rax # imm = 0x1122334455667788 - movswq %ax, %rax - andq $0xff, %rax - movl %eax, %eax - cmpq $0x88, %rax - je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/atoi_negative.aarch64.asm b/tests/snapshots/asm/atoi_negative.aarch64.asm index edbcac021..61f94053f 100644 --- a/tests/snapshots/asm/atoi_negative.aarch64.asm +++ b/tests/snapshots/asm/atoi_negative.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, bl @@ -22,9 +21,8 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -38,9 +36,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -50,12 +47,10 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm b/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm index c1ab8d686..f004aaddd 100644 --- a/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm +++ b/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm @@ -92,7 +92,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x50 mov x0, #0x1 // =1 mov x1, #0x2 // =2 mov x2, #0x3 // =3 @@ -105,9 +104,8 @@ Disassembly of section .text: cmp x0, #0x24 b.ne mov x1, #0x0 // =0 - b - sxtw x1, w0 mov x0, x1 - add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret + sxtw x1, w0 + b diff --git a/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm b/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm index 2c8e49c7d..d95a1cad5 100644 --- a/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm +++ b/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm @@ -129,7 +129,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x1, %edi movl $0x2, %esi @@ -147,12 +147,12 @@ Disassembly of section .text: cmpq $0x24, %rax jne xorq %rcx, %rcx - jmp - movslq %eax, %rcx movq (%rsp), %rbx movq %rcx, %rax - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq + movslq %eax, %rcx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/attribute_c23.aarch64.asm b/tests/snapshots/asm/attribute_c23.aarch64.asm index 0f604a92d..ac6ae7dea 100644 --- a/tests/snapshots/asm/attribute_c23.aarch64.asm +++ b/tests/snapshots/asm/attribute_c23.aarch64.asm @@ -19,31 +19,26 @@ Disassembly of section .text: mov x2, #0x0 // =0 cmp x0, #0x2 b.lt - b - sxtw x0, w0 - ret - mov x2, #0xa // =10 - add x0, x2, #0x1 - b + cmp x0, #0x2 + b.eq mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 + sxtw x0, w0 + ret + add x0, x2, #0x1 b cmp x0, #0x1 - b.eq - b - cmp x0, #0x2 - b.eq - b + b.ne + mov x2, #0xa // =10 b b
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + sub sp, sp, #0x30 sub x1, x29, #0x18 mov x2, #0x1 // =1 strb w2, [x1] @@ -51,39 +46,22 @@ Disassembly of section .text: add x1, x1, #0x1 mov x2, #0x2 // =2 str x2, [x1] - b - mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x18 ldrb w0, [x0] mov x17, #0x1 // =1 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x18 add x0, x0, #0x1 ldr x0, [x0] cmp x0, #0x2 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x5 // =5 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x6 - b.eq - mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 @@ -91,8 +69,7 @@ Disassembly of section .text: cmp x0, #0xb b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x2 // =2 @@ -100,8 +77,7 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x9 // =9 @@ -113,8 +89,7 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 @@ -137,17 +112,23 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret b b + mov x0, #0x1 // =1 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret : b diff --git a/tests/snapshots/asm/attribute_c23.x64.asm b/tests/snapshots/asm/attribute_c23.x64.asm index 96e9f3a8d..0feea7401 100644 --- a/tests/snapshots/asm/attribute_c23.x64.asm +++ b/tests/snapshots/asm/attribute_c23.x64.asm @@ -20,28 +20,23 @@ Disassembly of section .text: xorq %rcx, %rcx cmpq $0x2, %rdi jl - jmp + cmpq $0x2, %rdi + je + movabsq $-0x1, %rax movslq %eax, %rax retq - movl $0xa, %ecx leaq 0x1(%rcx), %rax jmp - movabsq $-0x1, %rax - jmp cmpq $0x1, %rdi - je - jmp - cmpq $0x2, %rdi - je - jmp + jne + movl $0xa, %ecx jmp jmp
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) + subq $0x30, %rsp leaq -0x18(%rbp), %rcx movl $0x1, %edx movb %dl, (%rcx) @@ -49,40 +44,23 @@ Disassembly of section .text: incq %rcx movl $0x2, %edx movq %rdx, (%rcx) - jmp - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax movsbq (%rax), %rax cmpq $0x1, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x18(%rbp), %rax incq %rax movq (%rax), %rax cmpq $0x2, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq - movl $0x5, %eax - incq %rax - movslq %eax, %rax - cmpq $0x6, %rax - je - movl $0x3, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq movl $0x1, %edi @@ -90,8 +68,7 @@ Disassembly of section .text: cmpq $0xb, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq movl $0x2, %edi @@ -99,8 +76,7 @@ Disassembly of section .text: cmpq $0x1, %rax je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq movl $0x9, %edi @@ -108,8 +84,7 @@ Disassembly of section .text: cmpq $-0x1, %rax je movl $0x6, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -133,17 +108,23 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x7, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq jmp jmp + movl $0x1, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x30, %rsp + popq %rbp + retq : jmp @@ -151,3 +132,4 @@ Disassembly of section .text: jmp xorq %rax, %rax retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/attribute_declspec.aarch64.asm b/tests/snapshots/asm/attribute_declspec.aarch64.asm index 230837548..79c5b06d4 100644 --- a/tests/snapshots/asm/attribute_declspec.aarch64.asm +++ b/tests/snapshots/asm/attribute_declspec.aarch64.asm @@ -23,24 +23,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - mov x0, #0x4 // =4 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x5 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x3 // =3 - lsl x0, x0, #1 - sxtw x0, w0 - cmp x0, #0x6 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 mov x1, #0x7 // =7 str w1, [x0] @@ -56,3 +38,11 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/attribute_declspec.x64.asm b/tests/snapshots/asm/attribute_declspec.x64.asm index e256b6007..0c23b6ecb 100644 --- a/tests/snapshots/asm/attribute_declspec.x64.asm +++ b/tests/snapshots/asm/attribute_declspec.x64.asm @@ -25,24 +25,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - movl $0x4, %eax - incq %rax - movslq %eax, %rax - cmpq $0x5, %rax - je - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - movl $0x3, %eax - shlq $0x1, %rax - movslq %eax, %rax - cmpq $0x6, %rax - je - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax movl $0x7, %ecx movl %ecx, (%rax) @@ -58,3 +40,12 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/attribute_noop.aarch64.asm b/tests/snapshots/asm/attribute_noop.aarch64.asm index 007df4bf4..4d6bb345f 100644 --- a/tests/snapshots/asm/attribute_noop.aarch64.asm +++ b/tests/snapshots/asm/attribute_noop.aarch64.asm @@ -42,15 +42,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - mov x0, #0x2 // =2 - mov x1, #0x3 // =3 - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x5 - b.eq - mov x0, #0xb // =11 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, mov x1, #0x1 // =1 @@ -61,10 +52,12 @@ Disassembly of section .text: mov x0, #0xc // =12 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xd // =13 + mov x0, #0x0 // =0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0xb // =11 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/attribute_noop.x64.asm b/tests/snapshots/asm/attribute_noop.x64.asm index c4b04ce32..00e0e6e8a 100644 --- a/tests/snapshots/asm/attribute_noop.x64.asm +++ b/tests/snapshots/asm/attribute_noop.x64.asm @@ -43,15 +43,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - movl $0x2, %eax - movl $0x3, %ecx - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x5, %rax - je - movl $0xb, %eax - popq %rbp - retq leaq , %rdi movl $0x1, %esi movl $0x2, %edx @@ -62,12 +53,13 @@ Disassembly of section .text: movl $0xc, %eax popq %rbp retq - jmp - movl $0xd, %eax + xorq %rax, %rax popq %rbp retq - xorq %rax, %rax + movl $0xb, %eax + popq %rbp + retq + movl $0xd, %eax popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/attribute_packed.aarch64.asm b/tests/snapshots/asm/attribute_packed.aarch64.asm index 5824c8bf5..ccd504109 100644 --- a/tests/snapshots/asm/attribute_packed.aarch64.asm +++ b/tests/snapshots/asm/attribute_packed.aarch64.asm @@ -13,36 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x40 - b - mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x20 add x0, x0, #0xd sub x1, x29, #0x20 @@ -110,3 +80,27 @@ Disassembly of section .text: ret b b + mov x0, #0x1 // =1 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/attribute_packed.x64.asm b/tests/snapshots/asm/attribute_packed.x64.asm index f096a9554..b2f0c3758 100644 --- a/tests/snapshots/asm/attribute_packed.x64.asm +++ b/tests/snapshots/asm/attribute_packed.x64.asm @@ -14,36 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x40, %rsp - jmp - movl $0x1, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp - movl $0x4, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x20(%rbp), %rax addq $0xd, %rax leaq -0x20(%rbp), %rcx @@ -102,4 +72,28 @@ Disassembly of section .text: retq jmp jmp + movl $0x1, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x40, %rsp + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/attribute_positions.aarch64.asm b/tests/snapshots/asm/attribute_positions.aarch64.asm index b1a864b28..1799a17d0 100644 --- a/tests/snapshots/asm/attribute_positions.aarch64.asm +++ b/tests/snapshots/asm/attribute_positions.aarch64.asm @@ -39,30 +39,6 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x2 // =2 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x3 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x3 // =3 - cmp x0, #0x3 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x7 // =7 - sxtw x0, w1 - cmp x0, #0x7 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 mov x1, #0xb // =11 str w1, [x0] @@ -84,14 +60,23 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - cmp x0, #0x0 - b.eq - mov x0, #0x6 // =6 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + b + mov x0, #0x2 // =2 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b diff --git a/tests/snapshots/asm/attribute_positions.x64.asm b/tests/snapshots/asm/attribute_positions.x64.asm index b869335c4..8bb0ccb34 100644 --- a/tests/snapshots/asm/attribute_positions.x64.asm +++ b/tests/snapshots/asm/attribute_positions.x64.asm @@ -40,30 +40,6 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movl $0x2, %eax - incq %rax - movslq %eax, %rax - cmpq $0x3, %rax - je - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x3, %eax - cmpq $0x3, %rax - je - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x7, %ecx - movslq %ecx, %rax - cmpq $0x7, %rax - je - movl $0x4, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax movl $0xb, %ecx movl %ecx, (%rax) @@ -89,15 +65,24 @@ Disassembly of section .text: popq %rbp retq xorq %rax, %rax - testq %rax, %rax - je - movl $0x6, %eax addq $0x20, %rsp popq %rbp retq - xorq %rax, %rax + jmp + movl $0x2, %eax addq $0x20, %rsp popq %rbp retq - jmp - addb %al, (%rax) + movl $0x3, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x20, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm b/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm index 58e9a3735..5adbefb03 100644 --- a/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm +++ b/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, bl @@ -21,10 +20,9 @@ Disassembly of section .text: cmp x0, #0x0 b.le mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm b/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm index 033c45d92..45f751570 100644 --- a/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm +++ b/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp leaq , %rdi movb $0x0, %al callq @@ -21,10 +20,10 @@ Disassembly of section .text: testq %rax, %rax jle xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/binary_integer_literal.aarch64.asm b/tests/snapshots/asm/binary_integer_literal.aarch64.asm index 6f600ebb2..11233e892 100644 --- a/tests/snapshots/asm/binary_integer_literal.aarch64.asm +++ b/tests/snapshots/asm/binary_integer_literal.aarch64.asm @@ -10,68 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xa // =10 - cmp x0, #0xa - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3 // =3 - cmp x0, #0x3 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xc0 // =192 - mov x17, #0xc0 // =192 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3f // =63 - mov x17, #0x3f // =63 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/binary_integer_literal.x64.asm b/tests/snapshots/asm/binary_integer_literal.x64.asm index 2dcd43714..70f4208a6 100644 --- a/tests/snapshots/asm/binary_integer_literal.x64.asm +++ b/tests/snapshots/asm/binary_integer_literal.x64.asm @@ -11,59 +11,17 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0xa, %eax - cmpq $0xa, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x3, %eax - cmpq $0x3, %rax - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0xc0, %eax - xorq $0xc0, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x3f, %eax - xorq $0x3f, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x1, %rax - cmpq $-0x1, %rax - je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x1, %eax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/binary_search_tree.aarch64.asm b/tests/snapshots/asm/binary_search_tree.aarch64.asm index 77ffe5d12..8ca65adfb 100644 --- a/tests/snapshots/asm/binary_search_tree.aarch64.asm +++ b/tests/snapshots/asm/binary_search_tree.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, x0 mov x21, x1 cmp x20, #0x0 @@ -26,11 +24,9 @@ Disassembly of section .text: str x21, [x0] str x1, [x0, #0x8] str x1, [x0, #0x10] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20] cmp x21, x0 @@ -40,11 +36,9 @@ Disassembly of section .text: bl str x0, [x20, #0x8] mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20, #0x10] mov x1, x21 @@ -55,54 +49,33 @@ Disassembly of section .text: : stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] - mov x20, x0 - mov x21, x1 - cmp x20, #0x0 + cmp x0, #0x0 b.ne mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - ldr x0, [x20] - cmp x0, x21 + ldr x2, [x0] + cmp x2, x1 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - ldr x0, [x20] - cmp x21, x0 + ldr x2, [x0] + cmp x1, x2 b.ge - ldr x0, [x20, #0x8] - mov x1, x21 + ldr x0, [x0, #0x8] bl - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - ldr x0, [x20, #0x10] - mov x1, x21 + ldr x0, [x0, #0x10] bl - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x0 // =0 mov x1, #0x32 // =50 bl @@ -126,10 +99,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x1, #0x28 // =40 mov x0, x20 @@ -137,10 +108,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x1, #0x63 // =99 mov x0, x20 @@ -148,14 +117,10 @@ Disassembly of section .text: cmp x0, #0x1 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret diff --git a/tests/snapshots/asm/binary_search_tree.x64.asm b/tests/snapshots/asm/binary_search_tree.x64.asm index 7855a5c3f..f974b515c 100644 --- a/tests/snapshots/asm/binary_search_tree.x64.asm +++ b/tests/snapshots/asm/binary_search_tree.x64.asm @@ -54,50 +54,31 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %rdi, %rbx - movq %rsi, %r12 - testq %rbx, %rbx + testq %rdi, %rdi jne xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x10, %rsp popq %rbp retq - movq (%rbx), %rax - cmpq %r12, %rax + movq (%rdi), %rax + cmpq %rsi, %rax jne movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x10, %rsp popq %rbp retq - movq (%rbx), %rax - cmpq %rax, %r12 + movq (%rdi), %rax + cmpq %rax, %rsi jge - movq 0x8(%rbx), %rdi - movq %r12, %rsi - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x10, %rsp + movq 0x8(%rdi), %rdi popq %rbp jmp - movq 0x10(%rbx), %rdi - movq %r12, %rsi - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x10, %rsp + movq 0x10(%rdi), %rdi popq %rbp jmp
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi @@ -125,7 +106,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x28, %esi @@ -136,7 +117,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x63, %esi @@ -147,13 +128,13 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm b/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm index 62ee42cff..0b1b6357e 100644 --- a/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm +++ b/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm @@ -10,46 +10,18 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x19, [sp, #0x10] - mov x0, #0xa // =10 - add x1, x0, #0x3 - add x1, x1, #0x7 - add x2, x0, #0x8 - sub x2, x2, #0x3 - sub x3, x0, #0x4 - add x3, x3, #0x9 - sub x4, x0, #0x2 - sub x4, x4, #0x5 - mov x17, #0x3f // =63 - and x5, x0, x17 - mov x17, #0x3 // =3 - orr x6, x0, x17 - mov x17, #0x3 // =3 - eor x0, x0, x17 - add x1, x1, x2 - add x1, x1, x3 - add x1, x1, x4 - add x1, x1, x5 - add x1, x1, x6 - add x0, x1, x0 - sxtw x20, w0 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x1, #0x53 // =83 adrp x0, add x0, x0, - mov x1, x20 bl sxtw x0, w0 - cmp x20, #0x53 - b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/binop_imm_chain_fold.x64.asm b/tests/snapshots/asm/binop_imm_chain_fold.x64.asm index f81ebfec4..774801056 100644 --- a/tests/snapshots/asm/binop_imm_chain_fold.x64.asm +++ b/tests/snapshots/asm/binop_imm_chain_fold.x64.asm @@ -13,42 +13,16 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) - movl $0xa, %eax - leaq 0x3(%rax), %rcx - addq $0x7, %rcx - leaq 0x8(%rax), %rdx - subq $0x3, %rdx - leaq -0x4(%rax), %rsi - addq $0x9, %rsi - leaq -0x2(%rax), %rdi - subq $0x5, %rdi - movq %rax, %r8 - andq $0x3f, %r8 - movq %rax, %r9 - orq $0x3, %r9 - xorq $0x3, %rax - addq %rdx, %rcx - addq %rsi, %rcx - addq %rdi, %rcx - addq %r8, %rcx - addq %r9, %rcx - addq %rcx, %rax - movslq %eax, %rbx + movl $0x53, %esi leaq , %rdi - movq %rbx, %rsi movb $0x0, %al callq movslq %eax, %rax - cmpq $0x53, %rbx - jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx - movq (%rsp), %rbx movq %rcx, %rax - addq $0x70, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.aarch64.asm b/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.aarch64.asm index 12cbbd282..8e3e70a85 100644 --- a/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.aarch64.asm +++ b/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.aarch64.asm @@ -15,18 +15,14 @@ Disassembly of section .text: sxtw x2, w2 ldrsw x1, [x0, x2, lsl #2] mov x4, #0x0 // =0 - sxtw x3, w5 - cmp x3, x2 - b.gt b - sxtw x3, w5 + ldrsw x6, [x0, x3, lsl #2] + add x4, x4, x6 + sxtw x4, w4 add x5, x3, #0x1 - b sxtw x3, w5 - ldrsw x3, [x0, x3, lsl #2] - add x3, x4, x3 - sxtw x4, w3 - b + cmp x3, x2 + b.le add x0, x4, x1 sxtw x0, w0 ret diff --git a/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.x64.asm b/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.x64.asm index 585c4b76b..fa8ff439e 100644 --- a/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.x64.asm +++ b/tests/snapshots/asm/binop_spill_lhs_rhs_in_dst.x64.asm @@ -16,18 +16,14 @@ Disassembly of section .text: movslq %edx, %rdx movslq (%rdi,%rdx,4), %rax xorq %rsi, %rsi - movslq %r8d, %rcx - cmpq %rdx, %rcx - jg jmp - movslq %r8d, %rcx + movslq (%rdi,%rcx,4), %r9 + addq %r9, %rsi + movslq %esi, %rsi leaq 0x1(%rcx), %r8 - jmp movslq %r8d, %rcx - movslq (%rdi,%rcx,4), %rcx - addq %rsi, %rcx - movslq %ecx, %rsi - jmp + cmpq %rdx, %rcx + jle addq %rsi, %rax movslq %eax, %rax retq @@ -58,5 +54,4 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfield_assign_value.aarch64.asm b/tests/snapshots/asm/bitfield_assign_value.aarch64.asm index c8db4ea81..f16df2c2d 100644 --- a/tests/snapshots/asm/bitfield_assign_value.aarch64.asm +++ b/tests/snapshots/asm/bitfield_assign_value.aarch64.asm @@ -27,53 +27,36 @@ Disassembly of section .text: strb w10, [x0, #0x3] ldr x10, [sp], #0x10 sub x0, x29, #0x8 - mov x1, #0x1 // =1 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffd // =65533 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - mov x3, #0x2 // =2 - orr x2, x2, x3 - str w2, [x0] - cmp x1, #0x1 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + and x1, x1, x17 + mov x17, #0x2 // =2 + orr x1, x1, x17 + str w1, [x0] sub x0, x29, #0x8 - mov x1, #0x5 // =5 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xffe3 // =65507 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - mov x3, #0x14 // =20 - orr x2, x2, x3 - str w2, [x0] - cmp x1, #0x5 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + and x1, x1, x17 + mov x17, #0x14 // =20 + orr x1, x1, x17 + str w1, [x0] sub x0, x29, #0x8 - mov x1, #0x5 // =5 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xffe3 // =65507 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - mov x3, #0x14 // =20 - orr x2, x2, x3 - str w2, [x0] - cmp x1, #0x5 - cset x1, ne - cbnz x1, + and x1, x1, x17 + mov x17, #0x14 // =20 + orr x1, x1, x17 + str w1, [x0] + mov x1, #0x0 // =0 sub x0, x29, #0x8 ldr w0, [x0] asr x0, x0, #2 @@ -101,23 +84,23 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x28 sub x1, x29, #0x28 - mov x2, #0x1 // =1 - ldr w3, [x1] + ldr w2, [x1] mov x17, #0xfffd // =65533 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x3, x3, x17 - mov x4, #0x2 // =2 - orr x3, x3, x4 - str w3, [x1] + and x2, x2, x17 + mov x17, #0x2 // =2 + orr x2, x2, x17 + str w2, [x1] ldr w1, [x0] mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - orr x1, x1, x2 + mov x17, #0x1 // =1 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x28 ldr w0, [x0] @@ -139,26 +122,16 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 - mov x1, #0xfffd // =65533 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfe1f // =65055 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - mov x3, #0x1a0 // =416 - orr x2, x2, x3 - str w2, [x0] - mov x17, #0xfffd // =65533 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x1, x17 - cset x1, ne - cbnz x1, + and x1, x1, x17 + mov x17, #0x1a0 // =416 + orr x1, x1, x17 + str w1, [x0] + mov x1, #0x0 // =0 sub x0, x29, #0x8 ldr w0, [x0] asr x0, x0, #5 @@ -182,5 +155,11 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret b - b - b + mov x0, #0x1 // =1 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/bitfield_assign_value.x64.asm b/tests/snapshots/asm/bitfield_assign_value.x64.asm index 7ad38d548..d43fed3b9 100644 --- a/tests/snapshots/asm/bitfield_assign_value.x64.asm +++ b/tests/snapshots/asm/bitfield_assign_value.x64.asm @@ -27,43 +27,21 @@ Disassembly of section .text: movb %dl, 0x3(%rax) popq %rdx leaq -0x8(%rbp), %rax - movl $0x1, %ecx - movl (%rax), %edx - andq $-0x3, %rdx - movl $0x2, %esi - orq %rsi, %rdx - movl %edx, (%rax) - cmpq $0x1, %rcx - je - movl $0x1, %eax - addq $0x50, %rsp - popq %rbp - retq + movl (%rax), %ecx + andq $-0x3, %rcx + orq $0x2, %rcx + movl %ecx, (%rax) leaq -0x8(%rbp), %rax - movl $0x5, %ecx - movl (%rax), %edx - andq $-0x1d, %rdx - movl $0x14, %esi - orq %rsi, %rdx - movl %edx, (%rax) - cmpq $0x5, %rcx - je - movl $0x2, %eax - addq $0x50, %rsp - popq %rbp - retq + movl (%rax), %ecx + andq $-0x1d, %rcx + orq $0x14, %rcx + movl %ecx, (%rax) leaq -0x8(%rbp), %rax - movl $0x5, %ecx - movl (%rax), %edx - andq $-0x1d, %rdx - movl $0x14, %esi - orq %rsi, %rdx - movl %edx, (%rax) - cmpq $0x5, %rcx - setne %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne + movl (%rax), %ecx + andq $-0x1d, %rcx + orq $0x14, %rcx + movl %ecx, (%rax) + xorq %rcx, %rcx leaq -0x8(%rbp), %rax movl (%rax), %eax sarq $0x2, %rax @@ -91,15 +69,13 @@ Disassembly of section .text: popq %rdx leaq -0x28(%rbp), %rax leaq -0x28(%rbp), %rcx - movl $0x1, %edx - movl (%rcx), %esi - andq $-0x3, %rsi - movl $0x2, %edi - orq %rdi, %rsi - movl %esi, (%rcx) + movl (%rcx), %edx + andq $-0x3, %rdx + orq $0x2, %rdx + movl %edx, (%rcx) movl (%rax), %ecx andq $-0x2, %rcx - orq %rdx, %rcx + orq $0x1, %rcx movl %ecx, (%rax) leaq -0x28(%rbp), %rax movl (%rax), %eax @@ -123,17 +99,11 @@ Disassembly of section .text: popq %rbp retq leaq -0x8(%rbp), %rax - movabsq $-0x3, %rcx - movl (%rax), %edx - andq $-0x1e1, %rdx # imm = 0xFE1F - movl $0x1a0, %esi # imm = 0x1A0 - orq %rsi, %rdx - movl %edx, (%rax) - cmpq $-0x3, %rcx - setne %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne + movl (%rax), %ecx + andq $-0x1e1, %rcx # imm = 0xFE1F + orq $0x1a0, %rcx # imm = 0x1A0 + movl %ecx, (%rax) + xorq %rcx, %rcx leaq -0x8(%rbp), %rax movl (%rax), %eax sarq $0x5, %rax @@ -154,5 +124,12 @@ Disassembly of section .text: popq %rbp retq jmp - jmp - jmp + movl $0x1, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x50, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfield_compound_assignment.aarch64.asm b/tests/snapshots/asm/bitfield_compound_assignment.aarch64.asm index 0cba37e11..57b680a94 100644 --- a/tests/snapshots/asm/bitfield_compound_assignment.aarch64.asm +++ b/tests/snapshots/asm/bitfield_compound_assignment.aarch64.asm @@ -167,14 +167,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 - mov x1, #0x1 // =1 - ldrh w2, [x0] + ldrh w1, [x0] mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x1 // =1 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 ldrh w1, [x0] @@ -183,8 +183,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xc0 // =192 - orr x1, x1, x2 + mov x17, #0xc0 // =192 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 ldrh w1, [x0] @@ -193,8 +193,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xc800 // =51200 - orr x1, x1, x2 + mov x17, #0xc800 // =51200 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 sub x1, x29, #0x8 diff --git a/tests/snapshots/asm/bitfield_compound_assignment.x64.asm b/tests/snapshots/asm/bitfield_compound_assignment.x64.asm index dc1b2e086..4874d19a2 100644 --- a/tests/snapshots/asm/bitfield_compound_assignment.x64.asm +++ b/tests/snapshots/asm/bitfield_compound_assignment.x64.asm @@ -122,22 +122,19 @@ Disassembly of section .text: popq %rbp retq leaq -0x8(%rbp), %rax - movl $0x1, %ecx - movzwq (%rax), %rdx - andq $-0x2, %rdx - orq %rdx, %rcx + movzwq (%rax), %rcx + andq $-0x2, %rcx + orq $0x1, %rcx movw %cx, (%rax) leaq -0x8(%rbp), %rax movzwq (%rax), %rcx andq $-0xf1, %rcx - movl $0xc0, %edx - orq %rdx, %rcx + orq $0xc0, %rcx movw %cx, (%rax) leaq -0x8(%rbp), %rax movzwq (%rax), %rcx andq $-0xff01, %rcx # imm = 0xFFFF00FF - movl $0xc800, %edx # imm = 0xC800 - orq %rdx, %rcx + orq $0xc800, %rcx # imm = 0xC800 movw %cx, (%rax) leaq -0x8(%rbp), %rax leaq -0x8(%rbp), %rcx @@ -284,4 +281,3 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfield_incdec.aarch64.asm b/tests/snapshots/asm/bitfield_incdec.aarch64.asm index 8b581c9a1..cf8044e92 100644 --- a/tests/snapshots/asm/bitfield_incdec.aarch64.asm +++ b/tests/snapshots/asm/bitfield_incdec.aarch64.asm @@ -287,14 +287,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 - mov x1, #0xf // =15 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff0 // =65520 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xf // =15 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x20 ldr w1, [x0] diff --git a/tests/snapshots/asm/bitfield_incdec.x64.asm b/tests/snapshots/asm/bitfield_incdec.x64.asm index f37af72e0..7ab5c1a4d 100644 --- a/tests/snapshots/asm/bitfield_incdec.x64.asm +++ b/tests/snapshots/asm/bitfield_incdec.x64.asm @@ -233,10 +233,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x20(%rbp), %rax - movl $0xf, %ecx - movl (%rax), %edx - andq $-0x10, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x10, %rcx + orq $0xf, %rcx movl %ecx, (%rax) leaq -0x20(%rbp), %rax movl (%rax), %ecx @@ -288,3 +287,4 @@ Disassembly of section .text: jmp jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfield_mixed_base_packing.aarch64.asm b/tests/snapshots/asm/bitfield_mixed_base_packing.aarch64.asm index 6534cb0c6..2ec818ebc 100644 --- a/tests/snapshots/asm/bitfield_mixed_base_packing.aarch64.asm +++ b/tests/snapshots/asm/bitfield_mixed_base_packing.aarch64.asm @@ -13,20 +13,15 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - b - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 - mov x1, #0xffff // =65535 - movk x1, #0x7fff, lsl #16 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0x80000000 // =2147483648 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xffff // =65535 + movk x17, #0x7fff, lsl #16 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldrb w1, [x0, #0x3] @@ -35,18 +30,18 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x80 // =128 - orr x1, x1, x2 + mov x17, #0x80 // =128 + orr x1, x1, x17 strb w1, [x0, #0x3] sub x0, x29, #0x10 - mov x1, #0xffff // =65535 - movk x1, #0x3fff, lsl #16 - ldr w2, [x0, #0x4] + ldr w1, [x0, #0x4] mov x17, #0xc0000000 // =3221225472 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xffff // =65535 + movk x17, #0x3fff, lsl #16 + orr x1, x1, x17 str w1, [x0, #0x4] sub x0, x29, #0x10 ldrb w1, [x0, #0x7] @@ -55,8 +50,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xc0 // =192 - orr x1, x1, x2 + mov x17, #0xc0 // =192 + orr x1, x1, x17 strb w1, [x0, #0x7] sub x0, x29, #0x10 mov x1, #0xbeef // =48879 @@ -162,30 +157,25 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x9 // =9 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x18 - mov x1, #0x1ff // =511 - ldrh w2, [x0] + ldrh w1, [x0] mov x17, #0xfe00 // =65024 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x1ff // =511 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x18 - mov x1, #0x123 // =291 - ldrh w2, [x0, #0x2] + ldrh w1, [x0, #0x2] mov x17, #0xfe00 // =65024 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x123 // =291 + orr x1, x1, x17 strh w1, [x0, #0x2] sub x0, x29, #0x18 ldrh w0, [x0] @@ -210,3 +200,11 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret b + mov x0, #0x1 // =1 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/bitfield_mixed_base_packing.x64.asm b/tests/snapshots/asm/bitfield_mixed_base_packing.x64.asm index 6aa106935..815995275 100644 --- a/tests/snapshots/asm/bitfield_mixed_base_packing.x64.asm +++ b/tests/snapshots/asm/bitfield_mixed_base_packing.x64.asm @@ -14,34 +14,25 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - jmp - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax - movl $0x7fffffff, %ecx # imm = 0x7FFFFFFF - movl (%rax), %edx - andq $-0x80000000, %rdx # imm = 0x80000000 - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x80000000, %rcx # imm = 0x80000000 + orq $0x7fffffff, %rcx # imm = 0x7FFFFFFF movl %ecx, (%rax) leaq -0x10(%rbp), %rax movzbq 0x3(%rax), %rcx andq $-0x81, %rcx - movl $0x80, %edx - orq %rdx, %rcx + orq $0x80, %rcx movb %cl, 0x3(%rax) leaq -0x10(%rbp), %rax - movl $0x3fffffff, %ecx # imm = 0x3FFFFFFF - movl 0x4(%rax), %edx - andq $-0x40000000, %rdx # imm = 0xC0000000 - orq %rdx, %rcx + movl 0x4(%rax), %ecx + andq $-0x40000000, %rcx # imm = 0xC0000000 + orq $0x3fffffff, %rcx # imm = 0x3FFFFFFF movl %ecx, 0x4(%rax) leaq -0x10(%rbp), %rax movzbq 0x7(%rax), %rcx andq $-0xc1, %rcx - movl $0xc0, %edx - orq %rdx, %rcx + orq $0xc0, %rcx movb %cl, 0x7(%rax) leaq -0x10(%rbp), %rax movl $0xdeadbeef, %ecx # imm = 0xDEADBEEF @@ -126,22 +117,15 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - jmp - movl $0x9, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax - movl $0x1ff, %ecx # imm = 0x1FF - movzwq (%rax), %rdx - andq $-0x200, %rdx # imm = 0xFE00 - orq %rdx, %rcx + movzwq (%rax), %rcx + andq $-0x200, %rcx # imm = 0xFE00 + orq $0x1ff, %rcx # imm = 0x1FF movw %cx, (%rax) leaq -0x18(%rbp), %rax - movl $0x123, %ecx # imm = 0x123 - movzwq 0x2(%rax), %rdx - andq $-0x200, %rdx # imm = 0xFE00 - orq %rdx, %rcx + movzwq 0x2(%rax), %rcx + andq $-0x200, %rcx # imm = 0xFE00 + orq $0x123, %rcx # imm = 0x123 movw %cx, 0x2(%rax) leaq -0x18(%rbp), %rax movzwq (%rax), %rax @@ -168,5 +152,12 @@ Disassembly of section .text: popq %rbp retq jmp - addb %al, (%rax) + movl $0x1, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x9, %eax + addq $0x20, %rsp + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfield_signed_read.aarch64.asm b/tests/snapshots/asm/bitfield_signed_read.aarch64.asm index ac0a29d93..5abd36f55 100644 --- a/tests/snapshots/asm/bitfield_signed_read.aarch64.asm +++ b/tests/snapshots/asm/bitfield_signed_read.aarch64.asm @@ -14,14 +14,14 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x20 sub x0, x29, #0x8 - mov x1, #0x3 // =3 - ldrh w2, [x0] + ldrh w1, [x0] mov x17, #0xfffc // =65532 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x3 // =3 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 ldrh w1, [x0] @@ -30,8 +30,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x4 // =4 - orr x1, x1, x2 + mov x17, #0x4 // =4 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 ldrh w1, [x0] @@ -40,8 +40,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x8000 // =32768 - orr x1, x1, x2 + mov x17, #0x8000 // =32768 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x8 ldrh w0, [x0] @@ -104,14 +104,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 - mov x1, #0x4 // =4 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x4 // =4 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w1, [x0] @@ -120,8 +120,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x400 // =1024 - orr x1, x1, x2 + mov x17, #0x400 // =1024 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w1, [x0] @@ -129,9 +129,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xf800 // =63488 - movk x2, #0xffff, lsl #16 - orr x1, x1, x2 + mov x17, #0xf800 // =63488 + movk x17, #0xffff, lsl #16 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w0, [x0] @@ -210,14 +210,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 - mov x1, #0x7 // =7 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xf000 // =61440 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x7 // =7 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldrh w1, [x0] @@ -226,8 +226,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x3000 // =12288 - orr x1, x1, x2 + mov x17, #0x3000 // =12288 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x18 ldrh w1, [x0] @@ -236,8 +236,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x4000 // =16384 - orr x1, x1, x2 + mov x17, #0x4000 // =16384 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x18 ldr w0, [x0] @@ -279,15 +279,14 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x6 // =6 - sub x1, x29, #0x18 - ldrh w1, [x1] - asr x1, x1, #12 + sub x0, x29, #0x18 + ldrh w0, [x0] + asr x0, x0, #12 mov x17, #0x3 // =3 - and x1, x1, x17 - lsl x1, x1, #62 - asr x1, x1, #62 - add x0, x1, x0 + and x0, x0, x17 + lsl x0, x0, #62 + asr x0, x0, #62 + add x0, x0, #0x6 sxtw x0, w0 cmp x0, #0x5 b.eq diff --git a/tests/snapshots/asm/bitfield_signed_read.x64.asm b/tests/snapshots/asm/bitfield_signed_read.x64.asm index 381f62229..e322ebd64 100644 --- a/tests/snapshots/asm/bitfield_signed_read.x64.asm +++ b/tests/snapshots/asm/bitfield_signed_read.x64.asm @@ -15,22 +15,19 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x20, %rsp leaq -0x8(%rbp), %rax - movl $0x3, %ecx - movzwq (%rax), %rdx - andq $-0x4, %rdx - orq %rdx, %rcx + movzwq (%rax), %rcx + andq $-0x4, %rcx + orq $0x3, %rcx movw %cx, (%rax) leaq -0x8(%rbp), %rax movzwq (%rax), %rcx andq $-0xd, %rcx - movl $0x4, %edx - orq %rdx, %rcx + orq $0x4, %rcx movw %cx, (%rax) leaq -0x8(%rbp), %rax movzwq (%rax), %rcx andq $-0xfff1, %rcx # imm = 0xFFFF000F - movl $0x8000, %edx # imm = 0x8000 - orq %rdx, %rcx + orq $0x8000, %rcx # imm = 0x8000 movw %cx, (%rax) leaq -0x8(%rbp), %rax movzwq (%rax), %rax @@ -81,23 +78,21 @@ Disassembly of section .text: popq %rbp retq leaq -0x10(%rbp), %rax - movl $0x4, %ecx - movl (%rax), %edx - andq $-0x8, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x8, %rcx + orq $0x4, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %ecx andq $-0x7f9, %rcx # imm = 0xF807 - movl $0x400, %edx # imm = 0x400 - orq %rdx, %rcx + orq $0x400, %rcx # imm = 0x400 movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %ecx movabsq $-0xfffff801, %r11 # imm = 0xFFFFFFFF000007FF andq %r11, %rcx - movl $0xfffff800, %edx # imm = 0xFFFFF800 - orq %rdx, %rcx + movl $0xfffff800, %r11d # imm = 0xFFFFF800 + orq %r11, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %eax @@ -157,22 +152,19 @@ Disassembly of section .text: popq %rbp retq leaq -0x18(%rbp), %rax - movl $0x7, %ecx - movl (%rax), %edx - andq $-0x1000, %rdx # imm = 0xF000 - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x1000, %rcx # imm = 0xF000 + orq $0x7, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movzwq (%rax), %rcx andq $-0x3001, %rcx # imm = 0xCFFF - movl $0x3000, %edx # imm = 0x3000 - orq %rdx, %rcx + orq $0x3000, %rcx # imm = 0x3000 movw %cx, (%rax) leaq -0x18(%rbp), %rax movzwq (%rax), %rcx andq $-0xc001, %rcx # imm = 0xFFFF3FFF - movl $0x4000, %edx # imm = 0x4000 - orq %rdx, %rcx + orq $0x4000, %rcx # imm = 0x4000 movw %cx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %eax @@ -207,14 +199,13 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movl $0x6, %eax - leaq -0x18(%rbp), %rcx - movzwq (%rcx), %rcx - sarq $0xc, %rcx - andq $0x3, %rcx - shlq $0x3e, %rcx - sarq $0x3e, %rcx - addq %rcx, %rax + leaq -0x18(%rbp), %rax + movzwq (%rax), %rax + sarq $0xc, %rax + andq $0x3, %rax + shlq $0x3e, %rax + sarq $0x3e, %rax + addq $0x6, %rax movslq %eax, %rax cmpq $0x5, %rax je diff --git a/tests/snapshots/asm/bitfield_storage_unit.aarch64.asm b/tests/snapshots/asm/bitfield_storage_unit.aarch64.asm index 680a89faf..75a5c983a 100644 --- a/tests/snapshots/asm/bitfield_storage_unit.aarch64.asm +++ b/tests/snapshots/asm/bitfield_storage_unit.aarch64.asm @@ -13,26 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - b - mov x0, #0xb // =11 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xc // =12 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xd // =13 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xe // =14 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 add x0, x0, #0x4 sub x1, x29, #0x10 @@ -54,14 +34,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 - mov x1, #0xab // =171 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xff00 // =65280 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xab // =171 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -70,8 +50,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x100 // =256 - orr x1, x1, x2 + mov x17, #0x100 // =256 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -79,9 +59,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x8a00 // =35328 - movk x2, #0x246, lsl #16 - orr x1, x1, x2 + mov x17, #0x8a00 // =35328 + movk x17, #0x246, lsl #16 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w0, [x0] @@ -119,14 +99,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 - mov x1, #0x55 // =85 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xff00 // =65280 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x55 // =85 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w0, [x0] @@ -164,14 +144,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 - mov x1, #0xff // =255 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xff00 // =65280 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xff // =255 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x20 ldr w1, [x0] @@ -180,8 +160,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x100 // =256 - orr x1, x1, x2 + mov x17, #0x100 // =256 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x20 ldr w1, [x0] @@ -189,9 +169,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xfe00 // =65024 - movk x2, #0xffff, lsl #16 - orr x1, x1, x2 + mov x17, #0xfe00 // =65024 + movk x17, #0xffff, lsl #16 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x20 mov x1, #0x0 // =0 @@ -257,3 +237,19 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x0, #0xb // =11 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/bitfield_storage_unit.x64.asm b/tests/snapshots/asm/bitfield_storage_unit.x64.asm index 3e5aa9fd4..2ceb7b083 100644 --- a/tests/snapshots/asm/bitfield_storage_unit.x64.asm +++ b/tests/snapshots/asm/bitfield_storage_unit.x64.asm @@ -14,26 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - jmp - movl $0xb, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0xc, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0xd, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0xe, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax addq $0x4, %rax leaq -0x10(%rbp), %rcx @@ -55,23 +35,20 @@ Disassembly of section .text: popq %rbp retq leaq -0x18(%rbp), %rax - movl $0xab, %ecx - movl (%rax), %edx - andq $-0x100, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x100, %rcx + orq $0xab, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx andq $-0x101, %rcx # imm = 0xFEFF - movl $0x100, %edx # imm = 0x100 - orq %rdx, %rcx + orq $0x100, %rcx # imm = 0x100 movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx movabsq $-0xfffffe01, %r11 # imm = 0xFFFFFFFF000001FF andq %r11, %rcx - movl $0x2468a00, %edx # imm = 0x2468A00 - orq %rdx, %rcx + orq $0x2468a00, %rcx # imm = 0x2468A00 movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %eax @@ -103,10 +80,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x18(%rbp), %rax - movl $0x55, %ecx - movl (%rax), %edx - andq $-0x100, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x100, %rcx + orq $0x55, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %eax @@ -138,23 +114,21 @@ Disassembly of section .text: popq %rbp retq leaq -0x20(%rbp), %rax - movl $0xff, %ecx - movl (%rax), %edx - andq $-0x100, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x100, %rcx + orq $0xff, %rcx movl %ecx, (%rax) leaq -0x20(%rbp), %rax movl (%rax), %ecx andq $-0x101, %rcx # imm = 0xFEFF - movl $0x100, %edx # imm = 0x100 - orq %rdx, %rcx + orq $0x100, %rcx # imm = 0x100 movl %ecx, (%rax) leaq -0x20(%rbp), %rax movl (%rax), %ecx movabsq $-0xfffffe01, %r11 # imm = 0xFFFFFFFF000001FF andq %r11, %rcx - movl $0xfffffe00, %edx # imm = 0xFFFFFE00 - orq %rdx, %rcx + movl $0xfffffe00, %r11d # imm = 0xFFFFFE00 + orq %r11, %rcx movl %ecx, (%rax) leaq -0x20(%rbp), %rax xorq %rcx, %rcx @@ -206,4 +180,21 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq + movl $0xb, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xc, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xd, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xe, %eax + addq $0x20, %rsp + popq %rbp + retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitfields.aarch64.asm b/tests/snapshots/asm/bitfields.aarch64.asm index 527db156f..585d94f24 100644 --- a/tests/snapshots/asm/bitfields.aarch64.asm +++ b/tests/snapshots/asm/bitfields.aarch64.asm @@ -14,24 +14,24 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x20 sub x0, x29, #0x10 - mov x1, #0x1 // =1 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x1 // =1 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 - mov x1, #0x0 // =0 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffd // =65533 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x0 // =0 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w1, [x0] @@ -40,8 +40,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x14 // =20 - orr x1, x1, x2 + mov x17, #0x14 // =20 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w1, [x0] @@ -50,17 +50,17 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x220 // =544 - orr x1, x1, x2 + mov x17, #0x220 // =544 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 - mov x1, #0x5678 // =22136 - movk x1, #0x1234, lsl #16 - ldr w2, [x0, #0x4] + ldr w1, [x0, #0x4] mov x17, #0xffff00000000 // =281470681743360 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x5678 // =22136 + movk x17, #0x1234, lsl #16 + orr x1, x1, x17 str w1, [x0, #0x4] sub x0, x29, #0x10 mov x1, #0x3e7 // =999 @@ -127,14 +127,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 - mov x1, #0x0 // =0 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x0 // =0 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w0, [x0] @@ -204,8 +204,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x1c // =28 - orr x1, x1, x2 + mov x17, #0x1c // =28 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w0, [x0] @@ -240,14 +240,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 - mov x1, #0x1 // =1 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x1 // =1 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -256,18 +256,18 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x2 // =2 - orr x1, x1, x2 + mov x17, #0x2 // =2 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 - mov x1, #0x0 // =0 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffb // =65531 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x0 // =0 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -276,8 +276,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x8 // =8 - orr x1, x1, x2 + mov x17, #0x8 // =8 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -286,8 +286,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xb0 // =176 - orr x1, x1, x2 + mov x17, #0xb0 // =176 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w1, [x0] @@ -296,8 +296,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0xc800 // =51200 - orr x1, x1, x2 + mov x17, #0xc800 // =51200 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x18 ldr w0, [x0] diff --git a/tests/snapshots/asm/bitfields.x64.asm b/tests/snapshots/asm/bitfields.x64.asm index c1b1c4d98..9eb778591 100644 --- a/tests/snapshots/asm/bitfields.x64.asm +++ b/tests/snapshots/asm/bitfields.x64.asm @@ -15,35 +15,30 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x20, %rsp leaq -0x10(%rbp), %rax - movl $0x1, %ecx - movl (%rax), %edx - andq $-0x2, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x2, %rcx + orq $0x1, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax - xorq %rcx, %rcx - movl (%rax), %edx - andq $-0x3, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x3, %rcx + orq $0x0, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %ecx andq $-0x1d, %rcx - movl $0x14, %edx - orq %rdx, %rcx + orq $0x14, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %ecx andq $-0x3e1, %rcx # imm = 0xFC1F - movl $0x220, %edx # imm = 0x220 - orq %rdx, %rcx + orq $0x220, %rcx # imm = 0x220 movl %ecx, (%rax) leaq -0x10(%rbp), %rax - movl $0x12345678, %ecx # imm = 0x12345678 - movl 0x4(%rax), %edx + movl 0x4(%rax), %ecx movabsq $-0x100000000, %r11 # imm = 0xFFFFFFFF00000000 - andq %r11, %rdx - orq %rdx, %rcx + andq %r11, %rcx + orq $0x12345678, %rcx # imm = 0x12345678 movl %ecx, 0x4(%rax) leaq -0x10(%rbp), %rax movl $0x3e7, %ecx # imm = 0x3E7 @@ -104,10 +99,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x10(%rbp), %rax - xorq %rcx, %rcx - movl (%rax), %edx - andq $-0x2, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x2, %rcx + orq $0x0, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %eax @@ -167,8 +161,7 @@ Disassembly of section .text: leaq -0x10(%rbp), %rax movl (%rax), %ecx andq $-0x1d, %rcx - movl $0x1c, %edx - orq %rdx, %rcx + orq $0x1c, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %eax @@ -200,40 +193,34 @@ Disassembly of section .text: popq %rbp retq leaq -0x18(%rbp), %rax - movl $0x1, %ecx - movl (%rax), %edx - andq $-0x2, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x2, %rcx + orq $0x1, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx andq $-0x3, %rcx - movl $0x2, %edx - orq %rdx, %rcx + orq $0x2, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax - xorq %rcx, %rcx - movl (%rax), %edx - andq $-0x5, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x5, %rcx + orq $0x0, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx andq $-0x9, %rcx - movl $0x8, %edx - orq %rdx, %rcx + orq $0x8, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx andq $-0xf1, %rcx - movl $0xb0, %edx - orq %rdx, %rcx + orq $0xb0, %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %ecx andq $-0xff01, %rcx # imm = 0xFFFF00FF - movl $0xc800, %edx # imm = 0xC800 - orq %rdx, %rcx + orq $0xc800, %rcx # imm = 0xC800 movl %ecx, (%rax) leaq -0x18(%rbp), %rax movl (%rax), %eax @@ -320,4 +307,3 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitop_common_type.aarch64.asm b/tests/snapshots/asm/bitop_common_type.aarch64.asm index c13c33227..2c033720f 100644 --- a/tests/snapshots/asm/bitop_common_type.aarch64.asm +++ b/tests/snapshots/asm/bitop_common_type.aarch64.asm @@ -10,94 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xf000 // =61440 - movk x0, #0x4006, lsl #16 - movk x0, #0x1, lsl #32 - mov x1, #0x0 // =0 - orr x2, x0, x1 - add x2, x2, #0x1 - mov x17, #0xf001 // =61441 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mvn x2, x1 - and x2, x0, x2 - add x2, x2, #0x1 - mov x17, #0xf001 // =61441 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - eor x2, x0, x1 - add x2, x2, #0x1 - mov x17, #0xf001 // =61441 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x2, #0xf001 // =61441 - movk x2, #0x4006, lsl #16 - movk x2, #0x1, lsl #32 - sub x2, x2, #0x1 - mov x17, #0xf // =15 - orr x2, x2, x17 - add x2, x2, #0x1 - mov x17, #0xf010 // =61456 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - orr x2, x0, x1 - mov x17, #0xf000 // =61440 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - orr x2, x0, x1 - mov x17, #0xf000 // =61440 - movk x17, #0x4006, lsl #16 - movk x17, #0x1, lsl #32 - cmp x2, x17 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - orr x0, x0, x1 - mov x17, #0x100000000 // =4294967296 - cmp x0, x17 - cset x0, hi - cmp x0, #0x0 - b.ne mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/bitop_common_type.x64.asm b/tests/snapshots/asm/bitop_common_type.x64.asm index ca37fb999..b73f0eff2 100644 --- a/tests/snapshots/asm/bitop_common_type.x64.asm +++ b/tests/snapshots/asm/bitop_common_type.x64.asm @@ -11,84 +11,20 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movabsq $0x14006f000, %rax # imm = 0x14006F000 - xorq %rcx, %rcx - movq %rax, %rdx - orq %rcx, %rdx - incq %rdx - movabsq $0x14006f001, %r11 # imm = 0x14006F001 - cmpq %r11, %rdx - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - movq %rcx, %rdx - xorq $-0x1, %rdx - andq %rax, %rdx - incq %rdx - movabsq $0x14006f001, %r11 # imm = 0x14006F001 - cmpq %r11, %rdx - je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - movq %rax, %rdx - xorq %rcx, %rdx - incq %rdx - movabsq $0x14006f001, %r11 # imm = 0x14006F001 - cmpq %r11, %rdx - je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq - movabsq $0x14006f001, %rdx # imm = 0x14006F001 - decq %rdx - orq $0xf, %rdx - incq %rdx - movabsq $0x14006f010, %r11 # imm = 0x14006F010 - cmpq %r11, %rdx - je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq - movq %rax, %rdx - orq %rcx, %rdx - movabsq $0x14006f000, %r11 # imm = 0x14006F000 - cmpq %r11, %rdx - je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq - movq %rax, %rdx - orq %rcx, %rdx - movabsq $0x14006f000, %r11 # imm = 0x14006F000 - cmpq %r11, %rdx - je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq - orq %rcx, %rax - movabsq $0x100000000, %r11 # imm = 0x100000000 - cmpq %r11, %rax - seta %al - movzbq %al, %rax - testq %rax, %rax - jne movl $0x7, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm b/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm index 514d31e53..f5e615203 100644 --- a/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm +++ b/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm @@ -34,9 +34,6 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 ldrb w2, [x0] lsl x2, x2, #24 mov w2, w2 @@ -51,81 +48,12 @@ Disassembly of section .text: sxtw x0, w0 add x0, x1, x0 sub x0, x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - mov x0, #0xfdc2 // =64962 - movk x0, #0xffff, lsl #16 - mov x1, #0x0 // =0 - mov w0, w0 - orr x0, x0, x1 - sxtw x0, w0 - mov x17, #0xfdc2 // =64962 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - mov x1, #0xfdc2 // =64962 - movk x1, #0xffff, lsl #16 - mov w1, w1 - orr x0, x0, x1 - sxtw x0, w0 - mov x17, #0xfdc2 // =64962 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xfdc2 // =64962 - movk x0, #0xffff, lsl #16 - mov x1, #0x0 // =0 - mov w0, w0 - eor x0, x0, x1 - sxtw x0, w0 - mov x17, #0xfdc2 // =64962 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xfdc2 // =64962 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - mov w0, w0 - and x0, x0, x1 - sxtw x0, w0 - mov x17, #0xfdc2 // =64962 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -170,3 +98,19 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm b/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm index 1d8abec55..c5c63ac87 100644 --- a/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm +++ b/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm @@ -35,9 +35,6 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movzbq (%rdi), %rax shlq $0x18, %rax movl %eax, %eax @@ -52,58 +49,12 @@ Disassembly of section .text: movslq %eax, %rax addq %rsi, %rax subq %rsi, %rax - addq $0x10, %rsp - popq %rbp retq
: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movl $0xfffffdc2, %eax # imm = 0xFFFFFDC2 - xorq %rcx, %rcx - movl %eax, %eax - orq %rcx, %rax - movslq %eax, %rax - cmpq $-0x23e, %rax # imm = 0xFDC2 - je - movl $0x1, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - movl $0xfffffdc2, %ecx # imm = 0xFFFFFDC2 - movl %ecx, %ecx - orq %rcx, %rax - movslq %eax, %rax - cmpq $-0x23e, %rax # imm = 0xFDC2 - je - movl $0x2, %eax - addq $0x30, %rsp - popq %rbp - retq - movl $0xfffffdc2, %eax # imm = 0xFFFFFDC2 - xorq %rcx, %rcx - movl %eax, %eax - xorq %rcx, %rax - movslq %eax, %rax - cmpq $-0x23e, %rax # imm = 0xFDC2 - je - movl $0x3, %eax - addq $0x30, %rsp - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movabsq $-0x23e, %rcx # imm = 0xFDC2 - movl %eax, %eax - andq %rcx, %rax - movslq %eax, %rax - cmpq $-0x23e, %rax # imm = 0xFDC2 - je - movl $0x4, %eax - addq $0x30, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax leaq , %rcx pushq %rdx @@ -143,5 +94,20 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x30, %rsp + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm b/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm index aaef702e5..ff3e74f2c 100644 --- a/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm +++ b/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm @@ -10,17 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x9 // =9 - adrp x1, - add x1, x1, - ldrsw x1, [x1] - add x0, x1, x0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + add x0, x0, #0x9 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : @@ -32,37 +26,17 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x5 // =5 - cmp x0, #0x5 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x5 // =5 - mov x1, #0x0 // =0 - adrp x2, - add x2, x2, - ldrsw x3, [x2] - add x1, x1, x3 - mov x3, #0x7 // =7 - str w3, [x2] - add x1, x1, x0 - sxtw x1, w1 - cmp x1, #0x69 + adrp x0, + add x0, x0, + ldrsw x1, [x0] + add x1, x1, #0x0 + mov x2, #0x7 // =7 + str w2, [x0] + add x0, x1, #0x5 + sxtw x0, w0 + cmp x0, #0x69 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - cmp x0, #0x5 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -70,34 +44,28 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x9 // =9 - adrp x1, - add x1, x1, - ldrsw x1, [x1] - add x0, x1, x0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + add x0, x0, #0x9 sxtw x0, w0 cmp x0, #0x40 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3 // =3 - adrp x1, - add x1, x1, - ldrsw x1, [x1] - add x0, x1, x0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + add x0, x0, #0x3 sxtw x0, w0 cmp x0, #0x50 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + ret + mov x0, #0x3 // =3 ret diff --git a/tests/snapshots/asm/block_extern_shadows_local.x64.asm b/tests/snapshots/asm/block_extern_shadows_local.x64.asm index 6a9271b49..a96aec3f5 100644 --- a/tests/snapshots/asm/block_extern_shadows_local.x64.asm +++ b/tests/snapshots/asm/block_extern_shadows_local.x64.asm @@ -11,16 +11,10 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x9, %eax - leaq , %rcx - movslq (%rcx), %rcx - addq %rcx, %rax + leaq , %rax + movslq (%rax), %rax + addq $0x9, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : @@ -31,69 +25,43 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0x5, %eax - cmpq $0x5, %rax - je - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x5, %eax - xorq %rcx, %rcx - leaq , %rdx - movslq (%rdx), %rsi - addq %rsi, %rcx - movl $0x7, %esi - movl %esi, (%rdx) - addq %rax, %rcx - movslq %ecx, %rcx - cmpq $0x69, %rcx + leaq , %rax + movslq (%rax), %rcx + addq $0x0, %rcx + movl $0x7, %edx + movl %edx, (%rax) + leaq 0x5(%rcx), %rax + movslq %eax, %rax + cmpq $0x69, %rax je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - cmpq $0x5, %rax - je - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x7, %rax je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x9, %eax - leaq , %rcx - movslq (%rcx), %rcx - addq %rcx, %rax + leaq , %rax + movslq (%rax), %rax + addq $0x9, %rax movslq %eax, %rax cmpq $0x40, %rax je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x3, %eax - leaq , %rcx - movslq (%rcx), %rcx - addq %rcx, %rax + leaq , %rax + movslq (%rax), %rax + addq $0x3, %rax movslq %eax, %rax cmpq $0x50, %rax je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) + movl $0x1, %eax + retq + movl $0x3, %eax + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/block_scope_extern.aarch64.asm b/tests/snapshots/asm/block_scope_extern.aarch64.asm index 929015418..2bebe9008 100644 --- a/tests/snapshots/asm/block_scope_extern.aarch64.asm +++ b/tests/snapshots/asm/block_scope_extern.aarch64.asm @@ -10,16 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0] cmp x1, #0x3 @@ -30,8 +25,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -39,8 +32,6 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -53,8 +44,6 @@ Disassembly of section .text: cmp x0, #0x3c b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -64,10 +53,8 @@ Disassembly of section .text: cmp x0, #0x9 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x5 // =5 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x5 // =5 + b b diff --git a/tests/snapshots/asm/block_scope_extern.x64.asm b/tests/snapshots/asm/block_scope_extern.x64.asm index 8bfd7dfad..9eb456cf9 100644 --- a/tests/snapshots/asm/block_scope_extern.x64.asm +++ b/tests/snapshots/asm/block_scope_extern.x64.asm @@ -11,15 +11,10 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax testq %rax, %rax jne movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movslq (%rax), %rcx cmpq $0x3, %rcx @@ -34,16 +29,12 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x5, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rcx @@ -55,8 +46,6 @@ Disassembly of section .text: cmpq $0x3c, %rax je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movl $0x9, %ecx @@ -65,11 +54,8 @@ Disassembly of section .text: cmpq $0x9, %rax jne xorq %rcx, %rcx - jmp - movl $0x5, %ecx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq + movl $0x5, %ecx + jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm b/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm index 44cdcacc9..85f4329ec 100644 --- a/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm +++ b/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm @@ -24,7 +24,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 bl adrp x0, add x0, x0, @@ -32,23 +31,19 @@ Disassembly of section .text: cmp x1, #0x5 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0] cmp x1, #0x5 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret cmp x0, x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm b/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm index c6ced4395..a7192074a 100644 --- a/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm +++ b/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm @@ -24,32 +24,26 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp callq leaq , %rax movslq (%rax), %rcx cmpq $0x5, %rcx je movl $0x1, %eax - addq $0x10, %rsp popq %rbp retq movslq (%rax), %rcx cmpq $0x5, %rcx je movl $0x2, %eax - addq $0x10, %rsp popq %rbp retq cmpq %rax, %rax je movl $0x3, %eax - addq $0x10, %rsp popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm b/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm index 3195cdf18..1b2f95f5d 100644 --- a/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm +++ b/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm @@ -10,49 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b - b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x19, [sp, #0x10] - mov x0, #0x28 // =40 - mov x1, #0x2 // =2 - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x2a - b.eq - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, adrp x1, @@ -61,31 +40,21 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x3 - cset x20, ne - cbnz x20, + mov x1, #0x0 // =0 adrp x0, add x0, x0, adrp x1, add x1, x1, bl cmp x0, #0x0 - cset x20, eq - cbz x20, + cset x1, eq + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -94,47 +63,28 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, mov x0, #0x5 // =5 - mov x1, #0x1 // =1 - mov x2, #0x2 // =2 - mov x3, #0x3 // =3 - add x1, x1, x2 - add x1, x1, x3 - sxtw x1, w1 - cmp x1, #0x6 - cset x2, ne - cbnz x2, - cmp x0, #0x5 - cset x2, ne - cbz x2, - mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7 // =7 - cmp x0, #0x7 - b.eq - mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x6 // =6 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - b - b : add x0, x0, x1 diff --git a/tests/snapshots/asm/block_scope_function_declaration.x64.asm b/tests/snapshots/asm/block_scope_function_declaration.x64.asm index 3c34a5e30..7f763b998 100644 --- a/tests/snapshots/asm/block_scope_function_declaration.x64.asm +++ b/tests/snapshots/asm/block_scope_function_declaration.x64.asm @@ -11,24 +11,9 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp - incq %rdi - incq %rsi - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp - retq movsbq (%rdi), %rax movsbq (%rsi), %rcx cmpq %rcx, %rax @@ -36,55 +21,38 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je + incq %rdi + incq %rsi jmp jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %al + movzbq %al, %rax + retq
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) - movl $0x28, %eax - movl $0x2, %ecx - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x2a, %rax - je - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq leaq , %rdi leaq , %rsi callq testq %rax, %rax jne movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq - movl $0x1, %eax - movl $0x2, %ecx - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x3, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx - jne + xorq %rcx, %rcx leaq , %rdi leaq , %rsi callq testq %rax, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq leaq , %rdi @@ -94,47 +62,24 @@ Disassembly of section .text: cmpq $0x4, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq - movl $0x5, %eax - movl $0x1, %ecx - movl $0x2, %edx - movl $0x3, %esi - addq %rdx, %rcx - addq %rsi, %rcx - movslq %ecx, %rcx - cmpq $0x6, %rcx - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne - cmpq $0x5, %rax - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq - movl $0x7, %eax - cmpq $0x7, %rax - je - movl $0x6, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + xorq %rax, %rax popq %rbp retq - xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp + movl $0x1, %eax + popq %rbp + retq + movl $0x6, %eax popq %rbp retq - jmp - jmp : leaq (%rdi,%rsi), %rax diff --git a/tests/snapshots/asm/block_scope_typedef_variadic_fnptr.aarch64.asm b/tests/snapshots/asm/block_scope_typedef_variadic_fnptr.aarch64.asm index 2cff6e648..dbb4fd030 100644 --- a/tests/snapshots/asm/block_scope_typedef_variadic_fnptr.aarch64.asm +++ b/tests/snapshots/asm/block_scope_typedef_variadic_fnptr.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x19, [sp] + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x40 mov x1, #0x0 // =0 strb w1, [x0] @@ -37,14 +36,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret <__c5_sys_snprintf>: diff --git a/tests/snapshots/asm/bool_normalize_c99.aarch64.asm b/tests/snapshots/asm/bool_normalize_c99.aarch64.asm index 10be5f0ea..084504b99 100644 --- a/tests/snapshots/asm/bool_normalize_c99.aarch64.asm +++ b/tests/snapshots/asm/bool_normalize_c99.aarch64.asm @@ -24,212 +24,163 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0xa0 - b - mov x0, #0x1 // =1 + mov x0, #0x3 // =3 + stur w0, [x29, #-0x30] + sub x0, x29, #0x30 + cmp x0, #0x0 + cset x0, ne + mov x17, #0xff // =255 + and x0, x0, x17 + cmp x0, #0x1 + b.eq + mov x0, #0x7 // =7 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 + mov x0, #0x3fe0000000000000 // =4602678819172646912 + mov x1, #0x0 // =0 + fmov d16, x0 + fmov d17, x1 + fcmp d16, d17 + cset x0, ne + mov x17, #0xff // =255 + and x0, x0, x17 cmp x0, #0x1 b.eq - mov x0, #0x2 // =2 + mov x0, #0x8 // =8 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x1, #0x0 // =0 - cmp x1, #0x0 + mov x0, #0x0 // =0 + fmov d16, x0 + fmov d17, x0 + fcmp d16, d17 + cset x0, ne + mov x17, #0xff // =255 + and x0, x0, x17 + cmp x0, #0x0 b.eq - mov x0, #0x3 // =3 + mov x0, #0x9 // =9 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x2, #0x1 // =1 - cmp x2, #0x1 + sub x0, x29, #0x58 + mov x1, #0x1 // =1 + strb w1, [x0] + sub x0, x29, #0x58 + mov x1, #0x7 // =7 + str w1, [x0, #0x4] + sub x0, x29, #0x58 + mov x1, #0x0 // =0 + strb w1, [x0, #0x8] + sub x0, x29, #0x58 + ldrb w0, [x0] + cmp x0, #0x1 b.eq - mov x0, #0x4 // =4 + mov x0, #0xa // =10 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x1 // =1 - cmp x3, #0x1 + sub x0, x29, #0x58 + ldrsw x0, [x0, #0x4] + cmp x0, #0x7 b.eq - mov x0, #0x5 // =5 + mov x0, #0xb // =11 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x1 // =1 - cmp x3, #0x1 + sub x0, x29, #0x58 + ldrb w0, [x0, #0x8] + cmp x0, #0x0 b.eq - mov x0, #0x6 // =6 + mov x0, #0xc // =12 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x3 // =3 - stur w3, [x29, #-0x30] - sub x3, x29, #0x30 - cmp x3, #0x0 + sub x0, x29, #0x60 + mov x1, #0x0 // =0 + mov x3, #0x1 // =1 + strb w3, [x0] + sub x0, x29, #0x60 + strb w1, [x0, #0x1] + sub x0, x29, #0x60 + strb w3, [x0, #0x2] + sub x0, x29, #0x60 + ldrb w0, [x0] + cmp x0, #0x1 + cset x0, ne + cbnz x0, + sub x0, x29, #0x60 + ldrb w0, [x0, #0x1] + cmp x0, #0x0 + cset x0, ne + cmp x0, #0x0 cset x3, ne - mov x17, #0xff // =255 - and x3, x3, x17 - cmp x3, #0x1 - b.eq - mov x0, #0x7 // =7 + cbnz x3, + sub x0, x29, #0x60 + ldrb w0, [x0, #0x2] + cmp x0, #0x1 + cset x3, ne + cbz x3, + mov x0, #0x10 // =16 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x3fe0000000000000 // =4602678819172646912 - mov x4, #0x0 // =0 - fmov d16, x3 - fmov d17, x4 - fcmp d16, d17 - cset x3, ne - mov x17, #0xff // =255 - and x3, x3, x17 - cmp x3, #0x1 - b.eq - mov x0, #0x8 // =8 + mov x0, #0x0 // =0 + mov x2, #0x0 // =0 + mov x2, x0 + cbz x2, + mov x0, #0x12 // =18 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x0 // =0 - fmov d16, x3 - fmov d17, x3 - fcmp d16, d17 - cset x3, ne - mov x17, #0xff // =255 - and x3, x3, x17 - cmp x3, #0x0 - b.eq - mov x0, #0x9 // =9 + mov x0, #0x0 // =0 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - sub x3, x29, #0x58 - mov x4, #0x1 // =1 - strb w4, [x3] - sub x3, x29, #0x58 - mov x4, #0x7 // =7 - str w4, [x3, #0x4] - sub x3, x29, #0x58 - mov x4, #0x0 // =0 - strb w4, [x3, #0x8] - sub x3, x29, #0x58 - ldrb w3, [x3] - cmp x3, #0x1 - b.eq - mov x0, #0xa // =10 + b + b + mov x0, #0x1 // =1 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - sub x3, x29, #0x58 - ldrsw x3, [x3, #0x4] - cmp x3, #0x7 - b.eq - mov x0, #0xb // =11 + mov x0, #0x2 // =2 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - sub x3, x29, #0x58 - ldrb w3, [x3, #0x8] - cmp x3, #0x0 - b.eq - mov x0, #0xc // =12 + mov x0, #0x3 // =3 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x2a // =42 - sxtw x3, w3 - cmp x3, #0x0 - cset x3, ne - cmp x3, #0x1 - b.eq - mov x0, #0xd // =13 + mov x0, #0x4 // =4 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x0 // =0 - sxtw x3, w3 - cmp x3, #0x0 - cset x3, ne - cmp x3, #0x0 - b.eq - mov x0, #0xe // =14 + mov x0, #0x5 // =5 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x3, #0x1 // =1 - mov x17, #0xff // =255 - and x3, x3, x17 - cmp x3, #0x1 - b.eq - mov x0, #0xf // =15 + mov x0, #0x6 // =6 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - sub x3, x29, #0x60 - mov x4, #0x0 // =0 - mov x6, #0x1 // =1 - strb w6, [x3] - sub x3, x29, #0x60 - strb w4, [x3, #0x1] - sub x3, x29, #0x60 - strb w6, [x3, #0x2] - sub x3, x29, #0x60 - ldrb w3, [x3] - cmp x3, #0x1 - cset x3, ne - cbnz x3, - sub x3, x29, #0x60 - ldrb w3, [x3, #0x1] - cmp x3, #0x0 - cset x3, ne - cmp x3, #0x0 - cset x6, ne - cbnz x6, - sub x3, x29, #0x60 - ldrb w3, [x3, #0x2] - cmp x3, #0x1 - cset x6, ne - cbz x6, - mov x0, #0x10 // =16 + mov x0, #0xd // =13 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - add x0, x0, x1 - add x0, x0, x2 - sxtw x0, w0 - cmp x0, #0x0 - cset x0, ne - mov x17, #0xff // =255 - and x0, x0, x17 - cmp x0, #0x1 - b.eq - mov x0, #0x11 // =17 + mov x0, #0xe // =14 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x1, #0x0 // =0 - cmp x0, #0x0 - cset x2, eq - cbnz x2, - mov x2, x1 - cbz x2, - mov x0, #0x12 // =18 + mov x0, #0xf // =15 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - cmp x0, #0x1 - b.eq - mov x0, #0x13 // =19 + mov x0, #0x11 // =17 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x13 // =19 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret - b - b - b diff --git a/tests/snapshots/asm/bool_normalize_c99.x64.asm b/tests/snapshots/asm/bool_normalize_c99.x64.asm index 60363586b..a7f011eb6 100644 --- a/tests/snapshots/asm/bool_normalize_c99.x64.asm +++ b/tests/snapshots/asm/bool_normalize_c99.x64.asm @@ -26,231 +26,178 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0xa0, %rsp - jmp - movl $0x1, %eax + movl $0x3, %eax + movl %eax, -0x30(%rbp) + leaq -0x30(%rbp), %rax + testq %rax, %rax + setne %al + movzbq %al, %rax + andq $0xff, %rax + cmpq $0x1, %rax + je + movl $0x7, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %eax + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + xorq %rcx, %rcx + movq %rax, %xmm14 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + andq $0xff, %rax cmpq $0x1, %rax je - movl $0x2, %eax + movl $0x8, %eax addq $0xa0, %rsp popq %rbp retq - xorq %rcx, %rcx - testq %rcx, %rcx + xorq %rax, %rax + movq %rax, %xmm14 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + andq $0xff, %rax + testq %rax, %rax je - movl $0x3, %eax + movl $0x9, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %edx - cmpq $0x1, %rdx + leaq -0x58(%rbp), %rax + movl $0x1, %ecx + movb %cl, (%rax) + leaq -0x58(%rbp), %rax + movl $0x7, %ecx + movl %ecx, 0x4(%rax) + leaq -0x58(%rbp), %rax + xorq %rcx, %rcx + movb %cl, 0x8(%rax) + leaq -0x58(%rbp), %rax + movzbq (%rax), %rax + cmpq $0x1, %rax je - movl $0x4, %eax + movl $0xa, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %esi - cmpq $0x1, %rsi + leaq -0x58(%rbp), %rax + movslq 0x4(%rax), %rax + cmpq $0x7, %rax je - movl $0x5, %eax + movl $0xb, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %esi - cmpq $0x1, %rsi + leaq -0x58(%rbp), %rax + movzbq 0x8(%rax), %rax + testq %rax, %rax je - movl $0x6, %eax + movl $0xc, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x3, %esi - movl %esi, -0x30(%rbp) - leaq -0x30(%rbp), %rsi + leaq -0x60(%rbp), %rax + xorq %rcx, %rcx + movl $0x1, %esi + movb %sil, (%rax) + leaq -0x60(%rbp), %rax + movb %cl, 0x1(%rax) + leaq -0x60(%rbp), %rax + movb %sil, 0x2(%rax) + leaq -0x60(%rbp), %rax + movzbq (%rax), %rax + cmpq $0x1, %rax + setne %al + movzbq %al, %rax + testq %rax, %rax + jne + leaq -0x60(%rbp), %rax + movzbq 0x1(%rax), %rax + testq %rax, %rax + setne %al + movzbq %al, %rax + testq %rax, %rax + setne %sil + movzbq %sil, %rsi testq %rsi, %rsi + jne + leaq -0x60(%rbp), %rax + movzbq 0x2(%rax), %rax + cmpq $0x1, %rax setne %sil movzbq %sil, %rsi - andq $0xff, %rsi - cmpq $0x1, %rsi + testq %rsi, %rsi je - movl $0x7, %eax + movl $0x10, %eax addq $0xa0, %rsp popq %rbp retq - movabsq $0x3fe0000000000000, %rsi # imm = 0x3FE0000000000000 - xorq %rdi, %rdi - movq %rsi, %xmm14 - movq %rdi, %xmm15 - ucomisd %xmm15, %xmm14 - setne %sil - movzbq %sil, %rsi - setp %r10b - movzbq %r10b, %r10 - orq %r10, %rsi - andq $0xff, %rsi - cmpq $0x1, %rsi + xorq %rax, %rax + xorq %rdx, %rdx + movq %rax, %rdx + testq %rdx, %rdx je - movl $0x8, %eax + movl $0x12, %eax addq $0xa0, %rsp popq %rbp retq - xorq %rsi, %rsi - movq %rsi, %xmm14 - movq %rsi, %xmm15 - ucomisd %xmm15, %xmm14 - setne %sil - movzbq %sil, %rsi - setp %r10b - movzbq %r10b, %r10 - orq %r10, %rsi - andq $0xff, %rsi - testq %rsi, %rsi - je - movl $0x9, %eax + xorq %rax, %rax addq $0xa0, %rsp popq %rbp retq - leaq -0x58(%rbp), %rsi - movl $0x1, %edi - movb %dil, (%rsi) - leaq -0x58(%rbp), %rsi - movl $0x7, %edi - movl %edi, 0x4(%rsi) - leaq -0x58(%rbp), %rsi - xorq %rdi, %rdi - movb %dil, 0x8(%rsi) - leaq -0x58(%rbp), %rsi - movzbq (%rsi), %rsi - cmpq $0x1, %rsi - je - movl $0xa, %eax + jmp + jmp + movl $0x1, %eax addq $0xa0, %rsp popq %rbp retq - leaq -0x58(%rbp), %rsi - movslq 0x4(%rsi), %rsi - cmpq $0x7, %rsi - je - movl $0xb, %eax + movl $0x2, %eax addq $0xa0, %rsp popq %rbp retq - leaq -0x58(%rbp), %rsi - movzbq 0x8(%rsi), %rsi - testq %rsi, %rsi - je - movl $0xc, %eax + movl $0x3, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x2a, %esi - movslq %esi, %rsi - testq %rsi, %rsi - setne %sil - movzbq %sil, %rsi - cmpq $0x1, %rsi - je - movl $0xd, %eax + movl $0x4, %eax addq $0xa0, %rsp popq %rbp retq - xorq %rsi, %rsi - movslq %esi, %rsi - testq %rsi, %rsi - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi - je - movl $0xe, %eax + movl $0x5, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %esi - andq $0xff, %rsi - cmpq $0x1, %rsi - je - movl $0xf, %eax + movl $0x6, %eax addq $0xa0, %rsp popq %rbp retq - leaq -0x60(%rbp), %rsi - xorq %rdi, %rdi - movl $0x1, %r9d - movb %r9b, (%rsi) - leaq -0x60(%rbp), %rsi - movb %dil, 0x1(%rsi) - leaq -0x60(%rbp), %rsi - movb %r9b, 0x2(%rsi) - leaq -0x60(%rbp), %rsi - movzbq (%rsi), %rsi - cmpq $0x1, %rsi - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi - jne - leaq -0x60(%rbp), %rsi - movzbq 0x1(%rsi), %rsi - testq %rsi, %rsi - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi - setne %r9b - movzbq %r9b, %r9 - testq %r9, %r9 - jne - leaq -0x60(%rbp), %rsi - movzbq 0x2(%rsi), %rsi - cmpq $0x1, %rsi - setne %r9b - movzbq %r9b, %r9 - testq %r9, %r9 - je - movl $0x10, %eax + movl $0xd, %eax addq $0xa0, %rsp popq %rbp retq - addq %rcx, %rax - addq %rdx, %rax - movslq %eax, %rax - testq %rax, %rax - setne %al - movzbq %al, %rax - andq $0xff, %rax - cmpq $0x1, %rax - je - movl $0x11, %eax + movl $0xe, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %eax - xorq %rcx, %rcx - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne - movq %rcx, %rdx - testq %rdx, %rdx - je - movl $0x12, %eax + movl $0xf, %eax addq $0xa0, %rsp popq %rbp retq - movl $0x1, %eax - cmpq $0x1, %rax - je - movl $0x13, %eax + movl $0x11, %eax addq $0xa0, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x13, %eax addq $0xa0, %rsp popq %rbp retq - jmp - jmp - jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bound_import_arg_narrowing.aarch64.asm b/tests/snapshots/asm/bound_import_arg_narrowing.aarch64.asm index 45dfe84ed..675abf293 100644 --- a/tests/snapshots/asm/bound_import_arg_narrowing.aarch64.asm +++ b/tests/snapshots/asm/bound_import_arg_narrowing.aarch64.asm @@ -14,10 +14,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -40,19 +39,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x3 // =3 - movk x0, #0x1, lsl #32 - sxtw x0, w0 - cmp x0, #0x3 - b.eq - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret sub x0, x29, #0x18 adrp x1, @@ -84,9 +72,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret sub x0, x29, #0x18 ldrb w0, [x0, #0x3] @@ -96,14 +83,16 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret b b + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 + ret diff --git a/tests/snapshots/asm/bound_import_arg_narrowing.x64.asm b/tests/snapshots/asm/bound_import_arg_narrowing.x64.asm index 81d201e6a..93411ec59 100644 --- a/tests/snapshots/asm/bound_import_arg_narrowing.x64.asm +++ b/tests/snapshots/asm/bound_import_arg_narrowing.x64.asm @@ -43,14 +43,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x100000003, %rax # imm = 0x100000003 - movslq %eax, %rax - cmpq $0x3, %rax - je - movl $0x2, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax leaq , %rcx pushq %rdx @@ -105,3 +97,8 @@ Disassembly of section .text: retq jmp jmp + movl $0x2, %eax + addq $0x40, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/brace_elided_struct_array_init.aarch64.asm b/tests/snapshots/asm/brace_elided_struct_array_init.aarch64.asm index b7705c96a..4e07e616f 100644 --- a/tests/snapshots/asm/brace_elided_struct_array_init.aarch64.asm +++ b/tests/snapshots/asm/brace_elided_struct_array_init.aarch64.asm @@ -10,17 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 adrp x0, add x0, x0, ldrsw x1, [x0] cmp x1, #0x7 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x1 @@ -33,8 +28,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x18] cmp x1, #0x0 @@ -45,8 +38,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x28] cmp x1, #0x2 @@ -59,8 +50,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x48] cmp x1, #0x3 @@ -73,8 +62,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x68] cmp x1, #0x0 @@ -85,12 +72,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/brace_elided_struct_array_init.x64.asm b/tests/snapshots/asm/brace_elided_struct_array_init.x64.asm index a06c2ba3b..4270178a1 100644 --- a/tests/snapshots/asm/brace_elided_struct_array_init.x64.asm +++ b/tests/snapshots/asm/brace_elided_struct_array_init.x64.asm @@ -11,16 +11,11 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x7, %rcx je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx cmpq $0x1, %rcx @@ -36,8 +31,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movq 0x18(%rax), %rcx testq %rcx, %rcx @@ -52,8 +45,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x28(%rax), %rcx cmpq $0x2, %rcx @@ -69,8 +60,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x48(%rax), %rcx cmpq $0x3, %rcx @@ -86,8 +75,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x68(%rax), %rcx testq %rcx, %rcx @@ -102,16 +89,11 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp jmp jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/brace_elided_toplevel_struct_array.aarch64.asm b/tests/snapshots/asm/brace_elided_toplevel_struct_array.aarch64.asm index 312c4997a..a6bfc3989 100644 --- a/tests/snapshots/asm/brace_elided_toplevel_struct_array.aarch64.asm +++ b/tests/snapshots/asm/brace_elided_toplevel_struct_array.aarch64.asm @@ -47,16 +47,6 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x10 // =16 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #3 - cmp x0, #0x2 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x0, [x0, #0x8] @@ -80,16 +70,6 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x18 // =24 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #3 - cmp x0, #0x3 - b.eq - mov x0, #0x5 // =5 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x28 ldrsw x0, [x0, #0x14] cmp x0, #0x10 @@ -114,16 +94,6 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x10 // =16 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #3 - cmp x0, #0x2 - b.eq - mov x0, #0x8 // =8 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x0, [x0, #0xc] @@ -166,3 +136,15 @@ Disassembly of section .text: b b b + mov x0, #0x2 // =2 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/brace_elided_toplevel_struct_array.x64.asm b/tests/snapshots/asm/brace_elided_toplevel_struct_array.x64.asm index 632ca8c48..cd951e31f 100644 --- a/tests/snapshots/asm/brace_elided_toplevel_struct_array.x64.asm +++ b/tests/snapshots/asm/brace_elided_toplevel_struct_array.x64.asm @@ -49,16 +49,6 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x10, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x3, %rax - cmpq $0x2, %rax - je - movl $0x2, %eax - addq $0x60, %rsp - popq %rbp - retq leaq , %rax movslq 0x8(%rax), %rax cmpq $0x1e, %rax @@ -85,16 +75,6 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x3, %rax - cmpq $0x3, %rax - je - movl $0x5, %eax - addq $0x60, %rsp - popq %rbp - retq leaq -0x28(%rbp), %rax movslq 0x14(%rax), %rax cmpq $0x10, %rax @@ -121,16 +101,6 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x10, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x3, %rax - cmpq $0x2, %rax - je - movl $0x8, %eax - addq $0x60, %rsp - popq %rbp - retq leaq , %rax movslq 0xc(%rax), %rax cmpq $0x18, %rax @@ -175,4 +145,16 @@ Disassembly of section .text: jmp jmp jmp + movl $0x2, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x60, %rsp + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/branch_relaxation.aarch64.asm b/tests/snapshots/asm/branch_relaxation.aarch64.asm index d92472562..1b0d70801 100644 --- a/tests/snapshots/asm/branch_relaxation.aarch64.asm +++ b/tests/snapshots/asm/branch_relaxation.aarch64.asm @@ -13,34 +13,29 @@ Disassembly of section .text: sxtw x0, w0 mov x2, #0x0 // =0 mov x1, x2 - sxtw x3, w2 - cmp x3, x0 - b.ge - b - sxtw x2, w2 - add x2, x2, #0x1 b - sxtw x3, w2 mov x4, #0x3 // =3 sdiv x17, x3, x4 - msub x3, x17, x4, x3 - cmp x3, #0x0 + msub x4, x17, x4, x3 + cmp x4, #0x0 b.ne - b - sxtw x0, w1 - ret add x1, x1, x2 b - sxtw x3, w2 mov x4, #0x3 // =3 sdiv x17, x3, x4 - msub x3, x17, x4, x3 - cmp x3, #0x1 + msub x4, x17, x4, x3 + cmp x4, #0x1 b.ne sub x1, x1, #0x1 b add x1, x1, #0x2 b + add x2, x3, #0x1 + sxtw x3, w2 + cmp x3, x0 + b.lt + sxtw x0, w1 + ret
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/branch_relaxation.x64.asm b/tests/snapshots/asm/branch_relaxation.x64.asm index 169bcd365..26b0cac3d 100644 --- a/tests/snapshots/asm/branch_relaxation.x64.asm +++ b/tests/snapshots/asm/branch_relaxation.x64.asm @@ -14,40 +14,41 @@ Disassembly of section .text: movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq %rdi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - movslq %ecx, %rdx movl $0x3, %esi pushq %rax + pushq %rdx movq %rdx, %rax cqto idivq %rsi + movq %rdx, %rsi + popq %rdx popq %rax - testq %rdx, %rdx + testq %rsi, %rsi jne - jmp - movslq %eax, %rax - retq addq %rcx, %rax jmp - movslq %ecx, %rdx movl $0x3, %esi pushq %rax + pushq %rdx movq %rdx, %rax cqto idivq %rsi + movq %rdx, %rsi + popq %rdx popq %rax - cmpq $0x1, %rdx + cmpq $0x1, %rsi jne decq %rax jmp addq $0x2, %rax jmp + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq %rdi, %rdx + jl + movslq %eax, %rax + retq
: pushq %rbp @@ -55,5 +56,4 @@ Disassembly of section .text: movl $0xa, %edi popq %rbp jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/break_continue.aarch64.asm b/tests/snapshots/asm/break_continue.aarch64.asm index 879a0ea04..1fe670032 100644 --- a/tests/snapshots/asm/break_continue.aarch64.asm +++ b/tests/snapshots/asm/break_continue.aarch64.asm @@ -12,30 +12,24 @@ Disassembly of section .text: brk #: mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w0 - cmp x2, #0xa - b.ge b - sxtw x0, w0 - add x0, x0, #0x1 - b - sxtw x2, w0 cmp x2, #0x5 - b.ne - b - sxtw x0, w1 - ret - b - sxtw x2, w0 + b.eq asr x3, x2, #63 lsr x3, x3, #63 - add x2, x2, x3 + add x4, x2, x3 mov x17, #0x1 // =1 - and x2, x2, x17 - sub x2, x2, x3 - cmp x2, #0x0 + and x4, x4, x17 + sub x3, x4, x3 + cmp x3, #0x0 b.ne b add x1, x1, x0 sxtw x1, w1 + add x0, x2, #0x1 + sxtw x2, w0 + cmp x2, #0xa + b.lt + sxtw x0, w1 + ret b diff --git a/tests/snapshots/asm/break_continue.x64.asm b/tests/snapshots/asm/break_continue.x64.asm index a894c7a41..3a183b80b 100644 --- a/tests/snapshots/asm/break_continue.x64.asm +++ b/tests/snapshots/asm/break_continue.x64.asm @@ -13,31 +13,27 @@ Disassembly of section .text:
: xorq %rcx, %rcx movq %rcx, %rax - movslq %eax, %rdx - cmpq $0xa, %rdx - jge jmp - movslq %eax, %rax - incq %rax - jmp - movslq %eax, %rdx cmpq $0x5, %rdx - jne - jmp - movslq %ecx, %rax - retq - jmp - movslq %eax, %rdx + je movq %rdx, %rsi sarq $0x3f, %rsi shrq $0x3f, %rsi - addq %rsi, %rdx - andq $0x1, %rdx - subq %rsi, %rdx - testq %rdx, %rdx + leaq (%rdx,%rsi), %rdi + andq $0x1, %rdi + movq %rsi, %r10 + movq %rdi, %rsi + subq %r10, %rsi + testq %rsi, %rsi jne jmp addq %rax, %rcx movslq %ecx, %rcx + leaq 0x1(%rdx), %rax + movslq %eax, %rdx + cmpq $0xa, %rdx + jl + movslq %ecx, %rax + retq jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bst_free.aarch64.asm b/tests/snapshots/asm/bst_free.aarch64.asm index 4dc5c4df1..20ddf7da9 100644 --- a/tests/snapshots/asm/bst_free.aarch64.asm +++ b/tests/snapshots/asm/bst_free.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, x0 cmp x20, #0x0 b.ne mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x8] bl @@ -32,19 +30,16 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, x0 mov x21, x1 cmp x20, #0x0 @@ -55,11 +50,9 @@ Disassembly of section .text: str x21, [x0] str x1, [x0, #0x8] str x1, [x0, #0x10] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20] cmp x21, x0 @@ -69,11 +62,9 @@ Disassembly of section .text: bl str x0, [x20, #0x8] mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20, #0x10] mov x1, x21 @@ -82,11 +73,9 @@ Disassembly of section .text: b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, #0x0 // =0 mov x1, #0x32 // =50 mov x0, x20 @@ -101,8 +90,6 @@ Disassembly of section .text: mov x0, x21 bl mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret diff --git a/tests/snapshots/asm/bst_free.x64.asm b/tests/snapshots/asm/bst_free.x64.asm index fc6c8b0a5..c55d10cc2 100644 --- a/tests/snapshots/asm/bst_free.x64.asm +++ b/tests/snapshots/asm/bst_free.x64.asm @@ -81,7 +81,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rbx, %rbx @@ -100,7 +100,7 @@ Disassembly of section .text: movq %rbx, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/builtin_bit_count.aarch64.asm b/tests/snapshots/asm/builtin_bit_count.aarch64.asm index 087096912..fe3121935 100644 --- a/tests/snapshots/asm/builtin_bit_count.aarch64.asm +++ b/tests/snapshots/asm/builtin_bit_count.aarch64.asm @@ -20,931 +20,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x1 // =1 - mov x1, #0x0 // =0 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sub x0, x1, x0 - mov x1, #0x1f // =31 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x80000000 // =2147483648 - mov x1, #0x40000000 // =1073741824 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sub x0, x1, x0 - mov x1, #0x0 // =0 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x10000 // =65536 - mov x1, #0x8000 // =32768 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sub x0, x1, x0 - mov x1, #0xf // =15 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xffff // =65535 - movk x1, #0x7fff, lsl #16 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sub x0, x1, x0 - mov x1, #0x0 // =0 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x1, x0, x1 - mov w1, w1 - lsr x2, x1, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x2, x2, x17 - sub x1, x1, x2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x2, x1, x17 - lsr x1, x1, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x1, x17 - add x1, x2, x1 - lsr x2, x1, #4 - add x1, x1, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x1, x1, x17 - lsr x2, x1, #8 - add x1, x1, x2 - lsr x2, x1, #16 - add x1, x1, x2 - mov x17, #0x7f // =127 - and x1, x1, x17 - sxtw x1, w1 - sxtw x0, w0 - cmp x1, x0 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0x7fff, lsl #16 - mov x1, #0xffff // =65535 - movk x1, #0x7fff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x1f // =31 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - mov x1, #0xffff // =65535 - movk x1, #0xfffe, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x10 // =16 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0x3fff, lsl #16 - mov x1, #0xffff // =65535 - movk x1, #0xbfff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x0, x0, x1 - mov w0, w0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x1e // =30 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x8 // =8 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - sub x1, x0, x0 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x2, x1, x17 - lsr x1, x1, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x1, x17 - add x1, x2, x1 - lsr x2, x1, #4 - add x1, x1, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x1, x1, x17 - lsr x2, x1, #8 - add x1, x1, x2 - lsr x2, x1, #16 - add x1, x1, x2 - mov x17, #0x7f // =127 - and x1, x1, x17 - sxtw x1, w1 - sxtw x0, w0 - cmp x1, x0 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x9 // =9 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0x5555 // =21845 - movk x1, #0x5555, lsl #16 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xa // =10 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xf0f // =3855 - movk x0, #0xf0f, lsl #16 - mov x1, #0x505 // =1285 - movk x1, #0x505, lsl #16 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x10 // =16 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xb // =11 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7 // =7 - mov x1, #0x3 // =3 - mov x2, #0x1 // =1 - sub x0, x0, x2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x2, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - and x0, x0, x17 - add x0, x2, x0 - lsr x2, x0, #4 - add x0, x0, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x0, x0, x17 - lsr x2, x0, #8 - add x0, x0, x2 - lsr x2, x0, #16 - add x0, x0, x2 - mov x17, #0x7f // =127 - and x0, x0, x17 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xc // =12 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x1 // =1 - mov x1, #0x0 // =0 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - lsr x1, x0, #32 - orr x0, x0, x1 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x40 // =64 - sub x0, x1, x0 - mov x1, #0x3f // =63 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xd // =13 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #-0x8000000000000000 // =-9223372036854775808 - mov x1, #0x4000000000000000 // =4611686018427387904 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - lsr x1, x0, #32 - orr x0, x0, x1 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x40 // =64 - sub x0, x1, x0 - mov x1, #0x0 // =0 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xe // =14 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x100000000 // =4294967296 - mov x1, #0x80000000 // =2147483648 - orr x0, x0, x1 - lsr x1, x0, #2 - orr x0, x0, x1 - lsr x1, x0, #4 - orr x0, x0, x1 - lsr x1, x0, #8 - orr x0, x0, x1 - lsr x1, x0, #16 - orr x0, x0, x1 - lsr x1, x0, #32 - orr x0, x0, x1 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x40 // =64 - sub x0, x1, x0 - mov x1, #0x1f // =31 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0xf // =15 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x1, x0, x1 - lsr x2, x1, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x2, x2, x17 - sub x1, x1, x2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x2, x1, x17 - lsr x1, x1, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x1, x17 - add x1, x2, x1 - lsr x2, x1, #4 - add x1, x1, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x1, x1, x17 - lsr x2, x1, #8 - add x1, x1, x2 - lsr x2, x1, #16 - add x1, x1, x2 - lsr x2, x1, #32 - add x1, x1, x2 - mov x17, #0x7f // =127 - and x1, x1, x17 - sxtw x1, w1 - sxtw x0, w0 - cmp x1, x0 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x10 // =16 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0x7fff, lsl #48 - and x0, x0, x0 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x3f // =63 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x11 // =17 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - movk x1, #0xfffe, lsl #32 - movk x1, #0xffff, lsl #48 - and x0, x0, x1 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x20 // =32 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x12 // =18 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x5555 // =21845 - movk x1, #0x5555, lsl #16 - movk x1, #0x5555, lsl #32 - movk x1, #0x5555, lsl #48 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x40 // =64 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x13 // =19 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xcafe // =51966 - movk x0, #0xbeef, lsl #16 - movk x0, #0xdead, lsl #32 - mov x1, #0x4555 // =17749 - movk x1, #0x5555, lsl #16 - movk x1, #0x4554, lsl #32 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x23 // =35 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x14 // =20 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret mov x0, #0xff // =255 movk x0, #0xff, lsl #16 stur w0, [x29, #-0x8] @@ -973,10 +48,8 @@ Disassembly of section .text: add x0, x0, x1 mov x17, #0x7f // =127 and x0, x0, x17 - mov x1, #0x10 // =16 sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 + cmp x0, #0x10 cset x0, eq cmp x0, #0x0 b.ne @@ -1022,10 +95,8 @@ Disassembly of section .text: and x0, x0, x17 mov x1, #0x20 // =32 sub x0, x1, x0 - mov x1, #0x8 // =8 sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 + cmp x0, #0x8 cset x0, eq cmp x0, #0x0 b.ne @@ -1062,199 +133,12 @@ Disassembly of section .text: add x0, x0, x1 mov x17, #0x7f // =127 and x0, x0, x17 - mov x1, #0x0 // =0 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x17 // =23 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x1, x0, x1 - lsr x2, x1, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x2, x2, x17 - sub x1, x1, x2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x2, x1, x17 - lsr x1, x1, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x1, x17 - add x1, x2, x1 - lsr x2, x1, #4 - add x1, x1, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x1, x1, x17 - lsr x2, x1, #8 - add x1, x1, x2 - lsr x2, x1, #16 - add x1, x1, x2 - lsr x2, x1, #32 - add x1, x1, x2 - mov x17, #0x7f // =127 - and x1, x1, x17 - sxtw x1, w1 - sxtw x0, w0 - cmp x1, x0 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x18 // =24 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - mov x1, #0xffff // =65535 - movk x1, #0xfffe, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - and x0, x0, x1 - lsr x1, x0, #1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - and x1, x1, x17 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x10 // =16 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq - cmp x0, #0x0 - b.ne - mov x0, #0x19 // =25 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7 // =7 - mov x1, #0x3 // =3 - mov x2, #0x1 // =1 - sub x0, x0, x2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x2, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x2, x0 - lsr x2, x0, #4 - add x0, x0, x2 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x2, x0, #8 - add x0, x0, x2 - lsr x2, x0, #16 - add x0, x0, x2 - lsr x2, x0, #32 - add x0, x0, x2 - mov x17, #0x7f // =127 - and x0, x0, x17 sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 - cset x0, eq cmp x0, #0x0 - b.ne - mov x0, #0x1a // =26 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xf0f // =3855 - movk x0, #0xf0f, lsl #16 - mov x1, #0x505 // =1285 - movk x1, #0x505, lsl #16 - sub x0, x0, x1 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x1, x0, x17 - lsr x0, x0, #2 - mov x17, #0x3333 // =13107 - movk x17, #0x3333, lsl #16 - movk x17, #0x3333, lsl #32 - movk x17, #0x3333, lsl #48 - and x0, x0, x17 - add x0, x1, x0 - lsr x1, x0, #4 - add x0, x0, x1 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - movk x17, #0xf0f, lsl #32 - movk x17, #0xf0f, lsl #48 - and x0, x0, x17 - lsr x1, x0, #8 - add x0, x0, x1 - lsr x1, x0, #16 - add x0, x0, x1 - lsr x1, x0, #32 - add x0, x0, x1 - mov x17, #0x7f // =127 - and x0, x0, x17 - mov x1, #0x10 // =16 - sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 cset x0, eq cmp x0, #0x0 b.ne - mov x0, #0x1b // =27 + mov x0, #0x17 // =23 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret @@ -1296,10 +180,8 @@ Disassembly of section .text: add x0, x0, x1 mov x17, #0x7f // =127 and x0, x0, x17 - mov x1, #0x10 // =16 sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 + cmp x0, #0x10 cset x0, eq cmp x0, #0x0 b.ne @@ -1345,10 +227,8 @@ Disassembly of section .text: add x0, x0, x1 mov x17, #0x7f // =127 and x0, x0, x17 - mov x1, #0x0 // =0 sxtw x0, w0 - sxtw x1, w1 - cmp x0, x1 + cmp x0, #0x0 cset x0, eq cmp x0, #0x0 b.ne @@ -1360,3 +240,99 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xa // =10 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xf // =15 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10 // =16 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x11 // =17 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x12 // =18 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x13 // =19 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x14 // =20 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x18 // =24 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x19 // =25 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1a // =26 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1b // =27 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/builtin_bit_count.x64.asm b/tests/snapshots/asm/builtin_bit_count.x64.asm index e987812b2..bc2a408bb 100644 --- a/tests/snapshots/asm/builtin_bit_count.x64.asm +++ b/tests/snapshots/asm/builtin_bit_count.x64.asm @@ -22,853 +22,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movl $0x1, %eax - xorq %rcx, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - movl $0x1f, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x80000000, %eax # imm = 0x80000000 - movl $0x40000000, %ecx # imm = 0x40000000 - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - xorq %rcx, %rcx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x10000, %eax # imm = 0x10000 - movl $0x8000, %ecx # imm = 0x8000 - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - movl $0xf, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0x7fffffff, %ecx # imm = 0x7FFFFFFF - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - xorq %rcx, %rcx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x4, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - movabsq $-0x2, %rcx - andq %rax, %rcx - movl %ecx, %ecx - movq %rcx, %rdx - shrq $0x1, %rdx - andq $0x55555555, %rdx # imm = 0x55555555 - subq %rdx, %rcx - movq %rcx, %rdx - andq $0x33333333, %rdx # imm = 0x33333333 - shrq $0x2, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x4, %rdx - addq %rdx, %rcx - andq $0xf0f0f0f, %rcx # imm = 0xF0F0F0F - movq %rcx, %rdx - shrq $0x8, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x10, %rdx - addq %rdx, %rcx - andq $0x7f, %rcx - movslq %ecx, %rcx - movslq %eax, %rax - cmpq %rax, %rcx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x5, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x7fffffff, %eax # imm = 0x7FFFFFFF - movabsq $-0x80000001, %rcx # imm = 0xFFFFFFFF7FFFFFFF - andq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x1f, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x6, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xffff, %eax # imm = 0xFFFF - movabsq $-0x10001, %rcx # imm = 0xFFFEFFFF - andq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x10, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x7, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x3fffffff, %eax # imm = 0x3FFFFFFF - movabsq $-0x40000001, %rcx # imm = 0xBFFFFFFF - andq %rcx, %rax - movl %eax, %eax - movq %rax, %rcx - shrq $0x1, %rcx - andq $0x55555555, %rcx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x1e, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x8, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - movq %rax, %rcx - subq %rax, %rcx - movq %rcx, %rdx - andq $0x33333333, %rdx # imm = 0x33333333 - shrq $0x2, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x4, %rdx - addq %rdx, %rcx - andq $0xf0f0f0f, %rcx # imm = 0xF0F0F0F - movq %rcx, %rdx - shrq $0x8, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x10, %rdx - addq %rdx, %rcx - andq $0x7f, %rcx - movslq %ecx, %rcx - movslq %eax, %rax - cmpq %rax, %rcx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x9, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0x55555555, %ecx # imm = 0x55555555 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xa, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xf0f0f0f, %eax # imm = 0xF0F0F0F - movl $0x5050505, %ecx # imm = 0x5050505 - subq %rcx, %rax - movq %rax, %rcx - andq $0x33333333, %rcx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x10, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xb, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x7, %eax - movl $0x3, %ecx - movl $0x1, %edx - subq %rdx, %rax - movq %rax, %rdx - andq $0x33333333, %rdx # imm = 0x33333333 - shrq $0x2, %rax - andq $0x33333333, %rax # imm = 0x33333333 - addq %rdx, %rax - movq %rax, %rdx - shrq $0x4, %rdx - addq %rdx, %rax - andq $0xf0f0f0f, %rax # imm = 0xF0F0F0F - movq %rax, %rdx - shrq $0x8, %rdx - addq %rdx, %rax - movq %rax, %rdx - shrq $0x10, %rdx - addq %rdx, %rax - andq $0x7f, %rax - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xc, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x1, %eax - xorq %rcx, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x40, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - movl $0x3f, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xd, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x40, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - xorq %rcx, %rcx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xe, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $0x100000000, %rax # imm = 0x100000000 - movl $0x80000000, %ecx # imm = 0x80000000 - orq %rcx, %rax - movq %rax, %rcx - shrq $0x2, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x8, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - orq %rcx, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x40, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - movl $0x1f, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0xf, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - movabsq $-0x2, %rcx - andq %rax, %rcx - movq %rcx, %rdx - shrq $0x1, %rdx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rdx - subq %rdx, %rcx - movabsq $0x3333333333333333, %rdx # imm = 0x3333333333333333 - andq %rcx, %rdx - shrq $0x2, %rcx - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rcx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x4, %rdx - addq %rdx, %rcx - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rcx - movq %rcx, %rdx - shrq $0x8, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x10, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x20, %rdx - addq %rdx, %rcx - andq $0x7f, %rcx - movslq %ecx, %rcx - movslq %eax, %rax - cmpq %rax, %rcx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x10, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $0x7fffffffffffffff, %rax # imm = 0x7FFFFFFFFFFFFFFF - andq %rax, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x3f, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x11, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movabsq $-0x100000001, %rcx # imm = 0xFFFFFFFEFFFFFFFF - andq %rcx, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x20, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x12, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - movabsq $0x5555555555555555, %rcx # imm = 0x5555555555555555 - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x40, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x13, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $0xdeadbeefcafe, %rax # imm = 0xDEADBEEFCAFE - movabsq $0x455455554555, %rcx # imm = 0x455455554555 - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x23, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x14, %eax - addq $0x20, %rsp - popq %rbp - retq movl $0xff00ff, %eax # imm = 0xFF00FF movl %eax, -0x8(%rbp) movl -0x8(%rbp), %eax @@ -892,10 +45,8 @@ Disassembly of section .text: shrq $0x10, %rcx addq %rcx, %rax andq $0x7f, %rax - movl $0x10, %ecx movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax + cmpq $0x10, %rax sete %al movzbq %al, %rax testq %rax, %rax @@ -945,10 +96,8 @@ Disassembly of section .text: movq %rax, %r10 movq %rcx, %rax subq %r10, %rax - movl $0x8, %ecx movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax + cmpq $0x8, %rax sete %al movzbq %al, %rax testq %rax, %rax @@ -982,168 +131,13 @@ Disassembly of section .text: shrq $0x10, %rcx addq %rcx, %rax andq $0x7f, %rax - xorq %rcx, %rcx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x17, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - movabsq $-0x2, %rcx - andq %rax, %rcx - movq %rcx, %rdx - shrq $0x1, %rdx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rdx - subq %rdx, %rcx - movabsq $0x3333333333333333, %rdx # imm = 0x3333333333333333 - andq %rcx, %rdx - shrq $0x2, %rcx - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rcx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x4, %rdx - addq %rdx, %rcx - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rcx - movq %rcx, %rdx - shrq $0x8, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x10, %rdx - addq %rdx, %rcx - movq %rcx, %rdx - shrq $0x20, %rdx - addq %rdx, %rcx - andq $0x7f, %rcx - movslq %ecx, %rcx - movslq %eax, %rax - cmpq %rax, %rcx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x18, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xffff, %eax # imm = 0xFFFF - movabsq $-0x10001, %rcx # imm = 0xFFFEFFFF - andq %rcx, %rax - movq %rax, %rcx - shrq $0x1, %rcx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - andq %r11, %rcx - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x10, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - movl $0x19, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x7, %eax - movl $0x3, %ecx - movl $0x1, %edx - subq %rdx, %rax - movabsq $0x3333333333333333, %rdx # imm = 0x3333333333333333 - andq %rax, %rdx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rdx, %rax - movq %rax, %rdx - shrq $0x4, %rdx - addq %rdx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rdx - shrq $0x8, %rdx - addq %rdx, %rax - movq %rax, %rdx - shrq $0x10, %rdx - addq %rdx, %rax - movq %rax, %rdx - shrq $0x20, %rdx - addq %rdx, %rax - andq $0x7f, %rax movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax testq %rax, %rax - jne - movl $0x1a, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xf0f0f0f, %eax # imm = 0xF0F0F0F - movl $0x5050505, %ecx # imm = 0x5050505 - subq %rcx, %rax - movabsq $0x3333333333333333, %rcx # imm = 0x3333333333333333 - andq %rax, %rcx - shrq $0x2, %rax - movabsq $0x3333333333333333, %r11 # imm = 0x3333333333333333 - andq %r11, %rax - addq %rcx, %rax - movq %rax, %rcx - shrq $0x4, %rcx - addq %rcx, %rax - movabsq $0xf0f0f0f0f0f0f0f, %r11 # imm = 0xF0F0F0F0F0F0F0F - andq %r11, %rax - movq %rax, %rcx - shrq $0x8, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x10, %rcx - addq %rcx, %rax - movq %rax, %rcx - shrq $0x20, %rcx - addq %rcx, %rax - andq $0x7f, %rax - movl $0x10, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax sete %al movzbq %al, %rax testq %rax, %rax jne - movl $0x1b, %eax + movl $0x17, %eax addq $0x20, %rsp popq %rbp retq @@ -1176,10 +170,8 @@ Disassembly of section .text: shrq $0x20, %rcx addq %rcx, %rax andq $0x7f, %rax - movl $0x10, %ecx movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax + cmpq $0x10, %rax sete %al movzbq %al, %rax testq %rax, %rax @@ -1218,10 +210,8 @@ Disassembly of section .text: shrq $0x20, %rcx addq %rcx, %rax andq $0x7f, %rax - xorq %rcx, %rcx movslq %eax, %rax - movslq %ecx, %rcx - cmpq %rcx, %rax + testq %rax, %rax sete %al movzbq %al, %rax testq %rax, %rax @@ -1234,4 +224,100 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x7, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x9, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xa, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xb, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xc, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xd, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xe, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xf, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x10, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x11, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x12, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x13, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x14, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x18, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x19, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x1a, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x1b, %eax + addq $0x20, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/builtin_bswap_expect.aarch64.asm b/tests/snapshots/asm/builtin_bswap_expect.aarch64.asm index 367f9a005..0e1f2de7c 100644 --- a/tests/snapshots/asm/builtin_bswap_expect.aarch64.asm +++ b/tests/snapshots/asm/builtin_bswap_expect.aarch64.asm @@ -10,62 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] - mov x0, #0x200 // =512 - mov x1, #0x1 // =1 - orr x0, x0, x1 - cmp x0, #0x201 - b.eq - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x4000000 // =67108864 - mov x1, #0x30000 // =196608 - orr x0, x0, x1 - mov x1, #0x200 // =512 - orr x0, x0, x1 - mov x1, #0x1 // =1 - orr x0, x0, x1 - mov x17, #0x201 // =513 - movk x17, #0x403, lsl #16 - cmp x0, x17 - b.eq - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x800000000000000 // =576460752303423488 - mov x1, #0x7000000000000 // =1970324836974592 - orr x0, x0, x1 - mov x1, #0x60000000000 // =6597069766656 - orr x0, x0, x1 - mov x1, #0x500000000 // =21474836480 - orr x0, x0, x1 - mov x1, #0x4000000 // =67108864 - orr x0, x0, x1 - mov x1, #0x30000 // =196608 - orr x0, x0, x1 - mov x1, #0x200 // =512 - orr x0, x0, x1 - mov x1, #0x1 // =1 - orr x0, x0, x1 - mov x17, #0x201 // =513 - movk x17, #0x403, lsl #16 - movk x17, #0x605, lsl #32 - movk x17, #0x807, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x30]! + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0xccdd // =52445 movk x0, #0xaabb, lsl #16 stur w0, [x29, #-0x8] @@ -92,32 +39,32 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 ret mov x0, #0x5 // =5 - cmp x0, #0x5 - cset x1, eq - cmp x1, #0x1 - b.eq - mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 ret - cmp x0, #0x5 - b.eq mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp], #0x30 ret - cmp x0, #0x5 - b.eq brk #0 - mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret + b diff --git a/tests/snapshots/asm/builtin_bswap_expect.x64.asm b/tests/snapshots/asm/builtin_bswap_expect.x64.asm index 498a282dd..b827bdf94 100644 --- a/tests/snapshots/asm/builtin_bswap_expect.x64.asm +++ b/tests/snapshots/asm/builtin_bswap_expect.x64.asm @@ -14,50 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - movl $0x200, %eax # imm = 0x200 - movl $0x1, %ecx - orq %rcx, %rax - cmpq $0x201, %rax # imm = 0x201 - je - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - movl $0x4000000, %eax # imm = 0x4000000 - movl $0x30000, %ecx # imm = 0x30000 - orq %rcx, %rax - movl $0x200, %ecx # imm = 0x200 - orq %rcx, %rax - movl $0x1, %ecx - orq %rcx, %rax - cmpq $0x4030201, %rax # imm = 0x4030201 - je - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp - retq - movabsq $0x800000000000000, %rax # imm = 0x800000000000000 - movabsq $0x7000000000000, %rcx # imm = 0x7000000000000 - orq %rcx, %rax - movabsq $0x60000000000, %rcx # imm = 0x60000000000 - orq %rcx, %rax - movabsq $0x500000000, %rcx # imm = 0x500000000 - orq %rcx, %rax - movl $0x4000000, %ecx # imm = 0x4000000 - orq %rcx, %rax - movl $0x30000, %ecx # imm = 0x30000 - orq %rcx, %rax - movl $0x200, %ecx # imm = 0x200 - orq %rcx, %rax - movl $0x1, %ecx - orq %rcx, %rax - movabsq $0x807060504030201, %r11 # imm = 0x807060504030201 - cmpq %r11, %rax - je - movl $0x3, %eax - addq $0x10, %rsp - popq %rbp - retq movl $0xaabbccdd, %eax # imm = 0xAABBCCDD movl %eax, -0x8(%rbp) movl -0x8(%rbp), %eax @@ -84,26 +40,30 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movl $0x5, %eax - cmpq $0x5, %rax - sete %cl - movzbq %cl, %rcx - cmpq $0x1, %rcx - je - movl $0x5, %eax + xorq %rax, %rax addq $0x10, %rsp popq %rbp retq - cmpq $0x5, %rax - je - movl $0x6, %eax + movl $0x1, %eax addq $0x10, %rsp popq %rbp retq - cmpq $0x5, %rax - je - ud2 - xorq %rax, %rax + movl $0x2, %eax addq $0x10, %rsp popq %rbp retq + movl $0x3, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x10, %rsp + popq %rbp + retq + ud2 + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/builtin_frame_address.aarch64.asm b/tests/snapshots/asm/builtin_frame_address.aarch64.asm index 0c48d69ec..a890dbb31 100644 --- a/tests/snapshots/asm/builtin_frame_address.aarch64.asm +++ b/tests/snapshots/asm/builtin_frame_address.aarch64.asm @@ -10,26 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x40]! + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x0, #0x0 // =0 add x1, x29, #0x0 add x0, x29, #0x0 cmp x1, #0x0 b.ne mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret cmp x1, x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret sub x0, x29, #0x8 sub x1, x1, x0 @@ -44,13 +41,11 @@ Disassembly of section .text: cmp x1, x17 b.le mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret b diff --git a/tests/snapshots/asm/builtin_trap.aarch64.asm b/tests/snapshots/asm/builtin_trap.aarch64.asm index b2ba1ae4d..c55b52f21 100644 --- a/tests/snapshots/asm/builtin_trap.aarch64.asm +++ b/tests/snapshots/asm/builtin_trap.aarch64.asm @@ -10,22 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 cmp x0, #0x0 b.lt - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret brk #0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/c11_atomic_specifier.aarch64.asm b/tests/snapshots/asm/c11_atomic_specifier.aarch64.asm index b5455bdb1..2290d3cfb 100644 --- a/tests/snapshots/asm/c11_atomic_specifier.aarch64.asm +++ b/tests/snapshots/asm/c11_atomic_specifier.aarch64.asm @@ -15,47 +15,13 @@ Disassembly of section .text: sub sp, sp, #0x50 mov x0, #0xc8 // =200 sturb w0, [x29, #-0x8] - mov x0, #0x9c40 // =40000 - mov x1, #0x3344 // =13124 - movk x1, #0x1122, lsl #16 - mov x2, #0x7788 // =30600 - movk x2, #0x5566, lsl #16 - movk x2, #0x3344, lsl #32 - movk x2, #0x1122, lsl #48 - ldurb w3, [x29, #-0x8] + ldurb w0, [x29, #-0x8] mov x17, #0xc8 // =200 - eor x3, x3, x17 - mov w3, w3 - cmp x3, #0x0 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x9c40 // =40000 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x3344 // =13124 - movk x17, #0x1122, lsl #16 - cmp x1, x17 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x7788 // =30600 - movk x17, #0x5566, lsl #16 - movk x17, #0x3344, lsl #32 - movk x17, #0x1122, lsl #48 - cmp x2, x17 - b.eq - mov x0, #0x4 // =4 + mov x0, #0x1 // =1 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret @@ -87,26 +53,19 @@ Disassembly of section .text: movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 stur w0, [x29, #-0x30] - mov x0, #0x63 // =99 - mov x1, #0xd // =13 - sturh w1, [x29, #-0x40] - ldursw x1, [x29, #-0x30] + mov x0, #0xd // =13 + sturh w0, [x29, #-0x40] + ldursw x0, [x29, #-0x30] mov x17, #0xfff9 // =65529 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - cmp x1, x17 + cmp x0, x17 b.eq mov x0, #0x7 // =7 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x63 - b.eq - mov x0, #0x8 // =8 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret ldursh x0, [x29, #-0x40] cmp x0, #0xd b.eq @@ -128,3 +87,19 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x2 // =2 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/c11_atomic_specifier.x64.asm b/tests/snapshots/asm/c11_atomic_specifier.x64.asm index 5363dbf32..28d13f7e9 100644 --- a/tests/snapshots/asm/c11_atomic_specifier.x64.asm +++ b/tests/snapshots/asm/c11_atomic_specifier.x64.asm @@ -16,37 +16,12 @@ Disassembly of section .text: subq $0x50, %rsp movl $0xc8, %eax movb %al, -0x8(%rbp) - movl $0x9c40, %eax # imm = 0x9C40 - movl $0x11223344, %ecx # imm = 0x11223344 - movabsq $0x1122334455667788, %rdx # imm = 0x1122334455667788 - movzbq -0x8(%rbp), %rsi - xorq $0xc8, %rsi - movl %esi, %esi - testq %rsi, %rsi - je - movl $0x1, %eax - addq $0x50, %rsp - popq %rbp - retq - xorq $0x9c40, %rax # imm = 0x9C40 + movzbq -0x8(%rbp), %rax + xorq $0xc8, %rax movl %eax, %eax testq %rax, %rax je - movl $0x2, %eax - addq $0x50, %rsp - popq %rbp - retq - cmpq $0x11223344, %rcx # imm = 0x11223344 - je - movl $0x3, %eax - addq $0x50, %rsp - popq %rbp - retq - movabsq $0x1122334455667788, %r11 # imm = 0x1122334455667788 - movq %rdx, %rax - cmpq %r11, %rdx - je - movl $0x4, %eax + movl $0x1, %eax addq $0x50, %rsp popq %rbp retq @@ -73,22 +48,15 @@ Disassembly of section .text: retq movabsq $-0x7, %rax movl %eax, -0x30(%rbp) - movl $0x63, %eax - movl $0xd, %ecx - movw %cx, -0x40(%rbp) - movslq -0x30(%rbp), %rcx - cmpq $-0x7, %rcx + movl $0xd, %eax + movw %ax, -0x40(%rbp) + movslq -0x30(%rbp), %rax + cmpq $-0x7, %rax je movl $0x7, %eax addq $0x50, %rsp popq %rbp retq - cmpq $0x63, %rax - je - movl $0x8, %eax - addq $0x50, %rsp - popq %rbp - retq movswq -0x40(%rbp), %rax cmpq $0xd, %rax je @@ -110,3 +78,21 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + movl $0x2, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x50, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/c4.aarch64.asm b/tests/snapshots/asm/c4.aarch64.asm index 8436ad765..7a637b464 100644 --- a/tests/snapshots/asm/c4.aarch64.asm +++ b/tests/snapshots/asm/c4.aarch64.asm @@ -10,21 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x170 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - ldrb w1, [x1] - str x1, [x0] - cbz x1, + stp x20, x21, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + b adrp x0, add x0, x0, ldr x1, [x0] @@ -35,27 +25,10 @@ Disassembly of section .text: ldr x0, [x0] cmp x0, #0xa b.ne - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldr x0, [x0] cbz x0, - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x23 - b.ne - b adrp x0, add x0, x0, adrp x1, @@ -75,20 +48,6 @@ Disassembly of section .text: b adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x1 - str x1, [x0] - b - adrp x0, - add x0, x0, - ldr x0, [x0] - adrp x1, - add x1, x1, - ldr x1, [x1] - cmp x0, x1 - b.ge - adrp x0, - add x0, x0, adrp x1, add x1, x1, adrp x20, @@ -106,8 +65,6 @@ Disassembly of section .text: ldr x0, [x0] cmp x0, #0x7 b.gt - b - b adrp x0, add x0, x0, adrp x1, @@ -123,25 +80,37 @@ Disassembly of section .text: add x0, x0, bl sxtw x0, w0 - b - b - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x61 - cset x0, ge - mov x20, #0x0 // =0 - cbz x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + cmp x0, x1 + b.ge b adrp x0, add x0, x0, ldr x0, [x0] + cmp x0, #0x23 + b.ne + adrp x0, + add x0, x0, + ldr x0, [x0] ldrb w0, [x0] cmp x0, #0x0 - cset x20, ne - cbz x20, - b + cset x1, ne + cbz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + mov x17, #0xa // =10 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + cset x1, ne + cbz x1, adrp x0, add x0, x0, ldr x1, [x0] @@ -152,642 +121,341 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0xa // =10 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x20, ne - cbz x20, - b + cmp x0, #0x61 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x7a cset x0, le cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x41 cset x0, ge - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, - b - cbnz x21, - b adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x5a cset x0, le cmp x0, #0x0 - cset x20, ne - cmp x20, #0x0 - cset x21, ne - b + cset x2, ne + cmp x2, #0x0 + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x5f - cset x21, eq - cbz x21, - adrp x0, - add x0, x0, - ldr x0, [x0] - sub x20, x0, #0x1 - b - b + cset x1, eq + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x30 cset x1, ge cbz x1, - b adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x61 - cset x0, ge - mov x21, #0x0 // =0 - cbz x0, - b + cmp x0, #0x39 + cset x1, le + cbnz x1, adrp x0, add x0, x0, - ldr x1, [x0] - mov x17, #0x93 // =147 - mul x1, x1, x17 - adrp x2, - add x2, x2, - ldr x3, [x2] - add x4, x3, #0x1 - str x4, [x2] - ldrb w2, [x3] - add x1, x1, x2 - str x1, [x0] - b + ldr x0, [x0] + cmp x0, #0x2f + b.ne adrp x0, add x0, x0, - ldr x1, [x0] - lsl x1, x1, #6 - adrp x2, - add x2, x2, - ldr x2, [x2] - sub x2, x2, x20 - add x1, x1, x2 - str x1, [x0] + ldr x0, [x0] + ldrb w0, [x0] + mov x17, #0x2f // =47 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + b.ne adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] + ldr x1, [x0] + add x1, x1, #0x1 str x1, [x0] - b adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - cmp x0, #0x7a - cset x0, le cmp x0, #0x0 - cset x21, ne - mov x22, #0x1 // =1 - cbnz x21, + cset x1, ne + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - cmp x0, #0x41 - cset x0, ge - mov x21, #0x0 // =0 - cbz x0, + mov x17, #0xa // =10 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + cset x1, ne + cbz x1, + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x1 + str x1, [x0] b - mov x21, #0x1 // =1 - cbnz x22, b adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x5a - cset x0, le - cmp x0, #0x0 - cset x21, ne - cmp x21, #0x0 - cset x22, ne - b + cmp x0, #0x27 + cset x1, eq + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x30 - cset x0, ge - mov x21, #0x0 // =0 - cbz x0, - b - cbnz x21, - b + cmp x0, #0x22 + cset x1, eq + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x39 - cset x0, le - cmp x0, #0x0 - cset x21, ne - cmp x21, #0x0 - cset x21, ne - b + cmp x0, #0x3d + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0x5f // =95 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x21, eq - cbz x21, - b + cmp x0, #0x2b + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldr x0, [x0] - cbz x0, + cmp x0, #0x2d + b.eq adrp x0, add x0, x0, ldr x0, [x0] - adrp x1, - add x1, x1, - ldr x1, [x1] - ldr x1, [x1, #0x8] - cmp x0, x1 - cset x1, eq - cbz x1, - b + cmp x0, #0x21 + b.eq adrp x0, add x0, x0, - ldr x1, [x0] - str x20, [x1, #0x10] - ldr x1, [x0] - adrp x2, - add x2, x2, - ldr x3, [x2] - str x3, [x1, #0x8] ldr x0, [x0] - mov x1, #0x0 // =0 - mov x3, #0x85 // =133 - str x3, [x0] - str x3, [x2] - mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret + cmp x0, #0x3c + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldr x0, [x0, #0x10] - adrp x1, - add x1, x1, - ldr x1, [x1] - sub x2, x1, x20 - mov x1, x20 - bl - sxtw x0, w0 - cmp x0, #0x0 - cset x1, eq - cbz x1, + cmp x0, #0x3e + b.eq adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - mov x2, #0x0 // =0 - ldr x1, [x1] - str x1, [x0] - mov x0, x2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x48 - str x1, [x0] - b + ldr x0, [x0] + cmp x0, #0x7c + b.eq adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x39 - cset x1, le - cbz x1, - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - sub x1, x1, #0x30 - str x1, [x0] - cbz x1, - b - b + cmp x0, #0x26 + b.eq adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2f - b.ne - b - b + cmp x0, #0x5e + b.eq adrp x0, add x0, x0, - mov x1, #0x80 // =128 - str x1, [x0] - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret + ldr x0, [x0] + cmp x0, #0x25 + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0x78 // =120 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x1, eq - cbnz x1, - b + cmp x0, #0x2a + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x30 - cset x1, ge - cbz x1, - b + cmp x0, #0x5b + b.eq adrp x0, add x0, x0, - ldr x1, [x0] - mov x17, #0xa // =10 - mul x1, x1, x17 - adrp x2, - add x2, x2, - ldr x3, [x2] - add x4, x3, #0x1 - str x4, [x2] - ldrb w2, [x3] - add x1, x1, x2 - sub x1, x1, #0x30 - str x1, [x0] - b - b + ldr x0, [x0] + cmp x0, #0x3f + b.eq adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x39 - cset x1, le - cbz x1, - b + cmp x0, #0x7e + cset x0, eq + mov x2, #0x1 // =1 + cbnz x0, adrp x0, add x0, x0, ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0x58 // =88 - eor x0, x0, x17 - mov w0, w0 + cmp x0, #0x3b + cset x0, eq cmp x0, #0x0 - cset x1, eq - cbz x1, - b - b - b + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x2, [x1] - add x2, x2, #0x1 - str x2, [x1] - ldrb w1, [x2] - str x1, [x0] - cbz x1, - b + ldr x0, [x0] + cmp x0, #0x7b + cset x0, eq + cmp x0, #0x0 + cset x1, ne + mov x2, #0x1 // =1 + cbnz x1, adrp x0, add x0, x0, - ldr x1, [x0] - lsl x1, x1, #4 - adrp x2, - add x2, x2, - ldr x3, [x2] - mov x17, #0xf // =15 - and x4, x3, x17 - add x1, x1, x4 - cmp x3, #0x41 - b.lt - b - b + ldr x0, [x0] + cmp x0, #0x7d + cset x0, eq + cmp x0, #0x0 + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x30 - cset x0, ge - mov x2, #0x0 // =0 - cbz x0, - b - cbz x1, - b + cmp x0, #0x28 + cset x0, eq + cmp x0, #0x0 + cset x1, ne + mov x2, #0x1 // =1 + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x39 - cset x0, le + cmp x0, #0x29 + cset x0, eq cmp x0, #0x0 cset x2, ne - mov x3, #0x1 // =1 + mov x1, #0x1 // =1 cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x61 - cset x0, ge - mov x2, #0x0 // =0 - cbz x0, - b - mov x1, #0x1 // =1 - cbnz x3, - b + cmp x0, #0x5d + cset x0, eq + cmp x0, #0x0 + cset x1, ne + mov x2, #0x1 // =1 + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x66 - cset x0, le + cmp x0, #0x2c + cset x0, eq cmp x0, #0x0 cset x2, ne - cmp x2, #0x0 - cset x3, ne - b + cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x41 - cset x0, ge - mov x2, #0x0 // =0 - cbz x0, + cmp x0, #0x3a + cset x2, eq + cbz x2, + b + b + b b b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x46 - cset x0, le - cmp x0, #0x0 - cset x2, ne - cmp x2, #0x0 - cset x1, ne b - mov x3, #0x9 // =9 b - mov x3, #0x0 // =0 - add x1, x1, x3 - str x1, [x0] b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x30 - cset x1, ge - cbz x1, b - adrp x0, - add x0, x0, - ldr x1, [x0] - lsl x1, x1, #3 - adrp x2, - add x2, x2, - ldr x3, [x2] - add x4, x3, #0x1 - str x4, [x2] - ldrb w2, [x3] - add x1, x1, x2 - sub x1, x1, #0x30 - str x1, [x0] b b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x37 - cset x1, le - cbz x1, b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0x2f // =47 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.ne b b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x27 - cset x1, eq - cbnz x1, b adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x1 str x1, [x0] - b - b adrp x0, add x0, x0, - mov x1, #0xa0 // =160 + adrp x1, + add x1, x1, + ldr x1, [x1] + ldrb w1, [x1] str x1, [x0] + cbnz x1, mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - ldr x0, [x0] - ldrb w0, [x0] - cmp x0, #0x0 - cset x1, ne - cbz x1, - b + mov x1, #0x8f // =143 + str x1, [x0] + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x1 + mov x1, #0xa4 // =164 str x1, [x0] - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldrb w0, [x0] - mov x17, #0xa // =10 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x1, ne - cbz x1, - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x22 - cset x1, eq - cbz x1, + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret adrp x0, add x0, x0, - ldr x0, [x0] - b - b + mov x1, #0x9f // =159 + str x1, [x0] + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x3d - b.ne - b - adrp x1, - add x1, x1, - ldr x1, [x1] - ldrb w1, [x1] - cmp x1, #0x0 - cset x2, ne - cbz x2, - b - adrp x1, - add x1, x1, - adrp x2, - add x2, x2, - ldr x3, [x2] - add x4, x3, #0x1 - str x4, [x2] - ldrb w2, [x3] - str x2, [x1] - cmp x2, #0x5c - b.ne - b - adrp x1, - add x1, x1, - ldr x2, [x1] - add x2, x2, #0x1 - str x2, [x1] - adrp x1, - add x1, x1, - ldr x1, [x1] - cmp x1, #0x22 - b.ne - b - adrp x1, - add x1, x1, - ldr x1, [x1] - ldrb w1, [x1] - adrp x2, - add x2, x2, - ldr x2, [x2] - cmp x1, x2 - cset x2, ne - cbz x2, - b - adrp x1, - add x1, x1, - adrp x2, - add x2, x2, - ldr x3, [x2] - add x4, x3, #0x1 - str x4, [x2] - ldrb w2, [x3] - str x2, [x1] - cmp x2, #0x6e - b.ne - b - adrp x1, - add x1, x1, - ldr x1, [x1] - cmp x1, #0x22 - b.ne - b - adrp x1, - add x1, x1, - mov x2, #0xa // =10 - str x2, [x1] - b - adrp x1, - add x1, x1, - ldr x2, [x1] - add x3, x2, #0x1 - str x3, [x1] - adrp x1, - add x1, x1, - ldr x1, [x1] - strb w1, [x2] - b - adrp x1, - add x1, x1, - str x0, [x1] + mov x1, #0xa1 // =161 + str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x80 // =128 + mov x1, #0x93 // =147 str x1, [x0] - b + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x3d // =61 + mov x17, #0x26 // =38 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x2b - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -795,38 +463,27 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x95 // =149 + mov x1, #0x91 // =145 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x8e // =142 + mov x1, #0x94 // =148 str x1, [x0] b adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x2b // =43 + mov x17, #0x7c // =124 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x2d - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -834,38 +491,27 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0xa2 // =162 + mov x1, #0x90 // =144 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x9d // =157 + mov x1, #0x92 // =146 str x1, [x0] b adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x2d // =45 + mov x17, #0x3d // =61 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x21 - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -873,38 +519,22 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0xa3 // =163 + mov x1, #0x9a // =154 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x9e // =158 - str x1, [x0] - b - adrp x0, - add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x3d // =61 + mov x17, #0x3e // =62 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x3c - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -912,16 +542,14 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x96 // =150 + mov x1, #0x9c // =156 str x1, [x0] - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret + b + adrp x0, + add x0, x0, + mov x1, #0x98 // =152 + str x1, [x0] + b adrp x0, add x0, x0, ldr x0, [x0] @@ -931,14 +559,6 @@ Disassembly of section .text: mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x3e - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -949,12 +569,9 @@ Disassembly of section .text: mov x1, #0x99 // =153 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -989,14 +606,6 @@ Disassembly of section .text: mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x7c - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -1004,21 +613,18 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x9a // =154 + mov x1, #0x96 // =150 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x3e // =62 + mov x17, #0x2d // =45 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 @@ -1030,31 +636,27 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x9c // =156 + mov x1, #0xa3 // =163 str x1, [x0] - b + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret adrp x0, add x0, x0, - mov x1, #0x98 // =152 + mov x1, #0x9e // =158 str x1, [x0] b adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x7c // =124 + mov x17, #0x2b // =43 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x26 - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -1062,38 +664,27 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x90 // =144 + mov x1, #0xa2 // =162 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x92 // =146 + mov x1, #0x9d // =157 str x1, [x0] b adrp x0, add x0, x0, ldr x0, [x0] ldrb w0, [x0] - mov x17, #0x26 // =38 + mov x17, #0x3d // =61 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 b.ne - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x5e - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -1101,196 +692,480 @@ Disassembly of section .text: str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x91 // =145 + mov x1, #0x95 // =149 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, - mov x1, #0x94 // =148 + mov x1, #0x8e // =142 str x1, [x0] b adrp x0, add x0, x0, - mov x1, #0x93 // =147 - str x1, [x0] + ldr x0, [x0] + adrp x1, + add x1, x1, + ldr x1, [x1] + ldrb w1, [x1] + cmp x1, #0x0 + cset x2, ne + cbz x2, + adrp x1, + add x1, x1, + ldr x1, [x1] + ldrb w1, [x1] + adrp x2, + add x2, x2, + ldr x2, [x2] + cmp x1, x2 + cset x2, ne + cbz x2, + adrp x1, + add x1, x1, + adrp x2, + add x2, x2, + ldr x3, [x2] + add x4, x3, #0x1 + str x4, [x2] + ldrb w2, [x3] + str x2, [x1] + cmp x2, #0x5c + b.ne + adrp x1, + add x1, x1, + adrp x2, + add x2, x2, + ldr x3, [x2] + add x4, x3, #0x1 + str x4, [x2] + ldrb w2, [x3] + str x2, [x1] + cmp x2, #0x6e + b.ne + adrp x1, + add x1, x1, + mov x2, #0xa // =10 + str x2, [x1] + adrp x1, + add x1, x1, + ldr x1, [x1] + cmp x1, #0x22 + b.ne + adrp x1, + add x1, x1, + ldr x2, [x1] + add x3, x2, #0x1 + str x3, [x1] + adrp x1, + add x1, x1, + ldr x1, [x1] + strb w1, [x2] + b + b + adrp x1, + add x1, x1, + ldr x2, [x1] + add x2, x2, #0x1 + str x2, [x1] + adrp x1, + add x1, x1, + ldr x1, [x1] + cmp x1, #0x22 + b.ne + adrp x1, + add x1, x1, + str x0, [x1] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret - b adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x25 - b.ne + mov x1, #0x80 // =128 + str x1, [x0] + b adrp x0, add x0, x0, - mov x1, #0xa1 // =161 + mov x1, #0xa0 // =160 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret - b adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x2a - b.ne + adrp x1, + add x1, x1, + ldr x1, [x1] + sub x1, x1, #0x30 + str x1, [x0] + cbz x1, adrp x0, add x0, x0, - mov x1, #0x9f // =159 - str x1, [x0] - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret - b + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x30 + cset x1, ge + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x5b - b.ne + ldrb w0, [x0] + cmp x0, #0x39 + cset x1, le + cbz x1, adrp x0, add x0, x0, - mov x1, #0xa4 // =164 + ldr x1, [x0] + mov x17, #0xa // =10 + mul x1, x1, x17 + adrp x2, + add x2, x2, + ldr x3, [x2] + add x4, x3, #0x1 + str x4, [x2] + ldrb w2, [x3] + add x1, x1, x2 + sub x1, x1, #0x30 str x1, [x0] - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret + b b adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x3f - b.ne - adrp x0, - add x0, x0, - mov x1, #0x8f // =143 + mov x1, #0x80 // =128 str x1, [x0] mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x7e - cset x0, eq - mov x2, #0x1 // =1 - cbnz x0, + ldrb w0, [x0] + mov x17, #0x78 // =120 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + cset x1, eq + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x3b - cset x0, eq + ldrb w0, [x0] + mov x17, #0x58 // =88 + eor x0, x0, x17 + mov w0, w0 cmp x0, #0x0 - cset x2, ne - mov x1, #0x1 // =1 - cbnz x2, + cset x1, eq + cbz x1, + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x2, [x1] + add x2, x2, #0x1 + str x2, [x1] + ldrb w1, [x2] + str x1, [x0] + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x7b - cset x0, eq - cmp x0, #0x0 - cset x1, ne - mov x2, #0x1 // =1 - cbnz x1, + cmp x0, #0x30 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x7d - cset x0, eq + cmp x0, #0x39 + cset x0, le cmp x0, #0x0 cset x2, ne - mov x1, #0x1 // =1 + mov x3, #0x1 // =1 cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x28 - cset x0, eq - cmp x0, #0x0 - cset x1, ne - mov x2, #0x1 // =1 - cbnz x1, + cmp x0, #0x61 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x29 - cset x0, eq + cmp x0, #0x66 + cset x0, le cmp x0, #0x0 cset x2, ne + cmp x2, #0x0 + cset x3, ne mov x1, #0x1 // =1 - cbnz x2, + cbnz x3, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x5d - cset x0, eq - cmp x0, #0x0 - cset x1, ne - mov x2, #0x1 // =1 - cbnz x1, + cmp x0, #0x41 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2c - cset x0, eq + cmp x0, #0x46 + cset x0, le cmp x0, #0x0 cset x2, ne - cbnz x2, + cmp x2, #0x0 + cset x1, ne + cbz x1, adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x3a - cset x2, eq - cbz x2, - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret - b - b - b - b - b - b - b + ldr x1, [x0] + lsl x1, x1, #4 + adrp x2, + add x2, x2, + ldr x3, [x2] + mov x17, #0xf // =15 + and x4, x3, x17 + add x1, x1, x4 + cmp x3, #0x41 + b.lt + mov x3, #0x9 // =9 + add x1, x1, x3 + str x1, [x0] + b + mov x3, #0x0 // =0 + b + b + b + b + b + b + b + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x30 + cset x1, ge + cbz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x37 + cset x1, le + cbz x1, + adrp x0, + add x0, x0, + ldr x1, [x0] + lsl x1, x1, #3 + adrp x2, + add x2, x2, + ldr x3, [x2] + add x4, x3, #0x1 + str x4, [x2] + ldrb w2, [x3] + add x1, x1, x2 + sub x1, x1, #0x30 + str x1, [x0] + b + b + b + adrp x0, + add x0, x0, + ldr x0, [x0] + sub x20, x0, #0x1 + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x61 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x7a + cset x0, le + cmp x0, #0x0 + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x41 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x5a + cset x0, le + cmp x0, #0x0 + cset x2, ne + cmp x2, #0x0 + cset x1, ne + mov x2, #0x1 // =1 + cbnz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x30 + cset x0, ge + mov x2, #0x0 // =0 + cbz x0, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + cmp x0, #0x39 + cset x0, le + cmp x0, #0x0 + cset x2, ne + cmp x2, #0x0 + cset x2, ne + cbnz x2, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldrb w0, [x0] + mov x17, #0x5f // =95 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + cset x2, eq + cbz x2, + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x17, #0x93 // =147 + mul x1, x1, x17 + adrp x2, + add x2, x2, + ldr x3, [x2] + add x4, x3, #0x1 + str x4, [x2] + ldrb w2, [x3] + add x1, x1, x2 + str x1, [x0] + b + b + b + b + b + b + b + adrp x0, + add x0, x0, + ldr x1, [x0] + lsl x1, x1, #6 + adrp x2, + add x2, x2, + ldr x2, [x2] + sub x2, x2, x20 + add x1, x1, x2 + str x1, [x0] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + str x1, [x0] + b + adrp x0, + add x0, x0, + ldr x0, [x0] + adrp x1, + add x1, x1, + ldr x1, [x1] + ldr x1, [x1, #0x8] + cmp x0, x1 + cset x1, eq + cbz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0, #0x10] + adrp x1, + add x1, x1, + ldr x1, [x1] + sub x2, x1, x20 + mov x1, x20 + bl + sxtw x0, w0 + cmp x0, #0x0 + cset x1, eq + cbz x1, + b + b + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x48 + str x1, [x0] + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0] + cbnz x0, + adrp x0, + add x0, x0, + ldr x1, [x0] + str x20, [x1, #0x10] + ldr x1, [x0] + adrp x2, + add x2, x2, + ldr x3, [x2] + str x3, [x1, #0x8] + ldr x0, [x0] + mov x1, #0x0 // =0 + mov x3, #0x85 // =133 + str x3, [x0] + str x3, [x2] + mov x0, x1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + mov x2, #0x0 // =0 + ldr x1, [x1] + str x1, [x0] + mov x0, x2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + b + b + b + b + b + b + b + b + b + b b b b @@ -1320,14 +1195,11 @@ Disassembly of section .text: b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x100 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, x0 adrp x21, add x21, x21, @@ -1348,90 +1220,48 @@ Disassembly of section .text: bl sxtw x0, w0 b + adrp x0, + add x0, x0, + ldr x22, [x0] ldr x0, [x21] - cmp x0, #0x80 + cmp x0, #0x8e b.ne + bl adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x22, #0x1 // =1 - str x22, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] + ldr x0, [x0] + ldr x0, [x0] + cmp x0, #0xa + cset x1, eq + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] - str x0, [x1] - bl + ldr x0, [x0] + cmp x0, #0x9 + cset x1, eq + cbz x1, adrp x0, add x0, x0, - str x22, [x0] - b - ldr x0, [x21] - cmp x0, #0x22 - b.ne + ldr x0, [x0] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x8e // =142 + bl adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - adrp x0, - add x0, x0, - ldr x0, [x0] - str x0, [x1] - bl - b - b - ldr x0, [x21] - cmp x0, #0x8c - b.ne - b - ldr x0, [x21] - cmp x0, #0x22 - b.ne - bl - b - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - mov x17, #0xfff8 // =65528 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - and x1, x1, x17 - str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x2 // =2 - str x1, [x0] - b - bl - ldr x0, [x21] - cmp x0, #0x28 - b.ne - b - b - ldr x0, [x21] - cmp x0, #0x85 + str x22, [x0] + cmp x22, #0x0 b.ne + mov x2, #0xc // =12 + str x2, [x1] b - bl - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - ldr x0, [x21] - cmp x0, #0x8a - b.ne + mov x2, #0xb // =11 b adrp x0, add x0, x0, @@ -1447,29 +1277,9 @@ Disassembly of section .text: bl sxtw x0, w0 b - bl - b - ldr x0, [x21] - cmp x0, #0x86 - b.ne - bl - adrp x0, - add x0, x0, - mov x1, #0x0 // =0 - str x1, [x0] - b - ldr x0, [x21] - cmp x0, #0x9f - b.ne - bl - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x2 - str x1, [x0] b ldr x0, [x21] - cmp x0, #0x29 + cmp x0, #0x8f b.ne bl adrp x0, @@ -1477,16 +1287,35 @@ Disassembly of section .text: ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0x1 // =1 + mov x2, #0x4 // =4 str x2, [x1] ldr x1, [x0] add x22, x1, #0x8 str x22, [x0] - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x0 + mov x0, #0x8e // =142 + bl + ldr x0, [x21] + cmp x0, #0x3a b.ne + bl + adrp x23, + add x23, x23, + ldr x0, [x23] + add x0, x0, #0x18 + str x0, [x22] + ldr x0, [x23] + add x0, x0, #0x8 + str x0, [x23] + mov x1, #0x2 // =2 + str x1, [x0] + ldr x0, [x23] + add x22, x0, #0x8 + str x22, [x23] + mov x0, #0x8f // =143 + bl + ldr x0, [x23] + add x0, x0, #0x8 + str x0, [x22] b adrp x0, add x0, x0, @@ -1502,373 +1331,543 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x1, #0x1 // =1 - b - mov x1, #0x8 // =8 - str x1, [x22] + ldr x0, [x21] + cmp x0, #0x90 + b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x5 // =5 + str x1, [x0] + ldr x0, [x22] + add x23, x0, #0x8 + str x23, [x22] + mov x0, #0x91 // =145 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x23] adrp x0, add x0, x0, mov x1, #0x1 // =1 str x1, [x0] b - adrp x0, - add x0, x0, - ldr x22, [x0] - bl - ldr x0, [x21] - cmp x0, #0x28 - b.ne - b - b ldr x0, [x21] - cmp x0, #0x28 + cmp x0, #0x91 b.ne - b bl - mov x23, #0x0 // =0 - b - b - ldr x0, [x22, #0x18] - cmp x0, #0x80 - b.ne - b - ldr x0, [x21] - cmp x0, #0x29 - b.eq - mov x0, #0x8e // =142 + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x4 // =4 + str x1, [x0] + ldr x0, [x22] + add x23, x0, #0x8 + str x23, [x22] + mov x0, #0x92 // =146 bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x23] adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + mov x1, #0x1 // =1 str x1, [x0] - mov x0, #0xd // =13 - str x0, [x1] - add x23, x23, #0x1 + b ldr x0, [x21] - cmp x0, #0x2c + cmp x0, #0x92 b.ne - b bl - ldr x0, [x22, #0x18] - cmp x0, #0x82 - b.ne - b + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x93 // =147 bl - b + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xe // =14 + str x1, [x0] adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + mov x1, #0x1 // =1 str x1, [x0] - ldr x0, [x22, #0x28] - str x0, [x1] - cbz x23, b - ldr x0, [x22, #0x18] - cmp x0, #0x81 + ldr x0, [x21] + cmp x0, #0x93 b.ne - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 str x1, [x0] - mov x2, #0x3 // =3 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + mov x0, #0x94 // =148 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xf // =15 str x1, [x0] - ldr x0, [x22, #0x28] - str x0, [x1] - b adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] + mov x1, #0x1 // =1 + str x1, [x0] + b + ldr x0, [x21] + cmp x0, #0x94 + b.ne bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x95 // =149 bl - sxtw x0, w0 - b + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x10 // =16 + str x1, [x0] adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + mov x1, #0x1 // =1 str x1, [x0] - mov x2, #0x7 // =7 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + b + ldr x0, [x21] + cmp x0, #0x95 + b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x97 // =151 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x11 // =17 str x1, [x0] - str x23, [x1] adrp x0, add x0, x0, - ldr x1, [x22, #0x20] + mov x1, #0x1 // =1 str x1, [x0] b - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + ldr x0, [x21] + cmp x0, #0x96 + b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 str x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + mov x0, #0x97 // =151 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x12 // =18 str x1, [x0] - ldr x0, [x22, #0x28] - str x0, [x1] adrp x0, add x0, x0, - str x2, [x0] + mov x1, #0x1 // =1 + str x1, [x0] b - ldr x0, [x22, #0x18] - cmp x0, #0x84 + ldr x0, [x21] + cmp x0, #0x97 b.ne - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 str x1, [x0] - mov x2, #0x0 // =0 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + mov x0, #0x9b // =155 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x13 // =19 str x1, [x0] adrp x0, add x0, x0, - ldr x0, [x0] - ldr x2, [x22, #0x28] - sub x0, x0, x2 - str x0, [x1] - adrp x0, - add x0, x0, - ldr x1, [x0] - add x23, x1, #0x8 - str x23, [x0] - adrp x0, - add x0, x0, - ldr x1, [x22, #0x20] + mov x1, #0x1 // =1 str x1, [x0] - cmp x1, #0x0 - b.ne b - ldr x0, [x22, #0x18] - cmp x0, #0x83 + ldr x0, [x21] + cmp x0, #0x98 b.ne - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 str x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + mov x0, #0x9b // =155 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x14 // =20 str x1, [x0] - ldr x0, [x22, #0x28] - str x0, [x1] - b adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b - mov x1, #0xa // =10 - b - mov x1, #0x9 // =9 - str x1, [x23] - b - bl - ldr x0, [x21] - cmp x0, #0x8a - cset x22, eq - cbnz x22, - b + mov x1, #0x1 // =1 + str x1, [x0] b ldr x0, [x21] - cmp x0, #0x9f + cmp x0, #0x99 b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x9b // =155 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x15 // =21 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] b ldr x0, [x21] - cmp x0, #0x86 - cset x22, eq - cbz x22, - ldr x0, [x21] - cmp x0, #0x8a + cmp x0, #0x9a b.ne - b - b - mov x0, #0x8e // =142 bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x9b // =155 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x16 // =22 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] + b ldr x0, [x21] - cmp x0, #0x29 + cmp x0, #0x9b b.ne - b - mov x22, #0x1 // =1 - b - mov x22, #0x0 // =0 bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x9d // =157 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x17 // =23 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] + b ldr x0, [x21] - cmp x0, #0x9f + cmp x0, #0x9c b.ne bl - add x22, x22, #0x2 + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0x9d // =157 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x18 // =24 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] b ldr x0, [x21] - cmp x0, #0x29 + cmp x0, #0x9d b.ne bl - mov x0, #0xa2 // =162 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0xd // =13 + str x0, [x1] + mov x0, #0x9f // =159 bl adrp x0, add x0, x0, str x22, [x0] - b + cmp x22, #0x2 + b.le adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b - bl - b + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0xd // =13 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x8 // =8 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x1b // =27 + str x0, [x1] adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x19 // =25 + str x0, [x1] b + ldr x0, [x21] + cmp x0, #0x9e + b.ne bl - mov x0, #0xa2 // =162 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0xd // =13 + str x0, [x1] + mov x0, #0x9f // =159 bl + cmp x22, #0x2 + cset x1, gt + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x1 - b.le - b - b - ldr x0, [x21] - cmp x0, #0x94 - b.ne - b + cmp x22, x0 + cset x1, eq + cbz x1, adrp x0, add x0, x0, ldr x1, [x0] - sub x1, x1, #0x2 + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1a // =26 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + mov x2, #0xd // =13 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x3, #0x8 // =8 + str x3, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x1c // =28 + str x0, [x1] + adrp x0, + add x0, x0, + str x2, [x0] + b adrp x0, add x0, x0, - ldr x1, [x0] - add x22, x1, #0x8 str x22, [x0] + cmp x22, #0x2 + b.le adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x0 - b.ne + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0xd // =13 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x8 // =8 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1b // =27 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x1a // =26 + str x0, [x1] b adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b - mov x1, #0xa // =10 + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x1a // =26 + str x0, [x1] b - mov x1, #0x9 // =9 - str x1, [x22] b + ldr x0, [x21] + cmp x0, #0x9f + b.ne bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] mov x0, #0xa2 // =162 bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x1b // =27 + str x1, [x0] adrp x0, add x0, x0, - ldr x0, [x0] - ldr x0, [x0] - cmp x0, #0xa - cset x22, eq - cbnz x22, + mov x1, #0x1 // =1 + str x1, [x0] b + ldr x0, [x21] + cmp x0, #0xa0 + b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0xa2 // =162 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x1c // =28 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] b ldr x0, [x21] - cmp x0, #0x21 + cmp x0, #0xa1 b.ne + bl + adrp x22, + add x22, x22, + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0xd // =13 + str x1, [x0] + mov x0, #0xa2 // =162 + bl + ldr x0, [x22] + add x0, x0, #0x8 + str x0, [x22] + mov x1, #0x1d // =29 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] b + ldr x0, [x21] + cmp x0, #0xa2 + cset x1, eq + cbnz x1, + ldr x0, [x21] + cmp x0, #0xa3 + cset x1, eq + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] ldr x0, [x0] - cmp x0, #0x9 - cset x22, eq - cbz x22, + cmp x0, #0xa + b.ne adrp x0, add x0, x0, ldr x1, [x0] - sub x1, x1, #0x8 - str x1, [x0] - adrp x0, - add x0, x0, + mov x2, #0xd // =13 + str x2, [x1] ldr x1, [x0] - add x1, x1, #0x2 + add x1, x1, #0x8 str x1, [x0] - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b - bl - mov x0, #0xa2 // =162 - bl + mov x0, #0xa // =10 + str x0, [x1] adrp x0, add x0, x0, ldr x1, [x0] @@ -1884,142 +1883,95 @@ Disassembly of section .text: ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x3, #0x0 // =0 - str x3, [x1] + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x2 + b.le + mov x2, #0x8 // =8 + str x2, [x1] + adrp x0, + add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x11 // =17 - str x0, [x1] - adrp x0, - add x0, x0, - str x2, [x0] - b ldr x0, [x21] - cmp x0, #0x7e + cmp x0, #0xa2 b.ne - bl - mov x0, #0xa2 // =162 - bl + mov x2, #0x19 // =25 + str x2, [x1] adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0xd // =13 + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x0 + b.ne + mov x2, #0xc // =12 str x2, [x1] + adrp x0, + add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0x1 // =1 + mov x2, #0xd // =13 str x2, [x1] ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x3, #0xffff // =65535 - movk x3, #0xffff, lsl #16 - movk x3, #0xffff, lsl #32 - movk x3, #0xffff, lsl #48 - str x3, [x1] + mov x2, #0x1 // =1 + str x2, [x1] ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0xf // =15 - str x0, [x1] - adrp x0, - add x0, x0, - str x2, [x0] - b - ldr x0, [x21] - cmp x0, #0x9d - b.ne - bl - mov x0, #0xa2 // =162 - bl adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - b - ldr x0, [x21] - cmp x0, #0x9e - b.ne - bl + ldr x0, [x0] + cmp x0, #0x2 + b.le + mov x2, #0x8 // =8 + str x2, [x1] adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x1 // =1 - str x0, [x1] ldr x0, [x21] - cmp x0, #0x80 + cmp x0, #0xa2 b.ne + mov x2, #0x1a // =26 + str x2, [x1] + bl b + mov x2, #0x19 // =25 b - ldr x0, [x21] - cmp x0, #0xa2 - cset x22, eq - cbnz x22, + mov x2, #0x1 // =1 b - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - adrp x0, - add x0, x0, - ldr x0, [x0] - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - str x0, [x1] - bl - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + mov x2, #0xb // =11 b - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - str x1, [x0] - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0xa2 // =162 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x1b // =27 - str x1, [x0] + mov x2, #0x1a // =26 + b + mov x2, #0x1 // =1 b - ldr x0, [x21] - cmp x0, #0xa3 - cset x22, eq - cbz x22, - ldr x22, [x21] - bl - mov x0, #0xa2 // =162 - bl adrp x0, add x0, x0, ldr x0, [x0] ldr x0, [x0] - cmp x0, #0xa + cmp x0, #0x9 b.ne - b + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x2, #0xd // =13 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x9 // =9 + str x0, [x1] b adrp x0, add x0, x0, @@ -2035,16 +1987,25 @@ Disassembly of section .text: bl sxtw x0, w0 b + ldr x0, [x21] + cmp x0, #0xa4 + b.ne + bl adrp x0, add x0, x0, ldr x1, [x0] - mov x2, #0xd // =13 - str x2, [x1] - ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0xa // =10 + mov x0, #0xd // =13 str x0, [x1] + mov x0, #0x8e // =142 + bl + ldr x0, [x21] + cmp x0, #0x5d + b.ne + bl + cmp x22, #0x2 + b.le adrp x0, add x0, x0, ldr x1, [x0] @@ -2058,36 +2019,73 @@ Disassembly of section .text: mov x2, #0x1 // =1 str x2, [x1] ldr x1, [x0] - add x23, x1, #0x8 - str x23, [x0] - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x2 - b.le - b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldr x0, [x0] - cmp x0, #0x9 - b.ne + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x8 // =8 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x1b // =27 + str x0, [x1] adrp x0, add x0, x0, ldr x1, [x0] - mov x2, #0xd // =13 + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x19 // =25 str x2, [x1] ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x9 // =9 - str x0, [x1] + adrp x0, + add x0, x0, + sub x2, x22, #0x2 + str x2, [x0] + cmp x2, #0x0 + b.ne + mov x2, #0xa // =10 + str x2, [x1] + b + mov x2, #0x9 // =9 + b + cmp x22, #0x2 + b.ge + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 + b + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 + b b adrp x0, add x0, x0, adrp x1, add x1, x1, ldr x1, [x1] + ldr x2, [x21] bl sxtw x0, w0 mov x0, #0xffff // =65535 @@ -2096,94 +2094,128 @@ Disassembly of section .text: movk x0, #0xffff, lsl #48 bl sxtw x0, w0 - b - mov x1, #0x8 // =8 - b - mov x1, #0x1 // =1 - str x1, [x23] + ldr x0, [x21] + cmp x0, x20 + b.ge + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 + ret + ldr x0, [x21] + cmp x0, #0x80 + b.ne adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - cmp x22, #0xa2 - b.ne - mov x2, #0x19 // =25 + mov x22, #0x1 // =1 + str x22, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + adrp x0, + add x0, x0, + ldr x0, [x0] + str x0, [x1] + bl + adrp x0, + add x0, x0, + str x22, [x0] b - mov x2, #0x1a // =26 - str x2, [x1] + ldr x0, [x21] + cmp x0, #0x22 + b.ne adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x0 - b.ne - mov x2, #0xc // =12 - b - mov x2, #0xb // =11 - str x2, [x1] + str x0, [x1] + bl b + bl ldr x0, [x21] - cmp x0, x20 - b.lt + cmp x0, #0x22 + b.eq adrp x0, add x0, x0, - ldr x22, [x0] + ldr x1, [x0] + add x1, x1, #0x8 + mov x17, #0xfff8 // =65528 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + and x1, x1, x17 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x2 // =2 + str x1, [x0] + b ldr x0, [x21] - cmp x0, #0x8e + cmp x0, #0x8c + b.ne + bl + ldr x0, [x21] + cmp x0, #0x28 b.ne - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 - ret bl adrp x0, add x0, x0, - ldr x0, [x0] - ldr x0, [x0] - cmp x0, #0xa - cset x23, eq - cbnz x23, - b - b + mov x1, #0x1 // =1 + str x1, [x0] ldr x0, [x21] - cmp x0, #0x8f + cmp x0, #0x8a b.ne + bl b + bl adrp x0, add x0, x0, - ldr x0, [x0] - ldr x0, [x0] - cmp x0, #0x9 - cset x23, eq - cbz x23, - adrp x0, - add x0, x0, - ldr x0, [x0] - mov x1, #0xd // =13 + ldr x1, [x0] + add x1, x1, #0x2 str x1, [x0] - mov x0, #0x8e // =142 + ldr x0, [x21] + cmp x0, #0x9f + b.eq + ldr x0, [x21] + cmp x0, #0x29 + b.ne bl adrp x0, add x0, x0, ldr x1, [x0] - add x23, x1, #0x8 - str x23, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] adrp x0, add x0, x0, - str x22, [x0] - cmp x22, #0x0 + ldr x0, [x0] + cmp x0, #0x0 b.ne + mov x2, #0x1 // =1 + str x2, [x1] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] + b + mov x2, #0x8 // =8 b adrp x0, add x0, x0, @@ -2199,52 +2231,14 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x1, #0xc // =12 - b - mov x1, #0xb // =11 - str x1, [x23] - b - bl - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x4 // =4 - str x2, [x1] - ldr x1, [x0] - add x22, x1, #0x8 - str x22, [x0] - mov x0, #0x8e // =142 - bl - ldr x0, [x21] - cmp x0, #0x3a - b.ne - b - b ldr x0, [x21] - cmp x0, #0x90 + cmp x0, #0x86 b.ne - b bl - adrp x23, - add x23, x23, - ldr x0, [x23] - add x0, x0, #0x18 - str x0, [x22] - ldr x0, [x23] - add x0, x0, #0x8 - str x0, [x23] - mov x1, #0x2 // =2 + adrp x0, + add x0, x0, + mov x1, #0x0 // =0 str x1, [x0] - ldr x0, [x23] - add x22, x0, #0x8 - str x22, [x23] - mov x0, #0x8f // =143 - bl - ldr x0, [x23] - add x0, x0, #0x8 - str x0, [x22] b adrp x0, add x0, x0, @@ -2260,393 +2254,351 @@ Disassembly of section .text: bl sxtw x0, w0 b - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x5 // =5 - str x1, [x0] - ldr x0, [x22] - add x23, x0, #0x8 - str x23, [x22] - mov x0, #0x91 // =145 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x23] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - b - ldr x0, [x21] - cmp x0, #0x91 - b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x4 // =4 - str x1, [x0] - ldr x0, [x22] - add x23, x0, #0x8 - str x23, [x22] - mov x0, #0x92 // =146 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x23] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - b - ldr x0, [x21] - cmp x0, #0x92 - b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x93 // =147 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xe // =14 - str x1, [x0] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - b ldr x0, [x21] - cmp x0, #0x93 + cmp x0, #0x85 b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x94 // =148 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xf // =15 - str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] - b + ldr x22, [x0] + bl ldr x0, [x21] - cmp x0, #0x94 + cmp x0, #0x28 b.ne bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x95 // =149 + mov x23, #0x0 // =0 + b + mov x0, #0x8e // =142 bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x10 // =16 - str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x1 // =1 + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] - b + mov x0, #0xd // =13 + str x0, [x1] + add x23, x23, #0x1 ldr x0, [x21] - cmp x0, #0x95 + cmp x0, #0x2c b.ne bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x97 // =151 + ldr x0, [x21] + cmp x0, #0x29 + b.ne bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x11 // =17 + ldr x0, [x22, #0x18] + cmp x0, #0x82 + b.ne + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + ldr x0, [x22, #0x28] + str x0, [x1] + cbz x23, adrp x0, add x0, x0, - mov x1, #0x1 // =1 + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x2, #0x7 // =7 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + str x23, [x1] + adrp x0, + add x0, x0, + ldr x1, [x22, #0x20] str x1, [x0] b - ldr x0, [x21] - cmp x0, #0x96 + ldr x0, [x22, #0x18] + cmp x0, #0x81 b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] - mov x0, #0x97 // =151 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x12 // =18 + mov x2, #0x3 // =3 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + ldr x0, [x22, #0x28] + str x0, [x1] + b adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 b - ldr x0, [x21] - cmp x0, #0x97 + ldr x0, [x22, #0x18] + cmp x0, #0x80 b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] - mov x0, #0x9b // =155 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x13 // =19 + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + ldr x0, [x22, #0x28] + str x0, [x1] adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + str x2, [x0] b - ldr x0, [x21] - cmp x0, #0x98 + ldr x0, [x22, #0x18] + cmp x0, #0x84 b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] - mov x0, #0x9b // =155 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x14 // =20 + mov x2, #0x0 // =0 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x1 // =1 + ldr x0, [x0] + ldr x2, [x22, #0x28] + sub x0, x0, x2 + str x0, [x1] + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + adrp x0, + add x0, x0, + ldr x2, [x22, #0x20] + str x2, [x0] + cmp x2, #0x0 + b.ne + mov x2, #0xa // =10 + str x2, [x1] b - ldr x0, [x21] - cmp x0, #0x99 + mov x2, #0x9 // =9 + b + ldr x0, [x22, #0x18] + cmp x0, #0x83 b.ne - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] - mov x0, #0x9b // =155 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x15 // =21 + mov x2, #0x1 // =1 + str x2, [x1] + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] + ldr x0, [x22, #0x28] + str x0, [x1] + b adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 b ldr x0, [x21] - cmp x0, #0x9a + cmp x0, #0x28 b.ne bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x9b // =155 + ldr x0, [x21] + cmp x0, #0x8a + cset x1, eq + cbnz x1, + ldr x0, [x21] + cmp x0, #0x86 + cset x1, eq + cbz x1, + ldr x0, [x21] + cmp x0, #0x8a + b.ne + mov x22, #0x1 // =1 bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x16 // =22 - str x1, [x0] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] b + bl + add x22, x22, #0x2 + ldr x0, [x21] + cmp x0, #0x9f + b.eq ldr x0, [x21] - cmp x0, #0x9b + cmp x0, #0x29 b.ne bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x9d // =157 + mov x0, #0xa2 // =162 bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x17 // =23 - str x1, [x0] adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + str x22, [x0] + b + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 + b + mov x22, #0x0 // =0 b + mov x0, #0x8e // =142 + bl ldr x0, [x21] - cmp x0, #0x9c + cmp x0, #0x29 b.ne bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0x9d // =157 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x18 // =24 - str x1, [x0] + b adrp x0, add x0, x0, - mov x1, #0x1 // =1 - str x1, [x0] + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 + b b ldr x0, [x21] - cmp x0, #0x9d + cmp x0, #0x9f b.ne bl + mov x0, #0xa2 // =162 + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x1 + b.le + adrp x0, + add x0, x0, + ldr x1, [x0] + sub x1, x1, #0x2 + str x1, [x0] adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0xd // =13 - str x0, [x1] - mov x0, #0x9f // =159 - bl adrp x0, add x0, x0, - str x22, [x0] - cmp x22, #0x2 - b.le + ldr x0, [x0] + cmp x0, #0x0 + b.ne + mov x2, #0xa // =10 + str x2, [x1] b + mov x2, #0x9 // =9 + b + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 b ldr x0, [x21] - cmp x0, #0x9e + cmp x0, #0x94 b.ne - b + bl + mov x0, #0xa2 // =162 + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0] + cmp x0, #0xa + cset x1, eq + cbnz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0] + cmp x0, #0x9 + cset x1, eq + cbz x1, adrp x0, add x0, x0, ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0xd // =13 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x8 // =8 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 + sub x1, x1, #0x8 str x1, [x0] - mov x0, #0x1b // =27 - str x0, [x1] adrp x0, add x0, x0, ldr x1, [x0] - add x1, x1, #0x8 + add x1, x1, #0x2 str x1, [x0] - mov x0, #0x19 // =25 - str x0, [x1] b - bl adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x0, #0xd // =13 - str x0, [x1] - mov x0, #0x9f // =159 + adrp x1, + add x1, x1, + ldr x1, [x1] bl - cmp x22, #0x2 - cset x23, gt - cbz x23, + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 b b ldr x0, [x21] - cmp x0, #0x9f + cmp x0, #0x21 b.ne - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x22, x0 - cset x23, eq - cbz x23, + bl + mov x0, #0xa2 // =162 + bl adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0x1a // =26 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] mov x2, #0xd // =13 str x2, [x1] ldr x1, [x0] @@ -2657,22 +2609,23 @@ Disassembly of section .text: ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x3, #0x8 // =8 + mov x3, #0x0 // =0 str x3, [x1] ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x1c // =28 + mov x0, #0x11 // =17 str x0, [x1] adrp x0, add x0, x0, str x2, [x0] b - adrp x0, - add x0, x0, - str x22, [x0] - cmp x22, #0x2 - b.le + ldr x0, [x21] + cmp x0, #0x7e + b.ne + bl + mov x0, #0xa2 // =162 + bl adrp x0, add x0, x0, ldr x1, [x0] @@ -2688,76 +2641,75 @@ Disassembly of section .text: ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x2, #0x8 // =8 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x1b // =27 - str x2, [x1] + mov x3, #0xffff // =65535 + movk x3, #0xffff, lsl #16 + movk x3, #0xffff, lsl #32 + movk x3, #0xffff, lsl #48 + str x3, [x1] ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x1a // =26 + mov x0, #0xf // =15 str x0, [x1] + adrp x0, + add x0, x0, + str x2, [x0] + b + ldr x0, [x21] + cmp x0, #0x9d + b.ne + bl + mov x0, #0xa2 // =162 + bl + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str x1, [x0] b + ldr x0, [x21] + cmp x0, #0x9e + b.ne + bl adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0x1a // =26 + mov x0, #0x1 // =1 str x0, [x1] - b - bl - adrp x22, - add x22, x22, - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0xa2 // =162 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x1b // =27 + ldr x0, [x21] + cmp x0, #0x80 + b.ne + adrp x0, + add x0, x0, + ldr x1, [x0] + add x1, x1, #0x8 str x1, [x0] adrp x0, add x0, x0, + ldr x0, [x0] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + mul x0, x0, x17 + str x0, [x1] + bl + adrp x0, + add x0, x0, mov x1, #0x1 // =1 str x1, [x0] b - ldr x0, [x21] - cmp x0, #0xa0 - b.ne - bl adrp x22, add x22, x22, ldr x0, [x22] add x0, x0, #0x8 str x0, [x22] - mov x1, #0xd // =13 - str x1, [x0] - mov x0, #0xa2 // =162 - bl - ldr x0, [x22] - add x0, x0, #0x8 - str x0, [x22] - mov x1, #0x1c // =28 - str x1, [x0] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 + mov x1, #0xffff // =65535 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 str x1, [x0] - b - ldr x0, [x21] - cmp x0, #0xa1 - b.ne - bl - adrp x22, - add x22, x22, ldr x0, [x22] add x0, x0, #0x8 str x0, [x22] @@ -2768,33 +2720,27 @@ Disassembly of section .text: ldr x0, [x22] add x0, x0, #0x8 str x0, [x22] - mov x1, #0x1d // =29 - str x1, [x0] - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 + mov x1, #0x1b // =27 str x1, [x0] b ldr x0, [x21] cmp x0, #0xa2 - cset x23, eq - cbnz x23, + cset x1, eq + cbnz x1, ldr x0, [x21] cmp x0, #0xa3 - cset x23, eq - cbz x23, + cset x1, eq + cbz x1, + ldr x22, [x21] + bl + mov x0, #0xa2 // =162 + bl adrp x0, add x0, x0, ldr x0, [x0] ldr x0, [x0] cmp x0, #0xa b.ne - b - b - ldr x0, [x21] - cmp x0, #0xa4 - b.ne - b adrp x0, add x0, x0, ldr x1, [x0] @@ -2818,60 +2764,23 @@ Disassembly of section .text: mov x2, #0x1 // =1 str x2, [x1] ldr x1, [x0] - add x22, x1, #0x8 - str x22, [x0] + add x1, x1, #0x8 + str x1, [x0] adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x2 b.le - b - adrp x0, - add x0, x0, - ldr x0, [x0] - ldr x0, [x0] - cmp x0, #0x9 - b.ne - adrp x0, - add x0, x0, - ldr x1, [x0] - mov x2, #0xd // =13 + mov x2, #0x8 // =8 str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x0, #0x9 // =9 - str x0, [x1] - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b - mov x1, #0x8 // =8 - b - mov x1, #0x1 // =1 - str x1, [x22] adrp x0, add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - ldr x0, [x21] - cmp x0, #0xa2 + cmp x22, #0xa2 b.ne mov x2, #0x19 // =25 - b - mov x2, #0x1a // =26 str x2, [x1] adrp x0, add x0, x0, @@ -2884,68 +2793,36 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x2, #0xc // =12 + str x2, [x1] b mov x2, #0xb // =11 - str x2, [x1] - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0xd // =13 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] + b + mov x2, #0x1a // =26 + b mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] + b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2 - b.le - mov x2, #0x8 // =8 - b - mov x2, #0x1 // =1 - str x2, [x1] + ldr x0, [x0] + cmp x0, #0x9 + b.ne adrp x0, add x0, x0, ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - ldr x0, [x21] - cmp x0, #0xa2 - b.ne - mov x2, #0x1a // =26 - b - mov x2, #0x19 // =25 + mov x2, #0xd // =13 str x2, [x1] - bl - b - bl - adrp x0, - add x0, x0, ldr x1, [x0] add x1, x1, #0x8 str x1, [x0] - mov x0, #0xd // =13 + mov x0, #0x9 // =9 str x0, [x1] - mov x0, #0x8e // =142 - bl - ldr x0, [x21] - cmp x0, #0x5d - b.ne - b b adrp x0, add x0, x0, adrp x1, add x1, x1, ldr x1, [x1] - ldr x2, [x21] bl sxtw x0, w0 mov x0, #0xffff // =65535 @@ -2955,10 +2832,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - bl - cmp x22, #0x2 - b.le - b adrp x0, add x0, x0, adrp x1, @@ -2973,65 +2846,48 @@ Disassembly of section .text: bl sxtw x0, w0 b - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0xd // =13 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x8 // =8 - str x2, [x1] - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x0, #0x1b // =27 - str x0, [x1] - adrp x0, - add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x2, #0x19 // =25 - str x2, [x1] - ldr x1, [x0] - add x23, x1, #0x8 - str x23, [x0] - adrp x0, - add x0, x0, - sub x1, x22, #0x2 - str x1, [x0] - cmp x1, #0x0 - b.ne b - cmp x22, #0x2 - b.ge - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 b - mov x1, #0xa // =10 b - mov x1, #0x9 // =9 - str x1, [x23] + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b b b b @@ -3041,13 +2897,11 @@ Disassembly of section .text: b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 adrp x20, add x20, x20, ldr x0, [x20] @@ -3055,42 +2909,14 @@ Disassembly of section .text: b.ne bl ldr x0, [x20] - cmp x0, #0x28 - b.ne - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - ldr x0, [x20] - cmp x0, #0x8d + cmp x0, #0x28 b.ne - b bl mov x0, #0x8e // =142 bl ldr x0, [x20] cmp x0, #0x29 b.ne - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b bl adrp x0, add x0, x0, @@ -3106,21 +2932,6 @@ Disassembly of section .text: ldr x0, [x20] cmp x0, #0x87 b.ne - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - bl - sxtw x0, w0 - b adrp x0, add x0, x0, ldr x1, [x0] @@ -3141,27 +2952,26 @@ Disassembly of section .text: ldr x0, [x0] add x0, x0, #0x8 str x0, [x21] + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 + ret b - bl adrp x0, add x0, x0, - ldr x0, [x0] - add x21, x0, #0x8 - ldr x0, [x20] - cmp x0, #0x28 - b.ne - b - b - ldr x0, [x20] - cmp x0, #0x8b - b.ne - b + adrp x1, + add x1, x1, + ldr x1, [x1] bl - mov x0, #0x8e // =142 + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 bl - ldr x0, [x20] - cmp x0, #0x29 - b.ne + sxtw x0, w0 b adrp x0, add x0, x0, @@ -3177,6 +2987,23 @@ Disassembly of section .text: bl sxtw x0, w0 b + ldr x0, [x20] + cmp x0, #0x8d + b.ne + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + add x21, x0, #0x8 + ldr x0, [x20] + cmp x0, #0x28 + b.ne + bl + mov x0, #0x8e // =142 + bl + ldr x0, [x20] + cmp x0, #0x29 + b.ne bl adrp x20, add x20, x20, @@ -3216,16 +3043,27 @@ Disassembly of section .text: bl sxtw x0, w0 b + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] bl - ldr x0, [x20] - cmp x0, #0x3b - b.eq - b + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + sxtw x0, w0 b ldr x0, [x20] - cmp x0, #0x7b + cmp x0, #0x8b b.ne - b + bl + ldr x0, [x20] + cmp x0, #0x3b + b.eq mov x0, #0x8e // =142 bl adrp x0, @@ -3254,20 +3092,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - bl - b - b ldr x0, [x20] - cmp x0, #0x3b + cmp x0, #0x7b b.ne + bl b + bl ldr x0, [x20] cmp x0, #0x7d - b.eq - bl - b + b.ne bl b + ldr x0, [x20] + cmp x0, #0x3b + b.ne bl b mov x0, #0x8e // =142 @@ -3292,27 +3130,27 @@ Disassembly of section .text: sxtw x0, w0 b b + b + b + b + b + b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x130 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] - str x26, [sp, #0x30] - str x27, [sp, #0x38] + stp x20, x21, [sp, #-0x140]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] str x19, [sp, #0x40] - sub x21, x0, #0x1 - add x22, x1, #0x8 - cmp x21, #0x0 + stp x29, x30, [sp, #0x130] + add x29, sp, #0x130 + sub x20, x0, #0x1 + add x21, x1, #0x8 + cmp x20, #0x0 cset x0, gt - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, - ldr x0, [x22] + ldr x0, [x21] ldrb w0, [x0] mov x17, #0x2d // =45 eor x0, x0, x17 @@ -3320,27 +3158,27 @@ Disassembly of section .text: cmp x0, #0x0 cset x0, eq cmp x0, #0x0 - cset x20, ne - cbz x20, - ldr x0, [x22] + cset x2, ne + cbz x2, + ldr x0, [x21] ldrb w0, [x0, #0x1] mov x17, #0x73 // =115 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x20, eq - cbz x20, + cset x2, eq + cbz x2, adrp x0, add x0, x0, mov x1, #0x1 // =1 str x1, [x0] - sub x21, x21, #0x1 - add x22, x22, #0x8 - cmp x21, #0x0 + sub x20, x20, #0x1 + add x21, x21, #0x8 + cmp x20, #0x0 cset x0, gt - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, - ldr x0, [x22] + ldr x0, [x21] ldrb w0, [x0] mov x17, #0x2d // =45 eor x0, x0, x17 @@ -3348,23 +3186,23 @@ Disassembly of section .text: cmp x0, #0x0 cset x0, eq cmp x0, #0x0 - cset x20, ne - cbz x20, - ldr x0, [x22] + cset x2, ne + cbz x2, + ldr x0, [x21] ldrb w0, [x0, #0x1] mov x17, #0x64 // =100 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x20, eq - cbz x20, + cset x2, eq + cbz x2, adrp x0, add x0, x0, mov x1, #0x1 // =1 str x1, [x0] - sub x21, x21, #0x1 - add x22, x22, #0x8 - cmp x21, #0x1 + sub x20, x20, #0x1 + add x21, x21, #0x8 + cmp x20, #0x1 b.ge adrp x0, add x0, x0, @@ -3374,50 +3212,40 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - ldr x0, [x22] + ldr x0, [x21] mov x1, #0x0 // =0 bl sxtw x0, w0 - mov x20, x0 - cmp x20, #0x0 + mov x22, x0 + cmp x22, #0x0 b.ge adrp x0, add x0, x0, - ldr x1, [x22] + ldr x1, [x21] bl sxtw x0, w0 mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret mov x23, #0x40000 // =262144 adrp x24, add x24, x24, - sxtw x0, w23 + mov x0, #0x40000 // =262144 bl str x0, [x24] cmp x0, #0x0 @@ -3431,23 +3259,18 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret adrp x24, add x24, x24, adrp x25, add x25, x25, - sxtw x0, w23 + mov x0, #0x40000 // =262144 bl str x0, [x25] str x0, [x24] @@ -3462,21 +3285,16 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret adrp x24, add x24, x24, - sxtw x0, w23 + mov x0, #0x40000 // =262144 bl str x0, [x24] cmp x0, #0x0 @@ -3490,82 +3308,203 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + mov x0, #0x40000 // =262144 + bl + mov x24, x0 + cmp x24, #0x0 + b.ne + adrp x0, + add x0, x0, + mov x1, x23 + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - sxtw x0, w23 + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x25, #0x0 // =0 + mov x2, #0x40000 // =262144 + mov x1, x25 + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x2, #0x40000 // =262144 + mov x1, x25 + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x2, #0x40000 // =262144 + mov x1, x25 + bl + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + str x1, [x0] + mov x25, #0x86 // =134 + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x26, #0x87 // =135 + str x25, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x25, #0x88 // =136 + str x26, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x26, #0x89 // =137 + str x25, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x25, #0x8a // =138 + str x26, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x26, #0x8b // =139 + str x25, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x25, #0x8c // =140 + str x26, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x26, #0x8d // =141 + str x25, [x0] + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + str x26, [x0] + mov x25, #0x1e // =30 + bl + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] + ldr x0, [x0] + mov x26, #0x1f // =31 + str x25, [x0, #0x28] + bl + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] + ldr x0, [x0] + mov x25, #0x20 // =32 + str x26, [x0, #0x28] bl - mov x24, x0 - cmp x24, #0x0 - b.ne adrp x0, add x0, x0, - mov x1, x23 + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] + ldr x0, [x0] + mov x26, #0x21 // =33 + str x25, [x0, #0x28] bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] ldr x0, [x0] - mov x25, #0x0 // =0 - sxtw x2, w23 - mov x1, x25 + mov x25, #0x22 // =34 + str x26, [x0, #0x28] bl adrp x0, add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] ldr x0, [x0] - sxtw x2, w23 - mov x1, x25 + mov x26, #0x23 // =35 + str x25, [x0, #0x28] bl adrp x0, add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] ldr x0, [x0] - sxtw x2, w23 - mov x1, x25 + mov x25, #0x24 // =36 + str x26, [x0, #0x28] bl adrp x0, add x0, x0, - adrp x1, - add x1, x1, - str x1, [x0] - mov x25, #0x86 // =134 - cmp x25, #0x8d - b.gt + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] + ldr x0, [x0] + mov x26, #0x25 // =37 + str x25, [x0, #0x28] bl adrp x0, add x0, x0, + ldr x1, [x0] + mov x2, #0x82 // =130 + str x2, [x1, #0x18] + ldr x1, [x0] + mov x2, #0x1 // =1 + str x2, [x1, #0x20] ldr x0, [x0] - add x1, x25, #0x1 - str x25, [x0] - mov x25, x1 - b - mov x25, #0x1e // =30 - cmp x25, #0x26 - b.gt + mov x25, #0x26 // =38 + str x26, [x0, #0x28] bl adrp x0, add x0, x0, @@ -3576,10 +3515,7 @@ Disassembly of section .text: mov x2, #0x1 // =1 str x2, [x1, #0x20] ldr x0, [x0] - add x1, x25, #0x1 str x25, [x0, #0x28] - mov x25, x1 - b bl adrp x25, add x25, x25, @@ -3592,7 +3528,7 @@ Disassembly of section .text: add x26, x26, adrp x27, add x27, x27, - sxtw x0, w23 + mov x0, #0x40000 // =262144 bl str x0, [x27] str x0, [x26] @@ -3607,57 +3543,48 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - sxtw x0, w20 + sxtw x0, w22 adrp x1, add x1, x1, ldr x1, [x1] - sub x2, x23, #0x1 - sxtw x2, w2 + mov x2, #0xffff // =65535 + movk x2, #0x3, lsl #16 bl sxtw x0, w0 - mov x26, x0 - cmp x26, #0x0 + cmp x0, #0x0 b.gt - adrp x0, - add x0, x0, - mov x1, x26 + adrp x1, + add x1, x1, + mov x16, x1 + mov x1, x0 + mov x0, x16 bl sxtw x0, w0 mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - adrp x0, - add x0, x0, - ldr x0, [x0] - add x0, x0, x26 + adrp x1, + add x1, x1, + ldr x1, [x1] + add x0, x1, x0 mov x1, #0x0 // =0 strb w1, [x0] - sxtw x0, w20 + sxtw x0, w22 bl sxtw x0, w0 adrp x0, @@ -3665,235 +3592,45 @@ Disassembly of section .text: mov x1, #0x1 // =1 str x1, [x0] bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cbz x0, - mov x20, #0x1 // =1 - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x8a - b.ne - b - ldr x25, [x25, #0x28] - cmp x25, #0x0 - b.ne - b - bl - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x86 - b.ne - bl - mov x20, #0x0 // =0 - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x88 - b.ne - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x7b - b.eq - b - b - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x7b - b.ne - bl - mov x26, #0x0 // =0 - b - b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x7d - b.eq - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x85 - b.eq - b - bl - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - adrp x2, - add x2, x2, - ldr x2, [x2] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x8e - b.ne - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x80 - b.eq b - adrp x0, - add x0, x0, - ldr x1, [x0] - mov x2, #0x80 // =128 - str x2, [x1, #0x18] - ldr x1, [x0] - mov x2, #0x1 // =1 - str x2, [x1, #0x20] - ldr x0, [x0] - add x26, x27, #0x1 - str x27, [x0, #0x28] + mov x22, #0x1 // =1 adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2c + cmp x0, #0x8a b.ne - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldr x27, [x0] - bl - b bl - b adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x3b - cset x26, ne - cbz x26, - b - mov x26, x20 - b - bl - b + cset x1, ne + cbz x1, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x7d - cset x26, ne - cbz x26, + cset x1, ne + cbz x1, + mov x26, x22 b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x9f - b.ne bl add x26, x26, #0x2 - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x85 + cmp x0, #0x9f b.eq adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, ldr x0, [x0] - ldr x0, [x0, #0x18] - cbz x0, + cmp x0, #0x85 + b.ne adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret + add x0, x0, + ldr x0, [x0] + ldr x0, [x0, #0x18] + cbnz x0, bl adrp x0, add x0, x0, @@ -3918,45 +3655,57 @@ Disassembly of section .text: bl mov x26, #0x0 // =0 b + mov x27, #0x1 // =1 adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2c + cmp x0, #0x8a b.ne + bl b + bl + add x27, x27, #0x2 adrp x0, add x0, x0, - ldr x1, [x0] - mov x2, #0x83 // =131 - str x2, [x1, #0x18] ldr x0, [x0] - adrp x1, - add x1, x1, - ldr x2, [x1] - str x2, [x0, #0x28] - ldr x0, [x1] - add x0, x0, #0x8 - str x0, [x1] - b + cmp x0, #0x9f + b.eq adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x29 + cmp x0, #0x85 + b.ne + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0, #0x18] + cmp x0, #0x84 b.eq - mov x27, #0x1 // =1 adrp x0, add x0, x0, + ldr x1, [x0] + ldr x2, [x1, #0x18] + str x2, [x1, #0x30] + ldr x1, [x0] + mov x2, #0x84 // =132 + str x2, [x1, #0x18] + ldr x1, [x0] + ldr x2, [x1, #0x20] + str x2, [x1, #0x38] + ldr x1, [x0] + str x27, [x1, #0x20] + ldr x1, [x0] + ldr x2, [x1, #0x28] + str x2, [x1, #0x40] ldr x0, [x0] - cmp x0, #0x8a - b.ne - b + add x27, x26, #0x1 + str x26, [x0, #0x28] bl adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x7b - b.eq - b + cmp x0, #0x2c + b.ne bl b adrp x0, @@ -3967,71 +3716,64 @@ Disassembly of section .text: bl mov x27, #0x0 // =0 b + b + mov x26, x27 adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x9f + cmp x0, #0x29 b.ne bl - add x27, x27, #0x2 - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x85 - b.eq + cmp x0, #0x7b + b.ne adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] + add x26, x26, #0x1 + str x26, [x0] bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldr x0, [x0] - ldr x0, [x0, #0x18] - cmp x0, #0x84 - b.ne + cmp x0, #0x8a + cset x1, eq + cbnz x1, adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] + ldr x0, [x0] + cmp x0, #0x86 + cset x1, eq + cbz x1, + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x8a + b.ne + mov x22, #0x1 // =1 bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret + b + mov x27, x22 + b + bl + add x27, x27, #0x2 + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x9f + b.eq + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x85 + b.ne + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0, #0x18] + cmp x0, #0x84 + b.eq adrp x0, add x0, x0, ldr x1, [x0] @@ -4049,7 +3791,7 @@ Disassembly of section .text: ldr x2, [x1, #0x28] str x2, [x1, #0x40] ldr x0, [x0] - add x27, x26, #0x1 + add x26, x26, #0x1 str x26, [x0, #0x28] bl adrp x0, @@ -4058,48 +3800,15 @@ Disassembly of section .text: cmp x0, #0x2c b.ne bl - mov x26, x27 - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - add x26, x26, #0x1 - str x26, [x0] - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x8a - cset x27, eq - cbnz x27, - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x8a + cmp x0, #0x3b b.ne + bl + b + mov x22, #0x0 // =0 + b b adrp x0, add x0, x0, @@ -4117,62 +3826,26 @@ Disassembly of section .text: sub x0, x26, x0 str x0, [x1] b - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x86 - cset x27, eq - cbz x27, - b - mov x20, #0x1 // =1 - b - mov x20, #0x0 // =0 - bl - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x3b - b.eq - mov x27, x20 - b bl - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x9f + cmp x0, #0x7d b.ne - bl - add x27, x27, #0x2 - b adrp x0, add x0, x0, - ldr x0, [x0] - cmp x0, #0x85 - b.eq + ldr x1, [x0] + add x1, x1, #0x8 + str x1, [x0] + mov x0, #0x8 // =8 + str x0, [x1] adrp x0, add x0, x0, adrp x1, add x1, x1, ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret + str x1, [x0] + b adrp x0, add x0, x0, ldr x0, [x0] @@ -4181,106 +3854,131 @@ Disassembly of section .text: b.ne adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - bl - sxtw x0, w0 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldr x1, [x0] - ldr x2, [x1, #0x18] - str x2, [x1, #0x30] ldr x1, [x0] - mov x2, #0x84 // =132 + ldr x2, [x1, #0x30] str x2, [x1, #0x18] ldr x1, [x0] - ldr x2, [x1, #0x20] - str x2, [x1, #0x38] + ldr x2, [x1, #0x38] + str x2, [x1, #0x20] ldr x1, [x0] - str x27, [x1, #0x20] + ldr x0, [x1, #0x40] + str x0, [x1, #0x28] + adrp x0, + add x0, x0, ldr x1, [x0] - ldr x2, [x1, #0x28] - str x2, [x1, #0x40] + add x1, x1, #0x48 + str x1, [x0] + adrp x0, + add x0, x0, + ldr x0, [x0] + ldr x0, [x0] + cbnz x0, + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x2c + b.ne + bl + b + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x2, #0x83 // =131 + str x2, [x1, #0x18] + ldr x0, [x0] + adrp x1, + add x1, x1, + ldr x2, [x1] + str x2, [x0, #0x28] + ldr x0, [x1] + add x0, x0, #0x8 + str x0, [x1] + b + b + adrp x0, + add x0, x0, ldr x0, [x0] - add x26, x26, #0x1 - str x26, [x0, #0x28] + cmp x0, #0x86 + b.ne bl + mov x22, #0x0 // =0 + b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x2c + cmp x0, #0x88 b.ne bl - b adrp x0, add x0, x0, ldr x0, [x0] - cmp x0, #0x7d + cmp x0, #0x7b b.eq bl - b adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x8 - str x1, [x0] - mov x0, #0x8 // =8 - str x0, [x1] + ldr x0, [x0] + cmp x0, #0x7b + b.ne + bl + mov x26, #0x0 // =0 + b adrp x0, add x0, x0, - adrp x1, - add x1, x1, - ldr x1, [x1] - str x1, [x0] + ldr x0, [x0] + cmp x0, #0x85 + b.ne + bl adrp x0, add x0, x0, ldr x0, [x0] - ldr x0, [x0] - cbz x0, + cmp x0, #0x8e + b.ne + bl adrp x0, add x0, x0, ldr x0, [x0] - ldr x0, [x0, #0x18] - cmp x0, #0x84 + cmp x0, #0x80 b.ne - b - b + adrp x0, + add x0, x0, + ldr x27, [x0] + bl adrp x0, add x0, x0, ldr x1, [x0] - ldr x2, [x1, #0x30] + mov x2, #0x80 // =128 str x2, [x1, #0x18] ldr x1, [x0] - ldr x2, [x1, #0x38] + mov x2, #0x1 // =1 str x2, [x1, #0x20] - ldr x1, [x0] - ldr x0, [x1, #0x40] - str x0, [x1, #0x28] + ldr x0, [x0] + add x26, x27, #0x1 + str x27, [x0, #0x28] adrp x0, add x0, x0, - ldr x1, [x0] - add x1, x1, #0x48 - str x1, [x0] + ldr x0, [x0] + cmp x0, #0x2c + b.ne + bl + b + mov x27, x26 b + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x7d + b.ne bl b + bl + adrp x0, + add x0, x0, + ldr x0, [x0] + cbnz x0, + ldr x3, [x25, #0x28] + cmp x3, #0x0 + b.ne adrp x0, add x0, x0, bl @@ -4289,70 +3987,46 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret adrp x0, add x0, x0, ldr x0, [x0] cbz x0, mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - add x23, x24, x23 - sub x0, x23, #0x8 + add x22, x24, x23 + sub x0, x22, #0x8 mov x1, #0x26 // =38 str x1, [x0] sub x0, x0, #0x8 mov x1, #0xd // =13 str x1, [x0] sub x1, x0, #0x8 - str x21, [x1] + str x20, [x1] sub x1, x1, #0x8 - str x22, [x1] + str x21, [x1] sub x21, x1, #0x8 str x0, [x21] mov x20, #0x0 // =0 - add x22, x25, #0x8 - ldr x24, [x25] + add x23, x3, #0x8 + ldr x24, [x3] add x20, x20, #0x1 adrp x0, add x0, x0, ldr x0, [x0] cbz x0, - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, adrp x1, @@ -4365,96 +4039,82 @@ Disassembly of section .text: sxtw x0, w0 cmp x24, #0x7 b.gt - b - cmp x24, #0x0 - b.ne - b - adrp x0, - add x0, x0, - ldr x1, [x22] - bl - sxtw x0, w0 - b adrp x0, add x0, x0, + ldr x1, [x23] bl sxtw x0, w0 - b - add x25, x22, #0x8 - ldr x0, [x22] + cmp x24, #0x0 + b.ne + add x3, x23, #0x8 + ldr x0, [x23] lsl x0, x0, #3 - add x0, x23, x0 + add x0, x22, x0 stur x0, [x29, #-0x48] b cmp x24, #0x1 b.ne - add x25, x22, #0x8 - ldr x0, [x22] + add x3, x23, #0x8 + ldr x0, [x23] stur x0, [x29, #-0x48] b cmp x24, #0x2 b.ne - ldr x25, [x22] + ldr x3, [x23] b cmp x24, #0x3 b.ne sub x21, x21, #0x8 - add x0, x22, #0x8 + add x0, x23, #0x8 str x0, [x21] - ldr x25, [x22] + ldr x3, [x23] b cmp x24, #0x4 b.ne ldur x0, [x29, #-0x48] cbz x0, + add x3, x23, #0x8 b + ldr x3, [x23] b cmp x24, #0x5 b.ne - b - add x25, x22, #0x8 - b - ldr x25, [x22] - b ldur x0, [x29, #-0x48] cbz x0, + ldr x3, [x23] b + add x3, x23, #0x8 b cmp x24, #0x6 b.ne - b - ldr x25, [x22] - b - add x25, x22, #0x8 - b sub x0, x21, #0x8 - str x23, [x0] - add x25, x22, #0x8 - ldr x1, [x22] + str x22, [x0] + add x3, x23, #0x8 + ldr x1, [x23] lsl x1, x1, #3 sub x21, x0, x1 - mov x23, x0 + mov x22, x0 b cmp x24, #0x7 b.ne - add x25, x22, #0x8 - ldr x0, [x22] + add x3, x23, #0x8 + ldr x0, [x23] lsl x0, x0, #3 add x21, x21, x0 b cmp x24, #0x8 b.ne - add x0, x23, #0x8 - ldr x23, [x23] + add x0, x22, #0x8 + ldr x22, [x22] add x21, x0, #0x8 - ldr x25, [x0] + ldr x3, [x0] b cmp x24, #0x9 b.ne ldur x0, [x29, #-0x48] ldr x0, [x0] stur x0, [x29, #-0x48] - mov x25, x22 + mov x3, x23 b cmp x24, #0xa b.ne @@ -4668,7 +4328,7 @@ Disassembly of section .text: b cmp x24, #0x21 b.ne - ldr x0, [x22, #0x8] + ldr x0, [x23, #0x8] lsl x0, x0, #3 add x0, x21, x0 sub x1, x0, #0x8 @@ -4727,6 +4387,11 @@ Disassembly of section .text: sxtw x0, w0 stur x0, [x29, #-0x48] b + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + b cmp x24, #0x26 b.ne adrp x0, @@ -4736,19 +4401,13 @@ Disassembly of section .text: bl sxtw x0, w0 ldr x0, [x21] - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret - b adrp x0, add x0, x0, mov x1, x24 @@ -4759,17 +4418,177 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + adrp x2, + add x2, x2, + ldr x2, [x2] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1] + bl + sxtw x0, w0 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x130] ldr x19, [sp, #0x40] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 ret b b @@ -4777,7 +4596,20 @@ Disassembly of section .text: b b b - mov x27, x26 + b + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x130] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x140 + ret + b + b + b + b + b b b b diff --git a/tests/snapshots/asm/c4.x64.asm b/tests/snapshots/asm/c4.x64.asm index 85f095c07..2508b7d3d 100644 --- a/tests/snapshots/asm/c4.x64.asm +++ b/tests/snapshots/asm/c4.x64.asm @@ -13,17 +13,10 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x160, %rsp # imm = 0x160 + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - leaq , %rax - leaq , %rcx - movq (%rcx), %rcx - movsbq (%rcx), %rcx - movq %rcx, (%rax) - testq %rcx, %rcx - je + jmp leaq , %rax movq (%rax), %rcx incq %rcx @@ -32,25 +25,10 @@ Disassembly of section .text: movq (%rax), %rax cmpq $0xa, %rax jne - jmp - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq leaq , %rax movq (%rax), %rax testq %rax, %rax je - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x23, %rax - jne - jmp leaq , %rdi leaq , %rax movq (%rax), %rsi @@ -66,17 +44,6 @@ Disassembly of section .text: movq (%rbx), %rax movq %rax, (%r12) jmp - leaq , %rax - movq (%rax), %rcx - incq %rcx - movq %rcx, (%rax) - jmp - leaq , %rax - movq (%rax), %rax - leaq , %rcx - movq (%rcx), %rcx - cmpq %rcx, %rax - jge leaq , %rdi leaq , %rax leaq , %rbx @@ -93,8 +60,6 @@ Disassembly of section .text: movq (%rax), %rax cmpq $0x7, %rax jg - jmp - jmp leaq , %rdi leaq , %rax movq (%rax), %rcx @@ -109,27 +74,33 @@ Disassembly of section .text: movb $0x0, %al callq movslq %eax, %rax - jmp - jmp + leaq , %rax + movq (%rax), %rax + leaq , %rcx + movq (%rcx), %rcx + cmpq %rcx, %rax + jge jmp leaq , %rax movq (%rax), %rax - cmpq $0x61, %rax - setge %al - movzbq %al, %rax - xorq %rbx, %rbx + cmpq $0x23, %rax + jne + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax testq %rax, %rax + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - jmp leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + cmpq $0xa, %rax + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - jmp leaq , %rax movq (%rax), %rcx incq %rcx @@ -138,60 +109,51 @@ Disassembly of section .text: jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0xa, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + cmpq $0x61, %rax + setge %al + movzbq %al, %rax + xorq %rdx, %rdx + testq %rax, %rax je - jmp leaq , %rax movq (%rax), %rax cmpq $0x7a, %rax setle %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq , %rax movq (%rax), %rax cmpq $0x41, %rax setge %al movzbq %al, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je - jmp - testq %r12, %r12 - jne - jmp leaq , %rax movq (%rax), %rax cmpq $0x5a, %rax setle %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx - setne %r12b - movzbq %r12b, %r12 - jmp + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne leaq , %rax movq (%rax), %rax cmpq $0x5f, %rax - sete %r12b - movzbq %r12b, %r12 - testq %r12, %r12 - je - leaq , %rax - movq (%rax), %rax - leaq -0x1(%rax), %rbx - jmp - jmp + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne leaq , %rax movq (%rax), %rax cmpq $0x30, %rax @@ -199,634 +161,330 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x61, %rax - setge %al - movzbq %al, %rax - xorq %r12, %r12 - testq %rax, %rax - je - jmp + cmpq $0x39, %rax + setle %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne leaq , %rax - movq (%rax), %rcx - imulq $0x93, %rcx, %rcx - leaq , %rdx - movq (%rdx), %rsi - leaq 0x1(%rsi), %rdi - movq %rdi, (%rdx) - movsbq (%rsi), %rdx - addq %rdx, %rcx - movq %rcx, (%rax) - jmp + movq (%rax), %rax + cmpq $0x2f, %rax + jne leaq , %rax - movq (%rax), %rcx - shlq $0x6, %rcx - leaq , %rdx - movq (%rdx), %rdx - subq %rbx, %rdx - addq %rdx, %rcx - movq %rcx, (%rax) + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x2f, %rax + jne leaq , %rax - leaq , %rcx - movq (%rcx), %rcx + movq (%rax), %rcx + incq %rcx movq %rcx, (%rax) - jmp leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x7a, %rax - setle %al - movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - movl $0x1, %r13d - testq %r12, %r12 - jne + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x41, %rax - setge %al - movzbq %al, %rax - xorq %r12, %r12 - testq %rax, %rax + cmpq $0xa, %rax + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je + leaq , %rax + movq (%rax), %rcx + incq %rcx + movq %rcx, (%rax) jmp - movl $0x1, %r12d - testq %r13, %r13 - jne jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x5a, %rax - setle %al - movzbq %al, %rax - testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 - setne %r13b - movzbq %r13b, %r13 - jmp + cmpq $0x27, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x30, %rax - setge %al - movzbq %al, %rax - xorq %r12, %r12 - testq %rax, %rax - je - jmp - testq %r12, %r12 + cmpq $0x22, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne - jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x39, %rax - setle %al - movzbq %al, %rax - testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 - setne %r12b - movzbq %r12b, %r12 - jmp + cmpq $0x3d, %rax + je leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x5f, %rax - sete %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + cmpq $0x2b, %rax je - jmp leaq , %rax movq (%rax), %rax + cmpq $0x2d, %rax + je + leaq , %rax movq (%rax), %rax - testq %rax, %rax + cmpq $0x21, %rax je leaq , %rax movq (%rax), %rax - leaq , %rcx - movq (%rcx), %rcx - movq 0x8(%rcx), %rcx - cmpq %rcx, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x3c, %rax je - jmp leaq , %rax - movq (%rax), %rcx - movq %rbx, 0x10(%rcx) - movq (%rax), %rcx - leaq , %rdx - movq (%rdx), %rsi - movq %rsi, 0x8(%rcx) movq (%rax), %rax - xorq %rcx, %rcx - movl $0x85, %esi - movq %rsi, (%rax) - movq %rsi, (%rdx) - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq %rcx, %rax - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq + cmpq $0x3e, %rax + je leaq , %rax movq (%rax), %rax - movq 0x10(%rax), %rdi + cmpq $0x7c, %rax + je leaq , %rax movq (%rax), %rax - movq %rax, %rdx - subq %rbx, %rdx - movq %rbx, %rsi - xorl %eax, %eax - callq - movslq %eax, %rax - testq %rax, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x26, %rax je leaq , %rax - leaq , %rcx - movq (%rcx), %rcx - xorq %rdx, %rdx - movq (%rcx), %rcx - movq %rcx, (%rax) - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq %rdx, %rax - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq - leaq , %rax - movq (%rax), %rcx - addq $0x48, %rcx - movq %rcx, (%rax) - jmp - leaq , %rax movq (%rax), %rax - cmpq $0x39, %rax - setle %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - leaq , %rax - leaq , %rcx - movq (%rcx), %rcx - subq $0x30, %rcx - movq %rcx, (%rax) - testq %rcx, %rcx + cmpq $0x5e, %rax je - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x2f, %rax - jne - jmp - jmp - leaq , %rax - movl $0x80, %ecx - movq %rcx, (%rax) - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x78, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne - jmp + cmpq $0x25, %rax + je leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x30, %rax - setge %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x2a, %rax je - jmp - leaq , %rax - movq (%rax), %rcx - imulq $0xa, %rcx, %rcx - leaq , %rdx - movq (%rdx), %rsi - leaq 0x1(%rsi), %rdi - movq %rdi, (%rdx) - movsbq (%rsi), %rdx - addq %rdx, %rcx - subq $0x30, %rcx - movq %rcx, (%rax) - jmp - jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x39, %rax - setle %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x5b, %rax je - jmp leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x58, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x3f, %rax je - jmp - jmp - jmp leaq , %rax - leaq , %rcx - movq (%rcx), %rdx - incq %rdx - movq %rdx, (%rcx) - movsbq (%rdx), %rcx - movq %rcx, (%rax) - testq %rcx, %rcx - je - jmp + movq (%rax), %rax + cmpq $0x7e, %rax + sete %al + movzbq %al, %rax + movl $0x1, %edx + testq %rax, %rax + jne leaq , %rax - movq (%rax), %rcx - shlq $0x4, %rcx - leaq , %rdx - movq (%rdx), %rsi - movq %rsi, %rdi - andq $0xf, %rdi - addq %rdi, %rcx - cmpq $0x41, %rsi - jl - jmp - jmp + movq (%rax), %rax + cmpq $0x3b, %rax + sete %al + movzbq %al, %rax + testq %rax, %rax + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx + jne leaq , %rax movq (%rax), %rax - cmpq $0x30, %rax - setge %al + cmpq $0x7b, %rax + sete %al movzbq %al, %rax - xorq %rdx, %rdx testq %rax, %rax - je - jmp + setne %cl + movzbq %cl, %rcx + movl $0x1, %edx testq %rcx, %rcx - je - jmp + jne leaq , %rax movq (%rax), %rax - cmpq $0x39, %rax - setle %al + cmpq $0x7d, %rax + sete %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx - movl $0x1, %esi + movl $0x1, %ecx testq %rdx, %rdx jne leaq , %rax movq (%rax), %rax - cmpq $0x61, %rax - setge %al + cmpq $0x28, %rax + sete %al movzbq %al, %rax - xorq %rdx, %rdx testq %rax, %rax - je - jmp - movl $0x1, %ecx - testq %rsi, %rsi + setne %cl + movzbq %cl, %rcx + movl $0x1, %edx + testq %rcx, %rcx jne - jmp leaq , %rax movq (%rax), %rax - cmpq $0x66, %rax - setle %al + cmpq $0x29, %rax + sete %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx + movl $0x1, %ecx testq %rdx, %rdx - setne %sil - movzbq %sil, %rsi - jmp + jne leaq , %rax movq (%rax), %rax - cmpq $0x41, %rax - setge %al + cmpq $0x5d, %rax + sete %al movzbq %al, %rax - xorq %rdx, %rdx testq %rax, %rax - je - jmp - jmp + setne %cl + movzbq %cl, %rcx + movl $0x1, %edx + testq %rcx, %rcx + jne leaq , %rax movq (%rax), %rax - cmpq $0x46, %rax - setle %al + cmpq $0x2c, %rax + sete %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx testq %rdx, %rdx - setne %cl - movzbq %cl, %rcx - jmp - movl $0x9, %esi - jmp - xorq %rsi, %rsi - addq %rsi, %rcx - movq %rcx, (%rax) - jmp + jne leaq , %rax movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x30, %rax - setge %cl - movzbq %cl, %rcx - testq %rcx, %rcx + cmpq $0x3a, %rax + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx je jmp - leaq , %rax - movq (%rax), %rcx - shlq $0x3, %rcx - leaq , %rdx - movq (%rdx), %rsi - leaq 0x1(%rsi), %rdi - movq %rdi, (%rdx) - movsbq (%rsi), %rdx - addq %rdx, %rcx - subq $0x30, %rcx - movq %rcx, (%rax) jmp jmp - leaq , %rax - movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x37, %rax - setle %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je jmp - leaq , %rax - movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x2f, %rax - jne jmp jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x27, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) - jmp - jmp leaq , %rax - movl $0xa0, %ecx + leaq , %rcx + movq (%rcx), %rcx + movsbq (%rcx), %rcx movq %rcx, (%rax) + testq %rcx, %rcx + jne xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movq (%rax), %rax - movsbq (%rax), %rax - testq %rax, %rax - setne %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - jmp - leaq , %rax - movq (%rax), %rcx - incq %rcx + movl $0x8f, %ecx movq %rcx, (%rax) - jmp - jmp - leaq , %rax - movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0xa, %rax - setne %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x22, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - leaq , %rax - movq (%rax), %rax - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x3d, %rax - jne - jmp - leaq , %rcx - movq (%rcx), %rcx - movsbq (%rcx), %rcx - testq %rcx, %rcx - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - jmp - leaq , %rcx - leaq , %rdx - movq (%rdx), %rsi - leaq 0x1(%rsi), %rdi - movq %rdi, (%rdx) - movsbq (%rsi), %rdx - movq %rdx, (%rcx) - cmpq $0x5c, %rdx - jne - jmp - leaq , %rcx - movq (%rcx), %rdx - incq %rdx - movq %rdx, (%rcx) - leaq , %rcx - movq (%rcx), %rcx - cmpq $0x22, %rcx - jne - jmp - leaq , %rcx - movq (%rcx), %rcx - movsbq (%rcx), %rcx - leaq , %rdx - movq (%rdx), %rdx - cmpq %rdx, %rcx - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - jmp - leaq , %rcx - leaq , %rdx - movq (%rdx), %rsi - leaq 0x1(%rsi), %rdi - movq %rdi, (%rdx) - movsbq (%rsi), %rdx - movq %rdx, (%rcx) - cmpq $0x6e, %rdx - jne - jmp - leaq , %rcx - movq (%rcx), %rcx - cmpq $0x22, %rcx - jne - jmp - leaq , %rcx - movl $0xa, %edx - movq %rdx, (%rcx) - jmp - leaq , %rcx - movq (%rcx), %rdx - leaq 0x1(%rdx), %rsi - movq %rsi, (%rcx) - leaq , %rcx - movq (%rcx), %rcx - movb %cl, (%rdx) - jmp - leaq , %rcx - movq %rax, (%rcx) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x80, %ecx + movl $0xa4, %ecx movq %rcx, (%rax) - jmp - leaq , %rax - movq (%rax), %rax - movsbq (%rax), %rax - cmpq $0x3d, %rax - jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x2b, %rax - jne - jmp + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq leaq , %rax - movq (%rax), %rcx - incq %rcx + movl $0x9f, %ecx movq %rcx, (%rax) + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq leaq , %rax - movl $0x95, %ecx + movl $0xa1, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x8e, %ecx + movl $0x93, %ecx movq %rcx, (%rax) - jmp + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x2b, %rax - jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x2d, %rax + cmpq $0x26, %rax jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0xa2, %ecx + movl $0x91, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x9d, %ecx + movl $0x94, %ecx movq %rcx, (%rax) jmp leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x2d, %rax - jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x21, %rax + cmpq $0x7c, %rax jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0xa3, %ecx + movl $0x90, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x9e, %ecx + movl $0x92, %ecx movq %rcx, (%rax) jmp leaq , %rax @@ -834,39 +492,41 @@ Disassembly of section .text: movsbq (%rax), %rax cmpq $0x3d, %rax jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x3c, %rax - jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0x96, %ecx + movl $0x9a, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x3d, %rax + cmpq $0x3e, %rax jne + leaq , %rax + movq (%rax), %rcx + incq %rcx + movq %rcx, (%rax) + leaq , %rax + movl $0x9c, %ecx + movq %rcx, (%rax) jmp + leaq , %rax + movl $0x98, %ecx + movq %rcx, (%rax) jmp leaq , %rax movq (%rax), %rax - cmpq $0x3e, %rax + movsbq (%rax), %rax + cmpq $0x3d, %rax jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx @@ -877,8 +537,7 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -903,289 +562,315 @@ Disassembly of section .text: movsbq (%rax), %rax cmpq $0x3d, %rax jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x7c, %rax - jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0x9a, %ecx + movl $0x96, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x3e, %rax + cmpq $0x2d, %rax jne leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0x9c, %ecx + movl $0xa3, %ecx movq %rcx, (%rax) - jmp + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq leaq , %rax - movl $0x98, %ecx + movl $0x9e, %ecx movq %rcx, (%rax) jmp leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x7c, %rax - jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x26, %rax + cmpq $0x2b, %rax jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0x90, %ecx + movl $0xa2, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x92, %ecx + movl $0x9d, %ecx movq %rcx, (%rax) jmp leaq , %rax movq (%rax), %rax movsbq (%rax), %rax - cmpq $0x26, %rax - jne - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x5e, %rax + cmpq $0x3d, %rax jne - jmp leaq , %rax movq (%rax), %rcx incq %rcx movq %rcx, (%rax) leaq , %rax - movl $0x91, %ecx + movl $0x95, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq leaq , %rax - movl $0x94, %ecx + movl $0x8e, %ecx movq %rcx, (%rax) jmp leaq , %rax - movl $0x93, %ecx - movq %rcx, (%rax) - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq - jmp - leaq , %rax movq (%rax), %rax - cmpq $0x25, %rax + leaq , %rcx + movq (%rcx), %rcx + movsbq (%rcx), %rcx + testq %rcx, %rcx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + je + leaq , %rcx + movq (%rcx), %rcx + movsbq (%rcx), %rcx + leaq , %rdx + movq (%rdx), %rdx + cmpq %rdx, %rcx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + je + leaq , %rcx + leaq , %rdx + movq (%rdx), %rsi + leaq 0x1(%rsi), %rdi + movq %rdi, (%rdx) + movsbq (%rsi), %rdx + movq %rdx, (%rcx) + cmpq $0x5c, %rdx jne - leaq , %rax - movl $0xa1, %ecx - movq %rcx, (%rax) + leaq , %rcx + leaq , %rdx + movq (%rdx), %rsi + leaq 0x1(%rsi), %rdi + movq %rdi, (%rdx) + movsbq (%rsi), %rdx + movq %rdx, (%rcx) + cmpq $0x6e, %rdx + jne + leaq , %rcx + movl $0xa, %edx + movq %rdx, (%rcx) + leaq , %rcx + movq (%rcx), %rcx + cmpq $0x22, %rcx + jne + leaq , %rcx + movq (%rcx), %rdx + leaq 0x1(%rdx), %rsi + movq %rsi, (%rcx) + leaq , %rcx + movq (%rcx), %rcx + movb %cl, (%rdx) + jmp + jmp + leaq , %rcx + movq (%rcx), %rdx + incq %rdx + movq %rdx, (%rcx) + leaq , %rcx + movq (%rcx), %rcx + cmpq $0x22, %rcx + jne + leaq , %rcx + movq %rax, (%rcx) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq - jmp leaq , %rax - movq (%rax), %rax - cmpq $0x2a, %rax - jne + movl $0x80, %ecx + movq %rcx, (%rax) + jmp leaq , %rax - movl $0x9f, %ecx + movl $0xa0, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq - jmp + leaq , %rax + leaq , %rcx + movq (%rcx), %rcx + subq $0x30, %rcx + movq %rcx, (%rax) + testq %rcx, %rcx + je leaq , %rax movq (%rax), %rax - cmpq $0x5b, %rax - jne + movsbq (%rax), %rax + cmpq $0x30, %rax + setge %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je leaq , %rax - movl $0xa4, %ecx + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x39, %rax + setle %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + movq (%rax), %rcx + imulq $0xa, %rcx, %rcx + leaq , %rdx + movq (%rdx), %rsi + leaq 0x1(%rsi), %rdi + movq %rdi, (%rdx) + movsbq (%rsi), %rdx + addq %rdx, %rcx + subq $0x30, %rcx movq %rcx, (%rax) - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq + jmp jmp leaq , %rax - movq (%rax), %rax - cmpq $0x3f, %rax - jne - leaq , %rax - movl $0x8f, %ecx + movl $0x80, %ecx movq %rcx, (%rax) xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 + addq $0x10, %rsp popq %rbp retq - jmp leaq , %rax movq (%rax), %rax - cmpq $0x7e, %rax - sete %al - movzbq %al, %rax - movl $0x1, %edx - testq %rax, %rax + movsbq (%rax), %rax + cmpq $0x78, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movq (%rax), %rax - cmpq $0x3b, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - setne %dl - movzbq %dl, %rdx - movl $0x1, %ecx - testq %rdx, %rdx - jne + movsbq (%rax), %rax + cmpq $0x58, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + leaq , %rcx + movq (%rcx), %rdx + incq %rdx + movq %rdx, (%rcx) + movsbq (%rdx), %rcx + movq %rcx, (%rax) + testq %rcx, %rcx + je leaq , %rax movq (%rax), %rax - cmpq $0x7b, %rax - sete %al + cmpq $0x30, %rax + setge %al movzbq %al, %rax + xorq %rdx, %rdx testq %rax, %rax - setne %cl - movzbq %cl, %rcx - movl $0x1, %edx - testq %rcx, %rcx - jne + je leaq , %rax movq (%rax), %rax - cmpq $0x7d, %rax - sete %al + cmpq $0x39, %rax + setle %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx - movl $0x1, %ecx + movl $0x1, %esi testq %rdx, %rdx jne leaq , %rax movq (%rax), %rax - cmpq $0x28, %rax - sete %al + cmpq $0x61, %rax + setge %al movzbq %al, %rax + xorq %rdx, %rdx testq %rax, %rax - setne %cl - movzbq %cl, %rcx - movl $0x1, %edx - testq %rcx, %rcx - jne + je leaq , %rax movq (%rax), %rax - cmpq $0x29, %rax - sete %al + cmpq $0x66, %rax + setle %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx - movl $0x1, %ecx testq %rdx, %rdx + setne %sil + movzbq %sil, %rsi + movl $0x1, %ecx + testq %rsi, %rsi jne leaq , %rax movq (%rax), %rax - cmpq $0x5d, %rax - sete %al + cmpq $0x41, %rax + setge %al movzbq %al, %rax + xorq %rdx, %rdx testq %rax, %rax - setne %cl - movzbq %cl, %rcx - movl $0x1, %edx - testq %rcx, %rcx - jne + je leaq , %rax movq (%rax), %rax - cmpq $0x2c, %rax - sete %al + cmpq $0x46, %rax + setle %al movzbq %al, %rax testq %rax, %rax setne %dl movzbq %dl, %rdx testq %rdx, %rdx - jne - leaq , %rax - movq (%rax), %rax - cmpq $0x3a, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp + leaq , %rax + movq (%rax), %rcx + shlq $0x4, %rcx + leaq , %rdx + movq (%rdx), %rsi + movq %rsi, %rdi + andq $0xf, %rdi + addq %rdi, %rcx + cmpq $0x41, %rsi + jl + movl $0x9, %esi + addq %rsi, %rcx + movq %rcx, (%rax) jmp + xorq %rsi, %rsi jmp jmp jmp @@ -1193,9 +878,125 @@ Disassembly of section .text: jmp jmp jmp + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x30, %rax + setge %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x37, %rax + setle %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + movq (%rax), %rcx + shlq $0x3, %rcx + leaq , %rdx + movq (%rdx), %rsi + leaq 0x1(%rsi), %rdi + movq %rdi, (%rdx) + movsbq (%rsi), %rdx + addq %rdx, %rcx + subq $0x30, %rcx + movq %rcx, (%rax) jmp jmp jmp + leaq , %rax + movq (%rax), %rax + leaq -0x1(%rax), %rbx + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x61, %rax + setge %al + movzbq %al, %rax + xorq %rdx, %rdx + testq %rax, %rax + je + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x7a, %rax + setle %al + movzbq %al, %rax + testq %rax, %rax + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx + jne + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x41, %rax + setge %al + movzbq %al, %rax + xorq %rdx, %rdx + testq %rax, %rax + je + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x5a, %rax + setle %al + movzbq %al, %rax + testq %rax, %rax + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %cl + movzbq %cl, %rcx + movl $0x1, %edx + testq %rcx, %rcx + jne + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x30, %rax + setge %al + movzbq %al, %rax + xorq %rdx, %rdx + testq %rax, %rax + je + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x39, %rax + setle %al + movzbq %al, %rax + testq %rax, %rax + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + jne + leaq , %rax + movq (%rax), %rax + movsbq (%rax), %rax + cmpq $0x5f, %rax + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx + je + leaq , %rax + movq (%rax), %rcx + imulq $0x93, %rcx, %rcx + leaq , %rdx + movq (%rdx), %rsi + leaq 0x1(%rsi), %rdi + movq %rdi, (%rdx) + movsbq (%rsi), %rdx + addq %rdx, %rcx + movq %rcx, (%rax) jmp jmp jmp @@ -1203,153 +1004,137 @@ Disassembly of section .text: jmp jmp jmp + leaq , %rax + movq (%rax), %rcx + shlq $0x6, %rcx + leaq , %rdx + movq (%rdx), %rdx + subq %rbx, %rdx + addq %rdx, %rcx + movq %rcx, (%rax) + leaq , %rax + leaq , %rcx + movq (%rcx), %rcx + movq %rcx, (%rax) jmp - -: - pushq %rbp - movq %rsp, %rbp - subq $0xf0, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movq %r14, 0x18(%rsp) - movq %rdi, %rbx - leaq , %r12 - movq (%r12), %rax - testq %rax, %rax - jne - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi + movq (%rax), %rax + leaq , %rcx + movq (%rcx), %rcx + movq 0x8(%rcx), %rcx + cmpq %rcx, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + movq (%rax), %rax + movq 0x10(%rax), %rdi + leaq , %rax + movq (%rax), %rax + movq %rax, %rdx + subq %rbx, %rdx + movq %rbx, %rsi xorl %eax, %eax callq movslq %eax, %rax + testq %rax, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + jmp jmp - movq (%r12), %rax - cmpq $0x80, %rax - jne leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1, %r13d - movq %r13, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + addq $0x48, %rcx movq %rcx, (%rax) leaq , %rax movq (%rax), %rax - movq %rax, (%rcx) - callq - leaq , %rax - movq %r13, (%rax) - jmp - movq (%r12), %rax - cmpq $0x22, %rax + movq (%rax), %rax + testq %rax, %rax jne leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) + movq %rbx, 0x10(%rcx) movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - leaq , %rax + leaq , %rdx + movq (%rdx), %rsi + movq %rsi, 0x8(%rcx) movq (%rax), %rax - movq %rax, (%rcx) - callq + xorq %rcx, %rcx + movl $0x85, %esi + movq %rsi, (%rax) + movq %rsi, (%rdx) + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq %rcx, %rax + addq $0x10, %rsp + popq %rbp + retq + leaq , %rax + leaq , %rcx + movq (%rcx), %rcx + xorq %rdx, %rdx + movq (%rcx), %rcx + movq %rcx, (%rax) + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq %rdx, %rax + addq $0x10, %rsp + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp jmp jmp - movq (%r12), %rax - cmpq $0x8c, %rax - jne jmp - movq (%r12), %rax - cmpq $0x22, %rax - jne - callq jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - andq $-0x8, %rcx - movq %rcx, (%rax) - leaq , %rax - movl $0x2, %ecx - movq %rcx, (%rax) jmp - callq - movq (%r12), %rax - cmpq $0x28, %rax - jne jmp jmp - movq (%r12), %rax - cmpq $0x85, %rax - jne jmp - callq - leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) - movq (%r12), %rax - cmpq $0x8a, %rax - jne jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax jmp - callq jmp - movq (%r12), %rax - cmpq $0x86, %rax - jne - callq - leaq , %rax - xorq %rcx, %rcx - movq %rcx, (%rax) jmp - movq (%r12), %rax - cmpq $0x9f, %rax - jne - callq - leaq , %rax - movq (%rax), %rcx - addq $0x2, %rcx - movq %rcx, (%rax) jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + +: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %rdi, %rbx + leaq , %r12 movq (%r12), %rax - cmpq $0x29, %rax - jne - callq - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - leaq 0x8(%rcx), %r13 - movq %r13, (%rax) - leaq , %rax - movq (%rax), %rax testq %rax, %rax jne - jmp leaq , %rdi leaq , %rax movq (%rax), %rsi @@ -1361,80 +1146,95 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0x1, %ecx - jmp - movl $0x8, %ecx - movq %rcx, (%r13) - leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) - jmp leaq , %rax movq (%rax), %r13 - callq movq (%r12), %rax - cmpq $0x28, %rax - jne - jmp - jmp - movq (%r12), %rax - cmpq $0x28, %rax + cmpq $0x8e, %rax jne - jmp callq - xorq %r14, %r14 - jmp - jmp - movq 0x18(%r13), %rax - cmpq $0x80, %rax + leaq , %rax + movq (%rax), %rax + movq (%rax), %rax + cmpq $0xa, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne - jmp - movq (%r12), %rax - cmpq $0x29, %rax + leaq , %rax + movq (%rax), %rax + movq (%rax), %rax + cmpq $0x9, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je + leaq , %rax + movq (%rax), %rax + movl $0xd, %ecx + movq %rcx, (%rax) movl $0x8e, %edi callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0xd, %eax - movq %rax, (%rcx) - incq %r14 - movq (%r12), %rax - cmpq $0x2c, %rax + leaq , %rax + movq %r13, (%rax) + testq %r13, %r13 jne + movl $0xc, %edx + movq %rdx, (%rcx) jmp - callq - movq 0x18(%r13), %rax - cmpq $0x82, %rax - jne + movl $0xb, %edx jmp + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax callq + movslq %eax, %rax jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movq 0x28(%r13), %rax - movq %rax, (%rcx) - testq %r14, %r14 - je jmp - movq 0x18(%r13), %rax - cmpq $0x81, %rax + movq (%r12), %rax + cmpq $0x8f, %rax jne + callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x3, %edx + movl $0x4, %edx movq %rdx, (%rcx) movq (%rax), %rcx - addq $0x8, %rcx + leaq 0x8(%rcx), %r13 + movq %r13, (%rax) + movl $0x8e, %edi + callq + movq (%r12), %rax + cmpq $0x3a, %rax + jne + callq + leaq , %r14 + movq (%r14), %rax + addq $0x18, %rax + movq %rax, (%r13) + movq (%r14), %rax + addq $0x8, %rax + movq %rax, (%r14) + movl $0x2, %ecx movq %rcx, (%rax) - movq 0x28(%r13), %rax - movq %rax, (%rcx) + movq (%r14), %rax + leaq 0x8(%rax), %r13 + movq %r13, (%r14) + movl $0x8f, %edi + callq + movq (%r14), %rax + addq $0x8, %rax + movq %rax, (%r13) jmp leaq , %rdi leaq , %rax @@ -1447,259 +1247,358 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x7, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + movq (%r12), %rax + cmpq $0x90, %rax + jne + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x5, %ecx movq %rcx, (%rax) - movq %r14, (%rcx) + movq (%r13), %rax + leaq 0x8(%rax), %r14 + movq %r14, (%r13) + movl $0x91, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r14) leaq , %rax - movq 0x20(%r13), %rcx + movl $0x1, %ecx movq %rcx, (%rax) jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + movq (%r12), %rax + cmpq $0x91, %rax + jne + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x4, %ecx movq %rcx, (%rax) - movq 0x28(%r13), %rax - movq %rax, (%rcx) + movq (%r13), %rax + leaq 0x8(%rax), %r14 + movq %r14, (%r13) + movl $0x92, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r14) leaq , %rax - movq %rdx, (%rax) + movl $0x1, %ecx + movq %rcx, (%rax) jmp - movq 0x18(%r13), %rax - cmpq $0x84, %rax + movq (%r12), %rax + cmpq $0x92, %rax jne - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx movq %rcx, (%rax) - xorq %rdx, %rdx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + movl $0x93, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xe, %ecx movq %rcx, (%rax) leaq , %rax - movq (%rax), %rax - movq 0x28(%r13), %rdx - subq %rdx, %rax - movq %rax, (%rcx) - leaq , %rax - movq (%rax), %rcx - leaq 0x8(%rcx), %r14 - movq %r14, (%rax) - leaq , %rax - movq 0x20(%r13), %rcx + movl $0x1, %ecx movq %rcx, (%rax) - testq %rcx, %rcx - jne jmp - movq 0x18(%r13), %rax - cmpq $0x83, %rax + movq (%r12), %rax + cmpq $0x93, %rax jne - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + movl $0x94, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xf, %ecx movq %rcx, (%rax) - movq 0x28(%r13), %rax - movq %rax, (%rcx) - jmp - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - jmp - movl $0xa, %ecx - jmp - movl $0x9, %ecx - movq %rcx, (%r14) - jmp - callq - movq (%r12), %rax - cmpq $0x8a, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 - jne - jmp + movl $0x1, %ecx + movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x9f, %rax + cmpq $0x94, %rax jne + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x95, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x10, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x86, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 - je - movq (%r12), %rax - cmpq $0x8a, %rax + cmpq $0x95, %rax jne + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x97, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x11, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp - jmp - movl $0x8e, %edi - callq movq (%r12), %rax - cmpq $0x29, %rax + cmpq $0x96, %rax jne - jmp - movl $0x1, %r13d - jmp - xorq %r13, %r13 callq - movq (%r12), %rax - cmpq $0x9f, %rax - jne + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x97, %edi callq - addq $0x2, %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x12, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x29, %rax + cmpq $0x97, %rax jne callq - movl $0xa2, %edi + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9b, %edi callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x13, %ecx + movq %rcx, (%rax) leaq , %rax - movq %r13, (%rax) + movl $0x1, %ecx + movq %rcx, (%rax) jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax + movq (%r12), %rax + cmpq $0x98, %rax + jne callq - movslq %eax, %rax - jmp + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9b, %edi callq - jmp - leaq , %rdi + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x14, %ecx + movq %rcx, (%rax) leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp + movq (%r12), %rax + cmpq $0x99, %rax + jne callq - movl $0xa2, %edi + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9b, %edi callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x15, %ecx + movq %rcx, (%rax) leaq , %rax - movq (%rax), %rax - cmpq $0x1, %rax - jle - jmp + movl $0x1, %ecx + movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x94, %rax + cmpq $0x9a, %rax jne - jmp - leaq , %rax - movq (%rax), %rcx - subq $0x2, %rcx + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9b, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x16, %ecx movq %rcx, (%rax) leaq , %rax - movq (%rax), %rcx - leaq 0x8(%rcx), %r13 - movq %r13, (%rax) - leaq , %rax - movq (%rax), %rax - testq %rax, %rax - jne + movl $0x1, %ecx + movq %rcx, (%rax) jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al + movq (%r12), %rax + cmpq $0x9b, %rax + jne callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9d, %edi callq - movslq %eax, %rax - jmp - movl $0xa, %ecx - jmp - movl $0x9, %ecx - movq %rcx, (%r13) + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x17, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp + movq (%r12), %rax + cmpq $0x9c, %rax + jne callq - movl $0xa2, %edi + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0x9d, %edi callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x18, %ecx + movq %rcx, (%rax) leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0xa, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 - jne - jmp + movl $0x1, %ecx + movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x21, %rax + cmpq $0x9d, %rax jne - jmp - leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0x9, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 - je + callq leaq , %rax movq (%rax), %rcx - addq $-0x8, %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movl $0xd, %eax + movq %rax, (%rcx) + movl $0x9f, %edi + callq + leaq , %rax + movq %r13, (%rax) + cmpq $0x2, %r13 + jle leaq , %rax movq (%rax), %rcx - addq $0x2, %rcx + addq $0x8, %rcx movq %rcx, (%rax) - jmp - leaq , %rdi + movl $0xd, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x8, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1b, %eax + movq %rax, (%rcx) leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x19, %eax + movq %rax, (%rcx) jmp + movq (%r12), %rax + cmpq $0x9e, %rax + jne callq - movl $0xa2, %edi + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0xd, %eax + movq %rax, (%rcx) + movl $0x9f, %edi callq + cmpq $0x2, %r13 + setg %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax + movq (%rax), %rax + cmpq %rax, %r13 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) + movl $0x1a, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) movl $0xd, %edx movq %rdx, (%rcx) movq (%rax), %rcx @@ -1710,22 +1609,20 @@ Disassembly of section .text: movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - xorq %rsi, %rsi + movl $0x8, %esi movq %rsi, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x11, %eax + movl $0x1c, %eax movq %rax, (%rcx) leaq , %rax movq %rdx, (%rax) jmp - movq (%r12), %rax - cmpq $0x7e, %rax - jne - callq - movl $0xa2, %edi - callq + leaq , %rax + movq %r13, (%rax) + cmpq $0x2, %r13 + jle leaq , %rax movq (%rax), %rcx addq $0x8, %rcx @@ -1740,67 +1637,74 @@ Disassembly of section .text: movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movabsq $-0x1, %rsi - movq %rsi, (%rcx) + movl $0x8, %edx + movq %rdx, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0xf, %eax - movq %rax, (%rcx) - leaq , %rax - movq %rdx, (%rax) - jmp - movq (%r12), %rax - cmpq $0x9d, %rax - jne - callq - movl $0xa2, %edi - callq - leaq , %rax - movl $0x1, %ecx + movl $0x1b, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movl $0x1a, %eax + movq %rax, (%rcx) jmp - movq (%r12), %rax - cmpq $0x9e, %rax - jne - callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1, %eax + movl $0x1a, %eax movq %rax, (%rcx) - movq (%r12), %rax - cmpq $0x80, %rax - jne jmp jmp movq (%r12), %rax - cmpq $0xa2, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + cmpq $0x9f, %rax jne - jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx + callq + leaq , %r13 + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0xd, %ecx movq %rcx, (%rax) - leaq , %rax - movq (%rax), %rax - imulq $-0x1, %rax, %rax - movq %rax, (%rcx) + movl $0xa2, %edi callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x1b, %ecx + movq %rcx, (%rax) leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) jmp + movq (%r12), %rax + cmpq $0xa0, %rax + jne + callq leaq , %r13 movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) - movabsq $-0x1, %rcx + movl $0xd, %ecx + movq %rcx, (%rax) + movl $0xa2, %edi + callq + movq (%r13), %rax + addq $0x8, %rax + movq %rax, (%r13) + movl $0x1c, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx movq %rcx, (%rax) + jmp + movq (%r12), %rax + cmpq $0xa1, %rax + jne + callq + leaq , %r13 movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) @@ -1811,25 +1715,132 @@ Disassembly of section .text: movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) - movl $0x1b, %ecx + movl $0x1d, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x1, %ecx movq %rcx, (%rax) jmp movq (%r12), %rax + cmpq $0xa2, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne + movq (%r12), %rax cmpq $0xa3, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - movq (%r12), %r13 - callq - movl $0xa2, %edi - callq leaq , %rax movq (%rax), %rax movq (%rax), %rax cmpq $0xa, %rax jne + leaq , %rax + movq (%rax), %rcx + movl $0xd, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0xa, %eax + movq %rax, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0xd, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + leaq , %rax + movq (%rax), %rax + cmpq $0x2, %rax + jle + movl $0x8, %edx + movq %rdx, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movq (%r12), %rax + cmpq $0xa2, %rax + jne + movl $0x19, %edx + movq %rdx, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + leaq , %rax + movq (%rax), %rax + testq %rax, %rax + jne + movl $0xc, %edx + movq %rdx, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0xd, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + leaq , %rax + movq (%rax), %rax + cmpq $0x2, %rax + jle + movl $0x8, %edx + movq %rdx, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movq (%r12), %rax + cmpq $0xa2, %rax + jne + movl $0x1a, %edx + movq %rdx, (%rcx) + callq + jmp + movl $0x19, %edx + jmp + movl $0x1, %edx + jmp + movl $0xb, %edx + jmp + movl $0x1a, %edx + jmp + movl $0x1, %edx jmp + leaq , %rax + movq (%rax), %rax + movq (%rax), %rax + cmpq $0x9, %rax + jne + leaq , %rax + movq (%rax), %rcx + movl $0xd, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x9, %eax + movq %rax, (%rcx) jmp leaq , %rdi leaq , %rax @@ -1842,49 +1853,66 @@ Disassembly of section .text: callq movslq %eax, %rax jmp + movq (%r12), %rax + cmpq $0xa4, %rax + jne + callq + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0xd, %eax + movq %rax, (%rcx) + movl $0x8e, %edi + callq + movq (%r12), %rax + cmpq $0x5d, %rax + jne + callq + cmpq $0x2, %r13 + jle leaq , %rax movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) movl $0xd, %edx movq %rdx, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0xa, %eax + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x8, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1b, %eax movq %rax, (%rcx) leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0xd, %edx + movl $0x19, %edx movq %rdx, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - leaq 0x8(%rcx), %r14 - movq %r14, (%rax) leaq , %rax - movq (%rax), %rax - cmpq $0x2, %rax - jle - jmp - leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0x9, %rax + leaq -0x2(%r13), %rdx + movq %rdx, (%rax) + testq %rdx, %rdx jne - leaq , %rax - movq (%rax), %rcx - movl $0xd, %edx + movl $0xa, %edx movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x9, %eax - movq %rax, (%rcx) jmp + movl $0x9, %edx + jmp + cmpq $0x2, %r13 + jge leaq , %rdi leaq , %rax movq (%rax), %rsi @@ -1896,513 +1924,481 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0x8, %ecx - jmp - movl $0x1, %ecx - movq %rcx, (%r14) - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - cmpq $0xa2, %r13 - jne - movl $0x19, %edx - jmp - movl $0x1a, %edx - movq %rdx, (%rcx) - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) + leaq , %rdi leaq , %rax - movq (%rax), %rax - testq %rax, %rax - jne - movl $0xc, %edx + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax jmp - movl $0xb, %edx - movq %rdx, (%rcx) jmp - movq (%r12), %rax - cmpq %rbx, %rax - jl + leaq , %rdi leaq , %rax - movq (%rax), %r13 + movq (%rax), %rsi + movq (%r12), %rdx + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax movq (%r12), %rax - cmpq $0x8e, %rax - jne - jmp + cmpq %rbx, %rax + jge xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0xf0, %rsp + addq $0x20, %rsp popq %rbp retq - callq - leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0xa, %rax - sete %r14b - movzbq %r14b, %r14 - testq %r14, %r14 - jne - jmp - jmp movq (%r12), %rax - cmpq $0x8f, %rax + cmpq $0x80, %rax jne - jmp leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0x9, %rax - sete %r14b - movzbq %r14b, %r14 - testq %r14, %r14 - je + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1, %r13d + movq %r13, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) leaq , %rax movq (%rax), %rax - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x8e, %edi + movq %rax, (%rcx) callq leaq , %rax - movq (%rax), %rcx - leaq 0x8(%rcx), %r14 - movq %r14, (%rax) - leaq , %rax movq %r13, (%rax) - testq %r13, %r13 - jne - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax jmp - movl $0xc, %ecx - jmp - movl $0xb, %ecx - movq %rcx, (%r14) - jmp - callq + movq (%r12), %rax + cmpq $0x22, %rax + jne leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x4, %edx + movl $0x1, %edx movq %rdx, (%rcx) movq (%rax), %rcx - leaq 0x8(%rcx), %r13 - movq %r13, (%rax) - movl $0x8e, %edi - callq - movq (%r12), %rax - cmpq $0x3a, %rax - jne - jmp - jmp - movq (%r12), %rax - cmpq $0x90, %rax - jne - jmp - callq - leaq , %r14 - movq (%r14), %rax - addq $0x18, %rax - movq %rax, (%r13) - movq (%r14), %rax - addq $0x8, %rax - movq %rax, (%r14) - movl $0x2, %ecx + addq $0x8, %rcx movq %rcx, (%rax) - movq (%r14), %rax - leaq 0x8(%rax), %r13 - movq %r13, (%r14) - movl $0x8f, %edi - callq - movq (%r14), %rax - addq $0x8, %rax - movq %rax, (%r13) - jmp - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax + movq (%rax), %rax + movq %rax, (%rcx) callq - movslq %eax, %rax jmp callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x5, %ecx + movq (%r12), %rax + cmpq $0x22, %rax + je + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + andq $-0x8, %rcx movq %rcx, (%rax) - movq (%r13), %rax - leaq 0x8(%rax), %r14 - movq %r14, (%r13) - movl $0x91, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r14) leaq , %rax - movl $0x1, %ecx + movl $0x2, %ecx movq %rcx, (%rax) jmp movq (%r12), %rax - cmpq $0x91, %rax + cmpq $0x8c, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x4, %ecx - movq %rcx, (%rax) - movq (%r13), %rax - leaq 0x8(%rax), %r14 - movq %r14, (%r13) - movl $0x92, %edi + movq (%r12), %rax + cmpq $0x28, %rax + jne callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r14) leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) - jmp movq (%r12), %rax - cmpq $0x92, %rax + cmpq $0x8a, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x93, %edi + jmp callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xe, %ecx - movq %rcx, (%rax) leaq , %rax - movl $0x1, %ecx + movq (%rax), %rcx + addq $0x2, %rcx movq %rcx, (%rax) - jmp movq (%r12), %rax - cmpq $0x93, %rax + cmpq $0x9f, %rax + je + movq (%r12), %rax + cmpq $0x29, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - movl $0x94, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xf, %ecx + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) leaq , %rax + movq (%rax), %rax + testq %rax, %rax + jne + movl $0x1, %edx + movq %rdx, (%rcx) + leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) jmp + movl $0x8, %edx + jmp + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + jmp movq (%r12), %rax - cmpq $0x94, %rax + cmpq $0x86, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x95, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x10, %ecx - movq %rcx, (%rax) leaq , %rax - movl $0x1, %ecx + xorq %rcx, %rcx movq %rcx, (%rax) jmp + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + jmp movq (%r12), %rax - cmpq $0x95, %rax + cmpq $0x85, %rax jne + leaq , %rax + movq (%rax), %r13 callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x97, %edi + movq (%r12), %rax + cmpq $0x28, %rax + jne + callq + xorq %r14, %r14 + jmp + movl $0x8e, %edi callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x11, %ecx - movq %rcx, (%rax) leaq , %rax - movl $0x1, %ecx + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - jmp + movl $0xd, %eax + movq %rax, (%rcx) + incq %r14 movq (%r12), %rax - cmpq $0x96, %rax + cmpq $0x2c, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x97, %edi + movq (%r12), %rax + cmpq $0x29, %rax + jne callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x12, %ecx + movq 0x18(%r13), %rax + cmpq $0x82, %rax + jne + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movq 0x28(%r13), %rax + movq %rax, (%rcx) + testq %r14, %r14 + je leaq , %rax - movl $0x1, %ecx + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x7, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movq %r14, (%rcx) + leaq , %rax + movq 0x20(%r13), %rcx movq %rcx, (%rax) jmp - movq (%r12), %rax - cmpq $0x97, %rax + movq 0x18(%r13), %rax + cmpq $0x81, %rax jne - callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - movl $0x9b, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x13, %ecx + movl $0x3, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movq 0x28(%r13), %rax + movq %rax, (%rcx) + jmp + leaq , %rdi leaq , %rax - movl $0x1, %ecx + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + jmp + movq 0x18(%r13), %rax + cmpq $0x80, %rax + jne + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movq 0x28(%r13), %rax + movq %rax, (%rcx) + leaq , %rax + movq %rdx, (%rax) jmp - movq (%r12), %rax - cmpq $0x98, %rax + movq 0x18(%r13), %rax + cmpq $0x84, %rax jne - callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - movl $0x9b, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x14, %ecx + xorq %rdx, %rdx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) leaq , %rax - movl $0x1, %ecx + movq (%rax), %rax + movq 0x28(%r13), %rdx + subq %rdx, %rax + movq %rax, (%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + leaq , %rax + movq 0x20(%r13), %rdx + movq %rdx, (%rax) + testq %rdx, %rdx + jne + movl $0xa, %edx + movq %rdx, (%rcx) jmp - movq (%r12), %rax - cmpq $0x99, %rax + movl $0x9, %edx + jmp + movq 0x18(%r13), %rax + cmpq $0x83, %rax jne - callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - movl $0x9b, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x15, %ecx + movl $0x1, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) + movq 0x28(%r13), %rax + movq %rax, (%rcx) + jmp + leaq , %rdi leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax jmp movq (%r12), %rax - cmpq $0x9a, %rax + cmpq $0x28, %rax + jne + callq + movq (%r12), %rax + cmpq $0x8a, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne + movq (%r12), %rax + cmpq $0x86, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + movq (%r12), %rax + cmpq $0x8a, %rax jne + movl $0x1, %r13d callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x9b, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x16, %ecx - movq %rcx, (%rax) - leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) jmp + callq + addq $0x2, %r13 movq (%r12), %rax - cmpq $0x9b, %rax + cmpq $0x9f, %rax + je + movq (%r12), %rax + cmpq $0x29, %rax jne callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x9d, %edi + movl $0xa2, %edi callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x17, %ecx - movq %rcx, (%rax) leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) + movq %r13, (%rax) jmp - movq (%r12), %rax - cmpq $0x9c, %rax - jne + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0x9d, %edi + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x18, %ecx - movq %rcx, (%rax) - leaq , %rax - movl $0x1, %ecx - movq %rcx, (%rax) + movslq %eax, %rax + jmp + xorq %r13, %r13 jmp + movl $0x8e, %edi + callq movq (%r12), %rax - cmpq $0x9d, %rax + cmpq $0x29, %rax jne callq + jmp + leaq , %rdi leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0xd, %eax - movq %rax, (%rcx) - movl $0x9f, %edi + movq (%rax), %rsi + movb $0x0, %al callq - leaq , %rax - movq %r13, (%rax) - cmpq $0x2, %r13 - jle + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax jmp jmp movq (%r12), %rax - cmpq $0x9e, %rax + cmpq $0x9f, %rax jne - jmp + callq + movl $0xa2, %edi + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x1, %rax + jle leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0xd, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx + subq $0x2, %rcx movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) + leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x8, %edx + leaq , %rax + movq (%rax), %rax + testq %rax, %rax + jne + movl $0xa, %edx movq %rdx, (%rcx) + jmp + movl $0x9, %edx + jmp + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + jmp + movq (%r12), %rax + cmpq $0x94, %rax + jne + callq + movl $0xa2, %edi + callq + leaq , %rax + movq (%rax), %rax + movq (%rax), %rax + cmpq $0xa, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne + leaq , %rax + movq (%rax), %rax + movq (%rax), %rax + cmpq $0x9, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je + leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx + addq $-0x8, %rcx movq %rcx, (%rax) - movl $0x1b, %eax - movq %rax, (%rcx) leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx + addq $0x2, %rcx movq %rcx, (%rax) - movl $0x19, %eax - movq %rax, (%rcx) jmp - callq + leaq , %rdi leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0xd, %eax - movq %rax, (%rcx) - movl $0x9f, %edi + movq (%rax), %rsi + movb $0x0, %al callq - cmpq $0x2, %r13 - setg %r14b - movzbq %r14b, %r14 - testq %r14, %r14 - je + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax jmp jmp movq (%r12), %rax - cmpq $0x9f, %rax + cmpq $0x21, %rax jne - jmp - leaq , %rax - movq (%rax), %rax - cmpq %rax, %r13 - sete %r14b - movzbq %r14b, %r14 - testq %r14, %r14 - je + callq + movl $0xa2, %edi + callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1a, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) movl $0xd, %edx movq %rdx, (%rcx) movq (%rax), %rcx @@ -2413,20 +2409,22 @@ Disassembly of section .text: movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x8, %esi + xorq %rsi, %rsi movq %rsi, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1c, %eax + movl $0x11, %eax movq %rax, (%rcx) leaq , %rax movq %rdx, (%rax) jmp - leaq , %rax - movq %r13, (%rax) - cmpq $0x2, %r13 - jle + movq (%r12), %rax + cmpq $0x7e, %rax + jne + callq + movl $0xa2, %edi + callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx @@ -2441,70 +2439,58 @@ Disassembly of section .text: movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x8, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1b, %edx - movq %rdx, (%rcx) + movabsq $-0x1, %rsi + movq %rsi, (%rcx) movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1a, %eax + movl $0xf, %eax movq %rax, (%rcx) + leaq , %rax + movq %rdx, (%rax) + jmp + movq (%r12), %rax + cmpq $0x9d, %rax + jne + callq + movl $0xa2, %edi + callq + leaq , %rax + movl $0x1, %ecx + movq %rcx, (%rax) jmp + movq (%r12), %rax + cmpq $0x9e, %rax + jne + callq leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0x1a, %eax + movl $0x1, %eax movq %rax, (%rcx) - jmp - callq - leaq , %r13 - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0xd, %ecx + movq (%r12), %rax + cmpq $0x80, %rax + jne + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx movq %rcx, (%rax) - movl $0xa2, %edi + leaq , %rax + movq (%rax), %rax + imulq $-0x1, %rax, %rax + movq %rax, (%rcx) callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x1b, %ecx - movq %rcx, (%rax) leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) jmp - movq (%r12), %rax - cmpq $0xa0, %rax - jne - callq leaq , %r13 movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) - movl $0xd, %ecx - movq %rcx, (%rax) - movl $0xa2, %edi - callq - movq (%r13), %rax - addq $0x8, %rax - movq %rax, (%r13) - movl $0x1c, %ecx - movq %rcx, (%rax) - leaq , %rax - movl $0x1, %ecx + movabsq $-0x1, %rcx movq %rcx, (%rax) - jmp - movq (%r12), %rax - cmpq $0xa1, %rax - jne - callq - leaq , %r13 movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) @@ -2515,35 +2501,30 @@ Disassembly of section .text: movq (%r13), %rax addq $0x8, %rax movq %rax, (%r13) - movl $0x1d, %ecx - movq %rcx, (%rax) - leaq , %rax - movl $0x1, %ecx + movl $0x1b, %ecx movq %rcx, (%rax) jmp movq (%r12), %rax cmpq $0xa2, %rax - sete %r14b - movzbq %r14b, %r14 - testq %r14, %r14 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne movq (%r12), %rax cmpq $0xa3, %rax - sete %r14b - movzbq %r14b, %r14 - testq %r14, %r14 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je + movq (%r12), %r13 + callq + movl $0xa2, %edi + callq leaq , %rax movq (%rax), %rax movq (%rax), %rax cmpq $0xa, %rax jne - jmp - jmp - movq (%r12), %rax - cmpq $0xa4, %rax - jne - jmp leaq , %rax movq (%rax), %rcx movl $0xd, %edx @@ -2565,53 +2546,21 @@ Disassembly of section .text: movl $0x1, %edx movq %rdx, (%rcx) movq (%rax), %rcx - leaq 0x8(%rcx), %r13 - movq %r13, (%rax) + addq $0x8, %rcx + movq %rcx, (%rax) leaq , %rax movq (%rax), %rax cmpq $0x2, %rax jle - jmp - leaq , %rax - movq (%rax), %rax - movq (%rax), %rax - cmpq $0x9, %rax - jne - leaq , %rax - movq (%rax), %rcx - movl $0xd, %edx + movl $0x8, %edx movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x9, %eax - movq %rax, (%rcx) - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - jmp - movl $0x8, %ecx - jmp - movl $0x1, %ecx - movq %rcx, (%r13) leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movq (%r12), %rax - cmpq $0xa2, %rax + cmpq $0xa2, %r13 jne movl $0x19, %edx - jmp - movl $0x1a, %edx movq %rdx, (%rcx) leaq , %rax movq (%rax), %rcx @@ -2622,62 +2571,32 @@ Disassembly of section .text: testq %rax, %rax jne movl $0xc, %edx + movq %rdx, (%rcx) jmp movl $0xb, %edx - movq %rdx, (%rcx) - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0xd, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) + jmp + movl $0x1a, %edx + jmp movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) + jmp leaq , %rax movq (%rax), %rax - cmpq $0x2, %rax - jle - movl $0x8, %edx - jmp - movl $0x1, %edx - movq %rdx, (%rcx) + movq (%rax), %rax + cmpq $0x9, %rax + jne leaq , %rax movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movq (%r12), %rax - cmpq $0xa2, %rax - jne - movl $0x1a, %edx - jmp - movl $0x19, %edx + movl $0xd, %edx movq %rdx, (%rcx) - callq - jmp - callq - leaq , %rax movq (%rax), %rcx addq $0x8, %rcx movq %rcx, (%rax) - movl $0xd, %eax + movl $0x9, %eax movq %rax, (%rcx) - movl $0x8e, %edi - callq - movq (%r12), %rax - cmpq $0x5d, %rax - jne - jmp jmp leaq , %rdi leaq , %rax movq (%rax), %rsi - movq (%r12), %rdx movb $0x0, %al callq movslq %eax, %rax @@ -2686,10 +2605,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - callq - cmpq $0x2, %r13 - jle - jmp leaq , %rdi leaq , %rax movq (%rax), %rsi @@ -2701,59 +2616,48 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0xd, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x8, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x1b, %eax - movq %rax, (%rcx) - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x19, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - leaq 0x8(%rcx), %r14 - movq %r14, (%rax) - leaq , %rax - leaq -0x2(%r13), %rcx - movq %rcx, (%rax) - testq %rcx, %rcx - jne jmp - cmpq $0x2, %r13 - jge - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax jmp - movl $0xa, %ecx jmp - movl $0x9, %ecx - movq %rcx, (%r14) + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp jmp jmp jmp @@ -2765,7 +2669,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -2777,36 +2681,12 @@ Disassembly of section .text: movq (%rbx), %rax cmpq $0x28, %rax jne - jmp - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x40, %rsp - popq %rbp - retq - movq (%rbx), %rax - cmpq $0x8d, %rax - jne - jmp - callq - movl $0x8e, %edi - callq - movq (%rbx), %rax - cmpq $0x29, %rax - jne - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax callq - movslq %eax, %rax - jmp + movl $0x8e, %edi + callq + movq (%rbx), %rax + cmpq $0x29, %rax + jne callq leaq , %rax movq (%rax), %rcx @@ -2821,18 +2701,6 @@ Disassembly of section .text: movq (%rbx), %rax cmpq $0x87, %rax jne - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - jmp leaq , %rax movq (%rax), %rcx addq $0x18, %rcx @@ -2851,26 +2719,24 @@ Disassembly of section .text: movq (%rax), %rax addq $0x8, %rax movq %rax, (%r12) + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0x20, %rsp + popq %rbp + retq jmp - callq + leaq , %rdi leaq , %rax - movq (%rax), %rax - leaq 0x8(%rax), %r12 - movq (%rbx), %rax - cmpq $0x28, %rax - jne - jmp - jmp - movq (%rbx), %rax - cmpq $0x8b, %rax - jne - jmp + movq (%rax), %rsi + movb $0x0, %al callq - movl $0x8e, %edi + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax callq - movq (%rbx), %rax - cmpq $0x29, %rax - jne + movslq %eax, %rax jmp leaq , %rdi leaq , %rax @@ -2883,6 +2749,22 @@ Disassembly of section .text: callq movslq %eax, %rax jmp + movq (%rbx), %rax + cmpq $0x8d, %rax + jne + callq + leaq , %rax + movq (%rax), %rax + leaq 0x8(%rax), %r12 + movq (%rbx), %rax + cmpq $0x28, %rax + jne + callq + movl $0x8e, %edi + callq + movq (%rbx), %rax + cmpq $0x29, %rax + jne callq leaq , %rbx movq (%rbx), %rax @@ -2918,16 +2800,24 @@ Disassembly of section .text: callq movslq %eax, %rax jmp + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al callq - movq (%rbx), %rax - cmpq $0x3b, %rax - je - jmp + movslq %eax, %rax + movabsq $-0x1, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax jmp movq (%rbx), %rax - cmpq $0x7b, %rax + cmpq $0x8b, %rax jne - jmp + callq + movq (%rbx), %rax + cmpq $0x3b, %rax + je movl $0x8e, %edi callq leaq , %rax @@ -2952,20 +2842,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - callq - jmp - jmp movq (%rbx), %rax - cmpq $0x3b, %rax + cmpq $0x7b, %rax jne + callq jmp + callq movq (%rbx), %rax cmpq $0x7d, %rax - je - callq - jmp + jne callq jmp + movq (%rbx), %rax + cmpq $0x3b, %rax + jne callq jmp movl $0x8e, %edi @@ -2987,6 +2877,11 @@ Disassembly of section .text: movslq %eax, %rax jmp jmp + jmp + jmp + jmp + jmp + jmp
: pushq %rbp @@ -2997,65 +2892,65 @@ Disassembly of section .text: movq %r13, 0x10(%rsp) movq %r14, 0x18(%rsp) movq %r15, 0x20(%rsp) - leaq -0x1(%rdi), %r12 - leaq 0x8(%rsi), %r13 - testq %r12, %r12 + leaq -0x1(%rdi), %rbx + leaq 0x8(%rsi), %r12 + testq %rbx, %rbx setg %al movzbq %al, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je - movq (%r13), %rax + movq (%r12), %rax movsbq (%rax), %rax cmpq $0x2d, %rax sete %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je - movq (%r13), %rax + movq (%r12), %rax movsbq 0x1(%rax), %rax cmpq $0x73, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) - decq %r12 - addq $0x8, %r13 - testq %r12, %r12 + decq %rbx + addq $0x8, %r12 + testq %rbx, %rbx setg %al movzbq %al, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je - movq (%r13), %rax + movq (%r12), %rax movsbq (%rax), %rax cmpq $0x2d, %rax sete %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je - movq (%r13), %rax + movq (%r12), %rax movsbq 0x1(%rax), %rax cmpq $0x64, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rax movl $0x1, %ecx movq %rcx, (%rax) - decq %r12 - addq $0x8, %r13 - cmpq $0x1, %r12 + decq %rbx + addq $0x8, %r12 + cmpq $0x1, %rbx jge leaq , %rdi movb $0x0, %al @@ -3070,16 +2965,16 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - movq (%r13), %rdi + movq (%r12), %rdi xorq %rsi, %rsi movb $0x0, %al callq movslq %eax, %rax - movq %rax, %rbx - testq %rbx, %rbx + movq %rax, %r13 + testq %r13, %r13 jge leaq , %rdi - movq (%r13), %rsi + movq (%r12), %rsi movb $0x0, %al callq movslq %eax, %rax @@ -3094,7 +2989,7 @@ Disassembly of section .text: retq movl $0x40000, %r14d # imm = 0x40000 leaq , %r15 - movslq %r14d, %rdi + movl $0x40000, %edi # imm = 0x40000 xorl %eax, %eax callq movq %rax, (%r15) @@ -3117,7 +3012,7 @@ Disassembly of section .text: leaq , %r15 leaq , %r10 movq %r10, 0x48(%rsp) - movslq %r14d, %rdi + movl $0x40000, %edi # imm = 0x40000 xorl %eax, %eax callq movq 0x48(%rsp), %r10 @@ -3140,7 +3035,7 @@ Disassembly of section .text: popq %rbp retq leaq , %r15 - movslq %r14d, %rdi + movl $0x40000, %edi # imm = 0x40000 xorl %eax, %eax callq movq %rax, (%r15) @@ -3160,7 +3055,7 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - movslq %r14d, %rdi + movl $0x40000, %edi # imm = 0x40000 xorl %eax, %eax callq movq %rax, %r15 @@ -3184,19 +3079,19 @@ Disassembly of section .text: movq (%rax), %rdi xorq %r10, %r10 movq %r10, 0x48(%rsp) - movslq %r14d, %rdx + movl $0x40000, %edx # imm = 0x40000 movq 0x48(%rsp), %rsi xorl %eax, %eax callq leaq , %rax movq (%rax), %rdi - movslq %r14d, %rdx + movl $0x40000, %edx # imm = 0x40000 movq 0x48(%rsp), %rsi xorl %eax, %eax callq leaq , %rax movq (%rax), %rdi - movslq %r14d, %rdx + movl $0x40000, %edx # imm = 0x40000 movq 0x48(%rsp), %rsi xorl %eax, %eax callq @@ -3205,23 +3100,166 @@ Disassembly of section .text: movq %rcx, (%rax) movl $0x86, %r10d movq %r10, 0x48(%rsp) - movq 0x48(%rsp), %rax - cmpq $0x8d, %rax - jg callq leaq , %rax movq (%rax), %rax - movq 0x48(%rsp), %rcx - incq %rcx + movl $0x87, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x88, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x89, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x8a, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x8b, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x8c, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movl $0x8d, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, (%rax) + callq + leaq , %rax + movq (%rax), %rax + movq 0x40(%rsp), %r11 + movq %r11, (%rax) + movl $0x1e, %r10d + movq %r10, 0x48(%rsp) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x1f, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x20, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x21, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x22, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x23, %r10d + movq %r10, 0x40(%rsp) + movq 0x48(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x24, %r10d + movq %r10, 0x48(%rsp) + movq 0x40(%rsp), %r11 + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x25, %r10d + movq %r10, 0x40(%rsp) movq 0x48(%rsp), %r11 - movq %r11, (%rax) - movq %rcx, 0x48(%rsp) - jmp - movl $0x1e, %r10d + movq %r11, 0x28(%rax) + callq + leaq , %rax + movq (%rax), %rcx + movl $0x82, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movl $0x1, %edx + movq %rdx, 0x20(%rcx) + movq (%rax), %rax + movl $0x26, %r10d movq %r10, 0x48(%rsp) - movq 0x48(%rsp), %rax - cmpq $0x26, %rax - jg + movq 0x40(%rsp), %r11 + movq %r11, 0x28(%rax) callq leaq , %rax movq (%rax), %rcx @@ -3231,12 +3269,8 @@ Disassembly of section .text: movl $0x1, %edx movq %rdx, 0x20(%rcx) movq (%rax), %rax - movq 0x48(%rsp), %rcx - incq %rcx movq 0x48(%rsp), %r11 movq %r11, 0x28(%rax) - movq %rcx, 0x48(%rsp) - jmp callq leaq , %r10 movq %r10, 0x48(%rsp) @@ -3252,7 +3286,7 @@ Disassembly of section .text: movq %r10, 0x40(%rsp) leaq , %r10 movq %r10, 0x38(%rsp) - movslq %r14d, %rdi + movl $0x40000, %edi # imm = 0x40000 xorl %eax, %eax callq movq 0x38(%rsp), %r10 @@ -3275,21 +3309,17 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - movslq %ebx, %rdi + movslq %r13d, %rdi leaq , %rax movq (%rax), %rsi - leaq -0x1(%r14), %rax - movslq %eax, %rdx + movl $0x3ffff, %edx # imm = 0x3FFFF xorl %eax, %eax callq movslq %eax, %rax - movq %rax, %r10 - movq %r10, 0x40(%rsp) - movq 0x40(%rsp), %rax testq %rax, %rax jg leaq , %rdi - movq 0x40(%rsp), %rsi + movq %rax, %rsi movb $0x0, %al callq movslq %eax, %rax @@ -3302,12 +3332,12 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - leaq , %rax - movq (%rax), %rax - addq 0x40(%rsp), %rax + leaq , %rcx + movq (%rcx), %rcx + addq %rcx, %rax xorq %rcx, %rcx movb %cl, (%rax) - movslq %ebx, %rdi + movslq %r13d, %rdi xorl %eax, %eax callq movslq %eax, %rax @@ -3315,204 +3345,46 @@ Disassembly of section .text: movl $0x1, %ecx movq %rcx, (%rax) callq - leaq , %rax - movq (%rax), %rax - testq %rax, %rax - je - movl $0x1, %ebx - leaq , %rax - movq (%rax), %rax - cmpq $0x8a, %rax - jne - jmp - movq 0x48(%rsp), %r10 - movq 0x28(%r10), %r10 - movq %r10, 0x48(%rsp) - movq 0x48(%rsp), %rax - testq %rax, %rax - jne - jmp - callq - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x86, %rax - jne - callq - xorq %rbx, %rbx - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x88, %rax - jne - callq - leaq , %rax - movq (%rax), %rax - cmpq $0x7b, %rax - je - jmp - jmp - callq - leaq , %rax - movq (%rax), %rax - cmpq $0x7b, %rax - jne - callq - xorq %r10, %r10 - movq %r10, 0x40(%rsp) - jmp - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x7d, %rax - je - leaq , %rax - movq (%rax), %rax - cmpq $0x85, %rax - je - jmp - callq - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - leaq , %rax - movq (%rax), %rdx - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq - callq - leaq , %rax - movq (%rax), %rax - cmpq $0x8e, %rax - jne - callq - leaq , %rax - movq (%rax), %rax - cmpq $0x80, %rax - je jmp - leaq , %rax - movq (%rax), %rcx - movl $0x80, %edx - movq %rdx, 0x18(%rcx) - movq (%rax), %rcx - movl $0x1, %edx - movq %rdx, 0x20(%rcx) - movq (%rax), %rax - movq 0x38(%rsp), %r10 - incq %r10 - movq %r10, 0x40(%rsp) - movq 0x38(%rsp), %r11 - movq %r11, 0x28(%rax) + movl $0x1, %r13d leaq , %rax movq (%rax), %rax - cmpq $0x2c, %rax + cmpq $0x8a, %rax jne - jmp - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq - leaq , %rax - movq (%rax), %r10 - movq %r10, 0x38(%rsp) callq - jmp - callq - jmp leaq , %rax movq (%rax), %rax cmpq $0x3b, %rax - setne %r10b - movzbq %r10b, %r10 - movq %r10, 0x40(%rsp) - movq 0x40(%rsp), %r10 - testq %r10, %r10 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - jmp - movq %rbx, 0x40(%rsp) - jmp - callq - jmp leaq , %rax movq (%rax), %rax cmpq $0x7d, %rax - setne %r10b - movzbq %r10b, %r10 - movq %r10, 0x40(%rsp) - movq 0x40(%rsp), %r10 - testq %r10, %r10 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je + movq %r13, 0x40(%rsp) jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x9f, %rax - jne callq movq 0x40(%rsp), %r10 addq $0x2, %r10 movq %r10, 0x40(%rsp) - jmp leaq , %rax movq (%rax), %rax - cmpq $0x85, %rax + cmpq $0x9f, %rax je - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + movq (%rax), %rax + cmpq $0x85, %rax + jne leaq , %rax movq (%rax), %rax movq 0x18(%rax), %rax testq %rax, %rax - je - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + jne callq leaq , %rax movq (%rax), %rax @@ -3535,98 +3407,31 @@ Disassembly of section .text: xorq %r10, %r10 movq %r10, 0x40(%rsp) jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x2c, %rax - jne - jmp - leaq , %rax - movq (%rax), %rcx - movl $0x83, %edx - movq %rdx, 0x18(%rcx) - movq (%rax), %rax - leaq , %rcx - movq (%rcx), %rdx - movq %rdx, 0x28(%rax) - movq (%rcx), %rax - addq $0x8, %rax - movq %rax, (%rcx) - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x29, %rax - je movl $0x1, %r10d movq %r10, 0x38(%rsp) leaq , %rax movq (%rax), %rax cmpq $0x8a, %rax jne - jmp - callq - leaq , %rax - movq (%rax), %rax - cmpq $0x7b, %rax - je - jmp callq jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x86, %rax - jne callq - xorq %r10, %r10 + movq 0x38(%rsp), %r10 + addq $0x2, %r10 movq %r10, 0x38(%rsp) - jmp leaq , %rax movq (%rax), %rax cmpq $0x9f, %rax - jne - callq - movq 0x38(%rsp), %r10 - addq $0x2, %r10 - movq %r10, 0x38(%rsp) - jmp + je leaq , %rax movq (%rax), %rax cmpq $0x85, %rax - je - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + jne leaq , %rax movq (%rax), %rax movq 0x18(%rax), %rax cmpq $0x84, %rax - jne - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + je leaq , %rax movq (%rax), %rcx movq 0x18(%rcx), %rdx @@ -3655,24 +3460,27 @@ Disassembly of section .text: cmpq $0x2c, %rax jne callq + jmp + leaq , %rax + movq (%rax), %rax + cmpq $0x86, %rax + jne + callq + xorq %r10, %r10 + movq %r10, 0x38(%rsp) + jmp + jmp movq 0x38(%rsp), %r11 movq %r11, 0x40(%rsp) - jmp - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al + movq (%rax), %rax + cmpq $0x29, %rax + jne callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + leaq , %rax + movq (%rax), %rax + cmpq $0x7b, %rax + jne leaq , %rax movq 0x40(%rsp), %r10 incq %r10 @@ -3683,104 +3491,43 @@ Disassembly of section .text: leaq , %rax movq (%rax), %rax cmpq $0x8a, %rax - sete %r10b - movzbq %r10b, %r10 - movq %r10, 0x38(%rsp) - movq 0x38(%rsp), %r10 - testq %r10, %r10 - jne - jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x8a, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne - jmp - leaq , %rax - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - movl $0x6, %edx - movq %rdx, (%rcx) - movq (%rax), %rcx - addq $0x8, %rcx - movq %rcx, (%rax) - leaq , %rax - movq (%rax), %rax - movq %rax, %r10 - movq 0x40(%rsp), %rax - subq %r10, %rax - movq %rax, (%rcx) - jmp leaq , %rax movq (%rax), %rax cmpq $0x86, %rax - sete %r10b - movzbq %r10b, %r10 - movq %r10, 0x38(%rsp) - movq 0x38(%rsp), %r10 - testq %r10, %r10 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je - jmp - movl $0x1, %ebx - jmp - xorq %rbx, %rbx - callq leaq , %rax movq (%rax), %rax - cmpq $0x3b, %rax - je - movq %rbx, 0x38(%rsp) - jmp + cmpq $0x8a, %rax + jne + movl $0x1, %r13d callq jmp - leaq , %rax - movq (%rax), %rax - cmpq $0x9f, %rax - jne + movq %r13, 0x38(%rsp) + jmp callq movq 0x38(%rsp), %r10 addq $0x2, %r10 movq %r10, 0x38(%rsp) - jmp leaq , %rax movq (%rax), %rax - cmpq $0x85, %rax + cmpq $0x9f, %rax je - leaq , %rdi leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + movq (%rax), %rax + cmpq $0x85, %rax + jne leaq , %rax movq (%rax), %rax movq 0x18(%rax), %rax cmpq $0x84, %rax - jne - leaq , %rdi - leaq , %rax - movq (%rax), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq + je leaq , %rax movq (%rax), %rcx movq 0x18(%rcx), %rdx @@ -3809,13 +3556,36 @@ Disassembly of section .text: cmpq $0x2c, %rax jne callq - jmp leaq , %rax movq (%rax), %rax - cmpq $0x7d, %rax - je + cmpq $0x3b, %rax + jne callq jmp + xorq %r13, %r13 + jmp + jmp + leaq , %rax + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + movl $0x6, %edx + movq %rdx, (%rcx) + movq (%rax), %rcx + addq $0x8, %rcx + movq %rcx, (%rax) + leaq , %rax + movq (%rax), %rax + movq %rax, %r10 + movq 0x40(%rsp), %rax + subq %r10, %rax + movq %rax, (%rcx) + jmp + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x7d, %rax + jne leaq , %rax movq (%rax), %rcx addq $0x8, %rcx @@ -3826,35 +3596,130 @@ Disassembly of section .text: leaq , %rcx movq (%rcx), %rcx movq %rcx, (%rax) + jmp + leaq , %rax + movq (%rax), %rax + movq 0x18(%rax), %rax + cmpq $0x84, %rax + jne + leaq , %rax + movq (%rax), %rcx + movq 0x30(%rcx), %rdx + movq %rdx, 0x18(%rcx) + movq (%rax), %rcx + movq 0x38(%rcx), %rdx + movq %rdx, 0x20(%rcx) + movq (%rax), %rcx + movq 0x40(%rcx), %rax + movq %rax, 0x28(%rcx) + leaq , %rax + movq (%rax), %rcx + addq $0x48, %rcx + movq %rcx, (%rax) leaq , %rax movq (%rax), %rax movq (%rax), %rax testq %rax, %rax - je + jne leaq , %rax movq (%rax), %rax - movq 0x18(%rax), %rax - cmpq $0x84, %rax + cmpq $0x2c, %rax + jne + callq + jmp + leaq , %rax + movq (%rax), %rcx + movl $0x83, %edx + movq %rdx, 0x18(%rcx) + movq (%rax), %rax + leaq , %rcx + movq (%rcx), %rdx + movq %rdx, 0x28(%rax) + movq (%rcx), %rax + addq $0x8, %rax + movq %rax, (%rcx) + jmp + jmp + leaq , %rax + movq (%rax), %rax + cmpq $0x86, %rax jne + callq + xorq %r13, %r13 jmp + leaq , %rax + movq (%rax), %rax + cmpq $0x88, %rax + jne + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x7b, %rax + je + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x7b, %rax + jne + callq + xorq %r10, %r10 + movq %r10, 0x40(%rsp) jmp leaq , %rax + movq (%rax), %rax + cmpq $0x85, %rax + jne + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x8e, %rax + jne + callq + leaq , %rax + movq (%rax), %rax + cmpq $0x80, %rax + jne + leaq , %rax + movq (%rax), %r10 + movq %r10, 0x38(%rsp) + callq + leaq , %rax movq (%rax), %rcx - movq 0x30(%rcx), %rdx + movl $0x80, %edx movq %rdx, 0x18(%rcx) movq (%rax), %rcx - movq 0x38(%rcx), %rdx + movl $0x1, %edx movq %rdx, 0x20(%rcx) - movq (%rax), %rcx - movq 0x40(%rcx), %rax - movq %rax, 0x28(%rcx) + movq (%rax), %rax + movq 0x38(%rsp), %r10 + incq %r10 + movq %r10, 0x40(%rsp) + movq 0x38(%rsp), %r11 + movq %r11, 0x28(%rax) leaq , %rax - movq (%rax), %rcx - addq $0x48, %rcx - movq %rcx, (%rax) + movq (%rax), %rax + cmpq $0x2c, %rax + jne + callq jmp + movq 0x40(%rsp), %r11 + movq %r11, 0x38(%rsp) + jmp + leaq , %rax + movq (%rax), %rax + cmpq $0x7d, %rax + jne callq jmp + callq + leaq , %rax + movq (%rax), %rax + testq %rax, %rax + jne + movq 0x48(%rsp), %r10 + movq 0x28(%r10), %rsi + testq %rsi, %rsi + jne leaq , %rdi movb $0x0, %al callq @@ -3881,39 +3746,27 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - addq %r15, %r14 - leaq -0x8(%r14), %rax + leaq (%r15,%r14), %r13 + leaq -0x8(%r13), %rax movl $0x26, %ecx movq %rcx, (%rax) addq $-0x8, %rax movl $0xd, %ecx movq %rcx, (%rax) leaq -0x8(%rax), %rcx - movq %r12, (%rcx) + movq %rbx, (%rcx) addq $-0x8, %rcx - movq %r13, (%rcx) + movq %r12, (%rcx) leaq -0x8(%rcx), %r12 movq %rax, (%r12) xorq %rbx, %rbx - movq 0x48(%rsp), %r13 - addq $0x8, %r13 - movq 0x48(%rsp), %r10 - movq (%r10), %r15 + leaq 0x8(%rsi), %r14 + movq (%rsi), %r15 incq %rbx leaq , %rax movq (%rax), %rax testq %rax, %rax je - jmp - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 - popq %rbp - retq leaq , %rdi leaq , %rax leaq (%r15,%r15,4), %rcx @@ -3924,110 +3777,85 @@ Disassembly of section .text: movslq %eax, %rax cmpq $0x7, %r15 jg - jmp - testq %r15, %r15 - jne - jmp - leaq , %rdi - movq (%r13), %rsi - movb $0x0, %al - callq - movslq %eax, %rax - jmp leaq , %rdi + movq (%r14), %rsi movb $0x0, %al callq movslq %eax, %rax - jmp - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - movq (%r13), %rax + testq %r15, %r15 + jne + leaq 0x8(%r14), %rsi + movq (%r14), %rax shlq $0x3, %rax - addq %r14, %rax + addq %r13, %rax movq %rax, -0x48(%rbp) jmp cmpq $0x1, %r15 jne - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - movq (%r13), %rax + leaq 0x8(%r14), %rsi + movq (%r14), %rax movq %rax, -0x48(%rbp) jmp cmpq $0x2, %r15 jne - movq (%r13), %r10 - movq %r10, 0x48(%rsp) + movq (%r14), %rsi jmp cmpq $0x3, %r15 jne addq $-0x8, %r12 - leaq 0x8(%r13), %rax + leaq 0x8(%r14), %rax movq %rax, (%r12) - movq (%r13), %r10 - movq %r10, 0x48(%rsp) + movq (%r14), %rsi jmp cmpq $0x4, %r15 jne movq -0x48(%rbp), %rax testq %rax, %rax je + leaq 0x8(%r14), %rsi jmp + movq (%r14), %rsi jmp cmpq $0x5, %r15 jne - jmp - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - jmp - movq (%r13), %r10 - movq %r10, 0x48(%rsp) - jmp movq -0x48(%rbp), %rax testq %rax, %rax je + movq (%r14), %rsi jmp + leaq 0x8(%r14), %rsi jmp cmpq $0x6, %r15 jne - jmp - movq (%r13), %r10 - movq %r10, 0x48(%rsp) - jmp - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - jmp leaq -0x8(%r12), %rax - movq %r14, (%rax) - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - movq (%r13), %rcx + movq %r13, (%rax) + leaq 0x8(%r14), %rsi + movq (%r14), %rcx shlq $0x3, %rcx movq %rax, %r12 subq %rcx, %r12 - movq %rax, %r14 + movq %rax, %r13 jmp cmpq $0x7, %r15 jne - leaq 0x8(%r13), %r10 - movq %r10, 0x48(%rsp) - movq (%r13), %rax + leaq 0x8(%r14), %rsi + movq (%r14), %rax shlq $0x3, %rax addq %rax, %r12 jmp cmpq $0x8, %r15 jne - leaq 0x8(%r14), %rax - movq (%r14), %r14 + leaq 0x8(%r13), %rax + movq (%r13), %r13 leaq 0x8(%rax), %r12 - movq (%rax), %r10 - movq %r10, 0x48(%rsp) + movq (%rax), %rsi jmp cmpq $0x9, %r15 jne movq -0x48(%rbp), %rax movq (%rax), %rax movq %rax, -0x48(%rbp) - movq %r13, 0x48(%rsp) + movq %r14, %rsi jmp cmpq $0xa, %r15 jne @@ -4270,7 +4098,7 @@ Disassembly of section .text: jmp cmpq $0x21, %r15 jne - movq 0x8(%r13), %rax + movq 0x8(%r14), %rax shlq $0x3, %rax addq %r12, %rax leaq -0x8(%rax), %rcx @@ -4327,6 +4155,11 @@ Disassembly of section .text: movslq %eax, %rax movq %rax, -0x48(%rbp) jmp + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + jmp cmpq $0x26, %r15 jne leaq , %rdi @@ -4344,7 +4177,6 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq - jmp leaq , %rdi movq %r15, %rsi movq %rbx, %rdx @@ -4360,16 +4192,166 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + leaq , %rax + movq (%rax), %rdx + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + leaq , %rdi + leaq , %rax + movq (%rax), %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movabsq $-0x1, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq jmp jmp jmp jmp jmp jmp - movq 0x40(%rsp), %r11 - movq %r11, 0x38(%rsp) + jmp + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp jmp jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/c4_selfhost_hello.aarch64.asm b/tests/snapshots/asm/c4_selfhost_hello.aarch64.asm index 8bbcc4fb9..419f7562d 100644 --- a/tests/snapshots/asm/c4_selfhost_hello.aarch64.asm +++ b/tests/snapshots/asm/c4_selfhost_hello.aarch64.asm @@ -10,17 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x7b // =123 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/c99_arith_common_width.aarch64.asm b/tests/snapshots/asm/c99_arith_common_width.aarch64.asm index 56baec623..93785d45d 100644 --- a/tests/snapshots/asm/c99_arith_common_width.aarch64.asm +++ b/tests/snapshots/asm/c99_arith_common_width.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,33 +48,37 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - add x0, x0, #0x1 - mov w0, w0 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + ldrsw x0, [x0] cmp x0, #0x0 b.ne - b + adrp x0, + add x0, x0, + bl + sxtw x0, w0 mov x0, #0x0 // =0 - sub x0, x0, #0x1 - mov w0, w0 - b + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0] + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret adrp x0, add x0, x0, mov x20, #0x1 // =1 @@ -92,21 +92,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x1 // =1 - sub x0, x0, x1 - mov w0, w0 b adrp x0, add x0, x0, @@ -121,21 +106,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w0 - mov x17, #0xfffe // =65534 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x1 // =1 - mul x0, x0, x1 - mov w0, w0 b adrp x0, add x0, x0, @@ -150,17 +120,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xc350 // =50000 - mul x0, x0, x0 - sxtw x0, w0 b adrp x0, add x0, x0, @@ -175,22 +134,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xf900 // =63744 - movk x17, #0x9502, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x1 // =1 - add x0, x0, x1 - mov w0, w0 b adrp x0, add x0, x0, @@ -205,17 +148,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x1 // =1 b adrp x0, add x0, x0, @@ -230,17 +162,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - cmp x0, x1 - cset x0, lt - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 b adrp x0, add x0, x0, @@ -255,18 +176,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - eor x0, x0, x1 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - adrp x0, - add x0, x0, - ldrsw x0, [x0] - cmp x0, #0x0 - b.ne b adrp x0, add x0, x0, @@ -281,21 +190,4 @@ Disassembly of section .text: bl sxtw x0, w0 b - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldrsw x0, [x0] - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret + b diff --git a/tests/snapshots/asm/c99_arith_common_width.x64.asm b/tests/snapshots/asm/c99_arith_common_width.x64.asm index 3280805ac..aab65f529 100644 --- a/tests/snapshots/asm/c99_arith_common_width.x64.asm +++ b/tests/snapshots/asm/c99_arith_common_width.x64.asm @@ -56,22 +56,27 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xd0, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - incq %rax - movl %eax, %eax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax + leaq , %rax + movslq (%rax), %rax testq %rax, %rax jne - jmp + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax xorq %rax, %rax - decq %rax - movl %eax, %eax - jmp + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + leaq , %rax + movslq (%rax), %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq leaq , %rax movl $0x1, %ebx movl %ebx, (%rax) @@ -85,18 +90,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax - movl $0x1, %ecx - subq %rcx, %rax - movl %eax, %eax jmp leaq , %rax movl $0x2, %ebx @@ -111,18 +104,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %eax, %eax - movl $0xfffffffe, %r11d # imm = 0xFFFFFFFE - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax - movl $0x1, %ecx - imulq %rcx, %rax - movl %eax, %eax jmp leaq , %rax movl $0x3, %ebx @@ -137,17 +118,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xc350, %eax # imm = 0xC350 - imulq %rax, %rax - movslq %eax, %rax jmp leaq , %rax movl $0x4, %ebx @@ -162,16 +132,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x6afd0700, %rax # imm = 0x9502F900 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax - movl $0x1, %ecx - addq %rcx, %rax - movl %eax, %eax jmp leaq , %rax movl $0x5, %ebx @@ -186,15 +146,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax - movl $0x1, %ecx jmp leaq , %rax movl $0x64, %ebx @@ -209,14 +160,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq %rcx, %rax - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF jmp leaq , %rax movl $0x65, %ebx @@ -231,18 +174,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - xorq %rcx, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq , %rax - movslq (%rax), %rax - testq %rax, %rax - jne jmp leaq , %rax movl $0x66, %ebx @@ -257,19 +188,5 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax - movq (%rsp), %rbx - addq $0xd0, %rsp - popq %rbp - retq - leaq , %rax - movslq (%rax), %rax - movq (%rsp), %rbx - addq $0xd0, %rsp - popq %rbp - retq + jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/c99_qualifiers.aarch64.asm b/tests/snapshots/asm/c99_qualifiers.aarch64.asm index 33b6aeb5b..563e16db5 100644 --- a/tests/snapshots/asm/c99_qualifiers.aarch64.asm +++ b/tests/snapshots/asm/c99_qualifiers.aarch64.asm @@ -17,20 +17,15 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x3, #0x0 // =0 mov x2, x3 - cmp x3, x1 - b.hs + b ldrsw x4, [x0] add x2, x2, x4 add x3, x3, #0x1 - b + cmp x3, x1 + b.lo sxtw x0, w2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: @@ -41,18 +36,6 @@ Disassembly of section .text: stur w0, [x29, #-0x28] sub x0, x29, #0x28 mov x1, #0x1 // =1 - mov x2, #0x2 // =2 - sxtw x1, w1 - mov w2, w2 - add x1, x1, x2 - mov w1, w1 - cmp x1, #0x3 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x1 // =1 bl cmp x0, #0x7 b.eq @@ -72,21 +55,6 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, mov x1, #0x1 // =1 @@ -105,3 +73,19 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/c99_qualifiers.x64.asm b/tests/snapshots/asm/c99_qualifiers.x64.asm index 55071dc20..9d369d2de 100644 --- a/tests/snapshots/asm/c99_qualifiers.x64.asm +++ b/tests/snapshots/asm/c99_qualifiers.x64.asm @@ -18,20 +18,15 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rcx, %rcx movq %rcx, %rax - cmpq %rsi, %rcx - jae + jmp movslq (%rdi), %rdx addq %rdx, %rax incq %rcx - jmp + cmpq %rsi, %rcx + jb movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -41,18 +36,6 @@ Disassembly of section .text: movl $0x7, %eax movl %eax, -0x28(%rbp) leaq -0x28(%rbp), %rdi - movl $0x1, %eax - movl $0x2, %ecx - movslq %eax, %rax - movl %ecx, %ecx - addq %rcx, %rax - movl %eax, %eax - cmpq $0x3, %rax - je - movl $0x1, %eax - addq $0x50, %rsp - popq %rbp - retq movl $0x1, %esi callq cmpq $0x7, %rax @@ -69,21 +52,6 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - jmp - movl $0x4, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x50, %rsp - popq %rbp - retq leaq , %rax movl $0x1, %ecx movl %ecx, (%rax) @@ -100,5 +68,20 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x50, %rsp + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/call_arg_extend_drop.aarch64.asm b/tests/snapshots/asm/call_arg_extend_drop.aarch64.asm new file mode 100644 index 000000000..3d9dacfb1 --- /dev/null +++ b/tests/snapshots/asm/call_arg_extend_drop.aarch64.asm @@ -0,0 +1,95 @@ + +call_arg_extend_drop.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + add x0, x0, x1 + sxtw x0, w0 + ret + +: + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x20, x0 + sxtw x20, w20 + cmp x20, #0x2 + b.ge + mov x0, x20 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + sub x0, x20, #0x1 + bl + mov x21, x0 + sub x0, x20, #0x2 + bl + add x0, x21, x0 + sxtw x0, w0 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + +: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + stur w0, [x29, #0x10] + add x0, x29, #0x10 + ldrsw x0, [x0] + mov x17, #0x3 // =3 + mul x0, x0, x17 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +: + sxtb x0, w0 + sxth x1, w1 + mov x17, #0x64 // =100 + mul x0, x0, x17 + add x0, x0, x1 + sxtw x0, w0 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x14 // =20 + bl + mov x17, #0x1a6d // =6765 + cmp x0, x17 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xfff9 // =65529 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffeb // =65515 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/call_arg_extend_drop.x64.asm b/tests/snapshots/asm/call_arg_extend_drop.x64.asm new file mode 100644 index 000000000..e97b256c3 --- /dev/null +++ b/tests/snapshots/asm/call_arg_extend_drop.x64.asm @@ -0,0 +1,99 @@ + +call_arg_extend_drop.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + leaq (%rdi,%rsi), %rax + movslq %eax, %rax + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %rdi, %rbx + movslq %ebx, %rbx + cmpq $0x2, %rbx + jge + movq %rbx, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + leaq -0x1(%rbx), %rdi + callq + movq %rax, %r12 + leaq -0x2(%rbx), %rdi + callq + addq %r12, %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + movl %edi, 0x10(%rbp) + leaq 0x10(%rbp), %rax + movslq (%rax), %rax + leaq (%rax,%rax,2), %rax + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +: + movsbq %dil, %rdi + movswq %si, %rsi + imulq $0x64, %rdi, %rax + addq %rsi, %rax + movslq %eax, %rax + retq + +
: + pushq %rbp + movq %rsp, %rbp + movl $0x14, %edi + callq + cmpq $0x1a6d, %rax # imm = 0x1A6D + je + movl $0x2, %eax + popq %rbp + retq + movabsq $-0x7, %rdi + callq + cmpq $-0x15, %rax + je + movl $0x3, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq + movl $0x1, %eax + popq %rbp + retq + movl $0x4, %eax + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/call_arg_int_to_double_conversion.aarch64.asm b/tests/snapshots/asm/call_arg_int_to_double_conversion.aarch64.asm index 87f823fea..d9aa2b6c2 100644 --- a/tests/snapshots/asm/call_arg_int_to_double_conversion.aarch64.asm +++ b/tests/snapshots/asm/call_arg_int_to_double_conversion.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x4000000000000000 // =4611686018427387904 mov x0, #0x1 // =1 scvtf d0, x0 @@ -26,10 +25,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x2 // =2 @@ -43,10 +41,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x3 // =3 @@ -60,10 +57,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x4 // =4 @@ -77,10 +73,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x2 // =2 mov x1, #0x4000000000000000 // =4611686018427387904 @@ -94,10 +89,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x3 // =3 mov x1, #0x4000000000000000 // =4611686018427387904 @@ -111,10 +105,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x2 // =2 @@ -128,18 +121,16 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/call_arg_int_to_double_conversion.x64.asm b/tests/snapshots/asm/call_arg_int_to_double_conversion.x64.asm index 3ba355d46..77dc922a1 100644 --- a/tests/snapshots/asm/call_arg_int_to_double_conversion.x64.asm +++ b/tests/snapshots/asm/call_arg_int_to_double_conversion.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movabsq $0x4000000000000000, %rbx # imm = 0x4000000000000000 movl $0x1, %eax @@ -33,7 +33,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 @@ -55,7 +55,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 @@ -77,7 +77,7 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 @@ -99,7 +99,7 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x2, %eax @@ -121,7 +121,7 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x3, %eax @@ -143,7 +143,7 @@ Disassembly of section .text: je movl $0x6, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 @@ -165,7 +165,7 @@ Disassembly of section .text: je movl $0x7, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -174,6 +174,6 @@ Disassembly of section .text: movslq %eax, %rax xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/call_indirect_target_scratch_collision.aarch64.asm b/tests/snapshots/asm/call_indirect_target_scratch_collision.aarch64.asm index f80c2f024..f1ce3d36c 100644 --- a/tests/snapshots/asm/call_indirect_target_scratch_collision.aarch64.asm +++ b/tests/snapshots/asm/call_indirect_target_scratch_collision.aarch64.asm @@ -17,39 +17,25 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x3, w3 ldr x5, [x0] mov x17, #0xffff // =65535 and x3, x3, x17 - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x5 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] - ldr x4, [sp, #0x40] blr x9 - add sp, sp, #0x50 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] + str x20, [sp, #-0x80]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -81,12 +67,11 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret + mov x1, #0x1 // =1 + b b diff --git a/tests/snapshots/asm/call_indirect_target_scratch_collision.x64.asm b/tests/snapshots/asm/call_indirect_target_scratch_collision.x64.asm index 8dff7c786..cdbd7f3d9 100644 --- a/tests/snapshots/asm/call_indirect_target_scratch_collision.x64.asm +++ b/tests/snapshots/asm/call_indirect_target_scratch_collision.x64.asm @@ -63,11 +63,11 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq %rcx, %rax addq $0x60, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp diff --git a/tests/snapshots/asm/call_sp_adjust_imm12_overflow.aarch64.asm b/tests/snapshots/asm/call_sp_adjust_imm12_overflow.aarch64.asm index d01f17e8b..79034aa3e 100644 --- a/tests/snapshots/asm/call_sp_adjust_imm12_overflow.aarch64.asm +++ b/tests/snapshots/asm/call_sp_adjust_imm12_overflow.aarch64.asm @@ -1577,13 +1577,12 @@ Disassembly of section .text: str x17, [x16] ldr x17, [x29, #0x2068] str x17, [x16, #0x8] - mov x0, #0x0 // =0 + sub x0, x29, #0x10 + ldr x0, [x0] sub x1, x29, #0x10 - ldr x1, [x1] - sub x2, x29, #0x10 - ldr x2, [x2, #0x8] - add x1, x1, x2 + ldr x1, [x1, #0x8] add x0, x0, x1 + add x0, x0, #0x0 sub x1, x29, #0x20 ldr x1, [x1] sub x2, x29, #0x20 @@ -3670,9 +3669,7 @@ Disassembly of section .text: sub sp, sp, #0x80 stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 - mov x8, #0x0 // =0 - add x0, x8, x0 + add x0, x0, #0x0 add x0, x0, x1 add x0, x0, x2 add x0, x0, x3 @@ -4433,7 +4430,6 @@ Disassembly of section .text: add x16, x16, #0x40 ldr x1, [x16] add x0, x0, x1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x1, lsl #12 // =0x1000 add sp, sp, #0x40 @@ -4442,27 +4438,18 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x1, lsl #12 // =0x1000 - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] - str x26, [sp, #0x30] - str x27, [sp, #0x38] + sub sp, sp, #0x7d0 + stp x20, x21, [sp] + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] str x28, [sp, #0x40] str x19, [sp, #0x50] adrp x20, - add x20, x20, #0x370 + add x20, x20, #0x36c adrp x21, add x21, x21, mov x1, #0x0 // =0 - cmp x1, #0x105 - b.ge - b - add x1, x1, #0x1 b adrp x0, add x0, x0, @@ -4473,7 +4460,9 @@ Disassembly of section .text: add x0, x0, x2 lsl x2, x1, #1 str x2, [x0, #0x8] - b + add x1, x1, #0x1 + cmp x1, #0x105 + b.lt adrp x0, add x0, x0, add x1, x0, #0x10 @@ -6285,18 +6274,13 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x28, [sp, #0x40] ldr x19, [sp, #0x50] - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x10 + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x7d0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 @@ -6796,1037 +6780,512 @@ Disassembly of section .text: str x16, [sp, #0x70] mov x16, #0x104 // =260 str x16, [sp, #0x68] - ldr x16, [sp, #0x68] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x80] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x98] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x110] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x128] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x140] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x158] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x170] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x188] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1a0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1b8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1d0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1e8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x200] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x218] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x230] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x248] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x260] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x278] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x290] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x2a8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x2c0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x2d8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x2f0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x308] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x320] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x338] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x350] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x368] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x380] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x398] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x3b0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x3c8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x3e0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x3f8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x410] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x428] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x440] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x458] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x470] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x488] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x4a0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x4b8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x4d0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x4e8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x500] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x518] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x530] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x548] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x560] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x578] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x590] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x5a8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x5c0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x5d8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x5f0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x608] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x620] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x638] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x650] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x668] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x680] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x698] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x6b0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x6c8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x6e0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x6f8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x710] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x728] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x740] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x758] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x770] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x788] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x7a0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x7b8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x7d0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x7e8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x800] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x818] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x830] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x848] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x860] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x878] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x890] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x8a8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x8c0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x8d8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x8f0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x908] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x920] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x938] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x950] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x968] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x980] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x998] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x9b0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x9c8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x9e0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x9f8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa10] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa28] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa40] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa58] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa70] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xa88] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xaa0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xab8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xad0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xae8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb00] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb18] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb30] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb48] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb60] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb78] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xb90] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xba8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xbc0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xbd8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xbf0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc08] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc20] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc38] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc50] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc68] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc80] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xc98] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xcb0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xcc8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xce0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xcf8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd10] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd28] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd40] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd58] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd70] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xd88] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xda0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xdb8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xdd0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xde8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe00] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe18] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe30] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe48] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe60] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe78] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xe90] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xea8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xec0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xed8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xef0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf08] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf20] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf38] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf50] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf68] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf80] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xf98] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xfb0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xfc8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xfe0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0xff8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1010] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1028] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1040] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1058] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1070] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1088] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x10a0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x10b8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x10d0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x10e8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1100] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1118] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1130] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1148] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1160] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1178] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1190] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x11a8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x11c0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x11d8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x11f0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1208] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1220] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1238] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1250] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1268] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1280] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1298] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x12b0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x12c8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x12e0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x12f8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1310] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1328] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1340] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1358] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1370] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1388] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x13a0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x13b8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x13d0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x13e8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1400] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1418] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1430] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1448] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1460] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1478] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1490] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x14a8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x14c0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x14d8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x14f0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1508] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1520] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1538] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1550] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1568] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1580] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1598] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x15b0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x15c8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x15e0] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x15f8] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1610] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1628] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1640] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1658] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1670] - str x16, [sp, #-0x10]! - ldr x16, [sp, #0x1688] - str x16, [sp, #-0x10]! - str x28, [sp, #-0x10]! - str x27, [sp, #-0x10]! - str x26, [sp, #-0x10]! - str x25, [sp, #-0x10]! - str x24, [sp, #-0x10]! - str x23, [sp, #-0x10]! - str x22, [sp, #-0x10]! - str x15, [sp, #-0x10]! - str x14, [sp, #-0x10]! - str x13, [sp, #-0x10]! - str x12, [sp, #-0x10]! - str x11, [sp, #-0x10]! - str x10, [sp, #-0x10]! - str x9, [sp, #-0x10]! - str x8, [sp, #-0x10]! - str x7, [sp, #-0x10]! - str x6, [sp, #-0x10]! - str x5, [sp, #-0x10]! - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! - mov x9, x20 - sub sp, sp, #0x7e0 - ldr x0, [sp, #0x7e0] - ldr x1, [sp, #0x7f0] - ldr x2, [sp, #0x800] - ldr x3, [sp, #0x810] - ldr x4, [sp, #0x820] - ldr x5, [sp, #0x830] - ldr x6, [sp, #0x840] - ldr x7, [sp, #0x850] - ldr x16, [sp, #0x860] - str x16, [sp] - ldr x16, [sp, #0x870] - str x16, [sp, #0x8] - ldr x16, [sp, #0x880] - str x16, [sp, #0x10] - ldr x16, [sp, #0x890] - str x16, [sp, #0x18] - ldr x16, [sp, #0x8a0] - str x16, [sp, #0x20] - ldr x16, [sp, #0x8b0] - str x16, [sp, #0x28] - ldr x16, [sp, #0x8c0] - str x16, [sp, #0x30] - ldr x16, [sp, #0x8d0] - str x16, [sp, #0x38] - ldr x16, [sp, #0x8e0] - str x16, [sp, #0x40] - ldr x16, [sp, #0x8f0] - str x16, [sp, #0x48] - ldr x16, [sp, #0x900] - str x16, [sp, #0x50] - ldr x16, [sp, #0x910] - str x16, [sp, #0x58] - ldr x16, [sp, #0x920] - str x16, [sp, #0x60] - ldr x16, [sp, #0x930] - str x16, [sp, #0x68] - ldr x16, [sp, #0x940] - str x16, [sp, #0x70] - ldr x16, [sp, #0x950] + mov x16, x20 + sub sp, sp, #0x7f0 + str x16, [sp, #0x7e0] + str x8, [sp] + str x9, [sp, #0x8] + str x10, [sp, #0x10] + str x11, [sp, #0x18] + str x12, [sp, #0x20] + str x13, [sp, #0x28] + str x14, [sp, #0x30] + str x15, [sp, #0x38] + str x22, [sp, #0x40] + str x23, [sp, #0x48] + str x24, [sp, #0x50] + str x25, [sp, #0x58] + str x26, [sp, #0x60] + str x27, [sp, #0x68] + str x28, [sp, #0x70] + ldr x16, [sp, #0xfb8] str x16, [sp, #0x78] - ldr x16, [sp, #0x960] + ldr x16, [sp, #0xfb0] str x16, [sp, #0x80] - ldr x16, [sp, #0x970] + ldr x16, [sp, #0xfa8] str x16, [sp, #0x88] - ldr x16, [sp, #0x980] + ldr x16, [sp, #0xfa0] str x16, [sp, #0x90] - ldr x16, [sp, #0x990] + ldr x16, [sp, #0xf98] str x16, [sp, #0x98] - ldr x16, [sp, #0x9a0] + ldr x16, [sp, #0xf90] str x16, [sp, #0xa0] - ldr x16, [sp, #0x9b0] + ldr x16, [sp, #0xf88] str x16, [sp, #0xa8] - ldr x16, [sp, #0x9c0] + ldr x16, [sp, #0xf80] str x16, [sp, #0xb0] - ldr x16, [sp, #0x9d0] + ldr x16, [sp, #0xf78] str x16, [sp, #0xb8] - ldr x16, [sp, #0x9e0] + ldr x16, [sp, #0xf70] str x16, [sp, #0xc0] - ldr x16, [sp, #0x9f0] + ldr x16, [sp, #0xf68] str x16, [sp, #0xc8] - ldr x16, [sp, #0xa00] + ldr x16, [sp, #0xf60] str x16, [sp, #0xd0] - ldr x16, [sp, #0xa10] + ldr x16, [sp, #0xf58] str x16, [sp, #0xd8] - ldr x16, [sp, #0xa20] + ldr x16, [sp, #0xf50] str x16, [sp, #0xe0] - ldr x16, [sp, #0xa30] + ldr x16, [sp, #0xf48] str x16, [sp, #0xe8] - ldr x16, [sp, #0xa40] + ldr x16, [sp, #0xf40] str x16, [sp, #0xf0] - ldr x16, [sp, #0xa50] + ldr x16, [sp, #0xf38] str x16, [sp, #0xf8] - ldr x16, [sp, #0xa60] + ldr x16, [sp, #0xf30] str x16, [sp, #0x100] - ldr x16, [sp, #0xa70] + ldr x16, [sp, #0xf28] str x16, [sp, #0x108] - ldr x16, [sp, #0xa80] + ldr x16, [sp, #0xf20] str x16, [sp, #0x110] - ldr x16, [sp, #0xa90] + ldr x16, [sp, #0xf18] str x16, [sp, #0x118] - ldr x16, [sp, #0xaa0] + ldr x16, [sp, #0xf10] str x16, [sp, #0x120] - ldr x16, [sp, #0xab0] + ldr x16, [sp, #0xf08] str x16, [sp, #0x128] - ldr x16, [sp, #0xac0] + ldr x16, [sp, #0xf00] str x16, [sp, #0x130] - ldr x16, [sp, #0xad0] + ldr x16, [sp, #0xef8] str x16, [sp, #0x138] - ldr x16, [sp, #0xae0] + ldr x16, [sp, #0xef0] str x16, [sp, #0x140] - ldr x16, [sp, #0xaf0] + ldr x16, [sp, #0xee8] str x16, [sp, #0x148] - ldr x16, [sp, #0xb00] + ldr x16, [sp, #0xee0] str x16, [sp, #0x150] - ldr x16, [sp, #0xb10] + ldr x16, [sp, #0xed8] str x16, [sp, #0x158] - ldr x16, [sp, #0xb20] + ldr x16, [sp, #0xed0] str x16, [sp, #0x160] - ldr x16, [sp, #0xb30] + ldr x16, [sp, #0xec8] str x16, [sp, #0x168] - ldr x16, [sp, #0xb40] + ldr x16, [sp, #0xec0] str x16, [sp, #0x170] - ldr x16, [sp, #0xb50] + ldr x16, [sp, #0xeb8] str x16, [sp, #0x178] - ldr x16, [sp, #0xb60] + ldr x16, [sp, #0xeb0] str x16, [sp, #0x180] - ldr x16, [sp, #0xb70] + ldr x16, [sp, #0xea8] str x16, [sp, #0x188] - ldr x16, [sp, #0xb80] + ldr x16, [sp, #0xea0] str x16, [sp, #0x190] - ldr x16, [sp, #0xb90] + ldr x16, [sp, #0xe98] str x16, [sp, #0x198] - ldr x16, [sp, #0xba0] + ldr x16, [sp, #0xe90] str x16, [sp, #0x1a0] - ldr x16, [sp, #0xbb0] + ldr x16, [sp, #0xe88] str x16, [sp, #0x1a8] - ldr x16, [sp, #0xbc0] + ldr x16, [sp, #0xe80] str x16, [sp, #0x1b0] - ldr x16, [sp, #0xbd0] + ldr x16, [sp, #0xe78] str x16, [sp, #0x1b8] - ldr x16, [sp, #0xbe0] + ldr x16, [sp, #0xe70] str x16, [sp, #0x1c0] - ldr x16, [sp, #0xbf0] + ldr x16, [sp, #0xe68] str x16, [sp, #0x1c8] - ldr x16, [sp, #0xc00] + ldr x16, [sp, #0xe60] str x16, [sp, #0x1d0] - ldr x16, [sp, #0xc10] + ldr x16, [sp, #0xe58] str x16, [sp, #0x1d8] - ldr x16, [sp, #0xc20] + ldr x16, [sp, #0xe50] str x16, [sp, #0x1e0] - ldr x16, [sp, #0xc30] + ldr x16, [sp, #0xe48] str x16, [sp, #0x1e8] - ldr x16, [sp, #0xc40] + ldr x16, [sp, #0xe40] str x16, [sp, #0x1f0] - ldr x16, [sp, #0xc50] + ldr x16, [sp, #0xe38] str x16, [sp, #0x1f8] - ldr x16, [sp, #0xc60] + ldr x16, [sp, #0xe30] str x16, [sp, #0x200] - ldr x16, [sp, #0xc70] + ldr x16, [sp, #0xe28] str x16, [sp, #0x208] - ldr x16, [sp, #0xc80] + ldr x16, [sp, #0xe20] str x16, [sp, #0x210] - ldr x16, [sp, #0xc90] + ldr x16, [sp, #0xe18] str x16, [sp, #0x218] - ldr x16, [sp, #0xca0] + ldr x16, [sp, #0xe10] str x16, [sp, #0x220] - ldr x16, [sp, #0xcb0] + ldr x16, [sp, #0xe08] str x16, [sp, #0x228] - ldr x16, [sp, #0xcc0] + ldr x16, [sp, #0xe00] str x16, [sp, #0x230] - ldr x16, [sp, #0xcd0] + ldr x16, [sp, #0xdf8] str x16, [sp, #0x238] - ldr x16, [sp, #0xce0] + ldr x16, [sp, #0xdf0] str x16, [sp, #0x240] - ldr x16, [sp, #0xcf0] + ldr x16, [sp, #0xde8] str x16, [sp, #0x248] - ldr x16, [sp, #0xd00] + ldr x16, [sp, #0xde0] str x16, [sp, #0x250] - ldr x16, [sp, #0xd10] + ldr x16, [sp, #0xdd8] str x16, [sp, #0x258] - ldr x16, [sp, #0xd20] + ldr x16, [sp, #0xdd0] str x16, [sp, #0x260] - ldr x16, [sp, #0xd30] + ldr x16, [sp, #0xdc8] str x16, [sp, #0x268] - ldr x16, [sp, #0xd40] + ldr x16, [sp, #0xdc0] str x16, [sp, #0x270] - ldr x16, [sp, #0xd50] + ldr x16, [sp, #0xdb8] str x16, [sp, #0x278] - ldr x16, [sp, #0xd60] + ldr x16, [sp, #0xdb0] str x16, [sp, #0x280] - ldr x16, [sp, #0xd70] + ldr x16, [sp, #0xda8] str x16, [sp, #0x288] - ldr x16, [sp, #0xd80] + ldr x16, [sp, #0xda0] str x16, [sp, #0x290] - ldr x16, [sp, #0xd90] + ldr x16, [sp, #0xd98] str x16, [sp, #0x298] - ldr x16, [sp, #0xda0] + ldr x16, [sp, #0xd90] str x16, [sp, #0x2a0] - ldr x16, [sp, #0xdb0] + ldr x16, [sp, #0xd88] str x16, [sp, #0x2a8] - ldr x16, [sp, #0xdc0] + ldr x16, [sp, #0xd80] str x16, [sp, #0x2b0] - ldr x16, [sp, #0xdd0] + ldr x16, [sp, #0xd78] str x16, [sp, #0x2b8] - ldr x16, [sp, #0xde0] + ldr x16, [sp, #0xd70] str x16, [sp, #0x2c0] - ldr x16, [sp, #0xdf0] + ldr x16, [sp, #0xd68] str x16, [sp, #0x2c8] - ldr x16, [sp, #0xe00] + ldr x16, [sp, #0xd60] str x16, [sp, #0x2d0] - ldr x16, [sp, #0xe10] + ldr x16, [sp, #0xd58] str x16, [sp, #0x2d8] - ldr x16, [sp, #0xe20] + ldr x16, [sp, #0xd50] str x16, [sp, #0x2e0] - ldr x16, [sp, #0xe30] + ldr x16, [sp, #0xd48] str x16, [sp, #0x2e8] - ldr x16, [sp, #0xe40] + ldr x16, [sp, #0xd40] str x16, [sp, #0x2f0] - ldr x16, [sp, #0xe50] + ldr x16, [sp, #0xd38] str x16, [sp, #0x2f8] - ldr x16, [sp, #0xe60] + ldr x16, [sp, #0xd30] str x16, [sp, #0x300] - ldr x16, [sp, #0xe70] + ldr x16, [sp, #0xd28] str x16, [sp, #0x308] - ldr x16, [sp, #0xe80] + ldr x16, [sp, #0xd20] str x16, [sp, #0x310] - ldr x16, [sp, #0xe90] + ldr x16, [sp, #0xd18] str x16, [sp, #0x318] - ldr x16, [sp, #0xea0] + ldr x16, [sp, #0xd10] str x16, [sp, #0x320] - ldr x16, [sp, #0xeb0] + ldr x16, [sp, #0xd08] str x16, [sp, #0x328] - ldr x16, [sp, #0xec0] + ldr x16, [sp, #0xd00] str x16, [sp, #0x330] - ldr x16, [sp, #0xed0] + ldr x16, [sp, #0xcf8] str x16, [sp, #0x338] - ldr x16, [sp, #0xee0] + ldr x16, [sp, #0xcf0] str x16, [sp, #0x340] - ldr x16, [sp, #0xef0] + ldr x16, [sp, #0xce8] str x16, [sp, #0x348] - ldr x16, [sp, #0xf00] + ldr x16, [sp, #0xce0] str x16, [sp, #0x350] - ldr x16, [sp, #0xf10] + ldr x16, [sp, #0xcd8] str x16, [sp, #0x358] - ldr x16, [sp, #0xf20] + ldr x16, [sp, #0xcd0] str x16, [sp, #0x360] - ldr x16, [sp, #0xf30] + ldr x16, [sp, #0xcc8] str x16, [sp, #0x368] - ldr x16, [sp, #0xf40] + ldr x16, [sp, #0xcc0] str x16, [sp, #0x370] - ldr x16, [sp, #0xf50] + ldr x16, [sp, #0xcb8] str x16, [sp, #0x378] - ldr x16, [sp, #0xf60] + ldr x16, [sp, #0xcb0] str x16, [sp, #0x380] - ldr x16, [sp, #0xf70] + ldr x16, [sp, #0xca8] str x16, [sp, #0x388] - ldr x16, [sp, #0xf80] + ldr x16, [sp, #0xca0] str x16, [sp, #0x390] - ldr x16, [sp, #0xf90] + ldr x16, [sp, #0xc98] str x16, [sp, #0x398] - ldr x16, [sp, #0xfa0] + ldr x16, [sp, #0xc90] str x16, [sp, #0x3a0] - ldr x16, [sp, #0xfb0] + ldr x16, [sp, #0xc88] str x16, [sp, #0x3a8] - ldr x16, [sp, #0xfc0] + ldr x16, [sp, #0xc80] str x16, [sp, #0x3b0] - ldr x16, [sp, #0xfd0] + ldr x16, [sp, #0xc78] str x16, [sp, #0x3b8] - ldr x16, [sp, #0xfe0] + ldr x16, [sp, #0xc70] str x16, [sp, #0x3c0] - ldr x16, [sp, #0xff0] + ldr x16, [sp, #0xc68] str x16, [sp, #0x3c8] - ldr x16, [sp, #0x1000] + ldr x16, [sp, #0xc60] str x16, [sp, #0x3d0] - ldr x16, [sp, #0x1010] + ldr x16, [sp, #0xc58] str x16, [sp, #0x3d8] - ldr x16, [sp, #0x1020] + ldr x16, [sp, #0xc50] str x16, [sp, #0x3e0] - ldr x16, [sp, #0x1030] + ldr x16, [sp, #0xc48] str x16, [sp, #0x3e8] - ldr x16, [sp, #0x1040] + ldr x16, [sp, #0xc40] str x16, [sp, #0x3f0] - ldr x16, [sp, #0x1050] + ldr x16, [sp, #0xc38] str x16, [sp, #0x3f8] - ldr x16, [sp, #0x1060] + ldr x16, [sp, #0xc30] str x16, [sp, #0x400] - ldr x16, [sp, #0x1070] + ldr x16, [sp, #0xc28] str x16, [sp, #0x408] - ldr x16, [sp, #0x1080] + ldr x16, [sp, #0xc20] str x16, [sp, #0x410] - ldr x16, [sp, #0x1090] + ldr x16, [sp, #0xc18] str x16, [sp, #0x418] - ldr x16, [sp, #0x10a0] + ldr x16, [sp, #0xc10] str x16, [sp, #0x420] - ldr x16, [sp, #0x10b0] + ldr x16, [sp, #0xc08] str x16, [sp, #0x428] - ldr x16, [sp, #0x10c0] + ldr x16, [sp, #0xc00] str x16, [sp, #0x430] - ldr x16, [sp, #0x10d0] + ldr x16, [sp, #0xbf8] str x16, [sp, #0x438] - ldr x16, [sp, #0x10e0] + ldr x16, [sp, #0xbf0] str x16, [sp, #0x440] - ldr x16, [sp, #0x10f0] + ldr x16, [sp, #0xbe8] str x16, [sp, #0x448] - ldr x16, [sp, #0x1100] + ldr x16, [sp, #0xbe0] str x16, [sp, #0x450] - ldr x16, [sp, #0x1110] + ldr x16, [sp, #0xbd8] str x16, [sp, #0x458] - ldr x16, [sp, #0x1120] + ldr x16, [sp, #0xbd0] str x16, [sp, #0x460] - ldr x16, [sp, #0x1130] + ldr x16, [sp, #0xbc8] str x16, [sp, #0x468] - ldr x16, [sp, #0x1140] + ldr x16, [sp, #0xbc0] str x16, [sp, #0x470] - ldr x16, [sp, #0x1150] + ldr x16, [sp, #0xbb8] str x16, [sp, #0x478] - ldr x16, [sp, #0x1160] + ldr x16, [sp, #0xbb0] str x16, [sp, #0x480] - ldr x16, [sp, #0x1170] + ldr x16, [sp, #0xba8] str x16, [sp, #0x488] - ldr x16, [sp, #0x1180] + ldr x16, [sp, #0xba0] str x16, [sp, #0x490] - ldr x16, [sp, #0x1190] + ldr x16, [sp, #0xb98] str x16, [sp, #0x498] - ldr x16, [sp, #0x11a0] + ldr x16, [sp, #0xb90] str x16, [sp, #0x4a0] - ldr x16, [sp, #0x11b0] + ldr x16, [sp, #0xb88] str x16, [sp, #0x4a8] - ldr x16, [sp, #0x11c0] + ldr x16, [sp, #0xb80] str x16, [sp, #0x4b0] - ldr x16, [sp, #0x11d0] + ldr x16, [sp, #0xb78] str x16, [sp, #0x4b8] - ldr x16, [sp, #0x11e0] + ldr x16, [sp, #0xb70] str x16, [sp, #0x4c0] - ldr x16, [sp, #0x11f0] + ldr x16, [sp, #0xb68] str x16, [sp, #0x4c8] - ldr x16, [sp, #0x1200] + ldr x16, [sp, #0xb60] str x16, [sp, #0x4d0] - ldr x16, [sp, #0x1210] + ldr x16, [sp, #0xb58] str x16, [sp, #0x4d8] - ldr x16, [sp, #0x1220] + ldr x16, [sp, #0xb50] str x16, [sp, #0x4e0] - ldr x16, [sp, #0x1230] + ldr x16, [sp, #0xb48] str x16, [sp, #0x4e8] - ldr x16, [sp, #0x1240] + ldr x16, [sp, #0xb40] str x16, [sp, #0x4f0] - ldr x16, [sp, #0x1250] + ldr x16, [sp, #0xb38] str x16, [sp, #0x4f8] - ldr x16, [sp, #0x1260] + ldr x16, [sp, #0xb30] str x16, [sp, #0x500] - ldr x16, [sp, #0x1270] + ldr x16, [sp, #0xb28] str x16, [sp, #0x508] - ldr x16, [sp, #0x1280] + ldr x16, [sp, #0xb20] str x16, [sp, #0x510] - ldr x16, [sp, #0x1290] + ldr x16, [sp, #0xb18] str x16, [sp, #0x518] - ldr x16, [sp, #0x12a0] + ldr x16, [sp, #0xb10] str x16, [sp, #0x520] - ldr x16, [sp, #0x12b0] + ldr x16, [sp, #0xb08] str x16, [sp, #0x528] - ldr x16, [sp, #0x12c0] + ldr x16, [sp, #0xb00] str x16, [sp, #0x530] - ldr x16, [sp, #0x12d0] + ldr x16, [sp, #0xaf8] str x16, [sp, #0x538] - ldr x16, [sp, #0x12e0] + ldr x16, [sp, #0xaf0] str x16, [sp, #0x540] - ldr x16, [sp, #0x12f0] + ldr x16, [sp, #0xae8] str x16, [sp, #0x548] - ldr x16, [sp, #0x1300] + ldr x16, [sp, #0xae0] str x16, [sp, #0x550] - ldr x16, [sp, #0x1310] + ldr x16, [sp, #0xad8] str x16, [sp, #0x558] - ldr x16, [sp, #0x1320] + ldr x16, [sp, #0xad0] str x16, [sp, #0x560] - ldr x16, [sp, #0x1330] + ldr x16, [sp, #0xac8] str x16, [sp, #0x568] - ldr x16, [sp, #0x1340] + ldr x16, [sp, #0xac0] str x16, [sp, #0x570] - ldr x16, [sp, #0x1350] + ldr x16, [sp, #0xab8] str x16, [sp, #0x578] - ldr x16, [sp, #0x1360] + ldr x16, [sp, #0xab0] str x16, [sp, #0x580] - ldr x16, [sp, #0x1370] + ldr x16, [sp, #0xaa8] str x16, [sp, #0x588] - ldr x16, [sp, #0x1380] + ldr x16, [sp, #0xaa0] str x16, [sp, #0x590] - ldr x16, [sp, #0x1390] + ldr x16, [sp, #0xa98] str x16, [sp, #0x598] - ldr x16, [sp, #0x13a0] + ldr x16, [sp, #0xa90] str x16, [sp, #0x5a0] - ldr x16, [sp, #0x13b0] + ldr x16, [sp, #0xa88] str x16, [sp, #0x5a8] - ldr x16, [sp, #0x13c0] + ldr x16, [sp, #0xa80] str x16, [sp, #0x5b0] - ldr x16, [sp, #0x13d0] + ldr x16, [sp, #0xa78] str x16, [sp, #0x5b8] - ldr x16, [sp, #0x13e0] + ldr x16, [sp, #0xa70] str x16, [sp, #0x5c0] - ldr x16, [sp, #0x13f0] + ldr x16, [sp, #0xa68] str x16, [sp, #0x5c8] - ldr x16, [sp, #0x1400] + ldr x16, [sp, #0xa60] str x16, [sp, #0x5d0] - ldr x16, [sp, #0x1410] + ldr x16, [sp, #0xa58] str x16, [sp, #0x5d8] - ldr x16, [sp, #0x1420] + ldr x16, [sp, #0xa50] str x16, [sp, #0x5e0] - ldr x16, [sp, #0x1430] + ldr x16, [sp, #0xa48] str x16, [sp, #0x5e8] - ldr x16, [sp, #0x1440] + ldr x16, [sp, #0xa40] str x16, [sp, #0x5f0] - ldr x16, [sp, #0x1450] + ldr x16, [sp, #0xa38] str x16, [sp, #0x5f8] - ldr x16, [sp, #0x1460] + ldr x16, [sp, #0xa30] str x16, [sp, #0x600] - ldr x16, [sp, #0x1470] + ldr x16, [sp, #0xa28] str x16, [sp, #0x608] - ldr x16, [sp, #0x1480] + ldr x16, [sp, #0xa20] str x16, [sp, #0x610] - ldr x16, [sp, #0x1490] + ldr x16, [sp, #0xa18] str x16, [sp, #0x618] - ldr x16, [sp, #0x14a0] + ldr x16, [sp, #0xa10] str x16, [sp, #0x620] - ldr x16, [sp, #0x14b0] + ldr x16, [sp, #0xa08] str x16, [sp, #0x628] - ldr x16, [sp, #0x14c0] + ldr x16, [sp, #0xa00] str x16, [sp, #0x630] - ldr x16, [sp, #0x14d0] + ldr x16, [sp, #0x9f8] str x16, [sp, #0x638] - ldr x16, [sp, #0x14e0] + ldr x16, [sp, #0x9f0] str x16, [sp, #0x640] - ldr x16, [sp, #0x14f0] + ldr x16, [sp, #0x9e8] str x16, [sp, #0x648] - ldr x16, [sp, #0x1500] + ldr x16, [sp, #0x9e0] str x16, [sp, #0x650] - ldr x16, [sp, #0x1510] + ldr x16, [sp, #0x9d8] str x16, [sp, #0x658] - ldr x16, [sp, #0x1520] + ldr x16, [sp, #0x9d0] str x16, [sp, #0x660] - ldr x16, [sp, #0x1530] + ldr x16, [sp, #0x9c8] str x16, [sp, #0x668] - ldr x16, [sp, #0x1540] + ldr x16, [sp, #0x9c0] str x16, [sp, #0x670] - ldr x16, [sp, #0x1550] + ldr x16, [sp, #0x9b8] str x16, [sp, #0x678] - ldr x16, [sp, #0x1560] + ldr x16, [sp, #0x9b0] str x16, [sp, #0x680] - ldr x16, [sp, #0x1570] + ldr x16, [sp, #0x9a8] str x16, [sp, #0x688] - ldr x16, [sp, #0x1580] + ldr x16, [sp, #0x9a0] str x16, [sp, #0x690] - ldr x16, [sp, #0x1590] + ldr x16, [sp, #0x998] str x16, [sp, #0x698] - ldr x16, [sp, #0x15a0] + ldr x16, [sp, #0x990] str x16, [sp, #0x6a0] - ldr x16, [sp, #0x15b0] + ldr x16, [sp, #0x988] str x16, [sp, #0x6a8] - ldr x16, [sp, #0x15c0] + ldr x16, [sp, #0x980] str x16, [sp, #0x6b0] - ldr x16, [sp, #0x15d0] + ldr x16, [sp, #0x978] str x16, [sp, #0x6b8] - ldr x16, [sp, #0x15e0] + ldr x16, [sp, #0x970] str x16, [sp, #0x6c0] - ldr x16, [sp, #0x15f0] + ldr x16, [sp, #0x968] str x16, [sp, #0x6c8] - ldr x16, [sp, #0x1600] + ldr x16, [sp, #0x960] str x16, [sp, #0x6d0] - ldr x16, [sp, #0x1610] + ldr x16, [sp, #0x958] str x16, [sp, #0x6d8] - ldr x16, [sp, #0x1620] + ldr x16, [sp, #0x950] str x16, [sp, #0x6e0] - ldr x16, [sp, #0x1630] + ldr x16, [sp, #0x948] str x16, [sp, #0x6e8] - ldr x16, [sp, #0x1640] + ldr x16, [sp, #0x940] str x16, [sp, #0x6f0] - ldr x16, [sp, #0x1650] + ldr x16, [sp, #0x938] str x16, [sp, #0x6f8] - ldr x16, [sp, #0x1660] + ldr x16, [sp, #0x930] str x16, [sp, #0x700] - ldr x16, [sp, #0x1670] + ldr x16, [sp, #0x928] str x16, [sp, #0x708] - ldr x16, [sp, #0x1680] + ldr x16, [sp, #0x920] str x16, [sp, #0x710] - ldr x16, [sp, #0x1690] + ldr x16, [sp, #0x918] str x16, [sp, #0x718] - ldr x16, [sp, #0x16a0] + ldr x16, [sp, #0x910] str x16, [sp, #0x720] - ldr x16, [sp, #0x16b0] + ldr x16, [sp, #0x908] str x16, [sp, #0x728] - ldr x16, [sp, #0x16c0] + ldr x16, [sp, #0x900] str x16, [sp, #0x730] - ldr x16, [sp, #0x16d0] + ldr x16, [sp, #0x8f8] str x16, [sp, #0x738] - ldr x16, [sp, #0x16e0] + ldr x16, [sp, #0x8f0] str x16, [sp, #0x740] - ldr x16, [sp, #0x16f0] + ldr x16, [sp, #0x8e8] str x16, [sp, #0x748] - ldr x16, [sp, #0x1700] + ldr x16, [sp, #0x8e0] str x16, [sp, #0x750] - ldr x16, [sp, #0x1710] + ldr x16, [sp, #0x8d8] str x16, [sp, #0x758] - ldr x16, [sp, #0x1720] + ldr x16, [sp, #0x8d0] str x16, [sp, #0x760] - ldr x16, [sp, #0x1730] + ldr x16, [sp, #0x8c8] str x16, [sp, #0x768] - ldr x16, [sp, #0x1740] + ldr x16, [sp, #0x8c0] str x16, [sp, #0x770] - ldr x16, [sp, #0x1750] + ldr x16, [sp, #0x8b8] str x16, [sp, #0x778] - ldr x16, [sp, #0x1760] + ldr x16, [sp, #0x8b0] str x16, [sp, #0x780] - ldr x16, [sp, #0x1770] + ldr x16, [sp, #0x8a8] str x16, [sp, #0x788] - ldr x16, [sp, #0x1780] + ldr x16, [sp, #0x8a0] str x16, [sp, #0x790] - ldr x16, [sp, #0x1790] + ldr x16, [sp, #0x898] str x16, [sp, #0x798] - ldr x16, [sp, #0x17a0] + ldr x16, [sp, #0x890] str x16, [sp, #0x7a0] - ldr x16, [sp, #0x17b0] + ldr x16, [sp, #0x888] str x16, [sp, #0x7a8] - ldr x16, [sp, #0x17c0] + ldr x16, [sp, #0x880] str x16, [sp, #0x7b0] - ldr x16, [sp, #0x17d0] + ldr x16, [sp, #0x878] str x16, [sp, #0x7b8] - ldr x16, [sp, #0x17e0] + ldr x16, [sp, #0x870] str x16, [sp, #0x7c0] - ldr x16, [sp, #0x17f0] + ldr x16, [sp, #0x868] str x16, [sp, #0x7c8] - ldr x16, [sp, #0x1800] + ldr x16, [sp, #0x860] str x16, [sp, #0x7d0] - ldr x16, [sp, #0x1810] + ldr x16, [sp, #0x858] str x16, [sp, #0x7d8] + ldr x9, [sp, #0x7e0] blr x9 - add sp, sp, #0x7e0 - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x40 + add sp, sp, #0x7f0 mov x17, #0x848a // =33930 cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x28, [sp, #0x40] ldr x19, [sp, #0x50] - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x10 + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x7d0 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -9642,32 +9101,22 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x28, [sp, #0x40] ldr x19, [sp, #0x50] - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x10 + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x7d0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - ldr x28, [sp, #0x40] ldr x19, [sp, #0x50] - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x10 + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x7d0 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/call_sp_adjust_imm12_overflow.x64.asm b/tests/snapshots/asm/call_sp_adjust_imm12_overflow.x64.asm index 1136e11f4..287382b1c 100644 --- a/tests/snapshots/asm/call_sp_adjust_imm12_overflow.x64.asm +++ b/tests/snapshots/asm/call_sp_adjust_imm12_overflow.x64.asm @@ -1055,13 +1055,12 @@ Disassembly of section .text: movq %r10, -0x1050(%rbp) movq 0x2078(%rbp), %r10 movq %r10, -0x1048(%rbp) - xorq %rax, %rax + leaq -0x10(%rbp), %rax + movq (%rax), %rax leaq -0x10(%rbp), %rcx - movq (%rcx), %rcx - leaq -0x10(%rbp), %rdx - movq 0x8(%rdx), %rdx - addq %rdx, %rcx + movq 0x8(%rcx), %rcx addq %rcx, %rax + addq $0x0, %rax leaq -0x20(%rbp), %rcx movq (%rcx), %rcx leaq -0x20(%rbp), %rdx @@ -3143,10 +3142,7 @@ Disassembly of section .text: pushq %r10 pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp - movq %rbx, (%rsp) - xorq %rax, %rax - addq %rdi, %rax + leaq (%rdi), %rax addq %rsi, %rax addq %rdx, %rax addq %rcx, %rax @@ -3660,8 +3656,6 @@ Disassembly of section .text: addq %rcx, %rax movq 0x1040(%rbp), %rcx addq %rcx, %rax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp popq %r11 addq $0x1040, %rsp # imm = 0x1040 @@ -3671,7 +3665,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x1050, %rsp # imm = 0x1050 + subq $0x810, %rsp # imm = 0x810 movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -3680,10 +3674,6 @@ Disassembly of section .text: leaq -, %rbx # leaq -, %r12 # xorq %rcx, %rcx - cmpq $0x105, %rcx # imm = 0x105 - jge - jmp - incq %rcx jmp leaq , %rax movq %rcx, %rdx @@ -3696,7 +3686,9 @@ Disassembly of section .text: movq %rcx, %rdx shlq $0x1, %rdx movq %rdx, 0x8(%rax) - jmp + incq %rcx + cmpq $0x105, %rcx # imm = 0x105 + jl leaq , %rdi leaq 0x10(%rdi), %rsi leaq 0x20(%rdi), %rdx @@ -5518,7 +5510,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x1050, %rsp # imm = 0x1050 + addq $0x810, %rsp # imm = 0x810 popq %rbp retq movl $0x1, %edi @@ -6550,7 +6542,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x1050, %rsp # imm = 0x1050 + addq $0x810, %rsp # imm = 0x810 popq %rbp retq leaq , %rdi @@ -8377,7 +8369,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x1050, %rsp # imm = 0x1050 + addq $0x810, %rsp # imm = 0x810 popq %rbp retq xorq %rax, %rax @@ -8386,7 +8378,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x1050, %rsp # imm = 0x1050 + addq $0x810, %rsp # imm = 0x810 popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/callee_save_pair_fold.aarch64.asm b/tests/snapshots/asm/callee_save_pair_fold.aarch64.asm new file mode 100644 index 000000000..f74fa5068 --- /dev/null +++ b/tests/snapshots/asm/callee_save_pair_fold.aarch64.asm @@ -0,0 +1,68 @@ + +callee_save_pair_fold.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x20, x0 + sxtw x20, w20 + cmp x20, #0x0 + b.gt + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + sub x0, x20, #0x1 + bl + add x0, x20, x0 + sxtw x0, w0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + +: + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] + str x24, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 + mov x20, x0 + mov x24, x4 + mov x23, x3 + mov x22, x2 + mov x21, x1 + sxtw x20, w20 + mov x0, x20 + bl + add x0, x0, x20 + add x0, x0, x21 + add x0, x0, x22 + add x0, x0, x23 + add x0, x0, x24 + sxtw x0, w0 + ldp x29, x30, [sp, #0x30] + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x1 // =1 + mov x1, #0x2 // =2 + mov x2, #0x3 // =3 + mov x3, #0x4 // =4 + mov x4, #0x5 // =5 + bl + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/callee_save_pair_fold.x64.asm b/tests/snapshots/asm/callee_save_pair_fold.x64.asm new file mode 100644 index 000000000..000d72291 --- /dev/null +++ b/tests/snapshots/asm/callee_save_pair_fold.x64.asm @@ -0,0 +1,77 @@ + +callee_save_pair_fold.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + movq %rdi, %rbx + movslq %ebx, %rbx + testq %rbx, %rbx + jg + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + leaq -0x1(%rbx), %rdi + callq + addq %rbx, %rax + movslq %eax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x30, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %r15, 0x20(%rsp) + movq %rdi, %rbx + movq %r8, %r15 + movq %rcx, %r14 + movq %rdx, %r13 + movq %rsi, %r12 + movslq %ebx, %rbx + movq %rbx, %rdi + callq + addq %rbx, %rax + addq %r12, %rax + addq %r13, %rax + addq %r14, %rax + addq %r15, %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x30, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + movl $0x1, %edi + movl $0x2, %esi + movl $0x3, %edx + movl $0x4, %ecx + movl $0x5, %r8d + popq %rbp + jmp diff --git a/tests/snapshots/asm/callee_save_pair_large_frame.aarch64.asm b/tests/snapshots/asm/callee_save_pair_large_frame.aarch64.asm new file mode 100644 index 000000000..a391b1820 --- /dev/null +++ b/tests/snapshots/asm/callee_save_pair_large_frame.aarch64.asm @@ -0,0 +1,64 @@ + +callee_save_pair_large_frame.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x20, x0 + sxtw x20, w20 + cmp x20, #0x0 + b.gt + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + sub x0, x20, #0x1 + bl + add x0, x20, x0 + sxtw x0, w0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + +: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x340 + stp x20, x21, [sp] + mov x20, x0 + mov x21, x1 + sub x0, x29, #0x320 + str w20, [x0] + sub x0, x29, #0x320 + str w21, [x0, #0x31c] + sub x0, x29, #0x320 + ldrsw x0, [x0] + bl + sub x1, x29, #0x320 + ldrsw x1, [x1, #0x31c] + add x0, x0, x1 + add x0, x0, x20 + add x0, x0, x21 + sxtw x0, w0 + ldp x20, x21, [sp] + add sp, sp, #0x340 + ldp x29, x30, [sp], #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x3 // =3 + mov x1, #0x4 // =4 + bl + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/callee_save_pair_large_frame.x64.asm b/tests/snapshots/asm/callee_save_pair_large_frame.x64.asm new file mode 100644 index 000000000..3e2d564f4 --- /dev/null +++ b/tests/snapshots/asm/callee_save_pair_large_frame.x64.asm @@ -0,0 +1,69 @@ + +callee_save_pair_large_frame.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + movq %rdi, %rbx + movslq %ebx, %rbx + testq %rbx, %rbx + jg + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + leaq -0x1(%rbx), %rdi + callq + addq %rbx, %rax + movslq %eax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x340, %rsp # imm = 0x340 + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %rdi, %rbx + movq %rsi, %r12 + leaq -0x320(%rbp), %rax + movl %ebx, (%rax) + leaq -0x320(%rbp), %rax + movl %r12d, 0x31c(%rax) + leaq -0x320(%rbp), %rax + movslq (%rax), %rdi + callq + leaq -0x320(%rbp), %rcx + movslq 0x31c(%rcx), %rcx + addq %rcx, %rax + addq %rbx, %rax + addq %r12, %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x340, %rsp # imm = 0x340 + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + movl $0x3, %edi + movl $0x4, %esi + popq %rbp + jmp diff --git a/tests/snapshots/asm/case_label_declaration.aarch64.asm b/tests/snapshots/asm/case_label_declaration.aarch64.asm index 479dbb423..d50e9e9bc 100644 --- a/tests/snapshots/asm/case_label_declaration.aarch64.asm +++ b/tests/snapshots/asm/case_label_declaration.aarch64.asm @@ -10,32 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x0, w0 - mov x1, #0x0 // =0 cmp x0, #0x2 b.lt - b + cmp x0, #0x2 + b.eq + mov x0, #0x1e // =30 sxtw x0, w0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xa // =10 - add x0, x1, x0 - b mov x0, #0x14 // =20 - add x0, x1, x0 - b - mov x0, #0x1e // =30 - add x0, x1, x0 b cmp x0, #0x1 - b.eq - b - cmp x0, #0x2 - b.eq + b.ne + mov x0, #0xa // =10 b b diff --git a/tests/snapshots/asm/case_label_declaration.x64.asm b/tests/snapshots/asm/case_label_declaration.x64.asm index 2563299ec..7614bd0b8 100644 --- a/tests/snapshots/asm/case_label_declaration.x64.asm +++ b/tests/snapshots/asm/case_label_declaration.x64.asm @@ -11,32 +11,19 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movslq %edi, %rdi - xorq %rax, %rax cmpq $0x2, %rdi jl - jmp + cmpq $0x2, %rdi + je + movl $0x1e, %eax movslq %eax, %rax - addq $0x20, %rsp - popq %rbp retq - movl $0xa, %ecx - addq %rcx, %rax - jmp - movl $0x14, %ecx - addq %rcx, %rax - jmp - movl $0x1e, %ecx - addq %rcx, %rax + movl $0x14, %eax jmp cmpq $0x1, %rdi - je - jmp - cmpq $0x2, %rdi - je + jne + movl $0xa, %eax jmp jmp @@ -68,4 +55,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/cast_abstract_fn_ptr.aarch64.asm b/tests/snapshots/asm/cast_abstract_fn_ptr.aarch64.asm index 802f8c972..4273734e7 100644 --- a/tests/snapshots/asm/cast_abstract_fn_ptr.aarch64.asm +++ b/tests/snapshots/asm/cast_abstract_fn_ptr.aarch64.asm @@ -20,31 +20,28 @@ Disassembly of section .text: ldr x10, [x1] str x10, [x0] ldr x10, [sp], #0x10 - mov x0, #0x0 // =0 - sub x1, x29, #0x8 - ldr x1, [x1] - cmp x1, #0x0 + sub x0, x29, #0x8 + ldr x0, [x0] + cmp x0, #0x0 b.eq mov x0, #0x1 // =1 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - adrp x1, - add x1, x1, - ldr x1, [x1] - cmp x1, #0x0 + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x0 b.eq mov x0, #0x2 // =2 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x0 - b.eq - mov x0, #0x3 // =3 + mov x0, #0x0 // =0 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x3 // =3 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/cast_abstract_fn_ptr.x64.asm b/tests/snapshots/asm/cast_abstract_fn_ptr.x64.asm index 33c4c3664..4c7485cb6 100644 --- a/tests/snapshots/asm/cast_abstract_fn_ptr.x64.asm +++ b/tests/snapshots/asm/cast_abstract_fn_ptr.x64.asm @@ -20,30 +20,27 @@ Disassembly of section .text: movq (%rcx), %rdx movq %rdx, (%rax) popq %rdx - xorq %rax, %rax - leaq -0x8(%rbp), %rcx - movq (%rcx), %rcx - testq %rcx, %rcx + leaq -0x8(%rbp), %rax + movq (%rax), %rax + testq %rax, %rax je movl $0x1, %eax addq $0x10, %rsp popq %rbp retq - leaq , %rcx - movq (%rcx), %rcx - testq %rcx, %rcx + leaq , %rax + movq (%rax), %rax + testq %rax, %rax je movl $0x2, %eax addq $0x10, %rsp popq %rbp retq - testq %rax, %rax - je - movl $0x3, %eax + xorq %rax, %rax addq $0x10, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x3, %eax addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/cast_fn_ptr_call.aarch64.asm b/tests/snapshots/asm/cast_fn_ptr_call.aarch64.asm index e535e4b82..1869e118b 100644 --- a/tests/snapshots/asm/cast_fn_ptr_call.aarch64.asm +++ b/tests/snapshots/asm/cast_fn_ptr_call.aarch64.asm @@ -20,63 +20,50 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x0, #0x29 // =41 - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x7 // =7 - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x8 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, mov x1, #0x15 // =21 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x2a b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/cast_fn_ptr_call.x64.asm b/tests/snapshots/asm/cast_fn_ptr_call.x64.asm index a0585b4b4..de01ac261 100644 --- a/tests/snapshots/asm/cast_fn_ptr_call.x64.asm +++ b/tests/snapshots/asm/cast_fn_ptr_call.x64.asm @@ -24,7 +24,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq -, %rbx # movl $0x29, %edi @@ -35,7 +35,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x7, %edi @@ -46,7 +46,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # @@ -57,12 +57,12 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/cast_fn_typedef_ptr_in_initializer.aarch64.asm b/tests/snapshots/asm/cast_fn_typedef_ptr_in_initializer.aarch64.asm index 6492c2a0f..ef1fd8b3e 100644 --- a/tests/snapshots/asm/cast_fn_typedef_ptr_in_initializer.aarch64.asm +++ b/tests/snapshots/asm/cast_fn_typedef_ptr_in_initializer.aarch64.asm @@ -15,46 +15,39 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, ldr x0, [x20] ldr x0, [x0] mov x1, #0x2 // =2 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20] ldrsw x0, [x0, #0x8] cmp x0, #0x7 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/cast_to_struct_pointer.aarch64.asm b/tests/snapshots/asm/cast_to_struct_pointer.aarch64.asm index c09fa96db..cce9c64a3 100644 --- a/tests/snapshots/asm/cast_to_struct_pointer.aarch64.asm +++ b/tests/snapshots/asm/cast_to_struct_pointer.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x10 // =16 bl mov x1, #0x2a // =42 @@ -21,7 +20,6 @@ Disassembly of section .text: mov x2, #0x0 // =0 str x2, [x0, #0x8] sxtw x0, w1 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/cast_to_struct_pointer.x64.asm b/tests/snapshots/asm/cast_to_struct_pointer.x64.asm index 86ca97f61..565164734 100644 --- a/tests/snapshots/asm/cast_to_struct_pointer.x64.asm +++ b/tests/snapshots/asm/cast_to_struct_pointer.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x10, %edi xorl %eax, %eax callq @@ -22,8 +21,6 @@ Disassembly of section .text: xorq %rdx, %rdx movq %rdx, 0x8(%rax) movslq %ecx, %rax - addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/char_constant_signedness.aarch64.asm b/tests/snapshots/asm/char_constant_signedness.aarch64.asm index e1bb4b899..e096f207b 100644 --- a/tests/snapshots/asm/char_constant_signedness.aarch64.asm +++ b/tests/snapshots/asm/char_constant_signedness.aarch64.asm @@ -13,55 +13,30 @@ Disassembly of section .text: ldrb w0, [x0] cmp x0, #0x80 b.lt - b + cmp x0, #0xff + b.lt + cmp x0, #0xff + b.eq mov x0, #0x0 // =0 ret - mov x0, #0x1 // =1 - ret mov x0, #0x2 // =2 ret + cmp x0, #0x80 + b.ne + mov x0, #0x1 // =1 + ret + cmp x0, #0x28 + b.ne mov x0, #0x3 // =3 ret mov x0, #0x0 // =0 ret - cmp x0, #0x28 - b.eq - b - cmp x0, #0xff - b.lt - b - cmp x0, #0x80 - b.eq - b - cmp x0, #0xff - b.eq - b b
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x80 // =128 - mov x17, #0x80 // =128 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xff // =255 - mov x17, #0xff // =255 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x18 mov x1, #0x80 // =128 strb w1, [x0] @@ -88,3 +63,11 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/char_constant_signedness.x64.asm b/tests/snapshots/asm/char_constant_signedness.x64.asm index 0067c084a..7d2ed1c82 100644 --- a/tests/snapshots/asm/char_constant_signedness.x64.asm +++ b/tests/snapshots/asm/char_constant_signedness.x64.asm @@ -14,49 +14,30 @@ Disassembly of section .text: movsbq (%rdi), %rax cmpq $-0x1, %rax jl - jmp + cmpq $0x28, %rax + jl + cmpq $0x28, %rax + je xorq %rax, %rax retq - movl $0x1, %eax + movl $0x3, %eax retq + cmpq $-0x1, %rax + jne movl $0x2, %eax retq - movl $0x3, %eax + cmpq $-0x80, %rax + jne + movl $0x1, %eax retq xorq %rax, %rax retq - cmpq $-0x80, %rax - je - jmp - cmpq $0x28, %rax - jl - jmp - cmpq $-0x1, %rax - je - jmp - cmpq $0x28, %rax - je - jmp jmp
: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $-0x80, %rax - cmpq $-0x80, %rax - je - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - cmpq $-0x1, %rax - je - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax movabsq $-0x80, %rcx movb %cl, (%rax) @@ -83,4 +64,12 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x20, %rsp + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/char_limits_consistency.aarch64.asm b/tests/snapshots/asm/char_limits_consistency.aarch64.asm index a508f2fe9..e29ab8fbd 100644 --- a/tests/snapshots/asm/char_limits_consistency.aarch64.asm +++ b/tests/snapshots/asm/char_limits_consistency.aarch64.asm @@ -10,46 +10,29 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xff // =255 - cmp x0, #0x0 - b.ge - mov x1, #0x1 // =1 - b - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x3 // =3 ret mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x4 // =4 + ret + mov x0, #0x0 // =0 + ret + mov x1, #0x1 // =1 b mov x1, #0x1 // =1 cbz x1, mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x1, #0x1 // =1 b mov x1, #0x1 // =1 cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b - mov x1, #0x0 // =0 - cbz x1, - mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x0 // =0 - mov x1, #0x0 // =0 - cbz x1, - mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret b diff --git a/tests/snapshots/asm/char_limits_consistency.x64.asm b/tests/snapshots/asm/char_limits_consistency.x64.asm index 657dbf1a6..1ad9d81b0 100644 --- a/tests/snapshots/asm/char_limits_consistency.x64.asm +++ b/tests/snapshots/asm/char_limits_consistency.x64.asm @@ -11,42 +11,27 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movabsq $-0x1, %rax - testq %rax, %rax - jge xorq %rcx, %rcx - jmp - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp - retq - movl $0x1, %ecx - jmp xorq %rcx, %rcx testq %rcx, %rcx je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rcx, %rcx xorq %rcx, %rcx testq %rcx, %rcx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq + xorq %rax, %rax + retq + movl $0x1, %ecx + jmp jmp movl $0x1, %ecx testq %rcx, %rcx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movl $0x1, %ecx jmp @@ -54,7 +39,5 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq jmp diff --git a/tests/snapshots/asm/clock_monotonic_advances.aarch64.asm b/tests/snapshots/asm/clock_monotonic_advances.aarch64.asm index 2c9fd8e6f..793ee93b4 100644 --- a/tests/snapshots/asm/clock_monotonic_advances.aarch64.asm +++ b/tests/snapshots/asm/clock_monotonic_advances.aarch64.asm @@ -10,11 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x80]! + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 sub x0, x29, #0x10 mov x1, #0xffff // =65535 movk x1, #0xffff, lsl #16 @@ -30,10 +28,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret sub x0, x29, #0x10 ldr x0, [x0] @@ -42,8 +38,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - cset x20, eq - cbz x20, + cset x1, eq + cbz x1, sub x0, x29, #0x10 ldr x0, [x0, #0x8] mov x17, #0xffff // =65535 @@ -51,57 +47,48 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - cset x20, eq - cbz x20, + cset x1, eq + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret sub x0, x29, #0x10 ldr x0, [x0] cmp x0, #0x0 b.ge mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret sub x0, x29, #0x10 ldr x0, [x0, #0x8] cmp x0, #0x0 - cset x20, lt - cbnz x20, + cset x1, lt + cbnz x1, sub x0, x29, #0x10 ldr x0, [x0, #0x8] mov x17, #0xca00 // =51712 movk x17, #0x3b9a, lsl #16 cmp x0, x17 - cset x20, ge - cbz x20, + cset x1, ge + cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret mov x1, #0x0 // =0 stur w1, [x29, #-0x28] + b + ldursw x2, [x29, #-0x28] + add x2, x2, #0x1 + stur w2, [x29, #-0x28] + add x1, x0, #0x1 sxtw x0, w1 mov x17, #0x4240 // =16960 movk x17, #0xf, lsl #16 cmp x0, x17 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - ldursw x0, [x29, #-0x28] - add x0, x0, #0x1 - stur w0, [x29, #-0x28] - b + b.lt mov x0, #0x1 // =1 sub x1, x29, #0x20 bl @@ -109,10 +96,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret sub x0, x29, #0x20 ldr x0, [x0] @@ -121,10 +106,8 @@ Disassembly of section .text: cmp x0, x1 b.ge mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret sub x0, x29, #0x20 ldr x0, [x0] @@ -141,16 +124,12 @@ Disassembly of section .text: cset x1, lt cbz x1, mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret b b diff --git a/tests/snapshots/asm/clock_monotonic_advances.x64.asm b/tests/snapshots/asm/clock_monotonic_advances.x64.asm index 9292601ae..d137d9ff1 100644 --- a/tests/snapshots/asm/clock_monotonic_advances.x64.asm +++ b/tests/snapshots/asm/clock_monotonic_advances.x64.asm @@ -13,8 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) + subq $0x60, %rsp leaq -0x10(%rbp), %rax movabsq $-0x1, %rcx movq %rcx, (%rax) @@ -28,27 +27,25 @@ Disassembly of section .text: testq %rax, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x10(%rbp), %rax movq (%rax), %rax cmpq $-0x1, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax cmpq $-0x1, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x10(%rbp), %rax @@ -56,42 +53,37 @@ Disassembly of section .text: testq %rax, %rax jge movl $0x3, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax testq %rax, %rax - setl %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setl %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax cmpq $0x3b9aca00, %rax # imm = 0x3B9ACA00 - setge %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setge %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq xorq %rcx, %rcx movl %ecx, -0x28(%rbp) - movslq %ecx, %rax - cmpq $0xf4240, %rax # imm = 0xF4240 - jge jmp - movslq %ecx, %rax + movslq -0x28(%rbp), %rdx + incq %rdx + movl %edx, -0x28(%rbp) leaq 0x1(%rax), %rcx - jmp - movslq -0x28(%rbp), %rax - incq %rax - movl %eax, -0x28(%rbp) - jmp + movslq %ecx, %rax + cmpq $0xf4240, %rax # imm = 0xF4240 + jl movl $0x1, %edi leaq -0x20(%rbp), %rsi xorl %eax, %eax @@ -100,8 +92,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -111,8 +102,7 @@ Disassembly of section .text: cmpq %rcx, %rax jge movl $0x6, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -134,16 +124,13 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x7, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/code_as_data.aarch64.asm b/tests/snapshots/asm/code_as_data.aarch64.asm index 2c77c09ac..0dc96e88e 100644 --- a/tests/snapshots/asm/code_as_data.aarch64.asm +++ b/tests/snapshots/asm/code_as_data.aarch64.asm @@ -14,12 +14,7 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldrsw x0, [x0] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/code_as_data.x64.asm b/tests/snapshots/asm/code_as_data.x64.asm index 61af9eb85..d4a77e284 100644 --- a/tests/snapshots/asm/code_as_data.x64.asm +++ b/tests/snapshots/asm/code_as_data.x64.asm @@ -15,11 +15,8 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - leaq -, %rax # + leaq -, %rax # movslq (%rax), %rax - addq $0x10, %rsp - popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/comma_operator_in_loops.aarch64.asm b/tests/snapshots/asm/comma_operator_in_loops.aarch64.asm index 39b3b9f41..3727c7485 100644 --- a/tests/snapshots/asm/comma_operator_in_loops.aarch64.asm +++ b/tests/snapshots/asm/comma_operator_in_loops.aarch64.asm @@ -19,11 +19,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, #0x0 // =0 add x20, x20, #0xa mov x21, #0x0 // =0 @@ -34,46 +32,37 @@ Disassembly of section .text: add x20, x20, #0x64 mov x0, #0x7 // =7 bl - b - mov x21, #0x0 // =0 - b - add x20, x20, #0x1 - b add x20, x20, #0x3e8 - b - mov x17, #0x869f // =34463 - movk x17, #0x1, lsl #16 - add x20, x20, x17 - b - b - b - b mov x0, #0x0 // =0 bl - sxtw x0, w21 - cmp x0, #0x3 - b.ge - b - sxtw x0, w21 - add x21, x0, #0x1 - b add x20, x20, #0x1 - b + mov x0, #0x0 // =0 + bl + add x20, x20, #0x1 + mov x0, #0x0 // =0 + bl + add x20, x20, #0x1 + mov x0, #0x0 // =0 + bl adrp x0, add x0, x0, ldrsw x0, [x0] cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret sub x0, x20, #0x456 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret + add x20, x20, #0x1 + b + mov x17, #0x869f // =34463 + movk x17, #0x1, lsl #16 + add x20, x20, x17 + b + b + b diff --git a/tests/snapshots/asm/comma_operator_in_loops.x64.asm b/tests/snapshots/asm/comma_operator_in_loops.x64.asm index 246d53036..96a51f5be 100644 --- a/tests/snapshots/asm/comma_operator_in_loops.x64.asm +++ b/tests/snapshots/asm/comma_operator_in_loops.x64.asm @@ -35,29 +35,18 @@ Disassembly of section .text: addq $0x64, %rbx movl $0x7, %edi callq - jmp - xorq %r12, %r12 - jmp - incq %rbx - jmp addq $0x3e8, %rbx # imm = 0x3E8 - jmp - addq $0x1869f, %rbx # imm = 0x1869F - jmp - jmp - jmp - jmp xorq %rdi, %rdi callq - movslq %r12d, %rax - cmpq $0x3, %rax - jge - jmp - movslq %r12d, %rax - leaq 0x1(%rax), %r12 - jmp incq %rbx - jmp + xorq %rdi, %rdi + callq + incq %rbx + xorq %rdi, %rdi + callq + incq %rbx + xorq %rdi, %rdi + callq leaq , %rax movslq (%rax), %rax cmpq $0x7, %rax @@ -75,4 +64,9 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) + incq %rbx + jmp + addq $0x1869f, %rbx # imm = 0x1869F + jmp + jmp + jmp diff --git a/tests/snapshots/asm/commutative_imm_lhs_swap.aarch64.asm b/tests/snapshots/asm/commutative_imm_lhs_swap.aarch64.asm index d75faaf40..f39a69fd6 100644 --- a/tests/snapshots/asm/commutative_imm_lhs_swap.aarch64.asm +++ b/tests/snapshots/asm/commutative_imm_lhs_swap.aarch64.asm @@ -10,84 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x7 // =7 - lsl x1, x0, #2 - sxtw x1, w1 - cmp x1, #0x1c - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - add x1, x0, #0x3 - sxtw x1, w1 - cmp x1, #0xa - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xf0 // =240 - and x1, x0, x17 - cmp x1, #0x0 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0x10 // =16 - orr x1, x0, x17 - cmp x1, #0x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xff // =255 - eor x1, x0, x17 - cmp x1, #0xf8 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x1 - cset x1, eq - cmp x1, #0x0 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x1 - cset x1, ne - cmp x1, #0x1 - b.eq mov x0, #0x7 // =7 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0xa // =10 - sub x1, x1, x0 - sxtw x1, w1 - cmp x1, #0x3 - b.eq mov x0, #0x8 // =8 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x8 - cset x0, lt - cmp x0, #0x0 - b.ne mov x0, #0x9 // =9 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/commutative_imm_lhs_swap.x64.asm b/tests/snapshots/asm/commutative_imm_lhs_swap.x64.asm index cb3a6d66d..a6ecd09d5 100644 --- a/tests/snapshots/asm/commutative_imm_lhs_swap.x64.asm +++ b/tests/snapshots/asm/commutative_imm_lhs_swap.x64.asm @@ -11,89 +11,24 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x7, %eax - movq %rax, %rcx - shlq $0x2, %rcx - movslq %ecx, %rcx - cmpq $0x1c, %rcx - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq - leaq 0x3(%rax), %rcx - movslq %ecx, %rcx - cmpq $0xa, %rcx - je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq - movq %rax, %rcx - andq $0xf0, %rcx - testq %rcx, %rcx - je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq - movq %rax, %rcx - orq $0x10, %rcx - cmpq $0x17, %rcx - je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq - movq %rax, %rcx - xorq $0xff, %rcx - cmpq $0xf8, %rcx - je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq - cmpq $0x1, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je movl $0x6, %eax - addq $0x10, %rsp - popq %rbp retq - cmpq $0x1, %rax - setne %cl - movzbq %cl, %rcx - cmpq $0x1, %rcx - je movl $0x7, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0xa, %ecx - subq %rax, %rcx - movslq %ecx, %rcx - cmpq $0x3, %rcx - je movl $0x8, %eax - addq $0x10, %rsp - popq %rbp retq - cmpq $0x8, %rax - setl %al - movzbq %al, %rax - testq %rax, %rax - jne movl $0x9, %eax - addq $0x10, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/comparison_imm_lhs_swap.aarch64.asm b/tests/snapshots/asm/comparison_imm_lhs_swap.aarch64.asm index 5fd980c66..4dbccfa5f 100644 --- a/tests/snapshots/asm/comparison_imm_lhs_swap.aarch64.asm +++ b/tests/snapshots/asm/comparison_imm_lhs_swap.aarch64.asm @@ -10,87 +10,49 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] - mov x20, #0x5 // =5 - mov x21, #0x0 // =0 - cmp x20, #0x0 - b.le - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0x0 - b.lt - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0xa - b.ge - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0xa - b.gt - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0x0 - b.ls - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0x0 - b.lo - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0xa - b.hs - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0xa - b.hi - add x0, x21, #0x1 - sxtw x21, w0 - cmp x20, #0xa - b.le - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - cmp x20, #0x0 - b.ge - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + mov x20, #0x0 // =0 + mov x20, #0x1 // =1 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 + add x0, x20, #0x1 + sxtw x20, w0 adrp x0, add x0, x0, - sxtw x1, w21 + sxtw x1, w20 bl sxtw x0, w0 - sxtw x0, w21 + sxtw x0, w20 cmp x0, #0x8 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x3 // =3 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret + mov x1, #0x3 // =3 b - b - b - b - b - b - b - b + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret diff --git a/tests/snapshots/asm/comparison_imm_lhs_swap.x64.asm b/tests/snapshots/asm/comparison_imm_lhs_swap.x64.asm index 1d00555b6..470f75d29 100644 --- a/tests/snapshots/asm/comparison_imm_lhs_swap.x64.asm +++ b/tests/snapshots/asm/comparison_imm_lhs_swap.x64.asm @@ -13,82 +13,48 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movl $0x5, %ebx - xorq %r12, %r12 - testq %rbx, %rbx - jle - leaq 0x1(%r12), %rax - movslq %eax, %r12 - testq %rbx, %rbx - jl - leaq 0x1(%r12), %rax - movslq %eax, %r12 - cmpq $0xa, %rbx - jge - leaq 0x1(%r12), %rax - movslq %eax, %r12 - cmpq $0xa, %rbx - jg - leaq 0x1(%r12), %rax - movslq %eax, %r12 - testq %rbx, %rbx - jbe - leaq 0x1(%r12), %rax - movslq %eax, %r12 - testq %rbx, %rbx - jb - leaq 0x1(%r12), %rax - movslq %eax, %r12 - cmpq $0xa, %rbx - jae - leaq 0x1(%r12), %rax - movslq %eax, %r12 - cmpq $0xa, %rbx - ja - leaq 0x1(%r12), %rax - movslq %eax, %r12 - cmpq $0xa, %rbx - jle - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x40, %rsp - popq %rbp - retq - testq %rbx, %rbx - jge - movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x40, %rsp - popq %rbp - retq + xorq %rbx, %rbx + movl $0x1, %ebx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx + leaq 0x1(%rbx), %rax + movslq %eax, %rbx leaq , %rdi - movslq %r12d, %rsi + movslq %ebx, %rsi movb $0x0, %al callq movslq %eax, %rax - movslq %r12d, %rax + movslq %ebx, %rax cmpq $0x8, %rax jne xorq %rcx, %rcx - jmp - movl $0x3, %ecx movq (%rsp), %rbx - movq 0x8(%rsp), %r12 movq %rcx, %rax - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq + movl $0x3, %ecx jmp - jmp - jmp - jmp - jmp - jmp - jmp - jmp - addb %al, 0x41(%rdx) + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/complement_preserves_type.aarch64.asm b/tests/snapshots/asm/complement_preserves_type.aarch64.asm index 4ff25defc..b46ca847a 100644 --- a/tests/snapshots/asm/complement_preserves_type.aarch64.asm +++ b/tests/snapshots/asm/complement_preserves_type.aarch64.asm @@ -10,91 +10,20 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0x7fff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x5 // =5 ret mov x0, #0x0 // =0 - mvn x0, x0 - lsr x0, x0, #1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - b.eq + ret + mov x0, #0x1 // =1 + ret mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - mvn x0, x0 - mov w0, w0 - lsr x0, x0, #1 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x2, ne - cbnz x2, - asr x0, x0, #1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x2, ne - cbz x2, - mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #-0x8000000000000000 // =-9223372036854775808 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - cset x0, hi - cmp x0, #0x0 - b.ne mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - b diff --git a/tests/snapshots/asm/complement_preserves_type.x64.asm b/tests/snapshots/asm/complement_preserves_type.x64.asm index 0e0afb7fb..9a53ed223 100644 --- a/tests/snapshots/asm/complement_preserves_type.x64.asm +++ b/tests/snapshots/asm/complement_preserves_type.x64.asm @@ -11,71 +11,22 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movabsq $0x7fffffffffffffff, %rax # imm = 0x7FFFFFFFFFFFFFFF - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx je - movl $0x1, %eax - addq $0x30, %rsp - popq %rbp + movl $0x5, %eax retq xorq %rax, %rax - xorq $-0x1, %rax - shrq $0x1, %rax - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax - je + retq + movl $0x1, %eax + retq movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - xorq %rax, %rax - xorq $-0x1, %rax - movl %eax, %eax - shrq $0x1, %rax - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - jmp movl $0x4, %eax - addq $0x30, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - cmpq $-0x1, %rax - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne - sarq $0x1, %rax - cmpq $-0x1, %rax - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax - seta %al - movzbq %al, %rax - testq %rax, %rax - jne movl $0x6, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm new file mode 100644 index 000000000..5cc0377cf --- /dev/null +++ b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm @@ -0,0 +1,272 @@ + +compound_assign_float_register_resident.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x30 + mov x0, #0x42c80000 // =1120403456 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d1, s1 + fmov d17, x0 + fadd d1, d1, d17 + fcvt s1, d1 + sub x17, x29, #0x10 + str s1, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d0, s1 + fmov d17, x0 + fadd d0, d0, d17 + fcvt s0, d0 + sub x17, x29, #0x10 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x42f00000 // =1123024896 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x1 // =1 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + sub x16, x29, #0x10 + ldr s0, [x16] + mov x0, #0x41100000 // =1091567616 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x2 // =2 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3f000000 // =1056964608 + fmov s16, w0 + sub x17, x29, #0x20 + str s16, [x17] + sub x16, x29, #0x20 + ldr s0, [x16] + mov x1, #-0x4010000000000000 // =-4616189618054758400 + fcvt d0, s0 + fmov d17, x1 + fadd d0, d0, d17 + fcvt s0, d0 + sub x17, x29, #0x20 + str s0, [x17] + sub x16, x29, #0x20 + ldr s0, [x16] + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 + cset x0, ne + cbz x0, + mov x0, #0x3 // =3 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + sub x17, x29, #0x28 + str s16, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] + mov x0, #0x4010000000000000 // =4616189618054758400 + fcvt d0, s0 + fmov d17, x0 + fmul d0, d0, d17 + fcvt s0, d0 + sub x17, x29, #0x28 + str s0, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fdiv s0, s0, s17 + sub x17, x29, #0x28 + str s0, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x4 // =4 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm new file mode 100644 index 000000000..3023a4484 --- /dev/null +++ b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm @@ -0,0 +1,234 @@ + +compound_assign_float_register_resident.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x30, %rsp + movl $0x42c80000, %eax # imm = 0x42C80000 + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) + movl $0x3f800000, %eax # imm = 0x3F800000 + movq %rax, %xmm14 + movss %xmm14, -0x10(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + addsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + movss %xmm1, -0x10(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm1, %xmm0 + movq %rax, %xmm15 + addsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x10(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x42f00000, %eax # imm = 0x42F00000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x30, %rsp + popq %rbp + retq + movss -0x10(%rbp,%riz), %xmm0 + movl $0x41100000, %eax # imm = 0x41100000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x2, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm14 + movss %xmm14, -0x20(%rbp,%riz) + movss -0x20(%rbp,%riz), %xmm0 + movabsq $-0x4010000000000000, %rcx # imm = 0xBFF0000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rcx, %xmm15 + addsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x20(%rbp,%riz) + movss -0x20(%rbp,%riz), %xmm0 + movq %rax, %xmm1 + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x3, %eax + addq $0x30, %rsp + popq %rbp + retq + movl $0x40400000, %eax # imm = 0x40400000 + movq %rax, %xmm14 + movss %xmm14, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 + movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + mulsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movq %rax, %xmm15 + divss %xmm15, %xmm0 + movss %xmm0, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x4, %eax + addq $0x30, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x30, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm b/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm index 1b8c8c987..7fabccda6 100644 --- a/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm +++ b/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm @@ -66,12 +66,11 @@ Disassembly of section .text: ret mov x0, #0x7 // =7 scvtf d0, x0 - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d17, x0 - fadd d0, d0, d17 + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 + fmov s16, w0 + fcvt d1, s16 + fadd d0, d0, d1 fcvtzs x0, d0 sxtw x0, w0 cmp x0, #0x9 diff --git a/tests/snapshots/asm/compound_assign_int_fp.x64.asm b/tests/snapshots/asm/compound_assign_int_fp.x64.asm index e0566c713..a054b57df 100644 --- a/tests/snapshots/asm/compound_assign_int_fp.x64.asm +++ b/tests/snapshots/asm/compound_assign_int_fp.x64.asm @@ -64,9 +64,10 @@ Disassembly of section .text: retq movl $0x7, %eax cvtsi2sd %rax, %xmm0 - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm15 - addsd %xmm15, %xmm0 + movl $0x4039999a, %eax # imm = 0x4039999A + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + addsd %xmm1, %xmm0 cvttsd2si %xmm0, %rax movslq %eax, %rax cmpq $0x9, %rax @@ -161,5 +162,3 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_assign_unsigned_div.aarch64.asm b/tests/snapshots/asm/compound_assign_unsigned_div.aarch64.asm index b22201f68..6eb9e3a9d 100644 --- a/tests/snapshots/asm/compound_assign_unsigned_div.aarch64.asm +++ b/tests/snapshots/asm/compound_assign_unsigned_div.aarch64.asm @@ -10,108 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - udiv x0, x0, x1 - mov w0, w0 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - udiv x17, x0, x1 - msub x0, x17, x1, x0 - mov w0, w0 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x2 // =2 - mov w0, w0 - udiv x0, x0, x1 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfff9 // =65529 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x3 // =3 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x3 // =3 - udiv x0, x0, x1 - mov x17, #0x5555 // =21845 - movk x17, #0x5555, lsl #16 - movk x17, #0x5555, lsl #32 - movk x17, #0x5555, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xff // =255 - mov x1, #0xfffe // =65534 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - sdiv x0, x0, x1 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0x81 // =129 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/compound_assign_unsigned_div.x64.asm b/tests/snapshots/asm/compound_assign_unsigned_div.x64.asm index 34cbd9cf6..08b6f730f 100644 --- a/tests/snapshots/asm/compound_assign_unsigned_div.x64.asm +++ b/tests/snapshots/asm/compound_assign_unsigned_div.x64.asm @@ -11,99 +11,17 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0xfffffffe, %ecx # imm = 0xFFFFFFFE - pushq %rdx - xorq %rdx, %rdx - divq %rcx - popq %rdx - movl %eax, %eax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0xfffffffe, %ecx # imm = 0xFFFFFFFE - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rdx, %rax - popq %rdx - movl %eax, %eax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x2, %rax - movl $0x2, %ecx - movl %eax, %eax - pushq %rdx - xorq %rdx, %rdx - divq %rcx - popq %rdx - movslq %eax, %rax - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x7, %rax - movl $0x3, %ecx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movslq %eax, %rax - cmpq $-0x1, %rax - je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x1, %rax - movl $0x3, %ecx - pushq %rdx - xorq %rdx, %rdx - divq %rcx - popq %rdx - movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 - cmpq %r11, %rax - je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0xff, %eax - movabsq $-0x2, %rcx - pushq %rdx - cqto - idivq %rcx - popq %rdx - andq $0xff, %rax - xorq $0x81, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_literal_block.aarch64.asm b/tests/snapshots/asm/compound_literal_block.aarch64.asm index 8c2bf1123..4c30cb301 100644 --- a/tests/snapshots/asm/compound_literal_block.aarch64.asm +++ b/tests/snapshots/asm/compound_literal_block.aarch64.asm @@ -17,9 +17,6 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x3, #0x0 // =0 ldrsw x1, [x0] cmp x1, #0x1 @@ -45,17 +42,12 @@ Disassembly of section .text: cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x3, #0x0 // =0 ldr x1, [x0] ldrb w1, [x1] @@ -94,8 +86,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/compound_literal_block.x64.asm b/tests/snapshots/asm/compound_literal_block.x64.asm index c750b2a5e..9b5a79f4f 100644 --- a/tests/snapshots/asm/compound_literal_block.x64.asm +++ b/tests/snapshots/asm/compound_literal_block.x64.asm @@ -18,9 +18,6 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rdx, %rdx movslq (%rdi), %rax cmpq $0x1, %rax @@ -56,17 +53,12 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rdx, %rdx movq (%rdi), %rax movsbq (%rax), %rax @@ -106,8 +98,6 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp @@ -289,5 +279,4 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_literal_file_scope.aarch64.asm b/tests/snapshots/asm/compound_literal_file_scope.aarch64.asm index 5409d5224..ef89912dd 100644 --- a/tests/snapshots/asm/compound_literal_file_scope.aarch64.asm +++ b/tests/snapshots/asm/compound_literal_file_scope.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldr x1, [x0] @@ -34,8 +31,6 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -62,8 +57,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -72,8 +65,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -98,8 +89,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -108,8 +97,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -136,12 +123,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/compound_literal_file_scope.x64.asm b/tests/snapshots/asm/compound_literal_file_scope.x64.asm index e84093574..64fafe2f2 100644 --- a/tests/snapshots/asm/compound_literal_file_scope.x64.asm +++ b/tests/snapshots/asm/compound_literal_file_scope.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movq (%rax), %rcx movslq (%rcx), %rcx @@ -41,8 +38,6 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -73,8 +68,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -82,8 +75,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -104,8 +95,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -113,8 +102,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -145,12 +132,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -159,4 +142,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/computed_goto.aarch64.asm b/tests/snapshots/asm/computed_goto.aarch64.asm index a409a5f2d..32aea7112 100644 --- a/tests/snapshots/asm/computed_goto.aarch64.asm +++ b/tests/snapshots/asm/computed_goto.aarch64.asm @@ -15,7 +15,7 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x10 stur w0, [x29, #0x10] - ldursw x0, [x29, #0x10] + sxtw x0, w0 cmp x0, #0x0 b.ne adr x0, @@ -25,7 +25,6 @@ Disassembly of section .text: stur x0, [x29, #-0x10] ldur x0, [x29, #-0x10] stur x0, [x29, #-0x8] - ldur x0, [x29, #-0x8] br x0 mov x0, #0xa // =10 add sp, sp, #0x10 @@ -57,11 +56,11 @@ Disassembly of section .text: stur w1, [x29, #-0x20] stur w1, [x29, #-0x28] sub x0, x29, #0x18 - ldur x1, [x29, #0x10] - ldursw x2, [x29, #-0x28] - add x3, x2, #0x1 + ldur x2, [x29, #0x10] + sxtw x1, w1 + add x3, x1, #0x1 stur w3, [x29, #-0x28] - ldrsw x1, [x1, x2, lsl #2] + ldrsw x1, [x2, x1, lsl #2] ldr x0, [x0, x1, lsl #3] br x0 ldursw x0, [x29, #-0x20] @@ -69,12 +68,11 @@ Disassembly of section .text: ldursw x2, [x29, #-0x28] add x3, x2, #0x1 stur w3, [x29, #-0x28] - ldrsw x1, [x1, x2, lsl #2] - add x0, x0, x1 + ldrsw x2, [x1, x2, lsl #2] + add x0, x0, x2 stur w0, [x29, #-0x20] sub x0, x29, #0x18 - ldur x1, [x29, #0x10] - ldursw x2, [x29, #-0x28] + sxtw x2, w3 add x3, x2, #0x1 stur w3, [x29, #-0x28] ldrsw x1, [x1, x2, lsl #2] @@ -85,12 +83,11 @@ Disassembly of section .text: ldursw x2, [x29, #-0x28] add x3, x2, #0x1 stur w3, [x29, #-0x28] - ldrsw x1, [x1, x2, lsl #2] - sub x0, x0, x1 + ldrsw x2, [x1, x2, lsl #2] + sub x0, x0, x2 stur w0, [x29, #-0x20] sub x0, x29, #0x18 - ldur x1, [x29, #0x10] - ldursw x2, [x29, #-0x28] + sxtw x2, w3 add x3, x2, #0x1 stur w3, [x29, #-0x28] ldrsw x1, [x1, x2, lsl #2] @@ -119,10 +116,10 @@ Disassembly of section .text: ldursw x0, [x29, #-0x18] add x0, x0, #0x1 stur w0, [x29, #-0x18] - sub x0, x29, #0x10 - ldursw x1, [x29, #-0x18] + sub x1, x29, #0x10 + sxtw x0, w0 ldursw x2, [x29, #0x10] - cmp x1, x2 + cmp x0, x2 b.ge b ldursw x0, [x29, #-0x18] @@ -130,13 +127,13 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret - mov x1, #0x0 // =0 - stur x1, [x29, #-0x20] + mov x0, #0x0 // =0 + stur x0, [x29, #-0x20] b - mov x1, #0x1 // =1 - stur x1, [x29, #-0x20] - ldur x1, [x29, #-0x20] - ldr x0, [x0, x1, lsl #3] + mov x0, #0x1 // =1 + stur x0, [x29, #-0x20] + ldur x0, [x29, #-0x20] + ldr x0, [x1, x0, lsl #3] br x0
: diff --git a/tests/snapshots/asm/computed_goto.x64.asm b/tests/snapshots/asm/computed_goto.x64.asm index 1a4ad7220..234706ddd 100644 --- a/tests/snapshots/asm/computed_goto.x64.asm +++ b/tests/snapshots/asm/computed_goto.x64.asm @@ -19,7 +19,7 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x10, %rsp movl %edi, 0x10(%rbp) - movslq 0x10(%rbp), %rax + movslq %edi, %rax testq %rax, %rax jne leaq , %rax # @@ -29,7 +29,6 @@ Disassembly of section .text: movq %rax, -0x10(%rbp) movq -0x10(%rbp), %rax movq %rax, -0x8(%rbp) - movq -0x8(%rbp), %rax jmpq *%rax movl $0xa, %eax addq $0x10, %rsp @@ -68,11 +67,11 @@ Disassembly of section .text: movl %ecx, -0x20(%rbp) movl %ecx, -0x28(%rbp) leaq -0x18(%rbp), %rax - movq 0x10(%rbp), %rcx - movslq -0x28(%rbp), %rdx - leaq 0x1(%rdx), %rsi + movq 0x10(%rbp), %rdx + movslq %ecx, %rcx + leaq 0x1(%rcx), %rsi movl %esi, -0x28(%rbp) - movslq (%rcx,%rdx,4), %rcx + movslq (%rdx,%rcx,4), %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movslq -0x20(%rbp), %rax @@ -80,12 +79,11 @@ Disassembly of section .text: movslq -0x28(%rbp), %rdx leaq 0x1(%rdx), %rsi movl %esi, -0x28(%rbp) - movslq (%rcx,%rdx,4), %rcx - addq %rcx, %rax + movslq (%rcx,%rdx,4), %rdx + addq %rdx, %rax movl %eax, -0x20(%rbp) leaq -0x18(%rbp), %rax - movq 0x10(%rbp), %rcx - movslq -0x28(%rbp), %rdx + movslq %esi, %rdx leaq 0x1(%rdx), %rsi movl %esi, -0x28(%rbp) movslq (%rcx,%rdx,4), %rcx @@ -96,12 +94,11 @@ Disassembly of section .text: movslq -0x28(%rbp), %rdx leaq 0x1(%rdx), %rsi movl %esi, -0x28(%rbp) - movslq (%rcx,%rdx,4), %rcx - subq %rcx, %rax + movslq (%rcx,%rdx,4), %rdx + subq %rdx, %rax movl %eax, -0x20(%rbp) leaq -0x18(%rbp), %rax - movq 0x10(%rbp), %rcx - movslq -0x28(%rbp), %rdx + movslq %esi, %rdx leaq 0x1(%rdx), %rsi movl %esi, -0x28(%rbp) movslq (%rcx,%rdx,4), %rcx @@ -135,10 +132,10 @@ Disassembly of section .text: movslq -0x18(%rbp), %rax incq %rax movl %eax, -0x18(%rbp) - leaq -0x10(%rbp), %rax - movslq -0x18(%rbp), %rcx + leaq -0x10(%rbp), %rcx + movslq %eax, %rax movslq 0x10(%rbp), %rdx - cmpq %rdx, %rcx + cmpq %rdx, %rax jge jmp movslq -0x18(%rbp), %rax @@ -148,13 +145,13 @@ Disassembly of section .text: addq $0x10, %rsp pushq %r11 retq - xorq %rcx, %rcx - movq %rcx, -0x20(%rbp) + xorq %rax, %rax + movq %rax, -0x20(%rbp) jmp - movl $0x1, %ecx - movq %rcx, -0x20(%rbp) - movq -0x20(%rbp), %rcx - movq (%rax,%rcx,8), %rax + movl $0x1, %eax + movq %rax, -0x20(%rbp) + movq -0x20(%rbp), %rax + movq (%rcx,%rax,8), %rax jmpq *%rax
: @@ -223,4 +220,4 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/computed_goto_static_table.aarch64.asm b/tests/snapshots/asm/computed_goto_static_table.aarch64.asm new file mode 100644 index 000000000..8e7c53970 --- /dev/null +++ b/tests/snapshots/asm/computed_goto_static_table.aarch64.asm @@ -0,0 +1,130 @@ + +computed_goto_static_table.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur x0, [x29, #0x10] + adrp x0, + add x0, x0, + ldrsb x1, [x0, #0x20] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x18] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + adr x1, + str x1, [x0, #0x18] + mov x1, #0x1 // =1 + strb w1, [x0, #0x20] + stur x1, [x29, #-0x18] + mov x1, #0x0 // =0 + stur w1, [x29, #-0x8] + stur w1, [x29, #-0x10] + ldur x2, [x29, #0x10] + sxtw x1, w1 + add x3, x1, #0x1 + stur w3, [x29, #-0x10] + add x1, x2, x1 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + ldur x2, [x29, #0x10] + ldursw x3, [x29, #-0x10] + add x4, x3, #0x1 + stur w4, [x29, #-0x10] + add x3, x2, x3 + ldrb w3, [x3] + add x1, x1, x3 + stur w1, [x29, #-0x8] + sxtw x1, w4 + add x3, x1, #0x1 + stur w3, [x29, #-0x10] + add x1, x2, x1 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + ldur x2, [x29, #0x10] + ldursw x3, [x29, #-0x10] + add x4, x3, #0x1 + stur w4, [x29, #-0x10] + add x3, x2, x3 + ldrb w3, [x3] + sub x1, x1, x3 + stur w1, [x29, #-0x8] + sxtw x1, w4 + add x3, x1, #0x1 + stur w3, [x29, #-0x10] + add x1, x2, x1 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + add x1, x1, x1 + stur w1, [x29, #-0x8] + ldur x1, [x29, #0x10] + ldursw x2, [x29, #-0x10] + add x3, x2, #0x1 + stur w3, [x29, #-0x10] + add x1, x1, x2 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x0, [x29, #-0x8] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +
: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + adrp x20, + add x20, x20, + mov x0, x20 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + adrp x0, + add x0, x0, + bl + cmp x0, #0xa + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, x20 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret diff --git a/tests/snapshots/asm/computed_goto_static_table.x64.asm b/tests/snapshots/asm/computed_goto_static_table.x64.asm new file mode 100644 index 000000000..264b8e152 --- /dev/null +++ b/tests/snapshots/asm/computed_goto_static_table.x64.asm @@ -0,0 +1,140 @@ + +computed_goto_static_table.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rdi, 0x10(%rbp) + leaq , %rax + movsbq 0x20(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x18(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + leaq , %rcx # + movq %rcx, 0x18(%rax) + movl $0x1, %ecx + movb %cl, 0x20(%rax) + movq %rcx, -0x18(%rbp) + xorq %rcx, %rcx + movl %ecx, -0x8(%rbp) + movl %ecx, -0x10(%rbp) + movq 0x10(%rbp), %rdx + movslq %ecx, %rcx + leaq 0x1(%rcx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + movq 0x10(%rbp), %rdx + movslq -0x10(%rbp), %rsi + leaq 0x1(%rsi), %rdi + movl %edi, -0x10(%rbp) + addq %rdx, %rsi + movzbq (%rsi), %rsi + addq %rsi, %rcx + movl %ecx, -0x8(%rbp) + movslq %edi, %rcx + leaq 0x1(%rcx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + movq 0x10(%rbp), %rdx + movslq -0x10(%rbp), %rsi + leaq 0x1(%rsi), %rdi + movl %edi, -0x10(%rbp) + addq %rdx, %rsi + movzbq (%rsi), %rsi + subq %rsi, %rcx + movl %ecx, -0x8(%rbp) + movslq %edi, %rcx + leaq 0x1(%rcx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + addq %rcx, %rcx + movl %ecx, -0x8(%rbp) + movq 0x10(%rbp), %rcx + movslq -0x10(%rbp), %rdx + leaq 0x1(%rdx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + leaq , %rbx + movq %rbx, %rdi + callq + cmpq $0x7, %rax + je + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + leaq , %rdi + callq + cmpq $0xa, %rax + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movq %rbx, %rdi + callq + cmpq $0x7, %rax + je + movl $0x3, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_addr_multidim_array_elem.aarch64.asm b/tests/snapshots/asm/const_addr_multidim_array_elem.aarch64.asm index 591dc85cb..ed30cd11a 100644 --- a/tests/snapshots/asm/const_addr_multidim_array_elem.aarch64.asm +++ b/tests/snapshots/asm/const_addr_multidim_array_elem.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, adrp x1, @@ -22,24 +19,18 @@ Disassembly of section .text: cmp x2, #0x300 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x2, [x1, #0x8] sub x2, x2, x0 cmp x2, #0x190 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x1, #0x10] sub x0, x1, x0 cmp x0, #0x8 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -50,8 +41,6 @@ Disassembly of section .text: cmp x1, #0x80 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x1, add x1, x1, @@ -60,10 +49,6 @@ Disassembly of section .text: cmp x0, #0x48 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/const_addr_multidim_array_elem.x64.asm b/tests/snapshots/asm/const_addr_multidim_array_elem.x64.asm index 359ea61d3..c39541e91 100644 --- a/tests/snapshots/asm/const_addr_multidim_array_elem.x64.asm +++ b/tests/snapshots/asm/const_addr_multidim_array_elem.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax leaq , %rcx movq (%rcx), %rdx @@ -21,16 +18,12 @@ Disassembly of section .text: cmpq $0x300, %rdx # imm = 0x300 je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rcx), %rdx subq %rax, %rdx cmpq $0x190, %rdx # imm = 0x190 je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rcx), %rcx movq %rax, %r10 @@ -39,8 +32,6 @@ Disassembly of section .text: cmpq $0x8, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax leaq , %rcx @@ -49,8 +40,6 @@ Disassembly of section .text: cmpq $0x80, %rcx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rcx movq 0x8(%rcx), %rcx @@ -60,11 +49,7 @@ Disassembly of section .text: cmpq $0x48, %rax je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_expr_arithmetic.aarch64.asm b/tests/snapshots/asm/const_expr_arithmetic.aarch64.asm index 723607a9b..032c6787c 100644 --- a/tests/snapshots/asm/const_expr_arithmetic.aarch64.asm +++ b/tests/snapshots/asm/const_expr_arithmetic.aarch64.asm @@ -10,126 +10,62 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x0 // =0 - mov x0, #0x20 // =32 - add x0, x0, x20 - asr x0, x0, #2 - cmp x0, #0x8 - b.eq + sxtw x0, w20 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret adrp x0, add x0, x0, - mov x1, #0x20 // =32 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x8 // =8 bl sxtw x0, w0 mov x20, #0x1 // =1 - mov x0, #0x18 // =24 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x6 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x18 // =24 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x6 // =6 bl sxtw x0, w0 mov x20, #0x2 // =2 - mov x0, #0x40 // =64 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x10 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x40 // =64 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x10 // =16 bl sxtw x0, w0 mov x20, #0x3 // =3 - mov x0, #0x40 // =64 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x10 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x40 // =64 mov x20, #0x4 // =4 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x10 // =16 bl sxtw x0, w0 - mov x0, #0x18 // =24 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x6 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x18 // =24 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x6 // =6 bl sxtw x0, w0 mov x20, #0x5 // =5 - mov x0, #0x20 // =32 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x8 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x20 // =32 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x8 // =8 bl sxtw x0, w0 mov x20, #0x6 // =6 - mov x0, #0x18 // =24 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x6 - b.eq + b adrp x0, add x0, x0, - mov x1, #0x18 // =24 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #2 + mov x1, #0x6 // =6 bl sxtw x0, w0 mov x20, #0x7 // =7 - sxtw x0, w20 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - b - b - b - b - b b diff --git a/tests/snapshots/asm/const_expr_arithmetic.x64.asm b/tests/snapshots/asm/const_expr_arithmetic.x64.asm index bdf375c3c..a29f0844a 100644 --- a/tests/snapshots/asm/const_expr_arithmetic.x64.asm +++ b/tests/snapshots/asm/const_expr_arithmetic.x64.asm @@ -16,126 +16,59 @@ Disassembly of section .text: subq $0x10, %rsp movq %rbx, (%rsp) xorq %rbx, %rbx - movl $0x20, %eax - addq %rbx, %rax - sarq $0x2, %rax - cmpq $0x8, %rax - je + movslq %ebx, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq leaq , %rdi - movl $0x20, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x8, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %ebx - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x6, %rax - je + jmp leaq , %rdi - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x6, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x2, %ebx - movl $0x40, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x10, %rax - je + jmp leaq , %rdi - movl $0x40, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x10, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x3, %ebx - movl $0x40, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x10, %rax - je + jmp leaq , %rdi - movl $0x40, %eax movl $0x4, %ebx - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x10, %esi movb $0x0, %al callq movslq %eax, %rax - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x6, %rax - je + jmp leaq , %rdi - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x6, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x5, %ebx - movl $0x20, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x8, %rax - je + jmp leaq , %rdi - movl $0x20, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x8, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x6, %ebx - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x6, %rax - je + jmp leaq , %rdi - movl $0x18, %eax - xorq %rcx, %rcx - addq %rcx, %rax - movq %rax, %rsi - sarq $0x2, %rsi + movl $0x6, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x7, %ebx - movslq %ebx, %rax - movq (%rsp), %rbx - addq $0x10, %rsp - popq %rbp - retq - jmp - jmp - jmp - jmp - jmp - jmp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_expr_cast_narrowing.aarch64.asm b/tests/snapshots/asm/const_expr_cast_narrowing.aarch64.asm index 35b123ab8..bf216dd0c 100644 --- a/tests/snapshots/asm/const_expr_cast_narrowing.aarch64.asm +++ b/tests/snapshots/asm/const_expr_cast_narrowing.aarch64.asm @@ -10,33 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/const_expr_cast_narrowing.x64.asm b/tests/snapshots/asm/const_expr_cast_narrowing.x64.asm index 3c0181d01..430392dd8 100644 --- a/tests/snapshots/asm/const_expr_cast_narrowing.x64.asm +++ b/tests/snapshots/asm/const_expr_cast_narrowing.x64.asm @@ -11,29 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - jmp + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq - jmp movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movslq %eax, %rax - cmpq $-0x1, %rax - je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/const_expr_unsigned_fold.aarch64.asm b/tests/snapshots/asm/const_expr_unsigned_fold.aarch64.asm index d60d73ebd..ac6019bf5 100644 --- a/tests/snapshots/asm/const_expr_unsigned_fold.aarch64.asm +++ b/tests/snapshots/asm/const_expr_unsigned_fold.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr x0, [x0] @@ -23,8 +20,6 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -36,8 +31,6 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -45,8 +38,6 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -54,8 +45,6 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -63,8 +52,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -73,26 +60,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x10 // =16 mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x4 - b.eq - mov x0, #0x7 // =7 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xc // =12 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x3 - cset x1, ne - cbnz x1, adrp x0, add x0, x0, ldrsw x0, [x0] @@ -100,11 +69,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x8 // =8 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - b + mov x0, #0x7 // =7 + ret diff --git a/tests/snapshots/asm/const_expr_unsigned_fold.x64.asm b/tests/snapshots/asm/const_expr_unsigned_fold.x64.asm index 94f7d29d4..60e90a735 100644 --- a/tests/snapshots/asm/const_expr_unsigned_fold.x64.asm +++ b/tests/snapshots/asm/const_expr_unsigned_fold.x64.asm @@ -11,17 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movq (%rax), %rax movabsq $0x5555555555555555, %r11 # imm = 0x5555555555555555 cmpq %r11, %rax je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -29,32 +24,24 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax cmpq $0x1, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x1, %rax je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax testq %rax, %rax je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -62,28 +49,8 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x6, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0x10, %eax xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x4, %rax - je - movl $0x7, %eax - addq $0x10, %rsp - popq %rbp - retq - movl $0xc, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x3, %rax - setne %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -92,12 +59,10 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x8, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq - jmp + movl $0x7, %eax + retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_float_div_zero.aarch64.asm b/tests/snapshots/asm/const_float_div_zero.aarch64.asm index fb9dabacf..81ad6ce88 100644 --- a/tests/snapshots/asm/const_float_div_zero.aarch64.asm +++ b/tests/snapshots/asm/const_float_div_zero.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr d0, [x0] @@ -26,8 +23,6 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -43,8 +38,6 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -53,8 +46,6 @@ Disassembly of section .text: cset x0, eq cbz x0, mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x0 // =0 @@ -71,10 +62,6 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/const_float_div_zero.x64.asm b/tests/snapshots/asm/const_float_div_zero.x64.asm index 1b5c9887d..e9a76f46a 100644 --- a/tests/snapshots/asm/const_float_div_zero.x64.asm +++ b/tests/snapshots/asm/const_float_div_zero.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movsd (%rax,%riz), %xmm0 movabsq $0x7fe1ccf385ebc8a0, %rax # imm = 0x7FE1CCF385EBC8A0 @@ -24,8 +21,6 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -43,8 +38,6 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -57,8 +50,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 xorq %rcx, %rcx @@ -73,10 +64,8 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm b/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm index 89fb258dd..57732d966 100644 --- a/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm +++ b/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm @@ -35,10 +35,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, eq cmp x0, #0x0 b.ne diff --git a/tests/snapshots/asm/const_float_init_int_lead.x64.asm b/tests/snapshots/asm/const_float_init_int_lead.x64.asm index e3dbcb6d3..c9e104746 100644 --- a/tests/snapshots/asm/const_float_init_int_lead.x64.asm +++ b/tests/snapshots/asm/const_float_init_int_lead.x64.asm @@ -41,10 +41,9 @@ Disassembly of section .text: retq leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -56,4 +55,3 @@ Disassembly of section .text: retq xorq %rax, %rax retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/constfold_post_inline.aarch64.asm b/tests/snapshots/asm/constfold_post_inline.aarch64.asm new file mode 100644 index 000000000..34ace8b07 --- /dev/null +++ b/tests/snapshots/asm/constfold_post_inline.aarch64.asm @@ -0,0 +1,395 @@ + +constfold_post_inline.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + add x0, x0, x1 + ret + +: + mul x0, x0, x1 + ret + +: + sub x0, x0, x1 + ret + +: + sxtw x1, w1 + lsl x0, x0, x1 + ret + +: + sxtw x1, w1 + lsr x0, x0, x1 + ret + +: + sxtw x1, w1 + asr x0, x0, x1 + ret + +: + udiv x0, x0, x1 + ret + +: + udiv x17, x0, x1 + msub x0, x17, x1, x0 + ret + +: + sdiv x0, x0, x1 + ret + +: + sdiv x17, x0, x1 + msub x0, x17, x1, x0 + ret + +: + sxtw x1, w1 + ror x0, x0, x1 + ret + +: + cmp x0, x1 + cset x0, lt + ret + +: + cmp x0, x1 + cset x0, gt + ret + +: + cmp x0, x1 + cset x0, le + ret + +: + cmp x0, x1 + cset x0, ge + ret + +: + cmp x0, x1 + cset x0, lo + ret + +: + cmp x0, x1 + cset x0, hi + ret + +: + cmp x0, x1 + cset x0, ls + ret + +: + cmp x0, x1 + cset x0, hs + ret + +: + cmp x0, x1 + cset x0, eq + ret + +: + cmp x0, x1 + cset x0, ne + ret + +: + sxtb x0, w0 + ret + +: + sxth x0, w0 + ret + +: + sxtw x0, w0 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x80 + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x14 // =20 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x15 // =21 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x16 // =22 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x17 // =23 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x18 // =24 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x19 // =25 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x1a // =26 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x1b // =27 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x1c // =28 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x1d // =29 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcdef // =52719 + movk x0, #0x89ab, lsl #16 + movk x0, #0x4567, lsl #32 + movk x0, #0x123, lsl #48 + stur x0, [x29, #-0x8] + ldur x0, [x29, #-0x8] + add x1, x0, #0x5 + mov x17, #0xcdf4 // =52724 + movk x17, #0x89ab, lsl #16 + movk x17, #0x4567, lsl #32 + movk x17, #0x123, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x24 // =36 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + add x1, x0, #0x5 + mov x17, #0xcdf4 // =52724 + movk x17, #0x89ab, lsl #16 + movk x17, #0x4567, lsl #32 + movk x17, #0x123, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x25 // =37 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + cmp x0, #0x64 + cset x1, hi + cmp x1, #0x0 + b.ne + mov x0, #0x26 // =38 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + cmp x0, #0x64 + b.hs + mov x0, #0x27 // =39 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + cset x1, ls + cmp x1, #0x0 + b.ne + mov x0, #0x28 // =40 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + ror x1, x0, #0x7 + mov x17, #0x579b // =22427 + movk x17, #0xcf13, lsl #16 + movk x17, #0x468a, lsl #32 + movk x17, #0xde02, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x29 // =41 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x17, #0x41 // =65 + lsl x0, x0, x17 + mov x17, #0x9bde // =39902 + movk x17, #0x1357, lsl #16 + movk x17, #0x8acf, lsl #32 + movk x17, #0x246, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x2a // =42 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xfff8 // =65528 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + stur x0, [x29, #-0x18] + ldur x0, [x29, #-0x18] + asr x0, x0, #1 + mov x17, #0xfffc // =65532 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x2b // =43 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xa // =10 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xf // =15 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10 // =16 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x11 // =17 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x12 // =18 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x13 // =19 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1e // =30 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1f // =31 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x20 // =32 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x21 // =33 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x22 // =34 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x23 // =35 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/constfold_post_inline.x64.asm b/tests/snapshots/asm/constfold_post_inline.x64.asm new file mode 100644 index 000000000..a4658a80b --- /dev/null +++ b/tests/snapshots/asm/constfold_post_inline.x64.asm @@ -0,0 +1,427 @@ + +constfold_post_inline.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + leaq (%rdi,%rsi), %rax + retq + +: + movq %rdi, %rax + imulq %rsi, %rax + retq + +: + movq %rdi, %rax + subq %rsi, %rax + retq + +: + movslq %esi, %rsi + movq %rdi, %rax + movq %rsi, %rcx + shlq %cl, %rax + retq + +: + movslq %esi, %rsi + movq %rdi, %rax + movq %rsi, %rcx + shrq %cl, %rax + retq + +: + movslq %esi, %rsi + movq %rdi, %rax + movq %rsi, %rcx + sarq %cl, %rax + retq + +: + pushq %rdx + movq %rdi, %rax + xorq %rdx, %rdx + divq %rsi + popq %rdx + retq + +: + pushq %rdx + movq %rdi, %rax + xorq %rdx, %rdx + divq %rsi + movq %rdx, %rax + popq %rdx + retq + +: + pushq %rdx + movq %rdi, %rax + cqto + idivq %rsi + popq %rdx + retq + +: + pushq %rdx + movq %rdi, %rax + cqto + idivq %rsi + movq %rdx, %rax + popq %rdx + retq + +: + movslq %esi, %rsi + movq %rdi, %rax + pushq %rcx + movq %rsi, %rcx + rorq %cl, %rax + popq %rcx + retq + +: + cmpq %rsi, %rdi + setl %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setg %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setle %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setge %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setb %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + seta %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setbe %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setae %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + sete %al + movzbq %al, %rax + retq + +: + cmpq %rsi, %rdi + setne %al + movzbq %al, %rax + retq + +: + movq %rdi, %rax + movsbq %al, %rax + retq + +: + movq %rdi, %rax + movswq %ax, %rax + retq + +: + movq %rdi, %rax + movslq %eax, %rax + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x80, %rsp + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x14, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x15, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x16, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x17, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x18, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x19, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x1a, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x1b, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x1c, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x1d, %eax + addq $0x80, %rsp + popq %rbp + retq + movabsq $0x123456789abcdef, %rax # imm = 0x123456789ABCDEF + movq %rax, -0x8(%rbp) + movq -0x8(%rbp), %rax + leaq 0x5(%rax), %rcx + movabsq $0x123456789abcdf4, %r11 # imm = 0x123456789ABCDF4 + cmpq %r11, %rcx + je + movl $0x24, %eax + addq $0x80, %rsp + popq %rbp + retq + leaq 0x5(%rax), %rcx + movabsq $0x123456789abcdf4, %r11 # imm = 0x123456789ABCDF4 + cmpq %r11, %rcx + je + movl $0x25, %eax + addq $0x80, %rsp + popq %rbp + retq + cmpq $0x64, %rax + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne + movl $0x26, %eax + addq $0x80, %rsp + popq %rbp + retq + cmpq $0x64, %rax + jae + movl $0x27, %eax + addq $0x80, %rsp + popq %rbp + retq + cmpq $-0x1, %rax + setbe %cl + movzbq %cl, %rcx + testq %rcx, %rcx + jne + movl $0x28, %eax + addq $0x80, %rsp + popq %rbp + retq + movq %rax, %rcx + rorq $0x7, %rcx + movabsq $-0x21fdb97530eca865, %r11 # imm = 0xDE02468ACF13579B + cmpq %r11, %rcx + je + movl $0x29, %eax + addq $0x80, %rsp + popq %rbp + retq + pushq %rcx + movl $0x41, %ecx + shlq %cl, %rax + popq %rcx + movabsq $0x2468acf13579bde, %r11 # imm = 0x2468ACF13579BDE + cmpq %r11, %rax + je + movl $0x2a, %eax + addq $0x80, %rsp + popq %rbp + retq + movabsq $-0x8, %rax + movq %rax, -0x18(%rbp) + movq -0x18(%rbp), %rax + sarq $0x1, %rax + cmpq $-0x4, %rax + je + movl $0x2b, %eax + addq $0x80, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x80, %rsp + popq %rbp + retq + movl $0x1, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x7, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x9, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xa, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xb, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xc, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xd, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xe, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0xf, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x10, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x11, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x12, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x13, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x1e, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x1f, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x20, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x21, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x22, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x23, %eax + addq $0x80, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/control_flow.aarch64.asm b/tests/snapshots/asm/control_flow.aarch64.asm index 8583086a6..a77474259 100644 --- a/tests/snapshots/asm/control_flow.aarch64.asm +++ b/tests/snapshots/asm/control_flow.aarch64.asm @@ -10,16 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x5 - b.ge - add x0, x1, #0x1 - sxtw x1, w0 - b - sxtw x0, w1 - cmp x0, #0x5 - b.ne mov x0, #0x1 // =1 ret mov x0, #0x0 // =0 diff --git a/tests/snapshots/asm/control_flow.x64.asm b/tests/snapshots/asm/control_flow.x64.asm index cd93566e8..be7cb2b07 100644 --- a/tests/snapshots/asm/control_flow.x64.asm +++ b/tests/snapshots/asm/control_flow.x64.asm @@ -11,16 +11,6 @@ Disassembly of section .text: ud2
: - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x5, %rax - jge - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - jmp - movslq %ecx, %rax - cmpq $0x5, %rax - jne movl $0x1, %eax retq xorq %rax, %rax diff --git a/tests/snapshots/asm/data_reloc_one_past_end.aarch64.asm b/tests/snapshots/asm/data_reloc_one_past_end.aarch64.asm index da8fa6471..3fec9e955 100644 --- a/tests/snapshots/asm/data_reloc_one_past_end.aarch64.asm +++ b/tests/snapshots/asm/data_reloc_one_past_end.aarch64.asm @@ -10,26 +10,21 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, #0x0 // =0 adrp x1, add x1, x1, + b + ldr x0, [x1] + add x2, x2, x0 + add x1, x1, #0x8 adrp x0, add x0, x0, ldr x0, [x0] cmp x1, x0 - b.eq - ldr x0, [x1] - add x2, x2, x0 - add x1, x1, #0x8 - b + b.ne adrp x0, add x0, x0, ldr x0, [x0, #0x18] add x0, x2, x0 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/data_reloc_one_past_end.x64.asm b/tests/snapshots/asm/data_reloc_one_past_end.x64.asm index 55f3dc1eb..a122e8ce9 100644 --- a/tests/snapshots/asm/data_reloc_one_past_end.x64.asm +++ b/tests/snapshots/asm/data_reloc_one_past_end.x64.asm @@ -11,25 +11,19 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rdx, %rdx leaq , %rcx - leaq , %rax - movq (%rax), %rax - cmpq %rax, %rcx - je + jmp movq (%rcx), %rax addq %rax, %rdx addq $0x8, %rcx - jmp + leaq , %rax + movq (%rax), %rax + cmpq %rax, %rcx + jne leaq , %rax movq 0x18(%rax), %rax addq %rdx, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/dead_local_load_frame_elide.aarch64.asm b/tests/snapshots/asm/dead_local_load_frame_elide.aarch64.asm new file mode 100644 index 000000000..29a87a2bb --- /dev/null +++ b/tests/snapshots/asm/dead_local_load_frame_elide.aarch64.asm @@ -0,0 +1,100 @@ + +dead_local_load_frame_elide.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + add x1, x0, #0x0 + ldrb w1, [x1] + mov x17, #0x0 // =0 + orr x1, x1, x17 + lsl x1, x1, #8 + ldrb w2, [x0, #0x1] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w2, [x0, #0x2] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w2, [x0, #0x3] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w2, [x0, #0x4] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w2, [x0, #0x5] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w2, [x0, #0x6] + orr x1, x1, x2 + lsl x1, x1, #8 + ldrb w0, [x0, #0x7] + orr x0, x1, x0 + ret + +: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + ldrb w0, [x0] + stur x0, [x29, #-0x8] + ldur x0, [x29, #-0x8] + mov x0, #0x9 // =9 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + sub x0, x29, #0x8 + add x0, x0, #0x0 + mov x1, #0x1 // =1 + strb w1, [x0] + sub x0, x29, #0x8 + mov x1, #0x2 // =2 + strb w1, [x0, #0x1] + sub x0, x29, #0x8 + mov x1, #0x3 // =3 + strb w1, [x0, #0x2] + sub x0, x29, #0x8 + mov x1, #0x4 // =4 + strb w1, [x0, #0x3] + sub x0, x29, #0x8 + mov x1, #0x5 // =5 + strb w1, [x0, #0x4] + sub x0, x29, #0x8 + mov x1, #0x6 // =6 + strb w1, [x0, #0x5] + sub x0, x29, #0x8 + mov x1, #0x7 // =7 + strb w1, [x0, #0x6] + sub x0, x29, #0x8 + mov x1, #0x8 // =8 + strb w1, [x0, #0x7] + sub x0, x29, #0x8 + bl + mov x17, #0x708 // =1800 + movk x17, #0x506, lsl #16 + movk x17, #0x304, lsl #32 + movk x17, #0x102, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/dead_local_load_frame_elide.x64.asm b/tests/snapshots/asm/dead_local_load_frame_elide.x64.asm new file mode 100644 index 000000000..29864b8e8 --- /dev/null +++ b/tests/snapshots/asm/dead_local_load_frame_elide.x64.asm @@ -0,0 +1,99 @@ + +dead_local_load_frame_elide.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + leaq (%rdi), %rax + movzbq (%rax), %rax + orq $0x0, %rax + shlq $0x8, %rax + movzbq 0x1(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x2(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x3(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x4(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x5(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x6(%rdi), %rcx + orq %rcx, %rax + shlq $0x8, %rax + movzbq 0x7(%rdi), %rcx + orq %rcx, %rax + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movzbq (%rdi), %rax + movq %rax, -0x8(%rbp) + movq -0x8(%rbp), %rax + movl $0x9, %eax + addq $0x10, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + leaq -0x8(%rbp), %rax + addq $0x0, %rax + movl $0x1, %ecx + movb %cl, (%rax) + leaq -0x8(%rbp), %rax + movl $0x2, %ecx + movb %cl, 0x1(%rax) + leaq -0x8(%rbp), %rax + movl $0x3, %ecx + movb %cl, 0x2(%rax) + leaq -0x8(%rbp), %rax + movl $0x4, %ecx + movb %cl, 0x3(%rax) + leaq -0x8(%rbp), %rax + movl $0x5, %ecx + movb %cl, 0x4(%rax) + leaq -0x8(%rbp), %rax + movl $0x6, %ecx + movb %cl, 0x5(%rax) + leaq -0x8(%rbp), %rax + movl $0x7, %ecx + movb %cl, 0x6(%rax) + leaq -0x8(%rbp), %rax + movl $0x8, %ecx + movb %cl, 0x7(%rax) + leaq -0x8(%rbp), %rdi + callq + movabsq $0x102030405060708, %r11 # imm = 0x102030405060708 + cmpq %r11, %rax + je + movl $0x1, %eax + addq $0x20, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x20, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x20, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/decimal_literal_over_signed_max.aarch64.asm b/tests/snapshots/asm/decimal_literal_over_signed_max.aarch64.asm index 4a1c0195a..3f57b2d05 100644 --- a/tests/snapshots/asm/decimal_literal_over_signed_max.aarch64.asm +++ b/tests/snapshots/asm/decimal_literal_over_signed_max.aarch64.asm @@ -10,20 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/decimal_literal_over_signed_max.x64.asm b/tests/snapshots/asm/decimal_literal_over_signed_max.x64.asm index 6c4f8e47c..7211e15b8 100644 --- a/tests/snapshots/asm/decimal_literal_over_signed_max.x64.asm +++ b/tests/snapshots/asm/decimal_literal_over_signed_max.x64.asm @@ -11,20 +11,16 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/decl_specifier_any_order.aarch64.asm b/tests/snapshots/asm/decl_specifier_any_order.aarch64.asm index 926afb583..fc98dcf2a 100644 --- a/tests/snapshots/asm/decl_specifier_any_order.aarch64.asm +++ b/tests/snapshots/asm/decl_specifier_any_order.aarch64.asm @@ -13,77 +13,49 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - b + sub x0, x29, #0x30 + mov x1, #0xfffb // =65531 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + str x1, [x0, #0x8] + sub x0, x29, #0x30 + ldr x0, [x0, #0x8] + cmp x0, #0x0 + b.lt + mov x0, #0x8 // =8 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret mov x0, #0x1 // =1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x2 // =2 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x100000000 // =4294967296 - asr x0, x0, #32 - cmp x0, #0x1 - b.eq mov x0, #0x3 // =3 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov w0, w0 - cmp x0, #0x0 - cset x0, hi - cmp x0, #0x0 - b.ne mov x0, #0x4 // =4 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0xff // =255 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x5 // =5 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x6 // =6 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x7 // =7 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x30 - mov x1, #0xfffb // =65531 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - str x1, [x0, #0x8] - sub x0, x29, #0x30 - ldr x0, [x0, #0x8] - cmp x0, #0x0 - b.lt - mov x0, #0x8 // =8 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/decl_specifier_any_order.x64.asm b/tests/snapshots/asm/decl_specifier_any_order.x64.asm index ff8048b3c..90f735d8d 100644 --- a/tests/snapshots/asm/decl_specifier_any_order.x64.asm +++ b/tests/snapshots/asm/decl_specifier_any_order.x64.asm @@ -14,67 +14,47 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - jmp + leaq -0x30(%rbp), %rax + movabsq $-0x5, %rcx + movq %rcx, 0x8(%rax) + leaq -0x30(%rbp), %rax + movq 0x8(%rax), %rax + testq %rax, %rax + jl + movl $0x8, %eax + addq $0x30, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x30, %rsp + popq %rbp + retq movl $0x1, %eax addq $0x30, %rsp popq %rbp retq - jmp movl $0x2, %eax addq $0x30, %rsp popq %rbp retq - movabsq $0x100000000, %rax # imm = 0x100000000 - sarq $0x20, %rax - cmpq $0x1, %rax - je movl $0x3, %eax addq $0x30, %rsp popq %rbp retq - movabsq $-0x1, %rax - movl %eax, %eax - testq %rax, %rax - seta %al - movzbq %al, %rax - testq %rax, %rax - jne movl $0x4, %eax addq $0x30, %rsp popq %rbp retq - movabsq $-0x1, %rax - andq $0xff, %rax - xorq $0xff, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x5, %eax addq $0x30, %rsp popq %rbp retq - jmp movl $0x6, %eax addq $0x30, %rsp popq %rbp retq - jmp movl $0x7, %eax addq $0x30, %rsp popq %rbp retq - leaq -0x30(%rbp), %rax - movabsq $-0x5, %rcx - movq %rcx, 0x8(%rax) - leaq -0x30(%rbp), %rax - movq 0x8(%rax), %rax - testq %rax, %rax - jl - movl $0x8, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/deferred_jit_thread_local.aarch64.asm b/tests/snapshots/asm/deferred_jit_thread_local.aarch64.asm index 7047b4158..37d37f95e 100644 --- a/tests/snapshots/asm/deferred_jit_thread_local.aarch64.asm +++ b/tests/snapshots/asm/deferred_jit_thread_local.aarch64.asm @@ -18,10 +18,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x0 // =0 bl mrs x0, TPIDR_EL0 @@ -30,9 +29,8 @@ Disassembly of section .text: cmp x1, #0x7 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -44,9 +42,8 @@ Disassembly of section .text: cmp x1, x17 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrsw x1, [x0] mrs x2, TPIDR_EL0 @@ -58,12 +55,10 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/deferred_libc_vfprintf_va_list.aarch64.asm b/tests/snapshots/asm/deferred_libc_vfprintf_va_list.aarch64.asm index 5d7066c47..0aacc47a2 100644 --- a/tests/snapshots/asm/deferred_libc_vfprintf_va_list.aarch64.asm +++ b/tests/snapshots/asm/deferred_libc_vfprintf_va_list.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x20 mov x16, x0 @@ -57,17 +56,15 @@ Disassembly of section .text: bl sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x19, [sp] + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x40 mov x1, #0x40 // =64 adrp x2, @@ -88,12 +85,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret diff --git a/tests/snapshots/asm/deferred_outer_2d_array_stride.aarch64.asm b/tests/snapshots/asm/deferred_outer_2d_array_stride.aarch64.asm index 333989c8d..d018a9695 100644 --- a/tests/snapshots/asm/deferred_outer_2d_array_stride.aarch64.asm +++ b/tests/snapshots/asm/deferred_outer_2d_array_stride.aarch64.asm @@ -10,24 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - b - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, add x1, x0, #0x10 @@ -35,8 +17,6 @@ Disassembly of section .text: cmp x0, #0x10 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -46,8 +26,6 @@ Disassembly of section .text: cmp x0, #0x10 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -70,8 +48,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -90,8 +66,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -110,18 +84,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x8 // =8 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x9 // =9 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xa // =10 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -129,8 +91,6 @@ Disassembly of section .text: cmp x0, #0xc b.eq mov x0, #0xb // =11 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -138,13 +98,19 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0xc // =12 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b b + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret + mov x0, #0x9 // =9 + ret + mov x0, #0xa // =10 + ret diff --git a/tests/snapshots/asm/deferred_outer_2d_array_stride.x64.asm b/tests/snapshots/asm/deferred_outer_2d_array_stride.x64.asm index 7261328c4..1c9071de6 100644 --- a/tests/snapshots/asm/deferred_outer_2d_array_stride.x64.asm +++ b/tests/snapshots/asm/deferred_outer_2d_array_stride.x64.asm @@ -11,24 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - jmp - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq leaq , %rax leaq 0x10(%rax), %rcx movq %rax, %r10 @@ -37,8 +19,6 @@ Disassembly of section .text: cmpq $0x10, %rax je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax leaq 0x20(%rax), %rcx @@ -49,8 +29,6 @@ Disassembly of section .text: cmpq $0x10, %rax je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -69,8 +47,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movq 0x10(%rax), %rax @@ -88,8 +64,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x7, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movq 0x20(%rax), %rax @@ -107,40 +81,32 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x8, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x9, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0xa, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movslq 0x2c(%rax), %rax cmpq $0xc, %rax je movl $0xb, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movslq 0x10(%rax), %rax cmpq $0x5, %rax je movl $0xc, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp jmp + movl $0x1, %eax + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq + movl $0x9, %eax + retq + movl $0xa, %eax + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.aarch64.asm b/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.aarch64.asm index b4bb7ef6a..245120a91 100644 --- a/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.aarch64.asm +++ b/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.aarch64.asm @@ -22,18 +22,13 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] - str x26, [sp, #0x30] - str x27, [sp, #0x38] + stp x20, x21, [sp, #-0xc0]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] str x28, [sp, #0x40] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 mov w0, w0 mov x17, #0x1111 // =4369 movk x17, #0x1111, lsl #16 @@ -92,12 +87,11 @@ Disassembly of section .text: eor x3, x3, x7 mov w3, w3 mov w4, w4 - mov x7, #0xc // =12 - ldr w8, [x1, #0xc] - eor x4, x4, x8 + ldr w7, [x1, #0xc] + eor x4, x4, x7 mov w4, w4 - ldr w8, [x1, #0x10] - eor x0, x0, x8 + ldr w7, [x1, #0x10] + eor x0, x0, x7 mov w0, w0 mov w6, w6 ldr w1, [x1, #0x14] @@ -111,205 +105,202 @@ Disassembly of section .text: eor x6, x6, x17 mov x17, #0xb821 // =47137 movk x17, #0x500f, lsl #16 - and x8, x5, x17 + and x7, x5, x17 mov x17, #0xedff // =60927 movk x17, #0xaeaa, lsl #16 - eor x8, x8, x17 + eor x7, x7, x17 mov x17, #0xa809 // =43017 movk x17, #0x40ef, lsl #16 - and x9, x5, x17 + and x8, x5, x17 mov x17, #0x6665 // =26213 movk x17, #0x3739, lsl #16 - eor x9, x9, x17 + eor x8, x8, x17 mov x17, #0xb28 // =2856 movk x17, #0xa5ec, lsl #16 - and x10, x5, x17 + and x9, x5, x17 mov x17, #0xb833 // =47155 movk x17, #0x68d7, lsl #16 - eor x10, x10, x17 + eor x9, x9, x17 mov x17, #0xf820 // =63520 movk x17, #0x252c, lsl #16 - and x11, x5, x17 + and x10, x5, x17 mov x17, #0x55bb // =21947 movk x17, #0xc9c7, lsl #16 - eor x11, x11, x17 + eor x10, x10, x17 mov x17, #0x5801 // =22529 movk x17, #0x4020, lsl #16 - and x12, x5, x17 + and x11, x5, x17 mov x17, #0x3606 // =13830 movk x17, #0x73fc, lsl #16 - eor x12, x12, x17 + eor x11, x11, x17 mov x17, #0xf929 // =63785 movk x17, #0xe220, lsl #16 - and x13, x5, x17 + and x12, x5, x17 mov x17, #0xa918 // =43288 movk x17, #0xa2a0, lsl #16 - eor x13, x13, x17 + eor x12, x12, x17 mov x17, #0xf9e1 // =63969 movk x17, #0x44a3, lsl #16 - and x14, x5, x17 + and x13, x5, x17 mov x17, #0xbd90 // =48528 movk x17, #0x8222, lsl #16 - eor x14, x14, x17 + eor x13, x13, x17 mov x17, #0x104a // =4170 movk x17, #0x794f, lsl #16 - and x15, x5, x17 + and x14, x5, x17 mov x17, #0xac77 // =44151 movk x17, #0xd6b6, lsl #16 - eor x15, x15, x17 + eor x14, x14, x17 mov x17, #0x320b // =12811 movk x17, #0x26f, lsl #16 - and x20, x5, x17 + and x15, x5, x17 mov x17, #0x300c // =12300 movk x17, #0x3069, lsl #16 - eor x20, x20, x17 + eor x15, x15, x17 mov x17, #0xb01a // =45082 movk x17, #0x7640, lsl #16 - and x21, x5, x17 + and x20, x5, x17 mov x17, #0xd5cc // =54732 movk x17, #0x6ce0, lsl #16 - eor x21, x21, x17 + eor x20, x20, x17 mov x17, #0x1572 // =5490 movk x17, #0x238f, lsl #16 - and x22, x5, x17 + and x21, x5, x17 mov x17, #0xa22d // =41517 movk x17, #0x59a9, lsl #16 - eor x22, x22, x17 + eor x21, x21, x17 mov x17, #0xc083 // =49283 movk x17, #0x7a63, lsl #16 - and x23, x5, x17 + and x22, x5, x17 mov x17, #0xbd4 // =3028 movk x17, #0xac6d, lsl #16 - eor x23, x23, x17 + eor x22, x22, x17 mov x17, #0xa000 // =40960 movk x17, #0x11cc, lsl #16 - and x24, x5, x17 + and x23, x5, x17 mov x17, #0x3200 // =12800 movk x17, #0x21c8, lsl #16 - eor x24, x24, x17 + eor x23, x23, x17 mov x17, #0x69aa // =27050 movk x17, #0x202f, lsl #16 - and x25, x5, x17 + and x24, x5, x17 mov x17, #0x2188 // =8584 movk x17, #0xa0e6, lsl #16 - eor x25, x25, x17 + eor x24, x24, x17 mov x17, #0x3be9 // =15337 movk x17, #0x51b3, lsl #16 - and x26, x5, x17 + and x25, x5, x17 mov x17, #0x655a // =25946 movk x17, #0xaf7d, lsl #16 - eor x26, x26, x17 + eor x25, x25, x17 mov x17, #0xe8ae // =59566 movk x17, #0x3b0f, lsl #16 - and x27, x5, x17 + and x26, x5, x17 mov x17, #0x8aa3 // =35491 movk x17, #0xf016, lsl #16 - eor x27, x27, x17 + eor x26, x26, x17 mov x17, #0x8816 // =34838 movk x17, #0x90bf, lsl #16 - and x28, x5, x17 + and x27, x5, x17 mov x17, #0x30c6 // =12486 movk x17, #0x90aa, lsl #16 - eor x28, x28, x17 + eor x27, x27, x17 mov x17, #0x4f9b // =20379 movk x17, #0x9e3, lsl #16 - and x16, x5, x17 - str x16, [sp, #0xa8] - ldr x16, [sp, #0xa8] + and x28, x5, x17 mov x17, #0x750a // =29962 movk x17, #0x5ab2, lsl #16 - eor x16, x16, x17 - str x16, [sp, #0xa8] + eor x28, x28, x17 mov x17, #0xbe88 // =48776 movk x17, #0x103, lsl #16 and x16, x5, x17 - str x16, [sp, #0xa0] - ldr x16, [sp, #0xa0] + str x16, [sp, #0xa8] + ldr x16, [sp, #0xa8] mov x17, #0xbe65 // =48741 movk x17, #0x5391, lsl #16 eor x16, x16, x17 - str x16, [sp, #0xa0] + str x16, [sp, #0xa8] mov x17, #0x8e25 // =36389 movk x17, #0x49ac, lsl #16 and x16, x5, x17 - str x16, [sp, #0x98] - ldr x16, [sp, #0x98] + str x16, [sp, #0xa0] + ldr x16, [sp, #0xa0] mov x17, #0x2baf // =11183 movk x17, #0x9337, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x98] + str x16, [sp, #0xa0] mov x17, #0x313d // =12605 movk x17, #0x922c, lsl #16 and x16, x5, x17 - str x16, [sp, #0x90] - ldr x16, [sp, #0x90] + str x16, [sp, #0x98] + ldr x16, [sp, #0x98] mov x17, #0x210c // =8460 movk x17, #0xf288, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x90] + str x16, [sp, #0x98] mov x17, #0x31b0 // =12720 movk x17, #0x70ef, lsl #16 and x16, x5, x17 - str x16, [sp, #0x88] - ldr x16, [sp, #0x88] + str x16, [sp, #0x90] + ldr x16, [sp, #0x90] mov x17, #0xf5c0 // =62912 movk x17, #0x920a, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x88] + str x16, [sp, #0x90] mov x17, #0x7100 // =28928 movk x17, #0x6a70, lsl #16 and x16, x5, x17 - str x16, [sp, #0x80] - ldr x16, [sp, #0x80] + str x16, [sp, #0x88] + ldr x16, [sp, #0x88] mov x17, #0x12c0 // =4800 movk x17, #0x63d3, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x80] + str x16, [sp, #0x88] mov x17, #0x9011 // =36881 movk x17, #0xb97c, lsl #16 and x16, x5, x17 - str x16, [sp, #0x78] - ldr x16, [sp, #0x78] + str x16, [sp, #0x80] + ldr x16, [sp, #0x80] mov x17, #0x3006 // =12294 movk x17, #0x537b, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x78] + str x16, [sp, #0x80] mov x17, #0xc959 // =51545 movk x17, #0xa320, lsl #16 and x16, x5, x17 - str x16, [sp, #0x70] - ldr x16, [sp, #0x70] + str x16, [sp, #0x78] + ldr x16, [sp, #0x78] mov x17, #0xb0a5 // =45221 movk x17, #0xa2ef, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x70] + str x16, [sp, #0x78] mov x17, #0xab4a // =43850 movk x17, #0x6ea0, lsl #16 and x16, x5, x17 - str x16, [sp, #0x68] - ldr x16, [sp, #0x68] + str x16, [sp, #0x70] + ldr x16, [sp, #0x70] mov x17, #0x96a5 // =38565 movk x17, #0xbc8f, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x68] + str x16, [sp, #0x70] mov x17, #0xddf8 // =56824 movk x17, #0x6953, lsl #16 and x16, x5, x17 - str x16, [sp, #0x60] - ldr x16, [sp, #0x60] + str x16, [sp, #0x68] + ldr x16, [sp, #0x68] mov x17, #0x76a5 // =30373 movk x17, #0xfad1, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x60] + str x16, [sp, #0x68] mov x17, #0x3e2b // =15915 movk x17, #0xf74f, lsl #16 and x16, x5, x17 - str x16, [sp, #0x58] - ldr x16, [sp, #0x58] + str x16, [sp, #0x60] + ldr x16, [sp, #0x60] mov x17, #0x14a3 // =5283 movk x17, #0x665a, lsl #16 eor x16, x16, x17 - str x16, [sp, #0x58] + str x16, [sp, #0x60] mov x17, #0x6cad // =27821 movk x17, #0xf030, lsl #16 and x5, x5, x17 @@ -317,122 +308,121 @@ Disassembly of section .text: movk x17, #0xf2ef, lsl #16 eor x5, x5, x17 mov w6, w6 - mov w8, w8 - and x8, x2, x8 - eor x6, x6, x8 + mov w7, w7 + and x7, x2, x7 + eor x6, x6, x7 + mov w7, w8 mov w8, w9 - mov w9, w10 + and x8, x2, x8 + eor x7, x7, x8 + mov w8, w10 + mov w9, w11 and x9, x2, x9 eor x8, x8, x9 - mov w9, w11 - mov w10, w12 + mov w9, w12 + mov w10, w13 and x10, x2, x10 eor x9, x9, x10 - mov w10, w13 - mov w11, w14 + mov w10, w14 + mov w11, w15 and x11, x2, x11 eor x10, x10, x11 - mov w11, w15 - mov w12, w20 + mov w11, w20 + mov w12, w21 and x12, x2, x12 eor x11, x11, x12 - mov w12, w21 - mov w13, w22 + mov w12, w22 + mov w13, w23 and x13, x2, x13 eor x12, x12, x13 - mov w13, w23 - mov w14, w24 - and x14, x2, x14 - eor x13, x13, x14 + mov w13, w24 mov w14, w25 mov w15, w26 - mov w20, w27 + and x15, x2, x15 + eor x14, x14, x15 + mov w15, w27 + mov w20, w28 and x20, x2, x20 eor x15, x15, x20 - mov w20, w28 ldr x16, [sp, #0xa8] + mov w20, w16 + ldr x16, [sp, #0xa0] mov w21, w16 and x21, x2, x21 eor x20, x20, x21 - ldr x16, [sp, #0xa0] - mov w21, w16 ldr x16, [sp, #0x98] + mov w21, w16 + ldr x16, [sp, #0x90] mov w22, w16 and x22, x2, x22 eor x21, x21, x22 - ldr x16, [sp, #0x90] - mov w22, w16 ldr x16, [sp, #0x88] + mov w22, w16 + ldr x16, [sp, #0x80] mov w23, w16 and x23, x2, x23 eor x22, x22, x23 - ldr x16, [sp, #0x80] - mov w23, w16 ldr x16, [sp, #0x78] + mov w23, w16 + ldr x16, [sp, #0x70] mov w24, w16 and x24, x2, x24 eor x23, x23, x24 - ldr x16, [sp, #0x70] - mov w24, w16 ldr x16, [sp, #0x68] - mov w25, w16 - and x25, x2, x25 - eor x24, x24, x25 + mov w24, w16 ldr x16, [sp, #0x60] mov w25, w16 - ldr x16, [sp, #0x58] - mov w26, w16 - and x2, x2, x26 - eor x2, x25, x2 + and x2, x2, x25 + eor x2, x24, x2 mov w5, w5 mov w6, w6 - mov w8, w8 - and x8, x3, x8 - eor x6, x6, x8 + mov w7, w7 + and x7, x3, x7 + eor x6, x6, x7 + mov w7, w8 mov w8, w9 - mov w9, w10 + and x8, x3, x8 + eor x7, x7, x8 + mov w8, w10 + mov w9, w11 and x9, x3, x9 eor x8, x8, x9 - mov w9, w11 - mov w10, w12 + mov w9, w12 + mov w10, w13 and x10, x3, x10 eor x9, x9, x10 - mov w10, w13 - mov w11, w14 + mov w10, w14 + mov w11, w15 and x11, x3, x11 eor x10, x10, x11 - mov w11, w15 - mov w12, w20 + mov w11, w20 + mov w12, w21 and x12, x3, x12 eor x11, x11, x12 - mov w12, w21 - mov w13, w22 + mov w12, w22 + mov w13, w23 and x13, x3, x13 eor x12, x12, x13 - mov w13, w23 - mov w14, w24 - and x14, x3, x14 - eor x13, x13, x14 mov w2, w2 mov w5, w5 and x3, x3, x5 eor x2, x2, x3 mov w3, w6 - mov w5, w8 + mov w5, w7 and x5, x4, x5 eor x3, x3, x5 - mov w5, w9 - mov w6, w10 + mov w5, w8 + mov w6, w9 and x6, x4, x6 eor x5, x5, x6 - mov w6, w11 - mov w8, w12 - and x8, x4, x8 - eor x6, x6, x8 - mov w8, w13 + mov w6, w10 + mov w7, w11 + and x7, x4, x7 + eor x6, x6, x7 + mov w7, w12 mov w2, w2 and x2, x4, x2 - eor x2, x8, x2 + eor x2, x7, x2 mov w3, w3 mov w4, w5 and x4, x0, x4 @@ -460,16 +450,11 @@ Disassembly of section .text: mov x17, #0x120 // =288 movk x17, #0x1202, lsl #16 and x1, x1, x17 - mov x3, #0x5 // =5 - sxtw x3, w3 mov w1, w1 - lsl x4, x1, x3 - mov w4, w4 - mov x5, #0x20 // =32 - sub x3, x5, x3 - sxtw x3, w3 - lsr x1, x1, x3 - orr x1, x4, x1 + lsl x3, x1, #5 + mov w3, w3 + lsr x1, x1, #27 + orr x1, x3, x1 orr x1, x2, x1 mov w1, w1 mov w2, w0 @@ -499,15 +484,11 @@ Disassembly of section .text: mov x17, #0x200 // =512 movk x17, #0x2000, lsl #16 and x2, x2, x17 - sxtw x3, w7 mov w2, w2 - lsl x4, x2, x3 - mov w4, w4 - mov x5, #0x20 // =32 - sub x3, x5, x3 - sxtw x3, w3 - lsr x2, x2, x3 - orr x2, x4, x2 + lsl x3, x2, #12 + mov w3, w3 + lsr x2, x2, #20 + orr x2, x3, x2 orr x1, x1, x2 mov w1, w1 mov w2, w0 @@ -537,16 +518,11 @@ Disassembly of section .text: mov x17, #0x1800 // =6144 movk x17, #0x4080, lsl #16 and x2, x2, x17 - mov x3, #0x11 // =17 - sxtw x3, w3 mov w2, w2 - lsl x4, x2, x3 - mov w4, w4 - mov x5, #0x20 // =32 - sub x3, x5, x3 - sxtw x3, w3 - lsr x2, x2, x3 - orr x2, x4, x2 + lsl x3, x2, #17 + mov w3, w3 + lsr x2, x2, #15 + orr x2, x3, x2 orr x1, x1, x2 mov w1, w1 mov w2, w0 @@ -569,16 +545,11 @@ Disassembly of section .text: mov x17, #0x8 // =8 movk x17, #0x8800, lsl #16 and x2, x2, x17 - mov x3, #0x18 // =24 - sxtw x3, w3 mov w2, w2 - lsl x4, x2, x3 - mov w4, w4 - mov x5, #0x20 // =32 - sub x3, x5, x3 - sxtw x3, w3 - lsr x2, x2, x3 - orr x2, x4, x2 + lsl x3, x2, #24 + mov w3, w3 + lsr x2, x2, #8 + orr x2, x3, x2 orr x1, x1, x2 mov w1, w1 mov w0, w0 @@ -593,54 +564,131 @@ Disassembly of section .text: lsr x0, x0, #6 orr x0, x1, x0 mov w0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] + ldp x29, x30, [sp, #0xb0] ldr x28, [sp, #0x40] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - mov x20, #0x0 // =0 - mov x21, #0xa5a5 // =42405 - movk x21, #0xa5a5, lsl #16 - mov x22, x20 - sxtw x0, w20 - cmp x0, #0x10 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 - b - mov w22, w22 - mov w0, w21 + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x0, #0xa5a5 // =42405 + movk x0, #0xa5a5, lsl #16 + adrp x1, + add x1, x1, + bl + mov x17, #0x0 // =0 + eor x0, x0, x17 + mov w20, w0 + mov x0, #0x1ac0 // =6848 + movk x0, #0xd2f5, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0xcf1f // =53023 + movk x0, #0x3849, lsl #16 adrp x1, add x1, x1, bl - eor x22, x22, x0 - mov w0, w21 - mov x17, #0x660d // =26125 - movk x17, #0x19, lsl #16 - mul x0, x0, x17 + eor x0, x20, x0 + mov w20, w0 + mov x0, #0xd1f2 // =53746 + movk x0, #0xbabb, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x8a9 // =2217 + movk x0, #0xe41, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0xb9f4 // =47604 + movk x0, #0xb7b0, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x9cc3 // =40131 + movk x0, #0x2353, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x9b46 // =39750 + movk x0, #0xa72e, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0xb9ed // =47597 + movk x0, #0x7580, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0xd268 // =53864 + movk x0, #0xa631, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x12a7 // =4775 + movk x0, #0x12f4, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x6fda // =28634 + movk x0, #0x4491, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x7d71 // =32113 + movk x0, #0x96ac, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x581c // =22556 + movk x0, #0xdd35, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x94cb // =38091 + movk x0, #0x53fb, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 + mov w20, w0 + mov x0, #0x63ae // =25518 + movk x0, #0x4551, lsl #16 + adrp x1, + add x1, x1, + bl + eor x0, x20, x0 mov w0, w0 - mov x17, #0xf35f // =62303 - movk x17, #0x3c6e, lsl #16 - add x0, x0, x17 - mov w21, w0 - b - mov w0, w22 lsr x1, x0, #8 eor x1, x0, x1 lsr x2, x0, #16 @@ -650,9 +698,6 @@ Disassembly of section .text: mov x17, #0xff // =255 and x0, x0, x17 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.x64.asm b/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.x64.asm index c1efa1168..c2f0d498c 100644 --- a/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.x64.asm +++ b/tests/snapshots/asm/des_ct_fconf_wide_imm_scratch.x64.asm @@ -32,7 +32,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x100, %rsp # imm = 0x100 + subq $0xf0, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -107,12 +107,11 @@ Disassembly of section .text: xorq %rbx, %rdx movl %edx, %edx movl %edi, %edi - movl $0xc, %ebx - movl 0xc(%rsi), %r12d - xorq %r12, %rdi + movl 0xc(%rsi), %ebx + xorq %rbx, %rdi movl %edi, %edi - movl 0x10(%rsi), %r12d - xorq %r12, %rax + movl 0x10(%rsi), %ebx + xorq %rbx, %rax movl %eax, %eax movl %r9d, %r9d movl 0x14(%rsi), %esi @@ -122,236 +121,223 @@ Disassembly of section .text: andq %r8, %r9 movl $0xefa72c4d, %r11d # imm = 0xEFA72C4D xorq %r11, %r9 - movq %r8, %r12 - andq $0x500fb821, %r12 # imm = 0x500FB821 + movq %r8, %rbx + andq $0x500fb821, %rbx # imm = 0x500FB821 movl $0xaeaaedff, %r11d # imm = 0xAEAAEDFF - xorq %r11, %r12 - movq %r8, %r13 - andq $0x40efa809, %r13 # imm = 0x40EFA809 - xorq $0x37396665, %r13 # imm = 0x37396665 - movl $0xa5ec0b28, %r14d # imm = 0xA5EC0B28 - andq %r8, %r14 - xorq $0x68d7b833, %r14 # imm = 0x68D7B833 - movq %r8, %r15 - andq $0x252cf820, %r15 # imm = 0x252CF820 + xorq %r11, %rbx + movq %r8, %r12 + andq $0x40efa809, %r12 # imm = 0x40EFA809 + xorq $0x37396665, %r12 # imm = 0x37396665 + movl $0xa5ec0b28, %r13d # imm = 0xA5EC0B28 + andq %r8, %r13 + xorq $0x68d7b833, %r13 # imm = 0x68D7B833 + movq %r8, %r14 + andq $0x252cf820, %r14 # imm = 0x252CF820 movl $0xc9c755bb, %r11d # imm = 0xC9C755BB - xorq %r11, %r15 - movq %r8, %r10 - andq $0x40205801, %r10 # imm = 0x40205801 - movq %r10, 0xf8(%rsp) - movq 0xf8(%rsp), %r10 - xorq $0x73fc3606, %r10 # imm = 0x73FC3606 - movq %r10, 0xf8(%rsp) + xorq %r11, %r14 + movq %r8, %r15 + andq $0x40205801, %r15 # imm = 0x40205801 + xorq $0x73fc3606, %r15 # imm = 0x73FC3606 movl $0xe220f929, %r10d # imm = 0xE220F929 andq %r8, %r10 - movq %r10, 0xf0(%rsp) - movq 0xf0(%rsp), %r10 - movl $0xa2a0a918, %r11d # imm = 0xA2A0A918 - xorq %r11, %r10 - movq %r10, 0xf0(%rsp) - movq %r8, %r10 - andq $0x44a3f9e1, %r10 # imm = 0x44A3F9E1 movq %r10, 0xe8(%rsp) movq 0xe8(%rsp), %r10 - movl $0x8222bd90, %r11d # imm = 0x8222BD90 + movl $0xa2a0a918, %r11d # imm = 0xA2A0A918 xorq %r11, %r10 movq %r10, 0xe8(%rsp) movq %r8, %r10 - andq $0x794f104a, %r10 # imm = 0x794F104A + andq $0x44a3f9e1, %r10 # imm = 0x44A3F9E1 movq %r10, 0xe0(%rsp) movq 0xe0(%rsp), %r10 - movl $0xd6b6ac77, %r11d # imm = 0xD6B6AC77 + movl $0x8222bd90, %r11d # imm = 0x8222BD90 xorq %r11, %r10 movq %r10, 0xe0(%rsp) movq %r8, %r10 - andq $0x26f320b, %r10 # imm = 0x26F320B + andq $0x794f104a, %r10 # imm = 0x794F104A movq %r10, 0xd8(%rsp) movq 0xd8(%rsp), %r10 - xorq $0x3069300c, %r10 # imm = 0x3069300C + movl $0xd6b6ac77, %r11d # imm = 0xD6B6AC77 + xorq %r11, %r10 movq %r10, 0xd8(%rsp) movq %r8, %r10 - andq $0x7640b01a, %r10 # imm = 0x7640B01A + andq $0x26f320b, %r10 # imm = 0x26F320B movq %r10, 0xd0(%rsp) movq 0xd0(%rsp), %r10 - xorq $0x6ce0d5cc, %r10 # imm = 0x6CE0D5CC + xorq $0x3069300c, %r10 # imm = 0x3069300C movq %r10, 0xd0(%rsp) movq %r8, %r10 - andq $0x238f1572, %r10 # imm = 0x238F1572 + andq $0x7640b01a, %r10 # imm = 0x7640B01A movq %r10, 0xc8(%rsp) movq 0xc8(%rsp), %r10 - xorq $0x59a9a22d, %r10 # imm = 0x59A9A22D + xorq $0x6ce0d5cc, %r10 # imm = 0x6CE0D5CC movq %r10, 0xc8(%rsp) movq %r8, %r10 - andq $0x7a63c083, %r10 # imm = 0x7A63C083 + andq $0x238f1572, %r10 # imm = 0x238F1572 movq %r10, 0xc0(%rsp) movq 0xc0(%rsp), %r10 - movl $0xac6d0bd4, %r11d # imm = 0xAC6D0BD4 - xorq %r11, %r10 + xorq $0x59a9a22d, %r10 # imm = 0x59A9A22D movq %r10, 0xc0(%rsp) movq %r8, %r10 - andq $0x11cca000, %r10 # imm = 0x11CCA000 + andq $0x7a63c083, %r10 # imm = 0x7A63C083 movq %r10, 0xb8(%rsp) movq 0xb8(%rsp), %r10 - xorq $0x21c83200, %r10 # imm = 0x21C83200 + movl $0xac6d0bd4, %r11d # imm = 0xAC6D0BD4 + xorq %r11, %r10 movq %r10, 0xb8(%rsp) movq %r8, %r10 - andq $0x202f69aa, %r10 # imm = 0x202F69AA + andq $0x11cca000, %r10 # imm = 0x11CCA000 movq %r10, 0xb0(%rsp) movq 0xb0(%rsp), %r10 - movl $0xa0e62188, %r11d # imm = 0xA0E62188 - xorq %r11, %r10 + xorq $0x21c83200, %r10 # imm = 0x21C83200 movq %r10, 0xb0(%rsp) movq %r8, %r10 - andq $0x51b33be9, %r10 # imm = 0x51B33BE9 + andq $0x202f69aa, %r10 # imm = 0x202F69AA movq %r10, 0xa8(%rsp) movq 0xa8(%rsp), %r10 - movl $0xaf7d655a, %r11d # imm = 0xAF7D655A + movl $0xa0e62188, %r11d # imm = 0xA0E62188 xorq %r11, %r10 movq %r10, 0xa8(%rsp) movq %r8, %r10 - andq $0x3b0fe8ae, %r10 # imm = 0x3B0FE8AE + andq $0x51b33be9, %r10 # imm = 0x51B33BE9 movq %r10, 0xa0(%rsp) movq 0xa0(%rsp), %r10 - movl $0xf0168aa3, %r11d # imm = 0xF0168AA3 + movl $0xaf7d655a, %r11d # imm = 0xAF7D655A xorq %r11, %r10 movq %r10, 0xa0(%rsp) - movl $0x90bf8816, %r10d # imm = 0x90BF8816 - andq %r8, %r10 + movq %r8, %r10 + andq $0x3b0fe8ae, %r10 # imm = 0x3B0FE8AE movq %r10, 0x98(%rsp) movq 0x98(%rsp), %r10 - movl $0x90aa30c6, %r11d # imm = 0x90AA30C6 + movl $0xf0168aa3, %r11d # imm = 0xF0168AA3 xorq %r11, %r10 movq %r10, 0x98(%rsp) - movq %r8, %r10 - andq $0x9e34f9b, %r10 # imm = 0x9E34F9B + movl $0x90bf8816, %r10d # imm = 0x90BF8816 + andq %r8, %r10 movq %r10, 0x90(%rsp) movq 0x90(%rsp), %r10 - xorq $0x5ab2750a, %r10 # imm = 0x5AB2750A + movl $0x90aa30c6, %r11d # imm = 0x90AA30C6 + xorq %r11, %r10 movq %r10, 0x90(%rsp) movq %r8, %r10 - andq $0x103be88, %r10 # imm = 0x103BE88 + andq $0x9e34f9b, %r10 # imm = 0x9E34F9B movq %r10, 0x88(%rsp) movq 0x88(%rsp), %r10 - xorq $0x5391be65, %r10 # imm = 0x5391BE65 + xorq $0x5ab2750a, %r10 # imm = 0x5AB2750A movq %r10, 0x88(%rsp) movq %r8, %r10 - andq $0x49ac8e25, %r10 # imm = 0x49AC8E25 + andq $0x103be88, %r10 # imm = 0x103BE88 movq %r10, 0x80(%rsp) movq 0x80(%rsp), %r10 - movl $0x93372baf, %r11d # imm = 0x93372BAF - xorq %r11, %r10 + xorq $0x5391be65, %r10 # imm = 0x5391BE65 movq %r10, 0x80(%rsp) - movl $0x922c313d, %r10d # imm = 0x922C313D - andq %r8, %r10 + movq %r8, %r10 + andq $0x49ac8e25, %r10 # imm = 0x49AC8E25 movq %r10, 0x78(%rsp) movq 0x78(%rsp), %r10 - movl $0xf288210c, %r11d # imm = 0xF288210C + movl $0x93372baf, %r11d # imm = 0x93372BAF xorq %r11, %r10 movq %r10, 0x78(%rsp) - movq %r8, %r10 - andq $0x70ef31b0, %r10 # imm = 0x70EF31B0 + movl $0x922c313d, %r10d # imm = 0x922C313D + andq %r8, %r10 movq %r10, 0x70(%rsp) movq 0x70(%rsp), %r10 - movl $0x920af5c0, %r11d # imm = 0x920AF5C0 + movl $0xf288210c, %r11d # imm = 0xF288210C xorq %r11, %r10 movq %r10, 0x70(%rsp) movq %r8, %r10 - andq $0x6a707100, %r10 # imm = 0x6A707100 + andq $0x70ef31b0, %r10 # imm = 0x70EF31B0 movq %r10, 0x68(%rsp) movq 0x68(%rsp), %r10 - xorq $0x63d312c0, %r10 # imm = 0x63D312C0 + movl $0x920af5c0, %r11d # imm = 0x920AF5C0 + xorq %r11, %r10 movq %r10, 0x68(%rsp) - movl $0xb97c9011, %r10d # imm = 0xB97C9011 - andq %r8, %r10 + movq %r8, %r10 + andq $0x6a707100, %r10 # imm = 0x6A707100 movq %r10, 0x60(%rsp) movq 0x60(%rsp), %r10 - xorq $0x537b3006, %r10 # imm = 0x537B3006 + xorq $0x63d312c0, %r10 # imm = 0x63D312C0 movq %r10, 0x60(%rsp) - movl $0xa320c959, %r10d # imm = 0xA320C959 + movl $0xb97c9011, %r10d # imm = 0xB97C9011 andq %r8, %r10 movq %r10, 0x58(%rsp) movq 0x58(%rsp), %r10 - movl $0xa2efb0a5, %r11d # imm = 0xA2EFB0A5 - xorq %r11, %r10 + xorq $0x537b3006, %r10 # imm = 0x537B3006 movq %r10, 0x58(%rsp) - movq %r8, %r10 - andq $0x6ea0ab4a, %r10 # imm = 0x6EA0AB4A + movl $0xa320c959, %r10d # imm = 0xA320C959 + andq %r8, %r10 movq %r10, 0x50(%rsp) movq 0x50(%rsp), %r10 - movl $0xbc8f96a5, %r11d # imm = 0xBC8F96A5 + movl $0xa2efb0a5, %r11d # imm = 0xA2EFB0A5 xorq %r11, %r10 movq %r10, 0x50(%rsp) movq %r8, %r10 - andq $0x6953ddf8, %r10 # imm = 0x6953DDF8 + andq $0x6ea0ab4a, %r10 # imm = 0x6EA0AB4A movq %r10, 0x48(%rsp) movq 0x48(%rsp), %r10 - movl $0xfad176a5, %r11d # imm = 0xFAD176A5 + movl $0xbc8f96a5, %r11d # imm = 0xBC8F96A5 xorq %r11, %r10 movq %r10, 0x48(%rsp) - movl $0xf74f3e2b, %r10d # imm = 0xF74F3E2B - andq %r8, %r10 + movq %r8, %r10 + andq $0x6953ddf8, %r10 # imm = 0x6953DDF8 movq %r10, 0x40(%rsp) movq 0x40(%rsp), %r10 - xorq $0x665a14a3, %r10 # imm = 0x665A14A3 + movl $0xfad176a5, %r11d # imm = 0xFAD176A5 + xorq %r11, %r10 movq %r10, 0x40(%rsp) + movl $0xf74f3e2b, %r10d # imm = 0xF74F3E2B + andq %r8, %r10 + movq %r10, 0x38(%rsp) + movq 0x38(%rsp), %r10 + xorq $0x665a14a3, %r10 # imm = 0x665A14A3 + movq %r10, 0x38(%rsp) movl $0xf0306cad, %r11d # imm = 0xF0306CAD andq %r11, %r8 movl $0xf2eff0cc, %r11d # imm = 0xF2EFF0CC xorq %r11, %r8 movl %r9d, %r9d - movl %r12d, %r12d - andq %rcx, %r12 - xorq %r12, %r9 + movl %ebx, %ebx + andq %rcx, %rbx + xorq %rbx, %r9 + movl %r12d, %ebx movl %r13d, %r12d - movl %r14d, %r13d + andq %rcx, %r12 + xorq %r12, %rbx + movl %r14d, %r12d + movl %r15d, %r13d andq %rcx, %r13 xorq %r13, %r12 - movl %r15d, %r13d - movq 0xf8(%rsp), %r14 + movq 0xe8(%rsp), %r13 + movl %r13d, %r13d + movq 0xe0(%rsp), %r14 movl %r14d, %r14d andq %rcx, %r14 xorq %r14, %r13 - movq 0xf0(%rsp), %r14 + movq 0xd8(%rsp), %r14 movl %r14d, %r14d - movq 0xe8(%rsp), %r15 + movq 0xd0(%rsp), %r15 movl %r15d, %r15d andq %rcx, %r15 xorq %r15, %r14 - movq 0xe0(%rsp), %r15 + movq 0xc8(%rsp), %r15 movl %r15d, %r15d - movq 0xd8(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf8(%rsp) - movq %rcx, %r10 - andq 0xf8(%rsp), %r10 - movq %r10, 0xf8(%rsp) - xorq 0xf8(%rsp), %r15 - movq 0xd0(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf8(%rsp) - movq 0xc8(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf0(%rsp) - movq %rcx, %r10 - andq 0xf0(%rsp), %r10 - movq %r10, 0xf0(%rsp) - movq 0xf8(%rsp), %r10 - xorq 0xf0(%rsp), %r10 - movq %r10, 0xf8(%rsp) movq 0xc0(%rsp), %r10 movl %r10d, %r10d - movq %r10, 0xf0(%rsp) - movq 0xb8(%rsp), %r10 - movl %r10d, %r10d movq %r10, 0xe8(%rsp) movq %rcx, %r10 andq 0xe8(%rsp), %r10 movq %r10, 0xe8(%rsp) - movq 0xf0(%rsp), %r10 - xorq 0xe8(%rsp), %r10 - movq %r10, 0xf0(%rsp) + xorq 0xe8(%rsp), %r15 + movq 0xb8(%rsp), %r10 + movl %r10d, %r10d + movq %r10, 0xe8(%rsp) movq 0xb0(%rsp), %r10 movl %r10d, %r10d + movq %r10, 0xe0(%rsp) + movq %rcx, %r10 + andq 0xe0(%rsp), %r10 + movq %r10, 0xe0(%rsp) + movq 0xe8(%rsp), %r10 + xorq 0xe0(%rsp), %r10 movq %r10, 0xe8(%rsp) movq 0xa8(%rsp), %r10 movl %r10d, %r10d @@ -359,17 +345,8 @@ Disassembly of section .text: movq 0xa0(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xd8(%rsp) - movq %rcx, %r10 - andq 0xd8(%rsp), %r10 - movq %r10, 0xd8(%rsp) - movq 0xe0(%rsp), %r10 - xorq 0xd8(%rsp), %r10 - movq %r10, 0xe0(%rsp) movq 0x98(%rsp), %r10 movl %r10d, %r10d - movq %r10, 0xd8(%rsp) - movq 0x90(%rsp), %r10 - movl %r10d, %r10d movq %r10, 0xd0(%rsp) movq %rcx, %r10 andq 0xd0(%rsp), %r10 @@ -377,10 +354,10 @@ Disassembly of section .text: movq 0xd8(%rsp), %r10 xorq 0xd0(%rsp), %r10 movq %r10, 0xd8(%rsp) - movq 0x88(%rsp), %r10 + movq 0x90(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xd0(%rsp) - movq 0x80(%rsp), %r10 + movq 0x88(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xc8(%rsp) movq %rcx, %r10 @@ -389,10 +366,10 @@ Disassembly of section .text: movq 0xd0(%rsp), %r10 xorq 0xc8(%rsp), %r10 movq %r10, 0xd0(%rsp) - movq 0x78(%rsp), %r10 + movq 0x80(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xc8(%rsp) - movq 0x70(%rsp), %r10 + movq 0x78(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xc0(%rsp) movq %rcx, %r10 @@ -401,10 +378,10 @@ Disassembly of section .text: movq 0xc8(%rsp), %r10 xorq 0xc0(%rsp), %r10 movq %r10, 0xc8(%rsp) - movq 0x68(%rsp), %r10 + movq 0x70(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xc0(%rsp) - movq 0x60(%rsp), %r10 + movq 0x68(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xb8(%rsp) movq %rcx, %r10 @@ -413,10 +390,10 @@ Disassembly of section .text: movq 0xc0(%rsp), %r10 xorq 0xb8(%rsp), %r10 movq %r10, 0xc0(%rsp) - movq 0x58(%rsp), %r10 + movq 0x60(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xb8(%rsp) - movq 0x50(%rsp), %r10 + movq 0x58(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xb0(%rsp) movq %rcx, %r10 @@ -425,91 +402,95 @@ Disassembly of section .text: movq 0xb8(%rsp), %r10 xorq 0xb0(%rsp), %r10 movq %r10, 0xb8(%rsp) + movq 0x50(%rsp), %r10 + movl %r10d, %r10d + movq %r10, 0xb0(%rsp) movq 0x48(%rsp), %r10 movl %r10d, %r10d + movq %r10, 0xa8(%rsp) + movq %rcx, %r10 + andq 0xa8(%rsp), %r10 + movq %r10, 0xa8(%rsp) + movq 0xb0(%rsp), %r10 + xorq 0xa8(%rsp), %r10 movq %r10, 0xb0(%rsp) movq 0x40(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xa8(%rsp) - andq 0xa8(%rsp), %rcx + movq 0x38(%rsp), %r10 + movl %r10d, %r10d + movq %r10, 0xa0(%rsp) + andq 0xa0(%rsp), %rcx movq %rcx, %r10 - movq 0xb0(%rsp), %rcx + movq 0xa8(%rsp), %rcx xorq %r10, %rcx movl %r8d, %r8d movl %r9d, %r9d - movl %r12d, %r12d - andq %rdx, %r12 - xorq %r12, %r9 + movl %ebx, %ebx + andq %rdx, %rbx + xorq %rbx, %r9 + movl %r12d, %ebx movl %r13d, %r12d - movl %r14d, %r13d + andq %rdx, %r12 + xorq %r12, %rbx + movl %r14d, %r12d + movl %r15d, %r13d andq %rdx, %r13 xorq %r13, %r12 - movl %r15d, %r13d - movq 0xf8(%rsp), %r14 + movq 0xe8(%rsp), %r13 + movl %r13d, %r13d + movq 0xe0(%rsp), %r14 movl %r14d, %r14d andq %rdx, %r14 xorq %r14, %r13 - movq 0xf0(%rsp), %r14 + movq 0xd8(%rsp), %r14 movl %r14d, %r14d - movq 0xe8(%rsp), %r15 + movq 0xd0(%rsp), %r15 movl %r15d, %r15d andq %rdx, %r15 xorq %r15, %r14 - movq 0xe0(%rsp), %r15 + movq 0xc8(%rsp), %r15 movl %r15d, %r15d - movq 0xd8(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf8(%rsp) - movq %rdx, %r10 - andq 0xf8(%rsp), %r10 - movq %r10, 0xf8(%rsp) - xorq 0xf8(%rsp), %r15 - movq 0xd0(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf8(%rsp) - movq 0xc8(%rsp), %r10 - movl %r10d, %r10d - movq %r10, 0xf0(%rsp) - movq %rdx, %r10 - andq 0xf0(%rsp), %r10 - movq %r10, 0xf0(%rsp) - movq 0xf8(%rsp), %r10 - xorq 0xf0(%rsp), %r10 - movq %r10, 0xf8(%rsp) movq 0xc0(%rsp), %r10 movl %r10d, %r10d - movq %r10, 0xf0(%rsp) + movq %r10, 0xe8(%rsp) + movq %rdx, %r10 + andq 0xe8(%rsp), %r10 + movq %r10, 0xe8(%rsp) + xorq 0xe8(%rsp), %r15 movq 0xb8(%rsp), %r10 movl %r10d, %r10d movq %r10, 0xe8(%rsp) + movq 0xb0(%rsp), %r10 + movl %r10d, %r10d + movq %r10, 0xe0(%rsp) movq %rdx, %r10 - andq 0xe8(%rsp), %r10 + andq 0xe0(%rsp), %r10 + movq %r10, 0xe0(%rsp) + movq 0xe8(%rsp), %r10 + xorq 0xe0(%rsp), %r10 movq %r10, 0xe8(%rsp) - movq 0xf0(%rsp), %r10 - xorq 0xe8(%rsp), %r10 - movq %r10, 0xf0(%rsp) movl %ecx, %ecx movl %r8d, %r8d andq %r8, %rdx xorq %rdx, %rcx movl %r9d, %edx - movl %r12d, %r8d + movl %ebx, %r8d andq %rdi, %r8 xorq %r8, %rdx - movl %r13d, %r8d - movl %r14d, %r9d + movl %r12d, %r8d + movl %r13d, %r9d andq %rdi, %r9 xorq %r9, %r8 - movl %r15d, %r9d - movq 0xf8(%rsp), %r12 - movl %r12d, %r12d - andq %rdi, %r12 - xorq %r12, %r9 - movq 0xf0(%rsp), %r12 - movl %r12d, %r12d + movl %r14d, %r9d + movl %r15d, %ebx + andq %rdi, %rbx + xorq %rbx, %r9 + movq 0xe8(%rsp), %rbx + movl %ebx, %ebx movl %ecx, %ecx andq %rdi, %rcx - xorq %r12, %rcx + xorq %rbx, %rcx movl %edx, %edx movl %r8d, %edi andq %rax, %rdi @@ -535,25 +516,12 @@ Disassembly of section .text: orq %rsi, %rdx movl %edx, %edx andq $0x12020120, %rcx # imm = 0x12020120 - movl $0x5, %esi - movslq %esi, %rsi movl %ecx, %ecx - movq %rcx, %rdi - pushq %rcx - movq %rsi, %rcx - shlq %cl, %rdi - popq %rcx - movl %edi, %edi - movl $0x20, %r8d - movq %rsi, %r10 - movq %r8, %rsi - subq %r10, %rsi - movslq %esi, %rsi - movq %rcx, %r11 - movq %rsi, %rcx - shrq %cl, %r11 - movq %r11, %rcx - orq %rdi, %rcx + movq %rcx, %rsi + shlq $0x5, %rsi + movl %esi, %esi + shrq $0x1b, %rcx + orq %rsi, %rcx orq %rdx, %rcx movl %ecx, %ecx movl %eax, %edx @@ -581,24 +549,12 @@ Disassembly of section .text: orq %rsi, %rcx movl %ecx, %ecx andq $0x20000200, %rdx # imm = 0x20000200 - movslq %ebx, %rsi movl %edx, %edx - movq %rdx, %rdi - pushq %rcx - movq %rsi, %rcx - shlq %cl, %rdi - popq %rcx - movl %edi, %edi - movl $0x20, %r8d - movq %rsi, %r10 - movq %r8, %rsi - subq %r10, %rsi - movslq %esi, %rsi - pushq %rcx - movq %rsi, %rcx - shrq %cl, %rdx - popq %rcx - orq %rdi, %rdx + movq %rdx, %rsi + shlq $0xc, %rsi + movl %esi, %esi + shrq $0x14, %rdx + orq %rsi, %rdx orq %rdx, %rcx movl %ecx, %ecx movl %eax, %edx @@ -626,25 +582,12 @@ Disassembly of section .text: orq %rsi, %rcx movl %ecx, %ecx andq $0x40801800, %rdx # imm = 0x40801800 - movl $0x11, %esi - movslq %esi, %rsi movl %edx, %edx - movq %rdx, %rdi - pushq %rcx - movq %rsi, %rcx - shlq %cl, %rdi - popq %rcx - movl %edi, %edi - movl $0x20, %r8d - movq %rsi, %r10 - movq %r8, %rsi - subq %r10, %rsi - movslq %esi, %rsi - pushq %rcx - movq %rsi, %rcx - shrq %cl, %rdx - popq %rcx - orq %rdi, %rdx + movq %rdx, %rsi + shlq $0x11, %rsi + movl %esi, %esi + shrq $0xf, %rdx + orq %rsi, %rdx orq %rdx, %rcx movl %ecx, %ecx movl %eax, %edx @@ -666,25 +609,12 @@ Disassembly of section .text: movl %ecx, %ecx movl $0x88000008, %r11d # imm = 0x88000008 andq %r11, %rdx - movl $0x18, %esi - movslq %esi, %rsi movl %edx, %edx - movq %rdx, %rdi - pushq %rcx - movq %rsi, %rcx - shlq %cl, %rdi - popq %rcx - movl %edi, %edi - movl $0x20, %r8d - movq %rsi, %r10 - movq %r8, %rsi - subq %r10, %rsi - movslq %esi, %rsi - pushq %rcx - movq %rsi, %rcx - shrq %cl, %rdx - popq %rcx - orq %rdi, %rdx + movq %rdx, %rsi + shlq $0x18, %rsi + movl %esi, %esi + shrq $0x8, %rdx + orq %rsi, %rdx orq %rdx, %rcx movl %ecx, %ecx movl %eax, %eax @@ -702,39 +632,95 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x100, %rsp # imm = 0x100 + addq $0xf0, %rsp popq %rbp retq
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - xorq %rbx, %rbx - movl $0xa5a5a5a5, %r12d # imm = 0xA5A5A5A5 - movq %rbx, %r13 - movslq %ebx, %rax - cmpq $0x10, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - jmp - movl %r13d, %r13d - movl %r12d, %edi + movl $0xa5a5a5a5, %edi # imm = 0xA5A5A5A5 + leaq , %rsi + callq + xorq $0x0, %rax + movl %eax, %ebx + movl $0xd2f51ac0, %edi # imm = 0xD2F51AC0 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x3849cf1f, %edi # imm = 0x3849CF1F + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xbabbd1f2, %edi # imm = 0xBABBD1F2 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xe4108a9, %edi # imm = 0xE4108A9 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xb7b0b9f4, %edi # imm = 0xB7B0B9F4 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x23539cc3, %edi # imm = 0x23539CC3 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xa72e9b46, %edi # imm = 0xA72E9B46 leaq , %rsi callq - xorq %rax, %r13 - movl %r12d, %eax - imulq $0x19660d, %rax, %rax # imm = 0x19660D + xorq %rbx, %rax + movl %eax, %ebx + movl $0x7580b9ed, %edi # imm = 0x7580B9ED + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xa631d268, %edi # imm = 0xA631D268 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x12f412a7, %edi # imm = 0x12F412A7 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x44916fda, %edi # imm = 0x44916FDA + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x96ac7d71, %edi # imm = 0x96AC7D71 + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0xdd35581c, %edi # imm = 0xDD35581C + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x53fb94cb, %edi # imm = 0x53FB94CB + leaq , %rsi + callq + xorq %rbx, %rax + movl %eax, %ebx + movl $0x455163ae, %edi # imm = 0x455163AE + leaq , %rsi + callq + xorq %rbx, %rax movl %eax, %eax - addq $0x3c6ef35f, %rax # imm = 0x3C6EF35F - movl %eax, %r12d - jmp - movl %r13d, %eax movq %rax, %rcx shrq $0x8, %rcx xorq %rax, %rcx @@ -746,10 +732,7 @@ Disassembly of section .text: andq $0xff, %rax movslq %eax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/designator_override_and_braced_string.aarch64.asm b/tests/snapshots/asm/designator_override_and_braced_string.aarch64.asm index 7e73e7513..b9134d043 100644 --- a/tests/snapshots/asm/designator_override_and_braced_string.aarch64.asm +++ b/tests/snapshots/asm/designator_override_and_braced_string.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x3, #0x0 // =0 ldrb w1, [x0] mov x17, #0x61 // =97 @@ -45,12 +42,10 @@ Disassembly of section .text: cset x2, eq cbz x2, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b b b @@ -58,57 +53,44 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] - adrp x20, - add x20, x20, - ldrsw x0, [x20] - cmp x0, #0x1 - cset x21, ne - cbnz x21, - ldrsw x0, [x20, #0x4] - cmp x0, #0x2 - cset x21, ne - cbz x21, + sub sp, sp, #0x60 + adrp x0, + add x0, x0, + ldrsw x1, [x0] + cmp x1, #0x1 + cset x2, ne + cbnz x2, + ldrsw x1, [x0, #0x4] + cmp x1, #0x2 + cset x2, ne + cbz x2, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x20, #0xc] + ldrb w1, [x0, #0xc] mov x17, #0x4 // =4 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, ne - mov x21, #0x1 // =1 - cbnz x0, - ldrb w0, [x20, #0xd] + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + cset x1, ne + mov x3, #0x1 // =1 + cbnz x1, + ldrb w1, [x0, #0xd] mov x17, #0x6 // =6 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, ne - cmp x0, #0x0 - cset x21, ne - cbnz x21, - ldrb w0, [x20, #0xe] + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + cset x1, ne + cmp x1, #0x0 + cset x3, ne + cbnz x3, + ldrb w0, [x0, #0xe] cmp x0, #0x0 - cset x21, ne - cbz x21, + cset x3, ne + cbz x3, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -119,7 +101,7 @@ Disassembly of section .text: mov w0, w0 cmp x0, #0x0 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, adrp x0, add x0, x0, @@ -130,21 +112,19 @@ Disassembly of section .text: cmp x0, #0x0 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, adrp x0, add x0, x0, ldrb w0, [x0, #0x5] cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 adrp x0, add x0, x0, ldrb w0, [x0] @@ -154,18 +134,16 @@ Disassembly of section .text: cmp x0, #0x0 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, adrp x0, add x0, x0, ldrb w0, [x0, #0x2] cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 @@ -192,7 +170,7 @@ Disassembly of section .text: mov w0, w0 cmp x0, #0x0 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x8 ldrb w0, [x0, #0x4] @@ -202,17 +180,15 @@ Disassembly of section .text: cmp x0, #0x0 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x8 ldrb w0, [x0, #0x5] cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 @@ -237,15 +213,11 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret b @@ -256,3 +228,7 @@ Disassembly of section .text: b b b + mov x0, #0x3 // =3 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/designator_override_and_braced_string.x64.asm b/tests/snapshots/asm/designator_override_and_braced_string.x64.asm index 675563caa..757db6dfe 100644 --- a/tests/snapshots/asm/designator_override_and_braced_string.x64.asm +++ b/tests/snapshots/asm/designator_override_and_braced_string.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rdx, %rdx movsbq (%rdi), %rax cmpq $0x61, %rax @@ -47,12 +44,10 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx + jmp jmp jmp jmp @@ -60,61 +55,48 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - leaq , %rbx - movslq (%rbx), %rax - cmpq $0x1, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + subq $0x60, %rsp + leaq , %rax + movslq (%rax), %rcx + cmpq $0x1, %rcx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne - movslq 0x4(%rbx), %rax - cmpq $0x2, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + movslq 0x4(%rax), %rcx + cmpq $0x2, %rcx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - movsbq 0xc(%rbx), %rax - cmpq $0x4, %rax - setne %al - movzbq %al, %rax - movl $0x1, %r12d - testq %rax, %rax + movsbq 0xc(%rax), %rcx + cmpq $0x4, %rcx + setne %cl + movzbq %cl, %rcx + movl $0x1, %esi + testq %rcx, %rcx jne - movsbq 0xd(%rbx), %rax - cmpq $0x6, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + movsbq 0xd(%rax), %rcx + cmpq $0x6, %rcx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne - movsbq 0xe(%rbx), %rax + movsbq 0xe(%rax), %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq , %rax @@ -122,7 +104,7 @@ Disassembly of section .text: cmpq $0x68, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq , %rax @@ -131,45 +113,41 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq , %rax movsbq 0x5(%rax), %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - movl $0x1, %ebx + movl $0x1, %edx leaq , %rax movsbq (%rax), %rax cmpq $0x68, %rax setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq , %rax movsbq 0x2(%rax), %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x8(%rbp), %rax @@ -193,7 +171,7 @@ Disassembly of section .text: cmpq $0x77, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x8(%rbp), %rax @@ -202,21 +180,19 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x8(%rbp), %rax movsbq 0x5(%rax), %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x6, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x18(%rbp), %rax @@ -240,15 +216,11 @@ Disassembly of section .text: testq %rax, %rax je movl $0x7, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq jmp @@ -259,3 +231,8 @@ Disassembly of section .text: jmp jmp jmp + movl $0x3, %eax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/dev_t_width.aarch64.asm b/tests/snapshots/asm/dev_t_width.aarch64.asm index ab3aca648..ef4575a6f 100644 --- a/tests/snapshots/asm/dev_t_width.aarch64.asm +++ b/tests/snapshots/asm/dev_t_width.aarch64.asm @@ -10,11 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/dev_t_width.x64.asm b/tests/snapshots/asm/dev_t_width.x64.asm index dd904df13..42a327d2b 100644 --- a/tests/snapshots/asm/dev_t_width.x64.asm +++ b/tests/snapshots/asm/dev_t_width.x64.asm @@ -11,11 +11,9 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/directive_in_macro_argument.aarch64.asm b/tests/snapshots/asm/directive_in_macro_argument.aarch64.asm index 0f1475cff..ed2df19c8 100644 --- a/tests/snapshots/asm/directive_in_macro_argument.aarch64.asm +++ b/tests/snapshots/asm/directive_in_macro_argument.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x1, #0x0 // =0 add x1, x1, #0x1 add x1, x1, #0x2 @@ -27,16 +26,14 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/dirent_readdir.aarch64.asm b/tests/snapshots/asm/dirent_readdir.aarch64.asm index 2f350c96f..c9cbd6ef7 100644 --- a/tests/snapshots/asm/dirent_readdir.aarch64.asm +++ b/tests/snapshots/asm/dirent_readdir.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 adrp x0, add x0, x0, bl @@ -24,19 +22,14 @@ Disassembly of section .text: cmp x20, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret mov x21, #0x0 // =0 mov x22, x21 - mov x0, x20 - bl - cmp x0, #0x0 - b.eq + b add x22, x22, #0x1 add x0, x0, #0x13 adrp x1, @@ -45,29 +38,28 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x0 b.ne + mov x21, #0x1 // =1 b mov x0, x20 bl + cmp x0, #0x0 + b.ne + mov x0, x20 + bl sxtw x0, w0 sxtw x0, w22 cmp x0, #0x2 cset x1, gt cbz x1, - b - mov x21, #0x1 // =1 - b sxtw x1, w21 cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x2 // =2 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret + mov x1, #0x2 // =2 b b diff --git a/tests/snapshots/asm/dirent_readdir.x64.asm b/tests/snapshots/asm/dirent_readdir.x64.asm index c7ec558e0..c87329925 100644 --- a/tests/snapshots/asm/dirent_readdir.x64.asm +++ b/tests/snapshots/asm/dirent_readdir.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -27,16 +27,12 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x20, %rsp popq %rbp retq xorq %r12, %r12 movq %r12, %r13 - movq %rbx, %rdi - xorl %eax, %eax - callq - testq %rax, %rax - je + jmp incq %r13 leaq 0x13(%rax), %rdi leaq , %rsi @@ -45,10 +41,16 @@ Disassembly of section .text: movslq %eax, %rax testq %rax, %rax jne + movl $0x1, %r12d jmp movq %rbx, %rdi xorl %eax, %eax callq + testq %rax, %rax + jne + movq %rbx, %rdi + xorl %eax, %eax + callq movslq %eax, %rax movslq %r13d, %rax cmpq $0x2, %rax @@ -56,22 +58,18 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - movl $0x1, %r12d - jmp movslq %r12d, %rcx testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x2, %ecx movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq %rcx, %rax - addq $0x60, %rsp + addq $0x20, %rsp popq %rbp retq + movl $0x2, %ecx jmp jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/divmod_preserves_rdx.aarch64.asm b/tests/snapshots/asm/divmod_preserves_rdx.aarch64.asm index ee3a58ba5..ae4c1e163 100644 --- a/tests/snapshots/asm/divmod_preserves_rdx.aarch64.asm +++ b/tests/snapshots/asm/divmod_preserves_rdx.aarch64.asm @@ -10,41 +10,18 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x19, [sp, #0x10] - mov x0, #0x64 // =100 - mov x1, #0x32 // =50 - mov x2, #0x19 // =25 - mov x3, #0xc // =12 - mov x4, #0x7 // =7 - sdiv x5, x0, x4 - sdiv x6, x1, x4 - sdiv x7, x2, x4 - sdiv x4, x3, x4 - add x5, x5, x6 - add x5, x5, x7 - add x4, x5, x4 - add x0, x4, x0 - add x0, x0, x1 - add x0, x0, x2 - add x0, x0, x3 - sxtw x20, w0 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x1, #0xd4 // =212 adrp x0, add x0, x0, - mov x1, x20 bl sxtw x0, w0 - cmp x20, #0xd4 - b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/divmod_preserves_rdx.x64.asm b/tests/snapshots/asm/divmod_preserves_rdx.x64.asm index c0adc9a40..3674a88ae 100644 --- a/tests/snapshots/asm/divmod_preserves_rdx.x64.asm +++ b/tests/snapshots/asm/divmod_preserves_rdx.x64.asm @@ -13,67 +13,16 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movl $0x64, %eax - movl $0x32, %ecx - movl $0x19, %edx - movl $0xc, %esi - movl $0x7, %edi - pushq %rax - pushq %rdx - cqto - idivq %rdi - movq %rax, %r8 - popq %rdx - popq %rax - pushq %rax - pushq %rdx - movq %rcx, %rax - cqto - idivq %rdi - movq %rax, %r9 - popq %rdx - popq %rax - pushq %rax - pushq %rdx - movq %rdx, %rax - cqto - idivq %rdi - movq %rax, %rbx - popq %rdx - popq %rax - pushq %rax - pushq %rdx - movq %rsi, %rax - cqto - idivq %rdi - movq %rax, %rdi - popq %rdx - popq %rax - addq %r9, %r8 - addq %rbx, %r8 - addq %r8, %rdi - addq %rdi, %rax - addq %rcx, %rax - addq %rdx, %rax - addq %rsi, %rax - movslq %eax, %rbx + movl $0xd4, %esi leaq , %rdi - movq %rbx, %rsi movb $0x0, %al callq movslq %eax, %rax - cmpq $0xd4, %rbx - jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 movq %rcx, %rax - addq $0x70, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/dlopen_atoi.aarch64.asm b/tests/snapshots/asm/dlopen_atoi.aarch64.asm index 36b1294bd..bdac37bf2 100644 --- a/tests/snapshots/asm/dlopen_atoi.aarch64.asm +++ b/tests/snapshots/asm/dlopen_atoi.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x0 // =0 mov x1, #0x2 // =2 bl @@ -23,44 +21,35 @@ Disassembly of section .text: cmp x20, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x1, add x1, x1, mov x0, x20 bl - mov x21, x0 - cmp x21, #0x0 + cmp x0, #0x0 b.ne mov x0, x20 bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - adrp x0, - add x0, x0, - str x0, [sp, #-0x10]! - mov x9, x21 - ldr x0, [sp] + adrp x1, + add x1, x1, + mov x9, x0 + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x21, w0 mov x0, x20 bl sxtw x0, w0 mov x0, x21 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/dlopen_atoi.x64.asm b/tests/snapshots/asm/dlopen_atoi.x64.asm index a596f223a..146426861 100644 --- a/tests/snapshots/asm/dlopen_atoi.x64.asm +++ b/tests/snapshots/asm/dlopen_atoi.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi @@ -26,15 +26,14 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rsi movq %rbx, %rdi xorl %eax, %eax callq - movq %rax, %r12 - testq %r12, %r12 + testq %rax, %rax jne movq %rbx, %rdi xorl %eax, %eax @@ -43,11 +42,10 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi - movq %r12, %rax callq *%rax movslq %eax, %r12 movq %rbx, %rdi @@ -57,6 +55,7 @@ Disassembly of section .text: movq %r12, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/dlopen_strlen.aarch64.asm b/tests/snapshots/asm/dlopen_strlen.aarch64.asm index c3f5435bd..b6bbb03ed 100644 --- a/tests/snapshots/asm/dlopen_strlen.aarch64.asm +++ b/tests/snapshots/asm/dlopen_strlen.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x0 // =0 mov x1, #0x2 // =2 bl @@ -22,13 +21,10 @@ Disassembly of section .text: bl adrp x1, add x1, x1, - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/dlopen_strlen.x64.asm b/tests/snapshots/asm/dlopen_strlen.x64.asm index 3a474c076..2148714a0 100644 --- a/tests/snapshots/asm/dlopen_strlen.x64.asm +++ b/tests/snapshots/asm/dlopen_strlen.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp xorq %rdi, %rdi movl $0x2, %esi xorl %eax, %eax @@ -25,6 +24,6 @@ Disassembly of section .text: leaq , %rdi callq *%rax movslq %eax, %rax - addq $0x20, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/do_while.aarch64.asm b/tests/snapshots/asm/do_while.aarch64.asm index 83cbdf4f7..fa58b6513 100644 --- a/tests/snapshots/asm/do_while.aarch64.asm +++ b/tests/snapshots/asm/do_while.aarch64.asm @@ -10,16 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x1, #0x0 // =0 add x0, x1, #0x1 sxtw x1, w0 cmp x1, #0x5 - b.lt + b.ge + b mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - b diff --git a/tests/snapshots/asm/do_while.x64.asm b/tests/snapshots/asm/do_while.x64.asm index f74be3db7..69db7eb9e 100644 --- a/tests/snapshots/asm/do_while.x64.asm +++ b/tests/snapshots/asm/do_while.x64.asm @@ -11,16 +11,13 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rcx, %rcx leaq 0x1(%rcx), %rax movslq %eax, %rcx cmpq $0x5, %rcx - jl + jge + jmp movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq - jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/do_while_zero_returns.aarch64.asm b/tests/snapshots/asm/do_while_zero_returns.aarch64.asm index 1ed194c95..e2b9e53fe 100644 --- a/tests/snapshots/asm/do_while_zero_returns.aarch64.asm +++ b/tests/snapshots/asm/do_while_zero_returns.aarch64.asm @@ -13,9 +13,6 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x0 b.ge - b - mov x0, #0x0 // =0 - ret mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 @@ -26,36 +23,28 @@ Disassembly of section .text: add x0, x0, #0x1 sxtw x0, w0 ret + mov x0, #0x0 // =0 + ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x0 b.ne - b mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b cmp x0, #0x0 b.le mov x1, #0x1 // =1 - b + mov x0, x1 + ret mov x1, #0xffff // =65535 movk x1, #0xffff, lsl #16 movk x1, #0xffff, lsl #32 movk x1, #0xffff, lsl #48 - mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + b + mov x0, #0x0 // =0 ret + b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/do_while_zero_returns.x64.asm b/tests/snapshots/asm/do_while_zero_returns.x64.asm index fb67d94db..2542b8332 100644 --- a/tests/snapshots/asm/do_while_zero_returns.x64.asm +++ b/tests/snapshots/asm/do_while_zero_returns.x64.asm @@ -14,42 +14,31 @@ Disassembly of section .text: movslq %edi, %rdi testq %rdi, %rdi jge - jmp - xorq %rax, %rax - retq imulq $-0x1, %rdi, %rax movslq %eax, %rax retq leaq 0x1(%rdi), %rax movslq %eax, %rax retq + xorq %rax, %rax + retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi testq %rdi, %rdi jne - jmp xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp - retq - jmp testq %rdi, %rdi jle movl $0x1, %ecx - jmp - movabsq $-0x1, %rcx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq + movabsq $-0x1, %rcx + jmp + xorq %rax, %rax + retq + jmp
: pushq %rbp @@ -93,4 +82,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/double_free.aarch64.asm b/tests/snapshots/asm/double_free.aarch64.asm index 2fc8a7083..33b0f306c 100644 --- a/tests/snapshots/asm/double_free.aarch64.asm +++ b/tests/snapshots/asm/double_free.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x8 // =8 bl mov x20, x0 @@ -25,8 +24,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/double_free.x64.asm b/tests/snapshots/asm/double_free.x64.asm index 76f55a713..c554ec308 100644 --- a/tests/snapshots/asm/double_free.x64.asm +++ b/tests/snapshots/asm/double_free.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x8, %edi xorl %eax, %eax @@ -29,6 +29,6 @@ Disassembly of section .text: movslq %eax, %rax xorq %rax, %rax movq (%rsp), %rbx - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/double_pointers.aarch64.asm b/tests/snapshots/asm/double_pointers.aarch64.asm index 40cc6c72e..abf29191a 100644 --- a/tests/snapshots/asm/double_pointers.aarch64.asm +++ b/tests/snapshots/asm/double_pointers.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x0, #0xa // =10 stur w0, [x29, #-0x8] sub x0, x29, #0x8 @@ -27,20 +26,18 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret ldur x0, [x29, #-0x10] ldrsw x0, [x0] cmp x0, #0x2a b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret mov x0, #0x8 // =8 bl @@ -55,24 +52,21 @@ Disassembly of section .text: cmp x0, #0x7b b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret ldr x0, [x20] ldrsw x0, [x0] cmp x0, #0x7b b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret diff --git a/tests/snapshots/asm/duff_switch_into_loop.aarch64.asm b/tests/snapshots/asm/duff_switch_into_loop.aarch64.asm index ece333320..d18e06d63 100644 --- a/tests/snapshots/asm/duff_switch_into_loop.aarch64.asm +++ b/tests/snapshots/asm/duff_switch_into_loop.aarch64.asm @@ -25,85 +25,67 @@ Disassembly of section .text: mov x17, #0x7 // =7 and x1, x1, x17 sub x0, x1, x0 - cmp x0, #0x4 - b.lt + cmp x0, #0x8 + b.hs b mov x0, #0x0 // =0 ret mov x1, x4 mov x2, x5 b - add x1, x4, #0x1 - add x2, x5, #0x1 - ldrb w0, [x5] - strb w0, [x4] - add x4, x1, #0x1 - add x5, x2, #0x1 - ldrb w0, [x2] - strb w0, [x1] - add x1, x4, #0x1 - add x2, x5, #0x1 - ldrb w0, [x5] - strb w0, [x4] - add x4, x1, #0x1 - add x5, x2, #0x1 - ldrb w0, [x2] - strb w0, [x1] - add x1, x4, #0x1 - add x2, x5, #0x1 - ldrb w0, [x5] - strb w0, [x4] - add x4, x1, #0x1 - add x5, x2, #0x1 - ldrb w0, [x2] - strb w0, [x1] + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 + add x0, x4, #0x1 + add x1, x5, #0x1 + ldrb w2, [x5] + strb w2, [x4] + mov x4, x0 + mov x5, x1 add x1, x4, #0x1 add x2, x5, #0x1 ldrb w0, [x5] strb w0, [x4] b - cmp x0, #0x2 - b.lt - b - cmp x0, #0x6 - b.lt - b - cmp x0, #0x1 - b.lt - b - cmp x0, #0x3 - b.lt - b - cmp x0, #0x0 - b.eq - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 - b.eq - b - cmp x0, #0x5 - b.lt - b - cmp x0, #0x7 - b.lt - b - cmp x0, #0x4 - b.eq - b - cmp x0, #0x5 - b.eq - b - cmp x0, #0x6 - b.eq - b - cmp x0, #0x7 - b.eq - b + adr x17, + ldrsw x16, [x17, x0, lsl #2] + add x17, x17, x16 + br x17 + + udf #0x50 + udf #0x54 + udf #0x58 + udf #0x5c + udf #0x60 + udf #0x64 + udf #0x68 b add x4, x1, #0x1 add x5, x2, #0x1 @@ -116,16 +98,11 @@ Disassembly of section .text: b.gt b b - mov x1, x4 - mov x2, x5 b b - mov x1, x4 - mov x2, x5 b b - mov x1, x4 - mov x2, x5 + b b b b @@ -135,48 +112,38 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x70 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x27 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x28 - sxtw x2, w1 - add x0, x0, x2 + sub x2, x29, #0x28 + add x2, x2, x0 mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - sub x0, x29, #0x50 - sxtw x2, w1 - add x0, x0, x2 - mov x2, #0x0 // =0 - strb w2, [x0] - b + and x3, x0, x17 + strb w3, [x2] + sub x2, x29, #0x50 + add x2, x2, x0 + mov x3, #0x0 // =0 + strb w3, [x2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x27 + b.lt sub x0, x29, #0x50 sub x1, x29, #0x28 mov x2, #0x27 // =39 bl mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x27 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x50 - sxtw x2, w1 - add x0, x0, x2 - ldrb w0, [x0] - sub x2, x29, #0x28 - sxtw x3, w1 - add x2, x2, x3 + sub x2, x29, #0x50 + add x2, x2, x0 ldrb w2, [x2] - cmp x0, x2 - b.eq - b + sub x3, x29, #0x28 + add x3, x3, x0 + ldrb w3, [x3] + cmp x2, x3 + b.ne + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x27 + b.lt mov x0, #0x0 // =0 add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 diff --git a/tests/snapshots/asm/duff_switch_into_loop.x64.asm b/tests/snapshots/asm/duff_switch_into_loop.x64.asm index 9c1b106bd..4d286e146 100644 --- a/tests/snapshots/asm/duff_switch_into_loop.x64.asm +++ b/tests/snapshots/asm/duff_switch_into_loop.x64.asm @@ -29,85 +29,74 @@ Disassembly of section .text: movq %rax, %r10 movq %rcx, %rax subq %r10, %rax - cmpq $0x4, %rax - jl + cmpq $0x8, %rax + jae jmp xorq %rax, %rax retq movq %rdi, %rcx movq %r8, %rdx jmp + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 + leaq 0x1(%rdi), %rax + leaq 0x1(%r8), %rcx + movsbq (%r8), %rdx + movb %dl, (%rdi) + movq %rax, %rdi + movq %rcx, %r8 leaq 0x1(%rdi), %rcx leaq 0x1(%r8), %rdx movsbq (%r8), %rax movb %al, (%rdi) - leaq 0x1(%rcx), %rdi - leaq 0x1(%rdx), %r8 - movsbq (%rdx), %rax - movb %al, (%rcx) - leaq 0x1(%rdi), %rcx - leaq 0x1(%r8), %rdx - movsbq (%r8), %rax - movb %al, (%rdi) - leaq 0x1(%rcx), %rdi - leaq 0x1(%rdx), %r8 - movsbq (%rdx), %rax - movb %al, (%rcx) - leaq 0x1(%rdi), %rcx - leaq 0x1(%r8), %rdx - movsbq (%r8), %rax - movb %al, (%rdi) - leaq 0x1(%rcx), %rdi - leaq 0x1(%rdx), %r8 - movsbq (%rdx), %rax - movb %al, (%rcx) - leaq 0x1(%rdi), %rcx - leaq 0x1(%r8), %rdx - movsbq (%r8), %rax - movb %al, (%rdi) - jmp - cmpq $0x2, %rax - jl - jmp - cmpq $0x6, %rax - jl - jmp - cmpq $0x1, %rax - jl - jmp - cmpq $0x3, %rax - jl - jmp - testq %rax, %rax - je - jmp - cmpq $0x1, %rax - je - jmp - cmpq $0x2, %rax - je - jmp - cmpq $0x3, %rax - je - jmp - cmpq $0x5, %rax - jl - jmp - cmpq $0x7, %rax - jl - jmp - cmpq $0x4, %rax - je - jmp - cmpq $0x5, %rax - je - jmp - cmpq $0x6, %rax - je - jmp - cmpq $0x7, %rax - je jmp + leaq , %r11 # + movslq (%r11,%rax,4), %r10 + addq %r11, %r10 + jmpq *%r10 + pushq %rbp + + decl (%rsi) + addb %al, (%rax) + pushq %rax + addb %al, (%rax) + addb %dl, (%rbp) + addb %al, (%rax) + popq %rdx + addb %al, (%rax) + addb %bl, (%rdi) + addb %al, (%rax) + addb %al, %fs:(%rax) + addb %ch, (%rcx) + addb %al, (%rax) jmp leaq 0x1(%rcx), %rdi leaq 0x1(%rdx), %r8 @@ -120,16 +109,11 @@ Disassembly of section .text: jg jmp jmp - movq %rdi, %rcx - movq %r8, %rdx jmp jmp - movq %rdi, %rcx - movq %r8, %rdx jmp jmp - movq %rdi, %rcx - movq %r8, %rdx + jmp jmp jmp jmp @@ -139,46 +123,37 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x70, %rsp xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x27, %rax - jge jmp - movslq %ecx, %rax + leaq -0x28(%rbp), %rdx + movslq %ecx, %rsi + addq %rax, %rdx + movb %sil, (%rdx) + leaq -0x50(%rbp), %rdx + addq %rax, %rdx + xorq %rsi, %rsi + movb %sil, (%rdx) leaq 0x1(%rax), %rcx - jmp - leaq -0x28(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - movb %dl, (%rax) - leaq -0x50(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - xorq %rdx, %rdx - movb %dl, (%rax) - jmp + movslq %ecx, %rax + cmpq $0x27, %rax + jl leaq -0x50(%rbp), %rdi leaq -0x28(%rbp), %rsi movl $0x27, %edx callq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x27, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0x50(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - movsbq (%rax), %rax - leaq -0x28(%rbp), %rdx - movslq %ecx, %rsi - addq %rsi, %rdx + leaq -0x50(%rbp), %rdx + addq %rax, %rdx movsbq (%rdx), %rdx - cmpq %rdx, %rax - je - jmp + leaq -0x28(%rbp), %rsi + addq %rax, %rsi + movsbq (%rsi), %rsi + cmpq %rsi, %rdx + jne + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x27, %rax + jl xorq %rax, %rax addq $0x70, %rsp popq %rbp @@ -189,4 +164,3 @@ Disassembly of section .text: retq jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/elf_symbol_version_default.aarch64.asm b/tests/snapshots/asm/elf_symbol_version_default.aarch64.asm index f24e19934..cbade9616 100644 --- a/tests/snapshots/asm/elf_symbol_version_default.aarch64.asm +++ b/tests/snapshots/asm/elf_symbol_version_default.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x8 bl sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x8 mov x1, #0x1 // =1 @@ -31,9 +29,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x38 sub x1, x29, #0x8 @@ -42,9 +39,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x38 bl @@ -53,7 +49,6 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret diff --git a/tests/snapshots/asm/empty_macro_arg_and_string_rows.aarch64.asm b/tests/snapshots/asm/empty_macro_arg_and_string_rows.aarch64.asm index a40b624cb..9f4f47749 100644 --- a/tests/snapshots/asm/empty_macro_arg_and_string_rows.aarch64.asm +++ b/tests/snapshots/asm/empty_macro_arg_and_string_rows.aarch64.asm @@ -10,19 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0x10 // =16 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #2 - cmp x0, #0x4 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x0, [x0] @@ -54,8 +41,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -85,8 +70,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -94,15 +77,13 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b b b b + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/empty_macro_arg_and_string_rows.x64.asm b/tests/snapshots/asm/empty_macro_arg_and_string_rows.x64.asm index 2dbd45b66..de71237ad 100644 --- a/tests/snapshots/asm/empty_macro_arg_and_string_rows.x64.asm +++ b/tests/snapshots/asm/empty_macro_arg_and_string_rows.x64.asm @@ -11,19 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0x10, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x2, %rax - cmpq $0x4, %rax - je - movl $0x1, %eax - addq $0x30, %rsp - popq %rbp - retq leaq , %rax movslq (%rax), %rax cmpq $0x1, %rax @@ -61,8 +48,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rax @@ -90,25 +75,20 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movsbq 0x6(%rax), %rax testq %rax, %rax je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp jmp jmp jmp + movl $0x1, %eax + retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/enum_bitfield_unsigned.aarch64.asm b/tests/snapshots/asm/enum_bitfield_unsigned.aarch64.asm index 26838e3c1..ea67976e7 100644 --- a/tests/snapshots/asm/enum_bitfield_unsigned.aarch64.asm +++ b/tests/snapshots/asm/enum_bitfield_unsigned.aarch64.asm @@ -13,40 +13,33 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x5 b.lt - b - mov x0, #0x0 // =0 - ret - mov x0, #0x0 // =0 - ret - mov x0, #0x28 // =40 - ret - mov x0, #0x32 // =50 - ret - mov x0, #0x3c // =60 - ret + cmp x0, #0x6 + b.lt + cmp x0, #0x6 + b.eq mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 ret + mov x0, #0x3c // =60 + ret + cmp x0, #0x5 + b.ne + mov x0, #0x32 // =50 + ret cmp x0, #0x4 b.lt - b - cmp x0, #0x6 - b.lt - b - cmp x0, #0x0 - b.eq - b cmp x0, #0x4 - b.eq - b - cmp x0, #0x5 - b.eq - b - cmp x0, #0x6 - b.eq - b + b.ne + mov x0, #0x28 // =40 + ret + cmp x0, #0x0 + b.ne + mov x0, #0x0 // =0 + ret + mov x0, #0x0 // =0 + ret b
: @@ -54,14 +47,14 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x20 sub x0, x29, #0x8 - mov x1, #0x6 // =6 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x6 // =6 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x8 ldr w0, [x0] @@ -75,14 +68,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 - mov x1, #0x4 // =4 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x4 // =4 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x8 ldr w0, [x0] @@ -96,14 +89,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 - mov x1, #0x2 // =2 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x2 // =2 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x8 ldr w0, [x0] @@ -117,14 +110,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 - mov x1, #0x5 // =5 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x5 // =5 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldr w0, [x0] diff --git a/tests/snapshots/asm/enum_bitfield_unsigned.x64.asm b/tests/snapshots/asm/enum_bitfield_unsigned.x64.asm index 2cad09e38..5395472c2 100644 --- a/tests/snapshots/asm/enum_bitfield_unsigned.x64.asm +++ b/tests/snapshots/asm/enum_bitfield_unsigned.x64.asm @@ -14,37 +14,30 @@ Disassembly of section .text: movslq %edi, %rdi cmpq $0x5, %rdi jl - jmp - xorq %rax, %rax - retq - xorq %rax, %rax - retq - movl $0x28, %eax - retq - movl $0x32, %eax + cmpq $0x6, %rdi + jl + cmpq $0x6, %rdi + je + movabsq $-0x1, %rax retq movl $0x3c, %eax retq - movabsq $-0x1, %rax + cmpq $0x5, %rdi + jne + movl $0x32, %eax retq cmpq $0x4, %rdi jl - jmp - cmpq $0x6, %rdi - jl - jmp - testq %rdi, %rdi - je - jmp cmpq $0x4, %rdi - je - jmp - cmpq $0x5, %rdi - je - jmp - cmpq $0x6, %rdi - je - jmp + jne + movl $0x28, %eax + retq + testq %rdi, %rdi + jne + xorq %rax, %rax + retq + xorq %rax, %rax + retq jmp
: @@ -52,10 +45,9 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x20, %rsp leaq -0x8(%rbp), %rax - movl $0x6, %ecx - movl (%rax), %edx - andq $-0x8, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x8, %rcx + orq $0x6, %rcx movl %ecx, (%rax) leaq -0x8(%rbp), %rax movl (%rax), %eax @@ -68,10 +60,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x8(%rbp), %rax - movl $0x4, %ecx - movl (%rax), %edx - andq $-0x8, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x8, %rcx + orq $0x4, %rcx movl %ecx, (%rax) leaq -0x8(%rbp), %rax movl (%rax), %eax @@ -84,10 +75,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x8(%rbp), %rax - movl $0x2, %ecx - movl (%rax), %edx - andq $-0x8, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x8, %rcx + orq $0x2, %rcx movl %ecx, (%rax) leaq -0x8(%rbp), %rax movl (%rax), %eax @@ -100,10 +90,9 @@ Disassembly of section .text: popq %rbp retq leaq -0x10(%rbp), %rax - movl $0x5, %ecx - movl (%rax), %edx - andq $-0x8, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x8, %rcx + orq $0x5, %rcx movl %ecx, (%rax) leaq -0x10(%rbp), %rax movl (%rax), %eax @@ -151,3 +140,4 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/enum_tag_types.aarch64.asm b/tests/snapshots/asm/enum_tag_types.aarch64.asm index 9fdfb22c2..a59b60b1b 100644 --- a/tests/snapshots/asm/enum_tag_types.aarch64.asm +++ b/tests/snapshots/asm/enum_tag_types.aarch64.asm @@ -15,77 +15,27 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x1 // =1 - cmp x0, #0x1 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - cmp x0, #0x1 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x8 // =8 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x2 // =2 - add x0, x0, #0x64 - sxtw x0, w0 - cmp x0, #0x66 - b.eq mov x0, #0x9 // =9 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0xa // =10 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x2a // =42 - add x0, x0, #0x64 - sxtw x0, w0 - cmp x0, #0x8e - b.eq mov x0, #0xb // =11 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/enum_tag_types.x64.asm b/tests/snapshots/asm/enum_tag_types.x64.asm index af98c7918..627b852e1 100644 --- a/tests/snapshots/asm/enum_tag_types.x64.asm +++ b/tests/snapshots/asm/enum_tag_types.x64.asm @@ -16,78 +16,28 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0x1, %eax - cmpq $0x1, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x1, %eax - cmpq $0x1, %rax - je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x7, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0x8, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x2, %eax - addq $0x64, %rax - movslq %eax, %rax - cmpq $0x66, %rax - je movl $0x9, %eax - addq $0x20, %rsp - popq %rbp retq - jmp movl $0xa, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x2a, %eax - addq $0x64, %rax - movslq %eax, %rax - cmpq $0x8e, %rax - je movl $0xb, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/environ_single_tu.aarch64.asm b/tests/snapshots/asm/environ_single_tu.aarch64.asm index a3eaab306..2d6fc11f7 100644 --- a/tests/snapshots/asm/environ_single_tu.aarch64.asm +++ b/tests/snapshots/asm/environ_single_tu.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, adrp x1, @@ -25,22 +24,19 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr x1, [x0] - ldr x0, [x1] - cbz x0, - b - add x1, x1, #0x8 b sxtw x0, w2 add x2, x0, #0x1 - b + add x1, x1, #0x8 + ldr x0, [x1] + cbnz x0, sxtw x0, w2 cmp x0, #0x0 b.le mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/environ_single_tu.x64.asm b/tests/snapshots/asm/environ_single_tu.x64.asm index 283a639e7..6a7b78c93 100644 --- a/tests/snapshots/asm/environ_single_tu.x64.asm +++ b/tests/snapshots/asm/environ_single_tu.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp leaq , %rdi leaq , %rsi movl $0x1, %edx @@ -23,23 +22,21 @@ Disassembly of section .text: xorq %rdx, %rdx leaq , %rax movq (%rax), %rcx - movq (%rcx), %rax - testq %rax, %rax - je - jmp - addq $0x8, %rcx jmp movslq %edx, %rax leaq 0x1(%rax), %rdx - jmp + addq $0x8, %rcx + movq (%rcx), %rax + testq %rax, %rax + jne movslq %edx, %rax testq %rax, %rax jle xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/errno_socket_constants.aarch64.asm b/tests/snapshots/asm/errno_socket_constants.aarch64.asm index 180eee8f8..3cac232b7 100644 --- a/tests/snapshots/asm/errno_socket_constants.aarch64.asm +++ b/tests/snapshots/asm/errno_socket_constants.aarch64.asm @@ -34,54 +34,40 @@ Disassembly of section .text: ldr x10, [x1, #0x38] str x10, [x0, #0x38] ldr x10, [sp], #0x10 - mov x0, #0x40 // =64 - mov x2, #0x0 // =0 - add x0, x0, x2 - asr x0, x0, #2 - sxtw x1, w2 - sxtw x3, w0 - cmp x1, x3 - b.ge + mov x1, #0x0 // =0 b - sxtw x1, w2 + sub x2, x29, #0x40 + ldrsw x2, [x2, x0, lsl #2] + cmp x2, #0x0 + b.le add x2, x1, #0x1 - b - sub x1, x29, #0x40 sxtw x3, w2 - ldrsw x1, [x1, x3, lsl #2] - cmp x1, #0x0 - b.gt b + sub x4, x29, #0x40 + ldrsw x4, [x4, x0, lsl #2] + sub x5, x29, #0x40 + ldrsw x5, [x5, x2, lsl #2] + cmp x4, x5 + b.eq + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x10 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x10 + b.lt mov x0, #0x0 // =0 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 + mov x0, #0x2 // =2 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - add x1, x2, #0x1 - sxtw x3, w1 - sxtw x1, w3 - sxtw x4, w0 - cmp x1, x4 - b.ge - b - sxtw x1, w3 - add x3, x1, #0x1 - b - sub x1, x29, #0x40 - sxtw x4, w2 - ldrsw x1, [x1, x4, lsl #2] - sub x4, x29, #0x40 - sxtw x5, w3 - ldrsw x4, [x4, x5, lsl #2] - cmp x1, x4 - b.ne - b - b - mov x0, #0x2 // =2 + mov x0, #0x1 // =1 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret b + b diff --git a/tests/snapshots/asm/errno_socket_constants.x64.asm b/tests/snapshots/asm/errno_socket_constants.x64.asm index a66ad4cd6..370c41041 100644 --- a/tests/snapshots/asm/errno_socket_constants.x64.asm +++ b/tests/snapshots/asm/errno_socket_constants.x64.asm @@ -34,55 +34,41 @@ Disassembly of section .text: movq 0x38(%rcx), %rdx movq %rdx, 0x38(%rax) popq %rdx - movl $0x40, %eax - xorq %rdx, %rdx - addq %rdx, %rax - sarq $0x2, %rax - movslq %edx, %rcx - movslq %eax, %rsi - cmpq %rsi, %rcx - jge + xorq %rcx, %rcx jmp - movslq %edx, %rcx + leaq -0x40(%rbp), %rdx + movslq (%rdx,%rax,4), %rdx + testq %rdx, %rdx + jle leaq 0x1(%rcx), %rdx - jmp - leaq -0x40(%rbp), %rcx movslq %edx, %rsi - movslq (%rcx,%rsi,4), %rcx - testq %rcx, %rcx - jg jmp + leaq -0x40(%rbp), %rdi + movslq (%rdi,%rax,4), %rdi + leaq -0x40(%rbp), %r8 + movslq (%r8,%rdx,4), %r8 + cmpq %r8, %rdi + je + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x10, %rdx + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x10, %rax + jl xorq %rax, %rax addq $0x60, %rsp popq %rbp retq - movl $0x1, %eax + movl $0x2, %eax addq $0x60, %rsp popq %rbp retq - leaq 0x1(%rdx), %rcx - movslq %ecx, %rsi - movslq %esi, %rcx - movslq %eax, %rdi - cmpq %rdi, %rcx - jge - jmp - movslq %esi, %rcx - leaq 0x1(%rcx), %rsi - jmp - leaq -0x40(%rbp), %rcx - movslq %edx, %rdi - movslq (%rcx,%rdi,4), %rcx - leaq -0x40(%rbp), %rdi - movslq %esi, %r8 - movslq (%rdi,%r8,4), %rdi - cmpq %rdi, %rcx - jne - jmp - jmp - movl $0x2, %eax + movl $0x1, %eax addq $0x60, %rsp popq %rbp retq jmp - addb %al, 0x41(%rdx) + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/extern_in_function.aarch64.asm b/tests/snapshots/asm/extern_in_function.aarch64.asm index 473a44a60..4a3260928 100644 --- a/tests/snapshots/asm/extern_in_function.aarch64.asm +++ b/tests/snapshots/asm/extern_in_function.aarch64.asm @@ -28,69 +28,13 @@ Disassembly of section .text: ret
: - mov x0, #0xfffb // =65531 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - cmp x0, #0x5 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - mov x0, #0x7 // =7 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - mov x17, #0xfff9 // =65529 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0xc // =12 ret - mov x0, #0x3 // =3 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - mov x17, #0xfffd // =65533 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0xd // =13 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - sxtw x1, w1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - cmp x1, x0 - b.eq mov x0, #0xe // =14 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/extern_in_function.x64.asm b/tests/snapshots/asm/extern_in_function.x64.asm index 0fff6bb8a..05839c6b1 100644 --- a/tests/snapshots/asm/extern_in_function.x64.asm +++ b/tests/snapshots/asm/extern_in_function.x64.asm @@ -21,36 +21,14 @@ Disassembly of section .text: retq
: - movabsq $-0x5, %rax - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq $0x5, %rax - je + xorq %rax, %rax + retq movl $0xb, %eax retq - movl $0x7, %eax - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq $-0x7, %rax - je movl $0xc, %eax retq - movl $0x3, %eax - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq $-0x3, %rax - je movl $0xd, %eax retq - movabsq $-0x1, %rax - imulq $-0x1, %rax, %rcx - movslq %ecx, %rcx - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq %rax, %rcx - je movl $0xe, %eax retq - xorq %rax, %rax - retq addb %al, (%rax) diff --git a/tests/snapshots/asm/extern_incomplete_struct_completion.aarch64.asm b/tests/snapshots/asm/extern_incomplete_struct_completion.aarch64.asm index a486b5507..8cafbf6e0 100644 --- a/tests/snapshots/asm/extern_incomplete_struct_completion.aarch64.asm +++ b/tests/snapshots/asm/extern_incomplete_struct_completion.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldrsw x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x1, add x1, x1, @@ -33,8 +28,6 @@ Disassembly of section .text: cmp x1, #0x7 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x1, add x1, x1, @@ -42,19 +35,13 @@ Disassembly of section .text: cmp x1, #0xb b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x1, add x1, x1, cmp x0, x1 b.ne mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/extern_incomplete_struct_completion.x64.asm b/tests/snapshots/asm/extern_incomplete_struct_completion.x64.asm index feccb35c9..37cd27f7a 100644 --- a/tests/snapshots/asm/extern_incomplete_struct_completion.x64.asm +++ b/tests/snapshots/asm/extern_incomplete_struct_completion.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x3, %rcx @@ -28,36 +25,25 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rcx movslq (%rcx), %rcx cmpq $0x7, %rcx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rcx movslq (%rcx), %rcx cmpq $0xb, %rcx je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rcx cmpq %rcx, %rax jne movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.aarch64.asm b/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.aarch64.asm index 1985dd1b1..03403ca91 100644 --- a/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.aarch64.asm +++ b/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.aarch64.asm @@ -10,15 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x140 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x150]! + stp x22, x23, [sp, #0x10] str x24, [sp, #0x20] str x19, [sp, #0x30] + stp x29, x30, [sp, #0x140] + add x29, sp, #0x140 sub x20, x29, #0x40 mov x21, #0x40 // =64 adrp x22, @@ -41,14 +38,11 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x140] ldr x19, [sp, #0x30] - add sp, sp, #0x140 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x150 ret sub x0, x29, #0xa8 mov x21, #0x0 // =0 @@ -103,30 +97,24 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x140] ldr x19, [sp, #0x30] - add sp, sp, #0x140 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x150 ret cmp x21, #0x0 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x140] ldr x19, [sp, #0x30] - add sp, sp, #0x140 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x150 ret + mov x1, #0x1 // =1 + b b <__c5_sys_fcntl>: diff --git a/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.x64.asm b/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.x64.asm index a9a17c270..9ba1859d9 100644 --- a/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.x64.asm +++ b/tests/snapshots/asm/fcntl_lock_via_cast_fnptr.x64.asm @@ -123,8 +123,6 @@ Disassembly of section .text: testq %r12, %r12 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 @@ -134,6 +132,8 @@ Disassembly of section .text: addq $0x130, %rsp # imm = 0x130 popq %rbp retq + movl $0x1, %ecx + jmp jmp <__c5_sys_fcntl>: diff --git a/tests/snapshots/asm/fd_set_macros.aarch64.asm b/tests/snapshots/asm/fd_set_macros.aarch64.asm index bed540373..b6e69d4a2 100644 --- a/tests/snapshots/asm/fd_set_macros.aarch64.asm +++ b/tests/snapshots/asm/fd_set_macros.aarch64.asm @@ -17,82 +17,50 @@ Disassembly of section .text: sub x0, x29, #0x80 mov x2, #0x0 // =0 b - mov x1, #0x0 // =0 - b - sxtw x1, w2 - cmp x1, #0x80 - b.ge - sxtw x1, w2 add x1, x0, x1 mov x3, #0x0 // =0 strb w3, [x1] add x1, x2, #0x1 sxtw x2, w1 + sxtw x1, w2 + cmp x1, #0x80 + b.lt + mov x1, #0x0 // =0 b - b - sxtw x0, w1 - cmp x0, #0x80 - b.ge - sub x0, x29, #0x80 - sxtw x2, w1 - add x0, x0, x2 + sub x2, x29, #0x80 + add x0, x2, x0 ldrb w0, [x0] cmp x0, #0x0 - b.eq - b - b - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 - ret + b.ne add x0, x1, #0x1 sxtw x1, w0 - b + sxtw x0, w1 + cmp x0, #0x80 + b.lt sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0x1 // =1 orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x80 - mov x1, #0x7 // =7 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0x80 // =128 orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x80 - mov x1, #0x8 // =8 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w1, [x0] + ldrb w1, [x0, #0x1] mov x17, #0x1 // =1 orr x1, x1, x17 - strb w1, [x0] + strb w1, [x0, #0x1] sub x0, x29, #0x80 - mov x1, #0x64 // =100 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w1, [x0] + ldrb w1, [x0, #0xc] mov x17, #0x10 // =16 orr x1, x1, x17 - strb w1, [x0] + strb w1, [x0, #0xc] sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x1 // =1 and x0, x0, x17 @@ -104,11 +72,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x7 // =7 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x80 // =128 and x0, x0, x17 @@ -120,12 +84,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x8 // =8 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0x1] mov x17, #0x1 // =1 and x0, x0, x17 cmp x0, #0x0 @@ -136,12 +95,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x64 // =100 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0xc] mov x17, #0x10 // =16 and x0, x0, x17 cmp x0, #0x0 @@ -152,11 +106,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x1 // =1 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x2 // =2 and x0, x0, x17 @@ -167,12 +117,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x32 // =50 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0x6] mov x17, #0x4 // =4 and x0, x0, x17 cbz x0, @@ -216,11 +161,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x7 // =7 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0xff7f // =65407 movk x17, #0xffff, lsl #16 @@ -229,11 +170,7 @@ Disassembly of section .text: and x2, x1, x17 strb w2, [x0] sub x0, x29, #0x80 - mov x1, #0x7 // =7 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x80 // =128 and x0, x0, x17 @@ -244,10 +181,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x1 // =1 and x0, x0, x17 @@ -259,12 +193,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x8 // =8 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0x1] mov x17, #0x1 // =1 and x0, x0, x17 cmp x0, #0x0 @@ -275,19 +204,13 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0x1 // =1 orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x1 // =1 and x0, x0, x17 @@ -301,39 +224,27 @@ Disassembly of section .text: sub x0, x29, #0x80 mov x2, #0x0 // =0 b - sub x0, x29, #0x80 - mov x1, #0x0 // =0 - add x1, x1, x1 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] - mov x17, #0x1 // =1 - and x0, x0, x17 - cbz x0, - b - sxtw x1, w2 - cmp x1, #0x80 - b.ge - sxtw x1, w2 add x1, x0, x1 mov x3, #0x0 // =0 strb w3, [x1] add x1, x2, #0x1 sxtw x2, w1 - b - b + sxtw x1, w2 + cmp x1, #0x80 + b.lt + sub x0, x29, #0x80 + add x0, x0, #0x0 + ldrb w0, [x0] + mov x17, #0x1 // =1 + and x0, x0, x17 + cbz x0, mov x0, #0x19 // =25 ldr x19, [sp] add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x64 // =100 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0xc] mov x17, #0x10 // =16 and x0, x0, x17 cbz x0, @@ -351,3 +262,17 @@ Disassembly of section .text: add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ldr x19, [sp] + add sp, sp, #0x100 + ldp x29, x30, [sp], #0x10 + ret + b + b + b + b + b + b + b + b + b diff --git a/tests/snapshots/asm/fd_set_macros.x64.asm b/tests/snapshots/asm/fd_set_macros.x64.asm index 538b29572..fb78f3493 100644 --- a/tests/snapshots/asm/fd_set_macros.x64.asm +++ b/tests/snapshots/asm/fd_set_macros.x64.asm @@ -17,77 +17,46 @@ Disassembly of section .text: leaq -0x80(%rbp), %rax xorq %rdx, %rdx jmp - xorq %rcx, %rcx - jmp - movslq %edx, %rcx - cmpq $0x80, %rcx - jge - movslq %edx, %rcx addq %rax, %rcx xorq %rsi, %rsi movb %sil, (%rcx) leaq 0x1(%rdx), %rcx movslq %ecx, %rdx + movslq %edx, %rcx + cmpq $0x80, %rcx + jl + xorq %rcx, %rcx jmp - jmp - movslq %ecx, %rax - cmpq $0x80, %rax - jge - leaq -0x80(%rbp), %rax - movslq %ecx, %rdx + leaq -0x80(%rbp), %rdx addq %rdx, %rax movsbq (%rax), %rax testq %rax, %rax - je - jmp - jmp - movl $0x1, %eax - addq $0xf0, %rsp - popq %rbp - retq + jne leaq 0x1(%rcx), %rax movslq %eax, %rcx - jmp + movslq %ecx, %rax + cmpq $0x80, %rax + jl leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx orq $0x1, %rcx movb %cl, (%rax) leaq -0x80(%rbp), %rax - movl $0x7, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx orq $0x80, %rcx movb %cl, (%rax) leaq -0x80(%rbp), %rax - movl $0x8, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rcx + movzbq 0x1(%rax), %rcx orq $0x1, %rcx - movb %cl, (%rax) + movb %cl, 0x1(%rax) leaq -0x80(%rbp), %rax - movl $0x64, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rcx + movzbq 0xc(%rax), %rcx orq $0x10, %rcx - movb %cl, (%rax) + movb %cl, 0xc(%rax) leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x1, %rax testq %rax, %rax @@ -97,11 +66,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x7, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x80, %rax testq %rax, %rax @@ -111,12 +76,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x8, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0x1(%rax), %rax andq $0x1, %rax testq %rax, %rax jne @@ -125,12 +85,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x64, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0xc(%rax), %rax andq $0x10, %rax testq %rax, %rax jne @@ -139,11 +94,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x1, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x2, %rax testq %rax, %rax @@ -153,12 +104,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x32, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0x6(%rax), %rax andq $0x4, %rax testq %rax, %rax je @@ -195,21 +141,13 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x7, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx movq %rcx, %rdx andq $-0x81, %rdx movb %dl, (%rax) leaq -0x80(%rbp), %rax - movl $0x7, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x80, %rax testq %rax, %rax @@ -219,10 +157,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x1, %rax testq %rax, %rax @@ -232,12 +167,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x8, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0x1(%rax), %rax andq $0x1, %rax testq %rax, %rax jne @@ -246,18 +176,12 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx orq $0x1, %rcx movb %cl, (%rax) leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x1, %rax testq %rax, %rax @@ -269,38 +193,26 @@ Disassembly of section .text: leaq -0x80(%rbp), %rax xorq %rdx, %rdx jmp - leaq -0x80(%rbp), %rax - xorq %rcx, %rcx - addq %rcx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax - andq $0x1, %rax - testq %rax, %rax - je - jmp - movslq %edx, %rcx - cmpq $0x80, %rcx - jge - movslq %edx, %rcx addq %rax, %rcx xorq %rsi, %rsi movb %sil, (%rcx) leaq 0x1(%rdx), %rcx movslq %ecx, %rdx - jmp - jmp + movslq %edx, %rcx + cmpq $0x80, %rcx + jl + leaq -0x80(%rbp), %rax + addq $0x0, %rax + movzbq (%rax), %rax + andq $0x1, %rax + testq %rax, %rax + je movl $0x19, %eax addq $0xf0, %rsp popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x64, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0xc(%rax), %rax andq $0x10, %rax testq %rax, %rax je @@ -316,3 +228,16 @@ Disassembly of section .text: addq $0xf0, %rsp popq %rbp retq + movl $0x1, %eax + addq $0xf0, %rsp + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp diff --git a/tests/snapshots/asm/fib.aarch64.asm b/tests/snapshots/asm/fib.aarch64.asm index 46a62bed8..9b9a62f24 100644 --- a/tests/snapshots/asm/fib.aarch64.asm +++ b/tests/snapshots/asm/fib.aarch64.asm @@ -10,49 +10,38 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, x0 sxtw x20, w20 cmp x20, #0x2 b.ge mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret sub x0, x20, #0x1 - sxtw x0, w0 bl mov x21, x0 sub x0, x20, #0x2 - sxtw x0, w0 bl add x0, x21, x0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 mov x0, #0x14 // =20 bl mov x17, #0x1a6d // =6765 cmp x0, x17 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/fib.x64.asm b/tests/snapshots/asm/fib.x64.asm index 5ac7d77d7..07e4a6bca 100644 --- a/tests/snapshots/asm/fib.x64.asm +++ b/tests/snapshots/asm/fib.x64.asm @@ -26,12 +26,10 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - leaq -0x1(%rbx), %rax - movslq %eax, %rdi + leaq -0x1(%rbx), %rdi callq movq %rax, %r12 - leaq -0x2(%rbx), %rax - movslq %eax, %rdi + leaq -0x2(%rbx), %rdi callq addq %r12, %rax movq (%rsp), %rbx @@ -43,16 +41,15 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x14, %edi callq cmpq $0x1a6d, %rax # imm = 0x1A6D je movl $0x1, %eax - addq $0x10, %rsp popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/file_io.aarch64.asm b/tests/snapshots/asm/file_io.aarch64.asm index 5789ef7a9..9a5c36ba4 100644 --- a/tests/snapshots/asm/file_io.aarch64.asm +++ b/tests/snapshots/asm/file_io.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 adrp x0, add x0, x0, mov x1, #0x0 // =0 @@ -27,12 +25,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret mov x0, #0xa // =10 bl @@ -48,10 +44,8 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x22 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret diff --git a/tests/snapshots/asm/file_io.x64.asm b/tests/snapshots/asm/file_io.x64.asm index 05c7a9ec8..5b1feadb5 100644 --- a/tests/snapshots/asm/file_io.x64.asm +++ b/tests/snapshots/asm/file_io.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -30,7 +30,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq movl $0xa, %edi @@ -53,7 +53,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/flex_array_member_sizing.aarch64.asm b/tests/snapshots/asm/flex_array_member_sizing.aarch64.asm index 8d578cec1..584093252 100644 --- a/tests/snapshots/asm/flex_array_member_sizing.aarch64.asm +++ b/tests/snapshots/asm/flex_array_member_sizing.aarch64.asm @@ -13,21 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - b - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 mov x1, #0x3344 // =13124 movk x1, #0x1122, lsl #16 @@ -70,3 +55,15 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/flex_array_member_sizing.x64.asm b/tests/snapshots/asm/flex_array_member_sizing.x64.asm index 41ae29ae3..7eecf8580 100644 --- a/tests/snapshots/asm/flex_array_member_sizing.x64.asm +++ b/tests/snapshots/asm/flex_array_member_sizing.x64.asm @@ -14,21 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - jmp - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x10, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax movl $0x11223344, %ecx # imm = 0x11223344 movl %ecx, (%rax) @@ -66,4 +51,17 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/flex_array_member_static_init.aarch64.asm b/tests/snapshots/asm/flex_array_member_static_init.aarch64.asm index 7446f5e60..500f9547d 100644 --- a/tests/snapshots/asm/flex_array_member_static_init.aarch64.asm +++ b/tests/snapshots/asm/flex_array_member_static_init.aarch64.asm @@ -37,36 +37,24 @@ Disassembly of section .text: str x10, [x1] ldr x10, [sp], #0x10 mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, #0x8 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - add x1, x0, #0x18 - sxtw x3, w2 - add x1, x1, x3 - ldrb w1, [x1] - sub x3, x29, #0x8 - sxtw x4, w2 - add x3, x3, x4 + add x3, x0, #0x18 + add x3, x3, x1 ldrb w3, [x3] - cmp x1, x3 - b.eq - b + sub x4, x29, #0x8 + add x4, x4, x1 + ldrb w4, [x4] + cmp x3, x4 + b.ne + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, #0x8 + b.lt adrp x0, add x0, x0, ldrsw x0, [x0] cmp x0, #0x5 b.eq - b - add x0, x2, #0xa - sxtw x0, w0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b mov x0, #0x14 // =20 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 @@ -74,24 +62,20 @@ Disassembly of section .text: adrp x0, add x0, x0, mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, #0x6 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - adrp x1, - add x1, x1, - add x1, x1, #0x4 - sxtw x3, w2 - add x1, x1, x3 - ldrb w1, [x1] - add x3, x0, x3 + adrp x3, + add x3, x3, + add x3, x3, #0x4 + add x3, x3, x1 ldrb w3, [x3] - cmp x1, x3 - b.eq - b + add x4, x0, x1 + ldrb w4, [x4] + cmp x3, x4 + b.ne + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, #0x6 + b.lt adrp x0, add x0, x0, ldrsw x0, [x0] @@ -99,18 +83,23 @@ Disassembly of section .text: movk x17, #0x1234, lsl #16 cmp x0, x17 b.eq - b - add x0, x2, #0x1e - sxtw x0, w0 + mov x0, #0x28 // =40 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x28 // =40 + mov x0, #0x0 // =0 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + add x0, x2, #0x1e + sxtw x0, w0 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + add x0, x2, #0xa + sxtw x0, w0 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + b + b diff --git a/tests/snapshots/asm/flex_array_member_static_init.x64.asm b/tests/snapshots/asm/flex_array_member_static_init.x64.asm index 059aa9692..0b5d6d520 100644 --- a/tests/snapshots/asm/flex_array_member_static_init.x64.asm +++ b/tests/snapshots/asm/flex_array_member_static_init.x64.asm @@ -36,74 +36,65 @@ Disassembly of section .text: movq %rax, (%rcx) popq %rax xorq %rdx, %rdx - movslq %edx, %rcx - cmpq $0x8, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx jmp - leaq 0x18(%rax), %rcx - movslq %edx, %rsi - addq %rsi, %rcx - movsbq (%rcx), %rcx - leaq -0x8(%rbp), %rsi - movslq %edx, %rdi - addq %rdi, %rsi + leaq 0x18(%rax), %rsi + addq %rcx, %rsi movsbq (%rsi), %rsi - cmpq %rsi, %rcx - je - jmp + leaq -0x8(%rbp), %rdi + addq %rcx, %rdi + movsbq (%rdi), %rdi + cmpq %rdi, %rsi + jne + leaq 0x1(%rcx), %rdx + movslq %edx, %rcx + cmpq $0x8, %rcx + jl leaq , %rax movslq (%rax), %rax cmpq $0x5, %rax je - jmp - leaq 0xa(%rdx), %rax - movslq %eax, %rax - addq $0x20, %rsp - popq %rbp - retq - jmp movl $0x14, %eax addq $0x20, %rsp popq %rbp retq leaq , %rax xorq %rdx, %rdx - movslq %edx, %rcx - cmpq $0x6, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx jmp - leaq , %rcx - addq $0x4, %rcx - movslq %edx, %rsi - addq %rsi, %rcx - movsbq (%rcx), %rcx - addq %rax, %rsi + leaq , %rsi + addq $0x4, %rsi + addq %rcx, %rsi movsbq (%rsi), %rsi - cmpq %rsi, %rcx - je - jmp + leaq (%rax,%rcx), %rdi + movsbq (%rdi), %rdi + cmpq %rdi, %rsi + jne + leaq 0x1(%rcx), %rdx + movslq %edx, %rcx + cmpq $0x6, %rcx + jl leaq , %rax movslq (%rax), %rax cmpq $0x12345678, %rax # imm = 0x12345678 je - jmp - leaq 0x1e(%rdx), %rax - movslq %eax, %rax + movl $0x28, %eax addq $0x20, %rsp popq %rbp retq - jmp - movl $0x28, %eax + xorq %rax, %rax addq $0x20, %rsp popq %rbp retq - xorq %rax, %rax + leaq 0x1e(%rdx), %rax + movslq %eax, %rax addq $0x20, %rsp popq %rbp retq + leaq 0xa(%rdx), %rax + movslq %eax, %rax + addq $0x20, %rsp + popq %rbp + retq + jmp + jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/flexible_array_member.aarch64.asm b/tests/snapshots/asm/flexible_array_member.aarch64.asm index 6180feed2..e5946dbca 100644 --- a/tests/snapshots/asm/flexible_array_member.aarch64.asm +++ b/tests/snapshots/asm/flexible_array_member.aarch64.asm @@ -13,16 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x60 - b - mov x0, #0x1 // =1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x50 mov x1, #0x2 // =2 str w1, [x0] @@ -69,3 +59,11 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/flexible_array_member.x64.asm b/tests/snapshots/asm/flexible_array_member.x64.asm index ba2e6ac07..6005eb6bb 100644 --- a/tests/snapshots/asm/flexible_array_member.x64.asm +++ b/tests/snapshots/asm/flexible_array_member.x64.asm @@ -14,16 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x60, %rsp - jmp - movl $0x1, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x60, %rsp - popq %rbp - retq leaq -0x50(%rbp), %rax movl $0x2, %ecx movl %ecx, (%rax) @@ -66,4 +56,12 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x60, %rsp + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/float_arg_single_precision.aarch64.asm b/tests/snapshots/asm/float_arg_single_precision.aarch64.asm index ace4c234e..49694ba86 100644 --- a/tests/snapshots/asm/float_arg_single_precision.aarch64.asm +++ b/tests/snapshots/asm/float_arg_single_precision.aarch64.asm @@ -10,106 +10,70 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fmul s0, s0, s1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fadd s0, s0, s1 fadd s0, s0, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x3fd8000000000000 // =4600427019358961664 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + mov x1, #0x3e800000 // =1048576000 + fmov s16, w0 + fmov s17, w1 + fmul s0, s16, s17 + mov x0, #0x3ec00000 // =1052770304 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x4024000000000000 // =4621819117588971520 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fneg s0, s16 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x41200000 // =1092616192 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x0 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 - mov x0, #0x3fec000000000000 // =4606056518893174784 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + mov x2, #0x3e000000 // =1040187392 + fmov s16, w0 + fmov s17, w1 + fadd s0, s16, s17 + fmov s17, w2 + fadd s0, s0, s17 + mov x0, #0x3f600000 // =1063256064 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - mov x1, #0x4020000000000000 // =4620693217682128896 - fmov d16, x0 - fmov d17, x1 - fdiv d0, d16, d17 - fcvt s0, d0 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x41000000 // =1090519040 + fmov s16, w0 + fmov s17, w1 + fdiv s0, s16, s17 + mov x0, #0x41800000 // =1098907648 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/float_arg_single_precision.x64.asm b/tests/snapshots/asm/float_arg_single_precision.x64.asm index 6dc7462b9..a0d05de1a 100644 --- a/tests/snapshots/asm/float_arg_single_precision.x64.asm +++ b/tests/snapshots/asm/float_arg_single_precision.x64.asm @@ -11,39 +11,23 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp mulss %xmm1, %xmm0 - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp addss %xmm1, %xmm0 addss %xmm2, %xmm0 - addq $0x20, %rsp - popq %rbp retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x3fd8000000000000, %rax # imm = 0x3FD8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + mulss %xmm15, %xmm0 + movl $0x3ec00000, %eax # imm = 0x3EC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -52,26 +36,21 @@ Disassembly of section .text: testq %rax, %rax je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -80,24 +59,18 @@ Disassembly of section .text: testq %rax, %rax je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x3fc0000000000000, %rax # imm = 0x3FC0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 - movabsq $0x3fec000000000000, %rax # imm = 0x3FEC000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movl $0x3e000000, %edx # imm = 0x3E000000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 + movl $0x3f600000, %eax # imm = 0x3F600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -106,23 +79,18 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movabsq $0x4020000000000000, %rcx # imm = 0x4020000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x41000000, %ecx # imm = 0x41000000 movq %rcx, %xmm15 movq %rax, %xmm0 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + divss %xmm15, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -131,10 +99,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm b/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm index faed97e86..1264783d2 100644 --- a/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm +++ b/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm @@ -10,44 +10,32 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr s0, [x0] - mov x1, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + mov x1, #0x40000000 // =1073741824 + fmov s17, w1 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr s0, [x0, #0x4] - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x1, #0x40200000 // =1075838976 + fmov s16, w1 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr s0, [x0, #0x8] - mov x0, #0x4028000000000000 // =4622945017495814144 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41400000 // =1094713344 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -72,8 +60,6 @@ Disassembly of section .text: cset x1, gt cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -85,11 +71,7 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/float_arith_in_static_init.x64.asm b/tests/snapshots/asm/float_arith_in_static_init.x64.asm index d58817a1d..2a56a7faf 100644 --- a/tests/snapshots/asm/float_arith_in_static_init.x64.asm +++ b/tests/snapshots/asm/float_arith_in_static_init.x64.asm @@ -11,15 +11,11 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %ecx # imm = 0x40000000 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -28,17 +24,14 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rcx # imm = 0x4004000000000000 + movl $0x40200000, %ecx # imm = 0x40200000 movq %rcx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -47,14 +40,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq movss 0x8(%rax,%riz), %xmm0 - movabsq $0x4028000000000000, %rax # imm = 0x4028000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41400000, %eax # imm = 0x41400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -63,8 +53,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -88,8 +76,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movsd 0x8(%rax,%riz), %xmm0 @@ -107,11 +93,8 @@ Disassembly of section .text: testq %rax, %rax je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_condition_negative_zero.aarch64.asm b/tests/snapshots/asm/float_condition_negative_zero.aarch64.asm index 0fb0a2ab4..94e0ba169 100644 --- a/tests/snapshots/asm/float_condition_negative_zero.aarch64.asm +++ b/tests/snapshots/asm/float_condition_negative_zero.aarch64.asm @@ -10,124 +10,107 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str d8, [sp] - str x20, [sp, #0x10] - str x21, [sp, #0x18] - str x19, [sp, #0x20] - mov x20, #0x0 // =0 - fmov d16, x20 - fneg d8, d16 - fmov d16, x20 + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 + mov x1, #0x0 // =0 + fmov d16, x1 + fneg d0, d16 + fmov d16, x1 sub x17, x29, #0x10 str d16, [x17] - fmov d17, x20 - fcmp d8, d17 + fmov d17, x1 + fcmp d0, d17 cset x0, ne cbz x0, - mov x17, #0x1 // =1 - orr x20, x20, x17 + mov x1, #0x1 // =1 sub x16, x29, #0x10 - ldr d0, [x16] - fcmp d0, d8 + ldr d1, [x16] + fcmp d1, d0 cset x0, eq cmp x0, #0x0 b.ne mov x17, #0x2 // =2 - orr x20, x20, x17 - mov x21, #0x0 // =0 + orr x1, x1, x17 + mov x2, #0x0 // =0 + b + add x2, x2, #0x1 + sxtw x0, w2 + cmp x0, #0x2 + b.gt mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ne - cbz x0, - add x21, x21, #0x1 - sxtw x0, w21 - cmp x0, #0x2 - b.le - b - sxtw x0, w21 + cbnz x0, + sxtw x0, w2 cmp x0, #0x0 b.eq - b - b - b mov x17, #0x4 // =4 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ne cbz x0, - b - b mov x17, #0x8 // =8 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ne cbz x0, - mov x1, #0x1 // =1 - b - mov x1, #0x0 // =0 - sxtw x0, w1 + mov x2, #0x1 // =1 + sxtw x0, w2 cmp x0, #0x0 b.eq mov x17, #0x10 // =16 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 - cset x21, ne - cbz x21, - mov x21, #0x1 // =1 - cbz x21, + fcmp d0, d17 + cset x2, ne + cbz x2, + mov x2, #0x1 // =1 + cbz x2, mov x17, #0x20 // =32 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 - cset x21, ne - cbnz x21, - mov x21, #0x0 // =0 - cbz x21, + fcmp d0, d17 + cset x2, ne + cbnz x2, + mov x2, #0x0 // =0 + cbz x2, mov x17, #0x40 // =64 - orr x20, x20, x17 - sxtw x0, w20 + orr x1, x1, x17 + sxtw x0, w1 cbz x0, adrp x0, add x0, x0, - sxtw x1, w20 + sxtw x1, w1 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret b b b b b + mov x2, #0x0 // =0 + b + b b b b diff --git a/tests/snapshots/asm/float_condition_negative_zero.x64.asm b/tests/snapshots/asm/float_condition_negative_zero.x64.asm index 6c7a92939..7c511cbef 100644 --- a/tests/snapshots/asm/float_condition_negative_zero.x64.asm +++ b/tests/snapshots/asm/float_condition_negative_zero.x64.asm @@ -13,20 +13,16 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - xorq %rbx, %rbx - movq %rbx, %xmm14 + subq $0x50, %rsp + xorq %rcx, %rcx + movq %rcx, %xmm0 movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm14 - movsd %xmm14, 0x18(%rsp) - movq %rbx, %xmm14 + xorpd %xmm15, %xmm0 + movq %rcx, %xmm14 movsd %xmm14, -0x10(%rbp,%riz) - movsd 0x18(%rsp), %xmm14 - movq %rbx, %xmm15 - ucomisd %xmm15, %xmm14 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -34,10 +30,9 @@ Disassembly of section .text: orq %r10, %rax testq %rax, %rax je - orq $0x1, %rbx - movsd -0x10(%rbp,%riz), %xmm0 - movsd 0x18(%rsp), %xmm15 - ucomisd %xmm15, %xmm0 + movl $0x1, %ecx + movsd -0x10(%rbp,%riz), %xmm1 + ucomisd %xmm0, %xmm1 sete %al movzbq %al, %rax setnp %r10b @@ -45,35 +40,30 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax jne - orq $0x2, %rbx - xorq %r12, %r12 + orq $0x2, %rcx + xorq %rdx, %rdx + jmp + incq %rdx + movslq %edx, %rax + cmpq $0x2, %rax + jg xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - je - incq %r12 - movslq %r12d, %rax - cmpq $0x2, %rax - jle - jmp - movslq %r12d, %rax + jne + movslq %edx, %rax testq %rax, %rax je - jmp - jmp - jmp - orq $0x4, %rbx + orq $0x4, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -81,13 +71,10 @@ Disassembly of section .text: orq %r10, %rax testq %rax, %rax je - jmp - jmp - orq $0x8, %rbx + orq $0x8, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -95,55 +82,49 @@ Disassembly of section .text: orq %r10, %rax testq %rax, %rax je - movl $0x1, %ecx - jmp - xorq %rcx, %rcx - movslq %ecx, %rax + movl $0x1, %edx + movslq %edx, %rax testq %rax, %rax je - orq $0x10, %rbx + orq $0x10, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 - setne %r12b - movzbq %r12b, %r12 + ucomisd %xmm15, %xmm0 + setne %dl + movzbq %dl, %rdx setp %r10b movzbq %r10b, %r10 - orq %r10, %r12 - testq %r12, %r12 + orq %r10, %rdx + testq %rdx, %rdx je - movl $0x1, %r12d - testq %r12, %r12 + movl $0x1, %edx + testq %rdx, %rdx je - orq $0x20, %rbx + orq $0x20, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 - setne %r12b - movzbq %r12b, %r12 + ucomisd %xmm15, %xmm0 + setne %dl + movzbq %dl, %rdx setp %r10b movzbq %r10b, %r10 - orq %r10, %r12 - testq %r12, %r12 + orq %r10, %rdx + testq %rdx, %rdx jne - xorq %r12, %r12 - testq %r12, %r12 + xorq %rdx, %rdx + testq %rdx, %rdx je - orq $0x40, %rbx - movslq %ebx, %rax + orq $0x40, %rcx + movslq %ecx, %rax testq %rax, %rax je leaq , %rdi - movslq %ebx, %rsi + movslq %ecx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x50, %rsp popq %rbp retq leaq , %rdi @@ -151,9 +132,7 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp + addq $0x50, %rsp popq %rbp retq jmp @@ -161,9 +140,11 @@ Disassembly of section .text: jmp jmp jmp + xorq %rdx, %rdx + jmp + jmp jmp jmp jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_double_mix.aarch64.asm b/tests/snapshots/asm/float_double_mix.aarch64.asm index 2e012e56b..0bdea6f8b 100644 --- a/tests/snapshots/asm/float_double_mix.aarch64.asm +++ b/tests/snapshots/asm/float_double_mix.aarch64.asm @@ -13,12 +13,11 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3fb9, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x0, #0x999a // =39322 movk x0, #0x9999, lsl #16 movk x0, #0x9999, lsl #32 @@ -26,6 +25,8 @@ Disassembly of section .text: fmov d16, x0 sub x17, x29, #0x10 str d16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] sub x16, x29, #0x10 ldr d1, [x16] fcvt d0, s0 @@ -64,12 +65,13 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3fb9, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] fcvt d0, s0 mov x0, #0xa0000000 // =2684354560 movk x0, #0x9999, lsl #32 @@ -114,12 +116,13 @@ Disassembly of section .text: sub x16, x29, #0x8 ldr d0, [x16] fcvt s0, d0 - mov x0, #0xe659 // =58969 - movk x0, #0x3b84, lsl #16 - movk x0, #0x9add, lsl #32 - movk x0, #0x3fbf, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0xd6ea // =55018 + movk x0, #0x3dfc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s1, [x16] fsub s2, s0, s1 mov x0, #0x0 // =0 scvtf d1, x0 @@ -128,13 +131,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s2, s2 - mov x0, #0x8c3a // =35898 - movk x0, #0xe230, lsl #16 - movk x0, #0x798e, lsl #32 - movk x0, #0x3e45, lsl #48 - fcvt d1, s2 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0xcc77 // =52343 + movk x0, #0x322b, lsl #16 + fmov s17, w0 + fcmp s2, s17 cset x0, gt cbz x0, mov x0, #0x3 // =3 @@ -180,12 +180,13 @@ Disassembly of section .text: fmov d17, x1 fdiv d0, d16, d17 fcvt s0, d0 - mov x0, #0x7c87 // =31879 - movk x0, #0x5fb6, lsl #16 - movk x0, #0x5555, lsl #32 - movk x0, #0x3fd5, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0xaaab // =43691 + movk x0, #0x3eaa, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s1, [x16] fsub s1, s0, s1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -194,13 +195,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0xaf48 // =44872 - movk x0, #0x9abc, lsl #16 - movk x0, #0xd7f2, lsl #32 - movk x0, #0x3e7a, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xbf95 // =49045 + movk x0, #0x33d6, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x5 // =5 diff --git a/tests/snapshots/asm/float_double_mix.x64.asm b/tests/snapshots/asm/float_double_mix.x64.asm index 70efaa1e9..0445e0fd6 100644 --- a/tests/snapshots/asm/float_double_mix.x64.asm +++ b/tests/snapshots/asm/float_double_mix.x64.asm @@ -14,12 +14,13 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) movabsq $0x3fc999999999999a, %rax # imm = 0x3FC999999999999A movq %rax, %xmm14 movsd %xmm14, -0x10(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 movsd -0x10(%rbp,%riz), %xmm1 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 @@ -61,9 +62,10 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 movq %rax, %xmm15 @@ -108,9 +110,10 @@ Disassembly of section .text: movsd %xmm14, -0x8(%rbp,%riz) movsd -0x8(%rbp,%riz), %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fbf9add3b84e659, %rax # imm = 0x3FBF9ADD3B84E659 + movl $0x3dfcd6ea, %eax # imm = 0x3DFCD6EA movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm1 movapd %xmm0, %xmm2 subss %xmm1, %xmm2 xorq %rax, %rax @@ -127,10 +130,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm2 - movabsq $0x3e45798ee2308c3a, %rax # imm = 0x3E45798EE2308C3A - cvtss2sd %xmm2, %xmm1 + movl $0x322bcc77, %eax # imm = 0x322BCC77 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm2 seta %al movzbq %al, %rax testq %rax, %rax @@ -188,9 +190,10 @@ Disassembly of section .text: movq %rax, %xmm0 divsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd555555fb67c87, %rax # imm = 0x3FD555555FB67C87 + movl $0x3eaaaaab, %eax # imm = 0x3EAAAAAB movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm1 movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subss %xmm15, %xmm1 @@ -208,10 +211,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3e7ad7f29abcaf48, %rax # imm = 0x3E7AD7F29ABCAF48 - cvtss2sd %xmm1, %xmm0 + movl $0x33d6bf95, %eax # imm = 0x33D6BF95 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax diff --git a/tests/snapshots/asm/float_global_init.aarch64.asm b/tests/snapshots/asm/float_global_init.aarch64.asm index b812597e8..11616b67f 100644 --- a/tests/snapshots/asm/float_global_init.aarch64.asm +++ b/tests/snapshots/asm/float_global_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d0, d0, d1 mov x0, #0xa9fc // =43516 movk x0, #0xd2f1, lsl #16 @@ -34,8 +31,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x2, ne mov x0, x2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/float_global_init.x64.asm b/tests/snapshots/asm/float_global_init.x64.asm index c1912c811..b93a1dd29 100644 --- a/tests/snapshots/asm/float_global_init.x64.asm +++ b/tests/snapshots/asm/float_global_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp subsd %xmm1, %xmm0 movabsq $0x3f50624dd2f1a9fc, %rax # imm = 0x3F50624DD2F1A9FC movq %rax, %xmm15 @@ -38,8 +35,6 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -134,4 +129,3 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_increment_decrement.aarch64.asm b/tests/snapshots/asm/float_increment_decrement.aarch64.asm index 10bb7e4dd..3675b1c54 100644 --- a/tests/snapshots/asm/float_increment_decrement.aarch64.asm +++ b/tests/snapshots/asm/float_increment_decrement.aarch64.asm @@ -13,61 +13,57 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0xb0 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 sub x17, x29, #0x8 - str s0, [x17] - sub x1, x29, #0x8 - ldr s0, [x1] - mov x2, #0x3ff0000000000000 // =4607182418800017408 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d1, s0 - fmov d17, x2 + fmov d17, x1 fadd d1, d1, d17 fcvt s1, d1 - str s1, [x1] - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x17, x29, #0x8 + str s1, [x17] + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, sub x16, x29, #0x8 ldr s0, [x16] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x1 // =1 add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 sub x17, x29, #0x18 - str s0, [x17] - sub x0, x29, #0x18 - ldr s0, [x0] - mov x1, #0x3ff0000000000000 // =4607182418800017408 + str s16, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + mov x0, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x1 + fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x0] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x17, x29, #0x18 + str s0, [x17] + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, sub x16, x29, #0x18 ldr s0, [x16] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x2 // =2 @@ -127,30 +123,29 @@ Disassembly of section .text: add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 sub x17, x29, #0x48 - str s0, [x17] - sub x1, x29, #0x48 - ldr s0, [x1] + str s16, [x17] + sub x0, x29, #0x48 + ldr s0, [x0] + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x0 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] - ldr s0, [x1] + str s0, [x0] + ldr s0, [x0] fcvt d0, s0 - fmov d17, x0 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] + str s0, [x0] sub x16, x29, #0x48 ldr s0, [x16] - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 @@ -182,10 +177,9 @@ Disassembly of section .text: str d0, [x0, #0x8] sub x0, x29, #0x60 ldr s0, [x0] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, sub x0, x29, #0x60 @@ -261,24 +255,23 @@ Disassembly of section .text: add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4170000000000000 // =4715268809856909312 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x4b800000 // =1266679808 + fmov s16, w0 sub x17, x29, #0x80 - str s0, [x17] - sub x1, x29, #0x80 - ldr s0, [x1] - mov x2, #0x3ff0000000000000 // =4607182418800017408 + str s16, [x17] + sub x16, x29, #0x80 + ldr s0, [x16] + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x2 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] + sub x17, x29, #0x80 + str s0, [x17] sub x16, x29, #0x80 ldr s0, [x16] - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 diff --git a/tests/snapshots/asm/float_increment_decrement.x64.asm b/tests/snapshots/asm/float_increment_decrement.x64.asm index e3d4a4920..7adb760d0 100644 --- a/tests/snapshots/asm/float_increment_decrement.x64.asm +++ b/tests/snapshots/asm/float_increment_decrement.x64.asm @@ -14,21 +14,18 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0xb0, %rsp - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x8(%rbp,%riz) - leaq -0x8(%rbp), %rcx - movss (%rcx,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm1 - movq %rdx, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm1 cvtsd2ss %xmm1, %xmm1 - movss %xmm1, (%rcx,%riz) - cvtss2sd %xmm0, %xmm0 + movss %xmm1, -0x8(%rbp,%riz) movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -37,10 +34,9 @@ Disassembly of section .text: testq %rcx, %rcx jne movss -0x8(%rbp,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -52,22 +48,19 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x18(%rbp,%riz) - leaq -0x18(%rbp), %rax - movss (%rax,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rcx, %xmm15 + movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rax,%riz) - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -76,10 +69,9 @@ Disassembly of section .text: testq %rcx, %rcx jne movss -0x18(%rbp,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -157,28 +149,27 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x48(%rbp,%riz) - leaq -0x48(%rbp), %rcx - movss (%rcx,%riz), %xmm0 + movss %xmm14, -0x48(%rbp,%riz) + leaq -0x48(%rbp), %rax + movss (%rax,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) - movss (%rcx,%riz), %xmm0 + movss %xmm0, (%rax,%riz) + movss (%rax,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) + movss %xmm0, (%rax,%riz) movss -0x48(%rbp,%riz), %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -214,10 +205,9 @@ Disassembly of section .text: movsd %xmm0, 0x8(%rax,%riz) leaq -0x60(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -316,22 +306,19 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x4170000000000000, %rax # imm = 0x4170000000000000 + movl $0x4b800000, %eax # imm = 0x4B800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x80(%rbp,%riz) - leaq -0x80(%rbp), %rcx - movss (%rcx,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movss %xmm14, -0x80(%rbp,%riz) + movss -0x80(%rbp,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rdx, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) + movss %xmm0, -0x80(%rbp,%riz) movss -0x80(%rbp,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -353,4 +340,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_is_four_bytes.aarch64.asm b/tests/snapshots/asm/float_is_four_bytes.aarch64.asm index 9c028eee0..805afd639 100644 --- a/tests/snapshots/asm/float_is_four_bytes.aarch64.asm +++ b/tests/snapshots/asm/float_is_four_bytes.aarch64.asm @@ -10,56 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fadd s0, s0, s1 fadd s0, s0, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] + str x20, [sp, #-0xa0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 mov x20, #0x0 // =0 - b - adrp x0, - add x0, x0, - mov x1, #0x4 // =4 - bl - sxtw x0, w0 - mov x20, #0x1 // =1 - b - adrp x0, - add x0, x0, - mov x1, #0x8 // =8 - bl - sxtw x0, w0 - mov x20, #0x2 // =2 - b - adrp x0, - add x0, x0, - mov x1, #0x4 // =4 - bl - sxtw x0, w0 - mov x20, #0x3 // =3 sub x0, x29, #0x18 - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0] + mov x1, #0x3fc00000 // =1069547520 + fmov s16, w1 + str s16, [x0] sub x0, x29, #0x18 mov x1, #0x5678 // =22136 movk x1, #0x1234, lsl #16 @@ -81,10 +48,9 @@ Disassembly of section .text: sxtw x0, w0 sub x0, x29, #0x18 ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -113,10 +79,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -131,10 +96,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -149,10 +113,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0x8] - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -167,10 +130,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0xc] - mov x0, #0x4012000000000000 // =4616752568008179712 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40900000 // =1083179008 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -182,12 +144,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xa // =10 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, adrp x0, @@ -195,12 +155,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xb // =11 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, adrp x0, @@ -208,13 +166,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xc // =12 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 - fcmp s0, s1 + mov x0, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w1 + fcmp s16, s17 cset x0, eq cbz x0, adrp x0, @@ -222,56 +178,51 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xd // =13 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 - mov x0, #0x401a000000000000 // =4619004367821864960 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + mov x2, #0x40600000 // =1080033280 + fmov s16, w0 + fmov s17, w1 + fadd s0, s16, s17 + fmov s17, w2 + fadd s0, s0, s17 + mov x0, #0x40d00000 // =1087373312 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, add x0, x0, - mov x1, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x400c000000000000 // =4615063718147915776 - fmov d16, x1 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 + mov x1, #0x3f800000 // =1065353216 + mov x2, #0x40000000 // =1073741824 + mov x3, #0x40600000 // =1080033280 + fmov s16, w1 + fmov s17, w2 + fadd s0, s16, s17 + fmov s17, w3 + fadd s0, s0, s17 fcvt d0, s0 bl sxtw x0, w0 mov x20, #0xe // =14 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fcvt d0, s0 - fmov d17, x0 - fadd d0, d0, d17 - fcvt s0, d0 - mov x0, #0x400a000000000000 // =4614500768194494464 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x30 + str s16, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + sub x17, x29, #0x38 + str s16, [x17] + sub x16, x29, #0x30 + ldr s0, [x16] + sub x16, x29, #0x38 + ldr s1, [x16] + mov x0, #0x3e800000 // =1048576000 + fmov s18, w0 + fmadd s0, s0, s1, s18 + mov x0, #0x40500000 // =1078984704 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -280,11 +231,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xf // =15 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 sub x17, x29, #0x48 - str s0, [x17] + str s16, [x17] sub x0, x29, #0x50 sub x1, x29, #0x48 mov x2, #0x4 // =4 @@ -302,10 +252,9 @@ Disassembly of section .text: sxtw x0, w0 mov x20, #0x10 // =16 sxtw x0, w20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret b b @@ -320,3 +269,24 @@ Disassembly of section .text: b b b + adrp x0, + add x0, x0, + mov x1, #0x4 // =4 + bl + sxtw x0, w0 + mov x20, #0x1 // =1 + b + adrp x0, + add x0, x0, + mov x1, #0x8 // =8 + bl + sxtw x0, w0 + mov x20, #0x2 // =2 + b + adrp x0, + add x0, x0, + mov x1, #0x4 // =4 + bl + sxtw x0, w0 + mov x20, #0x3 // =3 + b diff --git a/tests/snapshots/asm/float_is_four_bytes.x64.asm b/tests/snapshots/asm/float_is_four_bytes.x64.asm index 309c468c1..f177402fc 100644 --- a/tests/snapshots/asm/float_is_four_bytes.x64.asm +++ b/tests/snapshots/asm/float_is_four_bytes.x64.asm @@ -11,21 +11,11 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp addss %xmm1, %xmm0 addss %xmm2, %xmm0 - addq $0x20, %rsp - popq %rbp retq
: @@ -34,32 +24,10 @@ Disassembly of section .text: subq $0x80, %rsp movq %rbx, (%rsp) xorq %rbx, %rbx - jmp - leaq , %rdi - movl $0x4, %esi - movb $0x0, %al - callq - movslq %eax, %rax - movl $0x1, %ebx - jmp - leaq , %rdi - movl $0x8, %esi - movb $0x0, %al - callq - movslq %eax, %rax - movl $0x2, %ebx - jmp - leaq , %rdi - movl $0x4, %esi - movb $0x0, %al - callq - movslq %eax, %rax - movl $0x3, %ebx leaq -0x18(%rbp), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 + movl $0x3fc00000, %ecx # imm = 0x3FC00000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, (%rax,%riz) + movss %xmm14, (%rax,%riz) leaq -0x18(%rbp), %rax movl $0x12345678, %ecx # imm = 0x12345678 movl %ecx, 0x4(%rax) @@ -75,10 +43,9 @@ Disassembly of section .text: movslq %eax, %rax leaq -0x18(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -107,10 +74,9 @@ Disassembly of section .text: movl $0x6, %ebx leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -128,10 +94,9 @@ Disassembly of section .text: movl $0x7, %ebx leaq , %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -149,10 +114,9 @@ Disassembly of section .text: movl $0x8, %ebx leaq , %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -170,10 +134,9 @@ Disassembly of section .text: movl $0x9, %ebx leaq , %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -189,12 +152,10 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xa, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -207,12 +168,10 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xb, %ebx - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -225,13 +184,11 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xc, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movl $0x40200000, %ecx # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - ucomiss %xmm1, %xmm0 + movq %rcx, %xmm15 + ucomiss %xmm15, %xmm14 sete %al movzbq %al, %rax setnp %r10b @@ -244,21 +201,17 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xd, %ebx - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40000000, %ecx # imm = 0x40000000 + movl $0x40600000, %edx # imm = 0x40600000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -267,38 +220,35 @@ Disassembly of section .text: testq %rax, %rax je leaq , %rdi - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40000000, %ecx # imm = 0x40000000 + movl $0x40600000, %edx # imm = 0x40600000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0xe, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movss %xmm14, -0x30(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x400a000000000000, %rax # imm = 0x400A000000000000 - cvtss2sd %xmm0, %xmm1 + movss %xmm14, -0x38(%rbp,%riz) + movss -0x30(%rbp,%riz), %xmm0 + movss -0x38(%rbp,%riz), %xmm1 + movl $0x3e800000, %eax # imm = 0x3E800000 + movapd %xmm0, %xmm14 + movapd %xmm1, %xmm15 + movq %rax, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x40500000, %eax # imm = 0x40500000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -312,10 +262,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xf, %ebx - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x48(%rbp,%riz) + movss %xmm14, -0x48(%rbp,%riz) leaq -0x50(%rbp), %rdi leaq -0x48(%rbp), %rsi movl $0x4, %edx @@ -350,4 +299,26 @@ Disassembly of section .text: jmp jmp jmp + leaq , %rdi + movl $0x4, %esi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x1, %ebx + jmp + leaq , %rdi + movl $0x8, %esi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x2, %ebx + jmp + leaq , %rdi + movl $0x4, %esi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x3, %ebx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm b/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm new file mode 100644 index 000000000..3e77e327b --- /dev/null +++ b/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm @@ -0,0 +1,174 @@ + +float_literal_arith_single_precision.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fsub s0, s0, s17 + ret + +: + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + fmov s17, w1 + fmul s1, s1, s17 + fmov s17, w0 + fmadd s0, s0, s17, s1 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, #0x40200000 // =1075838976 + mov x1, #0x3f800000 // =1065353216 + fmov s16, w0 + fmov s17, w1 + fsub s0, s16, s17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x40400000 // =1077936128 + mov x1, #0x41000000 // =1090519040 + mov x2, #0x3f000000 // =1056964608 + mov x3, #0x3e800000 // =1048576000 + fmov s16, w1 + fmov s17, w3 + fmul s0, s16, s17 + fmov s16, w0 + fmov s17, w2 + fmadd s0, s16, s17, s0 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x2 // =2 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fcmp s0, s17 + cset x0, eq + cbz x0, + mov x0, #0x3 // =3 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x1 // =1 + movk x0, #0x3f80, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x4 // =4 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm b/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm new file mode 100644 index 000000000..36027d422 --- /dev/null +++ b/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm @@ -0,0 +1,163 @@ + +float_literal_arith_single_precision.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movl $0x3f800000, %eax # imm = 0x3F800000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + retq + +: + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movq %rcx, %xmm15 + mulss %xmm15, %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl $0x40200000, %eax # imm = 0x40200000 + movl $0x3f800000, %ecx # imm = 0x3F800000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + subss %xmm15, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x40400000, %eax # imm = 0x40400000 + movl $0x41000000, %ecx # imm = 0x41000000 + movl $0x3f000000, %edx # imm = 0x3F000000 + movl $0x3e800000, %esi # imm = 0x3E800000 + movq %rsi, %xmm15 + movq %rcx, %xmm0 + mulss %xmm15, %xmm0 + movq %rax, %xmm14 + movq %rdx, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x40600000, %eax # imm = 0x40600000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0x3, %eax + addq $0x10, %rsp + popq %rbp + retq + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3f800001, %eax # imm = 0x3F800001 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x4, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x10, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm b/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm new file mode 100644 index 000000000..63f0f358b --- /dev/null +++ b/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm @@ -0,0 +1,223 @@ + +float_literal_f_suffix.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0xc0 + str x0, [sp] + str x1, [sp, #0x8] + str x2, [sp, #0x10] + str x3, [sp, #0x18] + str x4, [sp, #0x20] + str x5, [sp, #0x28] + str x6, [sp, #0x30] + str x7, [sp, #0x38] + str d0, [sp, #0x40] + str d1, [sp, #0x50] + str d2, [sp, #0x60] + str d3, [sp, #0x70] + str d4, [sp, #0x80] + str d5, [sp, #0x90] + str d6, [sp, #0xa0] + str d7, [sp, #0xb0] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 + sub x0, x29, #0x20 + add x1, x29, #0x10 + mov x16, x0 + add x17, x29, #0xd0 + str x17, [x16] + add x17, x29, #0x50 + str x17, [x16, #0x8] + add x17, x29, #0xd0 + str x17, [x16, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x18] + mov x17, #0xff80 // =65408 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x1c] + mov x1, #0x0 // =0 + scvtf d0, x1 + b + sub x2, x29, #0x20 + mov x17, x2 + str x9, [sp, #-0x10]! + ldrsw x16, [x17, #0x1c] + cmp x16, #0x0 + b.ge + ldr x9, [x17, #0x10] + add x9, x9, x16 + add x16, x16, #0x10 + str w16, [x17, #0x1c] + cmp x16, #0x0 + b.gt + mov x16, x9 + b + ldr x16, [x17] + add x9, x16, #0x8 + str x9, [x17] + ldr x9, [sp], #0x10 + mov x2, x16 + ldr d1, [x2] + fadd d0, d0, d1 + add x1, x0, #0x1 + sxtw x0, w1 + ldursw x2, [x29, #0x10] + cmp x0, x2 + b.lt + sub x0, x29, #0x20 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 + add sp, sp, #0xc0 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x4b800000 // =1266679808 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 + cset x0, ne + cbz x0, + mov x0, #0x9 // =9 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10000000 // =268435456 + movk x0, #0x4170, lsl #48 + mov x1, #0x4170000000000000 // =4715268809856909312 + fmov d16, x0 + fmov d17, x1 + fcmp d16, d17 + cset x0, eq + cbz x0, + mov x0, #0xa // =10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + mov x1, #0x999a // =39322 + movk x1, #0x9999, lsl #16 + movk x1, #0x9999, lsl #32 + movk x1, #0x3fb9, lsl #48 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 + cset x0, eq + cbz x0, + mov x0, #0xb // =11 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + mov x1, #0xa0000000 // =2684354560 + movk x1, #0x9999, lsl #32 + movk x1, #0x3fb9, lsl #48 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0xc // =12 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + fneg s0, s16 + mov x0, #0xa0000000 // =2684354560 + movk x0, #0x9999, lsl #32 + movk x0, #0x3fb9, lsl #48 + fmov d16, x0 + fneg d1, d16 + fcvt d0, s0 + fcmp d0, d1 + cset x0, ne + cbz x0, + mov x0, #0xd // =13 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + mov x1, #0x3fc00000 // =1069547520 + fmov s16, w1 + fcvt d0, s16 + mov x1, #0x3e800000 // =1048576000 + fmov s16, w1 + fcvt d1, s16 + bl + mov x0, #0x3ffc000000000000 // =4610560118520545280 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0xe // =14 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, #0xcccd // =52429 + movk x1, #0x3dcc, lsl #16 + fmov s16, w1 + fcvt d0, s16 + bl + mov x0, #0xa0000000 // =2684354560 + movk x0, #0x9999, lsl #32 + movk x0, #0x3fb9, lsl #48 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0x10 // =16 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + movk x0, #0x4b80, lsl #16 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 + cset x0, ne + cbz x0, + mov x0, #0xf // =15 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/float_literal_f_suffix.x64.asm b/tests/snapshots/asm/float_literal_f_suffix.x64.asm new file mode 100644 index 000000000..6a1cc0032 --- /dev/null +++ b/tests/snapshots/asm/float_literal_f_suffix.x64.asm @@ -0,0 +1,236 @@ + +float_literal_f_suffix.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0xe0, %rsp + movq %rdi, -0xe0(%rbp) + movq %rsi, -0xd8(%rbp) + movq %rdx, -0xd0(%rbp) + movq %rcx, -0xc8(%rbp) + movq %r8, -0xc0(%rbp) + movq %r9, -0xb8(%rbp) + testb %al, %al + je + movsd %xmm0, -0xb0(%rbp,%riz) + movsd %xmm1, -0xa0(%rbp,%riz) + movsd %xmm2, -0x90(%rbp,%riz) + movsd %xmm3, -0x80(%rbp,%riz) + movsd %xmm4, -0x70(%rbp,%riz) + movsd %xmm5, -0x60(%rbp,%riz) + movsd %xmm6, -0x50(%rbp,%riz) + movsd %xmm7, -0x40(%rbp,%riz) + leaq -0x18(%rbp), %rax + leaq -0xe0(%rbp), %rcx + movl $0x8, (%rax) + movl $0x30, 0x4(%rax) + leaq 0x10(%rbp), %r10 + movq %r10, 0x8(%rax) + leaq -0xe0(%rbp), %r10 + movq %r10, 0x10(%rax) + xorq %rcx, %rcx + cvtsi2sd %rcx, %xmm0 + jmp + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 + movl 0x4(%r11), %r10d + cmpq $0xb0, %r10 + jae + addq 0x10(%r11), %r10 + addl $0x10, 0x4(%r11) + jmp + movq 0x8(%r11), %r10 + addq $0x8, 0x8(%r11) + movq %r10, %rdx + movsd (%rdx,%riz), %xmm1 + addsd %xmm1, %xmm0 + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + movslq -0xe0(%rbp), %rdx + cmpq %rdx, %rax + jl + leaq -0x18(%rbp), %rax + addq $0xe0, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + movl $0x4b800000, %eax # imm = 0x4B800000 + movq %rax, %xmm14 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x9, %eax + popq %rbp + retq + movabsq $0x4170000010000000, %rax # imm = 0x4170000010000000 + movabsq $0x4170000000000000, %rcx # imm = 0x4170000000000000 + movq %rax, %xmm14 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm14 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0xa, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movabsq $0x3fb999999999999a, %rcx # imm = 0x3FB999999999999A + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0xb, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movabsq $0x3fb99999a0000000, %rcx # imm = 0x3FB99999A0000000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xc, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm0 + movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 + movq %rax, %xmm1 + movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + cvtss2sd %xmm0, %xmm0 + ucomisd %xmm1, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xd, %eax + popq %rbp + retq + movl $0x2, %edi + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movl $0x3e800000, %eax # imm = 0x3E800000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + movb $0x2, %al + callq + movabsq $0x3ffc000000000000, %rax # imm = 0x3FFC000000000000 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xe, %eax + popq %rbp + retq + movl $0x1, %edi + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movb $0x1, %al + callq + movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x10, %eax + popq %rbp + retq + movl $0x4b800001, %eax # imm = 0x4B800001 + movq %rax, %xmm14 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xf, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq + movl $0x1, %eax + popq %rbp + retq + movl $0x2, %eax + popq %rbp + retq + movl $0x3, %eax + popq %rbp + retq + movl $0x4, %eax + popq %rbp + retq + movl $0x5, %eax + popq %rbp + retq + movl $0x6, %eax + popq %rbp + retq + movl $0x7, %eax + popq %rbp + retq + movl $0x8, %eax + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm b/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm new file mode 100644 index 000000000..0cae9dd81 --- /dev/null +++ b/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm @@ -0,0 +1,43 @@ + +float_literal_variadic_printf.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x2b0 // =688 + movk x1, #0x0, lsl #16 + b + brk #: + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 + sub x0, x29, #0x40 + mov x1, #0x40 // =64 + adrp x2, + add x2, x2, + mov x3, #0x3fc00000 // =1069547520 + fmov s16, w3 + fcvt d0, s16 + mov x3, #0xcccd // =52429 + movk x3, #0x3dcc, lsl #16 + fmov s16, w3 + fcvt d1, s16 + bl + sxtw x0, w0 + sub x0, x29, #0x40 + adrp x1, + add x1, x1, + bl + sxtw x0, w0 + cmp x0, #0x0 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret diff --git a/tests/snapshots/asm/float_literal_variadic_printf.x64.asm b/tests/snapshots/asm/float_literal_variadic_printf.x64.asm new file mode 100644 index 000000000..85eecf23c --- /dev/null +++ b/tests/snapshots/asm/float_literal_variadic_printf.x64.asm @@ -0,0 +1,44 @@ + +float_literal_variadic_printf.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x70, %rsp + leaq -0x40(%rbp), %rdi + movl $0x40, %esi + leaq , %rdx + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + movb $0x2, %al + callq + movslq %eax, %rax + leaq -0x40(%rbp), %rdi + leaq , %rsi + xorl %eax, %eax + callq + movslq %eax, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x70, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x70, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_long_double_suffix.aarch64.asm b/tests/snapshots/asm/float_long_double_suffix.aarch64.asm index d65021b9f..1d5ae2459 100644 --- a/tests/snapshots/asm/float_long_double_suffix.aarch64.asm +++ b/tests/snapshots/asm/float_long_double_suffix.aarch64.asm @@ -13,32 +13,23 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 + fcvt d0, s16 mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x0 - sub x17, x29, #0x8 - str d16, [x17] - fmov d16, x0 - sub x17, x29, #0x10 - str d16, [x17] - fmov d16, x0 sub x17, x29, #0x18 str d16, [x17] fmov d16, x0 sub x17, x29, #0x20 str d16, [x17] - sub x16, x29, #0x8 - ldr d0, [x16] - sub x16, x29, #0x10 - ldr d1, [x16] - fcmp d0, d1 + fcmp d0, d0 cset x0, ne cbz x0, mov x0, #0xb // =11 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] sub x16, x29, #0x18 ldr d1, [x16] fcmp d0, d1 @@ -48,8 +39,6 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] sub x16, x29, #0x20 ldr d1, [x16] fcmp d0, d1 @@ -59,8 +48,6 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d17, x0 fcmp d0, d17 @@ -86,14 +73,11 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7 // =7 - cmp x0, #0x7 - b.eq - mov x0, #0x10 // =16 + mov x0, #0x0 // =0 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x10 // =16 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/float_long_double_suffix.x64.asm b/tests/snapshots/asm/float_long_double_suffix.x64.asm index 254f4746e..1ff650c51 100644 --- a/tests/snapshots/asm/float_long_double_suffix.x64.asm +++ b/tests/snapshots/asm/float_long_double_suffix.x64.asm @@ -14,18 +14,15 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x8(%rbp,%riz) + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - movsd %xmm14, -0x10(%rbp,%riz) + cvtss2sd %xmm14, %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 movq %rax, %xmm14 movsd %xmm14, -0x18(%rbp,%riz) movq %rax, %xmm14 movsd %xmm14, -0x20(%rbp,%riz) - movsd -0x8(%rbp,%riz), %xmm0 - movsd -0x10(%rbp,%riz), %xmm1 - ucomisd %xmm1, %xmm0 + ucomisd %xmm0, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -37,7 +34,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movsd -0x18(%rbp,%riz), %xmm1 ucomisd %xmm1, %xmm0 setne %al @@ -51,7 +47,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movsd -0x20(%rbp,%riz), %xmm1 ucomisd %xmm1, %xmm0 setne %al @@ -65,7 +60,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 @@ -97,15 +91,11 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movl $0x7, %eax - cmpq $0x7, %rax - je - movl $0x10, %eax + xorq %rax, %rax addq $0x30, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x10, %eax addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/float_param_stack_overflow.aarch64.asm b/tests/snapshots/asm/float_param_stack_overflow.aarch64.asm new file mode 100644 index 000000000..32f42f3e2 --- /dev/null +++ b/tests/snapshots/asm/float_param_stack_overflow.aarch64.asm @@ -0,0 +1,122 @@ + +float_param_stack_overflow.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0x20 + ldr x16, [sp, #0x20] + str x16, [sp] + ldr x16, [sp, #0x28] + str x16, [sp, #0x10] + sub sp, sp, #0x80 + stp d8, d9, [sp, #-0x30]! + str d10, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + ldr s8, [x29, #0x90] + ldr s9, [x29, #0xa0] + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + fmov s17, w1 + fmul s1, s1, s17 + fmov s17, w0 + fmadd s0, s0, s17, s1 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fmadd s0, s2, s17, s0 + mov x0, #0x41000000 // =1090519040 + fmov s17, w0 + fmadd s0, s3, s17, s0 + mov x0, #0x41800000 // =1098907648 + fmov s17, w0 + fmadd s0, s4, s17, s0 + mov x0, #0x42000000 // =1107296256 + fmov s17, w0 + fmadd s0, s5, s17, s0 + mov x0, #0x42800000 // =1115684864 + fmov s17, w0 + fmadd s0, s6, s17, s0 + mov x0, #0x43000000 // =1124073472 + fmov s17, w0 + fmadd s0, s7, s17, s0 + mov x0, #0x43800000 // =1132462080 + fmov s17, w0 + fmadd s0, s8, s17, s0 + mov x0, #0x44000000 // =1140850688 + fmov s17, w0 + fmadd s0, s9, s17, s0 + fcvt d0, s0 + fcvtzs x0, d0 + ldp x29, x30, [sp, #0x20] + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x30 + add sp, sp, #0xa0 + ret + +
: + str d8, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + ldr s8, [x0] + sub sp, sp, #0x10 + str d8, [sp] + str d8, [sp, #0x8] + fmov d0, d8 + fmov d7, d8 + fmov d6, d8 + fmov d5, d8 + fmov d4, d8 + fmov d3, d8 + fmov d2, d8 + fmov d1, d8 + bl + add sp, sp, #0x10 + sxtw x0, w0 + cmp x0, #0x3ff + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret + adrp x0, + add x0, x0, + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x3f000000 // =1056964608 + mov x9, x0 + sub sp, sp, #0x10 + str x1, [sp] + str x2, [sp, #0x8] + fmov d0, d8 + fmov d7, d8 + fmov d6, d8 + fmov d5, d8 + fmov d4, d8 + fmov d3, d8 + fmov d2, d8 + fmov d1, d8 + blr x9 + add sp, sp, #0x10 + sxtw x0, w0 + cmp x0, #0x37f + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret diff --git a/tests/snapshots/asm/float_param_stack_overflow.x64.asm b/tests/snapshots/asm/float_param_stack_overflow.x64.asm new file mode 100644 index 000000000..e99523e47 --- /dev/null +++ b/tests/snapshots/asm/float_param_stack_overflow.x64.asm @@ -0,0 +1,133 @@ + +float_param_stack_overflow.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0xa0, %rsp + movq 0xa0(%rsp), %rax + movq %rax, 0x80(%rsp) + movq 0xa8(%rsp), %rax + movq %rax, 0x90(%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movss 0x90(%rbp,%riz), %xmm14 + movsd %xmm14, 0x18(%rsp) + movss 0xa0(%rbp,%riz), %xmm14 + movsd %xmm14, 0x10(%rsp) + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40000000, %ecx # imm = 0x40000000 + movq %rcx, %xmm15 + mulss %xmm15, %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x40800000, %eax # imm = 0x40800000 + movapd %xmm2, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x41000000, %eax # imm = 0x41000000 + movapd %xmm3, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movapd %xmm4, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x42000000, %eax # imm = 0x42000000 + movapd %xmm5, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x42800000, %eax # imm = 0x42800000 + movapd %xmm6, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x43000000, %eax # imm = 0x43000000 + movapd %xmm7, %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x43800000, %eax # imm = 0x43800000 + movsd 0x18(%rsp), %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x44000000, %eax # imm = 0x44000000 + movsd 0x10(%rsp), %xmm14 + movq %rax, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + cvtss2sd %xmm0, %xmm0 + cvttsd2si %xmm0, %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0xa0, %rsp + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + leaq , %rax + movss (%rax,%riz), %xmm14 + movsd %xmm14, 0x8(%rsp) + subq $0x10, %rsp + movq 0x18(%rsp), %r10 + movq %r10, (%rsp) + movq 0x18(%rsp), %r10 + movq %r10, 0x8(%rsp) + movsd 0x18(%rsp), %xmm0 + movsd 0x18(%rsp), %xmm1 + movsd 0x18(%rsp), %xmm2 + movsd 0x18(%rsp), %xmm3 + movsd 0x18(%rsp), %xmm4 + movsd 0x18(%rsp), %xmm5 + movsd 0x18(%rsp), %xmm6 + movsd 0x18(%rsp), %xmm7 + callq + addq $0x10, %rsp + movslq %eax, %rax + cmpq $0x3ff, %rax # imm = 0x3FF + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + leaq -, %rax # + movl $0x3fc00000, %edi # imm = 0x3FC00000 + movl $0x3f000000, %esi # imm = 0x3F000000 + subq $0x10, %rsp + movq %rdi, (%rsp) + movq %rsi, 0x8(%rsp) + movsd 0x18(%rsp), %xmm0 + movsd 0x18(%rsp), %xmm1 + movsd 0x18(%rsp), %xmm2 + movsd 0x18(%rsp), %xmm3 + movsd 0x18(%rsp), %xmm4 + movsd 0x18(%rsp), %xmm5 + movsd 0x18(%rsp), %xmm6 + movsd 0x18(%rsp), %xmm7 + callq *%rax + addq $0x10, %rsp + movslq %eax, %rax + cmpq $0x37f, %rax # imm = 0x37F + je + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/float_pointer_basics.aarch64.asm b/tests/snapshots/asm/float_pointer_basics.aarch64.asm index 924077a57..f0faf211f 100644 --- a/tests/snapshots/asm/float_pointer_basics.aarch64.asm +++ b/tests/snapshots/asm/float_pointer_basics.aarch64.asm @@ -10,103 +10,78 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] - mov x0, #0x4 // =4 - mov x1, #0x8 // =8 - cmp x0, #0x4 - b.eq - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - cmp x1, #0x8 - b.eq - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x20, #0x4 // =4 - lsl x0, x20, #2 - sxtw x0, w0 - bl - mov x21, x0 - lsl x0, x20, #3 - sxtw x0, w0 + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + mov x0, #0x10 // =16 bl mov x20, x0 + mov x0, #0x20 // =32 + bl + mov x21, x0 mov x0, #0x3f800000 // =1065353216 - str w0, [x21] + str w0, [x20] mov x0, #0x40000000 // =1073741824 - str w0, [x21, #0x4] + str w0, [x20, #0x4] mov x0, #0x3ff0000000000000 // =4607182418800017408 - str x0, [x20] + str x0, [x21] mov x0, #0x4000000000000000 // =4611686018427387904 - str x0, [x20, #0x8] - ldrsw x0, [x21] + str x0, [x21, #0x8] + ldrsw x0, [x20] mov x17, #0x3f800000 // =1065353216 cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - ldrsw x0, [x21, #0x4] + ldrsw x0, [x20, #0x4] mov x17, #0x40000000 // =1073741824 cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - ldr x0, [x20] + ldr x0, [x21] mov x17, #0x3ff0000000000000 // =4607182418800017408 cmp x0, x17 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - ldr x0, [x20, #0x8] + ldr x0, [x21, #0x8] mov x17, #0x4000000000000000 // =4611686018427387904 cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - mov x0, x21 + mov x0, x20 bl sxtw x0, w0 - mov x0, x20 + mov x0, x21 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/float_pointer_basics.x64.asm b/tests/snapshots/asm/float_pointer_basics.x64.asm index 3165e1783..5b2618891 100644 --- a/tests/snapshots/asm/float_pointer_basics.x64.asm +++ b/tests/snapshots/asm/float_pointer_basics.x64.asm @@ -13,97 +13,87 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movl $0x4, %eax - movl $0x8, %ecx - cmpq $0x4, %rax - je - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x40, %rsp - popq %rbp - retq - cmpq $0x8, %rcx - je - movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x40, %rsp - popq %rbp - retq - movl $0x4, %ebx - movq %rbx, %rax - shlq $0x2, %rax - movslq %eax, %rdi + movl $0x10, %edi xorl %eax, %eax callq - movq %rax, %r12 - movq %rbx, %rax - shlq $0x3, %rax - movslq %eax, %rdi + movq %rax, %rbx + movl $0x20, %edi xorl %eax, %eax callq - movq %rax, %rbx + movq %rax, %r12 movl $0x3f800000, %eax # imm = 0x3F800000 - movl %eax, (%r12) + movl %eax, (%rbx) movl $0x40000000, %eax # imm = 0x40000000 - movl %eax, 0x4(%r12) + movl %eax, 0x4(%rbx) movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, (%rbx) + movq %rax, (%r12) movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, 0x8(%rbx) - movslq (%r12), %rax + movq %rax, 0x8(%r12) + movslq (%rbx), %rax cmpq $0x3f800000, %rax # imm = 0x3F800000 je movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movslq 0x4(%r12), %rax + movslq 0x4(%rbx), %rax cmpq $0x40000000, %rax # imm = 0x40000000 je movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movq (%rbx), %rax + movq (%r12), %rax movabsq $0x3ff0000000000000, %r11 # imm = 0x3FF0000000000000 cmpq %r11, %rax je movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movq 0x8(%rbx), %rax + movq 0x8(%r12), %rax movabsq $0x4000000000000000, %r11 # imm = 0x4000000000000000 cmpq %r11, %rax je movl $0x6, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movq %r12, %rdi + movq %rbx, %rdi xorl %eax, %eax callq movslq %eax, %rax - movq %rbx, %rdi + movq %r12, %rdi xorl %eax, %eax callq movslq %eax, %rax xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp + popq %rbp + retq + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_register_resident.aarch64.asm b/tests/snapshots/asm/float_register_resident.aarch64.asm index 1a11c3dc8..35fc68913 100644 --- a/tests/snapshots/asm/float_register_resident.aarch64.asm +++ b/tests/snapshots/asm/float_register_resident.aarch64.asm @@ -10,41 +10,149 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fmadd s0, s0, s1, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s0, d16 - sxtw x0, w1 - cmp x0, #0xa - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sxtw x0, w1 - scvtf d1, x0 - fcvt s1, d1 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d1, s1 - fmov d17, x0 - fmul d1, d1, d17 - fcvt s1, d1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s1, s2, s0 - b + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x0, #0x0 // =0 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x1 // =1 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x2 // =2 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x3 // =3 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x4 // =4 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x5 // =5 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x6 // =6 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x7 // =7 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x8 // =8 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x9 // =9 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] fcvt d0, s0 fcvtzs x0, d0 add sp, sp, #0x30 diff --git a/tests/snapshots/asm/float_register_resident.x64.asm b/tests/snapshots/asm/float_register_resident.x64.asm index de37e093a..f54388b55 100644 --- a/tests/snapshots/asm/float_register_resident.x64.asm +++ b/tests/snapshots/asm/float_register_resident.x64.asm @@ -11,50 +11,152 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movapd %xmm0, %xmm14 movapd %xmm1, %xmm15 movapd %xmm2, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - addq $0x20, %rsp - popq %rbp retq
: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movslq %ecx, %rax - cmpq $0xa, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - movslq %ecx, %rax - cvtsi2sd %rax, %xmm1 - cvtsd2ss %xmm1, %xmm1 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm1, %xmm1 - movq %rax, %xmm15 - mulsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + xorq %rax, %rax movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm1, %xmm14 - movapd %xmm2, %xmm15 + movss %xmm14, -0x8(%rbp,%riz) + xorq %rax, %rax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x1, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x2, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x3, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x4, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x5, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x6, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x7, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x8, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x9, %eax + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - jmp + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_single_precision.aarch64.asm b/tests/snapshots/asm/float_single_precision.aarch64.asm index 67741d87f..7b02b1400 100644 --- a/tests/snapshots/asm/float_single_precision.aarch64.asm +++ b/tests/snapshots/asm/float_single_precision.aarch64.asm @@ -13,18 +13,18 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fmov d17, x1 - fdiv d0, d16, d17 - fcvt s0, d0 - mov x0, #0x7c87 // =31879 - movk x0, #0x5fb6, lsl #16 - movk x0, #0x5555, lsl #32 - movk x0, #0x3fd5, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x40400000 // =1077936128 + fmov s16, w0 + fmov s17, w1 + fdiv s0, s16, s17 + mov x0, #0xaaab // =43691 + movk x0, #0x3eaa, lsl #16 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] + sub x16, x29, #0x10 + ldr s1, [x16] fsub s1, s0, s1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -33,13 +33,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0xaf48 // =44872 - movk x0, #0x9abc, lsl #16 - movk x0, #0xd7f2, lsl #32 - movk x0, #0x3e7a, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xbf95 // =49045 + movk x0, #0x33d6, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x1 // =1 @@ -56,38 +53,100 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 sub x17, x29, #0x8 str s0, [x17] - sxtw x0, w1 - cmp x0, #0xa - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x8 - ldr s0, [x0] - mov x2, #0x999a // =39322 - movk x2, #0x9999, lsl #16 - movk x2, #0x9999, lsl #32 - movk x2, #0x3fb9, lsl #48 - fcvt d0, s0 - fmov d17, x2 - fadd d0, d0, d17 - fcvt s0, d0 - str s0, [x0] - b - mov x0, #0xf29b // =62107 - movk x0, #0x1ad7, lsl #16 - movk x0, #0x3ff0, lsl #48 - fmov d16, x0 - fcvt s0, d16 sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + mov x0, #0x1 // =1 + movk x0, #0x3f80, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x18 ldr s1, [x16] - fsub s1, s1, s0 + fsub s1, s0, s1 mov x0, #0x0 // =0 scvtf d0, x0 fcvt s0, d0 @@ -95,13 +154,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0xed8d // =60813 - movk x0, #0xa0b5, lsl #16 - movk x0, #0xc6f7, lsl #32 - movk x0, #0x3eb0, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x37bd // =14269 + movk x0, #0x3586, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x2 // =2 @@ -110,10 +166,9 @@ Disassembly of section .text: ret sub x16, x29, #0x8 ldr s0, [x16] - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fcmp s0, s17 cset x0, eq cbz x0, mov x0, #0x3 // =3 @@ -130,23 +185,19 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3ff1, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3f8c, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] fmul s1, s0, s0 fmul s1, s1, s0 - fmul s0, s1, s0 - mov x0, #0x2012 // =8210 - movk x0, #0x39f9, lsl #16 - movk x0, #0x6cf4, lsl #32 - movk x0, #0x3ff7, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fsub d0, d0, d17 - fcvt s1, d0 + mov x0, #0x67a2 // =26530 + movk x0, #0x3fbb, lsl #16 + fmov s18, w0 + fnmsub s1, s1, s0, s18 mov x0, #0x0 // =0 scvtf d0, x0 fcvt s0, d0 @@ -154,13 +205,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0x68f1 // =26865 - movk x0, #0x88e3, lsl #16 - movk x0, #0xf8b5, lsl #32 - movk x0, #0x3ee4, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xc5ac // =50604 + movk x0, #0x3727, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x4 // =4 diff --git a/tests/snapshots/asm/float_single_precision.x64.asm b/tests/snapshots/asm/float_single_precision.x64.asm index 1c5e572d9..dec5da20a 100644 --- a/tests/snapshots/asm/float_single_precision.x64.asm +++ b/tests/snapshots/asm/float_single_precision.x64.asm @@ -14,15 +14,15 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40400000, %ecx # imm = 0x40400000 movq %rcx, %xmm15 movq %rax, %xmm0 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd555555fb67c87, %rax # imm = 0x3FD555555FB67C87 + divss %xmm15, %xmm0 + movl $0x3eaaaaab, %eax # imm = 0x3EAAAAAB movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x10(%rbp,%riz) + movss -0x10(%rbp,%riz), %xmm1 movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subss %xmm15, %xmm1 @@ -40,10 +40,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3e7ad7f29abcaf48, %rax # imm = 0x3E7AD7F29ABCAF48 - cvtss2sd %xmm1, %xmm0 + movl $0x33d6bf95, %eax # imm = 0x33D6BF95 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -62,31 +61,67 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 movss %xmm0, -0x8(%rbp,%riz) - movslq %ecx, %rax - cmpq $0xa, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x8(%rbp), %rax - movss (%rax,%riz), %xmm0 - movabsq $0x3fb999999999999a, %rdx # imm = 0x3FB999999999999A - cvtss2sd %xmm0, %xmm0 - movq %rdx, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rax,%riz) - jmp - movabsq $0x3ff000001ad7f29b, %rax # imm = 0x3FF000001AD7F29B + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movl $0x3f800001, %eax # imm = 0x3F800001 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss -0x8(%rbp,%riz), %xmm1 - subss %xmm0, %xmm1 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x18(%rbp,%riz), %xmm1 + movapd %xmm1, %xmm15 + movapd %xmm0, %xmm1 + subss %xmm15, %xmm1 xorq %rax, %rax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 @@ -101,10 +136,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3eb0c6f7a0b5ed8d, %rax # imm = 0x3EB0C6F7A0B5ED8D - cvtss2sd %xmm1, %xmm0 + movl $0x358637bd, %eax # imm = 0x358637BD movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -114,10 +148,9 @@ Disassembly of section .text: popq %rbp retq movss -0x8(%rbp,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -139,20 +172,18 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3ff199999999999a, %rax # imm = 0x3FF199999999999A + movl $0x3f8ccccd, %eax # imm = 0x3F8CCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 movapd %xmm0, %xmm1 mulss %xmm0, %xmm1 mulss %xmm0, %xmm1 + movl $0x3fbb67a2, %eax # imm = 0x3FBB67A2 + movapd %xmm1, %xmm14 movapd %xmm0, %xmm15 - movapd %xmm1, %xmm0 - mulss %xmm15, %xmm0 - movabsq $0x3ff76cf439f92012, %rax # imm = 0x3FF76CF439F92012 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - subsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm1 + movq %rax, %xmm1 + vfmsub231ss %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) - xmm1 xorq %rax, %rax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 @@ -167,10 +198,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3ee4f8b588e368f1, %rax # imm = 0x3EE4F8B588E368F1 - cvtss2sd %xmm1, %xmm0 + movl $0x3727c5ac, %eax # imm = 0x3727C5AC movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -209,4 +239,3 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/float_ternary_promote.aarch64.asm b/tests/snapshots/asm/float_ternary_promote.aarch64.asm index 5000596d4..129c32fcc 100644 --- a/tests/snapshots/asm/float_ternary_promote.aarch64.asm +++ b/tests/snapshots/asm/float_ternary_promote.aarch64.asm @@ -10,141 +10,125 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x0, w0 fmov d2, d0 cbz x0, - b - fmov d2, d1 fmov d0, d2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + fmov d2, d1 + b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str d8, [sp] + str d8, [sp, #-0x70]! str x20, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x0, #0x1 // =1 - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d1, d16 - fcvt s1, d1 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov s16, w1 + fneg s0, s16 + fmov d1, d0 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x60] ldr x20, [sp, #0x10] - ldr d8, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr d8, [sp], #0x70 ret mov x0, #0x0 // =0 - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d8, d16 - fcvt s1, d8 + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40200000 // =1075838976 + fmov s16, w2 + fneg s8, s16 + fmov d1, d8 + fmov d0, x1 bl - fcvt d0, s0 - fcmp d0, d8 + fcmp s0, s8 cset x0, ne cbz x0, mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x60] ldr x20, [sp, #0x10] - ldr d8, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr d8, [sp], #0x70 ret - mov x0, #0x400a000000000000 // =4614500768194494464 - fmov d16, x0 - fcvt s2, d16 + mov x0, #0x40500000 // =1078984704 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] mov x0, #0x0 // =0 - fcvt d0, s2 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, gt cbz x0, - fmov d0, d2 - b - fneg s0, s2 + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x8 + ldr s1, [x16] mov x0, #0x0 // =0 - fcvt d1, s2 - fmov d17, x0 - fcmp d1, d17 + fmov s17, w0 + fcmp s1, s17 cset x0, mi cbz x0, - fneg s2, s2 - b - fadd s0, s0, s2 - mov x0, #0x401a000000000000 // =4619004367821864960 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x8 + ldr s1, [x16] + fneg s1, s1 + fadd s0, s0, s1 + mov x0, #0x40d00000 // =1087373312 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x60] ldr x20, [sp, #0x10] - ldr d8, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr d8, [sp], #0x70 ret - mov x0, #0x2 // =2 - cmp x0, #0x0 - b.ne - mov x0, #0x0 // =0 - fmov d16, x0 + mov x0, #0x41a00000 // =1101004800 + fmov s16, w0 + sub x17, x29, #0x40 + str s16, [x17] + sub x16, x29, #0x40 + ldr s0, [x16] sub x17, x29, #0x38 - str d16, [x17] - b - cmp x0, #0x1 - b.ne - b + str s0, [x17] sub x16, x29, #0x38 - ldr d0, [x16] - fcvt s0, d0 - mov x0, #0x4034000000000000 // =4626322717216342016 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + ldr s0, [x16] + mov x0, #0x41a00000 // =1101004800 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, - b - mov x0, #0x4024000000000000 // =4621819117588971520 - fmov d16, x0 - sub x17, x29, #0x40 - str d16, [x17] - b - mov x0, #0x4034000000000000 // =4626322717216342016 - fmov d16, x0 - sub x17, x29, #0x40 - str d16, [x17] - sub x16, x29, #0x40 - ldr d0, [x16] - sub x17, x29, #0x38 - str d0, [x17] - b mov x0, #0x4 // =4 + ldp x29, x30, [sp, #0x60] ldr x20, [sp, #0x10] - ldr d8, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr d8, [sp], #0x70 ret mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x60] ldr x20, [sp, #0x10] - ldr d8, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr d8, [sp], #0x70 ret + sub x16, x29, #0x8 + ldr s1, [x16] + b + sub x16, x29, #0x8 + ldr s0, [x16] + fneg s0, s0 + b + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x38 + str s16, [x17] + b + mov x0, #0x41200000 // =1092616192 + fmov s16, w0 + sub x17, x29, #0x40 + str s16, [x17] + b diff --git a/tests/snapshots/asm/float_ternary_promote.x64.asm b/tests/snapshots/asm/float_ternary_promote.x64.asm index 4baa9b1e4..f9ebfd2bc 100644 --- a/tests/snapshots/asm/float_ternary_promote.x64.asm +++ b/tests/snapshots/asm/float_ternary_promote.x64.asm @@ -11,19 +11,14 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movslq %edi, %rdi movapd %xmm0, %xmm2 testq %rdi, %rdi je - jmp - movapd %xmm1, %xmm2 movapd %xmm2, %xmm0 - addq $0x20, %rsp - popq %rbp retq + movapd %xmm1, %xmm2 + jmp
: pushq %rbp @@ -31,19 +26,17 @@ Disassembly of section .text: subq $0x60, %rsp movq %rbx, (%rsp) movl $0x1, %edi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %eax # imm = 0x40200000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 + movapd %xmm0, %xmm1 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -57,21 +50,18 @@ Disassembly of section .text: popq %rbp retq xorq %rdi, %rdi - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %esi # imm = 0x3FC00000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm14 movsd %xmm14, 0x18(%rsp) - movsd 0x18(%rsp), %xmm14 - cvtsd2ss %xmm14, %xmm1 + movq %rsi, %xmm0 + movsd 0x18(%rsp), %xmm1 callq - cvtss2sd %xmm0, %xmm0 movsd 0x18(%rsp), %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -84,27 +74,22 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movabsq $0x400a000000000000, %rax # imm = 0x400A000000000000 + movl $0x40500000, %eax # imm = 0x40500000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 xorq %rax, %rax - cvtss2sd %xmm2, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 seta %al movzbq %al, %rax testq %rax, %rax je - movapd %xmm2, %xmm0 - jmp - movapd %xmm2, %xmm0 - movl $0x80000000, %r10d # imm = 0x80000000 - movq %r10, %xmm15 - xorpd %xmm15, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + movss -0x8(%rbp,%riz), %xmm1 xorq %rax, %rax - cvtss2sd %xmm2, %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm1 setb %al movzbq %al, %rax setnp %r10b @@ -112,15 +97,14 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je + movss -0x8(%rbp,%riz), %xmm1 movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm2 - jmp - addss %xmm2, %xmm0 - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 - cvtss2sd %xmm0, %xmm0 + xorpd %xmm15, %xmm1 + addss %xmm1, %xmm0 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -133,22 +117,15 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x2, %eax - testq %rax, %rax - jne - xorq %rax, %rax + movl $0x41a00000, %eax # imm = 0x41A00000 movq %rax, %xmm14 - movsd %xmm14, -0x38(%rbp,%riz) - jmp - cmpq $0x1, %rax - jne - jmp - movsd -0x38(%rbp,%riz), %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4034000000000000, %rax # imm = 0x4034000000000000 - cvtss2sd %xmm0, %xmm0 + movss %xmm14, -0x40(%rbp,%riz) + movss -0x40(%rbp,%riz), %xmm0 + movss %xmm0, -0x38(%rbp,%riz) + movss -0x38(%rbp,%riz), %xmm0 + movl $0x41a00000, %eax # imm = 0x41A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -156,17 +133,6 @@ Disassembly of section .text: orq %r10, %rax testq %rax, %rax je - jmp - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) - jmp - movabsq $0x4034000000000000, %rax # imm = 0x4034000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) - movsd -0x40(%rbp,%riz), %xmm0 - movsd %xmm0, -0x38(%rbp,%riz) - jmp movl $0x4, %eax movq (%rsp), %rbx addq $0x60, %rsp @@ -177,5 +143,19 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + movss -0x8(%rbp,%riz), %xmm1 + jmp + movss -0x8(%rbp,%riz), %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm0 + jmp + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x38(%rbp,%riz) + jmp + movl $0x41200000, %eax # imm = 0x41200000 + movq %rax, %xmm14 + movss %xmm14, -0x40(%rbp,%riz) + jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_variadic_promotion.aarch64.asm b/tests/snapshots/asm/float_variadic_promotion.aarch64.asm index e0ea58670..54f41fc61 100644 --- a/tests/snapshots/asm/float_variadic_promotion.aarch64.asm +++ b/tests/snapshots/asm/float_variadic_promotion.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d1, d0, d1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -27,8 +24,6 @@ Disassembly of section .text: fmov d17, x0 fcmp d1, d17 cset x0, mi - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b @@ -50,10 +45,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -75,16 +69,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 scvtf d0, x1 - sxtw x0, w1 - ldursw x2, [x29, #0x10] - cmp x0, x2 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x20 - mov x17, x0 + sub x2, x29, #0x20 + mov x17, x2 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x1c] cmp x16, #0x0 @@ -101,46 +88,49 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr d1, [x0] + mov x2, x16 + ldr d1, [x2] fadd d0, d0, d1 - b + add x1, x0, #0x1 + sxtw x0, w1 + ldursw x2, [x29, #0x10] + cmp x0, x2 + b.lt sub x0, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str d8, [sp] - str d9, [sp, #0x8] - str x20, [sp, #0x10] - mov x20, #0xe148 // =57672 - movk x20, #0x147a, lsl #16 - movk x20, #0x47ae, lsl #32 - movk x20, #0x4051, lsl #48 - fmov d16, x20 - fcvt s8, d16 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s9, d16 + str x20, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 + mov x0, #0x3d71 // =15729 + movk x0, #0x428a, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] mov x0, #0x1 // =1 - fcvt d0, s8 + sub x16, x29, #0x8 + ldr s0, [x16] + fcvt d0, s0 bl - fmov d1, x20 + mov x0, #0xe148 // =57672 + movk x0, #0x147a, lsl #16 + movk x0, #0x47ae, lsl #32 + movk x0, #0x4051, lsl #48 + fmov d1, x0 bl cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret mov x0, #0x1 // =1 mov x20, #0x4004000000000000 // =4612811918334230528 @@ -153,15 +143,16 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret mov x0, #0x2 // =2 - fcvt d0, s8 - fcvt d1, s9 + sub x16, x29, #0x8 + ldr s0, [x16] + fcvt d0, s0 + sub x16, x29, #0x10 + ldr s1, [x16] + fcvt d1, s1 bl mov x0, #0xe148 // =57672 movk x0, #0x147a, lsl #16 @@ -172,17 +163,18 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret mov x0, #0x3 // =3 mov x1, #0xa // =10 scvtf d0, x1 - fcvt d1, s8 - fcvt d2, s9 + sub x16, x29, #0x8 + ldr s1, [x16] + fcvt d1, s1 + sub x16, x29, #0x10 + ldr s2, [x16] + fcvt d2, s2 bl mov x0, #0xe148 // =57672 movk x0, #0x147a, lsl #16 @@ -193,16 +185,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret diff --git a/tests/snapshots/asm/float_variadic_promotion.x64.asm b/tests/snapshots/asm/float_variadic_promotion.x64.asm index 43f790af3..22e89814f 100644 --- a/tests/snapshots/asm/float_variadic_promotion.x64.asm +++ b/tests/snapshots/asm/float_variadic_promotion.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subsd %xmm15, %xmm1 @@ -38,8 +35,6 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -73,16 +68,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx cvtsi2sd %rcx, %xmm0 - movslq %ecx, %rax - movslq -0xe0(%rbp), %rdx - cmpq %rdx, %rax - jge jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 movl 0x4(%r11), %r10d cmpq $0xb0, %r10 jae @@ -91,10 +79,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movsd (%rax,%riz), %xmm1 + movq %r10, %rdx + movsd (%rdx,%riz), %xmm1 addsd %xmm1, %xmm0 - jmp + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + movslq -0xe0(%rbp), %rdx + cmpq %rdx, %rax + jl leaq -0x18(%rbp), %rax addq $0xe0, %rsp popq %rbp @@ -103,28 +95,27 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x50, %rsp movq %rbx, (%rsp) - movabsq $0x405147ae147ae148, %rbx # imm = 0x405147AE147AE148 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x18(%rsp) - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x428a3d71, %eax # imm = 0x428A3D71 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x10(%rsp) + movss %xmm14, -0x8(%rbp,%riz) + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm14 + movss %xmm14, -0x10(%rbp,%riz) movl $0x1, %edi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq - movq %rbx, %xmm1 + movabsq $0x405147ae147ae148, %rdi # imm = 0x405147AE147AE148 + movq %rdi, %xmm1 callq testq %rax, %rax jne movl $0x1, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x1, %edi @@ -140,14 +131,14 @@ Disassembly of section .text: jne movl $0x2, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x2, %edi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 - movsd 0x10(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm1 + movss -0x8(%rbp,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + cvtss2sd %xmm1, %xmm1 movb $0x2, %al callq movabsq $0x4051a7ae147ae148, %rdi # imm = 0x4051A7AE147AE148 @@ -157,16 +148,16 @@ Disassembly of section .text: jne movl $0x3, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x3, %edi movl $0xa, %eax cvtsi2sd %rax, %xmm0 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm1 - movsd 0x10(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm2 + movss -0x8(%rbp,%riz), %xmm1 + cvtss2sd %xmm1, %xmm1 + movss -0x10(%rbp,%riz), %xmm2 + cvtss2sd %xmm2, %xmm2 movb $0x3, %al callq movabsq $0x405427ae147ae148, %rdi # imm = 0x405427AE147AE148 @@ -176,13 +167,12 @@ Disassembly of section .text: jne movl $0x4, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fma_contraction.aarch64.asm b/tests/snapshots/asm/fma_contraction.aarch64.asm index d722c4b08..8e5aa6d67 100644 --- a/tests/snapshots/asm/fma_contraction.aarch64.asm +++ b/tests/snapshots/asm/fma_contraction.aarch64.asm @@ -22,30 +22,15 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fmadd s0, s0, s1, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fnmsub s0, s0, s1, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 fmsub s0, s0, s1, s2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: @@ -90,55 +75,43 @@ Disassembly of section .text: cbz x0, mov x0, #0x3 // =3 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s2, d16 - fnmsub s0, s0, s1, s2 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fnmsub s0, s16, s17, s18 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s2, d16 - fmsub s0, s0, s1, s2 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmsub s0, s16, s17, s18 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x6 // =6 @@ -156,19 +129,15 @@ Disassembly of section .text: cbz x0, mov x0, #0x7 // =7 ret - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - mov x1, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x1 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + mov x2, #0x3e000000 // =1040187392 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 @@ -200,20 +169,16 @@ Disassembly of section .text: cbz x0, mov x0, #0xa // =10 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xb // =11 diff --git a/tests/snapshots/asm/fma_contraction.x64.asm b/tests/snapshots/asm/fma_contraction.x64.asm index 5ccfa7191..2b112f2ea 100644 --- a/tests/snapshots/asm/fma_contraction.x64.asm +++ b/tests/snapshots/asm/fma_contraction.x64.asm @@ -32,39 +32,24 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movapd %xmm0, %xmm14 movapd %xmm1, %xmm15 movapd %xmm2, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - addq $0x20, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movapd %xmm0, %xmm14 movapd %xmm1, %xmm15 movapd %xmm2, %xmm0 vfmsub231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) - xmm0 - addq $0x20, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movapd %xmm0, %xmm14 movapd %xmm1, %xmm15 movapd %xmm2, %xmm0 vfnmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = -(xmm14 * xmm15) + xmm0 - addq $0x20, %rsp - popq %rbp retq
: @@ -126,23 +111,16 @@ Disassembly of section .text: je movl $0x3, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -152,22 +130,15 @@ Disassembly of section .text: je movl $0x4, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmsub231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) - xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,25 +148,18 @@ Disassembly of section .text: je movl $0x5, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfnmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = -(xmm14 * xmm15) + xmm0 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -223,22 +187,15 @@ Disassembly of section .text: je movl $0x7, %eax retq - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movl $0x3e000000, %edx # imm = 0x3E000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x3fc0000000000000, %rcx # imm = 0x3FC0000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + movq %rcx, %xmm15 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -285,23 +242,16 @@ Disassembly of section .text: je movl $0xa, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/fma_numeric_kernels.aarch64.asm b/tests/snapshots/asm/fma_numeric_kernels.aarch64.asm index 303448f11..a4fc1b78d 100644 --- a/tests/snapshots/asm/fma_numeric_kernels.aarch64.asm +++ b/tests/snapshots/asm/fma_numeric_kernels.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d1, d0, d1 mov x0, #0x0 // =0 fmov d17, x0 @@ -27,15 +24,10 @@ Disassembly of section .text: fmov d17, x0 fcmp d1, d17 cset x0, mi - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sub x2, x1, #0x1 sxtw x2, w2 lsl x2, x2, #3 @@ -43,22 +35,16 @@ Disassembly of section .text: ldr d1, [x2] sub x1, x1, #0x2 sxtw x2, w1 - sxtw x1, w2 - cmp x1, #0x0 - b.lt b - sxtw x1, w2 + lsl x3, x1, #3 + add x3, x0, x3 + ldr d2, [x3] + fmadd d1, d1, d0, d2 sub x2, x1, #0x1 - b sxtw x1, w2 - lsl x1, x1, #3 - add x1, x0, x1 - ldr d2, [x1] - fmadd d1, d1, d0, d2 - b + cmp x1, #0x0 + b.ge fmov d0, d1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : @@ -67,36 +53,50 @@ Disassembly of section .text: sub sp, sp, #0x10 sxtw x2, w2 sxtw x3, w3 - mov x5, #0x0 // =0 - fmov d16, x5 + mov x4, #0x0 // =0 + fmov d16, x4 sub x17, x29, #0x8 str d16, [x17] - sxtw x4, w5 - cmp x4, #0x3 - b.ge - b - sxtw x4, w5 - add x5, x4, #0x1 - b sub x16, x29, #0x8 ldr d0, [x16] mov x17, #0x18 // =24 mul x4, x2, x17 add x4, x0, x4 - sxtw x6, w5 - lsl x7, x6, #3 - add x4, x4, x7 + add x4, x4, #0x0 ldr d1, [x4] + add x4, x1, #0x0 + lsl x5, x3, #3 + add x4, x4, x5 + ldr d2, [x4] + fmadd d0, d1, d2, d0 + sub x17, x29, #0x8 + str d0, [x17] + sub x16, x29, #0x8 + ldr d0, [x16] mov x17, #0x18 // =24 - mul x4, x6, x17 - add x4, x1, x4 - lsl x6, x3, #3 - add x4, x4, x6 + mul x4, x2, x17 + add x4, x0, x4 + ldr d1, [x4, #0x8] + add x4, x1, #0x18 + lsl x5, x3, #3 + add x4, x4, x5 ldr d2, [x4] fmadd d0, d1, d2, d0 sub x17, x29, #0x8 str d0, [x17] - b + sub x16, x29, #0x8 + ldr d0, [x16] + mov x17, #0x18 // =24 + mul x2, x2, x17 + add x0, x0, x2 + ldr d1, [x0, #0x10] + add x0, x1, #0x30 + lsl x1, x3, #3 + add x0, x0, x1 + ldr d2, [x0] + fmadd d0, d1, d2, d0 + sub x17, x29, #0x8 + str d0, [x17] sub x16, x29, #0x8 ldr d0, [x16] add sp, sp, #0x10 @@ -104,9 +104,6 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d17, x0 fmul d2, d1, d17 @@ -123,16 +120,12 @@ Disassembly of section .text: fmadd d2, d16, d2, d3 fadd d2, d2, d4 fmadd d0, d1, d2, d0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x110 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x120]! + stp x29, x30, [sp, #0x110] + add x29, sp, #0x110 sub x0, x29, #0x28 mov x1, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x1 @@ -164,10 +157,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 ret sub x0, x29, #0x28 mov x1, #0x5 // =5 @@ -180,101 +171,63 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 ret mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x3 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b - mov x20, #0x0 // =0 - b - sxtw x0, w2 - cmp x0, #0x3 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 + mov x3, #0x0 // =0 b - sub x0, x29, #0x70 - sxtw x3, w1 + sub x4, x29, #0x70 mov x17, #0x18 // =24 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 - lsl x5, x4, #3 - add x0, x0, x5 + mul x5, x0, x17 + add x4, x4, x5 + lsl x5, x2, #3 + add x4, x4, x5 mov x17, #0x3 // =3 - mul x3, x3, x17 - add x3, x3, x4 - add x3, x3, #0x1 - sxtw x3, w3 - scvtf d0, x3 - str d0, [x0] - sub x0, x29, #0xb8 - sxtw x3, w1 + mul x5, x0, x17 + add x5, x5, x2 + add x5, x5, #0x1 + sxtw x5, w5 + scvtf d0, x5 + str d0, [x4] + sub x4, x29, #0xb8 mov x17, #0x18 // =24 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 - lsl x5, x4, #3 - add x0, x0, x5 - cmp x3, x4 + mul x5, x0, x17 + add x4, x4, x5 + lsl x5, x2, #3 + add x4, x4, x5 + cmp x0, x2 b.ne - b - b - mov x3, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x3 + mov x5, #0x3ff0000000000000 // =4607182418800017408 + fmov d16, x5 sub x17, x29, #0xf8 str d16, [x17] + sub x16, x29, #0xf8 + ldr d0, [x16] + str d0, [x4] b - mov x3, #0x0 // =0 - fmov d16, x3 + mov x5, #0x0 // =0 + fmov d16, x5 sub x17, x29, #0xf8 str d16, [x17] - sub x16, x29, #0xf8 - ldr d0, [x16] - str d0, [x0] b - sxtw x0, w20 + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x3 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 cmp x0, #0x3 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 + b.lt + mov x20, #0x0 // =0 b mov x21, #0x0 // =0 b sub x0, x29, #0x70 - sub x1, x29, #0x70 - mov x2, #0x1 // =1 - mov x3, #0x2 // =2 - bl - mov x0, #0x4058000000000000 // =4636455816377925632 - fmov d1, x0 - bl - cmp x0, #0x0 - b.ne - b - sxtw x0, w21 - cmp x0, #0x3 - b.ge - b - sxtw x0, w21 - add x21, x0, #0x1 - b - sub x0, x29, #0x70 sub x1, x29, #0xb8 - sxtw x2, w20 - sxtw x3, w21 + mov x2, x20 + mov x3, x21 bl sub x0, x29, #0x70 sxtw x1, w20 @@ -287,21 +240,30 @@ Disassembly of section .text: ldr d1, [x0] bl cmp x0, #0x0 + b.eq + sxtw x0, w21 + add x21, x0, #0x1 + sxtw x0, w21 + cmp x0, #0x3 + b.lt + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0x3 + b.lt + sub x0, x29, #0x70 + sub x1, x29, #0x70 + mov x2, #0x1 // =1 + mov x3, #0x2 // =2 + bl + mov x0, #0x4058000000000000 // =4636455816377925632 + fmov d1, x0 + bl + cmp x0, #0x0 b.ne - b - b - mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 - ret - b mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x0 @@ -311,14 +273,6 @@ Disassembly of section .text: fmov d16, x0 fmov d17, x1 fdiv d0, d16, d17 - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x10 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b sub x16, x29, #0xd0 ldr d1, [x16] mov x0, #0x3fe0000000000000 // =4602678819172646912 @@ -339,7 +293,306 @@ Disassembly of section .text: fmadd d1, d5, d2, d1 sub x17, x29, #0xd0 str d1, [x17] - b + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d5, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d1, d5, d2, d1 + sub x17, x29, #0xd0 + str d1, [x17] + sub x16, x29, #0xd0 + ldr d1, [x16] + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d17, x0 + fmul d2, d0, d17 + fmadd d3, d2, d1, d1 + fmadd d2, d2, d3, d1 + fmadd d4, d0, d2, d1 + mov x0, #0x4018000000000000 // =4618441417868443648 + fmov d17, x0 + fdiv d0, d0, d17 + mov x0, #0x4000000000000000 // =4611686018427387904 + fmov d16, x0 + fmadd d3, d16, d3, d1 + fmov d16, x0 + fmadd d2, d16, d2, d3 + fadd d2, d2, d4 + fmadd d0, d0, d2, d1 + sub x17, x29, #0xd0 + str d0, [x17] mov x0, #0x5769 // =22377 movk x0, #0x8b14, lsl #16 movk x0, #0xbf0a, lsl #32 @@ -367,15 +620,18 @@ Disassembly of section .text: cset x0, gt cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 + ret + b + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x110] + ldp x20, x21, [sp], #0x120 ret b + b + b diff --git a/tests/snapshots/asm/fma_numeric_kernels.x64.asm b/tests/snapshots/asm/fma_numeric_kernels.x64.asm index d6838c151..831e320b4 100644 --- a/tests/snapshots/asm/fma_numeric_kernels.x64.asm +++ b/tests/snapshots/asm/fma_numeric_kernels.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subsd %xmm15, %xmm1 @@ -38,15 +35,10 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq -0x1(%rsi), %rax movslq %eax, %rax shlq $0x3, %rax @@ -54,73 +46,76 @@ Disassembly of section .text: movsd (%rax,%riz), %xmm1 leaq -0x2(%rsi), %rax movslq %eax, %rcx - movslq %ecx, %rax - testq %rax, %rax - jl - jmp - movslq %ecx, %rax - leaq -0x1(%rax), %rcx jmp - movslq %ecx, %rax - shlq $0x3, %rax - addq %rdi, %rax - movsd (%rax,%riz), %xmm2 + movq %rax, %rdx + shlq $0x3, %rdx + addq %rdi, %rdx + movsd (%rdx,%riz), %xmm2 movapd %xmm1, %xmm14 movapd %xmm0, %xmm15 movapd %xmm2, %xmm1 vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 - jmp + leaq -0x1(%rax), %rcx + movslq %ecx, %rax + testq %rax, %rax + jge movapd %xmm1, %xmm0 - addq $0x10, %rsp - popq %rbp retq : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp - movq %rbx, (%rsp) + subq $0x10, %rsp movslq %edx, %rdx movslq %ecx, %rcx - xorq %r8, %r8 - movq %r8, %xmm14 + xorq %rax, %rax + movq %rax, %xmm14 movsd %xmm14, -0x8(%rbp,%riz) - movslq %r8d, %rax - cmpq $0x3, %rax - jge - jmp - movslq %r8d, %rax - leaq 0x1(%rax), %r8 - jmp movsd -0x8(%rbp,%riz), %xmm0 imulq $0x18, %rdx, %rax addq %rdi, %rax - movslq %r8d, %r9 - movq %r9, %rbx - shlq $0x3, %rbx - addq %rbx, %rax + addq $0x0, %rax movsd (%rax,%riz), %xmm1 - imulq $0x18, %r9, %rax - addq %rsi, %rax - movq %rcx, %r9 - shlq $0x3, %r9 - addq %r9, %rax + leaq (%rsi), %rax + movq %rcx, %r8 + shlq $0x3, %r8 + addq %r8, %rax movsd (%rax,%riz), %xmm2 movapd %xmm1, %xmm14 movapd %xmm2, %xmm15 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 movsd %xmm0, -0x8(%rbp,%riz) - jmp movsd -0x8(%rbp,%riz), %xmm0 - movq (%rsp), %rbx - addq $0x20, %rsp + imulq $0x18, %rdx, %rax + addq %rdi, %rax + movsd 0x8(%rax,%riz), %xmm1 + leaq 0x18(%rsi), %rax + movq %rcx, %r8 + shlq $0x3, %r8 + addq %r8, %rax + movsd (%rax,%riz), %xmm2 + movapd %xmm1, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movsd %xmm0, -0x8(%rbp,%riz) + movsd -0x8(%rbp,%riz), %xmm0 + imulq $0x18, %rdx, %rax + addq %rdi, %rax + movsd 0x10(%rax,%riz), %xmm1 + leaq 0x30(%rsi), %rax + shlq $0x3, %rcx + addq %rcx, %rax + movsd (%rax,%riz), %xmm2 + movapd %xmm1, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movsd %xmm0, -0x8(%rbp,%riz) + movsd -0x8(%rbp,%riz), %xmm0 + addq $0x10, %rsp popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 movapd %xmm1, %xmm2 @@ -153,8 +148,6 @@ Disassembly of section .text: movapd %xmm1, %xmm14 movapd %xmm2, %xmm15 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - addq $0x20, %rsp - popq %rbp retq
: @@ -215,91 +208,55 @@ Disassembly of section .text: popq %rbp retq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x3, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp - xorq %rbx, %rbx - jmp - movslq %edx, %rax - cmpq $0x3, %rax - jge jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx + xorq %rsi, %rsi jmp - leaq -0x70(%rbp), %rax - movslq %ecx, %rsi - imulq $0x18, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - movq %rdi, %r8 + leaq -0x70(%rbp), %rdi + imulq $0x18, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r8 shlq $0x3, %r8 - addq %r8, %rax - leaq (%rsi,%rsi,2), %rsi - addq %rdi, %rsi - incq %rsi - movslq %esi, %rsi - cvtsi2sd %rsi, %xmm0 - movsd %xmm0, (%rax,%riz) - leaq -0xb8(%rbp), %rax - movslq %ecx, %rsi - imulq $0x18, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - movq %rdi, %r8 + addq %r8, %rdi + leaq (%rax,%rax,2), %r8 + addq %rdx, %r8 + incq %r8 + movslq %r8d, %r8 + cvtsi2sd %r8, %xmm0 + movsd %xmm0, (%rdi,%riz) + leaq -0xb8(%rbp), %rdi + imulq $0x18, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r8 shlq $0x3, %r8 - addq %r8, %rax - cmpq %rdi, %rsi + addq %r8, %rdi + cmpq %rdx, %rax jne - jmp - jmp - movabsq $0x3ff0000000000000, %rsi # imm = 0x3FF0000000000000 - movq %rsi, %xmm14 + movabsq $0x3ff0000000000000, %r8 # imm = 0x3FF0000000000000 + movq %r8, %xmm14 movsd %xmm14, -0xf8(%rbp,%riz) + movsd -0xf8(%rbp,%riz), %xmm0 + movsd %xmm0, (%rdi,%riz) jmp - xorq %rsi, %rsi - movq %rsi, %xmm14 + xorq %r8, %r8 + movq %r8, %xmm14 movsd %xmm14, -0xf8(%rbp,%riz) - movsd -0xf8(%rbp,%riz), %xmm0 - movsd %xmm0, (%rax,%riz) jmp - movslq %ebx, %rax + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x3, %rdx + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax cmpq $0x3, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx + jl + xorq %rbx, %rbx jmp xorq %r12, %r12 jmp leaq -0x70(%rbp), %rdi - leaq -0x70(%rbp), %rsi - movl $0x1, %edx - movl $0x2, %ecx - callq - movabsq $0x4058000000000000, %rdi # imm = 0x4058000000000000 - movq %rdi, %xmm1 - callq - testq %rax, %rax - jne - jmp - movslq %r12d, %rax - cmpq $0x3, %rax - jge - jmp - movslq %r12d, %rax - leaq 0x1(%rax), %r12 - jmp - leaq -0x70(%rbp), %rdi leaq -0xb8(%rbp), %rsi - movslq %ebx, %rdx - movslq %r12d, %rcx + movq %rbx, %rdx + movq %r12, %rcx callq leaq -0x70(%rbp), %rax movslq %ebx, %rcx @@ -311,16 +268,27 @@ Disassembly of section .text: movsd (%rax,%riz), %xmm1 callq testq %rax, %rax + je + movslq %r12d, %rax + leaq 0x1(%rax), %r12 + movslq %r12d, %rax + cmpq $0x3, %rax + jl + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0x3, %rax + jl + leaq -0x70(%rbp), %rdi + leaq -0x70(%rbp), %rsi + movl $0x1, %edx + movl $0x2, %ecx + callq + movabsq $0x4058000000000000, %rdi # imm = 0x4058000000000000 + movq %rdi, %xmm1 + callq + testq %rax, %rax jne - jmp - jmp - movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x110, %rsp # imm = 0x110 - popq %rbp - retq - jmp movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 @@ -334,14 +302,6 @@ Disassembly of section .text: movq %rcx, %xmm15 movq %rax, %xmm0 divsd %xmm15, %xmm0 - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x10, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp movsd -0xd0(%rbp,%riz), %xmm1 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 @@ -377,46 +337,578 @@ Disassembly of section .text: movapd %xmm2, %xmm15 vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 movsd %xmm1, -0xd0(%rbp,%riz) - jmp - movabsq $0x4005bf0a8b145769, %rax # imm = 0x4005BF0A8B145769 + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 movq %rax, %xmm14 - movsd %xmm14, -0xe8(%rbp,%riz) - movsd -0xd0(%rbp,%riz), %xmm0 - movsd -0xe8(%rbp,%riz), %xmm1 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 movapd %xmm1, %xmm15 - movapd %xmm0, %xmm1 - subsd %xmm15, %xmm1 - xorq %rax, %rax + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 - setb %al - movzbq %al, %rax - setnp %r10b - movzbq %r10b, %r10 - andq %r10, %rax - testq %rax, %rax - je - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 - movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - movabsq $0x3eb0c6f7a0b5ed8d, %rax # imm = 0x3EB0C6F7A0B5ED8D + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 - seta %al - movzbq %al, %rax - testq %rax, %rax - je - movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x110, %rsp # imm = 0x110 - popq %rbp - retq + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm5 + divsd %xmm15, %xmm5 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm5, %xmm14 + movapd %xmm2, %xmm15 + vfmadd231sd %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) + xmm1 + movsd %xmm1, -0xd0(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm1 + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm15 + movapd %xmm0, %xmm2 + mulsd %xmm15, %xmm2 + movapd %xmm2, %xmm14 + movapd %xmm1, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movapd %xmm2, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm4 + vfmadd231sd %xmm15, %xmm14, %xmm4 # xmm4 = (xmm14 * xmm15) + xmm4 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + movq %rax, %xmm15 + divsd %xmm15, %xmm0 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movq %rax, %xmm14 + movapd %xmm3, %xmm15 + movapd %xmm1, %xmm3 + vfmadd231sd %xmm15, %xmm14, %xmm3 # xmm3 = (xmm14 * xmm15) + xmm3 + movq %rax, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm3, %xmm2 + vfmadd231sd %xmm15, %xmm14, %xmm2 # xmm2 = (xmm14 * xmm15) + xmm2 + addsd %xmm4, %xmm2 + movapd %xmm0, %xmm14 + movapd %xmm2, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movsd %xmm0, -0xd0(%rbp,%riz) + movabsq $0x4005bf0a8b145769, %rax # imm = 0x4005BF0A8B145769 + movq %rax, %xmm14 + movsd %xmm14, -0xe8(%rbp,%riz) + movsd -0xd0(%rbp,%riz), %xmm0 + movsd -0xe8(%rbp,%riz), %xmm1 + movapd %xmm1, %xmm15 + movapd %xmm0, %xmm1 + subsd %xmm15, %xmm1 xorq %rax, %rax + movq %rax, %xmm15 + ucomisd %xmm15, %xmm1 + setb %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + movabsq $0x3eb0c6f7a0b5ed8d, %rax # imm = 0x3EB0C6F7A0B5ED8D + movq %rax, %xmm15 + ucomisd %xmm15, %xmm1 + seta %al + movzbq %al, %rax + testq %rax, %rax + je + movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x110, %rsp # imm = 0x110 popq %rbp retq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x110, %rsp # imm = 0x110 + popq %rbp + retq + jmp + movl $0x3, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x110, %rsp # imm = 0x110 + popq %rbp + retq + jmp + jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_arg_decay_then_deref_assign.aarch64.asm b/tests/snapshots/asm/fn_arg_decay_then_deref_assign.aarch64.asm index 700c8c601..334631602 100644 --- a/tests/snapshots/asm/fn_arg_decay_then_deref_assign.aarch64.asm +++ b/tests/snapshots/asm/fn_arg_decay_then_deref_assign.aarch64.asm @@ -32,7 +32,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x29 // =41 @@ -45,9 +44,8 @@ Disassembly of section .text: cmp x0, #0x2a b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/fn_arg_decay_then_deref_assign.x64.asm b/tests/snapshots/asm/fn_arg_decay_then_deref_assign.x64.asm index 32be651cd..ae4d80b12 100644 --- a/tests/snapshots/asm/fn_arg_decay_then_deref_assign.x64.asm +++ b/tests/snapshots/asm/fn_arg_decay_then_deref_assign.x64.asm @@ -30,7 +30,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movl $0x29, %ecx movl %ecx, (%rax) @@ -41,9 +40,9 @@ Disassembly of section .text: cmpq $0x2a, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_decay_inside_block.aarch64.asm b/tests/snapshots/asm/fn_ptr_decay_inside_block.aarch64.asm index 183981708..4b73bd843 100644 --- a/tests/snapshots/asm/fn_ptr_decay_inside_block.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_decay_inside_block.aarch64.asm @@ -15,78 +15,53 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x90]! str x19, [sp, #0x10] - mov x20, #0x0 // =0 + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 + adrp x20, + add x20, x20, mov x0, #0x1 // =1 - cmp x0, #0x0 - b.ne - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - adrp x1, - add x1, x1, - b - adrp x21, - add x21, x21, - mov x0, #0x1 // =1 - str x0, [sp, #-0x10]! - mov x9, x21 - ldr x0, [sp] + mov x9, x20 blr x9 - add sp, sp, #0x10 - add x20, x20, x0 + add x21, x0, #0x0 mov x0, #0x2 // =2 - str x0, [sp, #-0x10]! - mov x9, x21 - ldr x0, [sp] + mov x9, x20 blr x9 - add sp, sp, #0x10 - add x20, x20, x0 - b - cmp x1, #0x0 - b.eq - b - mov x1, #0x0 // =0 + add x20, x21, x0 + adrp x1, + add x1, x1, b mov x0, #0x3 // =3 - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 add x20, x20, x0 - b + mov x1, #0x0 // =0 + cmp x1, #0x0 + b.ne adrp x0, add x0, x0, stur x0, [x29, #-0x48] sub x0, x29, #0x48 ldr x0, [x0] mov x1, #0x4 // =4 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 add x0, x20, x0 sxtw x0, w0 cmp x0, #0x19a b.ne mov x1, #0x0 // =0 - b - mov x1, #0x2 // =2 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x80] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x90 + ret + mov x1, #0x2 // =2 + b + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x90 ret diff --git a/tests/snapshots/asm/fn_ptr_decay_inside_block.x64.asm b/tests/snapshots/asm/fn_ptr_decay_inside_block.x64.asm index a4422f6bd..b030ee486 100644 --- a/tests/snapshots/asm/fn_ptr_decay_inside_block.x64.asm +++ b/tests/snapshots/asm/fn_ptr_decay_inside_block.x64.asm @@ -21,38 +21,24 @@ Disassembly of section .text: subq $0x70, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - xorq %rbx, %rbx - movl $0x1, %eax - testq %rax, %rax - jne - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x70, %rsp - popq %rbp - retq - leaq -, %rcx # - jmp - leaq -, %r12 # + leaq -, %rbx # movl $0x1, %edi - movq %r12, %rax + movq %rbx, %rax callq *%rax - addq %rax, %rbx + leaq (%rax), %r12 movl $0x2, %edi - movq %r12, %rax + movq %rbx, %rax callq *%rax - addq %rax, %rbx - jmp - testq %rcx, %rcx - je - jmp - xorq %rcx, %rcx + leaq (%r12,%rax), %rbx + leaq -, %rcx # jmp movl $0x3, %edi movq %rcx, %rax callq *%rax addq %rax, %rbx - jmp + xorq %rcx, %rcx + testq %rcx, %rcx + jne leaq -, %rax # movq %rax, -0x48(%rbp) leaq -0x48(%rbp), %rax @@ -64,12 +50,18 @@ Disassembly of section .text: cmpq $0x19a, %rax # imm = 0x19A jne xorq %rcx, %rcx - jmp - movl $0x2, %ecx movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq %rcx, %rax addq $0x70, %rsp popq %rbp retq + movl $0x2, %ecx + jmp + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x70, %rsp + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_explicit_deref.aarch64.asm b/tests/snapshots/asm/fn_ptr_explicit_deref.aarch64.asm index b441ff29a..2f14b5ca6 100644 --- a/tests/snapshots/asm/fn_ptr_explicit_deref.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_explicit_deref.aarch64.asm @@ -15,82 +15,66 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + str x20, [sp, #-0x70]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 adrp x0, add x0, x0, stur x0, [x29, #-0x8] mov x0, #0x28 // =40 ldur x1, [x29, #-0x8] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x29 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0x28 // =40 ldur x1, [x29, #-0x8] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x29 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret sub x20, x29, #0x8 ldr x0, [x20] mov x1, #0x28 // =40 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x29 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret ldr x0, [x20] mov x1, #0x28 // =40 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x29 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0x2a // =42 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret diff --git a/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm index 3f5f29da9..908ba50c5 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm @@ -10,147 +10,101 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fmul s0, s0, s17 fcvt d0, s0 - fmov d17, x0 - fmul d0, d0, d17 fcvtzs x0, d0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fcvt d0, s0 fcvtzs x1, d0 add x0, x0, x1 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 - fmov x16, d0 - str x16, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] - ldr d0, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fcvt d0, s0 fcvtzs x1, d0 add x0, x0, x1 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x40200000 // =1075838976 mov x9, x20 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, mov x1, #0x3 // =3 - mov x2, #0x4012000000000000 // =4616752568008179712 - fmov d16, x2 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! - str x1, [sp, #-0x10]! + mov x2, #0x40900000 // =1083179008 mov x9, x0 - ldr x0, [sp] - ldr d0, [sp, #0x10] + fmov d0, x2 + mov x0, x1 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0xa // =10 adrp x1, add x1, x1, - mov x2, #0x4004000000000000 // =4612811918334230528 - fmov d16, x2 - fcvt s0, d16 + mov x2, #0x40200000 // =1075838976 + fmov d0, x2 bl cmp x0, #0xc b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x40600000 // =1080033280 mov x9, x20 - ldr d0, [sp] + fmov d0, x0 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/fn_ptr_float_arg.x64.asm b/tests/snapshots/asm/fn_ptr_float_arg.x64.asm index 450fb0832..82d8aac3e 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg.x64.asm @@ -11,116 +11,95 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - mulsd %xmm15, %xmm0 + mulss %xmm15, %xmm0 + cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax addq %rdi, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp movslq %edi, %rdi movq %rsi, %rax callq *%rax movslq %eax, %rax - addq $0x20, %rsp popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax addq %rdi, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq -, %rbx # - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edi # imm = 0x40200000 movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x5, %rax je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # movl $0x3, %edi - movabsq $0x4012000000000000, %rcx # imm = 0x4012000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40900000, %esi # imm = 0x40900000 + movq %rsi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x7, %rax je movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0xa, %edi leaq -, %rsi # - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edx # imm = 0x40200000 + movq %rdx, %xmm0 callq cmpq $0xc, %rax je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40600000, %edi # imm = 0x40600000 movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x7, %rax je movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm index fd5140825..cfa891a96 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm @@ -10,34 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fmul d0, d0, d17 - fcvt s0, d0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fmul s0, s0, s17 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fneg s0, s0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fadd s0, s0, s1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: @@ -57,71 +40,53 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x10 ldr x0, [x0] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 ldr x0, [x0, #0x8] - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x20, #0x40400000 // =1077936128 mov x9, x0 - ldr d0, [sp] + fmov d0, x20 blr x9 - add sp, sp, #0x10 - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - sub x1, x29, #0x10 - ldr x0, [x1, x0, lsl #3] - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + sub x0, x29, #0x10 + add x0, x0, #0x0 + ldr x0, [x0] + mov x1, #0x40800000 // =1082130432 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4020000000000000 // =4620693217682128896 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41000000 // =1090519040 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret @@ -134,76 +99,58 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x50 ldr x0, [x0] - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - fmov x16, d1 - str x16, [sp, #-0x10]! - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40000000 // =1073741824 mov x9, x0 - ldr d0, [sp] - ldr d1, [sp, #0x10] + fmov d0, x1 + fmov d1, x2 blr x9 - add sp, sp, #0x20 - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, - mov x1, #0x4014000000000000 // =4617315517961601024 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40a00000 // =1084227584 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40e00000 // =1088421888 + fmov s16, w0 + sub x17, x29, #0x88 + str s16, [x17] sub x0, x29, #0x10 ldr x0, [x0] - fmov x16, d0 - str x16, [sp, #-0x10]! + sub x16, x29, #0x88 + ldr s0, [x16] mov x9, x0 - ldr d0, [sp] blr x9 - add sp, sp, #0x10 - mov x0, #0x402c000000000000 // =4624070917402656768 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41600000 // =1096810496 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret @@ -219,80 +166,58 @@ Disassembly of section .text: sub x20, x29, #0xa8 sub x0, x29, #0xa8 ldr x0, [x0] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret ldr x0, [x20] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret ldr x0, [x20, #0x8] - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - fmov x16, d1 - str x16, [sp, #-0x10]! - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40000000 // =1073741824 mov x9, x0 - ldr d0, [sp] - ldr d1, [sp, #0x10] + fmov d0, x1 + fmov d1, x2 blr x9 - add sp, sp, #0x20 - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm b/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm index d10e5f1ad..60224da3d 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm @@ -11,36 +11,19 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - mulsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - addq $0x10, %rsp - popq %rbp + mulss %xmm15, %xmm0 retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp addss %xmm1, %xmm0 - addq $0x10, %rsp - popq %rbp retq
: @@ -58,14 +41,12 @@ Disassembly of section .text: popq %rdx leaq -0x10(%rbp), %rax movq (%rax), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -80,16 +61,14 @@ Disassembly of section .text: retq leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %ebx # imm = 0x40400000 + movq %rbx, %xmm0 callq *%rax movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -102,17 +81,15 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq - xorq %rax, %rax - leaq -0x10(%rbp), %rcx - movq (%rcx,%rax,8), %rax - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + leaq -0x10(%rbp), %rax + addq $0x0, %rax + movq (%rax), %rax + movl $0x40800000, %edi # imm = 0x40800000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4020000000000000, %rax # imm = 0x4020000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41000000, %eax # imm = 0x41000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -133,17 +110,14 @@ Disassembly of section .text: popq %rdx leaq -0x50(%rbp), %rax movq (%rax), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %edi # imm = 0x3FC00000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq *%rax - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -157,14 +131,12 @@ Disassembly of section .text: popq %rbp retq leaq -, %rax # - movabsq $0x4014000000000000, %rcx # imm = 0x4014000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,16 +149,16 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x88(%rbp,%riz) leaq -0x10(%rbp), %rax movq (%rax), %rax + movss -0x88(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x402c000000000000, %rax # imm = 0x402C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41600000, %eax # imm = 0x41600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -210,14 +182,12 @@ Disassembly of section .text: leaq -0xa8(%rbp), %rbx leaq -0xa8(%rbp), %rax movq (%rax), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -231,14 +201,12 @@ Disassembly of section .text: popq %rbp retq movq (%rbx), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -252,17 +220,14 @@ Disassembly of section .text: popq %rbp retq movq 0x8(%rbx), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %edi # imm = 0x3FC00000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq *%rax - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -280,4 +245,3 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm index 206e7029b..7ac5e77ae 100644 --- a/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm @@ -10,18 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40200000 // =1075838976 + fmov d0, x0 ret : sxtw x0, w0 scvtf d0, x0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d17, x0 - fmul d0, d0, d17 fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 ret : @@ -40,103 +39,86 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x9, x20 blr x9 - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, mov x1, #0xa // =10 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, mov x1, #0x4000000000000000 // =4611686018427387904 - str x1, [sp, #-0x10]! mov x9, x0 - ldr d0, [sp] + fmov d0, x1 blr x9 - add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x9, x20 blr x9 - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, mov x1, #0x8 // =8 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 mov x0, #0x4000000000000000 // =4611686018427387904 fmov d17, x0 fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/fn_ptr_float_return.x64.asm b/tests/snapshots/asm/fn_ptr_float_return.x64.asm index 2bd89bee7..bbbfbbe40 100644 --- a/tests/snapshots/asm/fn_ptr_float_return.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_return.x64.asm @@ -11,18 +11,18 @@ Disassembly of section .text: ud2 : - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movapd %xmm14, %xmm0 retq : movslq %edi, %rdi cvtsi2sd %rdi, %xmm0 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm15 - mulsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 retq : @@ -43,15 +43,14 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq -, %rbx # movq %rbx, %rax callq *%rax - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -61,16 +60,15 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # movl $0xa, %edi callq *%rax - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -80,17 +78,16 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 movq %rdi, %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -100,15 +97,14 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movq %rbx, %rax callq *%rax - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -118,7 +114,7 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # @@ -136,12 +132,11 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_multi_deref.aarch64.asm b/tests/snapshots/asm/fn_ptr_multi_deref.aarch64.asm index eca3e6117..8a74ff8e3 100644 --- a/tests/snapshots/asm/fn_ptr_multi_deref.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_multi_deref.aarch64.asm @@ -15,62 +15,39 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] + str x20, [sp, #-0xa0]! str x19, [sp, #0x10] - mov x0, #0x2 // =2 - mov x1, #0x3 // =3 - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x5 - b.eq - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 adrp x0, add x0, x0, adrp x20, add x20, x20, mov x1, #0x4 // =4 mov x2, #0x5 // =5 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x9 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret mov x0, #0x6 // =6 mov x1, #0x7 // =7 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0xd b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret sub x0, x29, #0x68 sub x1, x29, #0x68 @@ -83,23 +60,25 @@ Disassembly of section .text: cmp x1, #0xa b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret ldrsw x0, [x0, #0x8] cmp x0, #0x1e b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x90] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0xa0 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret diff --git a/tests/snapshots/asm/fn_ptr_multi_deref.x64.asm b/tests/snapshots/asm/fn_ptr_multi_deref.x64.asm index 3b5cdd6ae..daffc9e19 100644 --- a/tests/snapshots/asm/fn_ptr_multi_deref.x64.asm +++ b/tests/snapshots/asm/fn_ptr_multi_deref.x64.asm @@ -20,17 +20,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x80, %rsp movq %rbx, (%rsp) - movl $0x2, %eax - movl $0x3, %ecx - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x5, %rax - je - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x80, %rsp - popq %rbp - retq leaq -, %rax # leaq -, %rbx # movl $0x4, %edi @@ -84,4 +73,9 @@ Disassembly of section .text: addq $0x80, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x80, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_return_type.aarch64.asm b/tests/snapshots/asm/fn_ptr_return_type.aarch64.asm index 05454bf73..a5455a68b 100644 --- a/tests/snapshots/asm/fn_ptr_return_type.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_return_type.aarch64.asm @@ -30,11 +30,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x9, x20 @@ -43,10 +42,9 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x9, x20 blr x9 @@ -54,10 +52,9 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -67,10 +64,9 @@ Disassembly of section .text: cmp x0, #0x1e b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -80,14 +76,12 @@ Disassembly of section .text: cmp x0, #0xa b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/fn_ptr_return_type.x64.asm b/tests/snapshots/asm/fn_ptr_return_type.x64.asm index 9aa383377..fc065a7b7 100644 --- a/tests/snapshots/asm/fn_ptr_return_type.x64.asm +++ b/tests/snapshots/asm/fn_ptr_return_type.x64.asm @@ -29,7 +29,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq -, %rbx # movq %rbx, %rax @@ -39,7 +39,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movq %rbx, %rax @@ -49,7 +49,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # @@ -59,7 +59,7 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # @@ -69,12 +69,12 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_struct_return.aarch64.asm b/tests/snapshots/asm/fn_ptr_struct_return.aarch64.asm index 6a4d7e5fd..094bea0c1 100644 --- a/tests/snapshots/asm/fn_ptr_struct_return.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_struct_return.aarch64.asm @@ -15,114 +15,83 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x0 // =0 adrp x20, add x20, x20, ldr x1, [x20] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20] mov x1, #0x0 // =0 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20] mov x1, #0x0 // =0 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x21, add x21, x21, mov x0, #0x0 // =0 - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret ldr x0, [x20] mov x1, #0x0 // =0 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/fn_ptr_struct_return.x64.asm b/tests/snapshots/asm/fn_ptr_struct_return.x64.asm index 8da96bef9..60daf5915 100644 --- a/tests/snapshots/asm/fn_ptr_struct_return.x64.asm +++ b/tests/snapshots/asm/fn_ptr_struct_return.x64.asm @@ -17,7 +17,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi @@ -29,7 +29,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq movq (%rbx), %rax @@ -40,7 +40,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq movq (%rbx), %rax @@ -51,7 +51,7 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %r12 # @@ -63,7 +63,7 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rdi, %rdi @@ -74,7 +74,7 @@ Disassembly of section .text: movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq movq (%rbx), %rax @@ -85,13 +85,13 @@ Disassembly of section .text: movl $0x6, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_ternary_call_return.aarch64.asm b/tests/snapshots/asm/fn_ptr_ternary_call_return.aarch64.asm index 998365d77..cb10ed8c1 100644 --- a/tests/snapshots/asm/fn_ptr_ternary_call_return.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_ternary_call_return.aarch64.asm @@ -24,41 +24,28 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, #0x6789 // =26505 movk x20, #0x2345, lsl #16 movk x20, #0x1, lsl #32 adrp x1, add x1, x1, - b - adrp x1, - add x1, x1, - str x20, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] + mov x0, x20 blr x9 - add sp, sp, #0x10 mov x22, x0 adrp x1, add x1, x1, - b - adrp x1, - add x1, x1, mov x0, #0x7890 // =30864 movk x0, #0x3456, lsl #16 movk x0, #0x12, lsl #32 - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 - mov x21, x0 + mov x2, x0 cmp x22, x20 b.eq adrp x0, @@ -67,42 +54,41 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret mov x17, #0x7891 // =30865 movk x17, #0x3456, lsl #16 movk x17, #0x12, lsl #32 - cmp x21, x17 + cmp x2, x17 b.eq adrp x0, add x0, x0, - mov x1, x21 + mov x1, x2 bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret adrp x0, add x0, x0, mov x1, x22 - mov x2, x21 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret + adrp x1, + add x1, x1, + b + adrp x1, + add x1, x1, + b diff --git a/tests/snapshots/asm/fn_ptr_ternary_call_return.x64.asm b/tests/snapshots/asm/fn_ptr_ternary_call_return.x64.asm index 0c8c80e45..3a770038c 100644 --- a/tests/snapshots/asm/fn_ptr_ternary_call_return.x64.asm +++ b/tests/snapshots/asm/fn_ptr_ternary_call_return.x64.asm @@ -29,25 +29,21 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) movabsq $0x123456789, %rbx # imm = 0x123456789 leaq -, %rcx # - jmp - leaq -, %rcx # movq %rcx, %rax movq %rbx, %rdi callq *%rax movq %rax, %r13 leaq -, %rcx # - jmp - leaq -, %rcx # movabsq $0x1234567890, %rdi # imm = 0x1234567890 movq %rcx, %rax callq *%rax - movq %rax, %r12 + movq %rax, %rdx cmpq %rbx, %r13 je leaq , %rdi @@ -59,15 +55,15 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq movabsq $0x1234567891, %r11 # imm = 0x1234567891 - movq %r12, %rax - cmpq %r11, %r12 + movq %rdx, %rax + cmpq %r11, %rdx je leaq , %rdi - movq %r12, %rsi + movq %rdx, %rsi movb $0x0, %al callq movslq %eax, %rax @@ -75,12 +71,11 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq leaq , %rdi movq %r13, %rsi - movq %r12, %rdx movb $0x0, %al callq movslq %eax, %rax @@ -88,7 +83,12 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq + leaq -, %rcx # + jmp + leaq -, %rcx # + jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_typedef_multi_declarator.aarch64.asm b/tests/snapshots/asm/fn_ptr_typedef_multi_declarator.aarch64.asm index 5a7f5d34b..4fc16e402 100644 --- a/tests/snapshots/asm/fn_ptr_typedef_multi_declarator.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_typedef_multi_declarator.aarch64.asm @@ -19,12 +19,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x80]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 adrp x20, add x20, x20, adrp x21, @@ -37,11 +35,9 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret mov x9, x21 blr x9 @@ -51,47 +47,35 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret mov x0, #0x0 // =0 stur w0, [x29, #-0x28] adrp x21, add x21, x21, sub x0, x29, #0x28 - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sub x1, x29, #0x28 cmp x0, x1 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret sub x0, x29, #0x28 - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sub x1, x29, #0x28 cmp x0, x1 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret sub x0, x29, #0x38 str x20, [x0] @@ -107,11 +91,9 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret sub x0, x29, #0x38 ldr x0, [x0, #0x8] @@ -123,16 +105,12 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x80 ret diff --git a/tests/snapshots/asm/fn_returning_fn_ptr.aarch64.asm b/tests/snapshots/asm/fn_returning_fn_ptr.aarch64.asm index 825fff43e..b309417b5 100644 --- a/tests/snapshots/asm/fn_returning_fn_ptr.aarch64.asm +++ b/tests/snapshots/asm/fn_returning_fn_ptr.aarch64.asm @@ -15,93 +15,73 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 cbz x0, adrp x1, add x1, x1, - b - mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x0 // =0 + b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x1 // =1 bl mov x1, #0x7 // =7 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x4 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x1 // =1 bl mov x1, #0xa // =10 mov x2, #0x6 // =6 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x4 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 bl cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x1 // =1 bl mov x1, #0x9 // =9 mov x2, #0x2 // =2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/fn_returning_fn_ptr.x64.asm b/tests/snapshots/asm/fn_returning_fn_ptr.x64.asm index 22dd65627..b1b970c39 100644 --- a/tests/snapshots/asm/fn_returning_fn_ptr.x64.asm +++ b/tests/snapshots/asm/fn_returning_fn_ptr.x64.asm @@ -17,24 +17,18 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi testq %rdi, %rdi je leaq -, %rcx # - jmp - xorq %rcx, %rcx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq + xorq %rcx, %rcx + jmp
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp movl $0x1, %edi callq movl $0x7, %edi @@ -44,7 +38,6 @@ Disassembly of section .text: cmpq $0x4, %rax je movl $0x1, %eax - addq $0x50, %rsp popq %rbp retq movl $0x1, %edi @@ -56,7 +49,6 @@ Disassembly of section .text: cmpq $0x4, %rax je movl $0x2, %eax - addq $0x50, %rsp popq %rbp retq xorq %rdi, %rdi @@ -64,7 +56,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x50, %rsp popq %rbp retq movl $0x1, %edi @@ -76,11 +67,9 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x4, %eax - addq $0x50, %rsp popq %rbp retq xorq %rax, %rax - addq $0x50, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_type_typedef_cast.aarch64.asm b/tests/snapshots/asm/fn_type_typedef_cast.aarch64.asm index ce71efcab..22052c61b 100644 --- a/tests/snapshots/asm/fn_type_typedef_cast.aarch64.asm +++ b/tests/snapshots/asm/fn_type_typedef_cast.aarch64.asm @@ -36,9 +36,9 @@ Disassembly of section .text: cmp x0, x1 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/fn_type_typedef_cast.x64.asm b/tests/snapshots/asm/fn_type_typedef_cast.x64.asm index f94365224..829fa98dc 100644 --- a/tests/snapshots/asm/fn_type_typedef_cast.x64.asm +++ b/tests/snapshots/asm/fn_type_typedef_cast.x64.asm @@ -38,9 +38,9 @@ Disassembly of section .text: cmpq %rcx, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/fn_type_typedef_field.aarch64.asm b/tests/snapshots/asm/fn_type_typedef_field.aarch64.asm index 57b561f3d..d2151e8ac 100644 --- a/tests/snapshots/asm/fn_type_typedef_field.aarch64.asm +++ b/tests/snapshots/asm/fn_type_typedef_field.aarch64.asm @@ -38,12 +38,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0xc0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 sub x0, x29, #0x8 adrp x20, add x20, x20, @@ -66,19 +64,17 @@ Disassembly of section .text: sub x0, x29, #0x20 ldr x0, [x0] cmp x0, #0x7 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x20 ldr x0, [x0, #0x8] cmp x0, #0xe - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xc0 ret sub x0, x29, #0x8 str x20, [x0] @@ -111,18 +107,14 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xc0 ret b b diff --git a/tests/snapshots/asm/fn_type_typedef_field.x64.asm b/tests/snapshots/asm/fn_type_typedef_field.x64.asm index f74dd78ec..7ddfaf56e 100644 --- a/tests/snapshots/asm/fn_type_typedef_field.x64.asm +++ b/tests/snapshots/asm/fn_type_typedef_field.x64.asm @@ -64,16 +64,16 @@ Disassembly of section .text: leaq -0x20(%rbp), %rax movq (%rax), %rax cmpq $0x7, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x20(%rbp), %rax movq 0x8(%rax), %rax cmpq $0xe, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax movq (%rsp), %rbx diff --git a/tests/snapshots/asm/fn_type_typedef_local.aarch64.asm b/tests/snapshots/asm/fn_type_typedef_local.aarch64.asm index aa865ea2f..9a24738bf 100644 --- a/tests/snapshots/asm/fn_type_typedef_local.aarch64.asm +++ b/tests/snapshots/asm/fn_type_typedef_local.aarch64.asm @@ -38,12 +38,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x21, [sp, #0x8] + str x20, [sp, #-0xc0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 adrp x20, add x20, x20, mov x0, #0x7 // =7 @@ -64,19 +62,17 @@ Disassembly of section .text: sub x0, x29, #0x18 ldr x0, [x0] cmp x0, #0x7 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x18 ldr x0, [x0, #0x8] cmp x0, #0xe - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret mov x0, #0x3 // =3 mov x9, x20 @@ -89,11 +85,9 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret stur x20, [x29, #-0x28] mov x0, #0x4 // =4 @@ -108,11 +102,9 @@ Disassembly of section .text: cmp x0, #0x8 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x28 ldr x0, [x0] @@ -128,17 +120,13 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret b diff --git a/tests/snapshots/asm/fn_type_typedef_local.x64.asm b/tests/snapshots/asm/fn_type_typedef_local.x64.asm index ced9493b5..4553c37d7 100644 --- a/tests/snapshots/asm/fn_type_typedef_local.x64.asm +++ b/tests/snapshots/asm/fn_type_typedef_local.x64.asm @@ -43,7 +43,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0xa0, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) leaq -, %rbx # movl $0x7, %edi movq %rbx, %rax @@ -62,20 +61,19 @@ Disassembly of section .text: leaq -0x18(%rbp), %rax movq (%rax), %rax cmpq $0x7, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x18(%rbp), %rax movq 0x8(%rax), %rax cmpq $0xe, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0xa0, %rsp popq %rbp retq @@ -90,7 +88,6 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0xa0, %rsp popq %rbp retq @@ -106,7 +103,6 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0xa0, %rsp popq %rbp retq @@ -122,14 +118,13 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0xa0, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0xa0, %rsp popq %rbp retq jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/fnptr_param_indirection.aarch64.asm b/tests/snapshots/asm/fnptr_param_indirection.aarch64.asm index 4f5a7d96c..814f42b64 100644 --- a/tests/snapshots/asm/fnptr_param_indirection.aarch64.asm +++ b/tests/snapshots/asm/fnptr_param_indirection.aarch64.asm @@ -29,11 +29,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + str x20, [sp, #-0x70]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x0, #0x0 // =0 stur x0, [x29, #-0x8] sub x0, x29, #0x8 @@ -47,26 +46,21 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0xb // =11 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0xa // =10 ldur x1, [x29, #-0x8] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0xb b.eq mov x0, #0xc // =12 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret adrp x0, add x0, x0, @@ -76,25 +70,20 @@ Disassembly of section .text: cmp x1, x0 b.eq mov x0, #0xd // =13 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0xa // =10 - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x14 b.eq mov x0, #0xe // =14 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0x0 // =0 stur x0, [x29, #-0x20] @@ -106,25 +95,20 @@ Disassembly of section .text: cbnz x1, mov x0, #0x3 // =3 ldur x1, [x29, #-0x20] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x4 cset x1, ne cbz x1, mov x0, #0xf // =15 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret b diff --git a/tests/snapshots/asm/fnptr_typedef_return_proto.aarch64.asm b/tests/snapshots/asm/fnptr_typedef_return_proto.aarch64.asm index a444ea863..a0d8f22c9 100644 --- a/tests/snapshots/asm/fnptr_typedef_return_proto.aarch64.asm +++ b/tests/snapshots/asm/fnptr_typedef_return_proto.aarch64.asm @@ -25,29 +25,24 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x14 // =20 mov x2, #0x16 // =22 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x2a b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/fnptr_typedef_return_proto.x64.asm b/tests/snapshots/asm/fnptr_typedef_return_proto.x64.asm index d9fa1d747..3223191b7 100644 --- a/tests/snapshots/asm/fnptr_typedef_return_proto.x64.asm +++ b/tests/snapshots/asm/fnptr_typedef_return_proto.x64.asm @@ -26,7 +26,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp leaq -, %rax # movl $0x14, %edi movl $0x16, %esi @@ -35,9 +34,9 @@ Disassembly of section .text: cmpq $0x2a, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/for_init_decl_in_loop.aarch64.asm b/tests/snapshots/asm/for_init_decl_in_loop.aarch64.asm index 6d837689a..0e5bbbff1 100644 --- a/tests/snapshots/asm/for_init_decl_in_loop.aarch64.asm +++ b/tests/snapshots/asm/for_init_decl_in_loop.aarch64.asm @@ -12,29 +12,77 @@ Disassembly of section .text: brk #: mov x2, #0x0 // =0 mov x1, #0x1 // =1 - sxtw x0, w1 - cmp x0, #0x5 - b.ge b - sxtw x0, w1 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x0 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x1 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x2 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x3 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x5 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x6 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x7 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x8 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0x9 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xa + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xb + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xc + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xd + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xe + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x1, x17 + add x3, x3, #0xf + add x2, x2, x3 add x1, x0, #0x1 - b - mov x3, #0x0 // =0 - b + sxtw x0, w1 + cmp x0, #0x5 + b.lt sxtw x0, w2 ret - sxtw x0, w3 - cmp x0, #0x10 - b.ge - b - sxtw x0, w3 - add x3, x0, #0x1 - b - mov x17, #0x64 // =100 - mul x0, x1, x17 - add x0, x0, x3 - add x2, x2, x0 - b b
: diff --git a/tests/snapshots/asm/for_init_decl_in_loop.x64.asm b/tests/snapshots/asm/for_init_decl_in_loop.x64.asm index e0a268380..d0c5de9ae 100644 --- a/tests/snapshots/asm/for_init_decl_in_loop.x64.asm +++ b/tests/snapshots/asm/for_init_decl_in_loop.x64.asm @@ -13,28 +13,61 @@ Disassembly of section .text: : xorq %rdx, %rdx movl $0x1, %ecx - movslq %ecx, %rax - cmpq $0x5, %rax - jge jmp - movslq %ecx, %rax + imulq $0x64, %rcx, %rsi + addq $0x0, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + incq %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x2, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x3, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x5, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x6, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x7, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x8, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0x9, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xa, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xb, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xc, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xd, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xe, %rsi + addq %rsi, %rdx + imulq $0x64, %rcx, %rsi + addq $0xf, %rsi + addq %rsi, %rdx leaq 0x1(%rax), %rcx - jmp - xorq %rsi, %rsi - jmp + movslq %ecx, %rax + cmpq $0x5, %rax + jl movslq %edx, %rax retq - movslq %esi, %rax - cmpq $0x10, %rax - jge - jmp - movslq %esi, %rax - leaq 0x1(%rax), %rsi - jmp - imulq $0x64, %rcx, %rax - addq %rsi, %rax - addq %rax, %rdx - jmp jmp
: @@ -50,3 +83,4 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/for_init_declaration.aarch64.asm b/tests/snapshots/asm/for_init_declaration.aarch64.asm index 46c063053..4403af6dc 100644 --- a/tests/snapshots/asm/for_init_declaration.aarch64.asm +++ b/tests/snapshots/asm/for_init_declaration.aarch64.asm @@ -10,86 +10,22 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w1 - cmp x2, #0xa - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - add x0, x0, x1 - b - sxtw x0, w0 + mov x0, #0x2d // =45 ret : - mov x2, #0x0 // =0 - mov x1, #0xa // =10 - mov x0, x2 - sxtw x3, w2 - sxtw x4, w1 - cmp x3, x4 - b.ge - b - add x2, x2, #0x1 - sxtw x1, w1 - sub x1, x1, #0x1 - b - add x3, x2, x1 - add x0, x0, x3 - b - sxtw x0, w0 + mov x0, #0x32 // =50 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x2a // =42 - mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, #0x3 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 - b - b - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w1 - cmp x2, #0x5 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - add x0, x0, x1 - b - mov x2, #0xa // =10 - sxtw x1, w2 - cmp x1, #0xd - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 - b - add x0, x0, x2 - b - sxtw x0, w0 + mov x0, #0x2b // =43 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, mov x3, #0x0 // =0 @@ -100,26 +36,21 @@ Disassembly of section .text: str w2, [x0, #0x4] str w1, [x0, #0x8] mov x1, x0 - add x2, x0, #0xc - cmp x1, x2 - b.ge - b - add x1, x1, #0x4 b ldrsw x2, [x1] add x3, x3, x2 - b + add x1, x1, #0x4 + add x2, x0, #0xc + cmp x1, x2 + b.lt sxtw x0, w3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 bl cmp x0, #0x2d b.eq @@ -131,10 +62,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl cmp x0, #0x32 @@ -147,10 +77,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl cmp x0, #0x2a @@ -163,10 +92,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl cmp x0, #0x2b @@ -179,10 +107,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl cmp x0, #0x7 @@ -195,14 +122,12 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/for_init_declaration.x64.asm b/tests/snapshots/asm/for_init_declaration.x64.asm index 63f9cc919..7c9010bc8 100644 --- a/tests/snapshots/asm/for_init_declaration.x64.asm +++ b/tests/snapshots/asm/for_init_declaration.x64.asm @@ -11,86 +11,22 @@ Disassembly of section .text: ud2 : - xorq %rcx, %rcx - movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0xa, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - addq %rcx, %rax - jmp - movslq %eax, %rax + movl $0x2d, %eax retq : - xorq %rdx, %rdx - movl $0xa, %ecx - movq %rdx, %rax - movslq %edx, %rsi - movslq %ecx, %rdi - cmpq %rdi, %rsi - jge - jmp - incq %rdx - movslq %ecx, %rcx - decq %rcx - jmp - leaq (%rdx,%rcx), %rsi - addq %rsi, %rax - jmp - movslq %eax, %rax + movl $0x32, %eax retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0x2a, %eax - xorq %rdx, %rdx - movslq %edx, %rcx - cmpq $0x3, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx - jmp - jmp - addq $0x10, %rsp - popq %rbp retq : - xorq %rcx, %rcx - movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x5, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - addq %rcx, %rax - jmp - movl $0xa, %edx - movslq %edx, %rcx - cmpq $0xd, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx - jmp - addq %rdx, %rax - jmp - movslq %eax, %rax + movl $0x2b, %eax retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax xorq %rsi, %rsi movl $0x1, %ecx @@ -100,18 +36,14 @@ Disassembly of section .text: movl %edx, 0x4(%rax) movl %ecx, 0x8(%rax) movq %rax, %rcx - leaq 0xc(%rax), %rdx - cmpq %rdx, %rcx - jge - jmp - addq $0x4, %rcx jmp movslq (%rcx), %rdx addq %rdx, %rsi - jmp + addq $0x4, %rcx + leaq 0xc(%rax), %rdx + cmpq %rdx, %rcx + jl movslq %esi, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -199,4 +131,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/for_init_multiple_declarators.aarch64.asm b/tests/snapshots/asm/for_init_multiple_declarators.aarch64.asm index d98224fc6..0b11af577 100644 --- a/tests/snapshots/asm/for_init_multiple_declarators.aarch64.asm +++ b/tests/snapshots/asm/for_init_multiple_declarators.aarch64.asm @@ -10,87 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - mov x2, #0x0 // =0 - mov x0, #0x3 // =3 - mov x1, x2 - sxtw x3, w2 - cmp x3, x0 - b.ge - b - sxtw x2, w2 - add x2, x2, #0x1 - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sxtw x0, w1 - cmp x0, #0x3 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret - mov x3, #0x0 // =0 - mov x0, #0x4 // =4 - mov x1, #0x2 // =2 - mov x2, x3 - sxtw x4, w3 - cmp x4, x0 - b.ge - b - sxtw x3, w3 - add x3, x3, #0x1 - b - add x2, x2, x1 - b - sxtw x0, w2 - cmp x0, #0x8 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret - mov x2, #0x1 // =1 - mov x0, #0x5 // =5 - mov x1, x2 - cmp x2, x0 - b.gt - b - add x2, x2, #0x1 - b - mul x1, x1, x2 - b - cmp x1, #0x78 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret - mov x3, #0x0 // =0 - mov x2, #0x2 // =2 - add x0, x2, #0x3 - sxtw x0, w0 - sxtw x1, w2 - cmp x1, x0 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 - b - sxtw x1, w3 - add x3, x1, #0x1 - b - sxtw x0, w3 - cmp x0, #0x3 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/for_init_multiple_declarators.x64.asm b/tests/snapshots/asm/for_init_multiple_declarators.x64.asm index c13dd3ed9..ab8f72255 100644 --- a/tests/snapshots/asm/for_init_multiple_declarators.x64.asm +++ b/tests/snapshots/asm/for_init_multiple_declarators.x64.asm @@ -11,88 +11,13 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x70, %rsp - xorq %rdx, %rdx - movl $0x3, %eax - movq %rdx, %rcx - movslq %edx, %rsi - cmpq %rax, %rsi - jge - jmp - movslq %edx, %rdx - incq %rdx - jmp - movslq %ecx, %rcx - incq %rcx - jmp - movslq %ecx, %rax - cmpq $0x3, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x70, %rsp - popq %rbp retq - xorq %rsi, %rsi - movl $0x4, %eax - movl $0x2, %ecx - movq %rsi, %rdx - movslq %esi, %rdi - cmpq %rax, %rdi - jge - jmp - movslq %esi, %rsi - incq %rsi - jmp - addq %rcx, %rdx - jmp - movslq %edx, %rax - cmpq $0x8, %rax - je movl $0x2, %eax - addq $0x70, %rsp - popq %rbp retq - movl $0x1, %edx - movl $0x5, %eax - movq %rdx, %rcx - cmpq %rax, %rdx - jg - jmp - incq %rdx - jmp - imulq %rdx, %rcx - jmp - cmpq $0x78, %rcx - je movl $0x3, %eax - addq $0x70, %rsp - popq %rbp retq - xorq %rsi, %rsi - movl $0x2, %edx - leaq 0x3(%rdx), %rax - movslq %eax, %rax - movslq %edx, %rcx - cmpq %rax, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx - jmp - movslq %esi, %rcx - leaq 0x1(%rcx), %rsi - jmp - movslq %esi, %rax - cmpq $0x3, %rax - je movl $0x4, %eax - addq $0x70, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x70, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/for_loop.aarch64.asm b/tests/snapshots/asm/for_loop.aarch64.asm index 17a85aff4..c0d46dfcf 100644 --- a/tests/snapshots/asm/for_loop.aarch64.asm +++ b/tests/snapshots/asm/for_loop.aarch64.asm @@ -10,17 +10,5 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w0 - cmp x2, #0x5 - b.ge - b - sxtw x0, w0 - add x0, x0, #0x1 - b - add x1, x1, x0 - sxtw x1, w1 - b - sxtw x0, w1 + mov x0, #0xa // =10 ret diff --git a/tests/snapshots/asm/for_loop.x64.asm b/tests/snapshots/asm/for_loop.x64.asm index e3f65c4b5..afdfa414b 100644 --- a/tests/snapshots/asm/for_loop.x64.asm +++ b/tests/snapshots/asm/for_loop.x64.asm @@ -11,17 +11,6 @@ Disassembly of section .text: ud2
: - xorq %rcx, %rcx - movq %rcx, %rax - movslq %eax, %rdx - cmpq $0x5, %rdx - jge - jmp - movslq %eax, %rax - incq %rax - jmp - addq %rax, %rcx - movslq %ecx, %rcx - jmp - movslq %ecx, %rax + movl $0xa, %eax retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/for_loop_call_body_and_step.aarch64.asm b/tests/snapshots/asm/for_loop_call_body_and_step.aarch64.asm index 7fe9f5650..d3300e7b3 100644 --- a/tests/snapshots/asm/for_loop_call_body_and_step.aarch64.asm +++ b/tests/snapshots/asm/for_loop_call_body_and_step.aarch64.asm @@ -22,16 +22,14 @@ Disassembly of section .text: : mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - cmp x2, #0x7 - b.ge - b - add x1, x1, #0x1 - sxtw x1, w1 b add x0, x0, #0x1 sxtw x0, w0 - b + add x1, x1, #0x1 + sxtw x1, w1 + sxtw x2, w1 + cmp x2, #0x7 + b.lt mov x17, #0x6 // =6 mul x0, x0, x17 sxtw x0, w0 diff --git a/tests/snapshots/asm/for_loop_call_body_and_step.x64.asm b/tests/snapshots/asm/for_loop_call_body_and_step.x64.asm index c4307ea13..ef6a30475 100644 --- a/tests/snapshots/asm/for_loop_call_body_and_step.x64.asm +++ b/tests/snapshots/asm/for_loop_call_body_and_step.x64.asm @@ -23,16 +23,14 @@ Disassembly of section .text: : xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x7, %rdx - jge - jmp - incq %rcx - movslq %ecx, %rcx jmp incq %rax movslq %eax, %rax - jmp + incq %rcx + movslq %ecx, %rcx + movslq %ecx, %rdx + cmpq $0x7, %rdx + jl imulq $0x6, %rax, %rax movslq %eax, %rax retq diff --git a/tests/snapshots/asm/forge_code_pointer.aarch64.asm b/tests/snapshots/asm/forge_code_pointer.aarch64.asm index c1779ed6b..d6526d65b 100644 --- a/tests/snapshots/asm/forge_code_pointer.aarch64.asm +++ b/tests/snapshots/asm/forge_code_pointer.aarch64.asm @@ -10,19 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x2a // =42 mov x1, #0x0 // =0 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/forge_code_pointer.x64.asm b/tests/snapshots/asm/forge_code_pointer.x64.asm index 808c89ffa..e3e12c41c 100644 --- a/tests/snapshots/asm/forge_code_pointer.x64.asm +++ b/tests/snapshots/asm/forge_code_pointer.x64.asm @@ -13,13 +13,10 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x2a, %eax xorq %rdi, %rdi callq *%rax movslq %eax, %rax - addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/forward_fn_ptr_in_static_init.aarch64.asm b/tests/snapshots/asm/forward_fn_ptr_in_static_init.aarch64.asm index 58e057527..9a9946431 100644 --- a/tests/snapshots/asm/forward_fn_ptr_in_static_init.aarch64.asm +++ b/tests/snapshots/asm/forward_fn_ptr_in_static_init.aarch64.asm @@ -26,24 +26,20 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 sxtw x1, w1 adrp x2, add x2, x2, ldr x0, [x2, x0, lsl #3] - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/fp_arg_passed_in_fp_reg.aarch64.asm b/tests/snapshots/asm/fp_arg_passed_in_fp_reg.aarch64.asm index a1d22d0b1..972634802 100644 --- a/tests/snapshots/asm/fp_arg_passed_in_fp_reg.aarch64.asm +++ b/tests/snapshots/asm/fp_arg_passed_in_fp_reg.aarch64.asm @@ -41,17 +41,15 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3 // =3 - mov x1, #0x3ff8000000000000 // =4609434218613702656 - mov x2, #0x4 // =4 - mov x3, #0x4004000000000000 // =4612811918334230528 - sxtw x0, w0 - sxtw x2, w2 - scvtf d0, x0 - scvtf d1, x2 - fmov d16, x3 - fmul d1, d16, d1 + mov x0, #0x3ff8000000000000 // =4609434218613702656 + mov x1, #0x4004000000000000 // =4612811918334230528 + mov x2, #0x3 // =3 + mov x3, #0x4 // =4 + scvtf d0, x2 + scvtf d1, x3 fmov d16, x1 + fmul d1, d16, d1 + fmov d16, x0 fmadd d0, d16, d0, d1 mov x0, #0x402d000000000000 // =4624352392379367424 fmov d17, x0 diff --git a/tests/snapshots/asm/fp_arg_passed_in_fp_reg.x64.asm b/tests/snapshots/asm/fp_arg_passed_in_fp_reg.x64.asm index 0e83eb5ac..fc96ccc7f 100644 --- a/tests/snapshots/asm/fp_arg_passed_in_fp_reg.x64.asm +++ b/tests/snapshots/asm/fp_arg_passed_in_fp_reg.x64.asm @@ -52,18 +52,16 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movl $0x3, %eax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 - movl $0x4, %edx - movabsq $0x4004000000000000, %rsi # imm = 0x4004000000000000 - movslq %eax, %rax - movslq %edx, %rdx - cvtsi2sd %rax, %xmm0 - cvtsi2sd %rdx, %xmm1 + movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movabsq $0x4004000000000000, %rcx # imm = 0x4004000000000000 + movl $0x3, %edx + movl $0x4, %esi + cvtsi2sd %rdx, %xmm0 + cvtsi2sd %rsi, %xmm1 movapd %xmm1, %xmm15 - movq %rsi, %xmm1 + movq %rcx, %xmm1 mulsd %xmm15, %xmm1 - movq %rcx, %xmm14 + movq %rax, %xmm14 movapd %xmm0, %xmm15 movapd %xmm1, %xmm0 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 @@ -107,3 +105,4 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/fp_const_return.aarch64.asm b/tests/snapshots/asm/fp_const_return.aarch64.asm index 389391b90..a7717ffbd 100644 --- a/tests/snapshots/asm/fp_const_return.aarch64.asm +++ b/tests/snapshots/asm/fp_const_return.aarch64.asm @@ -18,20 +18,16 @@ Disassembly of section .text: fmov d16, x3 sub x17, x29, #0x8 str d16, [x17] - sxtw x2, w3 - cmp x2, x1 - b.ge - b - sxtw x2, w3 - add x3, x2, #0x1 b - sxtw x2, w3 - lsl x2, x2, #3 - add x2, x0, x2 - ldr d0, [x2] + lsl x4, x2, #3 + add x4, x0, x4 + ldr d0, [x4] sub x17, x29, #0x8 str d0, [x17] - b + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, x1 + b.lt sub x16, x29, #0x8 ldr d0, [x16] add sp, sp, #0x10 @@ -54,49 +50,36 @@ Disassembly of section .text: ret : - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3e800000 // =1048576000 + fmov d0, x0 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x1 sxtw x2, w2 sxtw x1, w2 cmp x1, #0x0 - cset x3, gt - cbz x3, - b - sxtw x1, w2 + cset x4, gt + cbz x4, + sub x3, x2, #0x1 + sxtw x3, w3 + ldr x3, [x0, x3, lsl #3] + cmp x3, #0x0 + cset x4, eq + cbz x4, sub x2, x1, #0x1 b - sxtw x1, w2 - cmp x1, #0x0 - b.ne b - sub x1, x2, #0x1 - sxtw x1, w1 - ldr x1, [x0, x1, lsl #3] cmp x1, #0x0 - cset x3, eq - cbz x3, - b + b.ne mov x0, #0x0 // =0 fmov d0, x0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret sub x1, x2, #0x1 sxtw x1, w1 ldr x0, [x0, x1, lsl #3] scvtf d0, x0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - b
: stp x29, x30, [sp, #-0x10]! @@ -177,10 +160,9 @@ Disassembly of section .text: sub x0, x29, #0x10 mov x1, #0x2 // =2 bl - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 + mov x0, #0x3e800000 // =1048576000 + fmov s16, w0 + fcvt d0, s16 mov x0, #0x3fd0000000000000 // =4598175219545276416 fmov d17, x0 fcmp d0, d17 diff --git a/tests/snapshots/asm/fp_const_return.x64.asm b/tests/snapshots/asm/fp_const_return.x64.asm index 78b7fdb33..fe45df9ae 100644 --- a/tests/snapshots/asm/fp_const_return.x64.asm +++ b/tests/snapshots/asm/fp_const_return.x64.asm @@ -18,19 +18,16 @@ Disassembly of section .text: xorq %rcx, %rcx movq %rcx, %xmm14 movsd %xmm14, -0x8(%rbp,%riz) - movslq %ecx, %rax - cmpq %rsi, %rax - jge jmp - movslq %ecx, %rax + movq %rax, %rdx + shlq $0x3, %rdx + addq %rdi, %rdx + movsd (%rdx,%riz), %xmm0 + movsd %xmm0, -0x8(%rbp,%riz) leaq 0x1(%rax), %rcx - jmp movslq %ecx, %rax - shlq $0x3, %rax - addq %rdi, %rax - movsd (%rax,%riz), %xmm0 - movsd %xmm0, -0x8(%rbp,%riz) - jmp + cmpq %rsi, %rax + jl movsd -0x8(%rbp,%riz), %xmm0 addq $0x10, %rsp popq %rbp @@ -55,53 +52,41 @@ Disassembly of section .text: retq : - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3e800000, %eax # imm = 0x3E800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movapd %xmm14, %xmm0 retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %esi, %rsi movslq %esi, %rax testq %rax, %rax - setg %cl - movzbq %cl, %rcx + setg %dl + movzbq %dl, %rdx + testq %rdx, %rdx + je + leaq -0x1(%rsi), %rcx + movslq %ecx, %rcx + movq (%rdi,%rcx,8), %rcx testq %rcx, %rcx + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx je - jmp - movslq %esi, %rax leaq -0x1(%rax), %rsi jmp - movslq %esi, %rax - testq %rax, %rax - jne jmp - leaq -0x1(%rsi), %rax - movslq %eax, %rax - movq (%rdi,%rax,8), %rax testq %rax, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - jmp + jne xorq %rax, %rax movq %rax, %xmm14 movapd %xmm14, %xmm0 - addq $0x10, %rsp - popq %rbp retq leaq -0x1(%rsi), %rax movslq %eax, %rax movq (%rdi,%rax,8), %rax cvtsi2sd %rax, %xmm0 - addq $0x10, %rsp - popq %rbp retq - jmp
: pushq %rbp @@ -195,10 +180,9 @@ Disassembly of section .text: leaq -0x10(%rbp), %rdi movl $0x2, %esi callq - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3e800000, %eax # imm = 0x3E800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 diff --git a/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm b/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm index e27ae1726..73a3b2902 100644 --- a/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm +++ b/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm @@ -41,31 +41,28 @@ Disassembly of section .text: movk x1, #0xffff, lsl #48 str x1, [x0] sub x0, x29, #0x28 - mov x1, #0x3ff4000000000000 // =4608308318706860032 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0, #0x8] + mov x1, #0x3fa00000 // =1067450368 + fmov s16, w1 + str s16, [x0, #0x8] sub x0, x29, #0x28 mov x2, #0x4004000000000000 // =4612811918334230528 fmov d16, x2 str d16, [x0, #0x10] sub x0, x29, #0x28 mov x2, #0x0 // =0 - fmov d16, x2 - fcvt s0, d16 - str s0, [x0, #0x18] + fmov s16, w2 + str s16, [x0, #0x18] sub x0, x29, #0x28 - str s0, [x0, #0x1c] + fmov s16, w2 + str s16, [x0, #0x1c] sub x0, x29, #0x28 - mov x2, #0x4013000000000000 // =4617034042984890368 - fmov d16, x2 - fcvt s0, d16 - str s0, [x0, #0x20] + mov x2, #0x40980000 // =1083703296 + fmov s16, w2 + str s16, [x0, #0x20] sub x0, x29, #0x28 ldr s0, [x0, #0x8] - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -85,10 +82,9 @@ Disassembly of section .text: ret sub x0, x29, #0x28 ldr s0, [x0, #0x20] - mov x0, #0x4013000000000000 // =4617034042984890368 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40980000 // =1083703296 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/fp_load_folded_disp.x64.asm b/tests/snapshots/asm/fp_load_folded_disp.x64.asm index e20c64f57..e8f521500 100644 --- a/tests/snapshots/asm/fp_load_folded_disp.x64.asm +++ b/tests/snapshots/asm/fp_load_folded_disp.x64.asm @@ -39,10 +39,9 @@ Disassembly of section .text: movabsq $-0x1, %rcx movq %rcx, (%rax) leaq -0x28(%rbp), %rax - movabsq $0x3ff4000000000000, %rcx # imm = 0x3FF4000000000000 + movl $0x3fa00000, %ecx # imm = 0x3FA00000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x8(%rax,%riz) + movss %xmm14, 0x8(%rax,%riz) leaq -0x28(%rbp), %rax movabsq $0x4004000000000000, %rdx # imm = 0x4004000000000000 movq %rdx, %xmm14 @@ -50,20 +49,18 @@ Disassembly of section .text: leaq -0x28(%rbp), %rax xorq %rdx, %rdx movq %rdx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x18(%rax,%riz) + movss %xmm14, 0x18(%rax,%riz) leaq -0x28(%rbp), %rax - movss %xmm0, 0x1c(%rax,%riz) + movq %rdx, %xmm14 + movss %xmm14, 0x1c(%rax,%riz) leaq -0x28(%rbp), %rax - movabsq $0x4013000000000000, %rdx # imm = 0x4013000000000000 + movl $0x40980000, %edx # imm = 0x40980000 movq %rdx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x20(%rax,%riz) + movss %xmm14, 0x20(%rax,%riz) leaq -0x28(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -93,10 +90,9 @@ Disassembly of section .text: retq leaq -0x28(%rbp), %rax movss 0x20(%rax,%riz), %xmm0 - movabsq $0x4013000000000000, %rax # imm = 0x4013000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40980000, %eax # imm = 0x40980000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -131,4 +127,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_param_after_int_overflow.aarch64.asm b/tests/snapshots/asm/fp_param_after_int_overflow.aarch64.asm index 585330d83..ee9a09acf 100644 --- a/tests/snapshots/asm/fp_param_after_int_overflow.aarch64.asm +++ b/tests/snapshots/asm/fp_param_after_int_overflow.aarch64.asm @@ -38,7 +38,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x70 mov x0, #0x1 // =1 mov x1, #0x2 // =2 mov x2, #0x3 // =3 @@ -61,7 +60,6 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0xa // =10 @@ -86,10 +84,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/fp_param_after_int_overflow.x64.asm b/tests/snapshots/asm/fp_param_after_int_overflow.x64.asm index 84ab4b091..7ab9ee95c 100644 --- a/tests/snapshots/asm/fp_param_after_int_overflow.x64.asm +++ b/tests/snapshots/asm/fp_param_after_int_overflow.x64.asm @@ -48,7 +48,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -85,7 +85,7 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq movl $0xa, %edi @@ -120,7 +120,7 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq xorq %rax, %rax @@ -128,7 +128,7 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm b/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm index 8db5ed786..40070bcdc 100644 --- a/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm +++ b/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm @@ -10,82 +10,58 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fcvt d0, s1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fcvt d0, s0 fadd d0, d0, d1 fcvt d1, s2 fadd d0, d0, d1 fadd d0, d0, d3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x4024000000000000 // =4621819117588971520 fcvt d1, s1 fmov d17, x0 fmadd d0, d0, d17, d1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 ret - mov x0, #0x401a000000000000 // =4619004367821864960 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40d00000 // =1087373312 + fmov s16, w0 + fcvt d0, s16 + fmov s16, w0 + fcvt d1, s16 + fcmp d0, d1 cset x0, ne cbz x0, mov x0, #0x2 // =2 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x4000000000000000 // =4611686018427387904 + mov x2, #0x40400000 // =1077936128 + mov x3, #0x4010000000000000 // =4616189618054758400 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fadd d0, d0, d17 - fcvt d1, s1 + fmov s16, w2 + fcvt d1, s16 fadd d0, d0, d1 - fmov d17, x1 + fmov d17, x3 fadd d0, d0, d17 mov x0, #0x4024000000000000 // =4621819117588971520 fmov d17, x0 @@ -95,13 +71,12 @@ Disassembly of section .text: mov x0, #0x3 // =3 ret mov x0, #0x4014000000000000 // =4617315517961601024 - mov x1, #0x4018000000000000 // =4618441417868443648 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 + mov x1, #0x40c00000 // =1086324736 + mov x2, #0x4024000000000000 // =4621819117588971520 + fmov s16, w1 + fcvt d0, s16 fmov d16, x0 - fmov d17, x1 + fmov d17, x2 fmadd d0, d16, d17, d0 mov x0, #0x404c000000000000 // =4633078116657397760 fmov d17, x0 diff --git a/tests/snapshots/asm/fp_param_float_before_double.x64.asm b/tests/snapshots/asm/fp_param_float_before_double.x64.asm index e5973e9d2..1d5166be3 100644 --- a/tests/snapshots/asm/fp_param_float_before_double.x64.asm +++ b/tests/snapshots/asm/fp_param_float_before_double.x64.asm @@ -11,56 +11,34 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp cvtss2sd %xmm1, %xmm0 - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 cvtss2sd %xmm2, %xmm1 addsd %xmm1, %xmm0 addsd %xmm3, %xmm0 - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 cvtss2sd %xmm1, %xmm1 movapd %xmm0, %xmm14 movq %rax, %xmm15 movapd %xmm1, %xmm0 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - addq $0x10, %rsp - popq %rbp retq
: - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -70,12 +48,12 @@ Disassembly of section .text: je movl $0x1, %eax retq - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + cvtss2sd %xmm14, %xmm0 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + ucomisd %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -85,20 +63,18 @@ Disassembly of section .text: je movl $0x2, %eax retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 + movl $0x40400000, %edx # imm = 0x40400000 + movabsq $0x4010000000000000, %rsi # imm = 0x4010000000000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 - cvtss2sd %xmm1, %xmm1 + movq %rdx, %xmm14 + cvtss2sd %xmm14, %xmm1 addsd %xmm1, %xmm0 - movq %rcx, %xmm15 + movq %rsi, %xmm15 addsd %xmm15, %xmm0 movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 movq %rax, %xmm15 @@ -113,13 +89,12 @@ Disassembly of section .text: movl $0x3, %eax retq movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movabsq $0x4018000000000000, %rcx # imm = 0x4018000000000000 + movl $0x40c00000, %ecx # imm = 0x40C00000 + movabsq $0x4024000000000000, %rdx # imm = 0x4024000000000000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4024000000000000, %rcx # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %rax, %xmm14 - movq %rcx, %xmm15 + movq %rdx, %xmm15 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 movabsq $0x404c000000000000, %rax # imm = 0x404C000000000000 movq %rax, %xmm15 @@ -135,3 +110,5 @@ Disassembly of section .text: retq xorq %rax, %rax retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_param_ternary.aarch64.asm b/tests/snapshots/asm/fp_param_ternary.aarch64.asm index f6301b43a..6e8b6cc7f 100644 --- a/tests/snapshots/asm/fp_param_ternary.aarch64.asm +++ b/tests/snapshots/asm/fp_param_ternary.aarch64.asm @@ -10,182 +10,137 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 fmov d1, d0 mov x17, #0x1 // =1 and x0, x0, x17 cbz x0, - b - fneg s1, s1 fmov d0, d1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + fneg s1, s1 + b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 sxtw x0, w0 fmov d2, d0 mov x17, #0x1 // =1 and x1, x0, x17 cbz x1, - b - fneg s2, s2 mov x17, #0x2 // =2 and x0, x0, x17 cbz x0, - b - fneg s1, s1 fadd s0, s2, s1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret + fneg s1, s1 + b + fneg s2, s2 + b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x0 // =0 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x1 // =1 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x2 // =2 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x3 // =3 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x1 // =1 - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x4004000000000000 // =4612811918334230528 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x21, #0x40200000 // =1075838976 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x21 - fneg d1, d16 - fmov d16, x20 - fadd d1, d16, d1 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w21 + fneg s1, s16 + fmov s16, w20 + fadd s1, s16, s1 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x2 // =2 - mov x20, #0x401d000000000000 // =4619848792751996928 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x40e80000 // =1088946176 + mov x21, #0x3e000000 // =1040187392 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x20 - fneg d1, d16 - fmov d17, x21 - fadd d1, d1, d17 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fmov s17, w21 + fadd s1, s1, s17 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x3 // =3 - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x4010000000000000 // =4616189618054758400 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x40400000 // =1077936128 + mov x21, #0x40800000 // =1082130432 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x20 - fmov d17, x21 - fadd d1, d16, d17 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fmov s17, w21 + fadd s1, s16, s17 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret diff --git a/tests/snapshots/asm/fp_param_ternary.x64.asm b/tests/snapshots/asm/fp_param_ternary.x64.asm index 69f2cee19..fc4f71529 100644 --- a/tests/snapshots/asm/fp_param_ternary.x64.asm +++ b/tests/snapshots/asm/fp_param_ternary.x64.asm @@ -11,51 +11,41 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi movapd %xmm0, %xmm1 movq %rdi, %rax andq $0x1, %rax testq %rax, %rax je - jmp + movapd %xmm1, %xmm0 + retq movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movapd %xmm1, %xmm0 - addq $0x10, %rsp - popq %rbp - retq + jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movslq %edi, %rdi movapd %xmm0, %xmm2 movq %rdi, %rax andq $0x1, %rax testq %rax, %rax je - jmp - movl $0x80000000, %r10d # imm = 0x80000000 - movq %r10, %xmm15 - xorpd %xmm15, %xmm2 movq %rdi, %rax andq $0x2, %rax testq %rax, %rax je - jmp - movl $0x80000000, %r10d # imm = 0x80000000 - movq %r10, %xmm15 - xorpd %xmm15, %xmm1 movapd %xmm2, %xmm0 addss %xmm1, %xmm0 - addq $0x30, %rsp - popq %rbp retq + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + jmp + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm2 + jmp
: pushq %rbp @@ -64,16 +54,14 @@ Disassembly of section .text: movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -88,13 +76,11 @@ Disassembly of section .text: popq %rbp retq movl $0x1, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,16 +95,14 @@ Disassembly of section .text: popq %rbp retq movl $0x2, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -133,13 +117,11 @@ Disassembly of section .text: popq %rbp retq movl $0x3, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -154,22 +136,19 @@ Disassembly of section .text: popq %rbp retq movl $0x1, %edi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %r12 # imm = 0x4004000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %r12d # imm = 0x40200000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %r12, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 movapd %xmm1, %xmm15 movq %rbx, %xmm1 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -184,21 +163,18 @@ Disassembly of section .text: popq %rbp retq movl $0x2, %edi - movabsq $0x401d000000000000, %rbx # imm = 0x401D000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fc0000000000000, %r12 # imm = 0x3FC0000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40e80000, %ebx # imm = 0x40E80000 + movl $0x3e000000, %r12d # imm = 0x3E000000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 movq %r12, %xmm15 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -213,18 +189,15 @@ Disassembly of section .text: popq %rbp retq movl $0x3, %edi - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %r12 # imm = 0x4010000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40400000, %ebx # imm = 0x40400000 + movl $0x40800000, %r12d # imm = 0x40800000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %r12, %xmm15 movq %rbx, %xmm1 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -244,4 +217,5 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_return_value.aarch64.asm b/tests/snapshots/asm/fp_return_value.aarch64.asm index 4306327ab..b19a462f2 100644 --- a/tests/snapshots/asm/fp_return_value.aarch64.asm +++ b/tests/snapshots/asm/fp_return_value.aarch64.asm @@ -21,25 +21,18 @@ Disassembly of section .text: sxtw x0, w0 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fdiv d0, d0, d17 - fcvt s0, d0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s0, s0, s17 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x0, #0x7 // =7 - sxtw x0, w0 scvtf d0, x0 mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d17, x0 fadd d0, d0, d17 mov x0, #0x2 // =2 - sxtw x0, w0 scvtf d1, x0 mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d17, x0 @@ -51,54 +44,39 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 - sxtw x0, w0 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fdiv d0, d0, d17 - fcvt s0, d0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s0, s0, s17 mov x0, #0x5 // =5 - sxtw x0, w0 scvtf d1, x0 fcvt s1, d1 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x0 - fdiv d1, d1, d17 - fcvt s1, d1 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s1, s1, s17 fadd s0, s0, s1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 - sxtw x0, w0 scvtf d0, x0 mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d17, x0 fadd d0, d0, d17 mov x0, #0x4000000000000000 // =4611686018427387904 mov x1, #0x6 // =6 - sxtw x1, w1 scvtf d1, x1 fcvt s1, d1 - mov x1, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x1 - fdiv d1, d1, d17 - fcvt s1, d1 + mov x1, #0x40800000 // =1082130432 + fmov s17, w1 + fdiv s1, s1, s17 fcvt d1, s1 fmov d17, x0 fmadd d0, d0, d17, d1 @@ -108,10 +86,6 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/fp_return_value.x64.asm b/tests/snapshots/asm/fp_return_value.x64.asm index 53562e005..810e8717a 100644 --- a/tests/snapshots/asm/fp_return_value.x64.asm +++ b/tests/snapshots/asm/fp_return_value.x64.asm @@ -22,25 +22,18 @@ Disassembly of section .text: movslq %edi, %rdi cvtsi2sd %rdi, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + divss %xmm15, %xmm0 retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movl $0x7, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm0 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 addsd %xmm15, %xmm0 movl $0x2, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm1 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 @@ -57,32 +50,23 @@ Disassembly of section .text: testq %rax, %rax je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x3, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + divss %xmm15, %xmm0 movl $0x5, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm1 cvtsd2ss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + divss %xmm15, %xmm1 addss %xmm1, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -91,25 +75,19 @@ Disassembly of section .text: testq %rax, %rax je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x1, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm0 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 addsd %xmm15, %xmm0 movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 movl $0x6, %ecx - movslq %ecx, %rcx cvtsi2sd %rcx, %xmm1 cvtsd2ss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + movl $0x40800000, %ecx # imm = 0x40800000 movq %rcx, %xmm15 - divsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + divss %xmm15, %xmm1 cvtss2sd %xmm1, %xmm1 movapd %xmm0, %xmm14 movq %rax, %xmm15 @@ -126,11 +104,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm b/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm index d519d9694..594fcec90 100644 --- a/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm +++ b/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm @@ -10,39 +10,32 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 + mov x0, #0x40800000 // =1082130432 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3e800000 // =1048576000 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x4022000000000000 // =4621256167635550208 fmov d16, x0 @@ -53,24 +46,20 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40600000 // =1080033280 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x400c000000000000 // =4615063718147915776 fmov d16, x0 @@ -81,14 +70,12 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fsqrt s0, s16 fcvt d0, s0 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d17, x0 @@ -96,9 +83,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x999a // =39322 movk x0, #0x9999, lsl #16 @@ -111,25 +97,20 @@ Disassembly of section .text: fcmp d0, d17 cset x1, ne cbnz x1, - mov x0, #0x6666 // =26214 - movk x0, #0x6666, lsl #16 - movk x0, #0x6666, lsl #32 - movk x0, #0x4002, lsl #48 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x3333 // =13107 + movk x0, #0x4013, lsl #16 + fmov s16, w0 + fneg s0, s16 frintm s0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x6666 // =26214 movk x0, #0x6666, lsl #16 @@ -142,25 +123,20 @@ Disassembly of section .text: fcmp d0, d17 cset x1, ne cbnz x1, - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 + fmov s16, w0 + fneg s0, s16 frintp s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x999a // =39322 movk x0, #0x9999, lsl #16 @@ -175,70 +151,58 @@ Disassembly of section .text: fcmp d0, d1 cset x1, ne cbnz x1, - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintz s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 + fmov s16, w0 + frintz s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x9 // =9 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fneg d1, d16 - fcvt s1, d1 - fabs s1, s1 - fsqrt s1, s1 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fneg s0, s16 + fabs s0, s0 + fsqrt s0, s0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xa // =10 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret + sub x16, x29, #0x10 + ldr s0, [x16] fmul s0, s0, s0 fsqrt s0, s0 - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x3fec, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fadd d0, d0, d17 - fcvt s0, d0 + mov x0, #0x6666 // =26214 + movk x0, #0x3f66, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 frintm s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret b b diff --git a/tests/snapshots/asm/fp_unary_intrinsic.x64.asm b/tests/snapshots/asm/fp_unary_intrinsic.x64.asm index a5eb60930..3783ac30e 100644 --- a/tests/snapshots/asm/fp_unary_intrinsic.x64.asm +++ b/tests/snapshots/asm/fp_unary_intrinsic.x64.asm @@ -14,14 +14,12 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -33,14 +31,12 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x3e800000, %eax # imm = 0x3E800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -69,18 +65,16 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -113,9 +107,8 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 @@ -145,20 +138,18 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4002666666666666, %rax # imm = 0x4002666666666666 + movl $0x40133333, %eax # imm = 0x40133333 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -183,20 +174,18 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A + movl $0x402ccccd, %eax # imm = 0x402CCCCD movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 roundss $0xa, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -227,14 +216,12 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x4039999a, %eax # imm = 0x4039999A + movq %rax, %xmm0 roundss $0xb, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -246,23 +233,21 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movss %xmm14, -0x10(%rbp,%riz) + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 - andpd %xmm15, %xmm1 - sqrtss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + andpd %xmm15, %xmm0 + sqrtss %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -274,19 +259,17 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + movss -0x10(%rbp,%riz), %xmm0 movapd %xmm0, %xmm15 mulss %xmm15, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x3feccccccccccccd, %rax # imm = 0x3FECCCCCCCCCCCCD - cvtss2sd %xmm0, %xmm0 + movl $0x3f666666, %eax # imm = 0x3F666666 movq %rax, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + addss %xmm15, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -305,3 +288,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fts_and_fd_set_headers.aarch64.asm b/tests/snapshots/asm/fts_and_fd_set_headers.aarch64.asm index d8f1212fc..b841e57e2 100644 --- a/tests/snapshots/asm/fts_and_fd_set_headers.aarch64.asm +++ b/tests/snapshots/asm/fts_and_fd_set_headers.aarch64.asm @@ -10,13 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x100 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] + stp x20, x21, [sp, #-0x100]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0xf0] + add x29, sp, #0xf0 sub x0, x29, #0x80 mov x2, #0x0 // =0 strb w2, [x0] @@ -41,85 +38,66 @@ Disassembly of section .text: cmp x20, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret mov x0, x20 bl - mov x21, x0 - cmp x21, #0x0 + cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret - ldrh w0, [x21, #0x5e] + ldrh w1, [x0, #0x5e] mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret - ldr x0, [x21, #0x30] - cmp x0, #0x0 - cset x22, eq - cbnz x22, - ldr x0, [x21, #0x30] - ldrb w0, [x0] + ldr x1, [x0, #0x30] + cmp x1, #0x0 + cset x2, eq + cbnz x2, + ldr x1, [x0, #0x30] + ldrb w1, [x1] mov x17, #0x2e // =46 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x22, ne - cbz x22, + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + cset x2, ne + cbz x2, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret - ldrh w22, [x21, #0x40] - ldr x0, [x21, #0x30] + ldrh w21, [x0, #0x40] + ldr x0, [x0, #0x30] bl sxtw x0, w0 mov x17, #0xffff // =65535 and x0, x0, x17 - cmp x22, x0 + cmp x21, x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret mov x0, x20 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xf0] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x100 ret b diff --git a/tests/snapshots/asm/fts_and_fd_set_headers.x64.asm b/tests/snapshots/asm/fts_and_fd_set_headers.x64.asm index d3eae51ee..7d4b41b80 100644 --- a/tests/snapshots/asm/fts_and_fd_set_headers.x64.asm +++ b/tests/snapshots/asm/fts_and_fd_set_headers.x64.asm @@ -13,10 +13,9 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xf0, %rsp + subq $0xe0, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) leaq -0x80(%rbp), %rax xorq %rdx, %rdx movb %dl, (%rax) @@ -43,68 +42,62 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq movq %rbx, %rdi xorl %eax, %eax callq - movq %rax, %r12 - testq %r12, %r12 + testq %rax, %rax jne movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq - movzwq 0x62(%r12), %rax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax + movzwq 0x62(%rax), %rcx + xorq $0x1, %rcx + movl %ecx, %ecx + testq %rcx, %rcx je movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq - movq 0x30(%r12), %rax - testq %rax, %rax - sete %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + movq 0x30(%rax), %rcx + testq %rcx, %rcx + sete %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne - movq 0x30(%r12), %rax - movsbq (%rax), %rax - cmpq $0x2e, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + movq 0x30(%rax), %rcx + movsbq (%rcx), %rcx + cmpq $0x2e, %rcx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq - movzwq 0x40(%r12), %r13 - movq 0x30(%r12), %rdi + movzwq 0x40(%rax), %r12 + movq 0x30(%rax), %rdi xorl %eax, %eax callq movslq %eax, %rax andq $0xffff, %rax # imm = 0xFFFF - cmpq %rax, %r13 + cmpq %rax, %r12 je movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq movq %rbx, %rdi @@ -114,9 +107,9 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xf0, %rsp + addq $0xe0, %rsp popq %rbp retq jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ftw_walk.aarch64.asm b/tests/snapshots/asm/ftw_walk.aarch64.asm index 5bcbe2e16..108634e95 100644 --- a/tests/snapshots/asm/ftw_walk.aarch64.asm +++ b/tests/snapshots/asm/ftw_walk.aarch64.asm @@ -24,7 +24,6 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x180 str x20, [sp] - str x21, [sp, #0x8] str x19, [sp, #0x10] sub x0, x29, #0x18 adrp x1, @@ -48,19 +47,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x180 ldp x29, x30, [sp], #0x10 ret mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0x3 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 b sub x0, x29, #0x118 mov x1, #0x100 // =256 @@ -74,10 +66,15 @@ Disassembly of section .text: adrp x1, add x1, x1, bl - mov x21, x0 - cmp x21, #0x0 - b.ne - b + cmp x0, #0x0 + b.eq + bl + sxtw x0, w0 + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0x3 + b.lt sub x0, x29, #0x18 adrp x1, add x1, x1, @@ -88,18 +85,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x1, eq cbz x1, - b - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x180 - ldp x29, x30, [sp], #0x10 - ret - mov x0, x21 - bl - sxtw x0, w0 - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -107,13 +92,18 @@ Disassembly of section .text: cset x1, ge cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x3 // =3 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x180 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x3 // =3 + b b + mov x0, #0x2 // =2 + ldr x19, [sp, #0x10] + ldr x20, [sp] + add sp, sp, #0x180 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/ftw_walk.x64.asm b/tests/snapshots/asm/ftw_walk.x64.asm index 8d6884dca..0fec53ec8 100644 --- a/tests/snapshots/asm/ftw_walk.x64.asm +++ b/tests/snapshots/asm/ftw_walk.x64.asm @@ -25,7 +25,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x170, %rsp # imm = 0x170 movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) leaq -0x18(%rbp), %rax leaq , %rcx pushq %rdx @@ -49,17 +48,10 @@ Disassembly of section .text: jne movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x170, %rsp # imm = 0x170 popq %rbp retq xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0x3, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp leaq -0x118(%rbp), %rdi movl $0x100, %esi # imm = 0x100 @@ -73,10 +65,17 @@ Disassembly of section .text: leaq , %rsi xorl %eax, %eax callq - movq %rax, %r12 - testq %r12, %r12 - jne - jmp + movq %rax, %rdi + testq %rdi, %rdi + je + xorl %eax, %eax + callq + movslq %eax, %rax + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0x3, %rax + jl leaq -0x18(%rbp), %rdi leaq -, %rsi # movl $0x10, %edx @@ -89,18 +88,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x170, %rsp # imm = 0x170 - popq %rbp - retq - movq %r12, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - jmp leaq , %rax movslq (%rax), %rax cmpq $0x4, %rax @@ -109,13 +96,16 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x3, %ecx movq (%rsp), %rbx - movq 0x8(%rsp), %r12 movq %rcx, %rax addq $0x170, %rsp # imm = 0x170 popq %rbp retq + movl $0x3, %ecx jmp - addb %al, (%rax) + jmp + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x170, %rsp # imm = 0x170 + popq %rbp + retq diff --git a/tests/snapshots/asm/func_name_array.aarch64.asm b/tests/snapshots/asm/func_name_array.aarch64.asm index 9150af6a9..2f307c15d 100644 --- a/tests/snapshots/asm/func_name_array.aarch64.asm +++ b/tests/snapshots/asm/func_name_array.aarch64.asm @@ -10,42 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, - b - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, #0x5 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - sxtw x1, w2 add x3, x0, x1 ldrb w3, [x3] adrp x4, add x4, x4, - add x1, x4, x1 - ldrsb x1, [x1] - eor x1, x3, x1 - mov w1, w1 - cmp x1, #0x0 - b.eq - b + add x4, x4, x1 + ldrsb x4, [x4] + eor x3, x3, x4 + mov w3, w3 + cmp x3, #0x0 + b.ne + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, #0x5 + b.lt mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 ret b diff --git a/tests/snapshots/asm/func_name_array.x64.asm b/tests/snapshots/asm/func_name_array.x64.asm index 09842f0d9..9ae49fb2a 100644 --- a/tests/snapshots/asm/func_name_array.x64.asm +++ b/tests/snapshots/asm/func_name_array.x64.asm @@ -11,38 +11,26 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax - jmp - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq xorq %rdx, %rdx - movslq %edx, %rcx - cmpq $0x5, %rcx - jge - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx jmp - movslq %edx, %rcx leaq (%rax,%rcx), %rsi movsbq (%rsi), %rsi leaq , %rdi - addq %rdi, %rcx - movsbq (%rcx), %rcx - cmpq %rcx, %rsi - je - jmp + addq %rcx, %rdi + movsbq (%rdi), %rdi + cmpq %rdi, %rsi + jne + leaq 0x1(%rcx), %rdx + movslq %edx, %rcx + cmpq $0x5, %rcx + jl xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq movl $0x2, %eax - addq $0x10, %rsp - popq %rbp + retq + movl $0x1, %eax retq jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/func_name_in_initializer.aarch64.asm b/tests/snapshots/asm/func_name_in_initializer.aarch64.asm index e13f26b26..7368ca798 100644 --- a/tests/snapshots/asm/func_name_in_initializer.aarch64.asm +++ b/tests/snapshots/asm/func_name_in_initializer.aarch64.asm @@ -10,30 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b - b : adrp x0, diff --git a/tests/snapshots/asm/func_name_in_initializer.x64.asm b/tests/snapshots/asm/func_name_in_initializer.x64.asm index 459cb6b0f..6c5b2a989 100644 --- a/tests/snapshots/asm/func_name_in_initializer.x64.asm +++ b/tests/snapshots/asm/func_name_in_initializer.x64.asm @@ -11,24 +11,9 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp - incq %rdi - incq %rsi - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp - retq movsbq (%rdi), %rax movsbq (%rsi), %rcx cmpq %rcx, %rax @@ -36,8 +21,16 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je + incq %rdi + incq %rsi jmp jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %al + movzbq %al, %rax + retq : leaq , %rax @@ -126,4 +119,4 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/funcptr_global_addressof_init.aarch64.asm b/tests/snapshots/asm/funcptr_global_addressof_init.aarch64.asm index 6075eb157..528f1723f 100644 --- a/tests/snapshots/asm/funcptr_global_addressof_init.aarch64.asm +++ b/tests/snapshots/asm/funcptr_global_addressof_init.aarch64.asm @@ -15,46 +15,37 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x29 // =41 adrp x20, add x20, x20, ldr x1, [x20] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x14 // =20 adrp x1, add x1, x1, ldr x1, [x1] - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x15 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20] adrp x1, @@ -63,14 +54,12 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/function_macro.aarch64.asm b/tests/snapshots/asm/function_macro.aarch64.asm index 02370c538..287c4025d 100644 --- a/tests/snapshots/asm/function_macro.aarch64.asm +++ b/tests/snapshots/asm/function_macro.aarch64.asm @@ -10,47 +10,37 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] cmp x0, #0x0 cset x0, eq mov x3, #0x0 // =0 cbz x0, - b - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b ldrb w0, [x1] cmp x0, #0x0 cset x0, eq cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b - b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x22, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, adrp x21, @@ -64,11 +54,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x15 // =21 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x1, add x1, x1, @@ -77,11 +65,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x16 // =22 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x1, add x1, x1, @@ -90,11 +76,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x17 // =23 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, x20 mov x1, x21 @@ -102,11 +86,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x18 // =24 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, x20 mov x1, x22 @@ -114,18 +96,14 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x19 // =25 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret : diff --git a/tests/snapshots/asm/function_macro.x64.asm b/tests/snapshots/asm/function_macro.x64.asm index 55659a7f5..2a86b553c 100644 --- a/tests/snapshots/asm/function_macro.x64.asm +++ b/tests/snapshots/asm/function_macro.x64.asm @@ -11,16 +11,20 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx + je incq %rdi incq %rsi jmp + jmp movsbq (%rdi), %rax testq %rax, %rax sete %al @@ -28,15 +32,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %cl - movzbq %cl, %rcx - testq %rcx, %rcx - je - jmp movsbq (%rsi), %rax testq %rax, %rax sete %al @@ -45,16 +40,13 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp - jmp : pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -70,7 +62,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq leaq , %rsi @@ -82,7 +74,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq leaq , %rsi @@ -94,7 +86,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq movq %rbx, %rdi @@ -106,7 +98,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq movq %rbx, %rdi @@ -118,14 +110,14 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq @@ -172,4 +164,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/function_pointer_typedefs.aarch64.asm b/tests/snapshots/asm/function_pointer_typedefs.aarch64.asm index 772792cfe..18911b127 100644 --- a/tests/snapshots/asm/function_pointer_typedefs.aarch64.asm +++ b/tests/snapshots/asm/function_pointer_typedefs.aarch64.asm @@ -37,42 +37,31 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 sxtw x2, w2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] + str x20, [sp, #-0x80]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 adrp x20, add x20, x20, mov x0, #0x3 // =3 mov x1, #0x5 // =5 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 @@ -81,45 +70,33 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret mov x0, #0x7 // =7 mov x1, #0x2 // =2 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x1 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret mov x0, #0x4 // =4 - str x0, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x1, x0 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret sub x0, x29, #0x20 adrp x1, @@ -135,53 +112,42 @@ Disassembly of section .text: ldr x0, [x0] mov x1, #0x2 // =2 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret sub x0, x29, #0x20 ldr x0, [x0, #0x8] mov x1, #0xa // =10 mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x6 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret sub x0, x29, #0x20 ldr x0, [x0, #0x10] mov x1, #0x1 // =1 mov x2, #0x2 // =2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 @@ -190,10 +156,9 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret adrp x0, add x0, x0, @@ -203,14 +168,12 @@ Disassembly of section .text: cmp x0, #0x11 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 ret diff --git a/tests/snapshots/asm/function_pointers.aarch64.asm b/tests/snapshots/asm/function_pointers.aarch64.asm index ffdb6acfc..27b47059e 100644 --- a/tests/snapshots/asm/function_pointers.aarch64.asm +++ b/tests/snapshots/asm/function_pointers.aarch64.asm @@ -20,39 +20,27 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x0, add x0, x0, mov x20, #0xa // =10 mov x1, #0x14 // =20 - str x1, [sp, #-0x10]! - str x20, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x20 blr x9 - add sp, sp, #0x20 mov x21, x0 adrp x0, add x0, x0, mov x1, #0x5 // =5 - str x1, [sp, #-0x10]! - str x20, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x20 blr x9 - add sp, sp, #0x20 mul x0, x21, x0 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/function_pointers.x64.asm b/tests/snapshots/asm/function_pointers.x64.asm index 596f81401..c98d839af 100644 --- a/tests/snapshots/asm/function_pointers.x64.asm +++ b/tests/snapshots/asm/function_pointers.x64.asm @@ -24,7 +24,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq -, %rax # @@ -41,7 +41,7 @@ Disassembly of section .text: movslq %eax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/function_type_typedef.aarch64.asm b/tests/snapshots/asm/function_type_typedef.aarch64.asm index 9ed73b202..e13b334d0 100644 --- a/tests/snapshots/asm/function_type_typedef.aarch64.asm +++ b/tests/snapshots/asm/function_type_typedef.aarch64.asm @@ -20,49 +20,38 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 sxtw x2, w2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 sxtw x2, w2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, mov x1, #0x3 // =3 @@ -72,9 +61,8 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -84,9 +72,8 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x1, #0x5 // =5 mov x2, #0x6 // =6 @@ -95,9 +82,8 @@ Disassembly of section .text: cmp x0, #0xb b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -107,12 +93,10 @@ Disassembly of section .text: cmp x0, #0xc b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/function_type_typedef_declaration.aarch64.asm b/tests/snapshots/asm/function_type_typedef_declaration.aarch64.asm index 8efb6f443..b88bfe637 100644 --- a/tests/snapshots/asm/function_type_typedef_declaration.aarch64.asm +++ b/tests/snapshots/asm/function_type_typedef_declaration.aarch64.asm @@ -20,70 +20,38 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 sxtw x2, w2 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] - mov x0, #0x3 // =3 - mov x1, #0x4 // =4 - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x7 - b.eq - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xa // =10 - mov x1, #0x4 // =4 - sub x0, x0, x1 - sxtw x0, w0 - cmp x0, #0x6 - b.eq - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x2 // =2 mov x2, #0x5 // =5 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -93,31 +61,33 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, mov x1, #0x8 // =8 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/function_type_typedef_declaration.x64.asm b/tests/snapshots/asm/function_type_typedef_declaration.x64.asm index 8775198fa..c3e9e97ac 100644 --- a/tests/snapshots/asm/function_type_typedef_declaration.x64.asm +++ b/tests/snapshots/asm/function_type_typedef_declaration.x64.asm @@ -37,27 +37,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp - movl $0x3, %eax - movl $0x4, %ecx - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x7, %rax - je - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0xa, %eax - movl $0x4, %ecx - subq %rcx, %rax - movslq %eax, %rax - cmpq $0x6, %rax - je - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -, %rax # movl $0x2, %edi movl $0x5, %esi @@ -66,7 +45,6 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x3, %eax - addq $0x20, %rsp popq %rbp retq leaq -, %rdi # @@ -76,7 +54,6 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x4, %eax - addq $0x20, %rsp popq %rbp retq leaq -, %rax # @@ -87,10 +64,16 @@ Disassembly of section .text: cmpq $0x5, %rax je movl $0x5, %eax - addq $0x20, %rsp popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp popq %rbp retq + movl $0x1, %eax + popq %rbp + retq + movl $0x2, %eax + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/function_typed_parameter.aarch64.asm b/tests/snapshots/asm/function_typed_parameter.aarch64.asm index 3cba0747e..50a36282e 100644 --- a/tests/snapshots/asm/function_typed_parameter.aarch64.asm +++ b/tests/snapshots/asm/function_typed_parameter.aarch64.asm @@ -10,53 +10,41 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : @@ -78,10 +66,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, mov x1, #0x15 // =21 @@ -90,9 +77,8 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -101,9 +87,8 @@ Disassembly of section .text: cmp x0, #0xb b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -115,9 +100,8 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x1, #0x10 // =16 mov x0, x20 @@ -125,12 +109,10 @@ Disassembly of section .text: cmp x0, #0x20 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/gcc_atomics.aarch64.asm b/tests/snapshots/asm/gcc_atomics.aarch64.asm index d1c0ea57b..293a619db 100644 --- a/tests/snapshots/asm/gcc_atomics.aarch64.asm +++ b/tests/snapshots/asm/gcc_atomics.aarch64.asm @@ -23,11 +23,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x1, eq cbz x1, - b - sub x0, x29, #0x8 - mov x1, #0x14 // =20 - str w1, [x0] - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -38,15 +33,15 @@ Disassembly of section .text: add x0, x0, mov x1, #0x1 // =1 str w1, [x0] - b + sub x0, x29, #0x8 + mov x1, #0x14 // =20 + str w1, [x0] ldursw x0, [x29, #-0x8] cmp x0, #0x14 cset x0, eq cmp x0, #0x0 cset x1, eq cbz x1, - b - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -57,7 +52,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x2 // =2 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x1e // =30 stp x9, x10, [sp, #-0x20]! @@ -76,8 +70,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x1, eq cbz x1, - b - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -88,17 +80,12 @@ Disassembly of section .text: add x0, x0, mov x1, #0x3 // =3 str w1, [x0] - b ldursw x0, [x29, #-0x8] cmp x0, #0x1e cset x0, eq cmp x0, #0x0 cset x1, eq cbz x1, - b - mov x0, #0x64 // =100 - stur w0, [x29, #-0x8] - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -109,7 +96,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0x4 // =4 str w1, [x0] - b + mov x0, #0x64 // =100 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x5 // =5 stp x9, x10, [sp, #-0x20]! @@ -128,8 +116,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x69 cset x0, eq @@ -148,7 +134,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x5 // =5 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x5 // =5 stp x9, x10, [sp, #-0x20]! @@ -167,10 +152,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0xf0 // =240 - stur w0, [x29, #-0x8] - b ldursw x0, [x29, #-0x8] cmp x0, #0x64 cset x0, eq @@ -189,7 +170,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0x6 // =6 str w1, [x0] - b + mov x0, #0xf0 // =240 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x3c // =60 stp x9, x10, [sp, #-0x20]! @@ -208,8 +190,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x30 cset x0, eq @@ -228,7 +208,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x7 // =7 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0xf // =15 stp x9, x10, [sp, #-0x20]! @@ -247,8 +226,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x3f cset x0, eq @@ -267,7 +244,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x8 // =8 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0xff // =255 stp x9, x10, [sp, #-0x20]! @@ -286,11 +262,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0x7 // =7 - stur w0, [x29, #-0x8] - stur w0, [x29, #-0x10] - b ldursw x0, [x29, #-0x8] cmp x0, #0xc0 cset x0, eq @@ -309,7 +280,9 @@ Disassembly of section .text: add x0, x0, mov x1, #0x9 // =9 str w1, [x0] - b + mov x0, #0x7 // =7 + stur w0, [x29, #-0x8] + stur w0, [x29, #-0x10] sub x0, x29, #0x8 sub x1, x29, #0x10 mov x2, #0x8 // =8 @@ -335,10 +308,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0x7 // =7 - stur w0, [x29, #-0x10] - b ldursw x0, [x29, #-0x8] cmp x0, #0x8 cset x0, eq @@ -357,7 +326,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0xa // =10 str w1, [x0] - b + mov x0, #0x7 // =7 + stur w0, [x29, #-0x10] sub x0, x29, #0x8 sub x1, x29, #0x10 mov x2, #0x9 // =9 @@ -383,10 +353,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0x64 // =100 - stur w0, [x29, #-0x8] - b ldursw x0, [x29, #-0x8] cmp x0, #0x8 cset x0, eq @@ -412,7 +378,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0xb // =11 str w1, [x0] - b + mov x0, #0x64 // =100 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x7 // =7 stp x9, x10, [sp, #-0x20]! @@ -431,8 +398,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x6b cset x0, eq @@ -451,7 +416,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0xc // =12 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x7 // =7 stp x9, x10, [sp, #-0x20]! @@ -465,14 +429,12 @@ Disassembly of section .text: ldp x11, x12, [sp, #0x10] ldp x9, x10, [sp], #0x20 mov x0, x16 - sub x0, x0, x1 + sub x0, x0, #0x7 sxtw x0, w0 cmp x0, #0x64 cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x64 cset x0, eq @@ -491,7 +453,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0xd // =13 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x1 // =1 stp x9, x10, [sp, #-0x20]! @@ -505,16 +466,12 @@ Disassembly of section .text: ldp x11, x12, [sp, #0x10] ldp x9, x10, [sp], #0x20 mov x0, x16 - add x0, x0, x1 + add x0, x0, #0x1 sxtw x0, w0 cmp x0, #0x65 cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0xcc // =204 - stur w0, [x29, #-0x8] - b ldursw x0, [x29, #-0x8] cmp x0, #0x65 cset x0, eq @@ -533,7 +490,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0xe // =14 str w1, [x0] - b + mov x0, #0xcc // =204 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x33 // =51 stp x9, x10, [sp, #-0x20]! @@ -552,8 +510,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0xff cset x0, eq @@ -572,7 +528,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0xf // =15 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0xf // =15 stp x9, x10, [sp, #-0x20]! @@ -592,8 +547,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0xf cset x0, eq @@ -612,7 +565,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x10 // =16 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0xff // =255 stp x9, x10, [sp, #-0x20]! @@ -632,10 +584,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0x5 // =5 - stur w0, [x29, #-0x8] - b ldursw x0, [x29, #-0x8] cmp x0, #0xf0 cset x0, eq @@ -654,7 +602,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0x11 // =17 str w1, [x0] - b + mov x0, #0x5 // =5 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x5 // =5 mov x2, #0x6 // =6 @@ -683,8 +632,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x6 cset x0, eq @@ -703,7 +650,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x12 // =18 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x5 // =5 mov x2, #0x7 // =7 @@ -732,8 +678,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x6 cset x0, eq @@ -752,7 +696,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x13 // =19 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x6 // =6 mov x2, #0x8 // =8 @@ -780,8 +723,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldursw x0, [x29, #-0x8] cmp x0, #0x8 cset x0, eq @@ -800,7 +741,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x14 // =20 str w1, [x0] - b sub x0, x29, #0x8 mov x1, #0x6 // =6 mov x2, #0x9 // =9 @@ -828,10 +768,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - mov x0, #0x1 // =1 - stur w0, [x29, #-0x8] - b ldursw x0, [x29, #-0x8] cmp x0, #0x8 cset x0, eq @@ -850,7 +786,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0x15 // =21 str w1, [x0] - b + mov x0, #0x1 // =1 + stur w0, [x29, #-0x8] sub x0, x29, #0x8 mov x1, #0x2 // =2 stp x9, x10, [sp, #-0x20]! @@ -868,11 +805,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - sub x0, x29, #0x8 - mov x1, #0x0 // =0 - str w1, [x0] - b ldursw x0, [x29, #-0x8] cmp x0, #0x2 cset x0, eq @@ -891,17 +823,15 @@ Disassembly of section .text: add x0, x0, mov x1, #0x16 // =22 str w1, [x0] - b + sub x0, x29, #0x8 + mov x1, #0x0 // =0 + str w1, [x0] ldursw x0, [x29, #-0x8] cmp x0, #0x0 cset x0, eq cmp x0, #0x0 cset x1, eq cbz x1, - b - mov x0, #0x0 // =0 - sturb w0, [x29, #-0x18] - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -912,7 +842,8 @@ Disassembly of section .text: add x0, x0, mov x1, #0x17 // =23 str w1, [x0] - b + mov x0, #0x0 // =0 + sturb w0, [x29, #-0x18] sub x0, x29, #0x18 mov x1, #0x1 // =1 stp x9, x10, [sp, #-0x20]! @@ -931,8 +862,6 @@ Disassembly of section .text: cset x0, eq mov x2, #0x0 // =0 cbz x0, - b - b ldurb w0, [x29, #-0x18] cmp x0, #0x0 cset x0, ne @@ -951,7 +880,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0x18 // =24 str w1, [x0] - b sub x0, x29, #0x18 mov x1, #0x1 // =1 stp x9, x10, [sp, #-0x20]! @@ -971,11 +899,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x1, eq cbz x1, - b - sub x0, x29, #0x18 - mov x1, #0x0 // =0 - strb w1, [x0] - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -986,18 +909,15 @@ Disassembly of section .text: add x0, x0, mov x1, #0x19 // =25 str w1, [x0] - b + sub x0, x29, #0x18 + mov x1, #0x0 // =0 + strb w1, [x0] ldurb w0, [x29, #-0x18] cmp x0, #0x0 cset x0, eq cmp x0, #0x0 cset x1, eq cbz x1, - b - dmb ish - dmb ish - dmb ish - b adrp x0, add x0, x0, ldrsw x0, [x0] @@ -1008,9 +928,15 @@ Disassembly of section .text: add x0, x0, mov x1, #0x1a // =26 str w1, [x0] - b + dmb ish + dmb ish + dmb ish mov x1, #0x0 // =0 - b + cbz x1, + adrp x0, + add x0, x0, + mov x1, #0x1b // =27 + str w1, [x0] adrp x0, add x0, x0, ldrsw x0, [x0] @@ -1018,16 +944,6 @@ Disassembly of section .text: add sp, sp, #0x1c0 ldp x29, x30, [sp], #0x10 ret - adrp x0, - add x0, x0, - ldrsw x0, [x0] - cmp x0, #0x0 - cset x1, eq - cbz x1, - adrp x0, - add x0, x0, - mov x1, #0x1b // =27 - str w1, [x0] b b b @@ -1075,3 +991,48 @@ Disassembly of section .text: b b b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + b + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x0 + cset x1, eq + b + b diff --git a/tests/snapshots/asm/gcc_atomics.x64.asm b/tests/snapshots/asm/gcc_atomics.x64.asm index 325a35231..11381fbc4 100644 --- a/tests/snapshots/asm/gcc_atomics.x64.asm +++ b/tests/snapshots/asm/gcc_atomics.x64.asm @@ -26,11 +26,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - leaq -0x8(%rbp), %rax - movl $0x14, %ecx - movl %ecx, (%rax) - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -41,7 +36,9 @@ Disassembly of section .text: leaq , %rax movl $0x1, %ecx movl %ecx, (%rax) - jmp + leaq -0x8(%rbp), %rax + movl $0x14, %ecx + movl %ecx, (%rax) movslq -0x8(%rbp), %rax cmpq $0x14, %rax sete %al @@ -51,8 +48,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -63,7 +58,6 @@ Disassembly of section .text: leaq , %rax movl $0x2, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x1e, %ecx movq %rax, %r11 @@ -79,8 +73,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -91,7 +83,6 @@ Disassembly of section .text: leaq , %rax movl $0x3, %ecx movl %ecx, (%rax) - jmp movslq -0x8(%rbp), %rax cmpq $0x1e, %rax sete %al @@ -101,10 +92,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - movl $0x64, %eax - movl %eax, -0x8(%rbp) - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -115,7 +102,8 @@ Disassembly of section .text: leaq , %rax movl $0x4, %ecx movl %ecx, (%rax) - jmp + movl $0x64, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x5, %ecx pushq %rax @@ -134,8 +122,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x69, %rax sete %al @@ -158,7 +144,6 @@ Disassembly of section .text: leaq , %rax movl $0x5, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x5, %ecx pushq %rax @@ -178,10 +163,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0xf0, %eax - movl %eax, -0x8(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0x64, %rax sete %al @@ -204,7 +185,8 @@ Disassembly of section .text: leaq , %rax movl $0x6, %ecx movl %ecx, (%rax) - jmp + movl $0xf0, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x3c, %ecx pushq %rax @@ -228,8 +210,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x30, %rax sete %al @@ -252,7 +232,6 @@ Disassembly of section .text: leaq , %rax movl $0x7, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0xf, %ecx pushq %rax @@ -276,8 +255,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x3f, %rax sete %al @@ -300,7 +277,6 @@ Disassembly of section .text: leaq , %rax movl $0x8, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0xff, %ecx pushq %rax @@ -324,11 +300,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0x7, %eax - movl %eax, -0x8(%rbp) - movl %eax, -0x10(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0xc0, %rax sete %al @@ -351,7 +322,9 @@ Disassembly of section .text: leaq , %rax movl $0x9, %ecx movl %ecx, (%rax) - jmp + movl $0x7, %eax + movl %eax, -0x8(%rbp) + movl %eax, -0x10(%rbp) leaq -0x8(%rbp), %rax leaq -0x10(%rbp), %rcx movl $0x8, %edx @@ -375,10 +348,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0x7, %eax - movl %eax, -0x10(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0x8, %rax sete %al @@ -401,7 +370,8 @@ Disassembly of section .text: leaq , %rax movl $0xa, %ecx movl %ecx, (%rax) - jmp + movl $0x7, %eax + movl %eax, -0x10(%rbp) leaq -0x8(%rbp), %rax leaq -0x10(%rbp), %rcx movl $0x9, %edx @@ -425,10 +395,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0x64, %eax - movl %eax, -0x8(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0x8, %rax sete %al @@ -461,7 +427,8 @@ Disassembly of section .text: leaq , %rax movl $0xb, %ecx movl %ecx, (%rax) - jmp + movl $0x64, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x7, %ecx pushq %rax @@ -480,8 +447,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x6b, %rax sete %al @@ -504,7 +469,6 @@ Disassembly of section .text: leaq , %rax movl $0xc, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x7, %ecx pushq %rax @@ -517,7 +481,7 @@ Disassembly of section .text: movq %rax, %r10 popq %rax movq %r10, %rax - subq %rcx, %rax + subq $0x7, %rax movslq %eax, %rax cmpq $0x64, %rax sete %al @@ -525,8 +489,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x64, %rax sete %al @@ -549,7 +511,6 @@ Disassembly of section .text: leaq , %rax movl $0xd, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x1, %ecx pushq %rax @@ -561,7 +522,7 @@ Disassembly of section .text: movq %rax, %r10 popq %rax movq %r10, %rax - addq %rcx, %rax + incq %rax movslq %eax, %rax cmpq $0x65, %rax sete %al @@ -569,10 +530,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0xcc, %eax - movl %eax, -0x8(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0x65, %rax sete %al @@ -595,7 +552,8 @@ Disassembly of section .text: leaq , %rax movl $0xe, %ecx movl %ecx, (%rax) - jmp + movl $0xcc, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x33, %ecx pushq %rax @@ -619,8 +577,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0xff, %rax sete %al @@ -643,7 +599,6 @@ Disassembly of section .text: leaq , %rax movl $0xf, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0xf, %ecx pushq %rax @@ -668,8 +623,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0xf, %rax sete %al @@ -692,7 +645,6 @@ Disassembly of section .text: leaq , %rax movl $0x10, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0xff, %ecx pushq %rax @@ -717,10 +669,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0x5, %eax - movl %eax, -0x8(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0xf0, %rax sete %al @@ -743,7 +691,8 @@ Disassembly of section .text: leaq , %rax movl $0x11, %ecx movl %ecx, (%rax) - jmp + movl $0x5, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x5, %ecx movl $0x6, %edx @@ -771,8 +720,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x6, %rax sete %al @@ -795,7 +742,6 @@ Disassembly of section .text: leaq , %rax movl $0x12, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x5, %ecx movl $0x7, %edx @@ -823,8 +769,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x6, %rax sete %al @@ -847,7 +791,6 @@ Disassembly of section .text: leaq , %rax movl $0x13, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x6, %ecx movl $0x8, %edx @@ -874,8 +817,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movslq -0x8(%rbp), %rax cmpq $0x8, %rax sete %al @@ -898,7 +839,6 @@ Disassembly of section .text: leaq , %rax movl $0x14, %ecx movl %ecx, (%rax) - jmp leaq -0x8(%rbp), %rax movl $0x6, %ecx movl $0x9, %edx @@ -925,10 +865,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - movl $0x1, %eax - movl %eax, -0x8(%rbp) - jmp movslq -0x8(%rbp), %rax cmpq $0x8, %rax sete %al @@ -951,7 +887,8 @@ Disassembly of section .text: leaq , %rax movl $0x15, %ecx movl %ecx, (%rax) - jmp + movl $0x1, %eax + movl %eax, -0x8(%rbp) leaq -0x8(%rbp), %rax movl $0x2, %ecx movq %rax, %r11 @@ -965,11 +902,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - leaq -0x8(%rbp), %rax - xorq %rcx, %rcx - movl %ecx, (%rax) - jmp movslq -0x8(%rbp), %rax cmpq $0x2, %rax sete %al @@ -992,7 +924,9 @@ Disassembly of section .text: leaq , %rax movl $0x16, %ecx movl %ecx, (%rax) - jmp + leaq -0x8(%rbp), %rax + xorq %rcx, %rcx + movl %ecx, (%rax) movslq -0x8(%rbp), %rax testq %rax, %rax sete %al @@ -1002,10 +936,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - xorq %rax, %rax - movb %al, -0x18(%rbp) - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -1016,7 +946,8 @@ Disassembly of section .text: leaq , %rax movl $0x17, %ecx movl %ecx, (%rax) - jmp + xorq %rax, %rax + movb %al, -0x18(%rbp) leaq -0x18(%rbp), %rax movl $0x1, %ecx movq %rax, %r11 @@ -1030,8 +961,6 @@ Disassembly of section .text: xorq %rdx, %rdx testq %rax, %rax je - jmp - jmp movzbq -0x18(%rbp), %rax testq %rax, %rax setne %al @@ -1054,7 +983,6 @@ Disassembly of section .text: leaq , %rax movl $0x18, %ecx movl %ecx, (%rax) - jmp leaq -0x18(%rbp), %rax movl $0x1, %ecx movq %rax, %r11 @@ -1070,11 +998,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - leaq -0x18(%rbp), %rax - xorq %rcx, %rcx - movb %cl, (%rax) - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -1085,7 +1008,9 @@ Disassembly of section .text: leaq , %rax movl $0x19, %ecx movl %ecx, (%rax) - jmp + leaq -0x18(%rbp), %rax + xorq %rcx, %rcx + movb %cl, (%rax) movzbq -0x18(%rbp), %rax testq %rax, %rax sete %al @@ -1095,11 +1020,6 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je - jmp - mfence - mfence - mfence - jmp leaq , %rax movslq (%rax), %rax testq %rax, %rax @@ -1110,24 +1030,40 @@ Disassembly of section .text: leaq , %rax movl $0x1a, %ecx movl %ecx, (%rax) - jmp + mfence + mfence + mfence xorq %rcx, %rcx - jmp - leaq , %rax - movslq (%rax), %rax - addq $0x1b0, %rsp # imm = 0x1B0 - popq %rbp - retq - leaq , %rax - movslq (%rax), %rax - testq %rax, %rax - sete %cl - movzbq %cl, %rcx testq %rcx, %rcx je leaq , %rax movl $0x1b, %ecx movl %ecx, (%rax) + leaq , %rax + movslq (%rax), %rax + addq $0x1b0, %rsp # imm = 0x1B0 + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp jmp jmp jmp @@ -1175,5 +1111,30 @@ Disassembly of section .text: jmp jmp jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + leaq , %rax + movslq (%rax), %rax + testq %rax, %rax + sete %cl + movzbq %cl, %rcx + jmp + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/getenv_value.aarch64.asm b/tests/snapshots/asm/getenv_value.aarch64.asm index 39951fd2f..7be12c6cc 100644 --- a/tests/snapshots/asm/getenv_value.aarch64.asm +++ b/tests/snapshots/asm/getenv_value.aarch64.asm @@ -10,22 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, bl cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w0, [x0] - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/getenv_value.x64.asm b/tests/snapshots/asm/getenv_value.x64.asm index ea1a124b7..6cfa2fbab 100644 --- a/tests/snapshots/asm/getenv_value.x64.asm +++ b/tests/snapshots/asm/getenv_value.x64.asm @@ -13,19 +13,14 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp leaq , %rdi xorl %eax, %eax callq testq %rax, %rax jne movl $0x1, %eax - addq $0x10, %rsp popq %rbp retq movsbq (%rax), %rax - addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/gettimeofday_usec_range.aarch64.asm b/tests/snapshots/asm/gettimeofday_usec_range.aarch64.asm index 09babb658..b7661f680 100644 --- a/tests/snapshots/asm/gettimeofday_usec_range.aarch64.asm +++ b/tests/snapshots/asm/gettimeofday_usec_range.aarch64.asm @@ -10,38 +10,18 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0x64 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 b sub x0, x29, #0x10 mov x1, #0x0 // =0 bl sxtw x0, w0 cmp x0, #0x0 - b.eq - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + b.ne sub x0, x29, #0x10 ldr x0, [x0, #0x8] cmp x0, #0x0 @@ -53,22 +33,36 @@ Disassembly of section .text: movk x17, #0xf, lsl #16 cmp x0, x17 cset x1, ge - cbz x1, - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret + cbnz x1, sub x0, x29, #0x10 ldr x0, [x0] cmp x0, #0x0 b.gt + b + b + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0x64 + b.lt + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x60 + ret mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x60 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x60 ret - b b diff --git a/tests/snapshots/asm/gettimeofday_usec_range.x64.asm b/tests/snapshots/asm/gettimeofday_usec_range.x64.asm index 107113984..590f37187 100644 --- a/tests/snapshots/asm/gettimeofday_usec_range.x64.asm +++ b/tests/snapshots/asm/gettimeofday_usec_range.x64.asm @@ -16,12 +16,6 @@ Disassembly of section .text: subq $0x40, %rsp movq %rbx, (%rsp) xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0x64, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp leaq -0x10(%rbp), %rdi xorq %rsi, %rsi @@ -29,18 +23,7 @@ Disassembly of section .text: callq movslq %eax, %rax testq %rax, %rax - je - jmp - xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq + jne leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax testq %rax, %rax @@ -54,21 +37,38 @@ Disassembly of section .text: setge %cl movzbq %cl, %rcx testq %rcx, %rcx - je - movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp - retq + jne leaq -0x10(%rbp), %rax movq (%rax), %rax testq %rax, %rax jg + jmp + jmp + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0x64, %rax + jl + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x40, %rsp + popq %rbp + retq movl $0x3, %eax movq (%rsp), %rbx addq $0x40, %rsp popq %rbp retq - jmp + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x40, %rsp + popq %rbp + retq + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x40, %rsp + popq %rbp + retq jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/global_init_midexpr_cast_narrow.aarch64.asm b/tests/snapshots/asm/global_init_midexpr_cast_narrow.aarch64.asm index 5f9f5faac..12aa0069e 100644 --- a/tests/snapshots/asm/global_init_midexpr_cast_narrow.aarch64.asm +++ b/tests/snapshots/asm/global_init_midexpr_cast_narrow.aarch64.asm @@ -14,21 +14,17 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, ldrsw x0, [x0] cmp x0, #0x1 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -40,10 +36,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -54,10 +48,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -65,10 +57,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -76,10 +66,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -87,20 +75,18 @@ Disassembly of section .text: adrp x1, add x1, x1, cmp x0, x1 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] ldrsw x0, [x0] cmp x0, #0x63 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -111,15 +97,11 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b diff --git a/tests/snapshots/asm/global_init_midexpr_cast_narrow.x64.asm b/tests/snapshots/asm/global_init_midexpr_cast_narrow.x64.asm index 3e2888502..b8a7883eb 100644 --- a/tests/snapshots/asm/global_init_midexpr_cast_narrow.x64.asm +++ b/tests/snapshots/asm/global_init_midexpr_cast_narrow.x64.asm @@ -17,15 +17,11 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp - movq %rbx, (%rsp) leaq , %rax movslq (%rax), %rax cmpq $0x1, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax @@ -33,8 +29,6 @@ Disassembly of section .text: cmpq $-0x1, %rax je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax @@ -44,8 +38,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax @@ -53,8 +45,6 @@ Disassembly of section .text: cmpq $0x1, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax @@ -62,29 +52,25 @@ Disassembly of section .text: cmpq $0x1, %rax je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax leaq , %rcx cmpq %rcx, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movq (%rax), %rax movslq (%rax), %rax cmpq $0x63, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x6, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax @@ -94,14 +80,10 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x7, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/global_struct_return_indirect.aarch64.asm b/tests/snapshots/asm/global_struct_return_indirect.aarch64.asm index 37fe733c0..d1d429728 100644 --- a/tests/snapshots/asm/global_struct_return_indirect.aarch64.asm +++ b/tests/snapshots/asm/global_struct_return_indirect.aarch64.asm @@ -38,10 +38,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xd0 - str x20, [sp] + str x20, [sp, #-0xe0]! + stp x29, x30, [sp, #0xd0] + add x29, sp, #0xd0 sub x8, x29, #0x80 bl sub x0, x29, #0x80 @@ -68,24 +67,23 @@ Disassembly of section .text: mov w0, w0 cmp x0, #0x0 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x18 ldrsw x0, [x0, #0x4] cmp x0, #0x2 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x18 ldrsw x0, [x0, #0x10] cmp x0, #0x5 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldr x20, [sp], #0xe0 ret sub x8, x29, #0xa8 bl @@ -101,14 +99,12 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldr x20, [sp], #0xe0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldr x20, [sp], #0xe0 ret b b diff --git a/tests/snapshots/asm/global_struct_return_indirect.x64.asm b/tests/snapshots/asm/global_struct_return_indirect.x64.asm index df6d4b05b..7b6138a9f 100644 --- a/tests/snapshots/asm/global_struct_return_indirect.x64.asm +++ b/tests/snapshots/asm/global_struct_return_indirect.x64.asm @@ -71,7 +71,7 @@ Disassembly of section .text: testq %rax, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x18(%rbp), %rax @@ -80,16 +80,16 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x18(%rbp), %rax movslq 0x10(%rax), %rax cmpq $0x5, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x1, %eax movq (%rsp), %rbx diff --git a/tests/snapshots/asm/gnu_extension_keyword.aarch64.asm b/tests/snapshots/asm/gnu_extension_keyword.aarch64.asm index 93d4fc358..6b21a6cd1 100644 --- a/tests/snapshots/asm/gnu_extension_keyword.aarch64.asm +++ b/tests/snapshots/asm/gnu_extension_keyword.aarch64.asm @@ -10,40 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] - mov x0, #0x0 // =0 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x1, #0x5 // =5 mov x2, #0x7 // =7 - cmp x0, #0x0 - b.eq - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - cmp x1, #0x5 - b.eq - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - cmp x2, #0x7 - b.eq - mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/gnu_extension_keyword.x64.asm b/tests/snapshots/asm/gnu_extension_keyword.x64.asm index 4fda2c5c3..3f895a555 100644 --- a/tests/snapshots/asm/gnu_extension_keyword.x64.asm +++ b/tests/snapshots/asm/gnu_extension_keyword.x64.asm @@ -13,34 +13,23 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - xorq %rax, %rax movl $0x5, %esi movl $0x7, %edx - testq %rax, %rax - je + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + popq %rbp + retq movl $0x1, %eax - addq $0x40, %rsp popq %rbp retq - cmpq $0x5, %rsi - je movl $0x2, %eax - addq $0x40, %rsp popq %rbp retq - cmpq $0x7, %rdx - je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp - retq - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax - addq $0x40, %rsp popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/goto.aarch64.asm b/tests/snapshots/asm/goto.aarch64.asm index 50c693f0e..5376a8035 100644 --- a/tests/snapshots/asm/goto.aarch64.asm +++ b/tests/snapshots/asm/goto.aarch64.asm @@ -13,17 +13,12 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - mov x1, #0x0 // =0 - add x0, x1, #0x1 - sxtw x1, w0 - cmp x1, #0x5 - b.ge - b - mov x0, x1 + mov x0, #0x5 // =5 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - ldursw x0, [x29, #-0x8] - add x0, x0, #0x64 - stur w0, [x29, #-0x8] + b + ldursw x1, [x29, #-0x8] + add x1, x1, #0x64 + stur w1, [x29, #-0x8] b diff --git a/tests/snapshots/asm/goto.x64.asm b/tests/snapshots/asm/goto.x64.asm index 2020c7f13..2af135766 100644 --- a/tests/snapshots/asm/goto.x64.asm +++ b/tests/snapshots/asm/goto.x64.asm @@ -14,17 +14,13 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - xorq %rcx, %rcx - leaq 0x1(%rcx), %rax - movslq %eax, %rcx - cmpq $0x5, %rcx - jge - jmp - movq %rcx, %rax + movl $0x5, %eax addq $0x10, %rsp popq %rbp retq - movslq -0x8(%rbp), %rax - addq $0x64, %rax - movl %eax, -0x8(%rbp) jmp + movslq -0x8(%rbp), %rcx + addq $0x64, %rcx + movl %ecx, -0x8(%rbp) + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hex_constant_unsigned_type.aarch64.asm b/tests/snapshots/asm/hex_constant_unsigned_type.aarch64.asm index 543bb0ae2..12dd8f7b5 100644 --- a/tests/snapshots/asm/hex_constant_unsigned_type.aarch64.asm +++ b/tests/snapshots/asm/hex_constant_unsigned_type.aarch64.asm @@ -10,44 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - eor x1, x0, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - eor x1, x0, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, ne - cmp x0, #0x0 - b.ne mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/hex_constant_unsigned_type.x64.asm b/tests/snapshots/asm/hex_constant_unsigned_type.x64.asm index 05a911d1f..90f752ca9 100644 --- a/tests/snapshots/asm/hex_constant_unsigned_type.x64.asm +++ b/tests/snapshots/asm/hex_constant_unsigned_type.x64.asm @@ -11,40 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movabsq $-0x1, %rax - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF - xorq %rax, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF - xorq %rax, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - jne movl $0x3, %eax - addq $0x10, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/hex_float_literal.aarch64.asm b/tests/snapshots/asm/hex_float_literal.aarch64.asm index ea6b29c21..34dd5b362 100644 --- a/tests/snapshots/asm/hex_float_literal.aarch64.asm +++ b/tests/snapshots/asm/hex_float_literal.aarch64.asm @@ -83,10 +83,12 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fmov d17, x0 - fcmp d16, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x3ff0000000000000 // =4607182418800017408 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/hex_float_literal.x64.asm b/tests/snapshots/asm/hex_float_literal.x64.asm index ee7d8ce0a..9e4a160ce 100644 --- a/tests/snapshots/asm/hex_float_literal.x64.asm +++ b/tests/snapshots/asm/hex_float_literal.x64.asm @@ -119,10 +119,12 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 movq %rax, %xmm14 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -187,5 +189,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hfa_param_interleave.aarch64.asm b/tests/snapshots/asm/hfa_param_interleave.aarch64.asm index 2f9edcf26..a9f033c9d 100644 --- a/tests/snapshots/asm/hfa_param_interleave.aarch64.asm +++ b/tests/snapshots/asm/hfa_param_interleave.aarch64.asm @@ -124,12 +124,10 @@ Disassembly of section .text: sub x1, x29, #0x10 sub x2, x29, #0x18 sub x3, x29, #0x20 - mov x4, #0x4023000000000000 // =4621537642612260864 - fmov d16, x4 - fcvt s0, d16 - sub x4, x29, #0x28 + mov x4, #0x41180000 // =1092091904 + sub x5, x29, #0x28 sub sp, sp, #0x10 - str d0, [sp] + str x4, [sp] ldr s0, [x0] ldr s1, [x0, #0x4] ldr s2, [x1] @@ -138,15 +136,13 @@ Disassembly of section .text: ldr s5, [x2, #0x4] ldr s6, [x3] ldr s7, [x3, #0x4] - mov x0, x4 + mov x0, x5 ldr x0, [x0] bl add sp, sp, #0x10 - mov x0, #0xc00000000000 // =211106232532992 - movk x0, #0x404b, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x425e0000 // =1113456640 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -164,12 +160,10 @@ Disassembly of section .text: sub x1, x29, #0x30 sub x2, x29, #0x30 sub x3, x29, #0x30 - mov x4, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x4 - fcvt s0, d16 - sub x4, x29, #0x28 + mov x4, #0x3e800000 // =1048576000 + sub x5, x29, #0x28 sub sp, sp, #0x10 - str d0, [sp] + str x4, [sp] ldr s0, [x0] ldr s1, [x0, #0x4] ldr s2, [x1] @@ -178,15 +172,13 @@ Disassembly of section .text: ldr s5, [x2, #0x4] ldr s6, [x3] ldr s7, [x3, #0x4] - mov x0, x4 + mov x0, x5 ldr x0, [x0] bl add sp, sp, #0x10 - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4024, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41240000 // =1092878336 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 diff --git a/tests/snapshots/asm/hfa_param_interleave.x64.asm b/tests/snapshots/asm/hfa_param_interleave.x64.asm index f7058c209..2fbd17c0c 100644 --- a/tests/snapshots/asm/hfa_param_interleave.x64.asm +++ b/tests/snapshots/asm/hfa_param_interleave.x64.asm @@ -115,11 +115,9 @@ Disassembly of section .text: leaq -0x10(%rbp), %rsi leaq -0x18(%rbp), %rdx leaq -0x20(%rbp), %rcx - movabsq $0x4023000000000000, %rax # imm = 0x4023000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - leaq -0x28(%rbp), %r8 - movapd %xmm0, %xmm4 + movl $0x41180000, %r8d # imm = 0x41180000 + leaq -0x28(%rbp), %r9 + movq %r8, %xmm4 movq %rdi, %r10 movsd (%r10,%riz), %xmm0 movq %rsi, %r10 @@ -128,13 +126,12 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm2 movq %rcx, %r10 movsd (%r10,%riz), %xmm3 - movq %r8, %rdi + movq %r9, %rdi movq (%rdi), %rdi callq - movabsq $0x404bc00000000000, %rax # imm = 0x404BC00000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x425e0000, %eax # imm = 0x425E0000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -156,11 +153,9 @@ Disassembly of section .text: leaq -0x30(%rbp), %rsi leaq -0x30(%rbp), %rdx leaq -0x30(%rbp), %rcx - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - leaq -0x28(%rbp), %r8 - movapd %xmm0, %xmm4 + movl $0x3e800000, %r8d # imm = 0x3E800000 + leaq -0x28(%rbp), %r9 + movq %r8, %xmm4 movq %rdi, %r10 movsd (%r10,%riz), %xmm0 movq %rsi, %r10 @@ -169,13 +164,12 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm2 movq %rcx, %r10 movsd (%r10,%riz), %xmm3 - movq %r8, %rdi + movq %r9, %rdi movq (%rdi), %rdi callq - movabsq $0x4024800000000000, %rax # imm = 0x4024800000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41240000, %eax # imm = 0x41240000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -191,4 +185,5 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hfa_struct_return.aarch64.asm b/tests/snapshots/asm/hfa_struct_return.aarch64.asm index 0fcdc0bb9..67bd9e5ea 100644 --- a/tests/snapshots/asm/hfa_struct_return.aarch64.asm +++ b/tests/snapshots/asm/hfa_struct_return.aarch64.asm @@ -170,7 +170,6 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x170 str x20, [sp] - str x21, [sp, #0x8] mov x20, #0x401c000000000000 // =4619567317775286272 fmov d0, x20 bl @@ -191,7 +190,6 @@ Disassembly of section .text: cbz x0, mov x0, #0x1 // =1 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -216,18 +214,17 @@ Disassembly of section .text: ldr d0, [x0] fmov d17, x20 fcmp d0, d17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x20 ldr d0, [x0, #0x8] mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d17, x0 fcmp d0, d17 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -258,7 +255,7 @@ Disassembly of section .text: fmov d17, x20 fcmp d0, d17 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x48 ldr d0, [x0, #0x8] @@ -267,18 +264,17 @@ Disassembly of section .text: fcmp d0, d17 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x48 ldr d0, [x0, #0x10] mov x0, #0x4008000000000000 // =4613937818241073152 fmov d17, x0 fcmp d0, d17 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x3 // =3 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -314,7 +310,7 @@ Disassembly of section .text: fmov d17, x20 fcmp d0, d17 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x80 ldr d0, [x0, #0x8] @@ -323,9 +319,9 @@ Disassembly of section .text: fcmp d0, d17 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x80 ldr d0, [x0, #0x10] mov x0, #0x403e000000000000 // =4629137466983448576 @@ -333,27 +329,24 @@ Disassembly of section .text: fcmp d0, d17 cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x80 ldr d0, [x0, #0x18] mov x0, #0x4044000000000000 // =4630826316843712512 fmov d17, x0 fcmp d0, d17 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x4 // =4 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov d0, x20 + fmov d1, x1 bl sub x16, x29, #0x150 str s0, [x16] @@ -367,22 +360,19 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0xa8 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 - cset x20, ne - cbnz x20, + fmov s17, w20 + fcmp s0, s17 + cset x1, ne + cbnz x1, sub x0, x29, #0xa8 ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 - cset x20, ne - cbz x20, + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 + cset x1, ne + cbz x1, mov x0, #0x5 // =5 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -406,7 +396,6 @@ Disassembly of section .text: cbz x0, mov x0, #0x6 // =6 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -423,7 +412,6 @@ Disassembly of section .text: cbz x0, mov x0, #0x7 // =7 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret @@ -433,21 +421,18 @@ Disassembly of section .text: ldr s2, [x0, #0x8] ldr s3, [x0, #0xc] bl - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/hfa_struct_return.x64.asm b/tests/snapshots/asm/hfa_struct_return.x64.asm index eae9f0c0b..5643675aa 100644 --- a/tests/snapshots/asm/hfa_struct_return.x64.asm +++ b/tests/snapshots/asm/hfa_struct_return.x64.asm @@ -222,7 +222,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x180, %rsp # imm = 0x180 movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) movabsq $0x401c000000000000, %rbx # imm = 0x401C000000000000 movq %rbx, %xmm0 callq @@ -247,7 +246,6 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -271,28 +269,27 @@ Disassembly of section .text: movsd (%rax,%riz), %xmm0 movq %rbx, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x20(%rbp), %rax movsd 0x8(%rax,%riz), %xmm0 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -322,7 +319,7 @@ Disassembly of section .text: setp %r10b movzbq %r10b, %r10 orq %r10, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x48(%rbp), %rax @@ -336,25 +333,24 @@ Disassembly of section .text: movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x48(%rbp), %rax movsd 0x10(%rax,%riz), %xmm0 movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %dl + movzbq %dl, %rdx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rdx + testq %rdx, %rdx je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -387,7 +383,7 @@ Disassembly of section .text: setp %r10b movzbq %r10b, %r10 orq %r10, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x80(%rbp), %rax @@ -401,10 +397,10 @@ Disassembly of section .text: movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x80(%rbp), %rax movsd 0x10(%rax,%riz), %xmm0 @@ -417,34 +413,31 @@ Disassembly of section .text: movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x80(%rbp), %rax movsd 0x18(%rax,%riz), %xmm0 movabsq $0x4044000000000000, %rax # imm = 0x4044000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r12b - movzbq %r12b, %r12 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r12 - testq %r12, %r12 + orq %r10, %rcx + testq %rcx, %rcx je movl $0x4, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %esi # imm = 0x40200000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 callq movsd %xmm0, -0x160(%rbp,%riz) leaq -0x160(%rbp), %rax @@ -456,32 +449,29 @@ Disassembly of section .text: movq %rcx, %rax leaq -0xa8(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0xa8(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx je movl $0x5, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -510,7 +500,6 @@ Disassembly of section .text: je movl $0x6, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -539,7 +528,6 @@ Disassembly of section .text: je movl $0x7, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq @@ -548,10 +536,9 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm0 movsd 0x8(%r10,%riz), %xmm1 callq - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -561,13 +548,11 @@ Disassembly of section .text: je movl $0x8, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x180, %rsp # imm = 0x180 popq %rbp retq diff --git a/tests/snapshots/asm/implicit_int_decl.aarch64.asm b/tests/snapshots/asm/implicit_int_decl.aarch64.asm index 824afecb9..169af0df0 100644 --- a/tests/snapshots/asm/implicit_int_decl.aarch64.asm +++ b/tests/snapshots/asm/implicit_int_decl.aarch64.asm @@ -15,13 +15,6 @@ Disassembly of section .text: ret
: - mov x0, #0x29 // =41 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x2a - b.eq - mov x0, #0x1 // =1 - ret adrp x0, add x0, x0, ldrsw x0, [x0] @@ -31,3 +24,5 @@ Disassembly of section .text: ret mov x0, #0x0 // =0 ret + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/implicit_int_decl.x64.asm b/tests/snapshots/asm/implicit_int_decl.x64.asm index dc018b616..298f5771b 100644 --- a/tests/snapshots/asm/implicit_int_decl.x64.asm +++ b/tests/snapshots/asm/implicit_int_decl.x64.asm @@ -16,13 +16,6 @@ Disassembly of section .text: retq
: - movl $0x29, %eax - incq %rax - movslq %eax, %rax - cmpq $0x2a, %rax - je - movl $0x1, %eax - retq leaq , %rax movslq (%rax), %rax cmpq $0x5, %rax @@ -31,4 +24,6 @@ Disassembly of section .text: retq xorq %rax, %rax retq + movl $0x1, %eax + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inc_dec_step_one.aarch64.asm b/tests/snapshots/asm/inc_dec_step_one.aarch64.asm index d94c406a3..cb1158d88 100644 --- a/tests/snapshots/asm/inc_dec_step_one.aarch64.asm +++ b/tests/snapshots/asm/inc_dec_step_one.aarch64.asm @@ -31,16 +31,13 @@ Disassembly of section .text: sxtw x0, w0 mov x2, #0x0 // =0 mov x1, x2 - sxtw x3, w2 - cmp x3, x0 - b.ge - b - sxtw x2, w2 - add x2, x2, #0x1 b add x1, x1, #0x1 sxtw x1, w1 - b + add x2, x3, #0x1 + sxtw x3, w2 + cmp x3, x0 + b.lt sxtw x0, w1 ret @@ -53,67 +50,31 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - mov x0, #0x29 // =41 - add x0, x0, #0x1 - sxtw x0, w0 + mov x0, #0x2a // =42 + bl cmp x0, #0x2a b.eq + mov x0, #0x5 // =5 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret mov x0, #0x1 // =1 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x2b // =43 - sub x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x2a - b.eq mov x0, #0x2 // =2 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xe3ff // =58367 - movk x0, #0x540b, lsl #16 - movk x0, #0x2, lsl #32 - add x0, x0, #0x1 - mov x17, #0xe400 // =58368 - movk x17, #0x540b, lsl #16 - movk x17, #0x2, lsl #32 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x29 // =41 - add x0, x0, #0x1 - cmp x0, #0x2a - b.eq mov x0, #0x4 // =4 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x2a // =42 - bl - cmp x0, #0x2a - b.eq - mov x0, #0x5 // =5 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov w0, w0 - add x0, x0, #0x1 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x6 // =6 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x29 // =41 - mov w0, w0 - add x0, x0, #0x1 - mov w0, w0 - cmp x0, #0x2a - b.eq mov x0, #0x7 // =7 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/inc_dec_step_one.x64.asm b/tests/snapshots/asm/inc_dec_step_one.x64.asm index 9f87306bb..1a6e054a7 100644 --- a/tests/snapshots/asm/inc_dec_step_one.x64.asm +++ b/tests/snapshots/asm/inc_dec_step_one.x64.asm @@ -32,16 +32,13 @@ Disassembly of section .text: movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq %rdi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp incq %rax movslq %eax, %rax - jmp + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq %rdi, %rdx + jl movslq %eax, %rax retq @@ -54,64 +51,31 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - movl $0x29, %eax - incq %rax - movslq %eax, %rax + movl $0x2a, %edi + callq cmpq $0x2a, %rax je + movl $0x5, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq movl $0x1, %eax popq %rbp retq - movl $0x2b, %eax - decq %rax - movslq %eax, %rax - cmpq $0x2a, %rax - je movl $0x2, %eax popq %rbp retq - movabsq $0x2540be3ff, %rax # imm = 0x2540BE3FF - incq %rax - movabsq $0x2540be400, %r11 # imm = 0x2540BE400 - cmpq %r11, %rax - je movl $0x3, %eax popq %rbp retq - movl $0x29, %eax - incq %rax - cmpq $0x2a, %rax - je movl $0x4, %eax popq %rbp retq - movl $0x2a, %edi - callq - cmpq $0x2a, %rax - je - movl $0x5, %eax - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl %eax, %eax - incq %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x6, %eax popq %rbp retq - movl $0x29, %eax - movl %eax, %eax - incq %rax - movl %eax, %eax - cmpq $0x2a, %rax - je movl $0x7, %eax popq %rbp retq - xorq %rax, %rax - popq %rbp - retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/include_macro_operand.aarch64.asm b/tests/snapshots/asm/include_macro_operand.aarch64.asm index 20c0aac4b..aa8137b3c 100644 --- a/tests/snapshots/asm/include_macro_operand.aarch64.asm +++ b/tests/snapshots/asm/include_macro_operand.aarch64.asm @@ -10,56 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x2a // =42 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x8 // =8 bl cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret bl sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - b.eq + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x21, #0x2a - b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/include_macro_operand.x64.asm b/tests/snapshots/asm/include_macro_operand.x64.asm index 0a689f4ed..cfc3df1e2 100644 --- a/tests/snapshots/asm/include_macro_operand.x64.asm +++ b/tests/snapshots/asm/include_macro_operand.x64.asm @@ -13,11 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movabsq $-0x1, %rbx - movl $0x2a, %r12d movl $0x8, %edi xorl %eax, %eax callq @@ -25,34 +20,17 @@ Disassembly of section .text: testq %rdi, %rdi jne movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp popq %rbp retq xorl %eax, %eax callq movslq %eax, %rax - cmpq $-0x1, %rbx - je - movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp + xorq %rax, %rax popq %rbp retq - cmpq $0x2a, %r12 - je - movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp + movl $0x2, %eax popq %rbp retq - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp + movl $0x3, %eax popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/indexed_load_store.aarch64.asm b/tests/snapshots/asm/indexed_load_store.aarch64.asm index 90ce90916..750629671 100644 --- a/tests/snapshots/asm/indexed_load_store.aarch64.asm +++ b/tests/snapshots/asm/indexed_load_store.aarch64.asm @@ -10,68 +10,88 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x2, w2 mov x5, #0x0 // =0 mov x4, x5 - sxtw x6, w4 - cmp x6, x2 - b.ge - b - sxtw x4, w4 - add x4, x4, #0x1 b - sxtw x6, w4 - lsl x6, x6, #2 - add x7, x0, x6 - ldrsw x8, [x7] - add x8, x8, x3 - add x6, x1, x6 - ldrsw x6, [x6] - sub x6, x6, x3 - str w6, [x7] - sxtw x6, w4 - str w8, [x1, x6, lsl #2] - sxtw x6, w4 - lsl x6, x6, #2 - add x7, x0, x6 + lsl x7, x6, #2 + add x8, x0, x7 + ldrsw x9, [x8] + add x9, x9, x3 + add x7, x1, x7 + ldrsw x7, [x7] + sub x7, x7, x3 + str w7, [x8] + str w9, [x1, x6, lsl #2] + lsl x7, x6, #2 + add x8, x0, x7 + ldrsw x8, [x8] + add x7, x1, x7 ldrsw x7, [x7] - add x6, x1, x6 - ldrsw x6, [x6] - mul x6, x7, x6 - add x5, x5, x6 + mul x7, x8, x7 + add x5, x5, x7 sxtw x5, w5 - b + add x4, x6, #0x1 + sxtw x6, w4 + cmp x6, x2 + b.lt sxtw x0, w5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x70 - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b sub x0, x29, #0x20 - sxtw x2, w1 - add x3, x2, #0x1 - str w3, [x0, x2, lsl #2] + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str w1, [x0] sub x0, x29, #0x40 - sxtw x2, w1 - add x3, x2, #0x1 - mov x17, #0xa // =10 - mul x3, x3, x17 - str w3, [x0, x2, lsl #2] - b + add x0, x0, #0x0 + mov x1, #0xa // =10 + str w1, [x0] + sub x0, x29, #0x20 + mov x1, #0x2 // =2 + str w1, [x0, #0x4] + sub x0, x29, #0x40 + mov x1, #0x14 // =20 + str w1, [x0, #0x4] + sub x0, x29, #0x20 + mov x1, #0x3 // =3 + str w1, [x0, #0x8] + sub x0, x29, #0x40 + mov x1, #0x1e // =30 + str w1, [x0, #0x8] + sub x0, x29, #0x20 + mov x1, #0x4 // =4 + str w1, [x0, #0xc] + sub x0, x29, #0x40 + mov x1, #0x28 // =40 + str w1, [x0, #0xc] + sub x0, x29, #0x20 + mov x1, #0x5 // =5 + str w1, [x0, #0x10] + sub x0, x29, #0x40 + mov x1, #0x32 // =50 + str w1, [x0, #0x10] + sub x0, x29, #0x20 + mov x1, #0x6 // =6 + str w1, [x0, #0x14] + sub x0, x29, #0x40 + mov x1, #0x3c // =60 + str w1, [x0, #0x14] + sub x0, x29, #0x20 + mov x1, #0x7 // =7 + str w1, [x0, #0x18] + sub x0, x29, #0x40 + mov x1, #0x46 // =70 + str w1, [x0, #0x18] + sub x0, x29, #0x20 + mov x1, #0x8 // =8 + str w1, [x0, #0x1c] + sub x0, x29, #0x40 + mov x1, #0x50 // =80 + str w1, [x0, #0x1c] sub x0, x29, #0x20 sub x1, x29, #0x40 mov x2, #0x8 // =8 @@ -80,9 +100,9 @@ Disassembly of section .text: cmp x0, #0xb7c b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/indexed_load_store.x64.asm b/tests/snapshots/asm/indexed_load_store.x64.asm index ec4045955..cdd21930c 100644 --- a/tests/snapshots/asm/indexed_load_store.x64.asm +++ b/tests/snapshots/asm/indexed_load_store.x64.asm @@ -13,46 +13,44 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) movslq %edx, %rdx xorq %r8, %r8 movq %r8, %rax - movslq %eax, %r9 - cmpq %rdx, %r9 - jge - jmp - movslq %eax, %rax - incq %rax jmp - movslq %eax, %r9 - shlq $0x2, %r9 - leaq (%rdi,%r9), %rbx - movslq (%rbx), %r12 - addq %rcx, %r12 - addq %rsi, %r9 - movslq (%r9), %r9 - subq %rcx, %r9 - movl %r9d, (%rbx) - movslq %eax, %r9 - movl %r12d, (%rsi,%r9,4) - movslq %eax, %r9 - shlq $0x2, %r9 - leaq (%rdi,%r9), %rbx + movq %r9, %rbx + shlq $0x2, %rbx + leaq (%rdi,%rbx), %r12 + movslq (%r12), %r13 + addq %rcx, %r13 + addq %rsi, %rbx + movslq (%rbx), %rbx + subq %rcx, %rbx + movl %ebx, (%r12) + movl %r13d, (%rsi,%r9,4) + movq %r9, %rbx + shlq $0x2, %rbx + leaq (%rdi,%rbx), %r12 + movslq (%r12), %r12 + addq %rsi, %rbx movslq (%rbx), %rbx - addq %rsi, %r9 - movslq (%r9), %r9 - imulq %rbx, %r9 - addq %r9, %r8 + imulq %r12, %rbx + addq %rbx, %r8 movslq %r8d, %r8 - jmp + leaq 0x1(%r9), %rax + movslq %eax, %r9 + cmpq %rdx, %r9 + jl movslq %r8d, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x40, %rsp + movq 0x18(%rsp), %r14 + addq $0x20, %rsp popq %rbp retq @@ -60,24 +58,56 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x70, %rsp - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x20(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movl %esi, (%rax,%rdx,4) + addq $0x0, %rax + movl $0x1, %ecx + movl %ecx, (%rax) leaq -0x40(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - imulq $0xa, %rsi, %rsi - movl %esi, (%rax,%rdx,4) - jmp + addq $0x0, %rax + movl $0xa, %ecx + movl %ecx, (%rax) + leaq -0x20(%rbp), %rax + movl $0x2, %ecx + movl %ecx, 0x4(%rax) + leaq -0x40(%rbp), %rax + movl $0x14, %ecx + movl %ecx, 0x4(%rax) + leaq -0x20(%rbp), %rax + movl $0x3, %ecx + movl %ecx, 0x8(%rax) + leaq -0x40(%rbp), %rax + movl $0x1e, %ecx + movl %ecx, 0x8(%rax) + leaq -0x20(%rbp), %rax + movl $0x4, %ecx + movl %ecx, 0xc(%rax) + leaq -0x40(%rbp), %rax + movl $0x28, %ecx + movl %ecx, 0xc(%rax) + leaq -0x20(%rbp), %rax + movl $0x5, %ecx + movl %ecx, 0x10(%rax) + leaq -0x40(%rbp), %rax + movl $0x32, %ecx + movl %ecx, 0x10(%rax) + leaq -0x20(%rbp), %rax + movl $0x6, %ecx + movl %ecx, 0x14(%rax) + leaq -0x40(%rbp), %rax + movl $0x3c, %ecx + movl %ecx, 0x14(%rax) + leaq -0x20(%rbp), %rax + movl $0x7, %ecx + movl %ecx, 0x18(%rax) + leaq -0x40(%rbp), %rax + movl $0x46, %ecx + movl %ecx, 0x18(%rax) + leaq -0x20(%rbp), %rax + movl $0x8, %ecx + movl %ecx, 0x1c(%rax) + leaq -0x40(%rbp), %rax + movl $0x50, %ecx + movl %ecx, 0x1c(%rax) leaq -0x20(%rbp), %rdi leaq -0x40(%rbp), %rsi movl $0x8, %edx @@ -86,10 +116,10 @@ Disassembly of section .text: cmpq $0xb7c, %rax # imm = 0xB7C jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x70, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/indexed_swap_shared_addr.aarch64.asm b/tests/snapshots/asm/indexed_swap_shared_addr.aarch64.asm index 4b496aba0..fc6e8b40f 100644 --- a/tests/snapshots/asm/indexed_swap_shared_addr.aarch64.asm +++ b/tests/snapshots/asm/indexed_swap_shared_addr.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x1, w1 sxtw x2, w2 ldr x3, [x0, x1, lsl #3] @@ -20,29 +17,28 @@ Disassembly of section .text: str x4, [x0, x1, lsl #3] str x3, [x0, x2, lsl #3] mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x5 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b + str x20, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x28 - sxtw x2, w1 - add x3, x2, #0x1 - sxtw x3, w3 - str x3, [x0, x2, lsl #3] - b + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str x1, [x0] + sub x0, x29, #0x28 + mov x1, #0x2 // =2 + str x1, [x0, #0x8] + sub x0, x29, #0x28 + mov x1, #0x3 // =3 + str x1, [x0, #0x10] + sub x0, x29, #0x28 + mov x1, #0x4 // =4 + str x1, [x0, #0x18] + sub x0, x29, #0x28 + mov x1, #0x5 // =5 + str x1, [x0, #0x20] sub x0, x29, #0x28 mov x20, #0x0 // =0 mov x2, #0x4 // =4 @@ -88,14 +84,12 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x20, [sp], #0x90 ret b b diff --git a/tests/snapshots/asm/indexed_swap_shared_addr.x64.asm b/tests/snapshots/asm/indexed_swap_shared_addr.x64.asm index 97eca6b70..b33ebd72b 100644 --- a/tests/snapshots/asm/indexed_swap_shared_addr.x64.asm +++ b/tests/snapshots/asm/indexed_swap_shared_addr.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %esi, %rsi movslq %edx, %rdx movq (%rdi,%rsi,8), %rax @@ -21,8 +18,6 @@ Disassembly of section .text: movq %rcx, (%rdi,%rsi,8) movq %rax, (%rdi,%rdx,8) xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -30,20 +25,22 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x80, %rsp movq %rbx, (%rsp) - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x28(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movslq %esi, %rsi - movq %rsi, (%rax,%rdx,8) - jmp + addq $0x0, %rax + movl $0x1, %ecx + movq %rcx, (%rax) + leaq -0x28(%rbp), %rax + movl $0x2, %ecx + movq %rcx, 0x8(%rax) + leaq -0x28(%rbp), %rax + movl $0x3, %ecx + movq %rcx, 0x10(%rax) + leaq -0x28(%rbp), %rax + movl $0x4, %ecx + movq %rcx, 0x18(%rax) + leaq -0x28(%rbp), %rax + movl $0x5, %ecx + movq %rcx, 0x20(%rax) leaq -0x28(%rbp), %rdi xorq %rbx, %rbx movl $0x4, %edx @@ -115,4 +112,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/indirect_call_mixed_fp_int_args.aarch64.asm b/tests/snapshots/asm/indirect_call_mixed_fp_int_args.aarch64.asm new file mode 100644 index 000000000..b21642b66 --- /dev/null +++ b/tests/snapshots/asm/indirect_call_mixed_fp_int_args.aarch64.asm @@ -0,0 +1,106 @@ + +indirect_call_mixed_fp_int_args.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x3, #0x4024000000000000 // =4621819117588971520 + fmov d17, x3 + fmul d0, d0, d17 + fcvtzs x3, d0 + add x0, x0, x3 + add x0, x0, x1 + mov x1, #0x4059000000000000 // =4636737291354636288 + fmov d17, x1 + fmul d0, d1, d17 + fcvtzs x1, d0 + add x0, x0, x1 + mov x1, #0x40000000 // =1073741824 + fmov s17, w1 + fmul s0, s2, s17 + fcvt d0, s0 + fcvtzs x1, d0 + add x0, x0, x1 + add x0, x0, x2 + sxtw x0, w0 + ret + +
: + str d8, [sp, #-0x40]! + str x20, [sp, #0x10] + str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldrsw x20, [x1] + adrp x1, + add x1, x1, + ldr d8, [x1] + add x1, x20, #0x2 + sxtw x1, w1 + mov x2, #0x3fd0000000000000 // =4598175219545276416 + mov x3, #0x3fc00000 // =1069547520 + mov x4, #0x7 // =7 + mov x9, x0 + fmov d0, d8 + fmov d1, x2 + fmov d2, x3 + mov x0, x20 + mov x2, x4 + blr x9 + sxtw x0, w0 + cmp x0, #0x40 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp, #0x20] + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 + ret + add x2, x20, #0x2 + mov x4, #0x3fd0000000000000 // =4598175219545276416 + mov x5, #0x3fc00000 // =1069547520 + mov x1, #0x4024000000000000 // =4621819117588971520 + fmov d17, x1 + fmul d0, d8, d17 + fcvtzs x1, d0 + add x1, x20, x1 + add x1, x1, x2 + mov x2, #0x4059000000000000 // =4636737291354636288 + fmov d16, x4 + fmov d17, x2 + fmul d0, d16, d17 + fcvtzs x2, d0 + add x1, x1, x2 + mov x2, #0x40000000 // =1073741824 + fmov s16, w5 + fmov s17, w2 + fmul s0, s16, s17 + fcvt d0, s0 + fcvtzs x2, d0 + add x1, x1, x2 + add x1, x1, #0x7 + sxtw x1, w1 + cmp x0, x1 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp, #0x20] + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp, #0x20] + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 + ret diff --git a/tests/snapshots/asm/indirect_call_mixed_fp_int_args.x64.asm b/tests/snapshots/asm/indirect_call_mixed_fp_int_args.x64.asm new file mode 100644 index 000000000..90cfe801b --- /dev/null +++ b/tests/snapshots/asm/indirect_call_mixed_fp_int_args.x64.asm @@ -0,0 +1,104 @@ + +indirect_call_mixed_fp_int_args.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 + movq %rax, %xmm15 + mulsd %xmm15, %xmm0 + cvttsd2si %xmm0, %rax + addq %rdi, %rax + addq %rsi, %rax + movabsq $0x4059000000000000, %rcx # imm = 0x4059000000000000 + movq %rcx, %xmm15 + movapd %xmm1, %xmm0 + mulsd %xmm15, %xmm0 + cvttsd2si %xmm0, %rcx + addq %rcx, %rax + movl $0x40000000, %ecx # imm = 0x40000000 + movq %rcx, %xmm15 + movapd %xmm2, %xmm0 + mulss %xmm15, %xmm0 + cvtss2sd %xmm0, %xmm0 + cvttsd2si %xmm0, %rcx + addq %rcx, %rax + addq %rdx, %rax + movslq %eax, %rax + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + leaq -, %rax # + leaq , %rcx + movslq (%rcx), %rbx + leaq , %rcx + movsd (%rcx,%riz), %xmm14 + movsd %xmm14, 0x18(%rsp) + leaq 0x2(%rbx), %rcx + movslq %ecx, %rsi + movabsq $0x3fd0000000000000, %rdx # imm = 0x3FD0000000000000 + movl $0x3fc00000, %ecx # imm = 0x3FC00000 + movl $0x7, %r8d + movsd 0x18(%rsp), %xmm0 + movq %rdx, %xmm1 + movq %rcx, %xmm2 + movq %rbx, %rdi + movq %r8, %rdx + callq *%rax + movslq %eax, %rax + cmpq $0x40, %rax + je + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x20, %rsp + popq %rbp + retq + leaq 0x2(%rbx), %rdx + movabsq $0x3fd0000000000000, %rdi # imm = 0x3FD0000000000000 + movl $0x3fc00000, %r8d # imm = 0x3FC00000 + movabsq $0x4024000000000000, %rcx # imm = 0x4024000000000000 + movq %rcx, %xmm15 + movsd 0x18(%rsp), %xmm0 + mulsd %xmm15, %xmm0 + cvttsd2si %xmm0, %rcx + addq %rbx, %rcx + addq %rdx, %rcx + movabsq $0x4059000000000000, %rdx # imm = 0x4059000000000000 + movq %rdx, %xmm15 + movq %rdi, %xmm0 + mulsd %xmm15, %xmm0 + cvttsd2si %xmm0, %rdx + addq %rdx, %rcx + movl $0x40000000, %edx # imm = 0x40000000 + movq %rdx, %xmm15 + movq %r8, %xmm0 + mulss %xmm15, %xmm0 + cvtss2sd %xmm0, %xmm0 + cvttsd2si %xmm0, %rdx + addq %rdx, %rcx + addq $0x7, %rcx + movslq %ecx, %rcx + cmpq %rcx, %rax + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x20, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x20, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/indirect_call_narrow_scalar_args.aarch64.asm b/tests/snapshots/asm/indirect_call_narrow_scalar_args.aarch64.asm new file mode 100644 index 000000000..aed0689e9 --- /dev/null +++ b/tests/snapshots/asm/indirect_call_narrow_scalar_args.aarch64.asm @@ -0,0 +1,72 @@ + +indirect_call_narrow_scalar_args.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sxtb x0, w0 + sxth x1, w1 + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + mul x0, x0, x17 + mov x17, #0xa // =10 + mul x1, x1, x17 + add x0, x0, x1 + add x0, x0, x2 + sxtw x0, w0 + ret + +
: + str x20, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldrsw x1, [x1] + sxtw x2, w1 + sxtb x3, w2 + sxth x4, w2 + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + mul x2, x3, x17 + mov x17, #0xa // =10 + mul x3, x4, x17 + add x2, x2, x3 + add x2, x2, x1 + sxtw x20, w2 + mov x9, x0 + mov x0, x1 + mov x2, x1 + blr x9 + sxtw x0, w0 + sxtw x1, w20 + cmp x1, x0 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret + mov x17, #0xcd17 // =52503 + movk x17, #0x6b, lsl #16 + cmp x0, x17 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret diff --git a/tests/snapshots/asm/indirect_call_narrow_scalar_args.x64.asm b/tests/snapshots/asm/indirect_call_narrow_scalar_args.x64.asm new file mode 100644 index 000000000..49ca3c60f --- /dev/null +++ b/tests/snapshots/asm/indirect_call_narrow_scalar_args.x64.asm @@ -0,0 +1,63 @@ + +indirect_call_narrow_scalar_args.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movsbq %dil, %rdi + movswq %si, %rsi + imulq $0x186a0, %rdi, %rax # imm = 0x186A0 + imulq $0xa, %rsi, %rcx + addq %rcx, %rax + addq %rdx, %rax + movslq %eax, %rax + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + leaq -, %rax # + leaq , %rcx + movslq (%rcx), %rdi + movslq %edi, %rcx + movsbq %cl, %rdx + movswq %cx, %rsi + imulq $0x186a0, %rdx, %rcx # imm = 0x186A0 + imulq $0xa, %rsi, %rdx + addq %rdx, %rcx + addq %rdi, %rcx + movslq %ecx, %rbx + movq %rdi, %rsi + movq %rdi, %rdx + callq *%rax + movslq %eax, %rax + movslq %ebx, %rcx + cmpq %rax, %rcx + je + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + cmpq $0x6bcd17, %rax # imm = 0x6BCD17 + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/indirect_call_six_args_spilled_target.aarch64.asm b/tests/snapshots/asm/indirect_call_six_args_spilled_target.aarch64.asm index cb0bf9aad..87415f66b 100644 --- a/tests/snapshots/asm/indirect_call_six_args_spilled_target.aarch64.asm +++ b/tests/snapshots/asm/indirect_call_six_args_spilled_target.aarch64.asm @@ -24,36 +24,26 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x5, #0x0 // =0 stur w5, [x29, #-0x8] ldr x5, [x0] sub x6, x29, #0x8 add x1, x1, #0x10 add x3, x3, #0x10 - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x6, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x5 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] - ldr x4, [sp, #0x40] - ldr x5, [sp, #0x50] + mov x5, x4 + mov x4, x3 + mov x3, x2 + mov x2, x1 + mov x1, x6 blr x9 - add sp, sp, #0x60 ldursw x1, [x29, #-0x8] add x0, x0, x1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret
: @@ -79,9 +69,9 @@ Disassembly of section .text: cmp x0, #0xc0d b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/indirect_call_six_args_spilled_target.x64.asm b/tests/snapshots/asm/indirect_call_six_args_spilled_target.x64.asm index bd0b8f8ca..ce2426efd 100644 --- a/tests/snapshots/asm/indirect_call_six_args_spilled_target.x64.asm +++ b/tests/snapshots/asm/indirect_call_six_args_spilled_target.x64.asm @@ -67,10 +67,10 @@ Disassembly of section .text: cmpq $0xc0d, %rax # imm = 0xC0D jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x80, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/indirect_call_target_scratch_exhausted.aarch64.asm b/tests/snapshots/asm/indirect_call_target_scratch_exhausted.aarch64.asm index 2cf53c42d..ae17cfda8 100644 --- a/tests/snapshots/asm/indirect_call_target_scratch_exhausted.aarch64.asm +++ b/tests/snapshots/asm/indirect_call_target_scratch_exhausted.aarch64.asm @@ -256,34 +256,128 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xd0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 adrp x0, add x0, x0, adrp x20, add x20, x20, + mov x1, #0x0 // =0 + adrp x2, + add x2, x2, + add x3, x2, #0x0 + str x1, [x3] + add x1, x2, #0x0 mov x2, #0x0 // =0 - cmp x2, #0x10 - b.ge - b - add x2, x2, #0x1 - b - adrp x1, - add x1, x1, - lsl x3, x2, #4 - add x3, x1, x3 - str x2, [x3] - lsl x3, x2, #4 - add x1, x1, x3 - lsl x3, x2, #1 - str x3, [x1, #0x8] - b + str x2, [x1, #0x8] + mov x1, #0x1 // =1 + adrp x2, + add x2, x2, + str x1, [x2, #0x10] + add x1, x2, #0x10 + mov x2, #0x2 // =2 + str x2, [x1, #0x8] + mov x1, #0x2 // =2 + adrp x2, + add x2, x2, + str x1, [x2, #0x20] + add x1, x2, #0x20 + mov x2, #0x4 // =4 + str x2, [x1, #0x8] + mov x1, #0x3 // =3 + adrp x2, + add x2, x2, + str x1, [x2, #0x30] + add x1, x2, #0x30 + mov x2, #0x6 // =6 + str x2, [x1, #0x8] + mov x1, #0x4 // =4 + adrp x2, + add x2, x2, + str x1, [x2, #0x40] + add x1, x2, #0x40 + mov x2, #0x8 // =8 + str x2, [x1, #0x8] + mov x1, #0x5 // =5 + adrp x2, + add x2, x2, + str x1, [x2, #0x50] + add x1, x2, #0x50 + mov x2, #0xa // =10 + str x2, [x1, #0x8] + mov x1, #0x6 // =6 + adrp x2, + add x2, x2, + str x1, [x2, #0x60] + add x1, x2, #0x60 + mov x2, #0xc // =12 + str x2, [x1, #0x8] + mov x1, #0x7 // =7 + adrp x2, + add x2, x2, + str x1, [x2, #0x70] + add x1, x2, #0x70 + mov x2, #0xe // =14 + str x2, [x1, #0x8] + mov x1, #0x8 // =8 + adrp x2, + add x2, x2, + str x1, [x2, #0x80] + add x1, x2, #0x80 + mov x2, #0x10 // =16 + str x2, [x1, #0x8] + mov x1, #0x9 // =9 + adrp x2, + add x2, x2, + str x1, [x2, #0x90] + add x1, x2, #0x90 + mov x2, #0x12 // =18 + str x2, [x1, #0x8] + mov x1, #0xa // =10 + adrp x2, + add x2, x2, + str x1, [x2, #0xa0] + add x1, x2, #0xa0 + mov x2, #0x14 // =20 + str x2, [x1, #0x8] + mov x1, #0xb // =11 + adrp x2, + add x2, x2, + str x1, [x2, #0xb0] + add x1, x2, #0xb0 + mov x2, #0x16 // =22 + str x2, [x1, #0x8] + mov x1, #0xc // =12 + adrp x2, + add x2, x2, + str x1, [x2, #0xc0] + add x1, x2, #0xc0 + mov x2, #0x18 // =24 + str x2, [x1, #0x8] + mov x1, #0xd // =13 + adrp x2, + add x2, x2, + str x1, [x2, #0xd0] + add x1, x2, #0xd0 + mov x2, #0x1a // =26 + str x2, [x1, #0x8] + mov x1, #0xe // =14 + adrp x2, + add x2, x2, + str x1, [x2, #0xe0] + add x1, x2, #0xe0 + mov x2, #0x1c // =28 + str x2, [x1, #0x8] + mov x1, #0xf // =15 + adrp x2, + add x2, x2, + str x1, [x2, #0xf0] + add x1, x2, #0xf0 + mov x2, #0x1e // =30 + str x2, [x1, #0x8] mov x1, #0x1 // =1 mov x2, #0x2 // =2 mov x3, #0x3 // =3 @@ -301,64 +395,36 @@ Disassembly of section .text: mov x15, #0xf // =15 mov x21, #0x10 // =16 mov x22, #0x11 // =17 - str x22, [sp, #-0x10]! - str x21, [sp, #-0x10]! - str x15, [sp, #-0x10]! - str x14, [sp, #-0x10]! - str x13, [sp, #-0x10]! - str x12, [sp, #-0x10]! - str x11, [sp, #-0x10]! - str x10, [sp, #-0x10]! - str x9, [sp, #-0x10]! - str x8, [sp, #-0x10]! - str x7, [sp, #-0x10]! - str x6, [sp, #-0x10]! - str x5, [sp, #-0x10]! - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - mov x9, x0 - sub sp, sp, #0x50 - ldr x0, [sp, #0x50] - ldr x1, [sp, #0x60] - ldr x2, [sp, #0x70] - ldr x3, [sp, #0x80] - ldr x4, [sp, #0x90] - ldr x5, [sp, #0xa0] - ldr x6, [sp, #0xb0] - ldr x7, [sp, #0xc0] - ldr x16, [sp, #0xd0] - str x16, [sp] - ldr x16, [sp, #0xe0] - str x16, [sp, #0x8] - ldr x16, [sp, #0xf0] - str x16, [sp, #0x10] - ldr x16, [sp, #0x100] - str x16, [sp, #0x18] - ldr x16, [sp, #0x110] - str x16, [sp, #0x20] - ldr x16, [sp, #0x120] - str x16, [sp, #0x28] - ldr x16, [sp, #0x130] - str x16, [sp, #0x30] - ldr x16, [sp, #0x140] - str x16, [sp, #0x38] - ldr x16, [sp, #0x150] - str x16, [sp, #0x40] + mov x16, x0 + sub sp, sp, #0x60 + str x16, [sp, #0x50] + str x9, [sp] + str x10, [sp, #0x8] + str x11, [sp, #0x10] + str x12, [sp, #0x18] + str x13, [sp, #0x20] + str x14, [sp, #0x28] + str x15, [sp, #0x30] + str x21, [sp, #0x38] + str x22, [sp, #0x40] + mov x0, x1 + mov x1, x2 + mov x2, x3 + mov x3, x4 + mov x4, x5 + mov x5, x6 + mov x6, x7 + mov x7, x8 + ldr x9, [sp, #0x50] blr x9 - add sp, sp, #0x50 - add sp, sp, #0x110 + add sp, sp, #0x60 cmp x0, #0x99 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret adrp x0, add x0, x0, @@ -457,20 +523,14 @@ Disassembly of section .text: cmp x0, #0x168 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret diff --git a/tests/snapshots/asm/indirect_call_target_scratch_exhausted.x64.asm b/tests/snapshots/asm/indirect_call_target_scratch_exhausted.x64.asm index a8a519a42..048d0a6ae 100644 --- a/tests/snapshots/asm/indirect_call_target_scratch_exhausted.x64.asm +++ b/tests/snapshots/asm/indirect_call_target_scratch_exhausted.x64.asm @@ -241,7 +241,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x110, %rsp # imm = 0x110 + subq $0x70, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -249,24 +249,103 @@ Disassembly of section .text: movq %r15, 0x20(%rsp) leaq -, %rax # leaq -, %rbx # + xorq %rcx, %rcx + leaq , %rdx + leaq (%rdx), %rsi + movq %rcx, (%rsi) + leaq (%rdx), %rcx xorq %rdx, %rdx - cmpq $0x10, %rdx - jge - jmp - incq %rdx - jmp - leaq , %rcx - movq %rdx, %rsi - shlq $0x4, %rsi - addq %rcx, %rsi - movq %rdx, (%rsi) - movq %rdx, %rsi - shlq $0x4, %rsi - addq %rsi, %rcx - movq %rdx, %rsi - shlq $0x1, %rsi - movq %rsi, 0x8(%rcx) - jmp + movq %rdx, 0x8(%rcx) + movl $0x1, %ecx + leaq , %rdx + movq %rcx, 0x10(%rdx) + leaq 0x10(%rdx), %rcx + movl $0x2, %edx + movq %rdx, 0x8(%rcx) + movl $0x2, %ecx + leaq , %rdx + movq %rcx, 0x20(%rdx) + leaq 0x20(%rdx), %rcx + movl $0x4, %edx + movq %rdx, 0x8(%rcx) + movl $0x3, %ecx + leaq , %rdx + movq %rcx, 0x30(%rdx) + leaq 0x30(%rdx), %rcx + movl $0x6, %edx + movq %rdx, 0x8(%rcx) + movl $0x4, %ecx + leaq , %rdx + movq %rcx, 0x40(%rdx) + leaq 0x40(%rdx), %rcx + movl $0x8, %edx + movq %rdx, 0x8(%rcx) + movl $0x5, %ecx + leaq , %rdx + movq %rcx, 0x50(%rdx) + leaq 0x50(%rdx), %rcx + movl $0xa, %edx + movq %rdx, 0x8(%rcx) + movl $0x6, %ecx + leaq , %rdx + movq %rcx, 0x60(%rdx) + leaq 0x60(%rdx), %rcx + movl $0xc, %edx + movq %rdx, 0x8(%rcx) + movl $0x7, %ecx + leaq , %rdx + movq %rcx, 0x70(%rdx) + leaq 0x70(%rdx), %rcx + movl $0xe, %edx + movq %rdx, 0x8(%rcx) + movl $0x8, %ecx + leaq , %rdx + movq %rcx, 0x80(%rdx) + leaq 0x80(%rdx), %rcx + movl $0x10, %edx + movq %rdx, 0x8(%rcx) + movl $0x9, %ecx + leaq , %rdx + movq %rcx, 0x90(%rdx) + leaq 0x90(%rdx), %rcx + movl $0x12, %edx + movq %rdx, 0x8(%rcx) + movl $0xa, %ecx + leaq , %rdx + movq %rcx, 0xa0(%rdx) + leaq 0xa0(%rdx), %rcx + movl $0x14, %edx + movq %rdx, 0x8(%rcx) + movl $0xb, %ecx + leaq , %rdx + movq %rcx, 0xb0(%rdx) + leaq 0xb0(%rdx), %rcx + movl $0x16, %edx + movq %rdx, 0x8(%rcx) + movl $0xc, %ecx + leaq , %rdx + movq %rcx, 0xc0(%rdx) + leaq 0xc0(%rdx), %rcx + movl $0x18, %edx + movq %rdx, 0x8(%rcx) + movl $0xd, %ecx + leaq , %rdx + movq %rcx, 0xd0(%rdx) + leaq 0xd0(%rdx), %rcx + movl $0x1a, %edx + movq %rdx, 0x8(%rcx) + movl $0xe, %ecx + leaq , %rdx + movq %rcx, 0xe0(%rdx) + leaq 0xe0(%rdx), %rcx + movl $0x1c, %edx + movq %rdx, 0x8(%rcx) + movl $0xf, %ecx + leaq , %rdx + movq %rcx, 0xf0(%rdx) + leaq 0xf0(%rdx), %rcx + movl $0x1e, %edx + movq %rdx, 0x8(%rcx) movl $0x1, %edi movl $0x2, %esi movl $0x3, %edx @@ -320,7 +399,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x110, %rsp # imm = 0x110 + addq $0x70, %rsp popq %rbp retq leaq , %rdi @@ -432,7 +511,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x110, %rsp # imm = 0x110 + addq $0x70, %rsp popq %rbp retq xorq %rax, %rax @@ -441,7 +520,8 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x110, %rsp # imm = 0x110 + addq $0x70, %rsp popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/indirect_call_ten_scalar_args.aarch64.asm b/tests/snapshots/asm/indirect_call_ten_scalar_args.aarch64.asm new file mode 100644 index 000000000..db7b3aa81 --- /dev/null +++ b/tests/snapshots/asm/indirect_call_ten_scalar_args.aarch64.asm @@ -0,0 +1,111 @@ + +indirect_call_ten_scalar_args.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0x20 + ldr x16, [sp, #0x20] + str x16, [sp] + ldr x16, [sp, #0x28] + str x16, [sp, #0x10] + sub sp, sp, #0x80 + stp x29, x30, [sp, #-0x10]! + mov x29, sp + lsl x1, x1, #1 + add x0, x0, x1 + mov x17, #0x3 // =3 + mul x1, x2, x17 + add x0, x0, x1 + lsl x1, x3, #2 + add x0, x0, x1 + mov x17, #0x5 // =5 + mul x1, x4, x17 + add x0, x0, x1 + mov x17, #0x6 // =6 + mul x1, x5, x17 + add x0, x0, x1 + mov x17, #0x7 // =7 + mul x1, x6, x17 + add x0, x0, x1 + lsl x1, x7, #3 + add x0, x0, x1 + ldur x1, [x29, #0x90] + mov x17, #0x9 // =9 + mul x1, x1, x17 + add x0, x0, x1 + ldur x1, [x29, #0xa0] + mov x17, #0xa // =10 + mul x1, x1, x17 + add x0, x0, x1 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0xa0 + ret + +
: + stp x20, x21, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x20, [x1] + add x1, x20, #0x1 + add x2, x20, #0x2 + add x3, x20, #0x3 + add x4, x20, #0x4 + add x5, x20, #0x5 + add x6, x20, #0x6 + add x7, x20, #0x7 + add x8, x20, #0x8 + add x9, x20, #0x9 + mov x10, x0 + sub sp, sp, #0x10 + str x8, [sp] + str x9, [sp, #0x8] + mov x0, x20 + blr x10 + add sp, sp, #0x10 + mov x21, x0 + cmp x21, #0x181 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + add x1, x20, #0x1 + add x2, x20, #0x2 + add x3, x20, #0x3 + add x4, x20, #0x4 + add x5, x20, #0x5 + add x6, x20, #0x6 + add x7, x20, #0x7 + add x0, x20, #0x8 + add x8, x20, #0x9 + sub sp, sp, #0x10 + str x0, [sp] + str x8, [sp, #0x8] + mov x0, x20 + bl + add sp, sp, #0x10 + cmp x21, x0 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret diff --git a/tests/snapshots/asm/indirect_call_ten_scalar_args.x64.asm b/tests/snapshots/asm/indirect_call_ten_scalar_args.x64.asm new file mode 100644 index 000000000..4608fcf41 --- /dev/null +++ b/tests/snapshots/asm/indirect_call_ten_scalar_args.x64.asm @@ -0,0 +1,134 @@ + +indirect_call_ten_scalar_args.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0xa0, %rsp + movq 0xa0(%rsp), %rax + movq %rax, 0x60(%rsp) + movq 0xa8(%rsp), %rax + movq %rax, 0x70(%rsp) + movq 0xb0(%rsp), %rax + movq %rax, 0x80(%rsp) + movq 0xb8(%rsp), %rax + movq %rax, 0x90(%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + movq %rsi, %rax + shlq $0x1, %rax + addq %rdi, %rax + leaq (%rdx,%rdx,2), %rdx + addq %rdx, %rax + shlq $0x2, %rcx + addq %rcx, %rax + leaq (%r8,%r8,4), %rcx + addq %rcx, %rax + imulq $0x6, %r9, %rcx + addq %rcx, %rax + movq 0x70(%rbp), %rcx + imulq $0x7, %rcx, %rcx + addq %rcx, %rax + movq 0x80(%rbp), %rcx + shlq $0x3, %rcx + addq %rcx, %rax + movq 0x90(%rbp), %rcx + leaq (%rcx,%rcx,8), %rcx + addq %rcx, %rax + movq 0xa0(%rbp), %rcx + imulq $0xa, %rcx, %rcx + addq %rcx, %rax + popq %rbp + popq %r11 + addq $0xa0, %rsp + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x30, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %r15, 0x20(%rsp) + leaq -, %rax # + leaq , %rcx + movq (%rcx), %rbx + leaq 0x1(%rbx), %rsi + leaq 0x2(%rbx), %rdx + leaq 0x3(%rbx), %rcx + leaq 0x4(%rbx), %r8 + leaq 0x5(%rbx), %r9 + leaq 0x6(%rbx), %rdi + leaq 0x7(%rbx), %r12 + leaq 0x8(%rbx), %r13 + leaq 0x9(%rbx), %r14 + subq $0x20, %rsp + movq %rdi, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %rbx, %rdi + callq *%rax + addq $0x20, %rsp + movq %rax, %r12 + cmpq $0x181, %r12 # imm = 0x181 + je + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x30, %rsp + popq %rbp + retq + leaq 0x1(%rbx), %rsi + leaq 0x2(%rbx), %rdx + leaq 0x3(%rbx), %rcx + leaq 0x4(%rbx), %r8 + leaq 0x5(%rbx), %r9 + leaq 0x6(%rbx), %rax + leaq 0x7(%rbx), %rdi + leaq 0x8(%rbx), %r13 + leaq 0x9(%rbx), %r14 + subq $0x20, %rsp + movq %rax, (%rsp) + movq %rdi, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %rbx, %rdi + callq + addq $0x20, %rsp + cmpq %rax, %r12 + je + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x30, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x30, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/indirect_call_through_global_fn_ptr.aarch64.asm b/tests/snapshots/asm/indirect_call_through_global_fn_ptr.aarch64.asm index 2ca837bb0..09420b50a 100644 --- a/tests/snapshots/asm/indirect_call_through_global_fn_ptr.aarch64.asm +++ b/tests/snapshots/asm/indirect_call_through_global_fn_ptr.aarch64.asm @@ -16,11 +16,10 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x0, add x0, x0, mov x1, #0x7 // =7 @@ -36,20 +35,13 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr x0, [x0] - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x20, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x0, x20 blr x9 - add sp, sp, #0x30 ldrsw x0, [x20] - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret
: diff --git a/tests/snapshots/asm/indirect_call_variadic_fp_control.aarch64.asm b/tests/snapshots/asm/indirect_call_variadic_fp_control.aarch64.asm new file mode 100644 index 000000000..42a78bcdc --- /dev/null +++ b/tests/snapshots/asm/indirect_call_variadic_fp_control.aarch64.asm @@ -0,0 +1,183 @@ + +indirect_call_variadic_fp_control.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0xc0 + str x0, [sp] + str x1, [sp, #0x8] + str x2, [sp, #0x10] + str x3, [sp, #0x18] + str x4, [sp, #0x20] + str x5, [sp, #0x28] + str x6, [sp, #0x30] + str x7, [sp, #0x38] + str d0, [sp, #0x40] + str d1, [sp, #0x50] + str d2, [sp, #0x60] + str d3, [sp, #0x70] + str d4, [sp, #0x80] + str d5, [sp, #0x90] + str d6, [sp, #0xa0] + str d7, [sp, #0xb0] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 + sub x0, x29, #0x20 + add x1, x29, #0x10 + mov x16, x0 + add x17, x29, #0xd0 + str x17, [x16] + add x17, x29, #0x50 + str x17, [x16, #0x8] + add x17, x29, #0xd0 + str x17, [x16, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x18] + mov x17, #0xff80 // =65408 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x1c] + mov x1, #0x0 // =0 + fmov d16, x1 + sub x17, x29, #0x28 + str d16, [x17] + b + asr x2, x0, #63 + lsr x2, x2, #63 + add x3, x0, x2 + mov x17, #0x1 // =1 + and x3, x3, x17 + sub x2, x3, x2 + cmp x2, #0x0 + b.ne + sub x16, x29, #0x28 + ldr d0, [x16] + sub x2, x29, #0x20 + mov x17, x2 + str x9, [sp, #-0x10]! + ldrsw x16, [x17, #0x18] + cmp x16, #0x0 + b.ge + ldr x9, [x17, #0x8] + add x9, x9, x16 + add x16, x16, #0x8 + str w16, [x17, #0x18] + cmp x16, #0x0 + b.gt + mov x16, x9 + b + ldr x16, [x17] + add x9, x16, #0x8 + str x9, [x17] + ldr x9, [sp], #0x10 + mov x2, x16 + ldrsw x2, [x2] + scvtf d1, x2 + fadd d0, d0, d1 + sub x17, x29, #0x28 + str d0, [x17] + b + sub x16, x29, #0x28 + ldr d0, [x16] + sub x2, x29, #0x20 + mov x17, x2 + str x9, [sp, #-0x10]! + ldrsw x16, [x17, #0x1c] + cmp x16, #0x0 + b.ge + ldr x9, [x17, #0x10] + add x9, x9, x16 + add x16, x16, #0x10 + str w16, [x17, #0x1c] + cmp x16, #0x0 + b.gt + mov x16, x9 + b + ldr x16, [x17] + add x9, x16, #0x8 + str x9, [x17] + ldr x9, [sp], #0x10 + mov x2, x16 + ldr d1, [x2] + fadd d0, d0, d1 + sub x17, x29, #0x28 + str d0, [x17] + add x1, x0, #0x1 + sxtw x0, w1 + ldursw x2, [x29, #0x10] + cmp x0, x2 + b.lt + sub x0, x29, #0x20 + sub x16, x29, #0x28 + ldr d0, [x16] + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 + add sp, sp, #0xc0 + ret + b + +
: + str d8, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + mov x1, #0x4 // =4 + mov x2, #0x1 // =1 + mov x3, #0x4004000000000000 // =4612811918334230528 + mov x4, #0x3 // =3 + mov x5, #0x4011000000000000 // =4616471093031469056 + mov x9, x0 + fmov d0, x3 + fmov d1, x5 + mov x0, x1 + mov x1, x2 + mov x2, x4 + blr x9 + fmov d8, d0 + mov x0, #0x800000000000 // =140737488355328 + movk x0, #0x4025, lsl #48 + fmov d17, x0 + fcmp d8, d17 + cset x0, ne + cbz x0, + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret + mov x0, #0x4 // =4 + mov x1, #0x1 // =1 + mov x2, #0x4004000000000000 // =4612811918334230528 + mov x3, #0x3 // =3 + mov x4, #0x4011000000000000 // =4616471093031469056 + fmov d0, x2 + fmov d1, x4 + mov x2, x3 + bl + fcmp d8, d0 + cset x0, ne + cbz x0, + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr d8, [sp], #0x30 + ret diff --git a/tests/snapshots/asm/indirect_call_variadic_fp_control.x64.asm b/tests/snapshots/asm/indirect_call_variadic_fp_control.x64.asm new file mode 100644 index 000000000..ba23b67ee --- /dev/null +++ b/tests/snapshots/asm/indirect_call_variadic_fp_control.x64.asm @@ -0,0 +1,158 @@ + +indirect_call_variadic_fp_control.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0xe0, %rsp + movq %rdi, -0xe0(%rbp) + movq %rsi, -0xd8(%rbp) + movq %rdx, -0xd0(%rbp) + movq %rcx, -0xc8(%rbp) + movq %r8, -0xc0(%rbp) + movq %r9, -0xb8(%rbp) + testb %al, %al + je + movsd %xmm0, -0xb0(%rbp,%riz) + movsd %xmm1, -0xa0(%rbp,%riz) + movsd %xmm2, -0x90(%rbp,%riz) + movsd %xmm3, -0x80(%rbp,%riz) + movsd %xmm4, -0x70(%rbp,%riz) + movsd %xmm5, -0x60(%rbp,%riz) + movsd %xmm6, -0x50(%rbp,%riz) + movsd %xmm7, -0x40(%rbp,%riz) + leaq -0x18(%rbp), %rax + leaq -0xe0(%rbp), %rcx + movl $0x8, (%rax) + movl $0x30, 0x4(%rax) + leaq 0x10(%rbp), %r10 + movq %r10, 0x8(%rax) + leaq -0xe0(%rbp), %r10 + movq %r10, 0x10(%rax) + xorq %rcx, %rcx + movq %rcx, %xmm14 + movsd %xmm14, -0x20(%rbp,%riz) + jmp + movq %rax, %rdx + sarq $0x3f, %rdx + shrq $0x3f, %rdx + leaq (%rax,%rdx), %rsi + andq $0x1, %rsi + movq %rdx, %r10 + movq %rsi, %rdx + subq %r10, %rdx + testq %rdx, %rdx + jne + movsd -0x20(%rbp,%riz), %xmm0 + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 + movl (%r11), %r10d + cmpq $0x30, %r10 + jae + addq 0x10(%r11), %r10 + addl $0x8, (%r11) + jmp + movq 0x8(%r11), %r10 + addq $0x8, 0x8(%r11) + movq %r10, %rdx + movslq (%rdx), %rdx + cvtsi2sd %rdx, %xmm1 + addsd %xmm1, %xmm0 + movsd %xmm0, -0x20(%rbp,%riz) + jmp + movsd -0x20(%rbp,%riz), %xmm0 + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 + movl 0x4(%r11), %r10d + cmpq $0xb0, %r10 + jae + addq 0x10(%r11), %r10 + addl $0x10, 0x4(%r11) + jmp + movq 0x8(%r11), %r10 + addq $0x8, 0x8(%r11) + movq %r10, %rdx + movsd (%rdx,%riz), %xmm1 + addsd %xmm1, %xmm0 + movsd %xmm0, -0x20(%rbp,%riz) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + movslq -0xe0(%rbp), %rdx + cmpq %rdx, %rax + jl + leaq -0x18(%rbp), %rax + movsd -0x20(%rbp,%riz), %xmm0 + addq $0xe0, %rsp + popq %rbp + retq + jmp + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + leaq -, %rax # + movl $0x4, %edi + movl $0x1, %esi + movabsq $0x4004000000000000, %rdx # imm = 0x4004000000000000 + movl $0x3, %ecx + movabsq $0x4011000000000000, %r8 # imm = 0x4011000000000000 + movq %rax, %r9 + movq %rdx, %xmm0 + movq %r8, %xmm1 + movq %rcx, %rdx + movb $0x2, %al + callq *%r9 + movsd %xmm0, 0x8(%rsp) + movabsq $0x4025800000000000, %rax # imm = 0x4025800000000000 + movsd 0x8(%rsp), %xmm14 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x4, %edi + movl $0x1, %esi + movabsq $0x4004000000000000, %rdx # imm = 0x4004000000000000 + movl $0x3, %ecx + movabsq $0x4011000000000000, %r8 # imm = 0x4011000000000000 + movq %rdx, %xmm0 + movq %r8, %xmm1 + movq %rcx, %rdx + movb $0x2, %al + callq + movsd 0x8(%rsp), %xmm14 + ucomisd %xmm0, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/indirect_struct_return.aarch64.asm b/tests/snapshots/asm/indirect_struct_return.aarch64.asm index d5cfa0611..be0a556c6 100644 --- a/tests/snapshots/asm/indirect_struct_return.aarch64.asm +++ b/tests/snapshots/asm/indirect_struct_return.aarch64.asm @@ -33,12 +33,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0xa0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 adrp x20, add x20, x20, mov x0, #0x7 // =7 @@ -56,19 +54,17 @@ Disassembly of section .text: sub x0, x29, #0x10 ldrsw x0, [x0] cmp x0, #0x7 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x10 ldrsw x0, [x0, #0x4] cmp x0, #0xe - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xa0 ret sub x0, x29, #0x18 str x20, [x0] @@ -90,19 +86,17 @@ Disassembly of section .text: sub x0, x29, #0x20 ldrsw x0, [x0] cmp x0, #0xa - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x20 ldrsw x0, [x0, #0x4] cmp x0, #0x14 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xa0 ret mov x21, #0x3 // =3 mov x9, x20 @@ -126,18 +120,14 @@ Disassembly of section .text: cmp x0, #0x9 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xa0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0xa0 ret b b diff --git a/tests/snapshots/asm/indirect_struct_return.x64.asm b/tests/snapshots/asm/indirect_struct_return.x64.asm index f69c2cb71..aade9e90d 100644 --- a/tests/snapshots/asm/indirect_struct_return.x64.asm +++ b/tests/snapshots/asm/indirect_struct_return.x64.asm @@ -54,16 +54,16 @@ Disassembly of section .text: leaq -0x10(%rbp), %rax movslq (%rax), %rax cmpq $0x7, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0xe, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax movq (%rsp), %rbx @@ -88,16 +88,16 @@ Disassembly of section .text: leaq -0x20(%rbp), %rax movslq (%rax), %rax cmpq $0xa, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x20(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x14, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx diff --git a/tests/snapshots/asm/indirect_struct_return_outptr.aarch64.asm b/tests/snapshots/asm/indirect_struct_return_outptr.aarch64.asm index e025d4a42..8da75e7b4 100644 --- a/tests/snapshots/asm/indirect_struct_return_outptr.aarch64.asm +++ b/tests/snapshots/asm/indirect_struct_return_outptr.aarch64.asm @@ -97,13 +97,11 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x120 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x130]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x120] + add x29, sp, #0x120 adrp x20, add x20, x20, adrp x21, @@ -131,27 +129,25 @@ Disassembly of section .text: ldr x0, [x0] cmp x0, #0xa cset x0, ne - mov x22, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x38 ldr x0, [x0, #0x10] cmp x0, #0xc cset x0, ne cmp x0, #0x0 - cset x22, ne - cbnz x22, + cset x2, ne + cbnz x2, sub x0, x29, #0x38 ldr x0, [x0, #0x20] cmp x0, #0xe - cset x22, ne - cbz x22, + cset x2, ne + cbz x2, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret mov x0, #0x7 // =7 mov x9, x21 @@ -171,20 +167,18 @@ Disassembly of section .text: sub x0, x29, #0x48 ldr x0, [x0] cmp x0, #0x7 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, sub x0, x29, #0x48 ldr x0, [x0, #0x8] cmp x0, #0xe - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret mov x0, #0x3 // =3 mov x9, x20 @@ -195,12 +189,10 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret mov x20, #0x5 // =5 mov x9, x21 @@ -223,20 +215,16 @@ Disassembly of section .text: cmp x0, #0xf b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret b b diff --git a/tests/snapshots/asm/indirect_struct_return_outptr.x64.asm b/tests/snapshots/asm/indirect_struct_return_outptr.x64.asm index c322f2556..f47ed69eb 100644 --- a/tests/snapshots/asm/indirect_struct_return_outptr.x64.asm +++ b/tests/snapshots/asm/indirect_struct_return_outptr.x64.asm @@ -36,12 +36,10 @@ Disassembly of section .text: movslq 0x20(%rbp), %rax leaq -0x28(%rbp), %rcx movq %rax, (%rcx) - movslq 0x20(%rbp), %rax - incq %rax - movslq %eax, %rax - leaq -0x28(%rbp), %rcx - movq %rax, 0x8(%rcx) - movslq 0x20(%rbp), %rax + leaq 0x1(%rax), %rcx + movslq %ecx, %rcx + leaq -0x28(%rbp), %rdx + movq %rcx, 0x8(%rdx) addq $0x2, %rax movslq %eax, %rax leaq -0x28(%rbp), %rcx @@ -139,7 +137,7 @@ Disassembly of section .text: cmpq $0xa, %rax setne %al movzbq %al, %rax - movl $0x1, %r13d + movl $0x1, %edx testq %rax, %rax jne leaq -0x38(%rbp), %rax @@ -148,16 +146,16 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x38(%rbp), %rax movq 0x20(%rax), %rax cmpq $0xe, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x1, %eax movq (%rsp), %rbx @@ -183,16 +181,16 @@ Disassembly of section .text: leaq -0x48(%rbp), %rax movq (%rax), %rax cmpq $0x7, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x48(%rbp), %rax movq 0x8(%rax), %rax cmpq $0xe, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx diff --git a/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm b/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm new file mode 100644 index 000000000..12c143195 --- /dev/null +++ b/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm @@ -0,0 +1,384 @@ + +init_brace_intermediate_cast.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x60 + sub x0, x29, #0x20 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [x1, #0x10] + str x10, [x0, #0x10] + ldr x10, [x1, #0x18] + str x10, [x0, #0x18] + ldr x10, [sp], #0x10 + sub x0, x29, #0x30 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [sp], #0x10 + sub x0, x29, #0x38 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [sp], #0x10 + sub x0, x29, #0x50 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [x1, #0x10] + str x10, [x0, #0x10] + ldr x10, [sp], #0x10 + adrp x0, + add x0, x0, + ldr x1, [x0] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x1, [x0, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + cmp x1, x17 + b.eq + mov x0, #0x2 // =2 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x1, [x0, #0x10] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x3 // =3 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x0, [x0, #0x18] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x4 // =4 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x5 // =5 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0, #0x8] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x6 // =6 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x7 // =7 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x4] + mov x17, #0x8000 // =32768 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x8 // =8 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x9 // =9 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xa // =10 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xb // =11 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xc // =12 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x0 + b.eq + mov x0, #0xd // =13 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr x0, [x0, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xe // =14 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x2 + b.eq + mov x0, #0xf // =15 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + ldr d0, [x0] + mov x0, #0x4008000000000000 // =4613937818241073152 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0x10 // =16 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x20 + ldr x0, [x0] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x11 // =17 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x20 + ldr x0, [x0, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + cmp x0, x17 + b.eq + mov x0, #0x12 // =18 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x20 + ldr x0, [x0, #0x10] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x13 // =19 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x20 + ldr x0, [x0, #0x18] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x14 // =20 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x30 + ldr x0, [x0] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x15 // =21 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x30 + ldr x0, [x0, #0x8] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x16 // =22 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x38 + ldrsw x0, [x0] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x17 // =23 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x38 + ldrsw x0, [x0, #0x4] + mov x17, #0x8000 // =32768 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x18 // =24 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x50 + ldr x0, [x0] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x19 // =25 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x50 + ldr x0, [x0, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x1a // =26 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x0, x29, #0x50 + ldrsw x0, [x0, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x1b // =27 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1c // =28 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm b/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm new file mode 100644 index 000000000..8427106e9 --- /dev/null +++ b/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm @@ -0,0 +1,284 @@ + +init_brace_intermediate_cast.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x60, %rsp + leaq -0x20(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + movq 0x10(%rcx), %rdx + movq %rdx, 0x10(%rax) + movq 0x18(%rcx), %rdx + movq %rdx, 0x18(%rax) + popq %rdx + leaq -0x30(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + popq %rdx + leaq -0x38(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + popq %rdx + leaq -0x50(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + movq 0x10(%rcx), %rdx + movq %rdx, 0x10(%rax) + popq %rdx + leaq , %rax + movq (%rax), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x8(%rax), %rcx + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + cmpq %r11, %rcx + je + movl $0x2, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x10(%rax), %rcx + cmpq $-0x1, %rcx + je + movl $0x3, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x18(%rax), %rax + cmpq $-0x1, %rax + je + movl $0x4, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq (%rax), %rax + cmpq $-0x1, %rax + je + movl $0x5, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq 0x8(%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x6, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movslq (%rax), %rax + cmpq $-0x38, %rax + je + movl $0x7, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movslq 0x4(%rax), %rax + cmpq $-0x8000, %rax # imm = 0x8000 + je + movl $0x8, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq (%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x9, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq 0x8(%rax), %rax + cmpq $-0x1, %rax + je + movl $0xa, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movslq 0x10(%rax), %rax + cmpq $-0x38, %rax + je + movl $0xb, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq (%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0xc, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq (%rax), %rax + testq %rax, %rax + je + movl $0xd, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movq 0x8(%rax), %rax + cmpq $-0x1, %rax + je + movl $0xe, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movslq (%rax), %rax + cmpq $0x2, %rax + je + movl $0xf, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rax + movsd (%rax,%riz), %xmm0 + movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x10, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rax + movq (%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x11, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rax + movq 0x8(%rax), %rax + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + cmpq %r11, %rax + je + movl $0x12, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rax + movq 0x10(%rax), %rax + cmpq $-0x1, %rax + je + movl $0x13, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rax + movq 0x18(%rax), %rax + cmpq $-0x1, %rax + je + movl $0x14, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x30(%rbp), %rax + movq (%rax), %rax + cmpq $-0x1, %rax + je + movl $0x15, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x30(%rbp), %rax + movq 0x8(%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x16, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x38(%rbp), %rax + movslq (%rax), %rax + cmpq $-0x38, %rax + je + movl $0x17, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x38(%rbp), %rax + movslq 0x4(%rax), %rax + cmpq $-0x8000, %rax # imm = 0x8000 + je + movl $0x18, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rax + movq (%rax), %rax + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x19, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rax + movq 0x8(%rax), %rax + cmpq $-0x1, %rax + je + movl $0x1a, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rax + movslq 0x10(%rax), %rax + cmpq $-0x38, %rax + je + movl $0x1b, %eax + addq $0x60, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x60, %rsp + popq %rbp + retq + movl $0x1c, %eax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/init_float_to_int.aarch64.asm b/tests/snapshots/asm/init_float_to_int.aarch64.asm index 2745bdb42..c5b17d0e8 100644 --- a/tests/snapshots/asm/init_float_to_int.aarch64.asm +++ b/tests/snapshots/asm/init_float_to_int.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 adrp x0, add x0, x0, ldrsw x1, [x0] @@ -35,8 +32,6 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -55,8 +50,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -67,8 +60,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -87,12 +78,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/init_float_to_int.x64.asm b/tests/snapshots/asm/init_float_to_int.x64.asm index a4db111ad..5ded081d8 100644 --- a/tests/snapshots/asm/init_float_to_int.x64.asm +++ b/tests/snapshots/asm/init_float_to_int.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x1, %rcx @@ -38,8 +35,6 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -56,8 +51,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movl (%rax), %eax @@ -66,8 +59,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -94,15 +85,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/init_scalar_conversion.aarch64.asm b/tests/snapshots/asm/init_scalar_conversion.aarch64.asm index e43a47c5d..4096138ac 100644 --- a/tests/snapshots/asm/init_scalar_conversion.aarch64.asm +++ b/tests/snapshots/asm/init_scalar_conversion.aarch64.asm @@ -66,12 +66,9 @@ Disassembly of section .text: b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] + stp x20, x21, [sp, #-0xe0]! + stp x29, x30, [sp, #0xd0] + add x29, sp, #0xd0 mov x20, #0x348 // =840 mov x21, #0x21c // =540 sub x0, x29, #0x20 @@ -95,22 +92,19 @@ Disassembly of section .text: movk x0, #0x408a, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, sub x0, x29, #0x20 ldr d0, [x0, #0x8] mov x0, #0xe00000000000 // =246290604621824 movk x0, #0x4080, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x40 adrp x1, @@ -143,22 +137,19 @@ Disassembly of section .text: movk x0, #0x408a, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, sub x0, x29, #0x40 ldr d0, [x0, #0x18] mov x0, #0xe00000000000 // =246290604621824 movk x0, #0x4080, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x50 adrp x1, @@ -181,22 +172,19 @@ Disassembly of section .text: movk x0, #0x408a, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, sub x0, x29, #0x50 ldr d0, [x0, #0x8] mov x0, #0xe00000000000 // =246290604621824 movk x0, #0x4080, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret mov x0, #0x3333 // =13107 movk x0, #0x3333, lsl #16 @@ -223,36 +211,37 @@ Disassembly of section .text: sub x0, x29, #0x60 ldrsw x0, [x0] cmp x0, #0x3 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, sub x0, x29, #0x60 ldrsw x0, [x0, #0x4] cmp x0, #0x7 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret mov x0, #0x0 // =0 - sub x1, x29, #0x70 - adrp x2, - add x2, x2, + fmov s16, w0 + sub x17, x29, #0x68 + str s16, [x17] + sub x0, x29, #0x70 + adrp x1, + add x1, x1, str x10, [sp, #-0x10]! - ldrb w10, [x2] - strb w10, [x1] - ldrb w10, [x2, #0x1] - strb w10, [x1, #0x1] - ldrb w10, [x2, #0x2] - strb w10, [x1, #0x2] - ldrb w10, [x2, #0x3] - strb w10, [x1, #0x3] + ldrb w10, [x1] + strb w10, [x0] + ldrb w10, [x1, #0x1] + strb w10, [x0, #0x1] + ldrb w10, [x1, #0x2] + strb w10, [x0, #0x2] + ldrb w10, [x1, #0x3] + strb w10, [x0, #0x3] ldr x10, [sp], #0x10 sub x16, x29, #0x58 ldr d0, [x16] + mov x0, #0x0 // =0 fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 @@ -260,30 +249,27 @@ Disassembly of section .text: str s0, [x0] sub x0, x29, #0x70 ldr s0, [x0] - mov x0, #0x851f // =34079 - movk x0, #0x51eb, lsl #16 - movk x0, #0x1eb8, lsl #32 - movk x0, #0x400f, lsl #48 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 - cset x22, mi - cbnz x22, - mov x0, #0xe148 // =57672 - movk x0, #0x147a, lsl #16 - movk x0, #0x47ae, lsl #32 - movk x0, #0x400f, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 - cset x22, gt - cbz x22, + sub x17, x29, #0x68 + str s0, [x17] + sub x16, x29, #0x68 + ldr s0, [x16] + mov x0, #0xf5c3 // =62915 + movk x0, #0x4078, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, mi + cbnz x1, + sub x16, x29, #0x68 + ldr s0, [x16] + mov x0, #0x3d71 // =15729 + movk x0, #0x407a, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, gt + cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x40 ldr d0, [x0] @@ -294,11 +280,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x98 adrp x1, @@ -334,18 +317,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xd0] + ldp x20, x21, [sp], #0xe0 ret b b diff --git a/tests/snapshots/asm/init_scalar_conversion.x64.asm b/tests/snapshots/asm/init_scalar_conversion.x64.asm index 8e043c803..93b186eea 100644 --- a/tests/snapshots/asm/init_scalar_conversion.x64.asm +++ b/tests/snapshots/asm/init_scalar_conversion.x64.asm @@ -96,10 +96,9 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xe0, %rsp + subq $0xd0, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) movl $0x348, %ebx # imm = 0x348 movl $0x21c, %r12d # imm = 0x21C leaq -0x20(%rbp), %rax @@ -121,30 +120,29 @@ Disassembly of section .text: movabsq $0x408a400000000000, %rax # imm = 0x408A400000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x20(%rbp), %rax movsd 0x8(%rax,%riz), %xmm0 movabsq $0x4080e00000000000, %rax # imm = 0x4080E00000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx je movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax @@ -176,30 +174,29 @@ Disassembly of section .text: movabsq $0x408a400000000000, %rax # imm = 0x408A400000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x40(%rbp), %rax movsd 0x18(%rax,%riz), %xmm0 movabsq $0x4080e00000000000, %rax # imm = 0x4080E00000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq leaq -0x50(%rbp), %rax @@ -221,30 +218,29 @@ Disassembly of section .text: movabsq $0x408a400000000000, %rax # imm = 0x408A400000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x50(%rbp), %rax movsd 0x8(%rax,%riz), %xmm0 movabsq $0x4080e00000000000, %rax # imm = 0x4080E00000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %r13b - movzbq %r13b, %r13 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r13 - testq %r13, %r13 + orq %r10, %rcx + testq %rcx, %rcx je movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq movabsq $0x400f333333333333, %rax # imm = 0x400F333333333333 @@ -266,38 +262,40 @@ Disassembly of section .text: leaq -0x60(%rbp), %rax movslq (%rax), %rax cmpq $0x3, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x60(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x7, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq xorq %rax, %rax - leaq -0x70(%rbp), %rcx - leaq , %rdx - pushq %rax - movzbq (%rdx), %rax - movb %al, (%rcx) - movzbq 0x1(%rdx), %rax - movb %al, 0x1(%rcx) - movzbq 0x2(%rdx), %rax - movb %al, 0x2(%rcx) - movzbq 0x3(%rdx), %rax - movb %al, 0x3(%rcx) - popq %rax + movq %rax, %xmm14 + movss %xmm14, -0x68(%rbp,%riz) + leaq -0x70(%rbp), %rax + leaq , %rcx + pushq %rdx + movzbq (%rcx), %rdx + movb %dl, (%rax) + movzbq 0x1(%rcx), %rdx + movb %dl, 0x1(%rax) + movzbq 0x2(%rcx), %rdx + movb %dl, 0x2(%rax) + movzbq 0x3(%rcx), %rdx + movb %dl, 0x3(%rax) + popq %rdx movsd -0x58(%rbp,%riz), %xmm0 + xorq %rax, %rax movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 @@ -305,30 +303,30 @@ Disassembly of section .text: movss %xmm0, (%rax,%riz) leaq -0x70(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x400f1eb851eb851f, %rax # imm = 0x400F1EB851EB851F - cvtss2sd %xmm0, %xmm1 + movss %xmm0, -0x68(%rbp,%riz) + movss -0x68(%rbp,%riz), %xmm0 + movl $0x4078f5c3, %eax # imm = 0x4078F5C3 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 - setb %r13b - movzbq %r13b, %r13 + ucomiss %xmm15, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %r13 - testq %r13, %r13 + andq %r10, %rcx + testq %rcx, %rcx jne - movabsq $0x400f47ae147ae148, %rax # imm = 0x400F47AE147AE148 - cvtss2sd %xmm0, %xmm0 + movss -0x68(%rbp,%riz), %xmm0 + movl $0x407a3d71, %eax # imm = 0x407A3D71 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - seta %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + ucomiss %xmm15, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq leaq -0x40(%rbp), %rdi @@ -349,8 +347,7 @@ Disassembly of section .text: movl $0x6, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq leaq -0x98(%rbp), %rax @@ -395,15 +392,13 @@ Disassembly of section .text: movl $0x7, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0xe0, %rsp + addq $0xd0, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/inline_arg_count_mismatch.aarch64.asm b/tests/snapshots/asm/inline_arg_count_mismatch.aarch64.asm index 397c5aaa9..0aae4b13d 100644 --- a/tests/snapshots/asm/inline_arg_count_mismatch.aarch64.asm +++ b/tests/snapshots/asm/inline_arg_count_mismatch.aarch64.asm @@ -17,22 +17,11 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - mov x0, #0x2 // =2 - mov x1, #0x3 // =3 - add x0, x0, x1 - sxtw x20, w0 mov x0, #0x7 // =7 bl - sxtw x0, w20 - cmp x0, #0x5 - b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_arg_count_mismatch.x64.asm b/tests/snapshots/asm/inline_arg_count_mismatch.x64.asm index 490c874e0..108ae66e2 100644 --- a/tests/snapshots/asm/inline_arg_count_mismatch.x64.asm +++ b/tests/snapshots/asm/inline_arg_count_mismatch.x64.asm @@ -18,23 +18,13 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) - movl $0x2, %eax - movl $0x3, %ecx - addq %rcx, %rax - movslq %eax, %rbx movl $0x7, %edi callq - movslq %ebx, %rax - cmpq $0x5, %rax - jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx - movq (%rsp), %rbx movq %rcx, %rax - addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_asm_hint.aarch64.asm b/tests/snapshots/asm/inline_asm_hint.aarch64.asm index 9a9fbcc9b..4e24408c5 100644 --- a/tests/snapshots/asm/inline_asm_hint.aarch64.asm +++ b/tests/snapshots/asm/inline_asm_hint.aarch64.asm @@ -10,27 +10,22 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 mov x2, #0x0 // =0 mov x1, x2 - sxtw x3, w2 - cmp x3, x0 - b.ge - b - sxtw x2, w2 - add x2, x2, #0x1 b yield add x1, x1, x2 - b + add x2, x3, #0x1 + sxtw x3, w2 + cmp x3, x0 + b.lt sxtw x0, w1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/inline_asm_hint.x64.asm b/tests/snapshots/asm/inline_asm_hint.x64.asm index 2dd5a2b67..4b6e1f95c 100644 --- a/tests/snapshots/asm/inline_asm_hint.x64.asm +++ b/tests/snapshots/asm/inline_asm_hint.x64.asm @@ -16,16 +16,13 @@ Disassembly of section .text: movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq %rdi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp pause addq %rcx, %rax - jmp + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq %rdi, %rdx + jl movslq %eax, %rax popq %rbp retq @@ -50,3 +47,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/inline_forward_ref_value.aarch64.asm b/tests/snapshots/asm/inline_forward_ref_value.aarch64.asm index 28202d6a6..4763030b5 100644 --- a/tests/snapshots/asm/inline_forward_ref_value.aarch64.asm +++ b/tests/snapshots/asm/inline_forward_ref_value.aarch64.asm @@ -27,53 +27,39 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 add x1, x0, #0x1 sxtw x20, w1 cbz x0, - add x21, x0, #0x64 - add x22, x0, #0x1 - cmp x21, #0x0 + add x1, x0, #0x64 + add x0, x0, #0x1 + cmp x1, #0x0 b.ne - b - mov x0, x1 - mov x1, x22 + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + lsl x2, x1, #1 + mov x1, x0 + mov x0, x2 bl sxtw x1, w20 add x0, x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0xfffe // =65534 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - lsl x1, x21, #1 - b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/inline_forward_ref_value.x64.asm b/tests/snapshots/asm/inline_forward_ref_value.x64.asm index 7bf8dd1c8..82aa58b4b 100644 --- a/tests/snapshots/asm/inline_forward_ref_value.x64.asm +++ b/tests/snapshots/asm/inline_forward_ref_value.x64.asm @@ -30,47 +30,37 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) leaq 0x1(%rdi), %rax movslq %eax, %rbx testq %rdi, %rdi je - leaq 0x64(%rdi), %r12 - leaq 0x1(%rdi), %r13 - testq %r12, %r12 + leaq 0x64(%rdi), %rax + leaq 0x1(%rdi), %rcx + testq %rax, %rax jne - jmp - movq %rcx, %rdi - movq %r13, %rsi + movabsq $-0x1, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movq %rax, %rdx + shlq $0x1, %rdx + movq %rdx, %rdi + movq %rcx, %rsi callq movslq %ebx, %rcx addq %rcx, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq movabsq $-0x2, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x50, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq - movq %r12, %rcx - shlq $0x1, %rcx - jmp
: pushq %rbp diff --git a/tests/snapshots/asm/inline_into_computed_goto.aarch64.asm b/tests/snapshots/asm/inline_into_computed_goto.aarch64.asm index e7023ee2e..30927a857 100644 --- a/tests/snapshots/asm/inline_into_computed_goto.aarch64.asm +++ b/tests/snapshots/asm/inline_into_computed_goto.aarch64.asm @@ -53,11 +53,11 @@ Disassembly of section .text: stur x1, [x29, #-0x20] stur w1, [x29, #-0x28] sub x0, x29, #0x18 - ldur x1, [x29, #0x10] - ldursw x2, [x29, #-0x28] - add x3, x2, #0x1 + ldur x2, [x29, #0x10] + sxtw x1, w1 + add x3, x1, #0x1 stur w3, [x29, #-0x28] - ldrsw x1, [x1, x2, lsl #2] + ldrsw x1, [x2, x1, lsl #2] ldr x0, [x0, x1, lsl #3] br x0 ldur x0, [x29, #-0x20] @@ -66,8 +66,8 @@ Disassembly of section .text: ldursw x3, [x29, #-0x28] add x4, x3, #0x1 stur w4, [x29, #-0x28] - ldrsw x2, [x2, x3, lsl #2] - ldr x1, [x1, x2, lsl #3] + ldrsw x3, [x2, x3, lsl #2] + ldr x1, [x1, x3, lsl #3] mov x17, #0xfffc // =65532 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 @@ -76,11 +76,10 @@ Disassembly of section .text: add x0, x0, x1 stur x0, [x29, #-0x20] sub x0, x29, #0x18 - ldur x1, [x29, #0x10] - ldursw x2, [x29, #-0x28] - add x3, x2, #0x1 + sxtw x1, w4 + add x3, x1, #0x1 stur w3, [x29, #-0x28] - ldrsw x1, [x1, x2, lsl #2] + ldrsw x1, [x2, x1, lsl #2] ldr x0, [x0, x1, lsl #3] br x0 ldur x0, [x29, #-0x20] @@ -132,9 +131,9 @@ Disassembly of section .text: cmp x0, #0x384 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_into_computed_goto.x64.asm b/tests/snapshots/asm/inline_into_computed_goto.x64.asm index 1b1c2e614..cf7ea24d8 100644 --- a/tests/snapshots/asm/inline_into_computed_goto.x64.asm +++ b/tests/snapshots/asm/inline_into_computed_goto.x64.asm @@ -56,11 +56,11 @@ Disassembly of section .text: movq %rcx, -0x20(%rbp) movl %ecx, -0x28(%rbp) leaq -0x18(%rbp), %rax - movq 0x10(%rbp), %rcx - movslq -0x28(%rbp), %rdx - leaq 0x1(%rdx), %rsi + movq 0x10(%rbp), %rdx + movslq %ecx, %rcx + leaq 0x1(%rcx), %rsi movl %esi, -0x28(%rbp) - movslq (%rcx,%rdx,4), %rcx + movslq (%rdx,%rcx,4), %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movq -0x20(%rbp), %rax @@ -69,17 +69,16 @@ Disassembly of section .text: movslq -0x28(%rbp), %rsi leaq 0x1(%rsi), %rdi movl %edi, -0x28(%rbp) - movslq (%rdx,%rsi,4), %rdx - movq (%rcx,%rdx,8), %rcx + movslq (%rdx,%rsi,4), %rsi + movq (%rcx,%rsi,8), %rcx andq $-0x4, %rcx addq %rcx, %rax movq %rax, -0x20(%rbp) leaq -0x18(%rbp), %rax - movq 0x10(%rbp), %rcx - movslq -0x28(%rbp), %rdx - leaq 0x1(%rdx), %rsi + movslq %edi, %rcx + leaq 0x1(%rcx), %rsi movl %esi, -0x28(%rbp) - movslq (%rcx,%rdx,4), %rcx + movslq (%rdx,%rcx,4), %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movq -0x20(%rbp), %rax @@ -132,11 +131,10 @@ Disassembly of section .text: cmpq $0x384, %rax # imm = 0x384 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_keyword_uncaps.aarch64.asm b/tests/snapshots/asm/inline_keyword_uncaps.aarch64.asm index 15feab0e2..0ddeea103 100644 --- a/tests/snapshots/asm/inline_keyword_uncaps.aarch64.asm +++ b/tests/snapshots/asm/inline_keyword_uncaps.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 add x0, x0, #0x1 add x0, x0, #0x2 add x0, x0, #0x3 @@ -29,55 +26,11 @@ Disassembly of section .text: add x0, x0, #0xe add x0, x0, #0xf add x0, x0, #0x10 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x0 // =0 - add x0, x0, #0x1 - add x0, x0, #0x2 - add x0, x0, #0x3 - add x0, x0, #0x4 - add x0, x0, #0x5 - add x0, x0, #0x6 - add x0, x0, #0x7 - add x0, x0, #0x8 - add x0, x0, #0x9 - add x0, x0, #0xa - add x0, x0, #0xb - add x0, x0, #0xc - add x0, x0, #0xd - add x0, x0, #0xe - add x0, x0, #0xf - add x0, x0, #0x10 - mov x1, #0x64 // =100 - add x1, x1, #0x1 - add x1, x1, #0x2 - add x1, x1, #0x3 - add x1, x1, #0x4 - add x1, x1, #0x5 - add x1, x1, #0x6 - add x1, x1, #0x7 - add x1, x1, #0x8 - add x1, x1, #0x9 - add x1, x1, #0xa - add x1, x1, #0xb - add x1, x1, #0xc - add x1, x1, #0xd - add x1, x1, #0xe - add x1, x1, #0xf - add x1, x1, #0x10 - add x0, x0, x1 - cmp x0, #0x174 - b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_keyword_uncaps.x64.asm b/tests/snapshots/asm/inline_keyword_uncaps.x64.asm index d90a9bba6..fc4a11aff 100644 --- a/tests/snapshots/asm/inline_keyword_uncaps.x64.asm +++ b/tests/snapshots/asm/inline_keyword_uncaps.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x80, %rsp leaq 0x1(%rdi), %rax addq $0x2, %rax addq $0x3, %rax @@ -30,56 +27,11 @@ Disassembly of section .text: addq $0xe, %rax addq $0xf, %rax addq $0x10, %rax - addq $0x80, %rsp - popq %rbp retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - xorq %rax, %rax - incq %rax - addq $0x2, %rax - addq $0x3, %rax - addq $0x4, %rax - addq $0x5, %rax - addq $0x6, %rax - addq $0x7, %rax - addq $0x8, %rax - addq $0x9, %rax - addq $0xa, %rax - addq $0xb, %rax - addq $0xc, %rax - addq $0xd, %rax - addq $0xe, %rax - addq $0xf, %rax - addq $0x10, %rax - movl $0x64, %ecx - incq %rcx - addq $0x2, %rcx - addq $0x3, %rcx - addq $0x4, %rcx - addq $0x5, %rcx - addq $0x6, %rcx - addq $0x7, %rcx - addq $0x8, %rcx - addq $0x9, %rcx - addq $0xa, %rcx - addq $0xb, %rcx - addq $0xc, %rcx - addq $0xd, %rcx - addq $0xe, %rcx - addq $0xf, %rcx - addq $0x10, %rcx - addq %rcx, %rax - cmpq $0x174, %rax # imm = 0x174 - jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/inline_linkage.aarch64.asm b/tests/snapshots/asm/inline_linkage.aarch64.asm index 4fe810d87..92aeeb708 100644 --- a/tests/snapshots/asm/inline_linkage.aarch64.asm +++ b/tests/snapshots/asm/inline_linkage.aarch64.asm @@ -25,36 +25,14 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xa // =10 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0xb - cset x0, eq mov x2, #0x0 // =0 - cbz x0, - mov x0, #0xa // =10 - add x0, x0, #0x2 - sxtw x0, w0 - cmp x0, #0xc - cset x0, eq - cmp x0, #0x0 - cset x2, ne + mov x2, #0x1 // =1 cbz x2, - mov x0, #0xa // =10 - add x0, x0, #0x3 - sxtw x0, w0 - cmp x0, #0xd - cset x2, eq + mov x2, #0x1 // =1 cbz x2, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b diff --git a/tests/snapshots/asm/inline_linkage.x64.asm b/tests/snapshots/asm/inline_linkage.x64.asm index 538a208d1..49b68f013 100644 --- a/tests/snapshots/asm/inline_linkage.x64.asm +++ b/tests/snapshots/asm/inline_linkage.x64.asm @@ -26,43 +26,17 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xa, %eax - incq %rax - movslq %eax, %rax - cmpq $0xb, %rax - sete %al - movzbq %al, %rax xorq %rdx, %rdx - testq %rax, %rax - je - movl $0xa, %eax - addq $0x2, %rax - movslq %eax, %rax - cmpq $0xc, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - setne %dl - movzbq %dl, %rdx + movl $0x1, %edx testq %rdx, %rdx je - movl $0xa, %eax - addq $0x3, %rax - movslq %eax, %rax - cmpq $0xd, %rax - sete %dl - movzbq %dl, %rdx + movl $0x1, %edx testq %rdx, %rdx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_multi_block_result_forward.aarch64.asm b/tests/snapshots/asm/inline_multi_block_result_forward.aarch64.asm index d12ebbcef..0fa39524f 100644 --- a/tests/snapshots/asm/inline_multi_block_result_forward.aarch64.asm +++ b/tests/snapshots/asm/inline_multi_block_result_forward.aarch64.asm @@ -15,19 +15,16 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 lsl x0, x0, #1 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : sxtw x0, w0 - b + sxtw x1, w0 + lsl x1, x1, #1 + sxtw x1, w1 add x2, x0, x0 cmp x0, #0x3 b.le @@ -36,10 +33,6 @@ Disassembly of section .text: add x0, x1, x2 sxtw x0, w0 ret - sxtw x1, w0 - lsl x1, x1, #1 - sxtw x1, w1 - b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/inline_multi_block_result_forward.x64.asm b/tests/snapshots/asm/inline_multi_block_result_forward.x64.asm index dfcc24e95..2ca360d7a 100644 --- a/tests/snapshots/asm/inline_multi_block_result_forward.x64.asm +++ b/tests/snapshots/asm/inline_multi_block_result_forward.x64.asm @@ -16,20 +16,17 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi movq %rdi, %rax shlq $0x1, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : movslq %edi, %rdi - jmp + movslq %edi, %rax + shlq $0x1, %rax + movslq %eax, %rcx leaq (%rdi,%rdi), %rdx cmpq $0x3, %rdi jle @@ -38,10 +35,6 @@ Disassembly of section .text: leaq (%rcx,%rdx), %rax movslq %eax, %rax retq - movslq %edi, %rax - shlq $0x1, %rax - movslq %eax, %rcx - jmp
: pushq %rbp @@ -49,4 +42,4 @@ Disassembly of section .text: movl $0x5, %edi popq %rbp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_one_word_struct.aarch64.asm b/tests/snapshots/asm/inline_one_word_struct.aarch64.asm index 34b58efa3..ae58d3f3d 100644 --- a/tests/snapshots/asm/inline_one_word_struct.aarch64.asm +++ b/tests/snapshots/asm/inline_one_word_struct.aarch64.asm @@ -24,57 +24,48 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x1, w1 mov x3, #0x0 // =0 mov x2, x3 - sxtw x4, w3 - cmp x4, x1 - b.ge - b - sxtw x3, w3 - add x3, x3, #0x1 b + ldr x5, [x0, x4, lsl #3] + add x2, x2, x5 + add x3, x4, #0x1 sxtw x4, w3 - ldr x4, [x0, x4, lsl #3] - add x2, x2, x4 - b + cmp x4, x1 + b.lt mov x0, x2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x50 - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x5 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b sub x0, x29, #0x28 - sxtw x2, w1 - add x3, x2, #0x1 - sxtw x3, w3 - mov x17, #0x64 // =100 - mul x3, x3, x17 - str x3, [x0, x2, lsl #3] - b + add x0, x0, #0x0 + mov x1, #0x64 // =100 + str x1, [x0] + sub x0, x29, #0x28 + mov x1, #0xc8 // =200 + str x1, [x0, #0x8] + sub x0, x29, #0x28 + mov x1, #0x12c // =300 + str x1, [x0, #0x10] + sub x0, x29, #0x28 + mov x1, #0x190 // =400 + str x1, [x0, #0x18] + sub x0, x29, #0x28 + mov x1, #0x1f4 // =500 + str x1, [x0, #0x20] sub x0, x29, #0x28 mov x1, #0x5 // =5 bl cmp x0, #0x5dc b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_one_word_struct.x64.asm b/tests/snapshots/asm/inline_one_word_struct.x64.asm index 5354fd8ad..4b008fdc7 100644 --- a/tests/snapshots/asm/inline_one_word_struct.x64.asm +++ b/tests/snapshots/asm/inline_one_word_struct.x64.asm @@ -28,57 +28,48 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movslq %esi, %rsi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq %rsi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp + movq (%rdi,%rdx,8), %r8 + addq %r8, %rax + leaq 0x1(%rdx), %rcx movslq %ecx, %rdx - movq (%rdi,%rdx,8), %rdx - addq %rdx, %rax - jmp - addq $0x20, %rsp - popq %rbp + cmpq %rsi, %rdx + jl retq
: pushq %rbp movq %rsp, %rbp subq $0x50, %rsp - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x28(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movslq %esi, %rsi - imulq $0x64, %rsi, %rsi - movq %rsi, (%rax,%rdx,8) - jmp + addq $0x0, %rax + movl $0x64, %ecx + movq %rcx, (%rax) + leaq -0x28(%rbp), %rax + movl $0xc8, %ecx + movq %rcx, 0x8(%rax) + leaq -0x28(%rbp), %rax + movl $0x12c, %ecx # imm = 0x12C + movq %rcx, 0x10(%rax) + leaq -0x28(%rbp), %rax + movl $0x190, %ecx # imm = 0x190 + movq %rcx, 0x18(%rax) + leaq -0x28(%rbp), %rax + movl $0x1f4, %ecx # imm = 0x1F4 + movq %rcx, 0x20(%rax) leaq -0x28(%rbp), %rdi movl $0x5, %esi callq cmpq $0x5dc, %rax # imm = 0x5DC jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_one_word_struct_return.aarch64.asm b/tests/snapshots/asm/inline_one_word_struct_return.aarch64.asm index 0d1d54650..573448955 100644 --- a/tests/snapshots/asm/inline_one_word_struct_return.aarch64.asm +++ b/tests/snapshots/asm/inline_one_word_struct_return.aarch64.asm @@ -44,30 +44,22 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - cmp x2, #0x5 - b.ge b - sxtw x1, w1 - add x1, x1, #0x1 - b - add x2, x1, #0x1 - sxtw x2, w2 + add x3, x1, #0x1 + sxtw x3, w3 mov x17, #0xa // =10 - mul x2, x2, x17 - add x0, x0, x2 - b + mul x3, x3, x17 + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + cmp x2, #0x5 + b.lt cmp x0, #0x96 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_one_word_struct_return.x64.asm b/tests/snapshots/asm/inline_one_word_struct_return.x64.asm index 919a19bad..9e879cb97 100644 --- a/tests/snapshots/asm/inline_one_word_struct_return.x64.asm +++ b/tests/snapshots/asm/inline_one_word_struct_return.x64.asm @@ -47,30 +47,23 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp xorq %rcx, %rcx movq %rcx, %rax + jmp + leaq 0x1(%rcx), %rsi + movslq %esi, %rsi + imulq $0xa, %rsi, %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx movslq %ecx, %rdx cmpq $0x5, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq 0x1(%rcx), %rdx - movslq %edx, %rdx - imulq $0xa, %rdx, %rdx - addq %rdx, %rax - jmp + jl cmpq $0x96, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x40, %rsp - popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_phi_caller_leaf_helper.aarch64.asm b/tests/snapshots/asm/inline_phi_caller_leaf_helper.aarch64.asm index 859958080..f42983518 100644 --- a/tests/snapshots/asm/inline_phi_caller_leaf_helper.aarch64.asm +++ b/tests/snapshots/asm/inline_phi_caller_leaf_helper.aarch64.asm @@ -29,32 +29,28 @@ Disassembly of section .text: mov x4, #0xf372 // =62322 movk x4, #0x3c6e, lsl #16 mov x3, #0x0 // =0 - sxtw x2, w3 - cmp x2, x1 - b.ge - b - sxtw x2, w3 - add x3, x2, #0x1 b - mov w2, w6 - mov w7, w5 + mov w7, w6 + mov w8, w5 mov w4, w4 - mov w2, w2 mov w7, w7 - and x7, x2, x7 - mvn x2, x2 - mov w2, w2 + mov w8, w8 + and x8, x7, x8 + mvn x7, x7 + mov w7, w7 mov w4, w4 - and x2, x2, x4 - eor x2, x7, x2 - sxtw x4, w3 - ldr w4, [x0, x4, lsl #2] - add x2, x2, x4 - mov w2, w2 + and x4, x7, x4 + eor x4, x8, x4 + ldr w7, [x0, x2, lsl #2] + add x4, x4, x7 + mov w7, w4 mov w4, w5 mov w5, w6 - mov w6, w2 - b + mov w6, w7 + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, x1 + b.lt mov w0, w6 mov w1, w5 eor x0, x0, x1 @@ -87,9 +83,9 @@ Disassembly of section .text: cmp x0, x17 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_phi_caller_leaf_helper.x64.asm b/tests/snapshots/asm/inline_phi_caller_leaf_helper.x64.asm index d81377a85..fb45cff68 100644 --- a/tests/snapshots/asm/inline_phi_caller_leaf_helper.x64.asm +++ b/tests/snapshots/asm/inline_phi_caller_leaf_helper.x64.asm @@ -24,40 +24,37 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) movslq %esi, %rsi movl $0x6a09e667, %r9d # imm = 0x6A09E667 movl $0xbb67ae85, %r8d # imm = 0xBB67AE85 movl $0x3c6ef372, %edx # imm = 0x3C6EF372 xorq %rcx, %rcx - movslq %ecx, %rax - cmpq %rsi, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - movl %r9d, %eax - movl %r8d, %ebx + movl %r9d, %ebx + movl %r8d, %r12d movl %edx, %edx - movl %eax, %eax movl %ebx, %ebx - andq %rax, %rbx - xorq $-0x1, %rax - movl %eax, %eax + movl %r12d, %r12d + andq %rbx, %r12 + xorq $-0x1, %rbx + movl %ebx, %ebx movl %edx, %edx - andq %rdx, %rax - xorq %rbx, %rax - movslq %ecx, %rdx - movl (%rdi,%rdx,4), %edx - addq %rdx, %rax - movl %eax, %eax + andq %rbx, %rdx + xorq %r12, %rdx + movl (%rdi,%rax,4), %ebx + addq %rbx, %rdx + movl %edx, %ebx movl %r8d, %edx movl %r9d, %r8d - movl %eax, %r9d - jmp + movl %ebx, %r9d + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq %rsi, %rax + jl movl %r9d, %eax movl %r8d, %ecx xorq %rcx, %rax @@ -65,7 +62,8 @@ Disassembly of section .text: xorq %rcx, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x10, %rsp + movq 0x10(%rsp), %r13 + addq $0x20, %rsp popq %rbp retq @@ -92,10 +90,10 @@ Disassembly of section .text: cmpq %r11, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x40, %rsp popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_phi_narrow_param_return.aarch64.asm b/tests/snapshots/asm/inline_phi_narrow_param_return.aarch64.asm index 8c3596d22..1e1b783d6 100644 --- a/tests/snapshots/asm/inline_phi_narrow_param_return.aarch64.asm +++ b/tests/snapshots/asm/inline_phi_narrow_param_return.aarch64.asm @@ -14,35 +14,26 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x0, w0 mov x3, #0x1 // =1 mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, x0 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b mov x17, #0x4243 // =16963 movk x17, #0xf, lsl #16 - mul x1, x3, x17 - add x1, x1, x2 - sxtw x1, w1 - add x3, x1, #0x1 - b + mul x3, x3, x17 + add x3, x3, x2 + sxtw x3, w3 + add x3, x3, #0x1 + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, x0 + b.lt mov x0, x3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 mov x0, #0x32 // =50 bl mov x17, #0x2046 // =8262 @@ -52,9 +43,8 @@ Disassembly of section .text: cmp x0, x17 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_phi_narrow_param_return.x64.asm b/tests/snapshots/asm/inline_phi_narrow_param_return.x64.asm index 492619a24..65b003f79 100644 --- a/tests/snapshots/asm/inline_phi_narrow_param_return.x64.asm +++ b/tests/snapshots/asm/inline_phi_narrow_param_return.x64.asm @@ -16,42 +16,32 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movslq %edi, %rdi movl $0x1, %edx xorq %rcx, %rcx - movslq %ecx, %rax - cmpq %rdi, %rax - jge jmp - movslq %ecx, %rax + imulq $0xf4243, %rdx, %rdx # imm = 0xF4243 + addq %rcx, %rdx + movslq %edx, %rdx + incq %rdx leaq 0x1(%rax), %rcx - jmp - imulq $0xf4243, %rdx, %rax # imm = 0xF4243 - addq %rcx, %rax - movslq %eax, %rax - leaq 0x1(%rax), %rdx - jmp + movslq %ecx, %rax + cmpq %rdi, %rax + jl movq %rdx, %rax - addq $0x20, %rsp - popq %rbp retq
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x32, %edi callq cmpq $-0x4728dfba, %rax # imm = 0xB8D72046 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + movl $0x1, %ecx + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/inline_struct_param_mutated.aarch64.asm b/tests/snapshots/asm/inline_struct_param_mutated.aarch64.asm index 75dd2e949..4cab15e55 100644 --- a/tests/snapshots/asm/inline_struct_param_mutated.aarch64.asm +++ b/tests/snapshots/asm/inline_struct_param_mutated.aarch64.asm @@ -48,9 +48,9 @@ Disassembly of section .text: cmp x0, x17 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_struct_param_mutated.x64.asm b/tests/snapshots/asm/inline_struct_param_mutated.x64.asm index 2010d9f2f..e849d482f 100644 --- a/tests/snapshots/asm/inline_struct_param_mutated.x64.asm +++ b/tests/snapshots/asm/inline_struct_param_mutated.x64.asm @@ -49,11 +49,11 @@ Disassembly of section .text: cmpq $0x19a2d, %rax # imm = 0x19A2D jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_struct_return_escape.aarch64.asm b/tests/snapshots/asm/inline_struct_return_escape.aarch64.asm index 371af26aa..c1fb6f46b 100644 --- a/tests/snapshots/asm/inline_struct_return_escape.aarch64.asm +++ b/tests/snapshots/asm/inline_struct_return_escape.aarch64.asm @@ -58,10 +58,10 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b diff --git a/tests/snapshots/asm/inline_struct_return_escape.x64.asm b/tests/snapshots/asm/inline_struct_return_escape.x64.asm index 9406501b6..11b4cbba2 100644 --- a/tests/snapshots/asm/inline_struct_return_escape.x64.asm +++ b/tests/snapshots/asm/inline_struct_return_escape.x64.asm @@ -61,12 +61,12 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x40, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_struct_return_reg.aarch64.asm b/tests/snapshots/asm/inline_struct_return_reg.aarch64.asm index 69e1f3fab..232c7ae32 100644 --- a/tests/snapshots/asm/inline_struct_return_reg.aarch64.asm +++ b/tests/snapshots/asm/inline_struct_return_reg.aarch64.asm @@ -54,43 +54,36 @@ Disassembly of section .text: str x10, [x0, #0x18] ldr x10, [sp], #0x10 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x4 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x20 + sub x3, x29, #0x40 + ldr x3, [x3, x0, lsl #3] + str x3, [x2, x0, lsl #3] add x1, x0, #0x1 - b + sxtw x0, w1 + cmp x0, #0x4 + b.lt sub x0, x29, #0x20 - sxtw x2, w1 - sub x3, x29, #0x40 - sxtw x4, w1 - ldr x3, [x3, x4, lsl #3] - str x3, [x0, x2, lsl #3] - b - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w1 - cmp x2, #0x4 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sub x2, x29, #0x20 - sxtw x3, w1 - ldr x2, [x2, x3, lsl #3] - add x0, x0, x2 - b - mov x1, #0x55 // =85 + add x0, x0, #0x0 + ldr x0, [x0] + add x0, x0, #0x0 + sub x1, x29, #0x20 + ldr x1, [x1, #0x8] + add x0, x0, x1 + sub x1, x29, #0x20 + ldr x1, [x1, #0x10] add x0, x0, x1 + sub x1, x29, #0x20 + ldr x1, [x1, #0x18] + add x0, x0, x1 + add x0, x0, #0x55 mov x17, #0xa055 // =41045 cmp x0, x17 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x90 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_struct_return_reg.x64.asm b/tests/snapshots/asm/inline_struct_return_reg.x64.asm index cc92ad35f..29bb2ae8b 100644 --- a/tests/snapshots/asm/inline_struct_return_reg.x64.asm +++ b/tests/snapshots/asm/inline_struct_return_reg.x64.asm @@ -57,44 +57,37 @@ Disassembly of section .text: movq %rdx, 0x18(%rax) popq %rdx xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x4, %rax - jge jmp - movslq %ecx, %rax + leaq -0x20(%rbp), %rdx + leaq -0x40(%rbp), %rsi + movq (%rsi,%rax,8), %rsi + movq %rsi, (%rdx,%rax,8) leaq 0x1(%rax), %rcx - jmp + movslq %ecx, %rax + cmpq $0x4, %rax + jl leaq -0x20(%rbp), %rax - movslq %ecx, %rdx - leaq -0x40(%rbp), %rsi - movslq %ecx, %rdi - movq (%rsi,%rdi,8), %rsi - movq %rsi, (%rax,%rdx,8) - jmp - xorq %rcx, %rcx - movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x4, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq -0x20(%rbp), %rdx - movslq %ecx, %rsi - movq (%rdx,%rsi,8), %rdx - addq %rdx, %rax - jmp - movl $0x55, %ecx + addq $0x0, %rax + movq (%rax), %rax + addq $0x0, %rax + leaq -0x20(%rbp), %rcx + movq 0x8(%rcx), %rcx + addq %rcx, %rax + leaq -0x20(%rbp), %rcx + movq 0x10(%rcx), %rcx addq %rcx, %rax + leaq -0x20(%rbp), %rcx + movq 0x18(%rcx), %rcx + addq %rcx, %rax + addq $0x55, %rax cmpq $0xa055, %rax # imm = 0xA055 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x90, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/inline_two_word_struct_return.aarch64.asm b/tests/snapshots/asm/inline_two_word_struct_return.aarch64.asm index 1f634d01a..df4c12052 100644 --- a/tests/snapshots/asm/inline_two_word_struct_return.aarch64.asm +++ b/tests/snapshots/asm/inline_two_word_struct_return.aarch64.asm @@ -46,84 +46,115 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x100 - mov x4, #0x0 // =0 - mov x0, x4 - sxtw x1, w0 - cmp x1, #0x8 - b.ge - b - sxtw x0, w0 - add x0, x0, #0x1 + mov x1, #0x0 // =0 b - sub x1, x29, #0x80 - sxtw x2, w0 - lsl x3, x2, #4 - add x1, x1, x3 + sub x2, x29, #0x80 + lsl x3, x0, #4 + add x2, x2, x3 mov x17, #0xa // =10 - mul x2, x2, x17 + mul x3, x0, x17 + sub x4, x29, #0xe8 + str w3, [x4] + sub x3, x29, #0xe8 + mov x4, #0x1 // =1 + str x4, [x3, #0x8] sub x3, x29, #0xe8 - str w2, [x3] - sub x2, x29, #0xe8 - mov x3, #0x1 // =1 - str x3, [x2, #0x8] - sub x2, x29, #0xe8 str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x1] - ldr x10, [x2, #0x8] - str x10, [x1, #0x8] + ldr x10, [x3] + str x10, [x2] + ldr x10, [x3, #0x8] + str x10, [x2, #0x8] ldr x10, [sp], #0x10 - b - mov x1, #0x0 // =0 + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b + b.lt sub x0, x29, #0x80 - sxtw x2, w1 - lsl x2, x2, #4 - add x0, x0, x2 + add x0, x0, #0x0 ldrsw x0, [x0] + sub x1, x29, #0x80 + add x1, x1, #0x0 + ldr x1, [x1, #0x8] + add x0, x0, x1 + add x0, x0, #0x0 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x10] sub x2, x29, #0x80 - sxtw x3, w1 - lsl x3, x3, #4 - add x2, x2, x3 + add x2, x2, #0x10 ldr x2, [x2, #0x8] - add x0, x0, x2 - add x4, x4, x0 - b - mov x0, #0xaaaa // =43690 - mov x1, #0xbbbb // =48059 - sub x2, x29, #0xf8 - str x0, [x2] - sub x0, x29, #0xf8 - str x1, [x0, #0x8] - sub x0, x29, #0xf8 - sub x1, x29, #0xb8 + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x20] + sub x2, x29, #0x80 + add x2, x2, #0x20 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x30] + sub x2, x29, #0x80 + add x2, x2, #0x30 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x40] + sub x2, x29, #0x80 + add x2, x2, #0x40 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x50] + sub x2, x29, #0x80 + add x2, x2, #0x50 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x60] + sub x2, x29, #0x80 + add x2, x2, #0x60 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + sub x1, x29, #0x80 + ldrsw x1, [x1, #0x70] + sub x2, x29, #0x80 + add x2, x2, #0x70 + ldr x2, [x2, #0x8] + add x1, x1, x2 + add x0, x0, x1 + mov x1, #0xaaaa // =43690 + mov x2, #0xbbbb // =48059 + sub x3, x29, #0xf8 + str x1, [x3] + sub x1, x29, #0xf8 + str x2, [x1, #0x8] + sub x1, x29, #0xf8 + sub x2, x29, #0xb8 str x10, [sp, #-0x10]! - ldr x10, [x0] - str x10, [x1] - ldr x10, [x0, #0x8] - str x10, [x1, #0x8] + ldr x10, [x1] + str x10, [x2] + ldr x10, [x1, #0x8] + str x10, [x2, #0x8] ldr x10, [sp], #0x10 - mov x0, x1 - sub x0, x29, #0xb8 - ldr x0, [x0] + mov x1, x2 sub x1, x29, #0xb8 - ldr x1, [x1, #0x8] + ldr x1, [x1] + sub x2, x29, #0xb8 + ldr x2, [x2, #0x8] + add x1, x1, x2 add x0, x0, x1 - add x0, x4, x0 mov x17, #0x6785 // =26501 movk x17, #0x1, lsl #16 cmp x0, x17 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/inline_two_word_struct_return.x64.asm b/tests/snapshots/asm/inline_two_word_struct_return.x64.asm index 3ff2d9b77..b70433a0c 100644 --- a/tests/snapshots/asm/inline_two_word_struct_return.x64.asm +++ b/tests/snapshots/asm/inline_two_word_struct_return.x64.asm @@ -47,83 +47,114 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x100, %rsp # imm = 0x100 - xorq %rdi, %rdi - movq %rdi, %rax - movslq %eax, %rcx - cmpq $0x8, %rcx - jge - jmp - movslq %eax, %rax - incq %rax + xorq %rcx, %rcx jmp - leaq -0x80(%rbp), %rcx - movslq %eax, %rdx - movq %rdx, %rsi + leaq -0x80(%rbp), %rdx + movq %rax, %rsi shlq $0x4, %rsi - addq %rsi, %rcx - imulq $0xa, %rdx, %rdx + addq %rsi, %rdx + imulq $0xa, %rax, %rsi + leaq -0xe8(%rbp), %rdi + movl %esi, (%rdi) + leaq -0xe8(%rbp), %rsi + movl $0x1, %edi + movq %rdi, 0x8(%rsi) leaq -0xe8(%rbp), %rsi - movl %edx, (%rsi) - leaq -0xe8(%rbp), %rdx - movl $0x1, %esi - movq %rsi, 0x8(%rdx) - leaq -0xe8(%rbp), %rdx pushq %rax - movq (%rdx), %rax - movq %rax, (%rcx) - movq 0x8(%rdx), %rax - movq %rax, 0x8(%rcx) + movq (%rsi), %rax + movq %rax, (%rdx) + movq 0x8(%rsi), %rax + movq %rax, 0x8(%rdx) popq %rax - jmp - xorq %rcx, %rcx + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp + jl leaq -0x80(%rbp), %rax - movslq %ecx, %rdx - shlq $0x4, %rdx - addq %rdx, %rax + addq $0x0, %rax movslq (%rax), %rax + leaq -0x80(%rbp), %rcx + addq $0x0, %rcx + movq 0x8(%rcx), %rcx + addq %rcx, %rax + addq $0x0, %rax + leaq -0x80(%rbp), %rcx + movslq 0x10(%rcx), %rcx leaq -0x80(%rbp), %rdx - movslq %ecx, %rsi - shlq $0x4, %rsi - addq %rsi, %rdx + addq $0x10, %rdx movq 0x8(%rdx), %rdx - addq %rdx, %rax - addq %rax, %rdi - jmp - movl $0xaaaa, %eax # imm = 0xAAAA - movl $0xbbbb, %ecx # imm = 0xBBBB - leaq -0xf8(%rbp), %rdx - movq %rax, (%rdx) - leaq -0xf8(%rbp), %rax - movq %rcx, 0x8(%rax) - leaq -0xf8(%rbp), %rax - leaq -0xb8(%rbp), %rcx - pushq %rdx - movq (%rax), %rdx - movq %rdx, (%rcx) - movq 0x8(%rax), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x20(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x20, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x30(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x30, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x40(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x40, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x50(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x50, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x60(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x60, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + leaq -0x80(%rbp), %rcx + movslq 0x70(%rcx), %rcx + leaq -0x80(%rbp), %rdx + addq $0x70, %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0xaaaa, %ecx # imm = 0xAAAA + movl $0xbbbb, %edx # imm = 0xBBBB + leaq -0xf8(%rbp), %rsi + movq %rcx, (%rsi) + leaq -0xf8(%rbp), %rcx movq %rdx, 0x8(%rcx) - popq %rdx - movq %rcx, %rax - leaq -0xb8(%rbp), %rax - movq (%rax), %rax + leaq -0xf8(%rbp), %rcx + leaq -0xb8(%rbp), %rdx + pushq %rax + movq (%rcx), %rax + movq %rax, (%rdx) + movq 0x8(%rcx), %rax + movq %rax, 0x8(%rdx) + popq %rax + movq %rdx, %rcx leaq -0xb8(%rbp), %rcx - movq 0x8(%rcx), %rcx + movq (%rcx), %rcx + leaq -0xb8(%rbp), %rdx + movq 0x8(%rdx), %rdx + addq %rdx, %rcx addq %rcx, %rax - addq %rdi, %rax cmpq $0x16785, %rax # imm = 0x16785 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x100, %rsp # imm = 0x100 popq %rbp retq - addb %al, (%rax) + movl $0x1, %ecx + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/int32_sign_extend_elision.aarch64.asm b/tests/snapshots/asm/int32_sign_extend_elision.aarch64.asm index 95f2c1250..5d6a59e11 100644 --- a/tests/snapshots/asm/int32_sign_extend_elision.aarch64.asm +++ b/tests/snapshots/asm/int32_sign_extend_elision.aarch64.asm @@ -17,36 +17,21 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 add x0, x0, x1 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mul x0, x0, x1 sxtw x0, w0 cmp x0, #0x0 cset x0, lt - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 add x1, x1, x2 sxtw x1, w1 ldrsw x0, [x0, x1, lsl #2] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : @@ -60,97 +45,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x40 - mov x0, #0xffff // =65535 - movk x0, #0x7fff, lsl #16 - mov x1, #0x80000000 // =2147483648 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - mov x2, #0x1 // =1 - mov x3, #0xffff // =65535 - movk x3, #0xffff, lsl #16 - movk x3, #0xffff, lsl #32 - movk x3, #0xffff, lsl #48 - add x0, x0, x2 - add x0, x0, x1 - add x0, x0, x3 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - add x0, x1, x0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x0, x17 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x9400 // =37888 - movk x0, #0x7735, lsl #16 - add x0, x0, x0 - sxtw x0, w0 - mov x17, #0x2800 // =10240 - movk x17, #0xee6b, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xfffd // =65533 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x2, #0x4 // =4 - mul x0, x0, x2 - sxtw x0, w0 - cmp x0, #0x0 - cset x0, lt - cmp x0, #0x1 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x2 // =2 - mul x0, x1, x0 - sxtw x0, w0 - cmp x0, #0x0 - cset x0, lt - cmp x0, #0x0 - b.eq - mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0x2 // =2 - mov w0, w0 - mov w1, w1 - add x0, x0, x1 - mov w0, w0 - cmp x0, #0x1 - b.eq - mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x28 adrp x1, add x1, x1, @@ -170,13 +64,8 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x28 add x0, x0, #0x8 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - add x1, x1, x1 - sxtw x1, w1 - ldrsw x0, [x0, x1, lsl #2] + sub x0, x0, #0x8 + ldrsw x0, [x0] cmp x0, #0xa b.eq mov x0, #0x7 // =7 @@ -187,3 +76,27 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/int32_sign_extend_elision.x64.asm b/tests/snapshots/asm/int32_sign_extend_elision.x64.asm index 104577112..27e4d49ed 100644 --- a/tests/snapshots/asm/int32_sign_extend_elision.x64.asm +++ b/tests/snapshots/asm/int32_sign_extend_elision.x64.asm @@ -18,38 +18,23 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq (%rdi,%rsi), %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movq %rdi, %rax imulq %rsi, %rax movslq %eax, %rax testq %rax, %rax setl %al movzbq %al, %rax - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq (%rsi,%rdx), %rax movslq %eax, %rax movslq (%rdi,%rax,4), %rax - addq $0x10, %rsp - popq %rbp retq : @@ -63,75 +48,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x40, %rsp - movl $0x7fffffff, %eax # imm = 0x7FFFFFFF - movabsq $-0x80000000, %rcx # imm = 0x80000000 - movl $0x1, %edx - movabsq $-0x1, %rsi - addq %rdx, %rax - addq %rcx, %rax - addq %rsi, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0x1, %eax - addq $0x40, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - addq %rcx, %rax - movslq %eax, %rax - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - je - movl $0x2, %eax - addq $0x40, %rsp - popq %rbp - retq - movl $0x77359400, %eax # imm = 0x77359400 - addq %rax, %rax - movslq %eax, %rax - cmpq $-0x1194d800, %rax # imm = 0xEE6B2800 - je - movl $0x3, %eax - addq $0x40, %rsp - popq %rbp - retq - movabsq $-0x3, %rax - movl $0x4, %edx - imulq %rdx, %rax - movslq %eax, %rax - testq %rax, %rax - setl %al - movzbq %al, %rax - cmpq $0x1, %rax - je - movl $0x4, %eax - addq $0x40, %rsp - popq %rbp - retq - movl $0x2, %eax - imulq %rcx, %rax - movslq %eax, %rax - testq %rax, %rax - setl %al - movzbq %al, %rax - testq %rax, %rax - je - movl $0x5, %eax - addq $0x40, %rsp - popq %rbp - retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0x2, %ecx - movl %eax, %eax - movl %ecx, %ecx - addq %rcx, %rax - movl %eax, %eax - cmpq $0x1, %rax - je - movl $0x6, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x28(%rbp), %rax leaq , %rcx pushq %rdx @@ -150,10 +66,8 @@ Disassembly of section .text: popq %rdx leaq -0x28(%rbp), %rax addq $0x8, %rax - movabsq $-0x1, %rcx - addq %rcx, %rcx - movslq %ecx, %rcx - movslq (%rax,%rcx,4), %rax + addq $-0x8, %rax + movslq (%rax), %rax cmpq $0xa, %rax je movl $0x7, %eax @@ -164,5 +78,27 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) + movl $0x1, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x40, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/int_literal_boundary_types.aarch64.asm b/tests/snapshots/asm/int_literal_boundary_types.aarch64.asm index 9aae0b7f2..8305551be 100644 --- a/tests/snapshots/asm/int_literal_boundary_types.aarch64.asm +++ b/tests/snapshots/asm/int_literal_boundary_types.aarch64.asm @@ -10,54 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xffff // =65535 - movk x0, #0x7fff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x0 // =0 - b mov x1, #0x0 // =0 cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x80000000 // =2147483648 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - cmp x1, x0 - b.hs - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x2, #0x1 // =1 mov x2, #0x0 // =0 @@ -65,20 +20,21 @@ Disassembly of section .text: mov x2, #0x0 // =0 cbz x2, mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x8 // =8 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - cmp x1, x0 - b.hs - mov x0, #0x8 // =8 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b + mov x0, #0x1 // =1 + ret + mov x1, #0x0 // =0 + b + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x5 // =5 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x8 // =8 + ret diff --git a/tests/snapshots/asm/int_literal_boundary_types.x64.asm b/tests/snapshots/asm/int_literal_boundary_types.x64.asm index 512073ab5..ea664d25c 100644 --- a/tests/snapshots/asm/int_literal_boundary_types.x64.asm +++ b/tests/snapshots/asm/int_literal_boundary_types.x64.asm @@ -11,48 +11,10 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movabsq $-0x80000001, %rax # imm = 0xFFFFFFFF7FFFFFFF - movabsq $-0x80000001, %r11 # imm = 0xFFFFFFFF7FFFFFFF - cmpq %r11, %rax - je - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rcx, %rcx - jmp xorq %rcx, %rcx testq %rcx, %rcx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x80000000, %eax # imm = 0x80000000 - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF - cmpq %rax, %rcx - jae - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x4, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x1, %edx xorq %rdx, %rdx @@ -62,19 +24,21 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x7, %eax - addq $0x20, %rsp - popq %rbp - retq - movl $0x8, %eax - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF - cmpq %rax, %rcx - jae - movl $0x8, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp + movl $0x1, %eax + retq + xorq %rcx, %rcx + jmp + movl $0x3, %eax + retq + movl $0x4, %eax + retq + movl $0x5, %eax + retq + movl $0x6, %eax + retq + movl $0x8, %eax + retq diff --git a/tests/snapshots/asm/int_times_double_into_local.aarch64.asm b/tests/snapshots/asm/int_times_double_into_local.aarch64.asm index f18545f67..72f35d9d5 100644 --- a/tests/snapshots/asm/int_times_double_into_local.aarch64.asm +++ b/tests/snapshots/asm/int_times_double_into_local.aarch64.asm @@ -36,10 +36,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x8 // =8 mov x20, #0x0 // =0 mov x1, x20 @@ -49,9 +48,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x8 // =8 mov x1, #0x1 // =1 @@ -69,9 +67,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x8 // =8 mov x1, #0x2 // =2 @@ -89,12 +86,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm b/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm index 4127980a5..9d8a46516 100644 --- a/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm +++ b/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm @@ -10,11 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x8 mov x1, #0xa // =10 strb w1, [x0] @@ -44,10 +42,8 @@ Disassembly of section .text: cmp x0, #0x64 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0xa // =10 scvtf d3, x0 @@ -58,10 +54,8 @@ Disassembly of section .text: cmp x0, #0x3e8 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0xa // =10 scvtf d3, x0 @@ -72,10 +66,8 @@ Disassembly of section .text: cmp x0, #0x7d0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x8 ldrb w0, [x0, #0x1] @@ -91,80 +83,58 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - mov x0, #0x4189 // =16777 - movk x0, #0xe560, lsl #16 - movk x0, #0x22d0, lsl #32 - movk x0, #0x3fd3, lsl #48 - fcvt d0, s0 - mov x1, #0x1062 // =4194 - movk x1, #0x3958, lsl #16 - movk x1, #0xc8b4, lsl #32 - movk x1, #0x3fe2, lsl #48 - fcvt d1, s1 - fmov d16, x1 - fmul d1, d16, d1 - fmov d16, x0 - fmadd d0, d16, d0, d1 - mov x0, #0x76c9 // =30409 - movk x0, #0x9fbe, lsl #16 - movk x0, #0x2f1a, lsl #32 - movk x0, #0x3fbd, lsl #48 - fcvt d1, s2 - fmov d16, x0 - fmadd d0, d16, d1, d0 - mov x0, #0x4060000000000000 // =4638707616191610880 - fmov d17, x0 - fsub d0, d0, d17 - fcvt s0, d0 - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4045, lsl #48 - fmov d16, x0 - fneg d1, d16 - fcvt d2, s0 - fcmp d2, d1 - cset x20, gt - cbnz x20, - mov x0, #0x4046000000000000 // =4631389266797133824 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 - cset x20, mi - cbz x20, + mov x0, #0x1687 // =5767 + movk x0, #0x3e99, lsl #16 + mov x1, #0x45a2 // =17826 + movk x1, #0x3f16, lsl #16 + fmov s16, w1 + fmul s1, s16, s1 + fmov s16, w0 + fmadd s0, s16, s0, s1 + mov x0, #0x78d5 // =30933 + movk x0, #0x3de9, lsl #16 + fmov s16, w0 + fmadd s0, s16, s2, s0 + mov x0, #0x43000000 // =1124073472 + fmov s17, w0 + fsub s0, s0, s17 + mov x0, #0x422c0000 // =1110179840 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 + cset x1, gt + cbnz x1, + mov x0, #0x42300000 // =1110441984 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 + cset x1, mi + cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0x7 // =7 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40e00000 // =1088421888 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret b diff --git a/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm b/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm index 7c5fc29c5..e1f6bd4aa 100644 --- a/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm +++ b/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm @@ -13,8 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp - movq %rbx, (%rsp) + subq $0x50, %rsp leaq -0x8(%rbp), %rax movl $0xa, %ecx movb %cl, (%rax) @@ -46,8 +45,7 @@ Disassembly of section .text: cmpq $0x64, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0xa, %eax @@ -61,8 +59,7 @@ Disassembly of section .text: cmpq $0x3e8, %rax # imm = 0x3E8 je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0xa, %eax @@ -76,8 +73,7 @@ Disassembly of section .text: cmpq $0x7d0, %rax # imm = 0x7D0 je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq -0x8(%rbp), %rax @@ -93,67 +89,58 @@ Disassembly of section .text: cmpq $0x2710, %rax # imm = 0x2710 je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq - movabsq $0x3fd322d0e5604189, %rax # imm = 0x3FD322D0E5604189 - cvtss2sd %xmm0, %xmm0 - movabsq $0x3fe2c8b439581062, %rcx # imm = 0x3FE2C8B439581062 - cvtss2sd %xmm1, %xmm1 + movl $0x3e991687, %eax # imm = 0x3E991687 + movl $0x3f1645a2, %ecx # imm = 0x3F1645A2 movapd %xmm1, %xmm15 movq %rcx, %xmm1 - mulsd %xmm15, %xmm1 + mulss %xmm15, %xmm1 movq %rax, %xmm14 movapd %xmm0, %xmm15 movapd %xmm1, %xmm0 - vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x3fbd2f1a9fbe76c9, %rax # imm = 0x3FBD2F1A9FBE76C9 - cvtss2sd %xmm2, %xmm1 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x3de978d5, %eax # imm = 0x3DE978D5 movq %rax, %xmm14 - movapd %xmm1, %xmm15 - vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4060000000000000, %rax # imm = 0x4060000000000000 + movapd %xmm2, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x43000000, %eax # imm = 0x43000000 movq %rax, %xmm15 - subsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4045800000000000, %rax # imm = 0x4045800000000000 + subss %xmm15, %xmm0 + movl $0x422c0000, %eax # imm = 0x422C0000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm2 - ucomisd %xmm1, %xmm2 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + ucomiss %xmm1, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne - movabsq $0x4046000000000000, %rax # imm = 0x4046000000000000 + movl $0x42300000, %eax # imm = 0x42300000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 - setb %bl - movzbq %bl, %rbx + ucomiss %xmm1, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x7, %eax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -162,8 +149,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x6, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq , %rdi @@ -171,9 +157,8 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq jmp - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/integer_boundary_c99.aarch64.asm b/tests/snapshots/asm/integer_boundary_c99.aarch64.asm index ac16c257e..03131b21a 100644 --- a/tests/snapshots/asm/integer_boundary_c99.aarch64.asm +++ b/tests/snapshots/asm/integer_boundary_c99.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,22 +48,37 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x170 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] - b + stp x20, x21, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x0 + b.ne + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0] + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret b adrp x0, add x0, x0, @@ -173,8 +184,6 @@ Disassembly of section .text: sxtw x0, w0 b b - mov x20, #0xff // =255 - b adrp x0, add x0, x0, mov x20, #0x6b // =107 @@ -188,64 +197,34 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xff // =255 - eor x0, x20, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - add x20, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x6e // =110 - str w21, [x0] + mov x20, #0x6e // =110 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x42 // =66 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xff // =255 - and x0, x20, x17 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x17, #0xff // =255 - and x0, x20, x17 - sub x0, x0, #0x1 b adrp x0, add x0, x0, - mov x21, #0x6f // =111 - str w21, [x0] + mov x20, #0x6f // =111 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x44 // =68 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0xff // =255 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x7f // =127 b adrp x0, add x0, x0, @@ -260,15 +239,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - cmp x0, #0x7f - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xff80 // =65408 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -283,42 +253,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xff80 // =65408 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - sub x0, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x72 // =114 - str w21, [x0] + mov x20, #0x72 // =114 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x4b // =75 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - sxtb x0, w0 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0x7f // =127 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 b adrp x0, add x0, x0, @@ -333,38 +281,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - eor x0, x20, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - add x0, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x78 // =120 - str w21, [x0] + mov x20, #0x78 // =120 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x53 // =83 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - and x0, x0, x17 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x0 // =0 - sub x0, x0, #0x1 b adrp x0, add x0, x0, @@ -379,17 +309,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0xffff // =65535 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x7fff // =32767 b adrp x0, add x0, x0, @@ -404,16 +323,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x7fff // =32767 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0x8000 // =32768 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -428,44 +337,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x8000 // =32768 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x17, #0xffff // =65535 - and x0, x20, x17 b adrp x0, add x0, x0, - mov x21, #0x7c // =124 - str w21, [x0] + mov x20, #0x7c // =124 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x5d // =93 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0x8000 // =32768 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x2345 // =9029 - movk x0, #0x1, lsl #16 - sxth x0, w0 b adrp x0, add x0, x0, @@ -480,16 +365,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x2345 // =9029 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffd6 // =65494 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -504,17 +379,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - sxtw x0, w0 - mov x17, #0xffd6 // =65494 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 b adrp x0, add x0, x0, @@ -529,37 +393,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w20 - mov x17, #0xffff // =65535 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x80 // =128 - str w21, [x0] + mov x20, #0x80 // =128 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x6e // =110 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 b adrp x0, add x0, x0, @@ -574,36 +422,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - add x0, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x82 // =130 - str w21, [x0] + mov x20, #0x82 // =130 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x76 // =118 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x0 // =0 - sub x0, x0, #0x1 b adrp x0, add x0, x0, @@ -618,16 +450,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0x7fff, lsl #16 b adrp x0, add x0, x0, @@ -642,16 +464,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0x80000000 // =2147483648 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -666,14 +478,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x80000000 // =2147483648 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -688,39 +492,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x80000000 // =2147483648 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 b adrp x0, add x0, x0, - mov x21, #0x87 // =135 - str w21, [x0] + mov x20, #0x87 // =135 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x86 // =134 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0x80000000 // =2147483648 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -735,63 +520,34 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - add x20, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x8c // =140 - str w21, [x0] + mov x20, #0x8c // =140 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x8e // =142 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - cmp x20, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - sub x0, x20, #0x1 b adrp x0, add x0, x0, - mov x21, #0x8d // =141 - str w21, [x0] + mov x20, #0x8d // =141 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x90 // =144 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0x7fff, lsl #48 b adrp x0, add x0, x0, @@ -806,19 +562,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -833,17 +576,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - asr x0, x0, #1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #-0x8000000000000000 // =-9223372036854775808 b adrp x0, add x0, x0, @@ -858,17 +590,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - lsr x0, x0, #1 - mov x17, #0x4000000000000000 // =4611686018427387904 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -883,19 +604,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - lsr x0, x0, #32 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xfed4 // =65236 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - sxtb x21, w20 b adrp x0, add x0, x0, @@ -910,88 +618,50 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffd4 // =65492 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x21, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x22, #0x96 // =150 - str w22, [x0] + mov x20, #0x96 // =150 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xa9 // =169 - mov x3, x22 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffd4 // =65492 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x21, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x17, #0xff // =255 - and x20, x20, x17 b adrp x0, add x0, x0, - mov x21, #0x97 // =151 - str w21, [x0] + mov x20, #0x97 // =151 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xaa // =170 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xff // =255 - and x0, x20, x17 - mov x17, #0xd4 // =212 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x98 // =152 - str w21, [x0] + mov x20, #0x98 // =152 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xaf // =175 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xff // =255 - and x0, x20, x17 - cmp x0, #0xd4 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x2345 // =9029 - movk x0, #0x1, lsl #16 - sxth x20, w0 b adrp x0, add x0, x0, @@ -1006,35 +676,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x2345 // =9029 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x9a // =154 - str w21, [x0] + mov x20, #0x9a // =154 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xb5 // =181 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0x2345 // =9029 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0x1, lsl #16 - sxth x20, w0 b adrp x0, add x0, x0, @@ -1049,41 +705,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x9c // =156 - str w21, [x0] + mov x20, #0x9c // =156 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xba // =186 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - mov x21, #0x1 // =1 b adrp x0, add x0, x0, @@ -1098,33 +734,20 @@ Disassembly of section .text: bl sxtw x0, w0 b - cmp x20, x21 - cset x0, hi - cmp x0, #0x0 - b.ne - b - sxtw x0, w20 - sxtw x1, w21 b adrp x0, add x0, x0, - mov x22, #0xa0 // =160 - str w22, [x0] + mov x20, #0xa0 // =160 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0xc2 // =194 - mov x3, x22 + mov x3, x20 bl sxtw x0, w0 b - cmp x0, x1 - cset x0, lt - cmp x0, #0x0 - b.ne - b - mov x0, #0x1 // =1 b adrp x0, add x0, x0, @@ -1139,15 +762,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - lsl x0, x0, #30 - sxtw x0, w0 - mov x17, #0x40000000 // =1073741824 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x1 // =1 b adrp x0, add x0, x0, @@ -1162,18 +776,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - lsl x0, x0, #31 - mov w0, w0 - mov x17, #0x80000000 // =2147483648 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -1188,17 +790,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 b adrp x0, add x0, x0, @@ -1213,18 +804,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - adrp x0, - add x0, x0, - ldrsw x0, [x0] - cmp x0, #0x0 - b.ne b adrp x0, add x0, x0, @@ -1239,25 +818,4 @@ Disassembly of section .text: bl sxtw x0, w0 b - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldrsw x0, [x0] - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x170 - ldp x29, x30, [sp], #0x10 - ret + b diff --git a/tests/snapshots/asm/integer_boundary_c99.x64.asm b/tests/snapshots/asm/integer_boundary_c99.x64.asm index aca9fb437..9a98b3c6e 100644 --- a/tests/snapshots/asm/integer_boundary_c99.x64.asm +++ b/tests/snapshots/asm/integer_boundary_c99.x64.asm @@ -56,11 +56,30 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x160, %rsp # imm = 0x160 + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - jmp + leaq , %rax + movslq (%rax), %rax + testq %rax, %rax + jne + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + leaq , %rax + movslq (%rax), %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq jmp leaq , %rax movl $0x64, %ebx @@ -166,8 +185,6 @@ Disassembly of section .text: movslq %eax, %rax jmp jmp - movl $0xff, %ebx - jmp leaq , %rax movl $0x6b, %ebx movl %ebx, (%rax) @@ -181,65 +198,34 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movq %rbx, %rax - xorq $0xff, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - incq %rbx jmp leaq , %rax - movl $0x6e, %r12d - movl %r12d, (%rax) + movl $0x6e, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x42, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movq %rbx, %rax - andq $0xff, %rax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movq %rbx, %rax - andq $0xff, %rax - decq %rax jmp leaq , %rax - movl $0x6f, %r12d - movl %r12d, (%rax) + movl $0x6f, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x44, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - andq $0xff, %rax - xorq $0xff, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x7f, %eax jmp leaq , %rax movl $0x70, %ebx @@ -254,13 +240,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x7f, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x80, %rbx jmp leaq , %rax movl $0x71, %ebx @@ -275,38 +254,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x80, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq -0x1(%rbx), %rax jmp leaq , %rax - movl $0x72, %r12d - movl %r12d, (%rax) + movl $0x72, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x4b, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movsbq %al, %rax - andq $0xff, %rax - xorq $0x7f, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xffff, %ebx # imm = 0xFFFF jmp leaq , %rax movl $0x73, %ebx @@ -321,39 +282,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movq %rbx, %rax - xorq $0xffff, %rax # imm = 0xFFFF - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq 0x1(%rbx), %rax jmp leaq , %rax - movl $0x78, %r12d - movl %r12d, (%rax) + movl $0x78, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x53, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - andq $0xffff, %rax # imm = 0xFFFF - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - xorq %rax, %rax - decq %rax jmp leaq , %rax movl $0x79, %ebx @@ -368,16 +310,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - andq $0xffff, %rax # imm = 0xFFFF - xorq $0xffff, %rax # imm = 0xFFFF - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x7fff, %eax # imm = 0x7FFF jmp leaq , %rax movl $0x7a, %ebx @@ -392,13 +324,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x7fff, %rax # imm = 0x7FFF - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x8000, %rbx # imm = 0x8000 jmp leaq , %rax movl $0x7b, %ebx @@ -413,39 +338,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x8000, %rbx # imm = 0x8000 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movq %rbx, %rax - andq $0xffff, %rax # imm = 0xFFFF jmp leaq , %rax - movl $0x7c, %r12d - movl %r12d, (%rax) + movl $0x7c, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x5d, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - andq $0xffff, %rax # imm = 0xFFFF - xorq $0x8000, %rax # imm = 0x8000 - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x12345, %eax # imm = 0x12345 - movswq %ax, %rax jmp leaq , %rax movl $0x7d, %ebx @@ -460,13 +366,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x2345, %rax # imm = 0x2345 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2a, %rax jmp leaq , %rax movl $0x7e, %ebx @@ -481,14 +380,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movslq %eax, %rax - cmpq $-0x2a, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xffff, %ebx # imm = 0xFFFF jmp leaq , %rax movl $0x7f, %ebx @@ -503,36 +394,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %ebx, %eax - xorq $0xffff, %rax # imm = 0xFFFF - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x80, %r12d - movl %r12d, (%rax) + movl $0x80, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x6e, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $0xffff, %rbx # imm = 0xFFFF - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xffffffff, %ebx # imm = 0xFFFFFFFF jmp leaq , %rax movl $0x81, %ebx @@ -547,38 +423,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rbx, %rax - cmpq %r11, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq 0x1(%rbx), %rax jmp leaq , %rax - movl $0x82, %r12d - movl %r12d, (%rax) + movl $0x82, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x76, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - xorq %rax, %rax - decq %rax jmp leaq , %rax movl $0x83, %ebx @@ -593,15 +451,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x7fffffff, %eax # imm = 0x7FFFFFFF jmp leaq , %rax movl $0x84, %ebx @@ -616,13 +465,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x80000000, %rbx # imm = 0x80000000 jmp leaq , %rax movl $0x85, %ebx @@ -637,12 +479,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x80000000, %rbx # imm = 0x80000000 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rax movl $0x86, %r12d @@ -657,35 +493,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x80000000, %rbx # imm = 0x80000000 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax jmp leaq , %rax - movl $0x87, %r12d - movl %r12d, (%rax) + movl $0x87, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x86, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl $0x80000000, %r11d # imm = 0x80000000 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rbx jmp leaq , %rax movl $0x88, %ebx @@ -700,55 +521,34 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x1, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - incq %rbx jmp leaq , %rax - movl $0x8c, %r12d - movl %r12d, (%rax) + movl $0x8c, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x8e, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - testq %rbx, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq -0x1(%rbx), %rax jmp leaq , %rax - movl $0x8d, %r12d - movl %r12d, (%rax) + movl $0x8d, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x90, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x1, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $0x7fffffffffffffff, %rax # imm = 0x7FFFFFFFFFFFFFFF jmp leaq , %rax movl $0x8e, %ebx @@ -763,14 +563,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax jmp leaq , %rax movl $0x8f, %ebx @@ -785,14 +577,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - sarq $0x1, %rax - cmpq $-0x1, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 jmp leaq , %rax movl $0x90, %ebx @@ -807,15 +591,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - shrq $0x1, %rax - movabsq $0x4000000000000000, %r11 # imm = 0x4000000000000000 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax jmp leaq , %rax movl $0x91, %ebx @@ -830,16 +605,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - shrq $0x20, %rax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x12c, %rbx # imm = 0xFED4 - movsbq %bl, %r12 jmp leaq , %rax movl $0x92, %ebx @@ -854,81 +619,50 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x2c, %r12 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x96, %r13d - movl %r13d, (%rax) + movl $0x96, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xa9, %edx - movq %r13, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x2c, %r12 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - andq $0xff, %rbx jmp leaq , %rax - movl $0x97, %r12d - movl %r12d, (%rax) + movl $0x97, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xaa, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movq %rbx, %rax - andq $0xff, %rax - xorq $0xd4, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x98, %r12d - movl %r12d, (%rax) + movl $0x98, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xaf, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movq %rbx, %rax - andq $0xff, %rax - cmpq $0xd4, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x12345, %eax # imm = 0x12345 - movswq %ax, %rbx jmp leaq , %rax movl $0x99, %ebx @@ -943,34 +677,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x2345, %rbx # imm = 0x2345 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x9a, %r12d - movl %r12d, (%rax) + movl $0x9a, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xb5, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $0x2345, %rbx # imm = 0x2345 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1ffff, %eax # imm = 0x1FFFF - movswq %ax, %rbx jmp leaq , %rax movl $0x9b, %ebx @@ -985,34 +706,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x1, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x9c, %r12d - movl %r12d, (%rax) + movl $0x9c, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xba, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x1, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xffffffff, %ebx # imm = 0xFFFFFFFF - movl $0x1, %r12d jmp leaq , %rax movl $0x9d, %ebx @@ -1027,35 +735,20 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq %r12, %rbx - seta %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movslq %ebx, %rax - movslq %r12d, %rcx jmp leaq , %rax - movl $0xa0, %r13d - movl %r13d, (%rax) + movl $0xa0, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0xc2, %edx - movq %r13, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq %rcx, %rax - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1, %eax jmp leaq , %rax movl $0xa1, %ebx @@ -1070,15 +763,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - shlq $0x1e, %rax - movslq %eax, %rax - cmpq $0x40000000, %rax # imm = 0x40000000 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1, %eax jmp leaq , %rax movl $0xaa, %ebx @@ -1093,16 +777,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - shlq $0x1f, %rax - movl %eax, %eax - movl $0x80000000, %r11d # imm = 0x80000000 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rax jmp leaq , %rax movl $0xab, %ebx @@ -1117,13 +791,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x1, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xffffffff, %eax # imm = 0xFFFFFFFF jmp leaq , %rax movl $0xac, %ebx @@ -1138,17 +805,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq , %rax - movslq (%rax), %rax - testq %rax, %rax - jne jmp leaq , %rax movl $0xad, %ebx @@ -1163,23 +819,5 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq - leaq , %rax - movslq (%rax), %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x160, %rsp # imm = 0x160 - popq %rbp - retq + jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/integer_literal_suffix.aarch64.asm b/tests/snapshots/asm/integer_literal_suffix.aarch64.asm index 8d1f57a44..d57ac8f70 100644 --- a/tests/snapshots/asm/integer_literal_suffix.aarch64.asm +++ b/tests/snapshots/asm/integer_literal_suffix.aarch64.asm @@ -10,90 +10,20 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xf, lsl #32 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xf, lsl #32 - cmp x0, x17 - b.eq + mov x1, #0x1 // =1 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0xe // =14 + ret + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x24 // =36 - mov x1, #0x1 // =1 - lsl x0, x1, x0 - sub x0, x0, #0x1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xf, lsl #32 - cmp x0, x17 - b.eq mov x0, #0xc // =12 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x6789 // =26505 - movk x0, #0x2345, lsl #16 - movk x0, #0x1, lsl #32 - add x0, x0, #0x1 - mov x17, #0x678a // =26506 - movk x17, #0x2345, lsl #16 - movk x17, #0x1, lsl #32 - cmp x0, x17 - b.eq mov x0, #0xd // =13 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x2, eq - cbz x2, - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x2, eq - cbz x2, - mov x0, #0xe // =14 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0xf // =15 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - add x0, x0, #0x1 - cmp x0, #0x0 - b.eq mov x0, #0x10 // =16 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b diff --git a/tests/snapshots/asm/integer_literal_suffix.x64.asm b/tests/snapshots/asm/integer_literal_suffix.x64.asm index 9701c3d5b..05dc882bc 100644 --- a/tests/snapshots/asm/integer_literal_suffix.x64.asm +++ b/tests/snapshots/asm/integer_literal_suffix.x64.asm @@ -11,76 +11,23 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movabsq $0xfffffffff, %rax # imm = 0xFFFFFFFFF - movabsq $0xfffffffff, %r11 # imm = 0xFFFFFFFFF - cmpq %r11, %rax + movl $0x1, %ecx + xorq %rcx, %rcx + testq %rcx, %rcx je + movl $0xe, %eax + retq + xorq %rax, %rax + retq movl $0xb, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x24, %eax - movl $0x1, %ecx - movq %rax, %r10 - movq %rcx, %rax - pushq %rcx - movq %r10, %rcx - shlq %cl, %rax - popq %rcx - decq %rax - movabsq $0xfffffffff, %r11 # imm = 0xFFFFFFFFF - cmpq %r11, %rax - je movl $0xc, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $0x123456789, %rax # imm = 0x123456789 - incq %rax - movabsq $0x12345678a, %r11 # imm = 0x12345678A - cmpq %r11, %rax - je movl $0xd, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $-0x1, %rax - cmpq $-0x1, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rax, %rdx - cmpq %r11, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - movl $0xe, %eax - addq $0x40, %rsp - popq %rbp - retq - cmpq $-0x1, %rax - je movl $0xf, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $-0x1, %rax - incq %rax - testq %rax, %rax - je movl $0x10, %eax - addq $0x40, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq - jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/integer_negate_shift_overflow.aarch64.asm b/tests/snapshots/asm/integer_negate_shift_overflow.aarch64.asm index 7ea75cef6..8d785ee9e 100644 --- a/tests/snapshots/asm/integer_negate_shift_overflow.aarch64.asm +++ b/tests/snapshots/asm/integer_negate_shift_overflow.aarch64.asm @@ -10,105 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0x80000000 // =2147483648 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0x80000000 // =2147483648 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x80000000 // =2147483648 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - mov x17, #0x80000000 // =2147483648 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0x7fff, lsl #16 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - sxtw x0, w0 - mov x17, #0x1 // =1 - movk x17, #0x8000, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x8000 // =32768 - lsl x0, x0, #16 - sxtw x0, w0 - asr x0, x0, #16 - mov x17, #0x8000 // =32768 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - b.eq mov x0, #0x7 // =7 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/integer_negate_shift_overflow.x64.asm b/tests/snapshots/asm/integer_negate_shift_overflow.x64.asm index 02c12b119..a7ce25eb4 100644 --- a/tests/snapshots/asm/integer_negate_shift_overflow.x64.asm +++ b/tests/snapshots/asm/integer_negate_shift_overflow.x64.asm @@ -11,70 +11,20 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movabsq $-0x80000000, %rax # imm = 0x80000000 - cmpq $-0x80000000, %rax # imm = 0x80000000 - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq - jmp movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq - movabsq $-0x80000000, %rax # imm = 0x80000000 - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq $-0x80000000, %rax # imm = 0x80000000 - je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x7fffffff, %eax # imm = 0x7FFFFFFF - imulq $-0x1, %rax, %rax - movslq %eax, %rax - cmpq $-0x7fffffff, %rax # imm = 0x80000001 - je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x8000, %eax # imm = 0x8000 - shlq $0x10, %rax - movslq %eax, %rax - sarq $0x10, %rax - cmpq $-0x8000, %rax # imm = 0x8000 - je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq - xorq %rax, %rax - imulq $-0x1, %rax, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x1, %eax - imulq $-0x1, %rax, %rax - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - je movl $0x7, %eax - addq $0x40, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/integer_ops_exhaustive.aarch64.asm b/tests/snapshots/asm/integer_ops_exhaustive.aarch64.asm index d64f4407f..f571a947b 100644 --- a/tests/snapshots/asm/integer_ops_exhaustive.aarch64.asm +++ b/tests/snapshots/asm/integer_ops_exhaustive.aarch64.asm @@ -10,21 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x130 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] - mov x20, #0xfffe // =65534 - movk x20, #0xffff, lsl #16 - mov x21, #0x1 // =1 - cmp x20, x21 - cset x0, hi - cmp x0, #0x0 - b.ne - b + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret b adrp x0, add x0, x0, @@ -33,19 +25,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, lo - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -54,19 +37,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, hs - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -75,19 +49,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, ls - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -96,19 +61,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, ne - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -117,27 +73,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, eq - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xfffe // =65534 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -145,19 +84,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, lt - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -166,19 +96,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, gt - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -187,19 +108,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, le - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -208,25 +120,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, ge - cmp x0, #0x0 - b.ne - b - mov x20, #0xfffe // =65534 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -234,19 +131,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, hi - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -255,19 +143,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, hs - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -276,25 +155,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, lo - cmp x0, #0x0 - b.ne - b - mov x20, #0xfffe // =65534 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x0, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -302,19 +166,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x0, x20 - cset x0, gt - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -323,22 +178,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, #0x0 - cset x0, lt - cmp x0, #0x0 - b.ne - b - mov x20, #0xfe // =254 - mov x21, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -346,19 +189,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, gt - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -367,25 +201,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, lt - cmp x0, #0x0 - b.ne - b - mov x20, #0xfffe // =65534 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -393,19 +212,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, x21 - cset x0, lt - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -414,22 +224,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x21, x20 - cset x0, gt - cmp x0, #0x0 - b.ne - b - mov x0, #0x64 // =100 - add x20, x0, #0x5 - b adrp x0, add x0, x0, adrp x1, @@ -437,26 +235,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0x69 // =105 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 - sub x20, x0, #0xa - b adrp x0, add x0, x0, adrp x1, @@ -464,26 +246,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0x5f // =95 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 - lsl x20, x0, #1 - b adrp x0, add x0, x0, adrp x1, @@ -491,27 +257,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0xbe // =190 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 - mov x1, #0x5 // =5 - udiv x20, x0, x1 - b adrp x0, add x0, x0, adrp x1, @@ -519,28 +268,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0x26 // =38 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 - mov x1, #0x7 // =7 - udiv x17, x0, x1 - msub x0, x17, x1, x0 - b adrp x0, add x0, x0, adrp x1, @@ -548,27 +279,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w0 - mov x17, #0x3 // =3 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x1 // =1 - sub x0, x0, #0x2 - mov w0, w0 - b adrp x0, add x0, x0, adrp x1, @@ -576,25 +290,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x3e8 // =1000 - add x20, x0, #0x19f - b adrp x0, add x0, x0, adrp x1, @@ -602,22 +301,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x20, #0x587 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x17, #0x3 // =3 - mul x20, x20, x17 - b adrp x0, add x0, x0, adrp x1, @@ -625,23 +312,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov x17, #0x1095 // =4245 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x5 // =5 - udiv x0, x20, x0 - b adrp x0, add x0, x0, adrp x1, @@ -649,33 +323,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x0, #0x351 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xff00 // =65280 - movk x0, #0xff00, lsl #16 - mov x17, #0xf0f // =3855 - movk x17, #0xf0f, lsl #16 - and x1, x0, x17 - mov x17, #0xf000 // =61440 - movk x17, #0xf, lsl #16 - orr x20, x0, x17 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - eor x21, x0, x17 - mvn x0, x0 - mov w22, w0 - b adrp x0, add x0, x0, adrp x1, @@ -683,24 +334,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w1 - mov x17, #0xf00 // =3840 - movk x17, #0xf00, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -709,22 +346,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0xff00 // =65280 - movk x17, #0xff0f, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -733,24 +358,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w21 - mov x17, #0xff // =255 - movk x17, #0xff, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -759,29 +370,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w22 - mov x17, #0xff // =255 - movk x17, #0xff, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x5678 // =22136 - movk x0, #0x1234, lsl #16 - lsl x0, x0, #4 - mov w0, w0 - b adrp x0, add x0, x0, adrp x1, @@ -789,28 +381,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w0 - mov x17, #0x6780 // =26496 - movk x17, #0x2345, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x1 // =1 - lsl x0, x0, #31 - mov w0, w0 - b adrp x0, add x0, x0, adrp x1, @@ -818,23 +392,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w0 - mov x17, #0x80000000 // =2147483648 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -842,27 +403,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - lsl x0, x0, #63 - mov x17, #-0x8000000000000000 // =-9223372036854775808 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x1 // =1 - b adrp x0, add x0, x0, adrp x1, @@ -870,20 +414,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - cmp x0, x21 - cset x0, hi - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -892,24 +426,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - sxtw x0, w21 - cmp x20, x0 - cset x0, lt - cmp x0, #0x0 - b.ne - b - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - add x20, x0, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -917,25 +437,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w20 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 - add x0, x0, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -943,23 +448,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xfe // =254 - add x20, x0, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -967,28 +459,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov x17, #0xff // =255 - and x0, x20, x17 - mov x17, #0xff // =255 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x17, #0xff // =255 - and x0, x20, x17 - add x0, x0, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -996,27 +470,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov x17, #0xff // =255 - and x0, x0, x17 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - add x20, x0, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -1024,25 +481,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - add x0, x20, #0x1 - b adrp x0, add x0, x0, adrp x1, @@ -1050,19 +492,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -1071,16 +504,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1088,16 +516,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1105,16 +528,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1122,16 +540,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1139,16 +552,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1156,16 +564,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1173,16 +576,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b - b adrp x0, add x0, x0, adrp x1, @@ -1190,23 +588,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b - b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, adrp x1, @@ -1214,11 +599,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b diff --git a/tests/snapshots/asm/integer_ops_exhaustive.x64.asm b/tests/snapshots/asm/integer_ops_exhaustive.x64.asm index 50a0286ae..11bc0e094 100644 --- a/tests/snapshots/asm/integer_ops_exhaustive.x64.asm +++ b/tests/snapshots/asm/integer_ops_exhaustive.x64.asm @@ -13,18 +13,9 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x120, %rsp # imm = 0x120 - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movl $0xfffffffe, %ebx # imm = 0xFFFFFFFE - movl $0x1, %r12d - cmpq %r12, %rbx - seta %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp + xorq %rax, %rax + popq %rbp + retq jmp leaq , %rdi leaq , %rsi @@ -32,19 +23,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setb %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -52,19 +33,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setae %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -72,19 +43,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setbe %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -92,19 +53,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setne %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -112,44 +63,18 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2, %rbx - movl $0x1, %r12d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -157,19 +82,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setg %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -177,19 +92,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setle %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -197,41 +102,18 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setge %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2, %rbx - movl $0x1, %r12d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - seta %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -239,19 +121,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setae %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -259,41 +131,18 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setb %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2, %rbx - movl $0x1, %eax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %rax - setg %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -301,41 +150,18 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - testq %rbx, %rbx - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xfe, %ebx - movl $0x1, %r12d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setg %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -343,41 +169,18 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2, %rbx - movl $0x1, %r12d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %r12, %rbx - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -385,284 +188,99 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq %rbx, %r12 - setg %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x64, %eax - leaq 0x5(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - xorq $0x69, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax - leaq -0xa(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - xorq $0x5f, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax - movq %rax, %rbx - shlq $0x1, %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - xorq $0xbe, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax - movl $0x5, %ecx - pushq %rax - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rax, %rbx - popq %rdx - popq %rax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - xorq $0x26, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax - movl $0x7, %ecx - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rdx, %rax - popq %rdx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %eax, %eax - xorq $0x3, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1, %eax - subq $0x2, %rax - movl %eax, %eax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x3e8, %eax # imm = 0x3E8 - leaq 0x19f(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq $0x587, %rbx # imm = 0x587 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq (%rbx,%rbx,2), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq $0x1095, %rbx # imm = 0x1095 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x5, %eax - movq %rax, %r10 - pushq %rdx - movq %rbx, %rax - xorq %rdx, %rdx - divq %r10 - popq %rdx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq $0x351, %rax # imm = 0x351 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xff00ff00, %eax # imm = 0xFF00FF00 - movq %rax, %rcx - andq $0xf0f0f0f, %rcx # imm = 0xF0F0F0F - movq %rax, %rbx - orq $0xff000, %rbx # imm = 0xFF000 - movl $0xffffffff, %r12d # imm = 0xFFFFFFFF - xorq %rax, %r12 - xorq $-0x1, %rax - movl %eax, %r13d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ecx, %eax - xorq $0xf000f00, %rax # imm = 0xF000F00 - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -670,21 +288,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - movl $0xff0fff00, %r11d # imm = 0xFF0FFF00 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -692,22 +298,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %r12d, %eax - xorq $0xff00ff, %rax # imm = 0xFF00FF - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -715,119 +308,45 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %r13d, %eax - xorq $0xff00ff, %rax # imm = 0xFF00FF - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x12345678, %eax # imm = 0x12345678 - shlq $0x4, %rax - movl %eax, %eax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %eax, %eax - xorq $0x23456780, %rax # imm = 0x23456780 - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1, %eax - shlq $0x1f, %rax - movl %eax, %eax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %eax, %eax - movl $0x80000000, %r11d # imm = 0x80000000 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x1, %eax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - shlq $0x3f, %rax - movabsq $-0x8000000000000000, %r11 # imm = 0x8000000000000000 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rbx - movl $0x1, %r12d - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - cmpq %r12, %rax - seta %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -835,160 +354,63 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movslq %r12d, %rax - cmpq %rax, %rbx - setl %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xfffffffe, %eax # imm = 0xFFFFFFFE - leaq 0x1(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %ebx, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax - incq %rax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xfe, %eax - leaq 0x1(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - movq %rbx, %rax - andq $0xff, %rax - xorq $0xff, %rax - movl %eax, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movq %rbx, %rax - andq $0xff, %rax - incq %rax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - andq $0xff, %rax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x2, %rax - leaq 0x1(%rax), %rbx - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - cmpq $-0x1, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq 0x1(%rbx), %rax - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rdi leaq , %rsi @@ -996,137 +418,87 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp jmp - jmp leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp - jmp - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 - popq %rbp - retq leaq , %rdi leaq , %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 popq %rbp retq jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/integer_suffixes.aarch64.asm b/tests/snapshots/asm/integer_suffixes.aarch64.asm index d7eaceb62..1a7ffa997 100644 --- a/tests/snapshots/asm/integer_suffixes.aarch64.asm +++ b/tests/snapshots/asm/integer_suffixes.aarch64.asm @@ -10,122 +10,35 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - mov x0, #0x1 // =1 - mov x1, #0x100000000 // =4294967296 - mov x2, #0x2 // =2 - mov x3, #0x3 // =3 - mov x4, #0x4 // =4 - mov x5, #0x5 // =5 - mov x6, #0x6 // =6 - mov x7, #0x7 // =7 - mov x8, #0x8 // =8 - mov x9, #0x9 // =9 - mov x10, #0xa // =10 - mov x11, #0xff // =255 - mov x12, #0xcafe // =51966 - mov x13, #0x1000 // =4096 - movk x13, #0xd4a5, lsl #16 - movk x13, #0xe8, lsl #32 - cmp x0, #0x1 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x2, #0x2 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x3, #0x3 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x4, #0x4 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x5, #0x5 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x6, #0x6 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x7, #0x7 - b.eq mov x0, #0x7 // =7 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x8, #0x8 - b.eq mov x0, #0x8 // =8 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x9, #0x9 - b.eq mov x0, #0x9 // =9 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x10, #0xa - b.eq mov x0, #0xa // =10 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - cmp x11, #0xff - b.eq mov x0, #0xb // =11 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xcafe // =51966 - cmp x12, x17 - b.eq mov x0, #0xc // =12 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x1000 // =4096 - movk x17, #0xd4a5, lsl #16 - movk x17, #0xe8, lsl #32 - cmp x13, x17 - b.eq + ret mov x0, #0xd // =13 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0x100000000 // =4294967296 - cmp x1, x17 - b.eq mov x0, #0xe // =14 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xa // =10 - cmp x0, #0xa - b.eq mov x0, #0xf // =15 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/integer_suffixes.x64.asm b/tests/snapshots/asm/integer_suffixes.x64.asm index f5dac1b03..52614a851 100644 --- a/tests/snapshots/asm/integer_suffixes.x64.asm +++ b/tests/snapshots/asm/integer_suffixes.x64.asm @@ -11,208 +11,36 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0xd0, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movq %r14, 0x18(%rsp) - movq %r15, 0x20(%rsp) - movl $0x1, %eax - movabsq $0x100000000, %rcx # imm = 0x100000000 - movl $0x2, %edx - movl $0x3, %esi - movl $0x4, %edi - movl $0x5, %r8d - movl $0x6, %r9d - movl $0x7, %ebx - movl $0x8, %r12d - movl $0x9, %r13d - movl $0xa, %r14d - movl $0xff, %r15d - movl $0xcafe, %r10d # imm = 0xCAFE - movq %r10, 0x48(%rsp) - movabsq $0xe8d4a51000, %r10 # imm = 0xE8D4A51000 - movq %r10, 0x40(%rsp) - cmpq $0x1, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x2, %rdx - je + retq movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x3, %rsi - je + retq movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x4, %rdi - je + retq movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x5, %r8 - je + retq movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x6, %r9 - je + retq movl $0x6, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x7, %rbx - je + retq movl $0x7, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x8, %r12 - je + retq movl $0x8, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0x9, %r13 - je + retq movl $0x9, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0xa, %r14 - je + retq movl $0xa, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - cmpq $0xff, %r15 - je + retq movl $0xb, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - movq 0x48(%rsp), %rax - cmpq $0xcafe, %rax # imm = 0xCAFE - je + retq movl $0xc, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - movq 0x40(%rsp), %rax - movabsq $0xe8d4a51000, %r11 # imm = 0xE8D4A51000 - cmpq %r11, %rax - je + retq movl $0xd, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - movabsq $0x100000000, %r11 # imm = 0x100000000 - movq %rcx, %rax - cmpq %r11, %rcx - je + retq movl $0xe, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp retq - movl $0xa, %eax - cmpq $0xa, %rax - je movl $0xf, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp retq - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0xd0, %rsp - popq %rbp - retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/inttypes_header.aarch64.asm b/tests/snapshots/asm/inttypes_header.aarch64.asm index a14887cc2..e5d713e90 100644 --- a/tests/snapshots/asm/inttypes_header.aarch64.asm +++ b/tests/snapshots/asm/inttypes_header.aarch64.asm @@ -20,66 +20,6 @@ Disassembly of section .text: stur x0, [x29, #-0x20] mov x0, #0x4 // =4 stur x0, [x29, #-0x40] - b - mov x0, #0xb // =11 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xc // =12 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xd // =13 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xe // =14 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xf // =15 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x10 // =16 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x11 // =17 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x12 // =18 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x13 // =19 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x14 // =20 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x15 // =21 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x16 // =22 - add sp, sp, #0x150 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrb w1, [x0] @@ -371,3 +311,51 @@ Disassembly of section .text: b b b + mov x0, #0xb // =11 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xf // =15 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10 // =16 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x11 // =17 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x12 // =18 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x13 // =19 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x14 // =20 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x15 // =21 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x16 // =22 + add sp, sp, #0x150 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/inttypes_header.x64.asm b/tests/snapshots/asm/inttypes_header.x64.asm index 5f6c13932..12dba84bc 100644 --- a/tests/snapshots/asm/inttypes_header.x64.asm +++ b/tests/snapshots/asm/inttypes_header.x64.asm @@ -18,66 +18,6 @@ Disassembly of section .text: movq %rax, -0x20(%rbp) movl $0x4, %eax movq %rax, -0x40(%rbp) - jmp - movl $0xb, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0xc, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0xd, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0xe, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0xf, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x10, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x11, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x12, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x13, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x14, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x15, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq - jmp - movl $0x16, %eax - addq $0x150, %rsp # imm = 0x150 - popq %rbp - retq leaq , %rax movsbq (%rax), %rcx cmpq $0x6c, %rcx @@ -369,3 +309,52 @@ Disassembly of section .text: jmp jmp jmp + movl $0xb, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0xc, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0xd, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0xe, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0xf, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x10, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x11, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x12, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x13, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x14, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x15, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + movl $0x16, %eax + addq $0x150, %rsp # imm = 0x150 + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ioctl_fionread_pipe.aarch64.asm b/tests/snapshots/asm/ioctl_fionread_pipe.aarch64.asm index f207bd9d4..eca5210c1 100644 --- a/tests/snapshots/asm/ioctl_fionread_pipe.aarch64.asm +++ b/tests/snapshots/asm/ioctl_fionread_pipe.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x0, #0x0 // =0 stur w0, [x29, #-0x10] sub x0, x29, #0x8 @@ -23,10 +22,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret sub x0, x29, #0x8 ldrsw x0, [x0, #0x4] @@ -38,10 +36,9 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret sub x0, x29, #0x8 ldrsw x0, [x0] @@ -52,19 +49,17 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret ldursw x0, [x29, #-0x10] cmp x0, #0x5 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret sub x0, x29, #0x8 mov x20, #0x0 // =0 @@ -76,8 +71,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret diff --git a/tests/snapshots/asm/ir_translation_while.aarch64.asm b/tests/snapshots/asm/ir_translation_while.aarch64.asm index c1a834ff0..4d688f0f0 100644 --- a/tests/snapshots/asm/ir_translation_while.aarch64.asm +++ b/tests/snapshots/asm/ir_translation_while.aarch64.asm @@ -10,8 +10,7 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b - mov x0, #0x1 // =1 - ret mov x0, #0x0 // =0 ret + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/ir_translation_while.x64.asm b/tests/snapshots/asm/ir_translation_while.x64.asm index d12c3a36c..c148e5300 100644 --- a/tests/snapshots/asm/ir_translation_while.x64.asm +++ b/tests/snapshots/asm/ir_translation_while.x64.asm @@ -11,8 +11,8 @@ Disassembly of section .text: ud2
: - jmp - movl $0x1, %eax - retq xorq %rax, %rax retq + movl $0x1, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/kr_old_style_def.aarch64.asm b/tests/snapshots/asm/kr_old_style_def.aarch64.asm index d0590e373..ef087ee79 100644 --- a/tests/snapshots/asm/kr_old_style_def.aarch64.asm +++ b/tests/snapshots/asm/kr_old_style_def.aarch64.asm @@ -22,29 +22,6 @@ Disassembly of section .text: ret
: - mov x0, #0x1 // =1 - mov x1, #0x0 // =0 - sxtw x2, w0 - sub x0, x2, x0 - mov x17, #0xff // =255 - and x1, x1, x17 - add x0, x0, x1 - cmp x0, #0x0 - b.eq - mov x0, #0x1 // =1 - ret - mov x0, #0xa // =10 - mov x1, #0x5 // =5 - mov x2, #0x3 // =3 - sxtw x0, w0 - sub x0, x0, x2 - mov x17, #0xff // =255 - and x1, x1, x17 - add x0, x0, x1 - cmp x0, #0xc - b.eq - mov x0, #0x2 // =2 - ret adrp x0, add x0, x0, ldrb w0, [x0] @@ -54,3 +31,7 @@ Disassembly of section .text: ret mov x0, #0x0 // =0 ret + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret diff --git a/tests/snapshots/asm/kr_old_style_def.x64.asm b/tests/snapshots/asm/kr_old_style_def.x64.asm index 14f0dd56f..020a440a5 100644 --- a/tests/snapshots/asm/kr_old_style_def.x64.asm +++ b/tests/snapshots/asm/kr_old_style_def.x64.asm @@ -23,29 +23,6 @@ Disassembly of section .text: retq
: - movl $0x1, %eax - xorq %rcx, %rcx - movslq %eax, %rdx - movsbq %cl, %rcx - movq %rax, %r10 - movq %rdx, %rax - subq %r10, %rax - addq %rcx, %rax - testq %rax, %rax - je - movl $0x1, %eax - retq - movl $0xa, %eax - movl $0x5, %ecx - movl $0x3, %edx - movslq %eax, %rax - movsbq %cl, %rcx - subq %rdx, %rax - addq %rcx, %rax - cmpq $0xc, %rax - je - movl $0x2, %eax - retq leaq , %rax movsbq (%rax), %rax cmpq $0x5a, %rax @@ -54,5 +31,7 @@ Disassembly of section .text: retq xorq %rax, %rax retq - addb %al, (%rax) - addb %al, 0x41(%rdx) + movl $0x1, %eax + retq + movl $0x2, %eax + retq diff --git a/tests/snapshots/asm/label_addr_array_init.aarch64.asm b/tests/snapshots/asm/label_addr_array_init.aarch64.asm index 8d5081aa9..ca8deea8a 100644 --- a/tests/snapshots/asm/label_addr_array_init.aarch64.asm +++ b/tests/snapshots/asm/label_addr_array_init.aarch64.asm @@ -15,20 +15,20 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x20 stur w0, [x29, #0x10] - adr x0, - sub x1, x29, #0x18 - str x0, [x1] - adr x0, - sub x1, x29, #0x18 - str x0, [x1, #0x8] - adr x0, + adr x1, + sub x2, x29, #0x18 + str x1, [x2] + adr x1, + sub x2, x29, #0x18 + str x1, [x2, #0x8] + adr x1, + sub x2, x29, #0x18 + str x1, [x2, #0x10] + mov x1, #0x0 // =0 + stur w1, [x29, #-0x20] sub x1, x29, #0x18 - str x0, [x1, #0x10] - mov x0, #0x0 // =0 - stur w0, [x29, #-0x20] - sub x0, x29, #0x18 - ldursw x1, [x29, #0x10] - ldr x0, [x0, x1, lsl #3] + sxtw x0, w0 + ldr x0, [x1, x0, lsl #3] br x0 mov x0, #0xa // =10 stur w0, [x29, #-0x20] @@ -52,13 +52,21 @@ Disassembly of section .text: stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x18] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x10] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + mov x1, #0x1 // =1 + strb w1, [x0, #0x18] + stur x1, [x29, #-0x10] mov x1, #0x0 // =0 - adr x2, - str x2, [x0] - adr x2, - str x2, [x0, #0x8] - adr x2, - str x2, [x0, #0x10] stur w1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] @@ -85,13 +93,21 @@ Disassembly of section .text: stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x18] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x10] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + mov x1, #0x1 // =1 + strb w1, [x0, #0x18] + stur x1, [x29, #-0x10] mov x1, #0x0 // =0 - adr x2, - str x2, [x0] - adr x2, - str x2, [x0, #0x8] - adr x2, - str x2, [x0, #0x10] stur w1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] diff --git a/tests/snapshots/asm/label_addr_array_init.x64.asm b/tests/snapshots/asm/label_addr_array_init.x64.asm index 0930f8ae9..011e95a29 100644 --- a/tests/snapshots/asm/label_addr_array_init.x64.asm +++ b/tests/snapshots/asm/label_addr_array_init.x64.asm @@ -31,7 +31,7 @@ Disassembly of section .text: xorq %rax, %rax movl %eax, -0x20(%rbp) leaq -0x18(%rbp), %rax - movslq 0x10(%rbp), %rcx + movslq %edi, %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movl $0xa, %eax @@ -60,13 +60,22 @@ Disassembly of section .text: subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x18(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x10(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + movl $0x1, %ecx + movb %cl, 0x18(%rax) + movq %rcx, -0x10(%rbp) xorq %rcx, %rcx - leaq , %rdx # - movq %rdx, (%rax) - leaq , %rdx # - movq %rdx, 0x8(%rax) - leaq , %rdx # - movq %rdx, 0x10(%rax) movl %ecx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax @@ -97,13 +106,22 @@ Disassembly of section .text: subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x18(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x10(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + movl $0x1, %ecx + movb %cl, 0x18(%rax) + movq %rcx, -0x10(%rbp) xorq %rcx, %rcx - leaq , %rdx # - movq %rdx, (%rax) - leaq , %rdx # - movq %rdx, 0x8(%rax) - leaq , %rdx # - movq %rdx, 0x10(%rax) movl %ecx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax @@ -200,3 +218,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/large_int_literal_auto_promotes.aarch64.asm b/tests/snapshots/asm/large_int_literal_auto_promotes.aarch64.asm index 9ec2c7c97..725fb7612 100644 --- a/tests/snapshots/asm/large_int_literal_auto_promotes.aarch64.asm +++ b/tests/snapshots/asm/large_int_literal_auto_promotes.aarch64.asm @@ -10,66 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0x7fff, lsl #48 - mov x1, #-0x8000000000000000 // =-9223372036854775808 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x17, #-0x8000000000000000 // =-9223372036854775808 - cmp x1, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0x7fff, lsl #48 - mov x17, #0xfffe // =65534 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #-0x8000000000000000 // =-9223372036854775808 - mov x17, #-0x8000000000000000 // =-9223372036854775808 - cmp x0, x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xf201 // =61953 - movk x0, #0x2a05, lsl #16 - movk x0, #0x1, lsl #32 - mov x17, #0xf201 // =61953 - movk x17, #0x2a05, lsl #16 - movk x17, #0x1, lsl #32 - cmp x0, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/large_int_literal_auto_promotes.x64.asm b/tests/snapshots/asm/large_int_literal_auto_promotes.x64.asm index c84b888e1..9a2cdc51a 100644 --- a/tests/snapshots/asm/large_int_literal_auto_promotes.x64.asm +++ b/tests/snapshots/asm/large_int_literal_auto_promotes.x64.asm @@ -11,53 +11,16 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movabsq $0x7fffffffffffffff, %rax # imm = 0x7FFFFFFFFFFFFFFF - movabsq $-0x8000000000000000, %rcx # imm = 0x8000000000000000 - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x8000000000000000, %r11 # imm = 0x8000000000000000 - movq %rcx, %rax - cmpq %r11, %rcx - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $0x7ffffffffffffffe, %rax # imm = 0x7FFFFFFFFFFFFFFE - movabsq $0x7ffffffffffffffe, %r11 # imm = 0x7FFFFFFFFFFFFFFE - cmpq %r11, %rax - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 - movabsq $-0x8000000000000000, %r11 # imm = 0x8000000000000000 - cmpq %r11, %rax - je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $0x12a05f201, %rax # imm = 0x12A05F201 - movabsq $0x12a05f201, %r11 # imm = 0x12A05F201 - cmpq %r11, %rax - je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/large_stack_frame.aarch64.asm b/tests/snapshots/asm/large_stack_frame.aarch64.asm index 319dcf7ab..897ef6d1c 100644 --- a/tests/snapshots/asm/large_stack_frame.aarch64.asm +++ b/tests/snapshots/asm/large_stack_frame.aarch64.asm @@ -10,22 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x1, lsl #12 // =0x1000 - sub sp, sp, #0x2c0 add x0, x0, #0x1 add x0, x0, #0x1 sxtw x0, w0 - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x2c0 - ldp x29, x30, [sp], #0x10 ret
: - mov x0, #0x28 // =40 - add x0, x0, #0x1 - add x0, x0, #0x1 - sxtw x0, w0 - sxtw x0, w0 + mov x0, #0x2a // =42 ret diff --git a/tests/snapshots/asm/large_stack_frame.x64.asm b/tests/snapshots/asm/large_stack_frame.x64.asm index 251f4d6ac..5e9358539 100644 --- a/tests/snapshots/asm/large_stack_frame.x64.asm +++ b/tests/snapshots/asm/large_stack_frame.x64.asm @@ -11,20 +11,13 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x12c0, %rsp # imm = 0x12C0 leaq 0x1(%rdi), %rax incq %rax movslq %eax, %rax - addq $0x12c0, %rsp # imm = 0x12C0 - popq %rbp retq
: - movl $0x28, %eax - incq %rax - incq %rax - movslq %eax, %rax - movslq %eax, %rax + movl $0x2a, %eax retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/large_struct_copy.aarch64.asm b/tests/snapshots/asm/large_struct_copy.aarch64.asm index d2735bac2..1bb59a05b 100644 --- a/tests/snapshots/asm/large_struct_copy.aarch64.asm +++ b/tests/snapshots/asm/large_struct_copy.aarch64.asm @@ -12,10 +12,8 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x490 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] + sub sp, sp, #0x480 + str x19, [sp] sub x0, x29, #0x210 mov x1, #0x64 // =100 str w1, [x0] @@ -59,29 +57,23 @@ Disassembly of section .text: mov x1, #0x320 // =800 str w1, [x0, #0x208] mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x28 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x210 + add x2, x2, #0x10 + add x3, x0, #0x3e8 + str w3, [x2, x0, lsl #2] + sub x2, x29, #0x210 + add x2, x2, #0xb4 + add x3, x0, #0x7d0 + str w3, [x2, x0, lsl #2] + sub x2, x29, #0x210 + add x2, x2, #0x158 + add x3, x0, #0xbb8 + str w3, [x2, x0, lsl #2] add x1, x0, #0x1 - b - sub x0, x29, #0x210 - add x0, x0, #0x10 - sxtw x2, w1 - add x3, x2, #0x3e8 - str w3, [x0, x2, lsl #2] - sub x0, x29, #0x210 - add x0, x0, #0xb4 - sxtw x2, w1 - add x3, x2, #0x7d0 - str w3, [x0, x2, lsl #2] - sub x0, x29, #0x210 - add x0, x0, #0x158 - sxtw x2, w1 - add x3, x2, #0xbb8 - str w3, [x0, x2, lsl #2] - b + sxtw x0, w1 + cmp x0, #0x28 + b.lt sub x0, x29, #0x420 mov x1, #0x7e // =126 mov x2, #0x20c // =524 @@ -232,66 +224,62 @@ Disassembly of section .text: ldrsw x0, [x0] cmp x0, #0x64 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x420 ldrsw x0, [x0, #0x4] cmp x0, #0xc8 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x420 ldrsw x0, [x0, #0x8] cmp x0, #0x12c cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x420 ldrsw x0, [x0, #0xc] cmp x0, #0x190 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x420 ldrsw x0, [x0, #0x1fc] cmp x0, #0x1f4 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x420 ldrsw x0, [x0, #0x200] cmp x0, #0x258 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x420 ldrsw x0, [x0, #0x204] cmp x0, #0x2bc cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x420 ldrsw x0, [x0, #0x208] cmp x0, #0x320 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x420 @@ -303,10 +291,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x420 @@ -318,10 +304,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x420 @@ -333,78 +317,62 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0x28 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 - b - sub x0, x29, #0x420 - add x0, x0, #0x10 - sxtw x1, w20 - ldrsw x0, [x0, x1, lsl #2] - add x1, x1, #0x3e8 - sxtw x1, w1 - cmp x0, x1 - b.eq + mov x1, #0x0 // =0 b + sub x2, x29, #0x420 + add x2, x2, #0x10 + ldrsw x2, [x2, x0, lsl #2] + add x3, x0, #0x3e8 + sxtw x3, w3 + cmp x2, x3 + b.ne + sub x2, x29, #0x420 + add x2, x2, #0xb4 + ldrsw x2, [x2, x0, lsl #2] + add x3, x0, #0x7d0 + sxtw x3, w3 + cmp x2, x3 + b.ne + sub x2, x29, #0x420 + add x2, x2, #0x158 + ldrsw x2, [x2, x0, lsl #2] + add x3, x0, #0xbb8 + sxtw x3, w3 + cmp x2, x3 + b.ne + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x28 + b.lt adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret - add x0, x20, #0xa + add x0, x1, #0x6e sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x420 - add x0, x0, #0xb4 - sxtw x1, w20 - ldrsw x0, [x0, x1, lsl #2] - add x1, x1, #0x7d0 - sxtw x1, w1 - cmp x0, x1 - b.eq - add x0, x20, #0x3c + add x0, x1, #0x3c sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x420 - add x0, x0, #0x158 - sxtw x1, w20 - ldrsw x0, [x0, x1, lsl #2] - add x1, x1, #0xbb8 - sxtw x1, w1 - cmp x0, x1 - b.eq - add x0, x20, #0x6e + add x0, x1, #0xa sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x490 + ldr x19, [sp] + add sp, sp, #0x480 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/large_struct_copy.x64.asm b/tests/snapshots/asm/large_struct_copy.x64.asm index 51475408f..7be95e142 100644 --- a/tests/snapshots/asm/large_struct_copy.x64.asm +++ b/tests/snapshots/asm/large_struct_copy.x64.asm @@ -13,9 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x480, %rsp # imm = 0x480 - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) + subq $0x470, %rsp # imm = 0x470 leaq -0x210(%rbp), %rax movl $0x64, %ecx movl %ecx, (%rax) @@ -50,29 +48,23 @@ Disassembly of section .text: movl $0x320, %ecx # imm = 0x320 movl %ecx, 0x208(%rax) xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x28, %rax - jge jmp - movslq %ecx, %rax + leaq -0x210(%rbp), %rdx + addq $0x10, %rdx + leaq 0x3e8(%rax), %rsi + movl %esi, (%rdx,%rax,4) + leaq -0x210(%rbp), %rdx + addq $0xb4, %rdx + leaq 0x7d0(%rax), %rsi + movl %esi, (%rdx,%rax,4) + leaq -0x210(%rbp), %rdx + addq $0x158, %rdx # imm = 0x158 + leaq 0xbb8(%rax), %rsi + movl %esi, (%rdx,%rax,4) leaq 0x1(%rax), %rcx - jmp - leaq -0x210(%rbp), %rax - addq $0x10, %rax - movslq %ecx, %rdx - leaq 0x3e8(%rdx), %rsi - movl %esi, (%rax,%rdx,4) - leaq -0x210(%rbp), %rax - addq $0xb4, %rax - movslq %ecx, %rdx - leaq 0x7d0(%rdx), %rsi - movl %esi, (%rax,%rdx,4) - leaq -0x210(%rbp), %rax - addq $0x158, %rax # imm = 0x158 - movslq %ecx, %rdx - leaq 0xbb8(%rdx), %rsi - movl %esi, (%rax,%rdx,4) - jmp + movslq %ecx, %rax + cmpq $0x28, %rax + jl leaq -0x420(%rbp), %rdi movl $0x7e, %esi movl $0x20c, %edx # imm = 0x20C @@ -225,7 +217,7 @@ Disassembly of section .text: cmpq $0x64, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x420(%rbp), %rax @@ -234,10 +226,10 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x420(%rbp), %rax movslq 0x8(%rax), %rax @@ -245,21 +237,19 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x420(%rbp), %rax movslq 0xc(%rax), %rax cmpq $0x190, %rax # imm = 0x190 - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq leaq -0x420(%rbp), %rax @@ -267,7 +257,7 @@ Disassembly of section .text: cmpq $0x1f4, %rax # imm = 0x1F4 setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x420(%rbp), %rax @@ -276,10 +266,10 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x420(%rbp), %rax movslq 0x204(%rax), %rax @@ -287,21 +277,19 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x420(%rbp), %rax movslq 0x208(%rax), %rax cmpq $0x320, %rax # imm = 0x320 - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq leaq -0x420(%rbp), %rax @@ -309,9 +297,7 @@ Disassembly of section .text: cmpq $-0x1, %rax je movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq leaq -0x420(%rbp), %rax @@ -319,9 +305,7 @@ Disassembly of section .text: cmpq $-0x2, %rax je movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq leaq -0x420(%rbp), %rax @@ -329,73 +313,57 @@ Disassembly of section .text: cmpq $-0x3, %rax je movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq - xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0x28, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - jmp - leaq -0x420(%rbp), %rax - addq $0x10, %rax - movslq %ebx, %rcx - movslq (%rax,%rcx,4), %rax - addq $0x3e8, %rcx # imm = 0x3E8 - movslq %ecx, %rcx - cmpq %rcx, %rax - je + xorq %rcx, %rcx jmp + leaq -0x420(%rbp), %rdx + addq $0x10, %rdx + movslq (%rdx,%rax,4), %rdx + leaq 0x3e8(%rax), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + jne + leaq -0x420(%rbp), %rdx + addq $0xb4, %rdx + movslq (%rdx,%rax,4), %rdx + leaq 0x7d0(%rax), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + jne + leaq -0x420(%rbp), %rdx + addq $0x158, %rdx # imm = 0x158 + movslq (%rdx,%rax,4), %rdx + leaq 0xbb8(%rax), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + jne + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x28, %rax + jl leaq , %rdi movb $0x0, %al callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq - leaq 0xa(%rbx), %rax + leaq 0x6e(%rcx), %rax movslq %eax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq - leaq -0x420(%rbp), %rax - addq $0xb4, %rax - movslq %ebx, %rcx - movslq (%rax,%rcx,4), %rax - addq $0x7d0, %rcx # imm = 0x7D0 - movslq %ecx, %rcx - cmpq %rcx, %rax - je - leaq 0x3c(%rbx), %rax + leaq 0x3c(%rcx), %rax movslq %eax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq - leaq -0x420(%rbp), %rax - addq $0x158, %rax # imm = 0x158 - movslq %ebx, %rcx - movslq (%rax,%rcx,4), %rax - addq $0xbb8, %rcx # imm = 0xBB8 - movslq %ecx, %rcx - cmpq %rcx, %rax - je - leaq 0x6e(%rbx), %rax + leaq 0xa(%rcx), %rax movslq %eax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x480, %rsp # imm = 0x480 + addq $0x470, %rsp # imm = 0x470 popq %rbp retq jmp @@ -405,4 +373,4 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/layout_bottom_test_loop.aarch64.asm b/tests/snapshots/asm/layout_bottom_test_loop.aarch64.asm new file mode 100644 index 000000000..49e0067e4 --- /dev/null +++ b/tests/snapshots/asm/layout_bottom_test_loop.aarch64.asm @@ -0,0 +1,14 @@ + +layout_bottom_test_loop.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x2d // =45 + ret diff --git a/tests/snapshots/asm/layout_bottom_test_loop.x64.asm b/tests/snapshots/asm/layout_bottom_test_loop.x64.asm new file mode 100644 index 000000000..fa76693d9 --- /dev/null +++ b/tests/snapshots/asm/layout_bottom_test_loop.x64.asm @@ -0,0 +1,16 @@ + +layout_bottom_test_loop.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + movl $0x2d, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/layout_goto_block_addr.aarch64.asm b/tests/snapshots/asm/layout_goto_block_addr.aarch64.asm new file mode 100644 index 000000000..d08ce3c96 --- /dev/null +++ b/tests/snapshots/asm/layout_goto_block_addr.aarch64.asm @@ -0,0 +1,79 @@ + +layout_goto_block_addr.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur w0, [x29, #0x10] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + adr x2, + str x2, [x0] + sub x0, x29, #0x10 + adr x2, + str x2, [x0, #0x8] + stur w1, [x29, #-0x18] + stur w1, [x29, #-0x20] + b + ldursw x0, [x29, #-0x18] + add x0, x0, #0x2 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x20] + add x0, x0, #0x1 + stur w0, [x29, #-0x20] + b + ldursw x0, [x29, #-0x18] + add x0, x0, #0x1 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x20] + add x0, x0, #0x1 + stur w0, [x29, #-0x20] + ldursw x0, [x29, #-0x20] + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt + ldursw x0, [x29, #-0x18] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + sub x0, x29, #0x10 + ldursw x1, [x29, #-0x20] + mov x17, #0x1 // =1 + and x1, x1, x17 + ldr x0, [x0, x1, lsl #3] + br x0 + +
: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x0, #0x0 // =0 + bl + add x20, x0, #0x0 + mov x0, #0x1 // =1 + bl + add x20, x20, x0 + mov x0, #0x2 // =2 + bl + add x20, x20, x0 + mov x0, #0x3 // =3 + bl + add x20, x20, x0 + mov x0, #0x4 // =4 + bl + add x0, x20, x0 + sxtw x0, w0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret diff --git a/tests/snapshots/asm/layout_goto_block_addr.x64.asm b/tests/snapshots/asm/layout_goto_block_addr.x64.asm new file mode 100644 index 000000000..d011bd135 --- /dev/null +++ b/tests/snapshots/asm/layout_goto_block_addr.x64.asm @@ -0,0 +1,87 @@ + +layout_goto_block_addr.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movl %edi, 0x10(%rbp) + leaq -0x10(%rbp), %rax + xorq %rcx, %rcx + leaq , %rdx # + movq %rdx, (%rax) + leaq -0x10(%rbp), %rax + leaq , %rdx # + movq %rdx, 0x8(%rax) + movl %ecx, -0x18(%rbp) + movl %ecx, -0x20(%rbp) + jmp + movslq -0x18(%rbp), %rax + addq $0x2, %rax + movl %eax, -0x18(%rbp) + movslq -0x20(%rbp), %rax + incq %rax + movl %eax, -0x20(%rbp) + jmp + movslq -0x18(%rbp), %rax + incq %rax + movl %eax, -0x18(%rbp) + movslq -0x20(%rbp), %rax + incq %rax + movl %eax, -0x20(%rbp) + movslq -0x20(%rbp), %rax + movslq 0x10(%rbp), %rcx + cmpq %rcx, %rax + jl + movslq -0x18(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + leaq -0x10(%rbp), %rax + movslq -0x20(%rbp), %rcx + andq $0x1, %rcx + movq (%rax,%rcx,8), %rax + jmpq *%rax + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + xorq %rdi, %rdi + callq + leaq (%rax), %rbx + movl $0x1, %edi + callq + addq %rax, %rbx + movl $0x2, %edi + callq + addq %rax, %rbx + movl $0x3, %edi + callq + addq %rax, %rbx + movl $0x4, %edi + callq + addq %rbx, %rax + movslq %eax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/layout_nested_loops.aarch64.asm b/tests/snapshots/asm/layout_nested_loops.aarch64.asm new file mode 100644 index 000000000..2b1431b78 --- /dev/null +++ b/tests/snapshots/asm/layout_nested_loops.aarch64.asm @@ -0,0 +1,40 @@ + +layout_nested_loops.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x1, #0x0 // =0 + mov x0, x1 + b + mov x4, #0x0 // =0 + b + add x5, x1, x4 + sxtw x5, w5 + mov x6, #0x3 // =3 + sdiv x17, x5, x6 + msub x5, x17, x6, x5 + cmp x5, #0x0 + b.ne + b + cmp x3, #0x4 + b.ne + b + add x0, x0, x4 + add x4, x3, #0x1 + sxtw x3, w4 + cmp x3, x2 + b.lt + add x0, x0, x1 + add x1, x2, #0x1 + sxtw x2, w1 + cmp x2, #0x6 + b.lt + sxtw x0, w0 + ret diff --git a/tests/snapshots/asm/layout_nested_loops.x64.asm b/tests/snapshots/asm/layout_nested_loops.x64.asm new file mode 100644 index 000000000..3149a89de --- /dev/null +++ b/tests/snapshots/asm/layout_nested_loops.x64.asm @@ -0,0 +1,49 @@ + +layout_nested_loops.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + xorq %rcx, %rcx + movq %rcx, %rax + jmp + xorq %rdi, %rdi + jmp + leaq (%rcx,%rdi), %r8 + movslq %r8d, %r8 + movl $0x3, %r9d + pushq %rax + pushq %rdx + movq %r8, %rax + cqto + idivq %r9 + movq %rdx, %r8 + popq %rdx + popq %rax + testq %r8, %r8 + jne + jmp + cmpq $0x4, %rsi + jne + jmp + addq %rdi, %rax + leaq 0x1(%rsi), %rdi + movslq %edi, %rsi + cmpq %rdx, %rsi + jl + addq %rcx, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq $0x6, %rdx + jl + movslq %eax, %rax + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm b/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm index 36edb6468..54beba9b6 100644 --- a/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm +++ b/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm @@ -13,9 +13,10 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f000000 // =1056964608 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x1, #0x3fd0000000000000 // =4598175219545276416 fmov d16, x1 sub x17, x29, #0x10 @@ -24,10 +25,14 @@ Disassembly of section .text: fmov d16, x1 sub x17, x29, #0x18 str d16, [x17] + mov x1, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x1 + fcvt s0, d16 mov x2, #0x1 // =1 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fcmp s1, s17 cset x0, ne cbz x0, mov x2, #0x0 // =0 @@ -47,22 +52,21 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x2, #0x0 // =0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x2, #0x0 // =0 sxtw x0, w2 cbz x0, mov x1, #0x7 // =7 - b - mov x1, #0x0 // =0 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x0 // =0 + b b b b diff --git a/tests/snapshots/asm/leading_dot_float_literal.x64.asm b/tests/snapshots/asm/leading_dot_float_literal.x64.asm index 143c480ac..2fdd8ecfd 100644 --- a/tests/snapshots/asm/leading_dot_float_literal.x64.asm +++ b/tests/snapshots/asm/leading_dot_float_literal.x64.asm @@ -14,19 +14,22 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) movabsq $0x3fd0000000000000, %rcx # imm = 0x3FD0000000000000 movq %rcx, %xmm14 movsd %xmm14, -0x10(%rbp,%riz) movabsq $0x4039000000000000, %rcx # imm = 0x4039000000000000 movq %rcx, %xmm14 movsd %xmm14, -0x18(%rbp,%riz) + movabsq $0x3fe0000000000000, %rcx # imm = 0x3FE0000000000000 + movq %rcx, %xmm14 + cvtsd2ss %xmm14, %xmm0 movl $0x1, %edx - cvtss2sd %xmm0, %xmm1 + movss -0x8(%rbp,%riz), %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm1 setne %al movzbq %al, %rax setp %r10b @@ -59,10 +62,9 @@ Disassembly of section .text: testq %rax, %rax je xorq %rdx, %rdx - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -75,14 +77,13 @@ Disassembly of section .text: testq %rax, %rax je movl $0x7, %ecx - jmp - xorq %rcx, %rcx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + xorq %rcx, %rcx + jmp jmp jmp jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/libc_address_in_static_init.aarch64.asm b/tests/snapshots/asm/libc_address_in_static_init.aarch64.asm index c749c5c9e..d803beb8b 100644 --- a/tests/snapshots/asm/libc_address_in_static_init.aarch64.asm +++ b/tests/snapshots/asm/libc_address_in_static_init.aarch64.asm @@ -29,32 +29,28 @@ Disassembly of section .text: str x2, [sp, #-0x10]! str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] ldur x2, [x29, #0x30] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x30 ret <__c5_sys_close>: str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x10 ret diff --git a/tests/snapshots/asm/libc_atoll_wcsrtombs.aarch64.asm b/tests/snapshots/asm/libc_atoll_wcsrtombs.aarch64.asm index 97228d06e..f61449371 100644 --- a/tests/snapshots/asm/libc_atoll_wcsrtombs.aarch64.asm +++ b/tests/snapshots/asm/libc_atoll_wcsrtombs.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 adrp x0, add x0, x0, bl @@ -24,9 +23,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret adrp x0, add x0, x0, @@ -48,13 +46,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret b diff --git a/tests/snapshots/asm/libc_basic.aarch64.asm b/tests/snapshots/asm/libc_basic.aarch64.asm index 8d87c560c..976d94d89 100644 --- a/tests/snapshots/asm/libc_basic.aarch64.asm +++ b/tests/snapshots/asm/libc_basic.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xc0 - str x19, [sp] + str x19, [sp, #-0xd0]! + stp x29, x30, [sp, #0xc0] + add x29, sp, #0xc0 adrp x0, add x0, x0, bl @@ -21,9 +20,8 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -32,9 +30,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -45,9 +42,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -59,9 +55,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -70,9 +65,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret ldrb w0, [x0] mov x17, #0x6c // =108 @@ -81,9 +75,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret sub x0, x29, #0x80 adrp x1, @@ -101,9 +94,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret sub x0, x29, #0x80 adrp x1, @@ -122,9 +114,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret sub x0, x29, #0x80 ldrb w0, [x0, #0x6] @@ -134,9 +125,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x9 // =9 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret sub x0, x29, #0x80 adrp x1, @@ -155,9 +145,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0xa // =10 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret sub x0, x29, #0x80 mov x1, #0x10 // =16 @@ -174,9 +163,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x20 // =32 bl @@ -184,9 +172,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x35 // =53 bl @@ -194,18 +181,16 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0xd // =13 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x61 // =97 bl sxtw x0, w0 cbz x0, mov x0, #0xe // =14 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x51 // =81 bl @@ -213,9 +198,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0xf // =15 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x7a // =122 bl @@ -223,9 +207,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x10 // =16 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x61 // =97 bl @@ -233,9 +216,8 @@ Disassembly of section .text: cmp x0, #0x41 b.eq mov x0, #0x11 // =17 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x5a // =90 bl @@ -243,9 +225,8 @@ Disassembly of section .text: cmp x0, #0x7a b.eq mov x0, #0x12 // =18 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x66 // =102 bl @@ -253,9 +234,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x13 // =19 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -264,9 +244,8 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x14 // =20 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret adrp x0, add x0, x0, @@ -279,9 +258,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x15 // =21 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0xfffb // =65531 movk x0, #0xffff, lsl #16 @@ -292,12 +270,10 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x16 // =22 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xc0] + ldr x19, [sp], #0xd0 ret diff --git a/tests/snapshots/asm/libc_data_globals.aarch64.asm b/tests/snapshots/asm/libc_data_globals.aarch64.asm index 79ea1c05c..8d4b3e20e 100644 --- a/tests/snapshots/asm/libc_data_globals.aarch64.asm +++ b/tests/snapshots/asm/libc_data_globals.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,20 +48,16 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x1 // =1 bl mov x20, x0 @@ -77,29 +69,23 @@ Disassembly of section .text: cmp x20, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret cmp x21, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -108,11 +94,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x20, add x20, x20, @@ -125,11 +109,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x2 // =2 bl @@ -140,16 +122,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/libc_data_globals.x64.asm b/tests/snapshots/asm/libc_data_globals.x64.asm index 064f33ff6..536628ad4 100644 --- a/tests/snapshots/asm/libc_data_globals.x64.asm +++ b/tests/snapshots/asm/libc_data_globals.x64.asm @@ -56,7 +56,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movl $0x1, %edi @@ -72,7 +72,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq testq %r12, %r12 @@ -80,7 +80,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq testq %rax, %rax @@ -88,7 +88,7 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -100,7 +100,7 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rbx @@ -116,7 +116,7 @@ Disassembly of section .text: movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x2, %edi @@ -131,13 +131,13 @@ Disassembly of section .text: movl $0x6, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_div.aarch64.asm b/tests/snapshots/asm/libc_div.aarch64.asm index 8a96bd17c..4b64755fb 100644 --- a/tests/snapshots/asm/libc_div.aarch64.asm +++ b/tests/snapshots/asm/libc_div.aarch64.asm @@ -71,17 +71,12 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0xc0 - mov x0, #0x11 // =17 - mov x1, #0x5 // =5 - sxtw x0, w0 - sxtw x1, w1 - sub x2, x29, #0x78 - sdiv x3, x0, x1 - str w3, [x2] - sub x2, x29, #0x78 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - str w0, [x2, #0x4] + sub x0, x29, #0x78 + mov x1, #0x3 // =3 + str w1, [x0] + sub x0, x29, #0x78 + mov x1, #0x2 // =2 + str w1, [x0, #0x4] sub x0, x29, #0x78 sub x1, x29, #0x8 str x10, [sp, #-0x10]! @@ -103,20 +98,18 @@ Disassembly of section .text: add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffef // =65519 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x5 // =5 - sxtw x0, w0 - sxtw x1, w1 - sub x2, x29, #0x88 - sdiv x3, x0, x1 - str w3, [x2] - sub x2, x29, #0x88 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - str w0, [x2, #0x4] + sub x0, x29, #0x88 + mov x1, #0xfffd // =65533 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + str w1, [x0] + sub x0, x29, #0x88 + mov x1, #0xfffe // =65534 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + str w1, [x0, #0x4] sub x0, x29, #0x88 sub x1, x29, #0x18 str x10, [sp, #-0x10]! @@ -164,15 +157,12 @@ Disassembly of section .text: add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x64 // =100 - mov x1, #0x7 // =7 - sub x2, x29, #0xa0 - sdiv x3, x0, x1 - str x3, [x2] - sub x2, x29, #0xa0 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - str x0, [x2, #0x8] + sub x0, x29, #0xa0 + mov x1, #0xe // =14 + str x1, [x0] + sub x0, x29, #0xa0 + mov x1, #0x2 // =2 + str x1, [x0, #0x8] sub x0, x29, #0xa0 sub x1, x29, #0x30 str x10, [sp, #-0x10]! @@ -196,15 +186,12 @@ Disassembly of section .text: add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3e8 // =1000 - mov x1, #0x3 // =3 - sub x2, x29, #0xb8 - sdiv x3, x0, x1 - str x3, [x2] - sub x2, x29, #0xb8 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - str x0, [x2, #0x8] + sub x0, x29, #0xb8 + mov x1, #0x14d // =333 + str x1, [x0] + sub x0, x29, #0xb8 + mov x1, #0x1 // =1 + str x1, [x0, #0x8] sub x0, x29, #0xb8 sub x1, x29, #0x50 str x10, [sp, #-0x10]! diff --git a/tests/snapshots/asm/libc_div.x64.asm b/tests/snapshots/asm/libc_div.x64.asm index 565b568be..5cb459b59 100644 --- a/tests/snapshots/asm/libc_div.x64.asm +++ b/tests/snapshots/asm/libc_div.x64.asm @@ -111,26 +111,12 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0xc0, %rsp - movl $0x11, %eax - movl $0x5, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - leaq -0x78(%rbp), %rdx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rsi - popq %rdx - popq %rax - movl %esi, (%rdx) - leaq -0x78(%rbp), %rdx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movl %eax, 0x4(%rdx) + leaq -0x78(%rbp), %rax + movl $0x3, %ecx + movl %ecx, (%rax) + leaq -0x78(%rbp), %rax + movl $0x2, %ecx + movl %ecx, 0x4(%rax) leaq -0x78(%rbp), %rax leaq -0x8(%rbp), %rcx pushq %rdx @@ -156,26 +142,12 @@ Disassembly of section .text: addq $0xc0, %rsp popq %rbp retq - movabsq $-0x11, %rax - movl $0x5, %ecx - movslq %eax, %rax - movslq %ecx, %rcx - leaq -0x88(%rbp), %rdx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rsi - popq %rdx - popq %rax - movl %esi, (%rdx) - leaq -0x88(%rbp), %rdx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movl %eax, 0x4(%rdx) + leaq -0x88(%rbp), %rax + movabsq $-0x3, %rcx + movl %ecx, (%rax) + leaq -0x88(%rbp), %rax + movabsq $-0x2, %rcx + movl %ecx, 0x4(%rax) leaq -0x88(%rbp), %rax leaq -0x18(%rbp), %rcx pushq %rdx @@ -214,24 +186,12 @@ Disassembly of section .text: addq $0xc0, %rsp popq %rbp retq - movl $0x64, %eax - movl $0x7, %ecx - leaq -0xa0(%rbp), %rdx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rsi - popq %rdx - popq %rax - movq %rsi, (%rdx) - leaq -0xa0(%rbp), %rdx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movq %rax, 0x8(%rdx) + leaq -0xa0(%rbp), %rax + movl $0xe, %ecx + movq %rcx, (%rax) + leaq -0xa0(%rbp), %rax + movl $0x2, %ecx + movq %rcx, 0x8(%rax) leaq -0xa0(%rbp), %rax leaq -0x30(%rbp), %rcx pushq %rdx @@ -259,24 +219,12 @@ Disassembly of section .text: addq $0xc0, %rsp popq %rbp retq - movl $0x3e8, %eax # imm = 0x3E8 - movl $0x3, %ecx - leaq -0xb8(%rbp), %rdx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rsi - popq %rdx - popq %rax - movq %rsi, (%rdx) - leaq -0xb8(%rbp), %rdx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movq %rax, 0x8(%rdx) + leaq -0xb8(%rbp), %rax + movl $0x14d, %ecx # imm = 0x14D + movq %rcx, (%rax) + leaq -0xb8(%rbp), %rax + movl $0x1, %ecx + movq %rcx, 0x8(%rax) leaq -0xb8(%rbp), %rax leaq -0x50(%rbp), %rcx pushq %rdx @@ -313,4 +261,3 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_fileno_isblank.aarch64.asm b/tests/snapshots/asm/libc_fileno_isblank.aarch64.asm index d28e4064e..5cd247b95 100644 --- a/tests/snapshots/asm/libc_fileno_isblank.aarch64.asm +++ b/tests/snapshots/asm/libc_fileno_isblank.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,17 +48,12 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x20 cset x1, eq @@ -73,16 +64,13 @@ Disassembly of section .text: cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x1 // =1 bl bl @@ -90,9 +78,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x2 // =2 bl @@ -101,46 +88,40 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x20 // =32 bl cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x9 // =9 bl cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x41 // =65 bl cbz x0, mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0xa // =10 bl cbz x0, mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/libc_fileno_isblank.x64.asm b/tests/snapshots/asm/libc_fileno_isblank.x64.asm index d2770e848..1cca75576 100644 --- a/tests/snapshots/asm/libc_fileno_isblank.x64.asm +++ b/tests/snapshots/asm/libc_fileno_isblank.x64.asm @@ -54,9 +54,6 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi cmpq $0x20, %rdi sete %al @@ -71,8 +68,6 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -132,4 +127,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_fp_classify.aarch64.asm b/tests/snapshots/asm/libc_fp_classify.aarch64.asm index c71127733..0e7cc2fb7 100644 --- a/tests/snapshots/asm/libc_fp_classify.aarch64.asm +++ b/tests/snapshots/asm/libc_fp_classify.aarch64.asm @@ -31,28 +31,25 @@ Disassembly of section .text: b.ne cmp x1, #0x0 b.ne - b - cmp x0, #0x7ff - b.ne - b mov x1, #0x2 // =2 - b - mov x1, #0x3 // =3 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x3 // =3 + b + cmp x0, #0x7ff + b.ne cmp x1, #0x0 b.ne - b - mov x0, #0x4 // =4 + mov x1, #0x1 // =1 + mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x1, #0x1 // =1 - b mov x1, #0x0 // =0 - mov x0, x1 + b + mov x0, #0x4 // =4 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret @@ -102,20 +99,17 @@ Disassembly of section .text: : stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x20 fcvt d0, s0 fcvt d1, s1 bl fcvt s0, d0 - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, #0x4008000000000000 // =4613937818241073152 mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x0 @@ -129,9 +123,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x20, #0x4008000000000000 // =4613937818241073152 fmov d16, x20 @@ -144,28 +137,24 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret - mov x20, #0x4000000000000000 // =4611686018427387904 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fneg d1, d16 - fcvt s1, d1 + mov x20, #0x40000000 // =1073741824 + mov x0, #0x40a00000 // =1084227584 + fmov s16, w0 + fneg s0, s16 + fmov d1, d0 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x0 @@ -174,18 +163,16 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x0 bl cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 fmov d16, x0 @@ -194,9 +181,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 fmov d0, x0 @@ -204,9 +190,8 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x0 @@ -214,9 +199,8 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x8 // =8 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0xc8a0 // =51360 movk x0, #0x85eb, lsl #16 @@ -230,9 +214,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x9 // =9 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 fmov d16, x0 @@ -242,9 +225,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0xa // =10 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0xe62b // =58923 movk x0, #0x8b70, lsl #16 @@ -254,12 +236,10 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0xb // =11 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/libc_fp_classify.x64.asm b/tests/snapshots/asm/libc_fp_classify.x64.asm index fdc7cc245..c57a4d943 100644 --- a/tests/snapshots/asm/libc_fp_classify.x64.asm +++ b/tests/snapshots/asm/libc_fp_classify.x64.asm @@ -28,28 +28,25 @@ Disassembly of section .text: jne testq %rcx, %rcx jne - jmp - cmpq $0x7ff, %rax # imm = 0x7FF - jne - jmp movl $0x2, %ecx - jmp - movl $0x3, %ecx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x3, %ecx + jmp + cmpq $0x7ff, %rax # imm = 0x7FF + jne testq %rcx, %rcx jne - jmp - movl $0x4, %eax + movl $0x1, %ecx + movq %rcx, %rax addq $0x30, %rsp popq %rbp retq - movl $0x1, %ecx - jmp xorq %rcx, %rcx - movq %rcx, %rax + jmp + movl $0x4, %eax addq $0x30, %rsp popq %rbp retq @@ -96,12 +93,10 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp cvtss2sd %xmm0, %xmm0 cvtss2sd %xmm1, %xmm1 callq cvtsd2ss %xmm0, %xmm0 - addq $0x20, %rsp popq %rbp retq @@ -158,22 +153,20 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rbx # imm = 0x4000000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x40000000, %ebx # imm = 0x40000000 + movl $0x40a00000, %eax # imm = 0x40A00000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 + movapd %xmm0, %xmm1 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_fp_return_value.aarch64.asm b/tests/snapshots/asm/libc_fp_return_value.aarch64.asm index f231dc9a1..2774d9b90 100644 --- a/tests/snapshots/asm/libc_fp_return_value.aarch64.asm +++ b/tests/snapshots/asm/libc_fp_return_value.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x1 // =1 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d16, x0 @@ -69,32 +68,27 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40600000 // =1080033280 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fsqrt s0, s16 fcvt d0, s0 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d17, x0 @@ -102,59 +96,47 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintm s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 + fmov s16, w0 + frintm s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x6666 // =26214 - movk x0, #0x6666, lsl #16 - movk x0, #0x6666, lsl #32 - movk x0, #0x4002, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintp s0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3333 // =13107 + movk x0, #0x4013, lsl #16 + fmov s16, w0 + frintp s0, s16 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40e00000 // =1088421888 + mov x1, #0x40800000 // =1082130432 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 sxtw x0, w20 cbz x0, mov x1, #0xb // =11 - b - mov x1, #0x0 // =0 mov x0, x1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret + mov x1, #0x0 // =0 + b b b b diff --git a/tests/snapshots/asm/libc_fp_return_value.x64.asm b/tests/snapshots/asm/libc_fp_return_value.x64.asm index cd8d99241..fad3af487 100644 --- a/tests/snapshots/asm/libc_fp_return_value.x64.asm +++ b/tests/snapshots/asm/libc_fp_return_value.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x1, %ebx movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 @@ -93,14 +93,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,18 +107,16 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -129,9 +125,8 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 @@ -145,14 +140,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x402ccccd, %eax # imm = 0x402CCCCD + movq %rax, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -161,14 +154,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4002666666666666, %rax # imm = 0x4002666666666666 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40133333, %eax # imm = 0x40133333 + movq %rax, %xmm0 roundss $0xa, %xmm0, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,18 +168,15 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40e00000, %edi # imm = 0x40E00000 + movl $0x40800000, %esi # imm = 0x40800000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -201,13 +189,13 @@ Disassembly of section .text: testq %rax, %rax je movl $0xb, %ecx - jmp - xorq %rcx, %rcx movq (%rsp), %rbx movq %rcx, %rax - addq $0x90, %rsp + addq $0x10, %rsp popq %rbp retq + xorq %rcx, %rcx + jmp jmp jmp jmp @@ -220,3 +208,4 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_int_arith.aarch64.asm b/tests/snapshots/asm/libc_int_arith.aarch64.asm index a8493fa31..486a5a046 100644 --- a/tests/snapshots/asm/libc_int_arith.aarch64.asm +++ b/tests/snapshots/asm/libc_int_arith.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x1, x0 cmp x1, #0x0 b.ge @@ -21,16 +18,11 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 mul x1, x1, x17 - b mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x1, x0 cmp x1, #0x0 b.ge @@ -39,16 +31,11 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 mul x1, x1, x17 - b mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x1, x0 cmp x1, #0x0 b.ge @@ -57,11 +44,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 mul x1, x1, x17 - b mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + b : stp x29, x30, [sp, #-0x10]! @@ -83,34 +68,29 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x2, w2 bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x2, w2 bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + sub sp, sp, #0x50 mov x0, #0xfff9 // =65529 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 @@ -119,8 +99,7 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0xfff7 // =65527 @@ -131,8 +110,7 @@ Disassembly of section .text: cmp x0, #0x9 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x80000000 // =2147483648 @@ -143,8 +121,7 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0xfff5 // =65525 @@ -155,22 +132,21 @@ Disassembly of section .text: cmp x0, #0xb b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffef // =65519 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x5 // =5 - sub x2, x29, #0x48 - sdiv x3, x0, x1 - str x3, [x2] - sub x2, x29, #0x48 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - str x0, [x2, #0x8] + sub x0, x29, #0x48 + mov x1, #0xfffd // =65533 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + str x1, [x0] + sub x0, x29, #0x48 + mov x1, #0xfffe // =65534 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + str x1, [x0, #0x8] sub x0, x29, #0x48 sub x1, x29, #0x10 str x10, [sp, #-0x10]! @@ -187,8 +163,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x10 ldr x0, [x0, #0x8] mov x17, #0xfffe // =65534 @@ -196,11 +172,10 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 @@ -217,8 +192,7 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -230,8 +204,7 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -242,13 +215,11 @@ Disassembly of section .text: cmp x0, #0xff b.eq mov x0, #0x8 // =8 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x60 + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/libc_int_arith.x64.asm b/tests/snapshots/asm/libc_int_arith.x64.asm index 67ef026a3..499dd64f4 100644 --- a/tests/snapshots/asm/libc_int_arith.x64.asm +++ b/tests/snapshots/asm/libc_int_arith.x64.asm @@ -11,43 +11,28 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp testq %rdi, %rdi jge imulq $-0x1, %rdi, %rdi - jmp movq %rdi, %rax - addq $0x10, %rsp - popq %rbp retq + jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp testq %rdi, %rdi jge imulq $-0x1, %rdi, %rdi - jmp movq %rdi, %rax - addq $0x10, %rsp - popq %rbp retq + jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp testq %rdi, %rdi jge imulq $-0x1, %rdi, %rdi - jmp movq %rdi, %rax - addq $0x10, %rsp - popq %rbp retq + jmp : pushq %rbp @@ -102,15 +87,13 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp - movq %rbx, (%rsp) + subq $0x50, %rsp movabsq $-0x7, %rdi callq cmpq $0x7, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movabsq $-0x9, %rdi @@ -118,8 +101,7 @@ Disassembly of section .text: cmpq $0x9, %rax je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movabsq $-0x80000000, %rdi # imm = 0x80000000 @@ -128,8 +110,7 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movabsq $-0xb, %rdi @@ -137,28 +118,15 @@ Disassembly of section .text: cmpq $0xb, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq - movabsq $-0x11, %rax - movl $0x5, %ecx - leaq -0x48(%rbp), %rdx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rsi - popq %rdx - popq %rax - movq %rsi, (%rdx) - leaq -0x48(%rbp), %rdx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movq %rax, 0x8(%rdx) + leaq -0x48(%rbp), %rax + movabsq $-0x3, %rcx + movq %rcx, (%rax) + leaq -0x48(%rbp), %rax + movabsq $-0x2, %rcx + movq %rcx, 0x8(%rax) leaq -0x48(%rbp), %rax leaq -0x10(%rbp), %rcx pushq %rdx @@ -171,20 +139,19 @@ Disassembly of section .text: leaq -0x10(%rbp), %rax movq (%rax), %rax cmpq $-0x3, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax cmpq $-0x2, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq -0x10(%rbp), %rax @@ -196,8 +163,7 @@ Disassembly of section .text: cmpq $-0x11, %rax je movl $0x6, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq , %rdi @@ -207,8 +173,7 @@ Disassembly of section .text: cmpq $0x3039, %rax # imm = 0x3039 je movl $0x7, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq , %rdi @@ -218,14 +183,13 @@ Disassembly of section .text: cmpq $0xff, %rax je movl $0x8, %eax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm b/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm index f49999c40..02f93f7ae 100644 --- a/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm +++ b/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm @@ -28,67 +28,59 @@ Disassembly of section .text: fsub d0, d0, d1 sub x17, x29, #0x18 str d0, [x17] - b - mov x0, #0x0 // =0 - fmov d16, x0 - sub x17, x29, #0x18 - str d16, [x17] sub x16, x29, #0x18 ldr d0, [x16] add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x0 // =0 + fmov d16, x0 + sub x17, x29, #0x18 + str d16, [x17] + b b b : stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x20 fcvt d0, s0 fcvt d1, s1 bl fcvt s0, d0 - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 fcvt d0, s0 bl fcvt s0, d0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: @@ -174,31 +166,27 @@ Disassembly of section .text: mov x0, #0x6 // =6 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x2 // =2 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x2 // =2 + fmov d0, x0 + mov x0, x1 bl - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40a00000 // =1084227584 + mov x1, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm b/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm index 582d52781..8e6eb70c0 100644 --- a/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm +++ b/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm @@ -41,26 +41,24 @@ Disassembly of section .text: je subsd %xmm1, %xmm0 movsd %xmm0, -0x18(%rbp,%riz) - jmp - xorq %rax, %rax - movq %rax, %xmm14 - movsd %xmm14, -0x18(%rbp,%riz) movsd -0x18(%rbp,%riz), %xmm0 addq $0x20, %rsp popq %rbp retq + xorq %rax, %rax + movq %rax, %xmm14 + movsd %xmm14, -0x18(%rbp,%riz) + jmp jmp jmp : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp cvtss2sd %xmm0, %xmm0 cvtss2sd %xmm1, %xmm1 callq cvtsd2ss %xmm0, %xmm0 - addq $0x20, %rsp popq %rbp retq @@ -85,13 +83,11 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp movslq %edi, %rdi cvtss2sd %xmm0, %xmm0 xorl %eax, %eax callq cvtsd2ss %xmm0, %xmm0 - addq $0x20, %rsp popq %rbp retq @@ -205,15 +201,14 @@ Disassembly of section .text: movl $0x6, %eax popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movl $0x2, %edi + movl $0x3f800000, %edi # imm = 0x3F800000 + movl $0x2, %esi + movq %rdi, %xmm0 + movq %rsi, %rdi callq - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -224,17 +219,14 @@ Disassembly of section .text: movl $0x7, %eax popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40a00000, %edi # imm = 0x40A00000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -248,3 +240,5 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm b/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm index efe380f82..94db4b2fa 100644 --- a/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm +++ b/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d1, d0, d1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -27,17 +24,14 @@ Disassembly of section .text: fmov d17, x0 fcmp d1, d17 cset x0, mi - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x0 // =0 fmov d0, x20 bl @@ -46,10 +40,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x0 @@ -60,10 +53,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x0 // =0 fmov d0, x20 @@ -73,10 +65,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x4000000000000000 // =4611686018427387904 fmov d0, x20 @@ -87,10 +78,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x4008000000000000 // =4613937818241073152 fmov d0, x20 @@ -101,10 +91,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x3fe0000000000000 // =4602678819172646912 fmov d0, x20 @@ -115,44 +104,40 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne mov x0, #0x8 // =8 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/libc_math_hyperbolic.x64.asm b/tests/snapshots/asm/libc_math_hyperbolic.x64.asm index 7038ffb82..47654fe03 100644 --- a/tests/snapshots/asm/libc_math_hyperbolic.x64.asm +++ b/tests/snapshots/asm/libc_math_hyperbolic.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subsd %xmm15, %xmm1 @@ -38,8 +35,6 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -133,13 +128,13 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne @@ -148,13 +143,13 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne @@ -168,3 +163,5 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_libm.aarch64.asm b/tests/snapshots/asm/libc_math_libm.aarch64.asm index d791528ac..b64bb3190 100644 --- a/tests/snapshots/asm/libc_math_libm.aarch64.asm +++ b/tests/snapshots/asm/libc_math_libm.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d1, d0, d1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -27,17 +24,14 @@ Disassembly of section .text: fmov d17, x0 fcmp d1, d17 cset x0, mi - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x403b000000000000 // =4628293042053316608 fmov d0, x0 bl @@ -47,10 +41,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4020000000000000 // =4620693217682128896 fmov d0, x0 @@ -61,10 +54,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x20 @@ -75,10 +67,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4014000000000000 // =4617315517961601024 mov x1, #0x4008000000000000 // =4613937818241073152 @@ -92,10 +83,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4004000000000000 // =4612811918334230528 fmov d0, x0 @@ -103,10 +93,9 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x400c000000000000 // =4615063718147915776 fmov d0, x0 @@ -114,10 +103,9 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4004000000000000 // =4612811918334230528 fmov d16, x0 @@ -130,33 +118,29 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x403b000000000000 // =4628293042053316608 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x41d80000 // =1104674816 + fmov d0, x0 bl fcvt d0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d1, x0 + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + fcvt d1, s16 bl cmp x0, #0x0 b.ne mov x0, #0x8 // =8 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40a00000 // =1084227584 + mov x1, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x1 bl fcvt d0, s0 mov x0, #0x3ff0000000000000 // =4607182418800017408 @@ -166,14 +150,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x9 // =9 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/libc_math_libm.x64.asm b/tests/snapshots/asm/libc_math_libm.x64.asm index 72b88b63a..3cf93165d 100644 --- a/tests/snapshots/asm/libc_math_libm.x64.asm +++ b/tests/snapshots/asm/libc_math_libm.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subsd %xmm15, %xmm1 @@ -38,8 +35,6 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -151,14 +146,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x403b000000000000, %rax # imm = 0x403B000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41d80000, %edi # imm = 0x41D80000 + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movabsq $0x4008000000000000, %rdi # imm = 0x4008000000000000 - movq %rdi, %xmm1 + movl $0x40400000, %eax # imm = 0x40400000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 callq testq %rax, %rax jne @@ -167,12 +162,10 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40a00000, %edi # imm = 0x40A00000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 @@ -194,4 +187,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/libc_math_minmax.aarch64.asm b/tests/snapshots/asm/libc_math_minmax.aarch64.asm index a379e3dcf..c02c52ca7 100644 --- a/tests/snapshots/asm/libc_math_minmax.aarch64.asm +++ b/tests/snapshots/asm/libc_math_minmax.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x4008000000000000 // =4613937818241073152 mov x1, #0x4010000000000000 // =4616189618054758400 fmov d0, x0 @@ -26,10 +25,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x4000000000000000 // =4611686018427387904 mov x1, #0x4008000000000000 // =4613937818241073152 @@ -41,10 +39,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4000000000000000 // =4611686018427387904 mov x20, #0x4008000000000000 // =4613937818241073152 @@ -56,10 +53,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 fmov d16, x0 @@ -73,10 +69,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x4014000000000000 // =4617315517961601024 mov x0, #0x0 // =0 @@ -91,69 +86,55 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40400000 // =1077936128 + mov x1, #0x40800000 // =1082130432 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x20, #0x4000000000000000 // =4611686018427387904 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + fmov d0, x20 + fmov d1, x1 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s1, d16 + mov x0, #0x40000000 // =1073741824 + mov x20, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/libc_math_minmax.x64.asm b/tests/snapshots/asm/libc_math_minmax.x64.asm index ede97aeca..680d8a979 100644 --- a/tests/snapshots/asm/libc_math_minmax.x64.asm +++ b/tests/snapshots/asm/libc_math_minmax.x64.asm @@ -121,18 +121,15 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40400000, %edi # imm = 0x40400000 + movl $0x40800000, %esi # imm = 0x40800000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -145,17 +142,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rbx # imm = 0x4000000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40000000, %ebx # imm = 0x40000000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -168,17 +162,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40000000, %edi # imm = 0x40000000 + movl $0x40400000, %ebx # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rbx, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_math_nextafter.aarch64.asm b/tests/snapshots/asm/libc_math_nextafter.aarch64.asm index 614167329..bfd30f632 100644 --- a/tests/snapshots/asm/libc_math_nextafter.aarch64.asm +++ b/tests/snapshots/asm/libc_math_nextafter.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x3ff0000000000000 // =4607182418800017408 mov x1, #0x4000000000000000 // =4611686018427387904 fmov d0, x20 @@ -25,10 +24,9 @@ Disassembly of section .text: cset x0, ls cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x3ff0000000000000 // =4607182418800017408 mov x1, #0x0 // =0 @@ -40,10 +38,9 @@ Disassembly of section .text: cset x0, ge cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x20 @@ -54,10 +51,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x4020000000000000 // =4620693217682128896 fmov d0, x0 @@ -66,10 +62,9 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x0 @@ -78,10 +73,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x3fd0000000000000 // =4598175219545276416 fmov d0, x0 @@ -94,45 +88,37 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x20, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + fmov d0, x20 + fmov d1, x1 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ls cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x41800000 // =1098907648 + fmov d0, x0 bl sxtw x0, w0 cmp x0, #0x4 b.eq mov x0, #0x8 // =8 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/libc_math_nextafter.x64.asm b/tests/snapshots/asm/libc_math_nextafter.x64.asm index 39de0d513..6d486b415 100644 --- a/tests/snapshots/asm/libc_math_nextafter.x64.asm +++ b/tests/snapshots/asm/libc_math_nextafter.x64.asm @@ -107,17 +107,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rbx # imm = 0x3FF0000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3f800000, %ebx # imm = 0x3F800000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setbe %al movzbq %al, %rax setnp %r10b @@ -130,9 +127,8 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %edi # imm = 0x41800000 + movq %rdi, %xmm0 xorl %eax, %eax callq movslq %eax, %rax @@ -148,4 +144,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_round.aarch64.asm b/tests/snapshots/asm/libc_math_round.aarch64.asm index 29d230192..f4f8a5d69 100644 --- a/tests/snapshots/asm/libc_math_round.aarch64.asm +++ b/tests/snapshots/asm/libc_math_round.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x4004000000000000 // =4612811918334230528 fmov d0, x0 bl @@ -23,9 +22,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x400c000000000000 // =4615063718147915776 fmov d0, x0 @@ -36,9 +34,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x4004000000000000 // =4612811918334230528 fmov d0, x0 @@ -49,9 +46,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x4004000000000000 // =4612811918334230528 fmov d0, x0 @@ -59,9 +55,8 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x4004000000000000 // =4612811918334230528 fmov d16, x0 @@ -74,9 +69,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x3333 // =13107 movk x0, #0x3333, lsl #16 @@ -87,9 +81,8 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x1000 // =4096 movk x0, #0xd4a5, lsl #16 @@ -105,42 +98,34 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40200000 // =1075838976 + fmov d0, x0 bl - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40600000 // =1080033280 + fmov d0, x0 bl - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/libc_math_round.x64.asm b/tests/snapshots/asm/libc_math_round.x64.asm index df23af437..f49bedaf1 100644 --- a/tests/snapshots/asm/libc_math_round.x64.asm +++ b/tests/snapshots/asm/libc_math_round.x64.asm @@ -107,15 +107,13 @@ Disassembly of section .text: movl $0x7, %eax popq %rbp retq - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edi # imm = 0x40200000 + movq %rdi, %xmm0 xorl %eax, %eax callq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -126,15 +124,13 @@ Disassembly of section .text: movl $0x8, %eax popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40600000, %edi # imm = 0x40600000 + movq %rdi, %xmm0 xorl %eax, %eax callq - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_math_special.aarch64.asm b/tests/snapshots/asm/libc_math_special.aarch64.asm index d18cfdb9d..4ad800004 100644 --- a/tests/snapshots/asm/libc_math_special.aarch64.asm +++ b/tests/snapshots/asm/libc_math_special.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d1, d0, d1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -27,18 +24,15 @@ Disassembly of section .text: fmov d17, x0 fcmp d1, d17 cset x0, mi - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str d8, [sp] + str d8, [sp, #-0x40]! str x20, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x0, #0x4014000000000000 // =4617315517961601024 fmov d0, x0 bl @@ -48,11 +42,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret mov x20, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x20 @@ -62,11 +55,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret mov x20, #0x0 // =0 fmov d0, x20 @@ -76,11 +68,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret mov x0, #0x0 // =0 fmov d0, x0 @@ -91,11 +82,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret mov x20, #0x3ff0000000000000 // =4607182418800017408 fmov d0, x20 @@ -109,15 +99,13 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40a00000 // =1084227584 + fmov d0, x0 bl fcvt d0, s0 mov x0, #0x4038000000000000 // =4627448617123184640 @@ -126,32 +114,29 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne mov x0, #0x7 // =7 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0x40 ret diff --git a/tests/snapshots/asm/libc_math_special.x64.asm b/tests/snapshots/asm/libc_math_special.x64.asm index 66dedf738..0ab9a618b 100644 --- a/tests/snapshots/asm/libc_math_special.x64.asm +++ b/tests/snapshots/asm/libc_math_special.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subsd %xmm15, %xmm1 @@ -38,8 +35,6 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -122,9 +117,8 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 @@ -138,13 +132,13 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne @@ -158,4 +152,4 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_pread64_pwrite64.aarch64.asm b/tests/snapshots/asm/libc_pread64_pwrite64.aarch64.asm index 7770e85ea..d4732a867 100644 --- a/tests/snapshots/asm/libc_pread64_pwrite64.aarch64.asm +++ b/tests/snapshots/asm/libc_pread64_pwrite64.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xd0 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0xe0]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0xd0] + add x29, sp, #0xd0 sub x20, x29, #0x40 adrp x21, add x21, x21, @@ -37,12 +35,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x58 adrp x1, @@ -61,12 +57,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x68 mov x21, #0x0 // =0 @@ -85,12 +79,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x58 sub x1, x29, #0x68 @@ -103,12 +95,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret adrp x0, add x0, x0, @@ -118,29 +108,21 @@ Disassembly of section .text: sub x2, x29, #0x58 mov x3, #0x8 // =8 mov x4, #0x10 // =16 - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x1, x2 + mov x2, x3 + mov x3, x4 blr x9 - add sp, sp, #0x40 cmp x0, #0x8 b.eq sub x0, x29, #0x40 bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x68 mov x1, #0x0 // =0 @@ -150,29 +132,19 @@ Disassembly of section .text: sxtw x0, w20 sub x1, x29, #0x68 mov x2, #0x8 // =8 - str x22, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x3, x22 blr x9 - add sp, sp, #0x40 cmp x0, #0x8 b.eq sub x0, x29, #0x40 bl sxtw x0, w0 mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sub x0, x29, #0x58 sub x1, x29, #0x68 @@ -185,12 +157,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret sxtw x0, w20 bl @@ -199,12 +169,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xd0] ldr x19, [sp, #0x20] - add sp, sp, #0xd0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xe0 ret <__c5_sys_pread64>: @@ -212,18 +180,16 @@ Disassembly of section .text: str x2, [sp, #-0x10]! str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] ldur x2, [x29, #0x30] ldur x3, [x29, #0x40] bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x40 ret @@ -232,17 +198,15 @@ Disassembly of section .text: str x2, [sp, #-0x10]! str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] ldur x2, [x29, #0x30] ldur x3, [x29, #0x40] bl - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x40 ret diff --git a/tests/snapshots/asm/libc_struct_arg_by_value.aarch64.asm b/tests/snapshots/asm/libc_struct_arg_by_value.aarch64.asm index 416e18eff..84cd4a246 100644 --- a/tests/snapshots/asm/libc_struct_arg_by_value.aarch64.asm +++ b/tests/snapshots/asm/libc_struct_arg_by_value.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x40]! + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 sub x0, x29, #0x8 mov x1, #0x7f // =127 movk x1, #0x100, lsl #16 @@ -28,9 +27,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret sub x0, x29, #0x10 mov x1, #0xa8c0 // =43200 @@ -46,12 +44,10 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret diff --git a/tests/snapshots/asm/libc_struct_buf_size.aarch64.asm b/tests/snapshots/asm/libc_struct_buf_size.aarch64.asm index cba1a7b43..0127c5e4c 100644 --- a/tests/snapshots/asm/libc_struct_buf_size.aarch64.asm +++ b/tests/snapshots/asm/libc_struct_buf_size.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x19, [sp] + str x19, [sp, #-0xc0]! + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 adrp x0, add x0, x0, sub x1, x29, #0x80 @@ -31,12 +30,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xb0] + ldr x19, [sp], #0xc0 ret mov x0, #0x2a // =42 - ldr x19, [sp] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xb0] + ldr x19, [sp], #0xc0 ret diff --git a/tests/snapshots/asm/libc_struct_return.aarch64.asm b/tests/snapshots/asm/libc_struct_return.aarch64.asm index 619c01ac7..afa626051 100644 --- a/tests/snapshots/asm/libc_struct_return.aarch64.asm +++ b/tests/snapshots/asm/libc_struct_return.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x0, #0x11 // =17 mov x1, #0x5 // =5 bl @@ -35,9 +34,8 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 ldrsw x0, [x0] @@ -48,9 +46,8 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x64 // =100 mov x1, #0x7 // =7 @@ -73,12 +70,10 @@ Disassembly of section .text: cmp x0, #0x10 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret diff --git a/tests/snapshots/asm/libc_time_widths.aarch64.asm b/tests/snapshots/asm/libc_time_widths.aarch64.asm index ea50b1003..3ed8601fd 100644 --- a/tests/snapshots/asm/libc_time_widths.aarch64.asm +++ b/tests/snapshots/asm/libc_time_widths.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x0, #0xf200 // =61952 movk x0, #0x2a05, lsl #16 movk x0, #0x1, lsl #32 @@ -29,11 +27,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret mov x20, #0x0 // =0 mov x0, x20 @@ -47,11 +43,9 @@ Disassembly of section .text: cmp x21, x17 b.ge mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret ldur x0, [x29, #-0x18] cmp x0, x21 @@ -63,17 +57,13 @@ Disassembly of section .text: cset x1, gt cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret b diff --git a/tests/snapshots/asm/line_directive.aarch64.asm b/tests/snapshots/asm/line_directive.aarch64.asm index c59a0c0d1..678c7bf32 100644 --- a/tests/snapshots/asm/line_directive.aarch64.asm +++ b/tests/snapshots/asm/line_directive.aarch64.asm @@ -10,14 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/line_directive.x64.asm b/tests/snapshots/asm/line_directive.x64.asm index 98762f1b7..80319df9e 100644 --- a/tests/snapshots/asm/line_directive.x64.asm +++ b/tests/snapshots/asm/line_directive.x64.asm @@ -11,14 +11,12 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/linked_list.aarch64.asm b/tests/snapshots/asm/linked_list.aarch64.asm index dbdad7fa9..fca542f27 100644 --- a/tests/snapshots/asm/linked_list.aarch64.asm +++ b/tests/snapshots/asm/linked_list.aarch64.asm @@ -10,42 +10,51 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] - mov x21, #0x0 // =0 - mov x20, x21 - mov x22, x21 - sxtw x0, w20 - cmp x0, #0x5 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 - mov x22, x1 - b + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 + mov x22, #0x0 // =0 + mov x0, #0x10 // =16 + bl + mov x20, x0 + mov x0, #0x0 // =0 + str x0, [x20] + str x22, [x20, #0x8] + mov x0, #0x10 // =16 + bl + mov x21, x0 + mov x0, #0x1 // =1 + str x0, [x21] + str x20, [x21, #0x8] + mov x0, #0x10 // =16 + bl + mov x20, x0 + mov x0, #0x2 // =2 + str x0, [x20] + str x21, [x20, #0x8] + mov x0, #0x10 // =16 + bl + mov x21, x0 + mov x0, #0x3 // =3 + str x0, [x21] + str x20, [x21, #0x8] mov x0, #0x10 // =16 bl mov x1, x0 - sxtw x0, w20 + mov x0, #0x4 // =4 str x0, [x1] - str x22, [x1, #0x8] + str x21, [x1, #0x8] b - cmp x22, #0x0 - b.eq - ldr x0, [x22] - add x21, x21, x0 - ldr x22, [x22, #0x8] - b - sxtw x0, w21 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldr x0, [x1] + add x22, x22, x0 + ldr x1, [x1, #0x8] + cmp x1, #0x0 + b.ne + sxtw x0, w22 + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret diff --git a/tests/snapshots/asm/linked_list.x64.asm b/tests/snapshots/asm/linked_list.x64.asm index f1c9e38b7..612425bf6 100644 --- a/tests/snapshots/asm/linked_list.x64.asm +++ b/tests/snapshots/asm/linked_list.x64.asm @@ -13,40 +13,56 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) - xorq %r12, %r12 - movq %r12, %rbx - movq %r12, %r13 - movslq %ebx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - movq %rcx, %r13 - jmp + xorq %r13, %r13 + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %rbx + xorq %rax, %rax + movq %rax, (%rbx) + movq %r13, 0x8(%rbx) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %r12 + movl $0x1, %eax + movq %rax, (%r12) + movq %rbx, 0x8(%r12) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %rbx + movl $0x2, %eax + movq %rax, (%rbx) + movq %r12, 0x8(%rbx) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %r12 + movl $0x3, %eax + movq %rax, (%r12) + movq %rbx, 0x8(%r12) movl $0x10, %edi xorl %eax, %eax callq movq %rax, %rcx - movslq %ebx, %rax + movl $0x4, %eax movq %rax, (%rcx) - movq %r13, 0x8(%rcx) - jmp - testq %r13, %r13 - je - movq (%r13), %rax - addq %rax, %r12 - movq 0x8(%r13), %r13 + movq %r12, 0x8(%rcx) jmp - movslq %r12d, %rax + movq (%rcx), %rax + addq %rax, %r13 + movq 0x8(%rcx), %rcx + testq %rcx, %rcx + jne + movslq %r13d, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/local_aggregate_runtime_init.x64.asm b/tests/snapshots/asm/local_aggregate_runtime_init.x64.asm index a73a628b6..121bbe6d6 100644 --- a/tests/snapshots/asm/local_aggregate_runtime_init.x64.asm +++ b/tests/snapshots/asm/local_aggregate_runtime_init.x64.asm @@ -211,4 +211,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/local_array_partial_init_zero.aarch64.asm b/tests/snapshots/asm/local_array_partial_init_zero.aarch64.asm index f4d7921df..7b553aef3 100644 --- a/tests/snapshots/asm/local_array_partial_init_zero.aarch64.asm +++ b/tests/snapshots/asm/local_array_partial_init_zero.aarch64.asm @@ -14,18 +14,14 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0xb0 mov x2, #0x0 // =0 - sxtw x1, w2 - cmp x1, #0x28 - b.ge - b - sxtw x1, w2 - add x2, x1, #0x1 b - sub x1, x29, #0xa0 - sxtw x3, w2 + sub x3, x29, #0xa0 mov w4, w0 - str w4, [x1, x3, lsl #2] - b + str w4, [x3, x1, lsl #2] + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, #0x28 + b.lt sub x0, x29, #0xa0 mov x1, #0x0 // =0 ldr w0, [x0] @@ -83,29 +79,24 @@ Disassembly of section .text: ldr x10, [sp], #0x10 mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - cmp x2, #0x19 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 b mov w0, w0 - sub x2, x29, #0x68 - sxtw x3, w1 - ldr w2, [x2, x3, lsl #2] - add x0, x0, x2 - b + sub x3, x29, #0x68 + ldr w3, [x3, x2, lsl #2] + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + cmp x2, #0x19 + b.lt mov w0, w0 add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0xbeef // =48879 movk x0, #0xdead, lsl #16 bl @@ -119,20 +110,17 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov w0, w0 cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/local_array_partial_init_zero.x64.asm b/tests/snapshots/asm/local_array_partial_init_zero.x64.asm index 6f3bed646..6a3dca556 100644 --- a/tests/snapshots/asm/local_array_partial_init_zero.x64.asm +++ b/tests/snapshots/asm/local_array_partial_init_zero.x64.asm @@ -15,18 +15,14 @@ Disassembly of section .text: movq %rsp, %rbp subq $0xb0, %rsp xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x28, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0xa0(%rbp), %rax - movslq %ecx, %rdx + leaq -0xa0(%rbp), %rdx movl %edi, %esi - movl %esi, (%rax,%rdx,4) - jmp + movl %esi, (%rdx,%rax,4) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x28, %rax + jl leaq -0xa0(%rbp), %rax xorq %rcx, %rcx movl (%rax), %eax @@ -83,19 +79,15 @@ Disassembly of section .text: popq %rdx xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x19, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp movl %eax, %eax - leaq -0x68(%rbp), %rdx - movslq %ecx, %rsi - movl (%rdx,%rsi,4), %edx - addq %rdx, %rax - jmp + leaq -0x68(%rbp), %rsi + movl (%rsi,%rdx,4), %esi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq $0x19, %rdx + jl movl %eax, %eax addq $0x80, %rsp popq %rbp @@ -134,3 +126,5 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/local_array_runtime_init.aarch64.asm b/tests/snapshots/asm/local_array_runtime_init.aarch64.asm index 836396f96..483fcb779 100644 --- a/tests/snapshots/asm/local_array_runtime_init.aarch64.asm +++ b/tests/snapshots/asm/local_array_runtime_init.aarch64.asm @@ -152,21 +152,19 @@ Disassembly of section .text: mov x0, #0x64 // =100 sub x1, x29, #0x8 strb w0, [x1, #0x3] - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w1 - cmp x2, #0x4 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sub x2, x29, #0x8 - sxtw x3, w1 - add x2, x2, x3 - ldrb w2, [x2] - add x0, x0, x2 - b + sub x0, x29, #0x8 + add x0, x0, #0x0 + ldrb w0, [x0] + add x0, x0, #0x0 + sub x1, x29, #0x8 + ldrb w1, [x1, #0x1] + add x0, x0, x1 + sub x1, x29, #0x8 + ldrb w1, [x1, #0x2] + add x0, x0, x1 + sub x1, x29, #0x8 + ldrb w1, [x1, #0x3] + add x0, x0, x1 sxtw x0, w0 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 diff --git a/tests/snapshots/asm/local_array_runtime_init.x64.asm b/tests/snapshots/asm/local_array_runtime_init.x64.asm index 76845ea63..a2fad9afa 100644 --- a/tests/snapshots/asm/local_array_runtime_init.x64.asm +++ b/tests/snapshots/asm/local_array_runtime_init.x64.asm @@ -147,21 +147,19 @@ Disassembly of section .text: movl $0x64, %eax leaq -0x8(%rbp), %rcx movb %al, 0x3(%rcx) - xorq %rcx, %rcx - movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x4, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq -0x8(%rbp), %rdx - movslq %ecx, %rsi - addq %rsi, %rdx - movsbq (%rdx), %rdx - addq %rdx, %rax - jmp + leaq -0x8(%rbp), %rax + addq $0x0, %rax + movsbq (%rax), %rax + addq $0x0, %rax + leaq -0x8(%rbp), %rcx + movsbq 0x1(%rcx), %rcx + addq %rcx, %rax + leaq -0x8(%rbp), %rcx + movsbq 0x2(%rcx), %rcx + addq %rcx, %rax + leaq -0x8(%rbp), %rcx + movsbq 0x3(%rcx), %rcx + addq %rcx, %rax movslq %eax, %rax addq $0x20, %rsp popq %rbp @@ -282,3 +280,4 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/local_init_and_block_scope.aarch64.asm b/tests/snapshots/asm/local_init_and_block_scope.aarch64.asm index 71e5f0c6b..949c8eabd 100644 --- a/tests/snapshots/asm/local_init_and_block_scope.aarch64.asm +++ b/tests/snapshots/asm/local_init_and_block_scope.aarch64.asm @@ -19,40 +19,21 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x70 - mov x0, #0x0 // =0 - mov x1, #0x41 // =65 - adrp x2, - add x2, x2, - mov x3, #0x1 // =1 - stur w3, [x29, #-0x20] - mov x3, #0x3 // =3 - mov x4, #0x2 // =2 - cmp x0, #0x0 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x41 // =65 - eor x0, x1, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - ldrb w0, [x2] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + stur w1, [x29, #-0x20] + ldrb w1, [x0] mov x17, #0x68 // =104 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 b.eq mov x0, #0x3 // =3 add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2, #0x1] + ldrb w0, [x0, #0x1] mov x17, #0x69 // =105 eor x0, x0, x17 mov w0, w0 @@ -63,8 +44,8 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldursw x0, [x29, #-0x20] - add x0, x0, x4 - add x0, x0, x3 + add x0, x0, #0x2 + add x0, x0, #0x3 sxtw x0, w0 cmp x0, #0x6 b.eq @@ -73,8 +54,8 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldursw x0, [x29, #-0x20] - add x0, x0, x4 - add x0, x0, x3 + add x0, x0, #0x2 + add x0, x0, #0x3 sxtw x1, w0 sxtw x2, w1 cmp x2, #0x6 @@ -91,35 +72,7 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xa // =10 - mov x2, #0x14 // =20 - mov x3, #0x1e // =30 - add x0, x0, x2 - add x0, x0, x3 - sxtw x0, w0 - sxtw x0, w0 - cmp x0, #0x3c - b.eq - mov x0, #0x8 // =8 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x63 // =99 - cmp x0, #0x63 - b.eq - mov x0, #0x9 // =9 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7 // =7 - cmp x0, #0x7 - b.eq - mov x0, #0xa // =10 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - sxtw x0, w1 - cmp x0, #0x6 + cmp x2, #0x6 b.eq mov x0, #0xb // =11 add sp, sp, #0x70 @@ -165,3 +118,23 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xa // =10 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/local_init_and_block_scope.x64.asm b/tests/snapshots/asm/local_init_and_block_scope.x64.asm index 2ec84d571..4d6e7d2ec 100644 --- a/tests/snapshots/asm/local_init_and_block_scope.x64.asm +++ b/tests/snapshots/asm/local_init_and_block_scope.x64.asm @@ -20,33 +20,17 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x70, %rsp - xorq %rax, %rax - movl $0x41, %ecx - leaq , %rdx - movl $0x1, %esi - movl %esi, -0x20(%rbp) - movl $0x3, %esi - movl $0x2, %edi - testq %rax, %rax - je - movl $0x1, %eax - addq $0x70, %rsp - popq %rbp - retq - cmpq $0x41, %rcx - je - movl $0x2, %eax - addq $0x70, %rsp - popq %rbp - retq - movsbq (%rdx), %rax - cmpq $0x68, %rax + leaq , %rax + movl $0x1, %ecx + movl %ecx, -0x20(%rbp) + movsbq (%rax), %rcx + cmpq $0x68, %rcx je movl $0x3, %eax addq $0x70, %rsp popq %rbp retq - movsbq 0x1(%rdx), %rax + movsbq 0x1(%rax), %rax cmpq $0x69, %rax je movl $0x4, %eax @@ -54,8 +38,8 @@ Disassembly of section .text: popq %rbp retq movslq -0x20(%rbp), %rax - addq %rdi, %rax - addq %rsi, %rax + addq $0x2, %rax + addq $0x3, %rax movslq %eax, %rax cmpq $0x6, %rax je @@ -64,8 +48,8 @@ Disassembly of section .text: popq %rbp retq movslq -0x20(%rbp), %rax - addq %rdi, %rax - addq %rsi, %rax + addq $0x2, %rax + addq $0x3, %rax movslq %eax, %rcx movslq %ecx, %rdx cmpq $0x6, %rdx @@ -82,35 +66,7 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - movl $0xa, %eax - movl $0x14, %edx - movl $0x1e, %esi - addq %rdx, %rax - addq %rsi, %rax - movslq %eax, %rax - movslq %eax, %rax - cmpq $0x3c, %rax - je - movl $0x8, %eax - addq $0x70, %rsp - popq %rbp - retq - movl $0x63, %eax - cmpq $0x63, %rax - je - movl $0x9, %eax - addq $0x70, %rsp - popq %rbp - retq - movl $0x7, %eax - cmpq $0x7, %rax - je - movl $0xa, %eax - addq $0x70, %rsp - popq %rbp - retq - movslq %ecx, %rax - cmpq $0x6, %rax + cmpq $0x6, %rdx je movl $0xb, %eax addq $0x70, %rsp @@ -156,4 +112,23 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + movl $0x1, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x9, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0xa, %eax + addq $0x70, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/local_init_int_to_float.aarch64.asm b/tests/snapshots/asm/local_init_int_to_float.aarch64.asm index b3937b0d7..dcd987bdb 100644 --- a/tests/snapshots/asm/local_init_int_to_float.aarch64.asm +++ b/tests/snapshots/asm/local_init_int_to_float.aarch64.asm @@ -10,12 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xc0 - str d8, [sp] - str x20, [sp, #0x10] - str x19, [sp, #0x20] + str x19, [sp, #-0xb0]! + stp x29, x30, [sp, #0xa0] + add x29, sp, #0xa0 sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -32,133 +29,109 @@ Disassembly of section .text: sub x0, x29, #0x8 ldrb w0, [x0] scvtf d0, x0 - fcvt s8, d0 - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0xf333, lsl #32 - movk x0, #0x4044, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, mi - cbnz x20, - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xccc, lsl #32 - movk x0, #0x4045, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, gt - cbz x20, + fcvt s0, d0 + mov x0, #0x999a // =39322 + movk x0, #0x4227, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, mi + cbnz x1, + mov x0, #0x6666 // =26214 + movk x0, #0x4228, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, gt + cbz x1, adrp x0, add x0, x0, - fcvt d0, s8 + fcvt d0, s0 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0x3039 // =12345 scvtf d0, x0 - fcvt s8, d0 - mov x0, #0x1c4000000000 // =31061203484672 - movk x0, #0x40c8, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, mi - cbnz x20, - mov x0, #0x1cc000000000 // =31610959298560 - movk x0, #0x40c8, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, gt - cbz x20, + fcvt s0, d0 + mov x0, #0xe200 // =57856 + movk x0, #0x4640, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, mi + cbnz x1, + mov x0, #0xe600 // =58880 + movk x0, #0x4640, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, gt + cbz x1, adrp x0, add x0, x0, - fcvt d0, s8 + fcvt d0, s0 bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0xfff9 // =65529 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - scvtf d8, x0 + scvtf d0, x0 mov x0, #0x401e000000000000 // =4620130267728707584 fmov d16, x0 - fneg d0, d16 - fcmp d8, d0 - cset x20, mi - cbnz x20, + fneg d1, d16 + fcmp d0, d1 + cset x1, mi + cbnz x1, mov x0, #0x401a000000000000 // =4619004367821864960 fmov d16, x0 - fneg d0, d16 - fcmp d8, d0 - cset x20, gt - cbz x20, + fneg d1, d16 + fcmp d0, d1 + cset x1, gt + cbz x1, adrp x0, add x0, x0, - fmov d0, d8 bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 scvtf d0, x0 - fcvt s8, d0 - mov x0, #0x90000000 // =2415919104 - movk x0, #0xf686, lsl #32 - movk x0, #0x41ef, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, mi - cbnz x20, - mov x0, #0xb0000000 // =2952790016 - movk x0, #0x4cc, lsl #32 - movk x0, #0x41f0, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 - cset x20, gt - cbz x20, + fcvt s0, d0 + mov x0, #0xb434 // =46132 + movk x0, #0x4f7f, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, mi + cbnz x1, + mov x0, #0x2666 // =9830 + movk x0, #0x4f80, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x1, gt + cbz x1, adrp x0, add x0, x0, - fcvt d0, s8 + fcvt d0, s0 bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x400d, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x406c, lsl #16 + fmov s16, w0 + sub x17, x29, #0x48 + str s16, [x17] + sub x16, x29, #0x48 + ldr s0, [x16] fcvt d0, s0 fcvtzs x0, d0 sxtw x1, w0 @@ -173,11 +146,8 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0x3333 // =13107 movk x0, #0x3333, lsl #16 @@ -202,18 +172,12 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x6 // =6 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret b b diff --git a/tests/snapshots/asm/local_init_int_to_float.x64.asm b/tests/snapshots/asm/local_init_int_to_float.x64.asm index afb7abe35..2ce572991 100644 --- a/tests/snapshots/asm/local_init_int_to_float.x64.asm +++ b/tests/snapshots/asm/local_init_int_to_float.x64.asm @@ -13,8 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xb0, %rsp - movq %rbx, (%rsp) + subq $0x90, %rsp leaq -0x8(%rbp), %rax leaq , %rcx pushq %rdx @@ -30,153 +29,128 @@ Disassembly of section .text: leaq -0x8(%rbp), %rax movzbq (%rax), %rax cvtsi2sd %rax, %xmm0 - cvtsd2ss %xmm0, %xmm14 - movsd %xmm14, 0x18(%rsp) - movabsq $0x4044f33333333333, %rax # imm = 0x4044F33333333333 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x4227999a, %eax # imm = 0x4227999A movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setb %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx jne - movabsq $0x40450ccccccccccd, %rax # imm = 0x40450CCCCCCCCCCD - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movl $0x42286666, %eax # imm = 0x42286666 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + ucomiss %xmm15, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je leaq , %rdi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq movl $0x3039, %eax # imm = 0x3039 cvtsi2sd %rax, %xmm0 - cvtsd2ss %xmm0, %xmm14 - movsd %xmm14, 0x18(%rsp) - movabsq $0x40c81c4000000000, %rax # imm = 0x40C81C4000000000 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x4640e200, %eax # imm = 0x4640E200 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setb %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx jne - movabsq $0x40c81cc000000000, %rax # imm = 0x40C81CC000000000 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movl $0x4640e600, %eax # imm = 0x4640E600 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + ucomiss %xmm15, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je leaq , %rdi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0x2, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq movabsq $-0x7, %rax - cvtsi2sd %rax, %xmm14 - movsd %xmm14, 0x18(%rsp) + cvtsi2sd %rax, %xmm0 movabsq $0x401e000000000000, %rax # imm = 0x401E000000000000 - movq %rax, %xmm0 + movq %rax, %xmm1 movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm0 - movsd 0x18(%rsp), %xmm14 - ucomisd %xmm0, %xmm14 - setb %bl - movzbq %bl, %rbx + xorpd %xmm15, %xmm1 + ucomisd %xmm1, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx jne movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 - movq %rax, %xmm0 + movq %rax, %xmm1 movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm0 - movsd 0x18(%rsp), %xmm14 - ucomisd %xmm0, %xmm14 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + xorpd %xmm15, %xmm1 + ucomisd %xmm1, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je leaq , %rdi - movsd 0x18(%rsp), %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0x3, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq movl $0xffffffff, %eax # imm = 0xFFFFFFFF cvtsi2sd %rax, %xmm0 - cvtsd2ss %xmm0, %xmm14 - movsd %xmm14, 0x18(%rsp) - movabsq $0x41eff68690000000, %rax # imm = 0x41EFF68690000000 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x4f7fb434, %eax # imm = 0x4F7FB434 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setb %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx jne - movabsq $0x41f004ccb0000000, %rax # imm = 0x41F004CCB0000000 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movl $0x4f802666, %eax # imm = 0x4F802666 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + ucomiss %xmm15, %xmm0 + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je leaq , %rdi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0x4, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq - movabsq $0x400d99999999999a, %rax # imm = 0x400D99999999999A + movl $0x406ccccd, %eax # imm = 0x406CCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x48(%rbp,%riz) + movss -0x48(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax movslq %eax, %rcx @@ -188,8 +162,7 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x5, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 @@ -207,13 +180,11 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x6, %eax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0xb0, %rsp + addq $0x90, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/local_struct_array_brace_init.aarch64.asm b/tests/snapshots/asm/local_struct_array_brace_init.aarch64.asm index 473fba6df..8a168fe24 100644 --- a/tests/snapshots/asm/local_struct_array_brace_init.aarch64.asm +++ b/tests/snapshots/asm/local_struct_array_brace_init.aarch64.asm @@ -10,28 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x1, w1 mov x3, #0x0 // =0 mov x2, x3 - sxtw x4, w3 - cmp x4, x1 - b.ge - b - sxtw x3, w3 - add x3, x3, #0x1 b + lsl x5, x4, #4 + add x5, x0, x5 + ldr x5, [x5, #0x8] + add x2, x2, x5 + add x3, x4, #0x1 sxtw x4, w3 - lsl x4, x4, #4 - add x4, x0, x4 - ldr x4, [x4, #0x8] - add x2, x2, x4 - b + cmp x4, x1 + b.lt mov x0, x2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: diff --git a/tests/snapshots/asm/local_struct_array_brace_init.x64.asm b/tests/snapshots/asm/local_struct_array_brace_init.x64.asm index a992093a8..9ef6a9f37 100644 --- a/tests/snapshots/asm/local_struct_array_brace_init.x64.asm +++ b/tests/snapshots/asm/local_struct_array_brace_init.x64.asm @@ -11,27 +11,19 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %esi, %rsi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq %rsi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp + movq %rdx, %r8 + shlq $0x4, %r8 + addq %rdi, %r8 + movq 0x8(%r8), %r8 + addq %r8, %rax + leaq 0x1(%rdx), %rcx movslq %ecx, %rdx - shlq $0x4, %rdx - addq %rdi, %rdx - movq 0x8(%rdx), %rdx - addq %rdx, %rax - jmp - addq $0x10, %rsp - popq %rbp + cmpq %rsi, %rdx + jl retq
: @@ -161,3 +153,4 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/logical_not_float.aarch64.asm b/tests/snapshots/asm/logical_not_float.aarch64.asm index f1fc69365..66d40040f 100644 --- a/tests/snapshots/asm/logical_not_float.aarch64.asm +++ b/tests/snapshots/asm/logical_not_float.aarch64.asm @@ -17,16 +17,11 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x0 // =0 fcvt d0, s0 fmov d17, x0 fcmp d0, d17 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: @@ -86,11 +81,10 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x0 // =0 - fcvt d0, s0 - fmov d17, x0 + mov x1, #0x0 // =0 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fcmp d0, d17 cset x0, eq cmp x0, #0x1 @@ -99,12 +93,11 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x0 // =0 - fcvt d0, s0 - fmov d17, x0 + mov x0, #0x40600000 // =1080033280 + mov x1, #0x0 // =0 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fcmp d0, d17 cset x0, eq cmp x0, #0x0 diff --git a/tests/snapshots/asm/logical_not_float.x64.asm b/tests/snapshots/asm/logical_not_float.x64.asm index b3587c9d1..dc3957aaf 100644 --- a/tests/snapshots/asm/logical_not_float.x64.asm +++ b/tests/snapshots/asm/logical_not_float.x64.asm @@ -22,9 +22,6 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rax, %rax cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 @@ -34,8 +31,6 @@ Disassembly of section .text: setnp %r10b movzbq %r10b, %r10 andq %r10, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -110,11 +105,10 @@ Disassembly of section .text: popq %rbp retq xorq %rax, %rax + xorq %rcx, %rcx movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 ucomisd %xmm15, %xmm0 sete %al movzbq %al, %rax @@ -127,12 +121,11 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 + xorq %rcx, %rcx movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 ucomisd %xmm15, %xmm0 sete %al movzbq %al, %rax diff --git a/tests/snapshots/asm/logical_op_normalize.aarch64.asm b/tests/snapshots/asm/logical_op_normalize.aarch64.asm index d8b739c10..7fcfefe46 100644 --- a/tests/snapshots/asm/logical_op_normalize.aarch64.asm +++ b/tests/snapshots/asm/logical_op_normalize.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x1, w1 mov x3, #0x1 // =1 cbnz x0, @@ -21,15 +18,10 @@ Disassembly of section .text: cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x0 cset x0, gt @@ -38,15 +30,10 @@ Disassembly of section .text: cmp x1, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x1, w1 mov x3, #0x0 // =0 cbz x0, @@ -55,15 +42,10 @@ Disassembly of section .text: cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 sxtw x1, w1 mov x3, #0x0 // =0 @@ -71,17 +53,13 @@ Disassembly of section .text: cmp x1, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 adrp x0, add x0, x0, ldrsw x20, [x0] @@ -91,10 +69,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x0 // =0 mov x1, #0x5 // =5 @@ -102,10 +78,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x0 // =0 mov x1, x20 @@ -113,10 +87,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x5 // =5 mov x1, #0x7 // =7 @@ -124,10 +96,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x5 // =5 mov x1, #0x0 // =0 @@ -135,10 +105,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x10 adrp x1, @@ -155,10 +123,8 @@ Disassembly of section .text: cmp x0, #0x14 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret sub x21, x29, #0x10 mov x0, #0x0 // =0 @@ -168,10 +134,8 @@ Disassembly of section .text: cmp x0, #0xa b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x1, #0x1 // =1 cbnz x20, @@ -182,10 +146,8 @@ Disassembly of section .text: cmp x2, #0x1 b.eq mov x0, #0x8 // =8 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x2, #0x0 // =0 mov x2, #0x1 // =1 @@ -195,16 +157,12 @@ Disassembly of section .text: cmp x1, #0x1 b.eq mov x0, #0x9 // =9 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret b b diff --git a/tests/snapshots/asm/logical_op_normalize.x64.asm b/tests/snapshots/asm/logical_op_normalize.x64.asm index 543917267..4e1fe8a70 100644 --- a/tests/snapshots/asm/logical_op_normalize.x64.asm +++ b/tests/snapshots/asm/logical_op_normalize.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %esi, %rsi movl $0x1, %ecx testq %rdi, %rdi @@ -25,15 +22,10 @@ Disassembly of section .text: setne %cl movzbq %cl, %rcx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi testq %rdi, %rdi setg %al @@ -45,15 +37,10 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %esi, %rsi xorq %rcx, %rcx testq %rdi, %rdi @@ -65,15 +52,10 @@ Disassembly of section .text: setne %cl movzbq %cl, %rcx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi movslq %esi, %rsi xorq %rcx, %rcx @@ -83,8 +65,6 @@ Disassembly of section .text: setne %cl movzbq %cl, %rcx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq jmp diff --git a/tests/snapshots/asm/long_double_libc_return.aarch64.asm b/tests/snapshots/asm/long_double_libc_return.aarch64.asm index d87f86496..0137668db 100644 --- a/tests/snapshots/asm/long_double_libc_return.aarch64.asm +++ b/tests/snapshots/asm/long_double_libc_return.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x0 // =0 @@ -25,9 +24,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -40,9 +38,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x3ff0000000000000 // =4607182418800017408 mov x1, #0x35 // =53 @@ -55,12 +52,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0xd // =13 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/long_double_libc_return.x64.asm b/tests/snapshots/asm/long_double_libc_return.x64.asm index 69bdfcc6c..060aaa636 100644 --- a/tests/snapshots/asm/long_double_libc_return.x64.asm +++ b/tests/snapshots/asm/long_double_libc_return.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp leaq , %rdi xorq %rsi, %rsi xorl %eax, %eax @@ -34,7 +33,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0xb, %eax - addq $0x30, %rsp popq %rbp retq leaq , %rdi @@ -57,7 +55,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0xc, %eax - addq $0x30, %rsp popq %rbp retq movabsq $0x3ff0000000000000, %rdi # imm = 0x3FF0000000000000 @@ -77,12 +74,9 @@ Disassembly of section .text: testq %rax, %rax je movl $0xd, %eax - addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/long_long_distinct.aarch64.asm b/tests/snapshots/asm/long_long_distinct.aarch64.asm index 6719db7f6..ca0856e3e 100644 --- a/tests/snapshots/asm/long_long_distinct.aarch64.asm +++ b/tests/snapshots/asm/long_long_distinct.aarch64.asm @@ -10,80 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x19, [sp] - b - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xcdef // =52719 - movk x0, #0x89ab, lsl #16 - movk x0, #0x4567, lsl #32 - movk x0, #0x123, lsl #48 - mov x17, #0xcdef // =52719 - movk x17, #0x89ab, lsl #16 - movk x17, #0x4567, lsl #32 - movk x17, #0x123, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x64 // =100 - mov x1, #0xc8 // =200 - add x0, x0, x1 - cmp x0, #0x12c - b.eq - mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x40 mov x1, #0xa // =10 str x1, [x0] @@ -98,17 +27,15 @@ Disassembly of section .text: cmp x1, #0x14 b.eq mov x0, #0x9 // =9 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret ldr x0, [x0, #0x10] cmp x0, #0x1e b.eq mov x0, #0xa // =10 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret sub x0, x29, #0x60 mov x1, #0x64 // =100 @@ -124,24 +51,53 @@ Disassembly of section .text: cmp x1, #0xc8 b.eq mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret ldr x0, [x0, #0x10] cmp x0, #0x12c b.eq mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x4 // =4 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x5 // =5 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x6 // =6 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x7 // =7 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 + ret + mov x0, #0x8 // =8 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret diff --git a/tests/snapshots/asm/long_long_distinct.x64.asm b/tests/snapshots/asm/long_long_distinct.x64.asm index 93151b009..39a3a2a69 100644 --- a/tests/snapshots/asm/long_long_distinct.x64.asm +++ b/tests/snapshots/asm/long_long_distinct.x64.asm @@ -14,55 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x70, %rsp - jmp - movl $0x1, %eax - addq $0x70, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x70, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x70, %rsp - popq %rbp - retq - jmp - movl $0x4, %eax - addq $0x70, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x70, %rsp - popq %rbp - retq - movabsq $0x123456789abcdef, %rax # imm = 0x123456789ABCDEF - movabsq $0x123456789abcdef, %r11 # imm = 0x123456789ABCDEF - cmpq %r11, %rax - je - movl $0x6, %eax - addq $0x70, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - cmpq $-0x1, %rax - je - movl $0x7, %eax - addq $0x70, %rsp - popq %rbp - retq - movl $0x64, %eax - movl $0xc8, %ecx - addq %rcx, %rax - cmpq $0x12c, %rax # imm = 0x12C - je - movl $0x8, %eax - addq $0x70, %rsp - popq %rbp - retq leaq -0x40(%rbp), %rax movl $0xa, %ecx movq %rcx, (%rax) @@ -119,3 +70,35 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x7, %eax + addq $0x70, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x70, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/lp64_predefine.aarch64.asm b/tests/snapshots/asm/lp64_predefine.aarch64.asm index 5dd5125ee..28187d6a8 100644 --- a/tests/snapshots/asm/lp64_predefine.aarch64.asm +++ b/tests/snapshots/asm/lp64_predefine.aarch64.asm @@ -10,18 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - b - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret mov x1, #0x0 // =0 - b - mov x1, #0x3 // =3 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ret + mov x1, #0x3 // =3 + b diff --git a/tests/snapshots/asm/lp64_predefine.x64.asm b/tests/snapshots/asm/lp64_predefine.x64.asm index f59b6e8af..2e835c014 100644 --- a/tests/snapshots/asm/lp64_predefine.x64.asm +++ b/tests/snapshots/asm/lp64_predefine.x64.asm @@ -11,20 +11,10 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - jmp - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq xorq %rcx, %rcx - jmp - movl $0x3, %ecx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) + movl $0x1, %eax + retq + movl $0x3, %ecx + jmp diff --git a/tests/snapshots/asm/macro_argument_rescan.aarch64.asm b/tests/snapshots/asm/macro_argument_rescan.aarch64.asm index 8dfad36be..a41a66124 100644 --- a/tests/snapshots/asm/macro_argument_rescan.aarch64.asm +++ b/tests/snapshots/asm/macro_argument_rescan.aarch64.asm @@ -10,14 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/macro_argument_rescan.x64.asm b/tests/snapshots/asm/macro_argument_rescan.x64.asm index 6582587c4..5c21f8d91 100644 --- a/tests/snapshots/asm/macro_argument_rescan.x64.asm +++ b/tests/snapshots/asm/macro_argument_rescan.x64.asm @@ -11,14 +11,12 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/macro_multiline_comment_body.aarch64.asm b/tests/snapshots/asm/macro_multiline_comment_body.aarch64.asm index a63ae4a95..657c46b6c 100644 --- a/tests/snapshots/asm/macro_multiline_comment_body.aarch64.asm +++ b/tests/snapshots/asm/macro_multiline_comment_body.aarch64.asm @@ -11,17 +11,10 @@ Disassembly of section .text: b brk #: mov x1, #0x0 // =0 - b - b mov x1, #0x7 // =7 - b - b sxtw x0, w1 cmp x0, #0x7 b.eq - b - mov x1, #0x63 // =99 - b mov x0, #0x1 // =1 ret adrp x0, @@ -33,3 +26,5 @@ Disassembly of section .text: ret mov x0, #0x0 // =0 ret + mov x1, #0x63 // =99 + b diff --git a/tests/snapshots/asm/macro_multiline_comment_body.x64.asm b/tests/snapshots/asm/macro_multiline_comment_body.x64.asm index f5ec17cad..566fdcaba 100644 --- a/tests/snapshots/asm/macro_multiline_comment_body.x64.asm +++ b/tests/snapshots/asm/macro_multiline_comment_body.x64.asm @@ -12,17 +12,10 @@ Disassembly of section .text:
: xorq %rcx, %rcx - jmp - jmp movl $0x7, %ecx - jmp - jmp movslq %ecx, %rax cmpq $0x7, %rax je - jmp - movl $0x63, %ecx - jmp movl $0x1, %eax retq leaq , %rax @@ -33,3 +26,6 @@ Disassembly of section .text: retq xorq %rax, %rax retq + movl $0x63, %ecx + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/macro_operators.aarch64.asm b/tests/snapshots/asm/macro_operators.aarch64.asm index 92a0db03a..3b8b04cb9 100644 --- a/tests/snapshots/asm/macro_operators.aarch64.asm +++ b/tests/snapshots/asm/macro_operators.aarch64.asm @@ -16,10 +16,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, ldrb w1, [x0] @@ -29,9 +28,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x1] mov x17, #0x65 // =101 @@ -40,9 +38,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x2] mov x17, #0x6c // =108 @@ -51,9 +48,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x3] mov x17, #0x6c // =108 @@ -62,9 +58,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x4] mov x17, #0x6f // =111 @@ -73,39 +68,15 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w0, [x0, #0x5] cmp x0, #0x0 b.eq mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x2a // =42 - cmp x0, #0x2a - b.eq - mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - add x0, x0, x1 - add x0, x0, x2 - sxtw x0, w0 - sxtw x0, w0 - cmp x0, #0x6 - b.eq - mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -115,7 +86,14 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x7 // =7 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret + mov x0, #0x8 // =8 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/macro_operators.x64.asm b/tests/snapshots/asm/macro_operators.x64.asm index 308f8cf7f..4396c7ca5 100644 --- a/tests/snapshots/asm/macro_operators.x64.asm +++ b/tests/snapshots/asm/macro_operators.x64.asm @@ -19,68 +19,41 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movsbq (%rax), %rcx cmpq $0x68, %rcx je movl $0x1, %eax - addq $0x40, %rsp popq %rbp retq movsbq 0x1(%rax), %rcx cmpq $0x65, %rcx je movl $0x2, %eax - addq $0x40, %rsp popq %rbp retq movsbq 0x2(%rax), %rcx cmpq $0x6c, %rcx je movl $0x3, %eax - addq $0x40, %rsp popq %rbp retq movsbq 0x3(%rax), %rcx cmpq $0x6c, %rcx je movl $0x4, %eax - addq $0x40, %rsp popq %rbp retq movsbq 0x4(%rax), %rcx cmpq $0x6f, %rcx je movl $0x5, %eax - addq $0x40, %rsp popq %rbp retq movsbq 0x5(%rax), %rax testq %rax, %rax je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp - retq - movl $0x2a, %eax - cmpq $0x2a, %rax - je - movl $0x7, %eax - addq $0x40, %rsp - popq %rbp - retq - movl $0x1, %eax - movl $0x2, %ecx - movl $0x3, %edx - addq %rcx, %rax - addq %rdx, %rax - movslq %eax, %rax - movslq %eax, %rax - cmpq $0x6, %rax - je - movl $0x8, %eax - addq $0x40, %rsp popq %rbp retq leaq , %rdi @@ -91,7 +64,12 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - addq $0x40, %rsp + popq %rbp + retq + movl $0x7, %eax + popq %rbp + retq + movl $0x8, %eax popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/macro_paste_rescan.aarch64.asm b/tests/snapshots/asm/macro_paste_rescan.aarch64.asm index 8a5acb561..1e86293f3 100644 --- a/tests/snapshots/asm/macro_paste_rescan.aarch64.asm +++ b/tests/snapshots/asm/macro_paste_rescan.aarch64.asm @@ -10,20 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - b mov x0, #0xf // =15 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/macro_paste_rescan.x64.asm b/tests/snapshots/asm/macro_paste_rescan.x64.asm index e1e31eef1..ffc92d5ad 100644 --- a/tests/snapshots/asm/macro_paste_rescan.x64.asm +++ b/tests/snapshots/asm/macro_paste_rescan.x64.asm @@ -11,20 +11,16 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - jmp movl $0xf, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/macro_paste_stringize_unexpanded.aarch64.asm b/tests/snapshots/asm/macro_paste_stringize_unexpanded.aarch64.asm index 5602a1d68..2b696afcf 100644 --- a/tests/snapshots/asm/macro_paste_stringize_unexpanded.aarch64.asm +++ b/tests/snapshots/asm/macro_paste_stringize_unexpanded.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 adrp x0, add x0, x0, mov x1, #0x1 // =1 @@ -28,8 +25,6 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -65,27 +60,13 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7 // =7 - cmp x0, #0x7 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x9 // =9 - cmp x0, #0x9 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b b + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret diff --git a/tests/snapshots/asm/macro_paste_stringize_unexpanded.x64.asm b/tests/snapshots/asm/macro_paste_stringize_unexpanded.x64.asm index 3bc557c5d..abf0d6fa9 100644 --- a/tests/snapshots/asm/macro_paste_stringize_unexpanded.x64.asm +++ b/tests/snapshots/asm/macro_paste_stringize_unexpanded.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp leaq , %rax movl $0x1, %ecx movl %ecx, (%rax) @@ -27,8 +24,6 @@ Disassembly of section .text: cmpq $0x3, %rax je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rcx @@ -64,28 +59,15 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp - retq - movl $0x7, %eax - cmpq $0x7, %rax - je - movl $0x3, %eax - addq $0x30, %rsp - popq %rbp - retq - movl $0x9, %eax - cmpq $0x9, %rax - je - movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp jmp + movl $0x3, %eax + retq + movl $0x4, %eax + retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/many_fp_args.aarch64.asm b/tests/snapshots/asm/many_fp_args.aarch64.asm index 2b407d63b..aa278e9a2 100644 --- a/tests/snapshots/asm/many_fp_args.aarch64.asm +++ b/tests/snapshots/asm/many_fp_args.aarch64.asm @@ -16,10 +16,9 @@ Disassembly of section .text: ldr x16, [sp, #0x28] str x16, [sp, #0x10] sub sp, sp, #0x80 - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str d8, [sp] + str d8, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 fadd d0, d0, d1 fadd d0, d0, d2 fadd d0, d0, d3 @@ -31,16 +30,14 @@ Disassembly of section .text: fadd d0, d0, d1 ldr d1, [x29, #0xa0] fadd d0, d0, d1 - ldr d8, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr d8, [sp], #0x20 add sp, sp, #0xa0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x60 mov x0, #0x3ff0000000000000 // =4607182418800017408 mov x1, #0x4000000000000000 // =4611686018427387904 mov x2, #0x4008000000000000 // =4613937818241073152 @@ -71,7 +68,6 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x3fe0000000000000 // =4602678819172646912 @@ -96,10 +92,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/many_fp_args.x64.asm b/tests/snapshots/asm/many_fp_args.x64.asm index 79ef0b38a..a9d5ff710 100644 --- a/tests/snapshots/asm/many_fp_args.x64.asm +++ b/tests/snapshots/asm/many_fp_args.x64.asm @@ -42,7 +42,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -83,7 +83,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x80, %rsp + addq $0x20, %rsp popq %rbp retq movabsq $0x3fe0000000000000, %rdi # imm = 0x3FE0000000000000 @@ -116,14 +116,14 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x80, %rsp + addq $0x20, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x80, %rsp + addq $0x20, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/math_classify.aarch64.asm b/tests/snapshots/asm/math_classify.aarch64.asm index 14768c97c..d8ec645bf 100644 --- a/tests/snapshots/asm/math_classify.aarch64.asm +++ b/tests/snapshots/asm/math_classify.aarch64.asm @@ -31,28 +31,25 @@ Disassembly of section .text: b.ne cmp x1, #0x0 b.ne - b - cmp x0, #0x7ff - b.ne - b mov x1, #0x2 // =2 - b - mov x1, #0x3 // =3 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x3 // =3 + b + cmp x0, #0x7ff + b.ne cmp x1, #0x0 b.ne - b - mov x0, #0x4 // =4 + mov x1, #0x1 // =1 + mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x1, #0x1 // =1 - b mov x1, #0x0 // =0 - mov x0, x1 + b + mov x0, #0x4 // =4 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret @@ -99,12 +96,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str d8, [sp] - str d9, [sp, #0x8] + stp d8, d9, [sp, #-0x60]! str d10, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x0, #0x0 // =0 fmov d16, x0 sub x17, x29, #0x8 @@ -123,75 +118,61 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x0 bl cbz x0, mov x0, #0x2 // =2 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d9 bl cbz x0, mov x0, #0x3 // =3 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d9 bl cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d10 bl cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x0 bl cbz x0, mov x0, #0x6 // =6 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d8 bl cbz x0, mov x0, #0x7 // =7 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x0 @@ -199,11 +180,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x8 // =8 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x0 // =0 fmov d0, x0 @@ -211,53 +190,43 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x9 // =9 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d9 bl cbz x0, mov x0, #0xa // =10 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d8 bl cbz x0, mov x0, #0xb // =11 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d8 bl cmp x0, #0x0 b.eq mov x0, #0xc // =12 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d9 bl cmp x0, #0x1 b.eq mov x0, #0xd // =13 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x0 @@ -265,38 +234,30 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0xe // =14 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret fmov d0, d10 bl cmp x0, #0x0 b.ne mov x0, #0xf // =15 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d0, x0 bl cbz x0, mov x0, #0x10 // =16 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr d8, [sp] - ldr d9, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr d10, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp d8, d9, [sp], #0x60 ret diff --git a/tests/snapshots/asm/math_classify.x64.asm b/tests/snapshots/asm/math_classify.x64.asm index 260477607..3d553a500 100644 --- a/tests/snapshots/asm/math_classify.x64.asm +++ b/tests/snapshots/asm/math_classify.x64.asm @@ -28,28 +28,25 @@ Disassembly of section .text: jne testq %rcx, %rcx jne - jmp - cmpq $0x7ff, %rax # imm = 0x7FF - jne - jmp movl $0x2, %ecx - jmp - movl $0x3, %ecx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x3, %ecx + jmp + cmpq $0x7ff, %rax # imm = 0x7FF + jne testq %rcx, %rcx jne - jmp - movl $0x4, %eax + movl $0x1, %ecx + movq %rcx, %rax addq $0x30, %rsp popq %rbp retq - movl $0x1, %ecx - jmp xorq %rcx, %rcx - movq %rcx, %rax + jmp + movl $0x4, %eax addq $0x30, %rsp popq %rbp retq @@ -258,4 +255,5 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mcpy_temp_aliases_src.aarch64.asm b/tests/snapshots/asm/mcpy_temp_aliases_src.aarch64.asm index f8900850e..1729121a9 100644 --- a/tests/snapshots/asm/mcpy_temp_aliases_src.aarch64.asm +++ b/tests/snapshots/asm/mcpy_temp_aliases_src.aarch64.asm @@ -13,45 +13,19 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x80 - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - mov x3, #0x4 // =4 - mov x4, #0x5 // =5 - mov x5, #0x6 // =6 - mov x6, #0x7 // =7 - mov x7, #0x8 // =8 - mov x8, #0x9 // =9 - mov x9, #0xa // =10 - add x0, x0, x1 - add x0, x0, x2 - add x0, x0, x3 - add x0, x0, x4 - add x0, x0, x5 - add x0, x0, x6 - add x0, x0, x7 - add x0, x0, x8 - add x0, x0, x9 - sxtw x0, w0 - sub x1, x29, #0x20 - adrp x2, - add x2, x2, + sub x0, x29, #0x20 + adrp x1, + add x1, x1, str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x1] - ldr x10, [x2, #0x8] - str x10, [x1, #0x8] - ldr x10, [x2, #0x10] - str x10, [x1, #0x10] - ldr x10, [x2, #0x18] - str x10, [x1, #0x18] + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [x1, #0x10] + str x10, [x0, #0x10] + ldr x10, [x1, #0x18] + str x10, [x0, #0x18] ldr x10, [sp], #0x10 - cmp x0, #0x37 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x20 ldr x0, [x0] mov x17, #0x1111 // =4369 @@ -92,3 +66,7 @@ Disassembly of section .text: add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/mcpy_temp_aliases_src.x64.asm b/tests/snapshots/asm/mcpy_temp_aliases_src.x64.asm index b42379b52..3edcc3c64 100644 --- a/tests/snapshots/asm/mcpy_temp_aliases_src.x64.asm +++ b/tests/snapshots/asm/mcpy_temp_aliases_src.x64.asm @@ -13,63 +13,25 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xa0, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movq %r14, 0x18(%rsp) - movl $0x1, %eax - movl $0x2, %ecx - movl $0x3, %edx - movl $0x4, %esi - movl $0x5, %edi - movl $0x6, %r8d - movl $0x7, %r9d - movl $0x8, %ebx - movl $0x9, %r12d - movl $0xa, %r13d - addq %rcx, %rax - addq %rdx, %rax - addq %rsi, %rax - addq %rdi, %rax - addq %r8, %rax - addq %r9, %rax - addq %rbx, %rax - addq %r12, %rax - addq %r13, %rax - movslq %eax, %rax - leaq -0x20(%rbp), %rcx - leaq , %rdx - pushq %rax - movq (%rdx), %rax - movq %rax, (%rcx) - movq 0x8(%rdx), %rax - movq %rax, 0x8(%rcx) - movq 0x10(%rdx), %rax - movq %rax, 0x10(%rcx) - movq 0x18(%rdx), %rax - movq %rax, 0x18(%rcx) - popq %rax - cmpq $0x37, %rax - je - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp - popq %rbp - retq + subq $0x80, %rsp + leaq -0x20(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + movq 0x10(%rcx), %rdx + movq %rdx, 0x10(%rax) + movq 0x18(%rcx), %rdx + movq %rdx, 0x18(%rax) + popq %rdx leaq -0x20(%rbp), %rax movq (%rax), %rax cmpq $0x1111, %rax # imm = 0x1111 je movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp + addq $0x80, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -77,11 +39,7 @@ Disassembly of section .text: cmpq $0x2222, %rax # imm = 0x2222 je movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp + addq $0x80, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -89,11 +47,7 @@ Disassembly of section .text: cmpq $0x3333, %rax # imm = 0x3333 je movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp + addq $0x80, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -101,20 +55,15 @@ Disassembly of section .text: cmpq $0x4444, %rax # imm = 0x4444 je movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp + addq $0x80, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp + addq $0x80, %rsp + popq %rbp + retq + movl $0x1, %eax + addq $0x80, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_addr_taken_neighbor.aarch64.asm b/tests/snapshots/asm/mem2reg_addr_taken_neighbor.aarch64.asm index 5780231d4..027c1d1ed 100644 --- a/tests/snapshots/asm/mem2reg_addr_taken_neighbor.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_addr_taken_neighbor.aarch64.asm @@ -13,19 +13,19 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x3, #0x0 // =0 - stur w3, [x29, #-0x8] + mov x1, #0x0 // =0 + stur w1, [x29, #-0x8] lsl x0, x0, #1 - sub x1, x29, #0x8 - sxtw x2, w3 - cmp x2, #0x3 - b.ge - ldrsw x2, [x1] - add x2, x2, x0 - str w2, [x1] - add x2, x3, #0x1 - sxtw x3, w2 - b + sub x2, x29, #0x8 + ldrsw x1, [x2] + add x1, x1, x0 + str w1, [x2] + sxtw x1, w1 + add x1, x1, x0 + str w1, [x2] + sxtw x1, w1 + add x0, x1, x0 + str w0, [x2] ldursw x0, [x29, #-0x8] add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 diff --git a/tests/snapshots/asm/mem2reg_addr_taken_neighbor.x64.asm b/tests/snapshots/asm/mem2reg_addr_taken_neighbor.x64.asm index b06dfd224..4e4847292 100644 --- a/tests/snapshots/asm/mem2reg_addr_taken_neighbor.x64.asm +++ b/tests/snapshots/asm/mem2reg_addr_taken_neighbor.x64.asm @@ -14,20 +14,20 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - xorq %rsi, %rsi - movl %esi, -0x8(%rbp) - movq %rdi, %rax - shlq $0x1, %rax - leaq -0x8(%rbp), %rcx - movslq %esi, %rdx - cmpq $0x3, %rdx - jge - movslq (%rcx), %rdx - addq %rax, %rdx - movl %edx, (%rcx) - leaq 0x1(%rsi), %rdx - movslq %edx, %rsi - jmp + xorq %rax, %rax + movl %eax, -0x8(%rbp) + movq %rdi, %rcx + shlq $0x1, %rcx + leaq -0x8(%rbp), %rdx + movslq (%rdx), %rax + addq %rcx, %rax + movl %eax, (%rdx) + movslq %eax, %rax + addq %rcx, %rax + movl %eax, (%rdx) + movslq %eax, %rax + addq %rcx, %rax + movl %eax, (%rdx) movslq -0x8(%rbp), %rax addq $0x20, %rsp popq %rbp @@ -39,5 +39,3 @@ Disassembly of section .text: movl $0x7, %edi popq %rbp jmp - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_cross_block.aarch64.asm b/tests/snapshots/asm/mem2reg_cross_block.aarch64.asm index 281801de4..1e73462d7 100644 --- a/tests/snapshots/asm/mem2reg_cross_block.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_cross_block.aarch64.asm @@ -10,20 +10,5 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xe // =14 - mov x2, #0x0 // =0 - mov x1, x2 - sxtw x3, w2 - cmp x3, #0x3 - b.ge - add x1, x1, x0 - add x2, x2, #0x1 - sxtw x2, w2 - b - sxtw x0, w1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + mov x0, #0x2a // =42 ret diff --git a/tests/snapshots/asm/mem2reg_cross_block.x64.asm b/tests/snapshots/asm/mem2reg_cross_block.x64.asm index f6d11c80b..cc4cec271 100644 --- a/tests/snapshots/asm/mem2reg_cross_block.x64.asm +++ b/tests/snapshots/asm/mem2reg_cross_block.x64.asm @@ -11,22 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xe, %eax - xorq %rdx, %rdx - movq %rdx, %rcx - movslq %edx, %rsi - cmpq $0x3, %rsi - jge - addq %rax, %rcx - incq %rdx - movslq %edx, %rdx - jmp - movslq %ecx, %rax - addq $0x20, %rsp - popq %rbp + movl $0x2a, %eax retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_i64_local.aarch64.asm b/tests/snapshots/asm/mem2reg_i64_local.aarch64.asm index 468817433..ebe4c2019 100644 --- a/tests/snapshots/asm/mem2reg_i64_local.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_i64_local.aarch64.asm @@ -10,21 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x17, #0x3 // =3 mul x0, x0, x17 - mov x2, #0x0 // =0 - mov x1, x2 - cmp x2, #0x4 - b.ge + add x1, x0, #0x0 add x1, x1, x0 - add x2, x2, #0x1 - b - mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + add x1, x1, x0 + add x0, x1, x0 ret
: diff --git a/tests/snapshots/asm/mem2reg_i64_local.x64.asm b/tests/snapshots/asm/mem2reg_i64_local.x64.asm index f255e4730..759e20abe 100644 --- a/tests/snapshots/asm/mem2reg_i64_local.x64.asm +++ b/tests/snapshots/asm/mem2reg_i64_local.x64.asm @@ -11,20 +11,11 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq (%rdi,%rdi,2), %rax - xorq %rdx, %rdx - movq %rdx, %rcx - cmpq $0x4, %rdx - jge + leaq (%rax), %rcx addq %rax, %rcx - incq %rdx - jmp - movq %rcx, %rax - addq $0x20, %rsp - popq %rbp + addq %rax, %rcx + addq %rcx, %rax retq
: @@ -35,5 +26,3 @@ Disassembly of section .text: movslq %eax, %rax popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_narrow_store_trunc.aarch64.asm b/tests/snapshots/asm/mem2reg_narrow_store_trunc.aarch64.asm index 6be73391c..aa8f431c5 100644 --- a/tests/snapshots/asm/mem2reg_narrow_store_trunc.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_narrow_store_trunc.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 mov x17, #0xff // =255 and x0, x0, x17 @@ -22,12 +19,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/mem2reg_narrow_store_trunc.x64.asm b/tests/snapshots/asm/mem2reg_narrow_store_trunc.x64.asm index cb6d91282..30e8e12fe 100644 --- a/tests/snapshots/asm/mem2reg_narrow_store_trunc.x64.asm +++ b/tests/snapshots/asm/mem2reg_narrow_store_trunc.x64.asm @@ -11,19 +11,14 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq %dil, %rax cmpq $0x2c, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq + movl $0x1, %ecx + jmp
: pushq %rbp @@ -32,4 +27,3 @@ Disassembly of section .text: popq %rbp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_param_promoted.aarch64.asm b/tests/snapshots/asm/mem2reg_param_promoted.aarch64.asm index d167d8e28..0b067cb4d 100644 --- a/tests/snapshots/asm/mem2reg_param_promoted.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_param_promoted.aarch64.asm @@ -10,33 +10,25 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, x0 sxtw x20, w20 cmp x20, #0x2 b.ge mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret sub x0, x20, #0x1 - sxtw x0, w0 bl mov x21, x0 sub x0, x20, #0x2 - sxtw x0, w0 bl add x0, x21, x0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/mem2reg_param_promoted.x64.asm b/tests/snapshots/asm/mem2reg_param_promoted.x64.asm index 1f49a1f6f..e105ec708 100644 --- a/tests/snapshots/asm/mem2reg_param_promoted.x64.asm +++ b/tests/snapshots/asm/mem2reg_param_promoted.x64.asm @@ -26,12 +26,10 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - leaq -0x1(%rbx), %rax - movslq %eax, %rdi + leaq -0x1(%rbx), %rdi callq movq %rax, %r12 - leaq -0x2(%rbx), %rax - movslq %eax, %rdi + leaq -0x2(%rbx), %rdi callq addq %r12, %rax movq (%rsp), %rbx @@ -81,5 +79,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_unsigned_narrow.aarch64.asm b/tests/snapshots/asm/mem2reg_unsigned_narrow.aarch64.asm index 1ed6f37bf..591cd5eb7 100644 --- a/tests/snapshots/asm/mem2reg_unsigned_narrow.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_unsigned_narrow.aarch64.asm @@ -10,62 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0x12c // =300 - mov x1, #0x2345 // =9029 - movk x1, #0x1, lsl #16 - mov x3, #0x0 // =0 - mov x2, x3 - mov x4, x3 - sxtw x5, w4 - cmp x5, #0x3 - b.ge - mov x17, #0xff // =255 - and x5, x0, x17 - add x2, x2, x5 - mov x17, #0xffff // =65535 - and x5, x1, x17 - add x3, x3, x5 - add x4, x4, #0x1 - sxtw x4, w4 - b - mov x5, #0x0 // =0 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0x2c // =44 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - add x0, x5, #0x1 - sxtw x5, w0 - mov x17, #0xffff // =65535 - and x0, x1, x17 - mov x17, #0x2345 // =9029 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - add x0, x5, #0x2 - sxtw x5, w0 - sxtw x0, w2 - cmp x0, #0x84 - b.eq - add x0, x5, #0x4 - sxtw x5, w0 - sxtw x0, w3 - mov x17, #0x69cf // =27087 - cmp x0, x17 - b.eq - add x0, x5, #0x8 - sxtw x5, w0 - sxtw x0, w5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + mov x1, #0x0 // =0 + sxtw x0, w1 ret + mov x1, #0x1 // =1 b + add x0, x1, #0x2 + sxtw x1, w0 b + add x0, x1, #0x4 + sxtw x1, w0 b + add x0, x1, #0x8 + sxtw x1, w0 b diff --git a/tests/snapshots/asm/mem2reg_unsigned_narrow.x64.asm b/tests/snapshots/asm/mem2reg_unsigned_narrow.x64.asm index 7cca09ce9..ce7c672f4 100644 --- a/tests/snapshots/asm/mem2reg_unsigned_narrow.x64.asm +++ b/tests/snapshots/asm/mem2reg_unsigned_narrow.x64.asm @@ -11,57 +11,19 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0x12c, %eax # imm = 0x12C - movl $0x12345, %ecx # imm = 0x12345 - xorq %rsi, %rsi - movq %rsi, %rdx - movq %rsi, %rdi - movslq %edi, %r8 - cmpq $0x3, %r8 - jge - movq %rax, %r8 - andq $0xff, %r8 - addq %r8, %rdx - movq %rcx, %r8 - andq $0xffff, %r8 # imm = 0xFFFF - addq %r8, %rsi - incq %rdi - movslq %edi, %rdi - jmp - xorq %r8, %r8 - andq $0xff, %rax - xorq $0x2c, %rax - movl %eax, %eax - testq %rax, %rax - je - leaq 0x1(%r8), %rax - movslq %eax, %r8 - movq %rcx, %rax - andq $0xffff, %rax # imm = 0xFFFF - xorq $0x2345, %rax # imm = 0x2345 - movl %eax, %eax - testq %rax, %rax - je - leaq 0x2(%r8), %rax - movslq %eax, %r8 - movslq %edx, %rax - cmpq $0x84, %rax - je - leaq 0x4(%r8), %rax - movslq %eax, %r8 - movslq %esi, %rax - cmpq $0x69cf, %rax # imm = 0x69CF - je - leaq 0x8(%r8), %rax - movslq %eax, %r8 - movslq %r8d, %rax - addq $0x30, %rsp - popq %rbp + xorq %rcx, %rcx + movslq %ecx, %rax retq + movl $0x1, %ecx jmp + leaq 0x2(%rcx), %rax + movslq %eax, %rcx jmp + leaq 0x4(%rcx), %rax + movslq %eax, %rcx jmp + leaq 0x8(%rcx), %rax + movslq %eax, %rcx jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mem2reg_value_across_call.aarch64.asm b/tests/snapshots/asm/mem2reg_value_across_call.aarch64.asm index 12d288506..fe5a69e75 100644 --- a/tests/snapshots/asm/mem2reg_value_across_call.aarch64.asm +++ b/tests/snapshots/asm/mem2reg_value_across_call.aarch64.asm @@ -19,40 +19,31 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, x0 adrp x21, add x21, x21, mov x22, #0x0 // =0 - mov x23, x22 - cmp x22, x20 - b.ge - lsl x0, x22, #1 - add x0, x0, #0x1 - add x23, x23, x0 - str x22, [sp, #-0x10]! + mov x0, x22 + b + lsl x1, x22, #1 + add x1, x1, #0x1 + add x23, x0, x1 mov x9, x21 - ldr x0, [sp] + mov x0, x22 blr x9 - add sp, sp, #0x10 - add x23, x23, x0 + add x0, x23, x0 add x22, x22, #0x1 - b - mov x0, x23 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + cmp x22, x20 + b.lt + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret
: diff --git a/tests/snapshots/asm/mem2reg_value_across_call.x64.asm b/tests/snapshots/asm/mem2reg_value_across_call.x64.asm index 60980ca3b..677ef971e 100644 --- a/tests/snapshots/asm/mem2reg_value_across_call.x64.asm +++ b/tests/snapshots/asm/mem2reg_value_across_call.x64.asm @@ -23,7 +23,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -31,25 +31,24 @@ Disassembly of section .text: movq %rdi, %rbx leaq -, %r12 # xorq %r13, %r13 - movq %r13, %r14 - cmpq %rbx, %r13 - jge movq %r13, %rax - shlq $0x1, %rax - incq %rax - addq %rax, %r14 + jmp + movq %r13, %rcx + shlq $0x1, %rcx + incq %rcx + leaq (%rax,%rcx), %r14 movq %r12, %rax movq %r13, %rdi callq *%rax - addq %rax, %r14 + addq %r14, %rax incq %r13 - jmp - movq %r14, %rax + cmpq %rbx, %r13 + jl movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x40, %rsp + addq $0x20, %rsp popq %rbp retq @@ -62,5 +61,4 @@ Disassembly of section .text: movslq %eax, %rax popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/memcpy_basic.aarch64.asm b/tests/snapshots/asm/memcpy_basic.aarch64.asm index bce641544..980d3377e 100644 --- a/tests/snapshots/asm/memcpy_basic.aarch64.asm +++ b/tests/snapshots/asm/memcpy_basic.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x40]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, #0x4 // =4 mov x0, x20 bl @@ -33,10 +31,8 @@ Disassembly of section .text: mov x1, x21 bl ldrb w0, [x22] - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x30] ldr x19, [sp, #0x20] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret diff --git a/tests/snapshots/asm/memcpy_basic.x64.asm b/tests/snapshots/asm/memcpy_basic.x64.asm index 4e9ad97f1..f73803c2e 100644 --- a/tests/snapshots/asm/memcpy_basic.x64.asm +++ b/tests/snapshots/asm/memcpy_basic.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -40,7 +40,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0x50, %rsp + addq $0x20, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/memcpy_oob_dst.aarch64.asm b/tests/snapshots/asm/memcpy_oob_dst.aarch64.asm index 85ebcedc8..1e15ec01d 100644 --- a/tests/snapshots/asm/memcpy_oob_dst.aarch64.asm +++ b/tests/snapshots/asm/memcpy_oob_dst.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x64 // =100 mov x0, x20 bl @@ -26,9 +24,7 @@ Disassembly of section .text: mov x2, x20 bl mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/memcpy_oob_dst.x64.asm b/tests/snapshots/asm/memcpy_oob_dst.x64.asm index 59ebb88e6..3289446f9 100644 --- a/tests/snapshots/asm/memcpy_oob_dst.x64.asm +++ b/tests/snapshots/asm/memcpy_oob_dst.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movl $0x64, %ebx @@ -32,7 +32,7 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/memcpy_oob_src.aarch64.asm b/tests/snapshots/asm/memcpy_oob_src.aarch64.asm index 8c05608be..ce1be2aa4 100644 --- a/tests/snapshots/asm/memcpy_oob_src.aarch64.asm +++ b/tests/snapshots/asm/memcpy_oob_src.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x8 // =8 bl mov x20, x0 @@ -26,9 +24,7 @@ Disassembly of section .text: mov x2, x21 bl mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/memcpy_oob_src.x64.asm b/tests/snapshots/asm/memcpy_oob_src.x64.asm index a7c7a4fd1..557cbff2f 100644 --- a/tests/snapshots/asm/memcpy_oob_src.x64.asm +++ b/tests/snapshots/asm/memcpy_oob_src.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movl $0x8, %edi @@ -32,6 +32,6 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/memory_ops.aarch64.asm b/tests/snapshots/asm/memory_ops.aarch64.asm index 74f6d9c0e..5de45ba89 100644 --- a/tests/snapshots/asm/memory_ops.aarch64.asm +++ b/tests/snapshots/asm/memory_ops.aarch64.asm @@ -10,16 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] + stp x20, x21, [sp, #-0x50]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] str x19, [sp, #0x30] + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x20, #0xa // =10 mov x0, x20 bl @@ -48,15 +44,11 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x30] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x50 ret mov x0, #0x42 // =66 strb w0, [x22, #0x5] @@ -68,24 +60,16 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x30] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x30] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x50 ret diff --git a/tests/snapshots/asm/memory_ops.x64.asm b/tests/snapshots/asm/memory_ops.x64.asm index d609d1d63..4dcecd4ac 100644 --- a/tests/snapshots/asm/memory_ops.x64.asm +++ b/tests/snapshots/asm/memory_ops.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp + subq $0x40, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -60,7 +60,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x70, %rsp + addq $0x40, %rsp popq %rbp retq movl $0x42, %eax @@ -79,7 +79,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x70, %rsp + addq $0x40, %rsp popq %rbp retq xorq %rax, %rax @@ -88,6 +88,6 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x70, %rsp + addq $0x40, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/memset_mcmp.aarch64.asm b/tests/snapshots/asm/memset_mcmp.aarch64.asm index df6065266..9bee69dbb 100644 --- a/tests/snapshots/asm/memset_mcmp.aarch64.asm +++ b/tests/snapshots/asm/memset_mcmp.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x5 // =5 bl mov x20, x0 @@ -31,14 +30,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2a // =42 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/memset_mcmp.x64.asm b/tests/snapshots/asm/memset_mcmp.x64.asm index 177908480..384ff7b33 100644 --- a/tests/snapshots/asm/memset_mcmp.x64.asm +++ b/tests/snapshots/asm/memset_mcmp.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x5, %edi xorl %eax, %eax @@ -31,11 +31,11 @@ Disassembly of section .text: jne movl $0x2a, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/memset_oob.aarch64.asm b/tests/snapshots/asm/memset_oob.aarch64.asm index e1fac184c..3f3bf5fbd 100644 --- a/tests/snapshots/asm/memset_oob.aarch64.asm +++ b/tests/snapshots/asm/memset_oob.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x8 // =8 bl mov x20, #0x0 // =0 @@ -22,8 +21,7 @@ Disassembly of section .text: mov x1, x20 bl mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/memset_oob.x64.asm b/tests/snapshots/asm/memset_oob.x64.asm index 9919f180c..0958de88f 100644 --- a/tests/snapshots/asm/memset_oob.x64.asm +++ b/tests/snapshots/asm/memset_oob.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x8, %edi xorl %eax, %eax @@ -26,6 +26,6 @@ Disassembly of section .text: callq movq %rbx, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/mixed_signed_unsigned_div.aarch64.asm b/tests/snapshots/asm/mixed_signed_unsigned_div.aarch64.asm index acc4cdae0..822557187 100644 --- a/tests/snapshots/asm/mixed_signed_unsigned_div.aarch64.asm +++ b/tests/snapshots/asm/mixed_signed_unsigned_div.aarch64.asm @@ -10,40 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x2 // =2 - mov w2, w0 - udiv x1, x2, x1 - mov w1, w1 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x1, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0x7 // =7 - mov w0, w0 - udiv x17, x0, x1 - msub x0, x17, x1, x0 - mov w0, w0 - mov x17, #0x3 // =3 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/mixed_signed_unsigned_div.x64.asm b/tests/snapshots/asm/mixed_signed_unsigned_div.x64.asm index 70218e0a6..8cee8a484 100644 --- a/tests/snapshots/asm/mixed_signed_unsigned_div.x64.asm +++ b/tests/snapshots/asm/mixed_signed_unsigned_div.x64.asm @@ -11,46 +11,9 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movabsq $-0x1, %rax - movl $0x2, %ecx - movl %eax, %edx - pushq %rax - pushq %rdx - movq %rdx, %rax - xorq %rdx, %rdx - divq %rcx - movq %rax, %rcx - popq %rdx - popq %rax - movl %ecx, %ecx - cmpq $0x7fffffff, %rcx # imm = 0x7FFFFFFF - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x7, %ecx - movl %eax, %eax - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rdx, %rax - popq %rdx - movl %eax, %eax - xorq $0x3, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/mixed_struct_gpr_abi.aarch64.asm b/tests/snapshots/asm/mixed_struct_gpr_abi.aarch64.asm index 0a8fa4e5a..8e60f9e18 100644 --- a/tests/snapshots/asm/mixed_struct_gpr_abi.aarch64.asm +++ b/tests/snapshots/asm/mixed_struct_gpr_abi.aarch64.asm @@ -76,40 +76,26 @@ Disassembly of section .text: str x10, [x0, #0x8] ldr x10, [sp], #0x10 sub x0, x29, #0x10 - mov x1, #0x2 // =2 - sxtw x1, w1 - ldr x2, [x0] - scvtf d0, x2 + ldr x1, [x0] + scvtf d0, x1 ldr d1, [x0, #0x8] mov x0, #0x4000000000000000 // =4611686018427387904 fmov d17, x0 fmadd d0, d1, d17, d0 fcvtzs x0, d0 - add x0, x0, x1 + add x0, x0, #0x2 cmp x0, #0xe b.eq mov x0, #0x1 // =1 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - mov x3, #0x4 // =4 - mov x4, #0x5 // =5 - mov x5, #0x6 // =6 - sub x6, x29, #0x10 - add x0, x0, x1 - add x0, x0, x2 - add x0, x0, x3 - add x0, x0, x4 - add x0, x0, x5 - sxtw x0, w0 - ldr x1, [x6] - add x0, x0, x1 - ldr d0, [x6, #0x8] - fcvtzs x1, d0 - add x0, x0, x1 + sub x0, x29, #0x10 + ldr x1, [x0] + add x1, x1, #0x15 + ldr d0, [x0, #0x8] + fcvtzs x0, d0 + add x0, x1, x0 cmp x0, #0x1c b.eq mov x0, #0x2 // =2 diff --git a/tests/snapshots/asm/mmap_anonymous.aarch64.asm b/tests/snapshots/asm/mmap_anonymous.aarch64.asm index abb3382b6..d60905955 100644 --- a/tests/snapshots/asm/mmap_anonymous.aarch64.asm +++ b/tests/snapshots/asm/mmap_anonymous.aarch64.asm @@ -10,13 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] + str x20, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x4000 // =16384 mov x0, #0x0 // =0 mov x2, #0x3 // =3 @@ -28,80 +25,64 @@ Disassembly of section .text: mov x1, x20 mov x5, x0 bl - mov x21, x0 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - cmp x21, x17 + cmp x0, x17 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 ret - mov x1, #0x0 // =0 - cmp x1, x20 - b.hs - b + add x1, x0, #0x0 + mov x2, #0x1 // =1 + strb w2, [x1] mov x17, #0x1000 // =4096 - add x1, x1, x17 + add x1, x0, x17 + mov x2, #0x2 // =2 + strb w2, [x1] + mov x17, #0x2000 // =8192 + add x1, x0, x17 + mov x2, #0x3 // =3 + strb w2, [x1] + mov x17, #0x3000 // =12288 + add x1, x0, x17 + mov x2, #0x4 // =4 + strb w2, [x1] + mov x2, #0x0 // =0 b - add x0, x21, x1 - lsr x2, x1, #12 - add x2, x2, #0x1 + add x1, x0, x2 + ldrb w1, [x1] + lsr x3, x2, #12 + add x3, x3, #0x1 mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - b - mov x22, #0x0 // =0 - cmp x22, x20 - b.hs - b + and x3, x3, x17 + cmp x1, x3 + b.ne mov x17, #0x1000 // =4096 - add x22, x22, x17 - b - add x0, x21, x22 - ldrb w0, [x0] - lsr x1, x22, #12 - add x1, x1, #0x1 - mov x17, #0xff // =255 - and x1, x1, x17 - cmp x0, x1 - b.eq - b - mov x0, x21 + add x2, x2, x17 + cmp x2, x20 + b.lo mov x1, x20 bl sxtw x0, w0 cmp x0, #0x0 b.eq - b - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - b mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x30 ret + b diff --git a/tests/snapshots/asm/mmap_anonymous.x64.asm b/tests/snapshots/asm/mmap_anonymous.x64.asm index cca8fd0c8..0dcfd08c2 100644 --- a/tests/snapshots/asm/mmap_anonymous.x64.asm +++ b/tests/snapshots/asm/mmap_anonymous.x64.asm @@ -13,10 +13,8 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) movl $0x4000, %ebx # imm = 0x4000 xorq %rdi, %rdi movl $0x3, %edx @@ -26,71 +24,59 @@ Disassembly of section .text: movq %rdi, %r9 xorl %eax, %eax callq - movq %rax, %r12 - cmpq $-0x1, %r12 + cmpq $-0x1, %rax jne movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq - xorq %rcx, %rcx - cmpq %rbx, %rcx - jae - jmp - addq $0x1000, %rcx # imm = 0x1000 - jmp - leaq (%r12,%rcx), %rax - movq %rcx, %rdx - shrq $0xc, %rdx - incq %rdx - movb %dl, (%rax) - jmp - xorq %r13, %r13 - cmpq %rbx, %r13 - jae - jmp - addq $0x1000, %r13 # imm = 0x1000 - jmp - leaq (%r12,%r13), %rax - movsbq (%rax), %rax - movq %r13, %rcx - shrq $0xc, %rcx - incq %rcx - movsbq %cl, %rcx - cmpq %rcx, %rax - je + leaq (%rax), %rcx + movl $0x1, %edx + movb %dl, (%rcx) + leaq 0x1000(%rax), %rcx + movl $0x2, %edx + movb %dl, (%rcx) + leaq 0x2000(%rax), %rcx + movl $0x3, %edx + movb %dl, (%rcx) + leaq 0x3000(%rax), %rcx + movl $0x4, %edx + movb %dl, (%rcx) + xorq %rdx, %rdx jmp - movq %r12, %rdi + leaq (%rax,%rdx), %rcx + movsbq (%rcx), %rcx + movq %rdx, %rsi + shrq $0xc, %rsi + incq %rsi + movsbq %sil, %rsi + cmpq %rsi, %rcx + jne + addq $0x1000, %rdx # imm = 0x1000 + cmpq %rbx, %rdx + jb + movq %rax, %rdi movq %rbx, %rsi xorl %eax, %eax callq movslq %eax, %rax testq %rax, %rax je - jmp - movl $0x2, %eax + movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq - jmp - movl $0x3, %eax + xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/msvc_callconv.aarch64.asm b/tests/snapshots/asm/msvc_callconv.aarch64.asm index f03aa77c1..e7438a6da 100644 --- a/tests/snapshots/asm/msvc_callconv.aarch64.asm +++ b/tests/snapshots/asm/msvc_callconv.aarch64.asm @@ -34,38 +34,26 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x0, add x0, x0, adrp x20, add x20, x20, mov x1, #0x14 // =20 mov x2, #0x16 // =22 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 - mov x1, #0x1 // =1 - add x1, x1, x1 - add x0, x0, x1 - mov x1, #0x3 // =3 - mov x2, #0x4 // =4 - add x1, x1, x2 - add x0, x0, x1 + add x0, x0, #0x2 + add x0, x0, #0x7 sxtw x21, w0 - str x21, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] + mov x0, x21 blr x9 - add sp, sp, #0x10 cmp x21, #0x33 cset x1, eq cbz x1, @@ -76,13 +64,11 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret + mov x1, #0x1 // =1 + b b diff --git a/tests/snapshots/asm/msvc_callconv.x64.asm b/tests/snapshots/asm/msvc_callconv.x64.asm index b4f8a33c3..04c9db330 100644 --- a/tests/snapshots/asm/msvc_callconv.x64.asm +++ b/tests/snapshots/asm/msvc_callconv.x64.asm @@ -36,7 +36,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq -, %rax # @@ -44,13 +44,8 @@ Disassembly of section .text: movl $0x14, %edi movl $0x16, %esi callq *%rax - movl $0x1, %ecx - addq %rcx, %rcx - addq %rcx, %rax - movl $0x3, %ecx - movl $0x4, %edx - addq %rdx, %rcx - addq %rcx, %rax + addq $0x2, %rax + addq $0x7, %rax movslq %eax, %r12 movq %rbx, %rax movq %r12, %rdi @@ -68,13 +63,14 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq %rcx, %rax - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/msvc_decl_decorators.aarch64.asm b/tests/snapshots/asm/msvc_decl_decorators.aarch64.asm index 1eca4b152..5ceb74428 100644 --- a/tests/snapshots/asm/msvc_decl_decorators.aarch64.asm +++ b/tests/snapshots/asm/msvc_decl_decorators.aarch64.asm @@ -26,27 +26,26 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mrs x0, TPIDR_EL0 add x0, x0, #0x10 ldrsw x1, [x0] add x1, x1, #0x1 - mov x2, #0x3 // =3 - add x1, x1, x2 + add x1, x1, #0x3 str w1, [x0] sxtw x0, w1 cmp x0, #0xb b.eq b mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b b b + b + b diff --git a/tests/snapshots/asm/msvc_decl_decorators.x64.asm b/tests/snapshots/asm/msvc_decl_decorators.x64.asm index a2182874b..2ed34b6bb 100644 --- a/tests/snapshots/asm/msvc_decl_decorators.x64.asm +++ b/tests/snapshots/asm/msvc_decl_decorators.x64.asm @@ -33,8 +33,7 @@ Disassembly of section .text: subq $0x8, %rax movslq (%rax), %rcx incq %rcx - movl $0x3, %edx - addq %rdx, %rcx + addq $0x3, %rcx movl %ecx, (%rax) movslq %ecx, %rax cmpq $0xb, %rax @@ -47,4 +46,6 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) + jmp + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/msvc_pragma_operator.aarch64.asm b/tests/snapshots/asm/msvc_pragma_operator.aarch64.asm index 5b5727988..2b3bd42db 100644 --- a/tests/snapshots/asm/msvc_pragma_operator.aarch64.asm +++ b/tests/snapshots/asm/msvc_pragma_operator.aarch64.asm @@ -10,14 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/msvc_pragma_operator.x64.asm b/tests/snapshots/asm/msvc_pragma_operator.x64.asm index ad8f6d22b..ab6dda6ae 100644 --- a/tests/snapshots/asm/msvc_pragma_operator.x64.asm +++ b/tests/snapshots/asm/msvc_pragma_operator.x64.asm @@ -11,14 +11,12 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/mul_pow2_to_shift.aarch64.asm b/tests/snapshots/asm/mul_pow2_to_shift.aarch64.asm index e4279de1e..e85e240f2 100644 --- a/tests/snapshots/asm/mul_pow2_to_shift.aarch64.asm +++ b/tests/snapshots/asm/mul_pow2_to_shift.aarch64.asm @@ -10,51 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x19, [sp, #0x10] - mov x0, #0x7 // =7 - lsl x1, x0, #1 - lsl x2, x0, #2 - lsl x3, x0, #3 - lsl x4, x0, #4 - lsl x5, x0, #10 - lsl x6, x0, #1 - mov w6, w6 - lsl x7, x0, #8 - mov w7, w7 - lsl x8, x0, #5 - lsl x0, x0, #16 - add x1, x1, x2 - add x1, x1, x3 - add x1, x1, x4 - add x1, x1, x5 - sxtw x1, w1 - mov w2, w6 - add x1, x1, x2 - mov w1, w1 - mov w2, w7 - add x1, x1, x2 - mov w1, w1 - add x1, x1, x8 - add x20, x1, x0 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x1, #0x24c0 // =9408 + movk x1, #0x7, lsl #16 adrp x0, add x0, x0, - mov x1, x20 bl sxtw x0, w0 - mov x17, #0x24c0 // =9408 - movk x17, #0x7, lsl #16 - cmp x20, x17 - b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/mul_pow2_to_shift.x64.asm b/tests/snapshots/asm/mul_pow2_to_shift.x64.asm index 60b6a54e2..8edab932a 100644 --- a/tests/snapshots/asm/mul_pow2_to_shift.x64.asm +++ b/tests/snapshots/asm/mul_pow2_to_shift.x64.asm @@ -13,59 +13,16 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xb0, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movl $0x7, %eax - movq %rax, %rcx - shlq $0x1, %rcx - movq %rax, %rdx - shlq $0x2, %rdx - movq %rax, %rsi - shlq $0x3, %rsi - movq %rax, %rdi - shlq $0x4, %rdi - movq %rax, %r8 - shlq $0xa, %r8 - movq %rax, %r9 - shlq $0x1, %r9 - movl %r9d, %r9d - movq %rax, %rbx - shlq $0x8, %rbx - movl %ebx, %ebx - movq %rax, %r12 - shlq $0x5, %r12 - shlq $0x10, %rax - addq %rdx, %rcx - addq %rsi, %rcx - addq %rdi, %rcx - addq %r8, %rcx - movslq %ecx, %rcx - movl %r9d, %edx - addq %rdx, %rcx - movl %ecx, %ecx - movl %ebx, %edx - addq %rdx, %rcx - movl %ecx, %ecx - addq %r12, %rcx - leaq (%rcx,%rax), %rbx + movl $0x724c0, %esi # imm = 0x724C0 leaq , %rdi - movq %rbx, %rsi movb $0x0, %al callq movslq %eax, %rax - cmpq $0x724c0, %rbx # imm = 0x724C0 - jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 movq %rcx, %rax - addq $0xb0, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/multi_declarator_prototypes.aarch64.asm b/tests/snapshots/asm/multi_declarator_prototypes.aarch64.asm index bfc554b67..380c6e1cd 100644 --- a/tests/snapshots/asm/multi_declarator_prototypes.aarch64.asm +++ b/tests/snapshots/asm/multi_declarator_prototypes.aarch64.asm @@ -23,19 +23,6 @@ Disassembly of section .text: add x0, x0, mov x1, #0xa // =10 str w1, [x0] - mov x1, #0x3 // =3 - sxtw x1, w1 - cmp x1, #0x3 - b.eq - mov x0, #0x1 // =1 - ret - mov x1, #0x3 // =3 - lsl x1, x1, #1 - sxtw x1, w1 - cmp x1, #0x6 - b.eq - mov x0, #0x2 // =2 - ret ldrsw x0, [x0] cmp x0, #0xa b.eq @@ -43,3 +30,7 @@ Disassembly of section .text: ret mov x0, #0x0 // =0 ret + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret diff --git a/tests/snapshots/asm/multi_declarator_prototypes.x64.asm b/tests/snapshots/asm/multi_declarator_prototypes.x64.asm index de5761e20..46c6b2e20 100644 --- a/tests/snapshots/asm/multi_declarator_prototypes.x64.asm +++ b/tests/snapshots/asm/multi_declarator_prototypes.x64.asm @@ -25,19 +25,6 @@ Disassembly of section .text: leaq , %rax movl $0xa, %ecx movl %ecx, (%rax) - movl $0x3, %ecx - movslq %ecx, %rcx - cmpq $0x3, %rcx - je - movl $0x1, %eax - retq - movl $0x3, %ecx - shlq $0x1, %rcx - movslq %ecx, %rcx - cmpq $0x6, %rcx - je - movl $0x2, %eax - retq movslq (%rax), %rax cmpq $0xa, %rax je @@ -45,3 +32,8 @@ Disassembly of section .text: retq xorq %rax, %rax retq + movl $0x1, %eax + retq + movl $0x2, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/multichar_constant.aarch64.asm b/tests/snapshots/asm/multichar_constant.aarch64.asm index 7fb9470b2..8393941b3 100644 --- a/tests/snapshots/asm/multichar_constant.aarch64.asm +++ b/tests/snapshots/asm/multichar_constant.aarch64.asm @@ -10,45 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - b - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret mov x2, #0x1 // =1 mov x2, #0x0 // =0 cbnz x2, mov x2, #0x0 // =0 cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 ret b + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x6 // =6 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b diff --git a/tests/snapshots/asm/multichar_constant.x64.asm b/tests/snapshots/asm/multichar_constant.x64.asm index 16bc5dd8c..b41ecc35c 100644 --- a/tests/snapshots/asm/multichar_constant.x64.asm +++ b/tests/snapshots/asm/multichar_constant.x64.asm @@ -11,24 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - jmp - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x10, %rsp - popq %rbp - retq movl $0x1, %edx xorq %rdx, %rdx testq %rdx, %rdx @@ -37,21 +19,18 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp + retq + xorq %rax, %rax retq jmp + movl $0x1, %eax + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq - jmp movl $0x6, %eax - addq $0x10, %rsp - popq %rbp retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp - retq - jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/multidim_array_init.aarch64.asm b/tests/snapshots/asm/multidim_array_init.aarch64.asm index 1a1223924..ae43397a1 100644 --- a/tests/snapshots/asm/multidim_array_init.aarch64.asm +++ b/tests/snapshots/asm/multidim_array_init.aarch64.asm @@ -10,22 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - b - mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x0, [x0, #0x10] cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -49,8 +39,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -58,8 +46,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -74,8 +60,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -90,8 +74,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -102,8 +84,6 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -114,8 +94,6 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x8 // =8 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -139,8 +117,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x9 // =9 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -155,8 +131,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0xa // =10 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -164,12 +138,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0xb // =11 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b @@ -178,3 +148,5 @@ Disassembly of section .text: b b b + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/multidim_array_init.x64.asm b/tests/snapshots/asm/multidim_array_init.x64.asm index f548134c3..192804cdb 100644 --- a/tests/snapshots/asm/multidim_array_init.x64.asm +++ b/tests/snapshots/asm/multidim_array_init.x64.asm @@ -11,21 +11,11 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - jmp - movl $0x1, %eax - addq $0x40, %rsp - popq %rbp - retq leaq , %rax movslq 0x10(%rax), %rax testq %rax, %rax je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x14(%rax), %rax @@ -53,16 +43,12 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x28(%rax), %rax testq %rax, %rax je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x3c(%rax), %rax @@ -79,8 +65,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x60(%rax), %rax @@ -97,8 +81,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x24(%rax), %rax @@ -107,8 +89,6 @@ Disassembly of section .text: cmpq %rcx, %rax je movl $0x7, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x60(%rax), %rax @@ -117,8 +97,6 @@ Disassembly of section .text: cmpq %rcx, %rax je movl $0x8, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -146,8 +124,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x9, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x18(%rax), %rax @@ -164,20 +140,14 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0xa, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq 0x20(%rax), %rax testq %rax, %rax je movl $0xb, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -186,3 +156,5 @@ Disassembly of section .text: jmp jmp jmp + movl $0x1, %eax + retq diff --git a/tests/snapshots/asm/narrow_param_entry_extend.aarch64.asm b/tests/snapshots/asm/narrow_param_entry_extend.aarch64.asm new file mode 100644 index 000000000..8730f6377 --- /dev/null +++ b/tests/snapshots/asm/narrow_param_entry_extend.aarch64.asm @@ -0,0 +1,103 @@ + +narrow_param_entry_extend.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + sxtb x0, w0 + sxth x1, w1 + mov x4, #0x0 // =0 + stur w4, [x29, #-0x8] + b + ldursw x5, [x29, #-0x8] + add x5, x5, x4 + stur w5, [x29, #-0x8] + add x4, x3, #0x1 + sxtw x3, w4 + cmp x3, #0x3 + b.lt + ldursw x3, [x29, #-0x8] + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + mul x0, x0, x17 + mov x17, #0xa // =10 + mul x1, x1, x17 + add x0, x0, x1 + add x0, x0, x2 + sxtw x0, w0 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x3, #0x0 // =0 + stur w3, [x29, #-0x8] + b + ldursw x4, [x29, #-0x8] + add x4, x4, x3 + stur w4, [x29, #-0x8] + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x3 + b.lt + ldursw x2, [x29, #-0x8] + mov x17, #0xff // =255 + and x0, x0, x17 + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + mul x0, x0, x17 + mov w0, w0 + mov x17, #0xffff // =65535 + and x1, x1, x17 + add x0, x0, x1 + mov w0, w0 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +
: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + adrp x0, + add x0, x0, + ldrsw x20, [x0] + mov x0, x20 + mov x2, x20 + mov x1, x20 + bl + mov x17, #0xcd17 // =52503 + movk x17, #0x6b, lsl #16 + cmp x0, x17 + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, x20 + mov x1, x20 + bl + mov x17, #0x6c65 // =27749 + movk x17, #0x69, lsl #16 + cmp x0, x17 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret diff --git a/tests/snapshots/asm/narrow_param_entry_extend.x64.asm b/tests/snapshots/asm/narrow_param_entry_extend.x64.asm new file mode 100644 index 000000000..3fae5ade1 --- /dev/null +++ b/tests/snapshots/asm/narrow_param_entry_extend.x64.asm @@ -0,0 +1,99 @@ + +narrow_param_entry_extend.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movsbq %dil, %rdi + movswq %si, %rsi + xorq %rcx, %rcx + movl %ecx, -0x8(%rbp) + jmp + movslq -0x8(%rbp), %r8 + addq %rcx, %r8 + movl %r8d, -0x8(%rbp) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x3, %rax + jl + movslq -0x8(%rbp), %rax + imulq $0x186a0, %rdi, %rax # imm = 0x186A0 + imulq $0xa, %rsi, %rcx + addq %rcx, %rax + addq %rdx, %rax + movslq %eax, %rax + addq $0x10, %rsp + popq %rbp + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + xorq %rcx, %rcx + movl %ecx, -0x8(%rbp) + jmp + movslq -0x8(%rbp), %rdx + addq %rcx, %rdx + movl %edx, -0x8(%rbp) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x3, %rax + jl + movslq -0x8(%rbp), %rax + movq %rdi, %rax + andq $0xff, %rax + imulq $0x186a0, %rax, %rax # imm = 0x186A0 + movl %eax, %eax + movq %rsi, %rcx + andq $0xffff, %rcx # imm = 0xFFFF + addq %rcx, %rax + movl %eax, %eax + addq $0x10, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + leaq , %rax + movslq (%rax), %rbx + movq %rbx, %rdi + movq %rbx, %rdx + movq %rbx, %rsi + callq + cmpq $0x6bcd17, %rax # imm = 0x6BCD17 + je + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movq %rbx, %rdi + movq %rbx, %rsi + callq + cmpq $0x696c65, %rax # imm = 0x696C65 + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/natural_width_local.aarch64.asm b/tests/snapshots/asm/natural_width_local.aarch64.asm index 90aea36d2..3fdcb4961 100644 --- a/tests/snapshots/asm/natural_width_local.aarch64.asm +++ b/tests/snapshots/asm/natural_width_local.aarch64.asm @@ -10,55 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0x12c // =300 - mov x1, #0xc8 // =200 - mov x3, #0x0 // =0 - mov x2, x3 - sxtw x4, w2 - cmp x4, #0x4 - b.ge - sxtb x4, w0 - add x3, x3, x4 - add x2, x2, #0x1 - sxtw x2, w2 - b - mov x4, #0x0 // =0 - sxtb x2, w0 - cmp x2, #0x2c - b.eq - add x2, x4, #0x1 - sxtw x4, w2 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0x2c // =44 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - add x0, x4, #0x2 - sxtw x4, w0 - sxtb x0, w1 - mov x17, #0xffc8 // =65480 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - add x0, x4, #0x4 - sxtw x4, w0 - sxtw x0, w3 - cmp x0, #0xb0 - b.eq - add x0, x4, #0x8 - sxtw x4, w0 - sxtw x0, w4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + mov x1, #0x0 // =0 + sxtw x0, w1 ret + mov x1, #0x1 // =1 b + add x0, x1, #0x2 + sxtw x1, w0 b + add x0, x1, #0x4 + sxtw x1, w0 b + add x0, x1, #0x8 + sxtw x1, w0 b diff --git a/tests/snapshots/asm/natural_width_local.x64.asm b/tests/snapshots/asm/natural_width_local.x64.asm index 5292b45d5..d11afaae1 100644 --- a/tests/snapshots/asm/natural_width_local.x64.asm +++ b/tests/snapshots/asm/natural_width_local.x64.asm @@ -11,49 +11,19 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0x12c, %eax # imm = 0x12C - movl $0xc8, %ecx - xorq %rsi, %rsi - movq %rsi, %rdx - movslq %edx, %rdi - cmpq $0x4, %rdi - jge - movsbq %al, %rdi - addq %rdi, %rsi - incq %rdx - movslq %edx, %rdx - jmp - xorq %rdi, %rdi - movsbq %al, %rdx - cmpq $0x2c, %rdx - je - leaq 0x1(%rdi), %rdx - movslq %edx, %rdi - andq $0xff, %rax - xorq $0x2c, %rax - movl %eax, %eax - testq %rax, %rax - je - leaq 0x2(%rdi), %rax - movslq %eax, %rdi - movsbq %cl, %rax - cmpq $-0x38, %rax - je - leaq 0x4(%rdi), %rax - movslq %eax, %rdi - movslq %esi, %rax - cmpq $0xb0, %rax - je - leaq 0x8(%rdi), %rax - movslq %eax, %rdi - movslq %edi, %rax - addq $0x30, %rsp - popq %rbp + xorq %rcx, %rcx + movslq %ecx, %rax retq + movl $0x1, %ecx jmp + leaq 0x2(%rcx), %rax + movslq %eax, %rcx jmp + leaq 0x4(%rcx), %rax + movslq %eax, %rcx jmp + leaq 0x8(%rcx), %rax + movslq %eax, %rcx jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm b/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm new file mode 100644 index 000000000..c50a33f1b --- /dev/null +++ b/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm @@ -0,0 +1,14 @@ + +ndebug_optimize_predefine.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm b/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm new file mode 100644 index 000000000..0869f692c --- /dev/null +++ b/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm @@ -0,0 +1,16 @@ + +ndebug_optimize_predefine.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + movl $0x1, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm b/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm new file mode 100644 index 000000000..d237ce617 --- /dev/null +++ b/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm @@ -0,0 +1,14 @@ + +ndebug_undef_reenables_assert.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x230 // =560 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x0 // =0 + ret diff --git a/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm b/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm new file mode 100644 index 000000000..b14dd7ff9 --- /dev/null +++ b/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm @@ -0,0 +1,15 @@ + +ndebug_undef_reenables_assert.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + xorq %rax, %rax + retq diff --git a/tests/snapshots/asm/negative_float_in_array_init.aarch64.asm b/tests/snapshots/asm/negative_float_in_array_init.aarch64.asm index d105f69ba..f6d3797ea 100644 --- a/tests/snapshots/asm/negative_float_in_array_init.aarch64.asm +++ b/tests/snapshots/asm/negative_float_in_array_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr d0, [x0] @@ -22,8 +19,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr d0, [x0, #0x8] mov x1, #0x4004000000000000 // =4612811918334230528 @@ -33,8 +28,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr d0, [x0, #0x10] mov x1, #0x94000000 // =2483027968 @@ -46,8 +39,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr d0, [x0] ldr d1, [x0, #0x8] @@ -77,11 +68,7 @@ Disassembly of section .text: cset x1, mi cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/negative_float_in_array_init.x64.asm b/tests/snapshots/asm/negative_float_in_array_init.x64.asm index 067bb05f4..4c3f0a6a6 100644 --- a/tests/snapshots/asm/negative_float_in_array_init.x64.asm +++ b/tests/snapshots/asm/negative_float_in_array_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movsd (%rax,%riz), %xmm0 movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 @@ -27,8 +24,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movsd 0x8(%rax,%riz), %xmm0 movabsq $0x4004000000000000, %rcx # imm = 0x4004000000000000 @@ -45,8 +40,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq movsd 0x10(%rax,%riz), %xmm0 movabsq $0x421e449a94000000, %rcx # imm = 0x421E449A94000000 @@ -63,8 +56,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq movsd (%rax,%riz), %xmm0 movsd 0x8(%rax,%riz), %xmm1 @@ -101,12 +92,7 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/negative_size_memset.aarch64.asm b/tests/snapshots/asm/negative_size_memset.aarch64.asm index f67fd7cf2..14c416753 100644 --- a/tests/snapshots/asm/negative_size_memset.aarch64.asm +++ b/tests/snapshots/asm/negative_size_memset.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x8 // =8 bl mov x20, #0x0 // =0 @@ -25,8 +24,7 @@ Disassembly of section .text: mov x1, x20 bl mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/negative_size_memset.x64.asm b/tests/snapshots/asm/negative_size_memset.x64.asm index 545e0a14f..5e370027c 100644 --- a/tests/snapshots/asm/negative_size_memset.x64.asm +++ b/tests/snapshots/asm/negative_size_memset.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x8, %edi xorl %eax, %eax @@ -26,7 +26,7 @@ Disassembly of section .text: callq movq %rbx, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/nested_designator_string_member.aarch64.asm b/tests/snapshots/asm/nested_designator_string_member.aarch64.asm index 37c037376..610593f56 100644 --- a/tests/snapshots/asm/nested_designator_string_member.aarch64.asm +++ b/tests/snapshots/asm/nested_designator_string_member.aarch64.asm @@ -10,38 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b - b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] + stp x20, x21, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 adrp x21, add x21, x21, @@ -52,41 +42,32 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret ldrb w0, [x21, #0x7] cmp x0, #0x0 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, ldrb w0, [x21, #0xb] cmp x0, #0x0 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret ldrsw x0, [x21, #0xc] cmp x0, #0x7 - cset x22, ne - cbnz x22, + cset x1, ne + cbnz x1, ldrsw x0, [x21] cmp x0, #0x5 - cset x22, ne - cbz x22, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x10 adrp x1, @@ -132,11 +113,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x10 ldrb w0, [x0, #0x8] @@ -149,11 +127,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x10 ldrsw x0, [x0, #0xc] @@ -170,18 +145,12 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldp x20, x21, [sp], #0x60 ret b b diff --git a/tests/snapshots/asm/nested_designator_string_member.x64.asm b/tests/snapshots/asm/nested_designator_string_member.x64.asm index afa5f07da..5695233eb 100644 --- a/tests/snapshots/asm/nested_designator_string_member.x64.asm +++ b/tests/snapshots/asm/nested_designator_string_member.x64.asm @@ -11,24 +11,9 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp - incq %rdi - incq %rsi - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp - retq movsbq (%rdi), %rax movsbq (%rsi), %rcx cmpq %rcx, %rax @@ -36,16 +21,23 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je + incq %rdi + incq %rsi jmp jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %al + movzbq %al, %rax + retq
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x50, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) movq %rdi, %rbx leaq , %r12 leaq 0x4(%r12), %rdi @@ -56,46 +48,43 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movsbq 0x7(%r12), %rax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne movsbq 0xb(%r12), %rax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movslq 0xc(%r12), %rax cmpq $0x7, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne movslq (%r12), %rax cmpq $0x5, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq -0x10(%rbp), %rax @@ -142,8 +131,7 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq -0x10(%rbp), %rax @@ -163,8 +151,7 @@ Disassembly of section .text: movl $0x5, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq leaq -0x10(%rbp), %rax @@ -188,19 +175,17 @@ Disassembly of section .text: movl $0x6, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq jmp jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/nested_function_calls.aarch64.asm b/tests/snapshots/asm/nested_function_calls.aarch64.asm index a1824c119..c3859cbf1 100644 --- a/tests/snapshots/asm/nested_function_calls.aarch64.asm +++ b/tests/snapshots/asm/nested_function_calls.aarch64.asm @@ -15,12 +15,5 @@ Disassembly of section .text: ret
: - mov x0, #0xa // =10 - mov x1, #0x14 // =20 - add x0, x0, x1 - mov x2, #0x1e // =30 - mov x3, #0x28 // =40 - add x2, x2, x3 - add x0, x0, x2 - sxtw x0, w0 + mov x0, #0x64 // =100 ret diff --git a/tests/snapshots/asm/nested_function_calls.x64.asm b/tests/snapshots/asm/nested_function_calls.x64.asm index 1e11f64dd..d582bbf4d 100644 --- a/tests/snapshots/asm/nested_function_calls.x64.asm +++ b/tests/snapshots/asm/nested_function_calls.x64.asm @@ -16,14 +16,6 @@ Disassembly of section .text: retq
: - movl $0xa, %eax - movl $0x14, %ecx - addq %rcx, %rax - movl $0x1e, %edx - movl $0x28, %esi - addq %rsi, %rdx - addq %rdx, %rax - movslq %eax, %rax + movl $0x64, %eax retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/nested_runtime_init.aarch64.asm b/tests/snapshots/asm/nested_runtime_init.aarch64.asm index 0fd8b819e..f91210253 100644 --- a/tests/snapshots/asm/nested_runtime_init.aarch64.asm +++ b/tests/snapshots/asm/nested_runtime_init.aarch64.asm @@ -14,179 +14,149 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x80 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x14 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x18 - adrp x2, - add x2, x2, + sub x2, x29, #0x18 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x0] - ldr x10, [x2, #0x8] - str x10, [x0, #0x8] + ldr x10, [x3] + str x10, [x2] + ldr x10, [x3, #0x8] + str x10, [x2, #0x8] ldr x10, [sp], #0x10 - sub x0, x29, #0x18 - str w1, [x0] - add x0, x1, #0x1 - sxtw x0, w0 sub x2, x29, #0x18 - str x0, [x2, #0x8] - sub x0, x29, #0x18 - ldrsw x0, [x0] - sxtw x2, w1 - cmp x0, x2 - cset x2, ne - cbnz x2, - b - mov x0, #0x0 // =0 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - sub x0, x29, #0x18 - ldr x0, [x0, #0x8] + str w1, [x2] add x2, x1, #0x1 sxtw x2, w2 - cmp x0, x2 - cset x2, ne - cbz x2, - mov x0, #0x1 // =1 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - sub x0, x29, #0x28 - adrp x2, - add x2, x2, + sub x3, x29, #0x18 + str x2, [x3, #0x8] + sub x2, x29, #0x18 + ldrsw x2, [x2] + cmp x2, x0 + cset x3, ne + cbnz x3, + sub x2, x29, #0x18 + ldr x2, [x2, #0x8] + add x3, x1, #0x1 + sxtw x3, w3 + cmp x2, x3 + cset x3, ne + cbnz x3, + sub x2, x29, #0x28 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x0] - ldr x10, [x2, #0x8] - str x10, [x0, #0x8] + ldr x10, [x3] + str x10, [x2] + ldr x10, [x3, #0x8] + str x10, [x2, #0x8] ldr x10, [sp], #0x10 - lsl x0, x1, #1 - sub x2, x29, #0x28 - str w0, [x2] - add x0, x1, #0x3 - sxtw x0, w0 - sub x2, x29, #0x28 - str x0, [x2, #0x8] - sub x0, x29, #0x28 - ldrsw x0, [x0] lsl x2, x1, #1 - sxtw x2, w2 - cmp x0, x2 - cset x2, ne - cbnz x2, - sub x0, x29, #0x28 - ldr x0, [x0, #0x8] + sub x3, x29, #0x28 + str w2, [x3] add x2, x1, #0x3 sxtw x2, w2 - cmp x0, x2 - cset x2, ne - cbz x2, - mov x0, #0x2 // =2 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - sub x0, x29, #0x38 - adrp x2, - add x2, x2, + sub x3, x29, #0x28 + str x2, [x3, #0x8] + sub x2, x29, #0x28 + ldrsw x2, [x2] + lsl x3, x1, #1 + sxtw x3, w3 + cmp x2, x3 + cset x3, ne + cbnz x3, + sub x2, x29, #0x28 + ldr x2, [x2, #0x8] + add x3, x1, #0x3 + sxtw x3, w3 + cmp x2, x3 + cset x3, ne + cbnz x3, + sub x2, x29, #0x38 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x0] - ldr x10, [x2, #0x8] - str x10, [x0, #0x8] + ldr x10, [x3] + str x10, [x2] + ldr x10, [x3, #0x8] + str x10, [x2, #0x8] ldr x10, [sp], #0x10 - sub x0, x29, #0x38 - str w1, [x0] - lsl x0, x1, #1 - sub x2, x29, #0x38 - str w0, [x2, #0x4] - add x0, x1, #0x5 - sxtw x0, w0 sub x2, x29, #0x38 - str x0, [x2, #0x8] - sub x0, x29, #0x38 - ldrsw x0, [x0] - sxtw x2, w1 - cmp x0, x2 - cset x0, ne - mov x3, #0x1 // =1 - cbnz x0, - sub x0, x29, #0x38 - ldrsw x0, [x0, #0x4] + str w1, [x2] lsl x2, x1, #1 - sxtw x2, w2 - cmp x0, x2 - cset x0, ne - cmp x0, #0x0 - cset x3, ne - cbnz x3, - sub x0, x29, #0x38 - ldr x0, [x0, #0x8] + sub x3, x29, #0x38 + str w2, [x3, #0x4] add x2, x1, #0x5 sxtw x2, w2 - cmp x0, x2 - cset x3, ne - cbz x3, - mov x0, #0x3 // =3 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - sub x0, x29, #0x48 - adrp x2, - add x2, x2, + sub x3, x29, #0x38 + str x2, [x3, #0x8] + sub x2, x29, #0x38 + ldrsw x2, [x2] + cmp x2, x0 + cset x2, ne + mov x4, #0x1 // =1 + cbnz x2, + sub x2, x29, #0x38 + ldrsw x2, [x2, #0x4] + lsl x3, x1, #1 + sxtw x3, w3 + cmp x2, x3 + cset x2, ne + cmp x2, #0x0 + cset x4, ne + cbnz x4, + sub x2, x29, #0x38 + ldr x2, [x2, #0x8] + add x3, x1, #0x5 + sxtw x3, w3 + cmp x2, x3 + cset x4, ne + cbnz x4, + sub x2, x29, #0x48 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x0] - ldrb w10, [x2, #0x8] - strb w10, [x0, #0x8] - ldrb w10, [x2, #0x9] - strb w10, [x0, #0x9] - ldrb w10, [x2, #0xa] - strb w10, [x0, #0xa] - ldrb w10, [x2, #0xb] - strb w10, [x0, #0xb] + ldr x10, [x3] + str x10, [x2] + ldrb w10, [x3, #0x8] + strb w10, [x2, #0x8] + ldrb w10, [x3, #0x9] + strb w10, [x2, #0x9] + ldrb w10, [x3, #0xa] + strb w10, [x2, #0xa] + ldrb w10, [x3, #0xb] + strb w10, [x2, #0xb] ldr x10, [sp], #0x10 - sub x0, x29, #0x48 - str w1, [x0] - add x0, x1, #0x1 - sub x2, x29, #0x48 - str w0, [x2, #0x4] - add x0, x1, #0x2 sub x2, x29, #0x48 - str w0, [x2, #0x8] - sub x0, x29, #0x48 - ldrsw x0, [x0] - sxtw x2, w1 - cmp x0, x2 - cset x0, ne - mov x3, #0x1 // =1 - cbnz x0, - sub x0, x29, #0x48 - ldrsw x0, [x0, #0x4] + str w1, [x2] add x2, x1, #0x1 - sxtw x2, w2 - cmp x0, x2 - cset x0, ne - cmp x0, #0x0 - cset x3, ne - cbnz x3, - sub x0, x29, #0x48 - ldrsw x0, [x0, #0x8] + sub x3, x29, #0x48 + str w2, [x3, #0x4] add x2, x1, #0x2 - sxtw x2, w2 - cmp x0, x2 - cset x3, ne - cbz x3, - mov x0, #0x4 // =4 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret + sub x3, x29, #0x48 + str w2, [x3, #0x8] + sub x2, x29, #0x48 + ldrsw x2, [x2] + cmp x2, x0 + cset x2, ne + mov x4, #0x1 // =1 + cbnz x2, + sub x2, x29, #0x48 + ldrsw x2, [x2, #0x4] + add x3, x1, #0x1 + sxtw x3, w3 + cmp x2, x3 + cset x2, ne + cmp x2, #0x0 + cset x4, ne + cbnz x4, + sub x2, x29, #0x48 + ldrsw x2, [x2, #0x8] + add x3, x1, #0x2 + sxtw x3, w3 + cmp x2, x3 + cset x4, ne + cbz x4, b b b @@ -194,3 +164,28 @@ Disassembly of section .text: b b b + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x14 + b.lt + mov x0, #0x0 // =0 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + b diff --git a/tests/snapshots/asm/nested_runtime_init.x64.asm b/tests/snapshots/asm/nested_runtime_init.x64.asm index 1ebd8c5bc..ae7eb2a1a 100644 --- a/tests/snapshots/asm/nested_runtime_init.x64.asm +++ b/tests/snapshots/asm/nested_runtime_init.x64.asm @@ -15,201 +15,171 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x80, %rsp xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x14, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0x18(%rbp), %rax - leaq , %rdx - pushq %rcx - movq (%rdx), %rcx - movq %rcx, (%rax) - movq 0x8(%rdx), %rcx - movq %rcx, 0x8(%rax) - popq %rcx - leaq -0x18(%rbp), %rax - movl %ecx, (%rax) - leaq 0x1(%rcx), %rax - movslq %eax, %rax leaq -0x18(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movq 0x8(%rsi), %rax movq %rax, 0x8(%rdx) - leaq -0x18(%rbp), %rax - movslq (%rax), %rax - movslq %ecx, %rdx - cmpq %rdx, %rax - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne - jmp - xorq %rax, %rax - addq $0x80, %rsp - popq %rbp - retq - leaq -0x18(%rbp), %rax - movq 0x8(%rax), %rax + popq %rax + leaq -0x18(%rbp), %rdx + movl %ecx, (%rdx) leaq 0x1(%rcx), %rdx movslq %edx, %rdx - cmpq %rdx, %rax - setne %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je - movl $0x1, %eax - addq $0x80, %rsp - popq %rbp - retq - leaq -0x28(%rbp), %rax - leaq , %rdx - pushq %rcx - movq (%rdx), %rcx - movq %rcx, (%rax) - movq 0x8(%rdx), %rcx - movq %rcx, 0x8(%rax) - popq %rcx - movq %rcx, %rax - shlq $0x1, %rax + leaq -0x18(%rbp), %rsi + movq %rdx, 0x8(%rsi) + leaq -0x18(%rbp), %rdx + movslq (%rdx), %rdx + cmpq %rax, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + jne + leaq -0x18(%rbp), %rdx + movq 0x8(%rdx), %rdx + leaq 0x1(%rcx), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + jne + leaq -0x28(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movq 0x8(%rsi), %rax + movq %rax, 0x8(%rdx) + popq %rax + movq %rcx, %rdx + shlq $0x1, %rdx + leaq -0x28(%rbp), %rsi + movl %edx, (%rsi) + leaq 0x3(%rcx), %rdx + movslq %edx, %rdx + leaq -0x28(%rbp), %rsi + movq %rdx, 0x8(%rsi) leaq -0x28(%rbp), %rdx - movl %eax, (%rdx) - leaq 0x3(%rcx), %rax - movslq %eax, %rax + movslq (%rdx), %rdx + movq %rcx, %rsi + shlq $0x1, %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + jne leaq -0x28(%rbp), %rdx + movq 0x8(%rdx), %rdx + leaq 0x3(%rcx), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + jne + leaq -0x38(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movq 0x8(%rsi), %rax movq %rax, 0x8(%rdx) - leaq -0x28(%rbp), %rax - movslq (%rax), %rax + popq %rax + leaq -0x38(%rbp), %rdx + movl %ecx, (%rdx) movq %rcx, %rdx shlq $0x1, %rdx + leaq -0x38(%rbp), %rsi + movl %edx, 0x4(%rsi) + leaq 0x5(%rcx), %rdx movslq %edx, %rdx - cmpq %rdx, %rax + leaq -0x38(%rbp), %rsi + movq %rdx, 0x8(%rsi) + leaq -0x38(%rbp), %rdx + movslq (%rdx), %rdx + cmpq %rax, %rdx setne %dl movzbq %dl, %rdx + movl $0x1, %edi testq %rdx, %rdx jne - leaq -0x28(%rbp), %rax - movq 0x8(%rax), %rax - leaq 0x3(%rcx), %rdx - movslq %edx, %rdx - cmpq %rdx, %rax + leaq -0x38(%rbp), %rdx + movslq 0x4(%rdx), %rdx + movq %rcx, %rsi + shlq $0x1, %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx setne %dl movzbq %dl, %rdx testq %rdx, %rdx - je - movl $0x2, %eax - addq $0x80, %rsp - popq %rbp - retq - leaq -0x38(%rbp), %rax - leaq , %rdx - pushq %rcx - movq (%rdx), %rcx - movq %rcx, (%rax) - movq 0x8(%rdx), %rcx - movq %rcx, 0x8(%rax) - popq %rcx - leaq -0x38(%rbp), %rax - movl %ecx, (%rax) - movq %rcx, %rax - shlq $0x1, %rax - leaq -0x38(%rbp), %rdx - movl %eax, 0x4(%rdx) - leaq 0x5(%rcx), %rax - movslq %eax, %rax - leaq -0x38(%rbp), %rdx - movq %rax, 0x8(%rdx) - leaq -0x38(%rbp), %rax - movslq (%rax), %rax - movslq %ecx, %rdx - cmpq %rdx, %rax - setne %al - movzbq %al, %rax - movl $0x1, %esi - testq %rax, %rax + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi jne - leaq -0x38(%rbp), %rax - movslq 0x4(%rax), %rax - movq %rcx, %rdx - shlq $0x1, %rdx - movslq %edx, %rdx - cmpq %rdx, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi + leaq -0x38(%rbp), %rdx + movq 0x8(%rdx), %rdx + leaq 0x5(%rcx), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi jne - leaq -0x38(%rbp), %rax - movq 0x8(%rax), %rax - leaq 0x5(%rcx), %rdx - movslq %edx, %rdx - cmpq %rdx, %rax - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi - je - movl $0x3, %eax - addq $0x80, %rsp - popq %rbp - retq - leaq -0x48(%rbp), %rax - leaq , %rdx - pushq %rcx - movq (%rdx), %rcx - movq %rcx, (%rax) - movzbq 0x8(%rdx), %rcx - movb %cl, 0x8(%rax) - movzbq 0x9(%rdx), %rcx - movb %cl, 0x9(%rax) - movzbq 0xa(%rdx), %rcx - movb %cl, 0xa(%rax) - movzbq 0xb(%rdx), %rcx - movb %cl, 0xb(%rax) - popq %rcx - leaq -0x48(%rbp), %rax - movl %ecx, (%rax) - leaq 0x1(%rcx), %rax leaq -0x48(%rbp), %rdx - movl %eax, 0x4(%rdx) - leaq 0x2(%rcx), %rax + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movzbq 0x8(%rsi), %rax + movb %al, 0x8(%rdx) + movzbq 0x9(%rsi), %rax + movb %al, 0x9(%rdx) + movzbq 0xa(%rsi), %rax + movb %al, 0xa(%rdx) + movzbq 0xb(%rsi), %rax + movb %al, 0xb(%rdx) + popq %rax leaq -0x48(%rbp), %rdx - movl %eax, 0x8(%rdx) - leaq -0x48(%rbp), %rax - movslq (%rax), %rax - movslq %ecx, %rdx - cmpq %rdx, %rax - setne %al - movzbq %al, %rax - movl $0x1, %esi - testq %rax, %rax - jne - leaq -0x48(%rbp), %rax - movslq 0x4(%rax), %rax + movl %ecx, (%rdx) leaq 0x1(%rcx), %rdx - movslq %edx, %rdx - cmpq %rdx, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi - jne - leaq -0x48(%rbp), %rax - movslq 0x8(%rax), %rax + leaq -0x48(%rbp), %rsi + movl %edx, 0x4(%rsi) leaq 0x2(%rcx), %rdx - movslq %edx, %rdx - cmpq %rdx, %rax - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi + leaq -0x48(%rbp), %rsi + movl %edx, 0x8(%rsi) + leaq -0x48(%rbp), %rdx + movslq (%rdx), %rdx + cmpq %rax, %rdx + setne %dl + movzbq %dl, %rdx + movl $0x1, %edi + testq %rdx, %rdx + jne + leaq -0x48(%rbp), %rdx + movslq 0x4(%rdx), %rdx + leaq 0x1(%rcx), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi + jne + leaq -0x48(%rbp), %rdx + movslq 0x8(%rdx), %rdx + leaq 0x2(%rcx), %rsi + movslq %esi, %rsi + cmpq %rsi, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi je - movl $0x4, %eax - addq $0x80, %rsp - popq %rbp - retq jmp jmp jmp @@ -217,3 +187,29 @@ Disassembly of section .text: jmp jmp jmp + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x14, %rax + jl + xorq %rax, %rax + addq $0x80, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x80, %rsp + popq %rbp + retq + movl $0x1, %eax + addq $0x80, %rsp + popq %rbp + retq + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/nonconst_local_struct_init.aarch64.asm b/tests/snapshots/asm/nonconst_local_struct_init.aarch64.asm index cf554db31..12c01086d 100644 --- a/tests/snapshots/asm/nonconst_local_struct_init.aarch64.asm +++ b/tests/snapshots/asm/nonconst_local_struct_init.aarch64.asm @@ -16,34 +16,31 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x120 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] - mov x20, #0x2a // =42 - mov x21, #0x63 // =99 - sub x0, x29, #0x18 - adrp x1, - add x1, x1, + sub sp, sp, #0x100 + str x19, [sp] + mov x0, #0x2a // =42 + mov x1, #0x63 // =99 + sub x2, x29, #0x18 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] + ldr x10, [x3] + str x10, [x2] ldr x10, [sp], #0x10 - sub x0, x29, #0x18 - str w20, [x0] - sub x0, x29, #0x18 - str w21, [x0, #0x4] - sub x0, x29, #0x18 - ldrsw x0, [x0] - cmp x0, #0x2a - cset x22, ne - cbnz x22, - sub x0, x29, #0x18 - ldrsw x0, [x0, #0x4] - cmp x0, #0x63 - cset x22, ne - cbz x22, + sub x2, x29, #0x18 + str w0, [x2] + sub x2, x29, #0x18 + str w1, [x2, #0x4] + sub x2, x29, #0x18 + ldrsw x2, [x2] + cmp x2, #0x2a + cset x3, ne + cbnz x3, + sub x2, x29, #0x18 + ldrsw x2, [x2, #0x4] + cmp x2, #0x63 + cset x3, ne + cbz x3, adrp x0, add x0, x0, sub x1, x29, #0x18 @@ -53,35 +50,32 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x20 - adrp x1, - add x1, x1, + sub x2, x29, #0x20 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] + ldr x10, [x3] + str x10, [x2] ldr x10, [sp], #0x10 - mov x0, #0x7 // =7 - sub x1, x29, #0x20 - str w0, [x1] - sub x0, x29, #0x20 - str w21, [x0, #0x4] - sub x0, x29, #0x20 - ldrsw x0, [x0] - cmp x0, #0x7 - cset x22, ne - cbnz x22, - sub x0, x29, #0x20 - ldrsw x0, [x0, #0x4] - cmp x0, #0x63 - cset x22, ne - cbz x22, + mov x2, #0x7 // =7 + sub x3, x29, #0x20 + str w2, [x3] + sub x2, x29, #0x20 + str w1, [x2, #0x4] + sub x2, x29, #0x20 + ldrsw x2, [x2] + cmp x2, #0x7 + cset x3, ne + cbnz x3, + sub x2, x29, #0x20 + ldrsw x2, [x2, #0x4] + cmp x2, #0x63 + cset x3, ne + cbz x3, adrp x0, add x0, x0, sub x1, x29, #0x20 @@ -91,36 +85,33 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x28 - adrp x1, - add x1, x1, + sub x2, x29, #0x28 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] + ldr x10, [x3] + str x10, [x2] ldr x10, [sp], #0x10 - mov x0, #0xb // =11 - sub x1, x29, #0x28 - str w0, [x1] - mov x0, #0x16 // =22 - sub x1, x29, #0x28 - str w0, [x1, #0x4] - sub x0, x29, #0x28 - ldrsw x0, [x0] - cmp x0, #0xb - cset x22, ne - cbnz x22, - sub x0, x29, #0x28 - ldrsw x0, [x0, #0x4] - cmp x0, #0x16 - cset x22, ne - cbz x22, + mov x2, #0xb // =11 + sub x3, x29, #0x28 + str w2, [x3] + mov x2, #0x16 // =22 + sub x3, x29, #0x28 + str w2, [x3, #0x4] + sub x2, x29, #0x28 + ldrsw x2, [x2] + cmp x2, #0xb + cset x3, ne + cbnz x3, + sub x2, x29, #0x28 + ldrsw x2, [x2, #0x4] + cmp x2, #0x16 + cset x3, ne + cbz x3, adrp x0, add x0, x0, sub x1, x29, #0x28 @@ -130,50 +121,47 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x38 - adrp x1, - add x1, x1, + sub x2, x29, #0x38 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] - ldrb w10, [x1, #0x8] - strb w10, [x0, #0x8] - ldrb w10, [x1, #0x9] - strb w10, [x0, #0x9] - ldrb w10, [x1, #0xa] - strb w10, [x0, #0xa] - ldrb w10, [x1, #0xb] - strb w10, [x0, #0xb] + ldr x10, [x3] + str x10, [x2] + ldrb w10, [x3, #0x8] + strb w10, [x2, #0x8] + ldrb w10, [x3, #0x9] + strb w10, [x2, #0x9] + ldrb w10, [x3, #0xa] + strb w10, [x2, #0xa] + ldrb w10, [x3, #0xb] + strb w10, [x2, #0xb] ldr x10, [sp], #0x10 - sub x0, x29, #0x38 - str w20, [x0] - sub x0, x29, #0x38 - str w21, [x0, #0x8] - sub x0, x29, #0x38 - ldrsw x0, [x0] - cmp x0, #0x2a - cset x0, ne - mov x22, #0x1 // =1 - cbnz x0, - sub x0, x29, #0x38 - ldrsw x0, [x0, #0x4] - cmp x0, #0x0 - cset x0, ne - cmp x0, #0x0 - cset x22, ne - cbnz x22, - sub x0, x29, #0x38 - ldrsw x0, [x0, #0x8] - cmp x0, #0x63 - cset x22, ne - cbz x22, + sub x2, x29, #0x38 + str w0, [x2] + sub x2, x29, #0x38 + str w1, [x2, #0x8] + sub x2, x29, #0x38 + ldrsw x2, [x2] + cmp x2, #0x2a + cset x2, ne + mov x4, #0x1 // =1 + cbnz x2, + sub x2, x29, #0x38 + ldrsw x2, [x2, #0x4] + cmp x2, #0x0 + cset x2, ne + cmp x2, #0x0 + cset x4, ne + cbnz x4, + sub x2, x29, #0x38 + ldrsw x2, [x2, #0x8] + cmp x2, #0x63 + cset x4, ne + cbz x4, adrp x0, add x0, x0, sub x1, x29, #0x38 @@ -185,50 +173,47 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x48 - adrp x1, - add x1, x1, + sub x2, x29, #0x48 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] - ldrb w10, [x1, #0x8] - strb w10, [x0, #0x8] - ldrb w10, [x1, #0x9] - strb w10, [x0, #0x9] - ldrb w10, [x1, #0xa] - strb w10, [x0, #0xa] - ldrb w10, [x1, #0xb] - strb w10, [x0, #0xb] + ldr x10, [x3] + str x10, [x2] + ldrb w10, [x3, #0x8] + strb w10, [x2, #0x8] + ldrb w10, [x3, #0x9] + strb w10, [x2, #0x9] + ldrb w10, [x3, #0xa] + strb w10, [x2, #0xa] + ldrb w10, [x3, #0xb] + strb w10, [x2, #0xb] ldr x10, [sp], #0x10 - sub x0, x29, #0x48 - str w21, [x0, #0x8] - sub x0, x29, #0x48 - str w20, [x0] - sub x0, x29, #0x48 - ldrsw x0, [x0] - cmp x0, #0x2a - cset x0, ne - mov x22, #0x1 // =1 - cbnz x0, - sub x0, x29, #0x48 - ldrsw x0, [x0, #0x4] - cmp x0, #0x0 - cset x0, ne - cmp x0, #0x0 - cset x22, ne - cbnz x22, - sub x0, x29, #0x48 - ldrsw x0, [x0, #0x8] - cmp x0, #0x63 - cset x22, ne - cbz x22, + sub x2, x29, #0x48 + str w1, [x2, #0x8] + sub x2, x29, #0x48 + str w0, [x2] + sub x2, x29, #0x48 + ldrsw x2, [x2] + cmp x2, #0x2a + cset x2, ne + mov x4, #0x1 // =1 + cbnz x2, + sub x2, x29, #0x48 + ldrsw x2, [x2, #0x4] + cmp x2, #0x0 + cset x2, ne + cmp x2, #0x0 + cset x4, ne + cbnz x4, + sub x2, x29, #0x48 + ldrsw x2, [x2, #0x8] + cmp x2, #0x63 + cset x4, ne + cbz x4, adrp x0, add x0, x0, sub x1, x29, #0x48 @@ -240,50 +225,47 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x58 - adrp x1, - add x1, x1, + sub x2, x29, #0x58 + adrp x3, + add x3, x3, str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] - ldrb w10, [x1, #0x8] - strb w10, [x0, #0x8] - ldrb w10, [x1, #0x9] - strb w10, [x0, #0x9] - ldrb w10, [x1, #0xa] - strb w10, [x0, #0xa] - ldrb w10, [x1, #0xb] - strb w10, [x0, #0xb] + ldr x10, [x3] + str x10, [x2] + ldrb w10, [x3, #0x8] + strb w10, [x2, #0x8] + ldrb w10, [x3, #0x9] + strb w10, [x2, #0x9] + ldrb w10, [x3, #0xa] + strb w10, [x2, #0xa] + ldrb w10, [x3, #0xb] + strb w10, [x2, #0xb] ldr x10, [sp], #0x10 + sub x2, x29, #0x58 + str w0, [x2] sub x0, x29, #0x58 - str w20, [x0] - sub x0, x29, #0x58 - str w21, [x0, #0x8] + str w1, [x0, #0x8] sub x0, x29, #0x58 ldrsw x0, [x0] cmp x0, #0x2a cset x0, ne - mov x20, #0x1 // =1 + mov x3, #0x1 // =1 cbnz x0, sub x0, x29, #0x58 ldrsw x0, [x0, #0x4] cmp x0, #0x0 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x3, ne + cbnz x3, sub x0, x29, #0x58 ldrsw x0, [x0, #0x8] cmp x0, #0x63 - cset x20, ne - cbz x20, + cset x3, ne + cbz x3, adrp x0, add x0, x0, sub x1, x29, #0x58 @@ -295,63 +277,60 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x68 - adrp x1, - add x1, x1, + adrp x2, + add x2, x2, str x10, [sp, #-0x10]! - ldr x10, [x1] + ldr x10, [x2] str x10, [x0] - ldrb w10, [x1, #0x8] + ldrb w10, [x2, #0x8] strb w10, [x0, #0x8] - ldrb w10, [x1, #0x9] + ldrb w10, [x2, #0x9] strb w10, [x0, #0x9] - ldrb w10, [x1, #0xa] + ldrb w10, [x2, #0xa] strb w10, [x0, #0xa] - ldrb w10, [x1, #0xb] + ldrb w10, [x2, #0xb] strb w10, [x0, #0xb] ldr x10, [sp], #0x10 sub x0, x29, #0x78 - adrp x1, - add x1, x1, + adrp x2, + add x2, x2, str x10, [sp, #-0x10]! - ldr x10, [x1] + ldr x10, [x2] str x10, [x0] - ldrb w10, [x1, #0x8] + ldrb w10, [x2, #0x8] strb w10, [x0, #0x8] - ldrb w10, [x1, #0x9] + ldrb w10, [x2, #0x9] strb w10, [x0, #0x9] - ldrb w10, [x1, #0xa] + ldrb w10, [x2, #0xa] strb w10, [x0, #0xa] - ldrb w10, [x1, #0xb] + ldrb w10, [x2, #0xb] strb w10, [x0, #0xb] ldr x10, [sp], #0x10 sub x0, x29, #0x78 - str w21, [x0, #0x4] + str w1, [x0, #0x4] sub x0, x29, #0x78 ldrsw x0, [x0] cmp x0, #0x0 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x78 ldrsw x0, [x0, #0x4] cmp x0, #0x63 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x78 ldrsw x0, [x0, #0x8] cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, adrp x0, add x0, x0, sub x1, x29, #0x78 @@ -363,19 +342,13 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/nonconst_local_struct_init.x64.asm b/tests/snapshots/asm/nonconst_local_struct_init.x64.asm index 949efc8e1..d1f5a227a 100644 --- a/tests/snapshots/asm/nonconst_local_struct_init.x64.asm +++ b/tests/snapshots/asm/nonconst_local_struct_init.x64.asm @@ -18,35 +18,32 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x110, %rsp # imm = 0x110 - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movl $0x2a, %ebx - movl $0x63, %r12d - leaq -0x18(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - popq %rdx - leaq -0x18(%rbp), %rax - movl %ebx, (%rax) - leaq -0x18(%rbp), %rax - movl %r12d, 0x4(%rax) - leaq -0x18(%rbp), %rax - movslq (%rax), %rax - cmpq $0x2a, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + subq $0xf0, %rsp + movl $0x2a, %eax + movl $0x63, %ecx + leaq -0x18(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + popq %rax + leaq -0x18(%rbp), %rdx + movl %eax, (%rdx) + leaq -0x18(%rbp), %rdx + movl %ecx, 0x4(%rdx) + leaq -0x18(%rbp), %rdx + movslq (%rdx), %rdx + cmpq $0x2a, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne - leaq -0x18(%rbp), %rax - movslq 0x4(%rax), %rax - cmpq $0x63, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x18(%rbp), %rdx + movslq 0x4(%rdx), %rdx + cmpq $0x63, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je leaq , %rdi leaq -0x18(%rbp), %rax @@ -57,36 +54,33 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq - leaq -0x20(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - popq %rdx - movl $0x7, %eax - leaq -0x20(%rbp), %rcx - movl %eax, (%rcx) - leaq -0x20(%rbp), %rax - movl %r12d, 0x4(%rax) - leaq -0x20(%rbp), %rax - movslq (%rax), %rax - cmpq $0x7, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x20(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + popq %rax + movl $0x7, %edx + leaq -0x20(%rbp), %rsi + movl %edx, (%rsi) + leaq -0x20(%rbp), %rdx + movl %ecx, 0x4(%rdx) + leaq -0x20(%rbp), %rdx + movslq (%rdx), %rdx + cmpq $0x7, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne - leaq -0x20(%rbp), %rax - movslq 0x4(%rax), %rax - cmpq $0x63, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x20(%rbp), %rdx + movslq 0x4(%rdx), %rdx + cmpq $0x63, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je leaq , %rdi leaq -0x20(%rbp), %rax @@ -97,37 +91,34 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq - leaq -0x28(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - popq %rdx - movl $0xb, %eax - leaq -0x28(%rbp), %rcx - movl %eax, (%rcx) - movl $0x16, %eax - leaq -0x28(%rbp), %rcx - movl %eax, 0x4(%rcx) - leaq -0x28(%rbp), %rax - movslq (%rax), %rax - cmpq $0xb, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x28(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + popq %rax + movl $0xb, %edx + leaq -0x28(%rbp), %rsi + movl %edx, (%rsi) + movl $0x16, %edx + leaq -0x28(%rbp), %rsi + movl %edx, 0x4(%rsi) + leaq -0x28(%rbp), %rdx + movslq (%rdx), %rdx + cmpq $0xb, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne - leaq -0x28(%rbp), %rax - movslq 0x4(%rax), %rax - cmpq $0x16, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x28(%rbp), %rdx + movslq 0x4(%rdx), %rdx + cmpq $0x16, %rdx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je leaq , %rdi leaq -0x28(%rbp), %rax @@ -138,54 +129,51 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq - leaq -0x38(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - movzbq 0x8(%rcx), %rdx - movb %dl, 0x8(%rax) - movzbq 0x9(%rcx), %rdx - movb %dl, 0x9(%rax) - movzbq 0xa(%rcx), %rdx - movb %dl, 0xa(%rax) - movzbq 0xb(%rcx), %rdx - movb %dl, 0xb(%rax) - popq %rdx - leaq -0x38(%rbp), %rax - movl %ebx, (%rax) - leaq -0x38(%rbp), %rax - movl %r12d, 0x8(%rax) - leaq -0x38(%rbp), %rax - movslq (%rax), %rax - cmpq $0x2a, %rax - setne %al - movzbq %al, %rax - movl $0x1, %r13d - testq %rax, %rax + leaq -0x38(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movzbq 0x8(%rsi), %rax + movb %al, 0x8(%rdx) + movzbq 0x9(%rsi), %rax + movb %al, 0x9(%rdx) + movzbq 0xa(%rsi), %rax + movb %al, 0xa(%rdx) + movzbq 0xb(%rsi), %rax + movb %al, 0xb(%rdx) + popq %rax + leaq -0x38(%rbp), %rdx + movl %eax, (%rdx) + leaq -0x38(%rbp), %rdx + movl %ecx, 0x8(%rdx) + leaq -0x38(%rbp), %rdx + movslq (%rdx), %rdx + cmpq $0x2a, %rdx + setne %dl + movzbq %dl, %rdx + movl $0x1, %edi + testq %rdx, %rdx jne - leaq -0x38(%rbp), %rax - movslq 0x4(%rax), %rax - testq %rax, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x38(%rbp), %rdx + movslq 0x4(%rdx), %rdx + testq %rdx, %rdx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi jne - leaq -0x38(%rbp), %rax - movslq 0x8(%rax), %rax - cmpq $0x63, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x38(%rbp), %rdx + movslq 0x8(%rdx), %rdx + cmpq $0x63, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi je leaq , %rdi leaq -0x38(%rbp), %rax @@ -198,54 +186,51 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq - leaq -0x48(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - movzbq 0x8(%rcx), %rdx - movb %dl, 0x8(%rax) - movzbq 0x9(%rcx), %rdx - movb %dl, 0x9(%rax) - movzbq 0xa(%rcx), %rdx - movb %dl, 0xa(%rax) - movzbq 0xb(%rcx), %rdx - movb %dl, 0xb(%rax) - popq %rdx - leaq -0x48(%rbp), %rax - movl %r12d, 0x8(%rax) - leaq -0x48(%rbp), %rax - movl %ebx, (%rax) - leaq -0x48(%rbp), %rax - movslq (%rax), %rax - cmpq $0x2a, %rax - setne %al - movzbq %al, %rax - movl $0x1, %r13d - testq %rax, %rax + leaq -0x48(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movzbq 0x8(%rsi), %rax + movb %al, 0x8(%rdx) + movzbq 0x9(%rsi), %rax + movb %al, 0x9(%rdx) + movzbq 0xa(%rsi), %rax + movb %al, 0xa(%rdx) + movzbq 0xb(%rsi), %rax + movb %al, 0xb(%rdx) + popq %rax + leaq -0x48(%rbp), %rdx + movl %ecx, 0x8(%rdx) + leaq -0x48(%rbp), %rdx + movl %eax, (%rdx) + leaq -0x48(%rbp), %rdx + movslq (%rdx), %rdx + cmpq $0x2a, %rdx + setne %dl + movzbq %dl, %rdx + movl $0x1, %edi + testq %rdx, %rdx jne - leaq -0x48(%rbp), %rax - movslq 0x4(%rax), %rax - testq %rax, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x48(%rbp), %rdx + movslq 0x4(%rdx), %rdx + testq %rdx, %rdx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi jne - leaq -0x48(%rbp), %rax - movslq 0x8(%rax), %rax - cmpq $0x63, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + leaq -0x48(%rbp), %rdx + movslq 0x8(%rdx), %rdx + cmpq $0x63, %rdx + setne %dil + movzbq %dil, %rdi + testq %rdi, %rdi je leaq , %rdi leaq -0x48(%rbp), %rax @@ -258,36 +243,33 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq + leaq -0x58(%rbp), %rdx + leaq , %rsi + pushq %rax + movq (%rsi), %rax + movq %rax, (%rdx) + movzbq 0x8(%rsi), %rax + movb %al, 0x8(%rdx) + movzbq 0x9(%rsi), %rax + movb %al, 0x9(%rdx) + movzbq 0xa(%rsi), %rax + movb %al, 0xa(%rdx) + movzbq 0xb(%rsi), %rax + movb %al, 0xb(%rdx) + popq %rax + leaq -0x58(%rbp), %rdx + movl %eax, (%rdx) leaq -0x58(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - movzbq 0x8(%rcx), %rdx - movb %dl, 0x8(%rax) - movzbq 0x9(%rcx), %rdx - movb %dl, 0x9(%rax) - movzbq 0xa(%rcx), %rdx - movb %dl, 0xa(%rax) - movzbq 0xb(%rcx), %rdx - movb %dl, 0xb(%rax) - popq %rdx - leaq -0x58(%rbp), %rax - movl %ebx, (%rax) - leaq -0x58(%rbp), %rax - movl %r12d, 0x8(%rax) + movl %ecx, 0x8(%rax) leaq -0x58(%rbp), %rax movslq (%rax), %rax cmpq $0x2a, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %esi testq %rax, %rax jne leaq -0x58(%rbp), %rax @@ -296,16 +278,16 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne leaq -0x58(%rbp), %rax movslq 0x8(%rax), %rax cmpq $0x63, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je leaq , %rdi leaq -0x58(%rbp), %rax @@ -318,48 +300,45 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x6, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq leaq -0x68(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - movzbq 0x8(%rcx), %rdx - movb %dl, 0x8(%rax) - movzbq 0x9(%rcx), %rdx - movb %dl, 0x9(%rax) - movzbq 0xa(%rcx), %rdx - movb %dl, 0xa(%rax) - movzbq 0xb(%rcx), %rdx - movb %dl, 0xb(%rax) - popq %rdx + leaq , %rdx + pushq %rcx + movq (%rdx), %rcx + movq %rcx, (%rax) + movzbq 0x8(%rdx), %rcx + movb %cl, 0x8(%rax) + movzbq 0x9(%rdx), %rcx + movb %cl, 0x9(%rax) + movzbq 0xa(%rdx), %rcx + movb %cl, 0xa(%rax) + movzbq 0xb(%rdx), %rcx + movb %cl, 0xb(%rax) + popq %rcx leaq -0x78(%rbp), %rax - leaq , %rcx - pushq %rdx - movq (%rcx), %rdx - movq %rdx, (%rax) - movzbq 0x8(%rcx), %rdx - movb %dl, 0x8(%rax) - movzbq 0x9(%rcx), %rdx - movb %dl, 0x9(%rax) - movzbq 0xa(%rcx), %rdx - movb %dl, 0xa(%rax) - movzbq 0xb(%rcx), %rdx - movb %dl, 0xb(%rax) - popq %rdx + leaq , %rdx + pushq %rcx + movq (%rdx), %rcx + movq %rcx, (%rax) + movzbq 0x8(%rdx), %rcx + movb %cl, 0x8(%rax) + movzbq 0x9(%rdx), %rcx + movb %cl, 0x9(%rax) + movzbq 0xa(%rdx), %rcx + movb %cl, 0xa(%rax) + movzbq 0xb(%rdx), %rcx + movb %cl, 0xb(%rax) + popq %rcx leaq -0x78(%rbp), %rax - movl %r12d, 0x4(%rax) + movl %ecx, 0x4(%rax) leaq -0x78(%rbp), %rax movslq (%rax), %rax testq %rax, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x78(%rbp), %rax @@ -368,16 +347,16 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x78(%rbp), %rax movslq 0x8(%rax), %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rdi leaq -0x78(%rbp), %rax @@ -390,17 +369,11 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x7, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x110, %rsp # imm = 0x110 + addq $0xf0, %rsp popq %rbp retq jmp @@ -414,5 +387,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm index 4f73df7fa..673b2ab06 100644 --- a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm +++ b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm @@ -6,69 +6,9 @@ Disassembly of section .text: <.text>: mov x29, #0x0 // =0 mov x0, sp - mov x1, #0x2b0 // =688 + mov x1, #0x230 // =560 movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x19, [sp, #0x10] - sxtw x2, w2 - adrp x3, - add x3, x3, - mov x16, x3 - mov x3, x2 - mov x2, x1 - mov x1, x0 - mov x0, x16 - bl - sxtw x0, w0 - mov x20, #0x0 // =0 - mov x0, x20 - bl - sxtw x0, w0 - brk #0 - mov x0, x20 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - -
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - mov x20, #0x7 // =7 - cmp x20, #0x7 - b.ne - mov x1, #0x0 // =0 - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - mov x2, #0x13 // =19 - bl - mov x1, x0 - add x0, x20, #0x1 - sxtw x0, w0 - cmp x0, #0x8 - b.ne - mov x1, #0x0 // =0 - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - mov x2, #0x14 // =20 - bl - mov x1, x0 mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm index e6496832e..3362c8253 100644 --- a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm +++ b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm @@ -10,61 +10,6 @@ Disassembly of section .text: callq ud2 -<__c5_assert_fail>: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movslq %edx, %rdx - leaq , %rax - movq %rdx, %rcx - movq %rsi, %rdx - movq %rdi, %rsi - movq %rax, %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rbx, %rbx - movq %rbx, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - ud2 - movq %rbx, %rax - movq (%rsp), %rbx - addq $0x10, %rsp - popq %rbp - retq -
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) - movl $0x7, %ebx - cmpq $0x7, %rbx - jne - xorq %rcx, %rcx - jmp - leaq , %rdi - leaq , %rsi - movl $0x13, %edx - callq - movq %rax, %rcx - leaq 0x1(%rbx), %rax - movslq %eax, %rax - cmpq $0x8, %rax - jne - xorq %rcx, %rcx - jmp - leaq , %rdi - leaq , %rsi - movl $0x14, %edx - callq - movq %rax, %rcx xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/octal_literal.aarch64.asm b/tests/snapshots/asm/octal_literal.aarch64.asm index eb390240a..d29a10cfe 100644 --- a/tests/snapshots/asm/octal_literal.aarch64.asm +++ b/tests/snapshots/asm/octal_literal.aarch64.asm @@ -10,29 +10,21 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x2a // =42 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - mov x0, #0x2a // =42 - ret diff --git a/tests/snapshots/asm/octal_literal.x64.asm b/tests/snapshots/asm/octal_literal.x64.asm index ed3fc1112..792f47853 100644 --- a/tests/snapshots/asm/octal_literal.x64.asm +++ b/tests/snapshots/asm/octal_literal.x64.asm @@ -11,30 +11,22 @@ Disassembly of section .text: ud2
: - jmp + movl $0x2a, %eax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - movl $0x2a, %eax - retq addb %al, (%rax) diff --git a/tests/snapshots/asm/oob_read.aarch64.asm b/tests/snapshots/asm/oob_read.aarch64.asm index 55a4305ab..ba4d65a5d 100644 --- a/tests/snapshots/asm/oob_read.aarch64.asm +++ b/tests/snapshots/asm/oob_read.aarch64.asm @@ -10,14 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x8 // =8 bl ldrsw x0, [x0, #0x190] - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/oob_read.x64.asm b/tests/snapshots/asm/oob_read.x64.asm index 1c62d6e7a..96e35c960 100644 --- a/tests/snapshots/asm/oob_read.x64.asm +++ b/tests/snapshots/asm/oob_read.x64.asm @@ -13,12 +13,11 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x8, %edi xorl %eax, %eax callq movslq 0x190(%rax), %rax - addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/optimizer_fp_arg_mask_remap.aarch64.asm b/tests/snapshots/asm/optimizer_fp_arg_mask_remap.aarch64.asm index 8ed8b887d..c94d5d7cd 100644 --- a/tests/snapshots/asm/optimizer_fp_arg_mask_remap.aarch64.asm +++ b/tests/snapshots/asm/optimizer_fp_arg_mask_remap.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str d8, [sp] - str d9, [sp, #0x8] + stp d8, d9, [sp, #-0x90]! str d10, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 mov x0, #0x3fe0000000000000 // =4602678819172646912 fmov d16, x0 sub x17, x29, #0x8 @@ -52,12 +50,10 @@ Disassembly of section .text: cset x1, gt cbz x1, mov x0, #0x1 // =1 - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr d10, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x90 ret mov x0, #0xf1aa // =61866 movk x0, #0x4dd2, lsl #16 @@ -76,12 +72,10 @@ Disassembly of section .text: cset x1, gt cbz x1, mov x0, #0x1 // =1 - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr d10, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x90 ret mov x0, #0x4000000000000000 // =4611686018427387904 fmov d17, x0 @@ -89,12 +83,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr d10, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x90 ret mov x0, #0x872b // =34603 movk x0, #0xd916, lsl #16 @@ -113,20 +105,16 @@ Disassembly of section .text: cset x1, gt cbz x1, mov x0, #0x1 // =1 - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr d10, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x90 ret mov x0, #0x13 // =19 - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr d10, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr d10, [sp, #0x10] + ldp d8, d9, [sp], #0x90 ret b b diff --git a/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm b/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm index bee1fb173..56d7c8eb9 100644 --- a/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm +++ b/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm @@ -92,19 +92,14 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x130 str x20, [sp] - str x21, [sp, #0x8] - mov x20, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s2, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s3, d16 + mov x20, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + mov x2, #0x40400000 // =1077936128 + mov x3, #0x40800000 // =1082130432 + fmov d0, x20 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 bl sub x16, x29, #0xa8 str s0, [x16] @@ -122,62 +117,52 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0x10 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x10 ldr s0, [x0, #0x4] - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x10 ldr s0, [x0, #0x8] - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x10 ldr s0, [x0, #0xc] - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 - cset x21, ne - cbz x21, + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 + cset x1, ne + cbz x1, mov x0, #0x1 // =1 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x130 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s2, d16 - mov x0, #0x4012000000000000 // =4616752568008179712 - fmov d16, x0 - fcvt s3, d16 - mov x0, #0x4016000000000000 // =4617878467915022336 - fmov d16, x0 - fcvt s4, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + mov x2, #0x40600000 // =1080033280 + mov x3, #0x40900000 // =1083179008 + mov x4, #0x40b00000 // =1085276160 + fmov d0, x20 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 + fmov d4, x4 sub x8, x29, #0xd8 bl sub x0, x29, #0xd8 @@ -199,55 +184,49 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0x38 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x38 ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x38 ldr s0, [x0, #0x8] - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 - cset x21, ne - mov x20, #0x1 // =1 - cbnz x21, + cset x1, ne + mov x2, #0x1 // =1 + cbnz x1, sub x0, x29, #0x38 ldr s0, [x0, #0xc] - mov x0, #0x4012000000000000 // =4616752568008179712 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40900000 // =1083179008 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x38 ldr s0, [x0, #0x10] - mov x0, #0x4016000000000000 // =4617878467915022336 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 - cset x20, ne - cbz x20, + mov x0, #0x40b00000 // =1085276160 + fmov s17, w0 + fcmp s0, s17 + cset x2, ne + cbz x2, mov x0, #0x2 // =2 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x130 ldp x29, x30, [sp], #0x10 ret @@ -298,13 +277,11 @@ Disassembly of section .text: cbz x2, mov x0, #0x3 // =3 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x130 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 ldr x20, [sp] - ldr x21, [sp, #0x8] add sp, sp, #0x130 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/out_pointer_return_float_args.x64.asm b/tests/snapshots/asm/out_pointer_return_float_args.x64.asm index b49b87843..6808d3d49 100644 --- a/tests/snapshots/asm/out_pointer_return_float_args.x64.asm +++ b/tests/snapshots/asm/out_pointer_return_float_args.x64.asm @@ -145,19 +145,14 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x170, %rsp # imm = 0x170 movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movabsq $0x3ff0000000000000, %rbx # imm = 0x3FF0000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm3 + movl $0x3f800000, %ebx # imm = 0x3F800000 + movl $0x40000000, %esi # imm = 0x40000000 + movl $0x40400000, %edx # imm = 0x40400000 + movl $0x40800000, %ecx # imm = 0x40800000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 + movq %rdx, %xmm2 + movq %rcx, %xmm3 callq movsd %xmm0, -0xa8(%rbp,%riz) movsd %xmm1, -0xa0(%rbp,%riz) @@ -172,105 +167,95 @@ Disassembly of section .text: movq %rcx, %rax leaq -0x10(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x10(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x10(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setne %r12b - movzbq %r12b, %r12 + ucomiss %xmm15, %xmm0 + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %r12 - testq %r12, %r12 + orq %r10, %rcx + testq %rcx, %rcx je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x170, %rsp # imm = 0x170 popq %rbp retq leaq -0xd8(%rbp), %rdi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0xe8(%rbp) - movq -0xe8(%rbp), %rsi - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %xmm0, %r10 + cvtss2sd %xmm14, %xmm1 + movq %xmm1, %r10 movq %r10, -0xf0(%rbp) - movq -0xf0(%rbp), %rdx - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %xmm0, %r10 + cvtss2sd %xmm14, %xmm2 + movq %xmm2, %r10 movq %r10, -0xf8(%rbp) - movq -0xf8(%rbp), %rcx - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %xmm0, %r10 + cvtss2sd %xmm14, %xmm3 + movq %xmm3, %r10 movq %r10, -0x100(%rbp) - movq -0x100(%rbp), %r8 - movabsq $0x4016000000000000, %rax # imm = 0x4016000000000000 + movl $0x40b00000, %eax # imm = 0x40B00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %xmm0, %r10 + cvtss2sd %xmm14, %xmm4 + movq %xmm4, %r10 movq %r10, -0x108(%rbp) - movq -0x108(%rbp), %r9 + movq %xmm0, %rsi + movq %xmm1, %rdx + movq %xmm2, %rcx + movq %xmm3, %r8 + movq %xmm4, %r9 callq leaq -0xd8(%rbp), %rax leaq -0x38(%rbp), %rcx @@ -291,83 +276,77 @@ Disassembly of section .text: movq %rcx, %rax leaq -0x38(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x38(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x38(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - movl $0x1, %ebx - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + movl $0x1, %edx + testq %rcx, %rcx jne leaq -0x38(%rbp), %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b movzbq %r10b, %r10 orq %r10, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x38(%rbp), %rax movss 0x10(%rax,%riz), %xmm0 - movabsq $0x4016000000000000, %rax # imm = 0x4016000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40b00000, %eax # imm = 0x40B00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + ucomiss %xmm15, %xmm0 + setne %dl + movzbq %dl, %rdx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rdx + testq %rdx, %rdx je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x170, %rsp # imm = 0x170 popq %rbp retq @@ -429,13 +408,11 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x170, %rsp # imm = 0x170 popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x170, %rsp # imm = 0x170 popq %rbp retq @@ -448,3 +425,4 @@ Disassembly of section .text: jmp jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/packed_bitfield_repack.aarch64.asm b/tests/snapshots/asm/packed_bitfield_repack.aarch64.asm index 51f763818..0ee6a1dac 100644 --- a/tests/snapshots/asm/packed_bitfield_repack.aarch64.asm +++ b/tests/snapshots/asm/packed_bitfield_repack.aarch64.asm @@ -34,20 +34,15 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 - mov x1, #0x55 // =85 - ldrb w2, [x0] + ldrb w1, [x0] mov x17, #0xff00 // =65280 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x55 // =85 + orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x8 mov x1, #0x7 // =7 @@ -71,13 +66,13 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x10 - mov x1, #0xfde8 // =65000 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfffe0000 // =4294836224 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0xfde8 // =65000 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x10 ldrh w1, [x0, #0x2] @@ -86,8 +81,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x3e8 // =1000 - orr x1, x1, x2 + mov x17, #0x3e8 // =1000 + orr x1, x1, x17 strh w1, [x0, #0x2] sub x0, x29, #0x10 mov x1, #0x9 // =9 @@ -129,14 +124,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 - mov x1, #0x3 // =3 - ldrb w2, [x0] + ldrb w1, [x0] mov x17, #0xfff8 // =65528 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x3 // =3 + orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x18 ldrh w1, [x0] @@ -145,8 +140,8 @@ Disassembly of section .text: movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 and x1, x1, x17 - mov x2, #0x1e0 // =480 - orr x1, x1, x2 + mov x17, #0x1e0 // =480 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x18 mov x1, #0x4 // =4 @@ -186,13 +181,13 @@ Disassembly of section .text: strb w1, [x0] sub x0, x29, #0x20 add x0, x0, #0x1 - mov x1, #0x7530 // =30000 - ldrh w2, [x0] + ldrh w1, [x0] mov x17, #0xffff0000 // =4294901760 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x7530 // =30000 + orr x1, x1, x17 strh w1, [x0] sub x0, x29, #0x20 ldrb w0, [x0] @@ -245,3 +240,7 @@ Disassembly of section .text: b b b + mov x0, #0x4 // =4 + add sp, sp, #0x70 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/packed_bitfield_repack.x64.asm b/tests/snapshots/asm/packed_bitfield_repack.x64.asm index 12b6325e0..455a71592 100644 --- a/tests/snapshots/asm/packed_bitfield_repack.x64.asm +++ b/tests/snapshots/asm/packed_bitfield_repack.x64.asm @@ -38,16 +38,10 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - jmp - movl $0x4, %eax - addq $0x70, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax - movl $0x55, %ecx - movzbq (%rax), %rdx - andq $-0x100, %rdx - orq %rdx, %rcx + movzbq (%rax), %rcx + andq $-0x100, %rcx + orq $0x55, %rcx movb %cl, (%rax) leaq -0x8(%rbp), %rax movl $0x7, %ecx @@ -72,16 +66,14 @@ Disassembly of section .text: popq %rbp retq leaq -0x10(%rbp), %rax - movl $0xfde8, %ecx # imm = 0xFDE8 - movl (%rax), %edx - andq $-0x20000, %rdx # imm = 0xFFFE0000 - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x20000, %rcx # imm = 0xFFFE0000 + orq $0xfde8, %rcx # imm = 0xFDE8 movl %ecx, (%rax) leaq -0x10(%rbp), %rax movzwq 0x2(%rax), %rcx andq $-0x7ff, %rcx # imm = 0xF801 - movl $0x3e8, %edx # imm = 0x3E8 - orq %rdx, %rcx + orq $0x3e8, %rcx # imm = 0x3E8 movw %cx, 0x2(%rax) leaq -0x10(%rbp), %rax movl $0x9, %ecx @@ -123,16 +115,14 @@ Disassembly of section .text: popq %rbp retq leaq -0x18(%rbp), %rax - movl $0x3, %ecx - movzbq (%rax), %rdx - andq $-0x8, %rdx - orq %rdx, %rcx + movzbq (%rax), %rcx + andq $-0x8, %rcx + orq $0x3, %rcx movb %cl, (%rax) leaq -0x18(%rbp), %rax movzwq (%rax), %rcx andq $-0x3f9, %rcx # imm = 0xFC07 - movl $0x1e0, %edx # imm = 0x1E0 - orq %rdx, %rcx + orq $0x1e0, %rcx # imm = 0x1E0 movw %cx, (%rax) leaq -0x18(%rbp), %rax movl $0x4, %ecx @@ -178,10 +168,9 @@ Disassembly of section .text: movb %cl, (%rax) leaq -0x20(%rbp), %rax incq %rax - movl $0x7530, %ecx # imm = 0x7530 - movzwq (%rax), %rdx - andq $-0x10000, %rdx # imm = 0xFFFF0000 - orq %rdx, %rcx + movzwq (%rax), %rcx + andq $-0x10000, %rcx # imm = 0xFFFF0000 + orq $0x7530, %rcx # imm = 0x7530 movw %cx, (%rax) leaq -0x20(%rbp), %rax movsbq (%rax), %rax @@ -233,5 +222,8 @@ Disassembly of section .text: jmp jmp jmp + movl $0x4, %eax + addq $0x70, %rsp + popq %rbp + retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm b/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm index 6fb5cfdc9..0d4343f55 100644 --- a/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm +++ b/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x17, #0x86a0 // =34464 movk x17, #0x1, lsl #16 mul x0, x0, x17 @@ -31,8 +28,6 @@ Disassembly of section .text: add x0, x0, x1 add x0, x0, x5 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: @@ -41,29 +36,15 @@ Disassembly of section .text: sub sp, sp, #0x50 mov x0, #0x7 // =7 stur w0, [x29, #-0x8] - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - sub x3, x29, #0x8 - mov x4, #0x4 // =4 - mov x5, #0x5 // =5 - mov x17, #0x86a0 // =34464 - movk x17, #0x1, lsl #16 - mul x0, x0, x17 - mov x17, #0x2710 // =10000 - mul x1, x1, x17 - add x0, x0, x1 - mov x17, #0x3e8 // =1000 - mul x1, x2, x17 - add x0, x0, x1 - ldrsw x1, [x3] + sub x1, x29, #0x8 + ldrsw x0, [x1] mov x17, #0x64 // =100 - mul x1, x1, x17 - add x0, x0, x1 - mov x17, #0xa // =10 - mul x1, x4, x17 - add x0, x0, x1 - add x0, x0, x5 + mul x0, x0, x17 + mov x17, #0xe078 // =57464 + movk x17, #0x1, lsl #16 + add x0, x0, x17 + add x0, x0, #0x28 + add x0, x0, #0x5 sxtw x0, w0 mov x17, #0xe361 // =58209 movk x17, #0x1, lsl #16 diff --git a/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm b/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm index e907fd96d..e3783e16d 100644 --- a/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm +++ b/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp imulq $0x186a0, %rdi, %rax # imm = 0x186A0 imulq $0x2710, %rsi, %rsi # imm = 0x2710 addq %rsi, %rax @@ -26,8 +23,6 @@ Disassembly of section .text: addq %rcx, %rax addq %r9, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -36,23 +31,12 @@ Disassembly of section .text: subq $0x50, %rsp movl $0x7, %eax movl %eax, -0x8(%rbp) - movl $0x1, %eax - movl $0x2, %ecx - movl $0x3, %edx - leaq -0x8(%rbp), %rsi - movl $0x4, %edi - movl $0x5, %r8d - imulq $0x186a0, %rax, %rax # imm = 0x186A0 - imulq $0x2710, %rcx, %rcx # imm = 0x2710 - addq %rcx, %rax - imulq $0x3e8, %rdx, %rcx # imm = 0x3E8 - addq %rcx, %rax - movslq (%rsi), %rcx - imulq $0x64, %rcx, %rcx - addq %rcx, %rax - imulq $0xa, %rdi, %rcx - addq %rcx, %rax - addq %r8, %rax + leaq -0x8(%rbp), %rcx + movslq (%rcx), %rax + imulq $0x64, %rax, %rax + addq $0x1e078, %rax # imm = 0x1E078 + addq $0x28, %rax + addq $0x5, %rax movslq %eax, %rax cmpq $0x1e361, %rax # imm = 0x1E361 je @@ -64,3 +48,5 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/param_incoming_reg_clobber.aarch64.asm b/tests/snapshots/asm/param_incoming_reg_clobber.aarch64.asm index 2cce03b92..36233a196 100644 --- a/tests/snapshots/asm/param_incoming_reg_clobber.aarch64.asm +++ b/tests/snapshots/asm/param_incoming_reg_clobber.aarch64.asm @@ -16,18 +16,18 @@ Disassembly of section .text: mov x29, sp mov x3, x0 stur x2, [x29, #0x30] - ldur w0, [x29, #0x30] - sub x2, x0, #0x1 - stur w2, [x29, #0x30] - cmp x0, #0x0 - b.eq + b add x0, x3, #0x1 add x2, x1, #0x1 ldrb w1, [x1] strb w1, [x3] mov x3, x0 mov x1, x2 - b + ldur w0, [x29, #0x30] + sub x2, x0, #0x1 + stur w2, [x29, #0x30] + cmp x0, #0x0 + b.ne mov x0, #0x0 // =0 ldp x29, x30, [sp], #0x10 add sp, sp, #0x30 @@ -39,88 +39,87 @@ Disassembly of section .text: sub sp, sp, #0x20 stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - mov x20, x0 mov x4, x1 sxtw x3, w3 stur x2, [x29, #0x30] cmp x3, #0x0 b.ne ldur w2, [x29, #0x30] - mov x0, x20 mov x1, x4 bl mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x40 ret - ldur w0, [x29, #0x30] - sub x0, x0, #0x1 - mov w0, w0 - add x1, x20, x0 - ldur w0, [x29, #0x30] - sub x2, x0, #0x1 - stur w2, [x29, #0x30] - cmp x0, #0x0 - b.eq + ldur w1, [x29, #0x30] + sub x1, x1, #0x1 + mov w1, w1 + add x1, x0, x1 + b sub x0, x1, #0x1 add x2, x4, #0x1 ldrb w3, [x4] strb w3, [x1] mov x1, x0 mov x4, x2 + ldur w0, [x29, #0x30] + sub x2, x0, #0x1 + stur w2, [x29, #0x30] + cmp x0, #0x0 + b.eq b b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b + str x20, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x8 - sxtw x2, w1 - add x0, x0, x2 - add x2, x2, #0x1 - mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - b + add x0, x0, #0x0 + mov x1, #0x1 // =1 + strb w1, [x0] + sub x0, x29, #0x8 + mov x1, #0x2 // =2 + strb w1, [x0, #0x1] + sub x0, x29, #0x8 + mov x1, #0x3 // =3 + strb w1, [x0, #0x2] + sub x0, x29, #0x8 + mov x1, #0x4 // =4 + strb w1, [x0, #0x3] + sub x0, x29, #0x8 + mov x1, #0x5 // =5 + strb w1, [x0, #0x4] + sub x0, x29, #0x8 + mov x1, #0x6 // =6 + strb w1, [x0, #0x5] + sub x0, x29, #0x8 + mov x1, #0x7 // =7 + strb w1, [x0, #0x6] + sub x0, x29, #0x8 + mov x1, #0x8 // =8 + strb w1, [x0, #0x7] sub x0, x29, #0x10 sub x1, x29, #0x8 mov x2, #0x8 // =8 mov x3, #0x1 // =1 bl - mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0x8 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 + mov x1, #0x0 // =0 b - sub x0, x29, #0x10 - sxtw x1, w20 - add x0, x0, x1 - ldrb w0, [x0] - mov x2, #0x8 // =8 - sub x1, x2, x1 - sxtw x1, w1 + sub x2, x29, #0x10 + add x2, x2, x0 + ldrb w2, [x2] + mov x3, #0x8 // =8 + sub x3, x3, x0 + sxtw x3, w3 mov x17, #0xff // =255 - and x1, x1, x17 - cmp x0, x1 - b.eq - b + and x3, x3, x17 + cmp x2, x3 + b.ne + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x8 + b.lt sub x0, x29, #0x10 sub x1, x29, #0x8 mov x2, #0x8 // =8 @@ -128,40 +127,32 @@ Disassembly of section .text: mov x3, x20 bl b - add x0, x20, #0xa - sxtw x0, w0 - ldr x20, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b + sub x1, x29, #0x10 + add x1, x1, x0 + ldrb w1, [x1] + add x2, x0, #0x1 + sxtw x2, w2 + mov x17, #0xff // =255 + and x2, x2, x17 + cmp x1, x2 + b.ne + add x20, x0, #0x1 sxtw x0, w20 cmp x0, #0x8 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 - b - sub x0, x29, #0x10 - sxtw x1, w20 - add x0, x0, x1 - ldrb w0, [x0] - add x1, x1, #0x1 - sxtw x1, w1 - mov x17, #0xff // =255 - and x1, x1, x17 - cmp x0, x1 - b.eq - b + b.lt mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret add x0, x20, #0x14 sxtw x0, w0 - ldr x20, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 ret + add x0, x1, #0xa + sxtw x0, w0 + ldp x29, x30, [sp, #0x50] + ldr x20, [sp], #0x60 + ret + b b diff --git a/tests/snapshots/asm/param_incoming_reg_clobber.x64.asm b/tests/snapshots/asm/param_incoming_reg_clobber.x64.asm index 064a9555d..fd932d6f8 100644 --- a/tests/snapshots/asm/param_incoming_reg_clobber.x64.asm +++ b/tests/snapshots/asm/param_incoming_reg_clobber.x64.asm @@ -18,18 +18,18 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp movq %rdx, 0x30(%rbp) - movl 0x30(%rbp), %eax - leaq -0x1(%rax), %rcx - movl %ecx, 0x30(%rbp) - testq %rax, %rax - je + jmp leaq 0x1(%rdi), %rax leaq 0x1(%rsi), %rcx movsbq (%rsi), %rdx movb %dl, (%rdi) movq %rax, %rdi movq %rcx, %rsi - jmp + movl 0x30(%rbp), %eax + leaq -0x1(%rax), %rcx + movl %ecx, 0x30(%rbp) + testq %rax, %rax + jne xorq %rax, %rax popq %rbp popq %r11 @@ -44,19 +44,13 @@ Disassembly of section .text: pushq %r10 pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movq %rdi, %rbx movslq %ecx, %rcx movq %rdx, 0x30(%rbp) testq %rcx, %rcx jne movl 0x30(%rbp), %edx - movq %rbx, %rdi callq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x10, %rsp popq %rbp popq %r11 addq $0x40, %rsp @@ -65,18 +59,19 @@ Disassembly of section .text: movl 0x30(%rbp), %eax decq %rax movl %eax, %eax - leaq (%rbx,%rax), %rcx - movl 0x30(%rbp), %eax - leaq -0x1(%rax), %rdx - movl %edx, 0x30(%rbp) - testq %rax, %rax - je + leaq (%rdi,%rax), %rcx + jmp leaq -0x1(%rcx), %rax leaq 0x1(%rsi), %rdx movsbq (%rsi), %rsi movb %sil, (%rcx) movq %rax, %rcx movq %rdx, %rsi + movl 0x30(%rbp), %eax + leaq -0x1(%rax), %rdx + movl %edx, 0x30(%rbp) + testq %rax, %rax + je jmp jmp @@ -85,47 +80,51 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x50, %rsp movq %rbx, (%rsp) - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x8(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - incq %rdx - movslq %edx, %rsi - movb %sil, (%rax) - jmp + addq $0x0, %rax + movl $0x1, %ecx + movb %cl, (%rax) + leaq -0x8(%rbp), %rax + movl $0x2, %ecx + movb %cl, 0x1(%rax) + leaq -0x8(%rbp), %rax + movl $0x3, %ecx + movb %cl, 0x2(%rax) + leaq -0x8(%rbp), %rax + movl $0x4, %ecx + movb %cl, 0x3(%rax) + leaq -0x8(%rbp), %rax + movl $0x5, %ecx + movb %cl, 0x4(%rax) + leaq -0x8(%rbp), %rax + movl $0x6, %ecx + movb %cl, 0x5(%rax) + leaq -0x8(%rbp), %rax + movl $0x7, %ecx + movb %cl, 0x6(%rax) + leaq -0x8(%rbp), %rax + movl $0x8, %ecx + movb %cl, 0x7(%rax) leaq -0x10(%rbp), %rdi leaq -0x8(%rbp), %rsi movl $0x8, %edx movl $0x1, %ecx callq - xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - jmp - leaq -0x10(%rbp), %rax - movslq %ebx, %rcx - addq %rcx, %rax - movsbq (%rax), %rax - movl $0x8, %edx - movq %rcx, %r10 - movq %rdx, %rcx - subq %r10, %rcx - movslq %ecx, %rdx - movsbq %dl, %rcx - cmpq %rcx, %rax - je + xorq %rcx, %rcx jmp + leaq -0x10(%rbp), %rdx + addq %rax, %rdx + movsbq (%rdx), %rdx + movl $0x8, %esi + subq %rax, %rsi + movslq %esi, %rdi + movsbq %dil, %rsi + cmpq %rsi, %rdx + jne + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x8, %rax + jl leaq -0x10(%rbp), %rdi leaq -0x8(%rbp), %rsi movl $0x8, %edx @@ -133,30 +132,18 @@ Disassembly of section .text: movq %rbx, %rcx callq jmp - leaq 0xa(%rbx), %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0x50, %rsp - popq %rbp - retq - jmp + leaq -0x10(%rbp), %rcx + addq %rax, %rcx + movsbq (%rcx), %rcx + leaq 0x1(%rax), %rdx + movslq %edx, %rsi + movsbq %sil, %rdx + cmpq %rdx, %rcx + jne + leaq 0x1(%rax), %rbx movslq %ebx, %rax cmpq $0x8, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - jmp - leaq -0x10(%rbp), %rax - movslq %ebx, %rcx - addq %rcx, %rax - movsbq (%rax), %rax - incq %rcx - movslq %ecx, %rdx - movsbq %dl, %rcx - cmpq %rcx, %rax - je - jmp + jl xorq %rax, %rax movq (%rsp), %rbx addq $0x50, %rsp @@ -168,5 +155,11 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + leaq 0xa(%rcx), %rax + movslq %eax, %rax + movq (%rsp), %rbx + addq $0x50, %rsp + popq %rbp + retq + jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/param_reg_swap.aarch64.asm b/tests/snapshots/asm/param_reg_swap.aarch64.asm index c5cd220f0..ff47f3b0e 100644 --- a/tests/snapshots/asm/param_reg_swap.aarch64.asm +++ b/tests/snapshots/asm/param_reg_swap.aarch64.asm @@ -33,108 +33,105 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x50 mov x5, #0x0 // =0 - sxtw x4, w5 - cmp x4, #0x4 - b.ge b - sxtw x4, w5 - add x5, x4, #0x1 - b - sub x4, x29, #0x40 + sub x6, x29, #0x40 mov x17, #0x5 // =5 - mul x6, x5, x17 - sxtw x6, w6 - lsl x7, x5, #2 + mul x7, x5, x17 sxtw x7, w7 - add x7, x3, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0x1 - sxtw x6, w6 - lsl x7, x5, #2 + lsl x8, x5, #2 + sxtw x8, w8 + add x8, x3, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0x1 sxtw x7, w7 - add x7, x2, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0x6 - sxtw x6, w6 - lsl x7, x5, #2 + lsl x8, x5, #2 + sxtw x8, w8 + add x8, x2, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0x6 sxtw x7, w7 - add x7, x1, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0xb - sxtw x6, w6 - add x7, x2, #0x10 lsl x8, x5, #2 sxtw x8, w8 - add x7, x7, x8 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - b + add x8, x1, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0xb + sxtw x7, w7 + add x8, x2, #0x10 + lsl x9, x5, #2 + sxtw x9, w9 + add x8, x8, x9 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + add x5, x4, #0x1 + sxtw x4, w5 + cmp x4, #0x4 + b.lt mov x1, #0x0 // =0 sub x2, x29, #0x40 ldr w2, [x2] @@ -159,36 +156,66 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x60 + sub x0, x29, #0x18 + add x0, x0, #0x0 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x10 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b + strb w1, [x0] sub x0, x29, #0x18 - sxtw x2, w1 - add x0, x0, x2 - mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - b + mov x1, #0x1 // =1 + strb w1, [x0, #0x1] + sub x0, x29, #0x18 + mov x1, #0x2 // =2 + strb w1, [x0, #0x2] + sub x0, x29, #0x18 + mov x1, #0x3 // =3 + strb w1, [x0, #0x3] + sub x0, x29, #0x18 + mov x1, #0x4 // =4 + strb w1, [x0, #0x4] + sub x0, x29, #0x18 + mov x1, #0x5 // =5 + strb w1, [x0, #0x5] + sub x0, x29, #0x18 + mov x1, #0x6 // =6 + strb w1, [x0, #0x6] + sub x0, x29, #0x18 + mov x1, #0x7 // =7 + strb w1, [x0, #0x7] + sub x0, x29, #0x18 + mov x1, #0x8 // =8 + strb w1, [x0, #0x8] + sub x0, x29, #0x18 + mov x1, #0x9 // =9 + strb w1, [x0, #0x9] + sub x0, x29, #0x18 + mov x1, #0xa // =10 + strb w1, [x0, #0xa] + sub x0, x29, #0x18 + mov x1, #0xb // =11 + strb w1, [x0, #0xb] + sub x0, x29, #0x18 + mov x1, #0xc // =12 + strb w1, [x0, #0xc] + sub x0, x29, #0x18 + mov x1, #0xd // =13 + strb w1, [x0, #0xd] + sub x0, x29, #0x18 + mov x1, #0xe // =14 + strb w1, [x0, #0xe] + sub x0, x29, #0x18 + mov x1, #0xf // =15 + strb w1, [x0, #0xf] mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x20 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x38 - sxtw x2, w1 - add x0, x0, x2 + sub x2, x29, #0x38 + add x2, x2, x0 mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - b + and x3, x0, x17 + strb w3, [x2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x20 + b.lt sub x0, x29, #0x8 sub x1, x29, #0x18 sub x2, x29, #0x38 diff --git a/tests/snapshots/asm/param_reg_swap.x64.asm b/tests/snapshots/asm/param_reg_swap.x64.asm index 17e5dae66..c7503626e 100644 --- a/tests/snapshots/asm/param_reg_swap.x64.asm +++ b/tests/snapshots/asm/param_reg_swap.x64.asm @@ -36,112 +36,110 @@ Disassembly of section .text: movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) xorq %r8, %r8 - movslq %r8d, %rax - cmpq $0x4, %rax - jge jmp - movslq %r8d, %rax - leaq 0x1(%rax), %r8 - jmp - leaq -0x40(%rbp), %rax - leaq (%r8,%r8,4), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + leaq -0x40(%rbp), %r9 + leaq (%r8,%r8,4), %rbx movslq %ebx, %rbx - addq %rcx, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movq %r8, %r12 + shlq $0x2, %r12 + movslq %r12d, %r12 + addq %rcx, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0x1(%r8), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0x1(%r8), %rbx movslq %ebx, %rbx - addq %rdx, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movq %r8, %r12 + shlq $0x2, %r12 + movslq %r12d, %r12 + addq %rdx, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0x6(%r8), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0x6(%r8), %rbx movslq %ebx, %rbx - addq %rsi, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0xb(%r8), %r9 - movslq %r9d, %r9 - leaq 0x10(%rdx), %rbx movq %r8, %r12 shlq $0x2, %r12 movslq %r12d, %r12 - addq %r12, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 + addq %rsi, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0xb(%r8), %rbx + movslq %ebx, %rbx + leaq 0x10(%rdx), %r12 + movq %r8, %r13 + shlq $0x2, %r13 + movslq %r13d, %r13 + addq %r13, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - jmp + movl %r12d, (%r9,%rbx,4) + leaq 0x1(%rax), %r8 + movslq %r8d, %rax + cmpq $0x4, %rax + jl xorq %rax, %rax leaq -0x40(%rbp), %rcx movl (%rcx), %ecx @@ -159,6 +157,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 addq $0x70, %rsp popq %rbp retq @@ -167,34 +166,66 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x60, %rsp + leaq -0x18(%rbp), %rax + addq $0x0, %rax xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x10, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp + movb %cl, (%rax) leaq -0x18(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - andq $0xff, %rdx - movb %dl, (%rax) - jmp + movl $0x1, %ecx + movb %cl, 0x1(%rax) + leaq -0x18(%rbp), %rax + movl $0x2, %ecx + movb %cl, 0x2(%rax) + leaq -0x18(%rbp), %rax + movl $0x3, %ecx + movb %cl, 0x3(%rax) + leaq -0x18(%rbp), %rax + movl $0x4, %ecx + movb %cl, 0x4(%rax) + leaq -0x18(%rbp), %rax + movl $0x5, %ecx + movb %cl, 0x5(%rax) + leaq -0x18(%rbp), %rax + movl $0x6, %ecx + movb %cl, 0x6(%rax) + leaq -0x18(%rbp), %rax + movl $0x7, %ecx + movb %cl, 0x7(%rax) + leaq -0x18(%rbp), %rax + movl $0x8, %ecx + movb %cl, 0x8(%rax) + leaq -0x18(%rbp), %rax + movl $0x9, %ecx + movb %cl, 0x9(%rax) + leaq -0x18(%rbp), %rax + movl $0xa, %ecx + movb %cl, 0xa(%rax) + leaq -0x18(%rbp), %rax + movl $0xb, %ecx + movb %cl, 0xb(%rax) + leaq -0x18(%rbp), %rax + movl $0xc, %ecx + movb %cl, 0xc(%rax) + leaq -0x18(%rbp), %rax + movl $0xd, %ecx + movb %cl, 0xd(%rax) + leaq -0x18(%rbp), %rax + movl $0xe, %ecx + movb %cl, 0xe(%rax) + leaq -0x18(%rbp), %rax + movl $0xf, %ecx + movb %cl, 0xf(%rax) xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x20, %rax - jge jmp - movslq %ecx, %rax + leaq -0x38(%rbp), %rdx + addq %rax, %rdx + movq %rax, %rsi + andq $0xff, %rsi + movb %sil, (%rdx) leaq 0x1(%rax), %rcx - jmp - leaq -0x38(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - andq $0xff, %rdx - movb %dl, (%rax) - jmp + movslq %ecx, %rax + cmpq $0x20, %rax + jl leaq -0x8(%rbp), %rdi leaq -0x18(%rbp), %rsi leaq -0x38(%rbp), %rdx diff --git a/tests/snapshots/asm/paren_comma_side_effect.aarch64.asm b/tests/snapshots/asm/paren_comma_side_effect.aarch64.asm index 3a29370c5..8db863dd6 100644 --- a/tests/snapshots/asm/paren_comma_side_effect.aarch64.asm +++ b/tests/snapshots/asm/paren_comma_side_effect.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,11 +48,9 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret : @@ -67,12 +61,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x0, #0x0 // =0 @@ -90,11 +82,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x1 // =1 str w0, [x20] @@ -114,16 +104,12 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x21 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/paren_string_char_array_init.aarch64.asm b/tests/snapshots/asm/paren_string_char_array_init.aarch64.asm index aa38c354f..aabdc2431 100644 --- a/tests/snapshots/asm/paren_string_char_array_init.aarch64.asm +++ b/tests/snapshots/asm/paren_string_char_array_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldrb w1, [x0, #0x8] @@ -40,40 +37,32 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret ldrb w1, [x0, #0x10] cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x2, #0x0 // =0 - adrp x1, - add x1, x1, - sxtw x3, w2 - add x1, x1, x3 - ldrsb x1, [x1] - cbz x1, - b - sxtw x1, w2 - add x2, x1, #0x1 b add x1, x0, #0x8 - sxtw x3, w2 add x1, x1, x3 ldrb w1, [x1] adrp x4, add x4, x4, - add x3, x4, x3 - ldrsb x3, [x3] + add x4, x4, x3 + ldrsb x4, [x4] mov x17, #0xff // =255 - and x3, x3, x17 - cmp x1, x3 - b.eq - b + and x4, x4, x17 + cmp x1, x4 + b.ne + add x2, x3, #0x1 + adrp x1, + add x1, x1, + sxtw x3, w2 + add x1, x1, x3 + ldrsb x1, [x1] + cbnz x1, adrp x0, add x0, x0, ldrb w0, [x0] @@ -84,12 +73,6 @@ Disassembly of section .text: cset x0, ne mov x2, #0x1 // =1 cbnz x0, - b - mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b adrp x0, add x0, x0, ldrb w0, [x0, #0x4] @@ -108,8 +91,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -130,8 +111,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -152,16 +131,15 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b b b + mov x0, #0x3 // =3 + ret + b b b diff --git a/tests/snapshots/asm/paren_string_char_array_init.x64.asm b/tests/snapshots/asm/paren_string_char_array_init.x64.asm index 2c28f5e6a..1d29c9435 100644 --- a/tests/snapshots/asm/paren_string_char_array_init.x64.asm +++ b/tests/snapshots/asm/paren_string_char_array_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movzbq 0x8(%rax), %rcx xorq $0x6e, %rcx @@ -44,38 +41,30 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq movzbq 0x10(%rax), %rcx testq %rcx, %rcx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rdx, %rdx - leaq , %rcx - movslq %edx, %rsi - addq %rsi, %rcx - movsbq (%rcx), %rcx - testq %rcx, %rcx - je - jmp - movslq %edx, %rcx - leaq 0x1(%rcx), %rdx jmp leaq 0x8(%rax), %rcx - movslq %edx, %rsi addq %rsi, %rcx movzbq (%rcx), %rcx leaq , %rdi - addq %rdi, %rsi - movsbq (%rsi), %rsi - andq $0xff, %rsi - cmpq %rsi, %rcx - je - jmp + addq %rsi, %rdi + movsbq (%rdi), %rdi + andq $0xff, %rdi + cmpq %rdi, %rcx + jne + leaq 0x1(%rsi), %rdx + leaq , %rcx + movslq %edx, %rsi + addq %rsi, %rcx + movsbq (%rcx), %rcx + testq %rcx, %rcx + jne leaq , %rax movsbq (%rax), %rax cmpq $0x68, %rax @@ -84,12 +73,6 @@ Disassembly of section .text: movl $0x1, %edx testq %rax, %rax jne - jmp - movl $0x3, %eax - addq $0x40, %rsp - popq %rbp - retq - jmp leaq , %rax movsbq 0x4(%rax), %rax cmpq $0x6f, %rax @@ -108,8 +91,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rax @@ -126,8 +107,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rax @@ -144,16 +123,17 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp jmp jmp + movl $0x3, %eax + retq + jmp jmp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/parenthesized_function_declarator.aarch64.asm b/tests/snapshots/asm/parenthesized_function_declarator.aarch64.asm index eb0379aa2..9c12e62ff 100644 --- a/tests/snapshots/asm/parenthesized_function_declarator.aarch64.asm +++ b/tests/snapshots/asm/parenthesized_function_declarator.aarch64.asm @@ -25,21 +25,8 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - mov x0, #0xa // =10 - add x0, x0, #0x1 - sxtw x20, w0 mov x0, #0x5 // =5 bl - sxtw x1, w20 - cmp x1, #0xb - b.eq - mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret cmp x0, #0x0 cset x2, eq cbnz x2, @@ -48,13 +35,12 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret b + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/parenthesized_function_declarator.x64.asm b/tests/snapshots/asm/parenthesized_function_declarator.x64.asm index a9d4a496d..7b32611e7 100644 --- a/tests/snapshots/asm/parenthesized_function_declarator.x64.asm +++ b/tests/snapshots/asm/parenthesized_function_declarator.x64.asm @@ -25,21 +25,8 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) - movl $0xa, %eax - incq %rax - movslq %eax, %rbx movl $0x5, %edi callq - movslq %ebx, %rcx - cmpq $0xb, %rcx - je - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp - popq %rbp - retq testq %rax, %rax sete %dl movzbq %dl, %rdx @@ -52,14 +39,13 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq jmp - addb %al, (%rax) + movl $0x1, %eax + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/phi_class_diamond_join.aarch64.asm b/tests/snapshots/asm/phi_class_diamond_join.aarch64.asm index 9808446cd..d80ead765 100644 --- a/tests/snapshots/asm/phi_class_diamond_join.aarch64.asm +++ b/tests/snapshots/asm/phi_class_diamond_join.aarch64.asm @@ -21,11 +21,9 @@ Disassembly of section .text: b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x1 // =1 mov x1, #0xa // =10 mov x20, #0x0 // =0 @@ -38,8 +36,6 @@ Disassembly of section .text: bl add x0, x21, x0 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret diff --git a/tests/snapshots/asm/phi_class_for_loop_sum.aarch64.asm b/tests/snapshots/asm/phi_class_for_loop_sum.aarch64.asm index cb20706a6..5c740efe6 100644 --- a/tests/snapshots/asm/phi_class_for_loop_sum.aarch64.asm +++ b/tests/snapshots/asm/phi_class_for_loop_sum.aarch64.asm @@ -13,16 +13,13 @@ Disassembly of section .text: sxtw x0, w0 mov x2, #0x0 // =0 mov x1, x2 - sxtw x3, w1 - cmp x3, x0 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 b add x2, x2, x1 sxtw x2, w2 - b + add x1, x3, #0x1 + sxtw x3, w1 + cmp x3, x0 + b.lt sxtw x0, w2 ret diff --git a/tests/snapshots/asm/phi_class_for_loop_sum.x64.asm b/tests/snapshots/asm/phi_class_for_loop_sum.x64.asm index c9dffea82..e74fdbcca 100644 --- a/tests/snapshots/asm/phi_class_for_loop_sum.x64.asm +++ b/tests/snapshots/asm/phi_class_for_loop_sum.x64.asm @@ -14,16 +14,13 @@ Disassembly of section .text: movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %eax, %rdx - cmpq %rdi, %rdx - jge - jmp - movslq %eax, %rax - incq %rax jmp addq %rax, %rcx movslq %ecx, %rcx - jmp + leaq 0x1(%rdx), %rax + movslq %eax, %rdx + cmpq %rdi, %rdx + jl movslq %ecx, %rax retq @@ -33,4 +30,3 @@ Disassembly of section .text: movl $0xa, %edi popq %rbp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/phi_class_nested_loops.aarch64.asm b/tests/snapshots/asm/phi_class_nested_loops.aarch64.asm index b21ea0a3f..c4b794e18 100644 --- a/tests/snapshots/asm/phi_class_nested_loops.aarch64.asm +++ b/tests/snapshots/asm/phi_class_nested_loops.aarch64.asm @@ -13,31 +13,24 @@ Disassembly of section .text: sxtw x0, w0 mov x2, #0x0 // =0 mov x1, x2 - sxtw x3, w1 - cmp x3, x0 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 b - mov x4, #0x0 // =0 - mov x3, x4 + mov x5, #0x0 // =0 + mov x4, x5 b + add x5, x5, #0x1 + sxtw x5, w5 + add x4, x6, #0x1 + sxtw x6, w4 + cmp x6, x0 + b.lt + add x2, x2, x5 + sxtw x2, w2 + add x1, x3, #0x1 + sxtw x3, w1 + cmp x3, x0 + b.lt sxtw x0, w2 ret - sxtw x5, w3 - cmp x5, x0 - b.ge - b - sxtw x3, w3 - add x3, x3, #0x1 - b - add x4, x4, #0x1 - sxtw x4, w4 - b - add x2, x2, x4 - sxtw x2, w2 - b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/phi_class_nested_loops.x64.asm b/tests/snapshots/asm/phi_class_nested_loops.x64.asm index bf70d374a..4f32693ba 100644 --- a/tests/snapshots/asm/phi_class_nested_loops.x64.asm +++ b/tests/snapshots/asm/phi_class_nested_loops.x64.asm @@ -11,34 +11,34 @@ Disassembly of section .text: ud2 : + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %eax, %rdx - cmpq %rdi, %rdx - jge jmp - movslq %eax, %rax - incq %rax - jmp - xorq %rsi, %rsi - movq %rsi, %rdx + xorq %r8, %r8 + movq %r8, %rsi jmp + incq %r8 + movslq %r8d, %r8 + leaq 0x1(%r9), %rsi + movslq %esi, %r9 + cmpq %rdi, %r9 + jl + addq %r8, %rcx + movslq %ecx, %rcx + leaq 0x1(%rdx), %rax + movslq %eax, %rdx + cmpq %rdi, %rdx + jl movslq %ecx, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp retq - movslq %edx, %r8 - cmpq %rdi, %r8 - jge - jmp - movslq %edx, %rdx - incq %rdx - jmp - incq %rsi - movslq %esi, %rsi - jmp - addq %rsi, %rcx - movslq %ecx, %rcx - jmp
: pushq %rbp @@ -46,3 +46,5 @@ Disassembly of section .text: movl $0x7, %edi popq %rbp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/plain_char_signedness.aarch64.asm b/tests/snapshots/asm/plain_char_signedness.aarch64.asm index 101112b6a..ef7410a3b 100644 --- a/tests/snapshots/asm/plain_char_signedness.aarch64.asm +++ b/tests/snapshots/asm/plain_char_signedness.aarch64.asm @@ -13,18 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x40 - mov x0, #0xffe3 // =65507 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xff // =255 - and x0, x0, x17 - cmp x0, #0xe3 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 mov x1, #0xffe3 // =65507 movk x1, #0xffff, lsl #16 @@ -63,28 +51,19 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffe3 // =65507 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0xffe3 // =65507 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x5 // =5 + mov x0, #0x0 // =0 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xe3 // =227 - cmp x0, #0xe3 - b.eq - mov x0, #0x6 // =6 + mov x0, #0x1 // =1 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x5 // =5 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/plain_char_signedness.x64.asm b/tests/snapshots/asm/plain_char_signedness.x64.asm index 845d5e0ec..863a12133 100644 --- a/tests/snapshots/asm/plain_char_signedness.x64.asm +++ b/tests/snapshots/asm/plain_char_signedness.x64.asm @@ -14,13 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x40, %rsp - movabsq $-0x1d, %rax - cmpq $-0x1d, %rax - je - movl $0x1, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax movabsq $-0x1d, %rcx movb %cl, (%rax) @@ -53,21 +46,19 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $-0x1d, %rax - cmpq $-0x1d, %rax - je - movl $0x5, %eax + xorq %rax, %rax addq $0x40, %rsp popq %rbp retq - movl $0xe3, %eax - cmpq $0xe3, %rax - je - movl $0x6, %eax + movl $0x1, %eax addq $0x40, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x5, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x6, %eax addq $0x40, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/pointer_arithmetic.aarch64.asm b/tests/snapshots/asm/pointer_arithmetic.aarch64.asm index 4d3b2f98d..677c4367e 100644 --- a/tests/snapshots/asm/pointer_arithmetic.aarch64.asm +++ b/tests/snapshots/asm/pointer_arithmetic.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x8 // =8 bl mov x1, #0x1 // =1 @@ -24,7 +23,6 @@ Disassembly of section .text: sxtw x0, w2 add x0, x1, x0 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/pointer_arithmetic.x64.asm b/tests/snapshots/asm/pointer_arithmetic.x64.asm index 65b567213..73a4251ae 100644 --- a/tests/snapshots/asm/pointer_arithmetic.x64.asm +++ b/tests/snapshots/asm/pointer_arithmetic.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x8, %edi xorl %eax, %eax callq @@ -25,7 +24,7 @@ Disassembly of section .text: movslq %edx, %rax addq %rcx, %rax movslq %eax, %rax - addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/pointer_arithmetic_scaling.aarch64.asm b/tests/snapshots/asm/pointer_arithmetic_scaling.aarch64.asm index d36be1b48..d816734ab 100644 --- a/tests/snapshots/asm/pointer_arithmetic_scaling.aarch64.asm +++ b/tests/snapshots/asm/pointer_arithmetic_scaling.aarch64.asm @@ -10,11 +10,5 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x64 // =100 - add x0, x0, #0x4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + mov x0, #0x68 // =104 ret diff --git a/tests/snapshots/asm/pointer_arithmetic_scaling.x64.asm b/tests/snapshots/asm/pointer_arithmetic_scaling.x64.asm index bf18ec34e..1cc093348 100644 --- a/tests/snapshots/asm/pointer_arithmetic_scaling.x64.asm +++ b/tests/snapshots/asm/pointer_arithmetic_scaling.x64.asm @@ -11,11 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x64, %eax - addq $0x4, %rax - addq $0x10, %rsp - popq %rbp + movl $0x68, %eax retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/pointer_to_array_arithmetic.aarch64.asm b/tests/snapshots/asm/pointer_to_array_arithmetic.aarch64.asm index 4bbb6f2e2..a8883cf56 100644 --- a/tests/snapshots/asm/pointer_to_array_arithmetic.aarch64.asm +++ b/tests/snapshots/asm/pointer_to_array_arithmetic.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, add x1, x0, #0x10 @@ -20,24 +17,18 @@ Disassembly of section .text: cmp x1, #0x10 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret add x1, x0, #0x8 sub x2, x1, x0 cmp x2, #0x8 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret add x2, x0, #0x10 sub x3, x2, x0 cmp x3, #0x10 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret ldrsw x3, [x2] cmp x3, #0x4 @@ -48,8 +39,6 @@ Disassembly of section .text: cset x4, ne cbz x4, mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret sub x1, x1, x0 asr x2, x1, #63 @@ -59,8 +48,6 @@ Disassembly of section .text: cmp x1, #0x1 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret add x1, x0, #0x8 ldrsw x2, [x0, #0x4] @@ -72,8 +59,6 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret add x1, x0, #0x20 sub x1, x1, #0x8 @@ -81,12 +66,8 @@ Disassembly of section .text: cmp x0, #0x18 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/pointer_to_array_arithmetic.x64.asm b/tests/snapshots/asm/pointer_to_array_arithmetic.x64.asm index 6961f8e8e..817a60af2 100644 --- a/tests/snapshots/asm/pointer_to_array_arithmetic.x64.asm +++ b/tests/snapshots/asm/pointer_to_array_arithmetic.x64.asm @@ -11,17 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax leaq 0x10(%rax), %rcx subq %rax, %rcx cmpq $0x10, %rcx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq 0x8(%rax), %rcx movq %rcx, %rdx @@ -29,8 +24,6 @@ Disassembly of section .text: cmpq $0x8, %rdx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq 0x10(%rax), %rdx movq %rdx, %rsi @@ -38,8 +31,6 @@ Disassembly of section .text: cmpq $0x10, %rsi je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq movslq (%rdx), %rsi cmpq $0x4, %rsi @@ -54,8 +45,6 @@ Disassembly of section .text: testq %rdi, %rdi je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq subq %rax, %rcx movq %rcx, %rdx @@ -66,8 +55,6 @@ Disassembly of section .text: cmpq $0x1, %rcx je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq leaq 0x8(%rax), %rcx movslq 0x4(%rax), %rdx @@ -83,8 +70,6 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq leaq 0x20(%rax), %rcx addq $-0x8, %rcx @@ -94,13 +79,8 @@ Disassembly of section .text: cmpq $0x18, %rax je movl $0x7, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/pointer_to_array_cast.aarch64.asm b/tests/snapshots/asm/pointer_to_array_cast.aarch64.asm index 3a7c9e142..a860a4816 100644 --- a/tests/snapshots/asm/pointer_to_array_cast.aarch64.asm +++ b/tests/snapshots/asm/pointer_to_array_cast.aarch64.asm @@ -14,20 +14,16 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x50 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x18 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x30 - sxtw x2, w1 + sub x2, x29, #0x30 mov x17, #0x3 // =3 - mul x3, x2, x17 + mul x3, x0, x17 sxtw x4, w3 - strh w4, [x0, x2, lsl #1] - b + strh w4, [x2, x0, lsl #1] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x18 + b.lt sub x0, x29, #0x30 sub x1, x29, #0x30 cmp x0, x1 diff --git a/tests/snapshots/asm/pointer_to_array_cast.x64.asm b/tests/snapshots/asm/pointer_to_array_cast.x64.asm index 863b7def6..612157180 100644 --- a/tests/snapshots/asm/pointer_to_array_cast.x64.asm +++ b/tests/snapshots/asm/pointer_to_array_cast.x64.asm @@ -15,19 +15,15 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x50, %rsp xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x18, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0x30(%rbp), %rax - movslq %ecx, %rdx - leaq (%rdx,%rdx,2), %rsi + leaq -0x30(%rbp), %rdx + leaq (%rax,%rax,2), %rsi movslq %esi, %rdi - movw %di, (%rax,%rdx,2) - jmp + movw %di, (%rdx,%rax,2) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x18, %rax + jl leaq -0x30(%rbp), %rax leaq -0x30(%rbp), %rcx cmpq %rcx, %rax @@ -63,4 +59,3 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/pointer_to_array_struct_field.aarch64.asm b/tests/snapshots/asm/pointer_to_array_struct_field.aarch64.asm index c026458b9..644591879 100644 --- a/tests/snapshots/asm/pointer_to_array_struct_field.aarch64.asm +++ b/tests/snapshots/asm/pointer_to_array_struct_field.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x50]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x20, x29, #0x8 mov x0, #0x40 // =64 bl @@ -24,52 +23,113 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x50 ret mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x4 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + add x2, x2, #0x0 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x0 + sxtw x4, w3 + strh w4, [x2] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x1 + sxtw x4, w3 + strh w4, [x2, #0x2] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x2 + sxtw x4, w3 + strh w4, [x2, #0x4] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x3 + sxtw x4, w3 + strh w4, [x2, #0x6] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x4 + sxtw x4, w3 + strh w4, [x2, #0x8] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x5 + sxtw x4, w3 + strh w4, [x2, #0xa] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x6 + sxtw x4, w3 + strh w4, [x2, #0xc] + sub x2, x29, #0x8 + ldr x2, [x2] + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x7 + sxtw x4, w3 + strh w4, [x2, #0xe] add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + sxtw x0, w1 + cmp x0, #0x4 + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x8 - b.ge + mov x3, #0x0 // =0 b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x8 - ldr x0, [x0] - sxtw x3, w1 - lsl x4, x3, #4 - add x0, x0, x4 - sxtw x4, w2 + sub x4, x29, #0x8 + ldr x4, [x4] + lsl x5, x0, #4 + add x4, x4, x5 + ldrsh x4, [x4, x2, lsl #1] mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - sxtw x5, w3 - strh w5, [x0, x4, lsl #1] - b - b + mul x5, x0, x17 + add x5, x5, x2 + sxtw x6, w5 + sxth x5, w6 + cmp x4, x5 + b.ne + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x8 + b.lt + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x4 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt sub x0, x29, #0x8 ldr x0, [x0] mov x1, #0xffff // =65535 @@ -86,45 +146,10 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 cmp x0, x17 b.eq - b - sxtw x0, w2 - cmp x0, #0x8 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x8 - ldr x0, [x0] - sxtw x3, w1 - lsl x4, x3, #4 - add x0, x0, x4 - sxtw x4, w2 - ldrsh x0, [x0, x4, lsl #1] - mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - sxtw x4, w3 - sxth x3, w4 - cmp x0, x3 - b.eq - b - b - lsl x0, x1, #3 - add x0, x0, #0xa - add x0, x0, x2 - sxtw x0, w0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - b mov x0, #0x63 // =99 - ldr x20, [sp] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x50 ret sub x0, x29, #0x8 ldr x0, [x0] @@ -135,8 +160,18 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x40] + ldr x19, [sp, #0x10] + ldr x20, [sp], #0x50 + ret + lsl x0, x1, #3 + add x0, x0, #0xa + add x0, x0, x3 + sxtw x0, w0 + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x50 ret + b + b + b diff --git a/tests/snapshots/asm/pointer_to_array_struct_field.x64.asm b/tests/snapshots/asm/pointer_to_array_struct_field.x64.asm index 5a4574dd8..5548b5615 100644 --- a/tests/snapshots/asm/pointer_to_array_struct_field.x64.asm +++ b/tests/snapshots/asm/pointer_to_array_struct_field.x64.asm @@ -30,46 +30,108 @@ Disassembly of section .text: popq %rbp retq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x4, %rax - jge jmp - movslq %ecx, %rax + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + addq $0x0, %rdx + imulq $0x64, %rax, %rsi + addq $0x0, %rsi + movslq %esi, %rdi + movw %di, (%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + incq %rsi + movslq %esi, %rdi + movw %di, 0x2(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x2, %rsi + movslq %esi, %rdi + movw %di, 0x4(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x3, %rsi + movslq %esi, %rdi + movw %di, 0x6(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x4, %rsi + movslq %esi, %rdi + movw %di, 0x8(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x5, %rsi + movslq %esi, %rdi + movw %di, 0xa(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x6, %rsi + movslq %esi, %rdi + movw %di, 0xc(%rdx) + leaq -0x8(%rbp), %rdx + movq (%rdx), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x7, %rsi + movslq %esi, %rdi + movw %di, 0xe(%rdx) leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp - xorq %rcx, %rcx - jmp - movslq %edx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x8(%rbp), %rax - movq (%rax), %rax - movslq %ecx, %rsi - movq %rsi, %rdi - shlq $0x4, %rdi - addq %rdi, %rax - movslq %edx, %rdi - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movslq %esi, %r8 - movw %r8w, (%rax,%rdi,2) - jmp - jmp movslq %ecx, %rax cmpq $0x4, %rax - jge + jl + xorq %rcx, %rcx jmp - movslq %ecx, %rax + xorq %rsi, %rsi + jmp + leaq -0x8(%rbp), %rdi + movq (%rdi), %rdi + movq %rax, %r8 + shlq $0x4, %r8 + addq %r8, %rdi + movswq (%rdi,%rdx,2), %rdi + imulq $0x64, %rax, %r8 + addq %rdx, %r8 + movslq %r8d, %r9 + movswq %r9w, %r8 + cmpq %r8, %rdi + jne + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x8, %rdx + jl leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + movslq %ecx, %rax + cmpq $0x4, %rax + jl leaq -0x8(%rbp), %rax movq (%rax), %rax movabsq $-0x1, %rcx @@ -79,40 +141,6 @@ Disassembly of section .text: movswq (%rax), %rax cmpq $-0x1, %rax je - jmp - movslq %edx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x8(%rbp), %rax - movq (%rax), %rax - movslq %ecx, %rsi - movq %rsi, %rdi - shlq $0x4, %rdi - addq %rdi, %rax - movslq %edx, %rdi - movswq (%rax,%rdi,2), %rax - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movslq %esi, %rdi - movswq %di, %rsi - cmpq %rsi, %rax - je - jmp - jmp - movq %rcx, %rax - shlq $0x3, %rax - addq $0xa, %rax - addq %rdx, %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0x30, %rsp - popq %rbp - retq - jmp movl $0x63, %eax movq (%rsp), %rbx addq $0x30, %rsp @@ -132,5 +160,15 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) + movq %rcx, %rax + shlq $0x3, %rax + addq $0xa, %rax + addq %rsi, %rax + movslq %eax, %rax + movq (%rsp), %rbx + addq $0x30, %rsp + popq %rbp + retq + jmp + jmp + jmp diff --git a/tests/snapshots/asm/posix_module_headers.aarch64.asm b/tests/snapshots/asm/posix_module_headers.aarch64.asm index a02236fa7..a6a1bc016 100644 --- a/tests/snapshots/asm/posix_module_headers.aarch64.asm +++ b/tests/snapshots/asm/posix_module_headers.aarch64.asm @@ -14,7 +14,6 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x400 str x20, [sp] - str x21, [sp, #0x8] str x19, [sp, #0x10] mov x0, #0x41 // =65 bl @@ -24,9 +23,8 @@ Disassembly of section .text: cmp x0, #0x41 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -34,18 +32,17 @@ Disassembly of section .text: bl sxtw x0, w0 cmp x0, #0x0 - cset x21, eq - cbnz x21, + cset x1, eq + cbnz x1, sxtw x0, w20 bl sxtw x0, w0 cmp x0, #0x0 - cset x21, eq - cbz x21, + cset x1, eq + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -55,9 +52,8 @@ Disassembly of section .text: cmp x0, #0x61 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -67,9 +63,8 @@ Disassembly of section .text: cmp x0, #0x41 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -84,9 +79,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -105,9 +99,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -118,9 +111,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -136,29 +128,19 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x8 // =8 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3 // =3 - mov x20, #0x1 // =1 - cmp x0, #0x0 - cset x1, lt - cbnz x1, - cmp x0, #0x0 - cset x0, lt - cmp x0, #0x0 - cset x21, ne - cbnz x21, - cmp x20, #0x1 - cset x21, ne - cbz x21, + mov x2, #0x1 // =1 + mov x2, #0x0 // =0 + cbnz x2, + mov x2, #0x0 // =0 + cbz x2, mov x0, #0x9 // =9 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -169,9 +151,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0xa // =10 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -180,33 +161,13 @@ Disassembly of section .text: str x1, [x0, #0x10] sub x0, x29, #0xd0 str x1, [x0] - b - mov x0, #0xb // =11 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x400 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x29c // =668 - mov x1, #0x3 // =3 - mov x2, #0xc // =12 - cmp x0, #0x0 - cset x0, eq - mov x4, #0x0 // =0 - cbz x0, - cmp x1, #0x0 - cset x0, eq - cmp x0, #0x0 - cset x4, ne - cbz x4, - cmp x2, #0x0 - cset x4, eq - cbz x4, + mov x2, #0x0 // =0 + cbz x2, + mov x2, #0x0 // =0 + cbz x2, mov x0, #0xc // =12 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -214,9 +175,8 @@ Disassembly of section .text: mov x1, #0x0 // =0 cbz x1, mov x0, #0xd // =13 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret @@ -247,25 +207,28 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0xe // =14 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x400 ldp x29, x30, [sp], #0x10 ret b - mov x21, x20 - b b b b b b + mov x0, #0xb // =11 + ldr x19, [sp, #0x10] + ldr x20, [sp] + add sp, sp, #0x400 + ldp x29, x30, [sp], #0x10 + ret + mov x2, #0x0 // =0 b diff --git a/tests/snapshots/asm/posix_module_headers.x64.asm b/tests/snapshots/asm/posix_module_headers.x64.asm index 3d0670946..eededb030 100644 --- a/tests/snapshots/asm/posix_module_headers.x64.asm +++ b/tests/snapshots/asm/posix_module_headers.x64.asm @@ -15,7 +15,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x3f0, %rsp # imm = 0x3F0 movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) movl $0x41, %edi xorl %eax, %eax callq @@ -26,7 +25,6 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -35,22 +33,21 @@ Disassembly of section .text: callq movslq %eax, %rax testq %rax, %rax - sete %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne movslq %ebx, %rdi xorl %eax, %eax callq movslq %eax, %rax testq %rax, %rax - sete %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -62,7 +59,6 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -74,7 +70,6 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -91,7 +86,6 @@ Disassembly of section .text: jne movl $0x5, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -114,7 +108,6 @@ Disassembly of section .text: je movl $0x6, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -127,7 +120,6 @@ Disassembly of section .text: je movl $0x7, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -146,33 +138,18 @@ Disassembly of section .text: je movl $0x8, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq - movl $0x3, %eax - movl $0x1, %ebx - testq %rax, %rax - setl %cl - movzbq %cl, %rcx - testq %rcx, %rcx - jne - testq %rax, %rax - setl %al - movzbq %al, %rax - testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + movl $0x1, %edx + xorq %rdx, %rdx + testq %rdx, %rdx jne - cmpq $0x1, %rbx - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + xorq %rdx, %rdx + testq %rdx, %rdx je movl $0x9, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -185,7 +162,6 @@ Disassembly of section .text: je movl $0xa, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -194,38 +170,14 @@ Disassembly of section .text: movq %rcx, 0x10(%rax) leaq -0xd0(%rbp), %rax movq %rcx, (%rax) - jmp - movl $0xb, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x3f0, %rsp # imm = 0x3F0 - popq %rbp - retq - movl $0x29c, %eax # imm = 0x29C - movl $0x3, %ecx - movl $0xc, %edx - testq %rax, %rax - sete %al - movzbq %al, %rax - xorq %rdi, %rdi - testq %rax, %rax - je - testq %rcx, %rcx - sete %al - movzbq %al, %rax - testq %rax, %rax - setne %dil - movzbq %dil, %rdi - testq %rdi, %rdi + xorq %rdx, %rdx + testq %rdx, %rdx je + xorq %rdx, %rdx testq %rdx, %rdx - sete %dil - movzbq %dil, %rdi - testq %rdi, %rdi je movl $0xc, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -235,7 +187,6 @@ Disassembly of section .text: je movl $0xd, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq @@ -277,23 +228,24 @@ Disassembly of section .text: je movl $0xe, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x3f0, %rsp # imm = 0x3F0 popq %rbp retq jmp - movq %rbx, %r12 - jmp jmp jmp jmp jmp jmp + movl $0xb, %eax + movq (%rsp), %rbx + addq $0x3f0, %rsp # imm = 0x3F0 + popq %rbp + retq + xorq %rdx, %rdx jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/posix_os_headers.aarch64.asm b/tests/snapshots/asm/posix_os_headers.aarch64.asm index 6c9b6dbbb..8a940c0ef 100644 --- a/tests/snapshots/asm/posix_os_headers.aarch64.asm +++ b/tests/snapshots/asm/posix_os_headers.aarch64.asm @@ -10,21 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] + str x20, [sp, #-0xc0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 sub x0, x29, #0x10 mov x1, #0x0 // =0 bl sxtw x0, w0 cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x10 ldr x0, [x0] @@ -33,20 +31,18 @@ Disassembly of section .text: cmp x0, x17 b.ge mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x18 bl sxtw x0, w0 cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x18 ldrsw x0, [x0, #0x4] @@ -58,10 +54,9 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x20 sub x1, x29, #0x18 @@ -81,10 +76,9 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x20 ldrsh x0, [x0, #0x6] @@ -93,10 +87,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret sub x0, x29, #0x18 mov x20, #0x0 // =0 @@ -117,8 +110,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x10] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xc0 ret diff --git a/tests/snapshots/asm/posix_unix_headers.aarch64.asm b/tests/snapshots/asm/posix_unix_headers.aarch64.asm index 46d3ddaee..75f61ae16 100644 --- a/tests/snapshots/asm/posix_unix_headers.aarch64.asm +++ b/tests/snapshots/asm/posix_unix_headers.aarch64.asm @@ -13,52 +13,30 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x240 - b - mov x0, #0x1 // =1 - add sp, sp, #0x240 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x80 mov x2, #0x0 // =0 b - b - sxtw x1, w2 - cmp x1, #0x80 - b.ge - sxtw x1, w2 add x1, x0, x1 mov x3, #0x0 // =0 strb w3, [x1] add x1, x2, #0x1 sxtw x2, w1 - b - b + sxtw x1, w2 + cmp x1, #0x80 + b.lt sub x0, x29, #0x80 - mov x1, #0x3 // =3 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0x8 // =8 orr x1, x1, x17 strb w1, [x0] sub x0, x29, #0x80 - mov x1, #0x28 // =40 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w1, [x0] + ldrb w1, [x0, #0x5] mov x17, #0x1 // =1 orr x1, x1, x17 - strb w1, [x0] + strb w1, [x0, #0x5] sub x0, x29, #0x80 - mov x1, #0x3 // =3 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x8 // =8 and x0, x0, x17 @@ -66,12 +44,7 @@ Disassembly of section .text: cset x1, eq cbnz x1, sub x0, x29, #0x80 - mov x1, #0x28 // =40 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 - ldrb w0, [x0] + ldrb w0, [x0, #0x5] mov x17, #0x1 // =1 and x0, x0, x17 cmp x0, #0x0 @@ -82,11 +55,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x4 // =4 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x10 // =16 and x0, x0, x17 @@ -96,11 +65,7 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x80 - mov x1, #0x3 // =3 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w1, [x0] mov x17, #0xfff7 // =65527 movk x17, #0xffff, lsl #16 @@ -109,11 +74,7 @@ Disassembly of section .text: and x2, x1, x17 strb w2, [x0] sub x0, x29, #0x80 - mov x1, #0x3 // =3 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - add x0, x0, x1 + add x0, x0, #0x0 ldrb w0, [x0] mov x17, #0x8 // =8 and x0, x0, x17 @@ -122,21 +83,6 @@ Disassembly of section .text: add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x240 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x240 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x7 // =7 - add sp, sp, #0x240 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x230 mov x1, #0x78 // =120 strb w1, [x0] @@ -169,3 +115,24 @@ Disassembly of section .text: ret b b + mov x0, #0x1 // =1 + add sp, sp, #0x240 + ldp x29, x30, [sp], #0x10 + ret + b + b + b + b + b + mov x0, #0x5 // =5 + add sp, sp, #0x240 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x240 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + add sp, sp, #0x240 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/posix_unix_headers.x64.asm b/tests/snapshots/asm/posix_unix_headers.x64.asm index 47b5db233..787a4ad75 100644 --- a/tests/snapshots/asm/posix_unix_headers.x64.asm +++ b/tests/snapshots/asm/posix_unix_headers.x64.asm @@ -14,50 +14,28 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x240, %rsp # imm = 0x240 - jmp - movl $0x1, %eax - addq $0x240, %rsp # imm = 0x240 - popq %rbp - retq leaq -0x80(%rbp), %rax xorq %rdx, %rdx jmp - jmp - movslq %edx, %rcx - cmpq $0x80, %rcx - jge - movslq %edx, %rcx addq %rax, %rcx xorq %rsi, %rsi movb %sil, (%rcx) leaq 0x1(%rdx), %rcx movslq %ecx, %rdx - jmp - jmp + movslq %edx, %rcx + cmpq $0x80, %rcx + jl leaq -0x80(%rbp), %rax - movl $0x3, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx orq $0x8, %rcx movb %cl, (%rax) leaq -0x80(%rbp), %rax - movl $0x28, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rcx + movzbq 0x5(%rax), %rcx orq $0x1, %rcx - movb %cl, (%rax) + movb %cl, 0x5(%rax) leaq -0x80(%rbp), %rax - movl $0x3, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x8, %rax testq %rax, %rax @@ -66,12 +44,7 @@ Disassembly of section .text: testq %rcx, %rcx jne leaq -0x80(%rbp), %rax - movl $0x28, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax - movzbq (%rax), %rax + movzbq 0x5(%rax), %rax andq $0x1, %rax testq %rax, %rax sete %cl @@ -83,11 +56,7 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x4, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x10, %rax testq %rax, %rax @@ -97,21 +66,13 @@ Disassembly of section .text: popq %rbp retq leaq -0x80(%rbp), %rax - movl $0x3, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rcx movq %rcx, %rdx andq $-0x9, %rdx movb %dl, (%rax) leaq -0x80(%rbp), %rax - movl $0x3, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - addq %rcx, %rax + addq $0x0, %rax movzbq (%rax), %rax andq $0x8, %rax testq %rax, %rax @@ -120,21 +81,6 @@ Disassembly of section .text: addq $0x240, %rsp # imm = 0x240 popq %rbp retq - jmp - movl $0x5, %eax - addq $0x240, %rsp # imm = 0x240 - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x240, %rsp # imm = 0x240 - popq %rbp - retq - jmp - movl $0x7, %eax - addq $0x240, %rsp # imm = 0x240 - popq %rbp - retq leaq -0x230(%rbp), %rax movl $0x78, %ecx movb %cl, (%rax) @@ -165,4 +111,25 @@ Disassembly of section .text: retq jmp jmp + movl $0x1, %eax + addq $0x240, %rsp # imm = 0x240 + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + movl $0x5, %eax + addq $0x240, %rsp # imm = 0x240 + popq %rbp + retq + movl $0x6, %eax + addq $0x240, %rsp # imm = 0x240 + popq %rbp + retq + movl $0x7, %eax + addq $0x240, %rsp # imm = 0x240 + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/posix_utime_errno_headers.aarch64.asm b/tests/snapshots/asm/posix_utime_errno_headers.aarch64.asm index b277f066b..c36d64dde 100644 --- a/tests/snapshots/asm/posix_utime_errno_headers.aarch64.asm +++ b/tests/snapshots/asm/posix_utime_errno_headers.aarch64.asm @@ -30,17 +30,15 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x2 // =2 + mov x0, #0x0 // =0 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x3 // =3 + mov x0, #0x2 // =2 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x3 // =3 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/posix_utime_errno_headers.x64.asm b/tests/snapshots/asm/posix_utime_errno_headers.x64.asm index 974861c74..1efed1481 100644 --- a/tests/snapshots/asm/posix_utime_errno_headers.x64.asm +++ b/tests/snapshots/asm/posix_utime_errno_headers.x64.asm @@ -31,17 +31,15 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - jmp - movl $0x2, %eax + xorq %rax, %rax addq $0x10, %rsp popq %rbp retq - jmp - movl $0x3, %eax + movl $0x2, %eax addq $0x10, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x3, %eax addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/pragma_operator.aarch64.asm b/tests/snapshots/asm/pragma_operator.aarch64.asm index 116793f22..f48125d0d 100644 --- a/tests/snapshots/asm/pragma_operator.aarch64.asm +++ b/tests/snapshots/asm/pragma_operator.aarch64.asm @@ -10,19 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - b - mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrb w1, [x0] @@ -40,11 +27,11 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret diff --git a/tests/snapshots/asm/pragma_operator.x64.asm b/tests/snapshots/asm/pragma_operator.x64.asm index fc6a2733c..fe4c80281 100644 --- a/tests/snapshots/asm/pragma_operator.x64.asm +++ b/tests/snapshots/asm/pragma_operator.x64.asm @@ -11,19 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - jmp - movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp - retq leaq , %rax movsbq (%rax), %rcx cmpq $0x5f, %rcx @@ -38,12 +25,11 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp - addb %al, 0x41(%rdx) + movl $0x1, %eax + retq + movl $0x2, %eax + retq diff --git a/tests/snapshots/asm/predefined_constants.aarch64.asm b/tests/snapshots/asm/predefined_constants.aarch64.asm index 9493e36c9..f4fe5c965 100644 --- a/tests/snapshots/asm/predefined_constants.aarch64.asm +++ b/tests/snapshots/asm/predefined_constants.aarch64.asm @@ -10,44 +10,31 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - b mov x0, #0x9 // =9 ret - b mov x0, #0xa // =10 ret - b mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/predefined_constants.x64.asm b/tests/snapshots/asm/predefined_constants.x64.asm index 294a3e090..7ba405f56 100644 --- a/tests/snapshots/asm/predefined_constants.x64.asm +++ b/tests/snapshots/asm/predefined_constants.x64.asm @@ -11,44 +11,32 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - jmp movl $0x9, %eax retq - jmp movl $0xa, %eax retq - jmp movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/predefined_macros.aarch64.asm b/tests/snapshots/asm/predefined_macros.aarch64.asm index 4028f4e41..c507f5a9d 100644 --- a/tests/snapshots/asm/predefined_macros.aarch64.asm +++ b/tests/snapshots/asm/predefined_macros.aarch64.asm @@ -10,24 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xf // =15 - mov x1, #0x10 // =16 - sub x0, x1, x0 - sxtw x0, w0 - cmp x0, #0x1 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrb w1, [x0, #0x3] @@ -37,8 +19,6 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrb w1, [x0, #0x6] mov x17, #0x20 // =32 @@ -47,15 +27,11 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrb w0, [x0, #0xb] cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -66,8 +42,6 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrb w1, [x0, #0x5] mov x17, #0x3a // =58 @@ -76,15 +50,11 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrb w0, [x0, #0x8] cmp x0, #0x0 b.eq mov x0, #0x8 // =8 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -92,10 +62,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x9 // =9 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 ret diff --git a/tests/snapshots/asm/predefined_macros.x64.asm b/tests/snapshots/asm/predefined_macros.x64.asm index 2c5dff8e3..82c486f1b 100644 --- a/tests/snapshots/asm/predefined_macros.x64.asm +++ b/tests/snapshots/asm/predefined_macros.x64.asm @@ -11,79 +11,47 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movl $0xf, %eax - movl $0x10, %ecx - movq %rax, %r10 - movq %rcx, %rax - subq %r10, %rax - movslq %eax, %rax - cmpq $0x1, %rax - je - movl $0x1, %eax - addq $0x30, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x30, %rsp - popq %rbp - retq leaq , %rax movsbq 0x3(%rax), %rcx cmpq $0x20, %rcx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movsbq 0x6(%rax), %rcx cmpq $0x20, %rcx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq movsbq 0xb(%rax), %rax testq %rax, %rax je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movsbq 0x2(%rax), %rcx cmpq $0x3a, %rcx je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp retq movsbq 0x5(%rax), %rcx cmpq $0x3a, %rcx je movl $0x7, %eax - addq $0x30, %rsp - popq %rbp retq movsbq 0x8(%rax), %rax testq %rax, %rax je movl $0x8, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rax testq %rax, %rax jne movl $0x9, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp + retq + movl $0x1, %eax + retq + movl $0x2, %eax retq diff --git a/tests/snapshots/asm/preinc_narrow_lvalue_wraps.aarch64.asm b/tests/snapshots/asm/preinc_narrow_lvalue_wraps.aarch64.asm index ebc77daa8..5082a20bd 100644 --- a/tests/snapshots/asm/preinc_narrow_lvalue_wraps.aarch64.asm +++ b/tests/snapshots/asm/preinc_narrow_lvalue_wraps.aarch64.asm @@ -10,156 +10,82 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xff // =255 - mov x2, #0x0 // =0 - add x0, x0, #0x1 - mov x17, #0xff // =255 - and x1, x0, x17 - cmp x1, #0x0 - b.ne - mov x2, #0x1 // =1 - sxtw x1, w2 - cmp x1, #0x1 - cset x2, eq - cbz x2, - mov x17, #0xff // =255 - and x0, x0, x17 - cmp x0, #0x0 - cset x2, eq - cbz x2, mov x1, #0x0 // =0 - b mov x1, #0x1 // =1 + sxtw x0, w1 + cmp x0, #0x1 + cset x1, eq + cbz x1, + mov x1, #0x1 // =1 + cbz x1, + mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xffff // =65535 - mov x2, #0x0 // =0 - add x0, x0, #0x1 - mov x17, #0xffff // =65535 - and x1, x0, x17 - cmp x1, #0x0 - b.ne - mov x2, #0x1 // =1 - sxtw x1, w2 - cmp x1, #0x1 - cset x2, eq - cbz x2, - mov x17, #0xffff // =65535 - and x0, x0, x17 - cmp x0, #0x0 - cset x2, eq - cbz x2, mov x1, #0x0 // =0 - b mov x1, #0x1 // =1 + sxtw x0, w1 + cmp x0, #0x1 + cset x1, eq + cbz x1, + mov x1, #0x1 // =1 + cbz x1, + mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x2, #0x0 // =0 - add x0, x0, #0x1 - mov w1, w0 - cmp x1, #0x0 - b.ne - mov x2, #0x1 // =1 - sxtw x1, w2 - cmp x1, #0x1 - cset x2, eq - cbz x2, - mov w0, w0 - cmp x0, #0x0 - cset x2, eq - cbz x2, mov x1, #0x0 // =0 - b mov x1, #0x1 // =1 + sxtw x0, w1 + cmp x0, #0x1 + cset x1, eq + cbz x1, + mov x1, #0x1 // =1 + cbz x1, + mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xf0 // =240 - mov x2, #0x0 // =0 - add x0, x0, #0x10 - mov x17, #0xff // =255 - and x1, x0, x17 - cmp x1, #0x0 - b.ne - mov x2, #0x1 // =1 - sxtw x1, w2 - cmp x1, #0x1 - cset x2, eq - cbz x2, - mov x17, #0xff // =255 - and x0, x0, x17 - cmp x0, #0x0 - cset x2, eq - cbz x2, mov x1, #0x0 // =0 - b mov x1, #0x1 // =1 + sxtw x0, w1 + cmp x0, #0x1 + cset x1, eq + cbz x1, + mov x1, #0x1 // =1 + cbz x1, + mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xfff0 // =65520 - mov x2, #0x0 // =0 - add x0, x0, #0x10 - mov x17, #0xffff // =65535 - and x1, x0, x17 - cmp x1, #0x0 - b.ne - mov x2, #0x1 // =1 - sxtw x1, w2 - cmp x1, #0x1 - cset x2, eq - cbz x2, - mov x17, #0xffff // =65535 - and x0, x0, x17 - cmp x0, #0x0 - cset x2, eq - cbz x2, mov x1, #0x0 // =0 - b mov x1, #0x1 // =1 + sxtw x0, w1 + cmp x0, #0x1 + cset x1, eq + cbz x1, + mov x1, #0x1 // =1 + cbz x1, + mov x1, #0x0 // =0 mov x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 b b @@ -187,24 +113,23 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] - mov x20, #0x0 // =0 + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 bl - orr x20, x20, x0 + mov x17, #0x0 // =0 + orr x20, x0, x17 bl orr x20, x20, x0 bl @@ -221,8 +146,7 @@ Disassembly of section .text: bl sxtw x0, w0 sxtw x0, w20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/preinc_narrow_lvalue_wraps.x64.asm b/tests/snapshots/asm/preinc_narrow_lvalue_wraps.x64.asm index 6d8d2d59c..aa57d7f14 100644 --- a/tests/snapshots/asm/preinc_narrow_lvalue_wraps.x64.asm +++ b/tests/snapshots/asm/preinc_narrow_lvalue_wraps.x64.asm @@ -11,171 +11,97 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xff, %eax - xorq %rdx, %rdx - incq %rax - movq %rax, %rcx - andq $0xff, %rcx + xorq %rcx, %rcx + movl $0x1, %ecx + movslq %ecx, %rax + cmpq $0x1, %rax + sete %cl + movzbq %cl, %rcx testq %rcx, %rcx - jne - movl $0x1, %edx - movslq %edx, %rcx - cmpq $0x1, %rcx - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx je - andq $0xff, %rax - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + movl $0x1, %ecx + testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xffff, %eax # imm = 0xFFFF - xorq %rdx, %rdx - incq %rax - movq %rax, %rcx - andq $0xffff, %rcx # imm = 0xFFFF + xorq %rcx, %rcx + movl $0x1, %ecx + movslq %ecx, %rax + cmpq $0x1, %rax + sete %cl + movzbq %cl, %rcx testq %rcx, %rcx - jne - movl $0x1, %edx - movslq %edx, %rcx - cmpq $0x1, %rcx - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx je - andq $0xffff, %rax # imm = 0xFFFF - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + movl $0x1, %ecx + testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - xorq %rdx, %rdx - incq %rax - movl %eax, %ecx + xorq %rcx, %rcx + movl $0x1, %ecx + movslq %ecx, %rax + cmpq $0x1, %rax + sete %cl + movzbq %cl, %rcx testq %rcx, %rcx - jne - movl $0x1, %edx - movslq %edx, %rcx - cmpq $0x1, %rcx - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx je - movl %eax, %eax - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + movl $0x1, %ecx + testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xf0, %eax - xorq %rdx, %rdx - addq $0x10, %rax - movq %rax, %rcx - andq $0xff, %rcx + xorq %rcx, %rcx + movl $0x1, %ecx + movslq %ecx, %rax + cmpq $0x1, %rax + sete %cl + movzbq %cl, %rcx testq %rcx, %rcx - jne - movl $0x1, %edx - movslq %edx, %rcx - cmpq $0x1, %rcx - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx je - andq $0xff, %rax - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + movl $0x1, %ecx + testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xfff0, %eax # imm = 0xFFF0 - xorq %rdx, %rdx - addq $0x10, %rax - movq %rax, %rcx - andq $0xffff, %rcx # imm = 0xFFFF + xorq %rcx, %rcx + movl $0x1, %ecx + movslq %ecx, %rax + cmpq $0x1, %rax + sete %cl + movzbq %cl, %rcx testq %rcx, %rcx - jne - movl $0x1, %edx - movslq %edx, %rcx - cmpq $0x1, %rcx - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx je - andq $0xffff, %rax # imm = 0xFFFF - testq %rax, %rax - sete %dl - movzbq %dl, %rdx - testq %rdx, %rdx + movl $0x1, %ecx + testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp - popq %rbp retq + movl $0x1, %ecx jmp jmp @@ -207,23 +133,23 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp jmp
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - xorq %rbx, %rbx callq - orq %rax, %rbx + movq %rax, %rbx + orq $0x0, %rbx callq orq %rax, %rbx callq @@ -241,6 +167,6 @@ Disassembly of section .text: movslq %eax, %rax movslq %ebx, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/printf.aarch64.asm b/tests/snapshots/asm/printf.aarch64.asm index e34990201..977aea4b0 100644 --- a/tests/snapshots/asm/printf.aarch64.asm +++ b/tests/snapshots/asm/printf.aarch64.asm @@ -10,17 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x7b // =123 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/printf_float.aarch64.asm b/tests/snapshots/asm/printf_float.aarch64.asm index eb9d7f6ae..e3067eec2 100644 --- a/tests/snapshots/asm/printf_float.aarch64.asm +++ b/tests/snapshots/asm/printf_float.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x3ff8000000000000 // =4609434218613702656 @@ -24,12 +23,10 @@ Disassembly of section .text: cmp x0, #0x9 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/pthread_cond_timedwait.aarch64.asm b/tests/snapshots/asm/pthread_cond_timedwait.aarch64.asm index f8e3c7b07..0bea87fca 100644 --- a/tests/snapshots/asm/pthread_cond_timedwait.aarch64.asm +++ b/tests/snapshots/asm/pthread_cond_timedwait.aarch64.asm @@ -20,8 +20,8 @@ Disassembly of section .text: sxtw x0, w0 cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret @@ -31,8 +31,8 @@ Disassembly of section .text: sxtw x0, w0 cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret @@ -41,8 +41,8 @@ Disassembly of section .text: sxtw x0, w0 cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret @@ -82,11 +82,11 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x1, #0x0 // =0 - b - mov x1, #0x4 // =4 mov x0, x1 - ldr x20, [sp] ldr x19, [sp, #0x10] + ldr x20, [sp] add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x4 // =4 + b diff --git a/tests/snapshots/asm/pthread_cond_timedwait.x64.asm b/tests/snapshots/asm/pthread_cond_timedwait.x64.asm index 3202f6d50..416c03588 100644 --- a/tests/snapshots/asm/pthread_cond_timedwait.x64.asm +++ b/tests/snapshots/asm/pthread_cond_timedwait.x64.asm @@ -92,11 +92,11 @@ Disassembly of section .text: testq %rax, %rax je xorq %rcx, %rcx - jmp - movl $0x4, %ecx movq (%rsp), %rbx movq %rcx, %rax addq $0xe0, %rsp popq %rbp retq + movl $0x4, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/pthread_create.aarch64.asm b/tests/snapshots/asm/pthread_create.aarch64.asm index 400bf422c..234a83e62 100644 --- a/tests/snapshots/asm/pthread_create.aarch64.asm +++ b/tests/snapshots/asm/pthread_create.aarch64.asm @@ -14,13 +14,11 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x90]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 mov x20, #0x0 // =0 mov x1, #0x2 // =2 mov x0, x20 @@ -39,31 +37,17 @@ Disassembly of section .text: sub x0, x29, #0x20 adrp x2, add x2, x2, - str x20, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x20, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x22 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x1, x20 + mov x3, x20 blr x9 - add sp, sp, #0x40 ldur x0, [x29, #-0x20] sub x1, x29, #0x28 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x21 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 ldur x0, [x29, #-0x28] - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret diff --git a/tests/snapshots/asm/pthread_key_once_width.aarch64.asm b/tests/snapshots/asm/pthread_key_once_width.aarch64.asm index eff9bb6ce..30c501e0e 100644 --- a/tests/snapshots/asm/pthread_key_once_width.aarch64.asm +++ b/tests/snapshots/asm/pthread_key_once_width.aarch64.asm @@ -10,25 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x1, #0x0 // =0 mov x1, #0x0 // =0 cbz x1, mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x2, #0x1 // =1 mov x2, #0x0 // =0 @@ -39,12 +24,12 @@ Disassembly of section .text: mov x1, #0x0 // =0 cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret diff --git a/tests/snapshots/asm/pthread_key_once_width.x64.asm b/tests/snapshots/asm/pthread_key_once_width.x64.asm index d66e58d31..fa36e742f 100644 --- a/tests/snapshots/asm/pthread_key_once_width.x64.asm +++ b/tests/snapshots/asm/pthread_key_once_width.x64.asm @@ -11,26 +11,11 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rcx, %rcx xorq %rcx, %rcx testq %rcx, %rcx je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x1, %edx xorq %rdx, %rdx @@ -44,12 +29,14 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp + movl $0x2, %eax + retq + movl $0x3, %eax + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/pthread_static_init.aarch64.asm b/tests/snapshots/asm/pthread_static_init.aarch64.asm index c8fbba229..726a58939 100644 --- a/tests/snapshots/asm/pthread_static_init.aarch64.asm +++ b/tests/snapshots/asm/pthread_static_init.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x0, x20 @@ -23,10 +22,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, x20 bl @@ -34,10 +32,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -46,14 +43,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/qsort_scan_extend_dedup.aarch64.asm b/tests/snapshots/asm/qsort_scan_extend_dedup.aarch64.asm new file mode 100644 index 000000000..8c6b61d0e --- /dev/null +++ b/tests/snapshots/asm/qsort_scan_extend_dedup.aarch64.asm @@ -0,0 +1,126 @@ + +qsort_scan_extend_dedup.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x20, x21, [sp, #-0x30]! + str x22, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + mov x20, x0 + mov x21, x2 + sxtw x1, w1 + sxtw x21, w21 + cmp x1, x21 + b.lt + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + add x0, x1, x21 + sxtw x0, w0 + asr x2, x0, #63 + lsr x2, x2, #63 + add x0, x0, x2 + asr x0, x0, #1 + ldrsw x0, [x20, x0, lsl #2] + mov x2, x21 + mov x22, x1 + b + b + add x22, x3, #0x1 + sxtw x3, w22 + ldrsw x4, [x20, x3, lsl #2] + cmp x4, x0 + b.lt + b + sub x2, x4, #0x1 + sxtw x4, w2 + ldrsw x5, [x20, x4, lsl #2] + cmp x5, x0 + b.gt + cmp x3, x4 + b.gt + ldrsw x5, [x20, x3, lsl #2] + ldrsw x6, [x20, x4, lsl #2] + str w6, [x20, x3, lsl #2] + str w5, [x20, x4, lsl #2] + add x22, x22, #0x1 + sub x2, x4, #0x1 + b + sxtw x3, w22 + sxtw x4, w2 + cmp x3, x4 + b.le + mov x0, x20 + bl + mov x0, x20 + mov x2, x21 + mov x1, x22 + bl + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x130 + mov x2, #0x3039 // =12345 + mov x1, #0x0 // =0 + b + mov w2, w2 + mov x17, #0x4e6d // =20077 + movk x17, #0x41c6, lsl #16 + mul x2, x2, x17 + mov w2, w2 + mov x17, #0x3039 // =12345 + add x2, x2, x17 + mov w2, w2 + sub x3, x29, #0x100 + mov w4, w2 + lsr x4, x4, #16 + mov x17, #0x4000 // =16384 + sub x4, x4, x17 + str w4, [x3, x0, lsl #2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + sub x0, x29, #0x100 + mov x1, #0x0 // =0 + mov x2, #0x3f // =63 + bl + mov x1, #0x1 // =1 + b + sub x2, x29, #0x100 + ldrsw x2, [x2, x0, lsl #2] + sub x3, x29, #0x100 + sub x4, x1, #0x1 + sxtw x4, w4 + ldrsw x3, [x3, x4, lsl #2] + cmp x2, x3 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + mov x0, #0x0 // =0 + add sp, sp, #0x130 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + add sp, sp, #0x130 + ldp x29, x30, [sp], #0x10 + ret + b diff --git a/tests/snapshots/asm/qsort_scan_extend_dedup.x64.asm b/tests/snapshots/asm/qsort_scan_extend_dedup.x64.asm new file mode 100644 index 000000000..54c8b3c93 --- /dev/null +++ b/tests/snapshots/asm/qsort_scan_extend_dedup.x64.asm @@ -0,0 +1,131 @@ + +qsort_scan_extend_dedup.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %rdi, %rbx + movq %rdx, %r12 + movslq %esi, %rsi + movslq %r12d, %r12 + cmpq %r12, %rsi + jl + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0x20, %rsp + popq %rbp + retq + leaq (%rsi,%r12), %rax + movslq %eax, %rax + movq %rax, %rcx + sarq $0x3f, %rcx + shrq $0x3f, %rcx + addq %rcx, %rax + sarq $0x1, %rax + movslq (%rbx,%rax,4), %rax + movq %r12, %rdx + movq %rsi, %r13 + jmp + jmp + leaq 0x1(%rcx), %r13 + movslq %r13d, %rcx + movslq (%rbx,%rcx,4), %rdi + cmpq %rax, %rdi + jl + jmp + leaq -0x1(%rdi), %rdx + movslq %edx, %rdi + movslq (%rbx,%rdi,4), %r8 + cmpq %rax, %r8 + jg + cmpq %rdi, %rcx + jg + movslq (%rbx,%rcx,4), %r8 + movslq (%rbx,%rdi,4), %r9 + movl %r9d, (%rbx,%rcx,4) + movl %r8d, (%rbx,%rdi,4) + incq %r13 + leaq -0x1(%rdi), %rdx + jmp + movslq %r13d, %rcx + movslq %edx, %rdi + cmpq %rdi, %rcx + jle + movq %rbx, %rdi + callq + movq %rbx, %rdi + movq %r12, %rdx + movq %r13, %rsi + callq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0x20, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x130, %rsp # imm = 0x130 + movl $0x3039, %edx # imm = 0x3039 + xorq %rcx, %rcx + jmp + movl %edx, %edx + imulq $0x41c64e6d, %rdx, %rdx # imm = 0x41C64E6D + movl %edx, %edx + addq $0x3039, %rdx # imm = 0x3039 + movl %edx, %edx + leaq -0x100(%rbp), %rsi + movl %edx, %edi + shrq $0x10, %rdi + subq $0x4000, %rdi # imm = 0x4000 + movl %edi, (%rsi,%rax,4) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + leaq -0x100(%rbp), %rdi + xorq %rsi, %rsi + movl $0x3f, %edx + callq + movl $0x1, %ecx + jmp + leaq -0x100(%rbp), %rdx + movslq (%rdx,%rax,4), %rdx + leaq -0x100(%rbp), %rsi + leaq -0x1(%rcx), %rdi + movslq %edi, %rdi + movslq (%rsi,%rdi,4), %rsi + cmpq %rsi, %rdx + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + xorq %rax, %rax + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + movl $0x1, %eax + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/queens.aarch64.asm b/tests/snapshots/asm/queens.aarch64.asm index d8abbb26d..11f277a50 100644 --- a/tests/snapshots/asm/queens.aarch64.asm +++ b/tests/snapshots/asm/queens.aarch64.asm @@ -10,109 +10,84 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 sxtw x1, w1 sxtw x2, w2 mov x4, #0x0 // =0 - sxtw x3, w4 - cmp x3, x1 - b.ge b - add x3, x4, #0x1 - sxtw x4, w3 - b - sxtw x3, w4 sub x5, x1, x3 sxtw x5, w5 - ldrsw x3, [x0, x3, lsl #2] - sub x3, x2, x3 - sxtw x6, w3 - cmp x6, #0x0 + ldrsw x6, [x0, x3, lsl #2] + sub x6, x2, x6 + sxtw x7, w6 + cmp x7, #0x0 b.ge - b - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - mul x3, x6, x17 - sxtw x6, w3 - sxtw x3, w4 + mul x6, x7, x17 + sxtw x7, w6 ldrsw x3, [x0, x3, lsl #2] cmp x3, x2 + b.eq + sxtw x3, w7 + cmp x5, x3 b.ne + b + b + add x3, x4, #0x1 + sxtw x4, w3 + sxtw x3, w4 + cmp x3, x1 + b.lt + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - sxtw x3, w6 - cmp x5, x3 - b.ne mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b - b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x30]! + stp x22, x23, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, x0 mov x21, x1 sxtw x21, w21 cmp x21, #0x8 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret mov x22, #0x0 // =0 mov x23, x22 - sxtw x0, w22 - cmp x0, #0x8 - b.ge b - add x0, x22, #0x1 - sxtw x22, w0 - b - sxtw x2, w22 mov x0, x20 + mov x2, x22 mov x1, x21 bl cbz x0, b - sxtw x0, w23 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b str w22, [x20, x21, lsl #2] - add x0, x21, #0x1 - sxtw x1, w0 + add x1, x21, #0x1 mov x0, x20 bl add x0, x23, x0 sxtw x23, w0 - b + add x0, x22, #0x1 + sxtw x22, w0 + sxtw x0, w22 + cmp x0, #0x8 + b.lt + sxtw x0, w23 + ldp x29, x30, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/queens.x64.asm b/tests/snapshots/asm/queens.x64.asm index fde1dd524..80c60038a 100644 --- a/tests/snapshots/asm/queens.x64.asm +++ b/tests/snapshots/asm/queens.x64.asm @@ -13,56 +13,53 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movslq %esi, %rsi movslq %edx, %rdx xorq %rcx, %rcx - movslq %ecx, %rax - cmpq %rsi, %rax - jge - jmp - leaq 0x1(%rcx), %rax - movslq %eax, %rcx jmp - movslq %ecx, %rax movq %rsi, %r8 subq %rax, %r8 movslq %r8d, %r8 - movslq (%rdi,%rax,4), %rax - movq %rax, %r10 - movq %rdx, %rax - subq %r10, %rax - movslq %eax, %r9 - testq %r9, %r9 + movslq (%rdi,%rax,4), %r9 + movq %r9, %r10 + movq %rdx, %r9 + subq %r10, %r9 + movslq %r9d, %rbx + testq %rbx, %rbx jge + imulq $-0x1, %rbx, %r9 + movslq %r9d, %rbx + movslq (%rdi,%rax,4), %rax + cmpq %rdx, %rax + je + movslq %ebx, %rax + cmpq %rax, %r8 + jne + jmp jmp + leaq 0x1(%rcx), %rax + movslq %eax, %rcx + movslq %ecx, %rax + cmpq %rsi, %rax + jl xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq - imulq $-0x1, %r9, %rax - movslq %eax, %r9 - movslq %ecx, %rax - movslq (%rdi,%rax,4), %rax - cmpq %rdx, %rax - jne movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq - movslq %r9d, %rax - cmpq %rax, %r8 - jne movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq jmp - jmp : pushq %rbp @@ -87,20 +84,25 @@ Disassembly of section .text: retq xorq %r13, %r13 movq %r13, %r14 - movslq %r13d, %rax - cmpq $0x8, %rax - jge - jmp - leaq 0x1(%r13), %rax - movslq %eax, %r13 jmp - movslq %r13d, %rdx movq %rbx, %rdi + movq %r13, %rdx movq %r12, %rsi callq testq %rax, %rax je jmp + movl %r13d, (%rbx,%r12,4) + leaq 0x1(%r12), %rsi + movq %rbx, %rdi + callq + addq %r14, %rax + movslq %eax, %r14 + leaq 0x1(%r13), %rax + movslq %eax, %r13 + movslq %r13d, %rax + cmpq $0x8, %rax + jl movslq %r14d, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 @@ -109,15 +111,6 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - jmp - movl %r13d, (%rbx,%r12,4) - leaq 0x1(%r12), %rax - movslq %eax, %rsi - movq %rbx, %rdi - callq - addq %r14, %rax - movslq %eax, %r14 - jmp
: pushq %rbp @@ -137,5 +130,3 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/quicksort.aarch64.asm b/tests/snapshots/asm/quicksort.aarch64.asm index 60f828ee8..9d92ddd76 100644 --- a/tests/snapshots/asm/quicksort.aarch64.asm +++ b/tests/snapshots/asm/quicksort.aarch64.asm @@ -18,14 +18,11 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] str x24, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, x0 mov x21, x2 mov x23, x1 @@ -33,18 +30,26 @@ Disassembly of section .text: sxtw x21, w21 ldrsw x22, [x20, x21, lsl #2] sub x24, x23, #0x1 - sxtw x0, w23 - cmp x0, x21 - b.ge - b - sxtw x0, w23 - add x23, x0, #0x1 b sxtw x0, w23 ldrsw x0, [x20, x0, lsl #2] cmp x0, x22 b.gt + add x24, x24, #0x1 + sxtw x0, w24 + lsl x0, x0, #2 + add x0, x20, x0 + sxtw x1, w23 + lsl x1, x1, #2 + add x1, x20, x1 + bl + b b + sxtw x0, w23 + add x23, x0, #0x1 + sxtw x0, w23 + cmp x0, x21 + b.lt add x0, x24, #0x1 sxtw x0, w0 lsl x0, x0, #2 @@ -54,33 +59,17 @@ Disassembly of section .text: bl add x0, x24, #0x1 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x24, [sp, #0x20] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret - add x24, x24, #0x1 - sxtw x0, w24 - lsl x0, x0, #2 - add x0, x20, x0 - sxtw x1, w23 - lsl x1, x1, #2 - add x1, x20, x1 - bl - b - b : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x30]! + stp x22, x23, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, x0 mov x22, x2 mov x21, x1 @@ -93,31 +82,25 @@ Disassembly of section .text: mov x1, x21 bl mov x23, x0 - sub x0, x23, #0x1 - sxtw x2, w0 + sub x2, x23, #0x1 mov x0, x20 mov x1, x21 bl - add x0, x23, #0x1 - sxtw x1, w0 + add x1, x23, #0x1 mov x0, x20 mov x2, x22 bl mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x30 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x14 // =20 bl mov x20, x0 @@ -139,50 +122,44 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldrsw x0, [x20, #0x4] cmp x0, #0x7 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldrsw x0, [x20, #0x8] cmp x0, #0xa b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldrsw x0, [x20, #0xc] cmp x0, #0xc b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldrsw x0, [x20, #0x10] cmp x0, #0xf b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/quicksort.x64.asm b/tests/snapshots/asm/quicksort.x64.asm index 1aababed7..482cec7de 100644 --- a/tests/snapshots/asm/quicksort.x64.asm +++ b/tests/snapshots/asm/quicksort.x64.asm @@ -34,18 +34,26 @@ Disassembly of section .text: movslq %r12d, %r12 movslq (%rbx,%r12,4), %r13 leaq -0x1(%r14), %r15 - movslq %r14d, %rax - cmpq %r12, %rax - jge - jmp - movslq %r14d, %rax - leaq 0x1(%rax), %r14 jmp movslq %r14d, %rax movslq (%rbx,%rax,4), %rax cmpq %r13, %rax jg + incq %r15 + movslq %r15d, %rax + shlq $0x2, %rax + leaq (%rbx,%rax), %rdi + movslq %r14d, %rax + shlq $0x2, %rax + leaq (%rbx,%rax), %rsi + callq + jmp jmp + movslq %r14d, %rax + leaq 0x1(%rax), %r14 + movslq %r14d, %rax + cmpq %r12, %rax + jl leaq 0x1(%r15), %rax movslq %eax, %rax shlq $0x2, %rax @@ -64,16 +72,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - incq %r15 - movslq %r15d, %rax - shlq $0x2, %rax - leaq (%rbx,%rax), %rdi - movslq %r14d, %rax - shlq $0x2, %rax - leaq (%rbx,%rax), %rsi - callq - jmp - jmp : pushq %rbp @@ -95,13 +93,11 @@ Disassembly of section .text: movq %r12, %rsi callq movq %rax, %r14 - leaq -0x1(%r14), %rax - movslq %eax, %rdx + leaq -0x1(%r14), %rdx movq %rbx, %rdi movq %r12, %rsi callq - leaq 0x1(%r14), %rax - movslq %eax, %rsi + leaq 0x1(%r14), %rsi movq %rbx, %rdi movq %r13, %rdx callq @@ -117,7 +113,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x14, %edi xorl %eax, %eax @@ -142,7 +138,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movslq 0x4(%rbx), %rax @@ -150,7 +146,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movslq 0x8(%rbx), %rax @@ -158,7 +154,7 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movslq 0xc(%rbx), %rax @@ -166,7 +162,7 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movslq 0x10(%rbx), %rax @@ -174,12 +170,13 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/recursion_factorial.aarch64.asm b/tests/snapshots/asm/recursion_factorial.aarch64.asm index c4d136beb..f69166775 100644 --- a/tests/snapshots/asm/recursion_factorial.aarch64.asm +++ b/tests/snapshots/asm/recursion_factorial.aarch64.asm @@ -10,27 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, x0 sxtw x20, w20 cmp x20, #0x2 b.ge mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret sub x0, x20, #0x1 - sxtw x0, w0 bl mul x0, x20, x0 sxtw x0, w0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/recursion_factorial.x64.asm b/tests/snapshots/asm/recursion_factorial.x64.asm index 839f71e7d..6e37aafab 100644 --- a/tests/snapshots/asm/recursion_factorial.x64.asm +++ b/tests/snapshots/asm/recursion_factorial.x64.asm @@ -24,8 +24,7 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - leaq -0x1(%rbx), %rax - movslq %eax, %rdi + leaq -0x1(%rbx), %rdi callq imulq %rbx, %rax movslq %eax, %rax @@ -40,4 +39,3 @@ Disassembly of section .text: movl $0x5, %edi popq %rbp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.aarch64.asm b/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.aarch64.asm new file mode 100644 index 000000000..a9115bfb7 --- /dev/null +++ b/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.aarch64.asm @@ -0,0 +1,126 @@ + +reg_alloc_callee_bank_call_block_before_loop.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x20, x21, [sp, #-0x30]! + str x22, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + mov x20, x0 + mov x21, x2 + sxtw x1, w1 + sxtw x21, w21 + cmp x1, x21 + b.lt + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + add x0, x1, x21 + sxtw x0, w0 + asr x2, x0, #63 + lsr x2, x2, #63 + add x0, x0, x2 + asr x0, x0, #1 + ldrsw x0, [x20, x0, lsl #2] + mov x2, x21 + mov x22, x1 + b + b + add x22, x3, #0x1 + sxtw x3, w22 + ldrsw x4, [x20, x3, lsl #2] + cmp x4, x0 + b.lt + b + sub x2, x4, #0x1 + sxtw x4, w2 + ldrsw x5, [x20, x4, lsl #2] + cmp x5, x0 + b.gt + cmp x3, x4 + b.gt + ldrsw x5, [x20, x3, lsl #2] + ldrsw x6, [x20, x4, lsl #2] + str w6, [x20, x3, lsl #2] + str w5, [x20, x4, lsl #2] + add x22, x22, #0x1 + sub x2, x4, #0x1 + b + sxtw x3, w22 + sxtw x4, w2 + cmp x3, x4 + b.le + mov x0, x20 + bl + mov x0, x20 + mov x2, x21 + mov x1, x22 + bl + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x130 + mov x2, #0x3039 // =12345 + mov x1, #0x0 // =0 + b + mov w2, w2 + mov x17, #0x4e6d // =20077 + movk x17, #0x41c6, lsl #16 + mul x2, x2, x17 + mov w2, w2 + mov x17, #0x3039 // =12345 + add x2, x2, x17 + mov w2, w2 + sub x3, x29, #0x100 + mov w4, w2 + mov x17, #0xffff // =65535 + movk x17, #0x7fff, lsl #16 + and x4, x4, x17 + str w4, [x3, x0, lsl #2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + sub x0, x29, #0x100 + mov x1, #0x0 // =0 + mov x2, #0x3f // =63 + bl + mov x1, #0x1 // =1 + b + sub x2, x29, #0x100 + ldrsw x2, [x2, x0, lsl #2] + sub x3, x29, #0x100 + sub x4, x1, #0x1 + sxtw x4, w4 + ldrsw x3, [x3, x4, lsl #2] + cmp x2, x3 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + mov x0, #0x0 // =0 + add sp, sp, #0x130 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + add sp, sp, #0x130 + ldp x29, x30, [sp], #0x10 + ret + b diff --git a/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.x64.asm b/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.x64.asm new file mode 100644 index 000000000..071aa0088 --- /dev/null +++ b/tests/snapshots/asm/reg_alloc_callee_bank_call_block_before_loop.x64.asm @@ -0,0 +1,130 @@ + +reg_alloc_callee_bank_call_block_before_loop.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %rdi, %rbx + movq %rdx, %r12 + movslq %esi, %rsi + movslq %r12d, %r12 + cmpq %r12, %rsi + jl + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0x20, %rsp + popq %rbp + retq + leaq (%rsi,%r12), %rax + movslq %eax, %rax + movq %rax, %rcx + sarq $0x3f, %rcx + shrq $0x3f, %rcx + addq %rcx, %rax + sarq $0x1, %rax + movslq (%rbx,%rax,4), %rax + movq %r12, %rdx + movq %rsi, %r13 + jmp + jmp + leaq 0x1(%rcx), %r13 + movslq %r13d, %rcx + movslq (%rbx,%rcx,4), %rdi + cmpq %rax, %rdi + jl + jmp + leaq -0x1(%rdi), %rdx + movslq %edx, %rdi + movslq (%rbx,%rdi,4), %r8 + cmpq %rax, %r8 + jg + cmpq %rdi, %rcx + jg + movslq (%rbx,%rcx,4), %r8 + movslq (%rbx,%rdi,4), %r9 + movl %r9d, (%rbx,%rcx,4) + movl %r8d, (%rbx,%rdi,4) + incq %r13 + leaq -0x1(%rdi), %rdx + jmp + movslq %r13d, %rcx + movslq %edx, %rdi + cmpq %rdi, %rcx + jle + movq %rbx, %rdi + callq + movq %rbx, %rdi + movq %r12, %rdx + movq %r13, %rsi + callq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0x20, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x130, %rsp # imm = 0x130 + movl $0x3039, %edx # imm = 0x3039 + xorq %rcx, %rcx + jmp + movl %edx, %edx + imulq $0x41c64e6d, %rdx, %rdx # imm = 0x41C64E6D + movl %edx, %edx + addq $0x3039, %rdx # imm = 0x3039 + movl %edx, %edx + leaq -0x100(%rbp), %rsi + movl %edx, %edi + andq $0x7fffffff, %rdi # imm = 0x7FFFFFFF + movl %edi, (%rsi,%rax,4) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + leaq -0x100(%rbp), %rdi + xorq %rsi, %rsi + movl $0x3f, %edx + callq + movl $0x1, %ecx + jmp + leaq -0x100(%rbp), %rdx + movslq (%rdx,%rax,4), %rdx + leaq -0x100(%rbp), %rsi + leaq -0x1(%rcx), %rdi + movslq %edi, %rdi + movslq (%rsi,%rdi,4), %rsi + cmpq %rsi, %rdx + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + xorq %rax, %rax + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + movl $0x1, %eax + addq $0x130, %rsp # imm = 0x130 + popq %rbp + retq + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/return_callee_saved_value.aarch64.asm b/tests/snapshots/asm/return_callee_saved_value.aarch64.asm index b60d7ddb6..2cc20ac9e 100644 --- a/tests/snapshots/asm/return_callee_saved_value.aarch64.asm +++ b/tests/snapshots/asm/return_callee_saved_value.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x17, #0x3 // =3 mul x0, x0, x17 add x20, x0, #0x1 @@ -23,10 +22,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret
: diff --git a/tests/snapshots/asm/return_callee_saved_value.x64.asm b/tests/snapshots/asm/return_callee_saved_value.x64.asm index 128817fdb..23a99e775 100644 --- a/tests/snapshots/asm/return_callee_saved_value.x64.asm +++ b/tests/snapshots/asm/return_callee_saved_value.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq (%rdi,%rdi,2), %rax leaq 0x1(%rax), %rbx @@ -23,7 +23,7 @@ Disassembly of section .text: movslq %eax, %rax movq %rbx, %rax movq (%rsp), %rbx - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/return_int_widens_to_double.aarch64.asm b/tests/snapshots/asm/return_int_widens_to_double.aarch64.asm index f43eddd90..2c3349b07 100644 --- a/tests/snapshots/asm/return_int_widens_to_double.aarch64.asm +++ b/tests/snapshots/asm/return_int_widens_to_double.aarch64.asm @@ -23,11 +23,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x0, #0x1f9 // =505 scvtf d0, x0 sub x17, x29, #0x8 @@ -41,10 +39,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret sub x16, x29, #0x8 ldr d0, [x16] @@ -52,21 +48,19 @@ Disassembly of section .text: movk x0, #0x407f, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x20, mi - cbnz x20, + cset x1, mi + cbnz x1, sub x16, x29, #0x8 ldr d0, [x16] mov x0, #0xa00000000000 // =175921860444160 movk x0, #0x407f, lsl #48 fmov d17, x0 fcmp d0, d17 - cset x20, gt - cbz x20, + cset x1, gt + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 @@ -80,10 +74,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 @@ -94,10 +86,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret sub x0, x29, #0x18 sub x1, x29, #0x8 @@ -109,15 +99,11 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret b diff --git a/tests/snapshots/asm/return_int_widens_to_double.x64.asm b/tests/snapshots/asm/return_int_widens_to_double.x64.asm index acf03ac41..acf34d891 100644 --- a/tests/snapshots/asm/return_int_widens_to_double.x64.asm +++ b/tests/snapshots/asm/return_int_widens_to_double.x64.asm @@ -23,8 +23,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp - movq %rbx, (%rsp) + subq $0x40, %rsp movl $0x1f9, %eax # imm = 0x1F9 cvtsi2sd %rax, %xmm0 movsd %xmm0, -0x8(%rbp,%riz) @@ -40,32 +39,30 @@ Disassembly of section .text: testq %rax, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq movsd -0x8(%rbp,%riz), %xmm0 movabsq $0x407f800000000000, %rax # imm = 0x407F800000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setb %bl - movzbq %bl, %rbx + setb %cl + movzbq %cl, %rcx setnp %r10b movzbq %r10b, %r10 - andq %r10, %rbx - testq %rbx, %rbx + andq %r10, %rcx + testq %rcx, %rcx jne movsd -0x8(%rbp,%riz), %xmm0 movabsq $0x407fa00000000000, %rax # imm = 0x407FA00000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - seta %bl - movzbq %bl, %rbx - testq %rbx, %rbx + seta %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq movabsq $-0x1, %rax @@ -84,8 +81,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq movabsq $-0x1, %rax @@ -99,8 +95,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq leaq -0x18(%rbp), %rdi @@ -113,13 +108,11 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/return_void_expression.aarch64.asm b/tests/snapshots/asm/return_void_expression.aarch64.asm index 43efabb7a..2cbb9178f 100644 --- a/tests/snapshots/asm/return_void_expression.aarch64.asm +++ b/tests/snapshots/asm/return_void_expression.aarch64.asm @@ -30,7 +30,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 bl bl adrp x0, @@ -39,9 +38,8 @@ Disassembly of section .text: cmp x0, #0x2 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/return_void_expression.x64.asm b/tests/snapshots/asm/return_void_expression.x64.asm index 12a9e7fae..0990906ff 100644 --- a/tests/snapshots/asm/return_void_expression.x64.asm +++ b/tests/snapshots/asm/return_void_expression.x64.asm @@ -29,7 +29,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp callq callq leaq , %rax @@ -37,10 +36,10 @@ Disassembly of section .text: cmpq $0x2, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/rotate_inline_const_count.aarch64.asm b/tests/snapshots/asm/rotate_inline_const_count.aarch64.asm new file mode 100644 index 000000000..c7269ad61 --- /dev/null +++ b/tests/snapshots/asm/rotate_inline_const_count.aarch64.asm @@ -0,0 +1,53 @@ + +rotate_inline_const_count.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sxtw x1, w1 + ror x0, x0, x1 + ret + +: + ror x1, x0, #0x1c + ror x2, x0, #0x22 + eor x1, x1, x2 + ror x0, x0, #0x27 + eor x0, x1, x0 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, #0xcdef // =52719 + movk x0, #0x89ab, lsl #16 + movk x0, #0x4567, lsl #32 + movk x0, #0x123, lsl #48 + stur x0, [x29, #-0x8] + ldur x0, [x29, #-0x8] + ror x1, x0, #0x1c + ror x2, x0, #0x22 + eor x1, x1, x2 + ror x0, x0, #0x27 + eor x0, x1, x0 + mov x17, #0xc1ab // =49579 + movk x17, #0xc7e, lsl #16 + movk x17, #0x7a10, lsl #32 + movk x17, #0xb7c5, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/rotate_inline_const_count.x64.asm b/tests/snapshots/asm/rotate_inline_const_count.x64.asm new file mode 100644 index 000000000..c1c898bd6 --- /dev/null +++ b/tests/snapshots/asm/rotate_inline_const_count.x64.asm @@ -0,0 +1,59 @@ + +rotate_inline_const_count.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movslq %esi, %rsi + movq %rdi, %rax + pushq %rcx + movq %rsi, %rcx + rorq %cl, %rax + popq %rcx + retq + +: + movq %rdi, %rax + rorq $0x1c, %rax + movq %rdi, %rcx + rorq $0x22, %rcx + xorq %rcx, %rax + movq %rdi, %rcx + rorq $0x27, %rcx + xorq %rcx, %rax + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movabsq $0x123456789abcdef, %rax # imm = 0x123456789ABCDEF + movq %rax, -0x8(%rbp) + movq -0x8(%rbp), %rax + movq %rax, %rcx + rorq $0x1c, %rcx + movq %rax, %rdx + rorq $0x22, %rdx + xorq %rdx, %rcx + rorq $0x27, %rax + xorq %rcx, %rax + movabsq $-0x483a85eff3813e55, %r11 # imm = 0xB7C57A100C7EC1AB + cmpq %r11, %rax + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/rotate_variable_count.aarch64.asm b/tests/snapshots/asm/rotate_variable_count.aarch64.asm index d9bf4ba51..d27f591cb 100644 --- a/tests/snapshots/asm/rotate_variable_count.aarch64.asm +++ b/tests/snapshots/asm/rotate_variable_count.aarch64.asm @@ -15,44 +15,33 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x3, #0x0 // =0 mov x2, x3 - sxtw x4, w3 - cmp x4, #0x40 - b.ge b - sxtw x3, w3 - add x3, x3, #0x1 + mov x5, #0x1 // =1 + lsl x5, x5, x4 + and x5, x0, x5 + cbz x5, + sub x5, x3, x1 + mov x17, #0x3f // =63 + and x5, x5, x17 + mov x6, #0x1 // =1 + sxtw x5, w5 + lsl x5, x6, x5 + orr x2, x2, x5 b - mov x4, #0x1 // =1 - sxtw x5, w3 - lsl x4, x4, x5 - and x4, x0, x4 - cbz x4, b + add x3, x4, #0x1 + sxtw x4, w3 + cmp x4, #0x40 + b.lt mov x0, x2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - sub x4, x3, x1 - mov x17, #0x3f // =63 - and x4, x4, x17 - mov x5, #0x1 // =1 - sxtw x4, w4 - lsl x4, x5, x4 - orr x2, x2, x4 - b - b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x80]! + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 sub x0, x29, #0x30 adrp x1, add x1, x1, @@ -71,21 +60,33 @@ Disassembly of section .text: str x10, [x0, #0x28] ldr x10, [sp], #0x10 mov x20, #0x0 // =0 - mov w0, w20 - mov x1, #0x30 // =48 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #3 - mov w1, w1 - cmp x0, x1 - b.hs - b - mov w0, w20 - add x20, x0, #0x1 b mov x0, #0x1 // =1 stur w0, [x29, #-0x40] b + sub x0, x29, #0x30 + mov w1, w20 + ldr x0, [x0, x1, lsl #3] + ldursw x1, [x29, #-0x40] + ror x21, x0, x1 + sub x0, x29, #0x30 + mov w1, w20 + ldr x0, [x0, x1, lsl #3] + ldursw x1, [x29, #-0x40] + bl + cmp x21, x0 + b.ne + ldursw x0, [x29, #-0x40] + add x0, x0, #0x1 + stur w0, [x29, #-0x40] + ldursw x0, [x29, #-0x40] + cmp x0, #0x40 + b.lt + mov w0, w20 + add x20, x0, #0x1 + mov w0, w20 + cmp x0, #0x6 + b.lo mov x0, #0xcdef // =52719 movk x0, #0x89ab, lsl #16 movk x0, #0x4567, lsl #32 @@ -100,45 +101,17 @@ Disassembly of section .text: bl cmp x20, x0 b.eq - b - ldursw x0, [x29, #-0x40] - cmp x0, #0x40 - b.ge - b - ldursw x0, [x29, #-0x40] - add x0, x0, #0x1 - stur w0, [x29, #-0x40] - b - sub x0, x29, #0x30 - mov w1, w20 - ldr x0, [x0, x1, lsl #3] - ldursw x1, [x29, #-0x40] - ror x21, x0, x1 - sub x0, x29, #0x30 - mov w1, w20 - ldr x0, [x0, x1, lsl #3] - ldursw x1, [x29, #-0x40] - bl - cmp x21, x0 - b.eq - b - b - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 - ret - b mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldp x20, x21, [sp], #0x80 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldp x20, x21, [sp], #0x80 ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldp x20, x21, [sp], #0x80 + ret + b + b diff --git a/tests/snapshots/asm/rotate_variable_count.x64.asm b/tests/snapshots/asm/rotate_variable_count.x64.asm index 2df0f9e20..e4831f528 100644 --- a/tests/snapshots/asm/rotate_variable_count.x64.asm +++ b/tests/snapshots/asm/rotate_variable_count.x64.asm @@ -20,45 +20,36 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x40, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - movl $0x1, %edx - movslq %ecx, %r8 + movl $0x1, %r8d pushq %rcx - movq %r8, %rcx - shlq %cl, %rdx + movq %rdx, %rcx + shlq %cl, %r8 popq %rcx - andq %rdi, %rdx - testq %rdx, %rdx + andq %rdi, %r8 + testq %r8, %r8 je - jmp - addq $0x20, %rsp - popq %rbp - retq - movq %rcx, %rdx - subq %rsi, %rdx - andq $0x3f, %rdx - movl $0x1, %r8d - movslq %edx, %rdx - movq %rdx, %r10 - movq %r8, %rdx + movq %rcx, %r8 + subq %rsi, %r8 + andq $0x3f, %r8 + movl $0x1, %r9d + movslq %r8d, %r8 + movq %r8, %r10 + movq %r9, %r8 pushq %rcx movq %r10, %rcx - shlq %cl, %rdx + shlq %cl, %r8 popq %rcx - orq %rdx, %rax + orq %r8, %rax jmp jmp + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + cmpq $0x40, %rdx + jl + retq
: pushq %rbp @@ -83,42 +74,10 @@ Disassembly of section .text: movq %rdx, 0x28(%rax) popq %rdx xorq %rbx, %rbx - movl %ebx, %eax - movl $0x30, %ecx - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x3, %rcx - movl %ecx, %ecx - cmpq %rcx, %rax - jae - jmp - movl %ebx, %eax - leaq 0x1(%rax), %rbx jmp movl $0x1, %eax movl %eax, -0x40(%rbp) jmp - movabsq $0x123456789abcdef, %rdi # imm = 0x123456789ABCDEF - movq %rdi, -0x48(%rbp) - movq -0x48(%rbp), %rax - shrq $0x7, %rax - movq -0x48(%rbp), %rcx - shlq $0x39, %rcx - movq %rax, %rbx - orq %rcx, %rbx - movl $0x7, %esi - callq - cmpq %rax, %rbx - je - jmp - movslq -0x40(%rbp), %rax - cmpq $0x40, %rax - jge - jmp - movslq -0x40(%rbp), %rax - incq %rax - movl %eax, -0x40(%rbp) - jmp leaq -0x30(%rbp), %rax movl %ebx, %ecx movq (%rax,%rcx,8), %rax @@ -131,26 +90,48 @@ Disassembly of section .text: movslq -0x40(%rbp), %rsi callq cmpq %rax, %r12 + jne + movslq -0x40(%rbp), %rax + incq %rax + movl %eax, -0x40(%rbp) + movslq -0x40(%rbp), %rax + cmpq $0x40, %rax + jl + movl %ebx, %eax + leaq 0x1(%rax), %rbx + movl %ebx, %eax + cmpq $0x6, %rax + jb + movabsq $0x123456789abcdef, %rdi # imm = 0x123456789ABCDEF + movq %rdi, -0x48(%rbp) + movq -0x48(%rbp), %rax + shrq $0x7, %rax + movq -0x48(%rbp), %rcx + shlq $0x39, %rcx + movq %rax, %rbx + orq %rcx, %rbx + movl $0x7, %esi + callq + cmpq %rax, %rbx je - jmp - jmp - movl $0x1, %eax + movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x70, %rsp popq %rbp retq - jmp - movl $0x2, %eax + xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x70, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x70, %rsp popq %rbp retq - addb %al, (%rax) + jmp + jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/scalar_brace_initializer.aarch64.asm b/tests/snapshots/asm/scalar_brace_initializer.aarch64.asm index faa411fc0..413f3aac5 100644 --- a/tests/snapshots/asm/scalar_brace_initializer.aarch64.asm +++ b/tests/snapshots/asm/scalar_brace_initializer.aarch64.asm @@ -10,74 +10,37 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0x5 // =5 + adrp x0, + add x0, x0, adrp x1, add x1, x1, - add x2, x0, #0x1 - sxtw x2, w2 - mov x3, #0x7 // =7 - add x4, x0, x2 - sxtw x4, w4 - cmp x4, #0xb - b.eq - mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - adrp x4, - add x4, x4, - ldrsw x4, [x4] - cmp x4, #0x29 + ldrsw x1, [x1] + cmp x1, #0x29 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x5 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - ldrb w0, [x1] + ldrb w1, [x0] mov x17, #0x78 // =120 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - cset x0, ne - mov x5, #0x1 // =1 - cbnz x0, - ldrb w0, [x1, #0x1] + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + cset x1, ne + mov x3, #0x1 // =1 + cbnz x1, + ldrb w1, [x0, #0x1] mov x17, #0x79 // =121 - eor x0, x0, x17 - mov w0, w0 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + cset x1, ne + cmp x1, #0x0 + cset x3, ne + cbnz x3, + ldrb w0, [x0, #0x2] cmp x0, #0x0 - cset x0, ne - cmp x0, #0x0 - cset x5, ne - cbnz x5, - ldrb w0, [x1, #0x2] - cmp x0, #0x0 - cset x5, ne - cbz x5, + cset x3, ne + cbz x3, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - cmp x2, #0x6 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - cmp x3, #0x7 - b.eq - mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -85,12 +48,16 @@ Disassembly of section .text: cmp x0, #0x64 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b + mov x0, #0x5 // =5 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x6 // =6 + ret diff --git a/tests/snapshots/asm/scalar_brace_initializer.x64.asm b/tests/snapshots/asm/scalar_brace_initializer.x64.asm index 462b54166..00a1bb56d 100644 --- a/tests/snapshots/asm/scalar_brace_initializer.x64.asm +++ b/tests/snapshots/asm/scalar_brace_initializer.x64.asm @@ -11,85 +11,54 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movl $0x5, %eax + leaq , %rax leaq , %rcx - leaq 0x1(%rax), %rdx - movslq %edx, %rdx - movl $0x7, %esi - leaq (%rax,%rdx), %rdi - movslq %edi, %rdi - cmpq $0xb, %rdi - je - movl $0x5, %eax - addq $0x40, %rsp - popq %rbp - retq - leaq , %rdi - movslq (%rdi), %rdi - cmpq $0x29, %rdi + movslq (%rcx), %rcx + cmpq $0x29, %rcx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp - retq - cmpq $0x5, %rax - je - movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq - movsbq (%rcx), %rax - cmpq $0x78, %rax - setne %al - movzbq %al, %rax - movl $0x1, %r8d - testq %rax, %rax + movsbq (%rax), %rcx + cmpq $0x78, %rcx + setne %cl + movzbq %cl, %rcx + movl $0x1, %esi + testq %rcx, %rcx jne - movsbq 0x1(%rcx), %rax - cmpq $0x79, %rax - setne %al - movzbq %al, %rax - testq %rax, %rax - setne %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + movsbq 0x1(%rax), %rcx + cmpq $0x79, %rcx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi jne - movsbq 0x2(%rcx), %rax + movsbq 0x2(%rax), %rax testq %rax, %rax - setne %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp - retq - cmpq $0x6, %rdx - je - movl $0x4, %eax - addq $0x40, %rsp - popq %rbp - retq - cmpq $0x7, %rsi - je - movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax cmpq $0x64, %rax je movl $0x7, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp + movl $0x5, %eax + retq + movl $0x2, %eax + retq + movl $0x4, %eax + retq + movl $0x6, %eax + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/scanf_fscanf_binding.aarch64.asm b/tests/snapshots/asm/scanf_fscanf_binding.aarch64.asm index 6ecfd7140..724e9c5fe 100644 --- a/tests/snapshots/asm/scanf_fscanf_binding.aarch64.asm +++ b/tests/snapshots/asm/scanf_fscanf_binding.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,18 +48,15 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sxtw x0, w0 mov x2, #0x0 // =0 stur w2, [x29, #-0x8] @@ -88,7 +81,6 @@ Disassembly of section .text: ldursw x1, [x29, #-0x10] add x0, x0, x1 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret diff --git a/tests/snapshots/asm/setenv_overwrite.aarch64.asm b/tests/snapshots/asm/setenv_overwrite.aarch64.asm index af5842795..e84eeee7b 100644 --- a/tests/snapshots/asm/setenv_overwrite.aarch64.asm +++ b/tests/snapshots/asm/setenv_overwrite.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, adrp x1, @@ -38,9 +37,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -59,12 +57,10 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/setenv_then_get.aarch64.asm b/tests/snapshots/asm/setenv_then_get.aarch64.asm index ed8896b45..08510435e 100644 --- a/tests/snapshots/asm/setenv_then_get.aarch64.asm +++ b/tests/snapshots/asm/setenv_then_get.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, adrp x1, @@ -27,12 +26,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w0, [x0] - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/setenv_then_get.x64.asm b/tests/snapshots/asm/setenv_then_get.x64.asm index e7a11f3cf..81dfd1e66 100644 --- a/tests/snapshots/asm/setenv_then_get.x64.asm +++ b/tests/snapshots/asm/setenv_then_get.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp leaq , %rdi leaq , %rsi movl $0x1, %edx @@ -26,11 +25,10 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x1, %eax - addq $0x20, %rsp popq %rbp retq movsbq (%rax), %rax - addq $0x20, %rsp popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/setjmp_longjmp.aarch64.asm b/tests/snapshots/asm/setjmp_longjmp.aarch64.asm index acb009f3d..fe73f4170 100644 --- a/tests/snapshots/asm/setjmp_longjmp.aarch64.asm +++ b/tests/snapshots/asm/setjmp_longjmp.aarch64.asm @@ -10,42 +10,31 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x1, w1 str w1, [x0, #0x200] bl uxtb w0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x250 - str x20, [sp] - str x19, [sp, #0x10] - b - mov x0, #0xb // =11 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 - ldp x29, x30, [sp], #0x10 - ret + sub sp, sp, #0x240 + str x19, [sp] mov x0, #0x0 // =0 sub x17, x29, #0x210 str w0, [x17] sub x0, x29, #0x208 bl sxtw x0, w0 - mov x20, x0 - sxtw x0, w20 - cmp x0, #0x0 + sxtw x1, w0 + cmp x1, #0x0 b.ne sub x16, x29, #0x210 ldrsw x0, [x16] @@ -56,18 +45,15 @@ Disassembly of section .text: mov x1, #0x7 // =7 bl mov x0, #0xc // =12 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 + ldr x19, [sp] + add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret - sxtw x0, w20 - cmp x0, #0x7 + cmp x1, #0x7 b.eq mov x0, #0xd // =13 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 + ldr x19, [sp] + add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret sub x16, x29, #0x210 @@ -75,9 +61,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0xe // =14 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 + ldr x19, [sp] + add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x208 @@ -85,14 +70,17 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0xf // =15 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 + ldr x19, [sp] + add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x250 + ldr x19, [sp] + add sp, sp, #0x240 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + ldr x19, [sp] + add sp, sp, #0x240 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/setjmp_longjmp.x64.asm b/tests/snapshots/asm/setjmp_longjmp.x64.asm index 9433b7070..f3d5191e8 100644 --- a/tests/snapshots/asm/setjmp_longjmp.x64.asm +++ b/tests/snapshots/asm/setjmp_longjmp.x64.asm @@ -25,23 +25,15 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x240, %rsp # imm = 0x240 - movq %rbx, (%rsp) - jmp - movl $0xb, %eax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 - popq %rbp - retq + subq $0x230, %rsp # imm = 0x230 xorq %rax, %rax movl %eax, -0x210(%rbp) leaq -0x208(%rbp), %rdi xorl %eax, %eax callq movslq %eax, %rax - movq %rax, %rbx - movslq %ebx, %rax - testq %rax, %rax + movslq %eax, %rcx + testq %rcx, %rcx jne movslq -0x210(%rbp), %rax incq %rax @@ -50,24 +42,20 @@ Disassembly of section .text: movl $0x7, %esi callq movl $0xc, %eax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 + addq $0x230, %rsp # imm = 0x230 popq %rbp retq - movslq %ebx, %rax - cmpq $0x7, %rax + cmpq $0x7, %rcx je movl $0xd, %eax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 + addq $0x230, %rsp # imm = 0x230 popq %rbp retq movslq -0x210(%rbp), %rax cmpq $0x1, %rax je movl $0xe, %eax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 + addq $0x230, %rsp # imm = 0x230 popq %rbp retq leaq -0x208(%rbp), %rax @@ -75,13 +63,15 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0xf, %eax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 + addq $0x230, %rsp # imm = 0x230 popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x240, %rsp # imm = 0x240 + addq $0x230, %rsp # imm = 0x230 + popq %rbp + retq + movl $0xb, %eax + addq $0x230, %rsp # imm = 0x230 popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/setjmp_longjmp_roundtrip.aarch64.asm b/tests/snapshots/asm/setjmp_longjmp_roundtrip.aarch64.asm index 2ce8811cd..4eea3e144 100644 --- a/tests/snapshots/asm/setjmp_longjmp_roundtrip.aarch64.asm +++ b/tests/snapshots/asm/setjmp_longjmp_roundtrip.aarch64.asm @@ -10,45 +10,35 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x19, [sp, #0x10] - mov x20, x1 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 sxtw x0, w0 - sxtw x20, w20 - adrp x1, - add x1, x1, - ldrsw x2, [x1] - add x2, x2, #0x1 - str w2, [x1] + sxtw x1, w1 + adrp x2, + add x2, x2, + ldrsw x3, [x2] + add x3, x3, #0x1 + str w3, [x2] cmp x0, #0x0 b.le sub x0, x0, #0x1 - sxtw x0, w0 - mov x1, x20 bl mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, - mov x1, x20 bl uxtb w0, w0 b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x0, #0x1 // =1 @@ -68,11 +58,9 @@ Disassembly of section .text: mov x1, #0x2a // =42 bl mov x0, #0xb // =11 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -80,11 +68,9 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0xc // =12 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x2 // =2 str w0, [x20] @@ -98,11 +84,9 @@ Disassembly of section .text: bl uxtb w0, w0 mov x0, #0x15 // =21 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -118,7 +102,11 @@ Disassembly of section .text: ldrsw x0, [x0] cmp x0, #0x1 b.eq - b + mov x0, #0x16 // =22 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret mov x0, #0x3 // =3 str w0, [x20] adrp x0, @@ -130,42 +118,20 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x0 b.eq - b - adrp x0, - add x0, x0, - mov x1, #0x1 // =1 - str w1, [x0] - mov x1, #0x0 // =0 - mov x0, x21 - bl - uxtb w0, w0 - mov x0, #0x17 // =23 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x16 // =22 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b adrp x0, add x0, x0, ldrsw x0, [x0] cmp x0, #0x7 b.eq - b + mov x0, #0x20 // =32 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, @@ -175,17 +141,22 @@ Disassembly of section .text: bl uxtb w0, w0 mov x0, #0x1f // =31 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret - mov x0, #0x20 // =32 - ldr x20, [sp] - ldr x21, [sp, #0x8] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + str w1, [x0] + mov x1, #0x0 // =0 + mov x0, x21 + bl + uxtb w0, w0 + mov x0, #0x17 // =23 + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret b + b diff --git a/tests/snapshots/asm/setjmp_longjmp_roundtrip.x64.asm b/tests/snapshots/asm/setjmp_longjmp_roundtrip.x64.asm index 9a21ee7f2..9ee1223cb 100644 --- a/tests/snapshots/asm/setjmp_longjmp_roundtrip.x64.asm +++ b/tests/snapshots/asm/setjmp_longjmp_roundtrip.x64.asm @@ -13,28 +13,20 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movq %rsi, %rbx movslq %edi, %rdi - movslq %ebx, %rbx + movslq %esi, %rsi leaq , %rax movslq (%rax), %rcx incq %rcx movl %ecx, (%rax) testq %rdi, %rdi jle - leaq -0x1(%rdi), %rax - movslq %eax, %rdi - movq %rbx, %rsi + decq %rdi callq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x10, %rsp popq %rbp retq leaq , %rdi - movq %rbx, %rsi xorl %eax, %eax callq movzbq %al, %rax @@ -110,7 +102,12 @@ Disassembly of section .text: movslq (%rax), %rax cmpq $0x1, %rax je - jmp + movl $0x16, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq movl $0x3, %eax movl %eax, (%rbx) leaq , %rax @@ -122,33 +119,16 @@ Disassembly of section .text: movslq %eax, %rax testq %rax, %rax je - jmp leaq , %rax - movl $0x1, %ecx - movl %ecx, (%rax) - xorq %rsi, %rsi - movq %r12, %rdi - xorl %eax, %eax - callq - movzbq %al, %rax - movl $0x17, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x10, %rsp - popq %rbp - retq - movl $0x16, %eax + movslq (%rax), %rax + cmpq $0x7, %rax + je + movl $0x20, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x10, %rsp popq %rbp retq - jmp - leaq , %rax - movslq (%rax), %rax - cmpq $0x7, %rax - je - jmp xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 @@ -168,12 +148,20 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movl $0x20, %eax + leaq , %rax + movl $0x1, %ecx + movl %ecx, (%rax) + xorq %rsi, %rsi + movq %r12, %rdi + xorl %eax, %eax + callq + movzbq %al, %rax + movl $0x17, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 addq $0x10, %rsp popq %rbp retq jmp + jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/setjmp_spill_slots_unshared.aarch64.asm b/tests/snapshots/asm/setjmp_spill_slots_unshared.aarch64.asm new file mode 100644 index 000000000..b3fb138ff --- /dev/null +++ b/tests/snapshots/asm/setjmp_spill_slots_unshared.aarch64.asm @@ -0,0 +1,317 @@ + +setjmp_spill_slots_unshared.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x300 // =768 + movk x1, #0x0, lsl #16 + b + brk #: + stp x20, x21, [sp, #-0x60]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] + str x19, [sp, #0x40] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 + mov x1, #0x0 // =0 + b + adrp x2, + add x2, x2, + add x3, x0, #0x1 + str w3, [x2, x0, lsl #2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + adrp x0, + add x0, x0, + ldrsw x1, [x0] + mov x17, #0x3 // =3 + mul x1, x1, x17 + sxtw x2, w1 + sxtw x20, w2 + ldrsw x1, [x0, #0x4] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x1 + sxtw x21, w1 + ldrsw x1, [x0, #0x8] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x2 + sxtw x22, w1 + ldrsw x1, [x0, #0xc] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x3 + sxtw x23, w1 + ldrsw x1, [x0, #0x10] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x4 + sxtw x24, w1 + ldrsw x1, [x0, #0x14] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x5 + sxtw x25, w1 + ldrsw x1, [x0, #0x18] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x6 + sxtw x26, w1 + ldrsw x0, [x0, #0x1c] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x7 + sxtw x27, w0 + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + cmp x0, #0x0 + b.eq + mov x2, #0x0 // =0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + mov x17, #0x3 // =3 + mul x0, x0, x17 + sxtw x1, w0 + sxtw x0, w1 + cmp x20, x0 + b.eq + mov x2, #0x1 // =1 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x4] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x1 + sxtw x0, w0 + cmp x21, x0 + b.eq + mov x17, #0x2 // =2 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x8] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x2 + sxtw x0, w0 + cmp x22, x0 + b.eq + mov x17, #0x4 // =4 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0xc] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x3 + sxtw x0, w0 + cmp x23, x0 + b.eq + mov x17, #0x8 // =8 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x10] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x4 + sxtw x0, w0 + cmp x24, x0 + b.eq + mov x17, #0x10 // =16 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x14] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x5 + sxtw x0, w0 + cmp x25, x0 + b.eq + mov x17, #0x20 // =32 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x18] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x6 + sxtw x0, w0 + cmp x26, x0 + b.eq + mov x17, #0x40 // =64 + orr x2, x2, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x1c] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x7 + sxtw x0, w0 + cmp x27, x0 + b.eq + mov x17, #0x80 // =128 + orr x2, x2, x17 + sxtw x0, w2 + cbz x0, + adrp x0, + add x0, x0, + sxtw x1, w2 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x60 + ret + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x60 + ret + b + b + b + b + b + b + b + b + adrp x0, + add x0, x0, + ldrsw x1, [x0, #0x40] + mov x17, #0x5 // =5 + mul x1, x1, x17 + add x1, x1, #0x1 + ldrsw x2, [x0, #0x44] + mov x17, #0x5 // =5 + mul x2, x2, x17 + add x2, x2, #0x2 + ldrsw x3, [x0, #0x48] + mov x17, #0x5 // =5 + mul x3, x3, x17 + add x3, x3, #0x3 + ldrsw x4, [x0, #0x4c] + mov x17, #0x5 // =5 + mul x4, x4, x17 + add x4, x4, #0x4 + ldrsw x5, [x0, #0x50] + mov x17, #0x5 // =5 + mul x5, x5, x17 + add x5, x5, #0x5 + ldrsw x6, [x0, #0x54] + mov x17, #0x5 // =5 + mul x6, x6, x17 + add x6, x6, #0x6 + ldrsw x7, [x0, #0x58] + mov x17, #0x5 // =5 + mul x7, x7, x17 + add x7, x7, #0x7 + ldrsw x8, [x0, #0x5c] + mov x17, #0x5 // =5 + mul x8, x8, x17 + add x8, x8, #0x8 + ldrsw x9, [x0, #0x60] + mov x17, #0x5 // =5 + mul x9, x9, x17 + add x9, x9, #0x9 + ldrsw x10, [x0, #0x64] + mov x17, #0x5 // =5 + mul x10, x10, x17 + add x10, x10, #0xa + ldrsw x11, [x0, #0x68] + mov x17, #0x5 // =5 + mul x11, x11, x17 + add x11, x11, #0xb + ldrsw x12, [x0, #0x6c] + mov x17, #0x5 // =5 + mul x12, x12, x17 + add x12, x12, #0xc + ldrsw x13, [x0, #0x70] + mov x17, #0x5 // =5 + mul x13, x13, x17 + add x13, x13, #0xd + ldrsw x14, [x0, #0x74] + mov x17, #0x5 // =5 + mul x14, x14, x17 + add x14, x14, #0xe + ldrsw x15, [x0, #0x78] + mov x17, #0x5 // =5 + mul x15, x15, x17 + add x15, x15, #0xf + ldrsw x20, [x0, #0x7c] + mov x17, #0x5 // =5 + mul x20, x20, x17 + add x20, x20, #0x10 + ldrsw x21, [x0, #0x80] + mov x17, #0x5 // =5 + mul x21, x21, x17 + add x21, x21, #0x11 + ldrsw x22, [x0, #0x84] + mov x17, #0x5 // =5 + mul x22, x22, x17 + add x22, x22, #0x12 + ldrsw x23, [x0, #0x88] + mov x17, #0x5 // =5 + mul x23, x23, x17 + add x23, x23, #0x13 + ldrsw x0, [x0, #0x8c] + mov x17, #0x5 // =5 + mul x0, x0, x17 + add x0, x0, #0x14 + adrp x24, + add x24, x24, + add x1, x1, x2 + add x1, x1, x3 + add x1, x1, x4 + add x1, x1, x5 + add x1, x1, x6 + add x1, x1, x7 + add x1, x1, x8 + add x1, x1, x9 + add x1, x1, x10 + add x1, x1, x11 + add x1, x1, x12 + add x1, x1, x13 + add x1, x1, x14 + add x1, x1, x15 + add x1, x1, x20 + add x1, x1, x21 + add x1, x1, x22 + add x1, x1, x23 + add x0, x1, x0 + str w0, [x24] + adrp x0, + add x0, x0, + mov x1, #0x1 // =1 + bl + uxtb w0, w0 + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x60 + ret diff --git a/tests/snapshots/asm/setjmp_spill_slots_unshared.x64.asm b/tests/snapshots/asm/setjmp_spill_slots_unshared.x64.asm new file mode 100644 index 000000000..8a6162c6f --- /dev/null +++ b/tests/snapshots/asm/setjmp_spill_slots_unshared.x64.asm @@ -0,0 +1,321 @@ + +setjmp_spill_slots_unshared.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x340, %rsp # imm = 0x340 + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %r15, 0x20(%rsp) + xorq %rcx, %rcx + jmp + leaq , %rdx + leaq 0x1(%rax), %rsi + movl %esi, (%rdx,%rax,4) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + leaq , %rax + movslq (%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + movslq %ecx, %rdx + movslq %edx, %rbx + movslq 0x4(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movslq %ecx, %r12 + movslq 0x8(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x2, %rcx + movslq %ecx, %r13 + movslq 0xc(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x3, %rcx + movslq %ecx, %r14 + movslq 0x10(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x4, %rcx + movslq %ecx, %r15 + movslq 0x14(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x5, %rcx + movslq %ecx, %r10 + movq %r10, 0x338(%rsp) + movslq 0x18(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x6, %rcx + movslq %ecx, %r10 + movq %r10, 0x330(%rsp) + movslq 0x1c(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x7, %rax + movslq %eax, %r10 + movq %r10, 0x328(%rsp) + leaq , %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + testq %rax, %rax + je + xorq %rdx, %rdx + leaq , %rax + movslq (%rax), %rax + leaq (%rax,%rax,2), %rax + movslq %eax, %rcx + movslq %ecx, %rax + cmpq %rax, %rbx + je + movl $0x1, %edx + leaq , %rax + movslq 0x4(%rax), %rax + leaq (%rax,%rax,2), %rax + incq %rax + movslq %eax, %rax + cmpq %rax, %r12 + je + orq $0x2, %rdx + leaq , %rax + movslq 0x8(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x2, %rax + movslq %eax, %rax + cmpq %rax, %r13 + je + orq $0x4, %rdx + leaq , %rax + movslq 0xc(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x3, %rax + movslq %eax, %rax + cmpq %rax, %r14 + je + orq $0x8, %rdx + leaq , %rax + movslq 0x10(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x4, %rax + movslq %eax, %rax + cmpq %rax, %r15 + je + orq $0x10, %rdx + leaq , %rax + movslq 0x14(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x5, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x338(%rsp), %rax + cmpq %r10, %rax + je + orq $0x20, %rdx + leaq , %rax + movslq 0x18(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x6, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x330(%rsp), %rax + cmpq %r10, %rax + je + orq $0x40, %rdx + leaq , %rax + movslq 0x1c(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x7, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x328(%rsp), %rax + cmpq %r10, %rax + je + orq $0x80, %rdx + movslq %edx, %rax + testq %rax, %rax + je + leaq , %rdi + movslq %edx, %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x340, %rsp # imm = 0x340 + popq %rbp + retq + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x340, %rsp # imm = 0x340 + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + leaq , %rax + movslq 0x40(%rax), %rcx + leaq (%rcx,%rcx,4), %rcx + incq %rcx + movslq 0x44(%rax), %rdx + leaq (%rdx,%rdx,4), %rdx + addq $0x2, %rdx + movslq 0x48(%rax), %rsi + leaq (%rsi,%rsi,4), %rsi + addq $0x3, %rsi + movslq 0x4c(%rax), %rdi + leaq (%rdi,%rdi,4), %rdi + addq $0x4, %rdi + movslq 0x50(%rax), %r8 + leaq (%r8,%r8,4), %r8 + addq $0x5, %r8 + movslq 0x54(%rax), %r9 + leaq (%r9,%r9,4), %r9 + addq $0x6, %r9 + movslq 0x58(%rax), %rbx + leaq (%rbx,%rbx,4), %rbx + addq $0x7, %rbx + movslq 0x5c(%rax), %r12 + leaq (%r12,%r12,4), %r12 + addq $0x8, %r12 + movslq 0x60(%rax), %r13 + leaq (%r13,%r13,4), %r13 + addq $0x9, %r13 + movslq 0x64(%rax), %r14 + leaq (%r14,%r14,4), %r14 + addq $0xa, %r14 + movslq 0x68(%rax), %r15 + leaq (%r15,%r15,4), %r15 + addq $0xb, %r15 + movslq 0x6c(%rax), %r10 + movq %r10, 0x2e8(%rsp) + movq 0x2e8(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x2e0(%rsp) + movq 0x2e0(%rsp), %r10 + addq $0xc, %r10 + movq %r10, 0x2c8(%rsp) + movslq 0x70(%rax), %r10 + movq %r10, 0x298(%rsp) + movq 0x298(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x290(%rsp) + movq 0x290(%rsp), %r10 + addq $0xd, %r10 + movq %r10, 0x278(%rsp) + movslq 0x74(%rax), %r10 + movq %r10, 0x248(%rsp) + movq 0x248(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x240(%rsp) + movq 0x240(%rsp), %r10 + addq $0xe, %r10 + movq %r10, 0x228(%rsp) + movslq 0x78(%rax), %r10 + movq %r10, 0x1f8(%rsp) + movq 0x1f8(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x1f0(%rsp) + movq 0x1f0(%rsp), %r10 + addq $0xf, %r10 + movq %r10, 0x1d8(%rsp) + movslq 0x7c(%rax), %r10 + movq %r10, 0x1a8(%rsp) + movq 0x1a8(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x1a0(%rsp) + movq 0x1a0(%rsp), %r10 + addq $0x10, %r10 + movq %r10, 0x188(%rsp) + movslq 0x80(%rax), %r10 + movq %r10, 0x158(%rsp) + movq 0x158(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x150(%rsp) + movq 0x150(%rsp), %r10 + addq $0x11, %r10 + movq %r10, 0x138(%rsp) + movslq 0x84(%rax), %r10 + movq %r10, 0x108(%rsp) + movq 0x108(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x100(%rsp) + movq 0x100(%rsp), %r10 + addq $0x12, %r10 + movq %r10, 0xe8(%rsp) + movslq 0x88(%rax), %r10 + movq %r10, 0xb8(%rsp) + movq 0xb8(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0xb0(%rsp) + movq 0xb0(%rsp), %r10 + addq $0x13, %r10 + movq %r10, 0x98(%rsp) + movslq 0x8c(%rax), %rax + leaq (%rax,%rax,4), %rax + addq $0x14, %rax + leaq , %r10 + movq %r10, 0x40(%rsp) + addq %rdx, %rcx + addq %rsi, %rcx + addq %rdi, %rcx + addq %r8, %rcx + addq %r9, %rcx + addq %rbx, %rcx + addq %r12, %rcx + addq %r13, %rcx + addq %r14, %rcx + addq %r15, %rcx + addq 0x2c8(%rsp), %rcx + addq 0x278(%rsp), %rcx + addq 0x228(%rsp), %rcx + addq 0x1d8(%rsp), %rcx + addq 0x188(%rsp), %rcx + addq 0x138(%rsp), %rcx + addq 0xe8(%rsp), %rcx + addq 0x98(%rsp), %rcx + addq %rcx, %rax + movq 0x40(%rsp), %r10 + movl %eax, (%r10) + leaq , %rdi + movl $0x1, %esi + xorl %eax, %eax + callq + movzbq %al, %rax + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x340, %rsp # imm = 0x340 + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/setjmp_value_live_across.aarch64.asm b/tests/snapshots/asm/setjmp_value_live_across.aarch64.asm index 75970a0c0..481caee6c 100644 --- a/tests/snapshots/asm/setjmp_value_live_across.aarch64.asm +++ b/tests/snapshots/asm/setjmp_value_live_across.aarch64.asm @@ -10,27 +10,24 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x1 // =1 bl uxtb w0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x17, #0x7 // =7 mul x0, x0, x17 add x0, x0, x1 @@ -41,32 +38,28 @@ Disassembly of section .text: sxtw x0, w0 cbz x0, mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret bl mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x20 mov x0, #0x5 // =5 mov x1, #0x7 // =7 bl cmp x0, #0x2a b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/setjmp_value_live_across.x64.asm b/tests/snapshots/asm/setjmp_value_live_across.x64.asm index 20238ed21..b6592e08e 100644 --- a/tests/snapshots/asm/setjmp_value_live_across.x64.asm +++ b/tests/snapshots/asm/setjmp_value_live_across.x64.asm @@ -25,7 +25,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) imulq $0x7, %rdi, %rax addq %rsi, %rax @@ -38,29 +38,28 @@ Disassembly of section .text: je movq %rbx, %rax movq (%rsp), %rbx - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq callq xorq %rax, %rax movq (%rsp), %rbx - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp movl $0x5, %edi movl $0x7, %esi callq cmpq $0x2a, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/setlocale_decimal_point.aarch64.asm b/tests/snapshots/asm/setlocale_decimal_point.aarch64.asm index a03282448..dc193b0e1 100644 --- a/tests/snapshots/asm/setlocale_decimal_point.aarch64.asm +++ b/tests/snapshots/asm/setlocale_decimal_point.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,20 +48,16 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 bl mov x20, x0 ldr x0, [x20] @@ -83,11 +75,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x6 // =6 adrp x1, @@ -108,11 +98,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret bl mov x21, x0 @@ -132,21 +120,17 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret b diff --git a/tests/snapshots/asm/setlocale_decimal_point.x64.asm b/tests/snapshots/asm/setlocale_decimal_point.x64.asm index a9047b9a2..3ff930b01 100644 --- a/tests/snapshots/asm/setlocale_decimal_point.x64.asm +++ b/tests/snapshots/asm/setlocale_decimal_point.x64.asm @@ -56,7 +56,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorl %eax, %eax @@ -80,7 +80,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x6, %edi @@ -104,7 +104,7 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorl %eax, %eax @@ -129,7 +129,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -139,7 +139,7 @@ Disassembly of section .text: xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/shift_result_promoted_type.aarch64.asm b/tests/snapshots/asm/shift_result_promoted_type.aarch64.asm index d8369d8bc..cd2ddda63 100644 --- a/tests/snapshots/asm/shift_result_promoted_type.aarch64.asm +++ b/tests/snapshots/asm/shift_result_promoted_type.aarch64.asm @@ -10,63 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xfffe00000000 // =281466386776064 - movk x0, #0xffff, lsl #48 - asr x0, x0, #1 - mov x17, #0xffff00000000 // =281470681743360 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #-0x8000000000000000 // =-9223372036854775808 - lsr x0, x0, #63 - cmp x0, #0x1 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x80000000 // =2147483648 - lsr x0, x0, #31 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfff0 // =65520 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - asr x0, x0, #2 - mov x17, #0xfffc // =65532 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x80 // =128 - lsr x0, x0, #3 - cmp x0, #0x10 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/shift_result_promoted_type.x64.asm b/tests/snapshots/asm/shift_result_promoted_type.x64.asm index 4630c329f..7d5579172 100644 --- a/tests/snapshots/asm/shift_result_promoted_type.x64.asm +++ b/tests/snapshots/asm/shift_result_promoted_type.x64.asm @@ -11,55 +11,16 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movabsq $-0x200000000, %rax # imm = 0xFFFFFFFE00000000 - sarq $0x1, %rax - movabsq $-0x100000000, %r11 # imm = 0xFFFFFFFF00000000 - cmpq %r11, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 - shrq $0x3f, %rax - cmpq $0x1, %rax - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x80000000, %eax # imm = 0x80000000 - shrq $0x1f, %rax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movabsq $-0x10, %rax - sarq $0x2, %rax - cmpq $-0x4, %rax - je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x80, %eax - shrq $0x3, %rax - cmpq $0x10, %rax - je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/shift_result_type_signedness.aarch64.asm b/tests/snapshots/asm/shift_result_type_signedness.aarch64.asm index f69ca3b48..adfda056b 100644 --- a/tests/snapshots/asm/shift_result_type_signedness.aarch64.asm +++ b/tests/snapshots/asm/shift_result_type_signedness.aarch64.asm @@ -19,88 +19,15 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0xfb // =251 - mov x1, #0x18 // =24 - sxtw x1, w1 - mov w0, w0 - lsl x0, x0, x1 - mov w0, w0 - sxtw x0, w0 - asr x0, x0, x1 - mov x17, #0xfffb // =65531 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xff // =255 - mov x1, #0x18 // =24 - sxtw x1, w1 - mov w0, w0 - lsl x0, x0, x1 - mov w0, w0 - sxtw x0, w0 - asr x0, x0, x1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x80 // =128 - mov x1, #0x18 // =24 - sxtw x1, w1 - mov w0, w0 - lsl x0, x0, x1 - mov w0, w0 - sxtw x0, w0 - asr x0, x0, x1 - mov x17, #0xff80 // =65408 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7f // =127 - mov x1, #0x18 // =24 - sxtw x1, w1 - mov w0, w0 - lsl x0, x0, x1 - mov w0, w0 - sxtw x0, w0 - asr x0, x0, x1 - cmp x0, #0x7f - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x8000 // =32768 - lsl x0, x0, #16 - sxtw x0, w0 - asr x0, x0, #16 - cmp x0, #0x0 - b.ne mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/shift_result_type_signedness.x64.asm b/tests/snapshots/asm/shift_result_type_signedness.x64.asm index 57c1cf981..82d429b95 100644 --- a/tests/snapshots/asm/shift_result_type_signedness.x64.asm +++ b/tests/snapshots/asm/shift_result_type_signedness.x64.asm @@ -26,78 +26,17 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0xfb, %eax - movl $0x18, %ecx - movslq %ecx, %rcx - movl %eax, %eax - shlq %cl, %rax - movl %eax, %eax - movslq %eax, %rax - sarq %cl, %rax - cmpq $-0x5, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0xff, %eax - movl $0x18, %ecx - movslq %ecx, %rcx - movl %eax, %eax - shlq %cl, %rax - movl %eax, %eax - movslq %eax, %rax - sarq %cl, %rax - cmpq $-0x1, %rax - je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0x80, %eax - movl $0x18, %ecx - movslq %ecx, %rcx - movl %eax, %eax - shlq %cl, %rax - movl %eax, %eax - movslq %eax, %rax - sarq %cl, %rax - cmpq $-0x80, %rax - je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0x7f, %eax - movl $0x18, %ecx - movslq %ecx, %rcx - movl %eax, %eax - shlq %cl, %rax - movl %eax, %eax - movslq %eax, %rax - sarq %cl, %rax - cmpq $0x7f, %rax - je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq - movl $0x8000, %eax # imm = 0x8000 - shlq $0x10, %rax - movslq %eax, %rax - sarq $0x10, %rax - testq %rax, %rax - jne movl $0x5, %eax - addq $0x10, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/shm_open_mode_arg.aarch64.asm b/tests/snapshots/asm/shm_open_mode_arg.aarch64.asm index cc6cd1fdf..afe78a1f4 100644 --- a/tests/snapshots/asm/shm_open_mode_arg.aarch64.asm +++ b/tests/snapshots/asm/shm_open_mode_arg.aarch64.asm @@ -10,13 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x120 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x130]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x120] + add x29, sp, #0x120 mov x22, #0x0 // =0 sub x20, x29, #0x40 adrp x21, @@ -41,12 +39,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret sxtw x0, w20 sub x1, x29, #0xc0 @@ -62,12 +58,10 @@ Disassembly of section .text: bl sxtw x0, w0 sxtw x0, w22 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0x120] ldr x19, [sp, #0x20] - add sp, sp, #0x120 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x130 ret sub x0, x29, #0xc0 ldrsw x0, [x0, #0x10] diff --git a/tests/snapshots/asm/short_types.aarch64.asm b/tests/snapshots/asm/short_types.aarch64.asm index 2901dc75c..b9b534cb1 100644 --- a/tests/snapshots/asm/short_types.aarch64.asm +++ b/tests/snapshots/asm/short_types.aarch64.asm @@ -34,99 +34,7 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0xf0 str x20, [sp] - mov x0, #0x4d2 // =1234 - mov x1, #0xffd6 // =65494 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - cmp x0, #0x4d2 - b.eq - mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0xffd6 // =65494 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x1, x17 - b.eq - mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - add x2, x0, x1 - sxtw x2, w2 - sxth x2, w2 - cmp x2, #0x4a8 - b.eq - mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - sub x2, x0, x1 - sxtw x2, w2 - sxth x2, w2 - cmp x2, #0x4fc - b.eq - mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x3 // =3 - mul x1, x1, x17 - sxtw x1, w1 - sxth x1, w1 - mov x17, #0xff82 // =65410 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x1, x17 - b.eq - mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x7 // =7 - sdiv x1, x0, x1 - sxth x1, w1 - cmp x1, #0xb0 - b.eq - mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x1, #0x7 // =7 - sdiv x17, x0, x1 - msub x0, x17, x1, x0 - sxth x0, w0 - cmp x0, #0x2 - b.eq - mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x20, #0x1 // =1 - lsl x0, x20, #14 - sxtw x0, w0 - sxth x0, w0 - mov x17, #0x4000 // =16384 - cmp x0, x17 - b.eq - mov x0, #0x8 // =8 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - lsl x0, x20, #16 - sxtw x0, w0 + mov x0, #0x10000 // =65536 bl sxth x0, w0 cmp x0, #0x0 @@ -136,8 +44,7 @@ Disassembly of section .text: add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret - lsl x0, x20, #15 - sxtw x0, w0 + mov x0, #0x8000 // =32768 bl sxth x0, w0 mov x17, #0x8000 // =32768 @@ -151,120 +58,6 @@ Disassembly of section .text: add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfff8 // =65528 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - asr x0, x0, #1 - sxth x0, w0 - mov x17, #0xfffc // =65532 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0xb // =11 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xfffe // =65534 - mov x1, #0x1 // =1 - add x2, x0, x1 - sxtw x2, w2 - sxtw x2, w2 - mov x17, #0xffff // =65535 - and x2, x2, x17 - mov x17, #0xffff // =65535 - and x2, x2, x17 - mov x17, #0xffff // =65535 - eor x2, x2, x17 - mov w2, w2 - cmp x2, #0x0 - b.eq - mov x0, #0xc // =12 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - add x0, x0, x1 - add x0, x0, #0x1 - sxtw x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0xffff // =65535 - and x0, x0, x17 - cmp x0, #0x0 - b.eq - mov x0, #0xd // =13 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x2, #0x1 // =1 - add x3, x2, x0 - sxtw x3, w3 - cmp x3, #0x0 - b.eq - mov x0, #0xe // =14 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0xffff // =65535 - and x0, x0, x17 - sxtw x3, w0 - mov x17, #0xffff // =65535 - cmp x3, x17 - b.eq - mov x0, #0xf // =15 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - sxtw x0, w0 - mov w0, w0 - cmp x0, x2 - b.hi - mov x0, #0x10 // =16 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - lsl x0, x1, #15 - sxtw x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0x8000 // =32768 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x11 // =17 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x8000 // =32768 - sxtw x0, w0 - asr x0, x0, #1 - sxtw x0, w0 - mov x17, #0x4000 // =16384 - cmp x0, x17 - b.eq - mov x0, #0x12 // =18 - ldr x20, [sp] - add sp, sp, #0xf0 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0xd8 mov x1, #0x64 // =100 strh w1, [x0] @@ -286,7 +79,6 @@ Disassembly of section .text: sub x1, x29, #0xd8 ldrsh x1, [x1, #0x4] add x0, x0, x1 - sxtw x0, w0 bl strh w0, [x20, #0x6] sub x0, x29, #0xd8 @@ -340,3 +132,83 @@ Disassembly of section .text: add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xf // =15 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10 // =16 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x11 // =17 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x12 // =18 + ldr x20, [sp] + add sp, sp, #0xf0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/short_types.x64.asm b/tests/snapshots/asm/short_types.x64.asm index 48c2120d0..61038ed7a 100644 --- a/tests/snapshots/asm/short_types.x64.asm +++ b/tests/snapshots/asm/short_types.x64.asm @@ -34,277 +34,169 @@ Disassembly of section .text: movq %rsp, %rbp subq $0xf0, %rsp movq %rbx, (%rsp) - movl $0x4d2, %eax # imm = 0x4D2 - movabsq $-0x2a, %rcx - cmpq $0x4d2, %rax # imm = 0x4D2 + movl $0x10000, %edi # imm = 0x10000 + callq + movswq %ax, %rax + testq %rax, %rax je - movl $0x1, %eax + movl $0x9, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - cmpq $-0x2a, %rcx + movl $0x8000, %edi # imm = 0x8000 + callq + movswq %ax, %rax + cmpq $-0x8000, %rax # imm = 0x8000 je - movl $0x2, %eax + movl $0xa, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - leaq (%rax,%rcx), %rdx - movslq %edx, %rdx - movswq %dx, %rdx - cmpq $0x4a8, %rdx # imm = 0x4A8 + leaq -0xd8(%rbp), %rax + movl $0x64, %ecx + movw %cx, (%rax) + leaq -0xd8(%rbp), %rax + movl $0xc8, %ecx + movw %cx, 0x2(%rax) + leaq -0xd8(%rbp), %rax + movabsq $-0x12c, %rcx # imm = 0xFED4 + movw %cx, 0x4(%rax) + leaq -0xd8(%rbp), %rbx + leaq -0xd8(%rbp), %rax + movswq (%rax), %rax + leaq -0xd8(%rbp), %rcx + movswq 0x2(%rcx), %rcx + addq %rcx, %rax + leaq -0xd8(%rbp), %rcx + movswq 0x4(%rcx), %rcx + leaq (%rax,%rcx), %rdi + callq + movw %ax, 0x6(%rbx) + leaq -0xd8(%rbp), %rax + movswq 0x6(%rax), %rax + testq %rax, %rax je - movl $0x3, %eax + movl $0x13, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movq %rax, %rdx - subq %rcx, %rdx - movslq %edx, %rdx - movswq %dx, %rdx - cmpq $0x4fc, %rdx # imm = 0x4FC + leaq -0xe0(%rbp), %rax + movl $0x7, %ecx + movw %cx, (%rax) + leaq -0xe0(%rbp), %rax + movabsq $-0x7, %rcx + movw %cx, 0x2(%rax) + leaq -0xe0(%rbp), %rax + movl $0xc0de, %ecx # imm = 0xC0DE + movw %cx, 0x4(%rax) + leaq -0xe0(%rbp), %rax + movswq (%rax), %rax + leaq -0xe0(%rbp), %rcx + movswq 0x2(%rcx), %rcx + addq %rcx, %rax + movslq %eax, %rax + testq %rax, %rax je - movl $0x4, %eax + movl $0x14, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - leaq (%rcx,%rcx,2), %rcx - movslq %ecx, %rcx - movswq %cx, %rcx - cmpq $-0x7e, %rcx + leaq -0xe0(%rbp), %rax + movzwq 0x4(%rax), %rax + xorq $0xc0de, %rax # imm = 0xC0DE + movl %eax, %eax + testq %rax, %rax je - movl $0x5, %eax + movl $0x15, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0x7, %ecx - pushq %rax - pushq %rdx - cqto - idivq %rcx - movq %rax, %rcx - popq %rdx - popq %rax - movswq %cx, %rcx - cmpq $0xb0, %rcx - je - movl $0x6, %eax + movl $0x2a, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0x7, %ecx - pushq %rdx - cqto - idivq %rcx - movq %rdx, %rax - popq %rdx - movswq %ax, %rax - cmpq $0x2, %rax - je - movl $0x7, %eax + movl $0x1, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0x1, %ebx - movq %rbx, %rax - shlq $0xe, %rax - movslq %eax, %rax - movswq %ax, %rax - cmpq $0x4000, %rax # imm = 0x4000 - je - movl $0x8, %eax + movl $0x2, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movq %rbx, %rax - shlq $0x10, %rax - movslq %eax, %rdi - callq - movswq %ax, %rax - testq %rax, %rax - je - movl $0x9, %eax + movl $0x3, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movq %rbx, %rax - shlq $0xf, %rax - movslq %eax, %rdi - callq - movswq %ax, %rax - cmpq $-0x8000, %rax # imm = 0x8000 - je - movl $0xa, %eax + movl $0x4, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movabsq $-0x8, %rax - sarq $0x1, %rax - movswq %ax, %rax - cmpq $-0x4, %rax - je - movl $0xb, %eax + movl $0x5, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0xfffe, %eax # imm = 0xFFFE - movl $0x1, %ecx - leaq (%rax,%rcx), %rdx - movslq %edx, %rdx - movslq %edx, %rdx - andq $0xffff, %rdx # imm = 0xFFFF - andq $0xffff, %rdx # imm = 0xFFFF - xorq $0xffff, %rdx # imm = 0xFFFF - movl %edx, %edx - testq %rdx, %rdx - je - movl $0xc, %eax + movl $0x6, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - addq %rcx, %rax - incq %rax - movslq %eax, %rax - movslq %eax, %rax - andq $0xffff, %rax # imm = 0xFFFF - andq $0xffff, %rax # imm = 0xFFFF - testq %rax, %rax - je - movl $0xd, %eax + movl $0x7, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movabsq $-0x1, %rax - movl $0x1, %edx - leaq (%rdx,%rax), %rsi - movslq %esi, %rsi - testq %rsi, %rsi - je - movl $0xe, %eax + movl $0x8, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - andq $0xffff, %rax # imm = 0xFFFF - movslq %eax, %rsi - cmpq $0xffff, %rsi # imm = 0xFFFF - je - movl $0xf, %eax + movl $0xb, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movslq %eax, %rax - movl %eax, %eax - cmpq %rdx, %rax - ja - movl $0x10, %eax + movl $0xc, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movq %rcx, %rax - shlq $0xf, %rax - movslq %eax, %rax - movslq %eax, %rax - andq $0xffff, %rax # imm = 0xFFFF - andq $0xffff, %rax # imm = 0xFFFF - xorq $0x8000, %rax # imm = 0x8000 - movl %eax, %eax - testq %rax, %rax - je - movl $0x11, %eax + movl $0xd, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0x8000, %eax # imm = 0x8000 - movslq %eax, %rax - sarq $0x1, %rax - movslq %eax, %rax - cmpq $0x4000, %rax # imm = 0x4000 - je - movl $0x12, %eax + movl $0xe, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - leaq -0xd8(%rbp), %rax - movl $0x64, %ecx - movw %cx, (%rax) - leaq -0xd8(%rbp), %rax - movl $0xc8, %ecx - movw %cx, 0x2(%rax) - leaq -0xd8(%rbp), %rax - movabsq $-0x12c, %rcx # imm = 0xFED4 - movw %cx, 0x4(%rax) - leaq -0xd8(%rbp), %rbx - leaq -0xd8(%rbp), %rax - movswq (%rax), %rax - leaq -0xd8(%rbp), %rcx - movswq 0x2(%rcx), %rcx - addq %rcx, %rax - leaq -0xd8(%rbp), %rcx - movswq 0x4(%rcx), %rcx - addq %rcx, %rax - movslq %eax, %rdi - callq - movw %ax, 0x6(%rbx) - leaq -0xd8(%rbp), %rax - movswq 0x6(%rax), %rax - testq %rax, %rax - je - movl $0x13, %eax + movl $0xf, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - leaq -0xe0(%rbp), %rax - movl $0x7, %ecx - movw %cx, (%rax) - leaq -0xe0(%rbp), %rax - movabsq $-0x7, %rcx - movw %cx, 0x2(%rax) - leaq -0xe0(%rbp), %rax - movl $0xc0de, %ecx # imm = 0xC0DE - movw %cx, 0x4(%rax) - leaq -0xe0(%rbp), %rax - movswq (%rax), %rax - leaq -0xe0(%rbp), %rcx - movswq 0x2(%rcx), %rcx - addq %rcx, %rax - movslq %eax, %rax - testq %rax, %rax - je - movl $0x14, %eax + movl $0x10, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - leaq -0xe0(%rbp), %rax - movzwq 0x4(%rax), %rax - xorq $0xc0de, %rax # imm = 0xC0DE - movl %eax, %eax - testq %rax, %rax - je - movl $0x15, %eax + movl $0x11, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp retq - movl $0x2a, %eax + movl $0x12, %eax movq (%rsp), %rbx addq $0xf0, %rsp popq %rbp diff --git a/tests/snapshots/asm/sieve_of_eratosthenes.aarch64.asm b/tests/snapshots/asm/sieve_of_eratosthenes.aarch64.asm index 29ba6377a..49bcd12eb 100644 --- a/tests/snapshots/asm/sieve_of_eratosthenes.aarch64.asm +++ b/tests/snapshots/asm/sieve_of_eratosthenes.aarch64.asm @@ -10,81 +10,62 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 mov x1, #0x2 // =2 - sxtw x0, w1 - mul x0, x0, x0 - mov x17, #0x86a0 // =34464 - movk x17, #0x1, lsl #16 - cmp x0, x17 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - adrp x0, - add x0, x0, - sxtw x2, w1 - add x0, x0, x2 - ldrb w0, [x0] - cmp x0, #0x0 + adrp x2, + add x2, x2, + add x2, x2, x0 + ldrb w2, [x2] + cmp x2, #0x0 b.ne + mul x2, x1, x1 + sxtw x3, w2 b - mov x2, #0x0 // =0 - mov x1, #0x2 // =2 - b - mul x0, x1, x1 - sxtw x2, w0 - b - b - sxtw x0, w2 + adrp x4, + add x4, x4, + add x2, x4, x2 + mov x4, #0x1 // =1 + strb w4, [x2] + add x3, x3, x1 + sxtw x2, w3 mov x17, #0x86a0 // =34464 movk x17, #0x1, lsl #16 - cmp x0, x17 - b.ge - b - add x2, x2, x1 + cmp x2, x17 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 + mul x2, x0, x0 + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + cmp x2, x17 + b.lt + mov x2, #0x0 // =0 + mov x1, #0x2 // =2 b - adrp x0, - add x0, x0, - sxtw x3, w2 - add x0, x0, x3 - mov x3, #0x1 // =1 - strb w3, [x0] + adrp x3, + add x3, x3, + add x3, x3, x0 + ldrb w3, [x3] + cmp x3, #0x0 + b.ne + sxtw x2, w2 + add x2, x2, #0x1 b b + add x1, x0, #0x1 sxtw x0, w1 mov x17, #0x86a0 // =34464 movk x17, #0x1, lsl #16 cmp x0, x17 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - adrp x0, - add x0, x0, - sxtw x3, w1 - add x0, x0, x3 - ldrb w0, [x0] - cmp x0, #0x0 - b.ne - b + b.lt sxtw x0, w2 mov x17, #0x2578 // =9592 cmp x0, x17 b.ne - b - sxtw x0, w2 - add x2, x0, #0x1 - b mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b + b b diff --git a/tests/snapshots/asm/sieve_of_eratosthenes.x64.asm b/tests/snapshots/asm/sieve_of_eratosthenes.x64.asm index aa1b2a8bc..a4fab242e 100644 --- a/tests/snapshots/asm/sieve_of_eratosthenes.x64.asm +++ b/tests/snapshots/asm/sieve_of_eratosthenes.x64.asm @@ -11,74 +11,55 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movl $0x2, %ecx - movslq %ecx, %rax - imulq %rax, %rax - cmpq $0x186a0, %rax # imm = 0x186A0 - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq , %rax - movslq %ecx, %rdx - addq %rdx, %rax - movsbq (%rax), %rax - testq %rax, %rax + leaq , %rdx + addq %rax, %rdx + movsbq (%rdx), %rdx + testq %rdx, %rdx jne + movq %rcx, %rdx + imulq %rcx, %rdx + movslq %edx, %rsi jmp + leaq , %rdi + addq %rdi, %rdx + movl $0x1, %edi + movb %dil, (%rdx) + addq %rcx, %rsi + movslq %esi, %rdx + cmpq $0x186a0, %rdx # imm = 0x186A0 + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + movq %rax, %rdx + imulq %rax, %rdx + cmpq $0x186a0, %rdx # imm = 0x186A0 + jl xorq %rdx, %rdx movl $0x2, %ecx jmp - movq %rcx, %rax - imulq %rcx, %rax - movslq %eax, %rdx - jmp - jmp - movslq %edx, %rax - cmpq $0x186a0, %rax # imm = 0x186A0 - jge - jmp - addq %rcx, %rdx - jmp - leaq , %rax - movslq %edx, %rsi - addq %rsi, %rax - movl $0x1, %esi - movb %sil, (%rax) + leaq , %rsi + addq %rax, %rsi + movsbq (%rsi), %rsi + testq %rsi, %rsi + jne + movslq %edx, %rdx + incq %rdx jmp jmp + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x186a0, %rax # imm = 0x186A0 - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq , %rax - movslq %ecx, %rsi - addq %rsi, %rax - movsbq (%rax), %rax - testq %rax, %rax - jne - jmp + jl movslq %edx, %rax cmpq $0x2578, %rax # imm = 0x2578 jne - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x30, %rsp - popq %rbp retq + movl $0x1, %ecx + jmp + jmp jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/signal_nsig.aarch64.asm b/tests/snapshots/asm/signal_nsig.aarch64.asm index 9a3a41405..f7e900dd0 100644 --- a/tests/snapshots/asm/signal_nsig.aarch64.asm +++ b/tests/snapshots/asm/signal_nsig.aarch64.asm @@ -13,16 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x110 - b - mov x0, #0x2 // =2 - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x110 add x0, x0, #0x108 sub x1, x29, #0x110 @@ -37,3 +27,11 @@ Disassembly of section .text: add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x2 // =2 + add sp, sp, #0x110 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x110 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/signal_nsig.x64.asm b/tests/snapshots/asm/signal_nsig.x64.asm index e5663132d..2f86f811c 100644 --- a/tests/snapshots/asm/signal_nsig.x64.asm +++ b/tests/snapshots/asm/signal_nsig.x64.asm @@ -14,16 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x110, %rsp # imm = 0x110 - jmp - movl $0x2, %eax - addq $0x110, %rsp # imm = 0x110 - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x110, %rsp # imm = 0x110 - popq %rbp - retq leaq -0x110(%rbp), %rax addq $0x108, %rax # imm = 0x108 leaq -0x110(%rbp), %rcx @@ -38,4 +28,12 @@ Disassembly of section .text: addq $0x110, %rsp # imm = 0x110 popq %rbp retq + movl $0x2, %eax + addq $0x110, %rsp # imm = 0x110 + popq %rbp + retq + movl $0x3, %eax + addq $0x110, %rsp # imm = 0x110 + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/signal_sig_t.aarch64.asm b/tests/snapshots/asm/signal_sig_t.aarch64.asm index 1bf2b2f45..c633a5fda 100644 --- a/tests/snapshots/asm/signal_sig_t.aarch64.asm +++ b/tests/snapshots/asm/signal_sig_t.aarch64.asm @@ -14,27 +14,15 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, - mov x1, #0x0 // =0 - adrp x2, - add x2, x2, - cmp x0, x2 + adrp x1, + add x1, x1, + cmp x0, x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - cmp x1, #0x0 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 ret diff --git a/tests/snapshots/asm/signal_sig_t.x64.asm b/tests/snapshots/asm/signal_sig_t.x64.asm index a5653e4c4..72feb82a5 100644 --- a/tests/snapshots/asm/signal_sig_t.x64.asm +++ b/tests/snapshots/asm/signal_sig_t.x64.asm @@ -15,26 +15,14 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - leaq -, %rax # - xorq %rcx, %rcx - leaq -, %rdx # - cmpq %rdx, %rax + leaq -, %rax # + leaq -, %rcx # + cmpq %rcx, %rax je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp - retq - testq %rcx, %rcx - je - movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq - addb %al, (%rax) + movl $0x2, %eax + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/signed_cast_extends.aarch64.asm b/tests/snapshots/asm/signed_cast_extends.aarch64.asm index 7839ee585..0b4dd6c90 100644 --- a/tests/snapshots/asm/signed_cast_extends.aarch64.asm +++ b/tests/snapshots/asm/signed_cast_extends.aarch64.asm @@ -10,159 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x19, [sp] - mov x0, #0xff // =255 - sxtb x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x80 // =128 - sxtb x0, w0 - sxtw x0, w0 - mov x17, #0xff80 // =65408 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7f // =127 - sxtb x0, w0 - sxtw x0, w0 - cmp x0, #0x7f - b.eq - mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xff // =255 - sxtb x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x5678 // =22136 - movk x0, #0x1234, lsl #16 - sxtb x0, w0 - sxtw x0, w0 - cmp x0, #0x78 - b.eq - mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xabff // =44031 - movk x0, #0x1234, lsl #16 - sxtb x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - sxth x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x8000 // =32768 - sxth x0, w0 - sxtw x0, w0 - mov x17, #0x8000 // =32768 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x5678 // =22136 - movk x0, #0x1234, lsl #16 - sxth x0, w0 - sxtw x0, w0 - mov x17, #0x5678 // =22136 - cmp x0, x17 - b.eq - mov x0, #0x9 // =9 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0x1234, lsl #16 - sxth x0, w0 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0xa // =10 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffd6 // =65494 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - sxtw x0, w0 - mov x17, #0xffd6 // =65494 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0xf0]! + stp x29, x30, [sp, #0xe0] + add x29, sp, #0xe0 sub x0, x29, #0xb8 mov x1, #0xff // =255 strb w1, [x0] @@ -183,9 +33,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 ret sub x0, x29, #0xb8 ldrb w0, [x0] @@ -202,16 +51,58 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0xd // =13 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x4 // =4 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x5 // =5 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x6 // =6 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x7 // =7 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x8 // =8 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0x9 // =9 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0xa // =10 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 + ret + mov x0, #0xb // =11 + ldp x29, x30, [sp, #0xe0] + ldr x19, [sp], #0xf0 ret diff --git a/tests/snapshots/asm/signed_cast_extends.x64.asm b/tests/snapshots/asm/signed_cast_extends.x64.asm index de545b56f..ecfe69de6 100644 --- a/tests/snapshots/asm/signed_cast_extends.x64.asm +++ b/tests/snapshots/asm/signed_cast_extends.x64.asm @@ -14,142 +14,88 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0xd0, %rsp - movl $0xff, %eax + leaq -0xb8(%rbp), %rax + movl $0xff, %ecx + movb %cl, (%rax) + leaq -0xb8(%rbp), %rax + movl $0x42, %ecx + movb %cl, 0x1(%rax) + leaq -0xb8(%rbp), %rax + movl $0x10, %ecx + movb %cl, 0x2(%rax) + leaq -0xb8(%rbp), %rax + movzbq (%rax), %rax movsbq %al, %rax movslq %eax, %rax cmpq $-0x1, %rax je - movl $0x1, %eax + movl $0xc, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x80, %eax + leaq -0xb8(%rbp), %rax + movzbq (%rax), %rax movsbq %al, %rax + shlq $0x8, %rax + leaq -0xb8(%rbp), %rcx + movzbq 0x1(%rcx), %rcx + orq %rcx, %rax movslq %eax, %rax - cmpq $-0x80, %rax + cmpq $-0xbe, %rax je - movl $0x2, %eax + movl $0xd, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x7f, %eax - movsbq %al, %rax + leaq , %rdi + movb $0x0, %al + callq movslq %eax, %rax - cmpq $0x7f, %rax - je - movl $0x3, %eax + xorq %rax, %rax addq $0xd0, %rsp popq %rbp retq - movl $0xff, %eax - movsbq %al, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0x4, %eax + movl $0x1, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x12345678, %eax # imm = 0x12345678 - movsbq %al, %rax - movslq %eax, %rax - cmpq $0x78, %rax - je - movl $0x5, %eax + movl $0x2, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x1234abff, %eax # imm = 0x1234ABFF - movsbq %al, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0x6, %eax + movl $0x3, %eax addq $0xd0, %rsp popq %rbp retq - movl $0xffff, %eax # imm = 0xFFFF - movswq %ax, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0x7, %eax + movl $0x4, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x8000, %eax # imm = 0x8000 - movswq %ax, %rax - movslq %eax, %rax - cmpq $-0x8000, %rax # imm = 0x8000 - je - movl $0x8, %eax + movl $0x5, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x12345678, %eax # imm = 0x12345678 - movswq %ax, %rax - movslq %eax, %rax - cmpq $0x5678, %rax # imm = 0x5678 - je - movl $0x9, %eax + movl $0x6, %eax addq $0xd0, %rsp popq %rbp retq - movl $0x1234ffff, %eax # imm = 0x1234FFFF - movswq %ax, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0xa, %eax + movl $0x7, %eax addq $0xd0, %rsp popq %rbp retq - movabsq $-0x2a, %rax - movslq %eax, %rax - cmpq $-0x2a, %rax - je - movl $0xb, %eax + movl $0x8, %eax addq $0xd0, %rsp popq %rbp retq - leaq -0xb8(%rbp), %rax - movl $0xff, %ecx - movb %cl, (%rax) - leaq -0xb8(%rbp), %rax - movl $0x42, %ecx - movb %cl, 0x1(%rax) - leaq -0xb8(%rbp), %rax - movl $0x10, %ecx - movb %cl, 0x2(%rax) - leaq -0xb8(%rbp), %rax - movzbq (%rax), %rax - movsbq %al, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je - movl $0xc, %eax + movl $0x9, %eax addq $0xd0, %rsp popq %rbp retq - leaq -0xb8(%rbp), %rax - movzbq (%rax), %rax - movsbq %al, %rax - shlq $0x8, %rax - leaq -0xb8(%rbp), %rcx - movzbq 0x1(%rcx), %rcx - orq %rcx, %rax - movslq %eax, %rax - cmpq $-0xbe, %rax - je - movl $0xd, %eax + movl $0xa, %eax addq $0xd0, %rsp popq %rbp retq - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax + movl $0xb, %eax addq $0xd0, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/sigpipe_ignored.aarch64.asm b/tests/snapshots/asm/sigpipe_ignored.aarch64.asm index a3d760b13..41d8211e4 100644 --- a/tests/snapshots/asm/sigpipe_ignored.aarch64.asm +++ b/tests/snapshots/asm/sigpipe_ignored.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x0, #0xd // =13 mov x1, #0x1 // =1 bl @@ -24,9 +23,8 @@ Disassembly of section .text: cmp x0, x17 b.ne mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 bl @@ -34,9 +32,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 ldrsw x0, [x0] @@ -56,12 +53,10 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret diff --git a/tests/snapshots/asm/size_t_is_unsigned.aarch64.asm b/tests/snapshots/asm/size_t_is_unsigned.aarch64.asm index 6c879e414..12b9e03d3 100644 --- a/tests/snapshots/asm/size_t_is_unsigned.aarch64.asm +++ b/tests/snapshots/asm/size_t_is_unsigned.aarch64.asm @@ -10,55 +10,21 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x9 // =9 - udiv x1, x0, x1 - cmp x1, #0x0 - b.ne + mov x0, #0x80000000 // =2147483648 + mov x2, x0 + mov w1, w2 + cmp x1, x0 + b.eq + mov x0, #0x4 // =4 + ret + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0x9 // =9 - udiv x1, x0, x1 - mov x17, #0x1c71 // =7281 - movk x17, #0x71c7, lsl #16 - movk x17, #0xc71c, lsl #32 - movk x17, #0x1c71, lsl #48 - cmp x1, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x3e8 - b.hs mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0x80000000 // =2147483648 - mov x2, #0x5 // =5 - udiv x0, x0, x2 - cmp x1, x0 - b.hs - mov x2, x1 + mov x2, #0x3333 // =13107 + movk x2, #0x3333, lsl #16 b - mov w2, w0 - mov w0, w2 - cmp x0, x1 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/size_t_is_unsigned.x64.asm b/tests/snapshots/asm/size_t_is_unsigned.x64.asm index c832fbd1c..98b111d1d 100644 --- a/tests/snapshots/asm/size_t_is_unsigned.x64.asm +++ b/tests/snapshots/asm/size_t_is_unsigned.x64.asm @@ -11,66 +11,21 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movabsq $-0x1, %rax - movl $0x9, %ecx - pushq %rax - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rax, %rcx - popq %rdx - popq %rax - testq %rcx, %rcx - jne + movl $0x80000000, %eax # imm = 0x80000000 + movq %rax, %rdx + movl %edx, %ecx + cmpq %rax, %rcx + je + movl $0x4, %eax + retq + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x9, %ecx - pushq %rax - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rax, %rcx - popq %rdx - popq %rax - movabsq $0x1c71c71c71c71c71, %r11 # imm = 0x1C71C71C71C71C71 - cmpq %r11, %rcx - je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq - cmpq $0x3e8, %rax # imm = 0x3E8 - jae movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq - movl $0x80000000, %ecx # imm = 0x80000000 - movl $0x5, %edx - movq %rdx, %r10 - pushq %rdx - xorq %rdx, %rdx - divq %r10 - popq %rdx - cmpq %rax, %rcx - jae - movq %rcx, %rdx + movl $0x33333333, %edx # imm = 0x33333333 jmp - movl %eax, %edx - movl %edx, %eax - cmpq %rcx, %rax - je - movl $0x4, %eax - addq $0x30, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x30, %rsp - popq %rbp - retq addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_abstract_fn_ptr.aarch64.asm b/tests/snapshots/asm/sizeof_abstract_fn_ptr.aarch64.asm index dc9a92033..ffbcf2df1 100644 --- a/tests/snapshots/asm/sizeof_abstract_fn_ptr.aarch64.asm +++ b/tests/snapshots/asm/sizeof_abstract_fn_ptr.aarch64.asm @@ -10,35 +10,25 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - b mov x0, #0x9 // =9 ret - b mov x0, #0xa // =10 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_abstract_fn_ptr.x64.asm b/tests/snapshots/asm/sizeof_abstract_fn_ptr.x64.asm index 38e9f325f..945e23f17 100644 --- a/tests/snapshots/asm/sizeof_abstract_fn_ptr.x64.asm +++ b/tests/snapshots/asm/sizeof_abstract_fn_ptr.x64.asm @@ -11,35 +11,25 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - jmp movl $0x9, %eax retq - jmp movl $0xa, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/sizeof_array_type_and_binding.aarch64.asm b/tests/snapshots/asm/sizeof_array_type_and_binding.aarch64.asm index d51d465e2..19e8f86f7 100644 --- a/tests/snapshots/asm/sizeof_array_type_and_binding.aarch64.asm +++ b/tests/snapshots/asm/sizeof_array_type_and_binding.aarch64.asm @@ -10,20 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_array_type_and_binding.x64.asm b/tests/snapshots/asm/sizeof_array_type_and_binding.x64.asm index 3a6911111..722b7943f 100644 --- a/tests/snapshots/asm/sizeof_array_type_and_binding.x64.asm +++ b/tests/snapshots/asm/sizeof_array_type_and_binding.x64.asm @@ -11,20 +11,16 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_basic.aarch64.asm b/tests/snapshots/asm/sizeof_basic.aarch64.asm index 95612b1be..09bb92fb8 100644 --- a/tests/snapshots/asm/sizeof_basic.aarch64.asm +++ b/tests/snapshots/asm/sizeof_basic.aarch64.asm @@ -10,26 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_basic.x64.asm b/tests/snapshots/asm/sizeof_basic.x64.asm index 39a96307c..d909750a6 100644 --- a/tests/snapshots/asm/sizeof_basic.x64.asm +++ b/tests/snapshots/asm/sizeof_basic.x64.asm @@ -11,26 +11,20 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_deref_array_clears_decay.aarch64.asm b/tests/snapshots/asm/sizeof_deref_array_clears_decay.aarch64.asm index 5d7acb19a..67d8571da 100644 --- a/tests/snapshots/asm/sizeof_deref_array_clears_decay.aarch64.asm +++ b/tests/snapshots/asm/sizeof_deref_array_clears_decay.aarch64.asm @@ -10,19 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - mov x0, #0xb8 // =184 - mov x1, #0x0 // =0 - add x0, x0, x1 - asr x0, x0, #3 - cmp x0, #0x17 - b.eq mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_deref_array_clears_decay.x64.asm b/tests/snapshots/asm/sizeof_deref_array_clears_decay.x64.asm index 8cdf23069..ba9bd0b14 100644 --- a/tests/snapshots/asm/sizeof_deref_array_clears_decay.x64.asm +++ b/tests/snapshots/asm/sizeof_deref_array_clears_decay.x64.asm @@ -11,20 +11,12 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - movl $0xb8, %eax - xorq %rcx, %rcx - addq %rcx, %rax - sarq $0x3, %rax - cmpq $0x17, %rax - je movl $0x3, %eax retq - xorq %rax, %rax - retq addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_expr.aarch64.asm b/tests/snapshots/asm/sizeof_expr.aarch64.asm index f42655b30..fc7b392e2 100644 --- a/tests/snapshots/asm/sizeof_expr.aarch64.asm +++ b/tests/snapshots/asm/sizeof_expr.aarch64.asm @@ -10,32 +10,23 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - b mov x0, #0x9 // =9 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_expr.x64.asm b/tests/snapshots/asm/sizeof_expr.x64.asm index d69c8dd8b..bde9b494a 100644 --- a/tests/snapshots/asm/sizeof_expr.x64.asm +++ b/tests/snapshots/asm/sizeof_expr.x64.asm @@ -11,32 +11,24 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - jmp movl $0x9, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_function_call_truncation.aarch64.asm b/tests/snapshots/asm/sizeof_function_call_truncation.aarch64.asm index 0c35ff3be..ff2457dd3 100644 --- a/tests/snapshots/asm/sizeof_function_call_truncation.aarch64.asm +++ b/tests/snapshots/asm/sizeof_function_call_truncation.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 sxtw x0, w0 mov x17, #0xff // =255 and x1, x0, x17 @@ -22,52 +19,14 @@ Disassembly of section .text: add x0, x1, x0 lsl x0, x0, #1 sxtw x0, w0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret
: - mov x0, #0x1234 // =4660 - sxtw x0, w0 - mov x17, #0xff // =255 - and x1, x0, x17 - asr x0, x0, #8 - mov x17, #0xff // =255 - and x0, x0, x17 - add x0, x1, x0 - lsl x0, x0, #1 - sxtw x0, w0 - cmp x0, #0x8c - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - mov x0, #0x0 // =0 - sxtw x0, w0 - mov x17, #0xff // =255 - and x1, x0, x17 - asr x0, x0, #8 - mov x17, #0xff // =255 - and x0, x0, x17 - add x0, x1, x0 - lsl x0, x0, #1 - sxtw x0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 ret - mov x0, #0xff00 // =65280 - sxtw x0, w0 - mov x17, #0xff // =255 - and x1, x0, x17 - asr x0, x0, #8 - mov x17, #0xff // =255 - and x0, x0, x17 - add x0, x1, x0 - lsl x0, x0, #1 - sxtw x0, w0 - cmp x0, #0x1fe - b.eq mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_function_call_truncation.x64.asm b/tests/snapshots/asm/sizeof_function_call_truncation.x64.asm index a5cb50d11..a5213d93b 100644 --- a/tests/snapshots/asm/sizeof_function_call_truncation.x64.asm +++ b/tests/snapshots/asm/sizeof_function_call_truncation.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movslq %edi, %rdi movq %rdi, %rax andq $0xff, %rax @@ -23,51 +20,14 @@ Disassembly of section .text: addq %rcx, %rax shlq $0x1, %rax movslq %eax, %rax - addq $0x30, %rsp - popq %rbp retq
: - movl $0x1234, %eax # imm = 0x1234 - movslq %eax, %rax - movq %rax, %rcx - andq $0xff, %rcx - sarq $0x8, %rax - andq $0xff, %rax - addq %rcx, %rax - shlq $0x1, %rax - movslq %eax, %rax - cmpq $0x8c, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax retq - xorq %rax, %rax - movslq %eax, %rax - movq %rax, %rcx - andq $0xff, %rcx - sarq $0x8, %rax - andq $0xff, %rax - addq %rcx, %rax - shlq $0x1, %rax - movslq %eax, %rax - testq %rax, %rax - je movl $0x2, %eax retq - movl $0xff00, %eax # imm = 0xFF00 - movslq %eax, %rax - movq %rax, %rcx - andq $0xff, %rcx - sarq $0x8, %rax - andq $0xff, %rax - addq %rcx, %rax - shlq $0x1, %rax - movslq %eax, %rax - cmpq $0x1fe, %rax # imm = 0x1FE - je movl $0x3, %eax retq - xorq %rax, %rax - retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sizeof_member_via_null_cast.aarch64.asm b/tests/snapshots/asm/sizeof_member_via_null_cast.aarch64.asm index 1bca61dfd..07e3ad0a5 100644 --- a/tests/snapshots/asm/sizeof_member_via_null_cast.aarch64.asm +++ b/tests/snapshots/asm/sizeof_member_via_null_cast.aarch64.asm @@ -10,26 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - b mov x0, #0xf // =15 ret - b mov x0, #0x10 // =16 ret - b mov x0, #0x11 // =17 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_member_via_null_cast.x64.asm b/tests/snapshots/asm/sizeof_member_via_null_cast.x64.asm index 7a5fa7dd6..c8aa6567f 100644 --- a/tests/snapshots/asm/sizeof_member_via_null_cast.x64.asm +++ b/tests/snapshots/asm/sizeof_member_via_null_cast.x64.asm @@ -11,26 +11,20 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - jmp movl $0xf, %eax retq - jmp movl $0x10, %eax retq - jmp movl $0x11, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_pointer_to_array_subscript.aarch64.asm b/tests/snapshots/asm/sizeof_pointer_to_array_subscript.aarch64.asm index 30229ecdf..c161a49d4 100644 --- a/tests/snapshots/asm/sizeof_pointer_to_array_subscript.aarch64.asm +++ b/tests/snapshots/asm/sizeof_pointer_to_array_subscript.aarch64.asm @@ -10,489 +10,364 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - sub x0, x29, #0x70 + adrp x0, + add x0, x0, adrp x1, add x1, x1, - str x1, [x0] - sub x0, x29, #0x70 - adrp x1, - add x1, x1, - str x1, [x0, #0x8] - sub x0, x29, #0x70 - adrp x1, - add x1, x1, - str x1, [x0, #0x10] - sub x0, x29, #0x70 - adrp x1, - add x1, x1, - str x1, [x0, #0x18] - sub x0, x29, #0x70 - adrp x1, - add x1, x1, - str x1, [x0, #0x20] - sub x0, x29, #0x70 - adrp x1, - add x1, x1, - str x1, [x0, #0x28] - sub x0, x29, #0x70 - ldr x0, [x0] - add x0, x0, #0x8 - sub x1, x29, #0x70 - ldr x1, [x1] - sub x0, x0, x1 + adrp x2, + add x2, x2, + adrp x3, + add x3, x3, + adrp x4, + add x4, x4, + adrp x5, + add x5, x5, + add x6, x0, #0x8 + sub x0, x6, x0 cmp x0, #0x8 b.eq mov x0, #0xb // =11 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x8] - add x0, x0, #0x10 - sub x1, x29, #0x70 - ldr x1, [x1, #0x8] + add x0, x1, #0x10 sub x0, x0, x1 cmp x0, #0x10 b.eq mov x0, #0xc // =12 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x10] - add x0, x0, #0x20 - sub x1, x29, #0x70 - ldr x1, [x1, #0x10] - sub x0, x0, x1 + add x0, x2, #0x20 + sub x0, x0, x2 cmp x0, #0x20 b.eq mov x0, #0xd // =13 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x18] - add x0, x0, #0x40 - sub x1, x29, #0x70 - ldr x1, [x1, #0x18] - sub x0, x0, x1 + add x0, x3, #0x40 + sub x0, x0, x3 cmp x0, #0x40 b.eq mov x0, #0xe // =14 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x20] - add x0, x0, #0x3c - sub x1, x29, #0x70 - ldr x1, [x1, #0x20] - sub x0, x0, x1 + add x0, x4, #0x3c + sub x0, x0, x4 cmp x0, #0x3c b.eq mov x0, #0xf // =15 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x20] - add x0, x0, #0x14 - sub x1, x29, #0x70 - ldr x1, [x1, #0x20] - sub x0, x0, x1 + add x0, x4, #0x14 + sub x0, x0, x4 cmp x0, #0x14 b.eq mov x0, #0x10 // =16 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - add x0, x0, #0x18 - sub x1, x29, #0x70 - ldr x1, [x1, #0x28] - sub x0, x0, x1 + add x0, x5, #0x18 + sub x0, x0, x5 cmp x0, #0x18 b.eq mov x0, #0x11 // =17 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - add x0, x0, #0xc - sub x1, x29, #0x70 - ldr x1, [x1, #0x28] - sub x0, x0, x1 + add x0, x5, #0xc + sub x0, x0, x5 cmp x0, #0xc b.eq mov x0, #0x12 // =18 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - add x0, x0, #0x4 - sub x1, x29, #0x70 - ldr x1, [x1, #0x28] - sub x0, x0, x1 + add x0, x5, #0x4 + sub x0, x0, x5 cmp x0, #0x4 b.eq mov x0, #0x13 // =19 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x8] - sxtw x2, w1 - add x3, x2, #0x3e8 - sxtw x4, w3 - strh w4, [x0, x2, lsl #1] + add x0, x1, #0x0 + mov x2, #0x3e8 // =1000 + strh w2, [x0] + mov x0, #0x3e9 // =1001 + strh w0, [x1, #0x2] + mov x0, #0x3ea // =1002 + strh w0, [x1, #0x4] + mov x0, #0x3eb // =1003 + strh w0, [x1, #0x6] + mov x0, #0x3ec // =1004 + strh w0, [x1, #0x8] + mov x0, #0x3ed // =1005 + strh w0, [x1, #0xa] + mov x0, #0x3ee // =1006 + strh w0, [x1, #0xc] + mov x0, #0x3ef // =1007 + strh w0, [x1, #0xe] + mov x2, #0x0 // =0 b - mov x1, #0x0 // =0 - sxtw x0, w1 + ldrsh x3, [x1, x0, lsl #1] + add x6, x0, #0x3e8 + sxtw x7, w6 + sxth x6, w7 + cmp x3, x6 + b.ne + add x2, x0, #0x1 + sxtw x0, w2 cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x8] - sxtw x2, w1 - ldrsh x0, [x0, x2, lsl #1] - add x2, x2, #0x3e8 - sxtw x3, w2 - sxth x2, w3 - cmp x0, x2 - b.eq - b - mov x1, #0x0 // =0 - b - add x0, x1, #0x14 - sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret + b.lt + mov x2, #0x0 // =0 b - sxtw x0, w1 + ldrsh x3, [x1, x0, lsl #1] + add x6, x0, #0x3e8 + sxtw x7, w6 + sxth x6, w7 + cmp x3, x6 + b.ne + add x2, x0, #0x1 + sxtw x0, w2 cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x8] - sxtw x2, w1 - ldrsh x0, [x0, x2, lsl #1] - add x2, x2, #0x3e8 - sxtw x3, w2 - sxth x2, w3 - cmp x0, x2 - b.eq - b + b.lt mov x1, #0x0 // =0 b - add x0, x1, #0x1c - sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret - b + mov x17, #0x14 // =20 + mul x2, x0, x17 + add x2, x4, x2 + add x2, x2, #0x0 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x0 + str w3, [x2] + mov x17, #0x14 // =20 + mul x2, x0, x17 + add x2, x4, x2 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x1 + str w3, [x2, #0x4] + mov x17, #0x14 // =20 + mul x2, x0, x17 + add x2, x4, x2 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x2 + str w3, [x2, #0x8] + mov x17, #0x14 // =20 + mul x2, x0, x17 + add x2, x4, x2 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x3 + str w3, [x2, #0xc] + mov x17, #0x14 // =20 + mul x2, x0, x17 + add x2, x4, x2 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x4 + str w3, [x2, #0x10] + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x3 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x5 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 + mov x3, #0x0 // =0 b - sub x0, x29, #0x70 - ldr x0, [x0, #0x20] - sxtw x3, w1 mov x17, #0x14 // =20 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 + mul x6, x0, x17 + add x6, x4, x6 + ldrsw x6, [x6, x2, lsl #2] mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - str w3, [x0, x4, lsl #2] - b - b + mul x7, x0, x17 + add x7, x7, x2 + sxtw x7, w7 + cmp x6, x7 + b.ne + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x5 + b.lt + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x3 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x5 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 + mov x3, #0x0 // =0 b - sub x0, x29, #0x70 - ldr x0, [x0, #0x20] - sxtw x3, w1 mov x17, #0x14 // =20 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 - ldrsw x0, [x0, x4, lsl #2] + mul x6, x0, x17 + add x6, x4, x6 + ldrsw x6, [x6, x2, lsl #2] mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - sxtw x3, w3 - cmp x0, x3 - b.eq - b - b - mov x17, #0x5 // =5 - mul x0, x1, x17 - add x0, x0, #0x28 - add x0, x0, x2 - sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret - b + mul x7, x0, x17 + add x7, x7, x2 + sxtw x7, w7 + cmp x6, x7 + b.ne + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x5 + b.lt + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x3 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x5 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x20] - sxtw x3, w1 - mov x17, #0x14 // =20 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 - ldrsw x0, [x0, x4, lsl #2] - mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - sxtw x3, w3 - cmp x0, x3 - b.eq - b - b - mov x17, #0x5 // =5 - mul x0, x1, x17 - add x0, x0, #0x3c - add x0, x0, x2 - sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret + mov x3, #0x0 // =0 b + mov x17, #0xc // =12 + mul x4, x0, x17 + add x6, x5, x4 + lsl x7, x2, #2 + add x6, x6, x7 + add x6, x6, #0x0 + add x4, x4, x7 + add x4, x4, #0x0 + mov x17, #0xff // =255 + and x4, x4, x17 + strb w4, [x6] + mov x17, #0xc // =12 + mul x4, x0, x17 + add x6, x5, x4 + lsl x7, x2, #2 + add x6, x6, x7 + add x4, x4, x7 + add x4, x4, #0x1 + mov x17, #0xff // =255 + and x4, x4, x17 + strb w4, [x6, #0x1] + mov x17, #0xc // =12 + mul x4, x0, x17 + add x6, x5, x4 + lsl x7, x2, #2 + add x6, x6, x7 + add x4, x4, x7 + add x4, x4, #0x2 + mov x17, #0xff // =255 + and x4, x4, x17 + strb w4, [x6, #0x2] + mov x17, #0xc // =12 + mul x4, x0, x17 + add x6, x5, x4 + lsl x7, x2, #2 + add x6, x6, x7 + add x4, x4, x7 + add x4, x4, #0x3 + mov x17, #0xff // =255 + and x4, x4, x17 + strb w4, [x6, #0x3] + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x3 + b.lt + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x2 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x3 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b mov x3, #0x0 // =0 b + mov x6, #0x0 // =0 b - sxtw x0, w3 - cmp x0, #0x4 - b.ge - b - sxtw x0, w3 - add x3, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - sxtw x4, w1 mov x17, #0xc // =12 - mul x4, x4, x17 - add x0, x0, x4 - sxtw x5, w2 - lsl x5, x5, #2 - add x0, x0, x5 - sxtw x6, w3 - add x0, x0, x6 - add x4, x4, x5 - add x4, x4, x6 + mul x7, x0, x17 + add x8, x5, x7 + lsl x9, x2, #2 + add x8, x8, x9 + add x8, x8, x4 + ldrb w8, [x8] + add x7, x7, x9 + add x7, x7, x4 + sxtw x7, w7 mov x17, #0xff // =255 - and x4, x4, x17 - strb w4, [x0] - b - b + and x7, x7, x17 + cmp x8, x7 + b.ne + add x6, x4, #0x1 + sxtw x4, w6 + cmp x4, #0x4 + b.lt + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x3 + b.lt + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x2 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + b.lt mov x1, #0x0 // =0 b - sxtw x0, w2 - cmp x0, #0x3 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b mov x3, #0x0 // =0 b + mov x6, #0x0 // =0 b - sxtw x0, w3 - cmp x0, #0x4 - b.ge - b - sxtw x0, w3 - add x3, x0, #0x1 - b - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - sxtw x4, w1 mov x17, #0xc // =12 - mul x4, x4, x17 - add x0, x0, x4 - sxtw x5, w2 - lsl x5, x5, #2 - add x0, x0, x5 - sxtw x6, w3 - add x0, x0, x6 - ldrb w0, [x0] - add x4, x4, x5 - add x4, x4, x6 - sxtw x4, w4 + mul x7, x0, x17 + add x8, x5, x7 + lsl x9, x2, #2 + add x8, x8, x9 + add x8, x8, x4 + ldrb w8, [x8] + add x7, x7, x9 + add x7, x7, x4 + sxtw x7, w7 mov x17, #0xff // =255 - and x4, x4, x17 - cmp x0, x4 - b.eq - b - b + and x7, x7, x17 + cmp x8, x7 + b.ne + add x6, x4, #0x1 + sxtw x4, w6 + cmp x4, #0x4 + b.lt + add x3, x2, #0x1 + sxtw x2, w3 + cmp x2, #0x3 + b.lt + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x2 + b.lt + mov x0, #0x0 // =0 + ret + mov x17, #0xc // =12 + mul x0, x1, x17 + add x0, x0, #0x6e + lsl x1, x3, #2 + add x0, x0, x1 + add x0, x0, x6 + sxtw x0, w0 + ret mov x17, #0xc // =12 mul x0, x1, x17 add x0, x0, #0x50 - lsl x1, x2, #2 + lsl x1, x3, #2 add x0, x0, x1 + add x0, x0, x6 + sxtw x0, w0 + ret + mov x17, #0x5 // =5 + mul x0, x1, x17 + add x0, x0, #0x3c + add x0, x0, x3 + sxtw x0, w0 + ret + mov x17, #0x5 // =5 + mul x0, x1, x17 + add x0, x0, #0x28 add x0, x0, x3 sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ret + add x0, x2, #0x1c + sxtw x0, w0 + ret + add x0, x2, #0x14 + sxtw x0, w0 ret b - sxtw x0, w1 - cmp x0, #0x2 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 b - mov x2, #0x0 // =0 b - mov x0, #0x0 // =0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret - sxtw x0, w2 - cmp x0, #0x3 - b.ge b - sxtw x0, w2 - add x2, x0, #0x1 b - mov x3, #0x0 // =0 b b - sxtw x0, w3 - cmp x0, #0x4 - b.ge b - sxtw x0, w3 - add x3, x0, #0x1 b - sub x0, x29, #0x70 - ldr x0, [x0, #0x28] - sxtw x4, w1 - mov x17, #0xc // =12 - mul x4, x4, x17 - add x0, x0, x4 - sxtw x5, w2 - lsl x5, x5, #2 - add x0, x0, x5 - sxtw x6, w3 - add x0, x0, x6 - ldrb w0, [x0] - add x4, x4, x5 - add x4, x4, x6 - sxtw x4, w4 - mov x17, #0xff // =255 - and x4, x4, x17 - cmp x0, x4 - b.eq b b - mov x17, #0xc // =12 - mul x0, x1, x17 - add x0, x0, #0x6e - lsl x1, x2, #2 - add x0, x0, x1 - add x0, x0, x3 - sxtw x0, w0 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret + b + b b diff --git a/tests/snapshots/asm/sizeof_pointer_to_array_subscript.x64.asm b/tests/snapshots/asm/sizeof_pointer_to_array_subscript.x64.asm index 7d533954c..b06adbc6c 100644 --- a/tests/snapshots/asm/sizeof_pointer_to_array_subscript.x64.asm +++ b/tests/snapshots/asm/sizeof_pointer_to_array_subscript.x64.asm @@ -13,8 +13,10 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xa0, %rsp + subq $0xb0, %rsp movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) leaq -0x70(%rbp), %rax leaq , %rcx movq %rcx, (%rax) @@ -43,7 +45,9 @@ Disassembly of section .text: je movl $0xb, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -56,7 +60,9 @@ Disassembly of section .text: je movl $0xc, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -69,7 +75,9 @@ Disassembly of section .text: je movl $0xd, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -82,7 +90,9 @@ Disassembly of section .text: je movl $0xe, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -95,7 +105,9 @@ Disassembly of section .text: je movl $0xf, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -108,7 +120,9 @@ Disassembly of section .text: je movl $0x10, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -121,7 +135,9 @@ Disassembly of section .text: je movl $0x11, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -134,7 +150,9 @@ Disassembly of section .text: je movl $0x12, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq leaq -0x70(%rbp), %rax @@ -147,351 +165,364 @@ Disassembly of section .text: je movl $0x13, %eax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x70(%rbp), %rax movq 0x8(%rax), %rax - movslq %ecx, %rdx - leaq 0x3e8(%rdx), %rsi - movslq %esi, %rdi - movw %di, (%rax,%rdx,2) - jmp - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp + addq $0x0, %rax + movl $0x3e8, %ecx # imm = 0x3E8 + movw %cx, (%rax) leaq -0x70(%rbp), %rax movq 0x8(%rax), %rax - movslq %ecx, %rdx - movswq (%rax,%rdx,2), %rax - addq $0x3e8, %rdx # imm = 0x3E8 - movslq %edx, %rsi - movswq %si, %rdx - cmpq %rdx, %rax - je - jmp + movl $0x3e9, %ecx # imm = 0x3E9 + movw %cx, 0x2(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3ea, %ecx # imm = 0x3EA + movw %cx, 0x4(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3eb, %ecx # imm = 0x3EB + movw %cx, 0x6(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3ec, %ecx # imm = 0x3EC + movw %cx, 0x8(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3ed, %ecx # imm = 0x3ED + movw %cx, 0xa(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3ee, %ecx # imm = 0x3EE + movw %cx, 0xc(%rax) + leaq -0x70(%rbp), %rax + movq 0x8(%rax), %rax + movl $0x3ef, %ecx # imm = 0x3EF + movw %cx, 0xe(%rax) xorq %rcx, %rcx jmp - leaq 0x14(%rcx), %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq - jmp + leaq -0x70(%rbp), %rdx + movq 0x8(%rdx), %rdx + movswq (%rdx,%rax,2), %rdx + leaq 0x3e8(%rax), %rsi + movslq %esi, %rdi + movswq %di, %rsi + cmpq %rsi, %rdx + jne + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x8, %rax - jge + jl + xorq %rcx, %rcx jmp - movslq %ecx, %rax + leaq -0x70(%rbp), %rdx + movq 0x8(%rdx), %rdx + movswq (%rdx,%rax,2), %rdx + leaq 0x3e8(%rax), %rsi + movslq %esi, %rdi + movswq %di, %rsi + cmpq %rsi, %rdx + jne leaq 0x1(%rax), %rcx - jmp - leaq -0x70(%rbp), %rax - movq 0x8(%rax), %rax - movslq %ecx, %rdx - movswq (%rax,%rdx,2), %rax - addq $0x3e8, %rdx # imm = 0x3E8 - movslq %edx, %rsi - movswq %si, %rdx - cmpq %rdx, %rax - je - jmp + movslq %ecx, %rax + cmpq $0x8, %rax + jl xorq %rcx, %rcx jmp - leaq 0x1c(%rcx), %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq - jmp + leaq -0x70(%rbp), %rdx + movq 0x20(%rdx), %rdx + imulq $0x14, %rax, %rsi + addq %rsi, %rdx + addq $0x0, %rdx + imulq $0x64, %rax, %rsi + addq $0x0, %rsi + movl %esi, (%rdx) + leaq -0x70(%rbp), %rdx + movq 0x20(%rdx), %rdx + imulq $0x14, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + incq %rsi + movl %esi, 0x4(%rdx) + leaq -0x70(%rbp), %rdx + movq 0x20(%rdx), %rdx + imulq $0x14, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x2, %rsi + movl %esi, 0x8(%rdx) + leaq -0x70(%rbp), %rdx + movq 0x20(%rdx), %rdx + imulq $0x14, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x3, %rsi + movl %esi, 0xc(%rdx) + leaq -0x70(%rbp), %rdx + movq 0x20(%rdx), %rdx + imulq $0x14, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x4, %rsi + movl %esi, 0x10(%rdx) + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x3, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + jl xorq %rcx, %rcx jmp - movslq %edx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x70(%rbp), %rax - movq 0x20(%rax), %rax - movslq %ecx, %rsi - imulq $0x14, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movl %esi, (%rax,%rdi,4) - jmp + xorq %rsi, %rsi jmp + leaq -0x70(%rbp), %rdi + movq 0x20(%rdi), %rdi + imulq $0x14, %rax, %r8 + addq %r8, %rdi + movslq (%rdi,%rdx,4), %rdi + imulq $0x64, %rax, %r8 + addq %rdx, %r8 + movslq %r8d, %r8 + cmpq %r8, %rdi + jne + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x5, %rdx + jl + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x3, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + jl xorq %rcx, %rcx jmp - movslq %edx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x70(%rbp), %rax - movq 0x20(%rax), %rax - movslq %ecx, %rsi - imulq $0x14, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - movslq (%rax,%rdi,4), %rax - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movslq %esi, %rsi - cmpq %rsi, %rax - je - jmp - jmp - leaq (%rcx,%rcx,4), %rax - addq $0x28, %rax - addq %rdx, %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq + xorq %rsi, %rsi jmp + leaq -0x70(%rbp), %rdi + movq 0x20(%rdi), %rdi + imulq $0x14, %rax, %r8 + addq %r8, %rdi + movslq (%rdi,%rdx,4), %rdi + imulq $0x64, %rax, %r8 + addq %rdx, %r8 + movslq %r8d, %r8 + cmpq %r8, %rdi + jne + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x5, %rdx + jl + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x3, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + jl xorq %rcx, %rcx jmp - movslq %edx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x70(%rbp), %rax - movq 0x20(%rax), %rax - movslq %ecx, %rsi - imulq $0x14, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - movslq (%rax,%rdi,4), %rax - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movslq %esi, %rsi - cmpq %rsi, %rax - je - jmp - jmp - leaq (%rcx,%rcx,4), %rax - addq $0x3c, %rax - addq %rdx, %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq + xorq %rsi, %rsi jmp + leaq -0x70(%rbp), %rdi + movq 0x28(%rdi), %rdi + imulq $0xc, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r9 + shlq $0x2, %r9 + addq %r9, %rdi + addq $0x0, %rdi + addq %r9, %r8 + addq $0x0, %r8 + movslq %r8d, %r9 + movb %r9b, (%rdi) + leaq -0x70(%rbp), %rdi + movq 0x28(%rdi), %rdi + imulq $0xc, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r9 + shlq $0x2, %r9 + addq %r9, %rdi + addq %r9, %r8 + incq %r8 + movslq %r8d, %r9 + movb %r9b, 0x1(%rdi) + leaq -0x70(%rbp), %rdi + movq 0x28(%rdi), %rdi + imulq $0xc, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r9 + shlq $0x2, %r9 + addq %r9, %rdi + addq %r9, %r8 + addq $0x2, %r8 + movslq %r8d, %r9 + movb %r9b, 0x2(%rdi) + leaq -0x70(%rbp), %rdi + movq 0x28(%rdi), %rdi + imulq $0xc, %rax, %r8 + addq %r8, %rdi + movq %rdx, %r9 + shlq $0x2, %r9 + addq %r9, %rdi + addq %r9, %r8 + addq $0x3, %r8 + movslq %r8d, %r9 + movb %r9b, 0x3(%rdi) + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x3, %rdx + jl + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x2, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + jl xorq %rcx, %rcx jmp - movslq %edx, %rax - cmpq $0x3, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp xorq %rsi, %rsi jmp - jmp - movslq %esi, %rax - cmpq $0x4, %rax - jge - jmp - movslq %esi, %rax - leaq 0x1(%rax), %rsi - jmp - leaq -0x70(%rbp), %rax - movq 0x28(%rax), %rax - movslq %ecx, %rdi - imulq $0xc, %rdi, %rdi - addq %rdi, %rax - movslq %edx, %r8 - shlq $0x2, %r8 - addq %r8, %rax - movslq %esi, %r9 - addq %r9, %rax - addq %r8, %rdi - addq %r9, %rdi - movslq %edi, %r8 - movb %r8b, (%rax) - jmp - jmp + xorq %r8, %r8 + jmp + leaq -0x70(%rbp), %r9 + movq 0x28(%r9), %r9 + imulq $0xc, %rax, %rbx + addq %rbx, %r9 + movq %rdx, %r12 + shlq $0x2, %r12 + addq %r12, %r9 + addq %rdi, %r9 + movsbq (%r9), %r9 + addq %r12, %rbx + addq %rdi, %rbx + movslq %ebx, %r12 + movsbq %r12b, %rbx + cmpq %rbx, %r9 + jne + leaq 0x1(%rdi), %r8 + movslq %r8d, %rdi + cmpq $0x4, %rdi + jl + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x3, %rdx + jl + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x2, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + jl xorq %rcx, %rcx jmp - movslq %edx, %rax - cmpq $0x3, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp xorq %rsi, %rsi jmp - jmp - movslq %esi, %rax - cmpq $0x4, %rax - jge - jmp - movslq %esi, %rax - leaq 0x1(%rax), %rsi - jmp - leaq -0x70(%rbp), %rax - movq 0x28(%rax), %rax - movslq %ecx, %rdi - imulq $0xc, %rdi, %rdi - addq %rdi, %rax - movslq %edx, %r8 - shlq $0x2, %r8 + xorq %r8, %r8 + jmp + leaq -0x70(%rbp), %r9 + movq 0x28(%r9), %r9 + imulq $0xc, %rax, %rbx + addq %rbx, %r9 + movq %rdx, %r12 + shlq $0x2, %r12 + addq %r12, %r9 + addq %rdi, %r9 + movsbq (%r9), %r9 + addq %r12, %rbx + addq %rdi, %rbx + movslq %ebx, %r12 + movsbq %r12b, %rbx + cmpq %rbx, %r9 + jne + leaq 0x1(%rdi), %r8 + movslq %r8d, %rdi + cmpq $0x4, %rdi + jl + leaq 0x1(%rdx), %rsi + movslq %esi, %rdx + cmpq $0x3, %rdx + jl + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x2, %rax + jl + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq + imulq $0xc, %rcx, %rax + addq $0x6e, %rax + movq %rsi, %rcx + shlq $0x2, %rcx + addq %rcx, %rax addq %r8, %rax - movslq %esi, %r9 - addq %r9, %rax - movsbq (%rax), %rax - addq %r8, %rdi - addq %r9, %rdi - movslq %edi, %r8 - movsbq %r8b, %rdi - cmpq %rdi, %rax - je - jmp - jmp + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq imulq $0xc, %rcx, %rax addq $0x50, %rax - movq %rdx, %rcx + movq %rsi, %rcx shlq $0x2, %rcx addq %rcx, %rax + addq %r8, %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq + leaq (%rcx,%rcx,4), %rax + addq $0x3c, %rax + addq %rsi, %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq + leaq (%rcx,%rcx,4), %rax + addq $0x28, %rax addq %rsi, %rax movslq %eax, %rax movq (%rsp), %rbx - addq $0xa0, %rsp + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq + leaq 0x1c(%rcx), %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp + popq %rbp + retq + leaq 0x14(%rcx), %rax + movslq %eax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + addq $0xb0, %rsp popq %rbp retq jmp - movslq %ecx, %rax - cmpq $0x2, %rax - jge jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - xorq %rdx, %rdx jmp - xorq %rax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq - movslq %edx, %rax - cmpq $0x3, %rax - jge jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx jmp - xorq %rsi, %rsi jmp jmp - movslq %esi, %rax - cmpq $0x4, %rax - jge jmp - movslq %esi, %rax - leaq 0x1(%rax), %rsi jmp - leaq -0x70(%rbp), %rax - movq 0x28(%rax), %rax - movslq %ecx, %rdi - imulq $0xc, %rdi, %rdi - addq %rdi, %rax - movslq %edx, %r8 - shlq $0x2, %r8 - addq %r8, %rax - movslq %esi, %r9 - addq %r9, %rax - movsbq (%rax), %rax - addq %r8, %rdi - addq %r9, %rdi - movslq %edi, %r8 - movsbq %r8b, %rdi - cmpq %rdi, %rax - je jmp jmp - imulq $0xc, %rcx, %rax - addq $0x6e, %rax - movq %rdx, %rcx - shlq $0x2, %rcx - addq %rcx, %rax - addq %rsi, %rax - movslq %eax, %rax - movq (%rsp), %rbx - addq $0xa0, %rsp - popq %rbp - retq jmp + jmp + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sizeof_string_literal.aarch64.asm b/tests/snapshots/asm/sizeof_string_literal.aarch64.asm index c326b5392..905384f40 100644 --- a/tests/snapshots/asm/sizeof_string_literal.aarch64.asm +++ b/tests/snapshots/asm/sizeof_string_literal.aarch64.asm @@ -10,26 +10,19 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - b mov x0, #0xf // =15 ret - b mov x0, #0x10 // =16 ret - b mov x0, #0x11 // =17 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_string_literal.x64.asm b/tests/snapshots/asm/sizeof_string_literal.x64.asm index 03cf95935..e54d7f49d 100644 --- a/tests/snapshots/asm/sizeof_string_literal.x64.asm +++ b/tests/snapshots/asm/sizeof_string_literal.x64.asm @@ -11,26 +11,20 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - jmp movl $0xf, %eax retq - jmp movl $0x10, %eax retq - jmp movl $0x11, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/sizeof_typedef_array.aarch64.asm b/tests/snapshots/asm/sizeof_typedef_array.aarch64.asm index 52092d4a1..caa2be6fe 100644 --- a/tests/snapshots/asm/sizeof_typedef_array.aarch64.asm +++ b/tests/snapshots/asm/sizeof_typedef_array.aarch64.asm @@ -10,23 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sizeof_typedef_array.x64.asm b/tests/snapshots/asm/sizeof_typedef_array.x64.asm index ed9e655af..ff75533c4 100644 --- a/tests/snapshots/asm/sizeof_typedef_array.x64.asm +++ b/tests/snapshots/asm/sizeof_typedef_array.x64.asm @@ -11,23 +11,17 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/sizeof_with_write.aarch64.asm b/tests/snapshots/asm/sizeof_with_write.aarch64.asm index 03b08869e..7c8b2f5b4 100644 --- a/tests/snapshots/asm/sizeof_with_write.aarch64.asm +++ b/tests/snapshots/asm/sizeof_with_write.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x10 // =16 mov x0, x20 bl @@ -30,8 +29,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/sizeof_with_write.x64.asm b/tests/snapshots/asm/sizeof_with_write.x64.asm index 6b5cfa79e..8d81f0d6b 100644 --- a/tests/snapshots/asm/sizeof_with_write.x64.asm +++ b/tests/snapshots/asm/sizeof_with_write.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x10, %ebx movq %rbx, %rdi @@ -32,6 +32,6 @@ Disassembly of section .text: movslq %eax, %rax movq %rbx, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/slot_coalesce_alloca.aarch64.asm b/tests/snapshots/asm/slot_coalesce_alloca.aarch64.asm index 09efdbb38..84bb7c736 100644 --- a/tests/snapshots/asm/slot_coalesce_alloca.aarch64.asm +++ b/tests/snapshots/asm/slot_coalesce_alloca.aarch64.asm @@ -14,40 +14,32 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0xe0 sxtw x0, w0 - mov x5, #0x0 // =0 - mov x1, x5 + mov x6, #0x0 // =0 + mov x1, x6 + b + sub x3, x29, #0xc0 + lsl x4, x2, #3 + add x3, x3, x4 + add x4, x2, #0x1 + sxtw x4, w4 + mul x4, x4, x0 + str x4, [x3] + add x1, x2, #0x1 sxtw x2, w1 cmp x2, #0x18 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 + b.lt + mov x1, #0x0 // =0 b sub x2, x29, #0xc0 - sxtw x3, w1 - lsl x4, x3, #3 - add x2, x2, x4 - add x3, x3, #0x1 - sxtw x3, w3 - mul x3, x3, x0 - str x3, [x2] - b - mov x1, #0x0 // =0 + lsl x3, x0, #3 + add x2, x2, x3 + ldr x2, [x2] + add x6, x6, x2 + add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x18 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0xc0 - sxtw x2, w1 - lsl x2, x2, #3 - add x0, x0, x2 - ldr x0, [x0] - add x5, x5, x0 - b - mov x0, x5 + b.lt + mov x0, x6 add sp, sp, #0xe0 ldp x29, x30, [sp], #0x10 ret @@ -118,22 +110,19 @@ Disassembly of section .text: stur x0, [x29, #-0x70] mov x0, #0x0 // =0 stur w0, [x29, #-0x78] - ldursw x0, [x29, #-0x78] - cmp x0, #0x8 - b.ge - b - ldursw x0, [x29, #-0x78] - add x0, x0, #0x1 - stur w0, [x29, #-0x78] b ldur x0, [x29, #-0x70] ldursw x1, [x29, #-0x78] ldur x2, [x29, #-0x68] add x2, x2, x1 str x2, [x0, x1, lsl #3] - b + ldursw x0, [x29, #-0x78] + add x0, x0, #0x1 + stur w0, [x29, #-0x78] + ldursw x0, [x29, #-0x78] + cmp x0, #0x8 + b.lt ldur x0, [x29, #-0x68] - sxtw x0, w0 bl stur x0, [x29, #-0x80] ldur x0, [x29, #-0x80] @@ -147,13 +136,6 @@ Disassembly of section .text: ret mov x0, #0x0 // =0 stur w0, [x29, #-0x88] - ldursw x0, [x29, #-0x88] - cmp x0, #0x8 - b.ge - b - ldursw x0, [x29, #-0x88] - add x0, x0, #0x1 - stur w0, [x29, #-0x88] b ldur x0, [x29, #-0x70] ldursw x1, [x29, #-0x88] @@ -161,8 +143,13 @@ Disassembly of section .text: ldur x2, [x29, #-0x68] add x1, x2, x1 cmp x0, x1 - b.eq - b + b.ne + ldursw x0, [x29, #-0x88] + add x0, x0, #0x1 + stur w0, [x29, #-0x88] + ldursw x0, [x29, #-0x88] + cmp x0, #0x8 + b.lt mov x0, #0x0 // =0 ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 diff --git a/tests/snapshots/asm/slot_coalesce_alloca.x64.asm b/tests/snapshots/asm/slot_coalesce_alloca.x64.asm index 6bc55e22e..d59e44a40 100644 --- a/tests/snapshots/asm/slot_coalesce_alloca.x64.asm +++ b/tests/snapshots/asm/slot_coalesce_alloca.x64.asm @@ -15,41 +15,34 @@ Disassembly of section .text: movq %rsp, %rbp subq $0xe0, %rsp movslq %edi, %rdi - xorq %r8, %r8 - movq %r8, %rax + xorq %r9, %r9 + movq %r9, %rax + jmp + leaq -0xc0(%rbp), %rdx + movq %rcx, %rsi + shlq $0x3, %rsi + addq %rsi, %rdx + leaq 0x1(%rcx), %rsi + movslq %esi, %rsi + imulq %rdi, %rsi + movq %rsi, (%rdx) + leaq 0x1(%rcx), %rax movslq %eax, %rcx cmpq $0x18, %rcx - jge - jmp - movslq %eax, %rax - incq %rax + jl + xorq %rcx, %rcx jmp - leaq -0xc0(%rbp), %rcx - movslq %eax, %rdx - movq %rdx, %rsi + leaq -0xc0(%rbp), %rdx + movq %rax, %rsi shlq $0x3, %rsi - addq %rsi, %rcx - incq %rdx - movslq %edx, %rdx - imulq %rdi, %rdx - movq %rdx, (%rcx) - jmp - xorq %rcx, %rcx + addq %rsi, %rdx + movq (%rdx), %rdx + addq %rdx, %r9 + leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x18, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0xc0(%rbp), %rax - movslq %ecx, %rdx - shlq $0x3, %rdx - addq %rdx, %rax - movq (%rax), %rax - addq %rax, %r8 - jmp - movq %r8, %rax + jl + movq %r9, %rax addq $0xe0, %rsp popq %rbp retq @@ -119,22 +112,19 @@ Disassembly of section .text: movq %rax, -0x70(%rbp) xorq %rax, %rax movl %eax, -0x78(%rbp) - movslq -0x78(%rbp), %rax - cmpq $0x8, %rax - jge - jmp - movslq -0x78(%rbp), %rax - incq %rax - movl %eax, -0x78(%rbp) jmp movq -0x70(%rbp), %rax movslq -0x78(%rbp), %rcx movq -0x68(%rbp), %rdx addq %rcx, %rdx movq %rdx, (%rax,%rcx,8) - jmp - movq -0x68(%rbp), %rax - movslq %eax, %rdi + movslq -0x78(%rbp), %rax + incq %rax + movl %eax, -0x78(%rbp) + movslq -0x78(%rbp), %rax + cmpq $0x8, %rax + jl + movq -0x68(%rbp), %rdi callq movq %rax, -0x80(%rbp) movq -0x80(%rbp), %rax @@ -146,13 +136,6 @@ Disassembly of section .text: retq xorq %rax, %rax movl %eax, -0x88(%rbp) - movslq -0x88(%rbp), %rax - cmpq $0x8, %rax - jge - jmp - movslq -0x88(%rbp), %rax - incq %rax - movl %eax, -0x88(%rbp) jmp movq -0x70(%rbp), %rax movslq -0x88(%rbp), %rcx @@ -160,8 +143,13 @@ Disassembly of section .text: movq -0x68(%rbp), %rdx addq %rdx, %rcx cmpq %rcx, %rax - je - jmp + jne + movslq -0x88(%rbp), %rax + incq %rax + movl %eax, -0x88(%rbp) + movslq -0x88(%rbp), %rax + cmpq $0x8, %rax + jl xorq %rax, %rax addq $0x2090, %rsp # imm = 0x2090 popq %rbp @@ -171,5 +159,4 @@ Disassembly of section .text: popq %rbp retq jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/slot_coalesce_declared.aarch64.asm b/tests/snapshots/asm/slot_coalesce_declared.aarch64.asm index b961e9bc4..e8ba21117 100644 --- a/tests/snapshots/asm/slot_coalesce_declared.aarch64.asm +++ b/tests/snapshots/asm/slot_coalesce_declared.aarch64.asm @@ -79,41 +79,26 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, #0x0 // =0 mov x1, x2 - cmp x2, x0 - b.ge - b - add x2, x2, #0x1 b mov x17, #0x3 // =3 mul x3, x2, x17 add x3, x3, #0x7 add x1, x1, x3 - b + add x2, x2, #0x1 + cmp x2, x0 + b.lt mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 mov x2, #0x0 // =0 mov x1, x2 - cmp x2, x0 - b.ge - b - add x2, x2, #0x1 b mov x17, #0x3 // =3 mul x3, x2, x17 - mov x4, #0x7 // =7 - add x4, x3, x4 + add x4, x3, #0x7 add x1, x1, x4 add x4, x2, x2 add x4, x4, x2 @@ -123,10 +108,10 @@ Disassembly of section .text: mul x3, x2, x17 sub x3, x3, x3 add x1, x1, x3 - b + add x2, x2, #0x1 + cmp x2, x0 + b.lt mov x0, x1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 ret : @@ -308,8 +293,7 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x1f0 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp] str x19, [sp, #0x10] mov x20, #0x32 // =50 mov x0, x20 @@ -322,57 +306,38 @@ Disassembly of section .text: mov x1, #0xabcd // =43981 movk x1, #0x1234, lsl #16 stur x1, [x29, #-0x10] - sub x2, x29, #0x10 - ldr x3, [x2] - mov x17, #0xfeed // =65261 - eor x3, x3, x17 - str x3, [x2] + sub x1, x29, #0x10 + ldr x2, [x1] mov x17, #0xfeed // =65261 - eor x1, x1, x17 + eor x2, x2, x17 + str x2, [x1] sxtw x0, w0 - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, ldur x0, [x29, #-0x10] - cmp x0, x1 + mov x17, #0x5520 // =21792 + movk x17, #0x1234, lsl #16 + cmp x0, x17 cset x0, eq cmp x0, #0x0 - cset x20, ne - mov x6, #0x0 // =0 - mov x0, x6 - mov x1, x6 - sxtw x2, w0 - cmp x2, #0x6 - b.ge - b - sxtw x0, w0 - add x0, x0, #0x1 - b - sub x2, x29, #0x50 - sxtw x3, w0 - add x4, x3, #0x3e8 - sxtw x4, w4 - str x4, [x2, x3, lsl #3] - add x2, x0, #0x3e8 - sxtw x2, w2 - add x1, x1, x2 - b - mov x2, #0x0 // =0 - sxtw x0, w2 - cmp x0, #0x6 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x50 - sxtw x3, w2 - ldr x0, [x0, x3, lsl #3] - add x6, x6, x0 - b - sxtw x0, w20 + cset x2, ne + mov x0, #0x3e8 // =1000 + mov x1, #0x3e9 // =1001 + mov x3, #0x3ea // =1002 + mov x4, #0x3eb // =1003 + mov x5, #0x3ec // =1004 + mov x6, #0x3ed // =1005 + add x0, x0, #0x0 + add x0, x0, x1 + add x0, x0, x3 + add x0, x0, x4 + add x0, x0, x5 + add x0, x0, x6 + sxtw x1, w2 mov x20, #0x0 // =0 - cbz x0, - cmp x6, x1 + cbz x1, + mov x17, #0x177f // =6015 + cmp x0, x17 cset x0, eq cmp x0, #0x0 cset x20, ne @@ -392,26 +357,26 @@ Disassembly of section .text: str x10, [x1, #0x18] ldr x10, [sp], #0x10 mov x0, x1 - mov x21, #0x579e // =22430 sxtw x0, w20 - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, sub x0, x29, #0x90 bl - cmp x0, x21 + mov x17, #0x579e // =22430 + cmp x0, x17 cset x0, eq cmp x0, #0x0 - cset x20, ne - mov x21, #0x0 // =0 - cbz x20, + cset x2, ne + mov x1, #0x0 // =0 + cbz x2, sub x0, x29, #0x90 ldr x0, [x0] cmp x0, #0x7b cset x0, eq cmp x0, #0x0 - cset x21, ne + cset x1, ne mov x20, #0x0 // =0 - cbz x21, + cbz x1, sub x0, x29, #0x90 ldr x0, [x0, #0x18] cmp x0, #0x171 @@ -443,15 +408,15 @@ Disassembly of section .text: ldr x10, [sp], #0x10 mov x0, x1 sxtw x0, w20 - mov x20, #0x0 // =0 + mov x2, #0x0 // =0 cbz x0, sub x0, x29, #0xf8 bl cmp x0, #0x65 cset x0, eq cmp x0, #0x0 - cset x20, ne - sxtw x0, w20 + cset x2, ne + sxtw x0, w2 cmp x0, #0x0 b.ne adrp x0, @@ -459,16 +424,14 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldp x20, x21, [sp] add sp, sp, #0x1f0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] + ldp x20, x21, [sp] add sp, sp, #0x1f0 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/slot_coalesce_declared.x64.asm b/tests/snapshots/asm/slot_coalesce_declared.x64.asm index 95fd0ecb4..01303c3ca 100644 --- a/tests/snapshots/asm/slot_coalesce_declared.x64.asm +++ b/tests/snapshots/asm/slot_coalesce_declared.x64.asm @@ -23,15 +23,13 @@ Disassembly of section .text: movq 0x20(%rbp), %rcx movq %rcx, (%rax) leaq -0x20(%rbp), %rax - movq 0x20(%rbp), %rcx - xorq $0x5555, %rcx # imm = 0x5555 - movq %rcx, 0x8(%rax) + movq %rcx, %rdx + xorq $0x5555, %rdx # imm = 0x5555 + movq %rdx, 0x8(%rax) leaq -0x20(%rbp), %rax - movq 0x20(%rbp), %rcx - addq $0x9, %rcx - movq %rcx, 0x10(%rax) + leaq 0x9(%rcx), %rdx + movq %rdx, 0x10(%rax) leaq -0x20(%rbp), %rax - movq 0x20(%rbp), %rcx leaq (%rcx,%rcx,2), %rcx movq %rcx, 0x18(%rax) movq 0x10(%rbp), %rax @@ -88,38 +86,23 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rcx, %rcx movq %rcx, %rax - cmpq %rdi, %rcx - jge - jmp - incq %rcx jmp leaq (%rcx,%rcx,2), %rdx addq $0x7, %rdx addq %rdx, %rax - jmp - addq $0x10, %rsp - popq %rbp + incq %rcx + cmpq %rdi, %rcx + jl retq : - pushq %rbp - movq %rsp, %rbp - subq $0x60, %rsp xorq %rcx, %rcx movq %rcx, %rax - cmpq %rdi, %rcx - jge - jmp - incq %rcx jmp leaq (%rcx,%rcx,2), %rdx - movl $0x7, %esi - addq %rdx, %rsi + leaq 0x7(%rdx), %rsi addq %rsi, %rax leaq (%rcx,%rcx), %rsi addq %rcx, %rsi @@ -131,9 +114,9 @@ Disassembly of section .text: movq %rdx, %r10 subq %r10, %rdx addq %rdx, %rax - jmp - addq $0x60, %rsp - popq %rbp + incq %rcx + cmpq %rdi, %rcx + jl retq : @@ -352,59 +335,38 @@ Disassembly of section .text: movzbq %al, %rax movl $0x1234abcd, %ecx # imm = 0x1234ABCD movq %rcx, -0x10(%rbp) - leaq -0x10(%rbp), %rdx - movq (%rdx), %rsi - xorq $0xfeed, %rsi # imm = 0xFEED - movq %rsi, (%rdx) - xorq $0xfeed, %rcx # imm = 0xFEED + leaq -0x10(%rbp), %rcx + movq (%rcx), %rdx + xorq $0xfeed, %rdx # imm = 0xFEED + movq %rdx, (%rcx) movslq %eax, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je movq -0x10(%rbp), %rax - cmpq %rcx, %rax + cmpq $0x12345520, %rax # imm = 0x12345520 sete %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - xorq %r9, %r9 - movq %r9, %rax - movq %r9, %rcx - movslq %eax, %rdx - cmpq $0x6, %rdx - jge - jmp - movslq %eax, %rax - incq %rax - jmp - leaq -0x50(%rbp), %rdx - movslq %eax, %rsi - leaq 0x3e8(%rsi), %rdi - movslq %edi, %rdi - movq %rdi, (%rdx,%rsi,8) - leaq 0x3e8(%rax), %rdx - movslq %edx, %rdx - addq %rdx, %rcx - jmp - xorq %rdx, %rdx - movslq %edx, %rax - cmpq $0x6, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x50(%rbp), %rax - movslq %edx, %rsi - movq (%rax,%rsi,8), %rax - addq %rax, %r9 - jmp - movslq %ebx, %rax + setne %dl + movzbq %dl, %rdx + movl $0x3e8, %eax # imm = 0x3E8 + movl $0x3e9, %ecx # imm = 0x3E9 + movl $0x3ea, %esi # imm = 0x3EA + movl $0x3eb, %edi # imm = 0x3EB + movl $0x3ec, %r8d # imm = 0x3EC + movl $0x3ed, %r9d # imm = 0x3ED + addq $0x0, %rax + addq %rcx, %rax + addq %rsi, %rax + addq %rdi, %rax + addq %r8, %rax + addq %r9, %rax + movslq %edx, %rcx xorq %rbx, %rbx - testq %rax, %rax + testq %rcx, %rcx je - cmpq %rcx, %r9 + cmpq $0x177f, %rax # imm = 0x177F sete %al movzbq %al, %rax testq %rax, %rax @@ -426,9 +388,8 @@ Disassembly of section .text: movq %rdx, 0x18(%rcx) popq %rdx movq %rcx, %rax - movl $0x579e, %r12d # imm = 0x579E movslq %ebx, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je leaq -0x90(%rbp), %rdi @@ -444,14 +405,14 @@ Disassembly of section .text: movq %r11, 0x18(%rsp) callq addq $0x20, %rsp - cmpq %r12, %rax + cmpq $0x579e, %rax # imm = 0x579E sete %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - xorq %r12, %r12 - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + xorq %rcx, %rcx + testq %rdx, %rdx je leaq -0x90(%rbp), %rax movq (%rax), %rax @@ -459,10 +420,10 @@ Disassembly of section .text: sete %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 + setne %cl + movzbq %cl, %rcx xorq %rbx, %rbx - testq %r12, %r12 + testq %rcx, %rcx je leaq -0x90(%rbp), %rax movq 0x18(%rax), %rax @@ -497,7 +458,7 @@ Disassembly of section .text: popq %rdx movq %rcx, %rax movslq %ebx, %rax - xorq %rbx, %rbx + xorq %rdx, %rdx testq %rax, %rax je leaq -0xf8(%rbp), %rdi @@ -525,9 +486,9 @@ Disassembly of section .text: sete %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movslq %ebx, %rax + setne %dl + movzbq %dl, %rdx + movslq %edx, %rax testq %rax, %rax jne leaq , %rdi @@ -552,4 +513,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/slot_coalesce_disjoint_temps.aarch64.asm b/tests/snapshots/asm/slot_coalesce_disjoint_temps.aarch64.asm index c647e3e12..a4c9472c8 100644 --- a/tests/snapshots/asm/slot_coalesce_disjoint_temps.aarch64.asm +++ b/tests/snapshots/asm/slot_coalesce_disjoint_temps.aarch64.asm @@ -10,124 +10,105 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 mov x1, #0x0 // =0 mov x0, x1 mov x2, x1 - sxtw x3, w1 - cmp x3, #0x40 - b.ge b - sxtw x1, w1 - add x1, x1, #0x1 - b - sxtw x3, w1 mov x17, #0x1 // =1 - and x3, x3, x17 - cbz x3, - b - sxtw x1, w2 - sxtw x0, w0 - cmp x1, x0 - b.ne - b + and x4, x3, x17 + cbz x4, mov x17, #0x3 // =3 - mul x3, x1, x17 - sxtw x4, w3 - b - add x3, x1, #0x7 - sxtw x4, w3 - sxtw x3, w4 - cmp x3, #0xa - cset x5, gt - cbz x5, - sxtw x3, w4 - cmp x3, #0x64 - cset x5, lt - cbz x5, - sub x3, x4, #0x1 - sxtw x5, w3 - b - add x3, x4, #0x1 - sxtw x5, w3 - sxtw x3, w5 - asr x6, x3, #63 - lsr x6, x6, #63 - add x3, x3, x6 + mul x4, x1, x17 + sxtw x5, w4 + sxtw x4, w5 + cmp x4, #0xa + cset x7, gt + cbz x7, + cmp x4, #0x64 + cset x7, lt + cbz x7, + sub x4, x5, #0x1 + sxtw x6, w4 + sxtw x8, w6 + asr x4, x8, #63 + lsr x4, x4, #63 + add x7, x8, x4 mov x17, #0x1 // =1 - and x3, x3, x17 - sub x3, x3, x6 - cmp x3, #0x0 - cset x6, eq - cbnz x6, - sxtw x3, w5 - cmp x3, #0x32 - cset x6, gt - cbz x6, - lsl x3, x5, #1 - sxtw x6, w3 - b - sxtw x6, w5 - add x3, x6, x4 - add x3, x3, x5 - add x2, x2, x3 - sxtw x3, w1 + and x7, x7, x17 + sub x4, x7, x4 + cmp x4, #0x0 + cset x7, eq + cbnz x7, + cmp x8, #0x32 + cset x7, gt + cbz x7, + lsl x4, x6, #1 + sxtw x8, w4 + add x4, x8, x5 + add x4, x4, x6 + add x2, x2, x4 mov x17, #0x1 // =1 - and x3, x3, x17 - cbz x3, + and x4, x3, x17 + cbz x4, mov x17, #0x3 // =3 - mul x3, x1, x17 - sxtw x4, w3 - sxtw x3, w4 - cmp x3, #0xa - cset x5, gt - cbz x5, + mul x4, x1, x17 + sxtw x5, w4 + sxtw x4, w5 + cmp x4, #0xa + cset x7, gt + cbz x7, + cmp x4, #0x64 + cset x7, lt + cbz x7, + sub x4, x5, #0x1 + sxtw x6, w4 + sxtw x8, w6 + asr x4, x8, #63 + lsr x4, x4, #63 + add x7, x8, x4 + mov x17, #0x1 // =1 + and x7, x7, x17 + sub x4, x7, x4 + cmp x4, #0x0 + cset x7, eq + cbnz x7, + cmp x8, #0x32 + cset x7, gt + cbz x7, + lsl x4, x6, #1 + sxtw x8, w4 + add x4, x8, x5 + add x4, x4, x6 + add x0, x0, x4 b - add x3, x1, #0x7 - sxtw x4, w3 b - sxtw x3, w4 - cmp x3, #0x64 - cset x5, lt - cbz x5, - sub x3, x4, #0x1 - sxtw x5, w3 - sxtw x3, w5 - asr x6, x3, #63 - lsr x6, x6, #63 - add x3, x3, x6 - mov x17, #0x1 // =1 - and x3, x3, x17 - sub x3, x3, x6 - cmp x3, #0x0 - cset x6, eq - cbnz x6, b - add x3, x4, #0x1 - sxtw x5, w3 + add x4, x5, #0x1 + sxtw x6, w4 b - sxtw x3, w5 - cmp x3, #0x32 - cset x6, gt - cbz x6, - lsl x3, x5, #1 - sxtw x6, w3 - add x3, x6, x4 - add x3, x3, x5 - add x0, x0, x3 b - sxtw x6, w5 + add x4, x1, #0x7 + sxtw x5, w4 b - mov x1, #0x0 // =0 b - mov x1, #0x1 // =1 - mov x0, x1 - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret b + add x4, x5, #0x1 + sxtw x6, w4 b b + add x4, x1, #0x7 + sxtw x5, w4 + b + add x1, x3, #0x1 + sxtw x3, w1 + cmp x3, #0x40 + b.lt + sxtw x1, w2 + sxtw x0, w0 + cmp x1, x0 + b.ne + mov x1, #0x0 // =0 + mov x0, x1 + ret + mov x1, #0x1 // =1 b diff --git a/tests/snapshots/asm/slot_coalesce_disjoint_temps.x64.asm b/tests/snapshots/asm/slot_coalesce_disjoint_temps.x64.asm index 6ca748820..08af3ec8d 100644 --- a/tests/snapshots/asm/slot_coalesce_disjoint_temps.x64.asm +++ b/tests/snapshots/asm/slot_coalesce_disjoint_temps.x64.asm @@ -13,138 +13,134 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp + subq $0x10, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) xorq %rcx, %rcx movq %rcx, %rax movq %rcx, %rdx - movslq %ecx, %rsi - cmpq $0x40, %rsi - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - movslq %ecx, %rsi - andq $0x1, %rsi - testq %rsi, %rsi + movq %rsi, %rdi + andq $0x1, %rdi + testq %rdi, %rdi je - jmp - movslq %edx, %rcx - movslq %eax, %rax - cmpq %rax, %rcx - jne - jmp - leaq (%rcx,%rcx,2), %rsi - movslq %esi, %rdi - jmp - leaq 0x7(%rcx), %rsi - movslq %esi, %rdi - movslq %edi, %rsi - cmpq $0xa, %rsi - setg %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + leaq (%rcx,%rcx,2), %rdi + movslq %edi, %r8 + movslq %r8d, %rdi + cmpq $0xa, %rdi + setg %bl + movzbq %bl, %rbx + testq %rbx, %rbx je - movslq %edi, %rsi - cmpq $0x64, %rsi - setl %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + cmpq $0x64, %rdi + setl %bl + movzbq %bl, %rbx + testq %rbx, %rbx je - leaq -0x1(%rdi), %rsi - movslq %esi, %r8 - jmp - leaq 0x1(%rdi), %rsi - movslq %esi, %r8 - movslq %r8d, %rsi - movq %rsi, %r9 - sarq $0x3f, %r9 - shrq $0x3f, %r9 - addq %r9, %rsi - andq $0x1, %rsi - subq %r9, %rsi - testq %rsi, %rsi - sete %r9b - movzbq %r9b, %r9 - testq %r9, %r9 + leaq -0x1(%r8), %rdi + movslq %edi, %r9 + movslq %r9d, %r12 + movq %r12, %rdi + sarq $0x3f, %rdi + shrq $0x3f, %rdi + leaq (%r12,%rdi), %rbx + andq $0x1, %rbx + movq %rdi, %r10 + movq %rbx, %rdi + subq %r10, %rdi + testq %rdi, %rdi + sete %bl + movzbq %bl, %rbx + testq %rbx, %rbx jne - movslq %r8d, %rsi - cmpq $0x32, %rsi - setg %r9b - movzbq %r9b, %r9 - testq %r9, %r9 + cmpq $0x32, %r12 + setg %bl + movzbq %bl, %rbx + testq %rbx, %rbx je - movq %r8, %rsi - shlq $0x1, %rsi - movslq %esi, %r9 - jmp - movslq %r8d, %r9 - leaq (%r9,%rdi), %rsi - addq %r8, %rsi - addq %rsi, %rdx - movslq %ecx, %rsi - andq $0x1, %rsi - testq %rsi, %rsi + movq %r9, %rdi + shlq $0x1, %rdi + movslq %edi, %r12 + leaq (%r12,%r8), %rdi + addq %r9, %rdi + addq %rdi, %rdx + movq %rsi, %rdi + andq $0x1, %rdi + testq %rdi, %rdi je - leaq (%rcx,%rcx,2), %rsi - movslq %esi, %rdi - movslq %edi, %rsi - cmpq $0xa, %rsi - setg %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + leaq (%rcx,%rcx,2), %rdi + movslq %edi, %r8 + movslq %r8d, %rdi + cmpq $0xa, %rdi + setg %bl + movzbq %bl, %rbx + testq %rbx, %rbx je - jmp - leaq 0x7(%rcx), %rsi - movslq %esi, %rdi - jmp - movslq %edi, %rsi - cmpq $0x64, %rsi - setl %r8b - movzbq %r8b, %r8 - testq %r8, %r8 + cmpq $0x64, %rdi + setl %bl + movzbq %bl, %rbx + testq %rbx, %rbx je - leaq -0x1(%rdi), %rsi - movslq %esi, %r8 - movslq %r8d, %rsi - movq %rsi, %r9 - sarq $0x3f, %r9 - shrq $0x3f, %r9 - addq %r9, %rsi - andq $0x1, %rsi - subq %r9, %rsi - testq %rsi, %rsi - sete %r9b - movzbq %r9b, %r9 - testq %r9, %r9 + leaq -0x1(%r8), %rdi + movslq %edi, %r9 + movslq %r9d, %r12 + movq %r12, %rdi + sarq $0x3f, %rdi + shrq $0x3f, %rdi + leaq (%r12,%rdi), %rbx + andq $0x1, %rbx + movq %rdi, %r10 + movq %rbx, %rdi + subq %r10, %rdi + testq %rdi, %rdi + sete %bl + movzbq %bl, %rbx + testq %rbx, %rbx jne + cmpq $0x32, %r12 + setg %bl + movzbq %bl, %rbx + testq %rbx, %rbx + je + movq %r9, %rdi + shlq $0x1, %rdi + movslq %edi, %r12 + leaq (%r12,%r8), %rdi + addq %r9, %rdi + addq %rdi, %rax jmp - leaq 0x1(%rdi), %rsi - movslq %esi, %r8 jmp - movslq %r8d, %rsi - cmpq $0x32, %rsi - setg %r9b - movzbq %r9b, %r9 - testq %r9, %r9 - je - movq %r8, %rsi - shlq $0x1, %rsi - movslq %esi, %r9 - leaq (%r9,%rdi), %rsi - addq %r8, %rsi - addq %rsi, %rax jmp - movslq %r8d, %r9 + leaq 0x1(%r8), %rdi + movslq %edi, %r9 jmp - xorq %rcx, %rcx jmp - movl $0x1, %ecx - movq %rcx, %rax - addq $0x90, %rsp - popq %rbp - retq + leaq 0x7(%rcx), %rdi + movslq %edi, %r8 + jmp jmp jmp + leaq 0x1(%r8), %rdi + movslq %edi, %r9 jmp jmp + leaq 0x7(%rcx), %rdi + movslq %edi, %r8 + jmp + leaq 0x1(%rsi), %rcx + movslq %ecx, %rsi + cmpq $0x40, %rsi + jl + movslq %edx, %rcx + movslq %eax, %rax + cmpq %rax, %rcx + jne + xorq %rcx, %rcx + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq %rcx, %rax + addq $0x10, %rsp + popq %rbp + retq + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/snprintf_truncation_c99.aarch64.asm b/tests/snapshots/asm/snprintf_truncation_c99.aarch64.asm index 6a76506f0..ffebc1a91 100644 --- a/tests/snapshots/asm/snprintf_truncation_c99.aarch64.asm +++ b/tests/snapshots/asm/snprintf_truncation_c99.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x20 mov x16, x0 @@ -57,17 +56,15 @@ Disassembly of section .text: bl sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x8 mov x1, #0x41 // =65 mov x2, #0x8 // =8 @@ -83,9 +80,8 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 adrp x1, @@ -95,9 +91,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x0 // =0 adrp x2, @@ -110,9 +105,8 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 mov x1, #0x41 // =65 @@ -128,9 +122,8 @@ Disassembly of section .text: cmp x0, #0x6 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 adrp x1, @@ -140,9 +133,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret sub x0, x29, #0x8 mov x1, #0x8 // =8 @@ -163,13 +155,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 ret b diff --git a/tests/snapshots/asm/socket_headers_abi.aarch64.asm b/tests/snapshots/asm/socket_headers_abi.aarch64.asm index 2b942ab83..db70e1bfb 100644 --- a/tests/snapshots/asm/socket_headers_abi.aarch64.asm +++ b/tests/snapshots/asm/socket_headers_abi.aarch64.asm @@ -13,61 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x60 - b - mov x0, #0x1 // =1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x4 // =4 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x5 // =5 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x7 // =7 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x8 // =8 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x9 // =9 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xa // =10 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xb // =11 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret mov x2, #0x1 // =1 mov x2, #0x0 // =0 cbnz x2, @@ -120,3 +65,47 @@ Disassembly of section .text: ret b b + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4 // =4 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x5 // =5 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xa // =10 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/socket_headers_abi.x64.asm b/tests/snapshots/asm/socket_headers_abi.x64.asm index 931640cce..8567f7873 100644 --- a/tests/snapshots/asm/socket_headers_abi.x64.asm +++ b/tests/snapshots/asm/socket_headers_abi.x64.asm @@ -14,61 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x60, %rsp - jmp - movl $0x1, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x4, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x5, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x7, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x8, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0x9, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0xa, %eax - addq $0x60, %rsp - popq %rbp - retq - jmp - movl $0xb, %eax - addq $0x60, %rsp - popq %rbp - retq movl $0x1, %edx xorq %rdx, %rdx testq %rdx, %rdx @@ -126,4 +71,49 @@ Disassembly of section .text: retq jmp jmp + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x4, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x5, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x6, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x7, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x8, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0x9, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0xa, %eax + addq $0x60, %rsp + popq %rbp + retq + movl $0xb, %eax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.aarch64.asm b/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.aarch64.asm index ba306bc1c..bfc652349 100644 --- a/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.aarch64.asm +++ b/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.aarch64.asm @@ -22,17 +22,12 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] - str x26, [sp, #0x30] - str x27, [sp, #0x38] + stp x20, x21, [sp, #-0x50]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 add x20, x0, #0x1 add x21, x0, #0x2 add x22, x0, #0x3 @@ -67,16 +62,11 @@ Disassembly of section .text: add x0, x0, x25 add x0, x0, x26 add x0, x0, x27 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x26, [sp, #0x30] - ldr x27, [sp, #0x38] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x50 ret
: diff --git a/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.x64.asm b/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.x64.asm index dbd6d96e6..eb0e4df4f 100644 --- a/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.x64.asm +++ b/tests/snapshots/asm/spill_slot_reuse_disjoint_calls.x64.asm @@ -22,7 +22,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0xf0, %rsp + subq $0x50, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -74,7 +74,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xf0, %rsp + addq $0x50, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/sqlite_min.aarch64.asm b/tests/snapshots/asm/sqlite_min.aarch64.asm index daa7312b1..f39e49987 100644 --- a/tests/snapshots/asm/sqlite_min.aarch64.asm +++ b/tests/snapshots/asm/sqlite_min.aarch64.asm @@ -10,15 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x110 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x120]! + stp x22, x23, [sp, #0x10] str x24, [sp, #0x20] str x19, [sp, #0x30] + stp x29, x30, [sp, #0x110] + add x29, sp, #0x110 adrp x0, add x0, x0, ldr x1, [x0] @@ -30,69 +27,47 @@ Disassembly of section .text: add x0, x0, mov x2, #0x42 // =66 mov x3, #0x1a4 // =420 - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x1, x2 + mov x2, x3 blr x9 - add sp, sp, #0x30 sxtw x24, w0 cmp x24, #0x0 b.ge mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x110] ldr x19, [sp, #0x30] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x120 ret mov x1, #0x400 // =1024 - str x1, [sp, #-0x10]! - str x24, [sp, #-0x10]! mov x9, x23 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x24 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x110] ldr x19, [sp, #0x30] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x120 ret sub x1, x29, #0xb8 - str x1, [sp, #-0x10]! - str x24, [sp, #-0x10]! mov x9, x22 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x24 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x110] ldr x19, [sp, #0x30] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x120 ret mov x1, #0x2 // =2 mov x2, #0x1 // =1 @@ -103,29 +78,21 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x110] ldr x19, [sp, #0x30] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x120 ret - str x24, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] + mov x0, x24 blr x9 - add sp, sp, #0x10 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] + ldp x29, x30, [sp, #0x110] ldr x19, [sp, #0x30] - add sp, sp, #0x110 - ldp x29, x30, [sp], #0x10 + ldr x24, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x120 ret <__c5_sys_open>: @@ -133,33 +100,29 @@ Disassembly of section .text: <__c5_sys_close>: str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x10 ret <__c5_sys_ftruncate>: str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x20 ret @@ -169,33 +132,29 @@ Disassembly of section .text: <__c5_sys_stat>: str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x20 ret <__c5_sys_fstat>: str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x20 ret diff --git a/tests/snapshots/asm/sroa_const_index_local_array.aarch64.asm b/tests/snapshots/asm/sroa_const_index_local_array.aarch64.asm new file mode 100644 index 000000000..5f99db340 --- /dev/null +++ b/tests/snapshots/asm/sroa_const_index_local_array.aarch64.asm @@ -0,0 +1,98 @@ + +sroa_const_index_local_array.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x9, x1 + add x1, x0, #0x0 + ldr x2, [x1] + ldr x3, [x0, #0x8] + ldr x4, [x0, #0x10] + ldr x5, [x0, #0x18] + ldr x6, [x0, #0x20] + ldr x7, [x0, #0x28] + ldr x8, [x0, #0x30] + ldr x1, [x0, #0x38] + b + lsl x0, x1, #1 + add x0, x8, x0 + lsl x8, x8, #1 + add x8, x7, x8 + lsl x7, x7, #1 + add x7, x6, x7 + lsl x6, x6, #1 + add x6, x5, x6 + lsl x5, x5, #1 + add x5, x4, x5 + lsl x4, x4, #1 + add x4, x3, x4 + lsl x3, x3, #1 + add x3, x2, x3 + lsl x2, x2, #1 + eor x2, x1, x2 + mov x1, x0 + sxtw x0, w9 + sub x9, x0, #0x1 + cmp x0, #0x0 + b.gt + add x0, x2, #0x0 + add x0, x0, x3 + add x0, x0, x4 + add x0, x0, x5 + add x0, x0, x6 + add x0, x0, x7 + add x0, x0, x8 + add x0, x0, x1 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x60 + sub x0, x29, #0x40 + add x0, x0, #0x0 + mov x1, #0x7 // =7 + str x1, [x0] + sub x0, x29, #0x40 + mov x1, #0x1118 // =4376 + str x1, [x0, #0x8] + sub x0, x29, #0x40 + mov x1, #0x2229 // =8745 + str x1, [x0, #0x10] + sub x0, x29, #0x40 + mov x1, #0x333a // =13114 + str x1, [x0, #0x18] + sub x0, x29, #0x40 + mov x1, #0x444b // =17483 + str x1, [x0, #0x20] + sub x0, x29, #0x40 + mov x1, #0x555c // =21852 + str x1, [x0, #0x28] + sub x0, x29, #0x40 + mov x1, #0x666d // =26221 + str x1, [x0, #0x30] + sub x0, x29, #0x40 + mov x1, #0x777e // =30590 + str x1, [x0, #0x38] + sub x0, x29, #0x40 + mov x1, #0x5 // =5 + bl + mov x17, #0xbf84 // =49028 + movk x17, #0x14e, lsl #16 + cmp x0, x17 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/sroa_const_index_local_array.x64.asm b/tests/snapshots/asm/sroa_const_index_local_array.x64.asm new file mode 100644 index 000000000..f06d6300f --- /dev/null +++ b/tests/snapshots/asm/sroa_const_index_local_array.x64.asm @@ -0,0 +1,113 @@ + +sroa_const_index_local_array.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %rsi, %r13 + leaq (%rdi), %rax + movq (%rax), %rcx + movq 0x8(%rdi), %rdx + movq 0x10(%rdi), %rsi + movq 0x18(%rdi), %r8 + movq 0x20(%rdi), %r9 + movq 0x28(%rdi), %rbx + movq 0x30(%rdi), %r12 + movq 0x38(%rdi), %rdi + jmp + movq %rdi, %rax + shlq $0x1, %rax + addq %r12, %rax + shlq $0x1, %r12 + addq %rbx, %r12 + shlq $0x1, %rbx + addq %r9, %rbx + shlq $0x1, %r9 + addq %r8, %r9 + shlq $0x1, %r8 + addq %rsi, %r8 + shlq $0x1, %rsi + addq %rdx, %rsi + shlq $0x1, %rdx + addq %rcx, %rdx + shlq $0x1, %rcx + xorq %rdi, %rcx + movq %rax, %rdi + movslq %r13d, %rax + leaq -0x1(%rax), %r13 + testq %rax, %rax + jg + leaq (%rcx), %rax + addq %rdx, %rax + addq %rsi, %rax + addq %r8, %rax + addq %r9, %rax + addq %rbx, %rax + addq %r12, %rax + addq %rdi, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + addq $0x20, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x60, %rsp + leaq -0x40(%rbp), %rax + addq $0x0, %rax + movl $0x7, %ecx + movq %rcx, (%rax) + leaq -0x40(%rbp), %rax + movl $0x1118, %ecx # imm = 0x1118 + movq %rcx, 0x8(%rax) + leaq -0x40(%rbp), %rax + movl $0x2229, %ecx # imm = 0x2229 + movq %rcx, 0x10(%rax) + leaq -0x40(%rbp), %rax + movl $0x333a, %ecx # imm = 0x333A + movq %rcx, 0x18(%rax) + leaq -0x40(%rbp), %rax + movl $0x444b, %ecx # imm = 0x444B + movq %rcx, 0x20(%rax) + leaq -0x40(%rbp), %rax + movl $0x555c, %ecx # imm = 0x555C + movq %rcx, 0x28(%rax) + leaq -0x40(%rbp), %rax + movl $0x666d, %ecx # imm = 0x666D + movq %rcx, 0x30(%rax) + leaq -0x40(%rbp), %rax + movl $0x777e, %ecx # imm = 0x777E + movq %rcx, 0x38(%rax) + leaq -0x40(%rbp), %rdi + movl $0x5, %esi + callq + cmpq $0x14ebf84, %rax # imm = 0x14EBF84 + je + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sroa_runtime_index_stays_memory.aarch64.asm b/tests/snapshots/asm/sroa_runtime_index_stays_memory.aarch64.asm new file mode 100644 index 000000000..177e3d8e4 --- /dev/null +++ b/tests/snapshots/asm/sroa_runtime_index_stays_memory.aarch64.asm @@ -0,0 +1,123 @@ + +sroa_runtime_index_stays_memory.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x50 + sxtw x1, w1 + sub x2, x29, #0x40 + add x2, x2, #0x0 + add x3, x0, #0x0 + ldr x3, [x3] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2] + sub x2, x29, #0x40 + ldr x3, [x0, #0x8] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x8] + sub x2, x29, #0x40 + ldr x3, [x0, #0x10] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x10] + sub x2, x29, #0x40 + ldr x3, [x0, #0x18] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x18] + sub x2, x29, #0x40 + ldr x3, [x0, #0x20] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x20] + sub x2, x29, #0x40 + ldr x3, [x0, #0x28] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x28] + sub x2, x29, #0x40 + ldr x3, [x0, #0x30] + mov x17, #0x3 // =3 + mul x3, x3, x17 + add x3, x3, #0x1 + str x3, [x2, #0x30] + sub x2, x29, #0x40 + ldr x0, [x0, #0x38] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x1 + str x0, [x2, #0x38] + sub x0, x29, #0x40 + mov x17, #0x7 // =7 + and x2, x1, x17 + ldr x0, [x0, x2, lsl #3] + sub x2, x29, #0x40 + add x1, x1, #0x5 + sxtw x1, w1 + mov x17, #0x7 // =7 + and x1, x1, x17 + ldr x1, [x2, x1, lsl #3] + add x0, x0, x1 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x60 + sub x0, x29, #0x40 + mov x1, #0x0 // =0 + add x0, x0, #0x0 + str x1, [x0] + sub x0, x29, #0x40 + mov x1, #0x1 // =1 + str x1, [x0, #0x8] + sub x0, x29, #0x40 + mov x1, #0x2 // =2 + str x1, [x0, #0x10] + sub x0, x29, #0x40 + mov x1, #0x3 // =3 + str x1, [x0, #0x18] + sub x0, x29, #0x40 + mov x1, #0x4 // =4 + str x1, [x0, #0x20] + sub x0, x29, #0x40 + mov x1, #0x5 // =5 + str x1, [x0, #0x28] + sub x0, x29, #0x40 + mov x1, #0x6 // =6 + str x1, [x0, #0x30] + sub x0, x29, #0x40 + mov x1, #0x7 // =7 + str x1, [x0, #0x38] + sub x0, x29, #0x40 + mov x1, #0xa // =10 + bl + cmp x0, #0x1d + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/sroa_runtime_index_stays_memory.x64.asm b/tests/snapshots/asm/sroa_runtime_index_stays_memory.x64.asm new file mode 100644 index 000000000..d38074507 --- /dev/null +++ b/tests/snapshots/asm/sroa_runtime_index_stays_memory.x64.asm @@ -0,0 +1,116 @@ + +sroa_runtime_index_stays_memory.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x50, %rsp + movslq %esi, %rsi + leaq -0x40(%rbp), %rax + addq $0x0, %rax + leaq (%rdi), %rcx + movq (%rcx), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, (%rax) + leaq -0x40(%rbp), %rax + movq 0x8(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x8(%rax) + leaq -0x40(%rbp), %rax + movq 0x10(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x10(%rax) + leaq -0x40(%rbp), %rax + movq 0x18(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x18(%rax) + leaq -0x40(%rbp), %rax + movq 0x20(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x20(%rax) + leaq -0x40(%rbp), %rax + movq 0x28(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x28(%rax) + leaq -0x40(%rbp), %rax + movq 0x30(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x30(%rax) + leaq -0x40(%rbp), %rax + movq 0x38(%rdi), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movq %rcx, 0x38(%rax) + leaq -0x40(%rbp), %rax + movq %rsi, %rcx + andq $0x7, %rcx + movq (%rax,%rcx,8), %rax + leaq -0x40(%rbp), %rcx + leaq 0x5(%rsi), %rdx + movslq %edx, %rdx + andq $0x7, %rdx + movq (%rcx,%rdx,8), %rcx + addq %rcx, %rax + addq $0x50, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x60, %rsp + leaq -0x40(%rbp), %rax + xorq %rcx, %rcx + addq $0x0, %rax + movq %rcx, (%rax) + leaq -0x40(%rbp), %rax + movl $0x1, %ecx + movq %rcx, 0x8(%rax) + leaq -0x40(%rbp), %rax + movl $0x2, %ecx + movq %rcx, 0x10(%rax) + leaq -0x40(%rbp), %rax + movl $0x3, %ecx + movq %rcx, 0x18(%rax) + leaq -0x40(%rbp), %rax + movl $0x4, %ecx + movq %rcx, 0x20(%rax) + leaq -0x40(%rbp), %rax + movl $0x5, %ecx + movq %rcx, 0x28(%rax) + leaq -0x40(%rbp), %rax + movl $0x6, %ecx + movq %rcx, 0x30(%rax) + leaq -0x40(%rbp), %rax + movl $0x7, %ecx + movq %rcx, 0x38(%rax) + leaq -0x40(%rbp), %rdi + movl $0xa, %esi + callq + cmpq $0x1d, %rax + je + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/ssa_bail_fixup_rollback.aarch64.asm b/tests/snapshots/asm/ssa_bail_fixup_rollback.aarch64.asm index 190ac2cbe..058257dc7 100644 --- a/tests/snapshots/asm/ssa_bail_fixup_rollback.aarch64.asm +++ b/tests/snapshots/asm/ssa_bail_fixup_rollback.aarch64.asm @@ -33,108 +33,105 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x50 mov x5, #0x0 // =0 - sxtw x4, w5 - cmp x4, #0x4 - b.ge - b - sxtw x4, w5 - add x5, x4, #0x1 b - sub x4, x29, #0x40 + sub x6, x29, #0x40 mov x17, #0x5 // =5 - mul x6, x5, x17 - sxtw x6, w6 - lsl x7, x5, #2 + mul x7, x5, x17 sxtw x7, w7 - add x7, x3, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0x1 - sxtw x6, w6 - lsl x7, x5, #2 + lsl x8, x5, #2 + sxtw x8, w8 + add x8, x3, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0x1 sxtw x7, w7 - add x7, x2, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0x6 - sxtw x6, w6 - lsl x7, x5, #2 + lsl x8, x5, #2 + sxtw x8, w8 + add x8, x2, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0x6 sxtw x7, w7 - add x7, x1, x7 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - sub x4, x29, #0x40 - add x6, x5, #0xb - sxtw x6, w6 - add x7, x2, #0x10 lsl x8, x5, #2 sxtw x8, w8 - add x7, x7, x8 - ldrb w8, [x7, #0x3] - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x2] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w9, [x7, #0x1] - orr x8, x8, x9 - mov w8, w8 - lsl x8, x8, #8 - mov w8, w8 - ldrb w7, [x7] - orr x7, x8, x7 - str w7, [x4, x6, lsl #2] - b + add x8, x1, x8 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + sub x6, x29, #0x40 + add x7, x5, #0xb + sxtw x7, w7 + add x8, x2, #0x10 + lsl x9, x5, #2 + sxtw x9, w9 + add x8, x8, x9 + ldrb w9, [x8, #0x3] + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x2] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w10, [x8, #0x1] + orr x9, x9, x10 + mov w9, w9 + lsl x9, x9, #8 + mov w9, w9 + ldrb w8, [x8] + orr x8, x9, x8 + str w8, [x6, x7, lsl #2] + add x5, x4, #0x1 + sxtw x4, w5 + cmp x4, #0x4 + b.lt mov x1, #0x0 // =0 sub x2, x29, #0x40 ldr w2, [x2] @@ -156,13 +153,10 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0xb0]! + stp x22, x23, [sp, #0x10] + stp x29, x30, [sp, #0xa0] + add x29, sp, #0xa0 mov x21, x0 mov x20, x4 mov x23, x2 @@ -170,44 +164,86 @@ Disassembly of section .text: cmp x23, #0x0 b.ne mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xb0 ret + sub x0, x29, #0x10 + add x0, x0, #0x0 mov x1, #0x0 // =0 - mov w0, w1 - cmp x0, #0x10 - b.hs - b - mov w0, w1 - add x1, x0, #0x1 - b + strb w1, [x0] sub x0, x29, #0x10 - mov w2, w1 - add x0, x0, x2 - mov x2, #0x0 // =0 - strb w2, [x0] - b mov x1, #0x0 // =0 - mov w0, w1 - cmp x0, #0x8 - b.hs - b - mov w0, w1 - add x1, x0, #0x1 - b + strb w1, [x0, #0x1] sub x0, x29, #0x10 - mov w2, w1 - add x0, x0, x2 - add x2, x3, x2 - ldrb w2, [x2] - strb w2, [x0] + mov x1, #0x0 // =0 + strb w1, [x0, #0x2] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x3] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x4] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x5] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x6] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x7] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x8] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0x9] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xa] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xb] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xc] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xd] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xe] + sub x0, x29, #0x10 + mov x1, #0x0 // =0 + strb w1, [x0, #0xf] + sub x0, x29, #0x10 + add x0, x0, #0x0 + add x1, x3, #0x0 + ldrb w1, [x1] + strb w1, [x0] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x1] + strb w1, [x0, #0x1] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x2] + strb w1, [x0, #0x2] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x3] + strb w1, [x0, #0x3] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x4] + strb w1, [x0, #0x4] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x5] + strb w1, [x0, #0x5] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x6] + strb w1, [x0, #0x6] + sub x0, x29, #0x10 + ldrb w1, [x3, #0x7] + strb w1, [x0, #0x7] b - cmp x23, #0x40 - b.lo sub x0, x29, #0x50 sub x1, x29, #0x10 adrp x3, @@ -216,34 +252,12 @@ Disassembly of section .text: bl mov x1, #0x0 // =0 b - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 - ret - mov w0, w1 - cmp x0, #0x40 - b.hs - b - mov w0, w1 - add x1, x0, #0x1 - b mov w0, w1 add x0, x21, x0 cbz x22, - b - sub x23, x23, #0x40 - add x21, x21, #0x40 - cbz x22, - b mov w2, w1 add x2, x22, x2 ldrb w3, [x2] - b - mov x3, #0x0 // =0 sub x2, x29, #0x50 mov w4, w1 add x2, x2, x4 @@ -251,9 +265,25 @@ Disassembly of section .text: eor x2, x3, x2 strb w2, [x0] b - add x22, x22, #0x40 + mov x3, #0x0 // =0 b + mov w0, w1 + add x1, x0, #0x1 + mov w0, w1 + cmp x0, #0x40 + b.lo + sub x23, x23, #0x40 + add x21, x21, #0x40 + cbz x22, + add x22, x22, #0x40 b + cmp x23, #0x40 + b.hs + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0xa0] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0xb0 + ret
: stp x29, x30, [sp, #-0x10]! @@ -267,20 +297,16 @@ Disassembly of section .text: str x10, [x0] ldr x10, [sp], #0x10 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x20 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x68 - sxtw x2, w1 - add x0, x0, x2 + sub x2, x29, #0x68 + add x2, x2, x0 mov x17, #0xff // =255 - and x2, x2, x17 - strb w2, [x0] - b + and x3, x0, x17 + strb w3, [x2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x20 + b.lt sub x0, x29, #0x40 mov x1, #0x0 // =0 mov x2, #0x40 // =64 @@ -295,9 +321,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0xa0 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/ssa_bail_fixup_rollback.x64.asm b/tests/snapshots/asm/ssa_bail_fixup_rollback.x64.asm index d6e6462c7..e28d53452 100644 --- a/tests/snapshots/asm/ssa_bail_fixup_rollback.x64.asm +++ b/tests/snapshots/asm/ssa_bail_fixup_rollback.x64.asm @@ -36,112 +36,110 @@ Disassembly of section .text: movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) xorq %r8, %r8 - movslq %r8d, %rax - cmpq $0x4, %rax - jge jmp - movslq %r8d, %rax - leaq 0x1(%rax), %r8 - jmp - leaq -0x40(%rbp), %rax - leaq (%r8,%r8,4), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + leaq -0x40(%rbp), %r9 + leaq (%r8,%r8,4), %rbx movslq %ebx, %rbx - addq %rcx, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movq %r8, %r12 + shlq $0x2, %r12 + movslq %r12d, %r12 + addq %rcx, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0x1(%r8), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0x1(%r8), %rbx movslq %ebx, %rbx - addq %rdx, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movq %r8, %r12 + shlq $0x2, %r12 + movslq %r12d, %r12 + addq %rdx, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0x6(%r8), %r9 - movslq %r9d, %r9 - movq %r8, %rbx - shlq $0x2, %rbx + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0x6(%r8), %rbx movslq %ebx, %rbx - addq %rsi, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 - orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - leaq -0x40(%rbp), %rax - leaq 0xb(%r8), %r9 - movslq %r9d, %r9 - leaq 0x10(%rdx), %rbx movq %r8, %r12 shlq $0x2, %r12 movslq %r12d, %r12 - addq %r12, %rbx - movzbq 0x3(%rbx), %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x2(%rbx), %r13 + addq %rsi, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq 0x1(%rbx), %r13 + movl %r12d, (%r9,%rbx,4) + leaq -0x40(%rbp), %r9 + leaq 0xb(%r8), %rbx + movslq %ebx, %rbx + leaq 0x10(%rdx), %r12 + movq %r8, %r13 + shlq $0x2, %r13 + movslq %r13d, %r13 + addq %r13, %r12 + movzbq 0x3(%r12), %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x2(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq 0x1(%r12), %r14 + orq %r14, %r13 + movl %r13d, %r13d + shlq $0x8, %r13 + movl %r13d, %r13d + movzbq (%r12), %r12 orq %r13, %r12 - movl %r12d, %r12d - shlq $0x8, %r12 - movl %r12d, %r12d - movzbq (%rbx), %rbx - orq %r12, %rbx - movl %ebx, (%rax,%r9,4) - jmp + movl %r12d, (%r9,%rbx,4) + leaq 0x1(%rax), %r8 + movslq %r8d, %rax + cmpq $0x4, %rax + jl xorq %rax, %rax leaq -0x40(%rbp), %rcx movl (%rcx), %ecx @@ -159,6 +157,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 addq $0x70, %rsp popq %rbp retq @@ -185,37 +184,82 @@ Disassembly of section .text: addq $0xa0, %rsp popq %rbp retq + leaq -0x10(%rbp), %rax + addq $0x0, %rax xorq %rdx, %rdx - movl %edx, %eax - cmpq $0x10, %rax - jae - jmp - movl %edx, %eax - leaq 0x1(%rax), %rdx - jmp + movb %dl, (%rax) leaq -0x10(%rbp), %rax - movl %edx, %esi - addq %rsi, %rax - xorq %rsi, %rsi - movb %sil, (%rax) - jmp xorq %rdx, %rdx - movl %edx, %eax - cmpq $0x8, %rax - jae - jmp - movl %edx, %eax - leaq 0x1(%rax), %rdx - jmp + movb %dl, 0x1(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x2(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x3(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x4(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x5(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x6(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x7(%rax) leaq -0x10(%rbp), %rax - movl %edx, %esi - addq %rsi, %rax - addq %rcx, %rsi - movzbq (%rsi), %rsi - movb %sil, (%rax) + xorq %rdx, %rdx + movb %dl, 0x8(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0x9(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xa(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xb(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xc(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xd(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xe(%rax) + leaq -0x10(%rbp), %rax + xorq %rdx, %rdx + movb %dl, 0xf(%rax) + leaq -0x10(%rbp), %rax + addq $0x0, %rax + leaq (%rcx), %rdx + movzbq (%rdx), %rdx + movb %dl, (%rax) + leaq -0x10(%rbp), %rax + movzbq 0x1(%rcx), %rdx + movb %dl, 0x1(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x2(%rcx), %rdx + movb %dl, 0x2(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x3(%rcx), %rdx + movb %dl, 0x3(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x4(%rcx), %rdx + movb %dl, 0x4(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x5(%rcx), %rdx + movb %dl, 0x5(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x6(%rcx), %rdx + movb %dl, 0x6(%rax) + leaq -0x10(%rbp), %rax + movzbq 0x7(%rcx), %rcx + movb %cl, 0x7(%rax) jmp - cmpq $0x40, %r14 - jb leaq -0x50(%rbp), %rdi leaq -0x10(%rbp), %rsi leaq , %rcx @@ -223,36 +267,13 @@ Disassembly of section .text: callq xorq %rcx, %rcx jmp - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - addq $0xa0, %rsp - popq %rbp - retq - movl %ecx, %eax - cmpq $0x40, %rax - jae - jmp - movl %ecx, %eax - leaq 0x1(%rax), %rcx - jmp movl %ecx, %eax addq %r12, %rax testq %r13, %r13 je - jmp - subq $0x40, %r14 - addq $0x40, %r12 - testq %r13, %r13 - je - jmp movl %ecx, %edx addq %r13, %rdx movzbq (%rdx), %rsi - jmp - xorq %rsi, %rsi leaq -0x50(%rbp), %rdx movl %ecx, %edi addq %rdi, %rdx @@ -260,9 +281,29 @@ Disassembly of section .text: xorq %rsi, %rdx movb %dl, (%rax) jmp - addq $0x40, %r13 + xorq %rsi, %rsi jmp + movl %ecx, %eax + leaq 0x1(%rax), %rcx + movl %ecx, %eax + cmpq $0x40, %rax + jb + subq $0x40, %r14 + addq $0x40, %r12 + testq %r13, %r13 + je + addq $0x40, %r13 jmp + cmpq $0x40, %r14 + jae + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + addq $0xa0, %rsp + popq %rbp + retq
: pushq %rbp @@ -275,19 +316,16 @@ Disassembly of section .text: movq %rdx, (%rax) popq %rdx xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x20, %rax - jge jmp - movslq %ecx, %rax + leaq -0x68(%rbp), %rdx + addq %rax, %rdx + movq %rax, %rsi + andq $0xff, %rsi + movb %sil, (%rdx) leaq 0x1(%rax), %rcx - jmp - leaq -0x68(%rbp), %rax - movslq %ecx, %rdx - addq %rdx, %rax - andq $0xff, %rdx - movb %dl, (%rax) - jmp + movslq %ecx, %rax + cmpq $0x20, %rax + jl leaq -0x40(%rbp), %rdi xorq %rsi, %rsi movl $0x40, %edx @@ -301,10 +339,9 @@ Disassembly of section .text: testq %rax, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0xa0, %rsp popq %rbp retq - addb %al, 0x41(%rdx) + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/ssa_c5_internal_fp_arg.aarch64.asm b/tests/snapshots/asm/ssa_c5_internal_fp_arg.aarch64.asm index 95ea73b0d..36f7bddac 100644 --- a/tests/snapshots/asm/ssa_c5_internal_fp_arg.aarch64.asm +++ b/tests/snapshots/asm/ssa_c5_internal_fp_arg.aarch64.asm @@ -22,10 +22,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 add x1, x0, #0x64 sub x1, x1, x0 sxtw x1, w1 @@ -42,9 +41,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0xd00000000000 // =228698418577408 movk x0, #0x4062, lsl #48 @@ -55,9 +53,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret scvtf d0, x1 scvtf d1, x1 @@ -66,9 +63,8 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret scvtf d0, x1 mov x0, #0x3fe0000000000000 // =4602678819172646912 @@ -80,16 +76,14 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/ssa_c5_internal_fp_arg.x64.asm b/tests/snapshots/asm/ssa_c5_internal_fp_arg.x64.asm index 939d5e8e1..8e956861a 100644 --- a/tests/snapshots/asm/ssa_c5_internal_fp_arg.x64.asm +++ b/tests/snapshots/asm/ssa_c5_internal_fp_arg.x64.asm @@ -33,7 +33,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp leaq 0x64(%rdi), %rax subq %rdi, %rax movslq %eax, %rax @@ -55,7 +54,6 @@ Disassembly of section .text: cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x20, %rsp popq %rbp retq movabsq $0x4062d00000000000, %rcx # imm = 0x4062D00000000000 @@ -70,7 +68,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x20, %rsp popq %rbp retq cvtsi2sd %rax, %xmm0 @@ -84,7 +81,6 @@ Disassembly of section .text: cmpq $0x1, %rcx je movl $0x3, %eax - addq $0x20, %rsp popq %rbp retq cvtsi2sd %rax, %xmm0 @@ -101,7 +97,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x4, %eax - addq $0x20, %rsp popq %rbp retq leaq , %rdi @@ -109,8 +104,6 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - addq $0x20, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ssa_call_result_spill.aarch64.asm b/tests/snapshots/asm/ssa_call_result_spill.aarch64.asm index 2e94eec81..35a3b05d5 100644 --- a/tests/snapshots/asm/ssa_call_result_spill.aarch64.asm +++ b/tests/snapshots/asm/ssa_call_result_spill.aarch64.asm @@ -22,23 +22,14 @@ Disassembly of section .text: ret : - mov x1, #0xe // =14 - sxtw x1, w1 - ror x1, x0, x1 - mov x2, #0x12 // =18 - sxtw x2, w2 - ror x2, x0, x2 + ror x1, x0, #0xe + ror x2, x0, #0x12 eor x1, x1, x2 - mov x2, #0x29 // =41 - sxtw x2, w2 - ror x0, x0, x2 + ror x0, x0, #0x29 eor x0, x1, x0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 mov x9, #0x100 // =256 mov x8, #0x200 // =512 mov x7, #0x400 // =1024 @@ -48,11 +39,25 @@ Disassembly of section .text: mov x3, #0x4000 // =16384 mov x2, #0x8000 // =32768 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x4 - b.ge b - sxtw x0, w1 + ror x10, x5, #0xe + ror x11, x5, #0x12 + eor x10, x10, x11 + ror x11, x5, #0x29 + eor x10, x10, x11 + and x11, x5, x4 + mvn x12, x5 + and x12, x12, x3 + eor x11, x11, x12 + add x10, x10, x11 + add x2, x10, x2 + ror x10, x9, #0xe + ror x11, x9, #0x12 + eor x10, x10, x11 + ror x11, x9, #0x29 + eor x10, x10, x11 + add x6, x6, x2 + add x2, x2, x10 add x1, x0, #0x1 mov x16, x3 mov x3, x4 @@ -63,38 +68,9 @@ Disassembly of section .text: mov x8, x9 mov x9, x2 mov x2, x16 - b - mov x0, #0xe // =14 - sxtw x0, w0 - ror x0, x5, x0 - mov x10, #0x12 // =18 - sxtw x10, w10 - ror x10, x5, x10 - eor x0, x0, x10 - mov x10, #0x29 // =41 - sxtw x10, w10 - ror x10, x5, x10 - eor x0, x0, x10 - and x10, x5, x4 - mvn x11, x5 - and x11, x11, x3 - eor x10, x10, x11 - add x0, x0, x10 - add x0, x0, x2 - mov x2, #0xe // =14 - sxtw x2, w2 - ror x2, x9, x2 - mov x10, #0x12 // =18 - sxtw x10, w10 - ror x10, x9, x10 - eor x2, x2, x10 - mov x10, #0x29 // =41 - sxtw x10, w10 - ror x10, x9, x10 - eor x2, x2, x10 - add x6, x6, x0 - add x2, x0, x2 - b + sxtw x0, w1 + cmp x0, #0x4 + b.lt mov x17, #0xbb19 // =47897 movk x17, #0xde61, lsl #16 movk x17, #0x5d88, lsl #32 @@ -102,8 +78,6 @@ Disassembly of section .text: cmp x9, x17 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret mov x17, #0xc800 // =51200 movk x17, #0x8, lsl #32 @@ -111,10 +85,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/ssa_call_result_spill.x64.asm b/tests/snapshots/asm/ssa_call_result_spill.x64.asm index d66f9a324..f149e6329 100644 --- a/tests/snapshots/asm/ssa_call_result_spill.x64.asm +++ b/tests/snapshots/asm/ssa_call_result_spill.x64.asm @@ -29,38 +29,20 @@ Disassembly of section .text: retq : - movl $0xe, %eax - movslq %eax, %rax - movq %rax, %r10 movq %rdi, %rax - pushq %rcx - movq %r10, %rcx - rorq %cl, %rax - popq %rcx - movl $0x12, %ecx - movslq %ecx, %rcx - movq %rcx, %r10 + rorq $0xe, %rax movq %rdi, %rcx - movq %rcx, %r11 - movq %r10, %rcx - rorq %cl, %r11 - movq %r11, %rcx + rorq $0x12, %rcx xorq %rcx, %rax - movl $0x29, %ecx - movslq %ecx, %rcx - movq %rcx, %r10 movq %rdi, %rcx - movq %rcx, %r11 - movq %r10, %rcx - rorq %cl, %r11 - movq %r11, %rcx + rorq $0x29, %rcx xorq %rcx, %rax retq
: pushq %rbp movq %rsp, %rbp - subq $0xb0, %rsp + subq $0x40, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -75,11 +57,36 @@ Disassembly of section .text: movl $0x4000, %esi # imm = 0x4000 movl $0x8000, %edx # imm = 0x8000 xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x4, %rax - jge jmp - movslq %ecx, %rax + movq %r8, %r14 + rorq $0xe, %r14 + movq %r8, %r15 + rorq $0x12, %r15 + xorq %r15, %r14 + movq %r8, %r15 + rorq $0x29, %r15 + xorq %r15, %r14 + movq %r8, %r15 + andq %rdi, %r15 + movq %r8, %r10 + xorq $-0x1, %r10 + movq %r10, 0x38(%rsp) + movq 0x38(%rsp), %r10 + andq %rsi, %r10 + movq %r10, 0x38(%rsp) + xorq 0x38(%rsp), %r15 + addq %r15, %r14 + addq %r14, %rdx + movq %r13, %r14 + rorq $0xe, %r14 + movq %r13, %r15 + rorq $0x12, %r15 + xorq %r15, %r14 + movq %r13, %r15 + rorq $0x29, %r15 + xorq %r15, %r14 + addq %rdx, %r9 + addq %r14, %rdx leaq 0x1(%rax), %rcx xchgq %rsi, %rdx xchgq %rsi, %r13 @@ -88,70 +95,9 @@ Disassembly of section .text: xchgq %rsi, %r9 xchgq %rsi, %r8 xchgq %rsi, %rdi - jmp - movl $0xe, %eax - movslq %eax, %rax - movq %rax, %r10 - movq %r8, %rax - pushq %rcx - movq %r10, %rcx - rorq %cl, %rax - popq %rcx - movl $0x12, %r14d - movslq %r14d, %r14 - movq %r14, %r10 - movq %r8, %r14 - pushq %rcx - movq %r10, %rcx - rorq %cl, %r14 - popq %rcx - xorq %r14, %rax - movl $0x29, %r14d - movslq %r14d, %r14 - movq %r14, %r10 - movq %r8, %r14 - pushq %rcx - movq %r10, %rcx - rorq %cl, %r14 - popq %rcx - xorq %r14, %rax - movq %r8, %r14 - andq %rdi, %r14 - movq %r8, %r15 - xorq $-0x1, %r15 - andq %rsi, %r15 - xorq %r15, %r14 - addq %r14, %rax - addq %rdx, %rax - movl $0xe, %edx - movslq %edx, %rdx - movq %rdx, %r10 - movq %r13, %rdx - pushq %rcx - movq %r10, %rcx - rorq %cl, %rdx - popq %rcx - movl $0x12, %r14d - movslq %r14d, %r14 - movq %r14, %r10 - movq %r13, %r14 - pushq %rcx - movq %r10, %rcx - rorq %cl, %r14 - popq %rcx - xorq %r14, %rdx - movl $0x29, %r14d - movslq %r14d, %r14 - movq %r14, %r10 - movq %r13, %r14 - pushq %rcx - movq %r10, %rcx - rorq %cl, %r14 - popq %rcx - xorq %r14, %rdx - addq %rax, %r9 - addq %rax, %rdx - jmp + movslq %ecx, %rax + cmpq $0x4, %rax + jl movabsq $0x30a55d88de61bb19, %r11 # imm = 0x30A55D88DE61BB19 movq %r13, %rax cmpq %r11, %r13 @@ -162,7 +108,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xb0, %rsp + addq $0x40, %rsp popq %rbp retq movabsq $0x440000080000c800, %r11 # imm = 0x440000080000C800 @@ -175,7 +121,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xb0, %rsp + addq $0x40, %rsp popq %rbp retq xorq %rax, %rax @@ -184,6 +130,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xb0, %rsp + addq $0x40, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ssa_callee_saved_x19.aarch64.asm b/tests/snapshots/asm/ssa_callee_saved_x19.aarch64.asm index 1ba675439..1d9717b21 100644 --- a/tests/snapshots/asm/ssa_callee_saved_x19.aarch64.asm +++ b/tests/snapshots/asm/ssa_callee_saved_x19.aarch64.asm @@ -20,11 +20,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x0, add x0, x0, mov x20, #0x0 // =0 @@ -33,8 +32,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/ssa_fp_compare_nan.aarch64.asm b/tests/snapshots/asm/ssa_fp_compare_nan.aarch64.asm index 11c5a0e4f..b223342b0 100644 --- a/tests/snapshots/asm/ssa_fp_compare_nan.aarch64.asm +++ b/tests/snapshots/asm/ssa_fp_compare_nan.aarch64.asm @@ -25,91 +25,80 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str d8, [sp] - str x20, [sp, #0x10] - str x19, [sp, #0x20] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 bl - fmov d8, d0 - mov x20, #0x0 // =0 - fmov d17, x20 - fcmp d8, d17 + mov x1, #0x0 // =0 + fmov d17, x1 + fcmp d0, d17 cset x0, mi cbz x0, - mov x17, #0x1 // =1 - orr x20, x20, x17 + mov x1, #0x1 // =1 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, gt cbz x0, mov x17, #0x2 // =2 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ls cbz x0, mov x17, #0x4 // =4 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ge cbz x0, mov x17, #0x8 // =8 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, eq cbz x0, mov x17, #0x10 // =16 - orr x20, x20, x17 + orr x1, x1, x17 mov x0, #0x0 // =0 fmov d17, x0 - fcmp d8, d17 + fcmp d0, d17 cset x0, ne cmp x0, #0x0 b.ne mov x17, #0x20 // =32 - orr x20, x20, x17 - fcmp d8, d8 + orr x1, x1, x17 + fcmp d0, d0 cset x0, mi cbz x0, mov x17, #0x40 // =64 - orr x20, x20, x17 - fcmp d8, d8 + orr x1, x1, x17 + fcmp d0, d0 cset x0, eq cbz x0, mov x17, #0x80 // =128 - orr x20, x20, x17 - sxtw x0, w20 + orr x1, x1, x17 + sxtw x0, w1 cbz x0, adrp x0, add x0, x0, - sxtw x1, w20 + sxtw x1, w1 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b diff --git a/tests/snapshots/asm/ssa_fp_compare_nan.x64.asm b/tests/snapshots/asm/ssa_fp_compare_nan.x64.asm index d21e42b19..9f181bd3d 100644 --- a/tests/snapshots/asm/ssa_fp_compare_nan.x64.asm +++ b/tests/snapshots/asm/ssa_fp_compare_nan.x64.asm @@ -27,14 +27,10 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) callq - movsd %xmm0, 0x18(%rsp) - xorq %rbx, %rbx - movsd 0x18(%rsp), %xmm14 - movq %rbx, %xmm15 - ucomisd %xmm15, %xmm14 + xorq %rcx, %rcx + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 setb %al movzbq %al, %rax setnp %r10b @@ -42,20 +38,18 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je - orq $0x1, %rbx + movl $0x1, %ecx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 seta %al movzbq %al, %rax testq %rax, %rax je - orq $0x2, %rbx + orq $0x2, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setbe %al movzbq %al, %rax setnp %r10b @@ -63,20 +57,18 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je - orq $0x4, %rbx + orq $0x4, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setae %al movzbq %al, %rax testq %rax, %rax je - orq $0x8, %rbx + orq $0x8, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -84,11 +76,10 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je - orq $0x10, %rbx + orq $0x10, %rcx xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -96,10 +87,8 @@ Disassembly of section .text: orq %r10, %rax testq %rax, %rax jne - orq $0x20, %rbx - movsd 0x18(%rsp), %xmm14 - movsd 0x18(%rsp), %xmm15 - ucomisd %xmm15, %xmm14 + orq $0x20, %rcx + ucomisd %xmm0, %xmm0 setb %al movzbq %al, %rax setnp %r10b @@ -107,10 +96,8 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je - orq $0x40, %rbx - movsd 0x18(%rsp), %xmm14 - movsd 0x18(%rsp), %xmm15 - ucomisd %xmm15, %xmm14 + orq $0x40, %rcx + ucomisd %xmm0, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -118,18 +105,16 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je - orq $0x80, %rbx - movslq %ebx, %rax + orq $0x80, %rcx + movslq %ecx, %rax testq %rax, %rax je leaq , %rdi - movslq %ebx, %rsi + movslq %ecx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq leaq , %rdi @@ -137,8 +122,6 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq jmp @@ -149,3 +132,4 @@ Disassembly of section .text: jmp jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ssa_fp_routing.aarch64.asm b/tests/snapshots/asm/ssa_fp_routing.aarch64.asm index 378f04ae3..c812220a7 100644 --- a/tests/snapshots/asm/ssa_fp_routing.aarch64.asm +++ b/tests/snapshots/asm/ssa_fp_routing.aarch64.asm @@ -69,13 +69,8 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fcvt s0, d0 fcvt d0, s0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: @@ -278,7 +273,6 @@ Disassembly of section .text: mov x0, #0x14 // =20 ret mov x0, #0x2a // =42 - sxtw x0, w0 scvtf d0, x0 mov x0, #0x4045000000000000 // =4631107791820423168 fmov d17, x0 @@ -291,7 +285,6 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - sxtw x0, w0 scvtf d0, x0 mov x0, #0x4008000000000000 // =4613937818241073152 fmov d16, x0 diff --git a/tests/snapshots/asm/ssa_fp_routing.x64.asm b/tests/snapshots/asm/ssa_fp_routing.x64.asm index 040625638..de0dc082e 100644 --- a/tests/snapshots/asm/ssa_fp_routing.x64.asm +++ b/tests/snapshots/asm/ssa_fp_routing.x64.asm @@ -90,13 +90,8 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp cvtsd2ss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 - addq $0x10, %rsp - popq %rbp retq
: @@ -384,7 +379,6 @@ Disassembly of section .text: movl $0x14, %eax retq movl $0x2a, %eax - movslq %eax, %rax cvtsi2sd %rax, %xmm0 movabsq $0x4045000000000000, %rax # imm = 0x4045000000000000 movq %rax, %xmm15 @@ -399,7 +393,6 @@ Disassembly of section .text: movl $0x15, %eax retq movabsq $-0x3, %rax - movslq %eax, %rax cvtsi2sd %rax, %xmm0 movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 movq %rax, %xmm1 @@ -466,3 +459,4 @@ Disassembly of section .text: xorq %rax, %rax retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ssa_va_arg_loop.aarch64.asm b/tests/snapshots/asm/ssa_va_arg_loop.aarch64.asm index ab94e97c1..de40d4f9d 100644 --- a/tests/snapshots/asm/ssa_va_arg_loop.aarch64.asm +++ b/tests/snapshots/asm/ssa_va_arg_loop.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -52,16 +51,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x10] - cmp x2, x3 - b.ge b - sxtw x1, w1 - add x1, x1, #0x1 - b - sub x2, x29, #0x20 - mov x17, x2 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,14 +70,17 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x2, x16 - ldr x2, [x2] - add x0, x0, x2 - b + mov x3, x16 + ldr x3, [x3] + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + ldursw x3, [x29, #0x10] + cmp x2, x3 + b.lt sub x1, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret @@ -107,10 +102,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -151,9 +145,8 @@ Disassembly of section .text: mov x0, x16 ldr x0, [x0] sub x1, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/ssa_va_arg_loop.x64.asm b/tests/snapshots/asm/ssa_va_arg_loop.x64.asm index 78c5b9234..d312ff102 100644 --- a/tests/snapshots/asm/ssa_va_arg_loop.x64.asm +++ b/tests/snapshots/asm/ssa_va_arg_loop.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xe0(%rbp), %rsi - cmpq %rsi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - leaq -0x18(%rbp), %rdx - movq %rdx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -58,10 +51,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rdx - movq (%rdx), %rdx - addq %rdx, %rax - jmp + movq %r10, %rsi + movq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + movslq -0xe0(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x18(%rbp), %rcx addq $0xe0, %rsp popq %rbp @@ -151,5 +148,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.aarch64.asm b/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.aarch64.asm index d68375565..57f08ac65 100644 --- a/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.aarch64.asm +++ b/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -94,9 +93,8 @@ Disassembly of section .text: mov x17, #0x3e8 // =1000 mul x1, x1, x17 add x0, x0, x1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret @@ -118,10 +116,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -198,17 +195,15 @@ Disassembly of section .text: mov x17, #0x11 // =17 mul x0, x0, x17 add x0, x0, x1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x2 // =2 mov x1, #0xb // =11 mov x2, #0x16 // =22 @@ -222,9 +217,8 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x1 // =1 mov x1, #0x7 // =7 @@ -237,12 +231,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.x64.asm b/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.x64.asm index f8ce235e9..a2b9e1362 100644 --- a/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.x64.asm +++ b/tests/snapshots/asm/ssa_va_start_va_copy_aliasing.x64.asm @@ -142,7 +142,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp movl $0x2, %edi movl $0xb, %esi movl $0x16, %edx @@ -156,7 +155,6 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - addq $0x20, %rsp popq %rbp retq movl $0x1, %edi @@ -171,11 +169,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x2, %eax - addq $0x20, %rsp popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/ssa_variadic_fp_arg.aarch64.asm b/tests/snapshots/asm/ssa_variadic_fp_arg.aarch64.asm index 54b26a39a..06ac09c2f 100644 --- a/tests/snapshots/asm/ssa_variadic_fp_arg.aarch64.asm +++ b/tests/snapshots/asm/ssa_variadic_fp_arg.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x50]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 adrp x0, add x0, x0, adrp x20, @@ -49,11 +47,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x50 ret ldr d0, [x20] mov x0, #0x900000000000 // =158329674399744 @@ -63,16 +59,12 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x50 ret diff --git a/tests/snapshots/asm/stat_timespec.aarch64.asm b/tests/snapshots/asm/stat_timespec.aarch64.asm index 1ad1059e1..a48bd61ab 100644 --- a/tests/snapshots/asm/stat_timespec.aarch64.asm +++ b/tests/snapshots/asm/stat_timespec.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x19, [sp] + str x19, [sp, #-0xb0]! + stp x29, x30, [sp, #0xa0] + add x29, sp, #0xa0 adrp x0, add x0, x0, sub x1, x29, #0x80 @@ -21,9 +20,8 @@ Disassembly of section .text: sxtw x0, w0 cbz x0, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret sub x0, x29, #0x80 ldr x0, [x0, #0x58] @@ -32,9 +30,8 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret sub x0, x29, #0x80 ldr x0, [x0, #0x58] @@ -43,9 +40,8 @@ Disassembly of section .text: cmp x0, x17 b.ge mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret sub x0, x29, #0x80 ldrsw x0, [x0, #0x10] @@ -57,12 +53,10 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret diff --git a/tests/snapshots/asm/static_assert_and_warning.aarch64.asm b/tests/snapshots/asm/static_assert_and_warning.aarch64.asm index a2e392a1b..6078ccd93 100644 --- a/tests/snapshots/asm/static_assert_and_warning.aarch64.asm +++ b/tests/snapshots/asm/static_assert_and_warning.aarch64.asm @@ -10,16 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x1, #0x0 // =0 - add x1, x1, #0x1 + mov x1, #0x1 // =1 sxtw x0, w1 add x1, x0, #0x1 sxtw x0, w1 cmp x0, #0x2 cset x0, ne - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/static_assert_and_warning.x64.asm b/tests/snapshots/asm/static_assert_and_warning.x64.asm index 9e8bdc092..b06f60888 100644 --- a/tests/snapshots/asm/static_assert_and_warning.x64.asm +++ b/tests/snapshots/asm/static_assert_and_warning.x64.asm @@ -11,18 +11,13 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rcx, %rcx - incq %rcx + movl $0x1, %ecx movslq %ecx, %rax leaq 0x1(%rax), %rcx movslq %ecx, %rax cmpq $0x2, %rax setne %al movzbq %al, %rax - addq $0x10, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/static_assert_in_struct.aarch64.asm b/tests/snapshots/asm/static_assert_in_struct.aarch64.asm index fc2395140..84fc3717d 100644 --- a/tests/snapshots/asm/static_assert_in_struct.aarch64.asm +++ b/tests/snapshots/asm/static_assert_in_struct.aarch64.asm @@ -10,52 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x8 mov x1, #0x1 // =1 str w1, [x0] sub x0, x29, #0x8 mov x1, #0x2 // =2 str w1, [x0, #0x4] - mov x20, #0x4 // =4 - b - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 ldrsw x0, [x0] cmp x0, #0x1 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x8 ldrsw x0, [x0, #0x4] cmp x0, #0x2 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - cmp x20, #0x0 - b.gt - mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret adrp x0, add x0, x0, @@ -67,10 +43,15 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret b + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 + ret diff --git a/tests/snapshots/asm/static_assert_in_struct.x64.asm b/tests/snapshots/asm/static_assert_in_struct.x64.asm index 8cdb0623b..b80e3b7ad 100644 --- a/tests/snapshots/asm/static_assert_in_struct.x64.asm +++ b/tests/snapshots/asm/static_assert_in_struct.x64.asm @@ -13,49 +13,29 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) + subq $0x40, %rsp leaq -0x8(%rbp), %rax movl $0x1, %ecx movl %ecx, (%rax) leaq -0x8(%rbp), %rax movl $0x2, %ecx movl %ecx, 0x4(%rax) - movl $0x4, %ebx - jmp - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x50, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax movslq (%rax), %rax cmpq $0x1, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x8(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x2, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x50, %rsp - popq %rbp - retq - testq %rbx, %rbx - jg - movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq leaq , %rdi @@ -68,10 +48,16 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq jmp - addb %al, 0x41(%rdx) + movl $0x1, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x40, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/static_init_cast_funcptr.aarch64.asm b/tests/snapshots/asm/static_init_cast_funcptr.aarch64.asm index 9043771ae..ca3f83c4e 100644 --- a/tests/snapshots/asm/static_init_cast_funcptr.aarch64.asm +++ b/tests/snapshots/asm/static_init_cast_funcptr.aarch64.asm @@ -24,36 +24,30 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, ldr x0, [x20, #0x8] mov x1, #0x15 // =21 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x20] mov x1, #0x7 // =7 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 mov x17, #0xfff9 // =65529 movk x17, #0xffff, lsl #16 @@ -62,36 +56,30 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x10] adrp x1, add x1, x1, - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x64 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x28] adrp x1, add x1, x1, - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 mov x17, #0xffef // =65519 movk x17, #0xffff, lsl #16 @@ -100,10 +88,9 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20] ldrb w0, [x0] @@ -113,10 +100,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x18] ldrb w0, [x0] @@ -126,33 +112,29 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret <__c5_sys_atoi>: str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x10 ret diff --git a/tests/snapshots/asm/static_init_once_guard.aarch64.asm b/tests/snapshots/asm/static_init_once_guard.aarch64.asm new file mode 100644 index 000000000..c47047fb6 --- /dev/null +++ b/tests/snapshots/asm/static_init_once_guard.aarch64.asm @@ -0,0 +1,134 @@ + +static_init_once_guard.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + stur w0, [x29, #0x10] + adrp x0, + add x0, x0, + ldrsb x1, [x0, #0x10] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x8] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + mov x1, #0x1 // =1 + strb w1, [x0, #0x10] + stur x1, [x29, #-0x8] + ldursw x1, [x29, #0x10] + cmp x1, #0x0 + b.ne + b + mov x0, #0xa // =10 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + mov x0, #0x14 // =20 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + adrp x1, + add x1, x1, + ldr x2, [x0] + str x2, [x1] + ldr x1, [x0, #0x8] + str x1, [x0] + br x1 + ldr x1, [x0] + ldr x2, [x0, #0x8] + cmp x1, x2 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + str x1, [x0] + br x1 + +: + sxtw x0, w0 + sxtw x1, w1 + adrp x2, + add x2, x2, + ldrsb x3, [x2, #0x10] + cbz x3, + mov x4, #0x0 // =0 + cbz x1, + mov x1, #0x7 // =7 + str w1, [x2, #0x4] + ldrsw x0, [x2, x0, lsl #2] + ret + mov x5, #0x0 // =0 + mov x5, #0x1 // =1 + str w5, [x2] + mov x3, #0x0 // =0 + str w3, [x2, #0x4] + mov x4, #0x1 // =1 + str w4, [x2, #0x8] + strb w4, [x2, #0x10] + b + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x0 // =0 + bl + cmp x0, #0x14 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + bl + cmp x0, #0xa + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, x0 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, #0x0 // =0 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x5 // =5 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + mov x1, x0 + bl + cmp x0, #0x1 + b.eq + mov x0, #0x6 // =6 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/static_init_once_guard.x64.asm b/tests/snapshots/asm/static_init_once_guard.x64.asm new file mode 100644 index 000000000..a6b40544a --- /dev/null +++ b/tests/snapshots/asm/static_init_once_guard.x64.asm @@ -0,0 +1,143 @@ + +static_init_once_guard.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax + movsbq 0x10(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x8(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + movl $0x1, %ecx + movb %cl, 0x10(%rax) + movq %rcx, -0x8(%rbp) + movslq 0x10(%rbp), %rcx + testq %rcx, %rcx + jne + jmp + movl $0xa, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + movl $0x14, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + leaq , %rcx + movq (%rax), %rdx + movq %rdx, (%rcx) + movq 0x8(%rax), %rcx + movq %rcx, (%rax) + jmpq *%rcx + movq (%rax), %rcx + movq 0x8(%rax), %rdx + cmpq %rdx, %rcx + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + leaq , %rcx + movq (%rcx), %rcx + movq %rcx, (%rax) + jmpq *%rcx + +: + movslq %edi, %rdi + movslq %esi, %rsi + leaq , %rax + movsbq 0x10(%rax), %rcx + testq %rcx, %rcx + je + xorq %rdx, %rdx + testq %rsi, %rsi + je + movl $0x7, %ecx + movl %ecx, 0x4(%rax) + movslq (%rax,%rdi,4), %rax + retq + xorq %r8, %r8 + movl $0x1, %r8d + movl %r8d, (%rax) + xorq %rcx, %rcx + movl %ecx, 0x4(%rax) + movl $0x1, %edx + movl %edx, 0x8(%rax) + movb %dl, 0x10(%rax) + jmp + +
: + pushq %rbp + movq %rsp, %rbp + xorq %rdi, %rdi + callq + cmpq $0x14, %rax + je + movl $0x2, %eax + popq %rbp + retq + movl $0x1, %edi + callq + cmpq $0xa, %rax + je + movl $0x3, %eax + popq %rbp + retq + movl $0x1, %edi + movq %rdi, %rsi + callq + cmpq $0x7, %rax + je + movl $0x4, %eax + popq %rbp + retq + movl $0x1, %edi + xorq %rsi, %rsi + callq + cmpq $0x7, %rax + je + movl $0x5, %eax + popq %rbp + retq + xorq %rdi, %rdi + movq %rdi, %rsi + callq + cmpq $0x1, %rax + je + movl $0x6, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq diff --git a/tests/snapshots/asm/static_init_paren_relocation.aarch64.asm b/tests/snapshots/asm/static_init_paren_relocation.aarch64.asm index c17c47c87..66e82088e 100644 --- a/tests/snapshots/asm/static_init_paren_relocation.aarch64.asm +++ b/tests/snapshots/asm/static_init_paren_relocation.aarch64.asm @@ -14,39 +14,32 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, mov x0, #0x0 // =0 ldr x1, [x20, #0x8] - str x0, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x1, x0 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldrsw x0, [x20, #0x10] cmp x0, #0x82 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -54,45 +47,38 @@ Disassembly of section .text: adrp x1, add x1, x1, cmp x0, x1 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] ldrsw x0, [x0] cmp x0, #0x63 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 adrp x1, add x1, x1, ldr x1, [x1] - str x0, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x1 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x1, x0 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret b diff --git a/tests/snapshots/asm/static_init_paren_relocation.x64.asm b/tests/snapshots/asm/static_init_paren_relocation.x64.asm index 7d0689fa8..aeec38853 100644 --- a/tests/snapshots/asm/static_init_paren_relocation.x64.asm +++ b/tests/snapshots/asm/static_init_paren_relocation.x64.asm @@ -17,7 +17,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq , %rbx xorq %rdi, %rdi @@ -29,7 +29,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movslq 0x10(%rbx), %rax @@ -37,28 +37,28 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax leaq , %rcx cmpq %rcx, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movq (%rax), %rax movslq (%rax), %rax cmpq $0x63, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rdi, %rdi @@ -71,12 +71,12 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/static_init_struct_fp_call.aarch64.asm b/tests/snapshots/asm/static_init_struct_fp_call.aarch64.asm index d82bcbcb7..1484ab012 100644 --- a/tests/snapshots/asm/static_init_struct_fp_call.aarch64.asm +++ b/tests/snapshots/asm/static_init_struct_fp_call.aarch64.asm @@ -20,54 +20,44 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, ldr x0, [x20] mov x1, #0x2 // =2 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x8] mov x1, #0xa // =10 mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x6 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/static_init_struct_fp_call.x64.asm b/tests/snapshots/asm/static_init_struct_fp_call.x64.asm index e4d183da6..71a7cedcd 100644 --- a/tests/snapshots/asm/static_init_struct_fp_call.x64.asm +++ b/tests/snapshots/asm/static_init_struct_fp_call.x64.asm @@ -24,7 +24,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq , %rbx movq (%rbx), %rax @@ -36,7 +36,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movq 0x8(%rbx), %rax @@ -48,12 +48,12 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/static_inline_function.aarch64.asm b/tests/snapshots/asm/static_inline_function.aarch64.asm index f65394ed9..b63afe53d 100644 --- a/tests/snapshots/asm/static_inline_function.aarch64.asm +++ b/tests/snapshots/asm/static_inline_function.aarch64.asm @@ -17,52 +17,20 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 mov x1, #0x0 // =0 - cbz x2, + b mov x17, #0x1 // =1 and x0, x2, x17 add x1, x1, x0 lsr x2, x2, #1 - b + cbnz x2, mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - mov x0, #0x2 // =2 - mov x17, #0x3 // =3 - mul x0, x0, x17 - add x0, x0, #0x1 - sxtw x0, w0 - cmp x0, #0x7 - b.eq - mov x0, #0x1 // =1 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0x3 // =3 - mul x0, x0, x17 - add x0, x0, #0x1 - sxtw x0, w0 - mov x17, #0xfffe // =65534 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - mov x0, #0x2 // =2 - ldp x29, x30, [sp], #0x10 - ret mov x0, #0xbeef // =48879 movk x0, #0xdead, lsl #16 bl @@ -81,3 +49,9 @@ Disassembly of section .text: mov x0, #0x0 // =0 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/static_inline_function.x64.asm b/tests/snapshots/asm/static_inline_function.x64.asm index 5ae141d65..f9517f9f3 100644 --- a/tests/snapshots/asm/static_inline_function.x64.asm +++ b/tests/snapshots/asm/static_inline_function.x64.asm @@ -17,43 +17,20 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rcx, %rcx - testq %rdi, %rdi - je + jmp movq %rdi, %rax andq $0x1, %rax addq %rax, %rcx shrq $0x1, %rdi - jmp + testq %rdi, %rdi + jne movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq
: pushq %rbp movq %rsp, %rbp - movl $0x2, %eax - leaq (%rax,%rax,2), %rax - incq %rax - movslq %eax, %rax - cmpq $0x7, %rax - je - movl $0x1, %eax - popq %rbp - retq - movabsq $-0x1, %rax - leaq (%rax,%rax,2), %rax - incq %rax - movslq %eax, %rax - cmpq $-0x2, %rax - je - movl $0x2, %eax - popq %rbp - retq movl $0xdeadbeef, %edi # imm = 0xDEADBEEF callq cmpq $0x18, %rax @@ -71,4 +48,10 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + movl $0x1, %eax + popq %rbp + retq + movl $0x2, %eax + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/static_linked_list.aarch64.asm b/tests/snapshots/asm/static_linked_list.aarch64.asm index 8fc5ddf99..a5d6bc382 100644 --- a/tests/snapshots/asm/static_linked_list.aarch64.asm +++ b/tests/snapshots/asm/static_linked_list.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, mov x1, #0x1 // =1 @@ -32,20 +29,16 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr x1, [x0] - cmp x1, #0x0 - b.eq + b ldrsw x0, [x1] add x2, x2, x0 ldr x1, [x1, #0x8] - b + cmp x1, #0x0 + b.ne sxtw x0, w2 cmp x0, #0x6 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/static_linked_list.x64.asm b/tests/snapshots/asm/static_linked_list.x64.asm index a73326a9a..7bd46fb43 100644 --- a/tests/snapshots/asm/static_linked_list.x64.asm +++ b/tests/snapshots/asm/static_linked_list.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movl $0x1, %ecx movl %ecx, (%rax) @@ -29,22 +26,17 @@ Disassembly of section .text: movq %rdx, 0x8(%rax) leaq , %rax movq (%rax), %rcx - testq %rcx, %rcx - je + jmp movslq (%rcx), %rax addq %rax, %rdx movq 0x8(%rcx), %rcx - jmp + testq %rcx, %rcx + jne movslq %edx, %rax cmpq $0x6, %rax je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/static_local_shadows_extern_fn.aarch64.asm b/tests/snapshots/asm/static_local_shadows_extern_fn.aarch64.asm index 21351003b..531869483 100644 --- a/tests/snapshots/asm/static_local_shadows_extern_fn.aarch64.asm +++ b/tests/snapshots/asm/static_local_shadows_extern_fn.aarch64.asm @@ -21,16 +21,10 @@ Disassembly of section .text: mov x2, #0x0 // =0 cmp x0, #0x2 b.lt - b + cmp x0, #0x2 + b.eq sxtw x0, w2 ret - adrp x0, - add x0, x0, - ldrb w1, [x0] - ldrb w0, [x0, #0x1] - add x0, x1, x0 - sxtw x2, w0 - b mov x2, #0xffff // =65535 movk x2, #0xffff, lsl #16 movk x2, #0xffff, lsl #32 @@ -39,10 +33,12 @@ Disassembly of section .text: cmp x0, #0x1 b.eq b - cmp x0, #0x2 - b.eq - b - b + adrp x0, + add x0, x0, + ldrb w1, [x0] + ldrb w0, [x0, #0x1] + add x0, x1, x0 + sxtw x2, w0 b b diff --git a/tests/snapshots/asm/static_local_shadows_extern_fn.x64.asm b/tests/snapshots/asm/static_local_shadows_extern_fn.x64.asm index a7d22e469..79c2efb1a 100644 --- a/tests/snapshots/asm/static_local_shadows_extern_fn.x64.asm +++ b/tests/snapshots/asm/static_local_shadows_extern_fn.x64.asm @@ -22,24 +22,20 @@ Disassembly of section .text: xorq %rcx, %rcx cmpq $0x2, %rdi jl - jmp + cmpq $0x2, %rdi + je movslq %ecx, %rax retq - leaq , %rax - movzbq (%rax), %rcx - movzbq 0x1(%rax), %rax - addq %rcx, %rax - movslq %eax, %rcx - jmp movabsq $-0x1, %rcx jmp cmpq $0x1, %rdi je jmp - cmpq $0x2, %rdi - je - jmp - jmp + leaq , %rax + movzbq (%rax), %rcx + movzbq 0x1(%rax), %rax + addq %rcx, %rax + movslq %eax, %rcx jmp jmp diff --git a/tests/snapshots/asm/static_local_shadows_global.aarch64.asm b/tests/snapshots/asm/static_local_shadows_global.aarch64.asm index 066472a19..f3c3a7a43 100644 --- a/tests/snapshots/asm/static_local_shadows_global.aarch64.asm +++ b/tests/snapshots/asm/static_local_shadows_global.aarch64.asm @@ -19,48 +19,42 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, ldrsw x0, [x20] cmp x0, #0x4d2 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret bl mov x17, #0x11d7 // =4567 cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret bl mov x17, #0x11d8 // =4568 cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret ldrsw x0, [x20] cmp x0, #0x4d2 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/static_neg_infinity_init.aarch64.asm b/tests/snapshots/asm/static_neg_infinity_init.aarch64.asm index 914159967..e71e5cb68 100644 --- a/tests/snapshots/asm/static_neg_infinity_init.aarch64.asm +++ b/tests/snapshots/asm/static_neg_infinity_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0xc8a0 // =51360 movk x0, #0x85eb, lsl #16 movk x0, #0xccf3, lsl #32 @@ -29,16 +26,13 @@ Disassembly of section .text: cmp x0, #0x0 cset x2, ne mov x0, x2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, ldr d0, [x20] @@ -46,9 +40,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -57,9 +50,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -68,9 +60,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret ldr d0, [x20] fneg d0, d0 @@ -83,12 +74,10 @@ Disassembly of section .text: cset x0, ls cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/static_neg_infinity_init.x64.asm b/tests/snapshots/asm/static_neg_infinity_init.x64.asm index 2ad932c0d..176451d6a 100644 --- a/tests/snapshots/asm/static_neg_infinity_init.x64.asm +++ b/tests/snapshots/asm/static_neg_infinity_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movabsq $0x7fe1ccf385ebc8a0, %rax # imm = 0x7FE1CCF385EBC8A0 movq %rax, %xmm1 movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 @@ -40,8 +37,6 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -104,4 +99,3 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/stdatomic_c11.aarch64.asm b/tests/snapshots/asm/stdatomic_c11.aarch64.asm index 1bb3db48f..416def331 100644 --- a/tests/snapshots/asm/stdatomic_c11.aarch64.asm +++ b/tests/snapshots/asm/stdatomic_c11.aarch64.asm @@ -165,32 +165,22 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7fff // =32767 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - mov x3, #0x0 // =0 - mov x17, #0x7fff // =32767 - cmp x0, x17 - cset x3, ne - cbz x3, + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, mov x0, #0xa // =10 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x1, x17 - b.eq - mov x0, #0xb // =11 + mov x0, #0x0 // =0 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xc // =12 + mov x0, #0xb // =11 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0xc // =12 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/stdatomic_c11.x64.asm b/tests/snapshots/asm/stdatomic_c11.x64.asm index 603ed7203..fb4a5648a 100644 --- a/tests/snapshots/asm/stdatomic_c11.x64.asm +++ b/tests/snapshots/asm/stdatomic_c11.x64.asm @@ -151,33 +151,23 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - movl $0x7fff, %eax # imm = 0x7FFF - movl $0xffffffff, %ecx # imm = 0xFFFFFFFF - xorq %rsi, %rsi - cmpq $0x7fff, %rax # imm = 0x7FFF - setne %sil - movzbq %sil, %rsi - testq %rsi, %rsi + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx je movl $0xa, %eax addq $0x50, %rsp popq %rbp retq - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rcx, %rax - cmpq %r11, %rcx - je - movl $0xb, %eax + xorq %rax, %rax addq $0x50, %rsp popq %rbp retq - jmp - movl $0xc, %eax + movl $0xb, %eax addq $0x50, %rsp popq %rbp retq - xorq %rax, %rax + movl $0xc, %eax addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/stdint_min_macros_type_and_value.aarch64.asm b/tests/snapshots/asm/stdint_min_macros_type_and_value.aarch64.asm index 5c323a604..bb46e73a5 100644 --- a/tests/snapshots/asm/stdint_min_macros_type_and_value.aarch64.asm +++ b/tests/snapshots/asm/stdint_min_macros_type_and_value.aarch64.asm @@ -10,40 +10,21 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - b - mov x0, #0x15 // =21 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x16 // =22 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xa // =10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xb // =11 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret mov x2, #0x1 // =1 mov x2, #0x0 // =0 cbnz x2, mov x2, #0x0 // =0 cbz x2, mov x0, #0x1e // =30 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b + mov x0, #0x15 // =21 + ret + mov x0, #0x16 // =22 + ret + mov x0, #0xa // =10 + ret + mov x0, #0xb // =11 + ret diff --git a/tests/snapshots/asm/stdint_min_macros_type_and_value.x64.asm b/tests/snapshots/asm/stdint_min_macros_type_and_value.x64.asm index 3b08365d0..556e46bae 100644 --- a/tests/snapshots/asm/stdint_min_macros_type_and_value.x64.asm +++ b/tests/snapshots/asm/stdint_min_macros_type_and_value.x64.asm @@ -11,29 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - jmp - movl $0x15, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x16, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0xa, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0xb, %eax - addq $0x10, %rsp - popq %rbp - retq movl $0x1, %edx xorq %rdx, %rdx testq %rdx, %rdx @@ -42,11 +19,17 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1e, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp + movl $0x15, %eax + retq + movl $0x16, %eax + retq + movl $0xa, %eax + retq + movl $0xb, %eax + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/stdint_widths.aarch64.asm b/tests/snapshots/asm/stdint_widths.aarch64.asm index 0541d20b0..19a6b9910 100644 --- a/tests/snapshots/asm/stdint_widths.aarch64.asm +++ b/tests/snapshots/asm/stdint_widths.aarch64.asm @@ -10,145 +10,84 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] - b + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 + mov x0, #0x2a // =42 + stur w0, [x29, #-0x18] + sub x0, x29, #0x18 + ldrsw x0, [x0] + cmp x0, #0x2a + b.eq + mov x0, #0x17 // =23 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0xd // =13 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0xe // =14 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0xf // =15 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - b mov x0, #0x10 // =16 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x7788 // =30600 - movk x0, #0x5566, lsl #16 - movk x0, #0x3344, lsl #32 - movk x0, #0x1122, lsl #48 - mov x17, #0x7788 // =30600 - movk x17, #0x5566, lsl #16 - movk x17, #0x3344, lsl #32 - movk x17, #0x1122, lsl #48 - cmp x0, x17 - b.eq + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret mov x0, #0x15 // =21 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x3210 // =12816 - movk x0, #0x7654, lsl #16 - movk x0, #0xba98, lsl #32 - movk x0, #0xfedc, lsl #48 - mov x17, #0x3210 // =12816 - movk x17, #0x7654, lsl #16 - movk x17, #0xba98, lsl #32 - movk x17, #0xfedc, lsl #48 - cmp x0, x17 - b.eq + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret mov x0, #0x16 // =22 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret - mov x0, #0x2a // =42 - stur w0, [x29, #-0x18] - sub x0, x29, #0x18 - ldrsw x0, [x0] - cmp x0, #0x2a - b.eq - mov x0, #0x17 // =23 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - sxtw x0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x18 // =24 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret diff --git a/tests/snapshots/asm/stdint_widths.x64.asm b/tests/snapshots/asm/stdint_widths.x64.asm index d272661d1..540674137 100644 --- a/tests/snapshots/asm/stdint_widths.x64.asm +++ b/tests/snapshots/asm/stdint_widths.x64.asm @@ -14,105 +14,81 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x50, %rsp - jmp + movl $0x2a, %eax + movl %eax, -0x18(%rbp) + leaq -0x18(%rbp), %rax + movslq (%rax), %rax + cmpq $0x2a, %rax + je + movl $0x17, %eax + addq $0x50, %rsp + popq %rbp + retq + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + addq $0x50, %rsp + popq %rbp + retq movl $0x1, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x2, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x3, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x4, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x5, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x6, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0xb, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0xc, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0xd, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0xe, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0xf, %eax addq $0x50, %rsp popq %rbp retq - jmp movl $0x10, %eax addq $0x50, %rsp popq %rbp retq - movabsq $0x1122334455667788, %rax # imm = 0x1122334455667788 - movabsq $0x1122334455667788, %r11 # imm = 0x1122334455667788 - cmpq %r11, %rax - je movl $0x15, %eax addq $0x50, %rsp popq %rbp retq - movabsq $-0x123456789abcdf0, %rax # imm = 0xFEDCBA9876543210 - movabsq $-0x123456789abcdf0, %r11 # imm = 0xFEDCBA9876543210 - cmpq %r11, %rax - je movl $0x16, %eax addq $0x50, %rsp popq %rbp retq - movl $0x2a, %eax - movl %eax, -0x18(%rbp) - leaq -0x18(%rbp), %rax - movslq (%rax), %rax - cmpq $0x2a, %rax - je - movl $0x17, %eax - addq $0x50, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - movslq %eax, %rax - cmpq $-0x1, %rax - je movl $0x18, %eax addq $0x50, %rsp popq %rbp retq - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax - addq $0x50, %rsp - popq %rbp - retq diff --git a/tests/snapshots/asm/stdio_fgetpos_roundtrip.aarch64.asm b/tests/snapshots/asm/stdio_fgetpos_roundtrip.aarch64.asm index 7d2322188..41194c947 100644 --- a/tests/snapshots/asm/stdio_fgetpos_roundtrip.aarch64.asm +++ b/tests/snapshots/asm/stdio_fgetpos_roundtrip.aarch64.asm @@ -10,20 +10,18 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] + str x20, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 bl mov x20, x0 cmp x20, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret adrp x0, add x0, x0, @@ -33,10 +31,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret sub x1, x29, #0x18 mov x0, x20 @@ -45,10 +42,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret adrp x0, add x0, x0, @@ -58,10 +54,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret sub x1, x29, #0x18 mov x0, x20 @@ -70,27 +65,24 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret mov x0, x20 bl cmp x0, #0xb b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret mov x0, x20 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x60 ret diff --git a/tests/snapshots/asm/store_forward_local_slot.aarch64.asm b/tests/snapshots/asm/store_forward_local_slot.aarch64.asm new file mode 100644 index 000000000..0622ee7b8 --- /dev/null +++ b/tests/snapshots/asm/store_forward_local_slot.aarch64.asm @@ -0,0 +1,127 @@ + +store_forward_local_slot.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur w0, [x29, #0x10] + adr x1, + stur x1, [x29, #-0x8] + sxtw x0, w0 + mov x17, #0x3 // =3 + mul x0, x0, x17 + stur w0, [x29, #-0x10] + sxtw x0, w0 + add x0, x0, x0 + stur w0, [x29, #-0x18] + br x1 + ldursw x0, [x29, #-0x18] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur w0, [x29, #0x10] + adr x1, + stur x1, [x29, #-0x8] + sxtw x0, w0 + stur w0, [x29, #-0x10] + ldursw x0, [x29, #-0x10] + stur w0, [x29, #-0x18] + br x1 + ldursw x0, [x29, #-0x18] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur w0, [x29, #0x10] + adr x1, + stur x1, [x29, #-0x8] + sub x2, x29, #0x10 + stur x2, [x29, #-0x18] + sxtw x0, w0 + stur w0, [x29, #-0x10] + add x0, x0, #0x1 + str w0, [x2] + ldursw x0, [x29, #-0x10] + stur w0, [x29, #-0x20] + br x1 + ldursw x0, [x29, #-0x20] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + stur w0, [x29, #0x10] + adr x1, + stur x1, [x29, #-0x8] + sxtw x0, w0 + lsl x0, x0, #1 + stur w0, [x29, #-0x10] + br x1 + ldursw x0, [x29, #-0x10] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x5 // =5 + bl + cmp x0, #0x1e + b.eq + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x7 // =7 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x9 // =9 + bl + cmp x0, #0xa + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x6 // =6 + bl + cmp x0, #0xc + b.eq + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/store_forward_local_slot.x64.asm b/tests/snapshots/asm/store_forward_local_slot.x64.asm new file mode 100644 index 000000000..fac8f71cc --- /dev/null +++ b/tests/snapshots/asm/store_forward_local_slot.x64.asm @@ -0,0 +1,149 @@ + +store_forward_local_slot.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax # + movq %rax, -0x8(%rbp) + movslq %edi, %rcx + leaq (%rcx,%rcx,2), %rcx + movl %ecx, -0x10(%rbp) + movslq %ecx, %rcx + addq %rcx, %rcx + movl %ecx, -0x18(%rbp) + jmpq *%rax + movslq -0x18(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax # + movq %rax, -0x8(%rbp) + movslq %edi, %rcx + movl %ecx, -0x10(%rbp) + movslq -0x10(%rbp), %rcx + movl %ecx, -0x18(%rbp) + jmpq *%rax + movslq -0x18(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax # + movq %rax, -0x8(%rbp) + leaq -0x10(%rbp), %rcx + movq %rcx, -0x18(%rbp) + movslq %edi, %rdx + movl %edx, -0x10(%rbp) + incq %rdx + movl %edx, (%rcx) + movslq -0x10(%rbp), %rcx + movl %ecx, -0x20(%rbp) + jmpq *%rax + movslq -0x20(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax # + movq %rax, -0x8(%rbp) + movslq %edi, %rcx + shlq $0x1, %rcx + movl %ecx, -0x10(%rbp) + jmpq *%rax + movslq -0x10(%rbp), %rax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + movl $0x5, %edi + callq + cmpq $0x1e, %rax + je + movl $0x1, %eax + popq %rbp + retq + movl $0x7, %edi + callq + cmpq $0x7, %rax + je + movl $0x2, %eax + popq %rbp + retq + movl $0x9, %edi + callq + cmpq $0xa, %rax + je + movl $0x3, %eax + popq %rbp + retq + movl $0x6, %edi + callq + cmpq $0xc, %rax + je + movl $0x4, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/store_to_load_forward.aarch64.asm b/tests/snapshots/asm/store_to_load_forward.aarch64.asm index 73af58e66..ffb7352c4 100644 --- a/tests/snapshots/asm/store_to_load_forward.aarch64.asm +++ b/tests/snapshots/asm/store_to_load_forward.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 str x1, [x0] str w2, [x0, #0x8] strh w2, [x0, #0xc] @@ -31,8 +28,6 @@ Disassembly of section .text: mov x17, #0xff // =255 and x0, x0, x17 add x0, x1, x0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret : @@ -41,23 +36,18 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] - str x21, [sp, #0x8] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, x0 - mov x21, #0x0 // =0 str x1, [x20] mov x0, x20 bl - add x0, x21, x0 + add x0, x0, #0x0 ldr x1, [x20] add x0, x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/store_to_load_forward.x64.asm b/tests/snapshots/asm/store_to_load_forward.x64.asm index d288098b7..b9ba0736d 100644 --- a/tests/snapshots/asm/store_to_load_forward.x64.asm +++ b/tests/snapshots/asm/store_to_load_forward.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movq %rsi, (%rdi) movl %edx, 0x8(%rdi) movw %dx, 0xc(%rdi) @@ -32,8 +29,6 @@ Disassembly of section .text: movq %rdi, %rcx andq $0xff, %rcx addq %rcx, %rax - addq $0x30, %rsp - popq %rbp retq : @@ -44,20 +39,17 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) movq %rdi, %rbx - xorq %r12, %r12 movq %rsi, (%rbx) movq %rbx, %rdi callq - addq %r12, %rax + addq $0x0, %rax movq (%rbx), %rcx addq %rcx, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/strength_reduce_pow2_divmod.aarch64.asm b/tests/snapshots/asm/strength_reduce_pow2_divmod.aarch64.asm index 08ac89d65..e2047b200 100644 --- a/tests/snapshots/asm/strength_reduce_pow2_divmod.aarch64.asm +++ b/tests/snapshots/asm/strength_reduce_pow2_divmod.aarch64.asm @@ -210,15 +210,16 @@ Disassembly of section .text: movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 stur x0, [x29, #-0x38] - ldur x1, [x29, #-0x38] - asr x2, x1, #63 - lsr x2, x2, #54 - add x1, x1, x2 - asr x1, x1, #10 - mov x2, #0x3ff // =1023 - add x0, x0, x2 + ldur x0, [x29, #-0x38] + asr x1, x0, #63 + lsr x1, x1, #54 + add x0, x0, x1 asr x0, x0, #10 - cmp x1, x0 + mov x17, #0xfb4b // =64331 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 cset x1, ne cbnz x1, ldur x0, [x29, #-0x38] @@ -228,16 +229,11 @@ Disassembly of section .text: mov x17, #0x3ff // =1023 and x0, x0, x17 sub x0, x0, x1 - mov x1, #0x2979 // =10617 - movk x1, #0xffed, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - mov x2, #0x3ff // =1023 - add x1, x1, x2 - mov x17, #0x3ff // =1023 - and x1, x1, x17 - sub x1, x1, x2 - cmp x0, x1 + mov x17, #0xfd79 // =64889 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 cset x1, ne cbz x1, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/strength_reduce_pow2_divmod.x64.asm b/tests/snapshots/asm/strength_reduce_pow2_divmod.x64.asm index 3202a769c..d114f1103 100644 --- a/tests/snapshots/asm/strength_reduce_pow2_divmod.x64.asm +++ b/tests/snapshots/asm/strength_reduce_pow2_divmod.x64.asm @@ -201,16 +201,13 @@ Disassembly of section .text: retq movabsq $-0x12d687, %rax # imm = 0xFFED2979 movq %rax, -0x38(%rbp) - movq -0x38(%rbp), %rcx - movq %rcx, %rdx - sarq $0x3f, %rdx - shrq $0x36, %rdx - addq %rdx, %rcx - sarq $0xa, %rcx - movl $0x3ff, %edx # imm = 0x3FF - addq %rdx, %rax + movq -0x38(%rbp), %rax + movq %rax, %rcx + sarq $0x3f, %rcx + shrq $0x36, %rcx + addq %rcx, %rax sarq $0xa, %rax - cmpq %rax, %rcx + cmpq $-0x4b5, %rax # imm = 0xFB4B setne %cl movzbq %cl, %rcx testq %rcx, %rcx @@ -222,12 +219,7 @@ Disassembly of section .text: addq %rcx, %rax andq $0x3ff, %rax # imm = 0x3FF subq %rcx, %rax - movabsq $-0x12d687, %rcx # imm = 0xFFED2979 - movl $0x3ff, %edx # imm = 0x3FF - addq %rdx, %rcx - andq $0x3ff, %rcx # imm = 0x3FF - subq %rdx, %rcx - cmpq %rcx, %rax + cmpq $-0x287, %rax # imm = 0xFD79 setne %cl movzbq %cl, %rcx testq %rcx, %rcx @@ -321,4 +313,3 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/stringize_whitespace.aarch64.asm b/tests/snapshots/asm/stringize_whitespace.aarch64.asm index 95d6ebc60..be788aae2 100644 --- a/tests/snapshots/asm/stringize_whitespace.aarch64.asm +++ b/tests/snapshots/asm/stringize_whitespace.aarch64.asm @@ -10,23 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x2, x0 ldrb w0, [x2] mov x4, #0x0 // =0 cbz x0, - b - add x2, x2, #0x1 - add x1, x1, #0x1 - b - ldrb w0, [x2] - cmp x0, #0x0 - cset x0, eq - mov x3, #0x0 // =0 - cbz x0, - b ldrb w0, [x1] cmp x0, #0x0 cset x4, ne @@ -36,19 +23,24 @@ Disassembly of section .text: cmp x0, x3 cset x4, eq cbz x4, + add x2, x2, #0x1 + add x1, x1, #0x1 + b b + b + ldrb w0, [x2] + cmp x0, #0x0 + cset x0, eq + mov x3, #0x0 // =0 + cbz x0, ldrb w0, [x1] cmp x0, #0x0 cset x0, eq cmp x0, #0x0 cset x3, ne mov x0, x3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b - b - b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/stringize_whitespace.x64.asm b/tests/snapshots/asm/stringize_whitespace.x64.asm index 574658b4f..1d3543aa5 100644 --- a/tests/snapshots/asm/stringize_whitespace.x64.asm +++ b/tests/snapshots/asm/stringize_whitespace.x64.asm @@ -11,25 +11,10 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movsbq (%rdi), %rax - xorq %rdx, %rdx - testq %rax, %rax - je - jmp - incq %rdi - incq %rsi - jmp movsbq (%rdi), %rax - testq %rax, %rax - sete %al - movzbq %al, %rax xorq %rdx, %rdx testq %rax, %rax je - jmp movsbq (%rsi), %rax testq %rax, %rax setne %dl @@ -43,7 +28,18 @@ Disassembly of section .text: movzbq %dl, %rdx testq %rdx, %rdx je + incq %rdi + incq %rsi + jmp + jmp jmp + movsbq (%rdi), %rax + testq %rax, %rax + sete %al + movzbq %al, %rax + xorq %rdx, %rdx + testq %rax, %rax + je movsbq (%rsi), %rax testq %rax, %rax sete %al @@ -52,12 +48,8 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x20, %rsp - popq %rbp retq jmp - jmp - jmp
: pushq %rbp @@ -122,3 +114,4 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/strtof_parses_float.aarch64.asm b/tests/snapshots/asm/strtof_parses_float.aarch64.asm index e30344a8e..c94206798 100644 --- a/tests/snapshots/asm/strtof_parses_float.aarch64.asm +++ b/tests/snapshots/asm/strtof_parses_float.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x40]! + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 adrp x0, add x0, x0, sub x1, x29, #0x8 @@ -24,9 +23,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret ldur x0, [x29, #-0x8] ldrb w0, [x0] @@ -36,9 +34,8 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret adrp x0, add x0, x0, @@ -51,12 +48,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 ret diff --git a/tests/snapshots/asm/strtold_aapcs_return.aarch64.asm b/tests/snapshots/asm/strtold_aapcs_return.aarch64.asm index 955bc6b86..b4fc5018c 100644 --- a/tests/snapshots/asm/strtold_aapcs_return.aarch64.asm +++ b/tests/snapshots/asm/strtold_aapcs_return.aarch64.asm @@ -10,12 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str d8, [sp] + str d8, [sp, #-0xa0]! str x20, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 adrp x0, add x0, x0, mov x20, #0x0 // =0 @@ -34,11 +33,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret mov x0, #0x43f0000000000000 // =4895412794951729152 fmov d17, x0 @@ -46,11 +44,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret adrp x0, add x0, x0, @@ -64,11 +61,10 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret sub x0, x29, #0x38 adrp x1, @@ -80,11 +76,10 @@ Disassembly of section .text: cmp x0, #0x0 b.gt mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret sub x0, x29, #0x38 ldrb w0, [x0] @@ -94,16 +89,14 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x20] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp, #0x10] + ldr d8, [sp], #0xa0 ret diff --git a/tests/snapshots/asm/strtoul_64bit_return.aarch64.asm b/tests/snapshots/asm/strtoul_64bit_return.aarch64.asm index 675319333..f7b395267 100644 --- a/tests/snapshots/asm/strtoul_64bit_return.aarch64.asm +++ b/tests/snapshots/asm/strtoul_64bit_return.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 adrp x0, add x0, x0, sub x1, x29, #0x8 @@ -23,9 +22,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret adrp x0, add x0, x0, @@ -36,9 +34,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret adrp x0, add x0, x0, @@ -49,9 +46,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret adrp x0, add x0, x0, @@ -64,12 +60,10 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret diff --git a/tests/snapshots/asm/struct_2d_array_field.aarch64.asm b/tests/snapshots/asm/struct_2d_array_field.aarch64.asm index 797e41b21..e99eab7c1 100644 --- a/tests/snapshots/asm/struct_2d_array_field.aarch64.asm +++ b/tests/snapshots/asm/struct_2d_array_field.aarch64.asm @@ -14,63 +14,69 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x50 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x3 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x30 + lsl x3, x0, #4 + add x2, x2, x3 + add x2, x2, #0x0 + mov x17, #0xa // =10 + mul x3, x0, x17 + add x3, x3, #0x0 + str w3, [x2] + sub x2, x29, #0x30 + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0xa // =10 + mul x3, x0, x17 + add x3, x3, #0x1 + str w3, [x2, #0x4] + sub x2, x29, #0x30 + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0xa // =10 + mul x3, x0, x17 + add x3, x3, #0x2 + str w3, [x2, #0x8] + sub x2, x29, #0x30 + lsl x3, x0, #4 + add x2, x2, x3 + mov x17, #0xa // =10 + mul x3, x0, x17 + add x3, x3, #0x3 + str w3, [x2, #0xc] add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + sxtw x0, w1 + cmp x0, #0x3 + b.lt sub x0, x29, #0x30 mov x2, #0x0 // =0 mov x1, x2 b - sxtw x0, w2 - cmp x0, #0x4 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x30 - sxtw x3, w1 lsl x4, x3, #4 - add x0, x0, x4 - sxtw x4, w2 - mov x17, #0xa // =10 - mul x3, x3, x17 - add x3, x3, x4 - str w3, [x0, x4, lsl #2] - b - b + add x4, x0, x4 + add x4, x4, #0x0 + ldrsw x4, [x4] + add x2, x2, x4 + lsl x4, x3, #4 + add x4, x0, x4 + ldrsw x4, [x4, #0x4] + add x2, x2, x4 + lsl x4, x3, #4 + add x4, x0, x4 + ldrsw x4, [x4, #0x8] + add x2, x2, x4 + lsl x4, x3, #4 + add x4, x0, x4 + ldrsw x4, [x4, #0xc] + add x2, x2, x4 + add x1, x3, #0x1 sxtw x3, w1 cmp x3, #0x3 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - mov x4, #0x0 // =0 - b + b.lt sub x0, x2, #0x6f sxtw x0, w0 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - sxtw x3, w4 - cmp x3, #0x4 - b.ge - b - sxtw x3, w4 - add x4, x3, #0x1 - b - sxtw x3, w1 - lsl x3, x3, #4 - add x3, x0, x3 - sxtw x5, w4 - ldrsw x3, [x3, x5, lsl #2] - add x2, x2, x3 b b diff --git a/tests/snapshots/asm/struct_2d_array_field.x64.asm b/tests/snapshots/asm/struct_2d_array_field.x64.asm index f51195795..99bdd252a 100644 --- a/tests/snapshots/asm/struct_2d_array_field.x64.asm +++ b/tests/snapshots/asm/struct_2d_array_field.x64.asm @@ -15,63 +15,74 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x50, %rsp xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x3, %rax - jge jmp - movslq %ecx, %rax + leaq -0x30(%rbp), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + addq $0x0, %rdx + imulq $0xa, %rax, %rsi + addq $0x0, %rsi + movl %esi, (%rdx) + leaq -0x30(%rbp), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0xa, %rax, %rsi + incq %rsi + movl %esi, 0x4(%rdx) + leaq -0x30(%rbp), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0xa, %rax, %rsi + addq $0x2, %rsi + movl %esi, 0x8(%rdx) + leaq -0x30(%rbp), %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + imulq $0xa, %rax, %rsi + addq $0x3, %rsi + movl %esi, 0xc(%rdx) leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + movslq %ecx, %rax + cmpq $0x3, %rax + jl leaq -0x30(%rbp), %rax xorq %rdx, %rdx movq %rdx, %rcx jmp - movslq %edx, %rax - cmpq $0x4, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x30(%rbp), %rax - movslq %ecx, %rsi movq %rsi, %rdi shlq $0x4, %rdi - addq %rdi, %rax - movslq %edx, %rdi - imulq $0xa, %rsi, %rsi - addq %rdi, %rsi - movl %esi, (%rax,%rdi,4) - jmp - jmp + addq %rax, %rdi + addq $0x0, %rdi + movslq (%rdi), %rdi + addq %rdi, %rdx + movq %rsi, %rdi + shlq $0x4, %rdi + addq %rax, %rdi + movslq 0x4(%rdi), %rdi + addq %rdi, %rdx + movq %rsi, %rdi + shlq $0x4, %rdi + addq %rax, %rdi + movslq 0x8(%rdi), %rdi + addq %rdi, %rdx + movq %rsi, %rdi + shlq $0x4, %rdi + addq %rax, %rdi + movslq 0xc(%rdi), %rdi + addq %rdi, %rdx + leaq 0x1(%rsi), %rcx movslq %ecx, %rsi cmpq $0x3, %rsi - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - xorq %rdi, %rdi - jmp + jl leaq -0x6f(%rdx), %rax movslq %eax, %rax addq $0x50, %rsp popq %rbp retq - movslq %edi, %rsi - cmpq $0x4, %rsi - jge - jmp - movslq %edi, %rsi - leaq 0x1(%rsi), %rdi - jmp - movslq %ecx, %rsi - shlq $0x4, %rsi - addq %rax, %rsi - movslq %edi, %r8 - movslq (%rsi,%r8,4), %rsi - addq %rsi, %rdx jmp jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/struct_arg_by_stack.aarch64.asm b/tests/snapshots/asm/struct_arg_by_stack.aarch64.asm index 847b6874b..47d1ac021 100644 --- a/tests/snapshots/asm/struct_arg_by_stack.aarch64.asm +++ b/tests/snapshots/asm/struct_arg_by_stack.aarch64.asm @@ -115,9 +115,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x21, [sp, #0x8] + sub sp, sp, #0x70 sub x0, x29, #0x20 mov x1, #0xb // =11 str x1, [x0] @@ -148,9 +146,7 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -158,7 +154,7 @@ Disassembly of section .text: ldr x0, [x0] cmp x0, #0xb cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, adrp x0, add x0, x0, @@ -166,45 +162,41 @@ Disassembly of section .text: cmp x0, #0x16 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x21 cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x2c - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x5 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr x0, [x0] cmp x0, #0x6 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 @@ -212,9 +204,7 @@ Disassembly of section .text: cmp x0, #0x455 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 @@ -228,15 +218,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x80 + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/struct_arg_by_stack.x64.asm b/tests/snapshots/asm/struct_arg_by_stack.x64.asm index a76b04f2c..ef2d39c65 100644 --- a/tests/snapshots/asm/struct_arg_by_stack.x64.asm +++ b/tests/snapshots/asm/struct_arg_by_stack.x64.asm @@ -106,9 +106,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) + subq $0x70, %rsp leaq -0x20(%rbp), %rax movl $0xb, %ecx movq %rcx, (%rax) @@ -150,9 +148,7 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq leaq , %rax @@ -160,7 +156,7 @@ Disassembly of section .text: cmpq $0xb, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq , %rax @@ -169,10 +165,10 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq , %rax movq (%rax), %rax @@ -180,41 +176,37 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movq (%rax), %rax cmpq $0x2c, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax cmpq $0x5, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movq (%rax), %rax cmpq $0x6, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq leaq -0x20(%rbp), %rdi @@ -233,9 +225,7 @@ Disassembly of section .text: cmpq $0x455, %rax # imm = 0x455 je movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -253,15 +243,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x70, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/struct_arg_in_registers.aarch64.asm b/tests/snapshots/asm/struct_arg_in_registers.aarch64.asm index e3d1a1f08..dcb84e5d5 100644 --- a/tests/snapshots/asm/struct_arg_in_registers.aarch64.asm +++ b/tests/snapshots/asm/struct_arg_in_registers.aarch64.asm @@ -261,20 +261,16 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x9 // =9 - sub x1, x29, #0x8 - mov x2, #0x2 // =2 - ldrsw x3, [x1] + sub x0, x29, #0x8 + ldrsw x1, [x0] mov x17, #0xa // =10 - mul x3, x3, x17 - add x0, x0, x3 - ldrsw x1, [x1, #0x4] - mov x17, #0x64 // =100 mul x1, x1, x17 - add x0, x0, x1 - mov x17, #0x3e8 // =1000 - mul x1, x2, x17 - add x0, x0, x1 + add x1, x1, #0x9 + ldrsw x0, [x0, #0x4] + mov x17, #0x64 // =100 + mul x0, x0, x17 + add x0, x1, x0 + add x0, x0, #0x7d0 sxtw x0, w0 cmp x0, #0x9eb b.eq diff --git a/tests/snapshots/asm/struct_arg_in_registers.x64.asm b/tests/snapshots/asm/struct_arg_in_registers.x64.asm index 62695f792..8c86e72ab 100644 --- a/tests/snapshots/asm/struct_arg_in_registers.x64.asm +++ b/tests/snapshots/asm/struct_arg_in_registers.x64.asm @@ -275,17 +275,14 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x9, %eax - leaq -0x8(%rbp), %rcx - movl $0x2, %edx - movslq (%rcx), %rsi - imulq $0xa, %rsi, %rsi - addq %rsi, %rax - movslq 0x4(%rcx), %rcx - imulq $0x64, %rcx, %rcx - addq %rcx, %rax - imulq $0x3e8, %rdx, %rcx # imm = 0x3E8 + leaq -0x8(%rbp), %rax + movslq (%rax), %rcx + imulq $0xa, %rcx, %rcx + addq $0x9, %rcx + movslq 0x4(%rax), %rax + imulq $0x64, %rax, %rax addq %rcx, %rax + addq $0x7d0, %rax # imm = 0x7D0 movslq %eax, %rax cmpq $0x9eb, %rax # imm = 0x9EB je @@ -349,5 +346,3 @@ Disassembly of section .text: popq %rbp retq jmp - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_arg_indirect_subscript.aarch64.asm b/tests/snapshots/asm/struct_arg_indirect_subscript.aarch64.asm index c3147bdf4..58491c680 100644 --- a/tests/snapshots/asm/struct_arg_indirect_subscript.aarch64.asm +++ b/tests/snapshots/asm/struct_arg_indirect_subscript.aarch64.asm @@ -34,18 +34,18 @@ Disassembly of section .text: add x1, x1, x3 cbz x0, mov x3, #0x0 // =0 - b - mov x3, #0x0 // =0 add x0, x1, x3 cbz x2, mov x2, #0x1 // =1 - b - mov x2, #0x0 // =0 add x0, x0, x2 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 add sp, sp, #0x40 ret + mov x2, #0x0 // =0 + b + mov x3, #0x0 // =0 + b : sub sp, sp, #0x10 @@ -79,10 +79,9 @@ Disassembly of section .text: sub sp, sp, #0x20 sub sp, sp, #0x10 sub sp, sp, #0x20 - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x16, x29, #0x10 str x2, [x16] str x3, [x16, #0x8] @@ -96,9 +95,8 @@ Disassembly of section .text: ldr x2, [x1, #0x8] ldr x1, [x1] blr x9 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0x50 ret @@ -106,10 +104,9 @@ Disassembly of section .text: sub sp, sp, #0x10 sub sp, sp, #0x10 sub sp, sp, #0x10 - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x40]! + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 sub x16, x29, #0x10 str d0, [x16] str d1, [x16, #0x8] @@ -121,9 +118,8 @@ Disassembly of section .text: ldr d1, [x1, #0x8] mov x0, x2 blr x9 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 add sp, sp, #0x30 ret @@ -193,28 +189,79 @@ Disassembly of section .text: sub x0, x29, #0x98 mov x1, #0x0 // =0 str x1, [x0] - sxtw x0, w1 - cmp x0, #0x8 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b sub x0, x29, #0x98 add x0, x0, #0x8 - sxtw x2, w1 - lsl x3, x2, #4 - add x0, x0, x3 - add x2, x2, #0x1 - sxtw x2, w2 - str x2, [x0] + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str x1, [x0] sub x0, x29, #0x98 add x0, x0, #0x8 - sxtw x2, w1 - lsl x3, x2, #4 - add x0, x0, x3 - str x2, [x0, #0x8] - b + mov x1, #0x0 // =0 + add x0, x0, #0x0 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x2 // =2 + str x1, [x0, #0x10] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x1 // =1 + add x0, x0, #0x10 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x3 // =3 + str x1, [x0, #0x20] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x2 // =2 + add x0, x0, #0x20 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x4 // =4 + str x1, [x0, #0x30] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x3 // =3 + add x0, x0, #0x30 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x5 // =5 + str x1, [x0, #0x40] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x4 // =4 + add x0, x0, #0x40 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x6 // =6 + str x1, [x0, #0x50] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x5 // =5 + add x0, x0, #0x50 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x7 // =7 + str x1, [x0, #0x60] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x6 // =6 + add x0, x0, #0x60 + str x1, [x0, #0x8] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x8 // =8 + str x1, [x0, #0x70] + sub x0, x29, #0x98 + add x0, x0, #0x8 + mov x1, #0x7 // =7 + add x0, x0, #0x70 + str x1, [x0, #0x8] sub x0, x29, #0x98 mov x1, #0x3 // =3 bl diff --git a/tests/snapshots/asm/struct_arg_indirect_subscript.x64.asm b/tests/snapshots/asm/struct_arg_indirect_subscript.x64.asm index 8573b6e09..1d4c80674 100644 --- a/tests/snapshots/asm/struct_arg_indirect_subscript.x64.asm +++ b/tests/snapshots/asm/struct_arg_indirect_subscript.x64.asm @@ -33,14 +33,10 @@ Disassembly of section .text: testq %rdi, %rdi je xorq %rsi, %rsi - jmp - xorq %rsi, %rsi addq %rsi, %rax testq %rdx, %rdx je movl $0x1, %edx - jmp - xorq %rdx, %rdx addq %rdx, %rax addq $0x20, %rsp popq %rbp @@ -48,6 +44,10 @@ Disassembly of section .text: addq $0x40, %rsp pushq %r11 retq + xorq %rdx, %rdx + jmp + xorq %rsi, %rsi + jmp : popq %r10 @@ -195,30 +195,79 @@ Disassembly of section .text: leaq -0x98(%rbp), %rax xorq %rcx, %rcx movq %rcx, (%rax) - movslq %ecx, %rax - cmpq $0x8, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp leaq -0x98(%rbp), %rax addq $0x8, %rax - movslq %ecx, %rdx - movq %rdx, %rsi - shlq $0x4, %rsi - addq %rsi, %rax - incq %rdx - movslq %edx, %rdx - movq %rdx, (%rax) + addq $0x0, %rax + movl $0x1, %ecx + movq %rcx, (%rax) leaq -0x98(%rbp), %rax addq $0x8, %rax - movslq %ecx, %rdx - movq %rdx, %rsi - shlq $0x4, %rsi - addq %rsi, %rax - movq %rdx, 0x8(%rax) - jmp + xorq %rcx, %rcx + addq $0x0, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x2, %ecx + movq %rcx, 0x10(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x1, %ecx + addq $0x10, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x3, %ecx + movq %rcx, 0x20(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x2, %ecx + addq $0x20, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x4, %ecx + movq %rcx, 0x30(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x3, %ecx + addq $0x30, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x5, %ecx + movq %rcx, 0x40(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x4, %ecx + addq $0x40, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x6, %ecx + movq %rcx, 0x50(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x5, %ecx + addq $0x50, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x7, %ecx + movq %rcx, 0x60(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x6, %ecx + addq $0x60, %rax + movq %rcx, 0x8(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x8, %ecx + movq %rcx, 0x70(%rax) + leaq -0x98(%rbp), %rax + addq $0x8, %rax + movl $0x7, %ecx + addq $0x70, %rax + movq %rcx, 0x8(%rax) leaq -0x98(%rbp), %rdi movl $0x3, %esi callq diff --git a/tests/snapshots/asm/struct_arg_two_eightbyte.aarch64.asm b/tests/snapshots/asm/struct_arg_two_eightbyte.aarch64.asm index 87cb23a89..fe2442f5d 100644 --- a/tests/snapshots/asm/struct_arg_two_eightbyte.aarch64.asm +++ b/tests/snapshots/asm/struct_arg_two_eightbyte.aarch64.asm @@ -93,8 +93,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] + sub sp, sp, #0x60 sub x0, x29, #0x8 mov x1, #0x9 // =9 str w1, [x0] @@ -125,8 +124,7 @@ Disassembly of section .text: cmp x0, #0x9 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -134,8 +132,8 @@ Disassembly of section .text: ldr x0, [x0] mov x17, #0x1111 // =4369 cmp x0, x17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr w0, [x0] @@ -143,11 +141,10 @@ Disassembly of section .text: eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -155,8 +152,8 @@ Disassembly of section .text: ldr x0, [x0] mov x17, #0x2222 // =8738 cmp x0, x17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldr w0, [x0] @@ -164,11 +161,10 @@ Disassembly of section .text: eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x18 @@ -196,8 +192,7 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -217,13 +212,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x70 + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/struct_arg_two_eightbyte.x64.asm b/tests/snapshots/asm/struct_arg_two_eightbyte.x64.asm index 0d1d8f15c..b93f53f9c 100644 --- a/tests/snapshots/asm/struct_arg_two_eightbyte.x64.asm +++ b/tests/snapshots/asm/struct_arg_two_eightbyte.x64.asm @@ -86,8 +86,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) + subq $0x60, %rsp leaq -0x8(%rbp), %rax movl $0x9, %ecx movl %ecx, (%rax) @@ -117,50 +116,47 @@ Disassembly of section .text: cmpq $0x9, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax cmpq $0x1111, %rax # imm = 0x1111 - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movl (%rax), %eax xorq $0x4, %rax movl %eax, %eax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax cmpq $0x2222, %rax # imm = 0x2222 - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movl (%rax), %eax xorq $0x6, %rax movl %eax, %eax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq -0x18(%rbp), %rdi @@ -188,8 +184,7 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq leaq , %rax @@ -209,17 +204,15 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq jmp jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_array_designator.aarch64.asm b/tests/snapshots/asm/struct_array_designator.aarch64.asm index 388d9e0ff..c81d2ad0e 100644 --- a/tests/snapshots/asm/struct_array_designator.aarch64.asm +++ b/tests/snapshots/asm/struct_array_designator.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 adrp x0, add x0, x0, ldrsw x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x0 @@ -36,8 +31,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x10] cmp x1, #0x1e @@ -48,12 +41,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/struct_array_designator.x64.asm b/tests/snapshots/asm/struct_array_designator.x64.asm index 2d22032ba..e476e42ad 100644 --- a/tests/snapshots/asm/struct_array_designator.x64.asm +++ b/tests/snapshots/asm/struct_array_designator.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0xa, %rcx @@ -28,8 +25,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx testq %rcx, %rcx @@ -44,8 +39,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x10(%rax), %rcx cmpq $0x1e, %rcx @@ -60,13 +53,10 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/struct_array_elided_runtime.aarch64.asm b/tests/snapshots/asm/struct_array_elided_runtime.aarch64.asm index b817d05bd..95d14008a 100644 --- a/tests/snapshots/asm/struct_array_elided_runtime.aarch64.asm +++ b/tests/snapshots/asm/struct_array_elided_runtime.aarch64.asm @@ -153,31 +153,26 @@ Disassembly of section .text: b
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0x14 - b.ge b + mov x0, x20 + bl + cbnz x0, sxtw x0, w20 add x20, x0, #0x1 - b sxtw x0, w20 - bl - cbz x0, - b + cmp x0, #0x14 + b.lt mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret add x0, x20, #0x1 sxtw x0, w0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret b diff --git a/tests/snapshots/asm/struct_array_elided_runtime.x64.asm b/tests/snapshots/asm/struct_array_elided_runtime.x64.asm index c8b92d823..d6c5e1a4c 100644 --- a/tests/snapshots/asm/struct_array_elided_runtime.x64.asm +++ b/tests/snapshots/asm/struct_array_elided_runtime.x64.asm @@ -177,18 +177,16 @@ Disassembly of section .text: subq $0x10, %rsp movq %rbx, (%rsp) xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0x14, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp - movslq %ebx, %rdi + movq %rbx, %rdi callq testq %rax, %rax - je - jmp + jne + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0x14, %rax + jl xorq %rax, %rax movq (%rsp), %rbx addq $0x10, %rsp diff --git a/tests/snapshots/asm/struct_array_init_from_lvalue.x64.asm b/tests/snapshots/asm/struct_array_init_from_lvalue.x64.asm index 5f99080a6..c2b3d3b2a 100644 --- a/tests/snapshots/asm/struct_array_init_from_lvalue.x64.asm +++ b/tests/snapshots/asm/struct_array_init_from_lvalue.x64.asm @@ -298,4 +298,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_basic.aarch64.asm b/tests/snapshots/asm/struct_basic.aarch64.asm index 8a218408c..8e827fc8c 100644 --- a/tests/snapshots/asm/struct_basic.aarch64.asm +++ b/tests/snapshots/asm/struct_basic.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x8 // =8 bl mov x1, #0x3 // =3 @@ -28,7 +27,6 @@ Disassembly of section .text: mul x0, x0, x2 add x0, x1, x0 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/struct_basic.x64.asm b/tests/snapshots/asm/struct_basic.x64.asm index 2a5261475..1e985e4d7 100644 --- a/tests/snapshots/asm/struct_basic.x64.asm +++ b/tests/snapshots/asm/struct_basic.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp movl $0x8, %edi xorl %eax, %eax callq @@ -29,8 +28,6 @@ Disassembly of section .text: imulq %rdx, %rax addq %rcx, %rax movslq %eax, %rax - addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_by_value_return.aarch64.asm b/tests/snapshots/asm/struct_by_value_return.aarch64.asm index fd37fc5c9..4d08c2713 100644 --- a/tests/snapshots/asm/struct_by_value_return.aarch64.asm +++ b/tests/snapshots/asm/struct_by_value_return.aarch64.asm @@ -25,21 +25,10 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x1, #0xdead // =57005 - mov x2, #0xbeef // =48879 - mov x3, #0xcafe // =51966 - mov x4, #0xacef // =44271 - movk x4, #0xf, lsl #16 - add x1, x1, x2 - add x1, x1, x3 - add x1, x1, x4 - add x0, x1, x0 + mov x17, #0x1589 // =5513 + movk x17, #0x12, lsl #16 + add x0, x0, x17 sxtw x0, w0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret : @@ -90,24 +79,6 @@ Disassembly of section .text: ldr x10, [x1] str x10, [x0] ldr x10, [sp], #0x10 - mov x0, #0x7 // =7 - mov x1, #0xdead // =57005 - mov x2, #0xbeef // =48879 - mov x3, #0xcafe // =51966 - mov x4, #0xacef // =44271 - movk x4, #0xf, lsl #16 - add x1, x1, x2 - add x1, x1, x3 - add x1, x1, x4 - add x0, x1, x0 - sxtw x0, w0 - sxtw x0, w0 - cmp x0, #0x0 - b.ne - mov x0, #0x63 // =99 - add sp, sp, #0xc0 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 ldrsw x0, [x0] cmp x0, #0xb @@ -258,3 +229,7 @@ Disassembly of section .text: add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x63 // =99 + add sp, sp, #0xc0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/struct_by_value_return.x64.asm b/tests/snapshots/asm/struct_by_value_return.x64.asm index 36256e15e..9954f0d4f 100644 --- a/tests/snapshots/asm/struct_by_value_return.x64.asm +++ b/tests/snapshots/asm/struct_by_value_return.x64.asm @@ -26,20 +26,8 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xdead, %eax # imm = 0xDEAD - movl $0xbeef, %ecx # imm = 0xBEEF - movl $0xcafe, %edx # imm = 0xCAFE - movl $0xfacef, %esi # imm = 0xFACEF - addq %rcx, %rax - addq %rdx, %rax - addq %rsi, %rax - addq %rdi, %rax + leaq 0x121589(%rdi), %rax movslq %eax, %rax - addq $0x20, %rsp - popq %rbp retq : @@ -91,23 +79,6 @@ Disassembly of section .text: movq (%rcx), %rdx movq %rdx, (%rax) popq %rdx - movl $0x7, %eax - movl $0xdead, %ecx # imm = 0xDEAD - movl $0xbeef, %edx # imm = 0xBEEF - movl $0xcafe, %esi # imm = 0xCAFE - movl $0xfacef, %edi # imm = 0xFACEF - addq %rdx, %rcx - addq %rsi, %rcx - addq %rdi, %rcx - addq %rcx, %rax - movslq %eax, %rax - movslq %eax, %rax - testq %rax, %rax - jne - movl $0x63, %eax - addq $0xc0, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax movslq (%rax), %rax cmpq $0xb, %rax @@ -258,4 +229,8 @@ Disassembly of section .text: addq $0xc0, %rsp popq %rbp retq + movl $0x63, %eax + addq $0xc0, %rsp + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_byval_param_followed_by_ptr.aarch64.asm b/tests/snapshots/asm/struct_byval_param_followed_by_ptr.aarch64.asm index f5cbeda89..37831774b 100644 --- a/tests/snapshots/asm/struct_byval_param_followed_by_ptr.aarch64.asm +++ b/tests/snapshots/asm/struct_byval_param_followed_by_ptr.aarch64.asm @@ -53,12 +53,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x70]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -88,11 +86,9 @@ Disassembly of section .text: bl sxtw x0, w0 sxtw x0, w21 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x70 ret ldursw x0, [x29, #-0x18] cmp x0, #0x1 @@ -103,20 +99,16 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x70 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x70 ret diff --git a/tests/snapshots/asm/struct_copy_comma_side_effect.aarch64.asm b/tests/snapshots/asm/struct_copy_comma_side_effect.aarch64.asm index 2ab708180..3e6a2d1fd 100644 --- a/tests/snapshots/asm/struct_copy_comma_side_effect.aarch64.asm +++ b/tests/snapshots/asm/struct_copy_comma_side_effect.aarch64.asm @@ -76,11 +76,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, mov x0, #0x0 // =0 @@ -91,10 +89,8 @@ Disassembly of section .text: cmp x0, #0xf b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret adrp x21, add x21, x21, @@ -106,10 +102,8 @@ Disassembly of section .text: cmp x0, #0xf b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x0 // =0 str w0, [x20, #0x4] @@ -121,14 +115,10 @@ Disassembly of section .text: cmp x0, #0xf b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 ret diff --git a/tests/snapshots/asm/struct_deref_va_arg.aarch64.asm b/tests/snapshots/asm/struct_deref_va_arg.aarch64.asm index ae4927055..5e32c93e4 100644 --- a/tests/snapshots/asm/struct_deref_va_arg.aarch64.asm +++ b/tests/snapshots/asm/struct_deref_va_arg.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x19, [sp] + str x19, [sp, #-0x40]! + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -80,9 +79,8 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x20 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldr x19, [sp], #0x40 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/struct_field_assign_from_call.aarch64.asm b/tests/snapshots/asm/struct_field_assign_from_call.aarch64.asm index f41acf079..9ac64515b 100644 --- a/tests/snapshots/asm/struct_field_assign_from_call.aarch64.asm +++ b/tests/snapshots/asm/struct_field_assign_from_call.aarch64.asm @@ -17,23 +17,18 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 mov x20, x0 mov x21, x1 ldr x22, [x20, #0x8] ldr x23, [x20, #0x18] add x1, x20, #0x14 ldrsw x0, [x20, #0x10] - add x0, x0, #0x1 - sxtw x2, w0 + add x2, x0, #0x1 mov x24, #0x10 // =16 mov x25, #0x7fff // =32767 mov x0, x22 @@ -46,7 +41,6 @@ Disassembly of section .text: add x1, x20, #0x24 ldrsw x2, [x20, #0x20] add x2, x2, #0x1 - sxtw x2, w2 mov x3, x24 mov x5, x21 mov x4, x25 @@ -56,27 +50,19 @@ Disassembly of section .text: cmp x22, x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret ldr x0, [x20, #0x18] cmp x23, x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret ldr x0, [x20, #0x8] mov x17, #0xabcd // =43981 @@ -84,14 +70,10 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret ldr x0, [x20, #0x18] mov x17, #0xabcd // =43981 @@ -99,58 +81,41 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret ldrsw x0, [x20, #0x14] cmp x0, #0x4 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret ldrsw x0, [x20, #0x24] cmp x0, #0x4 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, adrp x1, @@ -173,18 +138,16 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/struct_field_assign_from_call.x64.asm b/tests/snapshots/asm/struct_field_assign_from_call.x64.asm index c52c770fc..8a8713079 100644 --- a/tests/snapshots/asm/struct_field_assign_from_call.x64.asm +++ b/tests/snapshots/asm/struct_field_assign_from_call.x64.asm @@ -19,7 +19,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp + subq $0x40, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -31,8 +31,7 @@ Disassembly of section .text: movq 0x18(%rbx), %r14 leaq 0x14(%rbx), %rsi movslq 0x10(%rbx), %rax - incq %rax - movslq %eax, %rdx + leaq 0x1(%rax), %rdx movl $0x10, %r15d movl $0x7fff, %r10d # imm = 0x7FFF movq %r10, 0x38(%rsp) @@ -45,8 +44,7 @@ Disassembly of section .text: movq 0x18(%rbx), %rdi leaq 0x24(%rbx), %rsi movslq 0x20(%rbx), %rax - incq %rax - movslq %eax, %rdx + leaq 0x1(%rax), %rdx movq %r15, %rcx movq %r12, %r9 movq 0x38(%rsp), %r8 @@ -61,7 +59,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq movq 0x18(%rbx), %rax @@ -73,7 +71,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq movq 0x8(%rbx), %rax @@ -85,7 +83,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq movq 0x18(%rbx), %rax @@ -97,7 +95,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq movslq 0x14(%rbx), %rax @@ -109,7 +107,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq movslq 0x24(%rbx), %rax @@ -121,7 +119,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq xorq %rax, %rax @@ -130,7 +128,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x80, %rsp + addq $0x40, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/struct_field_displacement.aarch64.asm b/tests/snapshots/asm/struct_field_displacement.aarch64.asm index 0697cfc90..eb1e2a013 100644 --- a/tests/snapshots/asm/struct_field_displacement.aarch64.asm +++ b/tests/snapshots/asm/struct_field_displacement.aarch64.asm @@ -57,10 +57,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x18 mov x20, #0x1 // =1 str w20, [x0] @@ -95,39 +94,34 @@ Disassembly of section .text: cmp x0, #0x64 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x20, [sp], #0x50 ret sub x0, x29, #0x18 ldr x0, [x0, #0x8] cmp x0, #0x313 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x20, [sp], #0x50 ret sub x0, x29, #0x18 ldrsh x0, [x0, #0x10] cmp x0, #0x2c b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x20, [sp], #0x50 ret sub x0, x29, #0x18 ldrb w0, [x0, #0x12] cmp x0, #0x6 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x20, [sp], #0x50 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x20, [sp], #0x50 ret diff --git a/tests/snapshots/asm/struct_fn_ptr_field_deref_call.aarch64.asm b/tests/snapshots/asm/struct_fn_ptr_field_deref_call.aarch64.asm index 6c039fc4b..28cb75e89 100644 --- a/tests/snapshots/asm/struct_fn_ptr_field_deref_call.aarch64.asm +++ b/tests/snapshots/asm/struct_fn_ptr_field_deref_call.aarch64.asm @@ -20,12 +20,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, adrp x0, @@ -34,78 +32,60 @@ Disassembly of section .text: mov x1, #0x0 // =0 str w1, [x20, #0x8] mov x1, #0xa // =10 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x21, w0 ldr x0, [x20] mov x1, #0x14 // =20 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x21, #0xd b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret cmp x0, #0x17 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret adrp x0, add x0, x0, str x0, [x20] mov x1, #0x64 // =100 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x21, w0 ldr x0, [x20] mov x1, #0xc8 // =200 - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x1 blr x9 - add sp, sp, #0x10 sxtw x0, w0 cmp x21, #0x6b b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret cmp x0, #0xcf b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/struct_fn_ptr_field_deref_call.x64.asm b/tests/snapshots/asm/struct_fn_ptr_field_deref_call.x64.asm index 1b6811fcc..29b79bd18 100644 --- a/tests/snapshots/asm/struct_fn_ptr_field_deref_call.x64.asm +++ b/tests/snapshots/asm/struct_fn_ptr_field_deref_call.x64.asm @@ -23,7 +23,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq , %rbx @@ -43,7 +43,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq cmpq $0x17, %rax @@ -51,7 +51,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rax # @@ -68,7 +68,7 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq cmpq $0xcf, %rax @@ -76,12 +76,12 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x80, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/struct_initializers.aarch64.asm b/tests/snapshots/asm/struct_initializers.aarch64.asm index cac20dd47..c9523d159 100644 --- a/tests/snapshots/asm/struct_initializers.aarch64.asm +++ b/tests/snapshots/asm/struct_initializers.aarch64.asm @@ -20,59 +20,49 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x20, add x20, x20, ldrsw x0, [x20] cmp x0, #0x1 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x8] mov x1, #0x2 // =2 mov x2, #0x3 // =3 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x5 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x10] mov x1, #0xa // =10 mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x6 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret ldr x0, [x20, #0x18] ldrb w0, [x0] @@ -82,10 +72,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -93,31 +82,26 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0x5 // =5 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, ldr x0, [x0, #0x8] mov x1, #0x7 // =7 mov x2, #0x8 // =8 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0xf b.eq mov x0, #0x6 // =6 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -129,10 +113,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -140,51 +123,41 @@ Disassembly of section .text: cmp x0, #0x3 b.eq mov x0, #0x8 // =8 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, ldr x0, [x0, #0x8] mov x1, #0x1 // =1 - str x1, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x2 b.eq mov x0, #0x9 // =9 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, ldr x0, [x0, #0x10] mov x1, #0x5 // =5 mov x2, #0x1 // =1 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x4 b.eq mov x0, #0xa // =10 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -192,10 +165,9 @@ Disassembly of section .text: cmp x0, #0xa b.eq mov x0, #0xb // =11 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -203,10 +175,9 @@ Disassembly of section .text: cmp x0, #0x14 b.eq mov x0, #0xc // =12 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -214,10 +185,9 @@ Disassembly of section .text: cmp x0, #0x1 b.eq mov x0, #0xd // =13 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x0, add x0, x0, @@ -225,14 +195,12 @@ Disassembly of section .text: cmp x0, #0x2 b.eq mov x0, #0xe // =14 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/struct_initializers.x64.asm b/tests/snapshots/asm/struct_initializers.x64.asm index c36667392..247e0e2a2 100644 --- a/tests/snapshots/asm/struct_initializers.x64.asm +++ b/tests/snapshots/asm/struct_initializers.x64.asm @@ -24,7 +24,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq , %rbx movslq (%rbx), %rax @@ -32,7 +32,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movq 0x8(%rbx), %rax @@ -44,7 +44,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movq 0x10(%rbx), %rax @@ -56,7 +56,7 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movq 0x18(%rbx), %rax @@ -65,7 +65,7 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -74,7 +74,7 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -87,7 +87,7 @@ Disassembly of section .text: je movl $0x6, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -97,7 +97,7 @@ Disassembly of section .text: je movl $0x7, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -106,7 +106,7 @@ Disassembly of section .text: je movl $0x8, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -119,7 +119,7 @@ Disassembly of section .text: je movl $0x9, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -132,7 +132,7 @@ Disassembly of section .text: je movl $0xa, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -141,7 +141,7 @@ Disassembly of section .text: je movl $0xb, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -150,7 +150,7 @@ Disassembly of section .text: je movl $0xc, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -159,7 +159,7 @@ Disassembly of section .text: je movl $0xd, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -168,11 +168,11 @@ Disassembly of section .text: je movl $0xe, %eax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/struct_layout.aarch64.asm b/tests/snapshots/asm/struct_layout.aarch64.asm index eb997d0a3..77151fcc6 100644 --- a/tests/snapshots/asm/struct_layout.aarch64.asm +++ b/tests/snapshots/asm/struct_layout.aarch64.asm @@ -10,251 +10,169 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - b mov x0, #0x5 // =5 ret - b mov x0, #0x6 // =6 ret - b mov x0, #0x7 // =7 ret - b mov x0, #0x8 // =8 ret - b mov x0, #0xa // =10 ret - b mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - b mov x0, #0x14 // =20 ret - b mov x0, #0x15 // =21 ret - b mov x0, #0x16 // =22 ret - b mov x0, #0x17 // =23 ret - b mov x0, #0x1e // =30 ret - b mov x0, #0x1f // =31 ret - b mov x0, #0x20 // =32 ret - b mov x0, #0x21 // =33 ret - b mov x0, #0x28 // =40 ret - b mov x0, #0x29 // =41 ret - b mov x0, #0x2a // =42 ret - b mov x0, #0x2b // =43 ret - b mov x0, #0x32 // =50 ret - b mov x0, #0x33 // =51 ret - b mov x0, #0x34 // =52 ret - b mov x0, #0x35 // =53 ret - b mov x0, #0x3c // =60 ret - b mov x0, #0x3d // =61 ret - b mov x0, #0x3e // =62 ret - b mov x0, #0x3f // =63 ret - b mov x0, #0x40 // =64 ret - b mov x0, #0x46 // =70 ret - b mov x0, #0x47 // =71 ret - b mov x0, #0x48 // =72 ret - b mov x0, #0x49 // =73 ret - b mov x0, #0x4a // =74 ret - b mov x0, #0x4b // =75 ret - b mov x0, #0x4c // =76 ret - b mov x0, #0x4d // =77 ret - b mov x0, #0x50 // =80 ret - b mov x0, #0x51 // =81 ret - b mov x0, #0x52 // =82 ret - b mov x0, #0x53 // =83 ret - b mov x0, #0x5a // =90 ret - b mov x0, #0x5b // =91 ret - b mov x0, #0x5c // =92 ret - b mov x0, #0x5d // =93 ret - b mov x0, #0x5e // =94 ret - b mov x0, #0x5f // =95 ret - b mov x0, #0x60 // =96 ret - b mov x0, #0x61 // =97 ret - b mov x0, #0x64 // =100 ret - b mov x0, #0x65 // =101 ret - b mov x0, #0x66 // =102 ret - b mov x0, #0x67 // =103 ret - b mov x0, #0x68 // =104 ret - b mov x0, #0x69 // =105 ret - b mov x0, #0x6a // =106 ret - b mov x0, #0x6b // =107 ret - b mov x0, #0x6e // =110 ret - b mov x0, #0x6f // =111 ret - b mov x0, #0x78 // =120 ret - b mov x0, #0x79 // =121 ret - b mov x0, #0x82 // =130 ret - b mov x0, #0x83 // =131 ret - b mov x0, #0x8c // =140 ret - b mov x0, #0x8d // =141 ret - b mov x0, #0x8e // =142 ret - b mov x0, #0x8f // =143 ret - b mov x0, #0x96 // =150 ret - b mov x0, #0x97 // =151 ret - b mov x0, #0x98 // =152 ret - b mov x0, #0x99 // =153 ret - b mov x0, #0x9a // =154 ret - b mov x0, #0xa0 // =160 ret - b mov x0, #0xa1 // =161 ret - b mov x0, #0xa2 // =162 ret - b mov x0, #0xa3 // =163 ret - b mov x0, #0xa4 // =164 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/struct_layout.x64.asm b/tests/snapshots/asm/struct_layout.x64.asm index c48c1979a..5e75e4f8f 100644 --- a/tests/snapshots/asm/struct_layout.x64.asm +++ b/tests/snapshots/asm/struct_layout.x64.asm @@ -11,251 +11,169 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - jmp movl $0x5, %eax retq - jmp movl $0x6, %eax retq - jmp movl $0x7, %eax retq - jmp movl $0x8, %eax retq - jmp movl $0xa, %eax retq - jmp movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - jmp movl $0x14, %eax retq - jmp movl $0x15, %eax retq - jmp movl $0x16, %eax retq - jmp movl $0x17, %eax retq - jmp movl $0x1e, %eax retq - jmp movl $0x1f, %eax retq - jmp movl $0x20, %eax retq - jmp movl $0x21, %eax retq - jmp movl $0x28, %eax retq - jmp movl $0x29, %eax retq - jmp movl $0x2a, %eax retq - jmp movl $0x2b, %eax retq - jmp movl $0x32, %eax retq - jmp movl $0x33, %eax retq - jmp movl $0x34, %eax retq - jmp movl $0x35, %eax retq - jmp movl $0x3c, %eax retq - jmp movl $0x3d, %eax retq - jmp movl $0x3e, %eax retq - jmp movl $0x3f, %eax retq - jmp movl $0x40, %eax retq - jmp movl $0x46, %eax retq - jmp movl $0x47, %eax retq - jmp movl $0x48, %eax retq - jmp movl $0x49, %eax retq - jmp movl $0x4a, %eax retq - jmp movl $0x4b, %eax retq - jmp movl $0x4c, %eax retq - jmp movl $0x4d, %eax retq - jmp movl $0x50, %eax retq - jmp movl $0x51, %eax retq - jmp movl $0x52, %eax retq - jmp movl $0x53, %eax retq - jmp movl $0x5a, %eax retq - jmp movl $0x5b, %eax retq - jmp movl $0x5c, %eax retq - jmp movl $0x5d, %eax retq - jmp movl $0x5e, %eax retq - jmp movl $0x5f, %eax retq - jmp movl $0x60, %eax retq - jmp movl $0x61, %eax retq - jmp movl $0x64, %eax retq - jmp movl $0x65, %eax retq - jmp movl $0x66, %eax retq - jmp movl $0x67, %eax retq - jmp movl $0x68, %eax retq - jmp movl $0x69, %eax retq - jmp movl $0x6a, %eax retq - jmp movl $0x6b, %eax retq - jmp movl $0x6e, %eax retq - jmp movl $0x6f, %eax retq - jmp movl $0x78, %eax retq - jmp movl $0x79, %eax retq - jmp movl $0x82, %eax retq - jmp movl $0x83, %eax retq - jmp movl $0x8c, %eax retq - jmp movl $0x8d, %eax retq - jmp movl $0x8e, %eax retq - jmp movl $0x8f, %eax retq - jmp movl $0x96, %eax retq - jmp movl $0x97, %eax retq - jmp movl $0x98, %eax retq - jmp movl $0x99, %eax retq - jmp movl $0x9a, %eax retq - jmp movl $0xa0, %eax retq - jmp movl $0xa1, %eax retq - jmp movl $0xa2, %eax retq - jmp movl $0xa3, %eax retq - jmp movl $0xa4, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/struct_linked_list.aarch64.asm b/tests/snapshots/asm/struct_linked_list.aarch64.asm index 31c55d8ff..3bd75f834 100644 --- a/tests/snapshots/asm/struct_linked_list.aarch64.asm +++ b/tests/snapshots/asm/struct_linked_list.aarch64.asm @@ -10,39 +10,50 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x20, #0x0 // =0 - mov x21, x20 - sxtw x0, w20 - cmp x0, #0x5 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 - mov x21, x1 - b mov x0, #0x10 // =16 bl - mov x1, x0 - str w20, [x1] - str x21, [x1, #0x8] - b + mov x21, x0 + mov x0, #0x0 // =0 + str w0, [x21] + str x20, [x21, #0x8] + mov x0, #0x10 // =16 + bl + mov x20, x0 + mov x0, #0x1 // =1 + str w0, [x20] + str x21, [x20, #0x8] + mov x0, #0x10 // =16 + bl + mov x21, x0 + mov x0, #0x2 // =2 + str w0, [x21] + str x20, [x21, #0x8] + mov x0, #0x10 // =16 + bl + mov x20, x0 + mov x0, #0x3 // =3 + str w0, [x20] + str x21, [x20, #0x8] + mov x0, #0x10 // =16 + bl + mov x2, x0 + mov x0, #0x4 // =4 + str w0, [x2] + str x20, [x2, #0x8] mov x1, #0x0 // =0 - cmp x21, #0x0 - b.eq - ldrsw x0, [x21] - add x1, x1, x0 - ldr x21, [x21, #0x8] b + ldrsw x0, [x2] + add x1, x1, x0 + ldr x2, [x2, #0x8] + cmp x2, #0x0 + b.ne sxtw x0, w1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/struct_linked_list.x64.asm b/tests/snapshots/asm/struct_linked_list.x64.asm index adc26c550..f5144f361 100644 --- a/tests/snapshots/asm/struct_linked_list.x64.asm +++ b/tests/snapshots/asm/struct_linked_list.x64.asm @@ -13,37 +13,56 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rbx, %rbx - movq %rbx, %r12 - movslq %ebx, %rax - cmpq $0x5, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx - movq %rcx, %r12 - jmp movl $0x10, %edi xorl %eax, %eax callq - movq %rax, %rcx - movl %ebx, (%rcx) - movq %r12, 0x8(%rcx) - jmp + movq %rax, %r12 + xorq %rax, %rax + movl %eax, (%r12) + movq %rbx, 0x8(%r12) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %rbx + movl $0x1, %eax + movl %eax, (%rbx) + movq %r12, 0x8(%rbx) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %r12 + movl $0x2, %eax + movl %eax, (%r12) + movq %rbx, 0x8(%r12) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %rbx + movl $0x3, %eax + movl %eax, (%rbx) + movq %r12, 0x8(%rbx) + movl $0x10, %edi + xorl %eax, %eax + callq + movq %rax, %rdx + movl $0x4, %eax + movl %eax, (%rdx) + movq %rbx, 0x8(%rdx) xorq %rcx, %rcx - testq %r12, %r12 - je - movslq (%r12), %rax - addq %rax, %rcx - movq 0x8(%r12), %r12 jmp + movslq (%rdx), %rax + addq %rax, %rcx + movq 0x8(%rdx), %rdx + testq %rdx, %rdx + jne movslq %ecx, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/struct_member_brace_wrapped_string.aarch64.asm b/tests/snapshots/asm/struct_member_brace_wrapped_string.aarch64.asm index 815190922..270907e25 100644 --- a/tests/snapshots/asm/struct_member_brace_wrapped_string.aarch64.asm +++ b/tests/snapshots/asm/struct_member_brace_wrapped_string.aarch64.asm @@ -10,36 +10,28 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b - b
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x150 - str x20, [sp] + sub sp, sp, #0x140 adrp x0, add x0, x0, add x0, x0, #0x8 @@ -49,16 +41,15 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x150 + add sp, sp, #0x140 ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, ldrsw x0, [x0] cmp x0, #0x7 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, add x0, x0, #0x4 @@ -66,11 +57,10 @@ Disassembly of section .text: add x1, x1, bl cmp x0, #0x0 - cset x20, eq - cbz x20, + cset x1, eq + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x150 + add sp, sp, #0x140 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x108 @@ -152,8 +142,7 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x150 + add sp, sp, #0x140 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x120 @@ -187,13 +176,11 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x150 + add sp, sp, #0x140 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x150 + add sp, sp, #0x140 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/struct_member_brace_wrapped_string.x64.asm b/tests/snapshots/asm/struct_member_brace_wrapped_string.x64.asm index bc645f4c3..b893f0c49 100644 --- a/tests/snapshots/asm/struct_member_brace_wrapped_string.x64.asm +++ b/tests/snapshots/asm/struct_member_brace_wrapped_string.x64.asm @@ -11,24 +11,9 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp - incq %rdi - incq %rsi - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp - retq movsbq (%rdi), %rax movsbq (%rsi), %rcx cmpq %rcx, %rax @@ -36,14 +21,21 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je + incq %rdi + incq %rsi jmp jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %al + movzbq %al, %rax + retq
: pushq %rbp movq %rsp, %rbp - subq $0x150, %rsp # imm = 0x150 - movq %rbx, (%rsp) + subq $0x140, %rsp # imm = 0x140 leaq , %rax leaq 0x8(%rax), %rdi leaq , %rsi @@ -51,29 +43,27 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x1, %eax - movq (%rsp), %rbx - addq $0x150, %rsp # imm = 0x150 + addq $0x140, %rsp # imm = 0x140 popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x7, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax leaq 0x4(%rax), %rdi leaq , %rsi callq testq %rax, %rax - sete %bl - movzbq %bl, %rbx - testq %rbx, %rbx + sete %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x150, %rsp # imm = 0x150 + addq $0x140, %rsp # imm = 0x140 popq %rbp retq leaq -0x108(%rbp), %rax @@ -153,8 +143,7 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x3, %eax - movq (%rsp), %rbx - addq $0x150, %rsp # imm = 0x150 + addq $0x140, %rsp # imm = 0x140 popq %rbp retq leaq -0x120(%rbp), %rax @@ -190,14 +179,14 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x150, %rsp # imm = 0x150 + addq $0x140, %rsp # imm = 0x140 popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x150, %rsp # imm = 0x150 + addq $0x140, %rsp # imm = 0x140 popq %rbp retq jmp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_multi_byval.aarch64.asm b/tests/snapshots/asm/struct_multi_byval.aarch64.asm index c9adfba6d..480ed2d4d 100644 --- a/tests/snapshots/asm/struct_multi_byval.aarch64.asm +++ b/tests/snapshots/asm/struct_multi_byval.aarch64.asm @@ -186,9 +186,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x160 - str x20, [sp] - str x21, [sp, #0x8] + sub sp, sp, #0x150 sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -273,17 +271,15 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret mov x0, #0x32 // =50 sub x1, x29, #0xc8 str w0, [x1] - sub x1, x29, #0xc8 - add x0, x0, #0x1 - str w0, [x1, #0x4] + sub x0, x29, #0xc8 + mov x1, #0x33 // =51 + str w1, [x0, #0x4] sub x0, x29, #0xc8 sub x1, x29, #0x50 str x10, [sp, #-0x10]! @@ -294,31 +290,29 @@ Disassembly of section .text: sub x0, x29, #0x50 ldrsw x0, [x0] cmp x0, #0x32 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x50 ldrsw x0, [x0, #0x4] cmp x0, #0x33 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret mov x0, #0x3c // =60 sub x1, x29, #0xe0 str w0, [x1] - sub x1, x29, #0xe0 - add x2, x0, #0x1 - str w2, [x1, #0x4] - sub x1, x29, #0xe0 - add x2, x0, #0x2 - str w2, [x1, #0x8] - sub x1, x29, #0xe0 - add x0, x0, #0x3 - str w0, [x1, #0xc] + sub x0, x29, #0xe0 + mov x1, #0x3d // =61 + str w1, [x0, #0x4] + sub x0, x29, #0xe0 + mov x1, #0x3e // =62 + str w1, [x0, #0x8] + sub x0, x29, #0xe0 + mov x1, #0x3f // =63 + str w1, [x0, #0xc] sub x0, x29, #0xe0 sub x1, x29, #0x68 str x10, [sp, #-0x10]! @@ -332,32 +326,30 @@ Disassembly of section .text: ldrsw x0, [x0] cmp x0, #0x3c cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x68 ldrsw x0, [x0, #0x4] cmp x0, #0x3d cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x68 ldrsw x0, [x0, #0x8] cmp x0, #0x3e cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x68 ldrsw x0, [x0, #0xc] cmp x0, #0x3f - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret mov x0, #0x46 // =70 @@ -417,9 +409,7 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x50 @@ -450,15 +440,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x160 + add sp, sp, #0x150 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/struct_multi_byval.x64.asm b/tests/snapshots/asm/struct_multi_byval.x64.asm index 489c59d95..bb767fc41 100644 --- a/tests/snapshots/asm/struct_multi_byval.x64.asm +++ b/tests/snapshots/asm/struct_multi_byval.x64.asm @@ -147,11 +147,9 @@ Disassembly of section .text: movslq 0x20(%rbp), %rcx movl %ecx, (%rax) leaq -0x18(%rbp), %rax - movslq 0x20(%rbp), %rcx - incq %rcx - movl %ecx, 0x4(%rax) + leaq 0x1(%rcx), %rdx + movl %edx, 0x4(%rax) leaq -0x18(%rbp), %rax - movslq 0x20(%rbp), %rcx addq $0x2, %rcx movl %ecx, 0x8(%rax) leaq -0x18(%rbp), %rax @@ -189,7 +187,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x160, %rsp # imm = 0x160 movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) leaq -0x8(%rbp), %rax leaq , %rcx pushq %rdx @@ -275,16 +272,15 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq movl $0x32, %eax leaq -0xc8(%rbp), %rcx movl %eax, (%rcx) - leaq -0xc8(%rbp), %rcx - incq %rax - movl %eax, 0x4(%rcx) + leaq -0xc8(%rbp), %rax + movl $0x33, %ecx + movl %ecx, 0x4(%rax) leaq -0xc8(%rbp), %rax leaq -0x50(%rbp), %rcx pushq %rdx @@ -295,35 +291,34 @@ Disassembly of section .text: leaq -0x50(%rbp), %rax movslq (%rax), %rax cmpq $0x32, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x50(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x33, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq movl $0x3c, %eax leaq -0xe0(%rbp), %rcx movl %eax, (%rcx) - leaq -0xe0(%rbp), %rcx - leaq 0x1(%rax), %rdx - movl %edx, 0x4(%rcx) - leaq -0xe0(%rbp), %rcx - leaq 0x2(%rax), %rdx - movl %edx, 0x8(%rcx) - leaq -0xe0(%rbp), %rcx - addq $0x3, %rax - movl %eax, 0xc(%rcx) + leaq -0xe0(%rbp), %rax + movl $0x3d, %ecx + movl %ecx, 0x4(%rax) + leaq -0xe0(%rbp), %rax + movl $0x3e, %ecx + movl %ecx, 0x8(%rax) + leaq -0xe0(%rbp), %rax + movl $0x3f, %ecx + movl %ecx, 0xc(%rax) leaq -0xe0(%rbp), %rax leaq -0x68(%rbp), %rcx pushq %rdx @@ -338,7 +333,7 @@ Disassembly of section .text: cmpq $0x3c, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x68(%rbp), %rax @@ -347,10 +342,10 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x68(%rbp), %rax movslq 0x8(%rax), %rax @@ -358,20 +353,19 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x68(%rbp), %rax movslq 0xc(%rax), %rax cmpq $0x3f, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq @@ -449,7 +443,6 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq @@ -486,13 +479,11 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x160, %rsp # imm = 0x160 popq %rbp retq @@ -506,4 +497,4 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/struct_param_stack_spill.aarch64.asm b/tests/snapshots/asm/struct_param_stack_spill.aarch64.asm index 48db2b081..9d8880b11 100644 --- a/tests/snapshots/asm/struct_param_stack_spill.aarch64.asm +++ b/tests/snapshots/asm/struct_param_stack_spill.aarch64.asm @@ -91,28 +91,13 @@ Disassembly of section .text: ldr x10, [x1, #0x8] str x10, [x0, #0x8] ldr x10, [sp], #0x10 - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - mov x3, #0x4 // =4 - mov x4, #0x5 // =5 - mov x5, #0x6 // =6 - mov x6, #0x7 // =7 - mov x7, #0x8 // =8 - sub x8, x29, #0x10 - add x0, x0, x1 - add x0, x0, x2 - add x0, x0, x3 - add x0, x0, x4 - add x0, x0, x5 - add x0, x0, x6 - add x0, x0, x7 - ldr x1, [x8] + sub x0, x29, #0x10 + ldr x1, [x0] mov x17, #0x3e8 // =1000 mul x1, x1, x17 - add x0, x0, x1 - ldr x1, [x8, #0x8] - add x0, x0, x1 + add x1, x1, #0x24 + ldr x0, [x0, #0x8] + add x0, x1, x0 cmp x0, #0xbe0 b.eq mov x0, #0x1 // =1 @@ -134,34 +119,19 @@ Disassembly of section .text: ldrb w10, [x1, #0xb] strb w10, [x0, #0xb] ldr x10, [sp], #0x10 - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - mov x3, #0x4 // =4 - mov x4, #0x5 // =5 - mov x5, #0x6 // =6 - mov x6, #0x7 // =7 - mov x7, #0x8 // =8 - sub x8, x29, #0x20 - add x0, x0, x1 - add x0, x0, x2 - add x0, x0, x3 - add x0, x0, x4 - add x0, x0, x5 - add x0, x0, x6 - add x0, x0, x7 - ldrsw x1, [x8] + sub x0, x29, #0x20 + ldrsw x1, [x0] mov x17, #0x64 // =100 mul x1, x1, x17 sxtw x1, w1 - add x0, x0, x1 - ldrsw x1, [x8, #0x4] + add x1, x1, #0x24 + ldrsw x2, [x0, #0x4] mov x17, #0xa // =10 - mul x1, x1, x17 - sxtw x1, w1 - add x0, x0, x1 - ldrsw x1, [x8, #0x8] - add x0, x0, x1 + mul x2, x2, x17 + sxtw x2, w2 + add x1, x1, x2 + ldrsw x0, [x0, #0x8] + add x0, x1, x0 cmp x0, #0x10e b.eq mov x0, #0x2 // =2 diff --git a/tests/snapshots/asm/struct_return_by_value.aarch64.asm b/tests/snapshots/asm/struct_return_by_value.aarch64.asm index c846fb9ea..775c84997 100644 --- a/tests/snapshots/asm/struct_return_by_value.aarch64.asm +++ b/tests/snapshots/asm/struct_return_by_value.aarch64.asm @@ -148,14 +148,13 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x110 - str x20, [sp] + sub sp, sp, #0x100 mov x0, #0x7 // =7 sub x1, x29, #0x90 str w0, [x1] - sub x1, x29, #0x90 - add x0, x0, #0x1 - str w0, [x1, #0x4] + sub x0, x29, #0x90 + mov x1, #0x8 // =8 + str w1, [x0, #0x4] sub x0, x29, #0x90 sub x1, x29, #0x8 str x10, [sp, #-0x10]! @@ -166,16 +165,15 @@ Disassembly of section .text: sub x0, x29, #0x8 ldrsw x0, [x0] cmp x0, #0x7 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x8 ldrsw x0, [x0, #0x4] cmp x0, #0x8 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0xa // =10 @@ -196,38 +194,36 @@ Disassembly of section .text: ldr x0, [x0] cmp x0, #0xa cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x28 ldr x0, [x0, #0x8] cmp x0, #0xb cset x0, ne cmp x0, #0x0 - cset x20, ne - cbnz x20, + cset x2, ne + cbnz x2, sub x0, x29, #0x28 ldr x0, [x0, #0x10] cmp x0, #0xc - cset x20, ne - cbz x20, + cset x2, ne + cbz x2, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x14 // =20 sub x1, x29, #0xc8 str w0, [x1] - sub x1, x29, #0xc8 - add x0, x0, #0x1 - str w0, [x1, #0x4] + sub x0, x29, #0xc8 + mov x1, #0x15 // =21 + str w1, [x0, #0x4] sub x0, x29, #0xc8 ldrsw x0, [x0] cmp x0, #0x14 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1e // =30 @@ -238,17 +234,16 @@ Disassembly of section .text: cmp x0, #0x20 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x68 mov x1, #0x28 // =40 sub x2, x29, #0xe8 str w1, [x2] - sub x2, x29, #0xe8 - add x1, x1, #0x1 - str w1, [x2, #0x4] + sub x1, x29, #0xe8 + mov x2, #0x29 // =41 + str w2, [x1, #0x4] sub x1, x29, #0xe8 str x10, [sp, #-0x10]! ldr x10, [x1] @@ -257,16 +252,15 @@ Disassembly of section .text: sub x0, x29, #0x68 ldrsw x0, [x0] cmp x0, #0x28 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x68 ldrsw x0, [x0, #0x4] cmp x0, #0x29 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 @@ -274,8 +268,7 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x5 // =5 @@ -283,8 +276,7 @@ Disassembly of section .text: cmp x0, #0x12 b.eq mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x8 @@ -310,13 +302,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x8 // =8 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x110 + add sp, sp, #0x100 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/struct_return_by_value.x64.asm b/tests/snapshots/asm/struct_return_by_value.x64.asm index 561e09001..537d57b99 100644 --- a/tests/snapshots/asm/struct_return_by_value.x64.asm +++ b/tests/snapshots/asm/struct_return_by_value.x64.asm @@ -39,11 +39,9 @@ Disassembly of section .text: movq 0x20(%rbp), %rcx movq %rcx, (%rax) leaq -0x18(%rbp), %rax - movq 0x20(%rbp), %rcx - incq %rcx - movq %rcx, 0x8(%rax) + leaq 0x1(%rcx), %rdx + movq %rdx, 0x8(%rax) leaq -0x18(%rbp), %rax - movq 0x20(%rbp), %rcx addq $0x2, %rcx movq %rcx, 0x10(%rax) movq 0x10(%rbp), %rax @@ -175,14 +173,13 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x120, %rsp # imm = 0x120 - movq %rbx, (%rsp) + subq $0x110, %rsp # imm = 0x110 movl $0x7, %eax leaq -0x90(%rbp), %rcx movl %eax, (%rcx) - leaq -0x90(%rbp), %rcx - incq %rax - movl %eax, 0x4(%rcx) + leaq -0x90(%rbp), %rax + movl $0x8, %ecx + movl %ecx, 0x4(%rax) leaq -0x90(%rbp), %rax leaq -0x8(%rbp), %rcx pushq %rdx @@ -193,20 +190,19 @@ Disassembly of section .text: leaq -0x8(%rbp), %rax movslq (%rax), %rax cmpq $0x7, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x8(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x8, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq leaq -0xb0(%rbp), %rdi @@ -228,7 +224,7 @@ Disassembly of section .text: cmpq $0xa, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x28(%rbp), %rax @@ -237,35 +233,33 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x28(%rbp), %rax movq 0x10(%rax), %rax cmpq $0xc, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq movl $0x14, %eax leaq -0xd0(%rbp), %rcx movl %eax, (%rcx) - leaq -0xd0(%rbp), %rcx - incq %rax - movl %eax, 0x4(%rcx) + leaq -0xd0(%rbp), %rax + movl $0x15, %ecx + movl %ecx, 0x4(%rax) leaq -0xd0(%rbp), %rax movslq (%rax), %rax cmpq $0x14, %rax je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq leaq -0xe8(%rbp), %rdi @@ -276,17 +270,16 @@ Disassembly of section .text: cmpq $0x20, %rax je movl $0x4, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq leaq -0x68(%rbp), %rax movl $0x28, %ecx leaq -0xf8(%rbp), %rdx movl %ecx, (%rdx) - leaq -0xf8(%rbp), %rdx - incq %rcx - movl %ecx, 0x4(%rdx) + leaq -0xf8(%rbp), %rcx + movl $0x29, %edx + movl %edx, 0x4(%rcx) leaq -0xf8(%rbp), %rcx pushq %rdx movq (%rcx), %rdx @@ -295,20 +288,19 @@ Disassembly of section .text: leaq -0x68(%rbp), %rax movslq (%rax), %rax cmpq $0x28, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x68(%rbp), %rax movslq 0x4(%rax), %rax cmpq $0x29, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x5, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq movl $0x3, %edi @@ -316,8 +308,7 @@ Disassembly of section .text: cmpq $0x7, %rax je movl $0x6, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq movl $0x5, %edi @@ -325,8 +316,7 @@ Disassembly of section .text: cmpq $0x12, %rax je movl $0x7, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq leaq -0x8(%rbp), %rdi @@ -355,13 +345,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x8, %eax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x120, %rsp # imm = 0x120 + addq $0x110, %rsp # imm = 0x110 popq %rbp retq jmp @@ -369,5 +357,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_return_reg_computed_goto.aarch64.asm b/tests/snapshots/asm/struct_return_reg_computed_goto.aarch64.asm index 7e2ff9d3c..cedf457ea 100644 --- a/tests/snapshots/asm/struct_return_reg_computed_goto.aarch64.asm +++ b/tests/snapshots/asm/struct_return_reg_computed_goto.aarch64.asm @@ -32,7 +32,7 @@ Disassembly of section .text: br x0 mov x0, #0x7 // =7 stur w0, [x29, #-0x8] - ldursw x0, [x29, #-0x8] + sxtw x0, w0 cmp x0, #0x7 b.ne mov x0, #0x0 // =0 @@ -51,9 +51,9 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x40 stur w0, [x29, #0x10] - mov x0, #0x0 // =0 - stur w0, [x29, #-0x8] - ldursw x0, [x29, #0x10] + mov x1, #0x0 // =0 + stur w1, [x29, #-0x8] + sxtw x0, w0 cbz x0, adr x0, stur x0, [x29, #-0x28] @@ -70,7 +70,7 @@ Disassembly of section .text: ret mov x0, #0x2 // =2 stur w0, [x29, #-0x8] - ldursw x0, [x29, #-0x8] + sxtw x0, w0 cmp x0, #0x2 b.ne mov x0, #0x0 // =0 diff --git a/tests/snapshots/asm/struct_return_reg_computed_goto.x64.asm b/tests/snapshots/asm/struct_return_reg_computed_goto.x64.asm index b7772276c..4432936e8 100644 --- a/tests/snapshots/asm/struct_return_reg_computed_goto.x64.asm +++ b/tests/snapshots/asm/struct_return_reg_computed_goto.x64.asm @@ -33,7 +33,7 @@ Disassembly of section .text: jmpq *%rax movl $0x7, %eax movl %eax, -0x8(%rbp) - movslq -0x8(%rbp), %rax + movslq %eax, %rax cmpq $0x7, %rax jne xorq %rax, %rax @@ -57,7 +57,7 @@ Disassembly of section .text: movl %edi, 0x10(%rbp) xorq %rax, %rax movl %eax, -0x8(%rbp) - movslq 0x10(%rbp), %rax + movslq %edi, %rax testq %rax, %rax je leaq , %rax # @@ -77,7 +77,7 @@ Disassembly of section .text: retq movl $0x2, %eax movl %eax, -0x8(%rbp) - movslq -0x8(%rbp), %rax + movslq %eax, %rax cmpq $0x2, %rax jne xorq %rax, %rax @@ -112,4 +112,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_return_to_global.aarch64.asm b/tests/snapshots/asm/struct_return_to_global.aarch64.asm index dc073b792..103cda210 100644 --- a/tests/snapshots/asm/struct_return_to_global.aarch64.asm +++ b/tests/snapshots/asm/struct_return_to_global.aarch64.asm @@ -50,11 +50,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0xa0]! + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 mov x2, #0x0 // =0 adrp x20, add x20, x20, @@ -75,53 +73,59 @@ Disassembly of section .text: ldr x0, [x20] ldr x1, [x20, #0x8] add x0, x0, x1 - add x21, x2, x0 - sxtw x0, w2 - cmp x0, #0x4 - b.ge + add x0, x0, #0x0 b - sxtw x0, w2 - add x2, x0, #0x1 - b - adrp x0, - add x0, x0, - sxtw x1, w2 - lsl x3, x1, #4 - add x0, x0, x3 + adrp x3, + add x3, x3, + lsl x4, x1, #4 + add x3, x3, x4 mov x17, #0xa // =10 - mul x1, x1, x17 - sxtw x1, w1 - sub x3, x29, #0x70 - str x1, [x3] - sub x1, x29, #0x70 - mov x3, #0x1 // =1 - str x3, [x1, #0x8] - sub x1, x29, #0x70 + mul x4, x1, x17 + sxtw x4, w4 + sub x5, x29, #0x70 + str x4, [x5] + sub x4, x29, #0x70 + mov x5, #0x1 // =1 + str x5, [x4, #0x8] + sub x4, x29, #0x70 str x10, [sp, #-0x10]! - ldr x10, [x1] - str x10, [x0] - ldr x10, [x1, #0x8] - str x10, [x0, #0x8] + ldr x10, [x4] + str x10, [x3] + ldr x10, [x4, #0x8] + str x10, [x3, #0x8] ldr x10, [sp], #0x10 - b - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x4 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b - adrp x0, - add x0, x0, - sxtw x2, w1 - lsl x2, x2, #4 - add x0, x0, x2 - ldr x2, [x0] - ldr x0, [x0, #0x8] - add x0, x2, x0 - add x21, x21, x0 - b + add x2, x1, #0x1 + sxtw x1, w2 + cmp x1, #0x4 + b.lt + adrp x1, + add x1, x1, + add x1, x1, #0x0 + ldr x2, [x1] + ldr x1, [x1, #0x8] + add x1, x2, x1 + add x0, x0, x1 + adrp x1, + add x1, x1, + add x1, x1, #0x10 + ldr x2, [x1] + ldr x1, [x1, #0x8] + add x1, x2, x1 + add x0, x0, x1 + adrp x1, + add x1, x1, + add x1, x1, #0x20 + ldr x2, [x1] + ldr x1, [x1, #0x8] + add x1, x2, x1 + add x0, x0, x1 + adrp x1, + add x1, x1, + add x1, x1, #0x30 + ldr x2, [x1] + ldr x1, [x1, #0x8] + add x1, x2, x1 + add x21, x0, x1 sub x0, x29, #0x48 mov x1, #0x3 // =3 str x1, [x0] @@ -139,11 +143,9 @@ Disassembly of section .text: cmp x0, #0x4e b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x90] + ldp x20, x21, [sp], #0xa0 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/struct_return_to_global.x64.asm b/tests/snapshots/asm/struct_return_to_global.x64.asm index cd4d2935f..749db3fc6 100644 --- a/tests/snapshots/asm/struct_return_to_global.x64.asm +++ b/tests/snapshots/asm/struct_return_to_global.x64.asm @@ -77,51 +77,54 @@ Disassembly of section .text: movq (%rbx), %rax movq 0x8(%rbx), %rcx addq %rcx, %rax - leaq (%rdx,%rax), %r12 - movslq %edx, %rax - cmpq $0x4, %rax - jge + addq $0x0, %rax jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq , %rax + leaq , %rsi + movq %rcx, %rdi + shlq $0x4, %rdi + addq %rdi, %rsi + imulq $0xa, %rcx, %rdi + movslq %edi, %rdi + leaq -0x70(%rbp), %r8 + movq %rdi, (%r8) + leaq -0x70(%rbp), %rdi + movl $0x1, %r8d + movq %r8, 0x8(%rdi) + leaq -0x70(%rbp), %rdi + pushq %rax + movq (%rdi), %rax + movq %rax, (%rsi) + movq 0x8(%rdi), %rax + movq %rax, 0x8(%rsi) + popq %rax + leaq 0x1(%rcx), %rdx movslq %edx, %rcx - movq %rcx, %rsi - shlq $0x4, %rsi - addq %rsi, %rax - imulq $0xa, %rcx, %rcx - movslq %ecx, %rcx - leaq -0x70(%rbp), %rsi - movq %rcx, (%rsi) - leaq -0x70(%rbp), %rcx - movl $0x1, %esi - movq %rsi, 0x8(%rcx) - leaq -0x70(%rbp), %rcx - pushq %rdx + cmpq $0x4, %rcx + jl + leaq , %rcx + addq $0x0, %rcx movq (%rcx), %rdx - movq %rdx, (%rax) - movq 0x8(%rcx), %rdx - movq %rdx, 0x8(%rax) - popq %rdx - jmp - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x4, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq , %rax - movslq %ecx, %rdx - shlq $0x4, %rdx - addq %rdx, %rax - movq (%rax), %rdx - movq 0x8(%rax), %rax - addq %rdx, %rax - addq %rax, %r12 - jmp + movq 0x8(%rcx), %rcx + addq %rdx, %rcx + addq %rcx, %rax + leaq , %rcx + addq $0x10, %rcx + movq (%rcx), %rdx + movq 0x8(%rcx), %rcx + addq %rdx, %rcx + addq %rcx, %rax + leaq , %rcx + addq $0x20, %rcx + movq (%rcx), %rdx + movq 0x8(%rcx), %rcx + addq %rdx, %rcx + addq %rcx, %rax + leaq , %rcx + addq $0x30, %rcx + movq (%rcx), %rdx + movq 0x8(%rcx), %rcx + addq %rdx, %rcx + leaq (%rax,%rcx), %r12 leaq -0x48(%rbp), %rax movl $0x3, %ecx movq %rcx, (%rax) @@ -139,13 +142,12 @@ Disassembly of section .text: cmpq $0x4e, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq %rcx, %rax addq $0x90, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/struct_sizeof.aarch64.asm b/tests/snapshots/asm/struct_sizeof.aarch64.asm index 956cd06bd..bbbd74a39 100644 --- a/tests/snapshots/asm/struct_sizeof.aarch64.asm +++ b/tests/snapshots/asm/struct_sizeof.aarch64.asm @@ -10,17 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - b mov x0, #0x4 // =4 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/struct_sizeof.x64.asm b/tests/snapshots/asm/struct_sizeof.x64.asm index f6ae9c68c..32a4f7fd0 100644 --- a/tests/snapshots/asm/struct_sizeof.x64.asm +++ b/tests/snapshots/asm/struct_sizeof.x64.asm @@ -11,17 +11,13 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - jmp movl $0x4, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/struct_stack_arg_then_scalar.aarch64.asm b/tests/snapshots/asm/struct_stack_arg_then_scalar.aarch64.asm index aeb4c9621..eef15bdb8 100644 --- a/tests/snapshots/asm/struct_stack_arg_then_scalar.aarch64.asm +++ b/tests/snapshots/asm/struct_stack_arg_then_scalar.aarch64.asm @@ -39,8 +39,6 @@ Disassembly of section .text: mov x2, x3 cbz x0, mov x1, #0x1 // =1 - b - mov x1, #0x0 // =0 mov x17, #0x4240 // =16960 movk x17, #0xf, lsl #16 mul x0, x1, x17 @@ -73,6 +71,8 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 add sp, sp, #0x70 ret + mov x1, #0x0 // =0 + b : sub sp, sp, #0x10 diff --git a/tests/snapshots/asm/struct_stack_arg_then_scalar.x64.asm b/tests/snapshots/asm/struct_stack_arg_then_scalar.x64.asm index c7a6cbf0d..141c379f1 100644 --- a/tests/snapshots/asm/struct_stack_arg_then_scalar.x64.asm +++ b/tests/snapshots/asm/struct_stack_arg_then_scalar.x64.asm @@ -35,8 +35,6 @@ Disassembly of section .text: testq %rdi, %rdi je movl $0x1, %ecx - jmp - xorq %rcx, %rcx imulq $0xf4240, %rcx, %rax # imm = 0xF4240 movslq %eax, %rax leaq -0x10(%rbp), %rcx @@ -65,6 +63,8 @@ Disassembly of section .text: addq $0x70, %rsp pushq %r11 retq + xorq %rcx, %rcx + jmp : popq %r10 diff --git a/tests/snapshots/asm/struct_stat_abi_size.aarch64.asm b/tests/snapshots/asm/struct_stat_abi_size.aarch64.asm index 9bb9b723c..bc2bed417 100644 --- a/tests/snapshots/asm/struct_stat_abi_size.aarch64.asm +++ b/tests/snapshots/asm/struct_stat_abi_size.aarch64.asm @@ -10,28 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x100 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x110]! str x19, [sp, #0x10] - b - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 - ret + stp x29, x30, [sp, #0x100] + add x29, sp, #0x100 sub x20, x29, #0x40 adrp x21, add x21, x21, @@ -52,11 +34,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ge mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret sxtw x0, w20 adrp x1, @@ -70,11 +50,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret sub x0, x29, #0xc8 mov x1, #0x0 // =0 @@ -90,11 +68,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret sub x0, x29, #0xc8 ldr x0, [x0, #0x30] @@ -104,11 +80,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret sub x0, x29, #0xc8 ldrsw x0, [x0, #0x10] @@ -121,11 +95,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret sxtw x0, w20 bl @@ -134,9 +106,17 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x100] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x110 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x100] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x110 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x100] ldr x19, [sp, #0x10] - add sp, sp, #0x100 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x110 ret diff --git a/tests/snapshots/asm/struct_stat_abi_size.x64.asm b/tests/snapshots/asm/struct_stat_abi_size.x64.asm index 345e6a04d..19e5a3e53 100644 --- a/tests/snapshots/asm/struct_stat_abi_size.x64.asm +++ b/tests/snapshots/asm/struct_stat_abi_size.x64.asm @@ -16,20 +16,6 @@ Disassembly of section .text: subq $0x100, %rsp # imm = 0x100 movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - jmp - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x100, %rsp # imm = 0x100 - popq %rbp - retq - jmp - movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x100, %rsp # imm = 0x100 - popq %rbp - retq leaq -0x40(%rbp), %rbx leaq , %r12 xorl %eax, %eax @@ -140,3 +126,15 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x100, %rsp # imm = 0x100 + popq %rbp + retq + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x100, %rsp # imm = 0x100 + popq %rbp + retq diff --git a/tests/snapshots/asm/struct_tm_tm_zone_offset.aarch64.asm b/tests/snapshots/asm/struct_tm_tm_zone_offset.aarch64.asm index 68953310f..a45fdc979 100644 --- a/tests/snapshots/asm/struct_tm_tm_zone_offset.aarch64.asm +++ b/tests/snapshots/asm/struct_tm_tm_zone_offset.aarch64.asm @@ -10,28 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] - b - mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x0, #0x0 // =0 bl stur x0, [x29, #-0x8] @@ -41,18 +22,16 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x40 ldr x0, [x0, #0x30] cmp x0, #0x0 b.ne mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x40 ldr x0, [x0, #0x30] @@ -61,12 +40,22 @@ Disassembly of section .text: cmp x0, #0x40 b.le mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret diff --git a/tests/snapshots/asm/struct_tm_tm_zone_offset.x64.asm b/tests/snapshots/asm/struct_tm_tm_zone_offset.x64.asm index 3bed5fb76..ad36baa95 100644 --- a/tests/snapshots/asm/struct_tm_tm_zone_offset.x64.asm +++ b/tests/snapshots/asm/struct_tm_tm_zone_offset.x64.asm @@ -14,21 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x50, %rsp - jmp - movl $0x1, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x2, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x3, %eax - addq $0x50, %rsp - popq %rbp - retq xorq %rdi, %rdi xorl %eax, %eax callq @@ -66,4 +51,17 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + movl $0x1, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x2, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x3, %eax + addq $0x50, %rsp + popq %rbp + retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sub_word_return_narrow.aarch64.asm b/tests/snapshots/asm/sub_word_return_narrow.aarch64.asm index c83d89c8b..bf93b71d2 100644 --- a/tests/snapshots/asm/sub_word_return_narrow.aarch64.asm +++ b/tests/snapshots/asm/sub_word_return_narrow.aarch64.asm @@ -30,70 +30,27 @@ Disassembly of section .text: ret : + sxth x0, w0 lsl x0, x0, #8 sxtw x1, w0 sxth x0, w1 ret : + sxtb x0, w0 add x0, x0, #0x64 sxtw x1, w0 sxtb x0, w1 ret
: - mov x0, #0x3412 // =13330 - mov x17, #0xffff // =65535 - and x0, x0, x17 - lsr x1, x0, #8 - lsl x0, x0, #8 - sxtw x0, w0 - orr x0, x1, x0 - mov x17, #0xffff // =65535 - and x0, x0, x17 - mov x17, #0x1234 // =4660 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 ret - mov x0, #0x64 // =100 - mov x17, #0xff // =255 - and x0, x0, x17 - add x0, x0, #0xc8 - sxtw x0, w0 - mov x17, #0xff // =255 - and x0, x0, x17 - mov x17, #0x2c // =44 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 ret - mov x0, #0x140 // =320 - sxth x0, w0 - lsl x0, x0, #8 - sxtw x1, w0 - sxth x0, w1 - mov x17, #0x4000 // =16384 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 ret - mov x0, #0x64 // =100 - sxtb x0, w0 - add x0, x0, #0x64 - sxtw x1, w0 - sxtb x0, w1 - mov x17, #0xffc8 // =65480 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x4 // =4 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/sub_word_return_narrow.x64.asm b/tests/snapshots/asm/sub_word_return_narrow.x64.asm index d95e4a564..3fdb3c948 100644 --- a/tests/snapshots/asm/sub_word_return_narrow.x64.asm +++ b/tests/snapshots/asm/sub_word_return_narrow.x64.asm @@ -30,6 +30,7 @@ Disassembly of section .text: retq : + movswq %di, %rdi movq %rdi, %rax shlq $0x8, %rax movslq %eax, %rcx @@ -37,54 +38,21 @@ Disassembly of section .text: retq : + movsbq %dil, %rdi leaq 0x64(%rdi), %rax movslq %eax, %rcx movsbq %cl, %rax retq
: - movl $0x3412, %eax # imm = 0x3412 - andq $0xffff, %rax # imm = 0xFFFF - movq %rax, %rcx - shrq $0x8, %rcx - shlq $0x8, %rax - movslq %eax, %rax - orq %rcx, %rax - andq $0xffff, %rax # imm = 0xFFFF - xorq $0x1234, %rax # imm = 0x1234 - movl %eax, %eax - testq %rax, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax retq - movl $0x64, %eax - andq $0xff, %rax - addq $0xc8, %rax - movslq %eax, %rax - andq $0xff, %rax - xorq $0x2c, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x2, %eax retq - movl $0x140, %eax # imm = 0x140 - movswq %ax, %rax - shlq $0x8, %rax - movslq %eax, %rcx - movswq %cx, %rax - cmpq $0x4000, %rax # imm = 0x4000 - je movl $0x3, %eax retq - movl $0x64, %eax - movsbq %al, %rax - addq $0x64, %rax - movslq %eax, %rcx - movsbq %cl, %rax - cmpq $-0x38, %rax - je movl $0x4, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/switch_binary_search.aarch64.asm b/tests/snapshots/asm/switch_binary_search.aarch64.asm index d9b5a3e91..9204d98a2 100644 --- a/tests/snapshots/asm/switch_binary_search.aarch64.asm +++ b/tests/snapshots/asm/switch_binary_search.aarch64.asm @@ -13,24 +13,29 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x1 b.lt - b + cmp x0, #0x2a + b.lt + cmp x0, #0x3e8 + b.lt + cmp x0, #0x3e8 + b.eq mov x0, #0x0 // =0 ret - mov x0, #0x1 // =1 - ret - mov x0, #0x2 // =2 - ret - mov x0, #0x3 // =3 - ret - mov x0, #0x4 // =4 - ret - mov x0, #0x5 // =5 + mov x0, #0x7 // =7 ret + cmp x0, #0x2a + b.ne mov x0, #0x6 // =6 ret - mov x0, #0x7 // =7 + cmp x0, #0x7 + b.lt + cmp x0, #0x7 + b.ne + mov x0, #0x5 // =5 ret - mov x0, #0x0 // =0 + cmp x0, #0x1 + b.ne + mov x0, #0x4 // =4 ret mov x17, #0xfffd // =65533 movk x17, #0xffff, lsl #16 @@ -38,48 +43,30 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 cmp x0, x17 b.lt - b - cmp x0, #0x2a + cmp x0, #0x0 b.lt - b - mov x17, #0xff9c // =65436 + cmp x0, #0x0 + b.ne + mov x0, #0x3 // =3 + ret + mov x17, #0xfffd // =65533 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - b.eq - b - cmp x0, #0x0 - b.lt - b - mov x17, #0xfffd // =65533 + b.ne + mov x0, #0x2 // =2 + ret + mov x17, #0xff9c // =65436 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - b.eq - b - cmp x0, #0x0 - b.eq - b - cmp x0, #0x7 - b.lt - b - cmp x0, #0x3e8 - b.lt - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x7 - b.eq - b - cmp x0, #0x2a - b.eq - b - cmp x0, #0x3e8 - b.eq - b + b.ne + mov x0, #0x1 // =1 + ret + mov x0, #0x0 // =0 + ret b : @@ -88,53 +75,44 @@ Disassembly of section .text: movk x17, #0x7fff, lsl #16 cmp x0, x17 b.lo - b - mov x0, #0x0 // =0 - ret - mov x0, #0x1 // =1 - ret - mov x0, #0x2 // =2 - ret - mov x0, #0x3 // =3 - ret - mov x0, #0x4 // =4 - ret - mov x0, #0x5 // =5 - ret - mov x0, #0x0 // =0 - ret - cmp x0, #0x5 - b.lo - b mov x17, #0x80000000 // =2147483648 cmp x0, x17 b.lo - b - cmp x0, #0x0 - b.eq - b - cmp x0, #0x5 - b.eq - b mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 + movk x17, #0xffff, lsl #16 cmp x0, x17 - b.eq - b + b.lo mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 cmp x0, x17 - b.lo - b + b.eq + mov x0, #0x0 // =0 + ret + mov x0, #0x5 // =5 + ret mov x17, #0x80000000 // =2147483648 cmp x0, x17 - b.eq - b + b.ne + mov x0, #0x4 // =4 + ret mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 + movk x17, #0x7fff, lsl #16 cmp x0, x17 - b.eq - b + b.ne + mov x0, #0x3 // =3 + ret + cmp x0, #0x5 + b.lo + cmp x0, #0x5 + b.ne + mov x0, #0x2 // =2 + ret + cmp x0, #0x0 + b.ne + mov x0, #0x1 // =1 + ret + mov x0, #0x0 // =0 + ret b
: diff --git a/tests/snapshots/asm/switch_binary_search.x64.asm b/tests/snapshots/asm/switch_binary_search.x64.asm index 0be54ecfb..7766cb771 100644 --- a/tests/snapshots/asm/switch_binary_search.x64.asm +++ b/tests/snapshots/asm/switch_binary_search.x64.asm @@ -14,112 +14,90 @@ Disassembly of section .text: movslq %edi, %rdi cmpq $0x1, %rdi jl - jmp + cmpq $0x2a, %rdi + jl + cmpq $0x3e8, %rdi # imm = 0x3E8 + jl + cmpq $0x3e8, %rdi # imm = 0x3E8 + je xorq %rax, %rax retq - movl $0x1, %eax - retq - movl $0x2, %eax - retq - movl $0x3, %eax - retq - movl $0x4, %eax - retq - movl $0x5, %eax + movl $0x7, %eax retq + cmpq $0x2a, %rdi + jne movl $0x6, %eax retq - movl $0x7, %eax + cmpq $0x7, %rdi + jl + cmpq $0x7, %rdi + jne + movl $0x5, %eax retq - xorq %rax, %rax + cmpq $0x1, %rdi + jne + movl $0x4, %eax retq cmpq $-0x3, %rdi jl - jmp - cmpq $0x2a, %rdi - jl - jmp - cmpq $-0x64, %rdi - je - jmp testq %rdi, %rdi jl - jmp - cmpq $-0x3, %rdi - je - jmp testq %rdi, %rdi - je - jmp - cmpq $0x7, %rdi - jl - jmp - cmpq $0x3e8, %rdi # imm = 0x3E8 - jl - jmp - cmpq $0x1, %rdi - je - jmp - cmpq $0x7, %rdi - je - jmp - cmpq $0x2a, %rdi - je - jmp - cmpq $0x3e8, %rdi # imm = 0x3E8 - je - jmp - jmp - -: - movl %edi, %eax - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - jb - jmp - xorq %rax, %rax - retq - movl $0x1, %eax - retq - movl $0x2, %eax - retq + jne movl $0x3, %eax retq - movl $0x4, %eax + cmpq $-0x3, %rdi + jne + movl $0x2, %eax retq - movl $0x5, %eax + cmpq $-0x64, %rdi + jne + movl $0x1, %eax retq xorq %rax, %rax retq - cmpq $0x5, %rax - jb jmp + +: + movl %edi, %eax + cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF + jb movl $0x80000000, %r11d # imm = 0x80000000 movq %rax, %rcx cmpq %r11, %rax jb - jmp - testq %rax, %rax - je - jmp - cmpq $0x5, %rax - je - jmp - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - je - jmp movl $0xffffffff, %r11d # imm = 0xFFFFFFFF movq %rax, %rcx cmpq %r11, %rax jb - jmp - movl $0x80000000, %r11d # imm = 0x80000000 - cmpq %r11, %rax - je - jmp movl $0xffffffff, %r11d # imm = 0xFFFFFFFF cmpq %r11, %rax je - jmp + xorq %rax, %rax + retq + movl $0x5, %eax + retq + movl $0x80000000, %r11d # imm = 0x80000000 + cmpq %r11, %rax + jne + movl $0x4, %eax + retq + cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF + jne + movl $0x3, %eax + retq + cmpq $0x5, %rax + jb + cmpq $0x5, %rax + jne + movl $0x2, %eax + retq + testq %rax, %rax + jne + movl $0x1, %eax + retq + xorq %rax, %rax + retq jmp
: @@ -247,3 +225,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_break_calls.aarch64.asm b/tests/snapshots/asm/switch_break_calls.aarch64.asm index 8ec096b49..f4495bb32 100644 --- a/tests/snapshots/asm/switch_break_calls.aarch64.asm +++ b/tests/snapshots/asm/switch_break_calls.aarch64.asm @@ -29,28 +29,22 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x1 b.lt - b + cmp x0, #0x2 + b.lt + cmp x0, #0x2 + b.eq + mov x0, #0x190 // =400 sxtw x0, w0 ret - mov x0, #0x64 // =100 - b - mov x0, #0xc8 // =200 - b mov x0, #0x12c // =300 b - mov x0, #0x190 // =400 - b - cmp x0, #0x0 - b.eq - b - cmp x0, #0x2 - b.lt - b cmp x0, #0x1 - b.eq + b.ne + mov x0, #0xc8 // =200 b - cmp x0, #0x2 - b.eq + cmp x0, #0x0 + b.ne + mov x0, #0x64 // =100 b b diff --git a/tests/snapshots/asm/switch_break_calls.x64.asm b/tests/snapshots/asm/switch_break_calls.x64.asm index a4d82e1b0..b6d8d53fa 100644 --- a/tests/snapshots/asm/switch_break_calls.x64.asm +++ b/tests/snapshots/asm/switch_break_calls.x64.asm @@ -30,28 +30,22 @@ Disassembly of section .text: movslq %edi, %rdi cmpq $0x1, %rdi jl - jmp + cmpq $0x2, %rdi + jl + cmpq $0x2, %rdi + je + movl $0x190, %eax # imm = 0x190 movslq %eax, %rax retq - movl $0x64, %eax - jmp - movl $0xc8, %eax - jmp movl $0x12c, %eax # imm = 0x12C jmp - movl $0x190, %eax # imm = 0x190 - jmp - testq %rdi, %rdi - je - jmp - cmpq $0x2, %rdi - jl - jmp cmpq $0x1, %rdi - je + jne + movl $0xc8, %eax jmp - cmpq $0x2, %rdi - je + testq %rdi, %rdi + jne + movl $0x64, %eax jmp jmp diff --git a/tests/snapshots/asm/switch_case_label_promoted.aarch64.asm b/tests/snapshots/asm/switch_case_label_promoted.aarch64.asm index f0babd65b..543f52a90 100644 --- a/tests/snapshots/asm/switch_case_label_promoted.aarch64.asm +++ b/tests/snapshots/asm/switch_case_label_promoted.aarch64.asm @@ -10,82 +10,35 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x80000000 // =2147483648 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x17, #0x80000000 // =2147483648 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - b + mov x0, #0x1 // =1 sxtw x0, w0 cmp x0, #0x1 b.eq - b - mov x0, #0x1 // =1 - b - mov x0, #0x2 // =2 - b - b mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - mov x17, #0xfffe // =65534 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - b.eq - b + mov x0, #0x3 // =3 sxtw x0, w0 cmp x0, #0x3 b.eq - b - mov x0, #0x3 // =3 - b - mov x0, #0x4 // =4 - b - b mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff00000000 // =281470681743360 - movk x0, #0xffff, lsl #48 - mov x17, #0x80000000 // =2147483648 - cmp x0, x17 - b.lt - b + mov x0, #0x5 // =5 sxtw x0, w0 cmp x0, #0x5 b.eq + mov x0, #0x3 // =3 + ret + mov x0, #0x0 // =0 + ret + mov x0, #0x2 // =2 + b + b + mov x0, #0x4 // =4 b - mov x0, #0x5 // =5 b mov x0, #0x6 // =6 b mov x0, #0x7 // =7 b - mov x17, #0xffff00000000 // =281470681743360 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - b.eq - b - mov x17, #0x80000000 // =2147483648 - cmp x0, x17 - b.eq b b - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/switch_case_label_promoted.x64.asm b/tests/snapshots/asm/switch_case_label_promoted.x64.asm index 159dd2d1f..2ef8be485 100644 --- a/tests/snapshots/asm/switch_case_label_promoted.x64.asm +++ b/tests/snapshots/asm/switch_case_label_promoted.x64.asm @@ -11,76 +11,37 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movabsq $-0x80000000, %rax # imm = 0x80000000 - cmpq $-0x80000000, %rax # imm = 0x80000000 - je - jmp + movl $0x1, %eax movslq %eax, %rax cmpq $0x1, %rax je - jmp - movl $0x1, %eax - jmp - movl $0x2, %eax - jmp - jmp movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0xfffffffe, %eax # imm = 0xFFFFFFFE - movl $0xfffffffe, %r11d # imm = 0xFFFFFFFE - cmpq %r11, %rax - je - jmp + movl $0x3, %eax movslq %eax, %rax cmpq $0x3, %rax je - jmp - movl $0x3, %eax - jmp - movl $0x4, %eax - jmp - jmp movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - movabsq $-0x100000000, %rax # imm = 0xFFFFFFFF00000000 - movl $0x80000000, %r11d # imm = 0x80000000 - movq %rax, %rcx - cmpq %r11, %rax - jl - jmp + movl $0x5, %eax movslq %eax, %rax cmpq $0x5, %rax je + movl $0x3, %eax + retq + xorq %rax, %rax + retq + movl $0x2, %eax + jmp + jmp + movl $0x4, %eax jmp - movl $0x5, %eax jmp movl $0x6, %eax jmp movl $0x7, %eax jmp - movabsq $-0x100000000, %r11 # imm = 0xFFFFFFFF00000000 - cmpq %r11, %rax - je - jmp - movl $0x80000000, %r11d # imm = 0x80000000 - cmpq %r11, %rax - je jmp jmp - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp - retq addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_default_routing.aarch64.asm b/tests/snapshots/asm/switch_default_routing.aarch64.asm index 0f620113b..117ac1309 100644 --- a/tests/snapshots/asm/switch_default_routing.aarch64.asm +++ b/tests/snapshots/asm/switch_default_routing.aarch64.asm @@ -10,27 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x63 // =99 - cmp x0, #0x2 - b.lt - b + mov x0, #0x64 // =100 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xa // =10 b mov x0, #0x14 // =20 b - mov x0, #0x64 // =100 - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x2 - b.eq b b diff --git a/tests/snapshots/asm/switch_default_routing.x64.asm b/tests/snapshots/asm/switch_default_routing.x64.asm index 3319a3cc6..56a02db02 100644 --- a/tests/snapshots/asm/switch_default_routing.x64.asm +++ b/tests/snapshots/asm/switch_default_routing.x64.asm @@ -11,27 +11,13 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x63, %eax - cmpq $0x2, %rax - jl - jmp + movl $0x64, %eax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq movl $0xa, %eax jmp movl $0x14, %eax jmp - movl $0x64, %eax - jmp - cmpq $0x1, %rax - je - jmp - cmpq $0x2, %rax - je jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_goto_label_into_case.aarch64.asm b/tests/snapshots/asm/switch_goto_label_into_case.aarch64.asm index 0383966ce..9a5abb0c9 100644 --- a/tests/snapshots/asm/switch_goto_label_into_case.aarch64.asm +++ b/tests/snapshots/asm/switch_goto_label_into_case.aarch64.asm @@ -10,62 +10,43 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 sxtw x0, w0 cmp x0, #0x3 b.lt - b - mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xa // =10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x14 // =20 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x1e // =30 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - cmp x0, #0x5 - cset x2, ge - cbz x2, - b - cmp x0, #0x2 - b.lt - b cmp x0, #0x4 b.lt - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 - b.eq - b cmp x0, #0x4 b.eq - b - b - b + cmp x0, #0x5 + cset x2, ge + cbz x2, cmp x0, #0x8 cset x2, le cbz x2, + mov x0, #0x1e // =30 + ret + mov x0, #0x0 // =0 + ret + b + cmp x0, #0x3 + b.eq b + cmp x0, #0x2 + b.lt + cmp x0, #0x2 + b.ne + mov x0, #0x14 // =20 + ret + cmp x0, #0x1 + b.ne + mov x0, #0xa // =10 + ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b + b + b + b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/switch_goto_label_into_case.x64.asm b/tests/snapshots/asm/switch_goto_label_into_case.x64.asm index 8d34485a9..9599f9be5 100644 --- a/tests/snapshots/asm/switch_goto_label_into_case.x64.asm +++ b/tests/snapshots/asm/switch_goto_label_into_case.x64.asm @@ -11,66 +11,47 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movslq %edi, %rdi cmpq $0x3, %rdi jl - jmp - xorq %rax, %rax - addq $0x10, %rsp - popq %rbp - retq - movl $0xa, %eax - addq $0x10, %rsp - popq %rbp - retq - movl $0x14, %eax - addq $0x10, %rsp - popq %rbp - retq - movl $0x1e, %eax - addq $0x10, %rsp - popq %rbp - retq + cmpq $0x4, %rdi + jl + cmpq $0x4, %rdi + je cmpq $0x5, %rdi setge %cl movzbq %cl, %rcx testq %rcx, %rcx je - jmp - cmpq $0x2, %rdi - jl - jmp - cmpq $0x4, %rdi - jl - jmp - cmpq $0x1, %rdi - je - jmp - cmpq $0x2, %rdi - je - jmp - cmpq $0x3, %rdi - je - jmp - cmpq $0x4, %rdi - je - jmp - jmp - jmp cmpq $0x8, %rdi setle %cl movzbq %cl, %rcx testq %rcx, %rcx je + movl $0x1e, %eax + retq + xorq %rax, %rax + retq jmp + cmpq $0x3, %rdi + je + jmp + cmpq $0x2, %rdi + jl + cmpq $0x2, %rdi + jne + movl $0x14, %eax + retq + cmpq $0x1, %rdi + jne + movl $0xa, %eax + retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp + jmp + jmp + jmp
: pushq %rbp @@ -141,4 +122,5 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_jump_table_dense.aarch64.asm b/tests/snapshots/asm/switch_jump_table_dense.aarch64.asm new file mode 100644 index 000000000..24d979e5e --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_dense.aarch64.asm @@ -0,0 +1,421 @@ + +switch_jump_table_dense.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sxtw x0, w0 + sub x0, x0, #0x3 + cmp x0, #0x11 + b.hs + adr x17, + ldrsw x16, [x17, x0, lsl #2] + add x17, x17, x16 + br x17 + udf #0x44 + udf #0x4c + udf #0x54 + udf #0x5c + udf #0x64 + udf #0x6c + udf #0x74 + udf #0x7c + udf #0x84 + udf #0x8c + udf #0x94 + udf #0x9c + udf #0xa4 + udf #0xb8 + udf #0xc0 + udf #0xc8 + udf #0xd0 + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x5 // =5 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x7 // =7 + ret + mov x0, #0x8 // =8 + ret + mov x0, #0x9 // =9 + ret + mov x0, #0xa // =10 + ret + mov x0, #0xb // =11 + ret + mov x0, #0xc // =12 + ret + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ret + mov x0, #0xd // =13 + ret + mov x0, #0xe // =14 + ret + mov x0, #0xf // =15 + ret + mov x0, #0x10 // =16 + ret + mov x0, #0x0 // =0 + ret + b + +: + add x0, x0, #0x6 + cmp x0, #0x9 + b.hs + adr x17, + ldrsw x16, [x17, x0, lsl #2] + add x17, x17, x16 + br x17 + udf #0x24 + udf #0x2c + udf #0x34 + udf #0x3c + udf #0x44 + udf #0x4c + udf #0x54 + udf #0x5c + udf #0x64 + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x5 // =5 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x7 // =7 + ret + mov x0, #0x8 // =8 + ret + mov x0, #0x9 // =9 + ret + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ret + mov x0, #0x0 // =0 + ret + b + +: + mov w0, w0 + mov x17, #0xfff6 // =65526 + movk x17, #0xffff, lsl #16 + sub x0, x0, x17 + cmp x0, #0xa + b.hs + adr x17, + ldrsw x16, [x17, x0, lsl #2] + add x17, x17, x16 + br x17 + udf #0x28 + udf #0x30 + udf #0x38 + udf #0x40 + udf #0x48 + udf #0x50 + udf #0x58 + udf #0x60 + udf #0x68 + udf #0x70 + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x5 // =5 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x7 // =7 + ret + mov x0, #0x8 // =8 + ret + mov x0, #0x9 // =9 + ret + mov x0, #0xa // =10 + ret + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ret + mov x0, #0x0 // =0 + ret + b + +
: + stp x20, x21, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x20, #0x3 // =3 + b + sxtw x0, w20 + cmp x0, #0xf + b.eq + sxtw x0, w20 + cmp x0, #0xf + b.ge + sub x0, x20, #0x2 + sxtw x21, w0 + mov x0, x20 + bl + sxtw x1, w21 + cmp x0, x1 + b.eq + b + sub x0, x20, #0x3 + sxtw x21, w0 + b + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0x13 + b.le + mov x0, #0xf // =15 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x2 // =2 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x14 // =20 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x4 // =4 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x5 // =5 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x80000000 // =2147483648 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x6 // =6 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0xffff // =65535 + movk x0, #0x7fff, lsl #16 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x7 // =7 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x20, #0xfffa // =65530 + movk x20, #0xffff, lsl #16 + movk x20, #0xffff, lsl #32 + movk x20, #0xffff, lsl #48 + b + mov x0, x20 + bl + add x1, x20, #0x7 + sxtw x1, w1 + cmp x0, x1 + b.ne + add x20, x20, #0x1 + cmp x20, #0x2 + b.le + mov x0, #0xfff9 // =65529 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x9 // =9 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x3 // =3 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xa // =10 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x100000000 // =4294967296 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xb // =11 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0xffff00000000 // =281470681743360 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xc // =12 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x20, #0x0 // =0 + b + mov w0, w20 + mov x17, #0xfff6 // =65526 + movk x17, #0xffff, lsl #16 + add x0, x0, x17 + mov w0, w0 + bl + mov w1, w20 + add x1, x1, #0x1 + mov w1, w1 + sxtw x1, w1 + cmp x0, x1 + b.ne + mov w0, w20 + add x20, x0, #0x1 + mov w0, w20 + cmp x0, #0xa + b.lo + mov x0, #0xfff5 // =65525 + movk x0, #0xffff, lsl #16 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xe // =14 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x0 // =0 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0xf // =15 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0xffff // =65535 + movk x0, #0x7fff, lsl #16 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x10 // =16 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0xd // =13 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x8 // =8 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldp x20, x21, [sp], #0x20 + ret + b + b + b + b diff --git a/tests/snapshots/asm/switch_jump_table_dense.x64.asm b/tests/snapshots/asm/switch_jump_table_dense.x64.asm new file mode 100644 index 000000000..ffba9e6c6 --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_dense.x64.asm @@ -0,0 +1,399 @@ + +switch_jump_table_dense.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movslq %edi, %rdi + leaq -0x3(%rdi), %rax + cmpq $0x11, %rax + jae + leaq , %r11 # + movslq (%r11,%rax,4), %r10 + addq %r11, %r10 + jmpq *%r10 + addb %r8b, (%rax) + addb %cl, (%rdx) + addb %al, (%rax) + pushq %rax + addb %al, (%rax) + addb %dl, (%rsi) + addb %al, (%rax) + popq %rsp + addb %al, (%rax) + addb %ah, (%rdx) + addb %al, (%rax) + pushq $0x6e000000 # imm = 0x6E000000 + addb %al, (%rax) + addb %dh, (%rax,%rax) + addb %bh, (%rdx) + addb %al, (%rax) + addb $0x0, (%rax) + addb %al, -0x74000000(%rsi) + addb %al, (%rax) + addb %dl, -0x63000000(%rdi) + addb %al, (%rax) + addb %ah, -0x57000000(%rbx) + addb %al, (%rax) + addb %bh, 0x1(%rax) + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq + movl $0x4, %eax + retq + movl $0x5, %eax + retq + movl $0x6, %eax + retq + movl $0x7, %eax + retq + movl $0x8, %eax + retq + movl $0x9, %eax + retq + movl $0xa, %eax + retq + movl $0xb, %eax + retq + movl $0xc, %eax + retq + movabsq $-0x1, %rax + retq + movl $0xd, %eax + retq + movl $0xe, %eax + retq + movl $0xf, %eax + retq + movl $0x10, %eax + retq + xorq %rax, %rax + retq + jmp + +: + leaq 0x6(%rdi), %rax + cmpq $0x9, %rax + jae + leaq , %r11 # + movslq (%r11,%rax,4), %r10 + addq %r11, %r10 + jmpq *%r10 + andb $0x0, %al + addb %al, (%rax) + subb (%rax), %al + addb %al, (%rax) + xorb %al, (%rax) + addb %al, (%rax) + addb %al, %ss:(%rax) + addb %bh, (%rax,%rax) + addb %al, (%rax) + addb %al, (%rax) + addb %cl, (%rax) + addb %al, (%rax) + addb %r8b, (%rax) + addb %dl, (%rax,%rax) + addb %bh, 0x1(%rax) + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq + movl $0x4, %eax + retq + movl $0x5, %eax + retq + movl $0x6, %eax + retq + movl $0x7, %eax + retq + movl $0x8, %eax + retq + movl $0x9, %eax + retq + movabsq $-0x1, %rax + retq + xorq %rax, %rax + retq + jmp + +: + movl %edi, %eax + movl $0xfffffff6, %r11d # imm = 0xFFFFFFF6 + subq %r11, %rax + cmpq $0xa, %rax + jae + leaq , %r11 # + movslq (%r11,%rax,4), %r10 + addq %r11, %r10 + jmpq *%r10 + subb %al, (%rax) + addb %al, (%rax) + addb %al, %cs:(%rax) + addb %dh, (%rax,%rax) + addb %al, (%rax) + cmpb (%rax), %al + addb %al, (%rax) + addb %al, (%rax) + addb %al, (%rsi) + addb %al, (%rax) + addb %r8b, (%rax) + addb %dl, (%rdx) + addb %al, (%rax) + popq %rax + addb %al, (%rax) + addb %bl, (%rsi) + addb %al, (%rax) + movl $0x1, %eax + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq + movl $0x4, %eax + retq + movl $0x5, %eax + retq + movl $0x6, %eax + retq + movl $0x7, %eax + retq + movl $0x8, %eax + retq + movl $0x9, %eax + retq + movl $0xa, %eax + retq + movabsq $-0x1, %rax + retq + xorq %rax, %rax + retq + jmp + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movl $0x3, %ebx + jmp + movslq %ebx, %rax + cmpq $0xf, %rax + je + movslq %ebx, %rax + cmpq $0xf, %rax + jge + leaq -0x2(%rbx), %rax + movslq %eax, %r12 + movq %rbx, %rdi + callq + movslq %r12d, %rcx + cmpq %rcx, %rax + je + jmp + leaq -0x3(%rbx), %rax + movslq %eax, %r12 + jmp + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0x13, %rax + jle + movl $0xf, %edi + callq + cmpq $-0x1, %rax + je + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x2, %edi + callq + cmpq $-0x1, %rax + je + movl $0x3, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x14, %edi + callq + cmpq $-0x1, %rax + je + movl $0x4, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movabsq $-0x1, %rdi + callq + cmpq $-0x1, %rax + je + movl $0x5, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movabsq $-0x80000000, %rdi # imm = 0x80000000 + callq + cmpq $-0x1, %rax + je + movl $0x6, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x7fffffff, %edi # imm = 0x7FFFFFFF + callq + cmpq $-0x1, %rax + je + movl $0x7, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movabsq $-0x6, %rbx + jmp + movq %rbx, %rdi + callq + leaq 0x7(%rbx), %rcx + movslq %ecx, %rcx + cmpq %rcx, %rax + jne + incq %rbx + cmpq $0x2, %rbx + jle + movabsq $-0x7, %rdi + callq + cmpq $-0x1, %rax + je + movl $0x9, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x3, %edi + callq + cmpq $-0x1, %rax + je + movl $0xa, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movabsq $0x100000000, %rdi # imm = 0x100000000 + callq + cmpq $-0x1, %rax + je + movl $0xb, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movabsq $-0x100000000, %rdi # imm = 0xFFFFFFFF00000000 + callq + cmpq $-0x1, %rax + je + movl $0xc, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + xorq %rbx, %rbx + jmp + movl %ebx, %eax + movl $0xfffffff6, %r11d # imm = 0xFFFFFFF6 + addq %r11, %rax + movl %eax, %edi + callq + movl %ebx, %ecx + incq %rcx + movl %ecx, %ecx + movslq %ecx, %rcx + cmpq %rcx, %rax + jne + movl %ebx, %eax + leaq 0x1(%rax), %rbx + movl %ebx, %eax + cmpq $0xa, %rax + jb + movl $0xfffffff5, %edi # imm = 0xFFFFFFF5 + callq + cmpq $-0x1, %rax + je + movl $0xe, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + xorq %rdi, %rdi + callq + cmpq $-0x1, %rax + je + movl $0xf, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x7fffffff, %edi # imm = 0x7FFFFFFF + callq + cmpq $-0x1, %rax + je + movl $0x10, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0xd, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x8, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + jmp + jmp + jmp + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/switch_jump_table_phi_join.aarch64.asm b/tests/snapshots/asm/switch_jump_table_phi_join.aarch64.asm new file mode 100644 index 000000000..051945bd5 --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_phi_join.aarch64.asm @@ -0,0 +1,134 @@ + +switch_jump_table_phi_join.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x3, x1 + sxtw x0, w0 + cmp x0, #0xc + b.hs + adr x17, + ldrsw x16, [x17, x0, lsl #2] + add x17, x17, x16 + br x17 + udf #0x30 + udf #0x6c + udf #0x70 + udf #0x74 + udf #0x78 + udf #0x7c + udf #0x80 + udf #0x84 + udf #0x88 + udf #0x8c + udf #0x90 + udf #0xa8 + add x3, x3, #0x1 + add x2, x3, #0x2 + add x3, x3, x2 + mov x17, #0x3 // =3 + mul x2, x2, x17 + sub x3, x3, x2 + add x2, x2, x3 + lsl x3, x3, #1 + sub x2, x2, #0x1 + add x3, x3, #0x7 + add x2, x2, x3 + mov x17, #0x1f // =31 + mul x0, x3, x17 + add x0, x0, x2 + ret + b + b + b + b + b + b + b + b + b + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + mul x3, x3, x17 + b + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + mul x2, x2, x17 + b + mov x3, #0xd // =13 + mov x2, #0x11 // =17 + b + b + +
: + stp x20, x21, [sp, #-0x30]! + str x22, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + mov x1, #0x0 // =0 + mov x20, #0xfffe // =65534 + movk x20, #0xffff, lsl #16 + movk x20, #0xffff, lsl #32 + movk x20, #0xffff, lsl #48 + b + mov x21, #0xffff // =65535 + movk x21, #0xffff, lsl #16 + movk x21, #0xffff, lsl #32 + movk x21, #0xffff, lsl #48 + b + mov x2, #0x0 // =0 + mov x17, #0x21 // =33 + mul x22, x1, x17 + mov x0, x20 + mov x1, x21 + bl + add x0, x22, x0 + mov x2, #0x1 // =1 + mov x17, #0x21 // =33 + mul x22, x0, x17 + mov x0, x20 + mov x1, x21 + bl + add x0, x22, x0 + mov x2, #0x2 // =2 + mov x17, #0x21 // =33 + mul x22, x0, x17 + mov x0, x20 + mov x1, x21 + bl + add x1, x22, x0 + add x21, x21, #0x1 + cmp x21, #0x3 + b.lt + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0xe + b.lt + mov x17, #0x2760 // =10080 + movk x17, #0x4634, lsl #16 + movk x17, #0xf948, lsl #32 + movk x17, #0xd14a, lsl #48 + cmp x1, x17 + b.ne + mov x1, #0x0 // =0 + mov x0, x1 + ldp x29, x30, [sp, #0x20] + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + mov x1, #0x1 // =1 + b + b + b diff --git a/tests/snapshots/asm/switch_jump_table_phi_join.x64.asm b/tests/snapshots/asm/switch_jump_table_phi_join.x64.asm new file mode 100644 index 000000000..0000474a3 --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_phi_join.x64.asm @@ -0,0 +1,126 @@ + +switch_jump_table_phi_join.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movslq %edi, %rdi + cmpq $0xc, %rdi + jae + leaq , %r11 # + movslq (%r11,%rdi,4), %r10 + addq %r11, %r10 + jmpq *%r10 + xorb %al, (%rax) + addb %al, (%rax) + + addb %al, (%rax) + addb %ah, (%rdx) + addb %al, (%rax) + addb %al, %fs:(%rax) + addb %ah, (%rsi) + addb %al, (%rax) + pushq $0x6a000000 # imm = 0x6A000000 + addb %al, (%rax) + addb %ch, (%rax,%rax) + addb %ch, (%rsi) + addb %al, (%rax) + jo + addb %al, (%rax) + jb + addb %al, (%rax) + jnp + addb %al, (%rax) + incq %rsi + leaq 0x2(%rsi), %rdx + addq %rdx, %rsi + leaq (%rdx,%rdx,2), %rdx + subq %rdx, %rsi + addq %rsi, %rdx + shlq $0x1, %rsi + decq %rdx + addq $0x7, %rsi + addq %rsi, %rdx + imulq $0x1f, %rsi, %rax + addq %rdx, %rax + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + imulq $-0x1, %rsi, %rsi + jmp + imulq $-0x1, %rdx, %rdx + jmp + movl $0xd, %esi + movl $0x11, %edx + jmp + jmp + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + xorq %rcx, %rcx + movabsq $-0x2, %rbx + jmp + movabsq $-0x1, %r12 + jmp + xorq %rdx, %rdx + imulq $0x21, %rcx, %r13 + movq %rbx, %rdi + movq %r12, %rsi + callq + addq %r13, %rax + movl $0x1, %edx + imulq $0x21, %rax, %r13 + movq %rbx, %rdi + movq %r12, %rsi + callq + addq %r13, %rax + movl $0x2, %edx + imulq $0x21, %rax, %r13 + movq %rbx, %rdi + movq %r12, %rsi + callq + leaq (%r13,%rax), %rcx + incq %r12 + cmpq $0x3, %r12 + jl + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0xe, %rax + jl + movabsq $-0x2eb506b7b9cbd8a0, %r11 # imm = 0xD14AF94846342760 + movq %rcx, %rax + cmpq %r11, %rcx + jne + xorq %rcx, %rcx + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq %rcx, %rax + addq $0x20, %rsp + popq %rbp + retq + movl $0x1, %ecx + jmp + jmp + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/switch_jump_table_sparse_kept.aarch64.asm b/tests/snapshots/asm/switch_jump_table_sparse_kept.aarch64.asm new file mode 100644 index 000000000..19b359104 --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_sparse_kept.aarch64.asm @@ -0,0 +1,146 @@ + +switch_jump_table_sparse_kept.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sxtw x0, w0 + cmp x0, #0x32 + b.lt + cmp x0, #0x46 + b.lt + cmp x0, #0x50 + b.lt + cmp x0, #0x5a + b.lt + cmp x0, #0x5a + b.eq + mov x0, #0xffff // =65535 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + ret + mov x0, #0xa // =10 + ret + cmp x0, #0x50 + b.ne + mov x0, #0x9 // =9 + ret + cmp x0, #0x46 + b.ne + mov x0, #0x8 // =8 + ret + cmp x0, #0x3c + b.lt + cmp x0, #0x3c + b.ne + mov x0, #0x7 // =7 + ret + cmp x0, #0x32 + b.ne + mov x0, #0x6 // =6 + ret + cmp x0, #0x14 + b.lt + cmp x0, #0x1e + b.lt + cmp x0, #0x28 + b.lt + cmp x0, #0x28 + b.ne + mov x0, #0x5 // =5 + ret + cmp x0, #0x1e + b.ne + mov x0, #0x4 // =4 + ret + cmp x0, #0x14 + b.ne + mov x0, #0x3 // =3 + ret + cmp x0, #0xa + b.lt + cmp x0, #0xa + b.ne + mov x0, #0x2 // =2 + ret + cmp x0, #0x0 + b.ne + mov x0, #0x1 // =1 + ret + mov x0, #0x0 // =0 + ret + b + +
: + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x20, #0x0 // =0 + b + mov x17, #0xa // =10 + mul x0, x20, x17 + bl + add x1, x20, #0x1 + sxtw x1, w1 + cmp x0, x1 + b.ne + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0xa + b.lt + mov x0, #0x5 // =5 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0xfff6 // =65526 + movk x0, #0xffff, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x64 // =100 + bl + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x4 // =4 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + b diff --git a/tests/snapshots/asm/switch_jump_table_sparse_kept.x64.asm b/tests/snapshots/asm/switch_jump_table_sparse_kept.x64.asm new file mode 100644 index 000000000..dbca9ac06 --- /dev/null +++ b/tests/snapshots/asm/switch_jump_table_sparse_kept.x64.asm @@ -0,0 +1,136 @@ + +switch_jump_table_sparse_kept.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + movslq %edi, %rdi + cmpq $0x32, %rdi + jl + cmpq $0x46, %rdi + jl + cmpq $0x50, %rdi + jl + cmpq $0x5a, %rdi + jl + cmpq $0x5a, %rdi + je + movabsq $-0x1, %rax + retq + movl $0xa, %eax + retq + cmpq $0x50, %rdi + jne + movl $0x9, %eax + retq + cmpq $0x46, %rdi + jne + movl $0x8, %eax + retq + cmpq $0x3c, %rdi + jl + cmpq $0x3c, %rdi + jne + movl $0x7, %eax + retq + cmpq $0x32, %rdi + jne + movl $0x6, %eax + retq + cmpq $0x14, %rdi + jl + cmpq $0x1e, %rdi + jl + cmpq $0x28, %rdi + jl + cmpq $0x28, %rdi + jne + movl $0x5, %eax + retq + cmpq $0x1e, %rdi + jne + movl $0x4, %eax + retq + cmpq $0x14, %rdi + jne + movl $0x3, %eax + retq + cmpq $0xa, %rdi + jl + cmpq $0xa, %rdi + jne + movl $0x2, %eax + retq + testq %rdi, %rdi + jne + movl $0x1, %eax + retq + xorq %rax, %rax + retq + jmp + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + xorq %rbx, %rbx + jmp + imulq $0xa, %rbx, %rdi + callq + leaq 0x1(%rbx), %rcx + movslq %ecx, %rcx + cmpq %rcx, %rax + jne + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0xa, %rax + jl + movl $0x5, %edi + callq + cmpq $-0x1, %rax + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movabsq $-0xa, %rdi + callq + cmpq $-0x1, %rax + je + movl $0x3, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movl $0x64, %edi + callq + cmpq $-0x1, %rax + je + movl $0x4, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_label_after_terminator.aarch64.asm b/tests/snapshots/asm/switch_label_after_terminator.aarch64.asm index b4b81ea66..ad755a4b8 100644 --- a/tests/snapshots/asm/switch_label_after_terminator.aarch64.asm +++ b/tests/snapshots/asm/switch_label_after_terminator.aarch64.asm @@ -13,36 +13,30 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x2 b.lt - b - mov x0, #0x0 // =0 - ret - mov x1, #0x1 // =1 - b - mov x1, #0x2 // =2 - b - mov x1, #0x3 // =3 - b + cmp x0, #0x3 + b.lt + cmp x0, #0x3 + b.eq mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 ret - cmp x0, #0x1 - b.eq - b - cmp x0, #0x3 - b.lt - b + mov x1, #0x3 // =3 + add x0, x1, #0x64 + sxtw x0, w0 + ret cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 - b.eq + b.ne + mov x1, #0x2 // =2 b + cmp x0, #0x1 + b.ne + mov x1, #0x1 // =1 b - add x0, x1, #0x64 - sxtw x0, w0 + mov x0, #0x0 // =0 ret + b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/switch_label_after_terminator.x64.asm b/tests/snapshots/asm/switch_label_after_terminator.x64.asm index 7e090027d..8d6d3b5e1 100644 --- a/tests/snapshots/asm/switch_label_after_terminator.x64.asm +++ b/tests/snapshots/asm/switch_label_after_terminator.x64.asm @@ -14,33 +14,27 @@ Disassembly of section .text: movslq %edi, %rdi cmpq $0x2, %rdi jl - jmp - xorq %rax, %rax - retq - movl $0x1, %ecx - jmp - movl $0x2, %ecx - jmp - movl $0x3, %ecx - jmp - movabsq $-0x1, %rax - retq - cmpq $0x1, %rdi - je - jmp cmpq $0x3, %rdi jl - jmp - cmpq $0x2, %rdi - je - jmp cmpq $0x3, %rdi je - jmp - jmp + movabsq $-0x1, %rax + retq + movl $0x3, %ecx leaq 0x64(%rcx), %rax movslq %eax, %rax retq + cmpq $0x2, %rdi + jne + movl $0x2, %ecx + jmp + cmpq $0x1, %rdi + jne + movl $0x1, %ecx + jmp + xorq %rax, %rax + retq + jmp
: pushq %rbp diff --git a/tests/snapshots/asm/switch_multilabel.aarch64.asm b/tests/snapshots/asm/switch_multilabel.aarch64.asm index 533c5000d..141f216fd 100644 --- a/tests/snapshots/asm/switch_multilabel.aarch64.asm +++ b/tests/snapshots/asm/switch_multilabel.aarch64.asm @@ -13,70 +13,65 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x42 b.lt - b + cmp x0, #0x62 + b.lt + cmp x0, #0x63 + b.lt + cmp x0, #0x64 + b.lt + cmp x0, #0x64 + b.eq mov x0, #0x0 // =0 ret mov x0, #0x1 // =1 ret - mov x0, #0x2 // =2 - ret - mov x0, #0x3 // =3 - ret - mov x0, #0x0 // =0 - ret - cmp x0, #0x32 - b.lt + cmp x0, #0x63 + b.eq b cmp x0, #0x62 - b.lt + b.eq b - cmp x0, #0x31 + cmp x0, #0x61 b.lt + cmp x0, #0x61 + b.eq b + cmp x0, #0x42 + b.ne + mov x0, #0x2 // =2 + ret + cmp x0, #0x32 + b.lt cmp x0, #0x33 b.lt - b - cmp x0, #0x30 - b.eq - b - cmp x0, #0x31 + cmp x0, #0x41 + b.lt + cmp x0, #0x41 b.eq b + cmp x0, #0x33 + b.ne + mov x0, #0x3 // =3 + ret cmp x0, #0x32 b.eq b - cmp x0, #0x41 + cmp x0, #0x31 b.lt - b - cmp x0, #0x33 + cmp x0, #0x31 b.eq b - cmp x0, #0x41 + cmp x0, #0x30 b.eq b - cmp x0, #0x61 - b.lt - b - cmp x0, #0x63 - b.lt + mov x0, #0x0 // =0 + ret b - cmp x0, #0x42 - b.eq b - cmp x0, #0x61 - b.eq b - cmp x0, #0x62 - b.eq b - cmp x0, #0x64 - b.lt b - cmp x0, #0x63 - b.eq b - cmp x0, #0x64 - b.eq b b diff --git a/tests/snapshots/asm/switch_multilabel.x64.asm b/tests/snapshots/asm/switch_multilabel.x64.asm index b73986bfc..945acfa95 100644 --- a/tests/snapshots/asm/switch_multilabel.x64.asm +++ b/tests/snapshots/asm/switch_multilabel.x64.asm @@ -14,70 +14,65 @@ Disassembly of section .text: movslq %edi, %rdi cmpq $0x42, %rdi jl - jmp + cmpq $0x62, %rdi + jl + cmpq $0x63, %rdi + jl + cmpq $0x64, %rdi + jl + cmpq $0x64, %rdi + je xorq %rax, %rax retq movl $0x1, %eax retq - movl $0x2, %eax - retq - movl $0x3, %eax - retq - xorq %rax, %rax - retq - cmpq $0x32, %rdi - jl + cmpq $0x63, %rdi + je jmp cmpq $0x62, %rdi - jl + je jmp - cmpq $0x31, %rdi + cmpq $0x61, %rdi jl + cmpq $0x61, %rdi + je jmp + cmpq $0x42, %rdi + jne + movl $0x2, %eax + retq + cmpq $0x32, %rdi + jl cmpq $0x33, %rdi jl - jmp - cmpq $0x30, %rdi - je - jmp - cmpq $0x31, %rdi + cmpq $0x41, %rdi + jl + cmpq $0x41, %rdi je jmp + cmpq $0x33, %rdi + jne + movl $0x3, %eax + retq cmpq $0x32, %rdi je jmp - cmpq $0x41, %rdi + cmpq $0x31, %rdi jl - jmp - cmpq $0x33, %rdi + cmpq $0x31, %rdi je jmp - cmpq $0x41, %rdi + cmpq $0x30, %rdi je jmp - cmpq $0x61, %rdi - jl - jmp - cmpq $0x63, %rdi - jl + xorq %rax, %rax + retq jmp - cmpq $0x42, %rdi - je jmp - cmpq $0x61, %rdi - je jmp - cmpq $0x62, %rdi - je jmp - cmpq $0x64, %rdi - jl jmp - cmpq $0x63, %rdi - je jmp - cmpq $0x64, %rdi - je jmp jmp diff --git a/tests/snapshots/asm/switch_nested_case_in_compound.aarch64.asm b/tests/snapshots/asm/switch_nested_case_in_compound.aarch64.asm index bd4eb078f..85d600240 100644 --- a/tests/snapshots/asm/switch_nested_case_in_compound.aarch64.asm +++ b/tests/snapshots/asm/switch_nested_case_in_compound.aarch64.asm @@ -10,125 +10,61 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x19, [sp, #0x10] - mov x20, #0x0 // =0 - mov x0, #0x2 // =2 - cmp x0, #0x2 - b.lt - b - sxtw x0, w20 - cmp x0, #0x7 - b.eq - b - mov x0, #0x64 // =100 - add x1, x20, x0 - cmp x0, #0x64 - b.ne - b - add x0, x20, #0x1 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x1, #0x0 // =0 + add x0, x1, #0x1 add x0, x0, #0x2 - add x20, x0, #0x4 - b - mov x17, #0x4000 // =16384 - orr x20, x20, x17 - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x3 - b.lt - b - cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 + add x1, x0, #0x4 + sxtw x0, w1 + cmp x0, #0x7 b.eq - b - b - mov x17, #0x1000 // =4096 - orr x20, x1, x17 - b - mov x17, #0x2000 // =8192 - orr x20, x1, x17 - b adrp x0, add x0, x0, - sxtw x1, w20 + sxtw x1, w1 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x20, #0x0 // =0 - mov x0, #0x1 // =1 - cmp x0, #0x2 - b.lt - b - sxtw x0, w20 + mov x1, #0x0 // =0 + mov x1, #0x1064 // =4196 + add x0, x1, #0x1 + add x0, x0, #0x2 + add x1, x0, #0x4 + sxtw x0, w1 mov x17, #0x106b // =4203 cmp x0, x17 b.eq - b - mov x0, #0x64 // =100 - add x1, x20, x0 - cmp x0, #0x64 - b.ne - b - add x0, x20, #0x1 - add x0, x0, #0x2 - add x20, x0, #0x4 - b - mov x17, #0x4000 // =16384 - orr x20, x20, x17 - b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x3 - b.lt - b - cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 - b.eq - b - b - mov x17, #0x1000 // =4096 - orr x20, x1, x17 - b - mov x17, #0x2000 // =8192 - orr x20, x1, x17 - b adrp x0, add x0, x0, - sxtw x1, w20 + sxtw x1, w1 bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b + mov x1, #0x4000 // =16384 + b + b + b + b + mov x1, #0x1064 // =4196 b + mov x1, #0x2064 // =8292 b + mov x1, #0x4000 // =16384 b b b b + mov x1, #0x2064 // =8292 b diff --git a/tests/snapshots/asm/switch_nested_case_in_compound.x64.asm b/tests/snapshots/asm/switch_nested_case_in_compound.x64.asm index e91c5cbce..3978db765 100644 --- a/tests/snapshots/asm/switch_nested_case_in_compound.x64.asm +++ b/tests/snapshots/asm/switch_nested_case_in_compound.x64.asm @@ -13,117 +13,55 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) - xorq %rbx, %rbx - movl $0x2, %eax - cmpq $0x2, %rax - jl - jmp - movslq %ebx, %rax - cmpq $0x7, %rax - je - jmp - movl $0x64, %eax - leaq (%rbx,%rax), %rcx - cmpq $0x64, %rax - jne - jmp - leaq 0x1(%rbx), %rax + xorq %rcx, %rcx + leaq 0x1(%rcx), %rax addq $0x2, %rax - leaq 0x4(%rax), %rbx - jmp - orq $0x4000, %rbx # imm = 0x4000 - jmp - cmpq $0x1, %rax - je - jmp - cmpq $0x3, %rax - jl - jmp - cmpq $0x2, %rax - je - jmp - cmpq $0x3, %rax + leaq 0x4(%rax), %rcx + movslq %ecx, %rax + cmpq $0x7, %rax je - jmp - jmp - movq %rcx, %rbx - orq $0x1000, %rbx # imm = 0x1000 - jmp - movq %rcx, %rbx - orq $0x2000, %rbx # imm = 0x2000 - jmp leaq , %rdi - movslq %ebx, %rsi + movslq %ecx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq - xorq %rbx, %rbx - movl $0x1, %eax - cmpq $0x2, %rax - jl - jmp - movslq %ebx, %rax - cmpq $0x106b, %rax # imm = 0x106B - je - jmp - movl $0x64, %eax - leaq (%rbx,%rax), %rcx - cmpq $0x64, %rax - jne - jmp - leaq 0x1(%rbx), %rax + xorq %rcx, %rcx + movl $0x1064, %ecx # imm = 0x1064 + leaq 0x1(%rcx), %rax addq $0x2, %rax - leaq 0x4(%rax), %rbx - jmp - orq $0x4000, %rbx # imm = 0x4000 - jmp - cmpq $0x1, %rax - je - jmp - cmpq $0x3, %rax - jl - jmp - cmpq $0x2, %rax - je - jmp - cmpq $0x3, %rax + leaq 0x4(%rax), %rcx + movslq %ecx, %rax + cmpq $0x106b, %rax # imm = 0x106B je - jmp - jmp - movq %rcx, %rbx - orq $0x1000, %rbx # imm = 0x1000 - jmp - movq %rcx, %rbx - orq $0x2000, %rbx # imm = 0x2000 - jmp leaq , %rdi - movslq %ebx, %rsi + movslq %ecx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq jmp + movl $0x4000, %ecx # imm = 0x4000 + jmp + jmp + jmp + jmp + movl $0x1064, %ecx # imm = 0x1064 jmp + movl $0x2064, %ecx # imm = 0x2064 jmp + movl $0x4000, %ecx # imm = 0x4000 jmp jmp jmp jmp + movl $0x2064, %ecx # imm = 0x2064 jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_statement.aarch64.asm b/tests/snapshots/asm/switch_statement.aarch64.asm index 967464c06..2f901369d 100644 --- a/tests/snapshots/asm/switch_statement.aarch64.asm +++ b/tests/snapshots/asm/switch_statement.aarch64.asm @@ -10,37 +10,16 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x2 // =2 - mov x2, #0x0 // =0 - cmp x0, #0x2 - b.lt - b + mov x1, #0x0 // =0 + mov x1, #0x14 // =20 + add x0, x1, #0x5 + sxtw x0, w0 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xa // =10 b - mov x2, #0x14 // =20 - add x0, x2, #0x5 - sxtw x0, w0 - b mov x0, #0x64 // =100 b - cmp x0, #0x1 - b.eq - b - cmp x0, #0x3 - b.lt - b - cmp x0, #0x2 - b.eq - b - cmp x0, #0x3 - b.eq b b b diff --git a/tests/snapshots/asm/switch_statement.x64.asm b/tests/snapshots/asm/switch_statement.x64.asm index 092e43bd3..55f27e07a 100644 --- a/tests/snapshots/asm/switch_statement.x64.asm +++ b/tests/snapshots/asm/switch_statement.x64.asm @@ -11,38 +11,17 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x2, %eax - xorq %rdx, %rdx - cmpq $0x2, %rax - jl - jmp + xorq %rcx, %rcx + movl $0x14, %ecx + leaq 0x5(%rcx), %rax + movslq %eax, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq movl $0xa, %eax jmp - movl $0x14, %edx - leaq 0x5(%rdx), %rax - movslq %eax, %rax - jmp movl $0x64, %eax jmp - cmpq $0x1, %rax - je - jmp - cmpq $0x3, %rax - jl - jmp - cmpq $0x2, %rax - je - jmp - cmpq $0x3, %rax - je jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/switch_unsigned_negative_case.aarch64.asm b/tests/snapshots/asm/switch_unsigned_negative_case.aarch64.asm index a31023fab..aa6dd5e17 100644 --- a/tests/snapshots/asm/switch_unsigned_negative_case.aarch64.asm +++ b/tests/snapshots/asm/switch_unsigned_negative_case.aarch64.asm @@ -15,35 +15,30 @@ Disassembly of section .text: movk x17, #0xffff, lsl #16 cmp x0, x17 b.lo - b - mov x0, #0x0 // =0 - ret - mov x0, #0x64 // =100 - ret - mov x0, #0xc8 // =200 - ret - mov x0, #0x5 // =5 - ret - mov x0, #0x3e7 // =999 - ret - cmp x0, #0x5 - b.eq - b mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 cmp x0, x17 b.lo - b - mov x17, #0xfffe // =65534 + mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 cmp x0, x17 b.eq - b - mov x17, #0xffff // =65535 + mov x0, #0x3e7 // =999 + ret + mov x0, #0x64 // =100 + ret + mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 cmp x0, x17 - b.eq - b + b.ne + mov x0, #0xc8 // =200 + ret + cmp x0, #0x5 + b.ne + mov x0, #0x5 // =5 + ret + mov x0, #0x0 // =0 + ret b : @@ -55,25 +50,22 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 cmp x0, x17 b.lo - b - mov x0, #0x0 // =0 - ret - mov x0, #0x64 // =100 - ret - mov x0, #0x7 // =7 - ret - mov x0, #0x3e7 // =999 - ret - cmp x0, #0x7 - b.eq - b mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 b.eq - b + mov x0, #0x3e7 // =999 + ret + mov x0, #0x64 // =100 + ret + cmp x0, #0x7 + b.ne + mov x0, #0x7 // =7 + ret + mov x0, #0x0 // =0 + ret b : @@ -85,25 +77,22 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 cmp x0, x17 b.lo - b - mov x0, #0x0 // =0 - ret - mov x0, #0x64 // =100 - ret - mov x0, #0x3 // =3 - ret - mov x0, #0x3e7 // =999 - ret - cmp x0, #0x3 - b.eq - b mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 b.eq - b + mov x0, #0x3e7 // =999 + ret + mov x0, #0x64 // =100 + ret + cmp x0, #0x3 + b.ne + mov x0, #0x3 // =3 + ret + mov x0, #0x0 // =0 + ret b : @@ -114,29 +103,26 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 cmp x0, x17 b.lt - b - mov x0, #0x0 // =0 - ret - mov x0, #0x64 // =100 - ret - mov x0, #0xc8 // =200 - ret - mov x0, #0x3e7 // =999 - ret - mov x17, #0xfffe // =65534 + mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 b.eq - b - mov x17, #0xffff // =65535 + mov x0, #0x3e7 // =999 + ret + mov x0, #0x64 // =100 + ret + mov x17, #0xfffe // =65534 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 cmp x0, x17 - b.eq - b + b.ne + mov x0, #0xc8 // =200 + ret + mov x0, #0x0 // =0 + ret b
: diff --git a/tests/snapshots/asm/switch_unsigned_negative_case.x64.asm b/tests/snapshots/asm/switch_unsigned_negative_case.x64.asm index 60c264634..9df0f2207 100644 --- a/tests/snapshots/asm/switch_unsigned_negative_case.x64.asm +++ b/tests/snapshots/asm/switch_unsigned_negative_case.x64.asm @@ -16,33 +16,28 @@ Disassembly of section .text: movq %rax, %rcx cmpq %r11, %rax jb - jmp - xorq %rax, %rax + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + movq %rax, %rcx + cmpq %r11, %rax + jb + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + cmpq %r11, %rax + je + movl $0x3e7, %eax # imm = 0x3E7 retq movl $0x64, %eax retq + movl $0xfffffffe, %r11d # imm = 0xFFFFFFFE + cmpq %r11, %rax + jne movl $0xc8, %eax retq + cmpq $0x5, %rax + jne movl $0x5, %eax retq - movl $0x3e7, %eax # imm = 0x3E7 + xorq %rax, %rax retq - cmpq $0x5, %rax - je - jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rax, %rcx - cmpq %r11, %rax - jb - jmp - movl $0xfffffffe, %r11d # imm = 0xFFFFFFFE - cmpq %r11, %rax - je - jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - je - jmp jmp : @@ -50,21 +45,18 @@ Disassembly of section .text: andq $0xffff, %rax # imm = 0xFFFF cmpq $-0x1, %rax jb - jmp - xorq %rax, %rax + cmpq $-0x1, %rax + je + movl $0x3e7, %eax # imm = 0x3E7 retq movl $0x64, %eax retq + cmpq $0x7, %rax + jne movl $0x7, %eax retq - movl $0x3e7, %eax # imm = 0x3E7 + xorq %rax, %rax retq - cmpq $0x7, %rax - je - jmp - cmpq $-0x1, %rax - je - jmp jmp : @@ -72,42 +64,36 @@ Disassembly of section .text: andq $0xff, %rax cmpq $-0x1, %rax jb - jmp - xorq %rax, %rax + cmpq $-0x1, %rax + je + movl $0x3e7, %eax # imm = 0x3E7 retq movl $0x64, %eax retq + cmpq $0x3, %rax + jne movl $0x3, %eax retq - movl $0x3e7, %eax # imm = 0x3E7 + xorq %rax, %rax retq - cmpq $0x3, %rax - je - jmp - cmpq $-0x1, %rax - je - jmp jmp : movslq %edi, %rdi cmpq $-0x1, %rdi jl - jmp - xorq %rax, %rax + cmpq $-0x1, %rdi + je + movl $0x3e7, %eax # imm = 0x3E7 retq movl $0x64, %eax retq + cmpq $-0x2, %rdi + jne movl $0xc8, %eax retq - movl $0x3e7, %eax # imm = 0x3E7 + xorq %rax, %rax retq - cmpq $-0x2, %rdi - je - jmp - cmpq $-0x1, %rdi - je - jmp jmp
: diff --git a/tests/snapshots/asm/sxtw_fold_source_liveness.aarch64.asm b/tests/snapshots/asm/sxtw_fold_source_liveness.aarch64.asm index e812fb190..2e68ef52b 100644 --- a/tests/snapshots/asm/sxtw_fold_source_liveness.aarch64.asm +++ b/tests/snapshots/asm/sxtw_fold_source_liveness.aarch64.asm @@ -10,25 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 lsl x2, x0, #32 add x0, x0, x1 asr x2, x2, #32 add x0, x2, x0 add x0, x0, x1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: - mov x0, #0x2 // =2 - mov x1, #0x7 // =7 - lsl x2, x0, #32 - add x0, x0, x1 - asr x2, x2, #32 - add x0, x2, x0 - add x0, x0, x1 - sxtw x0, w0 + mov x0, #0x12 // =18 ret diff --git a/tests/snapshots/asm/sxtw_fold_source_liveness.x64.asm b/tests/snapshots/asm/sxtw_fold_source_liveness.x64.asm index 635b6be10..018a8fa00 100644 --- a/tests/snapshots/asm/sxtw_fold_source_liveness.x64.asm +++ b/tests/snapshots/asm/sxtw_fold_source_liveness.x64.asm @@ -11,26 +11,12 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq (%rdi,%rsi), %rcx movslq %edi, %rax addq %rcx, %rax addq %rsi, %rax - addq $0x20, %rsp - popq %rbp retq
: - movl $0x2, %eax - movl $0x7, %ecx - movq %rax, %rdx - shlq $0x20, %rdx - addq %rcx, %rax - sarq $0x20, %rdx - addq %rdx, %rax - addq %rcx, %rax - movslq %eax, %rax + movl $0x12, %eax retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/symbol_inner_array_size_no_leak.aarch64.asm b/tests/snapshots/asm/symbol_inner_array_size_no_leak.aarch64.asm index 31b7cb97a..ecbdc74ef 100644 --- a/tests/snapshots/asm/symbol_inner_array_size_no_leak.aarch64.asm +++ b/tests/snapshots/asm/symbol_inner_array_size_no_leak.aarch64.asm @@ -12,18 +12,15 @@ Disassembly of section .text: brk #: sxtw x1, w1 mov x3, #0x0 // =0 - sxtw x2, w3 - cmp x2, x1 - b.ge b - add x3, x3, #0x1 - b - sxtw x2, w3 mov x17, #0x3 // =3 mul x4, x2, x17 sxtw x5, w4 strh w5, [x0, x2, lsl #1] - b + add x3, x3, #0x1 + sxtw x2, w3 + cmp x2, x1 + b.lt sub x1, x1, #0x1 sxtw x1, w1 ldrsh x0, [x0, x1, lsl #1] diff --git a/tests/snapshots/asm/symbol_inner_array_size_no_leak.x64.asm b/tests/snapshots/asm/symbol_inner_array_size_no_leak.x64.asm index 77da3b126..dfb2422d3 100644 --- a/tests/snapshots/asm/symbol_inner_array_size_no_leak.x64.asm +++ b/tests/snapshots/asm/symbol_inner_array_size_no_leak.x64.asm @@ -13,17 +13,14 @@ Disassembly of section .text: : movslq %esi, %rsi xorq %rcx, %rcx - movslq %ecx, %rax - cmpq %rsi, %rax - jge jmp - incq %rcx - jmp - movslq %ecx, %rax leaq (%rax,%rax,2), %rdx movslq %edx, %r8 movw %r8w, (%rdi,%rax,2) - jmp + incq %rcx + movslq %ecx, %rax + cmpq %rsi, %rax + jl leaq -0x1(%rsi), %rax movslq %eax, %rax movswq (%rdi,%rax,2), %rax @@ -77,3 +74,5 @@ Disassembly of section .text: popq %rbp retq jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sys_addr_in_static_init.aarch64.asm b/tests/snapshots/asm/sys_addr_in_static_init.aarch64.asm index e84e66bcc..658ec32c1 100644 --- a/tests/snapshots/asm/sys_addr_in_static_init.aarch64.asm +++ b/tests/snapshots/asm/sys_addr_in_static_init.aarch64.asm @@ -10,97 +10,71 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xb0 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0xc0]! str x22, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0xb0] + add x29, sp, #0xb0 adrp x20, add x20, x20, ldr x0, [x20, #0x38] adrp x1, add x1, x1, mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x20] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x1, #0x0 // =0 ldr x0, [x20, #0x8] adrp x2, add x2, x2, - str x1, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x2, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x0, x2 + mov x2, x1 blr x9 - add sp, sp, #0x30 sxtw x21, w0 cmp x21, #0x0 b.ge mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x20] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret ldr x0, [x20, #0x68] sub x1, x29, #0x48 mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! - str x21, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x0, x21 blr x9 - add sp, sp, #0x30 sxtw x22, w0 ldr x0, [x20, #0x20] - str x21, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] + mov x0, x21 blr x9 - add sp, sp, #0x10 cmp x22, #0x4 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x20] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret mov x0, #0x2a // =42 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] + ldp x29, x30, [sp, #0xb0] ldr x19, [sp, #0x20] - add sp, sp, #0xb0 - ldp x29, x30, [sp], #0x10 + ldr x22, [sp, #0x10] + ldp x20, x21, [sp], #0xc0 ret <__c5_sys_open>: @@ -110,49 +84,43 @@ Disassembly of section .text: str x2, [sp, #-0x10]! str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] ldur x2, [x29, #0x30] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x30 ret <__c5_sys_close>: str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x10 ret <__c5_sys_access>: str x1, [sp, #-0x10]! str x0, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldur x0, [x29, #0x10] ldur x1, [x29, #0x20] bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 add sp, sp, #0x20 ret diff --git a/tests/snapshots/asm/sys_addr_zero_arg.aarch64.asm b/tests/snapshots/asm/sys_addr_zero_arg.aarch64.asm index 66ff60e60..53e39e819 100644 --- a/tests/snapshots/asm/sys_addr_zero_arg.aarch64.asm +++ b/tests/snapshots/asm/sys_addr_zero_arg.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, ldr x0, [x0] @@ -23,9 +22,8 @@ Disassembly of section .text: cmp x0, #0x0 b.gt mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -33,31 +31,26 @@ Disassembly of section .text: mov x9, x0 blr x9 mov x0, #0x2a // =42 - ldr x19, [sp] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret <__c5_sys_geteuid>: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret <__c5_sys_getpid>: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 bl sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/sys_addr_zero_arg.x64.asm b/tests/snapshots/asm/sys_addr_zero_arg.x64.asm index 25125c7f9..cc344fb31 100644 --- a/tests/snapshots/asm/sys_addr_zero_arg.x64.asm +++ b/tests/snapshots/asm/sys_addr_zero_arg.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movq (%rax), %rax callq *%rax @@ -21,14 +20,12 @@ Disassembly of section .text: testq %rax, %rax jg movl $0x1, %eax - addq $0x10, %rsp popq %rbp retq leaq , %rax movq (%rax), %rax callq *%rax movl $0x2a, %eax - addq $0x10, %rsp popq %rbp retq @@ -49,4 +46,4 @@ Disassembly of section .text: movslq %eax, %rax popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/sysconf_pagesize.aarch64.asm b/tests/snapshots/asm/sysconf_pagesize.aarch64.asm index 9e485fec7..a8ee1307d 100644 --- a/tests/snapshots/asm/sysconf_pagesize.aarch64.asm +++ b/tests/snapshots/asm/sysconf_pagesize.aarch64.asm @@ -10,84 +10,68 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x1e // =30 bl cmp x0, #0x0 b.gt mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret sub x1, x0, #0x1 and x1, x0, x1 cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x17, #0x1000 // =4096 cmp x0, x17 - cset x20, lt - cbnz x20, + cset x2, lt + cbnz x2, mov x17, #0x100000 // =1048576 cmp x0, x17 - cset x20, gt - cbz x20, + cset x2, gt + cbz x2, mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x3c // =60 bl cmp x0, #0x10 b.ge mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x4 // =4 bl cmp x0, #0x0 b.gt mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x54 // =84 bl cmp x0, #0x0 b.gt mov x0, #0x6 // =6 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x2 // =2 bl cmp x0, #0x0 b.gt mov x0, #0x7 // =7 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -96,15 +80,11 @@ Disassembly of section .text: cmp x0, #0x0 b.gt mov x0, #0x8 // =8 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b diff --git a/tests/snapshots/asm/sysconf_pagesize.x64.asm b/tests/snapshots/asm/sysconf_pagesize.x64.asm index 9f64c138a..feb213a3f 100644 --- a/tests/snapshots/asm/sysconf_pagesize.x64.asm +++ b/tests/snapshots/asm/sysconf_pagesize.x64.asm @@ -13,16 +13,12 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) movl $0x1e, %edi xorl %eax, %eax callq testq %rax, %rax jg movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq leaq -0x1(%rax), %rcx @@ -30,23 +26,19 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq cmpq $0x1000, %rax # imm = 0x1000 - setl %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setl %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne cmpq $0x100000, %rax # imm = 0x100000 - setg %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setg %dl + movzbq %dl, %rdx + testq %rdx, %rdx je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq movl $0x3c, %edi @@ -55,8 +47,6 @@ Disassembly of section .text: cmpq $0x10, %rax jge movl $0x4, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq movl $0x4, %edi @@ -65,8 +55,6 @@ Disassembly of section .text: testq %rax, %rax jg movl $0x5, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq movl $0x54, %edi @@ -75,8 +63,6 @@ Disassembly of section .text: testq %rax, %rax jg movl $0x6, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq movl $0x2, %edi @@ -85,8 +71,6 @@ Disassembly of section .text: testq %rax, %rax jg movl $0x7, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq leaq , %rdi @@ -96,15 +80,10 @@ Disassembly of section .text: testq %rax, %rax jg movl $0x8, %eax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp popq %rbp retq jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/syslimits_path_max.aarch64.asm b/tests/snapshots/asm/syslimits_path_max.aarch64.asm index 94b859329..439f86b72 100644 --- a/tests/snapshots/asm/syslimits_path_max.aarch64.asm +++ b/tests/snapshots/asm/syslimits_path_max.aarch64.asm @@ -10,21 +10,14 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x1, lsl #12 // =0x1000 - sub sp, sp, #0x20 mov x2, #0x0 // =0 mov x2, #0x1 // =1 cbz x2, mov x2, #0x1 // =1 cbz x2, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x1, lsl #12 // =0x1000 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b diff --git a/tests/snapshots/asm/syslimits_path_max.x64.asm b/tests/snapshots/asm/syslimits_path_max.x64.asm index 03eb78286..499f29bef 100644 --- a/tests/snapshots/asm/syslimits_path_max.x64.asm +++ b/tests/snapshots/asm/syslimits_path_max.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x1020, %rsp # imm = 0x1020 xorq %rdx, %rdx movl $0x1, %edx testq %rdx, %rdx @@ -22,11 +19,9 @@ Disassembly of section .text: testq %rdx, %rdx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x1020, %rsp # imm = 0x1020 - popq %rbp retq + movl $0x1, %ecx + jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/sysv_variadic_host_abi.aarch64.asm b/tests/snapshots/asm/sysv_variadic_host_abi.aarch64.asm index 2ba9142fd..04b31007c 100644 --- a/tests/snapshots/asm/sysv_variadic_host_abi.aarch64.asm +++ b/tests/snapshots/asm/sysv_variadic_host_abi.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x18 mov x16, x0 @@ -55,32 +54,17 @@ Disassembly of section .text: add x0, x0, x1 sxtw x2, w0 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0xa - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sxtw x0, w1 asr x3, x0, #63 lsr x3, x3, #63 - add x0, x0, x3 + add x4, x0, x3 mov x17, #0x1 // =1 - and x0, x0, x17 - sub x0, x0, x3 - cmp x0, #0x0 + and x4, x4, x17 + sub x3, x4, x3 + cmp x3, #0x0 b.ne - b - sub x0, x29, #0x20 - mov x0, x2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - add sp, sp, #0xc0 - ret - sub x0, x29, #0x20 - mov x17, x0 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -97,12 +81,12 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr x0, [x0] - add x2, x2, x0 + mov x3, x16 + ldr x3, [x3] + add x2, x2, x3 b - sub x0, x29, #0x20 - mov x17, x0 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x1c] cmp x16, #0x0 @@ -119,11 +103,21 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr d0, [x0] - fcvtzs x0, d0 - add x2, x2, x0 + mov x3, x16 + ldr d0, [x3] + fcvtzs x3, d0 + add x2, x2, x3 b + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0xa + b.lt + sub x0, x29, #0x20 + mov x0, x2 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 + add sp, sp, #0xc0 + ret : sub sp, sp, #0xc0 @@ -143,10 +137,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -168,16 +161,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 scvtf d0, x1 - sxtw x0, w1 - ldursw x2, [x29, #0x10] - cmp x0, x2 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x20 - mov x17, x0 + sub x2, x29, #0x20 + mov x17, x2 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x1c] cmp x16, #0x0 @@ -194,21 +180,23 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - ldr d1, [x0] + mov x2, x16 + ldr d1, [x2] fadd d0, d0, d1 - b + add x1, x0, #0x1 + sxtw x0, w1 + ldursw x2, [x29, #0x10] + cmp x0, x2 + b.lt sub x0, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x70 mov x0, #0x1 // =1 mov x1, #0x2 // =2 mov x3, #0x4000000000000000 // =4611686018427387904 @@ -234,7 +222,6 @@ Disassembly of section .text: cmp x0, #0x3a b.eq mov x0, #0x1 // =1 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0x9 // =9 @@ -266,10 +253,8 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/sysv_variadic_host_abi.x64.asm b/tests/snapshots/asm/sysv_variadic_host_abi.x64.asm index 2ceccdc5a..3a6808d1f 100644 --- a/tests/snapshots/asm/sysv_variadic_host_abi.x64.asm +++ b/tests/snapshots/asm/sysv_variadic_host_abi.x64.asm @@ -43,30 +43,19 @@ Disassembly of section .text: addq %rcx, %rax movslq %eax, %rdx xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0xa, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - movslq %ecx, %rax movq %rax, %rsi sarq $0x3f, %rsi shrq $0x3f, %rsi - addq %rsi, %rax - andq $0x1, %rax - subq %rsi, %rax - testq %rax, %rax + leaq (%rax,%rsi), %rdi + andq $0x1, %rdi + movq %rsi, %r10 + movq %rdi, %rsi + subq %r10, %rsi + testq %rsi, %rsi jne - jmp - leaq -0x18(%rbp), %rax - movq %rdx, %rax - addq $0xe0, %rsp - popq %rbp - retq - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -75,12 +64,12 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movq (%rax), %rax - addq %rax, %rdx + movq %r10, %rsi + movq (%rsi), %rsi + addq %rsi, %rdx jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl 0x4(%r11), %r10d cmpq $0xb0, %r10 jae @@ -89,11 +78,20 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movsd (%rax,%riz), %xmm0 - cvttsd2si %xmm0, %rax - addq %rax, %rdx + movq %r10, %rsi + movsd (%rsi,%riz), %xmm0 + cvttsd2si %xmm0, %rsi + addq %rsi, %rdx jmp + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0xa, %rax + jl + leaq -0x18(%rbp), %rax + movq %rdx, %rax + addq $0xe0, %rsp + popq %rbp + retq : pushq %rbp @@ -125,16 +123,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx cvtsi2sd %rcx, %xmm0 - movslq %ecx, %rax - movslq -0xe0(%rbp), %rdx - cmpq %rdx, %rax - jge jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 movl 0x4(%r11), %r10d cmpq $0xb0, %r10 jae @@ -143,10 +134,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - movsd (%rax,%riz), %xmm1 + movq %r10, %rdx + movsd (%rdx,%riz), %xmm1 addsd %xmm1, %xmm0 - jmp + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + movslq -0xe0(%rbp), %rdx + cmpq %rdx, %rax + jl leaq -0x18(%rbp), %rax addq $0xe0, %rsp popq %rbp @@ -155,7 +150,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp + subq $0x20, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -192,7 +187,7 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq movl $0x9, %edi @@ -233,7 +228,7 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq xorq %rax, %rax @@ -241,7 +236,6 @@ Disassembly of section .text: movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 - addq $0x90, %rsp + addq $0x20, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/tail_call_args_from_spill.aarch64.asm b/tests/snapshots/asm/tail_call_args_from_spill.aarch64.asm index 4b0f0f882..4f818e3c2 100644 --- a/tests/snapshots/asm/tail_call_args_from_spill.aarch64.asm +++ b/tests/snapshots/asm/tail_call_args_from_spill.aarch64.asm @@ -21,14 +21,11 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x40]! + stp x22, x23, [sp, #0x10] str x24, [sp, #0x20] + stp x29, x30, [sp, #0x30] + add x29, sp, #0x30 add x1, x0, #0x1 add x2, x0, #0x2 add x4, x0, #0x3 @@ -63,13 +60,10 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x24, [sp, #0x20] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret lsl x0, x6, #1 add x0, x2, x0 @@ -79,21 +73,17 @@ Disassembly of section .text: lsl x1, x20, #2 add x0, x0, x1 sxtw x0, w0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x30] ldr x24, [sp, #0x20] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x40 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0xa // =10 bl mov x20, x0 @@ -106,11 +96,10 @@ Disassembly of section .text: cmp x0, #0xbf b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/tail_call_args_from_spill.x64.asm b/tests/snapshots/asm/tail_call_args_from_spill.x64.asm index 7565dd947..b77d73860 100644 --- a/tests/snapshots/asm/tail_call_args_from_spill.x64.asm +++ b/tests/snapshots/asm/tail_call_args_from_spill.x64.asm @@ -24,7 +24,7 @@ Disassembly of section .text: : pushq %rbp movq %rsp, %rbp - subq $0x130, %rsp # imm = 0x130 + subq $0x80, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -72,7 +72,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 + addq $0x80, %rsp popq %rbp retq movq %r9, %rax @@ -89,14 +89,14 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0x130, %rsp # imm = 0x130 + addq $0x80, %rsp popq %rbp retq
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0xa, %edi callq @@ -110,12 +110,12 @@ Disassembly of section .text: cmpq $0xbf, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq %rcx, %rax - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/tail_call_no_address_escape.aarch64.asm b/tests/snapshots/asm/tail_call_no_address_escape.aarch64.asm index 45ef6e781..aafd5f1cb 100644 --- a/tests/snapshots/asm/tail_call_no_address_escape.aarch64.asm +++ b/tests/snapshots/asm/tail_call_no_address_escape.aarch64.asm @@ -10,19 +10,14 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 ldr x0, [x0] cmp x0, #0x11 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b : str x0, [sp, #-0x10]! diff --git a/tests/snapshots/asm/tail_call_no_address_escape.x64.asm b/tests/snapshots/asm/tail_call_no_address_escape.x64.asm index f6e467bfb..337b42844 100644 --- a/tests/snapshots/asm/tail_call_no_address_escape.x64.asm +++ b/tests/snapshots/asm/tail_call_no_address_escape.x64.asm @@ -11,19 +11,14 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movq (%rdi), %rax cmpq $0x11, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq + movl $0x1, %ecx + jmp : popq %r10 @@ -48,4 +43,3 @@ Disassembly of section .text: popq %rbp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/tentative_array_definition.aarch64.asm b/tests/snapshots/asm/tentative_array_definition.aarch64.asm index 25e1918fa..eeaaf239a 100644 --- a/tests/snapshots/asm/tentative_array_definition.aarch64.asm +++ b/tests/snapshots/asm/tentative_array_definition.aarch64.asm @@ -15,24 +15,20 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] - mov x21, #0x0 // =0 - adrp x20, - add x20, x20, - ldrb w0, [x20] - cmp x0, #0x0 + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x2, #0x0 // =0 + adrp x0, + add x0, x0, + ldrb w1, [x0] + cmp x1, #0x0 b.eq - mov x17, #0x1 // =1 - orr x21, x21, x17 - cmp x20, x20 + mov x2, #0x1 // =1 + cmp x0, x0 b.eq mov x17, #0x2 // =2 - orr x21, x21, x17 + orr x2, x2, x17 adrp x0, add x0, x0, ldrb w0, [x0] @@ -42,62 +38,51 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x17, #0x4 // =4 - orr x21, x21, x17 - mov x20, #0x0 // =0 - adrp x0, - add x0, x0, - sxtw x1, w20 - add x0, x0, x1 - ldrsb x0, [x0] - cbz x0, - b - sxtw x0, w20 - add x20, x0, #0x1 + orr x2, x2, x17 + mov x1, #0x0 // =0 b adrp x0, add x0, x0, - sxtw x1, w20 - add x0, x0, x1 + add x0, x0, x3 ldrb w0, [x0] - adrp x2, - add x2, x2, - add x1, x2, x1 - ldrsb x1, [x1] - eor x0, x0, x1 + adrp x4, + add x4, x4, + add x4, x4, x3 + ldrsb x4, [x4] + eor x0, x0, x4 mov w0, w0 cmp x0, #0x0 b.eq - b - sxtw x0, w21 - cbz x0, - b mov x17, #0x8 // =8 - orr x21, x21, x17 + orr x2, x2, x17 b + b + add x1, x3, #0x1 + adrp x0, + add x0, x0, + sxtw x3, w1 + add x0, x0, x3 + ldrsb x0, [x0] + cbnz x0, + sxtw x0, w2 + cbz x0, adrp x0, add x0, x0, - sxtw x1, w21 + sxtw x1, w2 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret b b b - b diff --git a/tests/snapshots/asm/tentative_array_definition.x64.asm b/tests/snapshots/asm/tentative_array_definition.x64.asm index a88a9e0aa..8e8567fa4 100644 --- a/tests/snapshots/asm/tentative_array_definition.x64.asm +++ b/tests/snapshots/asm/tentative_array_definition.x64.asm @@ -17,59 +17,49 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - xorq %r12, %r12 - leaq , %rbx - movsbq (%rbx), %rax - testq %rax, %rax + xorq %rdx, %rdx + leaq , %rax + movsbq (%rax), %rcx + testq %rcx, %rcx je - orq $0x1, %r12 - cmpq %rbx, %rbx + movl $0x1, %edx + cmpq %rax, %rax je - orq $0x2, %r12 + orq $0x2, %rdx leaq , %rax movsbq (%rax), %rax cmpq $0x68, %rax je - orq $0x4, %r12 - xorq %rbx, %rbx + orq $0x4, %rdx + xorq %rcx, %rcx + jmp leaq , %rax - movslq %ebx, %rcx - addq %rcx, %rax + addq %rsi, %rax movsbq (%rax), %rax - testq %rax, %rax + leaq , %rdi + addq %rsi, %rdi + movsbq (%rdi), %rdi + cmpq %rdi, %rax je + orq $0x8, %rdx jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp + leaq 0x1(%rsi), %rcx leaq , %rax - movslq %ebx, %rcx - addq %rcx, %rax + movslq %ecx, %rsi + addq %rsi, %rax movsbq (%rax), %rax - leaq , %rdx - addq %rdx, %rcx - movsbq (%rcx), %rcx - cmpq %rcx, %rax - je - jmp - movslq %r12d, %rax + testq %rax, %rax + jne + movslq %edx, %rax testq %rax, %rax je - jmp - orq $0x8, %r12 - jmp leaq , %rdi - movslq %r12d, %rsi + movslq %edx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp popq %rbp retq leaq , %rdi @@ -77,12 +67,9 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x30, %rsp popq %rbp retq jmp jmp jmp - jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/tentative_array_use_before_init.aarch64.asm b/tests/snapshots/asm/tentative_array_use_before_init.aarch64.asm index 081369a91..d2f2360cb 100644 --- a/tests/snapshots/asm/tentative_array_use_before_init.aarch64.asm +++ b/tests/snapshots/asm/tentative_array_use_before_init.aarch64.asm @@ -12,84 +12,73 @@ Disassembly of section .text: brk #: mov x1, #0x0 // =0 mov x0, x1 + b + sxtw x0, w0 + add x0, x0, #0x1 + add x1, x3, #0x1 adrp x2, add x2, x2, sxtw x3, w1 - lsl x3, x3, #4 - add x2, x2, x3 + lsl x4, x3, #4 + add x2, x2, x4 ldr x2, [x2] cmp x2, #0x0 - b.eq - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sxtw x0, w0 - add x0, x0, #0x1 - b + b.ne sxtw x0, w0 ret : - mov x1, #0x0 // =0 - mov x0, x1 - sxtw x2, w1 - cmp x2, #0x4 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - adrp x2, - add x2, x2, - sxtw x3, w1 - ldrsw x2, [x2, x3, lsl #2] - add x0, x0, x2 - b + adrp x0, + add x0, x0, + add x0, x0, #0x0 + ldrsw x0, [x0] + add x0, x0, #0x0 + adrp x1, + add x1, x1, + ldrsw x1, [x1, #0x4] + add x0, x0, x1 + adrp x1, + add x1, x1, + ldrsw x1, [x1, #0x8] + add x0, x0, x1 + adrp x1, + add x1, x1, + ldrsw x1, [x1, #0xc] + add x0, x0, x1 sxtw x0, w0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] bl cmp x0, #0x3 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, ldrsw x0, [x0, #0x8] cmp x0, #0xa - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, adrp x0, add x0, x0, ldrsw x0, [x0, #0x28] cmp x0, #0x1e - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret bl cmp x0, #0xa b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/tentative_array_use_before_init.x64.asm b/tests/snapshots/asm/tentative_array_use_before_init.x64.asm index 69f427e97..0c6c53077 100644 --- a/tests/snapshots/asm/tentative_array_use_before_init.x64.asm +++ b/tests/snapshots/asm/tentative_array_use_before_init.x64.asm @@ -13,86 +13,72 @@ Disassembly of section .text: : xorq %rcx, %rcx movq %rcx, %rax + jmp + movslq %eax, %rax + incq %rax + leaq 0x1(%rsi), %rcx leaq , %rdx movslq %ecx, %rsi - shlq $0x4, %rsi - addq %rsi, %rdx + movq %rsi, %rdi + shlq $0x4, %rdi + addq %rdi, %rdx movq (%rdx), %rdx testq %rdx, %rdx - je - jmp - movslq %ecx, %rcx - incq %rcx - jmp - movslq %eax, %rax - incq %rax - jmp + jne movslq %eax, %rax retq : - xorq %rcx, %rcx - movq %rcx, %rax - movslq %ecx, %rdx - cmpq $0x4, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq , %rdx - movslq %ecx, %rsi - movslq (%rdx,%rsi,4), %rdx - addq %rdx, %rax - jmp + leaq , %rax + addq $0x0, %rax + movslq (%rax), %rax + addq $0x0, %rax + leaq , %rcx + movslq 0x4(%rcx), %rcx + addq %rcx, %rax + leaq , %rcx + movslq 0x8(%rcx), %rcx + addq %rcx, %rax + leaq , %rcx + movslq 0xc(%rcx), %rcx + addq %rcx, %rax movslq %eax, %rax retq
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp - movq %rbx, (%rsp) callq cmpq $0x3, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq leaq , %rax movslq 0x8(%rax), %rax cmpq $0xa, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq , %rax movslq 0x28(%rax), %rax cmpq $0x1e, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq callq cmpq $0xa, %rax je movl $0x3, %eax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x20, %rsp popq %rbp retq jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/tentative_deferred_array_grows.aarch64.asm b/tests/snapshots/asm/tentative_deferred_array_grows.aarch64.asm index 28fb7ae37..020878815 100644 --- a/tests/snapshots/asm/tentative_deferred_array_grows.aarch64.asm +++ b/tests/snapshots/asm/tentative_deferred_array_grows.aarch64.asm @@ -16,9 +16,6 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr x0, [x0] @@ -29,8 +26,6 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -42,8 +37,6 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -64,8 +57,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -73,11 +64,7 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/tentative_deferred_array_grows.x64.asm b/tests/snapshots/asm/tentative_deferred_array_grows.x64.asm index fbbe760ce..407638846 100644 --- a/tests/snapshots/asm/tentative_deferred_array_grows.x64.asm +++ b/tests/snapshots/asm/tentative_deferred_array_grows.x64.asm @@ -16,17 +16,12 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movq (%rax), %rax movabsq $0x1111111111111111, %r11 # imm = 0x1111111111111111 cmpq %r11, %rax je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax @@ -34,8 +29,6 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movsbq (%rax), %rax @@ -52,19 +45,15 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movq (%rax), %rax testq %rax, %rax jne movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ternary_arith_common_type.aarch64.asm b/tests/snapshots/asm/ternary_arith_common_type.aarch64.asm index 770b56d7e..defddf378 100644 --- a/tests/snapshots/asm/ternary_arith_common_type.aarch64.asm +++ b/tests/snapshots/asm/ternary_arith_common_type.aarch64.asm @@ -10,58 +10,31 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - mov x0, #0x0 // =0 - cmp x0, #0x0 - b.ne - mov x2, #0x1 // =1 - b - mov x2, #0xffff // =65535 - movk x2, #0xffff, lsl #16 - cmp x2, #0x1 + mov x1, #0x1 // =1 + cmp x1, #0x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x0 - b.eq - mov x2, #0x1 // =1 - b - mov x2, #0xffff // =65535 - movk x2, #0xffff, lsl #16 + mov x1, #0xffff // =65535 + movk x1, #0xffff, lsl #16 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 - cmp x2, x17 + cmp x1, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x0 - b.ne - mov x2, #0xffff // =65535 - movk x2, #0xffff, lsl #16 - b - mov x2, #0x1 // =1 + mov x1, #0xffff // =65535 + movk x1, #0xffff, lsl #16 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 - cmp x2, x17 + cmp x1, x17 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - cmp x0, #0x0 - b.ne mov x1, #0xffff // =65535 movk x1, #0xffff, lsl #16 movk x1, #0xffff, lsl #32 movk x1, #0xffff, lsl #48 - b - mov x1, #0x0 // =0 mov x17, #0xffff // =65535 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 @@ -69,10 +42,15 @@ Disassembly of section .text: cmp x1, x17 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret + mov x1, #0xffff // =65535 + movk x1, #0xffff, lsl #16 + b + mov x1, #0x1 // =1 + b + mov x1, #0x1 // =1 + b + mov x1, #0x0 // =0 + b diff --git a/tests/snapshots/asm/ternary_arith_common_type.x64.asm b/tests/snapshots/asm/ternary_arith_common_type.x64.asm index 8c92a0e0f..46c66d603 100644 --- a/tests/snapshots/asm/ternary_arith_common_type.x64.asm +++ b/tests/snapshots/asm/ternary_arith_common_type.x64.asm @@ -11,60 +11,39 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x50, %rsp - xorq %rax, %rax - testq %rax, %rax - jne - movl $0x1, %edx - jmp - movl $0xffffffff, %edx # imm = 0xFFFFFFFF - cmpq $0x1, %rdx + movl $0x1, %ecx + cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x50, %rsp - popq %rbp retq - testq %rax, %rax - je - movl $0x1, %edx - jmp - movl $0xffffffff, %edx # imm = 0xFFFFFFFF + movl $0xffffffff, %ecx # imm = 0xFFFFFFFF movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rdx, %rcx - cmpq %r11, %rdx + movq %rcx, %rax + cmpq %r11, %rcx je movl $0x2, %eax - addq $0x50, %rsp - popq %rbp retq - testq %rax, %rax - jne - movl $0xffffffff, %edx # imm = 0xFFFFFFFF - jmp - movl $0x1, %edx + movl $0xffffffff, %ecx # imm = 0xFFFFFFFF movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rdx, %rcx - cmpq %r11, %rdx + movq %rcx, %rax + cmpq %r11, %rcx je movl $0x3, %eax - addq $0x50, %rsp - popq %rbp retq - testq %rax, %rax - jne movabsq $-0x1, %rcx - jmp - xorq %rcx, %rcx cmpq $-0x1, %rcx je movl $0x4, %eax - addq $0x50, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x50, %rsp - popq %rbp retq + movl $0xffffffff, %ecx # imm = 0xFFFFFFFF + jmp + movl $0x1, %ecx + jmp + movl $0x1, %ecx + jmp + xorq %rcx, %rcx + jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm b/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm index cdef9ff71..82e9a25e7 100644 --- a/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm +++ b/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm @@ -17,11 +17,6 @@ Disassembly of section .text: scvtf d0, x2 sub x17, x29, #0x20 str d0, [x17] - b - mov x2, #0x4000000000000000 // =4611686018427387904 - fmov d16, x2 - sub x17, x29, #0x20 - str d16, [x17] sub x16, x29, #0x20 ldr d0, [x16] mov x2, #0x3ff0000000000000 // =4607182418800017408 @@ -33,12 +28,6 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x2, #0x1 // =1 - scvtf d0, x2 - sub x17, x29, #0x28 - str d0, [x17] - b mov x2, #0x4000000000000000 // =4611686018427387904 fmov d16, x2 sub x17, x29, #0x28 @@ -58,11 +47,6 @@ Disassembly of section .text: fmov d16, x2 sub x17, x29, #0x30 str d16, [x17] - b - mov x2, #0x2 // =2 - scvtf d0, x2 - sub x17, x29, #0x30 - str d0, [x17] sub x16, x29, #0x30 ldr d0, [x16] mov x2, #0x3ff0000000000000 // =4607182418800017408 @@ -74,12 +58,6 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 - sub x17, x29, #0x38 - str d16, [x17] - b mov x2, #0x2 // =2 scvtf d0, x2 sub x17, x29, #0x38 @@ -95,15 +73,11 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 - sub x17, x29, #0x40 - str d16, [x17] - b - mov x2, #0x4000000000000000 // =4611686018427387904 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 + fcvt d0, s16 sub x17, x29, #0x40 - str d16, [x17] + str d0, [x17] sub x16, x29, #0x40 ldr d0, [x16] mov x2, #0x3ff0000000000000 // =4607182418800017408 @@ -115,12 +89,6 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 - sub x17, x29, #0x48 - str d16, [x17] - b mov x2, #0x4000000000000000 // =4611686018427387904 fmov d16, x2 sub x17, x29, #0x48 @@ -136,41 +104,31 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 sub x17, x29, #0x50 - str d16, [x17] - b - mov x2, #0x2 // =2 - scvtf d0, x2 - sub x17, x29, #0x50 - str d0, [x17] + str s16, [x17] sub x16, x29, #0x50 - ldr d0, [x16] - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d17, x2 - fcmp d0, d17 + ldr s0, [x16] + mov x2, #0x3f800000 // =1065353216 + fmov s17, w2 + fcmp s0, s17 cset x2, ne cbz x2, mov x0, #0x11 // =17 add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 - sub x17, x29, #0x58 - str d16, [x17] - b mov x2, #0x2 // =2 scvtf d0, x2 + fcvt s0, d0 sub x17, x29, #0x58 - str d0, [x17] + str s0, [x17] sub x16, x29, #0x58 - ldr d0, [x16] - mov x2, #0x4000000000000000 // =4611686018427387904 - fmov d17, x2 - fcmp d0, d17 + ldr s0, [x16] + mov x2, #0x40000000 // =1073741824 + fmov s17, w2 + fcmp s0, s17 cset x2, ne cbz x2, mov x0, #0x12 // =18 @@ -178,17 +136,12 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x2, #0xa // =10 - b - mov x2, #0x14 // =20 cmp x2, #0xa b.eq mov x0, #0x15 // =21 add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - b - mov x1, #0x1 // =1 - b mov x1, #0x2 // =2 cmp x1, #0x2 b.eq @@ -200,3 +153,49 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret + mov x2, #0x4000000000000000 // =4611686018427387904 + fmov d16, x2 + sub x17, x29, #0x20 + str d16, [x17] + b + mov x2, #0x1 // =1 + scvtf d0, x2 + sub x17, x29, #0x28 + str d0, [x17] + b + mov x2, #0x2 // =2 + scvtf d0, x2 + sub x17, x29, #0x30 + str d0, [x17] + b + mov x2, #0x3ff0000000000000 // =4607182418800017408 + fmov d16, x2 + sub x17, x29, #0x38 + str d16, [x17] + b + mov x2, #0x4000000000000000 // =4611686018427387904 + fmov d16, x2 + sub x17, x29, #0x40 + str d16, [x17] + b + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 + fcvt d0, s16 + sub x17, x29, #0x48 + str d0, [x17] + b + mov x2, #0x2 // =2 + scvtf d0, x2 + fcvt s0, d0 + sub x17, x29, #0x50 + str s0, [x17] + b + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 + sub x17, x29, #0x58 + str s16, [x17] + b + mov x2, #0x14 // =20 + b + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/ternary_arith_conversion.x64.asm b/tests/snapshots/asm/ternary_arith_conversion.x64.asm index df10a6466..22f21eb82 100644 --- a/tests/snapshots/asm/ternary_arith_conversion.x64.asm +++ b/tests/snapshots/asm/ternary_arith_conversion.x64.asm @@ -17,10 +17,6 @@ Disassembly of section .text: movl $0x1, %edx cvtsi2sd %rdx, %xmm0 movsd %xmm0, -0x20(%rbp,%riz) - jmp - movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 - movq %rdx, %xmm14 - movsd %xmm14, -0x20(%rbp,%riz) movsd -0x20(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 movq %rdx, %xmm15 @@ -36,11 +32,6 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - jmp - movl $0x1, %edx - cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x28(%rbp,%riz) - jmp movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 movq %rdx, %xmm14 movsd %xmm14, -0x28(%rbp,%riz) @@ -62,10 +53,6 @@ Disassembly of section .text: movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 movq %rdx, %xmm14 movsd %xmm14, -0x30(%rbp,%riz) - jmp - movl $0x2, %edx - cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x30(%rbp,%riz) movsd -0x30(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 movq %rdx, %xmm15 @@ -81,11 +68,6 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - jmp - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 - movq %rdx, %xmm14 - movsd %xmm14, -0x38(%rbp,%riz) - jmp movl $0x2, %edx cvtsi2sd %rdx, %xmm0 movsd %xmm0, -0x38(%rbp,%riz) @@ -104,13 +86,10 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) - jmp - movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 - movq %rdx, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) + cvtss2sd %xmm14, %xmm0 + movsd %xmm0, -0x40(%rbp,%riz) movsd -0x40(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 movq %rdx, %xmm15 @@ -126,11 +105,6 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - jmp - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 - movq %rdx, %xmm14 - movsd %xmm14, -0x48(%rbp,%riz) - jmp movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 movq %rdx, %xmm14 movsd %xmm14, -0x48(%rbp,%riz) @@ -149,17 +123,13 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x50(%rbp,%riz) - jmp - movl $0x2, %edx - cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x50(%rbp,%riz) - movsd -0x50(%rbp,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movss %xmm14, -0x50(%rbp,%riz) + movss -0x50(%rbp,%riz), %xmm0 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %dl movzbq %dl, %rdx setp %r10b @@ -171,18 +141,14 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - jmp - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 - movq %rdx, %xmm14 - movsd %xmm14, -0x58(%rbp,%riz) - jmp movl $0x2, %edx cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x58(%rbp,%riz) - movsd -0x58(%rbp,%riz), %xmm0 - movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x58(%rbp,%riz) + movss -0x58(%rbp,%riz), %xmm0 + movl $0x40000000, %edx # imm = 0x40000000 movq %rdx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %dl movzbq %dl, %rdx setp %r10b @@ -195,17 +161,12 @@ Disassembly of section .text: popq %rbp retq movl $0xa, %edx - jmp - movl $0x14, %edx cmpq $0xa, %rdx je movl $0x15, %eax addq $0x70, %rsp popq %rbp retq - jmp - movl $0x1, %ecx - jmp movl $0x2, %ecx cmpq $0x2, %rcx je @@ -217,4 +178,42 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq + movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 + movq %rdx, %xmm14 + movsd %xmm14, -0x20(%rbp,%riz) + jmp + movl $0x1, %edx + cvtsi2sd %rdx, %xmm0 + movsd %xmm0, -0x28(%rbp,%riz) + jmp + movl $0x2, %edx + cvtsi2sd %rdx, %xmm0 + movsd %xmm0, -0x30(%rbp,%riz) + jmp + movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movq %rdx, %xmm14 + movsd %xmm14, -0x38(%rbp,%riz) + jmp + movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 + movq %rdx, %xmm14 + movsd %xmm14, -0x40(%rbp,%riz) + jmp + movl $0x3f800000, %edx # imm = 0x3F800000 + movq %rdx, %xmm14 + cvtss2sd %xmm14, %xmm0 + movsd %xmm0, -0x48(%rbp,%riz) + jmp + movl $0x2, %edx + cvtsi2sd %rdx, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x50(%rbp,%riz) + jmp + movl $0x3f800000, %edx # imm = 0x3F800000 + movq %rdx, %xmm14 + movss %xmm14, -0x58(%rbp,%riz) + jmp + movl $0x14, %edx + jmp + movl $0x1, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ternary_middle_comma.aarch64.asm b/tests/snapshots/asm/ternary_middle_comma.aarch64.asm index 73a8071a0..91db9017e 100644 --- a/tests/snapshots/asm/ternary_middle_comma.aarch64.asm +++ b/tests/snapshots/asm/ternary_middle_comma.aarch64.asm @@ -12,14 +12,8 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x120 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] - str x24, [sp, #0x20] - str x25, [sp, #0x28] - str x19, [sp, #0x30] + sub sp, sp, #0xf0 + str x19, [sp] sub x0, x29, #0x8 adrp x1, add x1, x1, @@ -33,45 +27,32 @@ Disassembly of section .text: ldrb w10, [x1, #0x3] strb w10, [x0, #0x3] ldr x10, [sp], #0x10 - mov x20, #0x2a // =42 - mov w0, w20 - cmp x0, #0x80 - b.hs sub x0, x29, #0x8 - mov x17, #0xff // =255 - and x1, x20, x17 + mov x1, #0x2a // =42 strb w1, [x0] - mov x21, #0x1 // =1 - b - mov x21, #0x63 // =99 - sxtw x0, w21 + mov x1, #0x1 // =1 + sxtw x0, w1 cmp x0, #0x1 - cset x22, ne - cbnz x22, + cset x2, ne + cbnz x2, sub x0, x29, #0x8 ldrb w0, [x0] mov x17, #0x2a // =42 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x22, ne - cbz x22, + cset x2, ne + cbz x2, adrp x0, add x0, x0, - sxtw x1, w21 + sxtw x1, w1 sub x2, x29, #0x8 ldrb w2, [x2] bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x20 @@ -87,44 +68,32 @@ Disassembly of section .text: ldrb w10, [x1, #0x3] strb w10, [x0, #0x3] ldr x10, [sp], #0x10 - mov w0, w20 - cmp x0, #0x80 - b.hs sub x0, x29, #0x20 - mov x17, #0xff // =255 - and x1, x20, x17 + mov x1, #0x2a // =42 strb w1, [x0] - mov x21, #0x1 // =1 - b - mov x21, #0x63 // =99 - sxtw x0, w21 + mov x1, #0x1 // =1 + sxtw x0, w1 cmp x0, #0x1 - cset x22, ne - cbnz x22, + cset x2, ne + cbnz x2, sub x0, x29, #0x20 ldrb w0, [x0] mov x17, #0x2a // =42 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x22, ne - cbz x22, + cset x2, ne + cbz x2, adrp x0, add x0, x0, - sxtw x1, w21 + sxtw x1, w1 sub x2, x29, #0x20 ldrb w2, [x2] bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x30 @@ -140,101 +109,75 @@ Disassembly of section .text: ldrb w10, [x1, #0x3] strb w10, [x0, #0x3] ldr x10, [sp], #0x10 - mov w0, w20 - cmp x0, #0x80 - b.hs sub x0, x29, #0x30 - mov x17, #0xff // =255 - and x1, x20, x17 + mov x1, #0x2a // =42 strb w1, [x0] - mov x21, #0x1 // =1 - b - mov x21, #0x63 // =99 - sxtw x0, w21 + mov x1, #0x1 // =1 + sxtw x0, w1 cmp x0, #0x1 - cset x22, ne - cbnz x22, + cset x2, ne + cbnz x2, sub x0, x29, #0x30 ldrb w0, [x0] mov x17, #0x2a // =42 eor x0, x0, x17 mov w0, w0 cmp x0, #0x0 - cset x22, ne - cbz x22, + cset x2, ne + cbz x2, adrp x0, add x0, x0, - sxtw x1, w21 + sxtw x1, w1 sub x2, x29, #0x30 ldrb w2, [x2] bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret - mov x21, #0x0 // =0 - cmp x20, #0x0 - b.le - mov x23, #0x1 // =1 - mov x22, #0x2 // =2 - mov x21, #0x3 // =3 - add x0, x23, x22 - add x0, x0, x21 - sxtw x20, w0 - b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x22, x21 - mov x23, x21 - sxtw x0, w20 + mov x2, #0x0 // =0 + mov x4, #0x1 // =1 + mov x3, #0x2 // =2 + mov x2, #0x3 // =3 + mov x1, #0x6 // =6 + sxtw x0, w1 cmp x0, #0x6 cset x0, ne - mov x24, #0x1 // =1 + mov x6, #0x1 // =1 cbnz x0, - sxtw x0, w23 + sxtw x0, w4 cmp x0, #0x1 cset x0, ne cmp x0, #0x0 - cset x24, ne - mov x25, #0x1 // =1 - cbnz x24, - sxtw x0, w22 + cset x6, ne + mov x5, #0x1 // =1 + cbnz x6, + sxtw x0, w3 cmp x0, #0x2 cset x0, ne cmp x0, #0x0 - cset x25, ne - cbnz x25, - sxtw x0, w21 + cset x5, ne + cbnz x5, + sxtw x0, w2 cmp x0, #0x3 - cset x25, ne - cbz x25, + cset x5, ne + cbz x5, adrp x0, add x0, x0, - sxtw x1, w20 - sxtw x2, w23 - sxtw x3, w22 - sxtw x4, w21 + sxtw x1, w1 + sxtw x4, w4 + sxtw x3, w3 + sxtw x2, w2 + mov x16, x4 + mov x4, x2 + mov x2, x16 bl sxtw x0, w0 mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x60 @@ -250,53 +193,31 @@ Disassembly of section .text: ldrb w10, [x1, #0x3] strb w10, [x0, #0x3] ldr x10, [sp], #0x10 - mov x0, #0xc8 // =200 - mov w1, w0 - cmp x1, #0x80 - b.hs - sub x1, x29, #0x60 - mov x17, #0xff // =255 - and x0, x0, x17 - strb w0, [x1] - mov x20, #0x1 // =1 - b - mov x20, #0x63 // =99 - sxtw x0, w20 + mov x1, #0x63 // =99 + sxtw x0, w1 cmp x0, #0x63 - cset x21, ne - cbnz x21, + cset x2, ne + cbnz x2, sub x0, x29, #0x60 ldrb w0, [x0] cmp x0, #0x0 - cset x21, ne - cbz x21, + cset x2, ne + cbz x2, adrp x0, add x0, x0, - sxtw x1, w20 + sxtw x1, w1 sub x2, x29, #0x60 ldrb w2, [x2] bl sxtw x0, w0 mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] - ldr x24, [sp, #0x20] - ldr x25, [sp, #0x28] - ldr x19, [sp, #0x30] - add sp, sp, #0x120 + ldr x19, [sp] + add sp, sp, #0xf0 ldp x29, x30, [sp], #0x10 ret b @@ -306,3 +227,21 @@ Disassembly of section .text: b b b + mov x1, #0x63 // =99 + b + mov x1, #0x63 // =99 + b + mov x1, #0x63 // =99 + b + mov x1, #0xffff // =65535 + movk x1, #0xffff, lsl #16 + movk x1, #0xffff, lsl #32 + movk x1, #0xffff, lsl #48 + mov x3, x2 + mov x4, x2 + b + sub x0, x29, #0x60 + mov x1, #0xc8 // =200 + strb w1, [x0] + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/ternary_middle_comma.x64.asm b/tests/snapshots/asm/ternary_middle_comma.x64.asm index b35e04154..5a6368edb 100644 --- a/tests/snapshots/asm/ternary_middle_comma.x64.asm +++ b/tests/snapshots/asm/ternary_middle_comma.x64.asm @@ -13,12 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x120, %rsp # imm = 0x120 - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movq %r14, 0x18(%rsp) - movq %r15, 0x20(%rsp) + subq $0xe0, %rsp leaq -0x8(%rbp), %rax leaq , %rcx pushq %rdx @@ -31,46 +26,34 @@ Disassembly of section .text: movzbq 0x3(%rcx), %rdx movb %dl, 0x3(%rax) popq %rdx - movl $0x2a, %ebx - movl %ebx, %eax - cmpq $0x80, %rax - jae leaq -0x8(%rbp), %rax - movq %rbx, %rcx - andq $0xff, %rcx + movl $0x2a, %ecx movb %cl, (%rax) - movl $0x1, %r12d - jmp - movl $0x63, %r12d - movslq %r12d, %rax + movl $0x1, %ecx + movslq %ecx, %rax cmpq $0x1, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x8(%rbp), %rax movzbq (%rax), %rax xorq $0x2a, %rax movl %eax, %eax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rdi - movslq %r12d, %rsi + movslq %ecx, %rsi leaq -0x8(%rbp), %rax movzbq (%rax), %rdx movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq leaq -0x20(%rbp), %rax @@ -85,45 +68,34 @@ Disassembly of section .text: movzbq 0x3(%rcx), %rdx movb %dl, 0x3(%rax) popq %rdx - movl %ebx, %eax - cmpq $0x80, %rax - jae leaq -0x20(%rbp), %rax - movq %rbx, %rcx - andq $0xff, %rcx + movl $0x2a, %ecx movb %cl, (%rax) - movl $0x1, %r12d - jmp - movl $0x63, %r12d - movslq %r12d, %rax + movl $0x1, %ecx + movslq %ecx, %rax cmpq $0x1, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x20(%rbp), %rax movzbq (%rax), %rax xorq $0x2a, %rax movl %eax, %eax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rdi - movslq %r12d, %rsi + movslq %ecx, %rsi leaq -0x20(%rbp), %rax movzbq (%rax), %rdx movb $0x0, %al callq movslq %eax, %rax movl $0x2, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq leaq -0x30(%rbp), %rax @@ -138,112 +110,86 @@ Disassembly of section .text: movzbq 0x3(%rcx), %rdx movb %dl, 0x3(%rax) popq %rdx - movl %ebx, %eax - cmpq $0x80, %rax - jae leaq -0x30(%rbp), %rax - movq %rbx, %rcx - andq $0xff, %rcx + movl $0x2a, %ecx movb %cl, (%rax) - movl $0x1, %r12d - jmp - movl $0x63, %r12d - movslq %r12d, %rax + movl $0x1, %ecx + movslq %ecx, %rax cmpq $0x1, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x30(%rbp), %rax movzbq (%rax), %rax xorq $0x2a, %rax movl %eax, %eax testq %rax, %rax - setne %r13b - movzbq %r13b, %r13 - testq %r13, %r13 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rdi - movslq %r12d, %rsi + movslq %ecx, %rsi leaq -0x30(%rbp), %rax movzbq (%rax), %rdx movb $0x0, %al callq movslq %eax, %rax movl $0x3, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq - xorq %r12, %r12 - testq %rbx, %rbx - jle - movl $0x1, %r14d - movl $0x2, %r13d - movl $0x3, %r12d - leaq (%r14,%r13), %rax - addq %r12, %rax - movslq %eax, %rbx - jmp - movabsq $-0x1, %rbx - movq %r12, %r13 - movq %r12, %r14 - movslq %ebx, %rax + xorq %rdx, %rdx + movl $0x1, %edi + movl $0x2, %esi + movl $0x3, %edx + movl $0x6, %ecx + movslq %ecx, %rax cmpq $0x6, %rax setne %al movzbq %al, %rax - movl $0x1, %r15d + movl $0x1, %r9d testq %rax, %rax jne - movslq %r14d, %rax + movslq %edi, %rax cmpq $0x1, %rax setne %al movzbq %al, %rax testq %rax, %rax - setne %r15b - movzbq %r15b, %r15 - movl $0x1, %r10d - movq %r10, 0x38(%rsp) - testq %r15, %r15 + setne %r9b + movzbq %r9b, %r9 + movl $0x1, %r8d + testq %r9, %r9 jne - movslq %r13d, %rax + movslq %esi, %rax cmpq $0x2, %rax setne %al movzbq %al, %rax testq %rax, %rax - setne %r10b - movzbq %r10b, %r10 - movq %r10, 0x38(%rsp) - movq 0x38(%rsp), %r10 - testq %r10, %r10 + setne %r8b + movzbq %r8b, %r8 + testq %r8, %r8 jne - movslq %r12d, %rax + movslq %edx, %rax cmpq $0x3, %rax - setne %r10b - movzbq %r10b, %r10 - movq %r10, 0x38(%rsp) - movq 0x38(%rsp), %r10 - testq %r10, %r10 + setne %r8b + movzbq %r8b, %r8 + testq %r8, %r8 je - leaq , %rdi - movslq %ebx, %rsi - movslq %r14d, %rdx - movslq %r13d, %rcx - movslq %r12d, %r8 + leaq , %rax + movslq %ecx, %rcx + movslq %edi, %rdi + movslq %esi, %rsi + movslq %edx, %r8 + movq %rdi, %rdx + movq %rax, %rdi + xchgq %rsi, %rcx movb $0x0, %al callq movslq %eax, %rax movl $0x4, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq leaq -0x60(%rbp), %rax @@ -258,52 +204,33 @@ Disassembly of section .text: movzbq 0x3(%rcx), %rdx movb %dl, 0x3(%rax) popq %rdx - movl $0xc8, %eax - movl %eax, %ecx - cmpq $0x80, %rcx - jae - leaq -0x60(%rbp), %rcx - andq $0xff, %rax - movb %al, (%rcx) - movl $0x1, %ebx - jmp - movl $0x63, %ebx - movslq %ebx, %rax + movl $0x63, %ecx + movslq %ecx, %rax cmpq $0x63, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx jne leaq -0x60(%rbp), %rax movzbq (%rax), %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %dl + movzbq %dl, %rdx + testq %rdx, %rdx je leaq , %rdi - movslq %ebx, %rsi + movslq %ecx, %rsi leaq -0x60(%rbp), %rax movzbq (%rax), %rdx movb $0x0, %al callq movslq %eax, %rax movl $0x5, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - movq 0x18(%rsp), %r14 - movq 0x20(%rsp), %r15 - addq $0x120, %rsp # imm = 0x120 + addq $0xe0, %rsp popq %rbp retq jmp @@ -313,4 +240,18 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) + movl $0x63, %ecx + jmp + movl $0x63, %ecx + jmp + movl $0x63, %ecx + jmp + movabsq $-0x1, %rcx + movq %rdx, %rsi + movq %rdx, %rdi + jmp + leaq -0x60(%rbp), %rax + movl $0xc8, %ecx + movb %cl, (%rax) + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/thread_local_basic.aarch64.asm b/tests/snapshots/asm/thread_local_basic.aarch64.asm index d672fde1f..8a6cb9eda 100644 --- a/tests/snapshots/asm/thread_local_basic.aarch64.asm +++ b/tests/snapshots/asm/thread_local_basic.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mrs x0, TPIDR_EL0 add x0, x0, #0x10 ldrsw x1, [x0] cmp x1, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -30,9 +28,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x1, #0x7 // =7 str w1, [x0] @@ -44,9 +41,8 @@ Disassembly of section .text: cmp x1, #0x7 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -54,9 +50,8 @@ Disassembly of section .text: cmp x1, #0x2a b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrsw x1, [x0] mrs x2, TPIDR_EL0 @@ -68,12 +63,10 @@ Disassembly of section .text: cmp x0, #0x31 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/thread_local_gnu.aarch64.asm b/tests/snapshots/asm/thread_local_gnu.aarch64.asm index d5c7547e8..f539993bb 100644 --- a/tests/snapshots/asm/thread_local_gnu.aarch64.asm +++ b/tests/snapshots/asm/thread_local_gnu.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mrs x0, TPIDR_EL0 add x0, x0, #0x10 ldrsw x1, [x0] cmp x1, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -30,9 +28,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x1, #0x7 // =7 str w1, [x0] @@ -44,9 +41,8 @@ Disassembly of section .text: cmp x1, #0x7 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -54,9 +50,8 @@ Disassembly of section .text: cmp x1, #0x2a b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrsw x1, [x0] mrs x2, TPIDR_EL0 @@ -68,12 +63,10 @@ Disassembly of section .text: cmp x0, #0x31 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/thread_local_initializer.aarch64.asm b/tests/snapshots/asm/thread_local_initializer.aarch64.asm index 60d7ff222..bf74ce49a 100644 --- a/tests/snapshots/asm/thread_local_initializer.aarch64.asm +++ b/tests/snapshots/asm/thread_local_initializer.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mrs x0, TPIDR_EL0 add x0, x0, #0x10 ldrsw x1, [x0] cmp x1, #0x7 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x18 @@ -34,9 +32,8 @@ Disassembly of section .text: cmp x1, x17 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mrs x1, TPIDR_EL0 add x1, x1, #0x20 @@ -44,9 +41,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrsw x1, [x0] mrs x2, TPIDR_EL0 @@ -58,12 +54,10 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/thread_local_per_thread.aarch64.asm b/tests/snapshots/asm/thread_local_per_thread.aarch64.asm index cbbe5a7b3..f28948be9 100644 --- a/tests/snapshots/asm/thread_local_per_thread.aarch64.asm +++ b/tests/snapshots/asm/thread_local_per_thread.aarch64.asm @@ -10,19 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mrs x0, TPIDR_EL0 add x0, x0, #0x10 ldrsw x1, [x0] cmp x1, #0x0 b.eq mov x0, #0xbad1 // =47825 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x1, #0x63 // =99 str w1, [x0] @@ -30,25 +28,20 @@ Disassembly of section .text: cmp x1, #0x63 b.eq mov x0, #0xbad2 // =47826 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrsw x0, [x0] - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x23, [sp, #0x18] + stp x20, x21, [sp, #-0x90]! + stp x22, x23, [sp, #0x10] str x19, [sp, #0x20] + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 mrs x20, TPIDR_EL0 add x20, x20, #0x10 mov x0, #0x1 // =1 @@ -71,56 +64,35 @@ Disassembly of section .text: sub x0, x29, #0x20 adrp x2, add x2, x2, - str x21, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x21, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x23 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x1, x21 + mov x3, x21 blr x9 - add sp, sp, #0x40 ldur x0, [x29, #-0x20] sub x1, x29, #0x28 - str x1, [sp, #-0x10]! - str x0, [sp, #-0x10]! mov x9, x22 - ldr x0, [sp] - ldr x1, [sp, #0x10] blr x9 - add sp, sp, #0x20 ldur x0, [x29, #-0x28] cmp x0, #0x63 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret ldrsw x0, [x20] cmp x0, #0x1 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x23, [sp, #0x18] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x20] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp], #0x90 ret diff --git a/tests/snapshots/asm/three_dim_array_indexing.aarch64.asm b/tests/snapshots/asm/three_dim_array_indexing.aarch64.asm index 45a62a74f..0124f442e 100644 --- a/tests/snapshots/asm/three_dim_array_indexing.aarch64.asm +++ b/tests/snapshots/asm/three_dim_array_indexing.aarch64.asm @@ -21,10 +21,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, ldrb w1, [x0] @@ -38,9 +37,8 @@ Disassembly of section .text: cmp x1, #0xa b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret add x1, x0, #0x8 ldrb w2, [x1] @@ -54,9 +52,8 @@ Disassembly of section .text: cmp x1, #0x2a b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret add x1, x0, #0x10 ldrb w2, [x1] @@ -70,9 +67,8 @@ Disassembly of section .text: cmp x1, #0x4a b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0] mov x17, #0x1 // =1 @@ -81,9 +77,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0xb] mov x17, #0xc // =12 @@ -92,9 +87,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x5 // =5 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x17] mov x17, #0x18 // =24 @@ -103,9 +97,8 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x6 // =6 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0xc] ldrb w2, [x0] @@ -114,9 +107,8 @@ Disassembly of section .text: cmp x1, #0xc b.eq mov x0, #0x7 // =7 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret ldrb w1, [x0, #0x4] ldrb w0, [x0] @@ -125,16 +117,14 @@ Disassembly of section .text: cmp x0, #0x4 b.eq mov x0, #0x8 // =8 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/two_d_array_param_indexing.aarch64.asm b/tests/snapshots/asm/two_d_array_param_indexing.aarch64.asm index 6f6cf827c..acea2b99c 100644 --- a/tests/snapshots/asm/two_d_array_param_indexing.aarch64.asm +++ b/tests/snapshots/asm/two_d_array_param_indexing.aarch64.asm @@ -51,25 +51,20 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x4c0 mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x100 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x400 + lsl x3, x0, #2 + add x2, x2, x3 + mov x3, #0x0 // =0 + strh w3, [x2] + sub x2, x29, #0x400 + lsl x4, x0, #2 + add x2, x2, x4 + strh w3, [x2, #0x2] add x1, x0, #0x1 - b - sub x0, x29, #0x400 - sxtw x2, w1 - lsl x2, x2, #2 - add x0, x0, x2 - mov x2, #0x0 // =0 - strh w2, [x0] - sub x0, x29, #0x400 - sxtw x3, w1 - lsl x3, x3, #2 - add x0, x0, x3 - strh w2, [x0, #0x2] - b + sxtw x0, w1 + cmp x0, #0x100 + b.lt sub x0, x29, #0x400 mov x1, #0x1234 // =4660 strh w1, [x0, #0x14] @@ -77,10 +72,7 @@ Disassembly of section .text: mov x1, #0x10 // =16 strh w1, [x0, #0x16] sub x0, x29, #0x400 - mov x1, #0x5 // =5 - sxtw x1, w1 - lsl x1, x1, #2 - add x0, x0, x1 + add x0, x0, #0x14 ldrh w1, [x0] ldrh w0, [x0, #0x2] add x0, x1, x0 @@ -93,21 +85,38 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0xa - b.ge b - sxtw x0, w1 + sub x2, x29, #0x480 + mov x17, #0xc // =12 + mul x3, x0, x17 + add x2, x2, x3 + add x2, x2, #0x0 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x0 + str w3, [x2] + sub x2, x29, #0x480 + mov x17, #0xc // =12 + mul x3, x0, x17 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x1 + str w3, [x2, #0x4] + sub x2, x29, #0x480 + mov x17, #0xc // =12 + mul x3, x0, x17 + add x2, x2, x3 + mov x17, #0x64 // =100 + mul x3, x0, x17 + add x3, x3, #0x2 + str w3, [x2, #0x8] add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + sxtw x0, w1 + cmp x0, #0xa + b.lt sub x0, x29, #0x480 - mov x1, #0x7 // =7 - sxtw x1, w1 - mov x17, #0xc // =12 - mul x1, x1, x17 - add x0, x0, x1 + add x0, x0, #0x54 ldrsw x1, [x0] ldrsw x2, [x0, #0x4] add x1, x1, x2 @@ -116,45 +125,51 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x837 b.eq - b - sxtw x0, w2 - cmp x0, #0x3 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x480 - sxtw x3, w1 - mov x17, #0xc // =12 - mul x4, x3, x17 - add x0, x0, x4 - sxtw x4, w2 - mov x17, #0x64 // =100 - mul x3, x3, x17 - add x3, x3, x4 - str w3, [x0, x4, lsl #2] - b - b mov x0, #0x2 // =2 add sp, sp, #0x4c0 ldp x29, x30, [sp], #0x10 ret mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x8 - b.ge b - sxtw x0, w1 + sub x2, x29, #0x4a8 + lsl x3, x0, #2 + add x2, x2, x3 + add x2, x2, #0x0 + add x3, x0, #0x41 + add x3, x3, #0x0 + mov x17, #0xff // =255 + and x3, x3, x17 + strb w3, [x2] + sub x2, x29, #0x4a8 + lsl x3, x0, #2 + add x2, x2, x3 + add x3, x0, #0x41 + add x3, x3, #0x1 + mov x17, #0xff // =255 + and x3, x3, x17 + strb w3, [x2, #0x1] + sub x2, x29, #0x4a8 + lsl x3, x0, #2 + add x2, x2, x3 + add x3, x0, #0x41 + add x3, x3, #0x2 + mov x17, #0xff // =255 + and x3, x3, x17 + strb w3, [x2, #0x2] + sub x2, x29, #0x4a8 + lsl x3, x0, #2 + add x2, x2, x3 + add x3, x0, #0x41 + add x3, x3, #0x3 + mov x17, #0xff // =255 + and x3, x3, x17 + strb w3, [x2, #0x3] add x1, x0, #0x1 - b - mov x2, #0x0 // =0 - b + sxtw x0, w1 + cmp x0, #0x8 + b.lt sub x0, x29, #0x4a8 - mov x1, #0x3 // =3 - sxtw x1, w1 - lsl x1, x1, #2 - add x0, x0, x1 + add x0, x0, #0xc ldrb w1, [x0] ldrb w2, [x0, #0x1] add x1, x1, x2 @@ -165,27 +180,6 @@ Disassembly of section .text: sxtw x0, w0 cmp x0, #0x116 b.eq - b - sxtw x0, w2 - cmp x0, #0x4 - b.ge - b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x4a8 - sxtw x3, w1 - lsl x4, x3, #2 - add x0, x0, x4 - sxtw x4, w2 - add x0, x0, x4 - add x3, x3, #0x41 - add x3, x3, x4 - mov x17, #0xff // =255 - and x3, x3, x17 - strb w3, [x0] - b - b mov x0, #0x3 // =3 add sp, sp, #0x4c0 ldp x29, x30, [sp], #0x10 @@ -194,3 +188,5 @@ Disassembly of section .text: add sp, sp, #0x4c0 ldp x29, x30, [sp], #0x10 ret + b + b diff --git a/tests/snapshots/asm/two_d_array_param_indexing.x64.asm b/tests/snapshots/asm/two_d_array_param_indexing.x64.asm index 9f486b1c7..8b4aaa838 100644 --- a/tests/snapshots/asm/two_d_array_param_indexing.x64.asm +++ b/tests/snapshots/asm/two_d_array_param_indexing.x64.asm @@ -53,25 +53,22 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x4c0, %rsp # imm = 0x4C0 xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x100, %rax # imm = 0x100 - jge jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x400(%rbp), %rax - movslq %ecx, %rdx - shlq $0x2, %rdx - addq %rdx, %rax - xorq %rdx, %rdx - movw %dx, (%rax) - leaq -0x400(%rbp), %rax - movslq %ecx, %rsi + leaq -0x400(%rbp), %rdx + movq %rax, %rsi shlq $0x2, %rsi - addq %rsi, %rax - movw %dx, 0x2(%rax) - jmp + addq %rsi, %rdx + xorq %rsi, %rsi + movw %si, (%rdx) + leaq -0x400(%rbp), %rdx + movq %rax, %rdi + shlq $0x2, %rdi + addq %rdi, %rdx + movw %si, 0x2(%rdx) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x100, %rax # imm = 0x100 + jl leaq -0x400(%rbp), %rax movl $0x1234, %ecx # imm = 0x1234 movw %cx, 0x14(%rax) @@ -79,10 +76,7 @@ Disassembly of section .text: movl $0x10, %ecx movw %cx, 0x16(%rax) leaq -0x400(%rbp), %rax - movl $0x5, %ecx - movslq %ecx, %rcx - shlq $0x2, %rcx - addq %rcx, %rax + addq $0x14, %rax movzwq (%rax), %rcx movzwq 0x2(%rax), %rax addq %rcx, %rax @@ -94,20 +88,32 @@ Disassembly of section .text: popq %rbp retq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0xa, %rax - jge jmp - movslq %ecx, %rax + leaq -0x480(%rbp), %rdx + imulq $0xc, %rax, %rsi + addq %rsi, %rdx + addq $0x0, %rdx + imulq $0x64, %rax, %rsi + addq $0x0, %rsi + movl %esi, (%rdx) + leaq -0x480(%rbp), %rdx + imulq $0xc, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + incq %rsi + movl %esi, 0x4(%rdx) + leaq -0x480(%rbp), %rdx + imulq $0xc, %rax, %rsi + addq %rsi, %rdx + imulq $0x64, %rax, %rsi + addq $0x2, %rsi + movl %esi, 0x8(%rdx) leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + movslq %ecx, %rax + cmpq $0xa, %rax + jl leaq -0x480(%rbp), %rax - movl $0x7, %ecx - movslq %ecx, %rcx - imulq $0xc, %rcx, %rcx - addq %rcx, %rax + addq $0x54, %rax movslq (%rax), %rcx movslq 0x4(%rax), %rdx addq %rdx, %rcx @@ -116,43 +122,51 @@ Disassembly of section .text: movslq %eax, %rax cmpq $0x837, %rax # imm = 0x837 je - jmp - movslq %edx, %rax - cmpq $0x3, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x480(%rbp), %rax - movslq %ecx, %rsi - imulq $0xc, %rsi, %rdi - addq %rdi, %rax - movslq %edx, %rdi - imulq $0x64, %rsi, %rsi - addq %rdi, %rsi - movl %esi, (%rax,%rdi,4) - jmp - jmp movl $0x2, %eax addq $0x4c0, %rsp # imm = 0x4C0 popq %rbp retq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x8, %rax - jge jmp - movslq %ecx, %rax + leaq -0x4a8(%rbp), %rdx + movq %rax, %rsi + shlq $0x2, %rsi + addq %rsi, %rdx + addq $0x0, %rdx + leaq 0x41(%rax), %rsi + addq $0x0, %rsi + movslq %esi, %rdi + movb %dil, (%rdx) + leaq -0x4a8(%rbp), %rdx + movq %rax, %rsi + shlq $0x2, %rsi + addq %rsi, %rdx + leaq 0x41(%rax), %rsi + incq %rsi + movslq %esi, %rdi + movb %dil, 0x1(%rdx) + leaq -0x4a8(%rbp), %rdx + movq %rax, %rsi + shlq $0x2, %rsi + addq %rsi, %rdx + leaq 0x41(%rax), %rsi + addq $0x2, %rsi + movslq %esi, %rdi + movb %dil, 0x2(%rdx) + leaq -0x4a8(%rbp), %rdx + movq %rax, %rsi + shlq $0x2, %rsi + addq %rsi, %rdx + leaq 0x41(%rax), %rsi + addq $0x3, %rsi + movslq %esi, %rdi + movb %dil, 0x3(%rdx) leaq 0x1(%rax), %rcx - jmp - xorq %rdx, %rdx - jmp + movslq %ecx, %rax + cmpq $0x8, %rax + jl leaq -0x4a8(%rbp), %rax - movl $0x3, %ecx - movslq %ecx, %rcx - shlq $0x2, %rcx - addq %rcx, %rax + addq $0xc, %rax movsbq (%rax), %rcx movsbq 0x1(%rax), %rdx addq %rdx, %rcx @@ -163,27 +177,6 @@ Disassembly of section .text: movslq %eax, %rax cmpq $0x116, %rax # imm = 0x116 je - jmp - movslq %edx, %rax - cmpq $0x4, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx - jmp - leaq -0x4a8(%rbp), %rax - movslq %ecx, %rsi - movq %rsi, %rdi - shlq $0x2, %rdi - addq %rdi, %rax - movslq %edx, %rdi - addq %rdi, %rax - addq $0x41, %rsi - addq %rdi, %rsi - movslq %esi, %rdi - movb %dil, (%rax) - jmp - jmp movl $0x3, %eax addq $0x4c0, %rsp # imm = 0x4C0 popq %rbp @@ -192,4 +185,6 @@ Disassembly of section .text: addq $0x4c0, %rsp # imm = 0x4C0 popq %rbp retq + jmp + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm index 2291d318b..c0aa4ba83 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,62 +48,230 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x70]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 mov x20, #0x0 // =0 - sxtw x0, w20 - cmp x0, #0xc - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 b mov x21, #0x0 // =0 b - mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s0, d16 + adrp x2, + add x2, x2, + lsl x3, x0, #4 + add x2, x2, x3 + lsl x4, x1, #2 + add x2, x2, x4 + ldr s0, [x2] + adrp x2, + add x2, x2, + add x2, x2, x3 + add x2, x2, x4 + ldr s1, [x2] + fcmp s0, s1 + cset x2, ne + cbnz x2, + add x21, x1, #0x1 + sxtw x1, w21 + cmp x1, #0x4 + b.lt + add x20, x0, #0x1 + sxtw x0, w20 + cmp x0, #0xc + b.lt + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x0 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 sub x17, x29, #0x18 str s0, [x17] - b - sxtw x0, w21 - cmp x0, #0x4 - b.ge - b - sxtw x0, w21 - add x21, x0, #0x1 - b + sub x16, x29, #0x18 + ldr s0, [x16] adrp x0, add x0, x0, - sxtw x1, w20 - lsl x1, x1, #4 - add x0, x0, x1 - sxtw x2, w21 - lsl x2, x2, #2 - add x0, x0, x2 - ldr s0, [x0] + add x0, x0, #0x10 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] adrp x0, add x0, x0, - add x0, x0, x1 - add x0, x0, x2 + add x0, x0, #0x20 ldr s1, [x0] - fcmp s0, s1 + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x30 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x40 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x50 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x60 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x70 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x80 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0x90 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0xa0 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + adrp x0, + add x0, x0, + add x0, x0, #0xb0 + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 + fadd s0, s0, s1 + sub x17, x29, #0x18 + str s0, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] + mov x0, #0x0 // =0 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, - b - b + mov x20, #0x2 // =2 + mov x0, x20 + bl + adrp x1, + add x1, x1, + sub x16, x29, #0x18 + ldr s0, [x16] + fcvt d0, s0 + bl + sxtw x0, w0 + mov x0, x20 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x70 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x70 + ret mov x0, #0x2 // =2 bl adrp x1, @@ -131,64 +295,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x70 ret b - sxtw x0, w1 - cmp x0, #0xc - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x18 - ldr s0, [x0] - adrp x2, - add x2, x2, - sxtw x3, w1 - lsl x3, x3, #4 - add x2, x2, x3 - ldr s1, [x2] - ldr s2, [x2, #0x4] - fadd s1, s1, s2 - ldr s2, [x2, #0x8] - fadd s1, s1, s2 - fadd s0, s0, s1 - str s0, [x0] - b - sub x16, x29, #0x18 - ldr s0, [x16] - mov x0, #0x0 // =0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 - cset x0, ne - cbz x0, - mov x20, #0x2 // =2 - mov x0, x20 - bl - adrp x1, - add x1, x1, - sub x16, x29, #0x18 - ldr s0, [x16] - fcvt d0, s0 - bl - sxtw x0, w0 - mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm index e92d89514..e9dfed0c9 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm @@ -60,105 +60,164 @@ Disassembly of section .text: movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rbx, %rbx - movslq %ebx, %rax - cmpq $0xc, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp xorq %r12, %r12 jmp - xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x18(%rbp,%riz) - jmp - movslq %r12d, %rax - cmpq $0x4, %rax - jge - jmp - movslq %r12d, %rax - leaq 0x1(%rax), %r12 - jmp - leaq , %rax - movslq %ebx, %rcx - shlq $0x4, %rcx - addq %rcx, %rax - movslq %r12d, %rdx - shlq $0x2, %rdx - addq %rdx, %rax - movss (%rax,%riz), %xmm0 - leaq , %rax - addq %rcx, %rax - addq %rdx, %rax - movss (%rax,%riz), %xmm1 + leaq , %rdx + movq %rax, %rsi + shlq $0x4, %rsi + addq %rsi, %rdx + movq %rcx, %rdi + shlq $0x2, %rdi + addq %rdi, %rdx + movss (%rdx,%riz), %xmm0 + leaq , %rdx + addq %rsi, %rdx + addq %rdi, %rdx + movss (%rdx,%riz), %xmm1 ucomiss %xmm1, %xmm0 - setne %al - movzbq %al, %rax + setne %dl + movzbq %dl, %rdx setp %r10b movzbq %r10b, %r10 - orq %r10, %rax - testq %rax, %rax - je - jmp - jmp - movl $0x2, %edi - callq - movq %rax, %rdi - leaq , %rsi - movslq %ebx, %rdx + orq %r10, %rdx + testq %rdx, %rdx + jne + leaq 0x1(%rcx), %r12 movslq %r12d, %rcx + cmpq $0x4, %rcx + jl + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + cmpq $0xc, %rax + jl + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 leaq , %rax - movq %rdx, %r8 - shlq $0x4, %r8 - addq %r8, %rax - movq %rcx, %r9 - shlq $0x2, %r9 - addq %r9, %rax - movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 + addq $0x0, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 leaq , %rax - addq %r8, %rax - addq %r9, %rax + addq $0x10, %rax movss (%rax,%riz), %xmm1 - cvtss2sd %xmm1, %xmm1 - movb $0x2, %al - callq - movslq %eax, %rax - movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x50, %rsp - popq %rbp - retq - jmp - movslq %ecx, %rax - cmpq $0xc, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x18(%rbp), %rax - movss (%rax,%riz), %xmm0 - leaq , %rdx - movslq %ecx, %rsi - shlq $0x4, %rsi - addq %rsi, %rdx - movss (%rdx,%riz), %xmm1 - movss 0x4(%rdx,%riz), %xmm2 + movss 0x4(%rax,%riz), %xmm2 addss %xmm2, %xmm1 - movss 0x8(%rdx,%riz), %xmm2 + movss 0x8(%rax,%riz), %xmm2 addss %xmm2, %xmm1 addss %xmm1, %xmm0 - movss %xmm0, (%rax,%riz) - jmp + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x20, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x30, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x40, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x50, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x60, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x70, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x80, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0x90, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0xa0, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 + leaq , %rax + addq $0xb0, %rax + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x18(%rbp,%riz) movss -0x18(%rbp,%riz), %xmm0 xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -188,3 +247,36 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq + movl $0x2, %edi + callq + movq %rax, %rdi + leaq , %rsi + movslq %ebx, %rdx + movslq %r12d, %rcx + leaq , %rax + movq %rdx, %r8 + shlq $0x4, %r8 + addq %r8, %rax + movq %rcx, %r9 + shlq $0x2, %r9 + addq %r9, %rax + movss (%rax,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 + leaq , %rax + addq %r8, %rax + addq %r9, %rax + movss (%rax,%riz), %xmm1 + cvtss2sd %xmm1, %xmm1 + movb $0x2, %al + callq + movslq %eax, %rax + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x50, %rsp + popq %rbp + retq + jmp + jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm index 457e43b43..eb07efa71 100644 --- a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm +++ b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm @@ -33,32 +33,25 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x40 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 b - sub x0, x29, #0x508 - sxtw x2, w1 - lsl x3, x2, #2 - add x0, x0, x3 - scvtf d0, x2 + sub x2, x29, #0x508 + lsl x3, x0, #2 + add x2, x2, x3 + scvtf d0, x0 fcvt s0, d0 - mov x2, #0x3fd0000000000000 // =4598175219545276416 - fcvt d0, s0 - fmov d17, x2 - fmul d0, d0, d17 - fcvt s0, d0 - str s0, [x0] - b + mov x3, #0x3e800000 // =1048576000 + fmov s17, w3 + fmul s0, s0, s17 + str s0, [x2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt sub x0, x29, #0x508 ldr s0, [x0, #0x20] - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -66,16 +59,13 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x508 - mov x1, #0xc00000000000 // =211106232532992 - movk x1, #0x4058, lsl #48 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0] + mov x1, #0x42c60000 // =1120272384 + fmov s16, w1 + str s16, [x0] sub x0, x29, #0x508 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm index 89100c389..ece7aeb51 100644 --- a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm +++ b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm @@ -34,33 +34,26 @@ Disassembly of section .text: popq %rbp retq xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x40, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0x508(%rbp), %rax - movslq %ecx, %rdx - movq %rdx, %rsi + leaq -0x508(%rbp), %rdx + movq %rax, %rsi shlq $0x2, %rsi - addq %rsi, %rax - cvtsi2sd %rdx, %xmm0 + addq %rsi, %rdx + cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd0000000000000, %rdx # imm = 0x3FD0000000000000 - cvtss2sd %xmm0, %xmm0 - movq %rdx, %xmm15 - mulsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rax,%riz) - jmp + movl $0x3e800000, %esi # imm = 0x3E800000 + movq %rsi, %xmm15 + mulss %xmm15, %xmm0 + movss %xmm0, (%rdx,%riz) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl leaq -0x508(%rbp), %rax movss 0x20(%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -73,15 +66,13 @@ Disassembly of section .text: popq %rbp retq leaq -0x508(%rbp), %rax - movabsq $0x4058c00000000000, %rcx # imm = 0x4058C00000000000 + movl $0x42c60000, %ecx # imm = 0x42C60000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, (%rax,%riz) + movss %xmm14, (%rax,%riz) leaq -0x508(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -97,3 +88,5 @@ Disassembly of section .text: addq $0x520, %rsp # imm = 0x520 popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/type_warning_arity.aarch64.asm b/tests/snapshots/asm/type_warning_arity.aarch64.asm index e162eaec4..147ad8f0e 100644 --- a/tests/snapshots/asm/type_warning_arity.aarch64.asm +++ b/tests/snapshots/asm/type_warning_arity.aarch64.asm @@ -17,13 +17,8 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - mov x20, #0x1 // =1 - mov x0, x20 + mov x0, #0x1 // =1 bl mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/type_warning_arity.x64.asm b/tests/snapshots/asm/type_warning_arity.x64.asm index 1ed30b419..44b4113d3 100644 --- a/tests/snapshots/asm/type_warning_arity.x64.asm +++ b/tests/snapshots/asm/type_warning_arity.x64.asm @@ -18,13 +18,9 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movl $0x1, %ebx - movq %rbx, %rdi + movl $0x1, %edi callq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x10, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/type_warning_silenced_by_cast.aarch64.asm b/tests/snapshots/asm/type_warning_silenced_by_cast.aarch64.asm index 18032d845..d92c4e745 100644 --- a/tests/snapshots/asm/type_warning_silenced_by_cast.aarch64.asm +++ b/tests/snapshots/asm/type_warning_silenced_by_cast.aarch64.asm @@ -10,12 +10,5 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x5 // =5 - cmp x0, #0x0 - cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + mov x0, #0x0 // =0 ret diff --git a/tests/snapshots/asm/type_warning_silenced_by_cast.x64.asm b/tests/snapshots/asm/type_warning_silenced_by_cast.x64.asm index 2e55660e0..fbc7f624d 100644 --- a/tests/snapshots/asm/type_warning_silenced_by_cast.x64.asm +++ b/tests/snapshots/asm/type_warning_silenced_by_cast.x64.asm @@ -11,13 +11,5 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x5, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp + xorq %rax, %rax retq diff --git a/tests/snapshots/asm/typedef_array_comma_list.aarch64.asm b/tests/snapshots/asm/typedef_array_comma_list.aarch64.asm index 70bf7d3ba..22d284081 100644 --- a/tests/snapshots/asm/typedef_array_comma_list.aarch64.asm +++ b/tests/snapshots/asm/typedef_array_comma_list.aarch64.asm @@ -83,16 +83,6 @@ Disassembly of section .text: add sp, sp, #0x210 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x9 // =9 - add sp, sp, #0x210 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xa // =10 - add sp, sp, #0x210 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, mov x1, #0x2a // =42 @@ -153,12 +143,19 @@ Disassembly of section .text: add sp, sp, #0x210 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x10 // =16 + mov x0, #0x0 // =0 add sp, sp, #0x210 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x9 // =9 + add sp, sp, #0x210 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xa // =10 + add sp, sp, #0x210 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10 // =16 add sp, sp, #0x210 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/typedef_array_comma_list.x64.asm b/tests/snapshots/asm/typedef_array_comma_list.x64.asm index 0a2ed913c..565264863 100644 --- a/tests/snapshots/asm/typedef_array_comma_list.x64.asm +++ b/tests/snapshots/asm/typedef_array_comma_list.x64.asm @@ -77,16 +77,6 @@ Disassembly of section .text: addq $0x210, %rsp # imm = 0x210 popq %rbp retq - jmp - movl $0x9, %eax - addq $0x210, %rsp # imm = 0x210 - popq %rbp - retq - jmp - movl $0xa, %eax - addq $0x210, %rsp # imm = 0x210 - popq %rbp - retq leaq , %rax movl $0x2a, %ecx movq %rcx, 0x138(%rax) @@ -135,12 +125,20 @@ Disassembly of section .text: addq $0x210, %rsp # imm = 0x210 popq %rbp retq - jmp - movl $0x10, %eax + xorq %rax, %rax addq $0x210, %rsp # imm = 0x210 popq %rbp retq - xorq %rax, %rax + movl $0x9, %eax + addq $0x210, %rsp # imm = 0x210 + popq %rbp + retq + movl $0xa, %eax + addq $0x210, %rsp # imm = 0x210 + popq %rbp + retq + movl $0x10, %eax addq $0x210, %rsp # imm = 0x210 popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/typedef_array_outer_dim.aarch64.asm b/tests/snapshots/asm/typedef_array_outer_dim.aarch64.asm index 25dd3d627..4ac8dbf8a 100644 --- a/tests/snapshots/asm/typedef_array_outer_dim.aarch64.asm +++ b/tests/snapshots/asm/typedef_array_outer_dim.aarch64.asm @@ -10,46 +10,177 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x2, #0x0 // =0 mov x1, x2 + b + lsl x4, x3, #7 + add x4, x0, x4 + add x4, x4, #0x0 + lsl x5, x3, #4 + add x5, x5, #0x0 + sxtw x5, w5 + str x5, [x4] + lsl x4, x3, #7 + add x4, x0, x4 + add x4, x4, #0x0 + ldr x4, [x4] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x1 + sxtw x5, w5 + str x5, [x4, #0x8] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x8] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x2 + sxtw x5, w5 + str x5, [x4, #0x10] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x10] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x3 + sxtw x5, w5 + str x5, [x4, #0x18] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x18] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x4 + sxtw x5, w5 + str x5, [x4, #0x20] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x20] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x5 + sxtw x5, w5 + str x5, [x4, #0x28] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x28] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x6 + sxtw x5, w5 + str x5, [x4, #0x30] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x30] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x7 + sxtw x5, w5 + str x5, [x4, #0x38] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x38] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x8 + sxtw x5, w5 + str x5, [x4, #0x40] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x40] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0x9 + sxtw x5, w5 + str x5, [x4, #0x48] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x48] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xa + sxtw x5, w5 + str x5, [x4, #0x50] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x50] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xb + sxtw x5, w5 + str x5, [x4, #0x58] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x58] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xc + sxtw x5, w5 + str x5, [x4, #0x60] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x60] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xd + sxtw x5, w5 + str x5, [x4, #0x68] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x68] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xe + sxtw x5, w5 + str x5, [x4, #0x70] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x70] + add x2, x2, x4 + lsl x4, x3, #7 + add x4, x0, x4 + lsl x5, x3, #4 + add x5, x5, #0xf + sxtw x5, w5 + str x5, [x4, #0x78] + lsl x4, x3, #7 + add x4, x0, x4 + ldr x4, [x4, #0x78] + add x2, x2, x4 + add x1, x3, #0x1 sxtw x3, w1 cmp x3, #0x4 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - mov x4, #0x0 // =0 - b + b.lt mov x0, x2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - sxtw x3, w4 - cmp x3, #0x10 - b.ge - b - sxtw x3, w4 - add x4, x3, #0x1 - b - sxtw x3, w1 - lsl x5, x3, #7 - add x5, x0, x5 - sxtw x6, w4 - lsl x3, x3, #4 - add x3, x3, x6 - sxtw x3, w3 - str x3, [x5, x6, lsl #3] - sxtw x3, w1 - lsl x3, x3, #7 - add x3, x0, x3 - sxtw x5, w4 - ldr x3, [x3, x5, lsl #3] - add x2, x2, x3 - b b
: @@ -57,24 +188,14 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x230 str x20, [sp] - b - mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x230 - ldp x29, x30, [sp], #0x10 - ret mov x1, #0x0 // =0 mov x20, x1 - sxtw x0, w1 - cmp x0, #0x40 - b.ge b - sxtw x0, w1 + add x20, x20, x0 add x1, x0, #0x1 - b sxtw x0, w1 - add x20, x20, x0 - b + cmp x0, #0x40 + b.lt sub x0, x29, #0x200 bl cmp x0, x20 @@ -116,3 +237,8 @@ Disassembly of section .text: add sp, sp, #0x230 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ldr x20, [sp] + add sp, sp, #0x230 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/typedef_array_outer_dim.x64.asm b/tests/snapshots/asm/typedef_array_outer_dim.x64.asm index 968c6e8ed..c25db31ec 100644 --- a/tests/snapshots/asm/typedef_array_outer_dim.x64.asm +++ b/tests/snapshots/asm/typedef_array_outer_dim.x64.asm @@ -11,49 +11,225 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) xorq %rcx, %rcx movq %rcx, %rax + jmp + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + addq $0x0, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x0, %r8 + movslq %r8d, %r8 + movq %r8, (%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + addq $0x0, %rsi + movq (%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + incq %r8 + movslq %r8d, %r8 + movq %r8, 0x8(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x8(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x2, %r8 + movslq %r8d, %r8 + movq %r8, 0x10(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x10(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x3, %r8 + movslq %r8d, %r8 + movq %r8, 0x18(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x18(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x4, %r8 + movslq %r8d, %r8 + movq %r8, 0x20(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x20(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x5, %r8 + movslq %r8d, %r8 + movq %r8, 0x28(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x28(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x6, %r8 + movslq %r8d, %r8 + movq %r8, 0x30(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x30(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x7, %r8 + movslq %r8d, %r8 + movq %r8, 0x38(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x38(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x8, %r8 + movslq %r8d, %r8 + movq %r8, 0x40(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x40(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0x9, %r8 + movslq %r8d, %r8 + movq %r8, 0x48(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x48(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xa, %r8 + movslq %r8d, %r8 + movq %r8, 0x50(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x50(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xb, %r8 + movslq %r8d, %r8 + movq %r8, 0x58(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x58(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xc, %r8 + movslq %r8d, %r8 + movq %r8, 0x60(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x60(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xd, %r8 + movslq %r8d, %r8 + movq %r8, 0x68(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x68(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xe, %r8 + movslq %r8d, %r8 + movq %r8, 0x70(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x70(%rsi), %rsi + addq %rsi, %rcx + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq %rdx, %r8 + shlq $0x4, %r8 + addq $0xf, %r8 + movslq %r8d, %r8 + movq %r8, 0x78(%rsi) + movq %rdx, %rsi + shlq $0x7, %rsi + addq %rdi, %rsi + movq 0x78(%rsi), %rsi + addq %rsi, %rcx + leaq 0x1(%rdx), %rax movslq %eax, %rdx cmpq $0x4, %rdx - jge - jmp - movslq %eax, %rax - incq %rax - jmp - xorq %rsi, %rsi - jmp - movq (%rsp), %rbx + jl movq %rcx, %rax - addq $0x30, %rsp - popq %rbp retq - movslq %esi, %rdx - cmpq $0x10, %rdx - jge - jmp - movslq %esi, %rdx - leaq 0x1(%rdx), %rsi - jmp - movslq %eax, %rdx - movq %rdx, %r8 - shlq $0x7, %r8 - addq %rdi, %r8 - movslq %esi, %r9 - shlq $0x4, %rdx - addq %r9, %rdx - movslq %edx, %rdx - movq %rdx, (%r8,%r9,8) - movslq %eax, %rdx - shlq $0x7, %rdx - addq %rdi, %rdx - movslq %esi, %r8 - movq (%rdx,%r8,8), %rdx - addq %rdx, %rcx - jmp jmp
: @@ -61,24 +237,14 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x230, %rsp # imm = 0x230 movq %rbx, (%rsp) - jmp - movl $0x1, %eax - movq (%rsp), %rbx - addq $0x230, %rsp # imm = 0x230 - popq %rbp - retq xorq %rcx, %rcx movq %rcx, %rbx - movslq %ecx, %rax - cmpq $0x40, %rax - jge jmp - movslq %ecx, %rax + addq %rax, %rbx leaq 0x1(%rax), %rcx - jmp movslq %ecx, %rax - addq %rax, %rbx - jmp + cmpq $0x40, %rax + jl leaq -0x200(%rbp), %rdi callq cmpq %rbx, %rax @@ -120,4 +286,9 @@ Disassembly of section .text: addq $0x230, %rsp # imm = 0x230 popq %rbp retq + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x230, %rsp # imm = 0x230 + popq %rbp + retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/typedef_array_param_decay.aarch64.asm b/tests/snapshots/asm/typedef_array_param_decay.aarch64.asm index cded2f88c..cf09381ad 100644 --- a/tests/snapshots/asm/typedef_array_param_decay.aarch64.asm +++ b/tests/snapshots/asm/typedef_array_param_decay.aarch64.asm @@ -10,73 +10,138 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x3, #0x0 // =0 - sxtw x2, w3 - cmp x2, #0x10 - b.ge - b - sxtw x2, w3 - add x3, x2, #0x1 - b - sxtw x2, w3 - lsl x2, x2, #3 - add x4, x0, x2 - add x2, x1, x2 - ldr x2, [x2] - str x2, [x4] - b + add x2, x0, #0x0 + add x3, x1, #0x0 + ldr x3, [x3] + str x3, [x2] + ldr x2, [x1, #0x8] + str x2, [x0, #0x8] + ldr x2, [x1, #0x10] + str x2, [x0, #0x10] + ldr x2, [x1, #0x18] + str x2, [x0, #0x18] + ldr x2, [x1, #0x20] + str x2, [x0, #0x20] + ldr x2, [x1, #0x28] + str x2, [x0, #0x28] + ldr x2, [x1, #0x30] + str x2, [x0, #0x30] + ldr x2, [x1, #0x38] + str x2, [x0, #0x38] + ldr x2, [x1, #0x40] + str x2, [x0, #0x40] + ldr x2, [x1, #0x48] + str x2, [x0, #0x48] + ldr x2, [x1, #0x50] + str x2, [x0, #0x50] + ldr x2, [x1, #0x58] + str x2, [x0, #0x58] + ldr x2, [x1, #0x60] + str x2, [x0, #0x60] + ldr x2, [x1, #0x68] + str x2, [x0, #0x68] + ldr x2, [x1, #0x70] + str x2, [x0, #0x70] + ldr x1, [x1, #0x78] + str x1, [x0, #0x78] mov x0, #0x0 // =0 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x2, #0x0 // =0 - mov x1, x2 - sxtw x3, w1 - cmp x3, #0x10 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sxtw x3, w1 - ldr x3, [x0, x3, lsl #3] - add x2, x2, x3 - b - mov x0, x2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + add x1, x0, #0x0 + ldr x1, [x1] + add x1, x1, #0x0 + ldr x2, [x0, #0x8] + add x1, x1, x2 + ldr x2, [x0, #0x10] + add x1, x1, x2 + ldr x2, [x0, #0x18] + add x1, x1, x2 + ldr x2, [x0, #0x20] + add x1, x1, x2 + ldr x2, [x0, #0x28] + add x1, x1, x2 + ldr x2, [x0, #0x30] + add x1, x1, x2 + ldr x2, [x0, #0x38] + add x1, x1, x2 + ldr x2, [x0, #0x40] + add x1, x1, x2 + ldr x2, [x0, #0x48] + add x1, x1, x2 + ldr x2, [x0, #0x50] + add x1, x1, x2 + ldr x2, [x0, #0x58] + add x1, x1, x2 + ldr x2, [x0, #0x60] + add x1, x1, x2 + ldr x2, [x0, #0x68] + add x1, x1, x2 + ldr x2, [x0, #0x70] + add x1, x1, x2 + ldr x0, [x0, #0x78] + add x0, x1, x0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x120 - mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x10 - b.ge - b - sxtw x0, w1 - add x1, x0, #0x1 - b sub x0, x29, #0x80 - sxtw x2, w1 - add x3, x2, #0x1 - str x3, [x0, x2, lsl #3] - b + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str x1, [x0] + sub x0, x29, #0x80 + mov x1, #0x2 // =2 + str x1, [x0, #0x8] + sub x0, x29, #0x80 + mov x1, #0x3 // =3 + str x1, [x0, #0x10] + sub x0, x29, #0x80 + mov x1, #0x4 // =4 + str x1, [x0, #0x18] + sub x0, x29, #0x80 + mov x1, #0x5 // =5 + str x1, [x0, #0x20] + sub x0, x29, #0x80 + mov x1, #0x6 // =6 + str x1, [x0, #0x28] + sub x0, x29, #0x80 + mov x1, #0x7 // =7 + str x1, [x0, #0x30] + sub x0, x29, #0x80 + mov x1, #0x8 // =8 + str x1, [x0, #0x38] + sub x0, x29, #0x80 + mov x1, #0x9 // =9 + str x1, [x0, #0x40] + sub x0, x29, #0x80 + mov x1, #0xa // =10 + str x1, [x0, #0x48] + sub x0, x29, #0x80 + mov x1, #0xb // =11 + str x1, [x0, #0x50] + sub x0, x29, #0x80 + mov x1, #0xc // =12 + str x1, [x0, #0x58] + sub x0, x29, #0x80 + mov x1, #0xd // =13 + str x1, [x0, #0x60] + sub x0, x29, #0x80 + mov x1, #0xe // =14 + str x1, [x0, #0x68] + sub x0, x29, #0x80 + mov x1, #0xf // =15 + str x1, [x0, #0x70] + sub x0, x29, #0x80 + mov x1, #0x10 // =16 + str x1, [x0, #0x78] sub x0, x29, #0x100 sub x1, x29, #0x80 bl sub x0, x29, #0x100 bl - mov x1, #0x110 // =272 - mov x2, #0x0 // =0 - add x1, x1, x2 - asr x1, x1, #1 - cmp x0, x1 + cmp x0, #0x88 b.eq mov x0, #0x1 // =1 add sp, sp, #0x120 diff --git a/tests/snapshots/asm/typedef_array_param_decay.x64.asm b/tests/snapshots/asm/typedef_array_param_decay.x64.asm index 69f4b5a73..cee28422f 100644 --- a/tests/snapshots/asm/typedef_array_param_decay.x64.asm +++ b/tests/snapshots/asm/typedef_array_param_decay.x64.asm @@ -11,73 +11,138 @@ Disassembly of section .text: ud2 : - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x10, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - movslq %ecx, %rax - shlq $0x3, %rax - leaq (%rdi,%rax), %rdx - addq %rsi, %rax - movq (%rax), %rax - movq %rax, (%rdx) - jmp + leaq (%rdi), %rax + leaq (%rsi), %rcx + movq (%rcx), %rcx + movq %rcx, (%rax) + movq 0x8(%rsi), %rax + movq %rax, 0x8(%rdi) + movq 0x10(%rsi), %rax + movq %rax, 0x10(%rdi) + movq 0x18(%rsi), %rax + movq %rax, 0x18(%rdi) + movq 0x20(%rsi), %rax + movq %rax, 0x20(%rdi) + movq 0x28(%rsi), %rax + movq %rax, 0x28(%rdi) + movq 0x30(%rsi), %rax + movq %rax, 0x30(%rdi) + movq 0x38(%rsi), %rax + movq %rax, 0x38(%rdi) + movq 0x40(%rsi), %rax + movq %rax, 0x40(%rdi) + movq 0x48(%rsi), %rax + movq %rax, 0x48(%rdi) + movq 0x50(%rsi), %rax + movq %rax, 0x50(%rdi) + movq 0x58(%rsi), %rax + movq %rax, 0x58(%rdi) + movq 0x60(%rsi), %rax + movq %rax, 0x60(%rdi) + movq 0x68(%rsi), %rax + movq %rax, 0x68(%rdi) + movq 0x70(%rsi), %rax + movq %rax, 0x70(%rdi) + movq 0x78(%rsi), %rax + movq %rax, 0x78(%rdi) xorq %rax, %rax retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - xorq %rcx, %rcx - movq %rcx, %rax - movslq %eax, %rdx - cmpq $0x10, %rdx - jge - jmp - movslq %eax, %rax - incq %rax - jmp - movslq %eax, %rdx - movq (%rdi,%rdx,8), %rdx - addq %rdx, %rcx - jmp - movq %rcx, %rax - addq $0x10, %rsp - popq %rbp + leaq (%rdi), %rax + movq (%rax), %rax + addq $0x0, %rax + movq 0x8(%rdi), %rcx + addq %rcx, %rax + movq 0x10(%rdi), %rcx + addq %rcx, %rax + movq 0x18(%rdi), %rcx + addq %rcx, %rax + movq 0x20(%rdi), %rcx + addq %rcx, %rax + movq 0x28(%rdi), %rcx + addq %rcx, %rax + movq 0x30(%rdi), %rcx + addq %rcx, %rax + movq 0x38(%rdi), %rcx + addq %rcx, %rax + movq 0x40(%rdi), %rcx + addq %rcx, %rax + movq 0x48(%rdi), %rcx + addq %rcx, %rax + movq 0x50(%rdi), %rcx + addq %rcx, %rax + movq 0x58(%rdi), %rcx + addq %rcx, %rax + movq 0x60(%rdi), %rcx + addq %rcx, %rax + movq 0x68(%rdi), %rcx + addq %rcx, %rax + movq 0x70(%rdi), %rcx + addq %rcx, %rax + movq 0x78(%rdi), %rcx + addq %rcx, %rax retq
: pushq %rbp movq %rsp, %rbp subq $0x120, %rsp # imm = 0x120 - xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x10, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx - jmp - leaq -0x80(%rbp), %rax - movslq %ecx, %rdx - leaq 0x1(%rdx), %rsi - movq %rsi, (%rax,%rdx,8) - jmp + leaq -0x80(%rbp), %rax + addq $0x0, %rax + movl $0x1, %ecx + movq %rcx, (%rax) + leaq -0x80(%rbp), %rax + movl $0x2, %ecx + movq %rcx, 0x8(%rax) + leaq -0x80(%rbp), %rax + movl $0x3, %ecx + movq %rcx, 0x10(%rax) + leaq -0x80(%rbp), %rax + movl $0x4, %ecx + movq %rcx, 0x18(%rax) + leaq -0x80(%rbp), %rax + movl $0x5, %ecx + movq %rcx, 0x20(%rax) + leaq -0x80(%rbp), %rax + movl $0x6, %ecx + movq %rcx, 0x28(%rax) + leaq -0x80(%rbp), %rax + movl $0x7, %ecx + movq %rcx, 0x30(%rax) + leaq -0x80(%rbp), %rax + movl $0x8, %ecx + movq %rcx, 0x38(%rax) + leaq -0x80(%rbp), %rax + movl $0x9, %ecx + movq %rcx, 0x40(%rax) + leaq -0x80(%rbp), %rax + movl $0xa, %ecx + movq %rcx, 0x48(%rax) + leaq -0x80(%rbp), %rax + movl $0xb, %ecx + movq %rcx, 0x50(%rax) + leaq -0x80(%rbp), %rax + movl $0xc, %ecx + movq %rcx, 0x58(%rax) + leaq -0x80(%rbp), %rax + movl $0xd, %ecx + movq %rcx, 0x60(%rax) + leaq -0x80(%rbp), %rax + movl $0xe, %ecx + movq %rcx, 0x68(%rax) + leaq -0x80(%rbp), %rax + movl $0xf, %ecx + movq %rcx, 0x70(%rax) + leaq -0x80(%rbp), %rax + movl $0x10, %ecx + movq %rcx, 0x78(%rax) leaq -0x100(%rbp), %rdi leaq -0x80(%rbp), %rsi callq leaq -0x100(%rbp), %rdi callq - movl $0x110, %ecx # imm = 0x110 - xorq %rdx, %rdx - addq %rdx, %rcx - sarq $0x1, %rcx - cmpq %rcx, %rax + cmpq $0x88, %rax je movl $0x1, %eax addq $0x120, %rsp # imm = 0x120 diff --git a/tests/snapshots/asm/typedef_basic.aarch64.asm b/tests/snapshots/asm/typedef_basic.aarch64.asm index f1686eced..737700d75 100644 --- a/tests/snapshots/asm/typedef_basic.aarch64.asm +++ b/tests/snapshots/asm/typedef_basic.aarch64.asm @@ -18,42 +18,30 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x60 - mov x0, #0x64 // =100 - mov x1, #0x41 // =65 - mov x2, #0x2d2 // =722 - movk x2, #0x4996, lsl #16 - adrp x3, - add x3, x3, - sub x4, x29, #0x30 - mov x5, #0x7 // =7 - str w5, [x4] - sub x4, x29, #0x30 - mov x5, #0x0 // =0 - str x5, [x4, #0x8] - sub x4, x29, #0x38 - mov x5, #0xb // =11 - str w5, [x4] - sub x4, x29, #0x38 - mov x5, #0x16 // =22 - str w5, [x4, #0x4] - sub x4, x29, #0x48 - mov x5, #0x1 // =1 - str w5, [x4] - sub x4, x29, #0x48 - mov x5, #0x2 // =2 - str w5, [x4, #0x4] - sub x4, x29, #0x48 - mov x5, #0x3 // =3 - str w5, [x4, #0x8] - add x0, x0, x1 - sxtw x0, w0 - cmp x0, #0xa5 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - ldrb w0, [x3] + adrp x0, + add x0, x0, + sub x1, x29, #0x30 + mov x2, #0x7 // =7 + str w2, [x1] + sub x1, x29, #0x30 + mov x2, #0x0 // =0 + str x2, [x1, #0x8] + sub x1, x29, #0x38 + mov x2, #0xb // =11 + str w2, [x1] + sub x1, x29, #0x38 + mov x2, #0x16 // =22 + str w2, [x1, #0x4] + sub x1, x29, #0x48 + mov x2, #0x1 // =1 + str w2, [x1] + sub x1, x29, #0x48 + mov x2, #0x2 // =2 + str w2, [x1, #0x4] + sub x1, x29, #0x48 + mov x2, #0x3 // =3 + str w2, [x1, #0x8] + ldrb w0, [x0] mov x17, #0x68 // =104 eor x0, x0, x17 mov w0, w0 @@ -73,9 +61,9 @@ Disassembly of section .text: ret sub x0, x29, #0x38 ldrsw x0, [x0] - sub x3, x29, #0x38 - ldrsw x3, [x3, #0x4] - add x0, x0, x3 + sub x1, x29, #0x38 + ldrsw x1, [x1, #0x4] + add x0, x0, x1 sxtw x0, w0 cmp x0, #0x21 b.eq @@ -85,12 +73,12 @@ Disassembly of section .text: ret sub x0, x29, #0x48 ldrsw x0, [x0] - sub x3, x29, #0x48 - ldrsw x3, [x3, #0x4] - add x0, x0, x3 - sub x3, x29, #0x48 - ldrsw x3, [x3, #0x8] - add x0, x0, x3 + sub x1, x29, #0x48 + ldrsw x1, [x1, #0x4] + add x0, x0, x1 + sub x1, x29, #0x48 + ldrsw x1, [x1, #0x8] + add x0, x0, x1 sxtw x0, w0 cmp x0, #0x6 b.eq @@ -98,31 +86,27 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x17, #0x2d2 // =722 - movk x17, #0x4996, lsl #16 - cmp x2, x17 - b.eq + mov x0, #0x0 // =0 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret mov x0, #0x6 // =6 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - cmp x1, #0x41 - b.eq mov x0, #0x7 // =7 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x8 // =8 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - b mov x0, #0x9 // =9 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret diff --git a/tests/snapshots/asm/typedef_basic.x64.asm b/tests/snapshots/asm/typedef_basic.x64.asm index 9ea2e07ce..04e85771d 100644 --- a/tests/snapshots/asm/typedef_basic.x64.asm +++ b/tests/snapshots/asm/typedef_basic.x64.asm @@ -19,40 +19,29 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x60, %rsp - movl $0x64, %eax - movl $0x41, %ecx - movl $0x499602d2, %edx # imm = 0x499602D2 - leaq , %rsi - leaq -0x30(%rbp), %rdi - movl $0x7, %r8d - movl %r8d, (%rdi) - leaq -0x30(%rbp), %rdi - xorq %r8, %r8 - movq %r8, 0x8(%rdi) - leaq -0x38(%rbp), %rdi - movl $0xb, %r8d - movl %r8d, (%rdi) - leaq -0x38(%rbp), %rdi - movl $0x16, %r8d - movl %r8d, 0x4(%rdi) - leaq -0x48(%rbp), %rdi - movl $0x1, %r8d - movl %r8d, (%rdi) - leaq -0x48(%rbp), %rdi - movl $0x2, %r8d - movl %r8d, 0x4(%rdi) - leaq -0x48(%rbp), %rdi - movl $0x3, %r8d - movl %r8d, 0x8(%rdi) - addq %rcx, %rax - movslq %eax, %rax - cmpq $0xa5, %rax - je - movl $0x1, %eax - addq $0x60, %rsp - popq %rbp - retq - movsbq (%rsi), %rax + leaq , %rax + leaq -0x30(%rbp), %rcx + movl $0x7, %edx + movl %edx, (%rcx) + leaq -0x30(%rbp), %rcx + xorq %rdx, %rdx + movq %rdx, 0x8(%rcx) + leaq -0x38(%rbp), %rcx + movl $0xb, %edx + movl %edx, (%rcx) + leaq -0x38(%rbp), %rcx + movl $0x16, %edx + movl %edx, 0x4(%rcx) + leaq -0x48(%rbp), %rcx + movl $0x1, %edx + movl %edx, (%rcx) + leaq -0x48(%rbp), %rcx + movl $0x2, %edx + movl %edx, 0x4(%rcx) + leaq -0x48(%rbp), %rcx + movl $0x3, %edx + movl %edx, 0x8(%rcx) + movsbq (%rax), %rax cmpq $0x68, %rax je movl $0x2, %eax @@ -69,9 +58,9 @@ Disassembly of section .text: retq leaq -0x38(%rbp), %rax movslq (%rax), %rax - leaq -0x38(%rbp), %rsi - movslq 0x4(%rsi), %rsi - addq %rsi, %rax + leaq -0x38(%rbp), %rcx + movslq 0x4(%rcx), %rcx + addq %rcx, %rax movslq %eax, %rax cmpq $0x21, %rax je @@ -81,12 +70,12 @@ Disassembly of section .text: retq leaq -0x48(%rbp), %rax movslq (%rax), %rax - leaq -0x48(%rbp), %rsi - movslq 0x4(%rsi), %rsi - addq %rsi, %rax - leaq -0x48(%rbp), %rsi - movslq 0x8(%rsi), %rsi - addq %rsi, %rax + leaq -0x48(%rbp), %rcx + movslq 0x4(%rcx), %rcx + addq %rcx, %rax + leaq -0x48(%rbp), %rcx + movslq 0x8(%rcx), %rcx + addq %rcx, %rax movslq %eax, %rax cmpq $0x6, %rax je @@ -94,29 +83,27 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - cmpq $0x499602d2, %rdx # imm = 0x499602D2 - je + xorq %rax, %rax + addq $0x60, %rsp + popq %rbp + retq + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq movl $0x6, %eax addq $0x60, %rsp popq %rbp retq - cmpq $0x41, %rcx - je movl $0x7, %eax addq $0x60, %rsp popq %rbp retq - jmp movl $0x8, %eax addq $0x60, %rsp popq %rbp retq - jmp movl $0x9, %eax addq $0x60, %rsp popq %rbp retq - xorq %rax, %rax - addq $0x60, %rsp - popq %rbp - retq diff --git a/tests/snapshots/asm/typedef_fn_ptr_struct_field.aarch64.asm b/tests/snapshots/asm/typedef_fn_ptr_struct_field.aarch64.asm index 07e06d215..b3ae66947 100644 --- a/tests/snapshots/asm/typedef_fn_ptr_struct_field.aarch64.asm +++ b/tests/snapshots/asm/typedef_fn_ptr_struct_field.aarch64.asm @@ -15,11 +15,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x20, [sp] + str x20, [sp, #-0xb0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0xa0] + add x29, sp, #0xa0 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -31,84 +30,67 @@ Disassembly of section .text: ldr x0, [x20] mov x1, #0x3 // =3 mov x2, #0x7 // =7 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x15 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0xa0] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xb0 ret ldr x0, [x20] mov x1, #0x4 // =4 mov x2, #0x5 // =5 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x14 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0xa0] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xb0 ret sub x0, x29, #0x10 ldr x0, [x0] mov x1, #0x2 // =2 mov x2, #0x9 // =9 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x12 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0xa0] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xb0 ret sub x0, x29, #0x10 ldr x0, [x0] mov x1, #0x6 // =6 mov x2, #0x4 // =4 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x0, w0 cmp x0, #0x18 b.eq mov x0, #0x4 // =4 - ldr x20, [sp] + ldp x29, x30, [sp, #0xa0] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xb0 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0xa0] ldr x19, [sp, #0x10] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xb0 ret diff --git a/tests/snapshots/asm/typedef_in_function_body.aarch64.asm b/tests/snapshots/asm/typedef_in_function_body.aarch64.asm index 17ad37f64..12e107463 100644 --- a/tests/snapshots/asm/typedef_in_function_body.aarch64.asm +++ b/tests/snapshots/asm/typedef_in_function_body.aarch64.asm @@ -10,64 +10,26 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x7 // =7 - sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x2 // =2 - mov x1, #0x1 // =1 - mov x2, #0x7 // =7 - sxtw x2, w2 - cmp x2, #0x7 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x64 b.eq + mov x0, #0x3 // =3 + ret + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x2, #0x5 // =5 - cmp x2, #0x5 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - adrp x2, - add x2, x2, - ldrsw x2, [x2] - cmp x2, #0x64 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - cmp x0, #0x2 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - add x1, x0, x1 - add x0, x1, x0 - sub x0, x0, #0x5 - sxtw x0, w0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/typedef_in_function_body.x64.asm b/tests/snapshots/asm/typedef_in_function_body.x64.asm index 68ad97d5d..af6caf307 100644 --- a/tests/snapshots/asm/typedef_in_function_body.x64.asm +++ b/tests/snapshots/asm/typedef_in_function_body.x64.asm @@ -11,64 +11,26 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0x7, %eax - movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0x2, %eax - movl $0x1, %ecx - movl $0x7, %edx - movslq %edx, %rdx - cmpq $0x7, %rdx + leaq , %rax + movslq (%rax), %rax + cmpq $0x64, %rax je + movl $0x3, %eax + retq + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x5, %edx - cmpq $0x5, %rdx - je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - leaq , %rdx - movslq (%rdx), %rdx - cmpq $0x64, %rdx - je - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - cmpq $0x2, %rax - je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp - retq - addq %rax, %rcx - addq %rcx, %rax - subq $0x5, %rax - movslq %eax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/typedef_name_as_declarator.aarch64.asm b/tests/snapshots/asm/typedef_name_as_declarator.aarch64.asm index 70d242680..7b2aba193 100644 --- a/tests/snapshots/asm/typedef_name_as_declarator.aarch64.asm +++ b/tests/snapshots/asm/typedef_name_as_declarator.aarch64.asm @@ -23,46 +23,34 @@ Disassembly of section .text: sub x0, x29, #0x10 mov x1, #0x5 // =5 str x1, [x0, #0x8] - mov x0, #0x3 // =3 - b - mov x0, #0xb // =11 + sub x0, x29, #0x10 + ldrh w0, [x0] + mov x17, #0x9c40 // =40000 + eor x0, x0, x17 + mov w0, w0 + cmp x0, #0x0 + b.eq + mov x0, #0xd // =13 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xc // =12 + mov x0, #0x0 // =0 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - sub x1, x29, #0x10 - ldrh w1, [x1] - mov x17, #0x9c40 // =40000 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - mov x0, #0xd // =13 + mov x0, #0xb // =11 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x17, #0x3 // =3 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0xe // =14 + mov x0, #0xc // =12 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7 // =7 - sxtw x0, w0 - cmp x0, #0x7 - b.eq - mov x0, #0xf // =15 + mov x0, #0xe // =14 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0xf // =15 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/typedef_name_as_declarator.x64.asm b/tests/snapshots/asm/typedef_name_as_declarator.x64.asm index e294a4606..66db5474e 100644 --- a/tests/snapshots/asm/typedef_name_as_declarator.x64.asm +++ b/tests/snapshots/asm/typedef_name_as_declarator.x64.asm @@ -24,44 +24,33 @@ Disassembly of section .text: leaq -0x10(%rbp), %rax movl $0x5, %ecx movq %rcx, 0x8(%rax) - movl $0x3, %eax - jmp - movl $0xb, %eax + leaq -0x10(%rbp), %rax + movzwq (%rax), %rax + xorq $0x9c40, %rax # imm = 0x9C40 + movl %eax, %eax + testq %rax, %rax + je + movl $0xd, %eax addq $0x20, %rsp popq %rbp retq - jmp - movl $0xc, %eax + xorq %rax, %rax addq $0x20, %rsp popq %rbp retq - leaq -0x10(%rbp), %rcx - movzwq (%rcx), %rcx - xorq $0x9c40, %rcx # imm = 0x9C40 - movl %ecx, %ecx - testq %rcx, %rcx - je - movl $0xd, %eax + movl $0xb, %eax addq $0x20, %rsp popq %rbp retq - xorq $0x3, %rax - movl %eax, %eax - testq %rax, %rax - je - movl $0xe, %eax + movl $0xc, %eax addq $0x20, %rsp popq %rbp retq - movl $0x7, %eax - movslq %eax, %rax - cmpq $0x7, %rax - je - movl $0xf, %eax + movl $0xe, %eax addq $0x20, %rsp popq %rbp retq - xorq %rax, %rax + movl $0xf, %eax addq $0x20, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/typedef_shadowed_by_parameter_name.aarch64.asm b/tests/snapshots/asm/typedef_shadowed_by_parameter_name.aarch64.asm index 784d36520..a3ee025d6 100644 --- a/tests/snapshots/asm/typedef_shadowed_by_parameter_name.aarch64.asm +++ b/tests/snapshots/asm/typedef_shadowed_by_parameter_name.aarch64.asm @@ -10,14 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/typedef_shadowed_by_parameter_name.x64.asm b/tests/snapshots/asm/typedef_shadowed_by_parameter_name.x64.asm index 105d08a9b..5319151f7 100644 --- a/tests/snapshots/asm/typedef_shadowed_by_parameter_name.x64.asm +++ b/tests/snapshots/asm/typedef_shadowed_by_parameter_name.x64.asm @@ -11,14 +11,12 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - xorq %rax, %rax - retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/typedef_struct_carrier_reset.aarch64.asm b/tests/snapshots/asm/typedef_struct_carrier_reset.aarch64.asm index e7b9d4703..62f3781e6 100644 --- a/tests/snapshots/asm/typedef_struct_carrier_reset.aarch64.asm +++ b/tests/snapshots/asm/typedef_struct_carrier_reset.aarch64.asm @@ -10,33 +10,112 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x2, #0x0 // =0 - mov x1, x2 - sxtw x3, w1 - cmp x3, #0xa - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 - b - sxtw x3, w1 - str w1, [x0, x3, lsl #2] + mov x1, #0x0 // =0 + add x2, x0, #0x0 + str w1, [x2] + add x1, x0, #0x28 + add x1, x1, #0x0 + mov x2, #0x1 // =1 + str w2, [x1] + add x1, x0, #0x0 + ldrsw x1, [x1] + add x2, x0, #0x28 + add x2, x2, #0x0 + ldrsw x2, [x2] + add x1, x1, x2 + add x1, x1, #0x0 + mov x2, #0x1 // =1 + str w2, [x0, #0x4] + add x2, x0, #0x28 + mov x3, #0x2 // =2 + str w3, [x2, #0x4] + ldrsw x2, [x0, #0x4] add x3, x0, #0x28 - sxtw x4, w1 - add x5, x4, #0x1 - str w5, [x3, x4, lsl #2] - sxtw x3, w1 - lsl x3, x3, #2 - add x4, x0, x3 - ldrsw x4, [x4] - add x5, x0, #0x28 - add x3, x5, x3 - ldrsw x3, [x3] - add x3, x4, x3 + ldrsw x3, [x3, #0x4] add x2, x2, x3 - b - str w2, [x0, #0xa0] - sxtw x0, w2 + add x1, x1, x2 + mov x2, #0x2 // =2 + str w2, [x0, #0x8] + add x2, x0, #0x28 + mov x3, #0x3 // =3 + str w3, [x2, #0x8] + ldrsw x2, [x0, #0x8] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x8] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x3 // =3 + str w2, [x0, #0xc] + add x2, x0, #0x28 + mov x3, #0x4 // =4 + str w3, [x2, #0xc] + ldrsw x2, [x0, #0xc] + add x3, x0, #0x28 + ldrsw x3, [x3, #0xc] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x4 // =4 + str w2, [x0, #0x10] + add x2, x0, #0x28 + mov x3, #0x5 // =5 + str w3, [x2, #0x10] + ldrsw x2, [x0, #0x10] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x10] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x5 // =5 + str w2, [x0, #0x14] + add x2, x0, #0x28 + mov x3, #0x6 // =6 + str w3, [x2, #0x14] + ldrsw x2, [x0, #0x14] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x14] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x6 // =6 + str w2, [x0, #0x18] + add x2, x0, #0x28 + mov x3, #0x7 // =7 + str w3, [x2, #0x18] + ldrsw x2, [x0, #0x18] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x18] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x7 // =7 + str w2, [x0, #0x1c] + add x2, x0, #0x28 + mov x3, #0x8 // =8 + str w3, [x2, #0x1c] + ldrsw x2, [x0, #0x1c] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x1c] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x8 // =8 + str w2, [x0, #0x20] + add x2, x0, #0x28 + mov x3, #0x9 // =9 + str w3, [x2, #0x20] + ldrsw x2, [x0, #0x20] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x20] + add x2, x2, x3 + add x1, x1, x2 + mov x2, #0x9 // =9 + str w2, [x0, #0x24] + add x2, x0, #0x28 + mov x3, #0xa // =10 + str w3, [x2, #0x24] + ldrsw x2, [x0, #0x24] + add x3, x0, #0x28 + ldrsw x3, [x3, #0x24] + add x2, x2, x3 + add x1, x1, x2 + str w1, [x0, #0xa0] + sxtw x0, w1 ret
: diff --git a/tests/snapshots/asm/typedef_struct_carrier_reset.x64.asm b/tests/snapshots/asm/typedef_struct_carrier_reset.x64.asm index c51d98b52..038af0baa 100644 --- a/tests/snapshots/asm/typedef_struct_carrier_reset.x64.asm +++ b/tests/snapshots/asm/typedef_struct_carrier_reset.x64.asm @@ -11,33 +11,112 @@ Disassembly of section .text: ud2 : - xorq %rcx, %rcx - movq %rcx, %rax - movslq %eax, %rdx - cmpq $0xa, %rdx - jge - jmp - movslq %eax, %rax - incq %rax - jmp - movslq %eax, %rdx - movl %eax, (%rdi,%rdx,4) + xorq %rax, %rax + leaq (%rdi), %rcx + movl %eax, (%rcx) + leaq 0x28(%rdi), %rax + addq $0x0, %rax + movl $0x1, %ecx + movl %ecx, (%rax) + leaq (%rdi), %rax + movslq (%rax), %rax + leaq 0x28(%rdi), %rcx + addq $0x0, %rcx + movslq (%rcx), %rcx + addq %rcx, %rax + addq $0x0, %rax + movl $0x1, %ecx + movl %ecx, 0x4(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x2, %edx + movl %edx, 0x4(%rcx) + movslq 0x4(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x4(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x2, %ecx + movl %ecx, 0x8(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x3, %edx + movl %edx, 0x8(%rcx) + movslq 0x8(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x8(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x3, %ecx + movl %ecx, 0xc(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x4, %edx + movl %edx, 0xc(%rcx) + movslq 0xc(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0xc(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x4, %ecx + movl %ecx, 0x10(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x5, %edx + movl %edx, 0x10(%rcx) + movslq 0x10(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x10(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x5, %ecx + movl %ecx, 0x14(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x6, %edx + movl %edx, 0x14(%rcx) + movslq 0x14(%rdi), %rcx leaq 0x28(%rdi), %rdx - movslq %eax, %rsi - leaq 0x1(%rsi), %r8 - movl %r8d, (%rdx,%rsi,4) - movslq %eax, %rdx - shlq $0x2, %rdx - leaq (%rdi,%rdx), %rsi - movslq (%rsi), %rsi - leaq 0x28(%rdi), %r8 - addq %r8, %rdx - movslq (%rdx), %rdx - addq %rsi, %rdx + movslq 0x14(%rdx), %rdx addq %rdx, %rcx - jmp - movl %ecx, 0xa0(%rdi) - movslq %ecx, %rax + addq %rcx, %rax + movl $0x6, %ecx + movl %ecx, 0x18(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x7, %edx + movl %edx, 0x18(%rcx) + movslq 0x18(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x18(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x7, %ecx + movl %ecx, 0x1c(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x8, %edx + movl %edx, 0x1c(%rcx) + movslq 0x1c(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x1c(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x8, %ecx + movl %ecx, 0x20(%rdi) + leaq 0x28(%rdi), %rcx + movl $0x9, %edx + movl %edx, 0x20(%rcx) + movslq 0x20(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x20(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl $0x9, %ecx + movl %ecx, 0x24(%rdi) + leaq 0x28(%rdi), %rcx + movl $0xa, %edx + movl %edx, 0x24(%rcx) + movslq 0x24(%rdi), %rcx + leaq 0x28(%rdi), %rdx + movslq 0x24(%rdx), %rdx + addq %rdx, %rcx + addq %rcx, %rax + movl %eax, 0xa0(%rdi) + movslq %eax, %rax retq
: @@ -82,4 +161,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/typeof_operator.aarch64.asm b/tests/snapshots/asm/typeof_operator.aarch64.asm index 73f481d19..be05d9f01 100644 --- a/tests/snapshots/asm/typeof_operator.aarch64.asm +++ b/tests/snapshots/asm/typeof_operator.aarch64.asm @@ -33,13 +33,6 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x64 // =100 - cmp x0, #0x64 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 ldrsw x0, [x0] cmp x0, #0x8 @@ -56,47 +49,36 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0x1, lsl #32 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0x1, lsl #32 - cmp x0, x17 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x0 b.eq - mov x0, #0x5 // =5 + mov x0, #0x9 // =9 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x6 // =6 + mov x0, #0x0 // =0 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - movk x0, #0x1, lsl #32 - sxtw x0, w0 - cmp x0, #0x1 - b.eq - mov x0, #0x7 // =7 + mov x0, #0x2 // =2 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x8 // =8 + mov x0, #0x5 // =5 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - adrp x0, - add x0, x0, - ldrsw x0, [x0] - cmp x0, #0x0 - b.eq - mov x0, #0x9 // =9 + mov x0, #0x6 // =6 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x7 // =7 + add sp, sp, #0x50 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x8 // =8 add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/typeof_operator.x64.asm b/tests/snapshots/asm/typeof_operator.x64.asm index b41eceebb..92db7e980 100644 --- a/tests/snapshots/asm/typeof_operator.x64.asm +++ b/tests/snapshots/asm/typeof_operator.x64.asm @@ -33,13 +33,6 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - movl $0x64, %eax - cmpq $0x64, %rax - je - movl $0x2, %eax - addq $0x50, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax movslq (%rax), %rax cmpq $0x8, %rax @@ -56,41 +49,36 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - movabsq $0x1ffffffff, %rax # imm = 0x1FFFFFFFF - movabsq $0x1ffffffff, %r11 # imm = 0x1FFFFFFFF - cmpq %r11, %rax + leaq , %rax + movslq (%rax), %rax + testq %rax, %rax je - movl $0x5, %eax + movl $0x9, %eax addq $0x50, %rsp popq %rbp retq - jmp - movl $0x6, %eax + xorq %rax, %rax addq $0x50, %rsp popq %rbp retq - movabsq $0x100000001, %rax # imm = 0x100000001 - movslq %eax, %rax - cmpq $0x1, %rax - je - movl $0x7, %eax + movl $0x2, %eax addq $0x50, %rsp popq %rbp retq - jmp - movl $0x8, %eax + movl $0x5, %eax addq $0x50, %rsp popq %rbp retq - leaq , %rax - movslq (%rax), %rax - testq %rax, %rax - je - movl $0x9, %eax + movl $0x6, %eax addq $0x50, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x7, %eax + addq $0x50, %rsp + popq %rbp + retq + movl $0x8, %eax addq $0x50, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/u16_load_store.aarch64.asm b/tests/snapshots/asm/u16_load_store.aarch64.asm index 90830f1e4..224f0d270 100644 --- a/tests/snapshots/asm/u16_load_store.aarch64.asm +++ b/tests/snapshots/asm/u16_load_store.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -43,9 +42,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x20 ldrb w0, [x0, #0x2] @@ -64,18 +62,16 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x20 ldrb w0, [x0, #0x4] cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret sub x0, x29, #0x10 add x0, x0, #0x1 @@ -88,14 +84,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 ret b b diff --git a/tests/snapshots/asm/uint64_to_float.aarch64.asm b/tests/snapshots/asm/uint64_to_float.aarch64.asm index 6be1cf4a9..600bcb465 100644 --- a/tests/snapshots/asm/uint64_to_float.aarch64.asm +++ b/tests/snapshots/asm/uint64_to_float.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 mov x0, #-0x8000000000000000 // =-9223372036854775808 mov x1, #0xad2 // =2770 movk x1, #0xeb1f, lsl #16 @@ -30,8 +27,6 @@ Disassembly of section .text: cset x4, ne cbz x4, mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ucvtf d0, x1 mov x1, #0x63e1 // =25569 @@ -43,8 +38,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ucvtf d0, x2 mov x1, #0x43f0000000000000 // =4895412794951729152 @@ -53,8 +46,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ucvtf d0, x3 mov x1, #0x4059000000000000 // =4636737291354636288 @@ -63,8 +54,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret scvtf d0, x2 mov x1, #0x3ff0000000000000 // =4607182418800017408 @@ -74,22 +63,15 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ucvtf d0, x0 fcvt s0, d0 - mov x0, #0x43e0000000000000 // =4890909195324358656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x5f000000 // =1593835520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/uint64_to_float.x64.asm b/tests/snapshots/asm/uint64_to_float.x64.asm index 6c45131dc..c7b097286 100644 --- a/tests/snapshots/asm/uint64_to_float.x64.asm +++ b/tests/snapshots/asm/uint64_to_float.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 movabsq $-0x54ab567314e0f52e, %rcx # imm = 0xAB54A98CEB1F0AD2 movabsq $-0x1, %rdx @@ -40,8 +37,6 @@ Disassembly of section .text: testq %rdi, %rdi je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movq %rcx, %r10 testq %r10, %r10 @@ -65,8 +60,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movq %rdx, %r10 testq %r10, %r10 @@ -90,8 +83,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movq %rsi, %r10 testq %r10, %r10 @@ -115,8 +106,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq cvtsi2sd %rdx, %xmm0 movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 @@ -133,8 +122,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq movq %rax, %r10 testq %r10, %r10 @@ -148,10 +135,9 @@ Disassembly of section .text: cvtsi2sd %r11, %xmm0 addsd %xmm0, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x43e0000000000000, %rax # imm = 0x43E0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x5f000000, %eax # imm = 0x5F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -160,11 +146,7 @@ Disassembly of section .text: testq %rax, %rax je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/unary_minus_uint64_compare.aarch64.asm b/tests/snapshots/asm/unary_minus_uint64_compare.aarch64.asm index e9c0eb16b..7017e27bf 100644 --- a/tests/snapshots/asm/unary_minus_uint64_compare.aarch64.asm +++ b/tests/snapshots/asm/unary_minus_uint64_compare.aarch64.asm @@ -13,19 +13,6 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x40 - mov x0, #0xa8 // =168 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - mov x17, #0x1000 // =4096 - cmp x0, x17 - b.hs - mov x0, #0xb // =11 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -48,17 +35,6 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xa8 // =168 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - mov x17, #0x1000 // =4096 - cmp x0, x17 - b.hs - mov x1, #0x1 // =1 - b mov x1, #0x2 // =2 sxtw x0, w1 cmp x0, #0x2 @@ -67,20 +43,17 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x8 // =8 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x0, x0, x17 - mov x17, #0x1000 // =4096 - cmp x0, x17 - b.hs - mov x0, #0xe // =14 + mov x0, #0x0 // =0 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0xb // =11 + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + ret + mov x1, #0x1 // =1 + b + mov x0, #0xe // =14 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unary_minus_uint64_compare.x64.asm b/tests/snapshots/asm/unary_minus_uint64_compare.x64.asm index 236aed6ff..32f4dde3d 100644 --- a/tests/snapshots/asm/unary_minus_uint64_compare.x64.asm +++ b/tests/snapshots/asm/unary_minus_uint64_compare.x64.asm @@ -14,14 +14,6 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x40, %rsp - movl $0xa8, %eax - imulq $-0x1, %rax, %rax - cmpq $0x1000, %rax # imm = 0x1000 - jae - movl $0xb, %eax - addq $0x40, %rsp - popq %rbp - retq leaq -0x10(%rbp), %rax leaq , %rcx pushq %rdx @@ -38,12 +30,6 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movl $0xa8, %eax - imulq $-0x1, %rax, %rax - cmpq $0x1000, %rax # imm = 0x1000 - jae - movl $0x1, %ecx - jmp movl $0x2, %ecx movslq %ecx, %rax cmpq $0x2, %rax @@ -52,16 +38,17 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movl $0x8, %eax - imulq $-0x1, %rax, %rax - cmpq $0x1000, %rax # imm = 0x1000 - jae - movl $0xe, %eax + xorq %rax, %rax addq $0x40, %rsp popq %rbp retq - xorq %rax, %rax + movl $0xb, %eax + addq $0x40, %rsp + popq %rbp + retq + movl $0x1, %ecx + jmp + movl $0xe, %eax addq $0x40, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unary_minus_unsigned_int_truncation.aarch64.asm b/tests/snapshots/asm/unary_minus_unsigned_int_truncation.aarch64.asm index 6dbbf3f1e..0e1d7f43c 100644 --- a/tests/snapshots/asm/unary_minus_unsigned_int_truncation.aarch64.asm +++ b/tests/snapshots/asm/unary_minus_unsigned_int_truncation.aarch64.asm @@ -10,135 +10,21 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - mov x0, #0x1 // =1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x1, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - orr x1, x0, x1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x1, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - orr x1, x0, x1 - lsr x1, x1, #31 - cmp x1, #0x1 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x1, #0x0 // =0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x2, x1, x17 - mov w2, w2 - orr x1, x1, x2 - lsr x1, x1, #31 - cmp x1, #0x0 - b.eq mov x0, #0x4 // =4 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - mov w2, w1 - orr x2, x0, x2 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x2, x17 - b.eq mov x0, #0x5 // =5 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov w1, w1 - orr x0, x0, x1 - lsr x0, x0, #31 - cmp x0, #0x1 - b.eq mov x0, #0x6 // =6 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x1, #0x0 // =0 - eor x0, x0, x1 - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - orr x0, x0, x1 - lsr x0, x0, #31 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x7 // =7 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x5 // =5 - eor x0, x0, x0 - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - mul x1, x0, x17 - mov w1, w1 - orr x0, x0, x1 - lsr x0, x0, #31 - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x1 - b.eq mov x0, #0x8 // =8 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unary_minus_unsigned_int_truncation.x64.asm b/tests/snapshots/asm/unary_minus_unsigned_int_truncation.x64.asm index 63ccbf94d..869034af0 100644 --- a/tests/snapshots/asm/unary_minus_unsigned_int_truncation.x64.asm +++ b/tests/snapshots/asm/unary_minus_unsigned_int_truncation.x64.asm @@ -11,103 +11,21 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movl $0x1, %eax - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rcx - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - orq %rax, %rcx - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rcx - je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - orq %rax, %rcx - shrq $0x1f, %rcx - cmpq $0x1, %rcx - je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq - xorq %rcx, %rcx - imulq $-0x1, %rcx, %rdx - movl %edx, %edx - orq %rdx, %rcx - shrq $0x1f, %rcx - testq %rcx, %rcx - je movl $0x4, %eax - addq $0x40, %rsp - popq %rbp retq - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - movl %ecx, %edx - orq %rax, %rdx - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rdx - je movl $0x5, %eax - addq $0x40, %rsp - popq %rbp retq - movl %ecx, %ecx - orq %rcx, %rax - shrq $0x1f, %rax - cmpq $0x1, %rax - je movl $0x6, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x1, %eax - xorq %rcx, %rcx - xorq %rcx, %rax - movl %eax, %eax - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - orq %rcx, %rax - shrq $0x1f, %rax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x7, %eax - addq $0x40, %rsp - popq %rbp retq - movl $0x5, %eax - xorq %rax, %rax - movl %eax, %eax - imulq $-0x1, %rax, %rcx - movl %ecx, %ecx - orq %rcx, %rax - shrq $0x1f, %rax - xorq $0x1, %rax - movl %eax, %eax - cmpq $0x1, %rax - je movl $0x8, %eax - addq $0x40, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/unary_plus_init_and_param_shadow.aarch64.asm b/tests/snapshots/asm/unary_plus_init_and_param_shadow.aarch64.asm index 60b3de606..ac9d70928 100644 --- a/tests/snapshots/asm/unary_plus_init_and_param_shadow.aarch64.asm +++ b/tests/snapshots/asm/unary_plus_init_and_param_shadow.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 fsub d0, d0, d1 mov x0, #0xa9fc // =43516 movk x0, #0xd2f1, lsl #16 @@ -34,8 +31,6 @@ Disassembly of section .text: cmp x0, #0x0 cset x2, ne mov x0, x2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b @@ -44,10 +39,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x20, add x20, x20, ldr d0, [x20] @@ -61,9 +55,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret ldr d0, [x20, #0x8] mov x0, #0x6666 // =26214 @@ -75,9 +68,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret ldr d0, [x20, #0x10] mov x0, #0x3ff0000000000000 // =4607182418800017408 @@ -86,9 +78,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret ldr d0, [x20, #0x18] mov x0, #0x4000000000000000 // =4611686018427387904 @@ -98,9 +89,8 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret adrp x0, add x0, x0, @@ -137,33 +127,21 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x5 // =5 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret mov x0, #0x0 // =0 - sxtw x0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x6 // =6 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x2a // =42 - sxtw x0, w0 - cmp x0, #0x2a - b.eq - mov x0, #0x7 // =7 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret b b b + mov x0, #0x6 // =6 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret + mov x0, #0x7 // =7 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 + ret diff --git a/tests/snapshots/asm/unary_plus_init_and_param_shadow.x64.asm b/tests/snapshots/asm/unary_plus_init_and_param_shadow.x64.asm index a2869f73d..9fd05ba19 100644 --- a/tests/snapshots/asm/unary_plus_init_and_param_shadow.x64.asm +++ b/tests/snapshots/asm/unary_plus_init_and_param_shadow.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp subsd %xmm1, %xmm0 movabsq $0x3f50624dd2f1a9fc, %rax # imm = 0x3F50624DD2F1A9FC movq %rax, %xmm15 @@ -38,8 +35,6 @@ Disassembly of section .text: setne %dl movzbq %dl, %rdx movq %rdx, %rax - addq $0x10, %rsp - popq %rbp retq jmp @@ -51,7 +46,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq , %rbx movsd (%rbx,%riz), %xmm0 @@ -65,7 +60,7 @@ Disassembly of section .text: jne movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movsd 0x8(%rbx,%riz), %xmm0 @@ -76,7 +71,7 @@ Disassembly of section .text: jne movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movsd 0x10(%rbx,%riz), %xmm0 @@ -87,7 +82,7 @@ Disassembly of section .text: jne movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movsd 0x18(%rbx,%riz), %xmm0 @@ -101,7 +96,7 @@ Disassembly of section .text: jne movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rax @@ -142,32 +137,25 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax - movslq %eax, %rax - testq %rax, %rax - je - movl $0x6, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - movl $0x2a, %eax - movslq %eax, %rax - cmpq $0x2a, %rax - je - movl $0x7, %eax + jmp + jmp + jmp + movl $0x6, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x7, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq - jmp - jmp - jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unary_plus_preserves_float.aarch64.asm b/tests/snapshots/asm/unary_plus_preserves_float.aarch64.asm index e66beb2fd..3e0c08126 100644 --- a/tests/snapshots/asm/unary_plus_preserves_float.aarch64.asm +++ b/tests/snapshots/asm/unary_plus_preserves_float.aarch64.asm @@ -43,11 +43,6 @@ Disassembly of section .text: fneg d0, d16 sub x17, x29, #0x38 str d0, [x17] - b - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - sub x17, x29, #0x38 - str d16, [x17] sub x16, x29, #0x38 ldr d0, [x16] mov x0, #0x3fe0000000000000 // =4602678819172646912 @@ -83,11 +78,6 @@ Disassembly of section .text: fneg d1, d16 sub x17, x29, #0x40 str d1, [x17] - b - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - sub x17, x29, #0x40 - str d16, [x17] sub x16, x29, #0x40 ldr d1, [x16] fadd d0, d0, d1 @@ -112,11 +102,6 @@ Disassembly of section .text: fneg d1, d16 sub x17, x29, #0x48 str d1, [x17] - b - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - sub x17, x29, #0x48 - str d16, [x17] sub x16, x29, #0x48 ldr d1, [x16] fadd d0, d0, d1 @@ -139,11 +124,6 @@ Disassembly of section .text: fneg d1, d16 sub x17, x29, #0x50 str d1, [x17] - b - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - sub x17, x29, #0x50 - str d16, [x17] sub x16, x29, #0x50 ldr d1, [x16] fadd d0, d0, d1 @@ -175,11 +155,6 @@ Disassembly of section .text: fneg d1, d16 sub x17, x29, #0x58 str d1, [x17] - b - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - sub x17, x29, #0x58 - str d16, [x17] sub x16, x29, #0x58 ldr d1, [x16] fadd d0, d0, d1 @@ -195,14 +170,36 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x7 // =7 - cmp x0, #0x7 - b.eq - mov x0, #0x8 // =8 + mov x0, #0x0 // =0 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + sub x17, x29, #0x58 + str d16, [x17] + b + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + sub x17, x29, #0x50 + str d16, [x17] + b + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + sub x17, x29, #0x48 + str d16, [x17] + b + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + sub x17, x29, #0x40 + str d16, [x17] + b + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + sub x17, x29, #0x38 + str d16, [x17] + b + mov x0, #0x8 // =8 add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unary_plus_preserves_float.x64.asm b/tests/snapshots/asm/unary_plus_preserves_float.x64.asm index 2bb376f12..9c6f403d2 100644 --- a/tests/snapshots/asm/unary_plus_preserves_float.x64.asm +++ b/tests/snapshots/asm/unary_plus_preserves_float.x64.asm @@ -52,10 +52,6 @@ Disassembly of section .text: movq %r10, %xmm15 xorpd %xmm15, %xmm0 movsd %xmm0, -0x38(%rbp,%riz) - jmp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x38(%rbp,%riz) movsd -0x38(%rbp,%riz), %xmm0 movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 movq %rax, %xmm15 @@ -106,10 +102,6 @@ Disassembly of section .text: movq %r10, %xmm15 xorpd %xmm15, %xmm1 movsd %xmm1, -0x40(%rbp,%riz) - jmp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) movsd -0x40(%rbp,%riz), %xmm1 addsd %xmm1, %xmm0 movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 @@ -143,10 +135,6 @@ Disassembly of section .text: movq %r10, %xmm15 xorpd %xmm15, %xmm1 movsd %xmm1, -0x48(%rbp,%riz) - jmp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x48(%rbp,%riz) movsd -0x48(%rbp,%riz), %xmm1 addsd %xmm1, %xmm0 cvttsd2si %xmm0, %rax @@ -173,10 +161,6 @@ Disassembly of section .text: movq %r10, %xmm15 xorpd %xmm15, %xmm1 movsd %xmm1, -0x50(%rbp,%riz) - jmp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x50(%rbp,%riz) movsd -0x50(%rbp,%riz), %xmm1 addsd %xmm1, %xmm0 cvttsd2si %xmm0, %rax @@ -218,10 +202,6 @@ Disassembly of section .text: movq %r10, %xmm15 xorpd %xmm15, %xmm1 movsd %xmm1, -0x58(%rbp,%riz) - jmp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x58(%rbp,%riz) movsd -0x58(%rbp,%riz), %xmm1 addsd %xmm1, %xmm0 cvttsd2si %xmm0, %rax @@ -243,14 +223,33 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movl $0x7, %eax - cmpq $0x7, %rax - je - movl $0x8, %eax + xorq %rax, %rax addq $0x60, %rsp popq %rbp retq - xorq %rax, %rax + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + movsd %xmm14, -0x58(%rbp,%riz) + jmp + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + movsd %xmm14, -0x50(%rbp,%riz) + jmp + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + movsd %xmm14, -0x48(%rbp,%riz) + jmp + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + movsd %xmm14, -0x40(%rbp,%riz) + jmp + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + movsd %xmm14, -0x38(%rbp,%riz) + jmp + movl $0x8, %eax addq $0x60, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unary_plus_preserves_type.aarch64.asm b/tests/snapshots/asm/unary_plus_preserves_type.aarch64.asm index d74d01581..19e537365 100644 --- a/tests/snapshots/asm/unary_plus_preserves_type.aarch64.asm +++ b/tests/snapshots/asm/unary_plus_preserves_type.aarch64.asm @@ -10,39 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x0, #0x0 // =0 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - cmp x0, x1 - cset x2, hs - cmp x2, #0x0 - b.eq + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - cmp x0, x1 - cset x0, hs - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x100000000 // =4294967296 - mov x17, #0x100000000 // =4294967296 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unary_plus_preserves_type.x64.asm b/tests/snapshots/asm/unary_plus_preserves_type.x64.asm index f60ee1fe0..1fe198d1d 100644 --- a/tests/snapshots/asm/unary_plus_preserves_type.x64.asm +++ b/tests/snapshots/asm/unary_plus_preserves_type.x64.asm @@ -11,39 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp xorq %rax, %rax - movabsq $-0x1, %rcx - cmpq %rcx, %rax - setae %dl - movzbq %dl, %rdx - testq %rdx, %rdx - je + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - cmpq %rcx, %rax - setae %al - movzbq %al, %rax - testq %rax, %rax - je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - movabsq $0x100000000, %rax # imm = 0x100000000 - movabsq $0x100000000, %r11 # imm = 0x100000000 - cmpq %r11, %rax - je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/union_bitfield_layout.aarch64.asm b/tests/snapshots/asm/union_bitfield_layout.aarch64.asm index 8724ad9ea..6f83d9639 100644 --- a/tests/snapshots/asm/union_bitfield_layout.aarch64.asm +++ b/tests/snapshots/asm/union_bitfield_layout.aarch64.asm @@ -13,50 +13,25 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - b - mov x0, #0xb // =11 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xc // =12 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xd // =13 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0xe // =14 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x15 // =21 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x8 - mov x1, #0x5 // =5 - ldr w2, [x0] + ldr w1, [x0] mov x17, #0xfff0 // =65520 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x5 // =5 + orr x1, x1, x17 str w1, [x0] sub x0, x29, #0x8 - mov x1, #0x3 // =3 - ldr w2, [x0, #0x4] + ldr w1, [x0, #0x4] mov x17, #0xfff0 // =65520 movk x17, #0xffff, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - and x2, x2, x17 - orr x1, x2, x1 + and x1, x1, x17 + mov x17, #0x3 // =3 + orr x1, x1, x17 str w1, [x0, #0x4] sub x0, x29, #0x8 ldr w0, [x0] @@ -86,3 +61,23 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret + mov x0, #0xb // =11 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xc // =12 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xd // =13 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xe // =14 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x15 // =21 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/union_bitfield_layout.x64.asm b/tests/snapshots/asm/union_bitfield_layout.x64.asm index e9fa45f40..dabb2986b 100644 --- a/tests/snapshots/asm/union_bitfield_layout.x64.asm +++ b/tests/snapshots/asm/union_bitfield_layout.x64.asm @@ -14,42 +14,15 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - jmp - movl $0xb, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0xc, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0xd, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0xe, %eax - addq $0x10, %rsp - popq %rbp - retq - jmp - movl $0x15, %eax - addq $0x10, %rsp - popq %rbp - retq leaq -0x8(%rbp), %rax - movl $0x5, %ecx - movl (%rax), %edx - andq $-0x10, %rdx - orq %rdx, %rcx + movl (%rax), %ecx + andq $-0x10, %rcx + orq $0x5, %rcx movl %ecx, (%rax) leaq -0x8(%rbp), %rax - movl $0x3, %ecx - movl 0x4(%rax), %edx - andq $-0x10, %rdx - orq %rdx, %rcx + movl 0x4(%rax), %ecx + andq $-0x10, %rcx + orq $0x3, %rcx movl %ecx, 0x4(%rax) leaq -0x8(%rbp), %rax movl (%rax), %eax @@ -77,3 +50,23 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + movl $0xb, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0xc, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0xd, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0xe, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x15, %eax + addq $0x10, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/union_member_unbraced_init.aarch64.asm b/tests/snapshots/asm/union_member_unbraced_init.aarch64.asm index 24d4e7a16..de2bb93b1 100644 --- a/tests/snapshots/asm/union_member_unbraced_init.aarch64.asm +++ b/tests/snapshots/asm/union_member_unbraced_init.aarch64.asm @@ -30,19 +30,15 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x2, #0x8 // =8 - sxtw x1, w2 - cmp x1, #0x10 - b.ge b - sxtw x1, w2 + add x3, x0, x1 + ldrb w3, [x3] + cmp x3, #0x0 + b.ne add x2, x1, #0x1 - b sxtw x1, w2 - add x1, x0, x1 - ldrb w1, [x1] - cmp x1, #0x0 - b.eq - b + cmp x1, #0x10 + b.lt adrp x0, add x0, x0, ldr d0, [x0] @@ -51,12 +47,6 @@ Disassembly of section .text: fcmp d0, d17 cset x1, ne cbnz x1, - b - mov x0, #0x2 // =2 - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - b adrp x0, add x0, x0, ldrsw x0, [x0, #0x8] @@ -193,4 +183,9 @@ Disassembly of section .text: b b b + mov x0, #0x2 // =2 + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + b b diff --git a/tests/snapshots/asm/union_member_unbraced_init.x64.asm b/tests/snapshots/asm/union_member_unbraced_init.x64.asm index af4978ecd..a150cc53f 100644 --- a/tests/snapshots/asm/union_member_unbraced_init.x64.asm +++ b/tests/snapshots/asm/union_member_unbraced_init.x64.asm @@ -37,19 +37,15 @@ Disassembly of section .text: popq %rbp retq movl $0x8, %edx - movslq %edx, %rcx - cmpq $0x10, %rcx - jge jmp - movslq %edx, %rcx + leaq (%rax,%rcx), %rsi + movsbq (%rsi), %rsi + testq %rsi, %rsi + jne leaq 0x1(%rcx), %rdx - jmp movslq %edx, %rcx - addq %rax, %rcx - movsbq (%rcx), %rcx - testq %rcx, %rcx - je - jmp + cmpq $0x10, %rcx + jl leaq , %rax movsd (%rax,%riz), %xmm0 movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 @@ -62,12 +58,6 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - jmp - movl $0x2, %eax - addq $0x80, %rsp - popq %rbp - retq - jmp leaq , %rax movslq 0x8(%rax), %rax cmpq $0x2b, %rax @@ -231,5 +221,10 @@ Disassembly of section .text: jmp jmp jmp + movl $0x2, %eax + addq $0x80, %rsp + popq %rbp + retq + jmp jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/unions_basic.aarch64.asm b/tests/snapshots/asm/unions_basic.aarch64.asm index f1d5716c5..a50cc356f 100644 --- a/tests/snapshots/asm/unions_basic.aarch64.asm +++ b/tests/snapshots/asm/unions_basic.aarch64.asm @@ -87,11 +87,6 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret sub x0, x29, #0x18 mov x1, #0x1 // =1 str w1, [x0] @@ -141,12 +136,15 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x0, #0xb // =11 + mov x0, #0x0 // =0 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 + mov x0, #0x6 // =6 + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xb // =11 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unions_basic.x64.asm b/tests/snapshots/asm/unions_basic.x64.asm index 54804c99f..79b16db73 100644 --- a/tests/snapshots/asm/unions_basic.x64.asm +++ b/tests/snapshots/asm/unions_basic.x64.asm @@ -82,11 +82,6 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - jmp - movl $0x6, %eax - addq $0x20, %rsp - popq %rbp - retq leaq -0x18(%rbp), %rax movl $0x1, %ecx movl %ecx, (%rax) @@ -132,12 +127,15 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - jmp - movl $0xb, %eax + xorq %rax, %rax addq $0x20, %rsp popq %rbp retq - xorq %rax, %rax + movl $0x6, %eax + addq $0x20, %rsp + popq %rbp + retq + movl $0xb, %eax addq $0x20, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/unistd_exposes_posix_types.aarch64.asm b/tests/snapshots/asm/unistd_exposes_posix_types.aarch64.asm index dda7d5982..7921fdb45 100644 --- a/tests/snapshots/asm/unistd_exposes_posix_types.aarch64.asm +++ b/tests/snapshots/asm/unistd_exposes_posix_types.aarch64.asm @@ -10,23 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0xb // =11 ret - b mov x0, #0xc // =12 ret - b mov x0, #0xd // =13 ret - b mov x0, #0xe // =14 ret - b mov x0, #0xf // =15 ret - b mov x0, #0x10 // =16 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/unistd_exposes_posix_types.x64.asm b/tests/snapshots/asm/unistd_exposes_posix_types.x64.asm index 070706a35..771078e3a 100644 --- a/tests/snapshots/asm/unistd_exposes_posix_types.x64.asm +++ b/tests/snapshots/asm/unistd_exposes_posix_types.x64.asm @@ -11,23 +11,17 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0xb, %eax retq - jmp movl $0xc, %eax retq - jmp movl $0xd, %eax retq - jmp movl $0xe, %eax retq - jmp movl $0xf, %eax retq - jmp movl $0x10, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/unroll_const_trip_copy.aarch64.asm b/tests/snapshots/asm/unroll_const_trip_copy.aarch64.asm new file mode 100644 index 000000000..713722c40 --- /dev/null +++ b/tests/snapshots/asm/unroll_const_trip_copy.aarch64.asm @@ -0,0 +1,148 @@ + +unroll_const_trip_copy.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + adrp x0, + add x0, x0, + add x0, x0, #0x0 + mov x1, #0x1 // =1 + str x1, [x0] + adrp x0, + add x0, x0, + mov x1, #0x4 // =4 + str x1, [x0, #0x8] + adrp x0, + add x0, x0, + mov x1, #0x7 // =7 + str x1, [x0, #0x10] + adrp x0, + add x0, x0, + mov x1, #0xa // =10 + str x1, [x0, #0x18] + adrp x0, + add x0, x0, + mov x1, #0xd // =13 + str x1, [x0, #0x20] + adrp x0, + add x0, x0, + mov x1, #0x10 // =16 + str x1, [x0, #0x28] + adrp x0, + add x0, x0, + mov x1, #0x13 // =19 + str x1, [x0, #0x30] + adrp x0, + add x0, x0, + mov x1, #0x16 // =22 + str x1, [x0, #0x38] + adrp x0, + add x0, x0, + add x0, x0, #0x0 + adrp x1, + add x1, x1, + add x1, x1, #0x0 + ldr x1, [x1] + str x1, [x0] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x8] + str x1, [x0, #0x8] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x10] + str x1, [x0, #0x10] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x18] + str x1, [x0, #0x18] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x20] + str x1, [x0, #0x20] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x28] + str x1, [x0, #0x28] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x30] + str x1, [x0, #0x30] + adrp x0, + add x0, x0, + adrp x1, + add x1, x1, + ldr x1, [x1, #0x38] + str x1, [x0, #0x38] + adrp x0, + add x0, x0, + ldr x0, [x0, #0x8] + lsr x0, x0, #0 + add x0, x0, #0x0 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x10] + lsl x1, x1, #1 + add x0, x0, x1 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x18] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x0, x0, x1 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x20] + lsl x1, x1, #2 + add x0, x0, x1 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x28] + mov x17, #0x5 // =5 + mul x1, x1, x17 + add x0, x0, x1 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x30] + mov x17, #0x6 // =6 + mul x1, x1, x17 + add x0, x0, x1 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x38] + mov x17, #0x7 // =7 + mul x1, x1, x17 + add x0, x0, x1 + adrp x1, + add x1, x1, + add x1, x1, #0x0 + ldr x1, [x1] + lsl x1, x1, #3 + add x0, x0, x1 + cmp x0, #0x1c8 + b.eq + mov x0, #0x1 // =1 + ret + mov x0, #0x0 // =0 + ret + mov x0, #0x2 // =2 + ret diff --git a/tests/snapshots/asm/unroll_const_trip_copy.x64.asm b/tests/snapshots/asm/unroll_const_trip_copy.x64.asm new file mode 100644 index 000000000..2807dce52 --- /dev/null +++ b/tests/snapshots/asm/unroll_const_trip_copy.x64.asm @@ -0,0 +1,114 @@ + +unroll_const_trip_copy.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + leaq , %rax + addq $0x0, %rax + movl $0x1, %ecx + movq %rcx, (%rax) + leaq , %rax + movl $0x4, %ecx + movq %rcx, 0x8(%rax) + leaq , %rax + movl $0x7, %ecx + movq %rcx, 0x10(%rax) + leaq , %rax + movl $0xa, %ecx + movq %rcx, 0x18(%rax) + leaq , %rax + movl $0xd, %ecx + movq %rcx, 0x20(%rax) + leaq , %rax + movl $0x10, %ecx + movq %rcx, 0x28(%rax) + leaq , %rax + movl $0x13, %ecx + movq %rcx, 0x30(%rax) + leaq , %rax + movl $0x16, %ecx + movq %rcx, 0x38(%rax) + leaq , %rax + addq $0x0, %rax + leaq , %rcx + addq $0x0, %rcx + movq (%rcx), %rcx + movq %rcx, (%rax) + leaq , %rax + leaq , %rcx + movq 0x8(%rcx), %rcx + movq %rcx, 0x8(%rax) + leaq , %rax + leaq , %rcx + movq 0x10(%rcx), %rcx + movq %rcx, 0x10(%rax) + leaq , %rax + leaq , %rcx + movq 0x18(%rcx), %rcx + movq %rcx, 0x18(%rax) + leaq , %rax + leaq , %rcx + movq 0x20(%rcx), %rcx + movq %rcx, 0x20(%rax) + leaq , %rax + leaq , %rcx + movq 0x28(%rcx), %rcx + movq %rcx, 0x28(%rax) + leaq , %rax + leaq , %rcx + movq 0x30(%rcx), %rcx + movq %rcx, 0x30(%rax) + leaq , %rax + leaq , %rcx + movq 0x38(%rcx), %rcx + movq %rcx, 0x38(%rax) + leaq , %rax + movq 0x8(%rax), %rax + shlq $0x0, %rax + addq $0x0, %rax + leaq , %rcx + movq 0x10(%rcx), %rcx + shlq $0x1, %rcx + addq %rcx, %rax + leaq , %rcx + movq 0x18(%rcx), %rcx + leaq (%rcx,%rcx,2), %rcx + addq %rcx, %rax + leaq , %rcx + movq 0x20(%rcx), %rcx + shlq $0x2, %rcx + addq %rcx, %rax + leaq , %rcx + movq 0x28(%rcx), %rcx + leaq (%rcx,%rcx,4), %rcx + addq %rcx, %rax + leaq , %rcx + movq 0x30(%rcx), %rcx + imulq $0x6, %rcx, %rcx + addq %rcx, %rax + leaq , %rcx + movq 0x38(%rcx), %rcx + imulq $0x7, %rcx, %rcx + addq %rcx, %rax + leaq , %rcx + addq $0x0, %rcx + movq (%rcx), %rcx + shlq $0x3, %rcx + addq %rcx, %rax + cmpq $0x1c8, %rax # imm = 0x1C8 + je + movl $0x1, %eax + retq + xorq %rax, %rax + retq + movl $0x2, %eax + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unroll_trip_17_stays_rolled.aarch64.asm b/tests/snapshots/asm/unroll_trip_17_stays_rolled.aarch64.asm new file mode 100644 index 000000000..e6d506a63 --- /dev/null +++ b/tests/snapshots/asm/unroll_trip_17_stays_rolled.aarch64.asm @@ -0,0 +1,42 @@ + +unroll_trip_17_stays_rolled.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x3, #0x0 // =0 + mov x0, x3 + b + adrp x1, + add x1, x1, + str x0, [x1, x0, lsl #3] + add x0, x0, #0x1 + cmp x0, #0x11 + b.lt + mov x1, #0x0 // =0 + b + adrp x0, + add x0, x0, + ldr x0, [x0, x1, lsl #3] + add x3, x3, x0 + add x1, x1, #0x1 + cmp x1, #0x11 + b.lt + cmp x3, #0x88 + cset x0, eq + mov x3, #0x0 // =0 + cbz x0, + cmp x1, #0x11 + cset x0, eq + cmp x0, #0x0 + cset x3, ne + cmp x3, #0x0 + cset x0, eq + ret + b diff --git a/tests/snapshots/asm/unroll_trip_17_stays_rolled.x64.asm b/tests/snapshots/asm/unroll_trip_17_stays_rolled.x64.asm new file mode 100644 index 000000000..2d52b0979 --- /dev/null +++ b/tests/snapshots/asm/unroll_trip_17_stays_rolled.x64.asm @@ -0,0 +1,48 @@ + +unroll_trip_17_stays_rolled.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + xorq %rsi, %rsi + movq %rsi, %rax + jmp + leaq , %rcx + movq %rax, (%rcx,%rax,8) + incq %rax + cmpq $0x11, %rax + jl + xorq %rcx, %rcx + jmp + leaq , %rax + movq (%rax,%rcx,8), %rax + addq %rax, %rsi + incq %rcx + cmpq $0x11, %rcx + jl + cmpq $0x88, %rsi + sete %al + movzbq %al, %rax + xorq %rsi, %rsi + testq %rax, %rax + je + cmpq $0x11, %rcx + sete %al + movzbq %al, %rax + testq %rax, %rax + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + sete %al + movzbq %al, %rax + retq + jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unroll_volatile_stays_rolled.aarch64.asm b/tests/snapshots/asm/unroll_volatile_stays_rolled.aarch64.asm new file mode 100644 index 000000000..082bb08e0 --- /dev/null +++ b/tests/snapshots/asm/unroll_volatile_stays_rolled.aarch64.asm @@ -0,0 +1,37 @@ + +unroll_volatile_stays_rolled.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x1, #0x0 // =0 + b + adrp x0, + add x0, x0, + ldr x2, [x0] + add x2, x2, #0x1 + str x2, [x0] + add x1, x1, #0x1 + cmp x1, #0x4 + b.lt + adrp x0, + add x0, x0, + ldr x0, [x0] + cmp x0, #0x4 + cset x0, eq + mov x3, #0x0 // =0 + cbz x0, + cmp x1, #0x4 + cset x0, eq + cmp x0, #0x0 + cset x3, ne + cmp x3, #0x0 + cset x0, eq + ret + b diff --git a/tests/snapshots/asm/unroll_volatile_stays_rolled.x64.asm b/tests/snapshots/asm/unroll_volatile_stays_rolled.x64.asm new file mode 100644 index 000000000..7d13402aa --- /dev/null +++ b/tests/snapshots/asm/unroll_volatile_stays_rolled.x64.asm @@ -0,0 +1,42 @@ + +unroll_volatile_stays_rolled.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + xorq %rcx, %rcx + jmp + leaq , %rax + movq (%rax), %rdx + incq %rdx + movq %rdx, (%rax) + incq %rcx + cmpq $0x4, %rcx + jl + leaq , %rax + movq (%rax), %rax + cmpq $0x4, %rax + sete %al + movzbq %al, %rax + xorq %rsi, %rsi + testq %rax, %rax + je + cmpq $0x4, %rcx + sete %al + movzbq %al, %rax + testq %rax, %rax + setne %sil + movzbq %sil, %rsi + testq %rsi, %rsi + sete %al + movzbq %al, %rax + retq + jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/unsigned_arith_high_half.aarch64.asm b/tests/snapshots/asm/unsigned_arith_high_half.aarch64.asm index 3eeb02429..33a3d37db 100644 --- a/tests/snapshots/asm/unsigned_arith_high_half.aarch64.asm +++ b/tests/snapshots/asm/unsigned_arith_high_half.aarch64.asm @@ -10,50 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0xff00 // =65280 - movk x0, #0xff00, lsl #16 - mvn x0, x0 - mov w0, w0 - mov x17, #0xff // =255 - movk x17, #0xff, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x5678 // =22136 - movk x0, #0x1234, lsl #16 - lsl x0, x0, #4 - mov w0, w0 - mov x17, #0x6780 // =26496 - movk x17, #0x2345, lsl #16 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - sub x0, x0, x1 - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unsigned_arith_high_half.x64.asm b/tests/snapshots/asm/unsigned_arith_high_half.x64.asm index 23708534a..b4f7372a0 100644 --- a/tests/snapshots/asm/unsigned_arith_high_half.x64.asm +++ b/tests/snapshots/asm/unsigned_arith_high_half.x64.asm @@ -11,43 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0xff00ff00, %eax # imm = 0xFF00FF00 - xorq $-0x1, %rax - movl %eax, %eax - xorq $0xff00ff, %rax # imm = 0xFF00FF - movl %eax, %eax - testq %rax, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x12345678, %eax # imm = 0x12345678 - shlq $0x4, %rax - movl %eax, %eax - xorq $0x23456780, %rax # imm = 0x23456780 - movl %eax, %eax - testq %rax, %rax - je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq - movl $0x1, %eax - movl $0x2, %ecx - subq %rcx, %rax - movl %eax, %eax - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/unsigned_char_array.aarch64.asm b/tests/snapshots/asm/unsigned_char_array.aarch64.asm index 0f6107b4f..eb17b853f 100644 --- a/tests/snapshots/asm/unsigned_char_array.aarch64.asm +++ b/tests/snapshots/asm/unsigned_char_array.aarch64.asm @@ -10,68 +10,69 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x19, [sp, #0x10] - adrp x20, - add x20, x20, - ldrb w0, [x20] - mov x17, #0x1 // =1 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x0, add x0, x0, - ldrb w1, [x20] + ldrb w1, [x0] + mov x17, #0x1 // =1 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 + b.eq + adrp x1, + add x1, x1, + ldrb w0, [x0] + mov x16, x1 + mov x1, x0 + mov x0, x16 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - ldrb w0, [x20, #0x5] + ldrb w1, [x0, #0x5] mov x17, #0x6 // =6 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 b.eq - adrp x0, - add x0, x0, - ldrb w1, [x20, #0x5] + adrp x1, + add x1, x1, + ldrb w0, [x0, #0x5] + mov x16, x1 + mov x1, x0 + mov x0, x16 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - ldrb w0, [x20, #0x9] + ldrb w1, [x0, #0x9] mov x17, #0xa // =10 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 + eor x1, x1, x17 + mov w1, w1 + cmp x1, #0x0 b.eq - adrp x0, - add x0, x0, - ldrb w1, [x20, #0x9] + adrp x1, + add x1, x1, + ldrb w0, [x0, #0x9] + mov x16, x1 + mov x1, x0 + mov x0, x16 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - adrp x0, - add x0, x0, - ldr x0, [x0] - cmp x0, #0x64 + adrp x1, + add x1, x1, + ldr x1, [x1] + cmp x1, #0x64 b.eq adrp x0, add x0, x0, @@ -81,15 +82,13 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - adrp x0, - add x0, x0, - ldr x0, [x0, #0x20] - cmp x0, #0x1f4 + adrp x1, + add x1, x1, + ldr x1, [x1, #0x20] + cmp x1, #0x1f4 b.eq adrp x0, add x0, x0, @@ -99,14 +98,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x0, #0x5 // =5 - add x1, x20, x0 - ldrb w1, [x1] + ldrb w1, [x0, #0x5] mov x17, #0x6 // =6 eor x1, x1, x17 mov w1, w1 @@ -114,22 +109,17 @@ Disassembly of section .text: b.eq adrp x1, add x1, x1, - add x0, x20, x0 - ldrb w0, [x0] + ldrb w0, [x0, #0x5] mov x16, x1 mov x1, x0 mov x0, x16 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/unsigned_char_array.x64.asm b/tests/snapshots/asm/unsigned_char_array.x64.asm index f58e3df0c..c8147fef3 100644 --- a/tests/snapshots/asm/unsigned_char_array.x64.asm +++ b/tests/snapshots/asm/unsigned_char_array.x64.asm @@ -13,57 +13,49 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp - movq %rbx, (%rsp) - leaq , %rbx - movzbq (%rbx), %rax - xorq $0x1, %rax - movl %eax, %eax - testq %rax, %rax + leaq , %rax + movzbq (%rax), %rcx + xorq $0x1, %rcx + movl %ecx, %ecx + testq %rcx, %rcx je leaq , %rdi - movzbq (%rbx), %rsi + movzbq (%rax), %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq - movzbq 0x5(%rbx), %rax - xorq $0x6, %rax - movl %eax, %eax - testq %rax, %rax + movzbq 0x5(%rax), %rcx + xorq $0x6, %rcx + movl %ecx, %ecx + testq %rcx, %rcx je leaq , %rdi - movzbq 0x5(%rbx), %rsi + movzbq 0x5(%rax), %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq - movzbq 0x9(%rbx), %rax - xorq $0xa, %rax - movl %eax, %eax - testq %rax, %rax + movzbq 0x9(%rax), %rcx + xorq $0xa, %rcx + movl %ecx, %ecx + testq %rcx, %rcx je leaq , %rdi - movzbq 0x9(%rbx), %rsi + movzbq 0x9(%rax), %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq - leaq , %rax - movq (%rax), %rax - cmpq $0x64, %rax + leaq , %rcx + movq (%rcx), %rcx + cmpq $0x64, %rcx je leaq , %rdi leaq , %rax @@ -72,13 +64,11 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq - leaq , %rax - movq 0x20(%rax), %rax - cmpq $0x1f4, %rax # imm = 0x1F4 + leaq , %rcx + movq 0x20(%rcx), %rcx + cmpq $0x1f4, %rcx # imm = 0x1F4 je leaq , %rdi leaq , %rax @@ -87,30 +77,22 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq - movl $0x5, %eax - leaq (%rbx,%rax), %rcx - movzbq (%rcx), %rcx + movzbq 0x5(%rax), %rcx xorq $0x6, %rcx movl %ecx, %ecx testq %rcx, %rcx je leaq , %rdi - addq %rbx, %rax - movzbq (%rax), %rsi + movzbq 0x5(%rax), %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x30, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/unsigned_compare.aarch64.asm b/tests/snapshots/asm/unsigned_compare.aarch64.asm index 2fbfe6a56..dce7e39ac 100644 --- a/tests/snapshots/asm/unsigned_compare.aarch64.asm +++ b/tests/snapshots/asm/unsigned_compare.aarch64.asm @@ -10,192 +10,98 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] - mov x20, #0x1 // =1 - mov x21, #0xfffe // =65534 - movk x21, #0xffff, lsl #16 - cmp x20, x21 - b.ls + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 + ret adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x21, x20 - cset x0, hi - cmp x0, #0x0 - b.ne adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x20, #0x1 // =1 - mov x21, #0xfffe // =65534 - movk x21, #0xffff, lsl #16 - cmp x20, x21 - b.ls adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x21, x20 - cset x0, hi - cmp x0, #0x0 - b.ne adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x20, #0x1 // =1 - mov x21, #0xfffe // =65534 - movk x21, #0xffff, lsl #16 - movk x21, #0xffff, lsl #32 - movk x21, #0xffff, lsl #48 - cmp x20, x21 - b.ls adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x21, x20 - cset x0, hi - cmp x0, #0x0 - b.ne adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x20, #0x1 // =1 - mov x21, #0xfffe // =65534 - movk x21, #0xffff, lsl #16 - movk x21, #0xffff, lsl #32 - movk x21, #0xffff, lsl #48 - cmp x20, x21 - b.lo adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x21, x20 - cset x0, hs - cmp x0, #0x0 - b.ne adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x0, #0x0 // =0 - mov x1, #0xfe // =254 - cmp x1, x0 - b.gt adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - mov x20, #0x1 // =1 - mov x21, #0xfffe // =65534 - movk x21, #0xffff, lsl #16 - movk x21, #0xffff, lsl #32 - movk x21, #0xffff, lsl #48 - cmp x20, x21 - cset x0, gt - cmp x0, #0x0 - b.ne adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret - cmp x20, x21 - b.ge adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/unsigned_compare.x64.asm b/tests/snapshots/asm/unsigned_compare.x64.asm index 6a02e82e6..9b64ab05d 100644 --- a/tests/snapshots/asm/unsigned_compare.x64.asm +++ b/tests/snapshots/asm/unsigned_compare.x64.asm @@ -13,172 +13,85 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x80, %rsp - movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) - movl $0x1, %ebx - movl $0xfffffffe, %r12d # imm = 0xFFFFFFFE - cmpq %r12, %rbx - jbe + xorq %rax, %rax + popq %rbp + retq leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - cmpq %rbx, %r12 - seta %al - movzbq %al, %rax - testq %rax, %rax - jne leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - movl $0x1, %ebx - movl $0xfffffffe, %r12d # imm = 0xFFFFFFFE - cmpq %r12, %rbx - jbe leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - cmpq %rbx, %r12 - seta %al - movzbq %al, %rax - testq %rax, %rax - jne leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - movl $0x1, %ebx - movabsq $-0x2, %r12 - cmpq %r12, %rbx - jbe leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - cmpq %rbx, %r12 - seta %al - movzbq %al, %rax - testq %rax, %rax - jne leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - movl $0x1, %ebx - movabsq $-0x2, %r12 - cmpq %r12, %rbx - jb leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - cmpq %rbx, %r12 - setae %al - movzbq %al, %rax - testq %rax, %rax - jne leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - xorq %rax, %rax - movl $0xfe, %ecx - cmpq %rax, %rcx - jg leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - movl $0x1, %ebx - movabsq $-0x2, %r12 - cmpq %r12, %rbx - setg %al - movzbq %al, %rax - testq %rax, %rax - jne leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq - cmpq %r12, %rbx - jge leaq , %rdi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp - popq %rbp - retq - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - addq $0x80, %rsp popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unsigned_compound_assign.aarch64.asm b/tests/snapshots/asm/unsigned_compound_assign.aarch64.asm index ddf1b3e5a..9f69053ec 100644 --- a/tests/snapshots/asm/unsigned_compound_assign.aarch64.asm +++ b/tests/snapshots/asm/unsigned_compound_assign.aarch64.asm @@ -10,113 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] - str x19, [sp, #0x10] - mov x0, #0x64 // =100 - add x20, x0, #0x5 - mov w0, w20 - mov x17, #0x69 // =105 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - adrp x0, - add x0, x0, - mov w1, w20 - bl - sxtw x0, w0 - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov w0, w20 - sub x0, x0, #0x3 - mov w1, w0 - mov x17, #0x66 // =102 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - adrp x1, - add x1, x1, - mov w0, w0 - mov x16, x1 - mov x1, x0 - mov x0, x16 - bl - sxtw x0, w0 - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x3e8 // =1000 - add x1, x0, #0x19f - cmp x1, #0x587 - b.eq - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x41c // =1052 - mov x1, #0x19f // =415 - add x0, x0, x1 - mov w1, w0 - mov x17, #0x5bb // =1467 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - adrp x1, - add x1, x1, - mov w0, w0 - mov x16, x1 - mov x1, x0 - mov x0, x16 - bl - sxtw x0, w0 - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xc8 // =200 - add x0, x0, #0x3c - mov x17, #0xff // =255 - and x1, x0, x17 - mov x17, #0x4 // =4 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - adrp x1, - add x1, x1, - mov x17, #0xff // =255 - and x0, x0, x17 - mov x16, x1 - mov x1, x0 - mov x0, x16 - bl - sxtw x0, w0 - mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 - ret + str x19, [sp, #-0x80]! + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 + mov x1, #0x587 // =1415 sub x0, x29, #0x40 mov x1, #0x0 // =0 str w1, [x0] @@ -145,14 +42,54 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 + ret + adrp x0, + add x0, x0, + mov x1, #0x69 // =105 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 + ret + adrp x0, + add x0, x0, + mov x1, #0x66 // =102 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 + ret + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 + ret + adrp x0, + add x0, x0, + mov x1, #0x5bb // =1467 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 + ret + adrp x0, + add x0, x0, + mov x1, #0x4 // =4 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldp x29, x30, [sp, #0x70] + ldr x19, [sp], #0x80 ret diff --git a/tests/snapshots/asm/unsigned_compound_assign.x64.asm b/tests/snapshots/asm/unsigned_compound_assign.x64.asm index aaefd5bc9..581759d0d 100644 --- a/tests/snapshots/asm/unsigned_compound_assign.x64.asm +++ b/tests/snapshots/asm/unsigned_compound_assign.x64.asm @@ -13,124 +13,81 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp - movq %rbx, (%rsp) - movl $0x64, %eax - leaq 0x5(%rax), %rbx - movl %ebx, %eax - xorq $0x69, %rax - movl %eax, %eax - testq %rax, %rax + subq $0x60, %rsp + movl $0x587, %esi # imm = 0x587 + leaq -0x40(%rbp), %rax + xorq %rcx, %rcx + movl %ecx, (%rax) + leaq -0x40(%rbp), %rax + movl $0xa, %ecx + movl %ecx, 0x4(%rax) + leaq -0x40(%rbp), %rax + movl $0x14, %ecx + movl %ecx, 0x8(%rax) + leaq -0x40(%rbp), %rax + movl $0x1e, %ecx + movl %ecx, 0xc(%rax) + leaq -0x40(%rbp), %rax + movl $0x28, %ecx + movl %ecx, 0x10(%rax) + leaq -0x40(%rbp), %rax + movslq 0xc(%rax), %rcx + cmpq $0x1e, %rcx je leaq , %rdi - movl %ebx, %esi + movslq 0xc(%rax), %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x60, %rsp popq %rbp retq - movl %ebx, %eax - subq $0x3, %rax - movl %eax, %ecx - xorq $0x66, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je leaq , %rdi - movl %eax, %esi + movl $0x69, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - movl $0x3e8, %eax # imm = 0x3E8 - leaq 0x19f(%rax), %rsi - cmpq $0x587, %rsi # imm = 0x587 - je leaq , %rdi + movl $0x66, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - movl $0x41c, %eax # imm = 0x41C - movl $0x19f, %ecx # imm = 0x19F - addq %rcx, %rax - movl %eax, %ecx - xorq $0x5bb, %rcx # imm = 0x5BB - movl %ecx, %ecx - testq %rcx, %rcx - je leaq , %rdi - movl %eax, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - movl $0xc8, %eax - addq $0x3c, %rax - movq %rax, %rcx - andq $0xff, %rcx - xorq $0x4, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je leaq , %rdi - movq %rax, %rsi - andq $0xff, %rsi + movl $0x5bb, %esi # imm = 0x5BB movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - leaq -0x40(%rbp), %rax - xorq %rcx, %rcx - movl %ecx, (%rax) - leaq -0x40(%rbp), %rax - movl $0xa, %ecx - movl %ecx, 0x4(%rax) - leaq -0x40(%rbp), %rax - movl $0x14, %ecx - movl %ecx, 0x8(%rax) - leaq -0x40(%rbp), %rax - movl $0x1e, %ecx - movl %ecx, 0xc(%rax) - leaq -0x40(%rbp), %rax - movl $0x28, %ecx - movl %ecx, 0x10(%rax) - leaq -0x40(%rbp), %rax - movslq 0xc(%rax), %rcx - cmpq $0x1e, %rcx - je leaq , %rdi - movslq 0xc(%rax), %rsi + movl $0x4, %esi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x70, %rsp - popq %rbp - retq - xorq %rax, %rax - movq (%rsp), %rbx - addq $0x70, %rsp + addq $0x60, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unsigned_div_in_assign.aarch64.asm b/tests/snapshots/asm/unsigned_div_in_assign.aarch64.asm index 34d25036b..67bdf2fc4 100644 --- a/tests/snapshots/asm/unsigned_div_in_assign.aarch64.asm +++ b/tests/snapshots/asm/unsigned_div_in_assign.aarch64.asm @@ -47,9 +47,9 @@ Disassembly of section .text: cmp x0, #0x3ea b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/unsigned_div_in_assign.x64.asm b/tests/snapshots/asm/unsigned_div_in_assign.x64.asm index c270ea078..e4bdb1395 100644 --- a/tests/snapshots/asm/unsigned_div_in_assign.x64.asm +++ b/tests/snapshots/asm/unsigned_div_in_assign.x64.asm @@ -66,10 +66,10 @@ Disassembly of section .text: cmpq $0x3ea, %rax # imm = 0x3EA jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unsigned_div_mod.aarch64.asm b/tests/snapshots/asm/unsigned_div_mod.aarch64.asm index 268cf1779..bac0afd47 100644 --- a/tests/snapshots/asm/unsigned_div_mod.aarch64.asm +++ b/tests/snapshots/asm/unsigned_div_mod.aarch64.asm @@ -10,54 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - mov x1, #0x2 // =2 - udiv x0, x0, x1 - mov w0, w0 - mov x17, #0xffff // =65535 - movk x17, #0x7fff, lsl #16 - cmp x0, x17 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0x7 // =7 - udiv x17, x0, x1 - msub x0, x17, x1, x0 - mov w0, w0 - mov x17, #0x3 // =3 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0xfffe // =65534 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x1, #0x2 // =2 - udiv x0, x0, x1 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0x7fff, lsl #48 - cmp x0, x17 - b.eq mov x0, #0x3 // =3 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unsigned_div_mod.x64.asm b/tests/snapshots/asm/unsigned_div_mod.x64.asm index d03e81baf..01b1bf7b0 100644 --- a/tests/snapshots/asm/unsigned_div_mod.x64.asm +++ b/tests/snapshots/asm/unsigned_div_mod.x64.asm @@ -11,54 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x60, %rsp - movl $0xfffffffe, %eax # imm = 0xFFFFFFFE - movl $0x2, %ecx - pushq %rdx - xorq %rdx, %rdx - divq %rcx - popq %rdx - movl %eax, %eax - cmpq $0x7fffffff, %rax # imm = 0x7FFFFFFF - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x60, %rsp - popq %rbp retq - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movl $0x7, %ecx - pushq %rdx - xorq %rdx, %rdx - divq %rcx - movq %rdx, %rax - popq %rdx - movl %eax, %eax - xorq $0x3, %rax - movl %eax, %eax - testq %rax, %rax - je movl $0x2, %eax - addq $0x60, %rsp - popq %rbp retq - movabsq $-0x2, %rax - movl $0x2, %ecx - pushq %rdx - xorq %rdx, %rdx - divq %rcx - popq %rdx - movabsq $0x7fffffffffffffff, %r11 # imm = 0x7FFFFFFFFFFFFFFF - cmpq %r11, %rax - je movl $0x3, %eax - addq $0x60, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x60, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unsigned_right_shift.aarch64.asm b/tests/snapshots/asm/unsigned_right_shift.aarch64.asm index b07e6a06f..c3daef76f 100644 --- a/tests/snapshots/asm/unsigned_right_shift.aarch64.asm +++ b/tests/snapshots/asm/unsigned_right_shift.aarch64.asm @@ -10,31 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x80000000 // =2147483648 - lsr x0, x0, #1 - mov w0, w0 - mov x17, #0x40000000 // =1073741824 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret - mov x0, #-0x8000000000000000 // =-9223372036854775808 - lsr x0, x0, #1 - mov x17, #0x4000000000000000 // =4611686018427387904 - cmp x0, x17 - b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/unsigned_right_shift.x64.asm b/tests/snapshots/asm/unsigned_right_shift.x64.asm index 2b1016e9b..be68c94f4 100644 --- a/tests/snapshots/asm/unsigned_right_shift.x64.asm +++ b/tests/snapshots/asm/unsigned_right_shift.x64.asm @@ -11,32 +11,9 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0x80000000, %eax # imm = 0x80000000 - shrq $0x1, %rax - movl %eax, %eax - xorq $0x40000000, %rax # imm = 0x40000000 - movl %eax, %eax - testq %rax, %rax - je + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq - movabsq $-0x8000000000000000, %rax # imm = 0x8000000000000000 - shrq $0x1, %rax - movabsq $0x4000000000000000, %r11 # imm = 0x4000000000000000 - cmpq %r11, %rax - je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/unsigned_signed_relational_compare.aarch64.asm b/tests/snapshots/asm/unsigned_signed_relational_compare.aarch64.asm index 9f2172c87..608c1af4b 100644 --- a/tests/snapshots/asm/unsigned_signed_relational_compare.aarch64.asm +++ b/tests/snapshots/asm/unsigned_signed_relational_compare.aarch64.asm @@ -10,98 +10,27 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - mov x1, #0xffff // =65535 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - mov w2, w1 - cmp x0, x2 - b.hs + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x6 // =6 + ret + mov x1, #0x0 // =0 + mov x1, #0x0 // =0 + cbz x1, + mov x0, #0x7 // =7 + ret + mov x0, #0x0 // =0 + ret mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov w2, w1 - cmp x2, x0 - b.hs mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov w2, w1 - cmp x0, x2 - cset x2, ls - cmp x2, #0x0 - b.ne mov x0, #0x3 // =3 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov w2, w1 - cmp x0, x2 - cset x2, hs - cmp x2, #0x0 - b.ne mov x0, #0x4 // =4 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov w2, w1 - cmp x0, x2 - b.ls mov x0, #0x5 // =5 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x5 // =5 - mov x2, #0xa // =10 - cmp x0, x2 - cset x3, lo - cmp x3, #0x0 - cset x4, eq - cbnz x4, - cmp x2, x0 - cset x4, lo - cbz x4, - mov x0, #0x6 // =6 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xfffb // =65531 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - mov x2, #0x3 // =3 - cmp x0, x2 - cset x3, lt - cmp x3, #0x0 - cset x4, eq - cbnz x4, - cmp x2, x0 - cset x4, lt - cbz x4, - mov x0, #0x7 // =7 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xffff // =65535 - movk x0, #0xffff, lsl #16 - movk x0, #0xffff, lsl #32 - movk x0, #0xffff, lsl #48 - cmp x0, x1 - b.hs mov x0, #0x8 // =8 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret - mov x0, #0x0 // =0 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b - b diff --git a/tests/snapshots/asm/unsigned_signed_relational_compare.x64.asm b/tests/snapshots/asm/unsigned_signed_relational_compare.x64.asm index dbb93283f..9c8c0379a 100644 --- a/tests/snapshots/asm/unsigned_signed_relational_compare.x64.asm +++ b/tests/snapshots/asm/unsigned_signed_relational_compare.x64.asm @@ -11,100 +11,30 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x50, %rsp - movl $0xffffffff, %eax # imm = 0xFFFFFFFF - movabsq $-0x1, %rcx - movl %ecx, %edx - cmpq %rdx, %rax - jae + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x6, %eax + retq + xorq %rcx, %rcx + xorq %rcx, %rcx + testq %rcx, %rcx + je + movl $0x7, %eax + retq + xorq %rax, %rax + retq movl $0x1, %eax - addq $0x50, %rsp - popq %rbp retq - movl %ecx, %edx - cmpq %rax, %rdx - jae movl $0x2, %eax - addq $0x50, %rsp - popq %rbp retq - movl %ecx, %edx - cmpq %rdx, %rax - setbe %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne movl $0x3, %eax - addq $0x50, %rsp - popq %rbp retq - movl %ecx, %edx - cmpq %rdx, %rax - setae %dl - movzbq %dl, %rdx - testq %rdx, %rdx - jne movl $0x4, %eax - addq $0x50, %rsp - popq %rbp retq - movl %ecx, %edx - cmpq %rdx, %rax - jbe movl $0x5, %eax - addq $0x50, %rsp - popq %rbp retq - movl $0x5, %eax - movl $0xa, %edx - cmpq %rdx, %rax - setb %sil - movzbq %sil, %rsi - testq %rsi, %rsi - sete %dil - movzbq %dil, %rdi - testq %rdi, %rdi - jne - cmpq %rax, %rdx - setb %dil - movzbq %dil, %rdi - testq %rdi, %rdi - je - movl $0x6, %eax - addq $0x50, %rsp - popq %rbp - retq - movabsq $-0x5, %rax - movl $0x3, %edx - cmpq %rdx, %rax - setl %sil - movzbq %sil, %rsi - testq %rsi, %rsi - sete %dil - movzbq %dil, %rdi - testq %rdi, %rdi - jne - cmpq %rax, %rdx - setl %dil - movzbq %dil, %rdi - testq %rdi, %rdi - je - movl $0x7, %eax - addq $0x50, %rsp - popq %rbp - retq - movabsq $-0x1, %rax - cmpq %rcx, %rax - jae movl $0x8, %eax - addq $0x50, %rsp - popq %rbp - retq - xorq %rax, %rax - addq $0x50, %rsp - popq %rbp retq - jmp - jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/use_after_free.aarch64.asm b/tests/snapshots/asm/use_after_free.aarch64.asm index 820e83bcd..9ac1ee87e 100644 --- a/tests/snapshots/asm/use_after_free.aarch64.asm +++ b/tests/snapshots/asm/use_after_free.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x8 // =8 bl mov x20, x0 @@ -24,8 +23,7 @@ Disassembly of section .text: bl sxtw x0, w0 ldrsw x0, [x20] - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/use_after_free.x64.asm b/tests/snapshots/asm/use_after_free.x64.asm index 1dfe06821..81ab49d0c 100644 --- a/tests/snapshots/asm/use_after_free.x64.asm +++ b/tests/snapshots/asm/use_after_free.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x20, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x8, %edi xorl %eax, %eax @@ -27,7 +27,7 @@ Disassembly of section .text: movslq %eax, %rax movslq (%rbx), %rax movq (%rsp), %rbx - addq $0x20, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/va_arg_composite_straddle.aarch64.asm b/tests/snapshots/asm/va_arg_composite_straddle.aarch64.asm index ef52d20f8..34000c120 100644 --- a/tests/snapshots/asm/va_arg_composite_straddle.aarch64.asm +++ b/tests/snapshots/asm/va_arg_composite_straddle.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -51,15 +50,9 @@ Disassembly of section .text: movk x17, #0xffff, lsl #48 str w17, [x16, #0x1c] mov x1, #0x0 // =0 - sxtw x0, w1 - cmp x0, #0x6 - b.ge b - sxtw x0, w1 - add x1, x0, #0x1 - b - sub x0, x29, #0x20 - mov x17, x0 + sub x2, x29, #0x20 + mov x17, x2 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -76,8 +69,11 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x0, x16 - b + mov x2, x16 + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x6 + b.lt sub x0, x29, #0x20 mov x17, x0 str x9, [sp, #-0x10]! @@ -137,23 +133,20 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret cmp x0, #0x309 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret b diff --git a/tests/snapshots/asm/va_arg_composite_straddle.x64.asm b/tests/snapshots/asm/va_arg_composite_straddle.x64.asm index ca809d7fe..a6a45c234 100644 --- a/tests/snapshots/asm/va_arg_composite_straddle.x64.asm +++ b/tests/snapshots/asm/va_arg_composite_straddle.x64.asm @@ -39,15 +39,9 @@ Disassembly of section .text: leaq -0xf0(%rbp), %r10 movq %r10, 0x10(%rax) xorq %rcx, %rcx - movslq %ecx, %rax - cmpq $0x6, %rax - jge - jmp - movslq %ecx, %rax - leaq 0x1(%rax), %rcx jmp - leaq -0x18(%rbp), %rax - movq %rax, %r11 + leaq -0x18(%rbp), %rdx + movq %rdx, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -56,8 +50,11 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rax - jmp + movq %r10, %rdx + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x6, %rax + jl leaq -0x18(%rbp), %rax movq %rax, %r11 movl (%r11), %r10d @@ -159,4 +156,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/va_arg_int_seq.aarch64.asm b/tests/snapshots/asm/va_arg_int_seq.aarch64.asm index 9f9eb1889..11184802d 100644 --- a/tests/snapshots/asm/va_arg_int_seq.aarch64.asm +++ b/tests/snapshots/asm/va_arg_int_seq.aarch64.asm @@ -27,11 +27,10 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x70 - str x20, [sp] + str x20, [sp, #-0x80]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x70] + add x29, sp, #0x70 sub x0, x29, #0x20 add x1, x29, #0x18 mov x16, x0 @@ -58,13 +57,6 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0x0 // =0 - sxtw x0, w20 - ldursw x1, [x29, #0x18] - cmp x0, x1 - b.ge - b - sxtw x0, w20 - add x20, x0, #0x1 b sub x0, x29, #0x20 mov x17, x0 @@ -91,17 +83,21 @@ Disassembly of section .text: sxtw x1, w20 bl sxtw x0, w0 - b + sxtw x0, w20 + add x20, x0, #0x1 + sxtw x0, w20 + ldursw x1, [x29, #0x18] + cmp x0, x1 + b.lt sub x0, x29, #0x20 adrp x0, add x0, x0, bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x70] ldr x19, [sp, #0x10] - add sp, sp, #0x70 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x80 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/va_arg_int_seq.x64.asm b/tests/snapshots/asm/va_arg_int_seq.x64.asm index 6d69e9812..20e3f5f99 100644 --- a/tests/snapshots/asm/va_arg_int_seq.x64.asm +++ b/tests/snapshots/asm/va_arg_int_seq.x64.asm @@ -46,13 +46,6 @@ Disassembly of section .text: callq movslq %eax, %rax xorq %rbx, %rbx - movslq %ebx, %rax - movslq -0xe8(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq %ebx, %rax - leaq 0x1(%rax), %rbx jmp leaq -0x18(%rbp), %rax movq %rax, %r11 @@ -71,7 +64,12 @@ Disassembly of section .text: movb $0x0, %al callq movslq %eax, %rax - jmp + movslq %ebx, %rax + leaq 0x1(%rax), %rbx + movslq %ebx, %rax + movslq -0xe8(%rbp), %rcx + cmpq %rcx, %rax + jl leaq -0x18(%rbp), %rax leaq , %rdi movb $0x0, %al diff --git a/tests/snapshots/asm/va_arg_through_pointer.aarch64.asm b/tests/snapshots/asm/va_arg_through_pointer.aarch64.asm index a922faf63..20141ab5e 100644 --- a/tests/snapshots/asm/va_arg_through_pointer.aarch64.asm +++ b/tests/snapshots/asm/va_arg_through_pointer.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 adrp x1, add x1, x1, mov x17, x0 @@ -81,9 +80,8 @@ Disassembly of section .text: ldr d0, [x0] str d0, [x1] mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : @@ -104,10 +102,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -131,16 +128,14 @@ Disassembly of section .text: bl sub x0, x29, #0x20 mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 adrp x0, add x0, x0, adrp x1, @@ -155,7 +150,6 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -167,7 +161,6 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -191,11 +184,9 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/va_arg_through_pointer.x64.asm b/tests/snapshots/asm/va_arg_through_pointer.x64.asm index 59a544955..6d5c6a3cb 100644 --- a/tests/snapshots/asm/va_arg_through_pointer.x64.asm +++ b/tests/snapshots/asm/va_arg_through_pointer.x64.asm @@ -95,7 +95,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp leaq , %rdi leaq , %rsi movl $0x2a, %edx @@ -108,7 +107,6 @@ Disassembly of section .text: cmpq $0x2a, %rax je movl $0x1, %eax - addq $0x30, %rsp popq %rbp retq leaq , %rax @@ -124,7 +122,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x2, %eax - addq $0x30, %rsp popq %rbp retq leaq , %rax @@ -144,11 +141,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp popq %rbp retq jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/va_copy.aarch64.asm b/tests/snapshots/asm/va_copy.aarch64.asm index aa1d2fe5d..275d3ef79 100644 --- a/tests/snapshots/asm/va_copy.aarch64.asm +++ b/tests/snapshots/asm/va_copy.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -64,10 +63,7 @@ Disassembly of section .text: ldr x9, [sp], #0x10 mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x10] - cmp x2, x3 - b.ge + b sub x2, x29, #0x40 mov x17, x2 str x9, [sp, #-0x10]! @@ -91,13 +87,15 @@ Disassembly of section .text: add x0, x0, x2 add x1, x1, #0x1 sxtw x1, w1 - b + sxtw x2, w1 + ldursw x3, [x29, #0x10] + cmp x2, x3 + b.lt sub x1, x29, #0x40 sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/va_copy.x64.asm b/tests/snapshots/asm/va_copy.x64.asm index 14ece69be..ed0ac2dd0 100644 --- a/tests/snapshots/asm/va_copy.x64.asm +++ b/tests/snapshots/asm/va_copy.x64.asm @@ -50,10 +50,7 @@ Disassembly of section .text: popq %rdx xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xf0(%rbp), %rsi - cmpq %rsi, %rdx - jge + jmp leaq -0x30(%rbp), %rdx movq %rdx, %r11 movl (%r11), %r10d @@ -69,7 +66,10 @@ Disassembly of section .text: addq %rdx, %rax incq %rcx movslq %ecx, %rcx - jmp + movslq %ecx, %rdx + movslq -0xf0(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x30(%rbp), %rcx leaq -0x18(%rbp), %rcx movslq %eax, %rax diff --git a/tests/snapshots/asm/va_copy_under_pressure.aarch64.asm b/tests/snapshots/asm/va_copy_under_pressure.aarch64.asm index 8dcb6e4ae..58c7d8617 100644 --- a/tests/snapshots/asm/va_copy_under_pressure.aarch64.asm +++ b/tests/snapshots/asm/va_copy_under_pressure.aarch64.asm @@ -27,11 +27,10 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xe0 - str x20, [sp] + str x20, [sp, #-0xf0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0xe0] + add x29, sp, #0xe0 ldur x0, [x29, #0x10] mov x17, #0x3 // =3 mul x1, x0, x17 @@ -141,28 +140,24 @@ Disassembly of section .text: add x0, x1, x0 add x0, x0, x14 add x0, x0, x15 - ldr x20, [sp] + ldp x29, x30, [sp, #0xe0] ldr x19, [sp, #0x10] - add sp, sp, #0xe0 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xf0 add sp, sp, #0xc0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 mov x0, #0x2 // =2 mov x1, #0xa // =10 mov x2, #0x14 // =20 bl - mov x1, #0x160 // =352 - cmp x0, x1 + cmp x0, #0x160 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/va_copy_under_pressure.x64.asm b/tests/snapshots/asm/va_copy_under_pressure.x64.asm index 764d2443b..13d1bce34 100644 --- a/tests/snapshots/asm/va_copy_under_pressure.x64.asm +++ b/tests/snapshots/asm/va_copy_under_pressure.x64.asm @@ -139,21 +139,17 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp movl $0x2, %edi movl $0xa, %esi movl $0x14, %edx movb $0x0, %al callq - movl $0x160, %ecx # imm = 0x160 - cmpq %rcx, %rax + cmpq $0x160, %rax # imm = 0x160 jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variable_shadowing.aarch64.asm b/tests/snapshots/asm/variable_shadowing.aarch64.asm index 5bef69f32..17a5a650f 100644 --- a/tests/snapshots/asm/variable_shadowing.aarch64.asm +++ b/tests/snapshots/asm/variable_shadowing.aarch64.asm @@ -10,10 +10,5 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0xa // =10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/variable_shadowing.x64.asm b/tests/snapshots/asm/variable_shadowing.x64.asm index 5e1daa327..759ba633c 100644 --- a/tests/snapshots/asm/variable_shadowing.x64.asm +++ b/tests/snapshots/asm/variable_shadowing.x64.asm @@ -11,12 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0xa, %eax - addq $0x10, %rsp - popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variable_shift_rcx_loop.aarch64.asm b/tests/snapshots/asm/variable_shift_rcx_loop.aarch64.asm index 0bab3eb2d..92ed78296 100644 --- a/tests/snapshots/asm/variable_shift_rcx_loop.aarch64.asm +++ b/tests/snapshots/asm/variable_shift_rcx_loop.aarch64.asm @@ -10,28 +10,20 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x5, #0x0 // =0 mov x4, x5 - cmp x4, x0 - b.ge b + add x4, x5, x3 lsl x6, x1, x2 add x5, x5, x6 - b - add x4, x5, x3 - b + cmp x4, x0 + b.lt mov x0, x3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 mov x0, #0x64 // =100 mov x1, #0x2 // =2 mov x2, #0x3 // =3 @@ -40,9 +32,8 @@ Disassembly of section .text: cmp x0, #0x1 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/variable_shift_rcx_loop.x64.asm b/tests/snapshots/asm/variable_shift_rcx_loop.x64.asm index bd95a6d08..1466230b7 100644 --- a/tests/snapshots/asm/variable_shift_rcx_loop.x64.asm +++ b/tests/snapshots/asm/variable_shift_rcx_loop.x64.asm @@ -11,32 +11,24 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movq %rcx, %rax xorq %r8, %r8 movq %r8, %rcx - cmpq %rdi, %rcx - jge jmp + leaq (%r8,%rax), %rcx movq %rsi, %r9 pushq %rcx movq %rdx, %rcx shlq %cl, %r9 popq %rcx addq %r9, %r8 - jmp - leaq (%r8,%rax), %rcx - jmp - addq $0x10, %rsp - popq %rbp + cmpq %rdi, %rcx + jl retq
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp movl $0x64, %edi movl $0x2, %esi movl $0x3, %edx @@ -45,11 +37,8 @@ Disassembly of section .text: cmpq $0x1, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax - addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) + movl $0x1, %ecx + jmp diff --git a/tests/snapshots/asm/variadic_agg_return_classes.aarch64.asm b/tests/snapshots/asm/variadic_agg_return_classes.aarch64.asm index 576e0adb2..eb05d1379 100644 --- a/tests/snapshots/asm/variadic_agg_return_classes.aarch64.asm +++ b/tests/snapshots/asm/variadic_agg_return_classes.aarch64.asm @@ -92,8 +92,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] + sub sp, sp, #0x80 mov x0, #0x2 // =2 bl sub x16, x29, #0x58 @@ -113,18 +112,17 @@ Disassembly of section .text: mov x0, #0x4008000000000000 // =4613937818241073152 fmov d17, x0 fcmp d0, d17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x10 ldr d0, [x0, #0x8] mov x0, #0x4002000000000000 // =4612248968380809216 fmov d17, x0 fcmp d0, d17 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x90 + add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 @@ -154,13 +152,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x90 + add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x90 + add sp, sp, #0x80 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/variadic_agg_return_classes.x64.asm b/tests/snapshots/asm/variadic_agg_return_classes.x64.asm index 29d7a6db8..1a268e518 100644 --- a/tests/snapshots/asm/variadic_agg_return_classes.x64.asm +++ b/tests/snapshots/asm/variadic_agg_return_classes.x64.asm @@ -90,8 +90,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x90, %rsp - movq %rbx, (%rsp) + subq $0x80, %rsp movl $0x2, %edi movb $0x0, %al callq @@ -111,28 +110,27 @@ Disassembly of section .text: movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movsd 0x8(%rax,%riz), %xmm0 movabsq $0x4002000000000000, %rax # imm = 0x4002000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x90, %rsp + addq $0x80, %rsp popq %rbp retq movl $0x1, %edi @@ -169,13 +167,11 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x90, %rsp + addq $0x80, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x90, %rsp + addq $0x80, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/variadic_cast_fnptr_dispatch.aarch64.asm b/tests/snapshots/asm/variadic_cast_fnptr_dispatch.aarch64.asm index e2f561d40..bfbe49e74 100644 --- a/tests/snapshots/asm/variadic_cast_fnptr_dispatch.aarch64.asm +++ b/tests/snapshots/asm/variadic_cast_fnptr_dispatch.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x19, [sp] + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x20 mov x1, #0x0 // =0 strb w1, [x0] @@ -40,9 +39,8 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret sub x0, x29, #0x20 adrp x1, @@ -52,14 +50,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret <__c5_sys_snprintf>: diff --git a/tests/snapshots/asm/variadic_fn_ptr_init.aarch64.asm b/tests/snapshots/asm/variadic_fn_ptr_init.aarch64.asm index 1e258a00a..4dce80cbf 100644 --- a/tests/snapshots/asm/variadic_fn_ptr_init.aarch64.asm +++ b/tests/snapshots/asm/variadic_fn_ptr_init.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x18 mov x16, x0 @@ -52,16 +51,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x18] - cmp x2, x3 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 b - sub x2, x29, #0x20 - mov x17, x2 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,26 +70,28 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x2, x16 - ldrsw x2, [x2] - add x0, x0, x2 - b + mov x3, x16 + ldrsw x3, [x3] + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + ldursw x3, [x29, #0x18] + cmp x2, x3 + b.lt sub x1, x29, #0x20 ldur x1, [x29, #0x10] str w0, [x1] mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + str x20, [sp, #-0x70]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 adrp x20, add x20, x20, mov x0, #0xffff // =65535 @@ -115,10 +109,9 @@ Disassembly of section .text: cmp x0, #0x7b b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 @@ -136,14 +129,12 @@ Disassembly of section .text: cmp x0, #0x7b b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x60] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x70 ret diff --git a/tests/snapshots/asm/variadic_fn_ptr_init.x64.asm b/tests/snapshots/asm/variadic_fn_ptr_init.x64.asm index 6365fdc9e..2bfc4031e 100644 --- a/tests/snapshots/asm/variadic_fn_ptr_init.x64.asm +++ b/tests/snapshots/asm/variadic_fn_ptr_init.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xd8(%rbp), %rsi - cmpq %rsi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - leaq -0x18(%rbp), %rdx - movq %rdx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -58,10 +51,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rdx - movslq (%rdx), %rdx - addq %rdx, %rax - jmp + movq %r10, %rsi + movslq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + movslq -0xd8(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x18(%rbp), %rcx movq -0xe0(%rbp), %rcx movl %eax, (%rcx) @@ -116,5 +113,4 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variadic_fnptr_proto_erased.aarch64.asm b/tests/snapshots/asm/variadic_fnptr_proto_erased.aarch64.asm index 173e31cd7..00b75eecc 100644 --- a/tests/snapshots/asm/variadic_fnptr_proto_erased.aarch64.asm +++ b/tests/snapshots/asm/variadic_fnptr_proto_erased.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -52,16 +51,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x10] - cmp x2, x3 - b.ge b - sxtw x1, w1 - add x1, x1, #0x1 - b - sub x2, x29, #0x20 - mov x17, x2 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,23 +70,25 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x2, x16 - ldrsw x2, [x2] - add x0, x0, x2 - b + mov x3, x16 + ldrsw x3, [x3] + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + ldursw x3, [x29, #0x10] + cmp x2, x3 + b.lt sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldr x0, [x0] mov x1, #0x4 // =4 mov x2, #0x64 // =100 @@ -109,16 +103,14 @@ Disassembly of section .text: mov x4, x5 blr x9 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldr x0, [x0] mov x1, #0x3 // =3 mov x2, #0xb // =11 @@ -131,16 +123,14 @@ Disassembly of section .text: mov x3, x4 blr x9 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 ldr x0, [x0] mov x1, #0x2 // =2 mov x2, #0x28 // =40 @@ -151,9 +141,8 @@ Disassembly of section .text: mov x2, x3 blr x9 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret
: diff --git a/tests/snapshots/asm/variadic_fnptr_proto_erased.x64.asm b/tests/snapshots/asm/variadic_fnptr_proto_erased.x64.asm index eefdc4a6f..aa5b2f89d 100644 --- a/tests/snapshots/asm/variadic_fnptr_proto_erased.x64.asm +++ b/tests/snapshots/asm/variadic_fnptr_proto_erased.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xe0(%rbp), %rsi - cmpq %rsi, %rdx - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - leaq -0x18(%rbp), %rdx - movq %rdx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -58,10 +51,14 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rdx - movslq (%rdx), %rdx - addq %rdx, %rax - jmp + movq %r10, %rsi + movslq (%rsi), %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + movslq -0xe0(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x18(%rbp), %rcx movslq %eax, %rax addq $0xe0, %rsp @@ -154,4 +151,3 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/variadic_hfa_struct_arg.aarch64.asm b/tests/snapshots/asm/variadic_hfa_struct_arg.aarch64.asm index aa3007d4b..8b5a4e3d5 100644 --- a/tests/snapshots/asm/variadic_hfa_struct_arg.aarch64.asm +++ b/tests/snapshots/asm/variadic_hfa_struct_arg.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -83,9 +82,8 @@ Disassembly of section .text: sub x0, x29, #0x30 ldr d1, [x0, #0x8] fadd d0, d0, d1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret @@ -112,9 +110,9 @@ Disassembly of section .text: cset x0, eq cbz x0, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/variadic_hfa_struct_arg.x64.asm b/tests/snapshots/asm/variadic_hfa_struct_arg.x64.asm index c4ec0839c..ba49372b4 100644 --- a/tests/snapshots/asm/variadic_hfa_struct_arg.x64.asm +++ b/tests/snapshots/asm/variadic_hfa_struct_arg.x64.asm @@ -97,10 +97,10 @@ Disassembly of section .text: testq %rax, %rax je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/variadic_libc_fnptr_static_init.aarch64.asm b/tests/snapshots/asm/variadic_libc_fnptr_static_init.aarch64.asm index 737edf560..8c6e86315 100644 --- a/tests/snapshots/asm/variadic_libc_fnptr_static_init.aarch64.asm +++ b/tests/snapshots/asm/variadic_libc_fnptr_static_init.aarch64.asm @@ -10,10 +10,9 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0xa0 - str x19, [sp] + str x19, [sp, #-0xb0]! + stp x29, x30, [sp, #0xa0] + add x29, sp, #0xa0 sub x0, x29, #0x40 mov x1, #0x0 // =0 strb w1, [x0] @@ -44,14 +43,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0xa0 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0xa0] + ldr x19, [sp], #0xb0 ret <__c5_sys_snprintf>: diff --git a/tests/snapshots/asm/variadic_macro_named_rest.aarch64.asm b/tests/snapshots/asm/variadic_macro_named_rest.aarch64.asm index 7daafd95c..7bf36bd16 100644 --- a/tests/snapshots/asm/variadic_macro_named_rest.aarch64.asm +++ b/tests/snapshots/asm/variadic_macro_named_rest.aarch64.asm @@ -20,69 +20,27 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, - b + ldrb w0, [x2] + ldrb w3, [x1] + cmp x0, x3 + cset x3, eq + cbz x3, add x2, x2, #0x1 add x1, x1, #0x1 b + b ldrb w0, [x2] ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret - ldrb w0, [x2] - ldrb w3, [x1] - cmp x0, x3 - cset x3, eq - cbz x3, - b - b
: stp x29, x30, [sp, #-0x10]! mov x29, sp - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - add x0, x0, x1 - add x0, x0, x2 - sxtw x0, w0 - cmp x0, #0x6 - b.eq - mov x0, #0x1 // =1 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0xa // =10 - mov x1, #0xfffc // =65532 - movk x1, #0xffff, lsl #16 - movk x1, #0xffff, lsl #32 - movk x1, #0xffff, lsl #48 - mov x2, #0xfffa // =65530 - movk x2, #0xffff, lsl #16 - movk x2, #0xffff, lsl #32 - movk x2, #0xffff, lsl #48 - add x0, x0, x1 - add x0, x0, x2 - sxtw x0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x2 // =2 - ldp x29, x30, [sp], #0x10 - ret - mov x0, #0x5 // =5 - sxtw x0, w0 - cmp x0, #0x5 - b.eq - mov x0, #0x3 // =3 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, adrp x1, @@ -96,3 +54,12 @@ Disassembly of section .text: mov x0, #0x0 // =0 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/variadic_macro_named_rest.x64.asm b/tests/snapshots/asm/variadic_macro_named_rest.x64.asm index 42db04cd8..e2c702009 100644 --- a/tests/snapshots/asm/variadic_macro_named_rest.x64.asm +++ b/tests/snapshots/asm/variadic_macro_named_rest.x64.asm @@ -22,24 +22,9 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je - jmp - incq %rdi - incq %rsi - jmp - movsbq (%rdi), %rax - movsbq (%rsi), %rcx - cmpq %rcx, %rax - sete %al - movzbq %al, %rax - addq $0x10, %rsp - popq %rbp - retq movsbq (%rdi), %rax movsbq (%rsi), %rcx cmpq %rcx, %rax @@ -47,41 +32,20 @@ Disassembly of section .text: movzbq %cl, %rcx testq %rcx, %rcx je + incq %rdi + incq %rsi jmp jmp + movsbq (%rdi), %rax + movsbq (%rsi), %rcx + cmpq %rcx, %rax + sete %al + movzbq %al, %rax + retq
: pushq %rbp movq %rsp, %rbp - movl $0x1, %eax - movl $0x2, %ecx - movl $0x3, %edx - addq %rcx, %rax - addq %rdx, %rax - movslq %eax, %rax - cmpq $0x6, %rax - je - movl $0x1, %eax - popq %rbp - retq - movl $0xa, %eax - movabsq $-0x4, %rcx - movabsq $-0x6, %rdx - addq %rcx, %rax - addq %rdx, %rax - movslq %eax, %rax - testq %rax, %rax - je - movl $0x2, %eax - popq %rbp - retq - movl $0x5, %eax - movslq %eax, %rax - cmpq $0x5, %rax - je - movl $0x3, %eax - popq %rbp - retq leaq , %rdi leaq , %rsi callq @@ -93,4 +57,13 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + movl $0x1, %eax + popq %rbp + retq + movl $0x2, %eax + popq %rbp + retq + movl $0x3, %eax + popq %rbp + retq addb %al, (%rax) diff --git a/tests/snapshots/asm/variadic_optimizer_survives.aarch64.asm b/tests/snapshots/asm/variadic_optimizer_survives.aarch64.asm index e92d515c9..9b784e1f9 100644 --- a/tests/snapshots/asm/variadic_optimizer_survives.aarch64.asm +++ b/tests/snapshots/asm/variadic_optimizer_survives.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x50]! + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -94,23 +93,20 @@ Disassembly of section .text: cmp x0, #0x2a b.eq mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret cmp x1, #0x7 b.eq mov x0, #0x2 // =2 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x40] + ldr x19, [sp], #0x50 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/variadic_sprintf.aarch64.asm b/tests/snapshots/asm/variadic_sprintf.aarch64.asm index 8fff456ec..5a5d61fbb 100644 --- a/tests/snapshots/asm/variadic_sprintf.aarch64.asm +++ b/tests/snapshots/asm/variadic_sprintf.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x40 // =64 bl mov x20, x0 @@ -31,10 +30,9 @@ Disassembly of section .text: cmp x0, #0xb b.eq mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x1, add x1, x1, @@ -45,17 +43,15 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, x20 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/variadic_sprintf.x64.asm b/tests/snapshots/asm/variadic_sprintf.x64.asm index a6d8c24d4..efc4d0ffc 100644 --- a/tests/snapshots/asm/variadic_sprintf.x64.asm +++ b/tests/snapshots/asm/variadic_sprintf.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x40, %edi xorl %eax, %eax @@ -33,7 +33,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rsi @@ -46,7 +46,7 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq movq %rbx, %rdi @@ -55,7 +55,7 @@ Disassembly of section .text: movslq %eax, %rax xorq %rax, %rax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variadic_struct_arg.aarch64.asm b/tests/snapshots/asm/variadic_struct_arg.aarch64.asm index 20d726a85..265e8df5d 100644 --- a/tests/snapshots/asm/variadic_struct_arg.aarch64.asm +++ b/tests/snapshots/asm/variadic_struct_arg.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -52,16 +51,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x10] - cmp x2, x3 - b.ge - b - sxtw x1, w1 - add x1, x1, #0x1 b - sub x2, x29, #0x20 - mov x17, x2 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,25 +70,28 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x2, x16 - sub x3, x29, #0x38 + mov x3, x16 + sub x4, x29, #0x38 str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x3] + ldr x10, [x3] + str x10, [x4] ldr x10, [sp], #0x10 - mov x2, x3 - sub x2, x29, #0x38 - ldrsw x2, [x2] + mov x3, x4 sub x3, x29, #0x38 - ldrsw x3, [x3, #0x4] - add x2, x2, x3 - add x0, x0, x2 - b + ldrsw x3, [x3] + sub x4, x29, #0x38 + ldrsw x4, [x4, #0x4] + add x3, x3, x4 + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + ldursw x3, [x29, #0x10] + cmp x2, x3 + b.lt sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/variadic_struct_arg.x64.asm b/tests/snapshots/asm/variadic_struct_arg.x64.asm index 2bc14a1e0..39412dcd1 100644 --- a/tests/snapshots/asm/variadic_struct_arg.x64.asm +++ b/tests/snapshots/asm/variadic_struct_arg.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xe0(%rbp), %rsi - cmpq %rsi, %rdx - jge jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq -0x18(%rbp), %rdx - movq %rdx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -58,20 +51,24 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rdx - leaq -0x30(%rbp), %rsi + movq %r10, %rsi + leaq -0x30(%rbp), %rdi pushq %rax - movq (%rdx), %rax - movq %rax, (%rsi) + movq (%rsi), %rax + movq %rax, (%rdi) popq %rax - movq %rsi, %rdx - leaq -0x30(%rbp), %rdx - movslq (%rdx), %rdx + movq %rdi, %rsi leaq -0x30(%rbp), %rsi - movslq 0x4(%rsi), %rsi - addq %rsi, %rdx - addq %rdx, %rax - jmp + movslq (%rsi), %rsi + leaq -0x30(%rbp), %rdi + movslq 0x4(%rdi), %rdi + addq %rdi, %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + movslq -0xe0(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x18(%rbp), %rcx movslq %eax, %rax addq $0xe0, %rsp @@ -104,4 +101,5 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variadic_struct_arg_16b.aarch64.asm b/tests/snapshots/asm/variadic_struct_arg_16b.aarch64.asm index f12351cae..471bfdf20 100644 --- a/tests/snapshots/asm/variadic_struct_arg_16b.aarch64.asm +++ b/tests/snapshots/asm/variadic_struct_arg_16b.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -52,16 +51,9 @@ Disassembly of section .text: str w17, [x16, #0x1c] mov x1, #0x0 // =0 mov x0, x1 - sxtw x2, w1 - ldursw x3, [x29, #0x10] - cmp x2, x3 - b.ge b - sxtw x1, w1 - add x1, x1, #0x1 - b - sub x2, x29, #0x20 - mov x17, x2 + sub x3, x29, #0x20 + mov x17, x3 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -78,27 +70,30 @@ Disassembly of section .text: add x9, x16, #0x10 str x9, [x17] ldr x9, [sp], #0x10 - mov x2, x16 - sub x3, x29, #0x40 + mov x3, x16 + sub x4, x29, #0x40 str x10, [sp, #-0x10]! - ldr x10, [x2] - str x10, [x3] - ldr x10, [x2, #0x8] - str x10, [x3, #0x8] + ldr x10, [x3] + str x10, [x4] + ldr x10, [x3, #0x8] + str x10, [x4, #0x8] ldr x10, [sp], #0x10 - mov x2, x3 - sub x2, x29, #0x40 - ldr x2, [x2] + mov x3, x4 sub x3, x29, #0x40 - ldr x3, [x3, #0x8] - lsl x3, x3, #1 - add x2, x2, x3 - add x0, x0, x2 - b + ldr x3, [x3] + sub x4, x29, #0x40 + ldr x4, [x4, #0x8] + lsl x4, x4, #1 + add x3, x3, x4 + add x0, x0, x3 + add x1, x2, #0x1 + sxtw x2, w1 + ldursw x3, [x29, #0x10] + cmp x2, x3 + b.lt sub x1, x29, #0x20 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 add sp, sp, #0xc0 ret diff --git a/tests/snapshots/asm/variadic_struct_arg_16b.x64.asm b/tests/snapshots/asm/variadic_struct_arg_16b.x64.asm index b0ad13809..8ff72c742 100644 --- a/tests/snapshots/asm/variadic_struct_arg_16b.x64.asm +++ b/tests/snapshots/asm/variadic_struct_arg_16b.x64.asm @@ -40,16 +40,9 @@ Disassembly of section .text: movq %r10, 0x10(%rax) xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %rdx - movslq -0xf0(%rbp), %rsi - cmpq %rsi, %rdx - jge jmp - movslq %ecx, %rcx - incq %rcx - jmp - leaq -0x18(%rbp), %rdx - movq %rdx, %r11 + leaq -0x18(%rbp), %rsi + movq %rsi, %r11 movl (%r11), %r10d cmpq $0x28, %r10 jae @@ -58,23 +51,27 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x10, 0x8(%r11) - movq %r10, %rdx - leaq -0x38(%rbp), %rsi + movq %r10, %rsi + leaq -0x38(%rbp), %rdi pushq %rax - movq (%rdx), %rax - movq %rax, (%rsi) - movq 0x8(%rdx), %rax - movq %rax, 0x8(%rsi) + movq (%rsi), %rax + movq %rax, (%rdi) + movq 0x8(%rsi), %rax + movq %rax, 0x8(%rdi) popq %rax - movq %rsi, %rdx - leaq -0x38(%rbp), %rdx - movq (%rdx), %rdx + movq %rdi, %rsi leaq -0x38(%rbp), %rsi - movq 0x8(%rsi), %rsi - shlq $0x1, %rsi - addq %rsi, %rdx - addq %rdx, %rax - jmp + movq (%rsi), %rsi + leaq -0x38(%rbp), %rdi + movq 0x8(%rdi), %rdi + shlq $0x1, %rdi + addq %rdi, %rsi + addq %rsi, %rax + leaq 0x1(%rdx), %rcx + movslq %ecx, %rdx + movslq -0xf0(%rbp), %rsi + cmpq %rsi, %rdx + jl leaq -0x18(%rbp), %rcx addq $0xf0, %rsp popq %rbp @@ -130,4 +127,3 @@ Disassembly of section .text: addq $0x50, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/variadic_struct_by_value_arg.aarch64.asm b/tests/snapshots/asm/variadic_struct_by_value_arg.aarch64.asm index 5f517247b..e1ce17eda 100644 --- a/tests/snapshots/asm/variadic_struct_by_value_arg.aarch64.asm +++ b/tests/snapshots/asm/variadic_struct_by_value_arg.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x10 ldur x1, [x29, #0x18] str x10, [sp, #-0x10]! @@ -96,18 +95,15 @@ Disassembly of section .text: ldrb w2, [x2] add x1, x1, x2 add x0, x1, x0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x19, [sp, #0x10] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -123,28 +119,22 @@ Disassembly of section .text: add x2, x2, mov x3, #0x63 // =99 bl - mov x20, x0 - cmp x20, #0x12f + mov x1, x0 + cmp x1, #0x12f b.eq adrp x0, add x0, x0, - mov x1, x20 bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret adrp x0, add x0, x0, - mov x1, x20 bl sxtw x0, w0 mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 ret diff --git a/tests/snapshots/asm/variadic_struct_by_value_arg.x64.asm b/tests/snapshots/asm/variadic_struct_by_value_arg.x64.asm index b2afeb844..6605a345a 100644 --- a/tests/snapshots/asm/variadic_struct_by_value_arg.x64.asm +++ b/tests/snapshots/asm/variadic_struct_by_value_arg.x64.asm @@ -83,8 +83,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp - movq %rbx, (%rsp) + subq $0x40, %rsp leaq -0x10(%rbp), %rax leaq , %rcx pushq %rdx @@ -99,27 +98,22 @@ Disassembly of section .text: movl $0x63, %ecx movb $0x0, %al callq - movq %rax, %rbx - cmpq $0x12f, %rbx # imm = 0x12F + movq %rax, %rsi + cmpq $0x12f, %rsi # imm = 0x12F je leaq , %rdi - movq %rbx, %rsi movb $0x0, %al callq movslq %eax, %rax movl $0x1, %eax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq leaq , %rdi - movq %rbx, %rsi movb $0x0, %al callq movslq %eax, %rax xorq %rax, %rax - movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x40, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/variadic_struct_return.aarch64.asm b/tests/snapshots/asm/variadic_struct_return.aarch64.asm index 149abb4d7..fbcc3608e 100644 --- a/tests/snapshots/asm/variadic_struct_return.aarch64.asm +++ b/tests/snapshots/asm/variadic_struct_return.aarch64.asm @@ -95,10 +95,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -123,18 +122,11 @@ Disassembly of section .text: str x2, [x0] sub x0, x29, #0x30 str x2, [x0, #0x8] - sxtw x0, w2 - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge b - sxtw x0, w2 - add x2, x0, #0x1 - b - sub x0, x29, #0x30 - ldr x1, [x0] - sub x3, x29, #0x20 - mov x17, x3 + sub x1, x29, #0x30 + ldr x3, [x1] + sub x4, x29, #0x20 + mov x17, x4 str x9, [sp, #-0x10]! ldrsw x16, [x17, #0x18] cmp x16, #0x0 @@ -151,11 +143,15 @@ Disassembly of section .text: add x9, x16, #0x8 str x9, [x17] ldr x9, [sp], #0x10 - mov x3, x16 - ldrsw x3, [x3] - add x1, x1, x3 - str x1, [x0] - b + mov x4, x16 + ldrsw x4, [x4] + add x3, x3, x4 + str x3, [x1] + add x2, x0, #0x1 + sxtw x0, w2 + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt sub x0, x29, #0x20 sub x0, x29, #0x30 ldursw x1, [x29, #0x10] @@ -164,17 +160,15 @@ Disassembly of section .text: mov x16, x0 ldr x1, [x16, #0x8] ldr x0, [x16] - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 add sp, sp, #0xc0 ret
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0xc0 - str x20, [sp] + sub sp, sp, #0xb0 mov x0, #0x0 // =0 adrp x1, add x1, x1, @@ -195,8 +189,7 @@ Disassembly of section .text: cmp x0, #0x9 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0xc0 + add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 @@ -219,16 +212,15 @@ Disassembly of section .text: sub x0, x29, #0x20 ldr x0, [x0] cmp x0, #0xb - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x20 ldr x0, [x0, #0x8] cmp x0, #0x16 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0xc0 + add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x4 // =4 @@ -260,13 +252,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - ldr x20, [sp] - add sp, sp, #0xc0 + add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0xc0 + add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/variadic_struct_return.x64.asm b/tests/snapshots/asm/variadic_struct_return.x64.asm index 947501f8b..41f8117bf 100644 --- a/tests/snapshots/asm/variadic_struct_return.x64.asm +++ b/tests/snapshots/asm/variadic_struct_return.x64.asm @@ -107,18 +107,11 @@ Disassembly of section .text: movq %rdx, (%rax) leaq -0x28(%rbp), %rax movq %rdx, 0x8(%rax) - movslq %edx, %rax - movslq -0xe0(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq %edx, %rax - leaq 0x1(%rax), %rdx jmp - leaq -0x28(%rbp), %rax - movq (%rax), %rcx - leaq -0x18(%rbp), %rsi - movq %rsi, %r11 + leaq -0x28(%rbp), %rcx + movq (%rcx), %rsi + leaq -0x18(%rbp), %rdi + movq %rdi, %r11 movl (%r11), %r10d cmpq $0x30, %r10 jae @@ -127,11 +120,15 @@ Disassembly of section .text: jmp movq 0x8(%r11), %r10 addq $0x8, 0x8(%r11) - movq %r10, %rsi - movslq (%rsi), %rsi - addq %rsi, %rcx - movq %rcx, (%rax) - jmp + movq %r10, %rdi + movslq (%rdi), %rdi + addq %rdi, %rsi + movq %rsi, (%rcx) + leaq 0x1(%rax), %rdx + movslq %edx, %rax + movslq -0xe0(%rbp), %rcx + cmpq %rcx, %rax + jl leaq -0x18(%rbp), %rax leaq -0x28(%rbp), %rax movslq -0xe0(%rbp), %rcx @@ -147,8 +144,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xc0, %rsp - movq %rbx, (%rsp) + subq $0xb0, %rsp xorq %rdi, %rdi leaq , %rsi movl $0x1, %edx @@ -168,8 +164,7 @@ Disassembly of section .text: cmpq $0x9, %rax je movl $0x1, %eax - movq (%rsp), %rbx - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq xorq %rdi, %rdi @@ -191,20 +186,19 @@ Disassembly of section .text: leaq -0x20(%rbp), %rax movq (%rax), %rax cmpq $0xb, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x20(%rbp), %rax movq 0x8(%rax), %rax cmpq $0x16, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x2, %eax - movq (%rsp), %rbx - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq movl $0x4, %edi @@ -240,15 +234,13 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - movq (%rsp), %rbx - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/variadic_union_struct_return.aarch64.asm b/tests/snapshots/asm/variadic_union_struct_return.aarch64.asm index e7c98fdca..ea530f9d3 100644 --- a/tests/snapshots/asm/variadic_union_struct_return.aarch64.asm +++ b/tests/snapshots/asm/variadic_union_struct_return.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x18 mov x16, x0 @@ -95,8 +94,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq ldrb w3, [x0] - b - mov x3, #0x0 // =0 add x0, x3, x1 str w0, [x2] sub x0, x29, #0x40 @@ -106,11 +103,12 @@ Disassembly of section .text: mov x16, x0 ldr x1, [x16, #0x8] ldr x0, [x16] - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret + mov x3, #0x0 // =0 + b
: stp x29, x30, [sp, #-0x10]! diff --git a/tests/snapshots/asm/variadic_union_struct_return.x64.asm b/tests/snapshots/asm/variadic_union_struct_return.x64.asm index 0d4128f36..0d28176ff 100644 --- a/tests/snapshots/asm/variadic_union_struct_return.x64.asm +++ b/tests/snapshots/asm/variadic_union_struct_return.x64.asm @@ -67,8 +67,6 @@ Disassembly of section .text: testq %rax, %rax je movsbq (%rax), %rsi - jmp - xorq %rsi, %rsi leaq (%rsi,%rcx), %rax movl %eax, (%rdx) leaq -0x38(%rbp), %rax @@ -81,6 +79,8 @@ Disassembly of section .text: addq $0xf0, %rsp popq %rbp retq + xorq %rsi, %rsi + jmp
: pushq %rbp diff --git a/tests/snapshots/asm/variadic_via_fnptr.aarch64.asm b/tests/snapshots/asm/variadic_via_fnptr.aarch64.asm index b85a9317e..129cbbea3 100644 --- a/tests/snapshots/asm/variadic_via_fnptr.aarch64.asm +++ b/tests/snapshots/asm/variadic_via_fnptr.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x19, [sp] + str x19, [sp, #-0x60]! + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 sub x0, x29, #0x20 add x1, x29, #0x10 mov x16, x0 @@ -122,9 +121,8 @@ Disassembly of section .text: add x0, x0, x1 add x0, x0, x2 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x50] + ldr x19, [sp], #0x60 add sp, sp, #0xc0 ret @@ -133,10 +131,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x19, [sp] + str x19, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x9 // =9 mov x1, #0x1 // =1 mov x2, #0x2 // =2 @@ -146,9 +143,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0xb // =11 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -167,9 +163,8 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0xc // =12 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret adrp x0, add x0, x0, @@ -188,12 +183,10 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0xd // =13 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x19, [sp], #0x20 ret diff --git a/tests/snapshots/asm/variadic_via_fnptr.x64.asm b/tests/snapshots/asm/variadic_via_fnptr.x64.asm index ec489f90d..36feb3554 100644 --- a/tests/snapshots/asm/variadic_via_fnptr.x64.asm +++ b/tests/snapshots/asm/variadic_via_fnptr.x64.asm @@ -94,7 +94,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp movl $0x9, %edi movl $0x1, %esi movl $0x2, %edx @@ -104,7 +103,6 @@ Disassembly of section .text: cmpq $0x23a3, %rax # imm = 0x23A3 je movl $0xb, %eax - addq $0x30, %rsp popq %rbp retq leaq -, %rax # @@ -119,7 +117,6 @@ Disassembly of section .text: cmpq $0x23a3, %rax # imm = 0x23A3 je movl $0xc, %eax - addq $0x30, %rsp popq %rbp retq leaq -, %rax # @@ -134,11 +131,8 @@ Disassembly of section .text: cmpq $0x23a3, %rax # imm = 0x23A3 je movl $0xd, %eax - addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/vfork_shared_stack_slot_reuse.aarch64.asm b/tests/snapshots/asm/vfork_shared_stack_slot_reuse.aarch64.asm new file mode 100644 index 000000000..f9fa4d98d --- /dev/null +++ b/tests/snapshots/asm/vfork_shared_stack_slot_reuse.aarch64.asm @@ -0,0 +1,529 @@ + +vfork_shared_stack_slot_reuse.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x430 // =1072 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0xc0 + ldr x16, [sp, #0xc0] + str x16, [sp] + ldr x16, [sp, #0xc8] + str x16, [sp, #0x10] + ldr x16, [sp, #0xd0] + str x16, [sp, #0x20] + ldr x16, [sp, #0xd8] + str x16, [sp, #0x30] + ldr x16, [sp, #0xe0] + str x16, [sp, #0x40] + ldr x16, [sp, #0xe8] + str x16, [sp, #0x50] + ldr x16, [sp, #0xf0] + str x16, [sp, #0x60] + ldr x16, [sp, #0xf8] + str x16, [sp, #0x70] + ldr x16, [sp, #0x100] + str x16, [sp, #0x80] + ldr x16, [sp, #0x108] + str x16, [sp, #0x90] + ldr x16, [sp, #0x110] + str x16, [sp, #0xa0] + ldr x16, [sp, #0x118] + str x16, [sp, #0xb0] + sub sp, sp, #0x80 + stp x29, x30, [sp, #-0x10]! + mov x29, sp + add x0, x0, x1 + add x0, x0, x2 + add x0, x0, x3 + add x0, x0, x4 + add x0, x0, x5 + add x0, x0, x6 + add x0, x0, x7 + ldursw x1, [x29, #0x90] + add x0, x0, x1 + ldursw x1, [x29, #0xa0] + add x0, x0, x1 + ldursw x1, [x29, #0xb0] + add x0, x0, x1 + ldursw x1, [x29, #0xc0] + add x0, x0, x1 + ldursw x1, [x29, #0xd0] + add x0, x0, x1 + ldursw x1, [x29, #0xe0] + add x0, x0, x1 + ldursw x1, [x29, #0xf0] + add x0, x0, x1 + add x16, x29, #0x100 + ldrsw x1, [x16] + add x0, x0, x1 + add x16, x29, #0x110 + ldrsw x1, [x16] + add x0, x0, x1 + add x16, x29, #0x120 + ldrsw x1, [x16] + add x0, x0, x1 + add x16, x29, #0x130 + ldrsw x1, [x16] + add x0, x0, x1 + add x16, x29, #0x140 + ldrsw x1, [x16] + add x0, x0, x1 + sxtw x0, w0 + mov x17, #0x7f // =127 + and x0, x0, x17 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x140 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x250 + stp x20, x21, [sp] + stp x22, x23, [sp, #0x10] + stp x24, x25, [sp, #0x20] + stp x26, x27, [sp, #0x30] + str x28, [sp, #0x40] + str x19, [sp, #0x50] + mov x1, #0x0 // =0 + b + adrp x2, + add x2, x2, + add x3, x0, #0x1 + str w3, [x2, x0, lsl #2] + add x1, x0, #0x1 + sxtw x0, w1 + cmp x0, #0x40 + b.lt + adrp x0, + add x0, x0, + ldrsw x1, [x0] + mov x17, #0x3 // =3 + mul x1, x1, x17 + sxtw x2, w1 + sxtw x20, w2 + ldrsw x1, [x0, #0x4] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x1 + sxtw x21, w1 + ldrsw x1, [x0, #0x8] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x2 + sxtw x22, w1 + ldrsw x1, [x0, #0xc] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x3 + sxtw x23, w1 + ldrsw x1, [x0, #0x10] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x4 + sxtw x24, w1 + ldrsw x1, [x0, #0x14] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x5 + sxtw x25, w1 + ldrsw x1, [x0, #0x18] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x6 + sxtw x26, w1 + ldrsw x1, [x0, #0x1c] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x7 + sxtw x27, w1 + ldrsw x1, [x0, #0x20] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x8 + sxtw x28, w1 + ldrsw x1, [x0, #0x24] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0x9 + sxtw x16, w1 + str x16, [sp, #0x78] + ldrsw x1, [x0, #0x28] + mov x17, #0x3 // =3 + mul x1, x1, x17 + add x1, x1, #0xa + sxtw x16, w1 + str x16, [sp, #0x70] + ldrsw x0, [x0, #0x2c] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0xb + sxtw x16, w0 + str x16, [sp, #0x68] + bl + sxtw x0, w0 + sxtw x1, w0 + cmp x1, #0x0 + b.ge + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x2 // =2 + ldr x19, [sp, #0x50] + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x250 + ldp x29, x30, [sp], #0x10 + ret + cmp x1, #0x0 + b.eq + mov x16, #0x0 // =0 + str x16, [sp, #0x60] + ldr x16, [sp, #0x60] + stur w16, [x29, #-0x78] + sxtw x0, w0 + sub x1, x29, #0x78 + ldr x2, [sp, #0x60] + bl + sxtw x0, w0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + mov x17, #0x3 // =3 + mul x0, x0, x17 + sxtw x1, w0 + sxtw x0, w1 + cmp x20, x0 + b.eq + mov x16, #0x1 // =1 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x4] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x1 + sxtw x0, w0 + cmp x21, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x2 // =2 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x8] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x2 + sxtw x0, w0 + cmp x22, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x4 // =4 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0xc] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x3 + sxtw x0, w0 + cmp x23, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x8 // =8 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x10] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x4 + sxtw x0, w0 + cmp x24, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x10 // =16 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x14] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x5 + sxtw x0, w0 + cmp x25, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x20 // =32 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x18] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x6 + sxtw x0, w0 + cmp x26, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x40 // =64 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x1c] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x7 + sxtw x0, w0 + cmp x27, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x80 // =128 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x20] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x8 + sxtw x0, w0 + cmp x28, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x100 // =256 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x24] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0x9 + sxtw x0, w0 + ldr x16, [sp, #0x78] + cmp x16, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x200 // =512 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x28] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0xa + sxtw x0, w0 + ldr x16, [sp, #0x70] + cmp x16, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x400 // =1024 + orr x16, x16, x17 + str x16, [sp, #0x60] + adrp x0, + add x0, x0, + ldrsw x0, [x0, #0x2c] + mov x17, #0x3 // =3 + mul x0, x0, x17 + add x0, x0, #0xb + sxtw x0, w0 + ldr x16, [sp, #0x68] + cmp x16, x0 + b.eq + ldr x16, [sp, #0x60] + mov x17, #0x800 // =2048 + orr x16, x16, x17 + str x16, [sp, #0x60] + ldr x16, [sp, #0x60] + sxtw x0, w16 + cbz x0, + adrp x0, + add x0, x0, + ldr x16, [sp, #0x60] + sxtw x1, w16 + bl + sxtw x0, w0 + mov x0, #0x1 // =1 + ldr x19, [sp, #0x50] + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x250 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x0 // =0 + ldr x19, [sp, #0x50] + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x250 + ldp x29, x30, [sp], #0x10 + ret + b + b + b + b + b + b + b + b + b + b + b + b + adrp x0, + add x0, x0, + ldrsw x1, [x0, #0x40] + mov x17, #0x5 // =5 + mul x1, x1, x17 + add x1, x1, #0x1 + ldrsw x2, [x0, #0x44] + mov x17, #0x5 // =5 + mul x2, x2, x17 + add x2, x2, #0x2 + ldrsw x3, [x0, #0x48] + mov x17, #0x5 // =5 + mul x3, x3, x17 + add x3, x3, #0x3 + ldrsw x4, [x0, #0x4c] + mov x17, #0x5 // =5 + mul x4, x4, x17 + add x4, x4, #0x4 + ldrsw x5, [x0, #0x50] + mov x17, #0x5 // =5 + mul x5, x5, x17 + add x5, x5, #0x5 + ldrsw x6, [x0, #0x54] + mov x17, #0x5 // =5 + mul x6, x6, x17 + add x6, x6, #0x6 + ldrsw x7, [x0, #0x58] + mov x17, #0x5 // =5 + mul x7, x7, x17 + add x7, x7, #0x7 + ldrsw x8, [x0, #0x5c] + mov x17, #0x5 // =5 + mul x8, x8, x17 + add x8, x8, #0x8 + ldrsw x9, [x0, #0x60] + mov x17, #0x5 // =5 + mul x9, x9, x17 + add x9, x9, #0x9 + sxtw x9, w9 + ldrsw x10, [x0, #0x64] + mov x17, #0x5 // =5 + mul x10, x10, x17 + add x10, x10, #0xa + sxtw x10, w10 + ldrsw x11, [x0, #0x68] + mov x17, #0x5 // =5 + mul x11, x11, x17 + add x11, x11, #0xb + sxtw x11, w11 + ldrsw x12, [x0, #0x6c] + mov x17, #0x5 // =5 + mul x12, x12, x17 + add x12, x12, #0xc + sxtw x12, w12 + ldrsw x13, [x0, #0x70] + mov x17, #0x5 // =5 + mul x13, x13, x17 + add x13, x13, #0xd + sxtw x13, w13 + ldrsw x14, [x0, #0x74] + mov x17, #0x5 // =5 + mul x14, x14, x17 + add x14, x14, #0xe + sxtw x14, w14 + ldrsw x15, [x0, #0x78] + mov x17, #0x5 // =5 + mul x15, x15, x17 + add x15, x15, #0xf + sxtw x15, w15 + ldrsw x20, [x0, #0x7c] + mov x17, #0x5 // =5 + mul x20, x20, x17 + add x20, x20, #0x10 + sxtw x20, w20 + ldrsw x21, [x0, #0x80] + mov x17, #0x5 // =5 + mul x21, x21, x17 + add x21, x21, #0x11 + sxtw x21, w21 + ldrsw x22, [x0, #0x84] + mov x17, #0x5 // =5 + mul x22, x22, x17 + add x22, x22, #0x12 + sxtw x22, w22 + ldrsw x23, [x0, #0x88] + mov x17, #0x5 // =5 + mul x23, x23, x17 + add x23, x23, #0x13 + sxtw x23, w23 + ldrsw x0, [x0, #0x8c] + mov x17, #0x5 // =5 + mul x0, x0, x17 + add x0, x0, #0x14 + sxtw x0, w0 + sub sp, sp, #0x60 + str x9, [sp] + str x10, [sp, #0x8] + str x11, [sp, #0x10] + str x12, [sp, #0x18] + str x13, [sp, #0x20] + str x14, [sp, #0x28] + str x15, [sp, #0x30] + str x20, [sp, #0x38] + str x21, [sp, #0x40] + str x22, [sp, #0x48] + str x23, [sp, #0x50] + str x0, [sp, #0x58] + mov x0, x1 + mov x1, x2 + mov x2, x3 + mov x3, x4 + mov x4, x5 + mov x5, x6 + mov x6, x7 + mov x7, x8 + bl + add sp, sp, #0x60 + bl + sxtw x0, w0 + mov x0, #0x3 // =3 + ldr x19, [sp, #0x50] + ldr x28, [sp, #0x40] + ldp x26, x27, [sp, #0x30] + ldp x24, x25, [sp, #0x20] + ldp x22, x23, [sp, #0x10] + ldp x20, x21, [sp] + add sp, sp, #0x250 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/vfork_shared_stack_slot_reuse.x64.asm b/tests/snapshots/asm/vfork_shared_stack_slot_reuse.x64.asm new file mode 100644 index 000000000..c7a38f946 --- /dev/null +++ b/tests/snapshots/asm/vfork_shared_stack_slot_reuse.x64.asm @@ -0,0 +1,540 @@ + +vfork_shared_stack_slot_reuse.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x140, %rsp # imm = 0x140 + movq 0x140(%rsp), %rax + movq %rax, 0x60(%rsp) + movq 0x148(%rsp), %rax + movq %rax, 0x70(%rsp) + movq 0x150(%rsp), %rax + movq %rax, 0x80(%rsp) + movq 0x158(%rsp), %rax + movq %rax, 0x90(%rsp) + movq 0x160(%rsp), %rax + movq %rax, 0xa0(%rsp) + movq 0x168(%rsp), %rax + movq %rax, 0xb0(%rsp) + movq 0x170(%rsp), %rax + movq %rax, 0xc0(%rsp) + movq 0x178(%rsp), %rax + movq %rax, 0xd0(%rsp) + movq 0x180(%rsp), %rax + movq %rax, 0xe0(%rsp) + movq 0x188(%rsp), %rax + movq %rax, 0xf0(%rsp) + movq 0x190(%rsp), %rax + movq %rax, 0x100(%rsp) + movq 0x198(%rsp), %rax + movq %rax, 0x110(%rsp) + movq 0x1a0(%rsp), %rax + movq %rax, 0x120(%rsp) + movq 0x1a8(%rsp), %rax + movq %rax, 0x130(%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + leaq (%rdi,%rsi), %rax + addq %rdx, %rax + addq %rcx, %rax + addq %r8, %rax + addq %r9, %rax + movslq 0x70(%rbp), %rcx + addq %rcx, %rax + movslq 0x80(%rbp), %rcx + addq %rcx, %rax + movslq 0x90(%rbp), %rcx + addq %rcx, %rax + movslq 0xa0(%rbp), %rcx + addq %rcx, %rax + movslq 0xb0(%rbp), %rcx + addq %rcx, %rax + movslq 0xc0(%rbp), %rcx + addq %rcx, %rax + movslq 0xd0(%rbp), %rcx + addq %rcx, %rax + movslq 0xe0(%rbp), %rcx + addq %rcx, %rax + movslq 0xf0(%rbp), %rcx + addq %rcx, %rax + movslq 0x100(%rbp), %rcx + addq %rcx, %rax + movslq 0x110(%rbp), %rcx + addq %rcx, %rax + movslq 0x120(%rbp), %rcx + addq %rcx, %rax + movslq 0x130(%rbp), %rcx + addq %rcx, %rax + movslq 0x140(%rbp), %rcx + addq %rcx, %rax + movslq %eax, %rax + andq $0x7f, %rax + popq %rbp + popq %r11 + addq $0x140, %rsp # imm = 0x140 + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x5b0, %rsp # imm = 0x5B0 + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %r15, 0x20(%rsp) + xorq %rcx, %rcx + jmp + leaq , %rdx + leaq 0x1(%rax), %rsi + movl %esi, (%rdx,%rax,4) + leaq 0x1(%rax), %rcx + movslq %ecx, %rax + cmpq $0x40, %rax + jl + leaq , %rax + movslq (%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + movslq %ecx, %rdx + movslq %edx, %rbx + movslq 0x4(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + incq %rcx + movslq %ecx, %r12 + movslq 0x8(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x2, %rcx + movslq %ecx, %r13 + movslq 0xc(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x3, %rcx + movslq %ecx, %r14 + movslq 0x10(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x4, %rcx + movslq %ecx, %r15 + movslq 0x14(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x5, %rcx + movslq %ecx, %r10 + movq %r10, 0x3d8(%rsp) + movslq 0x18(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x6, %rcx + movslq %ecx, %r10 + movq %r10, 0x3d0(%rsp) + movslq 0x1c(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x7, %rcx + movslq %ecx, %r10 + movq %r10, 0x3c8(%rsp) + movslq 0x20(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x8, %rcx + movslq %ecx, %r10 + movq %r10, 0x3c0(%rsp) + movslq 0x24(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0x9, %rcx + movslq %ecx, %r10 + movq %r10, 0x3b8(%rsp) + movslq 0x28(%rax), %rcx + leaq (%rcx,%rcx,2), %rcx + addq $0xa, %rcx + movslq %ecx, %r10 + movq %r10, 0x3b0(%rsp) + movslq 0x2c(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0xb, %rax + movslq %eax, %r10 + movq %r10, 0x3a8(%rsp) + xorl %eax, %eax + callq + movslq %eax, %rax + movslq %eax, %rcx + testq %rcx, %rcx + jge + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x2, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x5b0, %rsp # imm = 0x5B0 + popq %rbp + retq + testq %rcx, %rcx + je + xorq %r10, %r10 + movq %r10, 0x30(%rsp) + movq 0x30(%rsp), %r10 + movl %r10d, -0x78(%rbp) + movslq %eax, %rdi + leaq -0x78(%rbp), %rsi + movq 0x30(%rsp), %rdx + xorl %eax, %eax + callq + movslq %eax, %rax + leaq , %rax + movslq (%rax), %rax + leaq (%rax,%rax,2), %rax + movslq %eax, %rcx + movslq %ecx, %rax + cmpq %rax, %rbx + je + movl $0x1, %r10d + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x4(%rax), %rax + leaq (%rax,%rax,2), %rax + incq %rax + movslq %eax, %rax + cmpq %rax, %r12 + je + movq 0x30(%rsp), %r10 + orq $0x2, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x8(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x2, %rax + movslq %eax, %rax + cmpq %rax, %r13 + je + movq 0x30(%rsp), %r10 + orq $0x4, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0xc(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x3, %rax + movslq %eax, %rax + cmpq %rax, %r14 + je + movq 0x30(%rsp), %r10 + orq $0x8, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x10(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x4, %rax + movslq %eax, %rax + cmpq %rax, %r15 + je + movq 0x30(%rsp), %r10 + orq $0x10, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x14(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x5, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3d8(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x20, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x18(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x6, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3d0(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x40, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x1c(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x7, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3c8(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x80, %r10 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x20(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x8, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3c0(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x100, %r10 # imm = 0x100 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x24(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0x9, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3b8(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x200, %r10 # imm = 0x200 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x28(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0xa, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3b0(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x400, %r10 # imm = 0x400 + movq %r10, 0x30(%rsp) + leaq , %rax + movslq 0x2c(%rax), %rax + leaq (%rax,%rax,2), %rax + addq $0xb, %rax + movslq %eax, %rax + movq %rax, %r10 + movq 0x3a8(%rsp), %rax + cmpq %r10, %rax + je + movq 0x30(%rsp), %r10 + orq $0x800, %r10 # imm = 0x800 + movq %r10, 0x30(%rsp) + movq 0x30(%rsp), %rax + movslq %eax, %rax + testq %rax, %rax + je + leaq , %rdi + movq 0x30(%rsp), %rsi + movslq %esi, %rsi + movb $0x0, %al + callq + movslq %eax, %rax + movl $0x1, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x5b0, %rsp # imm = 0x5B0 + popq %rbp + retq + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x5b0, %rsp # imm = 0x5B0 + popq %rbp + retq + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + jmp + leaq , %rax + movslq 0x40(%rax), %rcx + leaq (%rcx,%rcx,4), %rcx + leaq 0x1(%rcx), %rdi + movslq 0x44(%rax), %rcx + leaq (%rcx,%rcx,4), %rcx + leaq 0x2(%rcx), %rsi + movslq 0x48(%rax), %rcx + leaq (%rcx,%rcx,4), %rcx + leaq 0x3(%rcx), %rdx + movslq 0x4c(%rax), %rcx + leaq (%rcx,%rcx,4), %rcx + addq $0x4, %rcx + movslq 0x50(%rax), %r8 + leaq (%r8,%r8,4), %r8 + addq $0x5, %r8 + movslq 0x54(%rax), %r9 + leaq (%r9,%r9,4), %r9 + addq $0x6, %r9 + movslq 0x58(%rax), %rbx + leaq (%rbx,%rbx,4), %rbx + addq $0x7, %rbx + movslq %ebx, %rbx + movslq 0x5c(%rax), %r12 + leaq (%r12,%r12,4), %r12 + addq $0x8, %r12 + movslq %r12d, %r12 + movslq 0x60(%rax), %r13 + leaq (%r13,%r13,4), %r13 + addq $0x9, %r13 + movslq %r13d, %r13 + movslq 0x64(%rax), %r14 + leaq (%r14,%r14,4), %r14 + addq $0xa, %r14 + movslq %r14d, %r14 + movslq 0x68(%rax), %r15 + leaq (%r15,%r15,4), %r15 + addq $0xb, %r15 + movslq %r15d, %r15 + movslq 0x6c(%rax), %r10 + movq %r10, 0x370(%rsp) + movq 0x370(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x368(%rsp) + movq 0x368(%rsp), %r10 + addq $0xc, %r10 + movq %r10, 0x350(%rsp) + movq 0x350(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x340(%rsp) + movslq 0x70(%rax), %r10 + movq %r10, 0x320(%rsp) + movq 0x320(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x318(%rsp) + movq 0x318(%rsp), %r10 + addq $0xd, %r10 + movq %r10, 0x300(%rsp) + movq 0x300(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x2f0(%rsp) + movslq 0x74(%rax), %r10 + movq %r10, 0x2d0(%rsp) + movq 0x2d0(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x2c8(%rsp) + movq 0x2c8(%rsp), %r10 + addq $0xe, %r10 + movq %r10, 0x2b0(%rsp) + movq 0x2b0(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x2a0(%rsp) + movslq 0x78(%rax), %r10 + movq %r10, 0x280(%rsp) + movq 0x280(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x278(%rsp) + movq 0x278(%rsp), %r10 + addq $0xf, %r10 + movq %r10, 0x260(%rsp) + movq 0x260(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x250(%rsp) + movslq 0x7c(%rax), %r10 + movq %r10, 0x230(%rsp) + movq 0x230(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x228(%rsp) + movq 0x228(%rsp), %r10 + addq $0x10, %r10 + movq %r10, 0x210(%rsp) + movq 0x210(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x200(%rsp) + movslq 0x80(%rax), %r10 + movq %r10, 0x1e0(%rsp) + movq 0x1e0(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x1d8(%rsp) + movq 0x1d8(%rsp), %r10 + addq $0x11, %r10 + movq %r10, 0x1c0(%rsp) + movq 0x1c0(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x1b0(%rsp) + movslq 0x84(%rax), %r10 + movq %r10, 0x190(%rsp) + movq 0x190(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x188(%rsp) + movq 0x188(%rsp), %r10 + addq $0x12, %r10 + movq %r10, 0x170(%rsp) + movq 0x170(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x160(%rsp) + movslq 0x88(%rax), %r10 + movq %r10, 0x140(%rsp) + movq 0x140(%rsp), %r10 + leaq (%r10,%r10,4), %r10 + movq %r10, 0x138(%rsp) + movq 0x138(%rsp), %r10 + addq $0x13, %r10 + movq %r10, 0x120(%rsp) + movq 0x120(%rsp), %r10 + movslq %r10d, %r10 + movq %r10, 0x110(%rsp) + movslq 0x8c(%rax), %rax + leaq (%rax,%rax,4), %rax + addq $0x14, %rax + movslq %eax, %rax + subq $0x70, %rsp + movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) + movq %r13, 0x10(%rsp) + movq %r14, 0x18(%rsp) + movq %r15, 0x20(%rsp) + movq 0x3b0(%rsp), %r10 + movq %r10, 0x28(%rsp) + movq 0x360(%rsp), %r10 + movq %r10, 0x30(%rsp) + movq 0x310(%rsp), %r10 + movq %r10, 0x38(%rsp) + movq 0x2c0(%rsp), %r10 + movq %r10, 0x40(%rsp) + movq 0x270(%rsp), %r10 + movq %r10, 0x48(%rsp) + movq 0x220(%rsp), %r10 + movq %r10, 0x50(%rsp) + movq 0x1d0(%rsp), %r10 + movq %r10, 0x58(%rsp) + movq 0x180(%rsp), %r10 + movq %r10, 0x60(%rsp) + movq %rax, 0x68(%rsp) + callq + addq $0x70, %rsp + movq %rax, %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + movl $0x3, %eax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + movq 0x10(%rsp), %r13 + movq 0x18(%rsp), %r14 + movq 0x20(%rsp), %r15 + addq $0x5b0, %rsp # imm = 0x5B0 + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/vla_basic_sum.aarch64.asm b/tests/snapshots/asm/vla_basic_sum.aarch64.asm index 03acfe6fb..159c7f7e1 100644 --- a/tests/snapshots/asm/vla_basic_sum.aarch64.asm +++ b/tests/snapshots/asm/vla_basic_sum.aarch64.asm @@ -35,30 +35,20 @@ Disassembly of section .text: stur x0, [x29, #-0x8] mov x0, #0x0 // =0 stur w0, [x29, #-0x18] - ldursw x0, [x29, #-0x18] - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x18] - add x0, x0, #0x1 - stur w0, [x29, #-0x18] b ldur x0, [x29, #-0x8] ldursw x1, [x29, #-0x18] lsl x2, x1, #1 str w2, [x0, x1, lsl #2] - b - mov x0, #0x0 // =0 - stur w0, [x29, #-0x20] - stur w0, [x29, #-0x28] - ldursw x0, [x29, #-0x28] + ldursw x0, [x29, #-0x18] + add x0, x0, #0x1 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x18] ldursw x1, [x29, #0x10] cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x28] - add x0, x0, #0x1 + b.lt + mov x0, #0x0 // =0 + stur w0, [x29, #-0x20] stur w0, [x29, #-0x28] b ldursw x0, [x29, #-0x20] @@ -67,7 +57,13 @@ Disassembly of section .text: ldrsw x1, [x1, x2, lsl #2] add x0, x0, x1 stur w0, [x29, #-0x20] - b + ldursw x0, [x29, #-0x28] + add x0, x0, #0x1 + stur w0, [x29, #-0x28] + ldursw x0, [x29, #-0x28] + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt ldursw x0, [x29, #-0x20] ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 diff --git a/tests/snapshots/asm/vla_basic_sum.x64.asm b/tests/snapshots/asm/vla_basic_sum.x64.asm index 50e084120..44b7aec41 100644 --- a/tests/snapshots/asm/vla_basic_sum.x64.asm +++ b/tests/snapshots/asm/vla_basic_sum.x64.asm @@ -38,31 +38,21 @@ Disassembly of section .text: movq %rax, -0x8(%rbp) xorq %rax, %rax movl %eax, -0x18(%rbp) - movslq -0x18(%rbp), %rax - movslq 0x10(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq -0x18(%rbp), %rax - incq %rax - movl %eax, -0x18(%rbp) jmp movq -0x8(%rbp), %rax movslq -0x18(%rbp), %rcx movq %rcx, %rdx shlq $0x1, %rdx movl %edx, (%rax,%rcx,4) - jmp - xorq %rax, %rax - movl %eax, -0x20(%rbp) - movl %eax, -0x28(%rbp) - movslq -0x28(%rbp), %rax + movslq -0x18(%rbp), %rax + incq %rax + movl %eax, -0x18(%rbp) + movslq -0x18(%rbp), %rax movslq 0x10(%rbp), %rcx cmpq %rcx, %rax - jge - jmp - movslq -0x28(%rbp), %rax - incq %rax + jl + xorq %rax, %rax + movl %eax, -0x20(%rbp) movl %eax, -0x28(%rbp) jmp movslq -0x20(%rbp), %rax @@ -71,7 +61,13 @@ Disassembly of section .text: movslq (%rcx,%rdx,4), %rcx addq %rcx, %rax movl %eax, -0x20(%rbp) - jmp + movslq -0x28(%rbp), %rax + incq %rax + movl %eax, -0x28(%rbp) + movslq -0x28(%rbp), %rax + movslq 0x10(%rbp), %rcx + cmpq %rcx, %rax + jl movslq -0x20(%rbp), %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp diff --git a/tests/snapshots/asm/vla_param_decay.aarch64.asm b/tests/snapshots/asm/vla_param_decay.aarch64.asm index ead0a86c0..c994c5b49 100644 --- a/tests/snapshots/asm/vla_param_decay.aarch64.asm +++ b/tests/snapshots/asm/vla_param_decay.aarch64.asm @@ -13,22 +13,18 @@ Disassembly of section .text: sxtw x0, w0 mov x4, #0x0 // =0 mov x3, x4 - sxtw x5, w4 - cmp x5, x0 - b.ge - b - sxtw x4, w4 - add x4, x4, #0x1 b - sxtw x5, w4 - lsl x5, x5, #2 - add x6, x1, x5 + lsl x6, x5, #2 + add x7, x1, x6 + ldrsw x7, [x7] + add x6, x2, x6 ldrsw x6, [x6] - add x5, x2, x5 - ldrsw x5, [x5] - mul x5, x6, x5 - add x3, x3, x5 - b + mul x6, x7, x6 + add x3, x3, x6 + add x4, x5, #0x1 + sxtw x5, w4 + cmp x5, x0 + b.lt sxtw x0, w3 ret @@ -61,9 +57,9 @@ Disassembly of section .text: cmp x0, #0x46 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/vla_param_decay.x64.asm b/tests/snapshots/asm/vla_param_decay.x64.asm index c722865c1..de076eab6 100644 --- a/tests/snapshots/asm/vla_param_decay.x64.asm +++ b/tests/snapshots/asm/vla_param_decay.x64.asm @@ -15,27 +15,26 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x10, %rsp movq %rbx, (%rsp) + movq %r12, 0x8(%rsp) movslq %edi, %rdi xorq %rcx, %rcx movq %rcx, %rax - movslq %ecx, %r8 - cmpq %rdi, %r8 - jge - jmp - movslq %ecx, %rcx - incq %rcx jmp - movslq %ecx, %r8 - shlq $0x2, %r8 - leaq (%rsi,%r8), %r9 + movq %r8, %r9 + shlq $0x2, %r9 + leaq (%rsi,%r9), %rbx + movslq (%rbx), %rbx + addq %rdx, %r9 movslq (%r9), %r9 - addq %rdx, %r8 - movslq (%r8), %r8 - imulq %r9, %r8 - addq %r8, %rax - jmp + imulq %rbx, %r9 + addq %r9, %rax + leaq 0x1(%r8), %rcx + movslq %ecx, %r8 + cmpq %rdi, %r8 + jl movslq %eax, %rax movq (%rsp), %rbx + movq 0x8(%rsp), %r12 addq $0x10, %rsp popq %rbp retq @@ -67,11 +66,11 @@ Disassembly of section .text: cmpq $0x46, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x40, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/vla_scope_reclaim_loop.aarch64.asm b/tests/snapshots/asm/vla_scope_reclaim_loop.aarch64.asm index 98eb3131f..a0b4db72f 100644 --- a/tests/snapshots/asm/vla_scope_reclaim_loop.aarch64.asm +++ b/tests/snapshots/asm/vla_scope_reclaim_loop.aarch64.asm @@ -20,15 +20,6 @@ Disassembly of section .text: mov x0, #0x0 // =0 stur x0, [x29, #-0x8] stur w0, [x29, #-0x10] - ldursw x0, [x29, #-0x10] - mov x17, #0x86a0 // =34464 - movk x17, #0x1, lsl #16 - cmp x0, x17 - b.ge - b - ldursw x0, [x29, #-0x10] - add x0, x0, #0x1 - stur w0, [x29, #-0x10] b sub x17, x29, #0x50 ldr x0, [x17] @@ -52,23 +43,16 @@ Disassembly of section .text: mov x0, #0x0 // =0 stur w0, [x29, #-0x30] b - mov x0, #0x0 // =0 - stur x0, [x29, #-0x40] - stur w0, [x29, #-0x48] - b - ldursw x0, [x29, #-0x30] - ldursw x1, [x29, #-0x18] - cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x30] - add x0, x0, #0x1 - stur w0, [x29, #-0x30] - b ldur x0, [x29, #-0x20] ldursw x1, [x29, #-0x30] str w1, [x0, x1, lsl #2] - b + ldursw x0, [x29, #-0x30] + add x0, x0, #0x1 + stur w0, [x29, #-0x30] + ldursw x0, [x29, #-0x30] + ldursw x1, [x29, #-0x18] + cmp x0, x1 + b.lt ldur x0, [x29, #-0x8] ldur x1, [x29, #-0x20] ldursw x2, [x29, #-0x10] @@ -80,15 +64,16 @@ Disassembly of section .text: ldur x0, [x29, #-0x38] sub x17, x29, #0x50 str x0, [x17] - b - ldursw x0, [x29, #-0x48] + ldursw x0, [x29, #-0x10] + add x0, x0, #0x1 + stur w0, [x29, #-0x10] + ldursw x0, [x29, #-0x10] mov x17, #0x86a0 // =34464 movk x17, #0x1, lsl #16 cmp x0, x17 - b.ge - b - ldursw x0, [x29, #-0x48] - add x0, x0, #0x1 + b.lt + mov x0, #0x0 // =0 + stur x0, [x29, #-0x40] stur w0, [x29, #-0x48] b ldur x0, [x29, #-0x40] @@ -97,7 +82,14 @@ Disassembly of section .text: and x1, x1, x17 add x0, x0, x1 stur x0, [x29, #-0x40] - b + ldursw x0, [x29, #-0x48] + add x0, x0, #0x1 + stur w0, [x29, #-0x48] + ldursw x0, [x29, #-0x48] + mov x17, #0x86a0 // =34464 + movk x17, #0x1, lsl #16 + cmp x0, x17 + b.lt ldur x0, [x29, #-0x8] ldur x1, [x29, #-0x40] cmp x0, x1 @@ -106,11 +98,6 @@ Disassembly of section .text: sub x17, x29, #0x2, lsl #12 // =0x2000 sub x17, x17, #0x58 str x0, [x17] - b - mov x0, #0x1 // =1 - sub x17, x29, #0x2, lsl #12 // =0x2000 - sub x17, x17, #0x58 - str x0, [x17] sub x16, x29, #0x2, lsl #12 // =0x2000 sub x16, x16, #0x58 ldr x0, [x16] @@ -119,3 +106,8 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret + mov x0, #0x1 // =1 + sub x17, x29, #0x2, lsl #12 // =0x2000 + sub x17, x17, #0x58 + str x0, [x17] + b diff --git a/tests/snapshots/asm/vla_scope_reclaim_loop.x64.asm b/tests/snapshots/asm/vla_scope_reclaim_loop.x64.asm index fff4edf10..38582837d 100644 --- a/tests/snapshots/asm/vla_scope_reclaim_loop.x64.asm +++ b/tests/snapshots/asm/vla_scope_reclaim_loop.x64.asm @@ -19,13 +19,6 @@ Disassembly of section .text: xorq %rax, %rax movq %rax, -0x8(%rbp) movl %eax, -0x10(%rbp) - movslq -0x10(%rbp), %rax - cmpq $0x186a0, %rax # imm = 0x186A0 - jge - jmp - movslq -0x10(%rbp), %rax - incq %rax - movl %eax, -0x10(%rbp) jmp movq -0x50(%rbp), %rax movq %rax, -0x38(%rbp) @@ -49,23 +42,16 @@ Disassembly of section .text: xorq %rax, %rax movl %eax, -0x30(%rbp) jmp - xorq %rax, %rax - movq %rax, -0x40(%rbp) - movl %eax, -0x48(%rbp) - jmp - movslq -0x30(%rbp), %rax - movslq -0x18(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq -0x30(%rbp), %rax - incq %rax - movl %eax, -0x30(%rbp) - jmp movq -0x20(%rbp), %rax movslq -0x30(%rbp), %rcx movl %ecx, (%rax,%rcx,4) - jmp + movslq -0x30(%rbp), %rax + incq %rax + movl %eax, -0x30(%rbp) + movslq -0x30(%rbp), %rax + movslq -0x18(%rbp), %rcx + cmpq %rcx, %rax + jl movq -0x8(%rbp), %rax movq -0x20(%rbp), %rcx movslq -0x10(%rbp), %rdx @@ -75,13 +61,14 @@ Disassembly of section .text: movq %rax, -0x8(%rbp) movq -0x38(%rbp), %rax movq %rax, -0x50(%rbp) - jmp - movslq -0x48(%rbp), %rax - cmpq $0x186a0, %rax # imm = 0x186A0 - jge - jmp - movslq -0x48(%rbp), %rax + movslq -0x10(%rbp), %rax incq %rax + movl %eax, -0x10(%rbp) + movslq -0x10(%rbp), %rax + cmpq $0x186a0, %rax # imm = 0x186A0 + jl + xorq %rax, %rax + movq %rax, -0x40(%rbp) movl %eax, -0x48(%rbp) jmp movq -0x40(%rbp), %rax @@ -89,18 +76,23 @@ Disassembly of section .text: andq $0x3f, %rcx addq %rcx, %rax movq %rax, -0x40(%rbp) - jmp + movslq -0x48(%rbp), %rax + incq %rax + movl %eax, -0x48(%rbp) + movslq -0x48(%rbp), %rax + cmpq $0x186a0, %rax # imm = 0x186A0 + jl movq -0x8(%rbp), %rax movq -0x40(%rbp), %rcx cmpq %rcx, %rax jne xorq %rax, %rax movq %rax, -0x2058(%rbp) - jmp - movl $0x1, %eax - movq %rax, -0x2058(%rbp) movq -0x2058(%rbp), %rax addq $0x2060, %rsp # imm = 0x2060 popq %rbp retq + movl $0x1, %eax + movq %rax, -0x2058(%rbp) + jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/vla_size_from_arg.aarch64.asm b/tests/snapshots/asm/vla_size_from_arg.aarch64.asm index 6a8b6c376..50c388931 100644 --- a/tests/snapshots/asm/vla_size_from_arg.aarch64.asm +++ b/tests/snapshots/asm/vla_size_from_arg.aarch64.asm @@ -34,14 +34,6 @@ Disassembly of section .text: stur x0, [x29, #-0x8] mov x0, #0x0 // =0 stur w0, [x29, #-0x18] - ldursw x0, [x29, #-0x18] - ldursw x1, [x29, #0x10] - cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x18] - add x0, x0, #0x1 - stur w0, [x29, #-0x18] b ldur x0, [x29, #-0x8] ldursw x1, [x29, #-0x18] @@ -50,17 +42,15 @@ Disassembly of section .text: mov x17, #0xff // =255 and x1, x1, x17 strb w1, [x0] - b - mov x0, #0x0 // =0 - stur w0, [x29, #-0x20] - stur w0, [x29, #-0x28] - ldursw x0, [x29, #-0x28] + ldursw x0, [x29, #-0x18] + add x0, x0, #0x1 + stur w0, [x29, #-0x18] + ldursw x0, [x29, #-0x18] ldursw x1, [x29, #0x10] cmp x0, x1 - b.ge - b - ldursw x0, [x29, #-0x28] - add x0, x0, #0x1 + b.lt + mov x0, #0x0 // =0 + stur w0, [x29, #-0x20] stur w0, [x29, #-0x28] b ldursw x0, [x29, #-0x20] @@ -70,7 +60,13 @@ Disassembly of section .text: ldrb w1, [x1] add x0, x0, x1 stur w0, [x29, #-0x20] - b + ldursw x0, [x29, #-0x28] + add x0, x0, #0x1 + stur w0, [x29, #-0x28] + ldursw x0, [x29, #-0x28] + ldursw x1, [x29, #0x10] + cmp x0, x1 + b.lt ldursw x0, [x29, #-0x20] ldr x19, [sp] add sp, sp, #0x2, lsl #12 // =0x2000 diff --git a/tests/snapshots/asm/vla_size_from_arg.x64.asm b/tests/snapshots/asm/vla_size_from_arg.x64.asm index da81a961e..b65d6485f 100644 --- a/tests/snapshots/asm/vla_size_from_arg.x64.asm +++ b/tests/snapshots/asm/vla_size_from_arg.x64.asm @@ -37,14 +37,6 @@ Disassembly of section .text: movq %rax, -0x8(%rbp) xorq %rax, %rax movl %eax, -0x18(%rbp) - movslq -0x18(%rbp), %rax - movslq 0x10(%rbp), %rcx - cmpq %rcx, %rax - jge - jmp - movslq -0x18(%rbp), %rax - incq %rax - movl %eax, -0x18(%rbp) jmp movq -0x8(%rbp), %rax movslq -0x18(%rbp), %rcx @@ -52,17 +44,15 @@ Disassembly of section .text: incq %rcx movslq %ecx, %rdx movb %dl, (%rax) - jmp - xorq %rax, %rax - movl %eax, -0x20(%rbp) - movl %eax, -0x28(%rbp) - movslq -0x28(%rbp), %rax + movslq -0x18(%rbp), %rax + incq %rax + movl %eax, -0x18(%rbp) + movslq -0x18(%rbp), %rax movslq 0x10(%rbp), %rcx cmpq %rcx, %rax - jge - jmp - movslq -0x28(%rbp), %rax - incq %rax + jl + xorq %rax, %rax + movl %eax, -0x20(%rbp) movl %eax, -0x28(%rbp) jmp movslq -0x20(%rbp), %rax @@ -72,7 +62,13 @@ Disassembly of section .text: movsbq (%rcx), %rcx addq %rcx, %rax movl %eax, -0x20(%rbp) - jmp + movslq -0x28(%rbp), %rax + incq %rax + movl %eax, -0x28(%rbp) + movslq -0x28(%rbp), %rax + movslq 0x10(%rbp), %rcx + cmpq %rcx, %rax + jl movslq -0x20(%rbp), %rax addq $0x2030, %rsp # imm = 0x2030 popq %rbp diff --git a/tests/snapshots/asm/void_function_produces_no_value.aarch64.asm b/tests/snapshots/asm/void_function_produces_no_value.aarch64.asm index 3949fcacb..8dfc9273d 100644 --- a/tests/snapshots/asm/void_function_produces_no_value.aarch64.asm +++ b/tests/snapshots/asm/void_function_produces_no_value.aarch64.asm @@ -10,12 +10,7 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : @@ -28,22 +23,18 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x0, add x0, x0, mov x1, #0x6 // =6 mov x2, #0x7 // =7 - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] + mov x0, x1 + mov x1, x2 blr x9 - add sp, sp, #0x20 sxtw x1, w0 cmp x1, #0x0 b.eq @@ -52,10 +43,9 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret adrp x20, add x20, x20, @@ -63,11 +53,8 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 movk x0, #0xffff, lsl #32 movk x0, #0xffff, lsl #48 - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x1, w0 cmp x1, #0x0 b.eq @@ -76,17 +63,13 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x2 // =2 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x0, #0x5 // =5 - str x0, [sp, #-0x10]! mov x9, x20 - ldr x0, [sp] blr x9 - add sp, sp, #0x10 sxtw x1, w0 cmp x1, #0x0 b.eq @@ -95,17 +78,15 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x3 // =3 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret mov x20, #0x0 // =0 mov x0, x20 bl mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/void_function_produces_no_value.x64.asm b/tests/snapshots/asm/void_function_produces_no_value.x64.asm index 5e31f9f4b..ff0c3a874 100644 --- a/tests/snapshots/asm/void_function_produces_no_value.x64.asm +++ b/tests/snapshots/asm/void_function_produces_no_value.x64.asm @@ -11,12 +11,7 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq : @@ -31,7 +26,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) leaq -, %rax # movl $0x6, %edi @@ -46,7 +41,7 @@ Disassembly of section .text: movslq %eax, %rax movl $0x1, %eax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq leaq -, %rbx # @@ -62,7 +57,7 @@ Disassembly of section .text: movslq %eax, %rax movl $0x2, %eax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x5, %edi @@ -77,7 +72,7 @@ Disassembly of section .text: movslq %eax, %rax movl $0x3, %eax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rbx, %rbx @@ -85,8 +80,7 @@ Disassembly of section .text: callq movq %rbx, %rax movq (%rsp), %rbx - addq $0x50, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/volatile_param_classes.aarch64.asm b/tests/snapshots/asm/volatile_param_classes.aarch64.asm index 904d6827a..39036f390 100644 --- a/tests/snapshots/asm/volatile_param_classes.aarch64.asm +++ b/tests/snapshots/asm/volatile_param_classes.aarch64.asm @@ -64,8 +64,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + sub sp, sp, #0x30 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -92,21 +91,19 @@ Disassembly of section .text: mov x0, #0x401e000000000000 // =4620130267728707584 fmov d17, x0 fcmp d0, d17 - cset x20, ne - cbnz x20, + cset x1, ne + cbnz x1, sub x0, x29, #0x10 ldr x0, [x0, #0x8] cmp x0, #0x3 - cset x20, ne - cbz x20, + cset x1, ne + cbz x1, mov x0, #0x1 // =1 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40a00000 // =1084227584 + fmov d0, x0 bl mov x0, #0x4004000000000000 // =4612811918334230528 fmov d17, x0 @@ -114,13 +111,11 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 + add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/volatile_param_classes.x64.asm b/tests/snapshots/asm/volatile_param_classes.x64.asm index 48e885f7b..a1684c328 100644 --- a/tests/snapshots/asm/volatile_param_classes.x64.asm +++ b/tests/snapshots/asm/volatile_param_classes.x64.asm @@ -65,8 +65,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) + subq $0x30, %rsp leaq -0x10(%rbp), %rax leaq , %rcx pushq %rdx @@ -92,28 +91,26 @@ Disassembly of section .text: movabsq $0x401e000000000000, %rax # imm = 0x401E000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 - setne %bl - movzbq %bl, %rbx + setne %cl + movzbq %cl, %rcx setp %r10b movzbq %r10b, %r10 - orq %r10, %rbx - testq %rbx, %rbx + orq %r10, %rcx + testq %rcx, %rcx jne leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax cmpq $0x3, %rax - setne %bl - movzbq %bl, %rbx - testq %rbx, %rbx + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x1, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 callq movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 movq %rax, %xmm15 @@ -126,15 +123,12 @@ Disassembly of section .text: testq %rax, %rax je movl $0x2, %eax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x30, %rsp popq %rbp retq jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/volatile_ptr_alias_loop.aarch64.asm b/tests/snapshots/asm/volatile_ptr_alias_loop.aarch64.asm index 64920fc27..4c0a57301 100644 --- a/tests/snapshots/asm/volatile_ptr_alias_loop.aarch64.asm +++ b/tests/snapshots/asm/volatile_ptr_alias_loop.aarch64.asm @@ -17,9 +17,7 @@ Disassembly of section .text: stur w1, [x29, #-0x8] sub x0, x29, #0x8 stur x0, [x29, #-0x10] - ldursw x0, [x29, #-0x8] - cmp x0, #0x3 - b.ge + b ldur x0, [x29, #-0x10] ldursw x2, [x29, #-0x8] add x2, x2, #0x1 @@ -27,21 +25,21 @@ Disassembly of section .text: add x1, x1, #0x1 sxtw x0, w1 cmp x0, #0xa - b.le - b + b.gt + ldursw x0, [x29, #-0x8] + cmp x0, #0x3 + b.lt sxtw x0, w1 cmp x0, #0x3 b.ne - b - mov x0, #0x1 // =1 + mov x1, #0x0 // =0 + mov x0, x1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - b - mov x1, #0x0 // =0 - b mov x1, #0x2 // =2 - mov x0, x1 + b + mov x0, #0x1 // =1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/volatile_ptr_alias_loop.x64.asm b/tests/snapshots/asm/volatile_ptr_alias_loop.x64.asm index 9380e032e..e9eea562e 100644 --- a/tests/snapshots/asm/volatile_ptr_alias_loop.x64.asm +++ b/tests/snapshots/asm/volatile_ptr_alias_loop.x64.asm @@ -18,9 +18,7 @@ Disassembly of section .text: movl %ecx, -0x8(%rbp) leaq -0x8(%rbp), %rax movq %rax, -0x10(%rbp) - movslq -0x8(%rbp), %rax - cmpq $0x3, %rax - jge + jmp movq -0x10(%rbp), %rax movslq -0x8(%rbp), %rdx incq %rdx @@ -28,21 +26,21 @@ Disassembly of section .text: incq %rcx movslq %ecx, %rax cmpq $0xa, %rax - jle - jmp + jg + movslq -0x8(%rbp), %rax + cmpq $0x3, %rax + jl movslq %ecx, %rax cmpq $0x3, %rax jne - jmp - movl $0x1, %eax + xorq %rcx, %rcx + movq %rcx, %rax addq $0x20, %rsp popq %rbp retq - jmp - xorq %rcx, %rcx - jmp movl $0x2, %ecx - movq %rcx, %rax + jmp + movl $0x1, %eax addq $0x20, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/volatile_setjmp_longjmp.aarch64.asm b/tests/snapshots/asm/volatile_setjmp_longjmp.aarch64.asm index 6f3173e21..ac0f8807b 100644 --- a/tests/snapshots/asm/volatile_setjmp_longjmp.aarch64.asm +++ b/tests/snapshots/asm/volatile_setjmp_longjmp.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x50]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x40] + add x29, sp, #0x40 mov x0, #0x1 // =1 stur w0, [x29, #-0x8] adrp x20, @@ -34,11 +33,10 @@ Disassembly of section .text: cmp x0, #0x2 b.ne mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 - ldr x20, [sp] + ldp x29, x30, [sp, #0x40] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x50 ret + mov x1, #0x1 // =1 + b diff --git a/tests/snapshots/asm/volatile_setjmp_longjmp.x64.asm b/tests/snapshots/asm/volatile_setjmp_longjmp.x64.asm index 15c66763e..366da6657 100644 --- a/tests/snapshots/asm/volatile_setjmp_longjmp.x64.asm +++ b/tests/snapshots/asm/volatile_setjmp_longjmp.x64.asm @@ -35,11 +35,11 @@ Disassembly of section .text: cmpq $0x2, %rax jne xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq (%rsp), %rbx movq %rcx, %rax addq $0x30, %rsp popq %rbp retq + movl $0x1, %ecx + jmp addb %al, (%rax) diff --git a/tests/snapshots/asm/volatile_unused_read.aarch64.asm b/tests/snapshots/asm/volatile_unused_read.aarch64.asm index bd6be7743..ab920442a 100644 --- a/tests/snapshots/asm/volatile_unused_read.aarch64.asm +++ b/tests/snapshots/asm/volatile_unused_read.aarch64.asm @@ -28,10 +28,10 @@ Disassembly of section .text: cset x1, eq cbz x1, mov x1, #0x0 // =0 - b - mov x1, #0x1 // =1 mov x0, x1 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret + mov x1, #0x1 // =1 + b b diff --git a/tests/snapshots/asm/volatile_unused_read.x64.asm b/tests/snapshots/asm/volatile_unused_read.x64.asm index c216c17cc..0bd354c19 100644 --- a/tests/snapshots/asm/volatile_unused_read.x64.asm +++ b/tests/snapshots/asm/volatile_unused_read.x64.asm @@ -32,10 +32,10 @@ Disassembly of section .text: testq %rcx, %rcx je xorq %rcx, %rcx - jmp - movl $0x1, %ecx movq %rcx, %rax addq $0x20, %rsp popq %rbp retq + movl $0x1, %ecx + jmp jmp diff --git a/tests/snapshots/asm/vsnprintf_underscore_alias.aarch64.asm b/tests/snapshots/asm/vsnprintf_underscore_alias.aarch64.asm index 9df97c400..ec1ee3460 100644 --- a/tests/snapshots/asm/vsnprintf_underscore_alias.aarch64.asm +++ b/tests/snapshots/asm/vsnprintf_underscore_alias.aarch64.asm @@ -27,10 +27,9 @@ Disassembly of section .text: str d5, [sp, #0x90] str d6, [sp, #0xa0] str d7, [sp, #0xb0] - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x60 - str x19, [sp] + str x19, [sp, #-0x70]! + stp x29, x30, [sp, #0x60] + add x29, sp, #0x60 sub x0, x29, #0x20 add x1, x29, #0x20 mov x16, x0 @@ -57,17 +56,15 @@ Disassembly of section .text: bl sub x1, x29, #0x20 sxtw x0, w0 - ldr x19, [sp] - add sp, sp, #0x60 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x60] + ldr x19, [sp], #0x70 add sp, sp, #0xc0 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x19, [sp] + str x19, [sp, #-0xa0]! + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 sub x0, x29, #0x40 mov x1, #0x40 // =64 adrp x2, @@ -89,13 +86,11 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x1 // =1 - ldr x19, [sp] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x90] + ldr x19, [sp], #0xa0 ret mov x0, #0x0 // =0 - ldr x19, [sp] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x90] + ldr x19, [sp], #0xa0 ret b diff --git a/tests/snapshots/asm/vtable_back_to_back.aarch64.asm b/tests/snapshots/asm/vtable_back_to_back.aarch64.asm index 4419dc45f..afa52241b 100644 --- a/tests/snapshots/asm/vtable_back_to_back.aarch64.asm +++ b/tests/snapshots/asm/vtable_back_to_back.aarch64.asm @@ -26,10 +26,9 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x19, [sp] + str x19, [sp, #-0x90]! + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -47,39 +46,29 @@ Disassembly of section .text: add x2, x2, mov x3, #0x2a // =42 mov x4, #0x8 // =8 - str x4, [sp, #-0x10]! - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x0, x1 + mov x1, x2 + mov x2, x3 + mov x3, x4 blr x9 - add sp, sp, #0x40 sub x0, x29, #0x10 ldr x0, [x0] ldr x0, [x0, #0x8] sub x1, x29, #0x10 sub x2, x29, #0x40 mov x3, #0x1 // =1 - str x3, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x0, x1 + mov x1, x2 + mov x2, x3 blr x9 - add sp, sp, #0x30 adrp x0, add x0, x0, ldursw x1, [x29, #-0x40] bl sxtw x0, w0 ldursw x0, [x29, #-0x40] - ldr x19, [sp] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x80] + ldr x19, [sp], #0x90 ret diff --git a/tests/snapshots/asm/vtable_back_to_back_4arg.aarch64.asm b/tests/snapshots/asm/vtable_back_to_back_4arg.aarch64.asm index f155ae62f..bc0185fe8 100644 --- a/tests/snapshots/asm/vtable_back_to_back_4arg.aarch64.asm +++ b/tests/snapshots/asm/vtable_back_to_back_4arg.aarch64.asm @@ -27,11 +27,10 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x80 - str x20, [sp] + str x20, [sp, #-0x90]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x80] + add x29, sp, #0x80 sub x0, x29, #0x10 adrp x1, add x1, x1, @@ -49,36 +48,25 @@ Disassembly of section .text: add x2, x2, mov x20, #0x1 // =1 mov x3, #0x64 // =100 - str x3, [sp, #-0x10]! - str x20, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] - ldr x3, [sp, #0x30] + mov x0, x1 + mov x1, x2 + mov x2, x20 blr x9 - add sp, sp, #0x40 sub x0, x29, #0x10 ldr x0, [x0] ldr x0, [x0, #0x8] sub x1, x29, #0x10 sub x2, x29, #0x40 - str x20, [sp, #-0x10]! - str x2, [sp, #-0x10]! - str x1, [sp, #-0x10]! mov x9, x0 - ldr x0, [sp] - ldr x1, [sp, #0x10] - ldr x2, [sp, #0x20] + mov x0, x1 + mov x1, x2 + mov x2, x20 blr x9 - add sp, sp, #0x30 ldursw x0, [x29, #-0x40] - ldr x20, [sp] + ldp x29, x30, [sp, #0x80] ldr x19, [sp, #0x10] - add sp, sp, #0x80 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x90 ret
: diff --git a/tests/snapshots/asm/warn_dead_store.aarch64.asm b/tests/snapshots/asm/warn_dead_store.aarch64.asm index d66b2dde1..caf435d37 100644 --- a/tests/snapshots/asm/warn_dead_store.aarch64.asm +++ b/tests/snapshots/asm/warn_dead_store.aarch64.asm @@ -14,14 +14,7 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - mov x0, #0x5 // =5 - add x0, x0, #0x1 - sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + mov x0, #0x6 // =6 ret : @@ -46,21 +39,15 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 - str x20, [sp] - mov x0, #0x1 // =1 - mov x1, #0x5 // =5 - add x1, x1, #0x1 - add x20, x0, x1 + str x20, [sp, #-0x20]! + stp x29, x30, [sp, #0x10] + add x29, sp, #0x10 mov x0, #0x1 // =1 bl - add x20, x20, x0 + add x20, x0, #0x7 bl add x0, x20, x0 sxtw x0, w0 - ldr x20, [sp] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 + ldp x29, x30, [sp, #0x10] + ldr x20, [sp], #0x20 ret diff --git a/tests/snapshots/asm/warn_dead_store.x64.asm b/tests/snapshots/asm/warn_dead_store.x64.asm index 490439151..3aaa022b8 100644 --- a/tests/snapshots/asm/warn_dead_store.x64.asm +++ b/tests/snapshots/asm/warn_dead_store.x64.asm @@ -15,14 +15,7 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movl $0x5, %eax - incq %rax - movslq %eax, %rax - addq $0x10, %rsp - popq %rbp + movl $0x6, %eax retq : @@ -52,13 +45,9 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x10, %rsp movq %rbx, (%rsp) - movl $0x1, %eax - movl $0x5, %ecx - incq %rcx - leaq (%rax,%rcx), %rbx movl $0x1, %edi callq - addq %rax, %rbx + leaq 0x7(%rax), %rbx callq addq %rbx, %rax movslq %eax, %rax @@ -66,5 +55,3 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/warn_unused_symbols.aarch64.asm b/tests/snapshots/asm/warn_unused_symbols.aarch64.asm index 61c9cc1bc..53ef0340d 100644 --- a/tests/snapshots/asm/warn_unused_symbols.aarch64.asm +++ b/tests/snapshots/asm/warn_unused_symbols.aarch64.asm @@ -10,23 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 lsl x0, x0, #1 sxtw x0, w0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - mov x0, #0x5 // =5 - add x0, x0, #0x1 - lsl x0, x0, #1 - sxtw x0, w0 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + mov x0, #0xc // =12 ret diff --git a/tests/snapshots/asm/warn_unused_symbols.x64.asm b/tests/snapshots/asm/warn_unused_symbols.x64.asm index f6be19c33..25f8ec081 100644 --- a/tests/snapshots/asm/warn_unused_symbols.x64.asm +++ b/tests/snapshots/asm/warn_unused_symbols.x64.asm @@ -11,26 +11,13 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movq %rdi, %rax shlq $0x1, %rax movslq %eax, %rax - addq $0x20, %rsp - popq %rbp retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x50, %rsp - movl $0x5, %eax - incq %rax - shlq $0x1, %rax - movslq %eax, %rax - addq $0x50, %rsp - popq %rbp + movl $0xc, %eax retq addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/wide_char_utf8.aarch64.asm b/tests/snapshots/asm/wide_char_utf8.aarch64.asm index 6151078ea..3a47e334a 100644 --- a/tests/snapshots/asm/wide_char_utf8.aarch64.asm +++ b/tests/snapshots/asm/wide_char_utf8.aarch64.asm @@ -10,24 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - mov x0, #0xe1 // =225 - mov x1, #0x20ac // =8364 - cmp x0, #0xe1 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x20ac // =8364 - cmp x1, x17 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrb w0, [x0] @@ -37,8 +19,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -49,8 +29,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -58,13 +36,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -97,13 +68,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x7 // =7 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x8 // =8 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -130,12 +94,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x9 // =9 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 ret b b @@ -143,3 +103,11 @@ Disassembly of section .text: b b b + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x8 // =8 + ret diff --git a/tests/snapshots/asm/wide_char_utf8.x64.asm b/tests/snapshots/asm/wide_char_utf8.x64.asm index c0535556a..0839612b1 100644 --- a/tests/snapshots/asm/wide_char_utf8.x64.asm +++ b/tests/snapshots/asm/wide_char_utf8.x64.asm @@ -11,23 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x50, %rsp - movl $0xe1, %eax - movl $0x20ac, %ecx # imm = 0x20AC - cmpq $0xe1, %rax - je - movl $0x1, %eax - addq $0x50, %rsp - popq %rbp - retq - cmpq $0x20ac, %rcx # imm = 0x20AC - je - movl $0x2, %eax - addq $0x50, %rsp - popq %rbp - retq leaq , %rax movsbq (%rax), %rax andq $0xff, %rax @@ -36,8 +19,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x50, %rsp - popq %rbp retq leaq , %rax movsbq 0x1(%rax), %rax @@ -47,21 +28,12 @@ Disassembly of section .text: testq %rax, %rax je movl $0x4, %eax - addq $0x50, %rsp - popq %rbp retq leaq , %rax movsbq 0x2(%rax), %rax testq %rax, %rax je movl $0x5, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x50, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -100,13 +72,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x7, %eax - addq $0x50, %rsp - popq %rbp - retq - jmp - movl $0x8, %eax - addq $0x50, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rcx @@ -142,12 +107,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x9, %eax - addq $0x50, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x50, %rsp - popq %rbp retq jmp jmp @@ -155,5 +116,12 @@ Disassembly of section .text: jmp jmp jmp + movl $0x1, %eax + retq + movl $0x2, %eax + retq + movl $0x6, %eax + retq + movl $0x8, %eax + retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/wide_string_literal_alignment.aarch64.asm b/tests/snapshots/asm/wide_string_literal_alignment.aarch64.asm index 3f846a0a1..2b3c705d2 100644 --- a/tests/snapshots/asm/wide_string_literal_alignment.aarch64.asm +++ b/tests/snapshots/asm/wide_string_literal_alignment.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 adrp x21, add x21, x21, mov x17, #0x3 // =3 @@ -23,11 +21,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x1, #0x56 // =86 mov x0, x21 @@ -35,11 +31,9 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x1, #0x7a // =122 mov x0, x21 @@ -47,16 +41,12 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x30 ret diff --git a/tests/snapshots/asm/wide_string_literal_alignment.x64.asm b/tests/snapshots/asm/wide_string_literal_alignment.x64.asm index 6263a5306..13d95eeb1 100644 --- a/tests/snapshots/asm/wide_string_literal_alignment.x64.asm +++ b/tests/snapshots/asm/wide_string_literal_alignment.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq , %r12 @@ -24,7 +24,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x56, %esi @@ -36,7 +36,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x7a, %esi @@ -48,12 +48,12 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/wide_string_literal_size.aarch64.asm b/tests/snapshots/asm/wide_string_literal_size.aarch64.asm index 10eb420bd..4ff39a362 100644 --- a/tests/snapshots/asm/wide_string_literal_size.aarch64.asm +++ b/tests/snapshots/asm/wide_string_literal_size.aarch64.asm @@ -10,81 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - mov x0, #0x4 // =4 - mov x17, #0x4 // =4 - eor x1, x0, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - lsl x1, x0, #1 - mov w1, w1 - mov x17, #0x8 // =8 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x3 // =3 - mul x1, x0, x17 - mov w1, w1 - mov x17, #0xc // =12 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x3 // =3 - mul x1, x0, x17 - mov w1, w1 - mov x17, #0xc // =12 - eor x1, x1, x17 - mov w1, w1 - cmp x1, #0x0 - b.eq - mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - mov x17, #0x6 // =6 - mul x0, x0, x17 - mov w0, w0 - mov x17, #0x18 // =24 - eor x0, x0, x17 - mov w0, w0 - cmp x0, #0x0 - b.eq - mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - b - mov x0, #0x8 // =8 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, ldrsw x1, [x0] @@ -103,12 +28,24 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x9 // =9 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b + mov x0, #0x1 // =1 + ret + mov x0, #0x2 // =2 + ret + mov x0, #0x3 // =3 + ret + mov x0, #0x4 // =4 + ret + mov x0, #0x5 // =5 + ret + mov x0, #0x6 // =6 + ret + mov x0, #0x7 // =7 + ret + mov x0, #0x8 // =8 + ret diff --git a/tests/snapshots/asm/wide_string_literal_size.x64.asm b/tests/snapshots/asm/wide_string_literal_size.x64.asm index ce2c452c2..e2036badb 100644 --- a/tests/snapshots/asm/wide_string_literal_size.x64.asm +++ b/tests/snapshots/asm/wide_string_literal_size.x64.asm @@ -11,75 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp - movl $0x4, %eax - movq %rax, %rcx - xorq $0x4, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je - movl $0x1, %eax - addq $0x20, %rsp - popq %rbp - retq - movq %rax, %rcx - shlq $0x1, %rcx - movl %ecx, %ecx - xorq $0x8, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je - movl $0x2, %eax - addq $0x20, %rsp - popq %rbp - retq - leaq (%rax,%rax,2), %rcx - movl %ecx, %ecx - xorq $0xc, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je - movl $0x3, %eax - addq $0x20, %rsp - popq %rbp - retq - leaq (%rax,%rax,2), %rcx - movl %ecx, %ecx - xorq $0xc, %rcx - movl %ecx, %ecx - testq %rcx, %rcx - je - movl $0x4, %eax - addq $0x20, %rsp - popq %rbp - retq - imulq $0x6, %rax, %rax - movl %eax, %eax - xorq $0x18, %rax - movl %eax, %eax - testq %rax, %rax - je - movl $0x5, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x6, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x7, %eax - addq $0x20, %rsp - popq %rbp - retq - jmp - movl $0x8, %eax - addq $0x20, %rsp - popq %rbp - retq leaq , %rax movslq (%rax), %rcx cmpq $0x61, %rcx @@ -104,14 +35,24 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x9, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp - addb %al, (%rax) - addb %al, 0x41(%rdx) + movl $0x1, %eax + retq + movl $0x2, %eax + retq + movl $0x3, %eax + retq + movl $0x4, %eax + retq + movl $0x5, %eax + retq + movl $0x6, %eax + retq + movl $0x7, %eax + retq + movl $0x8, %eax + retq diff --git a/tests/snapshots/asm/width_typedefs.aarch64.asm b/tests/snapshots/asm/width_typedefs.aarch64.asm index 60eacd947..18c63aa50 100644 --- a/tests/snapshots/asm/width_typedefs.aarch64.asm +++ b/tests/snapshots/asm/width_typedefs.aarch64.asm @@ -10,17 +10,13 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - b + mov x0, #0x0 // =0 + ret mov x0, #0x64 // =100 ret - b mov x0, #0x1 // =1 ret - b mov x0, #0x2 // =2 ret - b mov x0, #0x3 // =3 ret - mov x0, #0x0 // =0 - ret diff --git a/tests/snapshots/asm/width_typedefs.x64.asm b/tests/snapshots/asm/width_typedefs.x64.asm index b7ab1e625..d279c6ae5 100644 --- a/tests/snapshots/asm/width_typedefs.x64.asm +++ b/tests/snapshots/asm/width_typedefs.x64.asm @@ -11,17 +11,13 @@ Disassembly of section .text: ud2
: - jmp + xorq %rax, %rax + retq movl $0x64, %eax retq - jmp movl $0x1, %eax retq - jmp movl $0x2, %eax retq - jmp movl $0x3, %eax retq - xorq %rax, %rax - retq diff --git a/tests/snapshots/asm/wmem_functions.aarch64.asm b/tests/snapshots/asm/wmem_functions.aarch64.asm index 10625d527..b77eea3a6 100644 --- a/tests/snapshots/asm/wmem_functions.aarch64.asm +++ b/tests/snapshots/asm/wmem_functions.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x90 - str x20, [sp] - str x21, [sp, #0x8] + str x20, [sp, #-0xa0]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x90] + add x29, sp, #0x90 sub x0, x29, #0x18 adrp x1, add x1, x1, @@ -42,11 +40,9 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret sub x0, x29, #0x18 mov x1, #0x63 // =99 @@ -55,11 +51,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x2 // =2 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret sub x0, x29, #0x30 sub x1, x29, #0x18 @@ -74,11 +68,9 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret sub x0, x29, #0x30 mov x1, #0x7 // =7 @@ -88,34 +80,32 @@ Disassembly of section .text: ldrsw x0, [x0] cmp x0, #0x7 cset x0, ne - mov x20, #0x1 // =1 + mov x2, #0x1 // =1 cbnz x0, sub x0, x29, #0x30 ldrsw x0, [x0, #0x4] cmp x0, #0x7 cset x0, ne cmp x0, #0x0 - cset x20, ne - mov x21, #0x1 // =1 - cbnz x20, + cset x2, ne + mov x1, #0x1 // =1 + cbnz x2, sub x0, x29, #0x30 ldrsw x0, [x0, #0x8] cmp x0, #0x7 cset x0, ne cmp x0, #0x0 - cset x21, ne - cbnz x21, + cset x1, ne + cbnz x1, sub x0, x29, #0x30 ldrsw x0, [x0, #0xc] cmp x0, #0x28 - cset x21, ne - cbz x21, + cset x1, ne + cbz x1, mov x0, #0x4 // =4 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret sub x0, x29, #0x30 add x0, x0, #0x4 @@ -141,18 +131,14 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x5 // =5 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x90] ldr x19, [sp, #0x10] - add sp, sp, #0x90 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0xa0 ret b b diff --git a/tests/snapshots/asm/wmem_functions.x64.asm b/tests/snapshots/asm/wmem_functions.x64.asm index 809fb6114..09d6bfd6a 100644 --- a/tests/snapshots/asm/wmem_functions.x64.asm +++ b/tests/snapshots/asm/wmem_functions.x64.asm @@ -15,7 +15,6 @@ Disassembly of section .text: movq %rsp, %rbp subq $0x80, %rsp movq %rbx, (%rsp) - movq %r12, 0x8(%rsp) leaq -0x18(%rbp), %rax leaq , %rcx pushq %rdx @@ -43,7 +42,6 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq @@ -56,7 +54,6 @@ Disassembly of section .text: je movl $0x2, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq @@ -76,7 +73,6 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq @@ -90,7 +86,7 @@ Disassembly of section .text: cmpq $0x7, %rax setne %al movzbq %al, %rax - movl $0x1, %ebx + movl $0x1, %edx testq %rax, %rax jne leaq -0x30(%rbp), %rax @@ -99,10 +95,10 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %bl - movzbq %bl, %rbx - movl $0x1, %r12d - testq %rbx, %rbx + setne %dl + movzbq %dl, %rdx + movl $0x1, %ecx + testq %rdx, %rdx jne leaq -0x30(%rbp), %rax movslq 0x8(%rax), %rax @@ -110,20 +106,19 @@ Disassembly of section .text: setne %al movzbq %al, %rax testq %rax, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx jne leaq -0x30(%rbp), %rax movslq 0xc(%rax), %rax cmpq $0x28, %rax - setne %r12b - movzbq %r12b, %r12 - testq %r12, %r12 + setne %cl + movzbq %cl, %rcx + testq %rcx, %rcx je movl $0x4, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq @@ -160,13 +155,11 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - movq 0x8(%rsp), %r12 addq $0x80, %rsp popq %rbp retq diff --git a/tests/snapshots/asm/write_stdout.aarch64.asm b/tests/snapshots/asm/write_stdout.aarch64.asm index b164fa7de..9d72c1455 100644 --- a/tests/snapshots/asm/write_stdout.aarch64.asm +++ b/tests/snapshots/asm/write_stdout.aarch64.asm @@ -10,11 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] + str x20, [sp, #-0x30]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 mov x0, #0x4 // =4 bl mov x1, x0 @@ -31,8 +30,7 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] + ldp x29, x30, [sp, #0x20] ldr x19, [sp, #0x10] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 + ldr x20, [sp], #0x30 ret diff --git a/tests/snapshots/asm/write_stdout.x64.asm b/tests/snapshots/asm/write_stdout.x64.asm index 783dda23f..6c3d78d7a 100644 --- a/tests/snapshots/asm/write_stdout.x64.asm +++ b/tests/snapshots/asm/write_stdout.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x4, %edi xorl %eax, %eax @@ -34,7 +34,7 @@ Disassembly of section .text: movslq %eax, %rax movq %rbx, %rax movq (%rsp), %rbx - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/zero_length_array.aarch64.asm b/tests/snapshots/asm/zero_length_array.aarch64.asm index 08c040293..66cedb3cb 100644 --- a/tests/snapshots/asm/zero_length_array.aarch64.asm +++ b/tests/snapshots/asm/zero_length_array.aarch64.asm @@ -10,14 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 - b - mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 - ret adrp x0, add x0, x0, mov x1, #0x3 // =3 @@ -32,8 +24,6 @@ Disassembly of section .text: cmp x1, #0x3 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrb w1, [x0, #0x4] mov x17, #0xa // =10 @@ -60,8 +50,6 @@ Disassembly of section .text: cset x3, ne cbz x3, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret add x0, x0, #0x4 adrp x1, @@ -70,8 +58,6 @@ Disassembly of section .text: cmp x0, x1 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -96,8 +82,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrh w0, [x0, #0x4] mov x17, #0xff // =255 @@ -105,13 +89,11 @@ Disassembly of section .text: cmp x0, #0xab b.eq mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b b + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/zero_length_array.x64.asm b/tests/snapshots/asm/zero_length_array.x64.asm index 77e79361b..6a3f92425 100644 --- a/tests/snapshots/asm/zero_length_array.x64.asm +++ b/tests/snapshots/asm/zero_length_array.x64.asm @@ -11,14 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp - jmp - movl $0x1, %eax - addq $0x30, %rsp - popq %rbp - retq leaq , %rax movl $0x3, %ecx movl %ecx, (%rax) @@ -32,8 +24,6 @@ Disassembly of section .text: cmpq $0x3, %rcx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movzbq 0x4(%rax), %rcx xorq $0xa, %rcx @@ -64,8 +54,6 @@ Disassembly of section .text: testq %rsi, %rsi je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq addq $0x4, %rax leaq , %rcx @@ -73,8 +61,6 @@ Disassembly of section .text: cmpq %rcx, %rax je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movl $0x1, %ecx @@ -100,22 +86,18 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq movzwq 0x4(%rax), %rax andq $0xff, %rax cmpq $0xab, %rax je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp jmp - addb %al, 0x41(%rdx) + movl $0x1, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/zero_sign_extension_32bit.aarch64.asm b/tests/snapshots/asm/zero_sign_extension_32bit.aarch64.asm index 716ccde0b..83d33644b 100644 --- a/tests/snapshots/asm/zero_sign_extension_32bit.aarch64.asm +++ b/tests/snapshots/asm/zero_sign_extension_32bit.aarch64.asm @@ -10,12 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x50 - str x20, [sp] - str x21, [sp, #0x8] + stp x20, x21, [sp, #-0x60]! str x19, [sp, #0x10] + stp x29, x30, [sp, #0x50] + add x29, sp, #0x50 mov x20, x0 sxtw x20, w20 adrp x21, @@ -23,11 +21,9 @@ Disassembly of section .text: ldr x0, [x21, x20, lsl #3] cbz x0, ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret sub x0, x29, #0x18 mov x1, #0x0 // =0 @@ -52,59 +48,98 @@ Disassembly of section .text: ldr x0, [x0] str x0, [x21, x20, lsl #3] ldr x0, [x21, x20, lsl #3] - ldr x20, [sp] - ldr x21, [sp, #0x8] + ldp x29, x30, [sp, #0x50] ldr x19, [sp, #0x10] - add sp, sp, #0x50 - ldp x29, x30, [sp], #0x10 + ldp x20, x21, [sp], #0x60 ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x130 - str x20, [sp] - str x21, [sp, #0x8] - str x22, [sp, #0x10] - str x19, [sp, #0x20] - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 + stp x20, x21, [sp, #-0x30]! + str x19, [sp, #0x10] + stp x29, x30, [sp, #0x20] + add x29, sp, #0x20 + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x20, x0 + sxtw x0, w20 + mov x17, #0x1 // =1 + movk x17, #0x8000, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - cmp x20, x17 + cmp x0, x17 cset x0, eq cmp x0, #0x0 b.ne - b - b adrp x0, add x0, x0, - mov x21, #0x1 // =1 + mov x21, #0x28 // =40 str w21, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, - mov x2, #0x1b // =27 + mov x2, #0x5d // =93 mov x3, x21 bl sxtw x0, w0 - b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 + sxtw x0, w20 + mov x17, #0x1 // =1 + movk x17, #0x8000, lsl #16 movk x17, #0xffff, lsl #32 movk x17, #0xffff, lsl #48 - cmp x20, x17 + cmp x0, x17 cset x0, eq cmp x0, #0x0 b.ne + adrp x0, + add x0, x0, + mov x20, #0x29 // =41 + str w20, [x0] + mov x0, #0x2 // =2 + bl + adrp x1, + add x1, x1, + mov x2, #0x5e // =94 + mov x3, x20 + bl + sxtw x0, w0 + adrp x0, + add x0, x0, + ldrsw x0, [x0] + cmp x0, #0x0 + b.ne + adrp x0, + add x0, x0, + bl + sxtw x0, w0 + mov x0, #0x0 // =0 + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + adrp x0, + add x0, x0, + ldrsw x0, [x0] + ldp x29, x30, [sp, #0x20] + ldr x19, [sp, #0x10] + ldp x20, x21, [sp], #0x30 + ret + b + adrp x0, + add x0, x0, + mov x20, #0x1 // =1 + str w20, [x0] + mov x0, #0x2 // =2 + bl + adrp x1, + add x1, x1, + mov x2, #0x1b // =27 + mov x3, x20 + bl + sxtw x0, w0 b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 b adrp x0, add x0, x0, @@ -119,39 +154,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x3 // =3 - str w21, [x0] + mov x20, #0x3 // =3 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x20 // =32 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0xfff9 // =65529 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov w21, w20 b adrp x0, add x0, x0, @@ -166,66 +183,34 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w21 - mov x17, #0xfff9 // =65529 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w21 - sxtw x0, w0 b adrp x0, add x0, x0, - mov x22, #0xa // =10 - str w22, [x0] + mov x20, #0xa // =10 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x28 // =40 - mov x3, x22 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xfff9 // =65529 - movk x17, #0xffff, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov w0, w20 b adrp x0, add x0, x0, - mov x21, #0xb // =11 - str w21, [x0] + mov x20, #0xb // =11 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x2a // =42 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xfff9 // =65529 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x4240 // =16960 - movk x0, #0xf, lsl #16 - mov x1, #0xbb8 // =3000 - mul x0, x0, x1 - sxtw x20, w0 b adrp x0, add x0, x0, @@ -240,41 +225,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x5e00 // =24064 - movk x17, #0xb2d0, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x14 // =20 - str w21, [x0] + mov x20, #0x14 // =20 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x3a // =58 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0x5e00 // =24064 - movk x17, #0xb2d0, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x10000 // =65536 - mul x0, x0, x0 - mov w20, w0 b adrp x0, add x0, x0, @@ -289,34 +254,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov w0, w20 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x16 // =22 - str w21, [x0] + mov x20, #0x16 // =22 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x40 // =64 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov w0, w20 - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x80000000 // =2147483648 - lsr x0, x0, #1 b adrp x0, add x0, x0, @@ -331,16 +283,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x40000000 // =1073741824 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x5678 // =22136 - movk x0, #0x1234, lsl #16 - lsl x0, x0, #4 - mov w0, w0 b adrp x0, add x0, x0, @@ -355,16 +297,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x6780 // =26496 - movk x17, #0x2345, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x0, #0x0 // =0 - mvn x0, x0 - mov w0, w0 b adrp x0, add x0, x0, @@ -379,18 +311,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0xffff // =65535 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x20, x0 b adrp x0, add x0, x0, @@ -405,91 +325,23 @@ Disassembly of section .text: bl sxtw x0, w0 b - sxtw x0, w20 - mov x17, #0x1 // =1 - movk x17, #0x8000, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b b - adrp x0, - add x0, x0, - mov x21, #0x28 // =40 - str w21, [x0] - mov x0, #0x2 // =2 - bl - adrp x1, - add x1, x1, - mov x2, #0x5d // =93 - mov x3, x21 - bl - sxtw x0, w0 b - sxtw x0, w20 - mov x17, #0x1 // =1 - movk x17, #0x8000, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b - mov x20, #0xffff // =65535 - movk x20, #0xffff, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 - mov x21, #0x1 // =1 - add x0, x20, x21 - mov w0, w0 b adrp x0, add x0, x0, - mov x20, #0x29 // =41 + mov x20, #0x32 // =50 str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, - mov x2, #0x5e // =94 - mov x3, x20 - bl - sxtw x0, w0 - b - cmp x0, #0x0 - cset x0, eq - cmp x0, #0x0 - b.ne - b - sub x0, x20, x21 - mov w0, w0 - b - adrp x0, - add x0, x0, - mov x22, #0x32 // =50 - str w22, [x0] - mov x0, #0x2 // =2 - bl - adrp x1, - add x1, x1, mov x2, #0x68 // =104 - mov x3, x22 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0xfffe // =65534 - movk x17, #0xffff, lsl #16 - cmp x0, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0x5678 // =22136 - movk x20, #0x1234, lsl #16 b adrp x0, add x0, x0, @@ -504,13 +356,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x5678 // =22136 - movk x17, #0x1234, lsl #16 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b b adrp x0, add x0, x0, @@ -525,17 +370,6 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x5678 // =22136 - movk x17, #0x1234, lsl #16 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - mov x20, #0x6c00 // =27648 - movk x20, #0x88ca, lsl #16 - movk x20, #0xffff, lsl #32 - movk x20, #0xffff, lsl #48 b adrp x0, add x0, x0, @@ -550,43 +384,21 @@ Disassembly of section .text: bl sxtw x0, w0 b - mov x17, #0x6c00 // =27648 - movk x17, #0x88ca, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne b b adrp x0, add x0, x0, - mov x21, #0x3e // =62 - str w21, [x0] + mov x20, #0x3e // =62 + str w20, [x0] mov x0, #0x2 // =2 bl adrp x1, add x1, x1, mov x2, #0x7a // =122 - mov x3, x21 + mov x3, x20 bl sxtw x0, w0 b - mov x17, #0x6c00 // =27648 - movk x17, #0x88ca, lsl #16 - movk x17, #0xffff, lsl #32 - movk x17, #0xffff, lsl #48 - cmp x20, x17 - cset x0, eq - cmp x0, #0x0 - b.ne - b - adrp x0, - add x0, x0, - ldrsw x0, [x0] - cmp x0, #0x0 - b.ne b adrp x0, add x0, x0, @@ -601,25 +413,4 @@ Disassembly of section .text: bl sxtw x0, w0 b - adrp x0, - add x0, x0, - bl - sxtw x0, w0 - mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret - adrp x0, - add x0, x0, - ldrsw x0, [x0] - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x22, [sp, #0x10] - ldr x19, [sp, #0x20] - add sp, sp, #0x130 - ldp x29, x30, [sp], #0x10 - ret + b diff --git a/tests/snapshots/asm/zero_sign_extension_32bit.x64.asm b/tests/snapshots/asm/zero_sign_extension_32bit.x64.asm index c67f14dd6..c56a35b60 100644 --- a/tests/snapshots/asm/zero_sign_extension_32bit.x64.asm +++ b/tests/snapshots/asm/zero_sign_extension_32bit.x64.asm @@ -56,38 +56,85 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x120, %rsp # imm = 0x120 + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movq %r13, 0x10(%rsp) - movabsq $-0x1, %rbx - cmpq $-0x1, %rbx + leaq , %rdi + xorl %eax, %eax + callq + movslq %eax, %rax + movq %rax, %rbx + movslq %ebx, %rax + cmpq $-0x7fffffff, %rax # imm = 0x80000001 sete %al movzbq %al, %rax testq %rax, %rax jne - jmp - jmp leaq , %rax - movl $0x1, %r12d + movl $0x28, %r12d movl %r12d, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi - movl $0x1b, %edx + movl $0x5d, %edx movq %r12, %rcx movb $0x0, %al callq movslq %eax, %rax - jmp - cmpq $-0x1, %rbx + movslq %ebx, %rax + cmpq $-0x7fffffff, %rax # imm = 0x80000001 sete %al movzbq %al, %rax testq %rax, %rax jne + leaq , %rax + movl $0x29, %ebx + movl %ebx, (%rax) + movl $0x2, %edi + callq + movq %rax, %rdi + leaq , %rsi + movl $0x5e, %edx + movq %rbx, %rcx + movb $0x0, %al + callq + movslq %eax, %rax + leaq , %rax + movslq (%rax), %rax + testq %rax, %rax + jne + leaq , %rdi + movb $0x0, %al + callq + movslq %eax, %rax + xorq %rax, %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + leaq , %rax + movslq (%rax), %rax + movq (%rsp), %rbx + movq 0x8(%rsp), %r12 + addq $0x10, %rsp + popq %rbp + retq + jmp + leaq , %rax + movl $0x1, %ebx + movl %ebx, (%rax) + movl $0x2, %edi + callq + movq %rax, %rdi + leaq , %rsi + movl $0x1b, %edx + movq %rbx, %rcx + movb $0x0, %al + callq + movslq %eax, %rax jmp - movl $0xffffffff, %ebx # imm = 0xFFFFFFFF jmp leaq , %rax movl $0x2, %ebx @@ -102,38 +149,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rbx, %rax - cmpq %r11, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x3, %r12d - movl %r12d, (%rax) + movl $0x3, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x20, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - movq %rbx, %rax - cmpq %r11, %rbx - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x7, %rbx - movl %ebx, %r12d jmp leaq , %rax movl $0x4, %ebx @@ -148,62 +178,34 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %r12d, %eax - movl $0xfffffff9, %r11d # imm = 0xFFFFFFF9 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %r12d, %eax - movslq %eax, %rax jmp leaq , %rax - movl $0xa, %r13d - movl %r13d, (%rax) + movl $0xa, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x28, %edx - movq %r13, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x7, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl %ebx, %eax jmp leaq , %rax - movl $0xb, %r12d - movl %r12d, (%rax) + movl $0xb, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x2a, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl $0xfffffff9, %r11d # imm = 0xFFFFFFF9 - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0xf4240, %eax # imm = 0xF4240 - movl $0xbb8, %ecx # imm = 0xBB8 - imulq %rcx, %rax - movslq %eax, %rbx jmp leaq , %rax movl $0xc, %ebx @@ -218,35 +220,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x4d2fa200, %rbx # imm = 0xB2D05E00 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x14, %r12d - movl %r12d, (%rax) + movl $0x14, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x3a, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x4d2fa200, %rbx # imm = 0xB2D05E00 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x10000, %eax # imm = 0x10000 - imulq %rax, %rax - movl %eax, %ebx jmp leaq , %rax movl $0x15, %ebx @@ -261,36 +249,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl %ebx, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x16, %r12d - movl %r12d, (%rax) + movl $0x16, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x40, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl %ebx, %eax - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x80000000, %eax # imm = 0x80000000 - shrq $0x1, %rax jmp leaq , %rax movl $0x17, %ebx @@ -305,15 +278,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x40000000, %rax # imm = 0x40000000 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x12345678, %eax # imm = 0x12345678 - shlq $0x4, %rax - movl %eax, %eax jmp leaq , %rax movl $0x1e, %ebx @@ -328,15 +292,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x23456780, %rax # imm = 0x23456780 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - xorq %rax, %rax - xorq $-0x1, %rax - movl %eax, %eax jmp leaq , %rax movl $0x1f, %ebx @@ -351,18 +306,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movl $0xffffffff, %r11d # imm = 0xFFFFFFFF - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq , %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - movq %rax, %rbx jmp leaq , %rax movl $0x20, %ebx @@ -377,83 +320,23 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - movslq %ebx, %rax - cmpq $-0x7fffffff, %rax # imm = 0x80000001 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp - leaq , %rax - movl $0x28, %r12d - movl %r12d, (%rax) - movl $0x2, %edi - callq - movq %rax, %rdi - leaq , %rsi - movl $0x5d, %edx - movq %r12, %rcx - movb $0x0, %al - callq - movslq %eax, %rax jmp - movslq %ebx, %rax - cmpq $-0x7fffffff, %rax # imm = 0x80000001 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x1, %rbx - movl $0x1, %r12d - leaq (%rbx,%r12), %rax - movl %eax, %eax jmp leaq , %rax - movl $0x29, %ebx + movl $0x32, %ebx movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi - movl $0x5e, %edx - movq %rbx, %rcx - movb $0x0, %al - callq - movslq %eax, %rax - jmp - testq %rax, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movq %rbx, %rax - subq %r12, %rax - movl %eax, %eax - jmp - leaq , %rax - movl $0x32, %r13d - movl %r13d, (%rax) - movl $0x2, %edi - callq - movq %rax, %rdi - leaq , %rsi movl $0x68, %edx - movq %r13, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - movl $0xfffffffe, %r11d # imm = 0xFFFFFFFE - cmpq %r11, %rax - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movl $0x12345678, %ebx # imm = 0x12345678 jmp leaq , %rax movl $0x33, %ebx @@ -468,12 +351,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x12345678, %rbx # imm = 0x12345678 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp jmp leaq , %rax movl $0x3c, %r12d @@ -488,13 +365,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $0x12345678, %rbx # imm = 0x12345678 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - movabsq $-0x77359400, %rbx # imm = 0x88CA6C00 jmp leaq , %rax movl $0x3d, %ebx @@ -509,36 +379,21 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - cmpq $-0x77359400, %rbx # imm = 0x88CA6C00 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne jmp jmp leaq , %rax - movl $0x3e, %r12d - movl %r12d, (%rax) + movl $0x3e, %ebx + movl %ebx, (%rax) movl $0x2, %edi callq movq %rax, %rdi leaq , %rsi movl $0x7a, %edx - movq %r12, %rcx + movq %rbx, %rcx movb $0x0, %al callq movslq %eax, %rax jmp - cmpq $-0x77359400, %rbx # imm = 0x88CA6C00 - sete %al - movzbq %al, %rax - testq %rax, %rax - jne - jmp - leaq , %rax - movslq (%rax), %rax - testq %rax, %rax - jne jmp leaq , %rax movl $0x3f, %ebx @@ -553,23 +408,6 @@ Disassembly of section .text: callq movslq %eax, %rax jmp - leaq , %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rax, %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 - popq %rbp - retq - leaq , %rax - movslq (%rax), %rax - movq (%rsp), %rbx - movq 0x8(%rsp), %r12 - movq 0x10(%rsp), %r13 - addq $0x120, %rsp # imm = 0x120 - popq %rbp - retq + jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/ssa/aapcs64_variadic_host_abi.ssa b/tests/snapshots/ssa/aapcs64_variadic_host_abi.ssa index 2ff233a7c..a96998484 100644 --- a/tests/snapshots/ssa/aapcs64_variadic_host_abi.ssa +++ b/tests/snapshots/ssa/aapcs64_variadic_host_abi.ssa @@ -10,29 +10,29 @@ fn ent_pc=0 n_params=1 variadic=true locals=5 v4 LocalAddr(2) -> x1 v5 Intrinsic { kind=4, args=[v3, v4] } -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 + v15 Extend { value=v8, kind=I32 } -> x6 + v16 LocalAddr(-3) -> x6 + v17 Imm(4) -> x7 + v18 Intrinsic { kind=5, args=[v16, v17] } -> x6 + v19 Load { addr=v18, disp=0, kind=I32 } -> x6 + v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 + v21 Imm(0) -> x6 + v22 Extend { value=v20, kind=I32 } -> x6 + terminator Jmp(b2) (exit_acc=v22) + block 2 start_pc=0 + v12 Extend { value=v7, kind=I32 } -> x2 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x2 + v14 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 v7 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x2 v8 Phi { incoming=[b0:v1, b2:v20], kind=I64 } -> x0 v9 Extend { value=v7, kind=I32 } -> x1 v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x1 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x2 - v14 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v13) - block 3 start_pc=0 - v15 Extend { value=v8, kind=I32 } -> x1 - v16 LocalAddr(-3) -> x1 - v17 Imm(4) -> x6 - v18 Intrinsic { kind=5, args=[v16, v17] } -> x1 - v19 Load { addr=v18, disp=0, kind=I32 } -> x1 - v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 - v21 Imm(0) -> x1 - v22 Extend { value=v20, kind=I32 } -> x1 - terminator Jmp(b2) (exit_acc=v22) + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v23 LocalAddr(-3) -> x1 v24 Intrinsic { kind=6, args=[v23] } -> x1 @@ -51,29 +51,29 @@ fn ent_pc=1 n_params=1 variadic=true locals=5 v5 LocalAddr(2) -> x1 v6 Intrinsic { kind=4, args=[v4, v5] } -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v8 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x2 - v9 Phi { incoming=[b0:v2, b2:v21], kind=F64 } -> d0 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 LoadLocal { off=2, kind=I32 } -> x1 - v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) - block 2 start_pc=0 - v13 Extend { value=v8, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 v16 LoadLocal { off=-4, kind=F64 } -> d1 - v17 LocalAddr(-3) -> x0 - v18 Imm(65544) -> x1 - v19 Intrinsic { kind=5, args=[v17, v18] } -> x0 + v17 LocalAddr(-3) -> x1 + v18 Imm(65544) -> x6 + v19 Intrinsic { kind=5, args=[v17, v18] } -> x1 v20 Load { addr=v19, disp=0, kind=F64 } -> d1 v21 Binop { op=fadd, lhs=v9, rhs=v20 } -> d0 - v22 Imm(0) -> x0 + v22 Imm(0) -> x1 v23 LoadLocal { off=-4, kind=F64 } -> d1 terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x2 + v9 Phi { incoming=[b0:v2, b2:v21], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x1 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x1 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v24 LocalAddr(-3) -> x0 v25 Intrinsic { kind=6, args=[v24] } -> x0 @@ -92,52 +92,52 @@ fn ent_pc=2 n_params=1 variadic=true locals=5 v5 LocalAddr(2) -> x1 v6 Intrinsic { kind=4, args=[v4, v5] } -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b6) (exit_acc=v1) block 1 start_pc=0 - v8 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x2 - v9 Phi { incoming=[b0:v2, b2:v29], kind=F64 } -> d0 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 LoadLocal { off=2, kind=I32 } -> x1 - v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v16 Extend { value=v8, kind=I32 } -> x1 + v17 BinopI { op=and, lhs=v10, rhs_imm=1 } -> x1 + terminator Bz { cond=v17, target=b4, fall=b2 } (exit_acc=v17) block 2 start_pc=0 - v13 Extend { value=v8, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 - v16 Extend { value=v8, kind=I32 } -> x0 - v17 BinopI { op=and, lhs=v16, rhs_imm=1 } -> x0 - terminator Bz { cond=v17, target=b7, fall=b5 } (exit_acc=v17) - block 4 start_pc=0 - v18 LocalAddr(-3) -> x0 - v19 Intrinsic { kind=6, args=[v18] } -> x0 - v20 LoadLocal { off=-4, kind=F64 } -> d1 - terminator Return(v9) (exit_acc=v9) - block 5 start_pc=0 v21 LoadLocal { off=-4, kind=F64 } -> d1 - v22 LocalAddr(-3) -> x0 - v23 Imm(65544) -> x1 - v24 Intrinsic { kind=5, args=[v22, v23] } -> x0 + v22 LocalAddr(-3) -> x1 + v23 Imm(65544) -> x6 + v24 Intrinsic { kind=5, args=[v22, v23] } -> x1 v25 Load { addr=v24, disp=0, kind=F64 } -> d1 v26 Binop { op=fadd, lhs=v9, rhs=v25 } -> d0 - v27 Imm(0) -> x0 + v27 Imm(0) -> x1 v28 LoadLocal { off=-4, kind=F64 } -> d1 - terminator Jmp(b6) (exit_acc=v26) - block 6 start_pc=0 - v29 Phi { incoming=[b5:v26, b7:v36], kind=F64 } -> d0 - terminator Jmp(b2) - block 7 start_pc=0 + terminator Jmp(b3) (exit_acc=v26) + block 3 start_pc=0 + v29 Phi { incoming=[b2:v26, b4:v36], kind=F64 } -> d0 + terminator Jmp(b5) + block 4 start_pc=0 v30 LoadLocal { off=-4, kind=F64 } -> d1 - v31 LocalAddr(-3) -> x0 - v32 Imm(4) -> x1 - v33 Intrinsic { kind=5, args=[v31, v32] } -> x0 - v34 Load { addr=v33, disp=0, kind=I32 } -> x0 + v31 LocalAddr(-3) -> x1 + v32 Imm(4) -> x6 + v33 Intrinsic { kind=5, args=[v31, v32] } -> x1 + v34 Load { addr=v33, disp=0, kind=I32 } -> x1 v35 FpCast { kind=IntToFp, value=v34 } -> d1 v36 Binop { op=fadd, lhs=v9, rhs=v35 } -> d0 - v37 Imm(0) -> x0 + v37 Imm(0) -> x1 v38 LoadLocal { off=-4, kind=F64 } -> d1 - terminator Jmp(b6) (exit_acc=v36) + terminator Jmp(b3) (exit_acc=v36) + block 5 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 + v15 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v14) + block 6 start_pc=0 + v8 Phi { incoming=[b0:v1, b5:v14], kind=I64 } -> x2 + v9 Phi { incoming=[b0:v2, b5:v29], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x1 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x1 + terminator Bnz { cond=v12, target=b1, fall=b7 } (exit_acc=v12) + block 7 start_pc=0 + v18 LocalAddr(-3) -> x0 + v19 Intrinsic { kind=6, args=[v18] } -> x0 + v20 LoadLocal { off=-4, kind=F64 } -> d1 + terminator Return(v9) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=icopy fn ent_pc=3 n_params=1 variadic=true locals=8 @@ -153,55 +153,55 @@ fn ent_pc=3 n_params=1 variadic=true locals=8 v7 LocalAddr(-3) -> x1 v8 Intrinsic { kind=7, args=[v6, v7] } -> x0 v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 + v18 Extend { value=v11, kind=I32 } -> x6 + v19 LocalAddr(-3) -> x6 + v20 Imm(4) -> x7 + v21 Intrinsic { kind=5, args=[v19, v20] } -> x6 + v22 Load { addr=v21, disp=0, kind=I32 } -> x6 + v23 Binop { op=add, lhs=v11, rhs=v22 } -> x0 + v24 Imm(0) -> x6 + v25 Extend { value=v23, kind=I32 } -> x6 + terminator Jmp(b2) (exit_acc=v25) + block 2 start_pc=0 + v15 Extend { value=v10, kind=I32 } -> x2 + v16 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x2 + v17 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v16) + block 3 start_pc=0 v10 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x2 v11 Phi { incoming=[b0:v1, b2:v23], kind=I64 } -> x0 v12 Extend { value=v10, kind=I32 } -> x1 v13 LoadLocal { off=2, kind=I32 } -> x6 - v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x1 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 2 start_pc=0 - v15 Extend { value=v10, kind=I32 } -> x1 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x2 - v17 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v16) - block 3 start_pc=0 - v18 Extend { value=v11, kind=I32 } -> x1 - v19 LocalAddr(-3) -> x1 - v20 Imm(4) -> x6 - v21 Intrinsic { kind=5, args=[v19, v20] } -> x1 - v22 Load { addr=v21, disp=0, kind=I32 } -> x1 - v23 Binop { op=add, lhs=v11, rhs=v22 } -> x0 - v24 Imm(0) -> x1 - v25 Extend { value=v23, kind=I32 } -> x1 - terminator Jmp(b2) (exit_acc=v25) + v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x6 + terminator Bnz { cond=v14, target=b1, fall=b4 } (exit_acc=v14) block 4 start_pc=0 v26 Imm(0) -> x2 v27 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v26) + terminator Jmp(b7) (exit_acc=v26) block 5 start_pc=0 + v36 Extend { value=v29, kind=I32 } -> x6 + v37 LocalAddr(-6) -> x6 + v38 Imm(4) -> x7 + v39 Intrinsic { kind=5, args=[v37, v38] } -> x6 + v40 Load { addr=v39, disp=0, kind=I32 } -> x6 + v41 Binop { op=add, lhs=v29, rhs=v40 } -> x0 + v42 Imm(0) -> x6 + v43 Extend { value=v41, kind=I32 } -> x6 + terminator Jmp(b6) (exit_acc=v43) + block 6 start_pc=0 + v33 Extend { value=v28, kind=I32 } -> x2 + v34 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x2 + v35 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v34) + block 7 start_pc=0 v28 Phi { incoming=[b4:v26, b6:v34], kind=I64 } -> x2 v29 Phi { incoming=[b4:v11, b6:v41], kind=I64 } -> x0 v30 Extend { value=v28, kind=I32 } -> x1 v31 LoadLocal { off=2, kind=I32 } -> x6 - v32 Binop { op=lt, lhs=v30, rhs=v31 } -> x1 - terminator Bz { cond=v32, target=b8, fall=b7 } (exit_acc=v32) - block 6 start_pc=0 - v33 Extend { value=v28, kind=I32 } -> x1 - v34 BinopI { op=add, lhs=v33, rhs_imm=1 } -> x2 - v35 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v34) - block 7 start_pc=0 - v36 Extend { value=v29, kind=I32 } -> x1 - v37 LocalAddr(-6) -> x1 - v38 Imm(4) -> x6 - v39 Intrinsic { kind=5, args=[v37, v38] } -> x1 - v40 Load { addr=v39, disp=0, kind=I32 } -> x1 - v41 Binop { op=add, lhs=v29, rhs=v40 } -> x0 - v42 Imm(0) -> x1 - v43 Extend { value=v41, kind=I32 } -> x1 - terminator Jmp(b6) (exit_acc=v43) + v32 Binop { op=lt, lhs=v30, rhs=v31 } -> x6 + terminator Bnz { cond=v32, target=b5, fall=b8 } (exit_acc=v32) block 8 start_pc=0 v44 LocalAddr(-6) -> x1 v45 Intrinsic { kind=6, args=[v44] } -> x1 @@ -295,15 +295,15 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v7 Imm(4) -> x8 v8 Call { target_pc=0, args=[v3, v4, v5, v6, v7, v3], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v9 BinopI { op=ne, lhs=v8, rhs_imm=15 } -> x0 - terminator Bz { cond=v9, target=b15, fall=b1 } (exit_acc=v9) + terminator Bz { cond=v9, target=b21, fall=b1 } (exit_acc=v9) block 1 start_pc=0 v10 LoadLocal { off=-1, kind=I32 } -> x0 - v11 BinopI { op=or, lhs=v1, rhs_imm=1 } -> x3 + v11 Imm(1) -> x3 v12 Imm(0) -> x0 - v13 Extend { value=v11, kind=I32 } -> x0 + v13 Imm(1) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v14 Phi { incoming=[b15:v1, b1:v11], kind=I64 } -> x3 + v14 Phi { incoming=[b21:v1, b1:v11], kind=I64 } -> x3 v15 Imm(12) -> x7 v16 Imm(1) -> x6 v17 Imm(2) -> x2 @@ -318,7 +318,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v26 Imm(11) -> [spill 0] v27 Call { target_pc=0, args=[v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v15], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=78 } -> x0 - terminator Bz { cond=v28, target=b16, fall=b3 } (exit_acc=v28) + terminator Bz { cond=v28, target=b20, fall=b3 } (exit_acc=v28) block 3 start_pc=0 v29 Extend { value=v14, kind=I32 } -> x0 v30 BinopI { op=or, lhs=v14, rhs_imm=2 } -> x3 @@ -326,7 +326,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v32 Extend { value=v30, kind=I32 } -> x0 terminator Jmp(b4) (exit_acc=v32) block 4 start_pc=0 - v33 Phi { incoming=[b16:v14, b3:v30], kind=I64 } -> x3 + v33 Phi { incoming=[b20:v14, b3:v30], kind=I64 } -> x3 v34 Imm(4) -> x7 v35 Imm(4609434218613702656) -> x6 v36 Imm(4612811918334230528) -> x2 @@ -335,7 +335,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v39 Call { target_pc=1, args=[v34, v35, v36, v37, v38], fixed_args=1, fp_return=true, fp_arg_mask=0x1e } -> d0 v40 Imm(4622382067542392832) -> x0 v41 Binop { op=fne, lhs=v39, rhs=v40 } -> x0 - terminator Bz { cond=v41, target=b17, fall=b5 } (exit_acc=v41) + terminator Bz { cond=v41, target=b19, fall=b5 } (exit_acc=v41) block 5 start_pc=0 v42 Extend { value=v33, kind=I32 } -> x0 v43 BinopI { op=or, lhs=v33, rhs_imm=4 } -> x3 @@ -343,7 +343,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v45 Extend { value=v43, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v45) block 6 start_pc=0 - v46 Phi { incoming=[b17:v33, b5:v43], kind=I64 } -> x3 + v46 Phi { incoming=[b19:v33, b5:v43], kind=I64 } -> x3 v47 Imm(10) -> x7 v48 Imm(4607182418800017408) -> x6 v49 Imm(4611686018427387904) -> x2 @@ -375,7 +375,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v71 Call { target_pc=2, args=[v66, v67, v68, v69, v70], fixed_args=1, fp_return=true, fp_arg_mask=0x14 } -> d0 v72 Imm(4629981891913580544) -> x0 v73 Binop { op=fne, lhs=v71, rhs=v72 } -> x0 - terminator Bz { cond=v73, target=b19, fall=b9 } (exit_acc=v73) + terminator Bz { cond=v73, target=b17, fall=b9 } (exit_acc=v73) block 9 start_pc=0 v74 Extend { value=v65, kind=I32 } -> x0 v75 BinopI { op=or, lhs=v65, rhs_imm=16 } -> x3 @@ -383,7 +383,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v77 Extend { value=v75, kind=I32 } -> x0 terminator Jmp(b10) (exit_acc=v77) block 10 start_pc=0 - v78 Phi { incoming=[b19:v65, b9:v75], kind=I64 } -> x3 + v78 Phi { incoming=[b17:v65, b9:v75], kind=I64 } -> x3 v79 Imm(5) -> x7 v80 Imm(2) -> x6 v81 Imm(4) -> x2 @@ -392,7 +392,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v84 Imm(10) -> x9 v85 Call { target_pc=3, args=[v79, v80, v81, v82, v83, v84], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v86 BinopI { op=ne, lhs=v85, rhs_imm=60 } -> x0 - terminator Bz { cond=v86, target=b20, fall=b11 } (exit_acc=v86) + terminator Bz { cond=v86, target=b16, fall=b11 } (exit_acc=v86) block 11 start_pc=0 v87 Extend { value=v78, kind=I32 } -> x0 v88 BinopI { op=or, lhs=v78, rhs_imm=32 } -> x3 @@ -400,7 +400,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v90 Extend { value=v88, kind=I32 } -> x0 terminator Jmp(b12) (exit_acc=v90) block 12 start_pc=0 - v91 Phi { incoming=[b20:v78, b11:v88], kind=I64 } -> x3 + v91 Phi { incoming=[b16:v78, b11:v88], kind=I64 } -> x3 v92 Imm(1) -> x7 v93 Imm(2) -> x6 v94 Imm(3) -> x2 @@ -416,7 +416,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v104 Imm(300) -> [spill 1] v105 Call { target_pc=4, args=[v92, v93, v94, v95, v96, v97, v98, v99, v100, v101, v102, v103, v104], fixed_args=10, fp_return=false, fp_arg_mask=0x0 } -> x0 v106 BinopI { op=ne, lhs=v105, rhs_imm=655 } -> x0 - terminator Bz { cond=v106, target=b21, fall=b13 } (exit_acc=v106) + terminator Bz { cond=v106, target=b15, fall=b13 } (exit_acc=v106) block 13 start_pc=0 v107 Extend { value=v91, kind=I32 } -> x0 v108 BinopI { op=or, lhs=v91, rhs_imm=64 } -> x3 @@ -424,23 +424,23 @@ fn ent_pc=5 n_params=0 variadic=false locals=14 v110 Extend { value=v108, kind=I32 } -> x0 terminator Jmp(b14) (exit_acc=v110) block 14 start_pc=0 - v111 Phi { incoming=[b21:v91, b13:v108], kind=I64 } -> x3 + v111 Phi { incoming=[b15:v91, b13:v108], kind=I64 } -> x3 v112 Extend { value=v111, kind=I32 } -> x0 terminator Return(v112) (exit_acc=v112) block 15 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b14) block 16 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b12) block 17 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b10) block 18 start_pc=0 terminator Jmp(b8) block 19 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b6) block 20 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b4) block 21 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/add_sub_negative_imm.ssa b/tests/snapshots/ssa/add_sub_negative_imm.ssa index 1355c00ca..0133a680a 100644 --- a/tests/snapshots/ssa/add_sub_negative_imm.ssa +++ b/tests/snapshots/ssa/add_sub_negative_imm.ssa @@ -82,24 +82,24 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v48 Imm(0) -> x0 v49 Imm(5) -> x0 v50 StoreLocal { off=-4, value=v49, kind=I32, volatile } -> - - terminator Jmp(b15) (exit_acc=v50) + terminator Jmp(b17) (exit_acc=v50) block 15 start_pc=0 - v51 Phi { incoming=[b14:v47, b16:v59], kind=I64 } -> x1 - v52 LoadLocal { off=-4, kind=I32, volatile } -> x0 - v53 BinopI { op=gt, lhs=v52, rhs_imm=0 } -> x0 - terminator Bz { cond=v53, target=b18, fall=b17 } (exit_acc=v53) - block 16 start_pc=0 - v54 LoadLocal { off=-4, kind=I32, volatile } -> x0 - v55 BinopI { op=add, lhs=v54, rhs_imm=-1 } -> x0 - v56 StoreLocal { off=-4, value=v55, kind=I32, volatile } -> - - terminator Jmp(b15) (exit_acc=v56) - block 17 start_pc=0 v57 Extend { value=v51, kind=I32 } -> x0 v58 LoadLocal { off=-4, kind=I32, volatile } -> x0 v59 Binop { op=add, lhs=v51, rhs=v58 } -> x1 v60 Imm(0) -> x0 v61 Extend { value=v59, kind=I32 } -> x0 terminator Jmp(b16) (exit_acc=v61) + block 16 start_pc=0 + v54 LoadLocal { off=-4, kind=I32, volatile } -> x0 + v55 BinopI { op=add, lhs=v54, rhs_imm=-1 } -> x0 + v56 StoreLocal { off=-4, value=v55, kind=I32, volatile } -> - + terminator Jmp(b17) (exit_acc=v56) + block 17 start_pc=0 + v51 Phi { incoming=[b14:v47, b16:v59], kind=I64 } -> x1 + v52 LoadLocal { off=-4, kind=I32, volatile } -> x0 + v53 BinopI { op=gt, lhs=v52, rhs_imm=0 } -> x0 + terminator Bnz { cond=v53, target=b15, fall=b18 } (exit_acc=v53) block 18 start_pc=0 v62 Extend { value=v51, kind=I32 } -> x0 v63 BinopI { op=ne, lhs=v62, rhs_imm=15 } -> x0 diff --git a/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa b/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa index 979d55492..978fb78e6 100644 --- a/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa +++ b/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=13 --- ; name=main fn ent_pc=13 n_params=0 variadic=false locals=17 - spill_count=2 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ImmExtCode(binding=48) -> x0 @@ -12,145 +12,125 @@ fn ent_pc=13 n_params=0 variadic=false locals=17 v6 Imm(0) -> x1 v7 ImmExtCode(binding=52) -> x13 v8 Imm(0) -> x1 - v9 Imm(4625196817309499392) -> x1 - v10 FpCast { kind=F64ToF32, value=v9 } -> d0 [f32] - v11 LoadLocal { off=-1, kind=I64 } -> x1 - v12 CallIndirect { target=v1, args=[v10], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v13 Imm(4616189618054758400) -> x0 - v14 FpCast { kind=F32ToF64, value=v12 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v13 } -> x0 - terminator Bz { cond=v15, target=b2, fall=b1 } (exit_acc=v15) + v9 Imm(1098907648) -> x7 [f32] + v10 LoadLocal { off=-1, kind=I64 } -> x1 + v11 CallIndirect { target=v1, args=[v9], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v12 Imm(1082130432) -> x0 [f32] + v13 Binop { op=fne, lhs=v11, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) block 1 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 2 start_pc=0 - v17 Imm(4613262278296967578) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 LoadLocal { off=-2, kind=I64 } -> x0 - v20 CallIndirect { target=v3, args=[v18], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v21 Imm(4611686018427387904) -> x0 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v15 Imm(1076677837) -> x7 [f32] + v16 LoadLocal { off=-2, kind=I64 } -> x0 + v17 CallIndirect { target=v3, args=[v15], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v18 Imm(1073741824) -> x0 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v24 Imm(3) -> x0 - terminator Return(v24) (exit_acc=v24) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v25 Imm(4611911198408756429) -> x0 - v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] - v27 LoadLocal { off=-3, kind=I64 } -> x0 - v28 CallIndirect { target=v5, args=[v26], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v29 Imm(4613937818241073152) -> x0 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fne, lhs=v30, rhs=v29 } -> x0 - terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) + v21 Imm(1074161254) -> x7 [f32] + v22 LoadLocal { off=-3, kind=I64 } -> x0 + v23 CallIndirect { target=v5, args=[v21], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v24 Imm(1077936128) -> x0 [f32] + v25 Binop { op=fne, lhs=v23, rhs=v24 } -> x0 + terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) block 5 start_pc=0 - v32 Imm(4) -> x0 - terminator Return(v32) (exit_acc=v32) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) block 6 start_pc=0 - v33 Imm(4613712638259704627) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d0 [f32] - v35 LoadLocal { off=-4, kind=I64 } -> x0 - v36 CallIndirect { target=v7, args=[v34], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v37 Imm(4611686018427387904) -> x0 - v38 FpCast { kind=F32ToF64, value=v36 } -> d0 - v39 Binop { op=fne, lhs=v38, rhs=v37 } -> x0 - terminator Bz { cond=v39, target=b8, fall=b7 } (exit_acc=v39) + v27 Imm(1077516698) -> x7 [f32] + v28 LoadLocal { off=-4, kind=I64 } -> x0 + v29 CallIndirect { target=v7, args=[v27], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v30 Imm(1073741824) -> x0 [f32] + v31 Binop { op=fne, lhs=v29, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v32 Imm(5) -> x0 + terminator Return(v32) (exit_acc=v32) block 8 start_pc=0 - v41 ImmExtCode(binding=49) -> x0 - v42 Imm(0) -> x1 - v43 Imm(4615063718147915776) -> x3 - v44 Fneg(v43) -> d0 - v45 FpCast { kind=F64ToF32, value=v44 } -> d0 [f32] - v46 LoadLocal { off=-5, kind=I64 } -> x1 - v47 CallIndirect { target=v41, args=[v45], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v48 FpCast { kind=F32ToF64, value=v47 } -> d0 - v49 Binop { op=fne, lhs=v48, rhs=v43 } -> x0 - terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) + v33 ImmExtCode(binding=49) -> x0 + v34 Imm(0) -> x1 + v35 Imm(1080033280) -> x3 [f32] + v36 Fneg(v35) -> d0 [f32] + v37 LoadLocal { off=-5, kind=I64 } -> x1 + v38 CallIndirect { target=v33, args=[v36], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v39 Binop { op=fne, lhs=v38, rhs=v35 } -> x0 + terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) block 9 start_pc=0 - v50 Imm(1) -> x0 - terminator Return(v50) (exit_acc=v50) + v40 Imm(1) -> x0 + terminator Return(v40) (exit_acc=v40) block 10 start_pc=0 - v51 LocalAddr(-8) -> x0 - v52 ImmData(8) -> x1 - v53 Mcpy { dst=v51, src=v52, size=24 } -> x0 - v54 Imm(4635400285215260672) -> x0 - v55 FpCast { kind=F64ToF32, value=v54 } -> d0 [f32] - v56 Imm(0) -> x0 - v57 Imm(4618328827877759386) -> x0 - v58 FpCast { kind=F64ToF32, value=v57 } -> [spill 0] [f32] - v59 Imm(0) -> x0 - v60 Imm(4611911198408756429) -> x0 - v61 FpCast { kind=F64ToF32, value=v60 } -> [spill 1] [f32] - v62 Imm(0) -> x0 - v63 LocalAddr(-8) -> x0 - v64 Imm(0) -> x1 - v65 Load { addr=v63, disp=0, kind=I64 } -> x0 - v66 LoadLocal { off=-9, kind=F32 } -> d1 [f32] - v67 CallIndirect { target=v65, args=[v55], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v68 Imm(4621256167635550208) -> x0 - v69 FpCast { kind=F32ToF64, value=v67 } -> d0 - v70 Binop { op=fne, lhs=v69, rhs=v68 } -> x0 - terminator Bz { cond=v70, target=b12, fall=b11 } (exit_acc=v70) + v41 LocalAddr(-8) -> x0 + v42 ImmData(8) -> x1 + v43 Mcpy { dst=v41, src=v42, size=24 } -> x0 + v44 Imm(1117913088) -> x0 [f32] + v45 StoreLocal { off=-9, value=v44, kind=F32 } -> - + v46 Imm(1086115021) -> x0 [f32] + v47 StoreLocal { off=-10, value=v46, kind=F32 } -> - + v48 Imm(1074161254) -> x0 [f32] + v49 StoreLocal { off=-11, value=v48, kind=F32 } -> - + v50 LocalAddr(-8) -> x0 + v51 Imm(0) -> x1 + v52 Load { addr=v50, disp=0, kind=I64 } -> x0 + v53 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v54 CallIndirect { target=v52, args=[v53], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v55 Imm(1091567616) -> x0 [f32] + v56 Binop { op=fne, lhs=v54, rhs=v55 } -> x0 + terminator Bz { cond=v56, target=b12, fall=b11 } (exit_acc=v56) block 11 start_pc=0 - v71 Imm(6) -> x0 - terminator Return(v71) (exit_acc=v71) + v57 Imm(6) -> x0 + terminator Return(v57) (exit_acc=v57) block 12 start_pc=0 - v72 LocalAddr(-8) -> x0 - v73 Imm(8) -> x1 - v74 BinopI { op=add, lhs=v72, rhs_imm=8 } -> x1 - v75 Load { addr=v72, disp=8, kind=I64 } -> x0 - v76 LoadLocal { off=-10, kind=F32 } -> d0 [f32] - v77 CallIndirect { target=v75, args=[v58], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v78 Imm(4617315517961601024) -> x0 - v79 FpCast { kind=F32ToF64, value=v77 } -> d0 - v80 Binop { op=fne, lhs=v79, rhs=v78 } -> x0 - terminator Bz { cond=v80, target=b14, fall=b13 } (exit_acc=v80) + v58 LocalAddr(-8) -> x0 + v59 Imm(8) -> x1 + v60 BinopI { op=add, lhs=v58, rhs_imm=8 } -> x1 + v61 Load { addr=v58, disp=8, kind=I64 } -> x0 + v62 LoadLocal { off=-10, kind=F32 } -> d0 [f32] + v63 CallIndirect { target=v61, args=[v62], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v64 Imm(1084227584) -> x0 [f32] + v65 Binop { op=fne, lhs=v63, rhs=v64 } -> x0 + terminator Bz { cond=v65, target=b14, fall=b13 } (exit_acc=v65) block 13 start_pc=0 - v81 Imm(7) -> x0 - terminator Return(v81) (exit_acc=v81) + v66 Imm(7) -> x0 + terminator Return(v66) (exit_acc=v66) block 14 start_pc=0 - v82 LocalAddr(-8) -> x0 - v83 Imm(16) -> x1 - v84 BinopI { op=add, lhs=v82, rhs_imm=16 } -> x1 - v85 Load { addr=v82, disp=16, kind=I64 } -> x0 - v86 LoadLocal { off=-11, kind=F32 } -> d0 [f32] - v87 CallIndirect { target=v85, args=[v61], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v88 Imm(4613937818241073152) -> x0 - v89 FpCast { kind=F32ToF64, value=v87 } -> d0 - v90 Binop { op=fne, lhs=v89, rhs=v88 } -> x0 - terminator Bz { cond=v90, target=b16, fall=b15 } (exit_acc=v90) + v67 LocalAddr(-8) -> x0 + v68 Imm(16) -> x1 + v69 BinopI { op=add, lhs=v67, rhs_imm=16 } -> x1 + v70 Load { addr=v67, disp=16, kind=I64 } -> x0 + v71 LoadLocal { off=-11, kind=F32 } -> d0 [f32] + v72 CallIndirect { target=v70, args=[v71], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v73 Imm(1077936128) -> x0 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x0 + terminator Bz { cond=v74, target=b16, fall=b15 } (exit_acc=v74) block 15 start_pc=0 - v91 Imm(8) -> x0 - terminator Return(v91) (exit_acc=v91) + v75 Imm(8) -> x0 + terminator Return(v75) (exit_acc=v75) block 16 start_pc=0 - v92 Imm(4619567317775286272) -> x0 - v93 Fneg(v92) -> d0 - v94 FpCast { kind=F64ToF32, value=v93 } -> d0 [f32] - v95 Intrinsic { kind=14, args=[v94] } -> d0 [f32] - v96 FpCast { kind=F32ToF64, value=v95 } -> d0 - v97 Binop { op=fne, lhs=v96, rhs=v92 } -> x0 - terminator Bz { cond=v97, target=b18, fall=b17 } (exit_acc=v97) + v76 Imm(1088421888) -> x0 [f32] + v77 Fneg(v76) -> d0 [f32] + v78 Intrinsic { kind=14, args=[v77] } -> d0 [f32] + v79 Binop { op=fne, lhs=v78, rhs=v76 } -> x0 + terminator Bz { cond=v79, target=b18, fall=b17 } (exit_acc=v79) block 17 start_pc=0 - v98 Imm(9) -> x0 - terminator Return(v98) (exit_acc=v98) + v80 Imm(9) -> x0 + terminator Return(v80) (exit_acc=v80) block 18 start_pc=0 - v99 Imm(4632092954238910464) -> x0 - v100 FpCast { kind=F64ToF32, value=v99 } -> d0 [f32] - v101 Intrinsic { kind=12, args=[v100] } -> d0 [f32] - v102 Imm(4619567317775286272) -> x0 - v103 FpCast { kind=F32ToF64, value=v101 } -> d0 - v104 Binop { op=fne, lhs=v103, rhs=v102 } -> x0 - terminator Bz { cond=v104, target=b20, fall=b19 } (exit_acc=v104) + v81 Imm(1111752704) -> x0 [f32] + v82 Intrinsic { kind=12, args=[v81] } -> d0 [f32] + v83 Imm(1088421888) -> x0 [f32] + v84 Binop { op=fne, lhs=v82, rhs=v83 } -> x0 + terminator Bz { cond=v84, target=b20, fall=b19 } (exit_acc=v84) block 19 start_pc=0 - v105 Imm(10) -> x0 - terminator Return(v105) (exit_acc=v105) + v85 Imm(10) -> x0 + terminator Return(v85) (exit_acc=v85) block 20 start_pc=0 - v106 Imm(0) -> x0 - terminator Return(v106) (exit_acc=v106) + v86 Imm(0) -> x0 + terminator Return(v86) (exit_acc=v86) ; --- SSA dump (ok=true) ent_pc=14 --- ; name=__c5_sys_sqrtf fn ent_pc=14 n_params=0 variadic=false locals=0 diff --git a/tests/snapshots/ssa/alignof_operator.ssa b/tests/snapshots/ssa/alignof_operator.ssa index 84155564a..dc8434ec0 100644 --- a/tests/snapshots/ssa/alignof_operator.ssa +++ b/tests/snapshots/ssa/alignof_operator.ssa @@ -13,55 +13,55 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 terminator Return(v4) (exit_acc=v4) block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v6 Imm(2) -> x0 - terminator Return(v6) (exit_acc=v6) - block 4 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v7) + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v8 Imm(3) -> x0 - terminator Return(v8) (exit_acc=v8) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v9) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v10 Imm(4) -> x0 - terminator Return(v10) (exit_acc=v10) + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) block 8 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v11) + v17 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v17) block 9 start_pc=0 - v12 Imm(5) -> x0 - terminator Return(v12) (exit_acc=v12) + v19 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v19) block 10 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v13) + v21 Imm(0) -> x0 + terminator Return(v21) (exit_acc=v21) block 11 start_pc=0 - v14 Imm(6) -> x0 - terminator Return(v14) (exit_acc=v14) + v6 Imm(2) -> x0 + terminator Return(v6) (exit_acc=v6) block 12 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v15) + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) block 13 start_pc=0 - v16 Imm(7) -> x0 - terminator Return(v16) (exit_acc=v16) + v10 Imm(4) -> x0 + terminator Return(v10) (exit_acc=v10) block 14 start_pc=0 - v17 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v17) + v12 Imm(5) -> x0 + terminator Return(v12) (exit_acc=v12) block 15 start_pc=0 - v18 Imm(8) -> x0 - terminator Return(v18) (exit_acc=v18) + v14 Imm(6) -> x0 + terminator Return(v14) (exit_acc=v14) block 16 start_pc=0 - v19 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v19) + v16 Imm(7) -> x0 + terminator Return(v16) (exit_acc=v16) block 17 start_pc=0 + v18 Imm(8) -> x0 + terminator Return(v18) (exit_acc=v18) + block 18 start_pc=0 v20 Imm(9) -> x0 terminator Return(v20) (exit_acc=v20) - block 18 start_pc=0 - v21 Imm(0) -> x0 - terminator Return(v21) (exit_acc=v21) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/alloca_alignment.ssa b/tests/snapshots/ssa/alloca_alignment.ssa index 2b29bb8ed..632221199 100644 --- a/tests/snapshots/ssa/alloca_alignment.ssa +++ b/tests/snapshots/ssa/alloca_alignment.ssa @@ -116,18 +116,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=1034 terminator Jmp(b8) (exit_acc=v84) block 8 start_pc=0 v85 LoadLocal { off=-1031, kind=I64 } -> x0 - terminator Bz { cond=v85, target=b10, fall=b9 } (exit_acc=v85) + terminator Bz { cond=v85, target=b11, fall=b9 } (exit_acc=v85) block 9 start_pc=0 v86 Imm(0) -> x0 v87 StoreLocal { off=-1034, value=v86, kind=I64 } -> - - terminator Jmp(b11) (exit_acc=v87) + terminator Jmp(b10) (exit_acc=v87) block 10 start_pc=0 - v88 Imm(1) -> x0 - v89 StoreLocal { off=-1034, value=v88, kind=I64 } -> - - terminator Jmp(b11) (exit_acc=v89) - block 11 start_pc=0 v90 LoadLocal { off=-1034, kind=I64 } -> x0 terminator Return(v90) (exit_acc=v90) + block 11 start_pc=0 + v88 Imm(1) -> x0 + v89 StoreLocal { off=-1034, value=v88, kind=I64 } -> - + terminator Jmp(b10) (exit_acc=v89) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/alloca_arena_in_bounds.ssa b/tests/snapshots/ssa/alloca_arena_in_bounds.ssa index 97dc75425..f31a74efa 100644 --- a/tests/snapshots/ssa/alloca_arena_in_bounds.ssa +++ b/tests/snapshots/ssa/alloca_arena_in_bounds.ssa @@ -13,17 +13,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=1030 v7 Imm(0) -> x0 v8 StoreLocal { off=-2, value=v7, kind=I32 } -> - v9 StoreLocal { off=-3, value=v7, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v10 LoadLocal { off=-3, kind=I32 } -> x0 - v11 BinopI { op=lt, lhs=v10, rhs_imm=8000 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 LoadLocal { off=-3, kind=I32 } -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x0 - v14 StoreLocal { off=-3, value=v13, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 v15 LoadLocal { off=-2, kind=I32 } -> x0 v16 LoadLocal { off=-1, kind=I64 } -> x1 v17 LoadLocal { off=-3, kind=I32 } -> x2 @@ -33,21 +24,30 @@ fn ent_pc=0 n_params=0 variadic=false locals=1030 v21 StoreLocal { off=-2, value=v20, kind=I32 } -> - v22 LoadLocal { off=-2, kind=I32 } -> x0 terminator Jmp(b2) (exit_acc=v22) + block 2 start_pc=0 + v12 LoadLocal { off=-3, kind=I32 } -> x0 + v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x0 + v14 StoreLocal { off=-3, value=v13, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v10 LoadLocal { off=-3, kind=I32 } -> x0 + v11 BinopI { op=lt, lhs=v10, rhs_imm=8000 } -> x0 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v23 LoadLocal { off=-2, kind=I32 } -> x0 v24 BinopI { op=eq, lhs=v23, rhs_imm=24000 } -> x0 - terminator Bz { cond=v24, target=b6, fall=b5 } (exit_acc=v24) + terminator Bz { cond=v24, target=b7, fall=b5 } (exit_acc=v24) block 5 start_pc=0 v25 Imm(0) -> x0 v26 StoreLocal { off=-1030, value=v25, kind=I64 } -> - - terminator Jmp(b7) (exit_acc=v26) + terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v27 Imm(1) -> x0 - v28 StoreLocal { off=-1030, value=v27, kind=I64 } -> - - terminator Jmp(b7) (exit_acc=v28) - block 7 start_pc=0 v29 LoadLocal { off=-1030, kind=I64 } -> x0 terminator Return(v29) (exit_acc=v29) + block 7 start_pc=0 + v27 Imm(1) -> x0 + v28 StoreLocal { off=-1030, value=v27, kind=I64 } -> - + terminator Jmp(b6) (exit_acc=v28) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/alloca_basic.ssa b/tests/snapshots/ssa/alloca_basic.ssa index a7c7c0e2d..f2449a62a 100644 --- a/tests/snapshots/ssa/alloca_basic.ssa +++ b/tests/snapshots/ssa/alloca_basic.ssa @@ -12,23 +12,23 @@ fn ent_pc=1 n_params=0 variadic=false locals=1029 v6 CallExt { binding_idx=54, args=[v4, v5, v1], fp_arg_mask=0x0 } -> x0 v7 Imm(0) -> x0 v8 StoreLocal { off=-2, value=v7, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v8) + terminator Jmp(b3) (exit_acc=v8) block 1 start_pc=0 - v9 LoadLocal { off=-2, kind=I32 } -> x0 - v10 BinopI { op=lt, lhs=v9, rhs_imm=32 } -> x0 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) - block 2 start_pc=0 - v11 LoadLocal { off=-2, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 - v13 StoreLocal { off=-2, value=v12, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v13) - block 3 start_pc=0 v14 LoadLocal { off=-1, kind=I64 } -> x0 v15 LoadLocal { off=-2, kind=I32 } -> x1 v16 Binop { op=add, lhs=v14, rhs=v15 } -> x0 v17 Load { addr=v16, disp=0, kind=I8 } -> x0 v18 BinopI { op=ne, lhs=v17, rhs_imm=85 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b5, fall=b2 } (exit_acc=v18) + block 2 start_pc=0 + v11 LoadLocal { off=-2, kind=I32 } -> x0 + v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 + v13 StoreLocal { off=-2, value=v12, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 + v9 LoadLocal { off=-2, kind=I32 } -> x0 + v10 BinopI { op=lt, lhs=v9, rhs_imm=32 } -> x0 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v20 Imm(0) -> x0 terminator Return(v20) (exit_acc=v20) @@ -54,18 +54,8 @@ fn ent_pc=2 n_params=1 variadic=false locals=1028 v9 Imm(0) -> x0 v10 StoreLocal { off=-3, value=v9, kind=I32 } -> - v11 StoreLocal { off=-2, value=v9, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v11) + terminator Jmp(b3) (exit_acc=v11) block 1 start_pc=0 - v12 LoadLocal { off=-2, kind=I32 } -> x0 - v13 LoadLocal { off=2, kind=I32 } -> x1 - v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 2 start_pc=0 - v15 LoadLocal { off=-2, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 - v17 StoreLocal { off=-2, value=v16, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v17) - block 3 start_pc=0 v18 LoadLocal { off=-1, kind=I64 } -> x0 v19 LoadLocal { off=-2, kind=I32 } -> x1 v20 BinopI { op=shl, lhs=v19, rhs_imm=2 } -> x2 @@ -78,21 +68,21 @@ fn ent_pc=2 n_params=1 variadic=false locals=1028 v27 Extend { value=v25, kind=I32 } -> x6 v28 StoreIndexed { base=v18, index=v19, scale=4, value=v25, kind=I32 } -> - terminator Jmp(b2) (exit_acc=v28) + block 2 start_pc=0 + v15 LoadLocal { off=-2, kind=I32 } -> x0 + v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 + v17 StoreLocal { off=-2, value=v16, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v17) + block 3 start_pc=0 + v12 LoadLocal { off=-2, kind=I32 } -> x0 + v13 LoadLocal { off=2, kind=I32 } -> x1 + v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x0 + terminator Bnz { cond=v14, target=b1, fall=b4 } (exit_acc=v14) block 4 start_pc=0 v29 Imm(0) -> x0 v30 StoreLocal { off=-2, value=v29, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v30) + terminator Jmp(b7) (exit_acc=v30) block 5 start_pc=0 - v31 LoadLocal { off=-2, kind=I32 } -> x0 - v32 LoadLocal { off=2, kind=I32 } -> x1 - v33 Binop { op=lt, lhs=v31, rhs=v32 } -> x0 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) - block 6 start_pc=0 - v34 LoadLocal { off=-2, kind=I32 } -> x0 - v35 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x0 - v36 StoreLocal { off=-2, value=v35, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v36) - block 7 start_pc=0 v37 LoadLocal { off=-3, kind=I32 } -> x0 v38 LoadLocal { off=-1, kind=I64 } -> x1 v39 LoadLocal { off=-2, kind=I32 } -> x2 @@ -103,6 +93,16 @@ fn ent_pc=2 n_params=1 variadic=false locals=1028 v44 StoreLocal { off=-3, value=v43, kind=I32 } -> - v45 LoadLocal { off=-3, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v45) + block 6 start_pc=0 + v34 LoadLocal { off=-2, kind=I32 } -> x0 + v35 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x0 + v36 StoreLocal { off=-2, value=v35, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v36) + block 7 start_pc=0 + v31 LoadLocal { off=-2, kind=I32 } -> x0 + v32 LoadLocal { off=2, kind=I32 } -> x1 + v33 Binop { op=lt, lhs=v31, rhs=v32 } -> x0 + terminator Bnz { cond=v33, target=b5, fall=b8 } (exit_acc=v33) block 8 start_pc=0 v46 LoadLocal { off=-3, kind=I32 } -> x0 terminator Return(v46) (exit_acc=v46) @@ -187,18 +187,8 @@ fn ent_pc=4 n_params=1 variadic=false locals=1028 v3 Imm(0) -> x0 v4 StoreLocal { off=-1, value=v3, kind=I32 } -> - v5 StoreLocal { off=-2, value=v3, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v6 LoadLocal { off=-2, kind=I32 } -> x0 - v7 LoadLocal { off=2, kind=I32 } -> x1 - v8 Binop { op=lt, lhs=v6, rhs=v7 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) - block 2 start_pc=0 - v9 LoadLocal { off=-2, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 - v11 StoreLocal { off=-2, value=v10, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 v12 Imm(8) -> x0 v13 Intrinsic { kind=1, args=[v12] } -> x0 v14 StoreLocal { off=-3, value=v13, kind=I64 } -> - @@ -214,6 +204,16 @@ fn ent_pc=4 n_params=1 variadic=false locals=1028 v24 StoreLocal { off=-1, value=v23, kind=I32 } -> - v25 LoadLocal { off=-1, kind=I32 } -> x0 terminator Jmp(b2) (exit_acc=v25) + block 2 start_pc=0 + v9 LoadLocal { off=-2, kind=I32 } -> x0 + v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 + v11 StoreLocal { off=-2, value=v10, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v11) + block 3 start_pc=0 + v6 LoadLocal { off=-2, kind=I32 } -> x0 + v7 LoadLocal { off=2, kind=I32 } -> x1 + v8 Binop { op=lt, lhs=v6, rhs=v7 } -> x0 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) block 4 start_pc=0 v26 LoadLocal { off=-1, kind=I32 } -> x0 terminator Return(v26) (exit_acc=v26) @@ -236,17 +236,8 @@ fn ent_pc=5 n_params=1 variadic=false locals=1029 v11 StoreLocal { off=-2, value=v10, kind=I32 } -> - v12 Imm(0) -> x0 v13 StoreLocal { off=-3, value=v12, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 1 start_pc=0 - v14 LoadLocal { off=-3, kind=I32 } -> x0 - v15 BinopI { op=lt, lhs=v14, rhs_imm=64 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 2 start_pc=0 - v16 LoadLocal { off=-3, kind=I32 } -> x0 - v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x0 - v18 StoreLocal { off=-3, value=v17, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v18) - block 3 start_pc=0 v19 LoadLocal { off=-1, kind=I64 } -> x0 v20 LoadLocal { off=-3, kind=I32 } -> x1 v21 Binop { op=add, lhs=v19, rhs=v20 } -> x0 @@ -255,22 +246,31 @@ fn ent_pc=5 n_params=1 variadic=false locals=1029 v24 BinopI { op=shl, lhs=v23, rhs_imm=56 } -> x2 v25 Extend { value=v23, kind=I8 } -> x1 v26 Binop { op=ne, lhs=v22, rhs=v25 } -> x0 - terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) + terminator Bnz { cond=v26, target=b7, fall=b2 } (exit_acc=v26) + block 2 start_pc=0 + v16 LoadLocal { off=-3, kind=I32 } -> x0 + v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x0 + v18 StoreLocal { off=-3, value=v17, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v18) + block 3 start_pc=0 + v14 LoadLocal { off=-3, kind=I32 } -> x0 + v15 BinopI { op=lt, lhs=v14, rhs_imm=64 } -> x0 + terminator Bnz { cond=v15, target=b1, fall=b4 } (exit_acc=v15) block 4 start_pc=0 v28 LoadLocal { off=-2, kind=I32 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=190 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v27 Imm(-1) -> x0 - terminator Return(v27) (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b2) - block 7 start_pc=0 v30 Imm(-2) -> x0 terminator Return(v30) (exit_acc=v30) - block 8 start_pc=0 + block 6 start_pc=0 v31 Imm(0) -> x0 terminator Return(v31) (exit_acc=v31) + block 7 start_pc=0 + v27 Imm(-1) -> x0 + terminator Return(v27) (exit_acc=v27) + block 8 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=6 --- ; name=main fn ent_pc=6 n_params=0 variadic=false locals=3 diff --git a/tests/snapshots/ssa/anon_struct_init.ssa b/tests/snapshots/ssa/anon_struct_init.ssa index 9131b1248..c8a59b7e5 100644 --- a/tests/snapshots/ssa/anon_struct_init.ssa +++ b/tests/snapshots/ssa/anon_struct_init.ssa @@ -11,7 +11,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v5 BinopI { op=eq, lhs=v4, rhs_imm=0 } -> x1 v6 Imm(0) -> x6 v7 Imm(0) -> x2 - terminator Bz { cond=v5, target=b21, fall=b1 } (exit_acc=v5) + terminator Bz { cond=v5, target=b26, fall=b1 } (exit_acc=v5) block 1 start_pc=0 v8 ImmData(8) -> x1 v9 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 @@ -21,7 +21,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v13 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v14 Phi { incoming=[b21:v6, b1:v12], kind=I64 } -> x6 + v14 Phi { incoming=[b26:v6, b1:v12], kind=I64 } -> x6 v15 LoadLocal { off=-4, kind=I64 } -> x0 v16 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) @@ -34,7 +34,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v20 BinopI { op=eq, lhs=v19, rhs_imm=1 } -> x0 v21 Imm(0) -> x2 v22 Imm(0) -> x1 - terminator Bz { cond=v20, target=b22, fall=b5 } (exit_acc=v20) + terminator Bz { cond=v20, target=b25, fall=b5 } (exit_acc=v20) block 5 start_pc=0 v23 ImmData(16) -> x0 v24 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x1 @@ -44,11 +44,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v28 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v27) block 6 start_pc=0 - v29 Phi { incoming=[b22:v21, b5:v27], kind=I64 } -> x2 + v29 Phi { incoming=[b25:v21, b5:v27], kind=I64 } -> x2 v30 LoadLocal { off=-6, kind=I64 } -> x0 v31 Imm(0) -> x1 v32 Imm(0) -> x0 - terminator Bz { cond=v29, target=b23, fall=b7 } (exit_acc=v29) + terminator Bz { cond=v29, target=b24, fall=b7 } (exit_acc=v29) block 7 start_pc=0 v33 ImmData(16) -> x0 v34 BinopI { op=add, lhs=v33, rhs_imm=8 } -> x1 @@ -58,7 +58,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v38 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Phi { incoming=[b23:v31, b7:v37], kind=I64 } -> x1 + v39 Phi { incoming=[b24:v31, b7:v37], kind=I64 } -> x1 v40 LoadLocal { off=-5, kind=I64 } -> x0 v41 BinopI { op=eq, lhs=v39, rhs_imm=0 } -> x0 terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) @@ -76,7 +76,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v50 BinopI { op=eq, lhs=v49, rhs_imm=0 } -> x0 v51 Imm(0) -> x2 v52 Imm(0) -> x1 - terminator Bz { cond=v50, target=b24, fall=b11 } (exit_acc=v50) + terminator Bz { cond=v50, target=b23, fall=b11 } (exit_acc=v50) block 11 start_pc=0 v53 LocalAddr(-1) -> x0 v54 BinopI { op=add, lhs=v53, rhs_imm=4 } -> x1 @@ -86,7 +86,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v58 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v57) block 12 start_pc=0 - v59 Phi { incoming=[b24:v51, b11:v57], kind=I64 } -> x2 + v59 Phi { incoming=[b23:v51, b11:v57], kind=I64 } -> x2 v60 LoadLocal { off=-7, kind=I64 } -> x0 v61 BinopI { op=eq, lhs=v59, rhs_imm=0 } -> x0 terminator Bz { cond=v61, target=b14, fall=b13 } (exit_acc=v61) @@ -102,7 +102,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v68 BinopI { op=eq, lhs=v67, rhs_imm=8 } -> x0 v69 Imm(0) -> x2 v70 Imm(0) -> x1 - terminator Bz { cond=v68, target=b25, fall=b15 } (exit_acc=v68) + terminator Bz { cond=v68, target=b22, fall=b15 } (exit_acc=v68) block 15 start_pc=0 v71 LocalAddr(-3) -> x0 v72 BinopI { op=add, lhs=v71, rhs_imm=4 } -> x1 @@ -112,11 +112,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v76 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v75) block 16 start_pc=0 - v77 Phi { incoming=[b25:v69, b15:v75], kind=I64 } -> x2 + v77 Phi { incoming=[b22:v69, b15:v75], kind=I64 } -> x2 v78 LoadLocal { off=-9, kind=I64 } -> x0 v79 Imm(0) -> x1 v80 Imm(0) -> x0 - terminator Bz { cond=v77, target=b26, fall=b17 } (exit_acc=v77) + terminator Bz { cond=v77, target=b21, fall=b17 } (exit_acc=v77) block 17 start_pc=0 v81 LocalAddr(-3) -> x0 v82 BinopI { op=add, lhs=v81, rhs_imm=8 } -> x1 @@ -126,7 +126,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v86 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v85) block 18 start_pc=0 - v87 Phi { incoming=[b26:v79, b17:v85], kind=I64 } -> x1 + v87 Phi { incoming=[b21:v79, b17:v85], kind=I64 } -> x1 v88 LoadLocal { off=-8, kind=I64 } -> x0 v89 BinopI { op=eq, lhs=v87, rhs_imm=0 } -> x0 terminator Bz { cond=v89, target=b20, fall=b19 } (exit_acc=v89) @@ -137,17 +137,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v91 Imm(0) -> x0 terminator Return(v91) (exit_acc=v91) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 23 start_pc=0 - terminator Jmp(b8) - block 24 start_pc=0 terminator Jmp(b12) + block 24 start_pc=0 + terminator Jmp(b8) block 25 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 26 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/anon_union_braced_init.ssa b/tests/snapshots/ssa/anon_union_braced_init.ssa index b6819cf3f..3e1b12986 100644 --- a/tests/snapshots/ssa/anon_union_braced_init.ssa +++ b/tests/snapshots/ssa/anon_union_braced_init.ssa @@ -38,19 +38,19 @@ fn ent_pc=0 n_params=2 variadic=false locals=6 block 2 start_pc=0 v29 Phi { incoming=[b6:v21, b1:v27], kind=I64 } -> x1 v30 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v29, target=b4, fall=b3 } (exit_acc=v29) + terminator Bz { cond=v29, target=b5, fall=b3 } (exit_acc=v29) block 3 start_pc=0 v31 Imm(0) -> x1 v32 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v31) + terminator Jmp(b4) (exit_acc=v31) block 4 start_pc=0 - v33 Imm(1) -> x1 - v34 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v33) - block 5 start_pc=0 - v35 Phi { incoming=[b3:v31, b4:v33], kind=I64 } -> x1 + v35 Phi { incoming=[b3:v31, b5:v33], kind=I64 } -> x1 v36 LoadLocal { off=-6, kind=I64 } -> x0 terminator Return(v35) (exit_acc=v35) + block 5 start_pc=0 + v33 Imm(1) -> x1 + v34 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v33) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -78,7 +78,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v13 BinopI { op=ne, lhs=v12, rhs_imm=1 } -> x0 v14 Imm(1) -> x2 v15 Imm(0) -> x1 - terminator Bnz { cond=v13, target=b17, fall=b3 } (exit_acc=v13) + terminator Bnz { cond=v13, target=b20, fall=b3 } (exit_acc=v13) block 3 start_pc=0 v16 LocalAddr(-2) -> x0 v17 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x1 @@ -89,10 +89,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v22 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v21) block 4 start_pc=0 - v23 Phi { incoming=[b17:v14, b3:v21], kind=I64 } -> x2 + v23 Phi { incoming=[b20:v14, b3:v21], kind=I64 } -> x2 v24 LoadLocal { off=-12, kind=I64 } -> x0 v25 Imm(0) -> x0 - terminator Bnz { cond=v23, target=b18, fall=b5 } (exit_acc=v23) + terminator Bnz { cond=v23, target=b19, fall=b5 } (exit_acc=v23) block 5 start_pc=0 v26 LocalAddr(-2) -> x0 v27 BinopI { op=add, lhs=v26, rhs_imm=8 } -> x1 @@ -102,7 +102,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v31 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v30) block 6 start_pc=0 - v32 Phi { incoming=[b18:v23, b5:v30], kind=I64 } -> x2 + v32 Phi { incoming=[b19:v23, b5:v30], kind=I64 } -> x2 v33 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v32, target=b8, fall=b7 } (exit_acc=v32) block 7 start_pc=0 @@ -116,7 +116,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v39 Load { addr=v38, disp=0, kind=I32 } -> x0 v40 BinopI { op=ne, lhs=v39, rhs_imm=3 } -> x1 v41 Imm(0) -> x0 - terminator Bnz { cond=v40, target=b19, fall=b9 } (exit_acc=v40) + terminator Bnz { cond=v40, target=b18, fall=b9 } (exit_acc=v40) block 9 start_pc=0 v42 LocalAddr(-6) -> x0 v43 BinopI { op=add, lhs=v42, rhs_imm=8 } -> x1 @@ -125,7 +125,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v46 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v45) block 10 start_pc=0 - v47 Phi { incoming=[b19:v40, b9:v45], kind=I64 } -> x1 + v47 Phi { incoming=[b18:v40, b9:v45], kind=I64 } -> x1 v48 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v47, target=b12, fall=b11 } (exit_acc=v47) block 11 start_pc=0 @@ -142,7 +142,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v57 Load { addr=v56, disp=0, kind=I32 } -> x0 v58 BinopI { op=ne, lhs=v57, rhs_imm=5 } -> x1 v59 Imm(0) -> x0 - terminator Bnz { cond=v58, target=b20, fall=b13 } (exit_acc=v58) + terminator Bnz { cond=v58, target=b17, fall=b13 } (exit_acc=v58) block 13 start_pc=0 v60 LocalAddr(-8) -> x0 v61 BinopI { op=add, lhs=v60, rhs_imm=8 } -> x1 @@ -152,7 +152,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v65 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v64) block 14 start_pc=0 - v66 Phi { incoming=[b20:v58, b13:v64], kind=I64 } -> x1 + v66 Phi { incoming=[b17:v58, b13:v64], kind=I64 } -> x1 v67 LoadLocal { off=-14, kind=I64 } -> x0 terminator Bz { cond=v66, target=b16, fall=b15 } (exit_acc=v66) block 15 start_pc=0 @@ -162,13 +162,13 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v69 Imm(0) -> x0 terminator Return(v69) (exit_acc=v69) block 17 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b14) block 18 start_pc=0 - terminator Jmp(b6) - block 19 start_pc=0 terminator Jmp(b10) + block 19 start_pc=0 + terminator Jmp(b6) block 20 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/anon_union_init.ssa b/tests/snapshots/ssa/anon_union_init.ssa index 507ab0c83..076678638 100644 --- a/tests/snapshots/ssa/anon_union_init.ssa +++ b/tests/snapshots/ssa/anon_union_init.ssa @@ -8,7 +8,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v2 Load { addr=v1, disp=0, kind=I32 } -> x1 v3 BinopI { op=ne, lhs=v2, rhs_imm=1 } -> x2 v4 Imm(0) -> x1 - terminator Bnz { cond=v3, target=b21, fall=b1 } (exit_acc=v3) + terminator Bnz { cond=v3, target=b26, fall=b1 } (exit_acc=v3) block 1 start_pc=0 v5 ImmData(8) -> x1 v6 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 @@ -17,7 +17,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v9 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v8) block 2 start_pc=0 - v10 Phi { incoming=[b21:v3, b1:v8], kind=I64 } -> x2 + v10 Phi { incoming=[b26:v3, b1:v8], kind=I64 } -> x2 v11 LoadLocal { off=-1, kind=I64 } -> x1 terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 @@ -29,7 +29,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v15 Load { addr=v1, disp=8, kind=I32 } -> x1 v16 BinopI { op=ne, lhs=v15, rhs_imm=3 } -> x2 v17 Imm(0) -> x1 - terminator Bnz { cond=v16, target=b22, fall=b5 } (exit_acc=v16) + terminator Bnz { cond=v16, target=b25, fall=b5 } (exit_acc=v16) block 5 start_pc=0 v18 ImmData(8) -> x1 v19 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -38,7 +38,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v22 Imm(0) -> x1 terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Phi { incoming=[b22:v16, b5:v21], kind=I64 } -> x2 + v23 Phi { incoming=[b25:v16, b5:v21], kind=I64 } -> x2 v24 LoadLocal { off=-2, kind=I64 } -> x1 terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) block 7 start_pc=0 @@ -50,7 +50,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v28 Load { addr=v1, disp=12, kind=I32 } -> x1 v29 BinopI { op=ne, lhs=v28, rhs_imm=4 } -> x2 v30 Imm(0) -> x1 - terminator Bnz { cond=v29, target=b23, fall=b9 } (exit_acc=v29) + terminator Bnz { cond=v29, target=b24, fall=b9 } (exit_acc=v29) block 9 start_pc=0 v31 ImmData(8) -> x1 v32 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x1 @@ -60,7 +60,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v36 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v35) block 10 start_pc=0 - v37 Phi { incoming=[b23:v29, b9:v35], kind=I64 } -> x2 + v37 Phi { incoming=[b24:v29, b9:v35], kind=I64 } -> x2 v38 LoadLocal { off=-3, kind=I64 } -> x0 terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) block 11 start_pc=0 @@ -72,7 +72,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v42 BinopI { op=ne, lhs=v41, rhs_imm=10 } -> x0 v43 Imm(1) -> x2 v44 Imm(0) -> x1 - terminator Bnz { cond=v42, target=b24, fall=b13 } (exit_acc=v42) + terminator Bnz { cond=v42, target=b23, fall=b13 } (exit_acc=v42) block 13 start_pc=0 v45 ImmData(32) -> x0 v46 BinopI { op=add, lhs=v45, rhs_imm=4 } -> x1 @@ -82,11 +82,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v50 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v49) block 14 start_pc=0 - v51 Phi { incoming=[b24:v43, b13:v49], kind=I64 } -> x2 + v51 Phi { incoming=[b23:v43, b13:v49], kind=I64 } -> x2 v52 LoadLocal { off=-6, kind=I64 } -> x0 v53 Imm(1) -> x1 v54 Imm(0) -> x0 - terminator Bnz { cond=v51, target=b25, fall=b15 } (exit_acc=v51) + terminator Bnz { cond=v51, target=b22, fall=b15 } (exit_acc=v51) block 15 start_pc=0 v55 ImmData(32) -> x0 v56 BinopI { op=add, lhs=v55, rhs_imm=8 } -> x1 @@ -96,10 +96,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v60 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v59) block 16 start_pc=0 - v61 Phi { incoming=[b25:v53, b15:v59], kind=I64 } -> x1 + v61 Phi { incoming=[b22:v53, b15:v59], kind=I64 } -> x1 v62 LoadLocal { off=-5, kind=I64 } -> x0 v63 Imm(0) -> x0 - terminator Bnz { cond=v61, target=b26, fall=b17 } (exit_acc=v61) + terminator Bnz { cond=v61, target=b21, fall=b17 } (exit_acc=v61) block 17 start_pc=0 v64 ImmData(32) -> x0 v65 BinopI { op=add, lhs=v64, rhs_imm=12 } -> x1 @@ -108,7 +108,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v68 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v67) block 18 start_pc=0 - v69 Phi { incoming=[b26:v61, b17:v67], kind=I64 } -> x1 + v69 Phi { incoming=[b21:v61, b17:v67], kind=I64 } -> x1 v70 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v69, target=b20, fall=b19 } (exit_acc=v69) block 19 start_pc=0 @@ -118,17 +118,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v72 Imm(0) -> x0 terminator Return(v72) (exit_acc=v72) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 23 start_pc=0 - terminator Jmp(b10) - block 24 start_pc=0 terminator Jmp(b14) + block 24 start_pc=0 + terminator Jmp(b10) block 25 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 26 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/anonymous_aggregates.ssa b/tests/snapshots/ssa/anonymous_aggregates.ssa index 44e3b135b..31856e70e 100644 --- a/tests/snapshots/ssa/anonymous_aggregates.ssa +++ b/tests/snapshots/ssa/anonymous_aggregates.ssa @@ -5,11 +5,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 LocalAddr(-1) -> x0 v4 Imm(1311768467294899695) -> x1 v5 Store { addr=v3, disp=0, value=v4, kind=I64 } -> - @@ -17,40 +14,40 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v7 Load { addr=v6, disp=0, kind=U32 } -> x0 v8 Imm(2427178479) -> x1 v9 BinopI { op=ne, lhs=v7, rhs_imm=2427178479 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) - block 3 start_pc=0 + terminator Bz { cond=v9, target=b3, fall=b2 } (exit_acc=v9) + block 2 start_pc=0 v10 Imm(2) -> x0 terminator Return(v10) (exit_acc=v10) - block 4 start_pc=0 + block 3 start_pc=0 v11 LocalAddr(-1) -> x0 v12 BinopI { op=add, lhs=v11, rhs_imm=4 } -> x1 v13 Load { addr=v11, disp=4, kind=I32 } -> x0 v14 Imm(305419896) -> x1 v15 BinopI { op=ne, lhs=v13, rhs_imm=305419896 } -> x0 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) - block 5 start_pc=0 + terminator Bz { cond=v15, target=b5, fall=b4 } (exit_acc=v15) + block 4 start_pc=0 v16 Imm(3) -> x0 terminator Return(v16) (exit_acc=v16) - block 6 start_pc=0 + block 5 start_pc=0 v17 LocalAddr(-1) -> x0 v18 Load { addr=v17, disp=0, kind=U32 } -> x0 v19 Imm(2427178479) -> x1 v20 BinopI { op=ne, lhs=v18, rhs_imm=2427178479 } -> x0 - terminator Bz { cond=v20, target=b8, fall=b7 } (exit_acc=v20) - block 7 start_pc=0 + terminator Bz { cond=v20, target=b7, fall=b6 } (exit_acc=v20) + block 6 start_pc=0 v21 Imm(4) -> x0 terminator Return(v21) (exit_acc=v21) - block 8 start_pc=0 + block 7 start_pc=0 v22 LocalAddr(-1) -> x0 v23 BinopI { op=add, lhs=v22, rhs_imm=4 } -> x1 v24 Load { addr=v22, disp=4, kind=I32 } -> x0 v25 Imm(305419896) -> x1 v26 BinopI { op=ne, lhs=v24, rhs_imm=305419896 } -> x0 - terminator Bz { cond=v26, target=b10, fall=b9 } (exit_acc=v26) - block 9 start_pc=0 + terminator Bz { cond=v26, target=b9, fall=b8 } (exit_acc=v26) + block 8 start_pc=0 v27 Imm(5) -> x0 terminator Return(v27) (exit_acc=v27) - block 10 start_pc=0 + block 9 start_pc=0 v28 LocalAddr(-1) -> x0 v29 Imm(3405691582) -> x1 v30 Store { addr=v28, disp=0, value=v29, kind=I32 } -> - @@ -61,30 +58,30 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v35 LocalAddr(-1) -> x0 v36 Load { addr=v35, disp=0, kind=U32 } -> x0 v37 BinopI { op=ne, lhs=v36, rhs_imm=3405691582 } -> x0 - terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) - block 11 start_pc=0 + terminator Bz { cond=v37, target=b11, fall=b10 } (exit_acc=v37) + block 10 start_pc=0 v38 Imm(6) -> x0 terminator Return(v38) (exit_acc=v38) - block 12 start_pc=0 + block 11 start_pc=0 v39 LocalAddr(-1) -> x0 v40 BinopI { op=add, lhs=v39, rhs_imm=4 } -> x1 v41 Load { addr=v39, disp=4, kind=I32 } -> x0 v42 Imm(195948557) -> x1 v43 BinopI { op=ne, lhs=v41, rhs_imm=195948557 } -> x0 - terminator Bz { cond=v43, target=b14, fall=b13 } (exit_acc=v43) - block 13 start_pc=0 + terminator Bz { cond=v43, target=b13, fall=b12 } (exit_acc=v43) + block 12 start_pc=0 v44 Imm(7) -> x0 terminator Return(v44) (exit_acc=v44) - block 14 start_pc=0 + block 13 start_pc=0 v45 LocalAddr(-1) -> x0 v46 Load { addr=v45, disp=0, kind=I64 } -> x0 v47 Imm(841592647419083454) -> x1 v48 BinopI { op=ne, lhs=v46, rhs_imm=841592647419083454 } -> x0 - terminator Bz { cond=v48, target=b16, fall=b15 } (exit_acc=v48) - block 15 start_pc=0 + terminator Bz { cond=v48, target=b15, fall=b14 } (exit_acc=v48) + block 14 start_pc=0 v49 Imm(8) -> x0 terminator Return(v49) (exit_acc=v49) - block 16 start_pc=0 + block 15 start_pc=0 v50 LocalAddr(-4) -> x0 v51 Imm(1) -> x1 v52 Store { addr=v50, disp=0, value=v51, kind=I32 } -> - @@ -99,29 +96,29 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v61 LocalAddr(-4) -> x0 v62 Load { addr=v61, disp=0, kind=I32 } -> x0 v63 BinopI { op=ne, lhs=v62, rhs_imm=1 } -> x0 - terminator Bz { cond=v63, target=b18, fall=b17 } (exit_acc=v63) - block 17 start_pc=0 + terminator Bz { cond=v63, target=b17, fall=b16 } (exit_acc=v63) + block 16 start_pc=0 v64 Imm(10) -> x0 terminator Return(v64) (exit_acc=v64) - block 18 start_pc=0 + block 17 start_pc=0 v65 LocalAddr(-4) -> x0 v66 BinopI { op=add, lhs=v65, rhs_imm=8 } -> x1 v67 Load { addr=v65, disp=8, kind=I32 } -> x0 v68 BinopI { op=ne, lhs=v67, rhs_imm=42 } -> x0 - terminator Bz { cond=v68, target=b20, fall=b19 } (exit_acc=v68) - block 19 start_pc=0 + terminator Bz { cond=v68, target=b19, fall=b18 } (exit_acc=v68) + block 18 start_pc=0 v69 Imm(11) -> x0 terminator Return(v69) (exit_acc=v69) - block 20 start_pc=0 + block 19 start_pc=0 v70 LocalAddr(-4) -> x0 v71 BinopI { op=add, lhs=v70, rhs_imm=16 } -> x1 v72 Load { addr=v70, disp=16, kind=I32 } -> x0 v73 BinopI { op=ne, lhs=v72, rhs_imm=99 } -> x0 - terminator Bz { cond=v73, target=b22, fall=b21 } (exit_acc=v73) - block 21 start_pc=0 + terminator Bz { cond=v73, target=b21, fall=b20 } (exit_acc=v73) + block 20 start_pc=0 v74 Imm(12) -> x0 terminator Return(v74) (exit_acc=v74) - block 22 start_pc=0 + block 21 start_pc=0 v75 LocalAddr(-4) -> x0 v76 BinopI { op=add, lhs=v75, rhs_imm=8 } -> x1 v77 Imm(4614253070214989087) -> x1 @@ -129,26 +126,23 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v79 LocalAddr(-4) -> x0 v80 Load { addr=v79, disp=0, kind=I32 } -> x0 v81 BinopI { op=ne, lhs=v80, rhs_imm=1 } -> x0 - terminator Bz { cond=v81, target=b24, fall=b23 } (exit_acc=v81) - block 23 start_pc=0 + terminator Bz { cond=v81, target=b23, fall=b22 } (exit_acc=v81) + block 22 start_pc=0 v82 Imm(13) -> x0 terminator Return(v82) (exit_acc=v82) - block 24 start_pc=0 + block 23 start_pc=0 v83 LocalAddr(-4) -> x0 v84 BinopI { op=add, lhs=v83, rhs_imm=16 } -> x1 v85 Load { addr=v83, disp=16, kind=I32 } -> x0 v86 BinopI { op=ne, lhs=v85, rhs_imm=99 } -> x0 - terminator Bz { cond=v86, target=b26, fall=b25 } (exit_acc=v86) - block 25 start_pc=0 + terminator Bz { cond=v86, target=b25, fall=b24 } (exit_acc=v86) + block 24 start_pc=0 v87 Imm(14) -> x0 terminator Return(v87) (exit_acc=v87) - block 26 start_pc=0 + block 25 start_pc=0 v88 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v88) - block 27 start_pc=0 - v89 Imm(20) -> x0 - terminator Return(v89) (exit_acc=v89) - block 28 start_pc=0 + terminator Jmp(b26) (exit_acc=v88) + block 26 start_pc=0 v90 LocalAddr(-6) -> x0 v91 Imm(10) -> x1 v92 Store { addr=v90, disp=0, value=v91, kind=I32 } -> - @@ -167,38 +161,38 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v105 LocalAddr(-6) -> x0 v106 Load { addr=v105, disp=0, kind=I32 } -> x0 v107 BinopI { op=ne, lhs=v106, rhs_imm=10 } -> x0 - terminator Bz { cond=v107, target=b30, fall=b29 } (exit_acc=v107) - block 29 start_pc=0 + terminator Bz { cond=v107, target=b28, fall=b27 } (exit_acc=v107) + block 27 start_pc=0 v108 Imm(21) -> x0 terminator Return(v108) (exit_acc=v108) - block 30 start_pc=0 + block 28 start_pc=0 v109 LocalAddr(-6) -> x0 v110 BinopI { op=add, lhs=v109, rhs_imm=4 } -> x1 v111 Load { addr=v109, disp=4, kind=I32 } -> x0 v112 BinopI { op=ne, lhs=v111, rhs_imm=20 } -> x0 - terminator Bz { cond=v112, target=b32, fall=b31 } (exit_acc=v112) - block 31 start_pc=0 + terminator Bz { cond=v112, target=b30, fall=b29 } (exit_acc=v112) + block 29 start_pc=0 v113 Imm(22) -> x0 terminator Return(v113) (exit_acc=v113) - block 32 start_pc=0 + block 30 start_pc=0 v114 LocalAddr(-6) -> x0 v115 BinopI { op=add, lhs=v114, rhs_imm=8 } -> x1 v116 Load { addr=v114, disp=8, kind=I32 } -> x0 v117 BinopI { op=ne, lhs=v116, rhs_imm=30 } -> x0 - terminator Bz { cond=v117, target=b34, fall=b33 } (exit_acc=v117) - block 33 start_pc=0 + terminator Bz { cond=v117, target=b32, fall=b31 } (exit_acc=v117) + block 31 start_pc=0 v118 Imm(23) -> x0 terminator Return(v118) (exit_acc=v118) - block 34 start_pc=0 + block 32 start_pc=0 v119 LocalAddr(-6) -> x0 v120 BinopI { op=add, lhs=v119, rhs_imm=12 } -> x1 v121 Load { addr=v119, disp=12, kind=I32 } -> x0 v122 BinopI { op=ne, lhs=v121, rhs_imm=40 } -> x0 - terminator Bz { cond=v122, target=b36, fall=b35 } (exit_acc=v122) - block 35 start_pc=0 + terminator Bz { cond=v122, target=b34, fall=b33 } (exit_acc=v122) + block 33 start_pc=0 v123 Imm(24) -> x0 terminator Return(v123) (exit_acc=v123) - block 36 start_pc=0 + block 34 start_pc=0 v124 LocalAddr(-8) -> x0 v125 Imm(7) -> x1 v126 Store { addr=v124, disp=0, value=v125, kind=I32 } -> - @@ -219,56 +213,56 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v141 LocalAddr(-8) -> x0 v142 Load { addr=v141, disp=0, kind=I32 } -> x0 v143 BinopI { op=ne, lhs=v142, rhs_imm=7 } -> x0 - terminator Bz { cond=v143, target=b38, fall=b37 } (exit_acc=v143) - block 37 start_pc=0 + terminator Bz { cond=v143, target=b36, fall=b35 } (exit_acc=v143) + block 35 start_pc=0 v144 Imm(30) -> x0 terminator Return(v144) (exit_acc=v144) - block 38 start_pc=0 + block 36 start_pc=0 v145 LocalAddr(-8) -> x0 v146 BinopI { op=add, lhs=v145, rhs_imm=4 } -> x1 v147 Load { addr=v145, disp=4, kind=I16 } -> x0 v148 BinopI { op=ne, lhs=v147, rhs_imm=4660 } -> x0 - terminator Bz { cond=v148, target=b40, fall=b39 } (exit_acc=v148) - block 39 start_pc=0 + terminator Bz { cond=v148, target=b38, fall=b37 } (exit_acc=v148) + block 37 start_pc=0 v149 Imm(31) -> x0 terminator Return(v149) (exit_acc=v149) - block 40 start_pc=0 + block 38 start_pc=0 v150 LocalAddr(-8) -> x0 v151 BinopI { op=add, lhs=v150, rhs_imm=6 } -> x1 v152 Load { addr=v150, disp=6, kind=I16 } -> x0 v153 Imm(22136) -> x1 v154 Imm(6230730084467081216) -> x1 v155 BinopI { op=ne, lhs=v152, rhs_imm=22136 } -> x0 - terminator Bz { cond=v155, target=b42, fall=b41 } (exit_acc=v155) - block 41 start_pc=0 + terminator Bz { cond=v155, target=b40, fall=b39 } (exit_acc=v155) + block 39 start_pc=0 v156 Imm(32) -> x0 terminator Return(v156) (exit_acc=v156) - block 42 start_pc=0 + block 40 start_pc=0 v157 LocalAddr(-8) -> x0 v158 BinopI { op=add, lhs=v157, rhs_imm=8 } -> x1 v159 Load { addr=v157, disp=8, kind=I32 } -> x0 v160 BinopI { op=ne, lhs=v159, rhs_imm=9 } -> x0 - terminator Bz { cond=v160, target=b44, fall=b43 } (exit_acc=v160) - block 43 start_pc=0 + terminator Bz { cond=v160, target=b42, fall=b41 } (exit_acc=v160) + block 41 start_pc=0 v161 Imm(33) -> x0 terminator Return(v161) (exit_acc=v161) - block 44 start_pc=0 + block 42 start_pc=0 v162 Imm(4660) -> x0 v163 Imm(22136) -> x0 v164 Imm(1450704896) -> x0 v165 Imm(1450709556) -> x0 - v166 Imm(0) -> x1 - v167 LocalAddr(-8) -> x1 - v168 BinopI { op=add, lhs=v167, rhs_imm=4 } -> x2 - v169 Load { addr=v167, disp=4, kind=I32 } -> x1 - v170 BinopI { op=and, lhs=v169, rhs_imm=4294967295 } -> x1 - v171 LoadLocal { off=-9, kind=U32 } -> x2 - v172 Binop { op=ne, lhs=v170, rhs=v165 } -> x0 - terminator Bz { cond=v172, target=b46, fall=b45 } (exit_acc=v172) - block 45 start_pc=0 + v166 Imm(0) -> x0 + v167 LocalAddr(-8) -> x0 + v168 BinopI { op=add, lhs=v167, rhs_imm=4 } -> x1 + v169 Load { addr=v167, disp=4, kind=I32 } -> x0 + v170 BinopI { op=and, lhs=v169, rhs_imm=4294967295 } -> x0 + v171 LoadLocal { off=-9, kind=U32 } -> x1 + v172 BinopI { op=ne, lhs=v170, rhs_imm=1450709556 } -> x0 + terminator Bz { cond=v172, target=b44, fall=b43 } (exit_acc=v172) + block 43 start_pc=0 v173 Imm(34) -> x0 terminator Return(v173) (exit_acc=v173) - block 46 start_pc=0 + block 44 start_pc=0 v174 LocalAddr(-11) -> x0 v175 Imm(88) -> x1 v176 Store { addr=v174, disp=0, value=v175, kind=I8 } -> - @@ -300,58 +294,64 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v202 LocalAddr(-11) -> x0 v203 Load { addr=v202, disp=0, kind=I8 } -> x0 v204 BinopI { op=ne, lhs=v203, rhs_imm=88 } -> x0 - terminator Bz { cond=v204, target=b48, fall=b47 } (exit_acc=v204) - block 47 start_pc=0 + terminator Bz { cond=v204, target=b46, fall=b45 } (exit_acc=v204) + block 45 start_pc=0 v205 Imm(40) -> x0 terminator Return(v205) (exit_acc=v205) - block 48 start_pc=0 + block 46 start_pc=0 v206 LocalAddr(-11) -> x0 v207 BinopI { op=add, lhs=v206, rhs_imm=1 } -> x1 v208 Load { addr=v206, disp=1, kind=I8 } -> x0 v209 BinopI { op=ne, lhs=v208, rhs_imm=97 } -> x0 - terminator Bz { cond=v209, target=b50, fall=b49 } (exit_acc=v209) - block 49 start_pc=0 + terminator Bz { cond=v209, target=b48, fall=b47 } (exit_acc=v209) + block 47 start_pc=0 v210 Imm(41) -> x0 terminator Return(v210) (exit_acc=v210) - block 50 start_pc=0 + block 48 start_pc=0 v211 LocalAddr(-11) -> x0 v212 BinopI { op=add, lhs=v211, rhs_imm=2 } -> x1 v213 Load { addr=v211, disp=2, kind=I8 } -> x0 v214 BinopI { op=ne, lhs=v213, rhs_imm=98 } -> x0 - terminator Bz { cond=v214, target=b52, fall=b51 } (exit_acc=v214) - block 51 start_pc=0 + terminator Bz { cond=v214, target=b50, fall=b49 } (exit_acc=v214) + block 49 start_pc=0 v215 Imm(42) -> x0 terminator Return(v215) (exit_acc=v215) - block 52 start_pc=0 + block 50 start_pc=0 v216 LocalAddr(-11) -> x0 v217 BinopI { op=add, lhs=v216, rhs_imm=3 } -> x1 v218 Load { addr=v216, disp=3, kind=I8 } -> x0 v219 BinopI { op=ne, lhs=v218, rhs_imm=99 } -> x0 - terminator Bz { cond=v219, target=b54, fall=b53 } (exit_acc=v219) - block 53 start_pc=0 + terminator Bz { cond=v219, target=b52, fall=b51 } (exit_acc=v219) + block 51 start_pc=0 v220 Imm(43) -> x0 terminator Return(v220) (exit_acc=v220) - block 54 start_pc=0 + block 52 start_pc=0 v221 LocalAddr(-11) -> x0 v222 BinopI { op=add, lhs=v221, rhs_imm=4 } -> x1 v223 Load { addr=v221, disp=4, kind=I8 } -> x0 v224 BinopI { op=ne, lhs=v223, rhs_imm=100 } -> x0 - terminator Bz { cond=v224, target=b56, fall=b55 } (exit_acc=v224) - block 55 start_pc=0 + terminator Bz { cond=v224, target=b54, fall=b53 } (exit_acc=v224) + block 53 start_pc=0 v225 Imm(44) -> x0 terminator Return(v225) (exit_acc=v225) - block 56 start_pc=0 + block 54 start_pc=0 v226 LocalAddr(-11) -> x0 v227 BinopI { op=add, lhs=v226, rhs_imm=8 } -> x1 v228 Load { addr=v226, disp=8, kind=I64 } -> x0 v229 BinopI { op=ne, lhs=v228, rhs_imm=1311768467463790320 } -> x0 - terminator Bz { cond=v229, target=b58, fall=b57 } (exit_acc=v229) - block 57 start_pc=0 + terminator Bz { cond=v229, target=b56, fall=b55 } (exit_acc=v229) + block 55 start_pc=0 v230 Imm(45) -> x0 terminator Return(v230) (exit_acc=v230) - block 58 start_pc=0 + block 56 start_pc=0 v231 Imm(0) -> x0 terminator Return(v231) (exit_acc=v231) + block 57 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 58 start_pc=0 + v89 Imm(20) -> x0 + terminator Return(v89) (exit_acc=v89) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/arg_register_cycle.ssa b/tests/snapshots/ssa/arg_register_cycle.ssa index 5ebf2cd4e..dac3fb2fa 100644 --- a/tests/snapshots/ssa/arg_register_cycle.ssa +++ b/tests/snapshots/ssa/arg_register_cycle.ssa @@ -24,10 +24,10 @@ fn ent_pc=0 n_params=3 variadic=false locals=3 v14 LoadLocal { off=3, kind=I32 } -> x0 v15 LoadLocal { off=2, kind=I32 } -> x0 v16 LoadLocal { off=4, kind=I32 } -> x0 - v17 BinopI { op=sub, lhs=v5, rhs_imm=1 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x2 - v20 Call { target_pc=0, args=[v3, v1, v19], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v17 BinopI { op=sub, lhs=v5, rhs_imm=1 } -> x2 + v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x0 + v19 Extend { value=v17, kind=I32 } -> x0 + v20 Call { target_pc=0, args=[v3, v1, v17], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 terminator Return(v20) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main diff --git a/tests/snapshots/ssa/array_2d_struct_init.ssa b/tests/snapshots/ssa/array_2d_struct_init.ssa index 8633b6d5e..157cf2fa8 100644 --- a/tests/snapshots/ssa/array_2d_struct_init.ssa +++ b/tests/snapshots/ssa/array_2d_struct_init.ssa @@ -11,7 +11,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v5 FpCast { kind=IntToFp, value=v4 } -> d1 v6 Binop { op=fne, lhs=v3, rhs=v5 } -> x1 v7 Imm(0) -> x2 - terminator Bnz { cond=v6, target=b21, fall=b1 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b27, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v8 ImmData(8) -> x1 v9 Imm(0) -> x1 @@ -26,11 +26,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v18 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 - v19 Phi { incoming=[b21:v4, b1:v17], kind=I64 } -> x6 + v19 Phi { incoming=[b27:v4, b1:v17], kind=I64 } -> x6 v20 LoadLocal { off=-3, kind=I64 } -> x1 v21 Imm(1) -> x2 v22 Imm(0) -> x1 - terminator Bnz { cond=v19, target=b22, fall=b3 } (exit_acc=v19) + terminator Bnz { cond=v19, target=b26, fall=b3 } (exit_acc=v19) block 3 start_pc=0 v23 ImmData(8) -> x1 v24 Imm(32) -> x1 @@ -44,10 +44,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v32 Imm(0) -> x1 terminator Jmp(b4) (exit_acc=v31) block 4 start_pc=0 - v33 Phi { incoming=[b22:v21, b3:v31], kind=I64 } -> x2 + v33 Phi { incoming=[b26:v21, b3:v31], kind=I64 } -> x2 v34 LoadLocal { off=-2, kind=I64 } -> x1 v35 Imm(0) -> x1 - terminator Bnz { cond=v33, target=b23, fall=b5 } (exit_acc=v33) + terminator Bnz { cond=v33, target=b25, fall=b5 } (exit_acc=v33) block 5 start_pc=0 v36 ImmData(8) -> x1 v37 Imm(32) -> x1 @@ -62,7 +62,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v46 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v45) block 6 start_pc=0 - v47 Phi { incoming=[b23:v33, b5:v45], kind=I64 } -> x2 + v47 Phi { incoming=[b25:v33, b5:v45], kind=I64 } -> x2 v48 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v47, target=b8, fall=b7 } (exit_acc=v47) block 7 start_pc=0 @@ -97,7 +97,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v71 Phi { incoming=[b24:v53, b9:v69], kind=I64 } -> x2 v72 LoadLocal { off=-5, kind=I64 } -> x0 v73 Imm(0) -> x0 - terminator Bnz { cond=v71, target=b25, fall=b11 } (exit_acc=v71) + terminator Bnz { cond=v71, target=b23, fall=b11 } (exit_acc=v71) block 11 start_pc=0 v74 ImmData(72) -> x0 v75 Imm(64) -> x1 @@ -112,7 +112,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v84 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v83) block 12 start_pc=0 - v85 Phi { incoming=[b25:v71, b11:v83], kind=I64 } -> x2 + v85 Phi { incoming=[b23:v71, b11:v83], kind=I64 } -> x2 v86 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v85, target=b14, fall=b13 } (exit_acc=v85) block 13 start_pc=0 @@ -127,7 +127,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v93 Binop { op=fne, lhs=v90, rhs=v92 } -> x0 v94 Imm(1) -> x2 v95 Imm(0) -> x1 - terminator Bnz { cond=v93, target=b26, fall=b15 } (exit_acc=v93) + terminator Bnz { cond=v93, target=b22, fall=b15 } (exit_acc=v93) block 15 start_pc=0 v96 ImmData(200) -> x0 v97 Imm(32) -> x1 @@ -142,10 +142,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v106 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v105) block 16 start_pc=0 - v107 Phi { incoming=[b26:v94, b15:v105], kind=I64 } -> x2 + v107 Phi { incoming=[b22:v94, b15:v105], kind=I64 } -> x2 v108 LoadLocal { off=-7, kind=I64 } -> x0 v109 Imm(0) -> x0 - terminator Bnz { cond=v107, target=b27, fall=b17 } (exit_acc=v107) + terminator Bnz { cond=v107, target=b21, fall=b17 } (exit_acc=v107) block 17 start_pc=0 v110 ImmData(200) -> x0 v111 Imm(0) -> x1 @@ -158,7 +158,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v118 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v117) block 18 start_pc=0 - v119 Phi { incoming=[b27:v107, b17:v117], kind=I64 } -> x2 + v119 Phi { incoming=[b21:v107, b17:v117], kind=I64 } -> x2 v120 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v119, target=b20, fall=b19 } (exit_acc=v119) block 19 start_pc=0 @@ -168,19 +168,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v122 Imm(0) -> x0 terminator Return(v122) (exit_acc=v122) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b16) block 23 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b12) block 24 start_pc=0 terminator Jmp(b10) block 25 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b6) block 26 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b4) block 27 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/array_compound_literal_static_init.ssa b/tests/snapshots/ssa/array_compound_literal_static_init.ssa index 8f3cad332..54bb81434 100644 --- a/tests/snapshots/ssa/array_compound_literal_static_init.ssa +++ b/tests/snapshots/ssa/array_compound_literal_static_init.ssa @@ -48,7 +48,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v30 Load { addr=v29, disp=0, kind=I8 } -> x1 v31 BinopI { op=ne, lhs=v30, rhs_imm=105 } -> x2 v32 Imm(0) -> x1 - terminator Bnz { cond=v31, target=b27, fall=b7 } (exit_acc=v31) + terminator Bnz { cond=v31, target=b28, fall=b7 } (exit_acc=v31) block 7 start_pc=0 v33 ImmData(168) -> x1 v34 Imm(8) -> x1 @@ -63,7 +63,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v43 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v42) block 8 start_pc=0 - v44 Phi { incoming=[b27:v31, b7:v42], kind=I64 } -> x2 + v44 Phi { incoming=[b28:v31, b7:v42], kind=I64 } -> x2 v45 LoadLocal { off=-1, kind=I64 } -> x1 terminator Bz { cond=v44, target=b10, fall=b9 } (exit_acc=v44) block 9 start_pc=0 @@ -149,7 +149,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v103 Load { addr=v100, disp=24, kind=I32 } -> x1 v104 BinopI { op=ne, lhs=v103, rhs_imm=0 } -> x2 v105 Imm(0) -> x1 - terminator Bnz { cond=v104, target=b28, fall=b21 } (exit_acc=v104) + terminator Bnz { cond=v104, target=b27, fall=b21 } (exit_acc=v104) block 21 start_pc=0 v106 ImmData(168) -> x1 v107 Imm(16) -> x1 @@ -161,7 +161,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v113 Imm(0) -> x1 terminator Jmp(b22) (exit_acc=v112) block 22 start_pc=0 - v114 Phi { incoming=[b28:v104, b21:v112], kind=I64 } -> x2 + v114 Phi { incoming=[b27:v104, b21:v112], kind=I64 } -> x2 v115 LoadLocal { off=-2, kind=I64 } -> x1 terminator Bz { cond=v114, target=b24, fall=b23 } (exit_acc=v114) block 23 start_pc=0 @@ -185,9 +185,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v127 Imm(0) -> x0 terminator Return(v127) (exit_acc=v127) block 27 start_pc=0 - terminator Jmp(b8) - block 28 start_pc=0 terminator Jmp(b22) + block 28 start_pc=0 + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/array_initializers.ssa b/tests/snapshots/ssa/array_initializers.ssa index 456f28e79..35f7c11e5 100644 --- a/tests/snapshots/ssa/array_initializers.ssa +++ b/tests/snapshots/ssa/array_initializers.ssa @@ -46,11 +46,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 terminator Return(v29) (exit_acc=v29) block 6 start_pc=0 v30 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v30) + terminator Jmp(b7) (exit_acc=v30) block 7 start_pc=0 - v31 Imm(4) -> x0 - terminator Return(v31) (exit_acc=v31) - block 8 start_pc=0 v32 ImmData(24) -> x0 v33 Imm(0) -> x1 v34 Load { addr=v32, disp=0, kind=I32 } -> x1 @@ -79,111 +76,105 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v57 BinopI { op=shl, lhs=v56, rhs_imm=32 } -> x1 v58 Extend { value=v56, kind=I32 } -> x0 v59 BinopI { op=ne, lhs=v58, rhs_imm=28 } -> x0 - terminator Bz { cond=v59, target=b10, fall=b9 } (exit_acc=v59) - block 9 start_pc=0 + terminator Bz { cond=v59, target=b9, fall=b8 } (exit_acc=v59) + block 8 start_pc=0 v60 Imm(5) -> x0 terminator Return(v60) (exit_acc=v60) - block 10 start_pc=0 + block 9 start_pc=0 v61 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v61) - block 11 start_pc=0 - v62 Imm(6) -> x0 - terminator Return(v62) (exit_acc=v62) - block 12 start_pc=0 + terminator Jmp(b10) (exit_acc=v61) + block 10 start_pc=0 v63 ImmData(48) -> x0 v64 Imm(0) -> x1 v65 Load { addr=v63, disp=0, kind=I8 } -> x0 v66 BinopI { op=ne, lhs=v65, rhs_imm=104 } -> x0 - terminator Bz { cond=v66, target=b14, fall=b13 } (exit_acc=v66) - block 13 start_pc=0 + terminator Bz { cond=v66, target=b12, fall=b11 } (exit_acc=v66) + block 11 start_pc=0 v67 Imm(7) -> x0 terminator Return(v67) (exit_acc=v67) - block 14 start_pc=0 + block 12 start_pc=0 v68 ImmData(48) -> x0 v69 Imm(1) -> x1 v70 BinopI { op=add, lhs=v68, rhs_imm=1 } -> x1 v71 Load { addr=v68, disp=1, kind=I8 } -> x0 v72 BinopI { op=ne, lhs=v71, rhs_imm=105 } -> x0 - terminator Bz { cond=v72, target=b16, fall=b15 } (exit_acc=v72) - block 15 start_pc=0 + terminator Bz { cond=v72, target=b14, fall=b13 } (exit_acc=v72) + block 13 start_pc=0 v73 Imm(8) -> x0 terminator Return(v73) (exit_acc=v73) - block 16 start_pc=0 + block 14 start_pc=0 v74 ImmData(48) -> x0 v75 Imm(2) -> x1 v76 BinopI { op=add, lhs=v74, rhs_imm=2 } -> x1 v77 Load { addr=v74, disp=2, kind=I8 } -> x0 v78 BinopI { op=ne, lhs=v77, rhs_imm=0 } -> x0 - terminator Bz { cond=v78, target=b18, fall=b17 } (exit_acc=v78) - block 17 start_pc=0 + terminator Bz { cond=v78, target=b16, fall=b15 } (exit_acc=v78) + block 15 start_pc=0 v79 Imm(9) -> x0 terminator Return(v79) (exit_acc=v79) - block 18 start_pc=0 + block 16 start_pc=0 v80 ImmData(48) -> x0 v81 Imm(15) -> x1 v82 BinopI { op=add, lhs=v80, rhs_imm=15 } -> x1 v83 Load { addr=v80, disp=15, kind=I8 } -> x0 v84 BinopI { op=ne, lhs=v83, rhs_imm=0 } -> x0 - terminator Bz { cond=v84, target=b20, fall=b19 } (exit_acc=v84) - block 19 start_pc=0 + terminator Bz { cond=v84, target=b18, fall=b17 } (exit_acc=v84) + block 17 start_pc=0 v85 Imm(10) -> x0 terminator Return(v85) (exit_acc=v85) - block 20 start_pc=0 + block 18 start_pc=0 v86 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v86) - block 21 start_pc=0 - v87 Imm(11) -> x0 - terminator Return(v87) (exit_acc=v87) - block 22 start_pc=0 + terminator Jmp(b19) (exit_acc=v86) + block 19 start_pc=0 v88 ImmData(72) -> x0 v89 Imm(0) -> x1 v90 Load { addr=v88, disp=0, kind=I32 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=1 } -> x0 - terminator Bz { cond=v91, target=b24, fall=b23 } (exit_acc=v91) - block 23 start_pc=0 + terminator Bz { cond=v91, target=b21, fall=b20 } (exit_acc=v91) + block 20 start_pc=0 v92 Imm(12) -> x0 terminator Return(v92) (exit_acc=v92) - block 24 start_pc=0 + block 21 start_pc=0 v93 ImmData(72) -> x0 v94 Imm(8) -> x1 v95 BinopI { op=add, lhs=v93, rhs_imm=8 } -> x1 v96 Load { addr=v93, disp=8, kind=I32 } -> x0 v97 BinopI { op=ne, lhs=v96, rhs_imm=3 } -> x0 - terminator Bz { cond=v97, target=b26, fall=b25 } (exit_acc=v97) - block 25 start_pc=0 + terminator Bz { cond=v97, target=b23, fall=b22 } (exit_acc=v97) + block 22 start_pc=0 v98 Imm(13) -> x0 terminator Return(v98) (exit_acc=v98) - block 26 start_pc=0 + block 23 start_pc=0 v99 ImmData(72) -> x0 v100 Imm(12) -> x1 v101 BinopI { op=add, lhs=v99, rhs_imm=12 } -> x1 v102 Load { addr=v99, disp=12, kind=I32 } -> x0 v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x0 - terminator Bz { cond=v103, target=b28, fall=b27 } (exit_acc=v103) - block 27 start_pc=0 + terminator Bz { cond=v103, target=b25, fall=b24 } (exit_acc=v103) + block 24 start_pc=0 v104 Imm(14) -> x0 terminator Return(v104) (exit_acc=v104) - block 28 start_pc=0 + block 25 start_pc=0 v105 ImmData(72) -> x0 v106 Imm(16) -> x1 v107 BinopI { op=add, lhs=v105, rhs_imm=16 } -> x1 v108 Load { addr=v105, disp=16, kind=I32 } -> x0 v109 BinopI { op=ne, lhs=v108, rhs_imm=0 } -> x0 - terminator Bz { cond=v109, target=b30, fall=b29 } (exit_acc=v109) - block 29 start_pc=0 + terminator Bz { cond=v109, target=b27, fall=b26 } (exit_acc=v109) + block 26 start_pc=0 v110 Imm(15) -> x0 terminator Return(v110) (exit_acc=v110) - block 30 start_pc=0 + block 27 start_pc=0 v111 ImmData(120) -> x0 v112 Imm(0) -> x1 v113 Load { addr=v111, disp=0, kind=I64 } -> x0 v114 Load { addr=v113, disp=0, kind=I8 } -> x0 v115 BinopI { op=ne, lhs=v114, rhs_imm=97 } -> x0 - terminator Bz { cond=v115, target=b32, fall=b31 } (exit_acc=v115) - block 31 start_pc=0 + terminator Bz { cond=v115, target=b29, fall=b28 } (exit_acc=v115) + block 28 start_pc=0 v116 Imm(16) -> x0 terminator Return(v116) (exit_acc=v116) - block 32 start_pc=0 + block 29 start_pc=0 v117 ImmData(120) -> x0 v118 Imm(8) -> x1 v119 BinopI { op=add, lhs=v117, rhs_imm=8 } -> x1 @@ -191,11 +182,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v121 Imm(0) -> x1 v122 Load { addr=v120, disp=0, kind=I8 } -> x0 v123 BinopI { op=ne, lhs=v122, rhs_imm=98 } -> x0 - terminator Bz { cond=v123, target=b34, fall=b33 } (exit_acc=v123) - block 33 start_pc=0 + terminator Bz { cond=v123, target=b31, fall=b30 } (exit_acc=v123) + block 30 start_pc=0 v124 Imm(17) -> x0 terminator Return(v124) (exit_acc=v124) - block 34 start_pc=0 + block 31 start_pc=0 v125 ImmData(120) -> x0 v126 Imm(16) -> x1 v127 BinopI { op=add, lhs=v125, rhs_imm=16 } -> x1 @@ -204,46 +195,43 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v130 BinopI { op=add, lhs=v128, rhs_imm=4 } -> x1 v131 Load { addr=v128, disp=4, kind=I8 } -> x0 v132 BinopI { op=ne, lhs=v131, rhs_imm=97 } -> x0 - terminator Bz { cond=v132, target=b36, fall=b35 } (exit_acc=v132) - block 35 start_pc=0 + terminator Bz { cond=v132, target=b33, fall=b32 } (exit_acc=v132) + block 32 start_pc=0 v133 Imm(18) -> x0 terminator Return(v133) (exit_acc=v133) - block 36 start_pc=0 + block 33 start_pc=0 v134 LocalAddr(-1) -> x0 v135 Imm(0) -> x1 v136 Load { addr=v134, disp=0, kind=I8 } -> x0 v137 BinopI { op=ne, lhs=v136, rhs_imm=119 } -> x0 - terminator Bz { cond=v137, target=b38, fall=b37 } (exit_acc=v137) - block 37 start_pc=0 + terminator Bz { cond=v137, target=b35, fall=b34 } (exit_acc=v137) + block 34 start_pc=0 v138 Imm(19) -> x0 terminator Return(v138) (exit_acc=v138) - block 38 start_pc=0 + block 35 start_pc=0 v139 LocalAddr(-1) -> x0 v140 Imm(4) -> x1 v141 BinopI { op=add, lhs=v139, rhs_imm=4 } -> x1 v142 Load { addr=v139, disp=4, kind=I8 } -> x0 v143 BinopI { op=ne, lhs=v142, rhs_imm=100 } -> x0 - terminator Bz { cond=v143, target=b40, fall=b39 } (exit_acc=v143) - block 39 start_pc=0 + terminator Bz { cond=v143, target=b37, fall=b36 } (exit_acc=v143) + block 36 start_pc=0 v144 Imm(20) -> x0 terminator Return(v144) (exit_acc=v144) - block 40 start_pc=0 + block 37 start_pc=0 v145 LocalAddr(-1) -> x0 v146 Imm(5) -> x1 v147 BinopI { op=add, lhs=v145, rhs_imm=5 } -> x1 v148 Load { addr=v145, disp=5, kind=I8 } -> x0 v149 BinopI { op=ne, lhs=v148, rhs_imm=0 } -> x0 - terminator Bz { cond=v149, target=b42, fall=b41 } (exit_acc=v149) - block 41 start_pc=0 + terminator Bz { cond=v149, target=b39, fall=b38 } (exit_acc=v149) + block 38 start_pc=0 v150 Imm(21) -> x0 terminator Return(v150) (exit_acc=v150) - block 42 start_pc=0 + block 39 start_pc=0 v151 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v151) - block 43 start_pc=0 - v152 Imm(22) -> x0 - terminator Return(v152) (exit_acc=v152) - block 44 start_pc=0 + terminator Jmp(b40) (exit_acc=v151) + block 40 start_pc=0 v153 LocalAddr(-3) -> x0 v154 Imm(0) -> x1 v155 Load { addr=v153, disp=0, kind=I32 } -> x0 @@ -262,107 +250,119 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x1 v169 Extend { value=v167, kind=I32 } -> x0 v170 BinopI { op=ne, lhs=v169, rhs_imm=600 } -> x0 - terminator Bz { cond=v170, target=b46, fall=b45 } (exit_acc=v170) - block 45 start_pc=0 + terminator Bz { cond=v170, target=b42, fall=b41 } (exit_acc=v170) + block 41 start_pc=0 v171 Imm(23) -> x0 terminator Return(v171) (exit_acc=v171) - block 46 start_pc=0 + block 42 start_pc=0 v172 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v172) - block 47 start_pc=0 - v173 Imm(24) -> x0 - terminator Return(v173) (exit_acc=v173) - block 48 start_pc=0 + terminator Jmp(b43) (exit_acc=v172) + block 43 start_pc=0 v174 LocalAddr(-4) -> x0 v175 Imm(0) -> x1 v176 Load { addr=v174, disp=0, kind=I8 } -> x0 v177 BinopI { op=ne, lhs=v176, rhs_imm=111 } -> x0 - terminator Bz { cond=v177, target=b50, fall=b49 } (exit_acc=v177) - block 49 start_pc=0 + terminator Bz { cond=v177, target=b45, fall=b44 } (exit_acc=v177) + block 44 start_pc=0 v178 Imm(25) -> x0 terminator Return(v178) (exit_acc=v178) - block 50 start_pc=0 + block 45 start_pc=0 v179 LocalAddr(-4) -> x0 v180 Imm(1) -> x1 v181 BinopI { op=add, lhs=v179, rhs_imm=1 } -> x1 v182 Load { addr=v179, disp=1, kind=I8 } -> x0 v183 BinopI { op=ne, lhs=v182, rhs_imm=107 } -> x0 - terminator Bz { cond=v183, target=b52, fall=b51 } (exit_acc=v183) - block 51 start_pc=0 + terminator Bz { cond=v183, target=b47, fall=b46 } (exit_acc=v183) + block 46 start_pc=0 v184 Imm(26) -> x0 terminator Return(v184) (exit_acc=v184) - block 52 start_pc=0 + block 47 start_pc=0 v185 LocalAddr(-4) -> x0 v186 Imm(2) -> x1 v187 BinopI { op=add, lhs=v185, rhs_imm=2 } -> x1 v188 Load { addr=v185, disp=2, kind=I8 } -> x0 v189 BinopI { op=ne, lhs=v188, rhs_imm=0 } -> x0 - terminator Bz { cond=v189, target=b54, fall=b53 } (exit_acc=v189) - block 53 start_pc=0 + terminator Bz { cond=v189, target=b49, fall=b48 } (exit_acc=v189) + block 48 start_pc=0 v190 Imm(27) -> x0 terminator Return(v190) (exit_acc=v190) - block 54 start_pc=0 + block 49 start_pc=0 v191 LocalAddr(-7) -> x0 v192 Imm(0) -> x1 v193 Load { addr=v191, disp=0, kind=I32 } -> x0 v194 BinopI { op=ne, lhs=v193, rhs_imm=100 } -> x0 - terminator Bz { cond=v194, target=b56, fall=b55 } (exit_acc=v194) - block 55 start_pc=0 + terminator Bz { cond=v194, target=b51, fall=b50 } (exit_acc=v194) + block 50 start_pc=0 v195 Imm(28) -> x0 terminator Return(v195) (exit_acc=v195) - block 56 start_pc=0 + block 51 start_pc=0 v196 LocalAddr(-7) -> x0 v197 Imm(8) -> x1 v198 BinopI { op=add, lhs=v196, rhs_imm=8 } -> x1 v199 Load { addr=v196, disp=8, kind=I32 } -> x0 v200 BinopI { op=ne, lhs=v199, rhs_imm=300 } -> x0 - terminator Bz { cond=v200, target=b58, fall=b57 } (exit_acc=v200) - block 57 start_pc=0 + terminator Bz { cond=v200, target=b53, fall=b52 } (exit_acc=v200) + block 52 start_pc=0 v201 Imm(29) -> x0 terminator Return(v201) (exit_acc=v201) - block 58 start_pc=0 + block 53 start_pc=0 v202 LocalAddr(-7) -> x0 v203 Imm(12) -> x1 v204 BinopI { op=add, lhs=v202, rhs_imm=12 } -> x1 v205 Load { addr=v202, disp=12, kind=I32 } -> x0 v206 BinopI { op=ne, lhs=v205, rhs_imm=0 } -> x0 - terminator Bz { cond=v206, target=b60, fall=b59 } (exit_acc=v206) - block 59 start_pc=0 + terminator Bz { cond=v206, target=b55, fall=b54 } (exit_acc=v206) + block 54 start_pc=0 v207 Imm(30) -> x0 terminator Return(v207) (exit_acc=v207) - block 60 start_pc=0 + block 55 start_pc=0 v208 LocalAddr(-7) -> x0 v209 Imm(16) -> x1 v210 BinopI { op=add, lhs=v208, rhs_imm=16 } -> x1 v211 Load { addr=v208, disp=16, kind=I32 } -> x0 v212 BinopI { op=ne, lhs=v211, rhs_imm=0 } -> x0 - terminator Bz { cond=v212, target=b62, fall=b61 } (exit_acc=v212) - block 61 start_pc=0 + terminator Bz { cond=v212, target=b57, fall=b56 } (exit_acc=v212) + block 56 start_pc=0 v213 Imm(31) -> x0 terminator Return(v213) (exit_acc=v213) - block 62 start_pc=0 + block 57 start_pc=0 v214 LocalAddr(-4) -> x0 v215 Imm(3) -> x1 v216 BinopI { op=add, lhs=v214, rhs_imm=3 } -> x1 v217 Load { addr=v214, disp=3, kind=I8 } -> x0 v218 BinopI { op=ne, lhs=v217, rhs_imm=0 } -> x0 - terminator Bz { cond=v218, target=b64, fall=b63 } (exit_acc=v218) - block 63 start_pc=0 + terminator Bz { cond=v218, target=b59, fall=b58 } (exit_acc=v218) + block 58 start_pc=0 v219 Imm(32) -> x0 terminator Return(v219) (exit_acc=v219) - block 64 start_pc=0 + block 59 start_pc=0 v220 LocalAddr(-4) -> x0 v221 Imm(7) -> x1 v222 BinopI { op=add, lhs=v220, rhs_imm=7 } -> x1 v223 Load { addr=v220, disp=7, kind=I8 } -> x0 v224 BinopI { op=ne, lhs=v223, rhs_imm=0 } -> x0 - terminator Bz { cond=v224, target=b66, fall=b65 } (exit_acc=v224) - block 65 start_pc=0 + terminator Bz { cond=v224, target=b61, fall=b60 } (exit_acc=v224) + block 60 start_pc=0 v225 Imm(33) -> x0 terminator Return(v225) (exit_acc=v225) - block 66 start_pc=0 + block 61 start_pc=0 v226 Imm(0) -> x0 terminator Return(v226) (exit_acc=v226) + block 62 start_pc=0 + v31 Imm(4) -> x0 + terminator Return(v31) (exit_acc=v31) + block 63 start_pc=0 + v62 Imm(6) -> x0 + terminator Return(v62) (exit_acc=v62) + block 64 start_pc=0 + v87 Imm(11) -> x0 + terminator Return(v87) (exit_acc=v87) + block 65 start_pc=0 + v152 Imm(22) -> x0 + terminator Return(v152) (exit_acc=v152) + block 66 start_pc=0 + v173 Imm(24) -> x0 + terminator Return(v173) (exit_acc=v173) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/array_of_struct_brace_elision.ssa b/tests/snapshots/ssa/array_of_struct_brace_elision.ssa index 83e8a8ea5..a1ffb7f1f 100644 --- a/tests/snapshots/ssa/array_of_struct_brace_elision.ssa +++ b/tests/snapshots/ssa/array_of_struct_brace_elision.ssa @@ -9,7 +9,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v3 Load { addr=v1, disp=0, kind=I64 } -> x1 v4 BinopI { op=ne, lhs=v3, rhs_imm=1 } -> x2 v5 Imm(0) -> x1 - terminator Bnz { cond=v4, target=b21, fall=b1 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b27, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v6 ImmData(8) -> x1 v7 Imm(8) -> x1 @@ -19,7 +19,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b21:v4, b1:v10], kind=I64 } -> x2 + v12 Phi { incoming=[b27:v4, b1:v10], kind=I64 } -> x2 v13 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) block 3 start_pc=0 @@ -32,7 +32,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v18 BinopI { op=ne, lhs=v17, rhs_imm=1 } -> x0 v19 Imm(1) -> x2 v20 Imm(0) -> x1 - terminator Bnz { cond=v18, target=b22, fall=b5 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b26, fall=b5 } (exit_acc=v18) block 5 start_pc=0 v21 ImmData(24) -> x0 v22 Imm(0) -> x1 @@ -43,11 +43,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v27 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v28 Phi { incoming=[b22:v19, b5:v26], kind=I64 } -> x2 + v28 Phi { incoming=[b26:v19, b5:v26], kind=I64 } -> x2 v29 LoadLocal { off=-4, kind=I64 } -> x0 v30 Imm(1) -> x1 v31 Imm(0) -> x0 - terminator Bnz { cond=v28, target=b23, fall=b7 } (exit_acc=v28) + terminator Bnz { cond=v28, target=b25, fall=b7 } (exit_acc=v28) block 7 start_pc=0 v32 ImmData(24) -> x0 v33 Imm(8) -> x1 @@ -58,7 +58,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v38 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Phi { incoming=[b23:v30, b7:v37], kind=I64 } -> x1 + v39 Phi { incoming=[b25:v30, b7:v37], kind=I64 } -> x1 v40 LoadLocal { off=-3, kind=I64 } -> x0 v41 Imm(0) -> x0 terminator Bnz { cond=v39, target=b24, fall=b9 } (exit_acc=v39) @@ -85,7 +85,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v55 BinopI { op=ne, lhs=v54, rhs_imm=10 } -> x0 v56 Imm(1) -> x2 v57 Imm(0) -> x1 - terminator Bnz { cond=v55, target=b25, fall=b13 } (exit_acc=v55) + terminator Bnz { cond=v55, target=b23, fall=b13 } (exit_acc=v55) block 13 start_pc=0 v58 ImmData(40) -> x0 v59 Imm(0) -> x1 @@ -96,11 +96,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v64 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v63) block 14 start_pc=0 - v65 Phi { incoming=[b25:v56, b13:v63], kind=I64 } -> x2 + v65 Phi { incoming=[b23:v56, b13:v63], kind=I64 } -> x2 v66 LoadLocal { off=-7, kind=I64 } -> x0 v67 Imm(1) -> x1 v68 Imm(0) -> x0 - terminator Bnz { cond=v65, target=b26, fall=b15 } (exit_acc=v65) + terminator Bnz { cond=v65, target=b22, fall=b15 } (exit_acc=v65) block 15 start_pc=0 v69 ImmData(40) -> x0 v70 Imm(8) -> x1 @@ -111,10 +111,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v75 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v74) block 16 start_pc=0 - v76 Phi { incoming=[b26:v67, b15:v74], kind=I64 } -> x1 + v76 Phi { incoming=[b22:v67, b15:v74], kind=I64 } -> x1 v77 LoadLocal { off=-6, kind=I64 } -> x0 v78 Imm(0) -> x0 - terminator Bnz { cond=v76, target=b27, fall=b17 } (exit_acc=v76) + terminator Bnz { cond=v76, target=b21, fall=b17 } (exit_acc=v76) block 17 start_pc=0 v79 ImmData(40) -> x0 v80 Imm(8) -> x1 @@ -125,7 +125,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v85 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v84) block 18 start_pc=0 - v86 Phi { incoming=[b27:v76, b17:v84], kind=I64 } -> x1 + v86 Phi { incoming=[b21:v76, b17:v84], kind=I64 } -> x1 v87 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v86, target=b20, fall=b19 } (exit_acc=v86) block 19 start_pc=0 @@ -135,19 +135,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v89 Imm(0) -> x0 terminator Return(v89) (exit_acc=v89) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 23 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b14) block 24 start_pc=0 terminator Jmp(b10) block 25 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b8) block 26 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 27 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/array_range_designator.ssa b/tests/snapshots/ssa/array_range_designator.ssa index 63513624c..3e7a9d937 100644 --- a/tests/snapshots/ssa/array_range_designator.ssa +++ b/tests/snapshots/ssa/array_range_designator.ssa @@ -39,7 +39,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v21 Load { addr=v1, disp=16, kind=I32 } -> x1 v22 BinopI { op=ne, lhs=v21, rhs_imm=7 } -> x2 v23 Imm(0) -> x1 - terminator Bnz { cond=v22, target=b19, fall=b7 } (exit_acc=v22) + terminator Bnz { cond=v22, target=b21, fall=b7 } (exit_acc=v22) block 7 start_pc=0 v24 ImmData(8) -> x1 v25 Imm(36) -> x1 @@ -49,7 +49,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v29 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v28) block 8 start_pc=0 - v30 Phi { incoming=[b19:v22, b7:v28], kind=I64 } -> x2 + v30 Phi { incoming=[b21:v22, b7:v28], kind=I64 } -> x2 v31 LoadLocal { off=-1, kind=I64 } -> x1 terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) block 9 start_pc=0 @@ -85,7 +85,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v51 Load { addr=v1, disp=48, kind=I32 } -> x1 v52 BinopI { op=ne, lhs=v51, rhs_imm=9 } -> x2 v53 Imm(0) -> x1 - terminator Bnz { cond=v52, target=b21, fall=b15 } (exit_acc=v52) + terminator Bnz { cond=v52, target=b19, fall=b15 } (exit_acc=v52) block 15 start_pc=0 v54 ImmData(8) -> x1 v55 Imm(60) -> x1 @@ -95,7 +95,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v59 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v58) block 16 start_pc=0 - v60 Phi { incoming=[b21:v52, b15:v58], kind=I64 } -> x2 + v60 Phi { incoming=[b19:v52, b15:v58], kind=I64 } -> x2 v61 LoadLocal { off=-3, kind=I64 } -> x0 terminator Bz { cond=v60, target=b18, fall=b17 } (exit_acc=v60) block 17 start_pc=0 @@ -105,65 +105,85 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v63 Imm(0) -> x0 terminator Return(v63) (exit_acc=v63) block 19 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b16) block 20 start_pc=0 terminator Jmp(b12) block 21 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=dispatch -fn ent_pc=1 n_params=1 variadic=false locals=0 +fn ent_pc=1 n_params=1 variadic=false locals=1 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - v3 ImmData(72) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x1 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x1 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 - v9 BlockAddr(block=2) -> x1 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x1 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 - v13 BlockAddr(block=3) -> x1 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 Imm(24) -> x1 - v16 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 - v17 BlockAddr(block=3) -> x1 - v18 Store { addr=v3, disp=24, value=v17, kind=I64 } -> - - v19 Imm(32) -> x1 - v20 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 - v21 BlockAddr(block=3) -> x1 - v22 Store { addr=v3, disp=32, value=v21, kind=I64 } -> - - v23 Imm(40) -> x1 - v24 BinopI { op=add, lhs=v3, rhs_imm=40 } -> x1 - v25 BlockAddr(block=3) -> x1 - v26 Store { addr=v3, disp=40, value=v25, kind=I64 } -> - - v27 Imm(48) -> x1 - v28 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x1 - v29 BlockAddr(block=3) -> x1 - v30 Store { addr=v3, disp=48, value=v29, kind=I64 } -> - - v31 Imm(56) -> x1 - v32 BinopI { op=add, lhs=v3, rhs_imm=56 } -> x1 - v33 BlockAddr(block=3) -> x1 - v34 Store { addr=v3, disp=56, value=v33, kind=I64 } -> - - v35 LoadLocal { off=2, kind=I32 } -> x1 - v36 BinopI { op=shl, lhs=v35, rhs_imm=3 } -> x2 - v37 Binop { op=add, lhs=v3, rhs=v36 } -> x2 - v38 LoadIndexed { base=v3, index=v35, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v38) (exit_acc=v38) + v4 Imm(64) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=64 } -> x1 + v6 Load { addr=v3, disp=64, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v39 Imm(100) -> x0 - terminator Return(v39) (exit_acc=v39) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-1, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v40 Imm(200) -> x0 - terminator Return(v40) (exit_acc=v40) + v9 ImmData(72) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 BlockAddr(block=6) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I64 } -> - + v25 Imm(32) -> x1 + v26 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v27 BlockAddr(block=6) -> x1 + v28 Store { addr=v3, disp=32, value=v27, kind=I64 } -> - + v29 Imm(40) -> x1 + v30 BinopI { op=add, lhs=v3, rhs_imm=40 } -> x1 + v31 BlockAddr(block=6) -> x1 + v32 Store { addr=v3, disp=40, value=v31, kind=I64 } -> - + v33 Imm(48) -> x1 + v34 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x1 + v35 BlockAddr(block=6) -> x1 + v36 Store { addr=v3, disp=48, value=v35, kind=I64 } -> - + v37 Imm(56) -> x1 + v38 BinopI { op=add, lhs=v3, rhs_imm=56 } -> x1 + v39 BlockAddr(block=6) -> x1 + v40 Store { addr=v3, disp=56, value=v39, kind=I64 } -> - + v41 Imm(64) -> x1 + v42 BinopI { op=add, lhs=v3, rhs_imm=64 } -> x1 + v43 Imm(1) -> x1 + v44 Store { addr=v3, disp=64, value=v43, kind=I8 } -> - + v45 Imm(72057594037927936) -> x2 + v46 StoreLocal { off=-1, value=v43, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v46) block 3 start_pc=0 - v41 Imm(999) -> x0 - terminator Return(v41) (exit_acc=v41) + v47 LoadLocal { off=-1, kind=I64 } -> x1 + v48 ImmData(72) -> x1 + v49 LoadLocal { off=2, kind=I32 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=3 } -> x2 + v51 Binop { op=add, lhs=v3, rhs=v50 } -> x2 + v52 LoadIndexed { base=v3, index=v49, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v52) (exit_acc=v52) + block 4 start_pc=0 + v53 Imm(100) -> x0 + terminator Return(v53) (exit_acc=v53) + block 5 start_pc=0 + v54 Imm(200) -> x0 + terminator Return(v54) (exit_acc=v54) + block 6 start_pc=0 + v55 Imm(999) -> x0 + terminator Return(v55) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=2 diff --git a/tests/snapshots/ssa/array_typedef_dimensions_propagate.ssa b/tests/snapshots/ssa/array_typedef_dimensions_propagate.ssa index 581aa85d7..9126a9c05 100644 --- a/tests/snapshots/ssa/array_typedef_dimensions_propagate.ssa +++ b/tests/snapshots/ssa/array_typedef_dimensions_propagate.ssa @@ -9,37 +9,37 @@ fn ent_pc=0 n_params=0 variadic=false locals=192 v1 Imm(512) -> x0 v2 Imm(2199023255552) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(11) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(512) -> x0 v6 Imm(2199023255552) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(12) -> x0 - terminator Return(v8) (exit_acc=v8) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 v9 Imm(512) -> x0 v10 Imm(2199023255552) -> x0 v11 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v11) - block 5 start_pc=0 - v12 Imm(13) -> x0 - terminator Return(v12) (exit_acc=v12) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v11) + block 3 start_pc=0 v13 Imm(512) -> x0 v14 Imm(2199023255552) -> x0 v15 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v15) + terminator Jmp(b4) (exit_acc=v15) + block 4 start_pc=0 + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) + block 5 start_pc=0 + v4 Imm(11) -> x0 + terminator Return(v4) (exit_acc=v4) + block 6 start_pc=0 + v8 Imm(12) -> x0 + terminator Return(v8) (exit_acc=v8) block 7 start_pc=0 + v12 Imm(13) -> x0 + terminator Return(v12) (exit_acc=v12) + block 8 start_pc=0 v16 Imm(14) -> x0 terminator Return(v16) (exit_acc=v16) - block 8 start_pc=0 - v17 Imm(0) -> x0 - terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/arrays_basic.ssa b/tests/snapshots/ssa/arrays_basic.ssa index 6a3587e8b..300fbcdef 100644 --- a/tests/snapshots/ssa/arrays_basic.ssa +++ b/tests/snapshots/ssa/arrays_basic.ssa @@ -11,30 +11,30 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 v5 Imm(0) -> x1 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b2) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v25], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v19], kind=I64 } -> x0 - v10 Extend { value=v8, kind=I32 } -> x2 - v11 LoadLocal { off=3, kind=I32 } -> x8 - v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x2 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) - block 2 start_pc=0 - v13 Extend { value=v9, kind=I32 } -> x2 - v14 LoadLocal { off=2, kind=I64 } -> x2 + v13 Extend { value=v9, kind=I32 } -> x8 + v14 LoadLocal { off=2, kind=I64 } -> x8 v15 Extend { value=v8, kind=I32 } -> x1 - v16 BinopI { op=shl, lhs=v15, rhs_imm=2 } -> x2 - v17 Binop { op=add, lhs=v1, rhs=v16 } -> x2 - v18 LoadIndexed { base=v1, index=v15, scale=4, kind=I32 } -> x2 + v16 BinopI { op=shl, lhs=v10, rhs_imm=2 } -> x1 + v17 Binop { op=add, lhs=v1, rhs=v16 } -> x1 + v18 LoadIndexed { base=v1, index=v10, scale=4, kind=I32 } -> x1 v19 Binop { op=add, lhs=v9, rhs=v18 } -> x0 - v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x2 - v21 Extend { value=v19, kind=I32 } -> x2 - v22 Imm(0) -> x2 - v23 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x1 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x1 + v21 Extend { value=v19, kind=I32 } -> x1 + v22 Imm(0) -> x1 + v23 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x2 v25 Extend { value=v23, kind=I32 } -> x1 v26 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v25) + terminator Jmp(b2) (exit_acc=v25) + block 2 start_pc=0 + v8 Phi { incoming=[b0:v5, b1:v25], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b1:v19], kind=I64 } -> x0 + v10 Extend { value=v8, kind=I32 } -> x2 + v11 LoadLocal { off=3, kind=I32 } -> x8 + v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x8 + terminator Bnz { cond=v12, target=b1, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v27 Extend { value=v9, kind=I32 } -> x0 terminator Return(v27) (exit_acc=v27) @@ -44,343 +44,822 @@ fn ent_pc=1 n_params=0 variadic=false locals=16 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v17], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=5 } -> x0 - terminator Bz { cond=v5, target=b3, fall=b2 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-3) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(1) -> x1 + v10 Imm(4294967296) -> x1 + v11 Imm(1) -> x1 + v12 Store { addr=v8, disp=0, value=v11, kind=I32 } -> - + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(4294967296) -> x0 + v16 Imm(1) -> x0 + v17 Imm(0) -> x0 + v18 Imm(1) -> x0 + v19 Imm(1) -> x0 + v20 LocalAddr(-3) -> x0 + v21 Imm(1) -> x1 + v22 Imm(4) -> x1 + v23 BinopI { op=add, lhs=v20, rhs_imm=4 } -> x1 + v24 Imm(2) -> x1 + v25 Imm(8589934592) -> x1 + v26 Imm(2) -> x1 + v27 Store { addr=v20, disp=4, value=v26, kind=I32 } -> - + v28 Imm(1) -> x0 + v29 Imm(2) -> x0 + v30 Imm(8589934592) -> x0 + v31 Imm(2) -> x0 + v32 Imm(0) -> x0 + v33 Imm(2) -> x0 + v34 Imm(1) -> x0 + v35 LocalAddr(-3) -> x0 + v36 Imm(2) -> x1 + v37 Imm(8) -> x1 + v38 BinopI { op=add, lhs=v35, rhs_imm=8 } -> x1 + v39 Imm(3) -> x1 + v40 Imm(12884901888) -> x1 + v41 Imm(3) -> x1 + v42 Store { addr=v35, disp=8, value=v41, kind=I32 } -> - + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(12884901888) -> x0 + v46 Imm(3) -> x0 + v47 Imm(0) -> x0 + v48 Imm(3) -> x0 + v49 Imm(1) -> x0 + v50 LocalAddr(-3) -> x0 + v51 Imm(3) -> x1 + v52 Imm(12) -> x1 + v53 BinopI { op=add, lhs=v50, rhs_imm=12 } -> x1 + v54 Imm(4) -> x1 + v55 Imm(17179869184) -> x1 + v56 Imm(4) -> x1 + v57 Store { addr=v50, disp=12, value=v56, kind=I32 } -> - + v58 Imm(3) -> x0 + v59 Imm(4) -> x0 + v60 Imm(17179869184) -> x0 + v61 Imm(4) -> x0 + v62 Imm(0) -> x0 + v63 Imm(4) -> x0 + v64 Imm(1) -> x0 + v65 LocalAddr(-3) -> x0 + v66 Imm(4) -> x1 + v67 Imm(16) -> x1 + v68 BinopI { op=add, lhs=v65, rhs_imm=16 } -> x1 + v69 Imm(5) -> x1 + v70 Imm(21474836480) -> x1 + v71 Imm(5) -> x1 + v72 Store { addr=v65, disp=16, value=v71, kind=I32 } -> - + v73 Imm(4) -> x0 + v74 Imm(5) -> x0 + v75 Imm(21474836480) -> x0 + v76 Imm(5) -> x0 + v77 Imm(0) -> x0 + v78 Imm(5) -> x0 + v79 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v79) block 2 start_pc=0 - v6 LocalAddr(-3) -> x0 - v7 Extend { value=v3, kind=I32 } -> x2 - v8 BinopI { op=shl, lhs=v7, rhs_imm=2 } -> x6 - v9 Binop { op=add, lhs=v6, rhs=v8 } -> x6 - v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x6 - v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x7 - v12 Extend { value=v10, kind=I32 } -> x7 - v13 StoreIndexed { base=v6, index=v7, scale=4, value=v10, kind=I32 } -> - - v14 Extend { value=v3, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 - v17 Extend { value=v15, kind=I32 } -> x1 - v18 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v17) + v80 LocalAddr(-3) -> x7 + v81 Imm(5) -> x6 + v82 Call { target_pc=0, args=[v80, v81], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v83 BinopI { op=ne, lhs=v82, rhs_imm=15 } -> x0 + terminator Bz { cond=v83, target=b4, fall=b3 } (exit_acc=v83) block 3 start_pc=0 - v19 LocalAddr(-3) -> x7 - v20 Imm(5) -> x6 - v21 Call { target_pc=0, args=[v19, v20], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=15 } -> x0 - terminator Bz { cond=v22, target=b5, fall=b4 } (exit_acc=v22) + v84 Imm(1) -> x0 + terminator Return(v84) (exit_acc=v84) block 4 start_pc=0 - v23 Imm(1) -> x0 - terminator Return(v23) (exit_acc=v23) + v85 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v85) block 5 start_pc=0 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v24) + v87 Imm(0) -> x0 + v88 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v87) block 6 start_pc=0 - v25 Imm(2) -> x0 - terminator Return(v25) (exit_acc=v25) + v89 Imm(0) -> x0 + v90 Imm(1) -> x0 + v91 ImmData(24) -> x0 + v92 Imm(0) -> x1 + v93 Imm(0) -> x1 + v94 BinopI { op=add, lhs=v91, rhs_imm=0 } -> x0 + v95 Imm(0) -> x1 + v96 Imm(0) -> x1 + v97 Imm(0) -> x1 + v98 Store { addr=v94, disp=0, value=v97, kind=I32 } -> - + v99 Imm(0) -> x0 + v100 Imm(1) -> x0 + v101 Imm(4294967296) -> x0 + v102 Imm(1) -> x0 + v103 Imm(0) -> x0 + v104 Imm(1) -> x0 + v105 Imm(1) -> x0 + v106 ImmData(24) -> x0 + v107 Imm(1) -> x1 + v108 Imm(4) -> x1 + v109 BinopI { op=add, lhs=v106, rhs_imm=4 } -> x1 + v110 Imm(10) -> x1 + v111 Imm(42949672960) -> x1 + v112 Imm(10) -> x1 + v113 Store { addr=v106, disp=4, value=v112, kind=I32 } -> - + v114 Imm(1) -> x0 + v115 Imm(2) -> x0 + v116 Imm(8589934592) -> x0 + v117 Imm(2) -> x0 + v118 Imm(0) -> x0 + v119 Imm(2) -> x0 + v120 Imm(1) -> x0 + v121 ImmData(24) -> x0 + v122 Imm(2) -> x1 + v123 Imm(8) -> x1 + v124 BinopI { op=add, lhs=v121, rhs_imm=8 } -> x1 + v125 Imm(20) -> x1 + v126 Imm(85899345920) -> x1 + v127 Imm(20) -> x1 + v128 Store { addr=v121, disp=8, value=v127, kind=I32 } -> - + v129 Imm(2) -> x0 + v130 Imm(3) -> x0 + v131 Imm(12884901888) -> x0 + v132 Imm(3) -> x0 + v133 Imm(0) -> x0 + v134 Imm(3) -> x0 + v135 Imm(1) -> x0 + v136 ImmData(24) -> x0 + v137 Imm(3) -> x1 + v138 Imm(12) -> x1 + v139 BinopI { op=add, lhs=v136, rhs_imm=12 } -> x1 + v140 Imm(30) -> x1 + v141 Imm(128849018880) -> x1 + v142 Imm(30) -> x1 + v143 Store { addr=v136, disp=12, value=v142, kind=I32 } -> - + v144 Imm(3) -> x0 + v145 Imm(4) -> x0 + v146 Imm(17179869184) -> x0 + v147 Imm(4) -> x0 + v148 Imm(0) -> x0 + v149 Imm(4) -> x0 + v150 Imm(1) -> x0 + v151 ImmData(24) -> x0 + v152 Imm(4) -> x1 + v153 Imm(16) -> x1 + v154 BinopI { op=add, lhs=v151, rhs_imm=16 } -> x1 + v155 Imm(40) -> x1 + v156 Imm(171798691840) -> x1 + v157 Imm(40) -> x1 + v158 Store { addr=v151, disp=16, value=v157, kind=I32 } -> - + v159 Imm(4) -> x0 + v160 Imm(5) -> x0 + v161 Imm(21474836480) -> x0 + v162 Imm(5) -> x0 + v163 Imm(0) -> x0 + v164 Imm(5) -> x0 + v165 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v165) block 7 start_pc=0 - v26 Imm(0) -> x1 - v27 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v26) + v166 ImmData(24) -> x0 + v167 Imm(0) -> x1 + v168 Load { addr=v166, disp=0, kind=I32 } -> x1 + v169 Imm(4) -> x2 + v170 BinopI { op=add, lhs=v166, rhs_imm=4 } -> x2 + v171 Load { addr=v166, disp=4, kind=I32 } -> x2 + v172 Binop { op=add, lhs=v168, rhs=v171 } -> x1 + v173 BinopI { op=shl, lhs=v172, rhs_imm=32 } -> x2 + v174 Extend { value=v172, kind=I32 } -> x2 + v175 Imm(8) -> x2 + v176 BinopI { op=add, lhs=v166, rhs_imm=8 } -> x2 + v177 Load { addr=v166, disp=8, kind=I32 } -> x2 + v178 Binop { op=add, lhs=v172, rhs=v177 } -> x1 + v179 BinopI { op=shl, lhs=v178, rhs_imm=32 } -> x2 + v180 Extend { value=v178, kind=I32 } -> x2 + v181 Imm(12) -> x2 + v182 BinopI { op=add, lhs=v166, rhs_imm=12 } -> x2 + v183 Load { addr=v166, disp=12, kind=I32 } -> x2 + v184 Binop { op=add, lhs=v178, rhs=v183 } -> x1 + v185 BinopI { op=shl, lhs=v184, rhs_imm=32 } -> x2 + v186 Extend { value=v184, kind=I32 } -> x2 + v187 Imm(16) -> x2 + v188 BinopI { op=add, lhs=v166, rhs_imm=16 } -> x2 + v189 Load { addr=v166, disp=16, kind=I32 } -> x0 + v190 Binop { op=add, lhs=v184, rhs=v189 } -> x0 + v191 BinopI { op=shl, lhs=v190, rhs_imm=32 } -> x1 + v192 Extend { value=v190, kind=I32 } -> x0 + v193 BinopI { op=ne, lhs=v192, rhs_imm=100 } -> x0 + terminator Bz { cond=v193, target=b9, fall=b8 } (exit_acc=v193) block 8 start_pc=0 - v28 Phi { incoming=[b7:v26, b9:v42], kind=I64 } -> x1 - v29 Extend { value=v28, kind=I32 } -> x0 - v30 BinopI { op=lt, lhs=v29, rhs_imm=5 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v194 Imm(3) -> x0 + terminator Return(v194) (exit_acc=v194) block 9 start_pc=0 - v31 ImmData(24) -> x0 - v32 Extend { value=v28, kind=I32 } -> x2 - v33 BinopI { op=shl, lhs=v32, rhs_imm=2 } -> x6 - v34 Binop { op=add, lhs=v31, rhs=v33 } -> x6 - v35 BinopI { op=mul, lhs=v32, rhs_imm=10 } -> x6 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x7 - v37 Extend { value=v35, kind=I32 } -> x7 - v38 StoreIndexed { base=v31, index=v32, scale=4, value=v35, kind=I32 } -> - - v39 Extend { value=v28, kind=I32 } -> x0 - v40 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x0 - v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x1 - v42 Extend { value=v40, kind=I32 } -> x1 - v43 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v42) + v195 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v195) block 10 start_pc=0 - v44 ImmData(24) -> x0 - v45 Imm(0) -> x1 - v46 Load { addr=v44, disp=0, kind=I32 } -> x1 - v47 Imm(4) -> x2 - v48 BinopI { op=add, lhs=v44, rhs_imm=4 } -> x2 - v49 Load { addr=v44, disp=4, kind=I32 } -> x2 - v50 Binop { op=add, lhs=v46, rhs=v49 } -> x1 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x2 - v52 Extend { value=v50, kind=I32 } -> x2 - v53 Imm(8) -> x2 - v54 BinopI { op=add, lhs=v44, rhs_imm=8 } -> x2 - v55 Load { addr=v44, disp=8, kind=I32 } -> x2 - v56 Binop { op=add, lhs=v50, rhs=v55 } -> x1 - v57 BinopI { op=shl, lhs=v56, rhs_imm=32 } -> x2 - v58 Extend { value=v56, kind=I32 } -> x2 - v59 Imm(12) -> x2 - v60 BinopI { op=add, lhs=v44, rhs_imm=12 } -> x2 - v61 Load { addr=v44, disp=12, kind=I32 } -> x2 - v62 Binop { op=add, lhs=v56, rhs=v61 } -> x1 - v63 BinopI { op=shl, lhs=v62, rhs_imm=32 } -> x2 - v64 Extend { value=v62, kind=I32 } -> x2 - v65 Imm(16) -> x2 - v66 BinopI { op=add, lhs=v44, rhs_imm=16 } -> x2 - v67 Load { addr=v44, disp=16, kind=I32 } -> x0 - v68 Binop { op=add, lhs=v62, rhs=v67 } -> x0 - v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x1 - v70 Extend { value=v68, kind=I32 } -> x0 - v71 BinopI { op=ne, lhs=v70, rhs_imm=100 } -> x0 - terminator Bz { cond=v71, target=b12, fall=b11 } (exit_acc=v71) + v197 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v197) block 11 start_pc=0 - v72 Imm(3) -> x0 - terminator Return(v72) (exit_acc=v72) + v199 ImmData(48) -> x0 + v200 Imm(0) -> x1 + v201 Imm(104) -> x2 + v202 Store { addr=v199, disp=0, value=v201, kind=I8 } -> - + v203 Imm(7493989779944505344) -> x6 + v204 Imm(1) -> x6 + v205 BinopI { op=add, lhs=v199, rhs_imm=1 } -> x6 + v206 Imm(105) -> x6 + v207 Store { addr=v199, disp=1, value=v206, kind=I8 } -> - + v208 Imm(7566047373982433280) -> x6 + v209 Imm(2) -> x6 + v210 BinopI { op=add, lhs=v199, rhs_imm=2 } -> x6 + v211 Store { addr=v199, disp=2, value=v200, kind=I8 } -> - + v212 Extend { value=v201, kind=I8 } -> x0 + v213 BinopI { op=ne, lhs=v212, rhs_imm=104 } -> x0 + terminator Bz { cond=v213, target=b13, fall=b12 } (exit_acc=v213) block 12 start_pc=0 - v73 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v73) + v214 Imm(6) -> x0 + terminator Return(v214) (exit_acc=v214) block 13 start_pc=0 - v74 Imm(4) -> x0 - terminator Return(v74) (exit_acc=v74) + v215 ImmData(48) -> x0 + v216 Imm(1) -> x1 + v217 BinopI { op=add, lhs=v215, rhs_imm=1 } -> x1 + v218 Load { addr=v215, disp=1, kind=I8 } -> x0 + v219 BinopI { op=ne, lhs=v218, rhs_imm=105 } -> x0 + terminator Bz { cond=v219, target=b15, fall=b14 } (exit_acc=v219) block 14 start_pc=0 - v75 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v75) + v220 Imm(7) -> x0 + terminator Return(v220) (exit_acc=v220) block 15 start_pc=0 - v76 Imm(5) -> x0 - terminator Return(v76) (exit_acc=v76) + v221 ImmData(48) -> x0 + v222 Imm(2) -> x1 + v223 BinopI { op=add, lhs=v221, rhs_imm=2 } -> x1 + v224 Load { addr=v221, disp=2, kind=I8 } -> x0 + v225 BinopI { op=ne, lhs=v224, rhs_imm=0 } -> x0 + terminator Bz { cond=v225, target=b17, fall=b16 } (exit_acc=v225) block 16 start_pc=0 - v77 ImmData(48) -> x0 - v78 Imm(0) -> x1 - v79 Imm(104) -> x2 - v80 Store { addr=v77, disp=0, value=v79, kind=I8 } -> - - v81 Imm(7493989779944505344) -> x6 - v82 Imm(1) -> x6 - v83 BinopI { op=add, lhs=v77, rhs_imm=1 } -> x6 - v84 Imm(105) -> x6 - v85 Store { addr=v77, disp=1, value=v84, kind=I8 } -> - - v86 Imm(7566047373982433280) -> x6 - v87 Imm(2) -> x6 - v88 BinopI { op=add, lhs=v77, rhs_imm=2 } -> x6 - v89 Store { addr=v77, disp=2, value=v78, kind=I8 } -> - - v90 Extend { value=v79, kind=I8 } -> x0 - v91 BinopI { op=ne, lhs=v90, rhs_imm=104 } -> x0 - terminator Bz { cond=v91, target=b18, fall=b17 } (exit_acc=v91) + v226 Imm(8) -> x0 + terminator Return(v226) (exit_acc=v226) block 17 start_pc=0 - v92 Imm(6) -> x0 - terminator Return(v92) (exit_acc=v92) + v227 Imm(0) -> x0 + v228 Imm(0) -> x1 + terminator Jmp(b18) (exit_acc=v227) block 18 start_pc=0 - v93 ImmData(48) -> x0 - v94 Imm(1) -> x1 - v95 BinopI { op=add, lhs=v93, rhs_imm=1 } -> x1 - v96 Load { addr=v93, disp=1, kind=I8 } -> x0 - v97 BinopI { op=ne, lhs=v96, rhs_imm=105 } -> x0 - terminator Bz { cond=v97, target=b20, fall=b19 } (exit_acc=v97) + v229 Imm(0) -> x0 + v230 Imm(1) -> x0 + v231 LocalAddr(-8) -> x0 + v232 Imm(0) -> x1 + v233 Imm(0) -> x2 + v234 BinopI { op=add, lhs=v231, rhs_imm=0 } -> x0 + v235 Store { addr=v234, disp=0, value=v232, kind=I32 } -> - + v236 LocalAddr(-8) -> x0 + v237 Imm(0) -> x1 + v238 Imm(0) -> x1 + v239 BinopI { op=add, lhs=v236, rhs_imm=0 } -> x0 + v240 BinopI { op=add, lhs=v239, rhs_imm=4 } -> x1 + v241 Imm(0) -> x1 + v242 Imm(0) -> x1 + v243 Imm(0) -> x1 + v244 Store { addr=v239, disp=4, value=v243, kind=I32 } -> - + v245 Imm(0) -> x0 + v246 Imm(1) -> x0 + v247 Imm(4294967296) -> x0 + v248 Imm(1) -> x0 + v249 Imm(0) -> x0 + v250 Imm(1) -> x0 + v251 Imm(1) -> x0 + v252 LocalAddr(-8) -> x0 + v253 Imm(1) -> x1 + v254 Imm(8) -> x2 + v255 BinopI { op=add, lhs=v252, rhs_imm=8 } -> x2 + v256 Store { addr=v252, disp=8, value=v253, kind=I32 } -> - + v257 LocalAddr(-8) -> x0 + v258 Imm(1) -> x1 + v259 Imm(8) -> x1 + v260 BinopI { op=add, lhs=v257, rhs_imm=8 } -> x0 + v261 BinopI { op=add, lhs=v260, rhs_imm=4 } -> x1 + v262 Imm(100) -> x1 + v263 Imm(429496729600) -> x1 + v264 Imm(100) -> x1 + v265 Store { addr=v260, disp=4, value=v264, kind=I32 } -> - + v266 Imm(1) -> x0 + v267 Imm(2) -> x0 + v268 Imm(8589934592) -> x0 + v269 Imm(2) -> x0 + v270 Imm(0) -> x0 + v271 Imm(2) -> x0 + v272 Imm(1) -> x0 + v273 LocalAddr(-8) -> x0 + v274 Imm(2) -> x1 + v275 Imm(16) -> x2 + v276 BinopI { op=add, lhs=v273, rhs_imm=16 } -> x2 + v277 Store { addr=v273, disp=16, value=v274, kind=I32 } -> - + v278 LocalAddr(-8) -> x0 + v279 Imm(2) -> x1 + v280 Imm(16) -> x1 + v281 BinopI { op=add, lhs=v278, rhs_imm=16 } -> x0 + v282 BinopI { op=add, lhs=v281, rhs_imm=4 } -> x1 + v283 Imm(200) -> x1 + v284 Imm(858993459200) -> x1 + v285 Imm(200) -> x1 + v286 Store { addr=v281, disp=4, value=v285, kind=I32 } -> - + v287 Imm(2) -> x0 + v288 Imm(3) -> x0 + v289 Imm(12884901888) -> x0 + v290 Imm(3) -> x0 + v291 Imm(0) -> x0 + v292 Imm(3) -> x0 + v293 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v293) block 19 start_pc=0 - v98 Imm(7) -> x0 - terminator Return(v98) (exit_acc=v98) + v294 LocalAddr(-8) -> x0 + v295 Imm(0) -> x1 + v296 Load { addr=v294, disp=0, kind=I32 } -> x0 + v297 BinopI { op=ne, lhs=v296, rhs_imm=0 } -> x0 + terminator Bz { cond=v297, target=b21, fall=b20 } (exit_acc=v297) block 20 start_pc=0 - v99 ImmData(48) -> x0 - v100 Imm(2) -> x1 - v101 BinopI { op=add, lhs=v99, rhs_imm=2 } -> x1 - v102 Load { addr=v99, disp=2, kind=I8 } -> x0 - v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x0 - terminator Bz { cond=v103, target=b22, fall=b21 } (exit_acc=v103) + v298 Imm(9) -> x0 + terminator Return(v298) (exit_acc=v298) block 21 start_pc=0 - v104 Imm(8) -> x0 - terminator Return(v104) (exit_acc=v104) + v299 LocalAddr(-8) -> x0 + v300 Imm(8) -> x1 + v301 BinopI { op=add, lhs=v299, rhs_imm=8 } -> x1 + v302 Load { addr=v299, disp=8, kind=I32 } -> x0 + v303 BinopI { op=ne, lhs=v302, rhs_imm=1 } -> x0 + terminator Bz { cond=v303, target=b23, fall=b22 } (exit_acc=v303) block 22 start_pc=0 - v105 Imm(0) -> x1 - v106 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v105) + v304 Imm(10) -> x0 + terminator Return(v304) (exit_acc=v304) block 23 start_pc=0 - v107 Phi { incoming=[b22:v105, b24:v127], kind=I64 } -> x1 - v108 Extend { value=v107, kind=I32 } -> x0 - v109 BinopI { op=lt, lhs=v108, rhs_imm=3 } -> x0 - terminator Bz { cond=v109, target=b25, fall=b24 } (exit_acc=v109) + v305 LocalAddr(-8) -> x0 + v306 Imm(16) -> x1 + v307 BinopI { op=add, lhs=v305, rhs_imm=16 } -> x1 + v308 BinopI { op=add, lhs=v305, rhs_imm=20 } -> x1 + v309 Load { addr=v305, disp=20, kind=I32 } -> x0 + v310 BinopI { op=ne, lhs=v309, rhs_imm=200 } -> x0 + terminator Bz { cond=v310, target=b25, fall=b24 } (exit_acc=v310) block 24 start_pc=0 - v110 LocalAddr(-8) -> x0 - v111 Extend { value=v107, kind=I32 } -> x2 - v112 BinopI { op=shl, lhs=v111, rhs_imm=3 } -> x2 - v113 Binop { op=add, lhs=v110, rhs=v112 } -> x0 - v114 Store { addr=v113, disp=0, value=v107, kind=I32 } -> - - v115 LocalAddr(-8) -> x0 - v116 Extend { value=v107, kind=I32 } -> x2 - v117 BinopI { op=shl, lhs=v116, rhs_imm=3 } -> x6 - v118 Binop { op=add, lhs=v115, rhs=v117 } -> x0 - v119 BinopI { op=add, lhs=v118, rhs_imm=4 } -> x6 - v120 BinopI { op=mul, lhs=v116, rhs_imm=100 } -> x2 - v121 BinopI { op=shl, lhs=v120, rhs_imm=32 } -> x6 - v122 Extend { value=v120, kind=I32 } -> x6 - v123 Store { addr=v118, disp=4, value=v120, kind=I32 } -> - - v124 Extend { value=v107, kind=I32 } -> x0 - v125 BinopI { op=add, lhs=v107, rhs_imm=1 } -> x0 - v126 BinopI { op=shl, lhs=v125, rhs_imm=32 } -> x1 - v127 Extend { value=v125, kind=I32 } -> x1 - v128 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v127) + v311 Imm(11) -> x0 + terminator Return(v311) (exit_acc=v311) block 25 start_pc=0 - v129 LocalAddr(-8) -> x0 - v130 Imm(0) -> x1 - v131 Load { addr=v129, disp=0, kind=I32 } -> x0 - v132 BinopI { op=ne, lhs=v131, rhs_imm=0 } -> x0 - terminator Bz { cond=v132, target=b27, fall=b26 } (exit_acc=v132) + v312 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v312) block 26 start_pc=0 - v133 Imm(9) -> x0 - terminator Return(v133) (exit_acc=v133) + v314 LocalAddr(-13) -> x0 + v315 BinopI { op=add, lhs=v314, rhs_imm=32 } -> x1 + v316 Imm(0) -> x1 + v317 Store { addr=v314, disp=32, value=v316, kind=I32 } -> - + v318 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v316) block 27 start_pc=0 - v134 LocalAddr(-8) -> x0 - v135 Imm(8) -> x1 - v136 BinopI { op=add, lhs=v134, rhs_imm=8 } -> x1 - v137 Load { addr=v134, disp=8, kind=I32 } -> x0 - v138 BinopI { op=ne, lhs=v137, rhs_imm=1 } -> x0 - terminator Bz { cond=v138, target=b29, fall=b28 } (exit_acc=v138) + v319 Imm(0) -> x0 + v320 Imm(1) -> x0 + v321 LocalAddr(-13) -> x0 + v322 Imm(0) -> x1 + v323 Imm(0) -> x1 + v324 BinopI { op=add, lhs=v321, rhs_imm=0 } -> x0 + v325 Imm(1) -> x1 + v326 Imm(4294967296) -> x1 + v327 Imm(1) -> x1 + v328 Store { addr=v324, disp=0, value=v327, kind=I32 } -> - + v329 LocalAddr(-13) -> x0 + v330 BinopI { op=add, lhs=v329, rhs_imm=32 } -> x1 + v331 LocalAddr(-13) -> x1 + v332 BinopI { op=add, lhs=v331, rhs_imm=32 } -> x2 + v333 Load { addr=v331, disp=32, kind=I32 } -> x1 + v334 LocalAddr(-13) -> x2 + v335 Imm(0) -> x6 + v336 Imm(0) -> x6 + v337 BinopI { op=add, lhs=v334, rhs_imm=0 } -> x2 + v338 Load { addr=v337, disp=0, kind=I32 } -> x2 + v339 Binop { op=add, lhs=v333, rhs=v338 } -> x1 + v340 BinopI { op=shl, lhs=v339, rhs_imm=32 } -> x2 + v341 Extend { value=v339, kind=I32 } -> x2 + v342 Store { addr=v329, disp=32, value=v339, kind=I32 } -> - + v343 Imm(0) -> x0 + v344 Imm(1) -> x0 + v345 Imm(4294967296) -> x0 + v346 Imm(1) -> x0 + v347 Imm(0) -> x0 + v348 Imm(1) -> x0 + v349 Imm(1) -> x0 + v350 LocalAddr(-13) -> x0 + v351 Imm(1) -> x1 + v352 Imm(4) -> x1 + v353 BinopI { op=add, lhs=v350, rhs_imm=4 } -> x1 + v354 Imm(2) -> x1 + v355 Imm(8589934592) -> x1 + v356 Imm(2) -> x1 + v357 Store { addr=v350, disp=4, value=v356, kind=I32 } -> - + v358 LocalAddr(-13) -> x0 + v359 BinopI { op=add, lhs=v358, rhs_imm=32 } -> x1 + v360 LocalAddr(-13) -> x1 + v361 BinopI { op=add, lhs=v360, rhs_imm=32 } -> x2 + v362 Load { addr=v360, disp=32, kind=I32 } -> x1 + v363 LocalAddr(-13) -> x2 + v364 Imm(1) -> x6 + v365 Imm(4) -> x6 + v366 BinopI { op=add, lhs=v363, rhs_imm=4 } -> x6 + v367 Load { addr=v363, disp=4, kind=I32 } -> x2 + v368 Binop { op=add, lhs=v362, rhs=v367 } -> x1 + v369 BinopI { op=shl, lhs=v368, rhs_imm=32 } -> x2 + v370 Extend { value=v368, kind=I32 } -> x2 + v371 Store { addr=v358, disp=32, value=v368, kind=I32 } -> - + v372 Imm(1) -> x0 + v373 Imm(2) -> x0 + v374 Imm(8589934592) -> x0 + v375 Imm(2) -> x0 + v376 Imm(0) -> x0 + v377 Imm(2) -> x0 + v378 Imm(1) -> x0 + v379 LocalAddr(-13) -> x0 + v380 Imm(2) -> x1 + v381 Imm(8) -> x1 + v382 BinopI { op=add, lhs=v379, rhs_imm=8 } -> x1 + v383 Imm(3) -> x1 + v384 Imm(12884901888) -> x1 + v385 Imm(3) -> x1 + v386 Store { addr=v379, disp=8, value=v385, kind=I32 } -> - + v387 LocalAddr(-13) -> x0 + v388 BinopI { op=add, lhs=v387, rhs_imm=32 } -> x1 + v389 LocalAddr(-13) -> x1 + v390 BinopI { op=add, lhs=v389, rhs_imm=32 } -> x2 + v391 Load { addr=v389, disp=32, kind=I32 } -> x1 + v392 LocalAddr(-13) -> x2 + v393 Imm(2) -> x6 + v394 Imm(8) -> x6 + v395 BinopI { op=add, lhs=v392, rhs_imm=8 } -> x6 + v396 Load { addr=v392, disp=8, kind=I32 } -> x2 + v397 Binop { op=add, lhs=v391, rhs=v396 } -> x1 + v398 BinopI { op=shl, lhs=v397, rhs_imm=32 } -> x2 + v399 Extend { value=v397, kind=I32 } -> x2 + v400 Store { addr=v387, disp=32, value=v397, kind=I32 } -> - + v401 Imm(2) -> x0 + v402 Imm(3) -> x0 + v403 Imm(12884901888) -> x0 + v404 Imm(3) -> x0 + v405 Imm(0) -> x0 + v406 Imm(3) -> x0 + v407 Imm(1) -> x0 + v408 LocalAddr(-13) -> x0 + v409 Imm(3) -> x1 + v410 Imm(12) -> x1 + v411 BinopI { op=add, lhs=v408, rhs_imm=12 } -> x1 + v412 Imm(4) -> x1 + v413 Imm(17179869184) -> x1 + v414 Imm(4) -> x1 + v415 Store { addr=v408, disp=12, value=v414, kind=I32 } -> - + v416 LocalAddr(-13) -> x0 + v417 BinopI { op=add, lhs=v416, rhs_imm=32 } -> x1 + v418 LocalAddr(-13) -> x1 + v419 BinopI { op=add, lhs=v418, rhs_imm=32 } -> x2 + v420 Load { addr=v418, disp=32, kind=I32 } -> x1 + v421 LocalAddr(-13) -> x2 + v422 Imm(3) -> x6 + v423 Imm(12) -> x6 + v424 BinopI { op=add, lhs=v421, rhs_imm=12 } -> x6 + v425 Load { addr=v421, disp=12, kind=I32 } -> x2 + v426 Binop { op=add, lhs=v420, rhs=v425 } -> x1 + v427 BinopI { op=shl, lhs=v426, rhs_imm=32 } -> x2 + v428 Extend { value=v426, kind=I32 } -> x2 + v429 Store { addr=v416, disp=32, value=v426, kind=I32 } -> - + v430 Imm(3) -> x0 + v431 Imm(4) -> x0 + v432 Imm(17179869184) -> x0 + v433 Imm(4) -> x0 + v434 Imm(0) -> x0 + v435 Imm(4) -> x0 + v436 Imm(1) -> x0 + v437 LocalAddr(-13) -> x0 + v438 Imm(4) -> x1 + v439 Imm(16) -> x1 + v440 BinopI { op=add, lhs=v437, rhs_imm=16 } -> x1 + v441 Imm(5) -> x1 + v442 Imm(21474836480) -> x1 + v443 Imm(5) -> x1 + v444 Store { addr=v437, disp=16, value=v443, kind=I32 } -> - + v445 LocalAddr(-13) -> x0 + v446 BinopI { op=add, lhs=v445, rhs_imm=32 } -> x1 + v447 LocalAddr(-13) -> x1 + v448 BinopI { op=add, lhs=v447, rhs_imm=32 } -> x2 + v449 Load { addr=v447, disp=32, kind=I32 } -> x1 + v450 LocalAddr(-13) -> x2 + v451 Imm(4) -> x6 + v452 Imm(16) -> x6 + v453 BinopI { op=add, lhs=v450, rhs_imm=16 } -> x6 + v454 Load { addr=v450, disp=16, kind=I32 } -> x2 + v455 Binop { op=add, lhs=v449, rhs=v454 } -> x1 + v456 BinopI { op=shl, lhs=v455, rhs_imm=32 } -> x2 + v457 Extend { value=v455, kind=I32 } -> x2 + v458 Store { addr=v445, disp=32, value=v455, kind=I32 } -> - + v459 Imm(4) -> x0 + v460 Imm(5) -> x0 + v461 Imm(21474836480) -> x0 + v462 Imm(5) -> x0 + v463 Imm(0) -> x0 + v464 Imm(5) -> x0 + v465 Imm(1) -> x0 + v466 LocalAddr(-13) -> x0 + v467 Imm(5) -> x1 + v468 Imm(20) -> x1 + v469 BinopI { op=add, lhs=v466, rhs_imm=20 } -> x1 + v470 Imm(6) -> x1 + v471 Imm(25769803776) -> x1 + v472 Imm(6) -> x1 + v473 Store { addr=v466, disp=20, value=v472, kind=I32 } -> - + v474 LocalAddr(-13) -> x0 + v475 BinopI { op=add, lhs=v474, rhs_imm=32 } -> x1 + v476 LocalAddr(-13) -> x1 + v477 BinopI { op=add, lhs=v476, rhs_imm=32 } -> x2 + v478 Load { addr=v476, disp=32, kind=I32 } -> x1 + v479 LocalAddr(-13) -> x2 + v480 Imm(5) -> x6 + v481 Imm(20) -> x6 + v482 BinopI { op=add, lhs=v479, rhs_imm=20 } -> x6 + v483 Load { addr=v479, disp=20, kind=I32 } -> x2 + v484 Binop { op=add, lhs=v478, rhs=v483 } -> x1 + v485 BinopI { op=shl, lhs=v484, rhs_imm=32 } -> x2 + v486 Extend { value=v484, kind=I32 } -> x2 + v487 Store { addr=v474, disp=32, value=v484, kind=I32 } -> - + v488 Imm(5) -> x0 + v489 Imm(6) -> x0 + v490 Imm(25769803776) -> x0 + v491 Imm(6) -> x0 + v492 Imm(0) -> x0 + v493 Imm(6) -> x0 + v494 Imm(1) -> x0 + v495 LocalAddr(-13) -> x0 + v496 Imm(6) -> x1 + v497 Imm(24) -> x1 + v498 BinopI { op=add, lhs=v495, rhs_imm=24 } -> x1 + v499 Imm(7) -> x1 + v500 Imm(30064771072) -> x1 + v501 Imm(7) -> x1 + v502 Store { addr=v495, disp=24, value=v501, kind=I32 } -> - + v503 LocalAddr(-13) -> x0 + v504 BinopI { op=add, lhs=v503, rhs_imm=32 } -> x1 + v505 LocalAddr(-13) -> x1 + v506 BinopI { op=add, lhs=v505, rhs_imm=32 } -> x2 + v507 Load { addr=v505, disp=32, kind=I32 } -> x1 + v508 LocalAddr(-13) -> x2 + v509 Imm(6) -> x6 + v510 Imm(24) -> x6 + v511 BinopI { op=add, lhs=v508, rhs_imm=24 } -> x6 + v512 Load { addr=v508, disp=24, kind=I32 } -> x2 + v513 Binop { op=add, lhs=v507, rhs=v512 } -> x1 + v514 BinopI { op=shl, lhs=v513, rhs_imm=32 } -> x2 + v515 Extend { value=v513, kind=I32 } -> x2 + v516 Store { addr=v503, disp=32, value=v513, kind=I32 } -> - + v517 Imm(6) -> x0 + v518 Imm(7) -> x0 + v519 Imm(30064771072) -> x0 + v520 Imm(7) -> x0 + v521 Imm(0) -> x0 + v522 Imm(7) -> x0 + v523 Imm(1) -> x0 + v524 LocalAddr(-13) -> x0 + v525 Imm(7) -> x1 + v526 Imm(28) -> x1 + v527 BinopI { op=add, lhs=v524, rhs_imm=28 } -> x1 + v528 Imm(8) -> x1 + v529 Imm(34359738368) -> x1 + v530 Imm(8) -> x1 + v531 Store { addr=v524, disp=28, value=v530, kind=I32 } -> - + v532 LocalAddr(-13) -> x0 + v533 BinopI { op=add, lhs=v532, rhs_imm=32 } -> x1 + v534 LocalAddr(-13) -> x1 + v535 BinopI { op=add, lhs=v534, rhs_imm=32 } -> x2 + v536 Load { addr=v534, disp=32, kind=I32 } -> x1 + v537 LocalAddr(-13) -> x2 + v538 Imm(7) -> x6 + v539 Imm(28) -> x6 + v540 BinopI { op=add, lhs=v537, rhs_imm=28 } -> x6 + v541 Load { addr=v537, disp=28, kind=I32 } -> x2 + v542 Binop { op=add, lhs=v536, rhs=v541 } -> x1 + v543 BinopI { op=shl, lhs=v542, rhs_imm=32 } -> x2 + v544 Extend { value=v542, kind=I32 } -> x2 + v545 Store { addr=v532, disp=32, value=v542, kind=I32 } -> - + v546 Imm(7) -> x0 + v547 Imm(8) -> x0 + v548 Imm(34359738368) -> x0 + v549 Imm(8) -> x0 + v550 Imm(0) -> x0 + v551 Imm(8) -> x0 + v552 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v552) block 28 start_pc=0 - v139 Imm(10) -> x0 - terminator Return(v139) (exit_acc=v139) + v553 LocalAddr(-13) -> x0 + v554 BinopI { op=add, lhs=v553, rhs_imm=32 } -> x1 + v555 Load { addr=v553, disp=32, kind=I32 } -> x0 + v556 BinopI { op=ne, lhs=v555, rhs_imm=36 } -> x0 + terminator Bz { cond=v556, target=b30, fall=b29 } (exit_acc=v556) block 29 start_pc=0 - v140 LocalAddr(-8) -> x0 - v141 Imm(16) -> x1 - v142 BinopI { op=add, lhs=v140, rhs_imm=16 } -> x1 - v143 BinopI { op=add, lhs=v140, rhs_imm=20 } -> x1 - v144 Load { addr=v140, disp=20, kind=I32 } -> x0 - v145 BinopI { op=ne, lhs=v144, rhs_imm=200 } -> x0 - terminator Bz { cond=v145, target=b31, fall=b30 } (exit_acc=v145) + v557 Imm(13) -> x0 + terminator Return(v557) (exit_acc=v557) block 30 start_pc=0 - v146 Imm(11) -> x0 - terminator Return(v146) (exit_acc=v146) + v558 Imm(0) -> x0 + v559 Imm(0) -> x1 + terminator Jmp(b31) (exit_acc=v558) block 31 start_pc=0 - v147 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v147) + v560 Imm(0) -> x0 + v561 Imm(1) -> x0 + v562 LocalAddr(-14) -> x0 + v563 Imm(0) -> x1 + v564 BinopI { op=add, lhs=v562, rhs_imm=0 } -> x0 + v565 Imm(65) -> x1 + v566 Imm(65) -> x1 + v567 Imm(279172874240) -> x1 + v568 Imm(65) -> x1 + v569 Store { addr=v564, disp=0, value=v568, kind=I8 } -> - + v570 Imm(4683743612465315840) -> x0 + v571 Imm(65) -> x0 + v572 Imm(0) -> x0 + v573 Imm(1) -> x0 + v574 Imm(4294967296) -> x0 + v575 Imm(1) -> x0 + v576 Imm(0) -> x0 + v577 Imm(1) -> x0 + v578 Imm(1) -> x0 + v579 LocalAddr(-14) -> x0 + v580 Imm(1) -> x1 + v581 BinopI { op=add, lhs=v579, rhs_imm=1 } -> x1 + v582 Imm(65) -> x1 + v583 Imm(66) -> x1 + v584 Imm(283467841536) -> x1 + v585 Imm(66) -> x1 + v586 Store { addr=v579, disp=1, value=v585, kind=I8 } -> - + v587 Imm(4755801206503243776) -> x0 + v588 Imm(66) -> x0 + v589 Imm(1) -> x0 + v590 Imm(2) -> x0 + v591 Imm(8589934592) -> x0 + v592 Imm(2) -> x0 + v593 Imm(0) -> x0 + v594 Imm(2) -> x0 + v595 Imm(1) -> x0 + v596 LocalAddr(-14) -> x0 + v597 Imm(2) -> x1 + v598 BinopI { op=add, lhs=v596, rhs_imm=2 } -> x1 + v599 Imm(65) -> x1 + v600 Imm(67) -> x1 + v601 Imm(287762808832) -> x1 + v602 Imm(67) -> x1 + v603 Store { addr=v596, disp=2, value=v602, kind=I8 } -> - + v604 Imm(4827858800541171712) -> x0 + v605 Imm(67) -> x0 + v606 Imm(2) -> x0 + v607 Imm(3) -> x0 + v608 Imm(12884901888) -> x0 + v609 Imm(3) -> x0 + v610 Imm(0) -> x0 + v611 Imm(3) -> x0 + v612 Imm(1) -> x0 + v613 LocalAddr(-14) -> x0 + v614 Imm(3) -> x1 + v615 BinopI { op=add, lhs=v613, rhs_imm=3 } -> x1 + v616 Imm(65) -> x1 + v617 Imm(68) -> x1 + v618 Imm(292057776128) -> x1 + v619 Imm(68) -> x1 + v620 Store { addr=v613, disp=3, value=v619, kind=I8 } -> - + v621 Imm(4899916394579099648) -> x0 + v622 Imm(68) -> x0 + v623 Imm(3) -> x0 + v624 Imm(4) -> x0 + v625 Imm(17179869184) -> x0 + v626 Imm(4) -> x0 + v627 Imm(0) -> x0 + v628 Imm(4) -> x0 + v629 Imm(1) -> x0 + v630 LocalAddr(-14) -> x0 + v631 Imm(4) -> x1 + v632 BinopI { op=add, lhs=v630, rhs_imm=4 } -> x1 + v633 Imm(65) -> x1 + v634 Imm(69) -> x1 + v635 Imm(296352743424) -> x1 + v636 Imm(69) -> x1 + v637 Store { addr=v630, disp=4, value=v636, kind=I8 } -> - + v638 Imm(4971973988617027584) -> x0 + v639 Imm(69) -> x0 + v640 Imm(4) -> x0 + v641 Imm(5) -> x0 + v642 Imm(21474836480) -> x0 + v643 Imm(5) -> x0 + v644 Imm(0) -> x0 + v645 Imm(5) -> x0 + v646 Imm(1) -> x0 + v647 LocalAddr(-14) -> x0 + v648 Imm(5) -> x1 + v649 BinopI { op=add, lhs=v647, rhs_imm=5 } -> x1 + v650 Imm(65) -> x1 + v651 Imm(70) -> x1 + v652 Imm(300647710720) -> x1 + v653 Imm(70) -> x1 + v654 Store { addr=v647, disp=5, value=v653, kind=I8 } -> - + v655 Imm(5044031582654955520) -> x0 + v656 Imm(70) -> x0 + v657 Imm(5) -> x0 + v658 Imm(6) -> x0 + v659 Imm(25769803776) -> x0 + v660 Imm(6) -> x0 + v661 Imm(0) -> x0 + v662 Imm(6) -> x0 + v663 Imm(1) -> x0 + v664 LocalAddr(-14) -> x0 + v665 Imm(6) -> x1 + v666 BinopI { op=add, lhs=v664, rhs_imm=6 } -> x1 + v667 Imm(65) -> x1 + v668 Imm(71) -> x1 + v669 Imm(304942678016) -> x1 + v670 Imm(71) -> x1 + v671 Store { addr=v664, disp=6, value=v670, kind=I8 } -> - + v672 Imm(5116089176692883456) -> x0 + v673 Imm(71) -> x0 + v674 Imm(6) -> x0 + v675 Imm(7) -> x0 + v676 Imm(30064771072) -> x0 + v677 Imm(7) -> x0 + v678 Imm(0) -> x0 + v679 Imm(7) -> x0 + v680 Imm(1) -> x0 + v681 LocalAddr(-14) -> x0 + v682 Imm(7) -> x1 + v683 BinopI { op=add, lhs=v681, rhs_imm=7 } -> x1 + v684 Imm(65) -> x1 + v685 Imm(72) -> x1 + v686 Imm(309237645312) -> x1 + v687 Imm(72) -> x1 + v688 Store { addr=v681, disp=7, value=v687, kind=I8 } -> - + v689 Imm(5188146770730811392) -> x0 + v690 Imm(72) -> x0 + v691 Imm(7) -> x0 + v692 Imm(8) -> x0 + v693 Imm(34359738368) -> x0 + v694 Imm(8) -> x0 + v695 Imm(0) -> x0 + v696 Imm(8) -> x0 + v697 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v697) block 32 start_pc=0 - v148 Imm(12) -> x0 - terminator Return(v148) (exit_acc=v148) + v698 LocalAddr(-14) -> x0 + v699 Imm(0) -> x1 + v700 Load { addr=v698, disp=0, kind=I8 } -> x0 + v701 BinopI { op=ne, lhs=v700, rhs_imm=65 } -> x0 + terminator Bz { cond=v701, target=b34, fall=b33 } (exit_acc=v701) block 33 start_pc=0 - v149 LocalAddr(-13) -> x0 - v150 BinopI { op=add, lhs=v149, rhs_imm=32 } -> x1 - v151 Imm(0) -> x1 - v152 Store { addr=v149, disp=32, value=v151, kind=I32 } -> - - v153 Imm(0) -> x0 - terminator Jmp(b34) (exit_acc=v151) + v702 Imm(14) -> x0 + terminator Return(v702) (exit_acc=v702) block 34 start_pc=0 - v154 Phi { incoming=[b33:v151, b35:v182], kind=I64 } -> x1 - v155 Extend { value=v154, kind=I32 } -> x0 - v156 BinopI { op=lt, lhs=v155, rhs_imm=8 } -> x0 - terminator Bz { cond=v156, target=b36, fall=b35 } (exit_acc=v156) + v703 LocalAddr(-14) -> x0 + v704 Imm(7) -> x1 + v705 BinopI { op=add, lhs=v703, rhs_imm=7 } -> x1 + v706 Load { addr=v703, disp=7, kind=I8 } -> x0 + v707 BinopI { op=ne, lhs=v706, rhs_imm=72 } -> x0 + terminator Bz { cond=v707, target=b36, fall=b35 } (exit_acc=v707) block 35 start_pc=0 - v157 LocalAddr(-13) -> x0 - v158 Extend { value=v154, kind=I32 } -> x2 - v159 BinopI { op=shl, lhs=v158, rhs_imm=2 } -> x6 - v160 Binop { op=add, lhs=v157, rhs=v159 } -> x6 - v161 BinopI { op=add, lhs=v158, rhs_imm=1 } -> x6 - v162 BinopI { op=shl, lhs=v161, rhs_imm=32 } -> x7 - v163 Extend { value=v161, kind=I32 } -> x7 - v164 StoreIndexed { base=v157, index=v158, scale=4, value=v161, kind=I32 } -> - - v165 LocalAddr(-13) -> x0 - v166 BinopI { op=add, lhs=v165, rhs_imm=32 } -> x2 - v167 LocalAddr(-13) -> x2 - v168 BinopI { op=add, lhs=v167, rhs_imm=32 } -> x6 - v169 Load { addr=v167, disp=32, kind=I32 } -> x2 - v170 LocalAddr(-13) -> x6 - v171 Extend { value=v154, kind=I32 } -> x7 - v172 BinopI { op=shl, lhs=v171, rhs_imm=2 } -> x8 - v173 Binop { op=add, lhs=v170, rhs=v172 } -> x8 - v174 LoadIndexed { base=v170, index=v171, scale=4, kind=I32 } -> x6 - v175 Binop { op=add, lhs=v169, rhs=v174 } -> x2 - v176 BinopI { op=shl, lhs=v175, rhs_imm=32 } -> x6 - v177 Extend { value=v175, kind=I32 } -> x6 - v178 Store { addr=v165, disp=32, value=v175, kind=I32 } -> - - v179 Extend { value=v154, kind=I32 } -> x0 - v180 BinopI { op=add, lhs=v154, rhs_imm=1 } -> x0 - v181 BinopI { op=shl, lhs=v180, rhs_imm=32 } -> x1 - v182 Extend { value=v180, kind=I32 } -> x1 - v183 Imm(0) -> x0 - terminator Jmp(b34) (exit_acc=v182) + v708 Imm(15) -> x0 + terminator Return(v708) (exit_acc=v708) block 36 start_pc=0 - v184 LocalAddr(-13) -> x0 - v185 BinopI { op=add, lhs=v184, rhs_imm=32 } -> x1 - v186 Load { addr=v184, disp=32, kind=I32 } -> x0 - v187 BinopI { op=ne, lhs=v186, rhs_imm=36 } -> x0 - terminator Bz { cond=v187, target=b38, fall=b37 } (exit_acc=v187) + v709 LocalAddr(-3) -> x0 + v710 Imm(8) -> x1 + v711 BinopI { op=add, lhs=v709, rhs_imm=8 } -> x0 + v712 Imm(0) -> x1 + v713 LoadLocal { off=-15, kind=I64 } -> x1 + v714 Imm(0) -> x1 + v715 Load { addr=v711, disp=0, kind=I32 } -> x1 + v716 Imm(4) -> x2 + v717 BinopI { op=add, lhs=v711, rhs_imm=4 } -> x2 + v718 Load { addr=v711, disp=4, kind=I32 } -> x2 + v719 Binop { op=add, lhs=v715, rhs=v718 } -> x1 + v720 BinopI { op=shl, lhs=v719, rhs_imm=32 } -> x2 + v721 Extend { value=v719, kind=I32 } -> x2 + v722 BinopI { op=add, lhs=v711, rhs_imm=8 } -> x2 + v723 Load { addr=v711, disp=8, kind=I32 } -> x0 + v724 Binop { op=add, lhs=v719, rhs=v723 } -> x0 + v725 BinopI { op=shl, lhs=v724, rhs_imm=32 } -> x1 + v726 Extend { value=v724, kind=I32 } -> x0 + v727 Imm(0) -> x1 + v728 LoadLocal { off=-5, kind=I32 } -> x1 + v729 BinopI { op=ne, lhs=v726, rhs_imm=12 } -> x0 + terminator Bz { cond=v729, target=b38, fall=b37 } (exit_acc=v729) block 37 start_pc=0 - v188 Imm(13) -> x0 - terminator Return(v188) (exit_acc=v188) + v730 Imm(16) -> x0 + terminator Return(v730) (exit_acc=v730) block 38 start_pc=0 - v189 Imm(0) -> x1 - v190 Imm(0) -> x0 - terminator Jmp(b39) (exit_acc=v189) + v731 Imm(0) -> x0 + terminator Return(v731) (exit_acc=v731) block 39 start_pc=0 - v191 Phi { incoming=[b38:v189, b40:v207], kind=I64 } -> x1 - v192 Extend { value=v191, kind=I32 } -> x0 - v193 BinopI { op=lt, lhs=v192, rhs_imm=8 } -> x0 - terminator Bz { cond=v193, target=b41, fall=b40 } (exit_acc=v193) + v86 Imm(2) -> x0 + terminator Return(v86) (exit_acc=v86) block 40 start_pc=0 - v194 LocalAddr(-14) -> x0 - v195 Extend { value=v191, kind=I32 } -> x2 - v196 Binop { op=add, lhs=v194, rhs=v195 } -> x0 - v197 Imm(65) -> x6 - v198 BinopI { op=add, lhs=v195, rhs_imm=65 } -> x2 - v199 BinopI { op=shl, lhs=v198, rhs_imm=32 } -> x6 - v200 Extend { value=v198, kind=I32 } -> x6 - v201 Store { addr=v196, disp=0, value=v198, kind=I8 } -> - - v202 BinopI { op=shl, lhs=v198, rhs_imm=56 } -> x0 - v203 Extend { value=v200, kind=I8 } -> x0 - v204 Extend { value=v191, kind=I32 } -> x0 - v205 BinopI { op=add, lhs=v191, rhs_imm=1 } -> x0 - v206 BinopI { op=shl, lhs=v205, rhs_imm=32 } -> x1 - v207 Extend { value=v205, kind=I32 } -> x1 - v208 Imm(0) -> x0 - terminator Jmp(b39) (exit_acc=v207) + v196 Imm(4) -> x0 + terminator Return(v196) (exit_acc=v196) block 41 start_pc=0 - v209 LocalAddr(-14) -> x0 - v210 Imm(0) -> x1 - v211 Load { addr=v209, disp=0, kind=I8 } -> x0 - v212 BinopI { op=ne, lhs=v211, rhs_imm=65 } -> x0 - terminator Bz { cond=v212, target=b43, fall=b42 } (exit_acc=v212) + v198 Imm(5) -> x0 + terminator Return(v198) (exit_acc=v198) block 42 start_pc=0 - v213 Imm(14) -> x0 - terminator Return(v213) (exit_acc=v213) - block 43 start_pc=0 - v214 LocalAddr(-14) -> x0 - v215 Imm(7) -> x1 - v216 BinopI { op=add, lhs=v214, rhs_imm=7 } -> x1 - v217 Load { addr=v214, disp=7, kind=I8 } -> x0 - v218 BinopI { op=ne, lhs=v217, rhs_imm=72 } -> x0 - terminator Bz { cond=v218, target=b45, fall=b44 } (exit_acc=v218) - block 44 start_pc=0 - v219 Imm(15) -> x0 - terminator Return(v219) (exit_acc=v219) - block 45 start_pc=0 - v220 LocalAddr(-3) -> x0 - v221 Imm(8) -> x1 - v222 BinopI { op=add, lhs=v220, rhs_imm=8 } -> x0 - v223 Imm(0) -> x1 - v224 LoadLocal { off=-15, kind=I64 } -> x1 - v225 Imm(0) -> x1 - v226 Load { addr=v222, disp=0, kind=I32 } -> x1 - v227 Imm(4) -> x2 - v228 BinopI { op=add, lhs=v222, rhs_imm=4 } -> x2 - v229 Load { addr=v222, disp=4, kind=I32 } -> x2 - v230 Binop { op=add, lhs=v226, rhs=v229 } -> x1 - v231 BinopI { op=shl, lhs=v230, rhs_imm=32 } -> x2 - v232 Extend { value=v230, kind=I32 } -> x2 - v233 BinopI { op=add, lhs=v222, rhs_imm=8 } -> x2 - v234 Load { addr=v222, disp=8, kind=I32 } -> x0 - v235 Binop { op=add, lhs=v230, rhs=v234 } -> x0 - v236 BinopI { op=shl, lhs=v235, rhs_imm=32 } -> x1 - v237 Extend { value=v235, kind=I32 } -> x0 - v238 Imm(0) -> x1 - v239 LoadLocal { off=-5, kind=I32 } -> x1 - v240 BinopI { op=ne, lhs=v237, rhs_imm=12 } -> x0 - terminator Bz { cond=v240, target=b47, fall=b46 } (exit_acc=v240) - block 46 start_pc=0 - v241 Imm(16) -> x0 - terminator Return(v241) (exit_acc=v241) - block 47 start_pc=0 - v242 Imm(0) -> x0 - terminator Return(v242) (exit_acc=v242) + v313 Imm(12) -> x0 + terminator Return(v313) (exit_acc=v313) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/assign_expr_value_narrowed.ssa b/tests/snapshots/ssa/assign_expr_value_narrowed.ssa index 88b36f111..587eb27c8 100644 --- a/tests/snapshots/ssa/assign_expr_value_narrowed.ssa +++ b/tests/snapshots/ssa/assign_expr_value_narrowed.ssa @@ -11,56 +11,56 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v2 Imm(0) -> x0 v3 Imm(216172782113783808) -> x0 v4 Imm(3) -> x0 - v5 Imm(0) -> x1 - v6 LoadLocal { off=-1, kind=U32 } -> x1 - v7 BinopI { op=ne, lhs=v4, rhs_imm=3 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Imm(0) -> x0 + v6 LoadLocal { off=-1, kind=U32 } -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 Imm(305441741) -> x0 v10 Imm(0) -> x0 v11 Imm(-6067193122998190080) -> x0 v12 Imm(-21555) -> x0 - v13 Imm(0) -> x1 - v14 Imm(4294945741) -> x1 - v15 BinopI { op=and, lhs=v12, rhs_imm=4294967295 } -> x0 - v16 BinopI { op=ne, lhs=v15, rhs_imm=4294945741 } -> x0 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) - block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) - block 4 start_pc=0 + v13 Imm(0) -> x0 + v14 Imm(4294945741) -> x0 + v15 Imm(4294945741) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 v18 Imm(4861) -> x0 v19 Imm(0) -> x0 v20 Imm(253) -> x0 - v21 Imm(0) -> x1 - v22 LoadLocal { off=-1, kind=U32 } -> x1 - v23 BinopI { op=ne, lhs=v20, rhs_imm=253 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) + v21 Imm(0) -> x0 + v22 LoadLocal { off=-1, kind=U32 } -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v23) + block 3 start_pc=0 + v25 Imm(1234605616436508552) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-5, kind=I64 } -> x0 + v28 Imm(0) -> x0 + v29 Imm(8613134287346073600) -> x0 + v30 Imm(30600) -> x0 + v31 Imm(0) -> x0 + v32 Imm(136) -> x0 + v33 Imm(0) -> x0 + v34 Imm(136) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v35) + block 4 start_pc=0 + v37 Imm(0) -> x0 + terminator Return(v37) (exit_acc=v37) block 5 start_pc=0 - v24 Imm(3) -> x0 - terminator Return(v24) (exit_acc=v24) + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) block 6 start_pc=0 - v25 Imm(1234605616436508552) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-5, kind=I64 } -> x1 - v28 Imm(0) -> x1 - v29 BinopI { op=shl, lhs=v25, rhs_imm=48 } -> x1 - v30 Extend { value=v25, kind=I16 } -> x0 - v31 Imm(0) -> x1 - v32 BinopI { op=and, lhs=v30, rhs_imm=255 } -> x0 - v33 Imm(0) -> x1 - v34 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=136 } -> x0 - terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) + v17 Imm(2) -> x0 + terminator Return(v17) (exit_acc=v17) block 7 start_pc=0 + v24 Imm(3) -> x0 + terminator Return(v24) (exit_acc=v24) + block 8 start_pc=0 v36 Imm(4) -> x0 terminator Return(v36) (exit_acc=v36) - block 8 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/atomic_operand_in_working_regs.ssa b/tests/snapshots/ssa/atomic_operand_in_working_regs.ssa index e305ce019..71637c86a 100644 --- a/tests/snapshots/ssa/atomic_operand_in_working_regs.ssa +++ b/tests/snapshots/ssa/atomic_operand_in_working_regs.ssa @@ -96,21 +96,21 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 v10 Imm(0) -> x1 v11 LoadLocal { off=-1, kind=I64 } -> x1 v12 BinopI { op=eq, lhs=v9, rhs_imm=36 } -> x1 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + terminator Bz { cond=v12, target=b3, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v13) + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 + v19 Phi { incoming=[b1:v13, b3:v17], kind=I64 } -> x1 + v20 LoadLocal { off=-10, kind=I64 } -> x0 + terminator Return(v19) (exit_acc=v19) + block 3 start_pc=0 v15 LoadLocal { off=-1, kind=I64 } -> x1 v16 BinopI { op=shl, lhs=v9, rhs_imm=32 } -> x1 v17 Extend { value=v9, kind=I32 } -> x1 v18 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v17) - block 3 start_pc=0 - v19 Phi { incoming=[b1:v13, b2:v17], kind=I64 } -> x1 - v20 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Return(v19) (exit_acc=v19) + terminator Jmp(b2) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/atomic_rmw_ops.ssa b/tests/snapshots/ssa/atomic_rmw_ops.ssa index 13f42b4cb..d1658b4ab 100644 --- a/tests/snapshots/ssa/atomic_rmw_ops.ssa +++ b/tests/snapshots/ssa/atomic_rmw_ops.ssa @@ -11,14 +11,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v5 AtomicRmw { op=Add, addr=v3, value=v4, width=8 } -> x0 v6 BinopI { op=ne, lhs=v5, rhs_imm=10 } -> x1 v7 Imm(0) -> x0 - terminator Bnz { cond=v6, target=b55, fall=b1 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b65, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v8 LoadLocal { off=-1, kind=I64 } -> x0 v9 BinopI { op=ne, lhs=v8, rhs_imm=15 } -> x1 v10 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v11 Phi { incoming=[b55:v6, b1:v9], kind=I64 } -> x1 + v11 Phi { incoming=[b65:v6, b1:v9], kind=I64 } -> x1 v12 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) block 3 start_pc=0 @@ -30,14 +30,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v16 AtomicRmw { op=Sub, addr=v14, value=v15, width=8 } -> x0 v17 BinopI { op=ne, lhs=v16, rhs_imm=15 } -> x1 v18 Imm(0) -> x0 - terminator Bnz { cond=v17, target=b56, fall=b5 } (exit_acc=v17) + terminator Bnz { cond=v17, target=b64, fall=b5 } (exit_acc=v17) block 5 start_pc=0 v19 LoadLocal { off=-1, kind=I64 } -> x0 v20 BinopI { op=ne, lhs=v19, rhs_imm=12 } -> x1 v21 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v20) block 6 start_pc=0 - v22 Phi { incoming=[b56:v17, b5:v20], kind=I64 } -> x1 + v22 Phi { incoming=[b64:v17, b5:v20], kind=I64 } -> x1 v23 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) block 7 start_pc=0 @@ -49,14 +49,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v27 AtomicRmw { op=And, addr=v25, value=v26, width=8 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=12 } -> x1 v29 Imm(0) -> x0 - terminator Bnz { cond=v28, target=b57, fall=b9 } (exit_acc=v28) + terminator Bnz { cond=v28, target=b63, fall=b9 } (exit_acc=v28) block 9 start_pc=0 v30 LoadLocal { off=-1, kind=I64 } -> x0 v31 BinopI { op=ne, lhs=v30, rhs_imm=0 } -> x1 v32 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v31) block 10 start_pc=0 - v33 Phi { incoming=[b57:v28, b9:v31], kind=I64 } -> x1 + v33 Phi { incoming=[b63:v28, b9:v31], kind=I64 } -> x1 v34 LoadLocal { off=-8, kind=I64 } -> x0 terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) block 11 start_pc=0 @@ -68,14 +68,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v38 AtomicRmw { op=Or, addr=v36, value=v37, width=8 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x1 v40 Imm(0) -> x0 - terminator Bnz { cond=v39, target=b58, fall=b13 } (exit_acc=v39) + terminator Bnz { cond=v39, target=b62, fall=b13 } (exit_acc=v39) block 13 start_pc=0 v41 LoadLocal { off=-1, kind=I64 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=5 } -> x1 v43 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v42) block 14 start_pc=0 - v44 Phi { incoming=[b58:v39, b13:v42], kind=I64 } -> x1 + v44 Phi { incoming=[b62:v39, b13:v42], kind=I64 } -> x1 v45 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v44, target=b16, fall=b15 } (exit_acc=v44) block 15 start_pc=0 @@ -87,14 +87,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v49 AtomicRmw { op=Xor, addr=v47, value=v48, width=8 } -> x0 v50 BinopI { op=ne, lhs=v49, rhs_imm=5 } -> x1 v51 Imm(0) -> x0 - terminator Bnz { cond=v50, target=b59, fall=b17 } (exit_acc=v50) + terminator Bnz { cond=v50, target=b61, fall=b17 } (exit_acc=v50) block 17 start_pc=0 v52 LoadLocal { off=-1, kind=I64 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=3 } -> x1 v54 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v53) block 18 start_pc=0 - v55 Phi { incoming=[b59:v50, b17:v53], kind=I64 } -> x1 + v55 Phi { incoming=[b61:v50, b17:v53], kind=I64 } -> x1 v56 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v55, target=b20, fall=b19 } (exit_acc=v55) block 19 start_pc=0 @@ -153,14 +153,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v87 LoadLocal { off=-1, kind=I64 } -> x0 v88 BinopI { op=ne, lhs=v87, rhs_imm=7 } -> x1 v89 Imm(0) -> x0 - terminator Bnz { cond=v88, target=b61, fall=b31 } (exit_acc=v88) + terminator Bnz { cond=v88, target=b59, fall=b31 } (exit_acc=v88) block 31 start_pc=0 v90 LoadLocal { off=-2, kind=I64 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=7 } -> x1 v92 Imm(0) -> x0 terminator Jmp(b32) (exit_acc=v91) block 32 start_pc=0 - v93 Phi { incoming=[b61:v88, b31:v91], kind=I64 } -> x1 + v93 Phi { incoming=[b59:v88, b31:v91], kind=I64 } -> x1 v94 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v93, target=b34, fall=b33 } (exit_acc=v93) block 33 start_pc=0 @@ -176,14 +176,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v102 Extend { value=v100, kind=I32 } -> x0 v103 BinopI { op=ne, lhs=v102, rhs_imm=4 } -> x1 v104 Imm(0) -> x0 - terminator Bnz { cond=v103, target=b62, fall=b35 } (exit_acc=v103) + terminator Bnz { cond=v103, target=b58, fall=b35 } (exit_acc=v103) block 35 start_pc=0 v105 LoadLocal { off=-3, kind=I32 } -> x0 v106 BinopI { op=ne, lhs=v105, rhs_imm=5 } -> x1 v107 Imm(0) -> x0 terminator Jmp(b36) (exit_acc=v106) block 36 start_pc=0 - v108 Phi { incoming=[b62:v103, b35:v106], kind=I64 } -> x1 + v108 Phi { incoming=[b58:v103, b35:v106], kind=I64 } -> x1 v109 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v108, target=b38, fall=b37 } (exit_acc=v108) block 37 start_pc=0 @@ -218,14 +218,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v128 Extend { value=v126, kind=I32 } -> x0 v129 BinopI { op=ne, lhs=v128, rhs_imm=12 } -> x1 v130 Imm(0) -> x0 - terminator Bnz { cond=v129, target=b63, fall=b43 } (exit_acc=v129) + terminator Bnz { cond=v129, target=b57, fall=b43 } (exit_acc=v129) block 43 start_pc=0 v131 LoadLocal { off=-5, kind=I32 } -> x0 v132 BinopI { op=ne, lhs=v131, rhs_imm=0 } -> x1 v133 Imm(0) -> x0 terminator Jmp(b44) (exit_acc=v132) block 44 start_pc=0 - v134 Phi { incoming=[b63:v129, b43:v132], kind=I64 } -> x1 + v134 Phi { incoming=[b57:v129, b43:v132], kind=I64 } -> x1 v135 LoadLocal { off=-14, kind=I64 } -> x0 terminator Bz { cond=v134, target=b46, fall=b45 } (exit_acc=v134) block 45 start_pc=0 @@ -239,14 +239,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v141 Extend { value=v139, kind=I32 } -> x0 v142 BinopI { op=ne, lhs=v141, rhs_imm=0 } -> x1 v143 Imm(0) -> x0 - terminator Bnz { cond=v142, target=b64, fall=b47 } (exit_acc=v142) + terminator Bnz { cond=v142, target=b56, fall=b47 } (exit_acc=v142) block 47 start_pc=0 v144 LoadLocal { off=-5, kind=I32 } -> x0 v145 BinopI { op=ne, lhs=v144, rhs_imm=5 } -> x1 v146 Imm(0) -> x0 terminator Jmp(b48) (exit_acc=v145) block 48 start_pc=0 - v147 Phi { incoming=[b64:v142, b47:v145], kind=I64 } -> x1 + v147 Phi { incoming=[b56:v142, b47:v145], kind=I64 } -> x1 v148 LoadLocal { off=-15, kind=I64 } -> x0 terminator Bz { cond=v147, target=b50, fall=b49 } (exit_acc=v147) block 49 start_pc=0 @@ -260,14 +260,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v154 Extend { value=v152, kind=I32 } -> x0 v155 BinopI { op=ne, lhs=v154, rhs_imm=5 } -> x1 v156 Imm(0) -> x0 - terminator Bnz { cond=v155, target=b65, fall=b51 } (exit_acc=v155) + terminator Bnz { cond=v155, target=b55, fall=b51 } (exit_acc=v155) block 51 start_pc=0 v157 LoadLocal { off=-5, kind=I32 } -> x0 v158 BinopI { op=ne, lhs=v157, rhs_imm=3 } -> x1 v159 Imm(0) -> x0 terminator Jmp(b52) (exit_acc=v158) block 52 start_pc=0 - v160 Phi { incoming=[b65:v155, b51:v158], kind=I64 } -> x1 + v160 Phi { incoming=[b55:v155, b51:v158], kind=I64 } -> x1 v161 LoadLocal { off=-16, kind=I64 } -> x0 terminator Bz { cond=v160, target=b54, fall=b53 } (exit_acc=v160) block 53 start_pc=0 @@ -277,27 +277,27 @@ fn ent_pc=0 n_params=0 variadic=false locals=16 v163 Imm(0) -> x0 terminator Return(v163) (exit_acc=v163) block 55 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b52) block 56 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b48) block 57 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b44) block 58 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b36) block 59 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b32) block 60 start_pc=0 terminator Jmp(b22) block 61 start_pc=0 - terminator Jmp(b32) + terminator Jmp(b18) block 62 start_pc=0 - terminator Jmp(b36) + terminator Jmp(b14) block 63 start_pc=0 - terminator Jmp(b44) + terminator Jmp(b10) block 64 start_pc=0 - terminator Jmp(b48) + terminator Jmp(b6) block 65 start_pc=0 - terminator Jmp(b52) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/attribute_c23.ssa b/tests/snapshots/ssa/attribute_c23.ssa index aab47dabe..7d02cd8f3 100644 --- a/tests/snapshots/ssa/attribute_c23.ssa +++ b/tests/snapshots/ssa/attribute_c23.ssa @@ -23,40 +23,40 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v6, target=b5, fall=b6 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b6, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b3:v13, b4:v16], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v8) (exit_acc=v8) + v19 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v19, target=b4, fall=b2 } (exit_acc=v19) block 2 start_pc=0 - v9 Imm(10) -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v9) + v16 Imm(-1) -> x0 + v17 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - v11 Phi { incoming=[b2:v9, b8:v3], kind=I64 } -> x1 + v7 Phi { incoming=[b5:v13, b2:v16], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + terminator Jmp(b5) + block 5 start_pc=0 + v11 Phi { incoming=[b7:v9, b4:v3], kind=I64 } -> x1 v12 Extend { value=v11, kind=I32 } -> x0 v13 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 v14 Imm(0) -> x1 v15 Extend { value=v13, kind=I32 } -> x1 - terminator Jmp(b1) (exit_acc=v15) - block 4 start_pc=0 - v16 Imm(-1) -> x0 - v17 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v16) - block 5 start_pc=0 - v18 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v18, target=b2, fall=b4 } (exit_acc=v18) + terminator Jmp(b3) (exit_acc=v15) block 6 start_pc=0 - v19 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v19, target=b8, fall=b4 } (exit_acc=v19) + v18 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v18, target=b2, fall=b7 } (exit_acc=v18) block 7 start_pc=0 - terminator Jmp(b2) + v9 Imm(10) -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 8 start_pc=0 - terminator Jmp(b3) + terminator Jmp(b7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 @@ -69,67 +69,61 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 v9 Imm(2) -> x2 v10 Store { addr=v8, disp=0, value=v9, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 LocalAddr(-3) -> x0 v13 Load { addr=v12, disp=0, kind=I8 } -> x0 - v14 BinopI { op=ne, lhs=v13, rhs_imm=1 } -> x3 + v14 BinopI { op=ne, lhs=v13, rhs_imm=1 } -> x1 v15 Imm(0) -> x0 - terminator Bnz { cond=v14, target=b19, fall=b3 } (exit_acc=v14) - block 3 start_pc=0 + terminator Bnz { cond=v14, target=b18, fall=b2 } (exit_acc=v14) + block 2 start_pc=0 v16 LocalAddr(-3) -> x0 v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x0 v18 Load { addr=v17, disp=0, kind=I64 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=2 } -> x3 + v19 BinopI { op=ne, lhs=v18, rhs_imm=2 } -> x1 v20 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v19) - block 4 start_pc=0 - v21 Phi { incoming=[b19:v14, b3:v19], kind=I64 } -> x3 + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v21 Phi { incoming=[b18:v14, b2:v19], kind=I64 } -> x1 v22 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bz { cond=v21, target=b5, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 + block 5 start_pc=0 v24 Imm(5) -> x0 - v25 Extend { value=v24, kind=I32 } -> x1 - v26 Imm(0) -> x1 - v27 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x0 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 - v29 Extend { value=v27, kind=I32 } -> x0 - v30 BinopI { op=ne, lhs=v29, rhs_imm=6 } -> x0 - terminator Bz { cond=v30, target=b8, fall=b7 } (exit_acc=v30) - block 7 start_pc=0 - v31 Imm(3) -> x0 - terminator Return(v31) (exit_acc=v31) - block 8 start_pc=0 + v25 Imm(5) -> x0 + v26 Imm(0) -> x0 + v27 Imm(6) -> x0 + v28 Imm(25769803776) -> x0 + v29 Imm(6) -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v30) + block 6 start_pc=0 v32 Imm(1) -> x7 v33 Call { target_pc=1, args=[v32], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v34 BinopI { op=ne, lhs=v33, rhs_imm=11 } -> x0 - terminator Bz { cond=v34, target=b10, fall=b9 } (exit_acc=v34) - block 9 start_pc=0 + terminator Bz { cond=v34, target=b8, fall=b7 } (exit_acc=v34) + block 7 start_pc=0 v35 Imm(4) -> x0 terminator Return(v35) (exit_acc=v35) - block 10 start_pc=0 + block 8 start_pc=0 v36 Imm(2) -> x7 v37 Call { target_pc=1, args=[v36], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v38 BinopI { op=ne, lhs=v37, rhs_imm=1 } -> x0 - terminator Bz { cond=v38, target=b12, fall=b11 } (exit_acc=v38) - block 11 start_pc=0 + terminator Bz { cond=v38, target=b10, fall=b9 } (exit_acc=v38) + block 9 start_pc=0 v39 Imm(5) -> x0 terminator Return(v39) (exit_acc=v39) - block 12 start_pc=0 + block 10 start_pc=0 v40 Imm(9) -> x7 v41 Call { target_pc=1, args=[v40], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=-1 } -> x0 - terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) - block 13 start_pc=0 + terminator Bz { cond=v42, target=b12, fall=b11 } (exit_acc=v42) + block 11 start_pc=0 v43 Imm(6) -> x0 terminator Return(v43) (exit_acc=v43) - block 14 start_pc=0 + block 12 start_pc=0 v44 LocalAddr(-4) -> x0 v45 Imm(7) -> x1 v46 Store { addr=v44, disp=0, value=v45, kind=I8 } -> - @@ -142,28 +136,34 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 v53 Load { addr=v52, disp=0, kind=I8 } -> x0 v54 BinopI { op=ne, lhs=v53, rhs_imm=7 } -> x1 v55 Imm(0) -> x0 - terminator Bnz { cond=v54, target=b20, fall=b15 } (exit_acc=v54) - block 15 start_pc=0 + terminator Bnz { cond=v54, target=b17, fall=b13 } (exit_acc=v54) + block 13 start_pc=0 v56 LocalAddr(-4) -> x0 v57 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x1 v58 Load { addr=v56, disp=4, kind=I32 } -> x0 v59 BinopI { op=ne, lhs=v58, rhs_imm=8 } -> x1 v60 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v59) - block 16 start_pc=0 - v61 Phi { incoming=[b20:v54, b15:v59], kind=I64 } -> x1 + terminator Jmp(b14) (exit_acc=v59) + block 14 start_pc=0 + v61 Phi { incoming=[b17:v54, b13:v59], kind=I64 } -> x1 v62 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v61, target=b18, fall=b17 } (exit_acc=v61) - block 17 start_pc=0 + terminator Bz { cond=v61, target=b16, fall=b15 } (exit_acc=v61) + block 15 start_pc=0 v63 Imm(7) -> x0 terminator Return(v63) (exit_acc=v63) - block 18 start_pc=0 + block 16 start_pc=0 v64 Imm(0) -> x0 terminator Return(v64) (exit_acc=v64) + block 17 start_pc=0 + terminator Jmp(b14) + block 18 start_pc=0 + terminator Jmp(b3) block 19 start_pc=0 - terminator Jmp(b4) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 20 start_pc=0 - terminator Jmp(b16) + v31 Imm(3) -> x0 + terminator Return(v31) (exit_acc=v31) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=die fn ent_pc=3 n_params=0 variadic=false locals=0 @@ -173,11 +173,11 @@ fn ent_pc=3 n_params=0 variadic=false locals=0 terminator Jmp(b1) (exit_acc=v0) block 1 start_pc=0 v1 Imm(1) -> x0 - terminator Jmp(b3) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 2 start_pc=0 terminator Jmp(b1) block 3 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b1) block 4 start_pc=0 v2 Imm(0) -> x0 terminator Return(v2) (exit_acc=v2) diff --git a/tests/snapshots/ssa/attribute_declspec.ssa b/tests/snapshots/ssa/attribute_declspec.ssa index 11fe61809..4f1172c14 100644 --- a/tests/snapshots/ssa/attribute_declspec.ssa +++ b/tests/snapshots/ssa/attribute_declspec.ssa @@ -31,42 +31,42 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 BinopI { op=ne, lhs=v6, rhs_imm=5 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(4) -> x0 + v3 Imm(0) -> x0 + v4 Imm(5) -> x0 + v5 Imm(21474836480) -> x0 + v6 Imm(5) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 Imm(3) -> x0 - v10 Extend { value=v9, kind=I32 } -> x1 - v11 Imm(0) -> x1 - v12 BinopI { op=shl, lhs=v9, rhs_imm=1 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x0 - v15 BinopI { op=ne, lhs=v14, rhs_imm=6 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) - block 4 start_pc=0 + v10 Imm(3) -> x0 + v11 Imm(0) -> x0 + v12 Imm(6) -> x0 + v13 Imm(25769803776) -> x0 + v14 Imm(6) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) + block 2 start_pc=0 v17 LocalAddr(-1) -> x0 v18 Imm(7) -> x1 v19 Store { addr=v17, disp=0, value=v18, kind=I32 } -> - v20 LocalAddr(-1) -> x0 v21 Load { addr=v20, disp=0, kind=I32 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=7 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) - block 5 start_pc=0 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) + block 3 start_pc=0 v23 Imm(3) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 + block 4 start_pc=0 v24 Imm(0) -> x0 terminator Return(v24) (exit_acc=v24) + block 5 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) + block 6 start_pc=0 + v16 Imm(2) -> x0 + terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/attribute_noop.ssa b/tests/snapshots/ssa/attribute_noop.ssa index 302f7bb93..b0d7dfaa0 100644 --- a/tests/snapshots/ssa/attribute_noop.ssa +++ b/tests/snapshots/ssa/attribute_noop.ssa @@ -32,38 +32,38 @@ fn ent_pc=4 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(3) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=5 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(3) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 Imm(3) -> x0 + v6 Imm(0) -> x0 + v7 Imm(5) -> x0 + v8 Imm(21474836480) -> x0 + v9 Imm(5) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(11) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 ImmData(36) -> x7 v13 Imm(1) -> x6 v14 Imm(2) -> x2 v15 Call { target_pc=2, args=[v12, v13, v14], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v16 BinopI { op=ne, lhs=v15, rhs_imm=42 } -> x0 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) - block 3 start_pc=0 + terminator Bz { cond=v16, target=b3, fall=b2 } (exit_acc=v16) + block 2 start_pc=0 v17 Imm(12) -> x0 terminator Return(v17) (exit_acc=v17) - block 4 start_pc=0 + block 3 start_pc=0 v18 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v18) + terminator Jmp(b4) (exit_acc=v18) + block 4 start_pc=0 + v20 Imm(0) -> x0 + terminator Return(v20) (exit_acc=v20) block 5 start_pc=0 + v11 Imm(11) -> x0 + terminator Return(v11) (exit_acc=v11) + block 6 start_pc=0 v19 Imm(13) -> x0 terminator Return(v19) (exit_acc=v19) - block 6 start_pc=0 - v20 Imm(0) -> x0 - terminator Return(v20) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/attribute_packed.ssa b/tests/snapshots/ssa/attribute_packed.ssa index e9792ce91..3e3fdfac0 100644 --- a/tests/snapshots/ssa/attribute_packed.ssa +++ b/tests/snapshots/ssa/attribute_packed.ssa @@ -5,43 +5,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) - block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 v9 Imm(0) -> x0 v10 Imm(1) -> x1 - terminator Jmp(b10) (exit_acc=v9) - block 9 start_pc=0 - v11 Imm(5) -> x0 - terminator Return(v11) (exit_acc=v11) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v9) + block 5 start_pc=0 v12 Imm(0) -> x0 v13 Imm(9) -> x1 - terminator Jmp(b12) (exit_acc=v12) - block 11 start_pc=0 - v14 Imm(6) -> x0 - terminator Return(v14) (exit_acc=v14) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v12) + block 6 start_pc=0 v15 LocalAddr(-4) -> x0 v16 Imm(13) -> x1 v17 BinopI { op=add, lhs=v15, rhs_imm=13 } -> x0 @@ -49,11 +31,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v19 Imm(0) -> x2 v20 Binop { op=sub, lhs=v17, rhs=v18 } -> x0 v21 BinopI { op=ne, lhs=v20, rhs_imm=13 } -> x0 - terminator Bz { cond=v21, target=b14, fall=b13 } (exit_acc=v21) - block 13 start_pc=0 + terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) + block 7 start_pc=0 v22 Imm(7) -> x0 terminator Return(v22) (exit_acc=v22) - block 14 start_pc=0 + block 8 start_pc=0 v23 LocalAddr(-6) -> x0 v24 Imm(1) -> x2 v25 Store { addr=v23, disp=0, value=v24, kind=I8 } -> - @@ -70,41 +52,59 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v36 Load { addr=v35, disp=0, kind=I8 } -> x0 v37 BinopI { op=ne, lhs=v36, rhs_imm=1 } -> x0 v38 Imm(0) -> x1 - terminator Bnz { cond=v37, target=b21, fall=b15 } (exit_acc=v37) - block 15 start_pc=0 + terminator Bnz { cond=v37, target=b16, fall=b9 } (exit_acc=v37) + block 9 start_pc=0 v39 LocalAddr(-6) -> x0 v40 BinopI { op=add, lhs=v39, rhs_imm=1 } -> x0 v41 Load { addr=v40, disp=0, kind=I64 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=1234605616436508552 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=0 } -> x2 v44 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v43) - block 16 start_pc=0 - v45 Phi { incoming=[b21:v24, b15:v43], kind=I64 } -> x2 + terminator Jmp(b10) (exit_acc=v43) + block 10 start_pc=0 + v45 Phi { incoming=[b16:v24, b9:v43], kind=I64 } -> x2 v46 LoadLocal { off=-8, kind=I64 } -> x0 v47 Imm(0) -> x0 - terminator Bnz { cond=v45, target=b22, fall=b17 } (exit_acc=v45) - block 17 start_pc=0 + terminator Bnz { cond=v45, target=b15, fall=b11 } (exit_acc=v45) + block 11 start_pc=0 v48 LocalAddr(-6) -> x0 v49 BinopI { op=add, lhs=v48, rhs_imm=9 } -> x0 v50 Load { addr=v49, disp=0, kind=I32 } -> x0 v51 BinopI { op=ne, lhs=v50, rhs_imm=-7 } -> x2 v52 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v51) - block 18 start_pc=0 - v53 Phi { incoming=[b22:v45, b17:v51], kind=I64 } -> x2 + terminator Jmp(b12) (exit_acc=v51) + block 12 start_pc=0 + v53 Phi { incoming=[b15:v45, b11:v51], kind=I64 } -> x2 v54 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v53, target=b20, fall=b19 } (exit_acc=v53) - block 19 start_pc=0 + terminator Bz { cond=v53, target=b14, fall=b13 } (exit_acc=v53) + block 13 start_pc=0 v55 Imm(8) -> x0 terminator Return(v55) (exit_acc=v55) - block 20 start_pc=0 + block 14 start_pc=0 v56 Imm(0) -> x0 terminator Return(v56) (exit_acc=v56) + block 15 start_pc=0 + terminator Jmp(b12) + block 16 start_pc=0 + terminator Jmp(b10) + block 17 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 18 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 19 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 20 start_pc=0 + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 21 start_pc=0 - terminator Jmp(b16) + v11 Imm(5) -> x0 + terminator Return(v11) (exit_acc=v11) block 22 start_pc=0 - terminator Jmp(b18) + v14 Imm(6) -> x0 + terminator Return(v14) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/attribute_positions.ssa b/tests/snapshots/ssa/attribute_positions.ssa index 2529452a1..975636bd3 100644 --- a/tests/snapshots/ssa/attribute_positions.ssa +++ b/tests/snapshots/ssa/attribute_positions.ssa @@ -58,36 +58,27 @@ fn ent_pc=4 n_params=0 variadic=false locals=3 terminator Return(v4) (exit_acc=v4) block 2 start_pc=0 v5 Imm(2) -> x0 - v6 Extend { value=v5, kind=I32 } -> x1 - v7 Imm(0) -> x1 - v8 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x0 - v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x1 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 BinopI { op=ne, lhs=v10, rhs_imm=3 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v6 Imm(2) -> x0 + v7 Imm(0) -> x0 + v8 Imm(3) -> x0 + v9 Imm(12884901888) -> x0 + v10 Imm(3) -> x0 + v11 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v11) block 3 start_pc=0 - v12 Imm(2) -> x0 - terminator Return(v12) (exit_acc=v12) - block 4 start_pc=0 v13 Imm(3) -> x0 - v14 BinopI { op=ne, lhs=v13, rhs_imm=3 } -> x0 - terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) - block 5 start_pc=0 - v15 Imm(3) -> x0 - terminator Return(v15) (exit_acc=v15) - block 6 start_pc=0 + v14 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v14) + block 4 start_pc=0 v16 Imm(100) -> x0 - v17 Imm(7) -> x1 - v18 Extend { value=v16, kind=I32 } -> x0 + v17 Imm(7) -> x0 + v18 Imm(100) -> x0 v19 Imm(0) -> x0 - v20 Extend { value=v17, kind=I32 } -> x0 - v21 Imm(0) -> x1 - v22 BinopI { op=ne, lhs=v20, rhs_imm=7 } -> x0 - terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) - block 7 start_pc=0 - v23 Imm(4) -> x0 - terminator Return(v23) (exit_acc=v23) - block 8 start_pc=0 + v20 Imm(7) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 v24 LocalAddr(-1) -> x0 v25 Imm(11) -> x1 v26 Store { addr=v24, disp=0, value=v25, kind=I32 } -> - @@ -99,36 +90,45 @@ fn ent_pc=4 n_params=0 variadic=false locals=3 v32 Load { addr=v31, disp=0, kind=I32 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=11 } -> x1 v34 Imm(0) -> x0 - terminator Bnz { cond=v33, target=b15, fall=b9 } (exit_acc=v33) - block 9 start_pc=0 + terminator Bnz { cond=v33, target=b11, fall=b6 } (exit_acc=v33) + block 6 start_pc=0 v35 LocalAddr(-1) -> x0 v36 BinopI { op=add, lhs=v35, rhs_imm=4 } -> x1 v37 Load { addr=v35, disp=4, kind=I32 } -> x0 v38 BinopI { op=ne, lhs=v37, rhs_imm=22 } -> x1 v39 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v38) - block 10 start_pc=0 - v40 Phi { incoming=[b15:v33, b9:v38], kind=I64 } -> x1 + terminator Jmp(b7) (exit_acc=v38) + block 7 start_pc=0 + v40 Phi { incoming=[b11:v33, b6:v38], kind=I64 } -> x1 v41 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) - block 11 start_pc=0 + terminator Bz { cond=v40, target=b9, fall=b8 } (exit_acc=v40) + block 8 start_pc=0 v42 Imm(5) -> x0 terminator Return(v42) (exit_acc=v42) - block 12 start_pc=0 + block 9 start_pc=0 v43 Imm(8) -> x0 - v44 Imm(0) -> x1 - v45 BinopI { op=and, lhs=v43, rhs_imm=255 } -> x0 + v44 Imm(0) -> x0 + v45 Imm(8) -> x0 v46 Imm(0) -> x0 - v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x0 - terminator Bz { cond=v47, target=b14, fall=b13 } (exit_acc=v47) - block 13 start_pc=0 - v48 Imm(6) -> x0 - terminator Return(v48) (exit_acc=v48) - block 14 start_pc=0 + v47 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v47) + block 10 start_pc=0 v49 Imm(0) -> x0 terminator Return(v49) (exit_acc=v49) + block 11 start_pc=0 + terminator Jmp(b7) + block 12 start_pc=0 + v12 Imm(2) -> x0 + terminator Return(v12) (exit_acc=v12) + block 13 start_pc=0 + v15 Imm(3) -> x0 + terminator Return(v15) (exit_acc=v15) + block 14 start_pc=0 + v23 Imm(4) -> x0 + terminator Return(v23) (exit_acc=v23) block 15 start_pc=0 - terminator Jmp(b10) + v48 Imm(6) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/auto_include_undeclared_libc.ssa b/tests/snapshots/ssa/auto_include_undeclared_libc.ssa index 4cf0a21eb..7c69fea33 100644 --- a/tests/snapshots/ssa/auto_include_undeclared_libc.ssa +++ b/tests/snapshots/ssa/auto_include_undeclared_libc.ssa @@ -8,19 +8,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v1 ImmData(36) -> x7 v2 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 v3 BinopI { op=gt, lhs=v2, rhs_imm=0 } -> x0 - terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + terminator Bz { cond=v3, target=b3, fall=b1 } (exit_acc=v3) block 1 start_pc=0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v4) + terminator Jmp(b2) (exit_acc=v4) block 2 start_pc=0 - v6 Imm(1) -> x1 - v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) - block 3 start_pc=0 - v8 Phi { incoming=[b1:v4, b2:v6], kind=I64 } -> x1 + v8 Phi { incoming=[b1:v4, b3:v6], kind=I64 } -> x1 v9 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v8) (exit_acc=v8) + block 3 start_pc=0 + v6 Imm(1) -> x1 + v7 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/binary_integer_literal.ssa b/tests/snapshots/ssa/binary_integer_literal.ssa index 5cc4d60a2..1feff2d4c 100644 --- a/tests/snapshots/ssa/binary_integer_literal.ssa +++ b/tests/snapshots/ssa/binary_integer_literal.ssa @@ -5,67 +5,67 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(10) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=ne, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 Imm(3) -> x0 - v7 Imm(0) -> x1 - v8 LoadLocal { off=-2, kind=I32 } -> x1 - v9 BinopI { op=ne, lhs=v6, rhs_imm=3 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v7 Imm(0) -> x0 + v8 LoadLocal { off=-2, kind=I32 } -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 + v11 Imm(192) -> x0 + v12 Imm(0) -> x0 + v13 LoadLocal { off=-3, kind=U8 } -> x0 + v14 Imm(0) -> x0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - v10 Imm(2) -> x0 - terminator Return(v10) (exit_acc=v10) + v18 Imm(63) -> x0 + v19 Imm(0) -> x0 + v20 LoadLocal { off=-4, kind=U8 } -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v23) block 4 start_pc=0 - v11 Imm(192) -> x0 - v12 Imm(0) -> x1 - v13 LoadLocal { off=-3, kind=U8 } -> x1 - v14 BinopI { op=xor, lhs=v11, rhs_imm=192 } -> x0 - v15 BinopI { op=and, lhs=v14, rhs_imm=4294967295 } -> x0 - v16 BinopI { op=ne, lhs=v15, rhs_imm=0 } -> x0 - terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) + v25 Imm(-1) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-5, kind=I64 } -> x0 + v28 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v28) block 5 start_pc=0 - v17 Imm(3) -> x0 - terminator Return(v17) (exit_acc=v17) + v30 Imm(1) -> x0 + v31 Imm(0) -> x0 + v32 LoadLocal { off=-6, kind=U32 } -> x0 + v33 Imm(0) -> x0 + v34 Imm(0) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v18 Imm(63) -> x0 - v19 Imm(0) -> x1 - v20 LoadLocal { off=-4, kind=U8 } -> x1 - v21 BinopI { op=xor, lhs=v18, rhs_imm=63 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) + v37 Imm(0) -> x0 + terminator Return(v37) (exit_acc=v37) block 7 start_pc=0 - v24 Imm(4) -> x0 - terminator Return(v24) (exit_acc=v24) + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) block 8 start_pc=0 - v25 Imm(-1) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-5, kind=I64 } -> x1 - v28 BinopI { op=ne, lhs=v25, rhs_imm=-1 } -> x0 - terminator Bz { cond=v28, target=b10, fall=b9 } (exit_acc=v28) + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) block 9 start_pc=0 - v29 Imm(5) -> x0 - terminator Return(v29) (exit_acc=v29) + v17 Imm(3) -> x0 + terminator Return(v17) (exit_acc=v17) block 10 start_pc=0 - v30 Imm(1) -> x0 - v31 Imm(0) -> x1 - v32 LoadLocal { off=-6, kind=U32 } -> x1 - v33 BinopI { op=xor, lhs=v30, rhs_imm=1 } -> x0 - v34 BinopI { op=and, lhs=v33, rhs_imm=4294967295 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x0 - terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) + v24 Imm(4) -> x0 + terminator Return(v24) (exit_acc=v24) block 11 start_pc=0 + v29 Imm(5) -> x0 + terminator Return(v29) (exit_acc=v29) + block 12 start_pc=0 v36 Imm(6) -> x0 terminator Return(v36) (exit_acc=v36) - block 12 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/binary_search_tree.ssa b/tests/snapshots/ssa/binary_search_tree.ssa index ad3973726..2677b2133 100644 --- a/tests/snapshots/ssa/binary_search_tree.ssa +++ b/tests/snapshots/ssa/binary_search_tree.ssa @@ -62,12 +62,12 @@ fn ent_pc=5 n_params=2 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=6 --- ; name=search fn ent_pc=6 n_params=2 variadic=false locals=2 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 ParamRef(0, kind=I64) -> x3 + v1 ParamRef(0, kind=I64) -> x7 v2 Imm(0) -> x0 - v3 ParamRef(1, kind=I64) -> x12 + v3 ParamRef(1, kind=I64) -> x6 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I64 } -> x0 v6 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 diff --git a/tests/snapshots/ssa/binop_imm_chain_fold.ssa b/tests/snapshots/ssa/binop_imm_chain_fold.ssa index 49e4b35bc..2f4ae0098 100644 --- a/tests/snapshots/ssa/binop_imm_chain_fold.ssa +++ b/tests/snapshots/ssa/binop_imm_chain_fold.ssa @@ -1,93 +1,93 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=12 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(10) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=3 } -> x1 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x2 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=add, lhs=v4, rhs_imm=7 } -> x1 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x2 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 Imm(0) -> x2 - v11 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x2 - v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x6 - v13 Extend { value=v11, kind=I32 } -> x6 - v14 BinopI { op=sub, lhs=v11, rhs_imm=3 } -> x2 - v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x6 - v16 Extend { value=v14, kind=I32 } -> x6 - v17 Imm(0) -> x6 - v18 BinopI { op=sub, lhs=v1, rhs_imm=4 } -> x6 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x7 - v20 Extend { value=v18, kind=I32 } -> x7 - v21 BinopI { op=add, lhs=v18, rhs_imm=9 } -> x6 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x7 - v23 Extend { value=v21, kind=I32 } -> x7 - v24 Imm(0) -> x7 - v25 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x7 - v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x8 - v27 Extend { value=v25, kind=I32 } -> x8 - v28 BinopI { op=sub, lhs=v25, rhs_imm=5 } -> x7 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x8 - v30 Extend { value=v28, kind=I32 } -> x8 - v31 Imm(0) -> x8 - v32 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x8 - v33 BinopI { op=and, lhs=v1, rhs_imm=63 } -> x8 - v34 Imm(0) -> x9 - v35 BinopI { op=or, lhs=v1, rhs_imm=1 } -> x9 - v36 BinopI { op=or, lhs=v1, rhs_imm=3 } -> x9 - v37 Imm(0) -> x3 - v38 BinopI { op=xor, lhs=v1, rhs_imm=5 } -> x3 - v39 BinopI { op=xor, lhs=v1, rhs_imm=3 } -> x0 - v40 Imm(0) -> x3 - v41 LoadLocal { off=-2, kind=I32 } -> x3 - v42 LoadLocal { off=-3, kind=I32 } -> x3 - v43 Binop { op=add, lhs=v7, rhs=v14 } -> x1 - v44 BinopI { op=shl, lhs=v43, rhs_imm=32 } -> x2 - v45 Extend { value=v43, kind=I32 } -> x2 - v46 LoadLocal { off=-4, kind=I32 } -> x2 - v47 Binop { op=add, lhs=v43, rhs=v21 } -> x1 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x2 - v49 Extend { value=v47, kind=I32 } -> x2 - v50 LoadLocal { off=-5, kind=I32 } -> x2 - v51 Binop { op=add, lhs=v47, rhs=v28 } -> x1 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x2 - v53 Extend { value=v51, kind=I32 } -> x2 - v54 Extend { value=v33, kind=I32 } -> x2 - v55 Binop { op=add, lhs=v51, rhs=v33 } -> x1 - v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x2 - v57 Extend { value=v55, kind=I32 } -> x2 - v58 Extend { value=v36, kind=I32 } -> x2 - v59 Binop { op=add, lhs=v55, rhs=v36 } -> x1 - v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x2 - v61 Extend { value=v59, kind=I32 } -> x2 - v62 Extend { value=v39, kind=I32 } -> x2 - v63 Binop { op=add, lhs=v59, rhs=v39 } -> x0 - v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x1 - v65 Extend { value=v63, kind=I32 } -> x3 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(13) -> x0 + v5 Imm(55834574848) -> x0 + v6 Imm(13) -> x0 + v7 Imm(20) -> x0 + v8 Imm(85899345920) -> x0 + v9 Imm(20) -> x0 + v10 Imm(0) -> x0 + v11 Imm(18) -> x0 + v12 Imm(77309411328) -> x0 + v13 Imm(18) -> x0 + v14 Imm(15) -> x0 + v15 Imm(64424509440) -> x0 + v16 Imm(15) -> x0 + v17 Imm(0) -> x0 + v18 Imm(6) -> x0 + v19 Imm(25769803776) -> x0 + v20 Imm(6) -> x0 + v21 Imm(15) -> x0 + v22 Imm(64424509440) -> x0 + v23 Imm(15) -> x0 + v24 Imm(0) -> x0 + v25 Imm(8) -> x0 + v26 Imm(34359738368) -> x0 + v27 Imm(8) -> x0 + v28 Imm(3) -> x0 + v29 Imm(12884901888) -> x0 + v30 Imm(3) -> x0 + v31 Imm(0) -> x0 + v32 Imm(10) -> x0 + v33 Imm(10) -> x0 + v34 Imm(0) -> x0 + v35 Imm(11) -> x0 + v36 Imm(11) -> x0 + v37 Imm(0) -> x0 + v38 Imm(15) -> x0 + v39 Imm(9) -> x0 + v40 Imm(0) -> x0 + v41 LoadLocal { off=-2, kind=I32 } -> x0 + v42 LoadLocal { off=-3, kind=I32 } -> x0 + v43 Imm(35) -> x0 + v44 Imm(150323855360) -> x0 + v45 Imm(35) -> x0 + v46 LoadLocal { off=-4, kind=I32 } -> x0 + v47 Imm(50) -> x0 + v48 Imm(214748364800) -> x0 + v49 Imm(50) -> x0 + v50 LoadLocal { off=-5, kind=I32 } -> x0 + v51 Imm(53) -> x0 + v52 Imm(227633266688) -> x0 + v53 Imm(53) -> x0 + v54 Imm(10) -> x0 + v55 Imm(63) -> x0 + v56 Imm(270582939648) -> x0 + v57 Imm(63) -> x0 + v58 Imm(11) -> x0 + v59 Imm(74) -> x0 + v60 Imm(317827579904) -> x0 + v61 Imm(74) -> x0 + v62 Imm(9) -> x0 + v63 Imm(83) -> x0 + v64 Imm(356482285568) -> x0 + v65 Imm(83) -> x6 v66 Imm(0) -> x0 v67 ImmData(36) -> x7 v68 LoadLocal { off=-9, kind=I32 } -> x0 v69 CallExt { binding_idx=0, args=[v67, v65], fp_arg_mask=0x0 } -> x0 v70 LoadLocal { off=-9, kind=I32 } -> x0 - v71 BinopI { op=eq, lhs=v65, rhs_imm=83 } -> x0 - terminator Bz { cond=v71, target=b2, fall=b1 } (exit_acc=v71) + v71 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v71) block 1 start_pc=0 v72 Imm(0) -> x1 v73 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v72) + terminator Jmp(b2) (exit_acc=v72) block 2 start_pc=0 - v74 Imm(1) -> x1 - v75 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v74) - block 3 start_pc=0 - v76 Phi { incoming=[b1:v72, b2:v74], kind=I64 } -> x1 + v76 Phi { incoming=[b1:v72, b3:v74], kind=I64 } -> x1 v77 LoadLocal { off=-12, kind=I64 } -> x0 terminator Return(v76) (exit_acc=v76) + block 3 start_pc=0 + v74 Imm(1) -> x1 + v75 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v74) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/binop_spill_lhs_rhs_in_dst.ssa b/tests/snapshots/ssa/binop_spill_lhs_rhs_in_dst.ssa index a9ba2417e..dadd4c429 100644 --- a/tests/snapshots/ssa/binop_spill_lhs_rhs_in_dst.ssa +++ b/tests/snapshots/ssa/binop_spill_lhs_rhs_in_dst.ssa @@ -20,31 +20,31 @@ fn ent_pc=0 n_params=3 variadic=false locals=3 v14 Imm(0) -> x1 v15 LoadLocal { off=3, kind=I32 } -> x1 v16 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 + v25 Extend { value=v17, kind=I32 } -> x9 + v26 LoadLocal { off=2, kind=I64 } -> x9 + v27 Extend { value=v18, kind=I32 } -> x9 + v28 BinopI { op=shl, lhs=v19, rhs_imm=2 } -> x9 + v29 Binop { op=add, lhs=v1, rhs=v28 } -> x9 + v30 LoadIndexed { base=v1, index=v19, scale=4, kind=I32 } -> x9 + v31 Binop { op=add, lhs=v17, rhs=v30 } -> x6 + v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x9 + v33 Extend { value=v31, kind=I32 } -> x6 + v34 Imm(0) -> x9 + terminator Jmp(b2) (exit_acc=v33) + block 2 start_pc=0 + v22 Extend { value=v18, kind=I32 } -> x8 + v23 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x8 + v24 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v23) + block 3 start_pc=0 v17 Phi { incoming=[b0:v13, b2:v33], kind=I64 } -> x6 v18 Phi { incoming=[b0:v3, b2:v23], kind=I64 } -> x8 v19 Extend { value=v18, kind=I32 } -> x1 v20 LoadLocal { off=4, kind=I32 } -> x9 - v21 Binop { op=le, lhs=v19, rhs=v5 } -> x1 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) - block 2 start_pc=0 - v22 Extend { value=v18, kind=I32 } -> x1 - v23 BinopI { op=add, lhs=v22, rhs_imm=1 } -> x8 - v24 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v23) - block 3 start_pc=0 - v25 Extend { value=v17, kind=I32 } -> x1 - v26 LoadLocal { off=2, kind=I64 } -> x1 - v27 Extend { value=v18, kind=I32 } -> x1 - v28 BinopI { op=shl, lhs=v27, rhs_imm=2 } -> x9 - v29 Binop { op=add, lhs=v1, rhs=v28 } -> x9 - v30 LoadIndexed { base=v1, index=v27, scale=4, kind=I32 } -> x1 - v31 Binop { op=add, lhs=v17, rhs=v30 } -> x1 - v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x6 - v33 Extend { value=v31, kind=I32 } -> x6 - v34 Imm(0) -> x1 - terminator Jmp(b2) (exit_acc=v33) + v21 Binop { op=le, lhs=v19, rhs=v5 } -> x9 + terminator Bnz { cond=v21, target=b1, fall=b4 } (exit_acc=v21) block 4 start_pc=0 v35 Extend { value=v17, kind=I32 } -> x1 v36 Extend { value=v11, kind=I32 } -> x1 diff --git a/tests/snapshots/ssa/bitfield_assign_value.ssa b/tests/snapshots/ssa/bitfield_assign_value.ssa index 3c37f18e6..3c63c05b9 100644 --- a/tests/snapshots/ssa/bitfield_assign_value.ssa +++ b/tests/snapshots/ssa/bitfield_assign_value.ssa @@ -9,115 +9,109 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v3 Mcpy { dst=v1, src=v2, size=4 } -> x0 v4 LocalAddr(-1) -> x0 v5 Imm(1) -> x1 - v6 Load { addr=v4, disp=0, kind=U32 } -> x2 - v7 BinopI { op=and, lhs=v6, rhs_imm=-3 } -> x2 - v8 Imm(2) -> x6 - v9 Binop { op=or, lhs=v7, rhs=v8 } -> x2 + v6 Load { addr=v4, disp=0, kind=U32 } -> x1 + v7 BinopI { op=and, lhs=v6, rhs_imm=-3 } -> x1 + v8 Imm(2) -> x2 + v9 BinopI { op=or, lhs=v7, rhs_imm=2 } -> x1 v10 Store { addr=v4, disp=0, value=v9, kind=I32 } -> - v11 Imm(0) -> x0 v12 LoadLocal { off=-2, kind=I32 } -> x0 - v13 BinopI { op=ne, lhs=v5, rhs_imm=1 } -> x0 - terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) + v13 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v13) block 1 start_pc=0 - v14 Imm(1) -> x0 - terminator Return(v14) (exit_acc=v14) - block 2 start_pc=0 v15 LocalAddr(-1) -> x0 v16 Imm(5) -> x1 - v17 Load { addr=v15, disp=0, kind=U32 } -> x2 - v18 BinopI { op=and, lhs=v17, rhs_imm=-29 } -> x2 - v19 Imm(20) -> x6 - v20 Binop { op=or, lhs=v18, rhs=v19 } -> x2 + v17 Load { addr=v15, disp=0, kind=U32 } -> x1 + v18 BinopI { op=and, lhs=v17, rhs_imm=-29 } -> x1 + v19 Imm(20) -> x2 + v20 BinopI { op=or, lhs=v18, rhs_imm=20 } -> x1 v21 Store { addr=v15, disp=0, value=v20, kind=I32 } -> - v22 Imm(0) -> x0 v23 LoadLocal { off=-3, kind=I32 } -> x0 - v24 BinopI { op=ne, lhs=v16, rhs_imm=5 } -> x0 - terminator Bz { cond=v24, target=b4, fall=b3 } (exit_acc=v24) - block 3 start_pc=0 - v25 Imm(2) -> x0 - terminator Return(v25) (exit_acc=v25) - block 4 start_pc=0 + v24 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v24) + block 2 start_pc=0 v26 LocalAddr(-1) -> x0 v27 Imm(13) -> x1 v28 Imm(5) -> x1 - v29 Load { addr=v26, disp=0, kind=U32 } -> x2 - v30 BinopI { op=and, lhs=v29, rhs_imm=-29 } -> x2 - v31 Imm(20) -> x6 - v32 Binop { op=or, lhs=v30, rhs=v31 } -> x2 + v29 Load { addr=v26, disp=0, kind=U32 } -> x1 + v30 BinopI { op=and, lhs=v29, rhs_imm=-29 } -> x1 + v31 Imm(20) -> x2 + v32 BinopI { op=or, lhs=v30, rhs_imm=20 } -> x1 v33 Store { addr=v26, disp=0, value=v32, kind=I32 } -> - v34 Imm(0) -> x0 v35 LoadLocal { off=-4, kind=I32 } -> x0 - v36 BinopI { op=ne, lhs=v28, rhs_imm=5 } -> x1 + v36 Imm(0) -> x1 v37 Imm(0) -> x0 - terminator Bnz { cond=v36, target=b17, fall=b5 } (exit_acc=v36) - block 5 start_pc=0 + terminator Jmp(b3) (exit_acc=v36) + block 3 start_pc=0 v38 LocalAddr(-1) -> x0 v39 Load { addr=v38, disp=0, kind=U32 } -> x0 v40 BinopI { op=shr, lhs=v39, rhs_imm=2 } -> x0 v41 BinopI { op=and, lhs=v40, rhs_imm=7 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=5 } -> x1 v43 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v42) - block 6 start_pc=0 - v44 Phi { incoming=[b17:v36, b5:v42], kind=I64 } -> x1 + terminator Jmp(b4) (exit_acc=v42) + block 4 start_pc=0 + v44 Phi { incoming=[b2:v36, b3:v42], kind=I64 } -> x1 v45 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v44, target=b8, fall=b7 } (exit_acc=v44) - block 7 start_pc=0 + terminator Bz { cond=v44, target=b6, fall=b5 } (exit_acc=v44) + block 5 start_pc=0 v46 Imm(3) -> x0 terminator Return(v46) (exit_acc=v46) - block 8 start_pc=0 + block 6 start_pc=0 v47 LocalAddr(-5) -> x0 v48 ImmData(12) -> x1 v49 Mcpy { dst=v47, src=v48, size=4 } -> x0 v50 LocalAddr(-5) -> x0 v51 LocalAddr(-5) -> x1 v52 Imm(1) -> x2 - v53 Load { addr=v51, disp=0, kind=U32 } -> x6 - v54 BinopI { op=and, lhs=v53, rhs_imm=-3 } -> x6 - v55 Imm(2) -> x7 - v56 Binop { op=or, lhs=v54, rhs=v55 } -> x6 + v53 Load { addr=v51, disp=0, kind=U32 } -> x2 + v54 BinopI { op=and, lhs=v53, rhs_imm=-3 } -> x2 + v55 Imm(2) -> x6 + v56 BinopI { op=or, lhs=v54, rhs_imm=2 } -> x2 v57 Store { addr=v51, disp=0, value=v56, kind=I32 } -> - v58 Load { addr=v50, disp=0, kind=U32 } -> x1 v59 BinopI { op=and, lhs=v58, rhs_imm=-2 } -> x1 - v60 Binop { op=or, lhs=v59, rhs=v52 } -> x1 + v60 BinopI { op=or, lhs=v59, rhs_imm=1 } -> x1 v61 Store { addr=v50, disp=0, value=v60, kind=I32 } -> - v62 LocalAddr(-5) -> x0 v63 Load { addr=v62, disp=0, kind=U32 } -> x0 v64 BinopI { op=and, lhs=v63, rhs_imm=1 } -> x0 v65 BinopI { op=ne, lhs=v64, rhs_imm=1 } -> x1 v66 Imm(0) -> x0 - terminator Bnz { cond=v65, target=b18, fall=b9 } (exit_acc=v65) - block 9 start_pc=0 + terminator Bnz { cond=v65, target=b15, fall=b7 } (exit_acc=v65) + block 7 start_pc=0 v67 LocalAddr(-5) -> x0 v68 Load { addr=v67, disp=0, kind=U32 } -> x0 v69 BinopI { op=shr, lhs=v68, rhs_imm=1 } -> x0 v70 BinopI { op=and, lhs=v69, rhs_imm=1 } -> x0 v71 BinopI { op=ne, lhs=v70, rhs_imm=1 } -> x1 v72 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v71) - block 10 start_pc=0 - v73 Phi { incoming=[b18:v65, b9:v71], kind=I64 } -> x1 + terminator Jmp(b8) (exit_acc=v71) + block 8 start_pc=0 + v73 Phi { incoming=[b15:v65, b7:v71], kind=I64 } -> x1 v74 LoadLocal { off=-8, kind=I64 } -> x0 - terminator Bz { cond=v73, target=b12, fall=b11 } (exit_acc=v73) - block 11 start_pc=0 + terminator Bz { cond=v73, target=b10, fall=b9 } (exit_acc=v73) + block 9 start_pc=0 v75 Imm(4) -> x0 terminator Return(v75) (exit_acc=v75) - block 12 start_pc=0 + block 10 start_pc=0 v76 LocalAddr(-1) -> x0 v77 Imm(-3) -> x1 - v78 Imm(13) -> x2 - v79 Load { addr=v76, disp=0, kind=U32 } -> x2 - v80 BinopI { op=and, lhs=v79, rhs_imm=-481 } -> x2 - v81 Imm(416) -> x6 - v82 Binop { op=or, lhs=v80, rhs=v81 } -> x2 + v78 Imm(13) -> x1 + v79 Load { addr=v76, disp=0, kind=U32 } -> x1 + v80 BinopI { op=and, lhs=v79, rhs_imm=-481 } -> x1 + v81 Imm(416) -> x2 + v82 BinopI { op=or, lhs=v80, rhs_imm=416 } -> x1 v83 Store { addr=v76, disp=0, value=v82, kind=I32 } -> - v84 Imm(-3458764513820540928) -> x0 v85 Imm(0) -> x0 v86 LoadLocal { off=-6, kind=I32 } -> x0 - v87 BinopI { op=ne, lhs=v77, rhs_imm=-3 } -> x1 + v87 Imm(0) -> x1 v88 Imm(0) -> x0 - terminator Bnz { cond=v87, target=b19, fall=b13 } (exit_acc=v87) - block 13 start_pc=0 + terminator Jmp(b11) (exit_acc=v87) + block 11 start_pc=0 v89 LocalAddr(-1) -> x0 v90 Load { addr=v89, disp=0, kind=U32 } -> x0 v91 BinopI { op=shr, lhs=v90, rhs_imm=5 } -> x0 @@ -126,23 +120,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v94 BinopI { op=shr, lhs=v93, rhs_imm=60 } -> x0 v95 BinopI { op=ne, lhs=v94, rhs_imm=-3 } -> x1 v96 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v95) - block 14 start_pc=0 - v97 Phi { incoming=[b19:v87, b13:v95], kind=I64 } -> x1 + terminator Jmp(b12) (exit_acc=v95) + block 12 start_pc=0 + v97 Phi { incoming=[b10:v87, b11:v95], kind=I64 } -> x1 v98 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v97, target=b16, fall=b15 } (exit_acc=v97) - block 15 start_pc=0 + terminator Bz { cond=v97, target=b14, fall=b13 } (exit_acc=v97) + block 13 start_pc=0 v99 Imm(5) -> x0 terminator Return(v99) (exit_acc=v99) - block 16 start_pc=0 + block 14 start_pc=0 v100 Imm(0) -> x0 terminator Return(v100) (exit_acc=v100) + block 15 start_pc=0 + terminator Jmp(b8) + block 16 start_pc=0 + v14 Imm(1) -> x0 + terminator Return(v14) (exit_acc=v14) block 17 start_pc=0 - terminator Jmp(b6) - block 18 start_pc=0 - terminator Jmp(b10) - block 19 start_pc=0 - terminator Jmp(b14) + v25 Imm(2) -> x0 + terminator Return(v25) (exit_acc=v25) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bitfield_compound_assignment.ssa b/tests/snapshots/ssa/bitfield_compound_assignment.ssa index d536c9aab..f2534147f 100644 --- a/tests/snapshots/ssa/bitfield_compound_assignment.ssa +++ b/tests/snapshots/ssa/bitfield_compound_assignment.ssa @@ -114,23 +114,23 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 block 8 start_pc=0 v93 LocalAddr(-1) -> x0 v94 Imm(1) -> x1 - v95 Load { addr=v93, disp=0, kind=U16 } -> x2 - v96 BinopI { op=and, lhs=v95, rhs_imm=-2 } -> x2 - v97 Binop { op=or, lhs=v96, rhs=v94 } -> x1 + v95 Load { addr=v93, disp=0, kind=U16 } -> x1 + v96 BinopI { op=and, lhs=v95, rhs_imm=-2 } -> x1 + v97 BinopI { op=or, lhs=v96, rhs_imm=1 } -> x1 v98 Store { addr=v93, disp=0, value=v97, kind=I16 } -> - v99 LocalAddr(-1) -> x0 v100 Imm(12) -> x1 v101 Load { addr=v99, disp=0, kind=U16 } -> x1 v102 BinopI { op=and, lhs=v101, rhs_imm=-241 } -> x1 v103 Imm(192) -> x2 - v104 Binop { op=or, lhs=v102, rhs=v103 } -> x1 + v104 BinopI { op=or, lhs=v102, rhs_imm=192 } -> x1 v105 Store { addr=v99, disp=0, value=v104, kind=I16 } -> - v106 LocalAddr(-1) -> x0 v107 Imm(200) -> x1 v108 Load { addr=v106, disp=0, kind=U16 } -> x1 v109 BinopI { op=and, lhs=v108, rhs_imm=-65281 } -> x1 v110 Imm(51200) -> x2 - v111 Binop { op=or, lhs=v109, rhs=v110 } -> x1 + v111 BinopI { op=or, lhs=v109, rhs_imm=51200 } -> x1 v112 Store { addr=v106, disp=0, value=v111, kind=I16 } -> - v113 LocalAddr(-1) -> x0 v114 LocalAddr(-1) -> x1 diff --git a/tests/snapshots/ssa/bitfield_incdec.ssa b/tests/snapshots/ssa/bitfield_incdec.ssa index 97d40f234..52babf556 100644 --- a/tests/snapshots/ssa/bitfield_incdec.ssa +++ b/tests/snapshots/ssa/bitfield_incdec.ssa @@ -20,7 +20,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v14 Extend { value=v6, kind=I32 } -> x0 v15 BinopI { op=ne, lhs=v14, rhs_imm=0 } -> x1 v16 Imm(0) -> x0 - terminator Bnz { cond=v15, target=b31, fall=b1 } (exit_acc=v15) + terminator Bnz { cond=v15, target=b34, fall=b1 } (exit_acc=v15) block 1 start_pc=0 v17 LocalAddr(-1) -> x0 v18 Load { addr=v17, disp=0, kind=U32 } -> x0 @@ -29,7 +29,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v21 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 - v22 Phi { incoming=[b31:v15, b1:v20], kind=I64 } -> x1 + v22 Phi { incoming=[b34:v15, b1:v20], kind=I64 } -> x1 v23 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 @@ -106,7 +106,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v80 Extend { value=v78, kind=I32 } -> x0 v81 BinopI { op=ne, lhs=v80, rhs_imm=3 } -> x1 v82 Imm(0) -> x0 - terminator Bnz { cond=v81, target=b32, fall=b11 } (exit_acc=v81) + terminator Bnz { cond=v81, target=b33, fall=b11 } (exit_acc=v81) block 11 start_pc=0 v83 LocalAddr(-1) -> x0 v84 Load { addr=v83, disp=0, kind=U32 } -> x0 @@ -115,7 +115,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v87 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v86) block 12 start_pc=0 - v88 Phi { incoming=[b32:v81, b11:v86], kind=I64 } -> x1 + v88 Phi { incoming=[b33:v81, b11:v86], kind=I64 } -> x1 v89 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v88, target=b14, fall=b13 } (exit_acc=v88) block 13 start_pc=0 @@ -195,7 +195,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v149 Extend { value=v140, kind=I32 } -> x0 v150 BinopI { op=ne, lhs=v149, rhs_imm=0 } -> x1 v151 Imm(0) -> x0 - terminator Bnz { cond=v150, target=b33, fall=b21 } (exit_acc=v150) + terminator Bnz { cond=v150, target=b32, fall=b21 } (exit_acc=v150) block 21 start_pc=0 v152 LocalAddr(-4) -> x0 v153 Load { addr=v152, disp=0, kind=U32 } -> x0 @@ -205,7 +205,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v157 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v156) block 22 start_pc=0 - v158 Phi { incoming=[b33:v150, b21:v156], kind=I64 } -> x1 + v158 Phi { incoming=[b32:v150, b21:v156], kind=I64 } -> x1 v159 LoadLocal { off=-8, kind=I64 } -> x0 terminator Bz { cond=v158, target=b24, fall=b23 } (exit_acc=v158) block 23 start_pc=0 @@ -214,9 +214,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 block 24 start_pc=0 v161 LocalAddr(-4) -> x0 v162 Imm(15) -> x1 - v163 Load { addr=v161, disp=0, kind=U32 } -> x2 - v164 BinopI { op=and, lhs=v163, rhs_imm=-16 } -> x2 - v165 Binop { op=or, lhs=v164, rhs=v162 } -> x1 + v163 Load { addr=v161, disp=0, kind=U32 } -> x1 + v164 BinopI { op=and, lhs=v163, rhs_imm=-16 } -> x1 + v165 BinopI { op=or, lhs=v164, rhs_imm=15 } -> x1 v166 Store { addr=v161, disp=0, value=v165, kind=I32 } -> - v167 LocalAddr(-4) -> x0 v168 Load { addr=v167, disp=0, kind=U32 } -> x1 @@ -244,7 +244,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v186 BinopI { op=shr, lhs=v185, rhs_imm=59 } -> x0 v187 BinopI { op=ne, lhs=v186, rhs_imm=1 } -> x1 v188 Imm(0) -> x0 - terminator Bnz { cond=v187, target=b34, fall=b27 } (exit_acc=v187) + terminator Bnz { cond=v187, target=b31, fall=b27 } (exit_acc=v187) block 27 start_pc=0 v189 LocalAddr(-4) -> x0 v190 Load { addr=v189, disp=0, kind=U32 } -> x0 @@ -254,7 +254,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v194 Imm(0) -> x0 terminator Jmp(b28) (exit_acc=v193) block 28 start_pc=0 - v195 Phi { incoming=[b34:v187, b27:v193], kind=I64 } -> x1 + v195 Phi { incoming=[b31:v187, b27:v193], kind=I64 } -> x1 v196 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v195, target=b30, fall=b29 } (exit_acc=v195) block 29 start_pc=0 @@ -264,13 +264,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v198 Imm(0) -> x0 terminator Return(v198) (exit_acc=v198) block 31 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b28) block 32 start_pc=0 - terminator Jmp(b12) - block 33 start_pc=0 terminator Jmp(b22) + block 33 start_pc=0 + terminator Jmp(b12) block 34 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bitfield_mixed_base_packing.ssa b/tests/snapshots/ssa/bitfield_mixed_base_packing.ssa index a056f566a..a91468953 100644 --- a/tests/snapshots/ssa/bitfield_mixed_base_packing.ssa +++ b/tests/snapshots/ssa/bitfield_mixed_base_packing.ssa @@ -5,16 +5,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 LocalAddr(-2) -> x0 v4 Imm(2147483647) -> x1 - v5 Load { addr=v3, disp=0, kind=U32 } -> x2 - v6 BinopI { op=and, lhs=v5, rhs_imm=-2147483648 } -> x2 - v7 Binop { op=or, lhs=v6, rhs=v4 } -> x1 + v5 Load { addr=v3, disp=0, kind=U32 } -> x1 + v6 BinopI { op=and, lhs=v5, rhs_imm=-2147483648 } -> x1 + v7 BinopI { op=or, lhs=v6, rhs_imm=2147483647 } -> x1 v8 Store { addr=v3, disp=0, value=v7, kind=I32 } -> - v9 LocalAddr(-2) -> x0 v10 BinopI { op=add, lhs=v9, rhs_imm=3 } -> x1 @@ -22,14 +19,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v12 Load { addr=v9, disp=3, kind=U8 } -> x1 v13 BinopI { op=and, lhs=v12, rhs_imm=-129 } -> x1 v14 Imm(128) -> x2 - v15 Binop { op=or, lhs=v13, rhs=v14 } -> x1 + v15 BinopI { op=or, lhs=v13, rhs_imm=128 } -> x1 v16 Store { addr=v9, disp=3, value=v15, kind=I8 } -> - v17 LocalAddr(-2) -> x0 v18 BinopI { op=add, lhs=v17, rhs_imm=4 } -> x1 v19 Imm(1073741823) -> x1 - v20 Load { addr=v17, disp=4, kind=U32 } -> x2 - v21 BinopI { op=and, lhs=v20, rhs_imm=-1073741824 } -> x2 - v22 Binop { op=or, lhs=v21, rhs=v19 } -> x1 + v20 Load { addr=v17, disp=4, kind=U32 } -> x1 + v21 BinopI { op=and, lhs=v20, rhs_imm=-1073741824 } -> x1 + v22 BinopI { op=or, lhs=v21, rhs_imm=1073741823 } -> x1 v23 Store { addr=v17, disp=4, value=v22, kind=I32 } -> - v24 LocalAddr(-2) -> x0 v25 BinopI { op=add, lhs=v24, rhs_imm=7 } -> x1 @@ -37,7 +34,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v27 Load { addr=v24, disp=7, kind=U8 } -> x1 v28 BinopI { op=and, lhs=v27, rhs_imm=-193 } -> x1 v29 Imm(192) -> x2 - v30 Binop { op=or, lhs=v28, rhs=v29 } -> x1 + v30 BinopI { op=or, lhs=v28, rhs_imm=192 } -> x1 v31 Store { addr=v24, disp=7, value=v30, kind=I8 } -> - v32 LocalAddr(-2) -> x0 v33 BinopI { op=add, lhs=v32, rhs_imm=8 } -> x1 @@ -52,52 +49,52 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v42 Load { addr=v41, disp=0, kind=U32 } -> x0 v43 BinopI { op=and, lhs=v42, rhs_imm=2147483647 } -> x0 v44 BinopI { op=ne, lhs=v43, rhs_imm=2147483647 } -> x0 - terminator Bz { cond=v44, target=b4, fall=b3 } (exit_acc=v44) - block 3 start_pc=0 + terminator Bz { cond=v44, target=b3, fall=b2 } (exit_acc=v44) + block 2 start_pc=0 v45 Imm(2) -> x0 terminator Return(v45) (exit_acc=v45) - block 4 start_pc=0 + block 3 start_pc=0 v46 LocalAddr(-2) -> x0 v47 BinopI { op=add, lhs=v46, rhs_imm=3 } -> x1 v48 Load { addr=v46, disp=3, kind=U8 } -> x0 v49 BinopI { op=shr, lhs=v48, rhs_imm=7 } -> x0 v50 BinopI { op=and, lhs=v49, rhs_imm=1 } -> x0 v51 BinopI { op=ne, lhs=v50, rhs_imm=1 } -> x0 - terminator Bz { cond=v51, target=b6, fall=b5 } (exit_acc=v51) - block 5 start_pc=0 + terminator Bz { cond=v51, target=b5, fall=b4 } (exit_acc=v51) + block 4 start_pc=0 v52 Imm(3) -> x0 terminator Return(v52) (exit_acc=v52) - block 6 start_pc=0 + block 5 start_pc=0 v53 LocalAddr(-2) -> x0 v54 BinopI { op=add, lhs=v53, rhs_imm=4 } -> x1 v55 Load { addr=v53, disp=4, kind=U32 } -> x0 v56 BinopI { op=and, lhs=v55, rhs_imm=1073741823 } -> x0 v57 BinopI { op=ne, lhs=v56, rhs_imm=1073741823 } -> x0 - terminator Bz { cond=v57, target=b8, fall=b7 } (exit_acc=v57) - block 7 start_pc=0 + terminator Bz { cond=v57, target=b7, fall=b6 } (exit_acc=v57) + block 6 start_pc=0 v58 Imm(4) -> x0 terminator Return(v58) (exit_acc=v58) - block 8 start_pc=0 + block 7 start_pc=0 v59 LocalAddr(-2) -> x0 v60 BinopI { op=add, lhs=v59, rhs_imm=7 } -> x1 v61 Load { addr=v59, disp=7, kind=U8 } -> x0 v62 BinopI { op=shr, lhs=v61, rhs_imm=6 } -> x0 v63 BinopI { op=and, lhs=v62, rhs_imm=3 } -> x0 v64 BinopI { op=ne, lhs=v63, rhs_imm=3 } -> x0 - terminator Bz { cond=v64, target=b10, fall=b9 } (exit_acc=v64) - block 9 start_pc=0 + terminator Bz { cond=v64, target=b9, fall=b8 } (exit_acc=v64) + block 8 start_pc=0 v65 Imm(5) -> x0 terminator Return(v65) (exit_acc=v65) - block 10 start_pc=0 + block 9 start_pc=0 v66 LocalAddr(-2) -> x0 v67 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x1 v68 Load { addr=v66, disp=8, kind=U32 } -> x0 v69 BinopI { op=ne, lhs=v68, rhs_imm=3735928559 } -> x0 - terminator Bz { cond=v69, target=b12, fall=b11 } (exit_acc=v69) - block 11 start_pc=0 + terminator Bz { cond=v69, target=b11, fall=b10 } (exit_acc=v69) + block 10 start_pc=0 v70 Imm(6) -> x0 terminator Return(v70) (exit_acc=v70) - block 12 start_pc=0 + block 11 start_pc=0 v71 LocalAddr(-2) -> x0 v72 BinopI { op=add, lhs=v71, rhs_imm=12 } -> x1 v73 Imm(0) -> x1 @@ -105,11 +102,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v75 BinopI { op=xor, lhs=v74, rhs_imm=171 } -> x0 v76 BinopI { op=and, lhs=v75, rhs_imm=4294967295 } -> x0 v77 BinopI { op=ne, lhs=v76, rhs_imm=0 } -> x0 - terminator Bz { cond=v77, target=b14, fall=b13 } (exit_acc=v77) - block 13 start_pc=0 + terminator Bz { cond=v77, target=b13, fall=b12 } (exit_acc=v77) + block 12 start_pc=0 v78 Imm(7) -> x0 terminator Return(v78) (exit_acc=v78) - block 14 start_pc=0 + block 13 start_pc=0 v79 LocalAddr(-2) -> x0 v80 Imm(0) -> x1 v81 Load { addr=v79, disp=0, kind=U32 } -> x2 @@ -126,56 +123,59 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v92 BinopI { op=add, lhs=v91, rhs_imm=8 } -> x1 v93 Load { addr=v91, disp=8, kind=U32 } -> x0 v94 BinopI { op=ne, lhs=v93, rhs_imm=3735928559 } -> x0 - terminator Bz { cond=v94, target=b16, fall=b15 } (exit_acc=v94) - block 15 start_pc=0 + terminator Bz { cond=v94, target=b15, fall=b14 } (exit_acc=v94) + block 14 start_pc=0 v95 Imm(8) -> x0 terminator Return(v95) (exit_acc=v95) - block 16 start_pc=0 + block 15 start_pc=0 v96 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v96) - block 17 start_pc=0 - v97 Imm(9) -> x0 - terminator Return(v97) (exit_acc=v97) - block 18 start_pc=0 + terminator Jmp(b16) (exit_acc=v96) + block 16 start_pc=0 v98 LocalAddr(-3) -> x0 v99 Imm(511) -> x1 - v100 Load { addr=v98, disp=0, kind=U16 } -> x2 - v101 BinopI { op=and, lhs=v100, rhs_imm=-512 } -> x2 - v102 Binop { op=or, lhs=v101, rhs=v99 } -> x1 + v100 Load { addr=v98, disp=0, kind=U16 } -> x1 + v101 BinopI { op=and, lhs=v100, rhs_imm=-512 } -> x1 + v102 BinopI { op=or, lhs=v101, rhs_imm=511 } -> x1 v103 Store { addr=v98, disp=0, value=v102, kind=I16 } -> - v104 LocalAddr(-3) -> x0 v105 BinopI { op=add, lhs=v104, rhs_imm=2 } -> x1 v106 Imm(291) -> x1 - v107 Load { addr=v104, disp=2, kind=U16 } -> x2 - v108 BinopI { op=and, lhs=v107, rhs_imm=-512 } -> x2 - v109 Binop { op=or, lhs=v108, rhs=v106 } -> x1 + v107 Load { addr=v104, disp=2, kind=U16 } -> x1 + v108 BinopI { op=and, lhs=v107, rhs_imm=-512 } -> x1 + v109 BinopI { op=or, lhs=v108, rhs_imm=291 } -> x1 v110 Store { addr=v104, disp=2, value=v109, kind=I16 } -> - v111 LocalAddr(-3) -> x0 v112 Load { addr=v111, disp=0, kind=U16 } -> x0 v113 BinopI { op=and, lhs=v112, rhs_imm=511 } -> x0 v114 BinopI { op=ne, lhs=v113, rhs_imm=511 } -> x1 v115 Imm(0) -> x0 - terminator Bnz { cond=v114, target=b23, fall=b19 } (exit_acc=v114) - block 19 start_pc=0 + terminator Bnz { cond=v114, target=b21, fall=b17 } (exit_acc=v114) + block 17 start_pc=0 v116 LocalAddr(-3) -> x0 v117 BinopI { op=add, lhs=v116, rhs_imm=2 } -> x1 v118 Load { addr=v116, disp=2, kind=U16 } -> x0 v119 BinopI { op=and, lhs=v118, rhs_imm=511 } -> x0 v120 BinopI { op=ne, lhs=v119, rhs_imm=291 } -> x1 v121 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v120) - block 20 start_pc=0 - v122 Phi { incoming=[b23:v114, b19:v120], kind=I64 } -> x1 + terminator Jmp(b18) (exit_acc=v120) + block 18 start_pc=0 + v122 Phi { incoming=[b21:v114, b17:v120], kind=I64 } -> x1 v123 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v122, target=b22, fall=b21 } (exit_acc=v122) - block 21 start_pc=0 + terminator Bz { cond=v122, target=b20, fall=b19 } (exit_acc=v122) + block 19 start_pc=0 v124 Imm(10) -> x0 terminator Return(v124) (exit_acc=v124) - block 22 start_pc=0 + block 20 start_pc=0 v125 Imm(0) -> x0 terminator Return(v125) (exit_acc=v125) + block 21 start_pc=0 + terminator Jmp(b18) + block 22 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 23 start_pc=0 - terminator Jmp(b20) + v97 Imm(9) -> x0 + terminator Return(v97) (exit_acc=v97) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bitfield_signed_read.ssa b/tests/snapshots/ssa/bitfield_signed_read.ssa index 8842bd97b..bf6b62f23 100644 --- a/tests/snapshots/ssa/bitfield_signed_read.ssa +++ b/tests/snapshots/ssa/bitfield_signed_read.ssa @@ -7,9 +7,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v1 LocalAddr(-1) -> x0 v2 Imm(-1) -> x1 v3 Imm(3) -> x1 - v4 Load { addr=v1, disp=0, kind=U16 } -> x2 - v5 BinopI { op=and, lhs=v4, rhs_imm=-4 } -> x2 - v6 Binop { op=or, lhs=v5, rhs=v3 } -> x1 + v4 Load { addr=v1, disp=0, kind=U16 } -> x1 + v5 BinopI { op=and, lhs=v4, rhs_imm=-4 } -> x1 + v6 BinopI { op=or, lhs=v5, rhs_imm=3 } -> x1 v7 Store { addr=v1, disp=0, value=v6, kind=I16 } -> - v8 Imm(-4611686018427387904) -> x0 v9 LocalAddr(-1) -> x0 @@ -17,7 +17,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v11 Load { addr=v9, disp=0, kind=U16 } -> x1 v12 BinopI { op=and, lhs=v11, rhs_imm=-13 } -> x1 v13 Imm(4) -> x2 - v14 Binop { op=or, lhs=v12, rhs=v13 } -> x1 + v14 BinopI { op=or, lhs=v12, rhs_imm=4 } -> x1 v15 Store { addr=v9, disp=0, value=v14, kind=I16 } -> - v16 Imm(4611686018427387904) -> x0 v17 LocalAddr(-1) -> x0 @@ -26,7 +26,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v20 Load { addr=v17, disp=0, kind=U16 } -> x1 v21 BinopI { op=and, lhs=v20, rhs_imm=-65521 } -> x1 v22 Imm(32768) -> x2 - v23 Binop { op=or, lhs=v21, rhs=v22 } -> x1 + v23 BinopI { op=or, lhs=v21, rhs_imm=32768 } -> x1 v24 Store { addr=v17, disp=0, value=v23, kind=I16 } -> - v25 Imm(-9223372036854775808) -> x0 v26 LocalAddr(-1) -> x0 @@ -81,9 +81,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v59 LocalAddr(-2) -> x0 v60 Imm(-4) -> x1 v61 Imm(4) -> x1 - v62 Load { addr=v59, disp=0, kind=U32 } -> x2 - v63 BinopI { op=and, lhs=v62, rhs_imm=-8 } -> x2 - v64 Binop { op=or, lhs=v63, rhs=v61 } -> x1 + v62 Load { addr=v59, disp=0, kind=U32 } -> x1 + v63 BinopI { op=and, lhs=v62, rhs_imm=-8 } -> x1 + v64 BinopI { op=or, lhs=v63, rhs_imm=4 } -> x1 v65 Store { addr=v59, disp=0, value=v64, kind=I32 } -> - v66 Imm(-9223372036854775808) -> x0 v67 LocalAddr(-2) -> x0 @@ -92,7 +92,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v70 Load { addr=v67, disp=0, kind=U32 } -> x1 v71 BinopI { op=and, lhs=v70, rhs_imm=-2041 } -> x1 v72 Imm(1024) -> x2 - v73 Binop { op=or, lhs=v71, rhs=v72 } -> x1 + v73 BinopI { op=or, lhs=v71, rhs_imm=1024 } -> x1 v74 Store { addr=v67, disp=0, value=v73, kind=I32 } -> - v75 LocalAddr(-2) -> x0 v76 Imm(-1) -> x1 @@ -100,7 +100,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v78 Load { addr=v75, disp=0, kind=U32 } -> x1 v79 BinopI { op=and, lhs=v78, rhs_imm=-4294965249 } -> x1 v80 Imm(4294965248) -> x2 - v81 Binop { op=or, lhs=v79, rhs=v80 } -> x1 + v81 BinopI { op=or, lhs=v79, rhs_imm=4294965248 } -> x1 v82 Store { addr=v75, disp=0, value=v81, kind=I32 } -> - v83 Imm(-8796093022208) -> x0 v84 LocalAddr(-2) -> x0 @@ -163,9 +163,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 18 start_pc=0 v122 LocalAddr(-3) -> x0 v123 Imm(7) -> x1 - v124 Load { addr=v122, disp=0, kind=U32 } -> x2 - v125 BinopI { op=and, lhs=v124, rhs_imm=-4096 } -> x2 - v126 Binop { op=or, lhs=v125, rhs=v123 } -> x1 + v124 Load { addr=v122, disp=0, kind=U32 } -> x1 + v125 BinopI { op=and, lhs=v124, rhs_imm=-4096 } -> x1 + v126 BinopI { op=or, lhs=v125, rhs_imm=7 } -> x1 v127 Store { addr=v122, disp=0, value=v126, kind=I32 } -> - v128 LocalAddr(-3) -> x0 v129 Imm(-1) -> x1 @@ -173,7 +173,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v131 Load { addr=v128, disp=0, kind=U16 } -> x1 v132 BinopI { op=and, lhs=v131, rhs_imm=-12289 } -> x1 v133 Imm(12288) -> x2 - v134 Binop { op=or, lhs=v132, rhs=v133 } -> x1 + v134 BinopI { op=or, lhs=v132, rhs_imm=12288 } -> x1 v135 Store { addr=v128, disp=0, value=v134, kind=I16 } -> - v136 Imm(-4611686018427387904) -> x0 v137 LocalAddr(-3) -> x0 @@ -181,7 +181,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v139 Load { addr=v137, disp=0, kind=U16 } -> x1 v140 BinopI { op=and, lhs=v139, rhs_imm=-49153 } -> x1 v141 Imm(16384) -> x2 - v142 Binop { op=or, lhs=v140, rhs=v141 } -> x1 + v142 BinopI { op=or, lhs=v140, rhs_imm=16384 } -> x1 v143 Store { addr=v137, disp=0, value=v142, kind=I16 } -> - v144 Imm(4611686018427387904) -> x0 v145 LocalAddr(-3) -> x0 @@ -218,15 +218,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 terminator Return(v165) (exit_acc=v165) block 24 start_pc=0 v166 Imm(6) -> x0 - v167 Imm(0) -> x1 - v168 LocalAddr(-3) -> x1 - v169 Load { addr=v168, disp=0, kind=U16 } -> x1 - v170 BinopI { op=shr, lhs=v169, rhs_imm=12 } -> x1 - v171 BinopI { op=and, lhs=v170, rhs_imm=3 } -> x1 - v172 BinopI { op=shl, lhs=v171, rhs_imm=62 } -> x1 - v173 BinopI { op=shr, lhs=v172, rhs_imm=62 } -> x1 - v174 LoadLocal { off=-4, kind=I32 } -> x2 - v175 Binop { op=add, lhs=v173, rhs=v166 } -> x0 + v167 Imm(0) -> x0 + v168 LocalAddr(-3) -> x0 + v169 Load { addr=v168, disp=0, kind=U16 } -> x0 + v170 BinopI { op=shr, lhs=v169, rhs_imm=12 } -> x0 + v171 BinopI { op=and, lhs=v170, rhs_imm=3 } -> x0 + v172 BinopI { op=shl, lhs=v171, rhs_imm=62 } -> x0 + v173 BinopI { op=shr, lhs=v172, rhs_imm=62 } -> x0 + v174 LoadLocal { off=-4, kind=I32 } -> x1 + v175 BinopI { op=add, lhs=v173, rhs_imm=6 } -> x0 v176 BinopI { op=shl, lhs=v175, rhs_imm=32 } -> x1 v177 Extend { value=v175, kind=I32 } -> x0 v178 BinopI { op=ne, lhs=v177, rhs_imm=5 } -> x0 diff --git a/tests/snapshots/ssa/bitfield_storage_unit.ssa b/tests/snapshots/ssa/bitfield_storage_unit.ssa index cec1d4f1f..8dc4b1db2 100644 --- a/tests/snapshots/ssa/bitfield_storage_unit.ssa +++ b/tests/snapshots/ssa/bitfield_storage_unit.ssa @@ -5,29 +5,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(11) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(12) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(13) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) - block 7 start_pc=0 - v8 Imm(14) -> x0 - terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 v9 LocalAddr(-2) -> x0 v10 Imm(4) -> x1 v11 BinopI { op=add, lhs=v9, rhs_imm=4 } -> x0 @@ -35,11 +23,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v13 Imm(0) -> x2 v14 Binop { op=sub, lhs=v11, rhs=v12 } -> x0 v15 BinopI { op=ne, lhs=v14, rhs_imm=4 } -> x0 - terminator Bz { cond=v15, target=b10, fall=b9 } (exit_acc=v15) - block 9 start_pc=0 + terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) + block 5 start_pc=0 v16 Imm(15) -> x0 terminator Return(v16) (exit_acc=v16) - block 10 start_pc=0 + block 6 start_pc=0 v17 LocalAddr(-2) -> x0 v18 Imm(8) -> x1 v19 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x0 @@ -47,114 +35,114 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v21 Imm(0) -> x2 v22 Binop { op=sub, lhs=v19, rhs=v20 } -> x0 v23 BinopI { op=ne, lhs=v22, rhs_imm=8 } -> x0 - terminator Bz { cond=v23, target=b12, fall=b11 } (exit_acc=v23) - block 11 start_pc=0 + terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) + block 7 start_pc=0 v24 Imm(16) -> x0 terminator Return(v24) (exit_acc=v24) - block 12 start_pc=0 + block 8 start_pc=0 v25 LocalAddr(-3) -> x0 v26 Imm(171) -> x1 - v27 Load { addr=v25, disp=0, kind=U32 } -> x2 - v28 BinopI { op=and, lhs=v27, rhs_imm=-256 } -> x2 - v29 Binop { op=or, lhs=v28, rhs=v26 } -> x1 + v27 Load { addr=v25, disp=0, kind=U32 } -> x1 + v28 BinopI { op=and, lhs=v27, rhs_imm=-256 } -> x1 + v29 BinopI { op=or, lhs=v28, rhs_imm=171 } -> x1 v30 Store { addr=v25, disp=0, value=v29, kind=I32 } -> - v31 LocalAddr(-3) -> x0 v32 Imm(1) -> x1 v33 Load { addr=v31, disp=0, kind=U32 } -> x1 v34 BinopI { op=and, lhs=v33, rhs_imm=-257 } -> x1 v35 Imm(256) -> x2 - v36 Binop { op=or, lhs=v34, rhs=v35 } -> x1 + v36 BinopI { op=or, lhs=v34, rhs_imm=256 } -> x1 v37 Store { addr=v31, disp=0, value=v36, kind=I32 } -> - v38 LocalAddr(-3) -> x0 v39 Imm(74565) -> x1 v40 Load { addr=v38, disp=0, kind=U32 } -> x1 v41 BinopI { op=and, lhs=v40, rhs_imm=-4294966785 } -> x1 v42 Imm(38177280) -> x2 - v43 Binop { op=or, lhs=v41, rhs=v42 } -> x1 + v43 BinopI { op=or, lhs=v41, rhs_imm=38177280 } -> x1 v44 Store { addr=v38, disp=0, value=v43, kind=I32 } -> - v45 LocalAddr(-3) -> x0 v46 Load { addr=v45, disp=0, kind=U32 } -> x0 v47 BinopI { op=and, lhs=v46, rhs_imm=255 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=171 } -> x0 - terminator Bz { cond=v48, target=b14, fall=b13 } (exit_acc=v48) - block 13 start_pc=0 + terminator Bz { cond=v48, target=b10, fall=b9 } (exit_acc=v48) + block 9 start_pc=0 v49 Imm(17) -> x0 terminator Return(v49) (exit_acc=v49) - block 14 start_pc=0 + block 10 start_pc=0 v50 LocalAddr(-3) -> x0 v51 Load { addr=v50, disp=0, kind=U32 } -> x0 v52 BinopI { op=shr, lhs=v51, rhs_imm=8 } -> x0 v53 BinopI { op=and, lhs=v52, rhs_imm=1 } -> x0 v54 BinopI { op=ne, lhs=v53, rhs_imm=1 } -> x0 - terminator Bz { cond=v54, target=b16, fall=b15 } (exit_acc=v54) - block 15 start_pc=0 + terminator Bz { cond=v54, target=b12, fall=b11 } (exit_acc=v54) + block 11 start_pc=0 v55 Imm(18) -> x0 terminator Return(v55) (exit_acc=v55) - block 16 start_pc=0 + block 12 start_pc=0 v56 LocalAddr(-3) -> x0 v57 Load { addr=v56, disp=0, kind=U32 } -> x0 v58 BinopI { op=shr, lhs=v57, rhs_imm=9 } -> x0 v59 BinopI { op=and, lhs=v58, rhs_imm=8388607 } -> x0 v60 BinopI { op=ne, lhs=v59, rhs_imm=74565 } -> x0 - terminator Bz { cond=v60, target=b18, fall=b17 } (exit_acc=v60) - block 17 start_pc=0 + terminator Bz { cond=v60, target=b14, fall=b13 } (exit_acc=v60) + block 13 start_pc=0 v61 Imm(19) -> x0 terminator Return(v61) (exit_acc=v61) - block 18 start_pc=0 + block 14 start_pc=0 v62 LocalAddr(-3) -> x0 v63 Imm(85) -> x1 - v64 Load { addr=v62, disp=0, kind=U32 } -> x2 - v65 BinopI { op=and, lhs=v64, rhs_imm=-256 } -> x2 - v66 Binop { op=or, lhs=v65, rhs=v63 } -> x1 + v64 Load { addr=v62, disp=0, kind=U32 } -> x1 + v65 BinopI { op=and, lhs=v64, rhs_imm=-256 } -> x1 + v66 BinopI { op=or, lhs=v65, rhs_imm=85 } -> x1 v67 Store { addr=v62, disp=0, value=v66, kind=I32 } -> - v68 LocalAddr(-3) -> x0 v69 Load { addr=v68, disp=0, kind=U32 } -> x0 v70 BinopI { op=and, lhs=v69, rhs_imm=255 } -> x0 v71 BinopI { op=ne, lhs=v70, rhs_imm=85 } -> x0 - terminator Bz { cond=v71, target=b20, fall=b19 } (exit_acc=v71) - block 19 start_pc=0 + terminator Bz { cond=v71, target=b16, fall=b15 } (exit_acc=v71) + block 15 start_pc=0 v72 Imm(20) -> x0 terminator Return(v72) (exit_acc=v72) - block 20 start_pc=0 + block 16 start_pc=0 v73 LocalAddr(-3) -> x0 v74 Load { addr=v73, disp=0, kind=U32 } -> x0 v75 BinopI { op=shr, lhs=v74, rhs_imm=8 } -> x0 v76 BinopI { op=and, lhs=v75, rhs_imm=1 } -> x0 v77 BinopI { op=ne, lhs=v76, rhs_imm=1 } -> x0 - terminator Bz { cond=v77, target=b22, fall=b21 } (exit_acc=v77) - block 21 start_pc=0 + terminator Bz { cond=v77, target=b18, fall=b17 } (exit_acc=v77) + block 17 start_pc=0 v78 Imm(21) -> x0 terminator Return(v78) (exit_acc=v78) - block 22 start_pc=0 + block 18 start_pc=0 v79 LocalAddr(-3) -> x0 v80 Load { addr=v79, disp=0, kind=U32 } -> x0 v81 BinopI { op=shr, lhs=v80, rhs_imm=9 } -> x0 v82 BinopI { op=and, lhs=v81, rhs_imm=8388607 } -> x0 v83 BinopI { op=ne, lhs=v82, rhs_imm=74565 } -> x0 - terminator Bz { cond=v83, target=b24, fall=b23 } (exit_acc=v83) - block 23 start_pc=0 + terminator Bz { cond=v83, target=b20, fall=b19 } (exit_acc=v83) + block 19 start_pc=0 v84 Imm(22) -> x0 terminator Return(v84) (exit_acc=v84) - block 24 start_pc=0 + block 20 start_pc=0 v85 LocalAddr(-4) -> x0 v86 Imm(255) -> x1 - v87 Load { addr=v85, disp=0, kind=U32 } -> x2 - v88 BinopI { op=and, lhs=v87, rhs_imm=-256 } -> x2 - v89 Binop { op=or, lhs=v88, rhs=v86 } -> x1 + v87 Load { addr=v85, disp=0, kind=U32 } -> x1 + v88 BinopI { op=and, lhs=v87, rhs_imm=-256 } -> x1 + v89 BinopI { op=or, lhs=v88, rhs_imm=255 } -> x1 v90 Store { addr=v85, disp=0, value=v89, kind=I32 } -> - v91 LocalAddr(-4) -> x0 v92 Imm(1) -> x1 v93 Load { addr=v91, disp=0, kind=U32 } -> x1 v94 BinopI { op=and, lhs=v93, rhs_imm=-257 } -> x1 v95 Imm(256) -> x2 - v96 Binop { op=or, lhs=v94, rhs=v95 } -> x1 + v96 BinopI { op=or, lhs=v94, rhs_imm=256 } -> x1 v97 Store { addr=v91, disp=0, value=v96, kind=I32 } -> - v98 LocalAddr(-4) -> x0 v99 Imm(8388607) -> x1 v100 Load { addr=v98, disp=0, kind=U32 } -> x1 v101 BinopI { op=and, lhs=v100, rhs_imm=-4294966785 } -> x1 v102 Imm(4294966784) -> x2 - v103 Binop { op=or, lhs=v101, rhs=v102 } -> x1 + v103 BinopI { op=or, lhs=v101, rhs_imm=4294966784 } -> x1 v104 Store { addr=v98, disp=0, value=v103, kind=I32 } -> - v105 LocalAddr(-4) -> x0 v106 BinopI { op=add, lhs=v105, rhs_imm=4 } -> x1 @@ -180,35 +168,47 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v126 Load { addr=v124, disp=4, kind=U32 } -> x0 v127 BinopI { op=and, lhs=v126, rhs_imm=255 } -> x0 v128 BinopI { op=ne, lhs=v127, rhs_imm=0 } -> x0 - terminator Bz { cond=v128, target=b26, fall=b25 } (exit_acc=v128) - block 25 start_pc=0 + terminator Bz { cond=v128, target=b22, fall=b21 } (exit_acc=v128) + block 21 start_pc=0 v129 Imm(23) -> x0 terminator Return(v129) (exit_acc=v129) - block 26 start_pc=0 + block 22 start_pc=0 v130 LocalAddr(-4) -> x0 v131 BinopI { op=add, lhs=v130, rhs_imm=4 } -> x1 v132 Load { addr=v130, disp=4, kind=U32 } -> x0 v133 BinopI { op=shr, lhs=v132, rhs_imm=8 } -> x0 v134 BinopI { op=and, lhs=v133, rhs_imm=1 } -> x0 v135 BinopI { op=ne, lhs=v134, rhs_imm=0 } -> x0 - terminator Bz { cond=v135, target=b28, fall=b27 } (exit_acc=v135) - block 27 start_pc=0 + terminator Bz { cond=v135, target=b24, fall=b23 } (exit_acc=v135) + block 23 start_pc=0 v136 Imm(24) -> x0 terminator Return(v136) (exit_acc=v136) - block 28 start_pc=0 + block 24 start_pc=0 v137 LocalAddr(-4) -> x0 v138 BinopI { op=add, lhs=v137, rhs_imm=4 } -> x1 v139 Load { addr=v137, disp=4, kind=U32 } -> x0 v140 BinopI { op=shr, lhs=v139, rhs_imm=9 } -> x0 v141 BinopI { op=and, lhs=v140, rhs_imm=8388607 } -> x0 v142 BinopI { op=ne, lhs=v141, rhs_imm=0 } -> x0 - terminator Bz { cond=v142, target=b30, fall=b29 } (exit_acc=v142) - block 29 start_pc=0 + terminator Bz { cond=v142, target=b26, fall=b25 } (exit_acc=v142) + block 25 start_pc=0 v143 Imm(25) -> x0 terminator Return(v143) (exit_acc=v143) - block 30 start_pc=0 + block 26 start_pc=0 v144 Imm(0) -> x0 terminator Return(v144) (exit_acc=v144) + block 27 start_pc=0 + v2 Imm(11) -> x0 + terminator Return(v2) (exit_acc=v2) + block 28 start_pc=0 + v4 Imm(12) -> x0 + terminator Return(v4) (exit_acc=v4) + block 29 start_pc=0 + v6 Imm(13) -> x0 + terminator Return(v6) (exit_acc=v6) + block 30 start_pc=0 + v8 Imm(14) -> x0 + terminator Return(v8) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bitfields.ssa b/tests/snapshots/ssa/bitfields.ssa index 483b8824a..9da98fd91 100644 --- a/tests/snapshots/ssa/bitfields.ssa +++ b/tests/snapshots/ssa/bitfields.ssa @@ -6,36 +6,36 @@ fn ent_pc=5 n_params=0 variadic=false locals=3 v0 AllocaInit(0) -> - v1 LocalAddr(-2) -> x0 v2 Imm(1) -> x1 - v3 Load { addr=v1, disp=0, kind=U32 } -> x2 - v4 BinopI { op=and, lhs=v3, rhs_imm=-2 } -> x2 - v5 Binop { op=or, lhs=v4, rhs=v2 } -> x1 + v3 Load { addr=v1, disp=0, kind=U32 } -> x1 + v4 BinopI { op=and, lhs=v3, rhs_imm=-2 } -> x1 + v5 BinopI { op=or, lhs=v4, rhs_imm=1 } -> x1 v6 Store { addr=v1, disp=0, value=v5, kind=I32 } -> - v7 LocalAddr(-2) -> x0 v8 Imm(0) -> x1 - v9 Load { addr=v7, disp=0, kind=U32 } -> x2 - v10 BinopI { op=and, lhs=v9, rhs_imm=-3 } -> x2 - v11 Binop { op=or, lhs=v10, rhs=v8 } -> x1 + v9 Load { addr=v7, disp=0, kind=U32 } -> x1 + v10 BinopI { op=and, lhs=v9, rhs_imm=-3 } -> x1 + v11 BinopI { op=or, lhs=v10, rhs_imm=0 } -> x1 v12 Store { addr=v7, disp=0, value=v11, kind=I32 } -> - v13 LocalAddr(-2) -> x0 v14 Imm(5) -> x1 v15 Load { addr=v13, disp=0, kind=U32 } -> x1 v16 BinopI { op=and, lhs=v15, rhs_imm=-29 } -> x1 v17 Imm(20) -> x2 - v18 Binop { op=or, lhs=v16, rhs=v17 } -> x1 + v18 BinopI { op=or, lhs=v16, rhs_imm=20 } -> x1 v19 Store { addr=v13, disp=0, value=v18, kind=I32 } -> - v20 LocalAddr(-2) -> x0 v21 Imm(17) -> x1 v22 Load { addr=v20, disp=0, kind=U32 } -> x1 v23 BinopI { op=and, lhs=v22, rhs_imm=-993 } -> x1 v24 Imm(544) -> x2 - v25 Binop { op=or, lhs=v23, rhs=v24 } -> x1 + v25 BinopI { op=or, lhs=v23, rhs_imm=544 } -> x1 v26 Store { addr=v20, disp=0, value=v25, kind=I32 } -> - v27 LocalAddr(-2) -> x0 v28 BinopI { op=add, lhs=v27, rhs_imm=4 } -> x1 v29 Imm(305419896) -> x1 - v30 Load { addr=v27, disp=4, kind=U32 } -> x2 - v31 BinopI { op=and, lhs=v30, rhs_imm=-4294967296 } -> x2 - v32 Binop { op=or, lhs=v31, rhs=v29 } -> x1 + v30 Load { addr=v27, disp=4, kind=U32 } -> x1 + v31 BinopI { op=and, lhs=v30, rhs_imm=-4294967296 } -> x1 + v32 BinopI { op=or, lhs=v31, rhs_imm=305419896 } -> x1 v33 Store { addr=v27, disp=4, value=v32, kind=I32 } -> - v34 LocalAddr(-2) -> x0 v35 BinopI { op=add, lhs=v34, rhs_imm=8 } -> x1 @@ -100,9 +100,9 @@ fn ent_pc=5 n_params=0 variadic=false locals=3 block 12 start_pc=0 v71 LocalAddr(-2) -> x0 v72 Imm(0) -> x1 - v73 Load { addr=v71, disp=0, kind=U32 } -> x2 - v74 BinopI { op=and, lhs=v73, rhs_imm=-2 } -> x2 - v75 Binop { op=or, lhs=v74, rhs=v72 } -> x1 + v73 Load { addr=v71, disp=0, kind=U32 } -> x1 + v74 BinopI { op=and, lhs=v73, rhs_imm=-2 } -> x1 + v75 BinopI { op=or, lhs=v74, rhs_imm=0 } -> x1 v76 Store { addr=v71, disp=0, value=v75, kind=I32 } -> - v77 LocalAddr(-2) -> x0 v78 Load { addr=v77, disp=0, kind=U32 } -> x0 @@ -166,7 +166,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=3 v112 Load { addr=v110, disp=0, kind=U32 } -> x1 v113 BinopI { op=and, lhs=v112, rhs_imm=-29 } -> x1 v114 Imm(28) -> x2 - v115 Binop { op=or, lhs=v113, rhs=v114 } -> x1 + v115 BinopI { op=or, lhs=v113, rhs_imm=28 } -> x1 v116 Store { addr=v110, disp=0, value=v115, kind=I32 } -> - v117 LocalAddr(-2) -> x0 v118 Load { addr=v117, disp=0, kind=U32 } -> x0 @@ -199,41 +199,41 @@ fn ent_pc=5 n_params=0 variadic=false locals=3 block 30 start_pc=0 v134 LocalAddr(-3) -> x0 v135 Imm(1) -> x1 - v136 Load { addr=v134, disp=0, kind=U32 } -> x2 - v137 BinopI { op=and, lhs=v136, rhs_imm=-2 } -> x2 - v138 Binop { op=or, lhs=v137, rhs=v135 } -> x1 + v136 Load { addr=v134, disp=0, kind=U32 } -> x1 + v137 BinopI { op=and, lhs=v136, rhs_imm=-2 } -> x1 + v138 BinopI { op=or, lhs=v137, rhs_imm=1 } -> x1 v139 Store { addr=v134, disp=0, value=v138, kind=I32 } -> - v140 LocalAddr(-3) -> x0 v141 Load { addr=v140, disp=0, kind=U32 } -> x1 v142 BinopI { op=and, lhs=v141, rhs_imm=-3 } -> x1 v143 Imm(2) -> x2 - v144 Binop { op=or, lhs=v142, rhs=v143 } -> x1 + v144 BinopI { op=or, lhs=v142, rhs_imm=2 } -> x1 v145 Store { addr=v140, disp=0, value=v144, kind=I32 } -> - v146 LocalAddr(-3) -> x0 v147 Imm(0) -> x1 - v148 Load { addr=v146, disp=0, kind=U32 } -> x2 - v149 BinopI { op=and, lhs=v148, rhs_imm=-5 } -> x2 - v150 Binop { op=or, lhs=v149, rhs=v147 } -> x1 + v148 Load { addr=v146, disp=0, kind=U32 } -> x1 + v149 BinopI { op=and, lhs=v148, rhs_imm=-5 } -> x1 + v150 BinopI { op=or, lhs=v149, rhs_imm=0 } -> x1 v151 Store { addr=v146, disp=0, value=v150, kind=I32 } -> - v152 LocalAddr(-3) -> x0 v153 Load { addr=v152, disp=0, kind=U32 } -> x1 v154 BinopI { op=and, lhs=v153, rhs_imm=-9 } -> x1 v155 Imm(8) -> x2 - v156 Binop { op=or, lhs=v154, rhs=v155 } -> x1 + v156 BinopI { op=or, lhs=v154, rhs_imm=8 } -> x1 v157 Store { addr=v152, disp=0, value=v156, kind=I32 } -> - v158 LocalAddr(-3) -> x0 v159 Imm(11) -> x1 v160 Load { addr=v158, disp=0, kind=U32 } -> x1 v161 BinopI { op=and, lhs=v160, rhs_imm=-241 } -> x1 v162 Imm(176) -> x2 - v163 Binop { op=or, lhs=v161, rhs=v162 } -> x1 + v163 BinopI { op=or, lhs=v161, rhs_imm=176 } -> x1 v164 Store { addr=v158, disp=0, value=v163, kind=I32 } -> - v165 LocalAddr(-3) -> x0 v166 Imm(200) -> x1 v167 Load { addr=v165, disp=0, kind=U32 } -> x1 v168 BinopI { op=and, lhs=v167, rhs_imm=-65281 } -> x1 v169 Imm(51200) -> x2 - v170 Binop { op=or, lhs=v168, rhs=v169 } -> x1 + v170 BinopI { op=or, lhs=v168, rhs_imm=51200 } -> x1 v171 Store { addr=v165, disp=0, value=v170, kind=I32 } -> - v172 LocalAddr(-3) -> x0 v173 Load { addr=v172, disp=0, kind=U32 } -> x0 diff --git a/tests/snapshots/ssa/bitop_common_type.ssa b/tests/snapshots/ssa/bitop_common_type.ssa index 487562fca..d761c105b 100644 --- a/tests/snapshots/ssa/bitop_common_type.ssa +++ b/tests/snapshots/ssa/bitop_common_type.ssa @@ -5,86 +5,86 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(5369163776) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I64 } -> x2 - v6 LoadLocal { off=-2, kind=I64 } -> x2 - v7 Binop { op=or, lhs=v1, rhs=v3 } -> x2 - v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x2 - v9 BinopI { op=ne, lhs=v8, rhs_imm=5369163777 } -> x2 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I64 } -> x0 + v6 LoadLocal { off=-2, kind=I64 } -> x0 + v7 Imm(5369163776) -> x0 + v8 Imm(5369163777) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) + v11 LoadLocal { off=-1, kind=I64 } -> x0 + v12 LoadLocal { off=-2, kind=I64 } -> x0 + v13 Imm(-1) -> x0 + v14 Imm(5369163776) -> x0 + v15 Imm(5369163777) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v11 LoadLocal { off=-1, kind=I64 } -> x2 - v12 LoadLocal { off=-2, kind=I64 } -> x2 - v13 BinopI { op=xor, lhs=v3, rhs_imm=-1 } -> x2 - v14 Binop { op=and, lhs=v1, rhs=v13 } -> x2 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x2 - v16 BinopI { op=ne, lhs=v15, rhs_imm=5369163777 } -> x2 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + v18 LoadLocal { off=-1, kind=I64 } -> x0 + v19 LoadLocal { off=-2, kind=I64 } -> x0 + v20 Imm(5369163776) -> x0 + v21 Imm(5369163777) -> x0 + v22 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v22) block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) + v24 Imm(5369163777) -> x0 + v25 Imm(0) -> x0 + v26 LoadLocal { off=-3, kind=I64 } -> x0 + v27 Imm(5369163776) -> x0 + v28 Imm(15) -> x0 + v29 Imm(64424509440) -> x0 + v30 Imm(5369163791) -> x0 + v31 Imm(5369163792) -> x0 + v32 Imm(0) -> x0 + v33 LoadLocal { off=-4, kind=I64 } -> x0 + v34 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v34) block 4 start_pc=0 - v18 LoadLocal { off=-1, kind=I64 } -> x2 - v19 LoadLocal { off=-2, kind=I64 } -> x2 - v20 Binop { op=xor, lhs=v1, rhs=v3 } -> x2 - v21 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x2 - v22 BinopI { op=ne, lhs=v21, rhs_imm=5369163777 } -> x2 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v36 LoadLocal { off=-1, kind=I64 } -> x0 + v37 LoadLocal { off=-2, kind=I64 } -> x0 + v38 Imm(5369163776) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v39) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v41 LoadLocal { off=-1, kind=I64 } -> x0 + v42 LoadLocal { off=-2, kind=I64 } -> x0 + v43 Imm(5369163776) -> x0 + v44 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v44) block 6 start_pc=0 - v24 Imm(5369163777) -> x2 - v25 Imm(0) -> x6 - v26 LoadLocal { off=-3, kind=I64 } -> x6 - v27 BinopI { op=sub, lhs=v24, rhs_imm=1 } -> x2 - v28 Imm(15) -> x6 - v29 Imm(64424509440) -> x6 - v30 BinopI { op=or, lhs=v27, rhs_imm=15 } -> x2 - v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x2 - v32 Imm(0) -> x6 - v33 LoadLocal { off=-4, kind=I64 } -> x6 - v34 BinopI { op=ne, lhs=v31, rhs_imm=5369163792 } -> x2 - terminator Bz { cond=v34, target=b8, fall=b7 } (exit_acc=v34) + v46 LoadLocal { off=-1, kind=I64 } -> x0 + v47 LoadLocal { off=-2, kind=I64 } -> x0 + v48 Imm(5369163776) -> x0 + v49 Imm(1) -> x0 + v50 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v50) block 7 start_pc=0 - v35 Imm(4) -> x0 - terminator Return(v35) (exit_acc=v35) + v52 Imm(0) -> x0 + terminator Return(v52) (exit_acc=v52) block 8 start_pc=0 - v36 LoadLocal { off=-1, kind=I64 } -> x2 - v37 LoadLocal { off=-2, kind=I64 } -> x2 - v38 Binop { op=or, lhs=v1, rhs=v3 } -> x2 - v39 BinopI { op=ne, lhs=v38, rhs_imm=5369163776 } -> x2 - terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) + v10 Imm(1) -> x0 + terminator Return(v10) (exit_acc=v10) block 9 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v17 Imm(2) -> x0 + terminator Return(v17) (exit_acc=v17) block 10 start_pc=0 - v41 LoadLocal { off=-1, kind=I64 } -> x2 - v42 LoadLocal { off=-2, kind=I64 } -> x2 - v43 Binop { op=or, lhs=v1, rhs=v3 } -> x2 - v44 BinopI { op=ne, lhs=v43, rhs_imm=5369163776 } -> x2 - terminator Bz { cond=v44, target=b12, fall=b11 } (exit_acc=v44) + v23 Imm(3) -> x0 + terminator Return(v23) (exit_acc=v23) block 11 start_pc=0 - v45 Imm(6) -> x0 - terminator Return(v45) (exit_acc=v45) + v35 Imm(4) -> x0 + terminator Return(v35) (exit_acc=v35) block 12 start_pc=0 - v46 LoadLocal { off=-1, kind=I64 } -> x2 - v47 LoadLocal { off=-2, kind=I64 } -> x2 - v48 Binop { op=or, lhs=v1, rhs=v3 } -> x0 - v49 BinopI { op=ugt, lhs=v48, rhs_imm=4294967296 } -> x0 - v50 BinopI { op=eq, lhs=v49, rhs_imm=0 } -> x0 - terminator Bz { cond=v50, target=b14, fall=b13 } (exit_acc=v50) + v40 Imm(5) -> x0 + terminator Return(v40) (exit_acc=v40) block 13 start_pc=0 + v45 Imm(6) -> x0 + terminator Return(v45) (exit_acc=v45) + block 14 start_pc=0 v51 Imm(7) -> x0 terminator Return(v51) (exit_acc=v51) - block 14 start_pc=0 - v52 Imm(0) -> x0 - terminator Return(v52) (exit_acc=v52) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bitop_common_type_sign_extend.ssa b/tests/snapshots/ssa/bitop_common_type_sign_extend.ssa index 63da5fd8b..10302f193 100644 --- a/tests/snapshots/ssa/bitop_common_type_sign_extend.ssa +++ b/tests/snapshots/ssa/bitop_common_type_sign_extend.ssa @@ -114,67 +114,55 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294966722) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Extend { value=v2, kind=I32 } -> x2 - v5 Imm(0) -> x2 - v6 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 - v7 Binop { op=or, lhs=v6, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=-574 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(4294966722) -> x0 + v7 Imm(4294966722) -> x0 + v8 Imm(-2465311227904) -> x0 + v9 Imm(-574) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(0) -> x0 - v13 Imm(4294966722) -> x1 - v14 Extend { value=v12, kind=I32 } -> x2 - v15 Imm(0) -> x2 - v16 Imm(0) -> x2 - v17 BinopI { op=and, lhs=v13, rhs_imm=4294967295 } -> x1 - v18 Binop { op=or, lhs=v12, rhs=v17 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=-574 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) - block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) - block 4 start_pc=0 + v13 Imm(4294966722) -> x0 + v14 Imm(0) -> x0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + v17 Imm(4294966722) -> x0 + v18 Imm(4294966722) -> x0 + v19 Imm(-2465311227904) -> x0 + v20 Imm(-574) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 v23 Imm(4294966722) -> x0 - v24 Imm(0) -> x1 - v25 Imm(0) -> x2 - v26 Extend { value=v24, kind=I32 } -> x2 - v27 Imm(0) -> x2 - v28 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x0 - v29 Binop { op=xor, lhs=v28, rhs=v24 } -> x0 - v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x1 - v31 Extend { value=v29, kind=I32 } -> x0 - v32 BinopI { op=ne, lhs=v31, rhs_imm=-574 } -> x0 - terminator Bz { cond=v32, target=b6, fall=b5 } (exit_acc=v32) - block 5 start_pc=0 - v33 Imm(3) -> x0 - terminator Return(v33) (exit_acc=v33) - block 6 start_pc=0 + v24 Imm(0) -> x0 + v25 Imm(0) -> x0 + v26 Imm(0) -> x0 + v27 Imm(0) -> x0 + v28 Imm(4294966722) -> x0 + v29 Imm(4294966722) -> x0 + v30 Imm(-2465311227904) -> x0 + v31 Imm(-574) -> x0 + v32 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v32) + block 3 start_pc=0 v34 Imm(4294967295) -> x0 - v35 Imm(4294966722) -> x1 - v36 Imm(-2465311227904) -> x1 - v37 Imm(-574) -> x1 - v38 Imm(0) -> x2 - v39 Extend { value=v37, kind=I32 } -> x2 - v40 Imm(0) -> x2 - v41 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x0 - v42 Binop { op=and, lhs=v41, rhs=v37 } -> x0 - v43 BinopI { op=shl, lhs=v42, rhs_imm=32 } -> x1 - v44 Extend { value=v42, kind=I32 } -> x0 - v45 BinopI { op=ne, lhs=v44, rhs_imm=-574 } -> x0 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) - block 7 start_pc=0 - v46 Imm(4) -> x0 - terminator Return(v46) (exit_acc=v46) - block 8 start_pc=0 + v35 Imm(4294966722) -> x0 + v36 Imm(-2465311227904) -> x0 + v37 Imm(-574) -> x0 + v38 Imm(0) -> x0 + v39 Imm(-574) -> x0 + v40 Imm(0) -> x0 + v41 Imm(4294967295) -> x0 + v42 Imm(4294966722) -> x0 + v43 Imm(-2465311227904) -> x0 + v44 Imm(-574) -> x0 + v45 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v45) + block 4 start_pc=0 v47 LocalAddr(-1) -> x0 v48 ImmData(8) -> x1 v49 Mcpy { dst=v47, src=v48, size=4 } -> x0 @@ -213,13 +201,25 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v82 Imm(0) -> x2 v83 Binop { op=sub, lhs=v81, rhs=v52 } -> x0 v84 BinopI { op=ne, lhs=v83, rhs_imm=-574 } -> x0 - terminator Bz { cond=v84, target=b10, fall=b9 } (exit_acc=v84) - block 9 start_pc=0 + terminator Bz { cond=v84, target=b6, fall=b5 } (exit_acc=v84) + block 5 start_pc=0 v85 Imm(5) -> x0 terminator Return(v85) (exit_acc=v85) - block 10 start_pc=0 + block 6 start_pc=0 v86 Imm(0) -> x0 terminator Return(v86) (exit_acc=v86) + block 7 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 8 start_pc=0 + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) + block 9 start_pc=0 + v33 Imm(3) -> x0 + terminator Return(v33) (exit_acc=v33) + block 10 start_pc=0 + v46 Imm(4) -> x0 + terminator Return(v46) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/block_extern_shadows_local.ssa b/tests/snapshots/ssa/block_extern_shadows_local.ssa index 82d25a647..3867d05d4 100644 --- a/tests/snapshots/ssa/block_extern_shadows_local.ssa +++ b/tests/snapshots/ssa/block_extern_shadows_local.ssa @@ -5,13 +5,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(9) -> x0 - v2 Imm(0) -> x1 - v3 ImmData(32) -> x1 - v4 Load { addr=v3, disp=0, kind=I32 } -> x1 - v5 Imm(0) -> x2 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 LoadLocal { off=-1, kind=I32 } -> x2 - v8 Binop { op=add, lhs=v4, rhs=v1 } -> x0 + v2 Imm(0) -> x0 + v3 ImmData(32) -> x0 + v4 Load { addr=v3, disp=0, kind=I32 } -> x0 + v5 Imm(0) -> x1 + v6 Extend { value=v4, kind=I32 } -> x1 + v7 LoadLocal { off=-1, kind=I32 } -> x1 + v8 BinopI { op=add, lhs=v4, rhs_imm=9 } -> x0 v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x1 v10 Extend { value=v8, kind=I32 } -> x0 terminator Return(v10) (exit_acc=v10) @@ -39,85 +39,85 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(5) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=ne, lhs=v1, rhs_imm=5 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 Imm(5) -> x0 - v7 Imm(0) -> x1 - v8 Imm(0) -> x1 - v9 Imm(0) -> x2 - v10 LoadLocal { off=-3, kind=I32 } -> x2 - v11 ImmData(8) -> x2 - v12 Load { addr=v11, disp=0, kind=I32 } -> x6 - v13 Binop { op=add, lhs=v8, rhs=v12 } -> x1 - v14 Imm(0) -> x6 - v15 Extend { value=v13, kind=I32 } -> x6 - v16 Imm(7) -> x6 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-3, kind=I32 } -> x0 + v11 ImmData(8) -> x0 + v12 Load { addr=v11, disp=0, kind=I32 } -> x1 + v13 BinopI { op=add, lhs=v12, rhs_imm=0 } -> x1 + v14 Imm(0) -> x2 + v15 Extend { value=v13, kind=I32 } -> x2 + v16 Imm(7) -> x2 v17 Store { addr=v11, disp=0, value=v16, kind=I32 } -> - - v18 Extend { value=v13, kind=I32 } -> x2 - v19 LoadLocal { off=-2, kind=I32 } -> x2 - v20 Binop { op=add, lhs=v13, rhs=v6 } -> x1 - v21 Imm(0) -> x2 - v22 Extend { value=v20, kind=I32 } -> x1 - v23 BinopI { op=ne, lhs=v22, rhs_imm=105 } -> x1 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) - block 3 start_pc=0 + v18 Extend { value=v13, kind=I32 } -> x0 + v19 LoadLocal { off=-2, kind=I32 } -> x0 + v20 BinopI { op=add, lhs=v13, rhs_imm=5 } -> x0 + v21 Imm(0) -> x1 + v22 Extend { value=v20, kind=I32 } -> x0 + v23 BinopI { op=ne, lhs=v22, rhs_imm=105 } -> x0 + terminator Bz { cond=v23, target=b3, fall=b2 } (exit_acc=v23) + block 2 start_pc=0 v24 Imm(2) -> x0 terminator Return(v24) (exit_acc=v24) + block 3 start_pc=0 + v25 LoadLocal { off=-2, kind=I32 } -> x0 + v26 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v26) block 4 start_pc=0 - v25 LoadLocal { off=-2, kind=I32 } -> x1 - v26 BinopI { op=ne, lhs=v6, rhs_imm=5 } -> x0 - terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) - block 5 start_pc=0 - v27 Imm(3) -> x0 - terminator Return(v27) (exit_acc=v27) - block 6 start_pc=0 v28 ImmData(8) -> x0 v29 Load { addr=v28, disp=0, kind=I32 } -> x0 v30 BinopI { op=ne, lhs=v29, rhs_imm=7 } -> x0 - terminator Bz { cond=v30, target=b8, fall=b7 } (exit_acc=v30) - block 7 start_pc=0 + terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + block 5 start_pc=0 v31 Imm(4) -> x0 terminator Return(v31) (exit_acc=v31) - block 8 start_pc=0 + block 6 start_pc=0 v32 Imm(9) -> x0 - v33 Imm(0) -> x1 - v34 ImmData(32) -> x1 - v35 Load { addr=v34, disp=0, kind=I32 } -> x1 - v36 Imm(0) -> x2 - v37 Extend { value=v35, kind=I32 } -> x2 - v38 Binop { op=add, lhs=v35, rhs=v32 } -> x0 + v33 Imm(0) -> x0 + v34 ImmData(32) -> x0 + v35 Load { addr=v34, disp=0, kind=I32 } -> x0 + v36 Imm(0) -> x1 + v37 Extend { value=v35, kind=I32 } -> x1 + v38 BinopI { op=add, lhs=v35, rhs_imm=9 } -> x0 v39 BinopI { op=shl, lhs=v38, rhs_imm=32 } -> x1 v40 Extend { value=v38, kind=I32 } -> x0 v41 BinopI { op=ne, lhs=v40, rhs_imm=64 } -> x0 - terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) - block 9 start_pc=0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) + block 7 start_pc=0 v42 Imm(5) -> x0 terminator Return(v42) (exit_acc=v42) - block 10 start_pc=0 + block 8 start_pc=0 v43 Imm(3) -> x0 - v44 Extend { value=v43, kind=I32 } -> x1 - v45 Imm(0) -> x1 - v46 ImmData(16) -> x1 - v47 Load { addr=v46, disp=0, kind=I32 } -> x1 - v48 Imm(0) -> x2 - v49 Extend { value=v47, kind=I32 } -> x2 - v50 Binop { op=add, lhs=v47, rhs=v43 } -> x0 + v44 Imm(3) -> x0 + v45 Imm(0) -> x0 + v46 ImmData(16) -> x0 + v47 Load { addr=v46, disp=0, kind=I32 } -> x0 + v48 Imm(0) -> x1 + v49 Extend { value=v47, kind=I32 } -> x1 + v50 BinopI { op=add, lhs=v47, rhs_imm=3 } -> x0 v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x1 v52 Extend { value=v50, kind=I32 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=80 } -> x0 - terminator Bz { cond=v53, target=b12, fall=b11 } (exit_acc=v53) - block 11 start_pc=0 + terminator Bz { cond=v53, target=b10, fall=b9 } (exit_acc=v53) + block 9 start_pc=0 v54 Imm(6) -> x0 terminator Return(v54) (exit_acc=v54) - block 12 start_pc=0 + block 10 start_pc=0 v55 Imm(0) -> x0 terminator Return(v55) (exit_acc=v55) + block 11 start_pc=0 + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) + block 12 start_pc=0 + v27 Imm(3) -> x0 + terminator Return(v27) (exit_acc=v27) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/block_scope_extern.ssa b/tests/snapshots/ssa/block_scope_extern.ssa index b867c6eec..476ce067a 100644 --- a/tests/snapshots/ssa/block_scope_extern.ssa +++ b/tests/snapshots/ssa/block_scope_extern.ssa @@ -65,19 +65,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v39 Store { addr=v37, disp=0, value=v38, kind=I32 } -> - v40 Extend { value=v38, kind=I32 } -> x0 v41 BinopI { op=eq, lhs=v40, rhs_imm=9 } -> x0 - terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) + terminator Bz { cond=v41, target=b13, fall=b11 } (exit_acc=v41) block 11 start_pc=0 v42 Imm(0) -> x1 v43 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v42) + terminator Jmp(b12) (exit_acc=v42) block 12 start_pc=0 - v44 Imm(5) -> x1 - v45 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v44) - block 13 start_pc=0 - v46 Phi { incoming=[b11:v42, b12:v44], kind=I64 } -> x1 + v46 Phi { incoming=[b11:v42, b13:v44], kind=I64 } -> x1 v47 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v46) (exit_acc=v46) + block 13 start_pc=0 + v44 Imm(5) -> x1 + v45 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v44) block 14 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/block_scope_function_declaration.ssa b/tests/snapshots/ssa/block_scope_function_declaration.ssa index 0939602ad..2e6290d25 100644 --- a/tests/snapshots/ssa/block_scope_function_declaration.ssa +++ b/tests/snapshots/ssa/block_scope_function_declaration.ssa @@ -10,13 +10,25 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b6, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -24,140 +36,124 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 LoadLocal { off=3, kind=I64 } -> x1 v19 Load { addr=v6, disp=0, kind=I8 } -> x1 v20 Binop { op=eq, lhs=v17, rhs=v19 } -> x0 terminator Return(v20) (exit_acc=v20) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b6:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(40) -> x0 - v2 Imm(2) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=42 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(2) -> x0 + v3 Imm(40) -> x0 + v4 Imm(0) -> x0 + v5 Imm(2) -> x0 + v6 Imm(0) -> x0 + v7 Imm(42) -> x0 + v8 Imm(180388626432) -> x0 + v9 Imm(42) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 ImmData(19) -> x7 v13 ImmData(8) -> x6 v14 Call { target_pc=0, args=[v12, v13], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 3 start_pc=0 + terminator Bz { cond=v15, target=b3, fall=b2 } (exit_acc=v15) + block 2 start_pc=0 v16 Imm(2) -> x0 terminator Return(v16) (exit_acc=v16) - block 4 start_pc=0 + block 3 start_pc=0 v17 Imm(1) -> x0 - v18 Imm(2) -> x1 - v19 Extend { value=v17, kind=I32 } -> x2 - v20 Imm(0) -> x2 - v21 Extend { value=v18, kind=I32 } -> x2 - v22 Imm(0) -> x2 - v23 Binop { op=add, lhs=v17, rhs=v18 } -> x0 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x1 - v25 Extend { value=v23, kind=I32 } -> x0 - v26 BinopI { op=ne, lhs=v25, rhs_imm=3 } -> x3 + v18 Imm(2) -> x0 + v19 Imm(1) -> x0 + v20 Imm(0) -> x0 + v21 Imm(2) -> x0 + v22 Imm(0) -> x0 + v23 Imm(3) -> x0 + v24 Imm(12884901888) -> x0 + v25 Imm(3) -> x0 + v26 Imm(0) -> x1 v27 Imm(0) -> x0 - terminator Bnz { cond=v26, target=b17, fall=b5 } (exit_acc=v26) - block 5 start_pc=0 + terminator Jmp(b4) (exit_acc=v26) + block 4 start_pc=0 v28 ImmData(19) -> x7 v29 ImmData(11) -> x6 v30 Call { target_pc=0, args=[v28, v29], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v31 BinopI { op=eq, lhs=v30, rhs_imm=0 } -> x3 + v31 BinopI { op=eq, lhs=v30, rhs_imm=0 } -> x1 v32 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v31) - block 6 start_pc=0 - v33 Phi { incoming=[b17:v26, b5:v31], kind=I64 } -> x3 + terminator Jmp(b5) (exit_acc=v31) + block 5 start_pc=0 + v33 Phi { incoming=[b3:v26, b4:v31], kind=I64 } -> x1 v34 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) - block 7 start_pc=0 + terminator Bz { cond=v33, target=b7, fall=b6 } (exit_acc=v33) + block 6 start_pc=0 v35 Imm(3) -> x0 terminator Return(v35) (exit_acc=v35) - block 8 start_pc=0 + block 7 start_pc=0 v36 ImmData(14) -> x7 v37 CallExt { binding_idx=5, args=[v36], fp_arg_mask=0x0 } -> x0 v38 BinopI { op=ne, lhs=v37, rhs_imm=4 } -> x0 - terminator Bz { cond=v38, target=b10, fall=b9 } (exit_acc=v38) - block 9 start_pc=0 + terminator Bz { cond=v38, target=b9, fall=b8 } (exit_acc=v38) + block 8 start_pc=0 v39 Imm(4) -> x0 terminator Return(v39) (exit_acc=v39) - block 10 start_pc=0 + block 9 start_pc=0 v40 Imm(5) -> x0 - v41 Imm(0) -> x1 - v42 Imm(1) -> x1 - v43 Imm(2) -> x2 - v44 Imm(3) -> x6 - v45 Extend { value=v42, kind=I32 } -> x7 - v46 Imm(0) -> x7 - v47 Extend { value=v43, kind=I32 } -> x7 - v48 Imm(0) -> x7 - v49 Extend { value=v44, kind=I32 } -> x7 - v50 Imm(0) -> x7 - v51 Binop { op=add, lhs=v42, rhs=v43 } -> x1 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x2 - v53 Extend { value=v51, kind=I32 } -> x2 - v54 Binop { op=add, lhs=v51, rhs=v44 } -> x1 - v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x2 - v56 Extend { value=v54, kind=I32 } -> x1 - v57 BinopI { op=ne, lhs=v56, rhs_imm=6 } -> x2 - v58 Imm(0) -> x1 - terminator Bnz { cond=v57, target=b18, fall=b11 } (exit_acc=v57) - block 11 start_pc=0 - v59 LoadLocal { off=-1, kind=I32 } -> x1 - v60 BinopI { op=ne, lhs=v40, rhs_imm=5 } -> x2 + v41 Imm(0) -> x0 + v42 Imm(1) -> x0 + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(1) -> x0 + v46 Imm(0) -> x0 + v47 Imm(2) -> x0 + v48 Imm(0) -> x0 + v49 Imm(3) -> x0 + v50 Imm(0) -> x0 + v51 Imm(3) -> x0 + v52 Imm(12884901888) -> x0 + v53 Imm(3) -> x0 + v54 Imm(6) -> x0 + v55 Imm(25769803776) -> x0 + v56 Imm(6) -> x0 + v57 Imm(0) -> x1 + v58 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v57) + block 10 start_pc=0 + v59 LoadLocal { off=-1, kind=I32 } -> x0 + v60 Imm(0) -> x1 v61 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v60) - block 12 start_pc=0 - v62 Phi { incoming=[b18:v57, b11:v60], kind=I64 } -> x2 + terminator Jmp(b11) (exit_acc=v60) + block 11 start_pc=0 + v62 Phi { incoming=[b9:v57, b10:v60], kind=I64 } -> x1 v63 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v62, target=b14, fall=b13 } (exit_acc=v62) - block 13 start_pc=0 + terminator Bz { cond=v62, target=b13, fall=b12 } (exit_acc=v62) + block 12 start_pc=0 v64 Imm(5) -> x0 terminator Return(v64) (exit_acc=v64) - block 14 start_pc=0 + block 13 start_pc=0 v65 Imm(7) -> x0 - v66 Imm(0) -> x1 - v67 LoadLocal { off=-2, kind=I32 } -> x1 - v68 BinopI { op=ne, lhs=v65, rhs_imm=7 } -> x0 - terminator Bz { cond=v68, target=b16, fall=b15 } (exit_acc=v68) + v66 Imm(0) -> x0 + v67 LoadLocal { off=-2, kind=I32 } -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v68) + block 14 start_pc=0 + v70 Imm(0) -> x0 + terminator Return(v70) (exit_acc=v70) block 15 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 16 start_pc=0 v69 Imm(6) -> x0 terminator Return(v69) (exit_acc=v69) - block 16 start_pc=0 - v70 Imm(0) -> x0 - terminator Return(v70) (exit_acc=v70) - block 17 start_pc=0 - terminator Jmp(b6) - block 18 start_pc=0 - terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=sum3 fn ent_pc=2 n_params=3 variadic=false locals=0 diff --git a/tests/snapshots/ssa/bool_normalize_c99.ssa b/tests/snapshots/ssa/bool_normalize_c99.ssa index c9f943d5c..fe66d3a0d 100644 --- a/tests/snapshots/ssa/bool_normalize_c99.ssa +++ b/tests/snapshots/ssa/bool_normalize_c99.ssa @@ -26,265 +26,263 @@ fn ent_pc=2 n_params=0 variadic=false locals=19 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(5) -> x0 v4 Imm(1) -> x0 - v5 Imm(0) -> x1 - v6 LoadLocal { off=-1, kind=U8 } -> x1 - v7 BinopI { op=ne, lhs=v4, rhs_imm=1 } -> x1 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v5 Imm(0) -> x0 + v6 LoadLocal { off=-1, kind=U8 } -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 LoadLocal { off=-2, kind=U8 } -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v12) block 3 start_pc=0 - v8 Imm(2) -> x0 - terminator Return(v8) (exit_acc=v8) + v14 Imm(-7) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 LoadLocal { off=-3, kind=U8 } -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v9 Imm(0) -> x1 - v10 Imm(0) -> x2 - v11 LoadLocal { off=-2, kind=U8 } -> x2 - v12 BinopI { op=ne, lhs=v9, rhs_imm=0 } -> x2 - terminator Bz { cond=v12, target=b6, fall=b5 } (exit_acc=v12) + v20 Imm(256) -> x0 + v21 Imm(1) -> x0 + v22 Imm(0) -> x0 + v23 LoadLocal { off=-4, kind=U8 } -> x0 + v24 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v24) block 5 start_pc=0 - v13 Imm(3) -> x0 - terminator Return(v13) (exit_acc=v13) + v26 Imm(42) -> x0 + v27 Imm(1) -> x0 + v28 Imm(0) -> x0 + v29 LoadLocal { off=-5, kind=U8 } -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v30) block 6 start_pc=0 - v14 Imm(-7) -> x2 - v15 Imm(1) -> x2 - v16 Imm(0) -> x6 - v17 LoadLocal { off=-3, kind=U8 } -> x6 - v18 BinopI { op=ne, lhs=v15, rhs_imm=1 } -> x6 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) + v32 Imm(3) -> x0 + v33 StoreLocal { off=-6, value=v32, kind=I32 } -> - + v34 LocalAddr(-6) -> x0 + v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x0 + v36 Imm(0) -> x1 + v37 BinopI { op=and, lhs=v35, rhs_imm=255 } -> x0 + v38 BinopI { op=ne, lhs=v37, rhs_imm=1 } -> x0 + terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) block 7 start_pc=0 - v19 Imm(4) -> x0 - terminator Return(v19) (exit_acc=v19) + v39 Imm(7) -> x0 + terminator Return(v39) (exit_acc=v39) block 8 start_pc=0 - v20 Imm(256) -> x6 - v21 Imm(1) -> x6 - v22 Imm(0) -> x7 - v23 LoadLocal { off=-4, kind=U8 } -> x7 - v24 BinopI { op=ne, lhs=v21, rhs_imm=1 } -> x6 - terminator Bz { cond=v24, target=b10, fall=b9 } (exit_acc=v24) + v40 Imm(4602678819172646912) -> x0 + v41 Imm(0) -> x1 + v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 + v43 Imm(0) -> x1 + v44 BinopI { op=and, lhs=v42, rhs_imm=255 } -> x0 + v45 BinopI { op=ne, lhs=v44, rhs_imm=1 } -> x0 + terminator Bz { cond=v45, target=b10, fall=b9 } (exit_acc=v45) block 9 start_pc=0 - v25 Imm(5) -> x0 - terminator Return(v25) (exit_acc=v25) + v46 Imm(8) -> x0 + terminator Return(v46) (exit_acc=v46) block 10 start_pc=0 - v26 Imm(42) -> x6 - v27 Imm(1) -> x6 - v28 Imm(0) -> x7 - v29 LoadLocal { off=-5, kind=U8 } -> x7 - v30 BinopI { op=ne, lhs=v27, rhs_imm=1 } -> x6 - terminator Bz { cond=v30, target=b12, fall=b11 } (exit_acc=v30) + v47 Imm(0) -> x0 + v48 Binop { op=fne, lhs=v47, rhs=v47 } -> x0 + v49 Imm(0) -> x1 + v50 BinopI { op=and, lhs=v48, rhs_imm=255 } -> x0 + v51 BinopI { op=ne, lhs=v50, rhs_imm=0 } -> x0 + terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) block 11 start_pc=0 - v31 Imm(6) -> x0 - terminator Return(v31) (exit_acc=v31) + v52 Imm(9) -> x0 + terminator Return(v52) (exit_acc=v52) block 12 start_pc=0 - v32 Imm(3) -> x6 - v33 StoreLocal { off=-6, value=v32, kind=I32 } -> - - v34 LocalAddr(-6) -> x6 - v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x6 - v36 Imm(0) -> x7 - v37 BinopI { op=and, lhs=v35, rhs_imm=255 } -> x6 - v38 BinopI { op=ne, lhs=v37, rhs_imm=1 } -> x6 - terminator Bz { cond=v38, target=b14, fall=b13 } (exit_acc=v38) + v53 LocalAddr(-11) -> x0 + v54 Imm(99) -> x1 + v55 Imm(1) -> x1 + v56 Store { addr=v53, disp=0, value=v55, kind=I8 } -> - + v57 LocalAddr(-11) -> x0 + v58 BinopI { op=add, lhs=v57, rhs_imm=4 } -> x1 + v59 Imm(7) -> x1 + v60 Store { addr=v57, disp=4, value=v59, kind=I32 } -> - + v61 LocalAddr(-11) -> x0 + v62 BinopI { op=add, lhs=v61, rhs_imm=8 } -> x1 + v63 Imm(0) -> x1 + v64 Store { addr=v61, disp=8, value=v63, kind=I8 } -> - + v65 LocalAddr(-11) -> x0 + v66 Load { addr=v65, disp=0, kind=U8 } -> x0 + v67 BinopI { op=ne, lhs=v66, rhs_imm=1 } -> x0 + terminator Bz { cond=v67, target=b14, fall=b13 } (exit_acc=v67) block 13 start_pc=0 - v39 Imm(7) -> x0 - terminator Return(v39) (exit_acc=v39) + v68 Imm(10) -> x0 + terminator Return(v68) (exit_acc=v68) block 14 start_pc=0 - v40 Imm(4602678819172646912) -> x6 - v41 Imm(0) -> x7 - v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x6 - v43 Imm(0) -> x7 - v44 BinopI { op=and, lhs=v42, rhs_imm=255 } -> x6 - v45 BinopI { op=ne, lhs=v44, rhs_imm=1 } -> x6 - terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) + v69 LocalAddr(-11) -> x0 + v70 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x1 + v71 Load { addr=v69, disp=4, kind=I32 } -> x0 + v72 BinopI { op=ne, lhs=v71, rhs_imm=7 } -> x0 + terminator Bz { cond=v72, target=b16, fall=b15 } (exit_acc=v72) block 15 start_pc=0 - v46 Imm(8) -> x0 - terminator Return(v46) (exit_acc=v46) + v73 Imm(11) -> x0 + terminator Return(v73) (exit_acc=v73) block 16 start_pc=0 - v47 Imm(0) -> x6 - v48 Binop { op=fne, lhs=v47, rhs=v47 } -> x6 - v49 Imm(0) -> x7 - v50 BinopI { op=and, lhs=v48, rhs_imm=255 } -> x6 - v51 BinopI { op=ne, lhs=v50, rhs_imm=0 } -> x6 - terminator Bz { cond=v51, target=b18, fall=b17 } (exit_acc=v51) + v74 LocalAddr(-11) -> x0 + v75 BinopI { op=add, lhs=v74, rhs_imm=8 } -> x1 + v76 Load { addr=v74, disp=8, kind=U8 } -> x0 + v77 BinopI { op=ne, lhs=v76, rhs_imm=0 } -> x0 + terminator Bz { cond=v77, target=b18, fall=b17 } (exit_acc=v77) block 17 start_pc=0 - v52 Imm(9) -> x0 - terminator Return(v52) (exit_acc=v52) + v78 Imm(12) -> x0 + terminator Return(v78) (exit_acc=v78) block 18 start_pc=0 - v53 LocalAddr(-11) -> x6 - v54 Imm(99) -> x7 - v55 Imm(1) -> x7 - v56 Store { addr=v53, disp=0, value=v55, kind=I8 } -> - - v57 LocalAddr(-11) -> x6 - v58 BinopI { op=add, lhs=v57, rhs_imm=4 } -> x7 - v59 Imm(7) -> x7 - v60 Store { addr=v57, disp=4, value=v59, kind=I32 } -> - - v61 LocalAddr(-11) -> x6 - v62 BinopI { op=add, lhs=v61, rhs_imm=8 } -> x7 - v63 Imm(0) -> x7 - v64 Store { addr=v61, disp=8, value=v63, kind=I8 } -> - - v65 LocalAddr(-11) -> x6 - v66 Load { addr=v65, disp=0, kind=U8 } -> x6 - v67 BinopI { op=ne, lhs=v66, rhs_imm=1 } -> x6 - terminator Bz { cond=v67, target=b20, fall=b19 } (exit_acc=v67) + v79 Imm(42) -> x0 + v80 Imm(42) -> x0 + v81 Imm(0) -> x0 + v82 Imm(1) -> x0 + v83 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v83) block 19 start_pc=0 - v68 Imm(10) -> x0 - terminator Return(v68) (exit_acc=v68) + v85 Imm(0) -> x0 + v86 Imm(0) -> x0 + v87 Imm(0) -> x0 + v88 Imm(0) -> x0 + v89 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v89) block 20 start_pc=0 - v69 LocalAddr(-11) -> x6 - v70 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x7 - v71 Load { addr=v69, disp=4, kind=I32 } -> x6 - v72 BinopI { op=ne, lhs=v71, rhs_imm=7 } -> x6 - terminator Bz { cond=v72, target=b22, fall=b21 } (exit_acc=v72) + v91 Imm(123) -> x0 + v92 Imm(1) -> x0 + v93 Imm(0) -> x0 + v94 Imm(1) -> x0 + v95 Imm(0) -> x0 + terminator Jmp(b21) (exit_acc=v95) block 21 start_pc=0 - v73 Imm(11) -> x0 - terminator Return(v73) (exit_acc=v73) + v97 LocalAddr(-12) -> x0 + v98 Imm(0) -> x1 + v99 Imm(9) -> x2 + v100 Imm(1) -> x6 + v101 Store { addr=v97, disp=0, value=v100, kind=I8 } -> - + v102 LocalAddr(-12) -> x0 + v103 BinopI { op=add, lhs=v102, rhs_imm=1 } -> x2 + v104 Store { addr=v102, disp=1, value=v98, kind=I8 } -> - + v105 LocalAddr(-12) -> x0 + v106 Imm(2) -> x1 + v107 BinopI { op=add, lhs=v105, rhs_imm=2 } -> x1 + v108 Imm(-3) -> x1 + v109 Store { addr=v105, disp=2, value=v100, kind=I8 } -> - + v110 LocalAddr(-12) -> x0 + v111 Load { addr=v110, disp=0, kind=U8 } -> x0 + v112 BinopI { op=ne, lhs=v111, rhs_imm=1 } -> x0 + v113 Imm(0) -> x1 + terminator Bnz { cond=v112, target=b35, fall=b22 } (exit_acc=v112) block 22 start_pc=0 - v74 LocalAddr(-11) -> x6 - v75 BinopI { op=add, lhs=v74, rhs_imm=8 } -> x7 - v76 Load { addr=v74, disp=8, kind=U8 } -> x6 - v77 BinopI { op=ne, lhs=v76, rhs_imm=0 } -> x6 - terminator Bz { cond=v77, target=b24, fall=b23 } (exit_acc=v77) + v114 LocalAddr(-12) -> x0 + v115 Imm(1) -> x1 + v116 BinopI { op=add, lhs=v114, rhs_imm=1 } -> x1 + v117 Load { addr=v114, disp=1, kind=U8 } -> x0 + v118 BinopI { op=ne, lhs=v117, rhs_imm=0 } -> x0 + v119 BinopI { op=ne, lhs=v118, rhs_imm=0 } -> x6 + v120 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v119) block 23 start_pc=0 - v78 Imm(12) -> x0 - terminator Return(v78) (exit_acc=v78) + v121 Phi { incoming=[b35:v100, b22:v119], kind=I64 } -> x6 + v122 LoadLocal { off=-18, kind=I64 } -> x0 + v123 Imm(0) -> x0 + terminator Bnz { cond=v121, target=b34, fall=b24 } (exit_acc=v121) block 24 start_pc=0 - v79 Imm(42) -> x6 - v80 Extend { value=v79, kind=I32 } -> x6 - v81 Imm(0) -> x7 - v82 BinopI { op=ne, lhs=v80, rhs_imm=0 } -> x6 - v83 BinopI { op=ne, lhs=v82, rhs_imm=1 } -> x6 - terminator Bz { cond=v83, target=b26, fall=b25 } (exit_acc=v83) + v124 LocalAddr(-12) -> x0 + v125 Imm(2) -> x1 + v126 BinopI { op=add, lhs=v124, rhs_imm=2 } -> x1 + v127 Load { addr=v124, disp=2, kind=U8 } -> x0 + v128 BinopI { op=ne, lhs=v127, rhs_imm=1 } -> x6 + v129 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v128) block 25 start_pc=0 - v84 Imm(13) -> x0 - terminator Return(v84) (exit_acc=v84) + v130 Phi { incoming=[b34:v121, b24:v128], kind=I64 } -> x6 + v131 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v130, target=b27, fall=b26 } (exit_acc=v130) block 26 start_pc=0 - v85 Imm(0) -> x6 - v86 Extend { value=v85, kind=I32 } -> x6 - v87 Imm(0) -> x7 - v88 BinopI { op=ne, lhs=v86, rhs_imm=0 } -> x6 - v89 BinopI { op=ne, lhs=v88, rhs_imm=0 } -> x6 - terminator Bz { cond=v89, target=b28, fall=b27 } (exit_acc=v89) + v132 Imm(16) -> x0 + terminator Return(v132) (exit_acc=v132) block 27 start_pc=0 - v90 Imm(14) -> x0 - terminator Return(v90) (exit_acc=v90) + v133 LoadLocal { off=-1, kind=U8 } -> x0 + v134 LoadLocal { off=-2, kind=U8 } -> x0 + v135 Imm(1) -> x0 + v136 Imm(4294967296) -> x0 + v137 Imm(1) -> x0 + v138 LoadLocal { off=-3, kind=U8 } -> x0 + v139 Imm(2) -> x0 + v140 Imm(8589934592) -> x0 + v141 Imm(2) -> x0 + v142 Imm(1) -> x0 + v143 Imm(0) -> x0 + v144 Imm(1) -> x0 + v145 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v145) block 28 start_pc=0 - v91 Imm(123) -> x6 - v92 Imm(1) -> x6 - v93 Imm(0) -> x7 - v94 BinopI { op=and, lhs=v92, rhs_imm=255 } -> x6 - v95 BinopI { op=ne, lhs=v94, rhs_imm=1 } -> x6 - terminator Bz { cond=v95, target=b30, fall=b29 } (exit_acc=v95) + v147 Imm(1) -> x0 + v148 Imm(0) -> x0 + v149 Imm(0) -> x0 + v150 Imm(0) -> x1 + v151 LoadLocal { off=-14, kind=U8 } -> x1 + v152 Imm(0) -> x2 + v153 Imm(0) -> x1 + terminator Jmp(b29) (exit_acc=v152) block 29 start_pc=0 - v96 Imm(15) -> x0 - terminator Return(v96) (exit_acc=v96) + v154 LoadLocal { off=-15, kind=U8 } -> x1 + v155 Imm(0) -> x1 + terminator Jmp(b30) (exit_acc=v149) block 30 start_pc=0 - v97 LocalAddr(-12) -> x6 - v98 Imm(0) -> x7 - v99 Imm(9) -> x8 - v100 Imm(1) -> x9 - v101 Store { addr=v97, disp=0, value=v100, kind=I8 } -> - - v102 LocalAddr(-12) -> x6 - v103 BinopI { op=add, lhs=v102, rhs_imm=1 } -> x8 - v104 Store { addr=v102, disp=1, value=v98, kind=I8 } -> - - v105 LocalAddr(-12) -> x6 - v106 Imm(2) -> x7 - v107 BinopI { op=add, lhs=v105, rhs_imm=2 } -> x7 - v108 Imm(-3) -> x7 - v109 Store { addr=v105, disp=2, value=v100, kind=I8 } -> - - v110 LocalAddr(-12) -> x6 - v111 Load { addr=v110, disp=0, kind=U8 } -> x6 - v112 BinopI { op=ne, lhs=v111, rhs_imm=1 } -> x6 - v113 Imm(0) -> x7 - terminator Bnz { cond=v112, target=b45, fall=b31 } (exit_acc=v112) + v156 Phi { incoming=[b28:v152, b29:v149], kind=I64 } -> x2 + v157 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v156, target=b32, fall=b31 } (exit_acc=v156) block 31 start_pc=0 - v114 LocalAddr(-12) -> x6 - v115 Imm(1) -> x7 - v116 BinopI { op=add, lhs=v114, rhs_imm=1 } -> x7 - v117 Load { addr=v114, disp=1, kind=U8 } -> x6 - v118 BinopI { op=ne, lhs=v117, rhs_imm=0 } -> x6 - v119 BinopI { op=ne, lhs=v118, rhs_imm=0 } -> x9 - v120 Imm(0) -> x6 - terminator Jmp(b32) (exit_acc=v119) + v158 Imm(18) -> x0 + terminator Return(v158) (exit_acc=v158) block 32 start_pc=0 - v121 Phi { incoming=[b45:v100, b31:v119], kind=I64 } -> x9 - v122 LoadLocal { off=-18, kind=I64 } -> x6 - v123 Imm(0) -> x6 - terminator Bnz { cond=v121, target=b46, fall=b33 } (exit_acc=v121) + v159 Imm(17) -> x0 + v160 Imm(1) -> x0 + v161 Imm(0) -> x0 + v162 LoadLocal { off=-16, kind=U8 } -> x0 + v163 Imm(0) -> x0 + terminator Jmp(b33) (exit_acc=v163) block 33 start_pc=0 - v124 LocalAddr(-12) -> x6 - v125 Imm(2) -> x7 - v126 BinopI { op=add, lhs=v124, rhs_imm=2 } -> x7 - v127 Load { addr=v124, disp=2, kind=U8 } -> x6 - v128 BinopI { op=ne, lhs=v127, rhs_imm=1 } -> x9 - v129 Imm(0) -> x6 - terminator Jmp(b34) (exit_acc=v128) + v165 Imm(0) -> x0 + terminator Return(v165) (exit_acc=v165) block 34 start_pc=0 - v130 Phi { incoming=[b46:v121, b33:v128], kind=I64 } -> x9 - v131 LoadLocal { off=-17, kind=I64 } -> x6 - terminator Bz { cond=v130, target=b36, fall=b35 } (exit_acc=v130) + terminator Jmp(b25) block 35 start_pc=0 - v132 Imm(16) -> x0 - terminator Return(v132) (exit_acc=v132) + terminator Jmp(b23) block 36 start_pc=0 - v133 LoadLocal { off=-1, kind=U8 } -> x6 - v134 LoadLocal { off=-2, kind=U8 } -> x6 - v135 Binop { op=add, lhs=v4, rhs=v9 } -> x0 - v136 BinopI { op=shl, lhs=v135, rhs_imm=32 } -> x1 - v137 Extend { value=v135, kind=I32 } -> x1 - v138 LoadLocal { off=-3, kind=U8 } -> x1 - v139 Binop { op=add, lhs=v135, rhs=v15 } -> x0 - v140 BinopI { op=shl, lhs=v139, rhs_imm=32 } -> x1 - v141 Extend { value=v139, kind=I32 } -> x0 - v142 BinopI { op=ne, lhs=v141, rhs_imm=0 } -> x0 - v143 Imm(0) -> x1 - v144 BinopI { op=and, lhs=v142, rhs_imm=255 } -> x0 - v145 BinopI { op=ne, lhs=v144, rhs_imm=1 } -> x0 - terminator Bz { cond=v145, target=b38, fall=b37 } (exit_acc=v145) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 37 start_pc=0 - v146 Imm(17) -> x0 - terminator Return(v146) (exit_acc=v146) + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) block 38 start_pc=0 - v147 Imm(1) -> x0 - v148 Imm(0) -> x1 - v149 Imm(0) -> x1 - v150 Imm(0) -> x2 - v151 LoadLocal { off=-14, kind=U8 } -> x2 - v152 BinopI { op=eq, lhs=v147, rhs_imm=0 } -> x2 - v153 Imm(0) -> x0 - terminator Bnz { cond=v152, target=b47, fall=b39 } (exit_acc=v152) + v13 Imm(3) -> x0 + terminator Return(v13) (exit_acc=v13) block 39 start_pc=0 - v154 LoadLocal { off=-15, kind=U8 } -> x0 - v155 Imm(0) -> x0 - terminator Jmp(b40) (exit_acc=v149) + v19 Imm(4) -> x0 + terminator Return(v19) (exit_acc=v19) block 40 start_pc=0 - v156 Phi { incoming=[b47:v152, b39:v149], kind=I64 } -> x2 - v157 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v156, target=b42, fall=b41 } (exit_acc=v156) + v25 Imm(5) -> x0 + terminator Return(v25) (exit_acc=v25) block 41 start_pc=0 - v158 Imm(18) -> x0 - terminator Return(v158) (exit_acc=v158) + v31 Imm(6) -> x0 + terminator Return(v31) (exit_acc=v31) block 42 start_pc=0 - v159 Imm(17) -> x0 - v160 Imm(1) -> x0 - v161 Imm(0) -> x1 - v162 LoadLocal { off=-16, kind=U8 } -> x1 - v163 BinopI { op=ne, lhs=v160, rhs_imm=1 } -> x0 - terminator Bz { cond=v163, target=b44, fall=b43 } (exit_acc=v163) + v84 Imm(13) -> x0 + terminator Return(v84) (exit_acc=v84) block 43 start_pc=0 - v164 Imm(19) -> x0 - terminator Return(v164) (exit_acc=v164) + v90 Imm(14) -> x0 + terminator Return(v90) (exit_acc=v90) block 44 start_pc=0 - v165 Imm(0) -> x0 - terminator Return(v165) (exit_acc=v165) + v96 Imm(15) -> x0 + terminator Return(v96) (exit_acc=v96) block 45 start_pc=0 - terminator Jmp(b32) + v146 Imm(17) -> x0 + terminator Return(v146) (exit_acc=v146) block 46 start_pc=0 - terminator Jmp(b34) - block 47 start_pc=0 - terminator Jmp(b40) + v164 Imm(19) -> x0 + terminator Return(v164) (exit_acc=v164) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/bound_import_arg_narrowing.ssa b/tests/snapshots/ssa/bound_import_arg_narrowing.ssa index 47b51d454..05d564844 100644 --- a/tests/snapshots/ssa/bound_import_arg_narrowing.ssa +++ b/tests/snapshots/ssa/bound_import_arg_narrowing.ssa @@ -33,14 +33,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 terminator Return(v14) (exit_acc=v14) block 2 start_pc=0 v15 Imm(4294967299) -> x0 - v16 Extend { value=v15, kind=I32 } -> x0 - v17 Imm(0) -> x1 - v18 BinopI { op=ne, lhs=v16, rhs_imm=3 } -> x0 - terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) + v16 Imm(3) -> x0 + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v18) block 3 start_pc=0 - v19 Imm(2) -> x0 - terminator Return(v19) (exit_acc=v19) - block 4 start_pc=0 v20 LocalAddr(-3) -> x0 v21 ImmData(24) -> x1 v22 Mcpy { dst=v20, src=v21, size=8 } -> x0 @@ -55,8 +52,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v31 BinopI { op=ne, lhs=v30, rhs_imm=0 } -> x0 v32 Imm(1) -> x2 v33 Imm(0) -> x1 - terminator Bnz { cond=v31, target=b13, fall=b5 } (exit_acc=v31) - block 5 start_pc=0 + terminator Bnz { cond=v31, target=b13, fall=b4 } (exit_acc=v31) + block 4 start_pc=0 v34 LocalAddr(-3) -> x0 v35 Imm(1) -> x1 v36 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x1 @@ -64,44 +61,47 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x2 v40 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v39) - block 6 start_pc=0 - v41 Phi { incoming=[b13:v32, b5:v39], kind=I64 } -> x2 + terminator Jmp(b5) (exit_acc=v39) + block 5 start_pc=0 + v41 Phi { incoming=[b13:v32, b4:v39], kind=I64 } -> x2 v42 LoadLocal { off=-8, kind=I64 } -> x0 v43 Imm(0) -> x0 - terminator Bnz { cond=v41, target=b14, fall=b7 } (exit_acc=v41) - block 7 start_pc=0 + terminator Bnz { cond=v41, target=b12, fall=b6 } (exit_acc=v41) + block 6 start_pc=0 v44 LocalAddr(-3) -> x0 v45 Imm(2) -> x1 v46 BinopI { op=add, lhs=v44, rhs_imm=2 } -> x1 v47 Load { addr=v44, disp=2, kind=I8 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=0 } -> x2 v49 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v48) - block 8 start_pc=0 - v50 Phi { incoming=[b14:v41, b7:v48], kind=I64 } -> x2 + terminator Jmp(b7) (exit_acc=v48) + block 7 start_pc=0 + v50 Phi { incoming=[b12:v41, b6:v48], kind=I64 } -> x2 v51 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v50, target=b10, fall=b9 } (exit_acc=v50) - block 9 start_pc=0 + terminator Bz { cond=v50, target=b9, fall=b8 } (exit_acc=v50) + block 8 start_pc=0 v52 Imm(3) -> x0 terminator Return(v52) (exit_acc=v52) - block 10 start_pc=0 + block 9 start_pc=0 v53 LocalAddr(-3) -> x0 v54 Imm(3) -> x1 v55 BinopI { op=add, lhs=v53, rhs_imm=3 } -> x1 v56 Load { addr=v53, disp=3, kind=I8 } -> x0 v57 BinopI { op=ne, lhs=v56, rhs_imm=9 } -> x0 - terminator Bz { cond=v57, target=b12, fall=b11 } (exit_acc=v57) - block 11 start_pc=0 + terminator Bz { cond=v57, target=b11, fall=b10 } (exit_acc=v57) + block 10 start_pc=0 v58 Imm(4) -> x0 terminator Return(v58) (exit_acc=v58) - block 12 start_pc=0 + block 11 start_pc=0 v59 Imm(0) -> x0 terminator Return(v59) (exit_acc=v59) + block 12 start_pc=0 + terminator Jmp(b7) block 13 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b5) block 14 start_pc=0 - terminator Jmp(b8) + v19 Imm(2) -> x0 + terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/brace_elided_struct_array_init.ssa b/tests/snapshots/ssa/brace_elided_struct_array_init.ssa index 41a71c7ea..30d0f4982 100644 --- a/tests/snapshots/ssa/brace_elided_struct_array_init.ssa +++ b/tests/snapshots/ssa/brace_elided_struct_array_init.ssa @@ -18,7 +18,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v8 Load { addr=v1, disp=8, kind=I32 } -> x1 v9 BinopI { op=ne, lhs=v8, rhs_imm=1 } -> x2 v10 Imm(0) -> x1 - terminator Bnz { cond=v9, target=b23, fall=b3 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b27, fall=b3 } (exit_acc=v9) block 3 start_pc=0 v11 ImmData(8) -> x1 v12 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -30,7 +30,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v18 Imm(0) -> x1 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b23:v9, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b27:v9, b3:v17], kind=I64 } -> x2 v20 LoadLocal { off=-1, kind=I64 } -> x1 terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) block 5 start_pc=0 @@ -44,7 +44,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v26 Load { addr=v1, disp=24, kind=I64 } -> x1 v27 BinopI { op=eq, lhs=v26, rhs_imm=0 } -> x2 v28 Imm(0) -> x1 - terminator Bnz { cond=v27, target=b24, fall=b7 } (exit_acc=v27) + terminator Bnz { cond=v27, target=b26, fall=b7 } (exit_acc=v27) block 7 start_pc=0 v29 ImmData(8) -> x1 v30 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -57,7 +57,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v37 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v36) block 8 start_pc=0 - v38 Phi { incoming=[b24:v27, b7:v36], kind=I64 } -> x2 + v38 Phi { incoming=[b26:v27, b7:v36], kind=I64 } -> x2 v39 LoadLocal { off=-2, kind=I64 } -> x1 terminator Bz { cond=v38, target=b10, fall=b9 } (exit_acc=v38) block 9 start_pc=0 @@ -100,7 +100,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v66 Load { addr=v1, disp=72, kind=I32 } -> x1 v67 BinopI { op=ne, lhs=v66, rhs_imm=3 } -> x2 v68 Imm(0) -> x1 - terminator Bnz { cond=v67, target=b26, fall=b15 } (exit_acc=v67) + terminator Bnz { cond=v67, target=b24, fall=b15 } (exit_acc=v67) block 15 start_pc=0 v69 ImmData(8) -> x1 v70 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -113,7 +113,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v77 Imm(0) -> x1 terminator Jmp(b16) (exit_acc=v76) block 16 start_pc=0 - v78 Phi { incoming=[b26:v67, b15:v76], kind=I64 } -> x2 + v78 Phi { incoming=[b24:v67, b15:v76], kind=I64 } -> x2 v79 LoadLocal { off=-4, kind=I64 } -> x1 terminator Bz { cond=v78, target=b18, fall=b17 } (exit_acc=v78) block 17 start_pc=0 @@ -127,7 +127,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v85 Load { addr=v1, disp=104, kind=I32 } -> x1 v86 BinopI { op=ne, lhs=v85, rhs_imm=0 } -> x2 v87 Imm(0) -> x1 - terminator Bnz { cond=v86, target=b27, fall=b19 } (exit_acc=v86) + terminator Bnz { cond=v86, target=b23, fall=b19 } (exit_acc=v86) block 19 start_pc=0 v88 ImmData(8) -> x1 v89 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -139,7 +139,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v95 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v94) block 20 start_pc=0 - v96 Phi { incoming=[b27:v86, b19:v94], kind=I64 } -> x2 + v96 Phi { incoming=[b23:v86, b19:v94], kind=I64 } -> x2 v97 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v96, target=b22, fall=b21 } (exit_acc=v96) block 21 start_pc=0 @@ -149,15 +149,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v99 Imm(0) -> x0 terminator Return(v99) (exit_acc=v99) block 23 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b20) block 24 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b16) block 25 start_pc=0 terminator Jmp(b12) block 26 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b8) block 27 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/brace_elided_toplevel_struct_array.ssa b/tests/snapshots/ssa/brace_elided_toplevel_struct_array.ssa index 26437029d..fc7a9c124 100644 --- a/tests/snapshots/ssa/brace_elided_toplevel_struct_array.ssa +++ b/tests/snapshots/ssa/brace_elided_toplevel_struct_array.ssa @@ -34,116 +34,107 @@ fn ent_pc=0 n_params=0 variadic=false locals=12 terminator Return(v21) (exit_acc=v21) block 4 start_pc=0 v22 Imm(16) -> x0 - v23 Imm(8) -> x1 - v24 Imm(0) -> x1 - v25 Binop { op=add, lhs=v22, rhs=v24 } -> x0 - v26 BinopI { op=shr, lhs=v25, rhs_imm=3 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=2 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v23 Imm(8) -> x0 + v24 Imm(0) -> x0 + v25 Imm(16) -> x0 + v26 Imm(2) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v27) block 5 start_pc=0 - v28 Imm(2) -> x0 - terminator Return(v28) (exit_acc=v28) - block 6 start_pc=0 v29 ImmData(32) -> x0 v30 Imm(8) -> x1 v31 BinopI { op=add, lhs=v29, rhs_imm=8 } -> x1 v32 Load { addr=v29, disp=8, kind=I32 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=30 } -> x0 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) - block 7 start_pc=0 + terminator Bz { cond=v33, target=b7, fall=b6 } (exit_acc=v33) + block 6 start_pc=0 v34 Imm(3) -> x0 terminator Return(v34) (exit_acc=v34) - block 8 start_pc=0 + block 7 start_pc=0 v35 LocalAddr(-2) -> x0 v36 Imm(0) -> x1 v37 BinopI { op=add, lhs=v35, rhs_imm=4 } -> x1 v38 Load { addr=v35, disp=4, kind=I32 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=200 } -> x1 v40 Imm(0) -> x0 - terminator Bnz { cond=v39, target=b30, fall=b9 } (exit_acc=v39) - block 9 start_pc=0 + terminator Bnz { cond=v39, target=b28, fall=b8 } (exit_acc=v39) + block 8 start_pc=0 v41 LocalAddr(-2) -> x0 v42 Imm(8) -> x1 v43 BinopI { op=add, lhs=v41, rhs_imm=8 } -> x1 v44 Load { addr=v41, disp=8, kind=I32 } -> x0 v45 BinopI { op=ne, lhs=v44, rhs_imm=300 } -> x1 v46 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v45) - block 10 start_pc=0 - v47 Phi { incoming=[b30:v39, b9:v45], kind=I64 } -> x1 + terminator Jmp(b9) (exit_acc=v45) + block 9 start_pc=0 + v47 Phi { incoming=[b28:v39, b8:v45], kind=I64 } -> x1 v48 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v47, target=b12, fall=b11 } (exit_acc=v47) - block 11 start_pc=0 + terminator Bz { cond=v47, target=b11, fall=b10 } (exit_acc=v47) + block 10 start_pc=0 v49 Imm(4) -> x0 terminator Return(v49) (exit_acc=v49) - block 12 start_pc=0 + block 11 start_pc=0 v50 Imm(24) -> x0 - v51 Imm(8) -> x1 - v52 Imm(0) -> x1 - v53 Binop { op=add, lhs=v50, rhs=v52 } -> x0 - v54 BinopI { op=shr, lhs=v53, rhs_imm=3 } -> x0 - v55 BinopI { op=ne, lhs=v54, rhs_imm=3 } -> x0 - terminator Bz { cond=v55, target=b14, fall=b13 } (exit_acc=v55) - block 13 start_pc=0 - v56 Imm(5) -> x0 - terminator Return(v56) (exit_acc=v56) - block 14 start_pc=0 + v51 Imm(8) -> x0 + v52 Imm(0) -> x0 + v53 Imm(24) -> x0 + v54 Imm(3) -> x0 + v55 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v55) + block 12 start_pc=0 v57 LocalAddr(-5) -> x0 v58 Imm(16) -> x1 v59 BinopI { op=add, lhs=v57, rhs_imm=16 } -> x1 v60 BinopI { op=add, lhs=v57, rhs_imm=20 } -> x1 v61 Load { addr=v57, disp=20, kind=I32 } -> x0 v62 BinopI { op=ne, lhs=v61, rhs_imm=16 } -> x0 - terminator Bz { cond=v62, target=b16, fall=b15 } (exit_acc=v62) - block 15 start_pc=0 + terminator Bz { cond=v62, target=b14, fall=b13 } (exit_acc=v62) + block 13 start_pc=0 v63 Imm(6) -> x0 terminator Return(v63) (exit_acc=v63) - block 16 start_pc=0 + block 14 start_pc=0 v64 ImmData(88) -> x0 v65 Imm(8) -> x1 v66 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x1 v67 Load { addr=v64, disp=8, kind=I32 } -> x0 v68 BinopI { op=ne, lhs=v67, rhs_imm=9 } -> x1 v69 Imm(0) -> x0 - terminator Bnz { cond=v68, target=b31, fall=b17 } (exit_acc=v68) - block 17 start_pc=0 + terminator Bnz { cond=v68, target=b27, fall=b15 } (exit_acc=v68) + block 15 start_pc=0 v70 ImmData(88) -> x0 v71 Imm(16) -> x1 v72 BinopI { op=add, lhs=v70, rhs_imm=16 } -> x1 v73 Load { addr=v70, disp=16, kind=I32 } -> x0 v74 BinopI { op=ne, lhs=v73, rhs_imm=0 } -> x1 v75 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v74) - block 18 start_pc=0 - v76 Phi { incoming=[b31:v68, b17:v74], kind=I64 } -> x1 + terminator Jmp(b16) (exit_acc=v74) + block 16 start_pc=0 + v76 Phi { incoming=[b27:v68, b15:v74], kind=I64 } -> x1 v77 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v76, target=b20, fall=b19 } (exit_acc=v76) - block 19 start_pc=0 + terminator Bz { cond=v76, target=b18, fall=b17 } (exit_acc=v76) + block 17 start_pc=0 v78 Imm(7) -> x0 terminator Return(v78) (exit_acc=v78) - block 20 start_pc=0 + block 18 start_pc=0 v79 Imm(16) -> x0 - v80 Imm(8) -> x1 - v81 Imm(0) -> x1 - v82 Binop { op=add, lhs=v79, rhs=v81 } -> x0 - v83 BinopI { op=shr, lhs=v82, rhs_imm=3 } -> x0 - v84 BinopI { op=ne, lhs=v83, rhs_imm=2 } -> x0 - terminator Bz { cond=v84, target=b22, fall=b21 } (exit_acc=v84) - block 21 start_pc=0 - v85 Imm(8) -> x0 - terminator Return(v85) (exit_acc=v85) - block 22 start_pc=0 + v80 Imm(8) -> x0 + v81 Imm(0) -> x0 + v82 Imm(16) -> x0 + v83 Imm(2) -> x0 + v84 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v84) + block 19 start_pc=0 v86 ImmData(112) -> x0 v87 Imm(8) -> x1 v88 BinopI { op=add, lhs=v86, rhs_imm=8 } -> x1 v89 BinopI { op=add, lhs=v86, rhs_imm=12 } -> x1 v90 Load { addr=v86, disp=12, kind=I32 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=24 } -> x0 - terminator Bz { cond=v91, target=b24, fall=b23 } (exit_acc=v91) - block 23 start_pc=0 + terminator Bz { cond=v91, target=b21, fall=b20 } (exit_acc=v91) + block 20 start_pc=0 v92 Imm(9) -> x0 terminator Return(v92) (exit_acc=v92) - block 24 start_pc=0 + block 21 start_pc=0 v93 LocalAddr(-8) -> x0 v94 ImmData(128) -> x1 v95 Mcpy { dst=v93, src=v94, size=24 } -> x0 @@ -153,8 +144,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=12 v99 Load { addr=v96, disp=8, kind=I32 } -> x0 v100 BinopI { op=ne, lhs=v99, rhs_imm=3 } -> x1 v101 Imm(0) -> x0 - terminator Bnz { cond=v100, target=b32, fall=b25 } (exit_acc=v100) - block 25 start_pc=0 + terminator Bnz { cond=v100, target=b26, fall=b22 } (exit_acc=v100) + block 22 start_pc=0 v102 LocalAddr(-8) -> x0 v103 Imm(16) -> x1 v104 BinopI { op=add, lhs=v102, rhs_imm=16 } -> x1 @@ -162,25 +153,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=12 v106 Load { addr=v102, disp=20, kind=I32 } -> x0 v107 BinopI { op=ne, lhs=v106, rhs_imm=6 } -> x1 v108 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v107) - block 26 start_pc=0 - v109 Phi { incoming=[b32:v100, b25:v107], kind=I64 } -> x1 + terminator Jmp(b23) (exit_acc=v107) + block 23 start_pc=0 + v109 Phi { incoming=[b26:v100, b22:v107], kind=I64 } -> x1 v110 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Bz { cond=v109, target=b28, fall=b27 } (exit_acc=v109) - block 27 start_pc=0 + terminator Bz { cond=v109, target=b25, fall=b24 } (exit_acc=v109) + block 24 start_pc=0 v111 Imm(10) -> x0 terminator Return(v111) (exit_acc=v111) - block 28 start_pc=0 + block 25 start_pc=0 v112 Imm(0) -> x0 terminator Return(v112) (exit_acc=v112) + block 26 start_pc=0 + terminator Jmp(b23) + block 27 start_pc=0 + terminator Jmp(b16) + block 28 start_pc=0 + terminator Jmp(b9) block 29 start_pc=0 terminator Jmp(b2) block 30 start_pc=0 - terminator Jmp(b10) + v28 Imm(2) -> x0 + terminator Return(v28) (exit_acc=v28) block 31 start_pc=0 - terminator Jmp(b18) + v56 Imm(5) -> x0 + terminator Return(v56) (exit_acc=v56) block 32 start_pc=0 - terminator Jmp(b26) + v85 Imm(8) -> x0 + terminator Return(v85) (exit_acc=v85) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/branch_relaxation.ssa b/tests/snapshots/ssa/branch_relaxation.ssa index 6e4a04a26..9867db5a8 100644 --- a/tests/snapshots/ssa/branch_relaxation.ssa +++ b/tests/snapshots/ssa/branch_relaxation.ssa @@ -9,59 +9,59 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b9) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v24], kind=I64 } -> x0 - v8 Extend { value=v6, kind=I32 } -> x2 - v9 LoadLocal { off=2, kind=I32 } -> x6 - v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v14 Extend { value=v6, kind=I32 } -> x6 + v15 Imm(3) -> x6 + v16 Binop { op=mod, lhs=v8, rhs=v15 } -> x6 + v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x6 + terminator Bz { cond=v17, target=b4, fall=b2 } (exit_acc=v17) block 2 start_pc=0 - v11 Extend { value=v6, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 - v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) + v19 Extend { value=v7, kind=I32 } -> x6 + v20 Extend { value=v6, kind=I32 } -> x6 + v21 Binop { op=add, lhs=v7, rhs=v6 } -> x0 + v22 Imm(0) -> x6 + v23 Extend { value=v21, kind=I32 } -> x6 + terminator Jmp(b3) (exit_acc=v23) block 3 start_pc=0 - v14 Extend { value=v6, kind=I32 } -> x2 - v15 Imm(3) -> x6 - v16 Binop { op=mod, lhs=v14, rhs=v15 } -> x2 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 - terminator Bz { cond=v17, target=b7, fall=b5 } (exit_acc=v17) + v24 Phi { incoming=[b2:v21, b6:v33], kind=I64 } -> x0 + terminator Jmp(b8) block 4 start_pc=0 - v18 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v18) (exit_acc=v18) + v25 Extend { value=v6, kind=I32 } -> x6 + v26 Imm(3) -> x6 + v27 Binop { op=mod, lhs=v8, rhs=v26 } -> x6 + v28 BinopI { op=eq, lhs=v27, rhs_imm=1 } -> x6 + terminator Bz { cond=v28, target=b7, fall=b5 } (exit_acc=v28) block 5 start_pc=0 - v19 Extend { value=v7, kind=I32 } -> x2 - v20 Extend { value=v6, kind=I32 } -> x2 - v21 Binop { op=add, lhs=v7, rhs=v6 } -> x0 - v22 Imm(0) -> x2 - v23 Extend { value=v21, kind=I32 } -> x2 - terminator Jmp(b6) (exit_acc=v23) + v29 Extend { value=v7, kind=I32 } -> x6 + v30 BinopI { op=sub, lhs=v7, rhs_imm=1 } -> x0 + v31 Imm(0) -> x6 + v32 Extend { value=v30, kind=I32 } -> x6 + terminator Jmp(b6) (exit_acc=v32) block 6 start_pc=0 - v24 Phi { incoming=[b5:v21, b9:v33], kind=I64 } -> x0 - terminator Jmp(b2) + v33 Phi { incoming=[b5:v30, b7:v35], kind=I64 } -> x0 + terminator Jmp(b3) block 7 start_pc=0 - v25 Extend { value=v6, kind=I32 } -> x2 - v26 Imm(3) -> x6 - v27 Binop { op=mod, lhs=v25, rhs=v26 } -> x2 - v28 BinopI { op=eq, lhs=v27, rhs_imm=1 } -> x2 - terminator Bz { cond=v28, target=b10, fall=b8 } (exit_acc=v28) + v34 Extend { value=v7, kind=I32 } -> x6 + v35 BinopI { op=add, lhs=v7, rhs_imm=2 } -> x0 + v36 Imm(0) -> x6 + v37 Extend { value=v35, kind=I32 } -> x6 + terminator Jmp(b6) (exit_acc=v37) block 8 start_pc=0 - v29 Extend { value=v7, kind=I32 } -> x2 - v30 BinopI { op=sub, lhs=v7, rhs_imm=1 } -> x0 - v31 Imm(0) -> x2 - v32 Extend { value=v30, kind=I32 } -> x2 - terminator Jmp(b9) (exit_acc=v32) + v11 Extend { value=v6, kind=I32 } -> x1 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v13 Imm(0) -> x2 + terminator Jmp(b9) (exit_acc=v12) block 9 start_pc=0 - v33 Phi { incoming=[b8:v30, b10:v35], kind=I64 } -> x0 - terminator Jmp(b6) + v6 Phi { incoming=[b0:v3, b8:v12], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b8:v24], kind=I64 } -> x0 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 LoadLocal { off=2, kind=I32 } -> x6 + v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b10 } (exit_acc=v10) block 10 start_pc=0 - v34 Extend { value=v7, kind=I32 } -> x2 - v35 BinopI { op=add, lhs=v7, rhs_imm=2 } -> x0 - v36 Imm(0) -> x2 - v37 Extend { value=v35, kind=I32 } -> x2 - terminator Jmp(b9) (exit_acc=v37) + v18 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v18) (exit_acc=v18) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/break_continue.ssa b/tests/snapshots/ssa/break_continue.ssa index c11c6d93c..04d990536 100644 --- a/tests/snapshots/ssa/break_continue.ssa +++ b/tests/snapshots/ssa/break_continue.ssa @@ -7,48 +7,48 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b6) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x0 - v6 Extend { value=v5, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v12 Extend { value=v5, kind=I32 } -> x6 + v13 BinopI { op=eq, lhs=v6, rhs_imm=5 } -> x6 + terminator Bnz { cond=v13, target=b7, fall=b2 } (exit_acc=v13) block 2 start_pc=0 - v8 Phi { incoming=[b7:v4, b8:v27], kind=I64 } -> x1 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 - v11 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v10) + v15 Extend { value=v5, kind=I32 } -> x6 + v16 Imm(2) -> x6 + v17 BinopI { op=shr, lhs=v6, rhs_imm=63 } -> x6 + v18 BinopI { op=shru, lhs=v17, rhs_imm=63 } -> x6 + v19 Binop { op=add, lhs=v6, rhs=v18 } -> x7 + v20 BinopI { op=and, lhs=v19, rhs_imm=1 } -> x7 + v21 Binop { op=sub, lhs=v20, rhs=v18 } -> x6 + v22 BinopI { op=eq, lhs=v21, rhs_imm=0 } -> x6 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 - v12 Extend { value=v5, kind=I32 } -> x2 - v13 BinopI { op=eq, lhs=v12, rhs_imm=5 } -> x2 - terminator Bz { cond=v13, target=b6, fall=b5 } (exit_acc=v13) + terminator Jmp(b5) block 4 start_pc=0 - v14 Extend { value=v4, kind=I32 } -> x0 - terminator Return(v14) (exit_acc=v14) + v23 Extend { value=v4, kind=I32 } -> x6 + v24 Extend { value=v5, kind=I32 } -> x6 + v25 Binop { op=add, lhs=v4, rhs=v5 } -> x1 + v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x6 + v27 Extend { value=v25, kind=I32 } -> x1 + v28 Imm(0) -> x6 + terminator Jmp(b5) (exit_acc=v27) block 5 start_pc=0 - terminator Jmp(b4) + v8 Phi { incoming=[b3:v4, b4:v27], kind=I64 } -> x1 + v9 Extend { value=v5, kind=I32 } -> x0 + v10 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x0 + v11 Imm(0) -> x2 + terminator Jmp(b6) (exit_acc=v10) block 6 start_pc=0 - v15 Extend { value=v5, kind=I32 } -> x2 - v16 Imm(2) -> x6 - v17 BinopI { op=shr, lhs=v15, rhs_imm=63 } -> x6 - v18 BinopI { op=shru, lhs=v17, rhs_imm=63 } -> x6 - v19 Binop { op=add, lhs=v15, rhs=v18 } -> x2 - v20 BinopI { op=and, lhs=v19, rhs_imm=1 } -> x2 - v21 Binop { op=sub, lhs=v20, rhs=v18 } -> x2 - v22 BinopI { op=eq, lhs=v21, rhs_imm=0 } -> x2 - terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) + v4 Phi { incoming=[b0:v1, b5:v8], kind=I64 } -> x1 + v5 Phi { incoming=[b0:v1, b5:v10], kind=I64 } -> x0 + v6 Extend { value=v5, kind=I32 } -> x2 + v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x6 + terminator Bnz { cond=v7, target=b1, fall=b7 } (exit_acc=v7) block 7 start_pc=0 - terminator Jmp(b2) + v14 Extend { value=v4, kind=I32 } -> x0 + terminator Return(v14) (exit_acc=v14) block 8 start_pc=0 - v23 Extend { value=v4, kind=I32 } -> x2 - v24 Extend { value=v5, kind=I32 } -> x2 - v25 Binop { op=add, lhs=v4, rhs=v5 } -> x1 - v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x2 - v27 Extend { value=v25, kind=I32 } -> x1 - v28 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v27) + terminator Jmp(b7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/builtin_bit_count.ssa b/tests/snapshots/ssa/builtin_bit_count.ssa index 562ed4174..2dc64c65c 100644 --- a/tests/snapshots/ssa/builtin_bit_count.ssa +++ b/tests/snapshots/ssa/builtin_bit_count.ssa @@ -19,693 +19,633 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 Binop { op=or, lhs=v1, rhs=v2 } -> x0 - v4 BinopI { op=shru, lhs=v3, rhs_imm=2 } -> x1 - v5 Binop { op=or, lhs=v3, rhs=v4 } -> x0 - v6 BinopI { op=shru, lhs=v5, rhs_imm=4 } -> x1 - v7 Binop { op=or, lhs=v5, rhs=v6 } -> x0 - v8 BinopI { op=shru, lhs=v7, rhs_imm=8 } -> x1 - v9 Binop { op=or, lhs=v7, rhs=v8 } -> x0 - v10 BinopI { op=shru, lhs=v9, rhs_imm=16 } -> x1 - v11 Binop { op=or, lhs=v9, rhs=v10 } -> x0 - v12 BinopI { op=and, lhs=v11, rhs_imm=4294967295 } -> x0 - v13 BinopI { op=shru, lhs=v12, rhs_imm=1 } -> x1 - v14 BinopI { op=and, lhs=v13, rhs_imm=1431655765 } -> x1 - v15 Binop { op=sub, lhs=v12, rhs=v14 } -> x0 - v16 BinopI { op=and, lhs=v15, rhs_imm=858993459 } -> x1 - v17 BinopI { op=shru, lhs=v15, rhs_imm=2 } -> x0 - v18 BinopI { op=and, lhs=v17, rhs_imm=858993459 } -> x0 - v19 Binop { op=add, lhs=v16, rhs=v18 } -> x0 - v20 BinopI { op=shru, lhs=v19, rhs_imm=4 } -> x1 - v21 Binop { op=add, lhs=v19, rhs=v20 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=252645135 } -> x0 - v23 BinopI { op=shru, lhs=v22, rhs_imm=8 } -> x1 - v24 Binop { op=add, lhs=v22, rhs=v23 } -> x0 - v25 BinopI { op=shru, lhs=v24, rhs_imm=16 } -> x1 - v26 Binop { op=add, lhs=v24, rhs=v25 } -> x0 - v27 BinopI { op=and, lhs=v26, rhs_imm=127 } -> x0 - v28 Imm(32) -> x1 - v29 Binop { op=sub, lhs=v28, rhs=v27 } -> x0 - v30 Imm(31) -> x1 - v31 Extend { value=v29, kind=I32 } -> x0 - v32 Imm(0) -> x2 - v33 Extend { value=v30, kind=I32 } -> x1 - v34 Imm(0) -> x2 - v35 Binop { op=eq, lhs=v31, rhs=v33 } -> x0 - v36 BinopI { op=eq, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b2, fall=b1 } (exit_acc=v36) + v2 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + v10 Imm(0) -> x0 + v11 Imm(1) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(1) -> x0 + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + v19 Imm(1) -> x0 + v20 Imm(0) -> x0 + v21 Imm(1) -> x0 + v22 Imm(1) -> x0 + v23 Imm(0) -> x0 + v24 Imm(1) -> x0 + v25 Imm(0) -> x0 + v26 Imm(1) -> x0 + v27 Imm(1) -> x0 + v28 Imm(32) -> x0 + v29 Imm(31) -> x0 + v30 Imm(31) -> x0 + v31 Imm(31) -> x0 + v32 Imm(0) -> x0 + v33 Imm(31) -> x0 + v34 Imm(0) -> x0 + v35 Imm(1) -> x0 + v36 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v36) block 1 start_pc=0 - v37 Imm(1) -> x0 - terminator Return(v37) (exit_acc=v37) - block 2 start_pc=0 v38 Imm(2147483648) -> x0 - v39 Imm(1073741824) -> x1 - v40 Binop { op=or, lhs=v38, rhs=v39 } -> x0 - v41 BinopI { op=shru, lhs=v40, rhs_imm=2 } -> x1 - v42 Binop { op=or, lhs=v40, rhs=v41 } -> x0 - v43 BinopI { op=shru, lhs=v42, rhs_imm=4 } -> x1 - v44 Binop { op=or, lhs=v42, rhs=v43 } -> x0 - v45 BinopI { op=shru, lhs=v44, rhs_imm=8 } -> x1 - v46 Binop { op=or, lhs=v44, rhs=v45 } -> x0 - v47 BinopI { op=shru, lhs=v46, rhs_imm=16 } -> x1 - v48 Binop { op=or, lhs=v46, rhs=v47 } -> x0 - v49 BinopI { op=and, lhs=v48, rhs_imm=4294967295 } -> x0 - v50 BinopI { op=shru, lhs=v49, rhs_imm=1 } -> x1 - v51 BinopI { op=and, lhs=v50, rhs_imm=1431655765 } -> x1 - v52 Binop { op=sub, lhs=v49, rhs=v51 } -> x0 - v53 BinopI { op=and, lhs=v52, rhs_imm=858993459 } -> x1 - v54 BinopI { op=shru, lhs=v52, rhs_imm=2 } -> x0 - v55 BinopI { op=and, lhs=v54, rhs_imm=858993459 } -> x0 - v56 Binop { op=add, lhs=v53, rhs=v55 } -> x0 - v57 BinopI { op=shru, lhs=v56, rhs_imm=4 } -> x1 - v58 Binop { op=add, lhs=v56, rhs=v57 } -> x0 - v59 BinopI { op=and, lhs=v58, rhs_imm=252645135 } -> x0 - v60 BinopI { op=shru, lhs=v59, rhs_imm=8 } -> x1 - v61 Binop { op=add, lhs=v59, rhs=v60 } -> x0 - v62 BinopI { op=shru, lhs=v61, rhs_imm=16 } -> x1 - v63 Binop { op=add, lhs=v61, rhs=v62 } -> x0 - v64 BinopI { op=and, lhs=v63, rhs_imm=127 } -> x0 - v65 Imm(32) -> x1 - v66 Binop { op=sub, lhs=v65, rhs=v64 } -> x0 - v67 Imm(0) -> x1 - v68 Extend { value=v66, kind=I32 } -> x0 - v69 Imm(0) -> x2 - v70 Extend { value=v67, kind=I32 } -> x1 - v71 Imm(0) -> x2 - v72 Binop { op=eq, lhs=v68, rhs=v70 } -> x0 - v73 BinopI { op=eq, lhs=v72, rhs_imm=0 } -> x0 - terminator Bz { cond=v73, target=b4, fall=b3 } (exit_acc=v73) - block 3 start_pc=0 - v74 Imm(2) -> x0 - terminator Return(v74) (exit_acc=v74) - block 4 start_pc=0 + v39 Imm(1073741824) -> x0 + v40 Imm(3221225472) -> x0 + v41 Imm(805306368) -> x0 + v42 Imm(4026531840) -> x0 + v43 Imm(251658240) -> x0 + v44 Imm(4278190080) -> x0 + v45 Imm(16711680) -> x0 + v46 Imm(4294901760) -> x0 + v47 Imm(65535) -> x0 + v48 Imm(4294967295) -> x0 + v49 Imm(4294967295) -> x0 + v50 Imm(2147483647) -> x0 + v51 Imm(1431655765) -> x0 + v52 Imm(2863311530) -> x0 + v53 Imm(572662306) -> x0 + v54 Imm(715827882) -> x0 + v55 Imm(572662306) -> x0 + v56 Imm(1145324612) -> x0 + v57 Imm(71582788) -> x0 + v58 Imm(1216907400) -> x0 + v59 Imm(134744072) -> x0 + v60 Imm(526344) -> x0 + v61 Imm(135270416) -> x0 + v62 Imm(2064) -> x0 + v63 Imm(135272480) -> x0 + v64 Imm(32) -> x0 + v65 Imm(32) -> x0 + v66 Imm(0) -> x0 + v67 Imm(0) -> x0 + v68 Imm(0) -> x0 + v69 Imm(0) -> x0 + v70 Imm(0) -> x0 + v71 Imm(0) -> x0 + v72 Imm(1) -> x0 + v73 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v73) + block 2 start_pc=0 v75 Imm(65536) -> x0 - v76 Imm(32768) -> x1 - v77 Binop { op=or, lhs=v75, rhs=v76 } -> x0 - v78 BinopI { op=shru, lhs=v77, rhs_imm=2 } -> x1 - v79 Binop { op=or, lhs=v77, rhs=v78 } -> x0 - v80 BinopI { op=shru, lhs=v79, rhs_imm=4 } -> x1 - v81 Binop { op=or, lhs=v79, rhs=v80 } -> x0 - v82 BinopI { op=shru, lhs=v81, rhs_imm=8 } -> x1 - v83 Binop { op=or, lhs=v81, rhs=v82 } -> x0 - v84 BinopI { op=shru, lhs=v83, rhs_imm=16 } -> x1 - v85 Binop { op=or, lhs=v83, rhs=v84 } -> x0 - v86 BinopI { op=and, lhs=v85, rhs_imm=4294967295 } -> x0 - v87 BinopI { op=shru, lhs=v86, rhs_imm=1 } -> x1 - v88 BinopI { op=and, lhs=v87, rhs_imm=1431655765 } -> x1 - v89 Binop { op=sub, lhs=v86, rhs=v88 } -> x0 - v90 BinopI { op=and, lhs=v89, rhs_imm=858993459 } -> x1 - v91 BinopI { op=shru, lhs=v89, rhs_imm=2 } -> x0 - v92 BinopI { op=and, lhs=v91, rhs_imm=858993459 } -> x0 - v93 Binop { op=add, lhs=v90, rhs=v92 } -> x0 - v94 BinopI { op=shru, lhs=v93, rhs_imm=4 } -> x1 - v95 Binop { op=add, lhs=v93, rhs=v94 } -> x0 - v96 BinopI { op=and, lhs=v95, rhs_imm=252645135 } -> x0 - v97 BinopI { op=shru, lhs=v96, rhs_imm=8 } -> x1 - v98 Binop { op=add, lhs=v96, rhs=v97 } -> x0 - v99 BinopI { op=shru, lhs=v98, rhs_imm=16 } -> x1 - v100 Binop { op=add, lhs=v98, rhs=v99 } -> x0 - v101 BinopI { op=and, lhs=v100, rhs_imm=127 } -> x0 - v102 Imm(32) -> x1 - v103 Binop { op=sub, lhs=v102, rhs=v101 } -> x0 - v104 Imm(15) -> x1 - v105 Extend { value=v103, kind=I32 } -> x0 - v106 Imm(0) -> x2 - v107 Extend { value=v104, kind=I32 } -> x1 - v108 Imm(0) -> x2 - v109 Binop { op=eq, lhs=v105, rhs=v107 } -> x0 - v110 BinopI { op=eq, lhs=v109, rhs_imm=0 } -> x0 - terminator Bz { cond=v110, target=b6, fall=b5 } (exit_acc=v110) - block 5 start_pc=0 - v111 Imm(3) -> x0 - terminator Return(v111) (exit_acc=v111) - block 6 start_pc=0 + v76 Imm(32768) -> x0 + v77 Imm(98304) -> x0 + v78 Imm(24576) -> x0 + v79 Imm(122880) -> x0 + v80 Imm(7680) -> x0 + v81 Imm(130560) -> x0 + v82 Imm(510) -> x0 + v83 Imm(131070) -> x0 + v84 Imm(1) -> x0 + v85 Imm(131071) -> x0 + v86 Imm(131071) -> x0 + v87 Imm(65535) -> x0 + v88 Imm(21845) -> x0 + v89 Imm(109226) -> x0 + v90 Imm(74274) -> x0 + v91 Imm(27306) -> x0 + v92 Imm(8738) -> x0 + v93 Imm(83012) -> x0 + v94 Imm(5188) -> x0 + v95 Imm(88200) -> x0 + v96 Imm(67592) -> x0 + v97 Imm(264) -> x0 + v98 Imm(67856) -> x0 + v99 Imm(1) -> x0 + v100 Imm(67857) -> x0 + v101 Imm(17) -> x0 + v102 Imm(32) -> x0 + v103 Imm(15) -> x0 + v104 Imm(15) -> x0 + v105 Imm(15) -> x0 + v106 Imm(0) -> x0 + v107 Imm(15) -> x0 + v108 Imm(0) -> x0 + v109 Imm(1) -> x0 + v110 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v110) + block 3 start_pc=0 v112 Imm(4294967295) -> x0 - v113 Imm(2147483647) -> x1 - v114 Binop { op=or, lhs=v112, rhs=v113 } -> x0 - v115 BinopI { op=shru, lhs=v114, rhs_imm=2 } -> x1 - v116 Binop { op=or, lhs=v114, rhs=v115 } -> x0 - v117 BinopI { op=shru, lhs=v116, rhs_imm=4 } -> x1 - v118 Binop { op=or, lhs=v116, rhs=v117 } -> x0 - v119 BinopI { op=shru, lhs=v118, rhs_imm=8 } -> x1 - v120 Binop { op=or, lhs=v118, rhs=v119 } -> x0 - v121 BinopI { op=shru, lhs=v120, rhs_imm=16 } -> x1 - v122 Binop { op=or, lhs=v120, rhs=v121 } -> x0 - v123 BinopI { op=and, lhs=v122, rhs_imm=4294967295 } -> x0 - v124 BinopI { op=shru, lhs=v123, rhs_imm=1 } -> x1 - v125 BinopI { op=and, lhs=v124, rhs_imm=1431655765 } -> x1 - v126 Binop { op=sub, lhs=v123, rhs=v125 } -> x0 - v127 BinopI { op=and, lhs=v126, rhs_imm=858993459 } -> x1 - v128 BinopI { op=shru, lhs=v126, rhs_imm=2 } -> x0 - v129 BinopI { op=and, lhs=v128, rhs_imm=858993459 } -> x0 - v130 Binop { op=add, lhs=v127, rhs=v129 } -> x0 - v131 BinopI { op=shru, lhs=v130, rhs_imm=4 } -> x1 - v132 Binop { op=add, lhs=v130, rhs=v131 } -> x0 - v133 BinopI { op=and, lhs=v132, rhs_imm=252645135 } -> x0 - v134 BinopI { op=shru, lhs=v133, rhs_imm=8 } -> x1 - v135 Binop { op=add, lhs=v133, rhs=v134 } -> x0 - v136 BinopI { op=shru, lhs=v135, rhs_imm=16 } -> x1 - v137 Binop { op=add, lhs=v135, rhs=v136 } -> x0 - v138 BinopI { op=and, lhs=v137, rhs_imm=127 } -> x0 - v139 Imm(32) -> x1 - v140 Binop { op=sub, lhs=v139, rhs=v138 } -> x0 - v141 Imm(0) -> x1 - v142 Extend { value=v140, kind=I32 } -> x0 - v143 Imm(0) -> x2 - v144 Extend { value=v141, kind=I32 } -> x1 - v145 Imm(0) -> x2 - v146 Binop { op=eq, lhs=v142, rhs=v144 } -> x0 - v147 BinopI { op=eq, lhs=v146, rhs_imm=0 } -> x0 - terminator Bz { cond=v147, target=b8, fall=b7 } (exit_acc=v147) - block 7 start_pc=0 - v148 Imm(4) -> x0 - terminator Return(v148) (exit_acc=v148) - block 8 start_pc=0 + v113 Imm(2147483647) -> x0 + v114 Imm(4294967295) -> x0 + v115 Imm(1073741823) -> x0 + v116 Imm(4294967295) -> x0 + v117 Imm(268435455) -> x0 + v118 Imm(4294967295) -> x0 + v119 Imm(16777215) -> x0 + v120 Imm(4294967295) -> x0 + v121 Imm(65535) -> x0 + v122 Imm(4294967295) -> x0 + v123 Imm(4294967295) -> x0 + v124 Imm(2147483647) -> x0 + v125 Imm(1431655765) -> x0 + v126 Imm(2863311530) -> x0 + v127 Imm(572662306) -> x0 + v128 Imm(715827882) -> x0 + v129 Imm(572662306) -> x0 + v130 Imm(1145324612) -> x0 + v131 Imm(71582788) -> x0 + v132 Imm(1216907400) -> x0 + v133 Imm(134744072) -> x0 + v134 Imm(526344) -> x0 + v135 Imm(135270416) -> x0 + v136 Imm(2064) -> x0 + v137 Imm(135272480) -> x0 + v138 Imm(32) -> x0 + v139 Imm(32) -> x0 + v140 Imm(0) -> x0 + v141 Imm(0) -> x0 + v142 Imm(0) -> x0 + v143 Imm(0) -> x0 + v144 Imm(0) -> x0 + v145 Imm(0) -> x0 + v146 Imm(1) -> x0 + v147 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v147) + block 4 start_pc=0 v149 Imm(1) -> x0 v150 Imm(0) -> x0 - v151 Imm(-2) -> x1 - v152 Binop { op=and, lhs=v150, rhs=v151 } -> x1 - v153 BinopI { op=and, lhs=v152, rhs_imm=4294967295 } -> x1 - v154 BinopI { op=shru, lhs=v153, rhs_imm=1 } -> x2 - v155 BinopI { op=and, lhs=v154, rhs_imm=1431655765 } -> x2 - v156 Binop { op=sub, lhs=v153, rhs=v155 } -> x1 - v157 BinopI { op=and, lhs=v156, rhs_imm=858993459 } -> x2 - v158 BinopI { op=shru, lhs=v156, rhs_imm=2 } -> x1 - v159 BinopI { op=and, lhs=v158, rhs_imm=858993459 } -> x1 - v160 Binop { op=add, lhs=v157, rhs=v159 } -> x1 - v161 BinopI { op=shru, lhs=v160, rhs_imm=4 } -> x2 - v162 Binop { op=add, lhs=v160, rhs=v161 } -> x1 - v163 BinopI { op=and, lhs=v162, rhs_imm=252645135 } -> x1 - v164 BinopI { op=shru, lhs=v163, rhs_imm=8 } -> x2 - v165 Binop { op=add, lhs=v163, rhs=v164 } -> x1 - v166 BinopI { op=shru, lhs=v165, rhs_imm=16 } -> x2 - v167 Binop { op=add, lhs=v165, rhs=v166 } -> x1 - v168 BinopI { op=and, lhs=v167, rhs_imm=127 } -> x1 - v169 Extend { value=v168, kind=I32 } -> x1 - v170 Imm(0) -> x2 - v171 Extend { value=v150, kind=I32 } -> x0 - v172 Imm(0) -> x2 - v173 Binop { op=eq, lhs=v169, rhs=v171 } -> x0 - v174 BinopI { op=eq, lhs=v173, rhs_imm=0 } -> x0 - terminator Bz { cond=v174, target=b10, fall=b9 } (exit_acc=v174) - block 9 start_pc=0 - v175 Imm(5) -> x0 - terminator Return(v175) (exit_acc=v175) - block 10 start_pc=0 + v151 Imm(-2) -> x0 + v152 Imm(0) -> x0 + v153 Imm(0) -> x0 + v154 Imm(0) -> x0 + v155 Imm(0) -> x0 + v156 Imm(0) -> x0 + v157 Imm(0) -> x0 + v158 Imm(0) -> x0 + v159 Imm(0) -> x0 + v160 Imm(0) -> x0 + v161 Imm(0) -> x0 + v162 Imm(0) -> x0 + v163 Imm(0) -> x0 + v164 Imm(0) -> x0 + v165 Imm(0) -> x0 + v166 Imm(0) -> x0 + v167 Imm(0) -> x0 + v168 Imm(0) -> x0 + v169 Imm(0) -> x0 + v170 Imm(0) -> x0 + v171 Imm(0) -> x0 + v172 Imm(0) -> x0 + v173 Imm(1) -> x0 + v174 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v174) + block 5 start_pc=0 v176 Imm(2147483648) -> x0 v177 Imm(2147483647) -> x0 - v178 Imm(-2147483649) -> x1 - v179 Binop { op=and, lhs=v177, rhs=v178 } -> x0 - v180 BinopI { op=and, lhs=v179, rhs_imm=4294967295 } -> x0 - v181 BinopI { op=shru, lhs=v180, rhs_imm=1 } -> x1 - v182 BinopI { op=and, lhs=v181, rhs_imm=1431655765 } -> x1 - v183 Binop { op=sub, lhs=v180, rhs=v182 } -> x0 - v184 BinopI { op=and, lhs=v183, rhs_imm=858993459 } -> x1 - v185 BinopI { op=shru, lhs=v183, rhs_imm=2 } -> x0 - v186 BinopI { op=and, lhs=v185, rhs_imm=858993459 } -> x0 - v187 Binop { op=add, lhs=v184, rhs=v186 } -> x0 - v188 BinopI { op=shru, lhs=v187, rhs_imm=4 } -> x1 - v189 Binop { op=add, lhs=v187, rhs=v188 } -> x0 - v190 BinopI { op=and, lhs=v189, rhs_imm=252645135 } -> x0 - v191 BinopI { op=shru, lhs=v190, rhs_imm=8 } -> x1 - v192 Binop { op=add, lhs=v190, rhs=v191 } -> x0 - v193 BinopI { op=shru, lhs=v192, rhs_imm=16 } -> x1 - v194 Binop { op=add, lhs=v192, rhs=v193 } -> x0 - v195 BinopI { op=and, lhs=v194, rhs_imm=127 } -> x0 - v196 Imm(31) -> x1 - v197 Extend { value=v195, kind=I32 } -> x0 - v198 Imm(0) -> x2 - v199 Extend { value=v196, kind=I32 } -> x1 - v200 Imm(0) -> x2 - v201 Binop { op=eq, lhs=v197, rhs=v199 } -> x0 - v202 BinopI { op=eq, lhs=v201, rhs_imm=0 } -> x0 - terminator Bz { cond=v202, target=b12, fall=b11 } (exit_acc=v202) - block 11 start_pc=0 - v203 Imm(6) -> x0 - terminator Return(v203) (exit_acc=v203) - block 12 start_pc=0 + v178 Imm(-2147483649) -> x0 + v179 Imm(2147483647) -> x0 + v180 Imm(2147483647) -> x0 + v181 Imm(1073741823) -> x0 + v182 Imm(357913941) -> x0 + v183 Imm(1789569706) -> x0 + v184 Imm(572662306) -> x0 + v185 Imm(447392426) -> x0 + v186 Imm(304226850) -> x0 + v187 Imm(876889156) -> x0 + v188 Imm(54805572) -> x0 + v189 Imm(931694728) -> x0 + v190 Imm(117966856) -> x0 + v191 Imm(460808) -> x0 + v192 Imm(118427664) -> x0 + v193 Imm(1807) -> x0 + v194 Imm(118429471) -> x0 + v195 Imm(31) -> x0 + v196 Imm(31) -> x0 + v197 Imm(31) -> x0 + v198 Imm(0) -> x0 + v199 Imm(31) -> x0 + v200 Imm(0) -> x0 + v201 Imm(1) -> x0 + v202 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v202) + block 6 start_pc=0 v204 Imm(65536) -> x0 v205 Imm(65535) -> x0 - v206 Imm(-65537) -> x1 - v207 Binop { op=and, lhs=v205, rhs=v206 } -> x0 - v208 BinopI { op=and, lhs=v207, rhs_imm=4294967295 } -> x0 - v209 BinopI { op=shru, lhs=v208, rhs_imm=1 } -> x1 - v210 BinopI { op=and, lhs=v209, rhs_imm=1431655765 } -> x1 - v211 Binop { op=sub, lhs=v208, rhs=v210 } -> x0 - v212 BinopI { op=and, lhs=v211, rhs_imm=858993459 } -> x1 - v213 BinopI { op=shru, lhs=v211, rhs_imm=2 } -> x0 - v214 BinopI { op=and, lhs=v213, rhs_imm=858993459 } -> x0 - v215 Binop { op=add, lhs=v212, rhs=v214 } -> x0 - v216 BinopI { op=shru, lhs=v215, rhs_imm=4 } -> x1 - v217 Binop { op=add, lhs=v215, rhs=v216 } -> x0 - v218 BinopI { op=and, lhs=v217, rhs_imm=252645135 } -> x0 - v219 BinopI { op=shru, lhs=v218, rhs_imm=8 } -> x1 - v220 Binop { op=add, lhs=v218, rhs=v219 } -> x0 - v221 BinopI { op=shru, lhs=v220, rhs_imm=16 } -> x1 - v222 Binop { op=add, lhs=v220, rhs=v221 } -> x0 - v223 BinopI { op=and, lhs=v222, rhs_imm=127 } -> x0 - v224 Imm(16) -> x1 - v225 Extend { value=v223, kind=I32 } -> x0 - v226 Imm(0) -> x2 - v227 Extend { value=v224, kind=I32 } -> x1 - v228 Imm(0) -> x2 - v229 Binop { op=eq, lhs=v225, rhs=v227 } -> x0 - v230 BinopI { op=eq, lhs=v229, rhs_imm=0 } -> x0 - terminator Bz { cond=v230, target=b14, fall=b13 } (exit_acc=v230) - block 13 start_pc=0 - v231 Imm(7) -> x0 - terminator Return(v231) (exit_acc=v231) - block 14 start_pc=0 + v206 Imm(-65537) -> x0 + v207 Imm(65535) -> x0 + v208 Imm(65535) -> x0 + v209 Imm(32767) -> x0 + v210 Imm(21845) -> x0 + v211 Imm(43690) -> x0 + v212 Imm(8738) -> x0 + v213 Imm(10922) -> x0 + v214 Imm(8738) -> x0 + v215 Imm(17476) -> x0 + v216 Imm(1092) -> x0 + v217 Imm(18568) -> x0 + v218 Imm(2056) -> x0 + v219 Imm(8) -> x0 + v220 Imm(2064) -> x0 + v221 Imm(0) -> x0 + v222 Imm(2064) -> x0 + v223 Imm(16) -> x0 + v224 Imm(16) -> x0 + v225 Imm(16) -> x0 + v226 Imm(0) -> x0 + v227 Imm(16) -> x0 + v228 Imm(0) -> x0 + v229 Imm(1) -> x0 + v230 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v230) + block 7 start_pc=0 v232 Imm(1073741824) -> x0 v233 Imm(1073741823) -> x0 - v234 Imm(-1073741825) -> x1 - v235 Binop { op=and, lhs=v233, rhs=v234 } -> x0 - v236 BinopI { op=and, lhs=v235, rhs_imm=4294967295 } -> x0 - v237 BinopI { op=shru, lhs=v236, rhs_imm=1 } -> x1 - v238 BinopI { op=and, lhs=v237, rhs_imm=1431655765 } -> x1 - v239 Binop { op=sub, lhs=v236, rhs=v238 } -> x0 - v240 BinopI { op=and, lhs=v239, rhs_imm=858993459 } -> x1 - v241 BinopI { op=shru, lhs=v239, rhs_imm=2 } -> x0 - v242 BinopI { op=and, lhs=v241, rhs_imm=858993459 } -> x0 - v243 Binop { op=add, lhs=v240, rhs=v242 } -> x0 - v244 BinopI { op=shru, lhs=v243, rhs_imm=4 } -> x1 - v245 Binop { op=add, lhs=v243, rhs=v244 } -> x0 - v246 BinopI { op=and, lhs=v245, rhs_imm=252645135 } -> x0 - v247 BinopI { op=shru, lhs=v246, rhs_imm=8 } -> x1 - v248 Binop { op=add, lhs=v246, rhs=v247 } -> x0 - v249 BinopI { op=shru, lhs=v248, rhs_imm=16 } -> x1 - v250 Binop { op=add, lhs=v248, rhs=v249 } -> x0 - v251 BinopI { op=and, lhs=v250, rhs_imm=127 } -> x0 - v252 Imm(30) -> x1 - v253 Extend { value=v251, kind=I32 } -> x0 - v254 Imm(0) -> x2 - v255 Extend { value=v252, kind=I32 } -> x1 - v256 Imm(0) -> x2 - v257 Binop { op=eq, lhs=v253, rhs=v255 } -> x0 - v258 BinopI { op=eq, lhs=v257, rhs_imm=0 } -> x0 - terminator Bz { cond=v258, target=b16, fall=b15 } (exit_acc=v258) - block 15 start_pc=0 - v259 Imm(8) -> x0 - terminator Return(v259) (exit_acc=v259) - block 16 start_pc=0 + v234 Imm(-1073741825) -> x0 + v235 Imm(1073741823) -> x0 + v236 Imm(1073741823) -> x0 + v237 Imm(536870911) -> x0 + v238 Imm(357913941) -> x0 + v239 Imm(715827882) -> x0 + v240 Imm(572662306) -> x0 + v241 Imm(178956970) -> x0 + v242 Imm(35791394) -> x0 + v243 Imm(608453700) -> x0 + v244 Imm(38028356) -> x0 + v245 Imm(646482056) -> x0 + v246 Imm(101189640) -> x0 + v247 Imm(395272) -> x0 + v248 Imm(101584912) -> x0 + v249 Imm(1550) -> x0 + v250 Imm(101586462) -> x0 + v251 Imm(30) -> x0 + v252 Imm(30) -> x0 + v253 Imm(30) -> x0 + v254 Imm(0) -> x0 + v255 Imm(30) -> x0 + v256 Imm(0) -> x0 + v257 Imm(1) -> x0 + v258 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v258) + block 8 start_pc=0 v260 Imm(0) -> x0 - v261 Binop { op=sub, lhs=v260, rhs=v260 } -> x1 - v262 BinopI { op=and, lhs=v261, rhs_imm=858993459 } -> x2 - v263 BinopI { op=shru, lhs=v261, rhs_imm=2 } -> x1 - v264 BinopI { op=and, lhs=v263, rhs_imm=858993459 } -> x1 - v265 Binop { op=add, lhs=v262, rhs=v264 } -> x1 - v266 BinopI { op=shru, lhs=v265, rhs_imm=4 } -> x2 - v267 Binop { op=add, lhs=v265, rhs=v266 } -> x1 - v268 BinopI { op=and, lhs=v267, rhs_imm=252645135 } -> x1 - v269 BinopI { op=shru, lhs=v268, rhs_imm=8 } -> x2 - v270 Binop { op=add, lhs=v268, rhs=v269 } -> x1 - v271 BinopI { op=shru, lhs=v270, rhs_imm=16 } -> x2 - v272 Binop { op=add, lhs=v270, rhs=v271 } -> x1 - v273 BinopI { op=and, lhs=v272, rhs_imm=127 } -> x1 - v274 Extend { value=v273, kind=I32 } -> x1 - v275 Imm(0) -> x2 - v276 Extend { value=v260, kind=I32 } -> x0 - v277 Imm(0) -> x2 - v278 Binop { op=eq, lhs=v274, rhs=v276 } -> x0 - v279 BinopI { op=eq, lhs=v278, rhs_imm=0 } -> x0 - terminator Bz { cond=v279, target=b18, fall=b17 } (exit_acc=v279) - block 17 start_pc=0 - v280 Imm(9) -> x0 - terminator Return(v280) (exit_acc=v280) - block 18 start_pc=0 + v261 Imm(0) -> x0 + v262 Imm(0) -> x0 + v263 Imm(0) -> x0 + v264 Imm(0) -> x0 + v265 Imm(0) -> x0 + v266 Imm(0) -> x0 + v267 Imm(0) -> x0 + v268 Imm(0) -> x0 + v269 Imm(0) -> x0 + v270 Imm(0) -> x0 + v271 Imm(0) -> x0 + v272 Imm(0) -> x0 + v273 Imm(0) -> x0 + v274 Imm(0) -> x0 + v275 Imm(0) -> x0 + v276 Imm(0) -> x0 + v277 Imm(0) -> x0 + v278 Imm(1) -> x0 + v279 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v279) + block 9 start_pc=0 v281 Imm(4294967295) -> x0 - v282 Imm(2147483647) -> x1 - v283 Imm(1431655765) -> x1 - v284 Binop { op=sub, lhs=v281, rhs=v283 } -> x0 - v285 BinopI { op=and, lhs=v284, rhs_imm=858993459 } -> x1 - v286 BinopI { op=shru, lhs=v284, rhs_imm=2 } -> x0 - v287 BinopI { op=and, lhs=v286, rhs_imm=858993459 } -> x0 - v288 Binop { op=add, lhs=v285, rhs=v287 } -> x0 - v289 BinopI { op=shru, lhs=v288, rhs_imm=4 } -> x1 - v290 Binop { op=add, lhs=v288, rhs=v289 } -> x0 - v291 BinopI { op=and, lhs=v290, rhs_imm=252645135 } -> x0 - v292 BinopI { op=shru, lhs=v291, rhs_imm=8 } -> x1 - v293 Binop { op=add, lhs=v291, rhs=v292 } -> x0 - v294 BinopI { op=shru, lhs=v293, rhs_imm=16 } -> x1 - v295 Binop { op=add, lhs=v293, rhs=v294 } -> x0 - v296 BinopI { op=and, lhs=v295, rhs_imm=127 } -> x0 - v297 Imm(32) -> x1 - v298 Extend { value=v296, kind=I32 } -> x0 - v299 Imm(0) -> x2 - v300 Extend { value=v297, kind=I32 } -> x1 - v301 Imm(0) -> x2 - v302 Binop { op=eq, lhs=v298, rhs=v300 } -> x0 - v303 BinopI { op=eq, lhs=v302, rhs_imm=0 } -> x0 - terminator Bz { cond=v303, target=b20, fall=b19 } (exit_acc=v303) - block 19 start_pc=0 - v304 Imm(10) -> x0 - terminator Return(v304) (exit_acc=v304) - block 20 start_pc=0 + v282 Imm(2147483647) -> x0 + v283 Imm(1431655765) -> x0 + v284 Imm(2863311530) -> x0 + v285 Imm(572662306) -> x0 + v286 Imm(715827882) -> x0 + v287 Imm(572662306) -> x0 + v288 Imm(1145324612) -> x0 + v289 Imm(71582788) -> x0 + v290 Imm(1216907400) -> x0 + v291 Imm(134744072) -> x0 + v292 Imm(526344) -> x0 + v293 Imm(135270416) -> x0 + v294 Imm(2064) -> x0 + v295 Imm(135272480) -> x0 + v296 Imm(32) -> x0 + v297 Imm(32) -> x0 + v298 Imm(32) -> x0 + v299 Imm(0) -> x0 + v300 Imm(32) -> x0 + v301 Imm(0) -> x0 + v302 Imm(1) -> x0 + v303 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v303) + block 10 start_pc=0 v305 Imm(252645135) -> x0 - v306 Imm(126322567) -> x1 - v307 Imm(84215045) -> x1 - v308 Binop { op=sub, lhs=v305, rhs=v307 } -> x0 - v309 BinopI { op=and, lhs=v308, rhs_imm=858993459 } -> x1 - v310 BinopI { op=shru, lhs=v308, rhs_imm=2 } -> x0 - v311 BinopI { op=and, lhs=v310, rhs_imm=858993459 } -> x0 - v312 Binop { op=add, lhs=v309, rhs=v311 } -> x0 - v313 BinopI { op=shru, lhs=v312, rhs_imm=4 } -> x1 - v314 Binop { op=add, lhs=v312, rhs=v313 } -> x0 - v315 BinopI { op=and, lhs=v314, rhs_imm=252645135 } -> x0 - v316 BinopI { op=shru, lhs=v315, rhs_imm=8 } -> x1 - v317 Binop { op=add, lhs=v315, rhs=v316 } -> x0 - v318 BinopI { op=shru, lhs=v317, rhs_imm=16 } -> x1 - v319 Binop { op=add, lhs=v317, rhs=v318 } -> x0 - v320 BinopI { op=and, lhs=v319, rhs_imm=127 } -> x0 - v321 Imm(16) -> x1 - v322 Extend { value=v320, kind=I32 } -> x0 - v323 Imm(0) -> x2 - v324 Extend { value=v321, kind=I32 } -> x1 - v325 Imm(0) -> x2 - v326 Binop { op=eq, lhs=v322, rhs=v324 } -> x0 - v327 BinopI { op=eq, lhs=v326, rhs_imm=0 } -> x0 - terminator Bz { cond=v327, target=b22, fall=b21 } (exit_acc=v327) - block 21 start_pc=0 - v328 Imm(11) -> x0 - terminator Return(v328) (exit_acc=v328) - block 22 start_pc=0 + v306 Imm(126322567) -> x0 + v307 Imm(84215045) -> x0 + v308 Imm(168430090) -> x0 + v309 Imm(33686018) -> x0 + v310 Imm(42107522) -> x0 + v311 Imm(33686018) -> x0 + v312 Imm(67372036) -> x0 + v313 Imm(4210752) -> x0 + v314 Imm(71582788) -> x0 + v315 Imm(67372036) -> x0 + v316 Imm(263172) -> x0 + v317 Imm(67635208) -> x0 + v318 Imm(1032) -> x0 + v319 Imm(67636240) -> x0 + v320 Imm(16) -> x0 + v321 Imm(16) -> x0 + v322 Imm(16) -> x0 + v323 Imm(0) -> x0 + v324 Imm(16) -> x0 + v325 Imm(0) -> x0 + v326 Imm(1) -> x0 + v327 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v327) + block 11 start_pc=0 v329 Imm(7) -> x0 - v330 Imm(3) -> x1 - v331 Imm(1) -> x2 - v332 Binop { op=sub, lhs=v329, rhs=v331 } -> x0 - v333 BinopI { op=and, lhs=v332, rhs_imm=858993459 } -> x2 - v334 BinopI { op=shru, lhs=v332, rhs_imm=2 } -> x0 - v335 BinopI { op=and, lhs=v334, rhs_imm=858993459 } -> x0 - v336 Binop { op=add, lhs=v333, rhs=v335 } -> x0 - v337 BinopI { op=shru, lhs=v336, rhs_imm=4 } -> x2 - v338 Binop { op=add, lhs=v336, rhs=v337 } -> x0 - v339 BinopI { op=and, lhs=v338, rhs_imm=252645135 } -> x0 - v340 BinopI { op=shru, lhs=v339, rhs_imm=8 } -> x2 - v341 Binop { op=add, lhs=v339, rhs=v340 } -> x0 - v342 BinopI { op=shru, lhs=v341, rhs_imm=16 } -> x2 - v343 Binop { op=add, lhs=v341, rhs=v342 } -> x0 - v344 BinopI { op=and, lhs=v343, rhs_imm=127 } -> x0 - v345 Extend { value=v344, kind=I32 } -> x0 - v346 Imm(0) -> x2 - v347 Extend { value=v330, kind=I32 } -> x1 - v348 Imm(0) -> x2 - v349 Binop { op=eq, lhs=v345, rhs=v347 } -> x0 - v350 BinopI { op=eq, lhs=v349, rhs_imm=0 } -> x0 - terminator Bz { cond=v350, target=b24, fall=b23 } (exit_acc=v350) - block 23 start_pc=0 - v351 Imm(12) -> x0 - terminator Return(v351) (exit_acc=v351) - block 24 start_pc=0 + v330 Imm(3) -> x0 + v331 Imm(1) -> x0 + v332 Imm(6) -> x0 + v333 Imm(2) -> x0 + v334 Imm(1) -> x0 + v335 Imm(1) -> x0 + v336 Imm(3) -> x0 + v337 Imm(0) -> x0 + v338 Imm(3) -> x0 + v339 Imm(3) -> x0 + v340 Imm(0) -> x0 + v341 Imm(3) -> x0 + v342 Imm(0) -> x0 + v343 Imm(3) -> x0 + v344 Imm(3) -> x0 + v345 Imm(3) -> x0 + v346 Imm(0) -> x0 + v347 Imm(3) -> x0 + v348 Imm(0) -> x0 + v349 Imm(1) -> x0 + v350 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v350) + block 12 start_pc=0 v352 Imm(1) -> x0 - v353 Imm(0) -> x1 - v354 Binop { op=or, lhs=v352, rhs=v353 } -> x0 - v355 BinopI { op=shru, lhs=v354, rhs_imm=2 } -> x1 - v356 Binop { op=or, lhs=v354, rhs=v355 } -> x0 - v357 BinopI { op=shru, lhs=v356, rhs_imm=4 } -> x1 - v358 Binop { op=or, lhs=v356, rhs=v357 } -> x0 - v359 BinopI { op=shru, lhs=v358, rhs_imm=8 } -> x1 - v360 Binop { op=or, lhs=v358, rhs=v359 } -> x0 - v361 BinopI { op=shru, lhs=v360, rhs_imm=16 } -> x1 - v362 Binop { op=or, lhs=v360, rhs=v361 } -> x0 - v363 BinopI { op=shru, lhs=v362, rhs_imm=32 } -> x1 - v364 Binop { op=or, lhs=v362, rhs=v363 } -> x0 - v365 BinopI { op=shru, lhs=v364, rhs_imm=1 } -> x1 - v366 BinopI { op=and, lhs=v365, rhs_imm=6148914691236517205 } -> x1 - v367 Binop { op=sub, lhs=v364, rhs=v366 } -> x0 - v368 BinopI { op=and, lhs=v367, rhs_imm=3689348814741910323 } -> x1 - v369 BinopI { op=shru, lhs=v367, rhs_imm=2 } -> x0 - v370 BinopI { op=and, lhs=v369, rhs_imm=3689348814741910323 } -> x0 - v371 Binop { op=add, lhs=v368, rhs=v370 } -> x0 - v372 BinopI { op=shru, lhs=v371, rhs_imm=4 } -> x1 - v373 Binop { op=add, lhs=v371, rhs=v372 } -> x0 - v374 BinopI { op=and, lhs=v373, rhs_imm=1085102592571150095 } -> x0 - v375 BinopI { op=shru, lhs=v374, rhs_imm=8 } -> x1 - v376 Binop { op=add, lhs=v374, rhs=v375 } -> x0 - v377 BinopI { op=shru, lhs=v376, rhs_imm=16 } -> x1 - v378 Binop { op=add, lhs=v376, rhs=v377 } -> x0 - v379 BinopI { op=shru, lhs=v378, rhs_imm=32 } -> x1 - v380 Binop { op=add, lhs=v378, rhs=v379 } -> x0 - v381 BinopI { op=and, lhs=v380, rhs_imm=127 } -> x0 - v382 Imm(64) -> x1 - v383 Binop { op=sub, lhs=v382, rhs=v381 } -> x0 - v384 Imm(63) -> x1 - v385 Extend { value=v383, kind=I32 } -> x0 - v386 Imm(0) -> x2 - v387 Extend { value=v384, kind=I32 } -> x1 - v388 Imm(0) -> x2 - v389 Binop { op=eq, lhs=v385, rhs=v387 } -> x0 - v390 BinopI { op=eq, lhs=v389, rhs_imm=0 } -> x0 - terminator Bz { cond=v390, target=b26, fall=b25 } (exit_acc=v390) - block 25 start_pc=0 - v391 Imm(13) -> x0 - terminator Return(v391) (exit_acc=v391) - block 26 start_pc=0 + v353 Imm(0) -> x0 + v354 Imm(1) -> x0 + v355 Imm(0) -> x0 + v356 Imm(1) -> x0 + v357 Imm(0) -> x0 + v358 Imm(1) -> x0 + v359 Imm(0) -> x0 + v360 Imm(1) -> x0 + v361 Imm(0) -> x0 + v362 Imm(1) -> x0 + v363 Imm(0) -> x0 + v364 Imm(1) -> x0 + v365 Imm(0) -> x0 + v366 Imm(0) -> x0 + v367 Imm(1) -> x0 + v368 Imm(1) -> x0 + v369 Imm(0) -> x0 + v370 Imm(0) -> x0 + v371 Imm(1) -> x0 + v372 Imm(0) -> x0 + v373 Imm(1) -> x0 + v374 Imm(1) -> x0 + v375 Imm(0) -> x0 + v376 Imm(1) -> x0 + v377 Imm(0) -> x0 + v378 Imm(1) -> x0 + v379 Imm(0) -> x0 + v380 Imm(1) -> x0 + v381 Imm(1) -> x0 + v382 Imm(64) -> x0 + v383 Imm(63) -> x0 + v384 Imm(63) -> x0 + v385 Imm(63) -> x0 + v386 Imm(0) -> x0 + v387 Imm(63) -> x0 + v388 Imm(0) -> x0 + v389 Imm(1) -> x0 + v390 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v390) + block 13 start_pc=0 v392 Imm(-9223372036854775808) -> x0 - v393 Imm(4611686018427387904) -> x1 - v394 Binop { op=or, lhs=v392, rhs=v393 } -> x0 - v395 BinopI { op=shru, lhs=v394, rhs_imm=2 } -> x1 - v396 Binop { op=or, lhs=v394, rhs=v395 } -> x0 - v397 BinopI { op=shru, lhs=v396, rhs_imm=4 } -> x1 - v398 Binop { op=or, lhs=v396, rhs=v397 } -> x0 - v399 BinopI { op=shru, lhs=v398, rhs_imm=8 } -> x1 - v400 Binop { op=or, lhs=v398, rhs=v399 } -> x0 - v401 BinopI { op=shru, lhs=v400, rhs_imm=16 } -> x1 - v402 Binop { op=or, lhs=v400, rhs=v401 } -> x0 - v403 BinopI { op=shru, lhs=v402, rhs_imm=32 } -> x1 - v404 Binop { op=or, lhs=v402, rhs=v403 } -> x0 - v405 BinopI { op=shru, lhs=v404, rhs_imm=1 } -> x1 - v406 BinopI { op=and, lhs=v405, rhs_imm=6148914691236517205 } -> x1 - v407 Binop { op=sub, lhs=v404, rhs=v406 } -> x0 - v408 BinopI { op=and, lhs=v407, rhs_imm=3689348814741910323 } -> x1 - v409 BinopI { op=shru, lhs=v407, rhs_imm=2 } -> x0 - v410 BinopI { op=and, lhs=v409, rhs_imm=3689348814741910323 } -> x0 - v411 Binop { op=add, lhs=v408, rhs=v410 } -> x0 - v412 BinopI { op=shru, lhs=v411, rhs_imm=4 } -> x1 - v413 Binop { op=add, lhs=v411, rhs=v412 } -> x0 - v414 BinopI { op=and, lhs=v413, rhs_imm=1085102592571150095 } -> x0 - v415 BinopI { op=shru, lhs=v414, rhs_imm=8 } -> x1 - v416 Binop { op=add, lhs=v414, rhs=v415 } -> x0 - v417 BinopI { op=shru, lhs=v416, rhs_imm=16 } -> x1 - v418 Binop { op=add, lhs=v416, rhs=v417 } -> x0 - v419 BinopI { op=shru, lhs=v418, rhs_imm=32 } -> x1 - v420 Binop { op=add, lhs=v418, rhs=v419 } -> x0 - v421 BinopI { op=and, lhs=v420, rhs_imm=127 } -> x0 - v422 Imm(64) -> x1 - v423 Binop { op=sub, lhs=v422, rhs=v421 } -> x0 - v424 Imm(0) -> x1 - v425 Extend { value=v423, kind=I32 } -> x0 - v426 Imm(0) -> x2 - v427 Extend { value=v424, kind=I32 } -> x1 - v428 Imm(0) -> x2 - v429 Binop { op=eq, lhs=v425, rhs=v427 } -> x0 - v430 BinopI { op=eq, lhs=v429, rhs_imm=0 } -> x0 - terminator Bz { cond=v430, target=b28, fall=b27 } (exit_acc=v430) - block 27 start_pc=0 - v431 Imm(14) -> x0 - terminator Return(v431) (exit_acc=v431) - block 28 start_pc=0 + v393 Imm(4611686018427387904) -> x0 + v394 Imm(-4611686018427387904) -> x0 + v395 Imm(3458764513820540928) -> x0 + v396 Imm(-1152921504606846976) -> x0 + v397 Imm(1080863910568919040) -> x0 + v398 Imm(-72057594037927936) -> x0 + v399 Imm(71776119061217280) -> x0 + v400 Imm(-281474976710656) -> x0 + v401 Imm(281470681743360) -> x0 + v402 Imm(-4294967296) -> x0 + v403 Imm(4294967295) -> x0 + v404 Imm(-1) -> x0 + v405 Imm(9223372036854775807) -> x0 + v406 Imm(6148914691236517205) -> x0 + v407 Imm(-6148914691236517206) -> x0 + v408 Imm(2459565876494606882) -> x0 + v409 Imm(3074457345618258602) -> x0 + v410 Imm(2459565876494606882) -> x0 + v411 Imm(4919131752989213764) -> x0 + v412 Imm(307445734561825860) -> x0 + v413 Imm(5226577487551039624) -> x0 + v414 Imm(578721382704613384) -> x0 + v415 Imm(2260630401189896) -> x0 + v416 Imm(580982013105803280) -> x0 + v417 Imm(8865081987088) -> x0 + v418 Imm(580990878187790368) -> x0 + v419 Imm(135272480) -> x0 + v420 Imm(580990878323062848) -> x0 + v421 Imm(64) -> x0 + v422 Imm(64) -> x0 + v423 Imm(0) -> x0 + v424 Imm(0) -> x0 + v425 Imm(0) -> x0 + v426 Imm(0) -> x0 + v427 Imm(0) -> x0 + v428 Imm(0) -> x0 + v429 Imm(1) -> x0 + v430 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v430) + block 14 start_pc=0 v432 Imm(4294967296) -> x0 - v433 Imm(2147483648) -> x1 - v434 Binop { op=or, lhs=v432, rhs=v433 } -> x0 - v435 BinopI { op=shru, lhs=v434, rhs_imm=2 } -> x1 - v436 Binop { op=or, lhs=v434, rhs=v435 } -> x0 - v437 BinopI { op=shru, lhs=v436, rhs_imm=4 } -> x1 - v438 Binop { op=or, lhs=v436, rhs=v437 } -> x0 - v439 BinopI { op=shru, lhs=v438, rhs_imm=8 } -> x1 - v440 Binop { op=or, lhs=v438, rhs=v439 } -> x0 - v441 BinopI { op=shru, lhs=v440, rhs_imm=16 } -> x1 - v442 Binop { op=or, lhs=v440, rhs=v441 } -> x0 - v443 BinopI { op=shru, lhs=v442, rhs_imm=32 } -> x1 - v444 Binop { op=or, lhs=v442, rhs=v443 } -> x0 - v445 BinopI { op=shru, lhs=v444, rhs_imm=1 } -> x1 - v446 BinopI { op=and, lhs=v445, rhs_imm=6148914691236517205 } -> x1 - v447 Binop { op=sub, lhs=v444, rhs=v446 } -> x0 - v448 BinopI { op=and, lhs=v447, rhs_imm=3689348814741910323 } -> x1 - v449 BinopI { op=shru, lhs=v447, rhs_imm=2 } -> x0 - v450 BinopI { op=and, lhs=v449, rhs_imm=3689348814741910323 } -> x0 - v451 Binop { op=add, lhs=v448, rhs=v450 } -> x0 - v452 BinopI { op=shru, lhs=v451, rhs_imm=4 } -> x1 - v453 Binop { op=add, lhs=v451, rhs=v452 } -> x0 - v454 BinopI { op=and, lhs=v453, rhs_imm=1085102592571150095 } -> x0 - v455 BinopI { op=shru, lhs=v454, rhs_imm=8 } -> x1 - v456 Binop { op=add, lhs=v454, rhs=v455 } -> x0 - v457 BinopI { op=shru, lhs=v456, rhs_imm=16 } -> x1 - v458 Binop { op=add, lhs=v456, rhs=v457 } -> x0 - v459 BinopI { op=shru, lhs=v458, rhs_imm=32 } -> x1 - v460 Binop { op=add, lhs=v458, rhs=v459 } -> x0 - v461 BinopI { op=and, lhs=v460, rhs_imm=127 } -> x0 - v462 Imm(64) -> x1 - v463 Binop { op=sub, lhs=v462, rhs=v461 } -> x0 - v464 Imm(31) -> x1 - v465 Extend { value=v463, kind=I32 } -> x0 - v466 Imm(0) -> x2 - v467 Extend { value=v464, kind=I32 } -> x1 - v468 Imm(0) -> x2 - v469 Binop { op=eq, lhs=v465, rhs=v467 } -> x0 - v470 BinopI { op=eq, lhs=v469, rhs_imm=0 } -> x0 - terminator Bz { cond=v470, target=b30, fall=b29 } (exit_acc=v470) - block 29 start_pc=0 - v471 Imm(15) -> x0 - terminator Return(v471) (exit_acc=v471) - block 30 start_pc=0 + v433 Imm(2147483648) -> x0 + v434 Imm(6442450944) -> x0 + v435 Imm(1610612736) -> x0 + v436 Imm(8053063680) -> x0 + v437 Imm(503316480) -> x0 + v438 Imm(8556380160) -> x0 + v439 Imm(33423360) -> x0 + v440 Imm(8589803520) -> x0 + v441 Imm(131070) -> x0 + v442 Imm(8589934590) -> x0 + v443 Imm(1) -> x0 + v444 Imm(8589934591) -> x0 + v445 Imm(4294967295) -> x0 + v446 Imm(1431655765) -> x0 + v447 Imm(7158278826) -> x0 + v448 Imm(4867629602) -> x0 + v449 Imm(1789569706) -> x0 + v450 Imm(572662306) -> x0 + v451 Imm(5440291908) -> x0 + v452 Imm(340018244) -> x0 + v453 Imm(5780310152) -> x0 + v454 Imm(4429711368) -> x0 + v455 Imm(17303560) -> x0 + v456 Imm(4447014928) -> x0 + v457 Imm(67856) -> x0 + v458 Imm(4447082784) -> x0 + v459 Imm(1) -> x0 + v460 Imm(4447082785) -> x0 + v461 Imm(33) -> x0 + v462 Imm(64) -> x0 + v463 Imm(31) -> x0 + v464 Imm(31) -> x0 + v465 Imm(31) -> x0 + v466 Imm(0) -> x0 + v467 Imm(31) -> x0 + v468 Imm(0) -> x0 + v469 Imm(1) -> x0 + v470 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v470) + block 15 start_pc=0 v472 Imm(1) -> x0 v473 Imm(0) -> x0 - v474 Imm(-2) -> x1 - v475 Binop { op=and, lhs=v473, rhs=v474 } -> x1 - v476 BinopI { op=shru, lhs=v475, rhs_imm=1 } -> x2 - v477 BinopI { op=and, lhs=v476, rhs_imm=6148914691236517205 } -> x2 - v478 Binop { op=sub, lhs=v475, rhs=v477 } -> x1 - v479 BinopI { op=and, lhs=v478, rhs_imm=3689348814741910323 } -> x2 - v480 BinopI { op=shru, lhs=v478, rhs_imm=2 } -> x1 - v481 BinopI { op=and, lhs=v480, rhs_imm=3689348814741910323 } -> x1 - v482 Binop { op=add, lhs=v479, rhs=v481 } -> x1 - v483 BinopI { op=shru, lhs=v482, rhs_imm=4 } -> x2 - v484 Binop { op=add, lhs=v482, rhs=v483 } -> x1 - v485 BinopI { op=and, lhs=v484, rhs_imm=1085102592571150095 } -> x1 - v486 BinopI { op=shru, lhs=v485, rhs_imm=8 } -> x2 - v487 Binop { op=add, lhs=v485, rhs=v486 } -> x1 - v488 BinopI { op=shru, lhs=v487, rhs_imm=16 } -> x2 - v489 Binop { op=add, lhs=v487, rhs=v488 } -> x1 - v490 BinopI { op=shru, lhs=v489, rhs_imm=32 } -> x2 - v491 Binop { op=add, lhs=v489, rhs=v490 } -> x1 - v492 BinopI { op=and, lhs=v491, rhs_imm=127 } -> x1 - v493 Extend { value=v492, kind=I32 } -> x1 - v494 Imm(0) -> x2 - v495 Extend { value=v473, kind=I32 } -> x0 - v496 Imm(0) -> x2 - v497 Binop { op=eq, lhs=v493, rhs=v495 } -> x0 - v498 BinopI { op=eq, lhs=v497, rhs_imm=0 } -> x0 - terminator Bz { cond=v498, target=b32, fall=b31 } (exit_acc=v498) - block 31 start_pc=0 - v499 Imm(16) -> x0 - terminator Return(v499) (exit_acc=v499) - block 32 start_pc=0 + v474 Imm(-2) -> x0 + v475 Imm(0) -> x0 + v476 Imm(0) -> x0 + v477 Imm(0) -> x0 + v478 Imm(0) -> x0 + v479 Imm(0) -> x0 + v480 Imm(0) -> x0 + v481 Imm(0) -> x0 + v482 Imm(0) -> x0 + v483 Imm(0) -> x0 + v484 Imm(0) -> x0 + v485 Imm(0) -> x0 + v486 Imm(0) -> x0 + v487 Imm(0) -> x0 + v488 Imm(0) -> x0 + v489 Imm(0) -> x0 + v490 Imm(0) -> x0 + v491 Imm(0) -> x0 + v492 Imm(0) -> x0 + v493 Imm(0) -> x0 + v494 Imm(0) -> x0 + v495 Imm(0) -> x0 + v496 Imm(0) -> x0 + v497 Imm(1) -> x0 + v498 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v498) + block 16 start_pc=0 v500 Imm(-9223372036854775808) -> x0 v501 Imm(9223372036854775807) -> x0 - v502 Binop { op=and, lhs=v501, rhs=v501 } -> x0 - v503 BinopI { op=shru, lhs=v502, rhs_imm=1 } -> x1 - v504 BinopI { op=and, lhs=v503, rhs_imm=6148914691236517205 } -> x1 - v505 Binop { op=sub, lhs=v502, rhs=v504 } -> x0 - v506 BinopI { op=and, lhs=v505, rhs_imm=3689348814741910323 } -> x1 - v507 BinopI { op=shru, lhs=v505, rhs_imm=2 } -> x0 - v508 BinopI { op=and, lhs=v507, rhs_imm=3689348814741910323 } -> x0 - v509 Binop { op=add, lhs=v506, rhs=v508 } -> x0 - v510 BinopI { op=shru, lhs=v509, rhs_imm=4 } -> x1 - v511 Binop { op=add, lhs=v509, rhs=v510 } -> x0 - v512 BinopI { op=and, lhs=v511, rhs_imm=1085102592571150095 } -> x0 - v513 BinopI { op=shru, lhs=v512, rhs_imm=8 } -> x1 - v514 Binop { op=add, lhs=v512, rhs=v513 } -> x0 - v515 BinopI { op=shru, lhs=v514, rhs_imm=16 } -> x1 - v516 Binop { op=add, lhs=v514, rhs=v515 } -> x0 - v517 BinopI { op=shru, lhs=v516, rhs_imm=32 } -> x1 - v518 Binop { op=add, lhs=v516, rhs=v517 } -> x0 - v519 BinopI { op=and, lhs=v518, rhs_imm=127 } -> x0 - v520 Imm(63) -> x1 - v521 Extend { value=v519, kind=I32 } -> x0 - v522 Imm(0) -> x2 - v523 Extend { value=v520, kind=I32 } -> x1 - v524 Imm(0) -> x2 - v525 Binop { op=eq, lhs=v521, rhs=v523 } -> x0 - v526 BinopI { op=eq, lhs=v525, rhs_imm=0 } -> x0 - terminator Bz { cond=v526, target=b34, fall=b33 } (exit_acc=v526) - block 33 start_pc=0 - v527 Imm(17) -> x0 - terminator Return(v527) (exit_acc=v527) - block 34 start_pc=0 + v502 Imm(9223372036854775807) -> x0 + v503 Imm(4611686018427387903) -> x0 + v504 Imm(1537228672809129301) -> x0 + v505 Imm(7686143364045646506) -> x0 + v506 Imm(2459565876494606882) -> x0 + v507 Imm(1921535841011411626) -> x0 + v508 Imm(1306644371887759906) -> x0 + v509 Imm(3766210248382366788) -> x0 + v510 Imm(235388140523897924) -> x0 + v511 Imm(4001598388906264712) -> x0 + v512 Imm(506663788666685448) -> x0 + v513 Imm(1979155424479240) -> x0 + v514 Imm(508642944091164688) -> x0 + v515 Imm(7761275392016) -> x0 + v516 Imm(508650705366556704) -> x0 + v517 Imm(118429471) -> x0 + v518 Imm(508650705484986175) -> x0 + v519 Imm(63) -> x0 + v520 Imm(63) -> x0 + v521 Imm(63) -> x0 + v522 Imm(0) -> x0 + v523 Imm(63) -> x0 + v524 Imm(0) -> x0 + v525 Imm(1) -> x0 + v526 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v526) + block 17 start_pc=0 v528 Imm(4294967296) -> x0 v529 Imm(4294967295) -> x0 - v530 Imm(-4294967297) -> x1 - v531 Binop { op=and, lhs=v529, rhs=v530 } -> x0 - v532 BinopI { op=shru, lhs=v531, rhs_imm=1 } -> x1 - v533 BinopI { op=and, lhs=v532, rhs_imm=6148914691236517205 } -> x1 - v534 Binop { op=sub, lhs=v531, rhs=v533 } -> x0 - v535 BinopI { op=and, lhs=v534, rhs_imm=3689348814741910323 } -> x1 - v536 BinopI { op=shru, lhs=v534, rhs_imm=2 } -> x0 - v537 BinopI { op=and, lhs=v536, rhs_imm=3689348814741910323 } -> x0 - v538 Binop { op=add, lhs=v535, rhs=v537 } -> x0 - v539 BinopI { op=shru, lhs=v538, rhs_imm=4 } -> x1 - v540 Binop { op=add, lhs=v538, rhs=v539 } -> x0 - v541 BinopI { op=and, lhs=v540, rhs_imm=1085102592571150095 } -> x0 - v542 BinopI { op=shru, lhs=v541, rhs_imm=8 } -> x1 - v543 Binop { op=add, lhs=v541, rhs=v542 } -> x0 - v544 BinopI { op=shru, lhs=v543, rhs_imm=16 } -> x1 - v545 Binop { op=add, lhs=v543, rhs=v544 } -> x0 - v546 BinopI { op=shru, lhs=v545, rhs_imm=32 } -> x1 - v547 Binop { op=add, lhs=v545, rhs=v546 } -> x0 - v548 BinopI { op=and, lhs=v547, rhs_imm=127 } -> x0 - v549 Imm(32) -> x1 - v550 Extend { value=v548, kind=I32 } -> x0 - v551 Imm(0) -> x2 - v552 Extend { value=v549, kind=I32 } -> x1 - v553 Imm(0) -> x2 - v554 Binop { op=eq, lhs=v550, rhs=v552 } -> x0 - v555 BinopI { op=eq, lhs=v554, rhs_imm=0 } -> x0 - terminator Bz { cond=v555, target=b36, fall=b35 } (exit_acc=v555) - block 35 start_pc=0 - v556 Imm(18) -> x0 - terminator Return(v556) (exit_acc=v556) - block 36 start_pc=0 + v530 Imm(-4294967297) -> x0 + v531 Imm(4294967295) -> x0 + v532 Imm(2147483647) -> x0 + v533 Imm(1431655765) -> x0 + v534 Imm(2863311530) -> x0 + v535 Imm(572662306) -> x0 + v536 Imm(715827882) -> x0 + v537 Imm(572662306) -> x0 + v538 Imm(1145324612) -> x0 + v539 Imm(71582788) -> x0 + v540 Imm(1216907400) -> x0 + v541 Imm(134744072) -> x0 + v542 Imm(526344) -> x0 + v543 Imm(135270416) -> x0 + v544 Imm(2064) -> x0 + v545 Imm(135272480) -> x0 + v546 Imm(0) -> x0 + v547 Imm(135272480) -> x0 + v548 Imm(32) -> x0 + v549 Imm(32) -> x0 + v550 Imm(32) -> x0 + v551 Imm(0) -> x0 + v552 Imm(32) -> x0 + v553 Imm(0) -> x0 + v554 Imm(1) -> x0 + v555 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v555) + block 18 start_pc=0 v557 Imm(-1) -> x0 - v558 Imm(9223372036854775807) -> x1 - v559 Imm(6148914691236517205) -> x1 - v560 Binop { op=sub, lhs=v557, rhs=v559 } -> x0 - v561 BinopI { op=and, lhs=v560, rhs_imm=3689348814741910323 } -> x1 - v562 BinopI { op=shru, lhs=v560, rhs_imm=2 } -> x0 - v563 BinopI { op=and, lhs=v562, rhs_imm=3689348814741910323 } -> x0 - v564 Binop { op=add, lhs=v561, rhs=v563 } -> x0 - v565 BinopI { op=shru, lhs=v564, rhs_imm=4 } -> x1 - v566 Binop { op=add, lhs=v564, rhs=v565 } -> x0 - v567 BinopI { op=and, lhs=v566, rhs_imm=1085102592571150095 } -> x0 - v568 BinopI { op=shru, lhs=v567, rhs_imm=8 } -> x1 - v569 Binop { op=add, lhs=v567, rhs=v568 } -> x0 - v570 BinopI { op=shru, lhs=v569, rhs_imm=16 } -> x1 - v571 Binop { op=add, lhs=v569, rhs=v570 } -> x0 - v572 BinopI { op=shru, lhs=v571, rhs_imm=32 } -> x1 - v573 Binop { op=add, lhs=v571, rhs=v572 } -> x0 - v574 BinopI { op=and, lhs=v573, rhs_imm=127 } -> x0 - v575 Imm(64) -> x1 - v576 Extend { value=v574, kind=I32 } -> x0 - v577 Imm(0) -> x2 - v578 Extend { value=v575, kind=I32 } -> x1 - v579 Imm(0) -> x2 - v580 Binop { op=eq, lhs=v576, rhs=v578 } -> x0 - v581 BinopI { op=eq, lhs=v580, rhs_imm=0 } -> x0 - terminator Bz { cond=v581, target=b38, fall=b37 } (exit_acc=v581) - block 37 start_pc=0 - v582 Imm(19) -> x0 - terminator Return(v582) (exit_acc=v582) - block 38 start_pc=0 + v558 Imm(9223372036854775807) -> x0 + v559 Imm(6148914691236517205) -> x0 + v560 Imm(-6148914691236517206) -> x0 + v561 Imm(2459565876494606882) -> x0 + v562 Imm(3074457345618258602) -> x0 + v563 Imm(2459565876494606882) -> x0 + v564 Imm(4919131752989213764) -> x0 + v565 Imm(307445734561825860) -> x0 + v566 Imm(5226577487551039624) -> x0 + v567 Imm(578721382704613384) -> x0 + v568 Imm(2260630401189896) -> x0 + v569 Imm(580982013105803280) -> x0 + v570 Imm(8865081987088) -> x0 + v571 Imm(580990878187790368) -> x0 + v572 Imm(135272480) -> x0 + v573 Imm(580990878323062848) -> x0 + v574 Imm(64) -> x0 + v575 Imm(64) -> x0 + v576 Imm(64) -> x0 + v577 Imm(0) -> x0 + v578 Imm(64) -> x0 + v579 Imm(0) -> x0 + v580 Imm(1) -> x0 + v581 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v581) + block 19 start_pc=0 v583 Imm(244837814094590) -> x0 - v584 Imm(122418907047295) -> x1 - v585 Imm(76228511221077) -> x1 - v586 Binop { op=sub, lhs=v583, rhs=v585 } -> x0 - v587 BinopI { op=and, lhs=v586, rhs_imm=3689348814741910323 } -> x1 - v588 BinopI { op=shru, lhs=v586, rhs_imm=2 } -> x0 - v589 BinopI { op=and, lhs=v588, rhs_imm=3689348814741910323 } -> x0 - v590 Binop { op=add, lhs=v587, rhs=v589 } -> x0 - v591 BinopI { op=shru, lhs=v590, rhs_imm=4 } -> x1 - v592 Binop { op=add, lhs=v590, rhs=v591 } -> x0 - v593 BinopI { op=and, lhs=v592, rhs_imm=1085102592571150095 } -> x0 - v594 BinopI { op=shru, lhs=v593, rhs_imm=8 } -> x1 - v595 Binop { op=add, lhs=v593, rhs=v594 } -> x0 - v596 BinopI { op=shru, lhs=v595, rhs_imm=16 } -> x1 - v597 Binop { op=add, lhs=v595, rhs=v596 } -> x0 - v598 BinopI { op=shru, lhs=v597, rhs_imm=32 } -> x1 - v599 Binop { op=add, lhs=v597, rhs=v598 } -> x0 - v600 BinopI { op=and, lhs=v599, rhs_imm=127 } -> x0 - v601 Imm(35) -> x1 - v602 Extend { value=v600, kind=I32 } -> x0 - v603 Imm(0) -> x2 - v604 Extend { value=v601, kind=I32 } -> x1 - v605 Imm(0) -> x2 - v606 Binop { op=eq, lhs=v602, rhs=v604 } -> x0 - v607 BinopI { op=eq, lhs=v606, rhs_imm=0 } -> x0 - terminator Bz { cond=v607, target=b40, fall=b39 } (exit_acc=v607) - block 39 start_pc=0 - v608 Imm(20) -> x0 - terminator Return(v608) (exit_acc=v608) - block 40 start_pc=0 + v584 Imm(122418907047295) -> x0 + v585 Imm(76228511221077) -> x0 + v586 Imm(168609302873513) -> x0 + v587 Imm(18765266944289) -> x0 + v588 Imm(42152325718378) -> x0 + v589 Imm(37461008982306) -> x0 + v590 Imm(56226275926595) -> x0 + v591 Imm(3514142245412) -> x0 + v592 Imm(59740418172007) -> x0 + v593 Imm(6618645726215) -> x0 + v594 Imm(25854084868) -> x0 + v595 Imm(6644499811083) -> x0 + v596 Imm(101387021) -> x0 + v597 Imm(6644601198104) -> x0 + v598 Imm(1547) -> x0 + v599 Imm(6644601199651) -> x0 + v600 Imm(35) -> x0 + v601 Imm(35) -> x0 + v602 Imm(35) -> x0 + v603 Imm(0) -> x0 + v604 Imm(35) -> x0 + v605 Imm(0) -> x0 + v606 Imm(1) -> x0 + v607 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v607) + block 20 start_pc=0 v609 Imm(16711935) -> x0 v610 StoreLocal { off=-1, value=v609, kind=I32, volatile } -> - v611 LoadLocal { off=-1, kind=U32, volatile } -> x0 @@ -726,16 +666,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v626 BinopI { op=and, lhs=v625, rhs_imm=127 } -> x0 v627 Imm(16) -> x1 v628 Extend { value=v626, kind=I32 } -> x0 - v629 Imm(0) -> x2 - v630 Extend { value=v627, kind=I32 } -> x1 - v631 Imm(0) -> x2 - v632 Binop { op=eq, lhs=v628, rhs=v630 } -> x0 + v629 Imm(0) -> x1 + v630 Imm(16) -> x1 + v631 Imm(0) -> x1 + v632 BinopI { op=eq, lhs=v628, rhs_imm=16 } -> x0 v633 BinopI { op=eq, lhs=v632, rhs_imm=0 } -> x0 - terminator Bz { cond=v633, target=b42, fall=b41 } (exit_acc=v633) - block 41 start_pc=0 + terminator Bz { cond=v633, target=b22, fall=b21 } (exit_acc=v633) + block 21 start_pc=0 v634 Imm(21) -> x0 terminator Return(v634) (exit_acc=v634) - block 42 start_pc=0 + block 22 start_pc=0 v635 LoadLocal { off=-1, kind=U32, volatile } -> x0 v636 BinopI { op=shru, lhs=v635, rhs_imm=1 } -> x1 v637 Binop { op=or, lhs=v635, rhs=v636 } -> x0 @@ -767,16 +707,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v663 Binop { op=sub, lhs=v662, rhs=v661 } -> x0 v664 Imm(8) -> x1 v665 Extend { value=v663, kind=I32 } -> x0 - v666 Imm(0) -> x2 - v667 Extend { value=v664, kind=I32 } -> x1 - v668 Imm(0) -> x2 - v669 Binop { op=eq, lhs=v665, rhs=v667 } -> x0 + v666 Imm(0) -> x1 + v667 Imm(8) -> x1 + v668 Imm(0) -> x1 + v669 BinopI { op=eq, lhs=v665, rhs_imm=8 } -> x0 v670 BinopI { op=eq, lhs=v669, rhs_imm=0 } -> x0 - terminator Bz { cond=v670, target=b44, fall=b43 } (exit_acc=v670) - block 43 start_pc=0 + terminator Bz { cond=v670, target=b24, fall=b23 } (exit_acc=v670) + block 23 start_pc=0 v671 Imm(22) -> x0 terminator Return(v671) (exit_acc=v671) - block 44 start_pc=0 + block 24 start_pc=0 v672 LoadLocal { off=-1, kind=U32, volatile } -> x0 v673 BinopI { op=sub, lhs=v672, rhs_imm=1 } -> x1 v674 BinopI { op=xor, lhs=v672, rhs_imm=-1 } -> x0 @@ -799,140 +739,128 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v691 BinopI { op=and, lhs=v690, rhs_imm=127 } -> x0 v692 Imm(0) -> x1 v693 Extend { value=v691, kind=I32 } -> x0 - v694 Imm(0) -> x2 - v695 Extend { value=v692, kind=I32 } -> x1 - v696 Imm(0) -> x2 - v697 Binop { op=eq, lhs=v693, rhs=v695 } -> x0 + v694 Imm(0) -> x1 + v695 Imm(0) -> x1 + v696 Imm(0) -> x1 + v697 BinopI { op=eq, lhs=v693, rhs_imm=0 } -> x0 v698 BinopI { op=eq, lhs=v697, rhs_imm=0 } -> x0 - terminator Bz { cond=v698, target=b46, fall=b45 } (exit_acc=v698) - block 45 start_pc=0 + terminator Bz { cond=v698, target=b26, fall=b25 } (exit_acc=v698) + block 25 start_pc=0 v699 Imm(23) -> x0 terminator Return(v699) (exit_acc=v699) - block 46 start_pc=0 + block 26 start_pc=0 v700 Imm(1) -> x0 v701 Imm(0) -> x0 - v702 Imm(-2) -> x1 - v703 Binop { op=and, lhs=v701, rhs=v702 } -> x1 - v704 BinopI { op=shru, lhs=v703, rhs_imm=1 } -> x2 - v705 BinopI { op=and, lhs=v704, rhs_imm=6148914691236517205 } -> x2 - v706 Binop { op=sub, lhs=v703, rhs=v705 } -> x1 - v707 BinopI { op=and, lhs=v706, rhs_imm=3689348814741910323 } -> x2 - v708 BinopI { op=shru, lhs=v706, rhs_imm=2 } -> x1 - v709 BinopI { op=and, lhs=v708, rhs_imm=3689348814741910323 } -> x1 - v710 Binop { op=add, lhs=v707, rhs=v709 } -> x1 - v711 BinopI { op=shru, lhs=v710, rhs_imm=4 } -> x2 - v712 Binop { op=add, lhs=v710, rhs=v711 } -> x1 - v713 BinopI { op=and, lhs=v712, rhs_imm=1085102592571150095 } -> x1 - v714 BinopI { op=shru, lhs=v713, rhs_imm=8 } -> x2 - v715 Binop { op=add, lhs=v713, rhs=v714 } -> x1 - v716 BinopI { op=shru, lhs=v715, rhs_imm=16 } -> x2 - v717 Binop { op=add, lhs=v715, rhs=v716 } -> x1 - v718 BinopI { op=shru, lhs=v717, rhs_imm=32 } -> x2 - v719 Binop { op=add, lhs=v717, rhs=v718 } -> x1 - v720 BinopI { op=and, lhs=v719, rhs_imm=127 } -> x1 - v721 Extend { value=v720, kind=I32 } -> x1 - v722 Imm(0) -> x2 - v723 Extend { value=v701, kind=I32 } -> x0 - v724 Imm(0) -> x2 - v725 Binop { op=eq, lhs=v721, rhs=v723 } -> x0 - v726 BinopI { op=eq, lhs=v725, rhs_imm=0 } -> x0 - terminator Bz { cond=v726, target=b48, fall=b47 } (exit_acc=v726) - block 47 start_pc=0 - v727 Imm(24) -> x0 - terminator Return(v727) (exit_acc=v727) - block 48 start_pc=0 + v702 Imm(-2) -> x0 + v703 Imm(0) -> x0 + v704 Imm(0) -> x0 + v705 Imm(0) -> x0 + v706 Imm(0) -> x0 + v707 Imm(0) -> x0 + v708 Imm(0) -> x0 + v709 Imm(0) -> x0 + v710 Imm(0) -> x0 + v711 Imm(0) -> x0 + v712 Imm(0) -> x0 + v713 Imm(0) -> x0 + v714 Imm(0) -> x0 + v715 Imm(0) -> x0 + v716 Imm(0) -> x0 + v717 Imm(0) -> x0 + v718 Imm(0) -> x0 + v719 Imm(0) -> x0 + v720 Imm(0) -> x0 + v721 Imm(0) -> x0 + v722 Imm(0) -> x0 + v723 Imm(0) -> x0 + v724 Imm(0) -> x0 + v725 Imm(1) -> x0 + v726 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v726) + block 27 start_pc=0 v728 Imm(65536) -> x0 v729 Imm(65535) -> x0 - v730 Imm(-65537) -> x1 - v731 Binop { op=and, lhs=v729, rhs=v730 } -> x0 - v732 BinopI { op=shru, lhs=v731, rhs_imm=1 } -> x1 - v733 BinopI { op=and, lhs=v732, rhs_imm=6148914691236517205 } -> x1 - v734 Binop { op=sub, lhs=v731, rhs=v733 } -> x0 - v735 BinopI { op=and, lhs=v734, rhs_imm=3689348814741910323 } -> x1 - v736 BinopI { op=shru, lhs=v734, rhs_imm=2 } -> x0 - v737 BinopI { op=and, lhs=v736, rhs_imm=3689348814741910323 } -> x0 - v738 Binop { op=add, lhs=v735, rhs=v737 } -> x0 - v739 BinopI { op=shru, lhs=v738, rhs_imm=4 } -> x1 - v740 Binop { op=add, lhs=v738, rhs=v739 } -> x0 - v741 BinopI { op=and, lhs=v740, rhs_imm=1085102592571150095 } -> x0 - v742 BinopI { op=shru, lhs=v741, rhs_imm=8 } -> x1 - v743 Binop { op=add, lhs=v741, rhs=v742 } -> x0 - v744 BinopI { op=shru, lhs=v743, rhs_imm=16 } -> x1 - v745 Binop { op=add, lhs=v743, rhs=v744 } -> x0 - v746 BinopI { op=shru, lhs=v745, rhs_imm=32 } -> x1 - v747 Binop { op=add, lhs=v745, rhs=v746 } -> x0 - v748 BinopI { op=and, lhs=v747, rhs_imm=127 } -> x0 - v749 Imm(16) -> x1 - v750 Extend { value=v748, kind=I32 } -> x0 - v751 Imm(0) -> x2 - v752 Extend { value=v749, kind=I32 } -> x1 - v753 Imm(0) -> x2 - v754 Binop { op=eq, lhs=v750, rhs=v752 } -> x0 - v755 BinopI { op=eq, lhs=v754, rhs_imm=0 } -> x0 - terminator Bz { cond=v755, target=b50, fall=b49 } (exit_acc=v755) - block 49 start_pc=0 - v756 Imm(25) -> x0 - terminator Return(v756) (exit_acc=v756) - block 50 start_pc=0 + v730 Imm(-65537) -> x0 + v731 Imm(65535) -> x0 + v732 Imm(32767) -> x0 + v733 Imm(21845) -> x0 + v734 Imm(43690) -> x0 + v735 Imm(8738) -> x0 + v736 Imm(10922) -> x0 + v737 Imm(8738) -> x0 + v738 Imm(17476) -> x0 + v739 Imm(1092) -> x0 + v740 Imm(18568) -> x0 + v741 Imm(2056) -> x0 + v742 Imm(8) -> x0 + v743 Imm(2064) -> x0 + v744 Imm(0) -> x0 + v745 Imm(2064) -> x0 + v746 Imm(0) -> x0 + v747 Imm(2064) -> x0 + v748 Imm(16) -> x0 + v749 Imm(16) -> x0 + v750 Imm(16) -> x0 + v751 Imm(0) -> x0 + v752 Imm(16) -> x0 + v753 Imm(0) -> x0 + v754 Imm(1) -> x0 + v755 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v755) + block 28 start_pc=0 v757 Imm(7) -> x0 - v758 Imm(3) -> x1 - v759 Imm(1) -> x2 - v760 Binop { op=sub, lhs=v757, rhs=v759 } -> x0 - v761 BinopI { op=and, lhs=v760, rhs_imm=3689348814741910323 } -> x2 - v762 BinopI { op=shru, lhs=v760, rhs_imm=2 } -> x0 - v763 BinopI { op=and, lhs=v762, rhs_imm=3689348814741910323 } -> x0 - v764 Binop { op=add, lhs=v761, rhs=v763 } -> x0 - v765 BinopI { op=shru, lhs=v764, rhs_imm=4 } -> x2 - v766 Binop { op=add, lhs=v764, rhs=v765 } -> x0 - v767 BinopI { op=and, lhs=v766, rhs_imm=1085102592571150095 } -> x0 - v768 BinopI { op=shru, lhs=v767, rhs_imm=8 } -> x2 - v769 Binop { op=add, lhs=v767, rhs=v768 } -> x0 - v770 BinopI { op=shru, lhs=v769, rhs_imm=16 } -> x2 - v771 Binop { op=add, lhs=v769, rhs=v770 } -> x0 - v772 BinopI { op=shru, lhs=v771, rhs_imm=32 } -> x2 - v773 Binop { op=add, lhs=v771, rhs=v772 } -> x0 - v774 BinopI { op=and, lhs=v773, rhs_imm=127 } -> x0 - v775 Extend { value=v774, kind=I32 } -> x0 - v776 Imm(0) -> x2 - v777 Extend { value=v758, kind=I32 } -> x1 - v778 Imm(0) -> x2 - v779 Binop { op=eq, lhs=v775, rhs=v777 } -> x0 - v780 BinopI { op=eq, lhs=v779, rhs_imm=0 } -> x0 - terminator Bz { cond=v780, target=b52, fall=b51 } (exit_acc=v780) - block 51 start_pc=0 - v781 Imm(26) -> x0 - terminator Return(v781) (exit_acc=v781) - block 52 start_pc=0 + v758 Imm(3) -> x0 + v759 Imm(1) -> x0 + v760 Imm(6) -> x0 + v761 Imm(2) -> x0 + v762 Imm(1) -> x0 + v763 Imm(1) -> x0 + v764 Imm(3) -> x0 + v765 Imm(0) -> x0 + v766 Imm(3) -> x0 + v767 Imm(3) -> x0 + v768 Imm(0) -> x0 + v769 Imm(3) -> x0 + v770 Imm(0) -> x0 + v771 Imm(3) -> x0 + v772 Imm(0) -> x0 + v773 Imm(3) -> x0 + v774 Imm(3) -> x0 + v775 Imm(3) -> x0 + v776 Imm(0) -> x0 + v777 Imm(3) -> x0 + v778 Imm(0) -> x0 + v779 Imm(1) -> x0 + v780 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v780) + block 29 start_pc=0 v782 Imm(252645135) -> x0 - v783 Imm(126322567) -> x1 - v784 Imm(84215045) -> x1 - v785 Binop { op=sub, lhs=v782, rhs=v784 } -> x0 - v786 BinopI { op=and, lhs=v785, rhs_imm=3689348814741910323 } -> x1 - v787 BinopI { op=shru, lhs=v785, rhs_imm=2 } -> x0 - v788 BinopI { op=and, lhs=v787, rhs_imm=3689348814741910323 } -> x0 - v789 Binop { op=add, lhs=v786, rhs=v788 } -> x0 - v790 BinopI { op=shru, lhs=v789, rhs_imm=4 } -> x1 - v791 Binop { op=add, lhs=v789, rhs=v790 } -> x0 - v792 BinopI { op=and, lhs=v791, rhs_imm=1085102592571150095 } -> x0 - v793 BinopI { op=shru, lhs=v792, rhs_imm=8 } -> x1 - v794 Binop { op=add, lhs=v792, rhs=v793 } -> x0 - v795 BinopI { op=shru, lhs=v794, rhs_imm=16 } -> x1 - v796 Binop { op=add, lhs=v794, rhs=v795 } -> x0 - v797 BinopI { op=shru, lhs=v796, rhs_imm=32 } -> x1 - v798 Binop { op=add, lhs=v796, rhs=v797 } -> x0 - v799 BinopI { op=and, lhs=v798, rhs_imm=127 } -> x0 - v800 Imm(16) -> x1 - v801 Extend { value=v799, kind=I32 } -> x0 - v802 Imm(0) -> x2 - v803 Extend { value=v800, kind=I32 } -> x1 - v804 Imm(0) -> x2 - v805 Binop { op=eq, lhs=v801, rhs=v803 } -> x0 - v806 BinopI { op=eq, lhs=v805, rhs_imm=0 } -> x0 - terminator Bz { cond=v806, target=b54, fall=b53 } (exit_acc=v806) - block 53 start_pc=0 - v807 Imm(27) -> x0 - terminator Return(v807) (exit_acc=v807) - block 54 start_pc=0 + v783 Imm(126322567) -> x0 + v784 Imm(84215045) -> x0 + v785 Imm(168430090) -> x0 + v786 Imm(33686018) -> x0 + v787 Imm(42107522) -> x0 + v788 Imm(33686018) -> x0 + v789 Imm(67372036) -> x0 + v790 Imm(4210752) -> x0 + v791 Imm(71582788) -> x0 + v792 Imm(67372036) -> x0 + v793 Imm(263172) -> x0 + v794 Imm(67635208) -> x0 + v795 Imm(1032) -> x0 + v796 Imm(67636240) -> x0 + v797 Imm(0) -> x0 + v798 Imm(67636240) -> x0 + v799 Imm(16) -> x0 + v800 Imm(16) -> x0 + v801 Imm(16) -> x0 + v802 Imm(0) -> x0 + v803 Imm(16) -> x0 + v804 Imm(0) -> x0 + v805 Imm(1) -> x0 + v806 Imm(0) -> x0 + terminator Jmp(b30) (exit_acc=v806) + block 30 start_pc=0 v808 Imm(16711935) -> x0 v809 StoreLocal { off=-2, value=v808, kind=I64, volatile } -> - v810 LoadLocal { off=-2, kind=I64, volatile } -> x0 @@ -955,16 +883,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v827 BinopI { op=and, lhs=v826, rhs_imm=127 } -> x0 v828 Imm(16) -> x1 v829 Extend { value=v827, kind=I32 } -> x0 - v830 Imm(0) -> x2 - v831 Extend { value=v828, kind=I32 } -> x1 - v832 Imm(0) -> x2 - v833 Binop { op=eq, lhs=v829, rhs=v831 } -> x0 + v830 Imm(0) -> x1 + v831 Imm(16) -> x1 + v832 Imm(0) -> x1 + v833 BinopI { op=eq, lhs=v829, rhs_imm=16 } -> x0 v834 BinopI { op=eq, lhs=v833, rhs_imm=0 } -> x0 - terminator Bz { cond=v834, target=b56, fall=b55 } (exit_acc=v834) - block 55 start_pc=0 + terminator Bz { cond=v834, target=b32, fall=b31 } (exit_acc=v834) + block 31 start_pc=0 v835 Imm(28) -> x0 terminator Return(v835) (exit_acc=v835) - block 56 start_pc=0 + block 32 start_pc=0 v836 LoadLocal { off=-2, kind=I64, volatile } -> x0 v837 BinopI { op=sub, lhs=v836, rhs_imm=1 } -> x1 v838 BinopI { op=xor, lhs=v836, rhs_imm=-1 } -> x0 @@ -988,18 +916,90 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v856 BinopI { op=and, lhs=v855, rhs_imm=127 } -> x0 v857 Imm(0) -> x1 v858 Extend { value=v856, kind=I32 } -> x0 - v859 Imm(0) -> x2 - v860 Extend { value=v857, kind=I32 } -> x1 - v861 Imm(0) -> x2 - v862 Binop { op=eq, lhs=v858, rhs=v860 } -> x0 + v859 Imm(0) -> x1 + v860 Imm(0) -> x1 + v861 Imm(0) -> x1 + v862 BinopI { op=eq, lhs=v858, rhs_imm=0 } -> x0 v863 BinopI { op=eq, lhs=v862, rhs_imm=0 } -> x0 - terminator Bz { cond=v863, target=b58, fall=b57 } (exit_acc=v863) - block 57 start_pc=0 + terminator Bz { cond=v863, target=b34, fall=b33 } (exit_acc=v863) + block 33 start_pc=0 v864 Imm(29) -> x0 terminator Return(v864) (exit_acc=v864) - block 58 start_pc=0 + block 34 start_pc=0 v865 Imm(0) -> x0 terminator Return(v865) (exit_acc=v865) + block 35 start_pc=0 + v37 Imm(1) -> x0 + terminator Return(v37) (exit_acc=v37) + block 36 start_pc=0 + v74 Imm(2) -> x0 + terminator Return(v74) (exit_acc=v74) + block 37 start_pc=0 + v111 Imm(3) -> x0 + terminator Return(v111) (exit_acc=v111) + block 38 start_pc=0 + v148 Imm(4) -> x0 + terminator Return(v148) (exit_acc=v148) + block 39 start_pc=0 + v175 Imm(5) -> x0 + terminator Return(v175) (exit_acc=v175) + block 40 start_pc=0 + v203 Imm(6) -> x0 + terminator Return(v203) (exit_acc=v203) + block 41 start_pc=0 + v231 Imm(7) -> x0 + terminator Return(v231) (exit_acc=v231) + block 42 start_pc=0 + v259 Imm(8) -> x0 + terminator Return(v259) (exit_acc=v259) + block 43 start_pc=0 + v280 Imm(9) -> x0 + terminator Return(v280) (exit_acc=v280) + block 44 start_pc=0 + v304 Imm(10) -> x0 + terminator Return(v304) (exit_acc=v304) + block 45 start_pc=0 + v328 Imm(11) -> x0 + terminator Return(v328) (exit_acc=v328) + block 46 start_pc=0 + v351 Imm(12) -> x0 + terminator Return(v351) (exit_acc=v351) + block 47 start_pc=0 + v391 Imm(13) -> x0 + terminator Return(v391) (exit_acc=v391) + block 48 start_pc=0 + v431 Imm(14) -> x0 + terminator Return(v431) (exit_acc=v431) + block 49 start_pc=0 + v471 Imm(15) -> x0 + terminator Return(v471) (exit_acc=v471) + block 50 start_pc=0 + v499 Imm(16) -> x0 + terminator Return(v499) (exit_acc=v499) + block 51 start_pc=0 + v527 Imm(17) -> x0 + terminator Return(v527) (exit_acc=v527) + block 52 start_pc=0 + v556 Imm(18) -> x0 + terminator Return(v556) (exit_acc=v556) + block 53 start_pc=0 + v582 Imm(19) -> x0 + terminator Return(v582) (exit_acc=v582) + block 54 start_pc=0 + v608 Imm(20) -> x0 + terminator Return(v608) (exit_acc=v608) + block 55 start_pc=0 + v727 Imm(24) -> x0 + terminator Return(v727) (exit_acc=v727) + block 56 start_pc=0 + v756 Imm(25) -> x0 + terminator Return(v756) (exit_acc=v756) + block 57 start_pc=0 + v781 Imm(26) -> x0 + terminator Return(v781) (exit_acc=v781) + block 58 start_pc=0 + v807 Imm(27) -> x0 + terminator Return(v807) (exit_acc=v807) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/builtin_bswap_expect.ssa b/tests/snapshots/ssa/builtin_bswap_expect.ssa index e093fa1ad..052dccf16 100644 --- a/tests/snapshots/ssa/builtin_bswap_expect.ssa +++ b/tests/snapshots/ssa/builtin_bswap_expect.ssa @@ -8,68 +8,59 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v1 Imm(258) -> x0 v2 Imm(2) -> x0 v3 Imm(512) -> x0 - v4 Imm(1) -> x1 - v5 Binop { op=or, lhs=v3, rhs=v4 } -> x0 - v6 BinopI { op=ne, lhs=v5, rhs_imm=513 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(1) -> x0 + v5 Imm(513) -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 Imm(16909060) -> x0 v9 Imm(4) -> x0 v10 Imm(67108864) -> x0 - v11 Imm(66051) -> x1 - v12 Imm(3) -> x1 - v13 Imm(196608) -> x1 - v14 Binop { op=or, lhs=v10, rhs=v13 } -> x0 - v15 Imm(258) -> x1 - v16 Imm(2) -> x1 - v17 Imm(512) -> x1 - v18 Binop { op=or, lhs=v14, rhs=v17 } -> x0 - v19 Imm(1) -> x1 - v20 Binop { op=or, lhs=v18, rhs=v19 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=67305985 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) - block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) - block 4 start_pc=0 + v11 Imm(66051) -> x0 + v12 Imm(3) -> x0 + v13 Imm(196608) -> x0 + v14 Imm(67305472) -> x0 + v15 Imm(258) -> x0 + v16 Imm(2) -> x0 + v17 Imm(512) -> x0 + v18 Imm(67305984) -> x0 + v19 Imm(1) -> x0 + v20 Imm(67305985) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 v23 Imm(72623859790382856) -> x0 v24 Imm(8) -> x0 v25 Imm(576460752303423488) -> x0 - v26 Imm(283686952306183) -> x1 - v27 Imm(7) -> x1 - v28 Imm(1970324836974592) -> x1 - v29 Binop { op=or, lhs=v25, rhs=v28 } -> x0 - v30 Imm(1108152157446) -> x1 - v31 Imm(6) -> x1 - v32 Imm(6597069766656) -> x1 - v33 Binop { op=or, lhs=v29, rhs=v32 } -> x0 - v34 Imm(4328719365) -> x1 - v35 Imm(5) -> x1 - v36 Imm(21474836480) -> x1 - v37 Binop { op=or, lhs=v33, rhs=v36 } -> x0 - v38 Imm(16909060) -> x1 - v39 Imm(4) -> x1 - v40 Imm(67108864) -> x1 - v41 Binop { op=or, lhs=v37, rhs=v40 } -> x0 - v42 Imm(66051) -> x1 - v43 Imm(3) -> x1 - v44 Imm(196608) -> x1 - v45 Binop { op=or, lhs=v41, rhs=v44 } -> x0 - v46 Imm(258) -> x1 - v47 Imm(2) -> x1 - v48 Imm(512) -> x1 - v49 Binop { op=or, lhs=v45, rhs=v48 } -> x0 - v50 Imm(1) -> x1 - v51 Binop { op=or, lhs=v49, rhs=v50 } -> x0 - v52 BinopI { op=ne, lhs=v51, rhs_imm=578437695752307201 } -> x0 - terminator Bz { cond=v52, target=b6, fall=b5 } (exit_acc=v52) - block 5 start_pc=0 - v53 Imm(3) -> x0 - terminator Return(v53) (exit_acc=v53) - block 6 start_pc=0 + v26 Imm(283686952306183) -> x0 + v27 Imm(7) -> x0 + v28 Imm(1970324836974592) -> x0 + v29 Imm(578431077140398080) -> x0 + v30 Imm(1108152157446) -> x0 + v31 Imm(6) -> x0 + v32 Imm(6597069766656) -> x0 + v33 Imm(578437674210164736) -> x0 + v34 Imm(4328719365) -> x0 + v35 Imm(5) -> x0 + v36 Imm(21474836480) -> x0 + v37 Imm(578437695685001216) -> x0 + v38 Imm(16909060) -> x0 + v39 Imm(4) -> x0 + v40 Imm(67108864) -> x0 + v41 Imm(578437695752110080) -> x0 + v42 Imm(66051) -> x0 + v43 Imm(3) -> x0 + v44 Imm(196608) -> x0 + v45 Imm(578437695752306688) -> x0 + v46 Imm(258) -> x0 + v47 Imm(2) -> x0 + v48 Imm(512) -> x0 + v49 Imm(578437695752307200) -> x0 + v50 Imm(1) -> x0 + v51 Imm(578437695752307201) -> x0 + v52 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v52) + block 3 start_pc=0 v54 Imm(2864434397) -> x0 v55 StoreLocal { off=-1, value=v54, kind=I32, volatile } -> - v56 LoadLocal { off=-1, kind=U32, volatile } -> x0 @@ -87,37 +78,46 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v68 BinopI { op=and, lhs=v67, rhs_imm=255 } -> x0 v69 Binop { op=or, lhs=v66, rhs=v68 } -> x0 v70 BinopI { op=ne, lhs=v69, rhs_imm=3721182122 } -> x0 - terminator Bz { cond=v70, target=b8, fall=b7 } (exit_acc=v70) - block 7 start_pc=0 + terminator Bz { cond=v70, target=b5, fall=b4 } (exit_acc=v70) + block 4 start_pc=0 v71 Imm(4) -> x0 terminator Return(v71) (exit_acc=v71) - block 8 start_pc=0 + block 5 start_pc=0 v72 Imm(5) -> x0 - v73 Imm(0) -> x1 - v74 LoadLocal { off=-2, kind=I32 } -> x1 - v75 BinopI { op=eq, lhs=v72, rhs_imm=5 } -> x1 - v76 BinopI { op=ne, lhs=v75, rhs_imm=1 } -> x1 - terminator Bz { cond=v76, target=b10, fall=b9 } (exit_acc=v76) + v73 Imm(0) -> x0 + v74 LoadLocal { off=-2, kind=I32 } -> x0 + v75 Imm(1) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v76) + block 6 start_pc=0 + v78 LoadLocal { off=-2, kind=I32 } -> x0 + v79 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v79) + block 7 start_pc=0 + v81 LoadLocal { off=-2, kind=I32 } -> x0 + v82 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v82) + block 8 start_pc=0 + v84 Imm(0) -> x0 + terminator Return(v84) (exit_acc=v84) block 9 start_pc=0 - v77 Imm(5) -> x0 - terminator Return(v77) (exit_acc=v77) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 10 start_pc=0 - v78 LoadLocal { off=-2, kind=I32 } -> x1 - v79 BinopI { op=ne, lhs=v72, rhs_imm=5 } -> x1 - terminator Bz { cond=v79, target=b12, fall=b11 } (exit_acc=v79) + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) block 11 start_pc=0 - v80 Imm(6) -> x0 - terminator Return(v80) (exit_acc=v80) + v53 Imm(3) -> x0 + terminator Return(v53) (exit_acc=v53) block 12 start_pc=0 - v81 LoadLocal { off=-2, kind=I32 } -> x1 - v82 BinopI { op=ne, lhs=v72, rhs_imm=5 } -> x0 - terminator Bz { cond=v82, target=b14, fall=b13 } (exit_acc=v82) + v77 Imm(5) -> x0 + terminator Return(v77) (exit_acc=v77) block 13 start_pc=0 - v83 Intrinsic { kind=10, args=[] } -> x0 - terminator Jmp(b14) (exit_acc=v83) + v80 Imm(6) -> x0 + terminator Return(v80) (exit_acc=v80) block 14 start_pc=0 - v84 Imm(0) -> x0 - terminator Return(v84) (exit_acc=v84) + v83 Intrinsic { kind=10, args=[] } -> x0 + terminator Jmp(b8) (exit_acc=v83) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/c11_atomic_specifier.ssa b/tests/snapshots/ssa/c11_atomic_specifier.ssa index 8bcb10c36..76b48e4b9 100644 --- a/tests/snapshots/ssa/c11_atomic_specifier.ssa +++ b/tests/snapshots/ssa/c11_atomic_specifier.ssa @@ -7,43 +7,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v1 Imm(200) -> x0 v2 StoreLocal { off=-1, value=v1, kind=I8 } -> - v3 Imm(40000) -> x0 - v4 Imm(0) -> x1 - v5 Imm(287454020) -> x1 - v6 Imm(0) -> x2 - v7 Imm(1234605616436508552) -> x2 - v8 Imm(0) -> x6 - v9 LoadLocal { off=-1, kind=U8 } -> x6 - v10 BinopI { op=xor, lhs=v9, rhs_imm=200 } -> x6 - v11 BinopI { op=and, lhs=v10, rhs_imm=4294967295 } -> x6 - v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x6 + v4 Imm(0) -> x0 + v5 Imm(287454020) -> x0 + v6 Imm(0) -> x0 + v7 Imm(1234605616436508552) -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=U8 } -> x0 + v10 BinopI { op=xor, lhs=v9, rhs_imm=200 } -> x0 + v11 BinopI { op=and, lhs=v10, rhs_imm=4294967295 } -> x0 + v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 Imm(1) -> x0 terminator Return(v13) (exit_acc=v13) block 2 start_pc=0 - v14 LoadLocal { off=-2, kind=U16 } -> x6 - v15 BinopI { op=xor, lhs=v3, rhs_imm=40000 } -> x0 - v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=0 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) + v14 LoadLocal { off=-2, kind=U16 } -> x0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v17) block 3 start_pc=0 - v18 Imm(2) -> x0 - terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 v19 LoadLocal { off=-3, kind=U32 } -> x0 - v20 BinopI { op=ne, lhs=v5, rhs_imm=287454020 } -> x0 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) - block 5 start_pc=0 - v21 Imm(3) -> x0 - terminator Return(v21) (exit_acc=v21) - block 6 start_pc=0 + v20 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v20) + block 4 start_pc=0 v22 LoadLocal { off=-4, kind=I64 } -> x0 - v23 BinopI { op=ne, lhs=v7, rhs_imm=1234605616436508552 } -> x0 - terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) - block 7 start_pc=0 - v24 Imm(4) -> x0 - terminator Return(v24) (exit_acc=v24) - block 8 start_pc=0 + v23 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v23) + block 5 start_pc=0 v25 LocalAddr(-1) -> x0 v26 Imm(0) -> x1 v27 LoadLocal { off=-5, kind=I64 } -> x1 @@ -51,11 +42,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v29 BinopI { op=xor, lhs=v28, rhs_imm=200 } -> x1 v30 BinopI { op=and, lhs=v29, rhs_imm=4294967295 } -> x1 v31 BinopI { op=ne, lhs=v30, rhs_imm=0 } -> x1 - terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) - block 9 start_pc=0 + terminator Bz { cond=v31, target=b7, fall=b6 } (exit_acc=v31) + block 6 start_pc=0 v32 Imm(5) -> x0 terminator Return(v32) (exit_acc=v32) - block 10 start_pc=0 + block 7 start_pc=0 v33 LoadLocal { off=-5, kind=I64 } -> x1 v34 Imm(250) -> x1 v35 Store { addr=v25, disp=0, value=v34, kind=I8 } -> - @@ -63,38 +54,35 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v37 BinopI { op=xor, lhs=v36, rhs_imm=250 } -> x0 v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x0 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) - block 11 start_pc=0 + terminator Bz { cond=v39, target=b9, fall=b8 } (exit_acc=v39) + block 8 start_pc=0 v40 Imm(6) -> x0 terminator Return(v40) (exit_acc=v40) - block 12 start_pc=0 + block 9 start_pc=0 v41 Imm(-7) -> x0 v42 StoreLocal { off=-6, value=v41, kind=I32 } -> - v43 Imm(99) -> x0 - v44 Imm(0) -> x1 - v45 Imm(13) -> x1 + v44 Imm(0) -> x0 + v45 Imm(13) -> x0 v46 StoreLocal { off=-8, value=v45, kind=I16, volatile } -> - - v47 LoadLocal { off=-6, kind=I32 } -> x1 - v48 BinopI { op=ne, lhs=v47, rhs_imm=-7 } -> x1 - terminator Bz { cond=v48, target=b14, fall=b13 } (exit_acc=v48) - block 13 start_pc=0 + v47 LoadLocal { off=-6, kind=I32 } -> x0 + v48 BinopI { op=ne, lhs=v47, rhs_imm=-7 } -> x0 + terminator Bz { cond=v48, target=b11, fall=b10 } (exit_acc=v48) + block 10 start_pc=0 v49 Imm(7) -> x0 terminator Return(v49) (exit_acc=v49) - block 14 start_pc=0 - v50 LoadLocal { off=-7, kind=I64 } -> x1 - v51 BinopI { op=ne, lhs=v43, rhs_imm=99 } -> x0 - terminator Bz { cond=v51, target=b16, fall=b15 } (exit_acc=v51) - block 15 start_pc=0 - v52 Imm(8) -> x0 - terminator Return(v52) (exit_acc=v52) - block 16 start_pc=0 + block 11 start_pc=0 + v50 LoadLocal { off=-7, kind=I64 } -> x0 + v51 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v51) + block 12 start_pc=0 v53 LoadLocal { off=-8, kind=I16, volatile } -> x0 v54 BinopI { op=ne, lhs=v53, rhs_imm=13 } -> x0 - terminator Bz { cond=v54, target=b18, fall=b17 } (exit_acc=v54) - block 17 start_pc=0 + terminator Bz { cond=v54, target=b14, fall=b13 } (exit_acc=v54) + block 13 start_pc=0 v55 Imm(9) -> x0 terminator Return(v55) (exit_acc=v55) - block 18 start_pc=0 + block 14 start_pc=0 v56 LocalAddr(-6) -> x0 v57 Imm(0) -> x1 v58 LoadLocal { off=-9, kind=I64 } -> x1 @@ -102,13 +90,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v60 Store { addr=v56, disp=0, value=v59, kind=I32 } -> - v61 LoadLocal { off=-6, kind=I32 } -> x0 v62 BinopI { op=ne, lhs=v61, rhs_imm=21 } -> x0 - terminator Bz { cond=v62, target=b20, fall=b19 } (exit_acc=v62) - block 19 start_pc=0 + terminator Bz { cond=v62, target=b16, fall=b15 } (exit_acc=v62) + block 15 start_pc=0 v63 Imm(10) -> x0 terminator Return(v63) (exit_acc=v63) - block 20 start_pc=0 + block 16 start_pc=0 v64 Imm(0) -> x0 terminator Return(v64) (exit_acc=v64) + block 17 start_pc=0 + v18 Imm(2) -> x0 + terminator Return(v18) (exit_acc=v18) + block 18 start_pc=0 + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) + block 19 start_pc=0 + v24 Imm(4) -> x0 + terminator Return(v24) (exit_acc=v24) + block 20 start_pc=0 + v52 Imm(8) -> x0 + terminator Return(v52) (exit_acc=v52) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/c4.ssa b/tests/snapshots/ssa/c4.ssa index ac7b93bcd..d5a1f48a6 100644 --- a/tests/snapshots/ssa/c4.ssa +++ b/tests/snapshots/ssa/c4.ssa @@ -1,18 +1,11 @@ ; --- SSA dump (ok=true) ent_pc=6 --- ; name=next fn ent_pc=6 n_params=0 variadic=false locals=39 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - terminator Jmp(b1) (exit_acc=v0) + terminator Jmp(b82) (exit_acc=v0) block 1 start_pc=0 - v1 ImmData(1832) -> x0 - v2 ImmData(1776) -> x1 - v3 Load { addr=v2, disp=0, kind=I64 } -> x1 - v4 Load { addr=v3, disp=0, kind=I8 } -> x1 - v5 Store { addr=v1, disp=0, value=v4, kind=I64 } -> - - terminator Bz { cond=v4, target=b3, fall=b2 } (exit_acc=v4) - block 2 start_pc=0 v6 ImmData(1776) -> x0 v7 Load { addr=v6, disp=0, kind=I64 } -> x1 v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 @@ -20,22 +13,12 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v10 ImmData(1832) -> x0 v11 Load { addr=v10, disp=0, kind=I64 } -> x0 v12 BinopI { op=eq, lhs=v11, rhs_imm=10 } -> x0 - terminator Bz { cond=v12, target=b6, fall=b4 } (exit_acc=v12) - block 3 start_pc=0 - v13 Imm(0) -> x0 - terminator Return(v13) (exit_acc=v13) - block 4 start_pc=0 + terminator Bz { cond=v12, target=b8, fall=b2 } (exit_acc=v12) + block 2 start_pc=0 v14 ImmData(1872) -> x0 v15 Load { addr=v14, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) - block 5 start_pc=0 - terminator Jmp(b1) - block 6 start_pc=0 - v16 ImmData(1832) -> x0 - v17 Load { addr=v16, disp=0, kind=I64 } -> x0 - v18 BinopI { op=eq, lhs=v17, rhs_imm=35 } -> x0 - terminator Bz { cond=v18, target=b17, fall=b15 } (exit_acc=v18) - block 7 start_pc=0 + terminator Bz { cond=v15, target=b81, fall=b3 } (exit_acc=v15) + block 3 start_pc=0 v19 ImmData(32) -> x7 v20 ImmData(1864) -> x0 v21 Load { addr=v20, disp=0, kind=I64 } -> x6 @@ -48,21 +31,8 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v28 CallExt { binding_idx=0, args=[v19, v21, v26, v25], fp_arg_mask=0x0 } -> x0 v29 Load { addr=v22, disp=0, kind=I64 } -> x0 v30 Store { addr=v24, disp=0, value=v29, kind=I64 } -> - - terminator Jmp(b9) (exit_acc=v30) - block 8 start_pc=0 - v31 ImmData(1864) -> x0 - v32 Load { addr=v31, disp=0, kind=I64 } -> x1 - v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x1 - v34 Store { addr=v31, disp=0, value=v33, kind=I64 } -> - - terminator Jmp(b5) (exit_acc=v34) - block 9 start_pc=0 - v35 ImmData(1808) -> x0 - v36 Load { addr=v35, disp=0, kind=I64 } -> x0 - v37 ImmData(1800) -> x1 - v38 Load { addr=v37, disp=0, kind=I64 } -> x1 - v39 Binop { op=lt, lhs=v36, rhs=v38 } -> x0 - terminator Bz { cond=v39, target=b11, fall=b10 } (exit_acc=v39) - block 10 start_pc=0 + terminator Jmp(b7) (exit_acc=v30) + block 4 start_pc=0 v40 ImmData(41) -> x7 v41 ImmData(47) -> x0 v42 ImmData(1808) -> x3 @@ -76,10 +46,8 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v50 Load { addr=v42, disp=0, kind=I64 } -> x0 v51 Load { addr=v50, disp=0, kind=I64 } -> x0 v52 BinopI { op=le, lhs=v51, rhs_imm=7 } -> x0 - terminator Bz { cond=v52, target=b14, fall=b12 } (exit_acc=v52) - block 11 start_pc=0 - terminator Jmp(b8) - block 12 start_pc=0 + terminator Bz { cond=v52, target=b6, fall=b5 } (exit_acc=v52) + block 5 start_pc=0 v53 ImmData(243) -> x7 v54 ImmData(1808) -> x0 v55 Load { addr=v54, disp=0, kind=I64 } -> x1 @@ -87,646 +55,673 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v57 Store { addr=v54, disp=0, value=v56, kind=I64 } -> - v58 Load { addr=v56, disp=0, kind=I64 } -> x6 v59 CallExt { binding_idx=0, args=[v53, v58], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b13) (exit_acc=v59) - block 13 start_pc=0 - terminator Jmp(b9) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v59) + block 6 start_pc=0 v60 ImmData(248) -> x7 v61 CallExt { binding_idx=0, args=[v60], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b13) (exit_acc=v61) - block 15 start_pc=0 - terminator Jmp(b18) - block 16 start_pc=0 - terminator Jmp(b5) - block 17 start_pc=0 - v62 ImmData(1832) -> x0 - v63 Load { addr=v62, disp=0, kind=I64 } -> x0 - v64 BinopI { op=ge, lhs=v63, rhs_imm=97 } -> x0 - v65 Imm(0) -> x3 - v66 Imm(0) -> x1 - terminator Bz { cond=v64, target=b213, fall=b23 } (exit_acc=v64) - block 18 start_pc=0 + terminator Jmp(b7) (exit_acc=v61) + block 7 start_pc=0 + v35 ImmData(1808) -> x0 + v36 Load { addr=v35, disp=0, kind=I64 } -> x0 + v37 ImmData(1800) -> x1 + v38 Load { addr=v37, disp=0, kind=I64 } -> x1 + v39 Binop { op=lt, lhs=v36, rhs=v38 } -> x0 + terminator Bz { cond=v39, target=b81, fall=b4 } (exit_acc=v39) + block 8 start_pc=0 + v16 ImmData(1832) -> x0 + v17 Load { addr=v16, disp=0, kind=I64 } -> x0 + v18 BinopI { op=eq, lhs=v17, rhs_imm=35 } -> x0 + terminator Bz { cond=v18, target=b14, fall=b9 } (exit_acc=v18) + block 9 start_pc=0 v67 ImmData(1776) -> x0 v68 Load { addr=v67, disp=0, kind=I64 } -> x0 v69 Load { addr=v68, disp=0, kind=I8 } -> x0 - v70 BinopI { op=ne, lhs=v69, rhs_imm=0 } -> x3 + v70 BinopI { op=ne, lhs=v69, rhs_imm=0 } -> x1 v71 Imm(0) -> x0 - terminator Bz { cond=v70, target=b214, fall=b21 } (exit_acc=v70) - block 19 start_pc=0 - v72 ImmData(1776) -> x0 - v73 Load { addr=v72, disp=0, kind=I64 } -> x1 - v74 BinopI { op=add, lhs=v73, rhs_imm=1 } -> x1 - v75 Store { addr=v72, disp=0, value=v74, kind=I64 } -> - - terminator Jmp(b18) (exit_acc=v75) - block 20 start_pc=0 - terminator Jmp(b16) - block 21 start_pc=0 + terminator Bz { cond=v70, target=b13, fall=b10 } (exit_acc=v70) + block 10 start_pc=0 v76 ImmData(1776) -> x0 v77 Load { addr=v76, disp=0, kind=I64 } -> x0 v78 Load { addr=v77, disp=0, kind=I8 } -> x0 - v79 BinopI { op=ne, lhs=v78, rhs_imm=10 } -> x3 + v79 BinopI { op=ne, lhs=v78, rhs_imm=10 } -> x1 v80 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v79) - block 22 start_pc=0 - v81 Phi { incoming=[b214:v70, b21:v79], kind=I64 } -> x3 + terminator Jmp(b11) (exit_acc=v79) + block 11 start_pc=0 + v81 Phi { incoming=[b13:v70, b10:v79], kind=I64 } -> x1 v82 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v81, target=b20, fall=b19 } (exit_acc=v81) - block 23 start_pc=0 + terminator Bz { cond=v81, target=b82, fall=b12 } (exit_acc=v81) + block 12 start_pc=0 + v72 ImmData(1776) -> x0 + v73 Load { addr=v72, disp=0, kind=I64 } -> x1 + v74 BinopI { op=add, lhs=v73, rhs_imm=1 } -> x1 + v75 Store { addr=v72, disp=0, value=v74, kind=I64 } -> - + terminator Jmp(b9) (exit_acc=v75) + block 13 start_pc=0 + terminator Jmp(b11) + block 14 start_pc=0 + v62 ImmData(1832) -> x0 + v63 Load { addr=v62, disp=0, kind=I64 } -> x0 + v64 BinopI { op=ge, lhs=v63, rhs_imm=97 } -> x0 + v65 Imm(0) -> x2 + v66 Imm(0) -> x1 + terminator Bz { cond=v64, target=b80, fall=b15 } (exit_acc=v64) + block 15 start_pc=0 v83 ImmData(1832) -> x0 v84 Load { addr=v83, disp=0, kind=I64 } -> x0 v85 BinopI { op=le, lhs=v84, rhs_imm=122 } -> x0 - v86 BinopI { op=ne, lhs=v85, rhs_imm=0 } -> x3 + v86 BinopI { op=ne, lhs=v85, rhs_imm=0 } -> x2 v87 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v86) - block 24 start_pc=0 - v88 Phi { incoming=[b213:v65, b23:v86], kind=I64 } -> x3 + terminator Jmp(b16) (exit_acc=v86) + block 16 start_pc=0 + v88 Phi { incoming=[b80:v65, b15:v86], kind=I64 } -> x2 v89 LoadLocal { off=-9, kind=I64 } -> x0 - v90 Imm(1) -> x12 + v90 Imm(1) -> x1 v91 Imm(0) -> x0 - terminator Bnz { cond=v88, target=b215, fall=b25 } (exit_acc=v88) - block 25 start_pc=0 + terminator Bnz { cond=v88, target=b79, fall=b17 } (exit_acc=v88) + block 17 start_pc=0 v92 ImmData(1832) -> x0 v93 Load { addr=v92, disp=0, kind=I64 } -> x0 v94 BinopI { op=ge, lhs=v93, rhs_imm=65 } -> x0 - v95 Imm(0) -> x3 + v95 Imm(0) -> x2 v96 Imm(0) -> x1 - terminator Bz { cond=v94, target=b216, fall=b27 } (exit_acc=v94) - block 26 start_pc=0 - v97 Phi { incoming=[b215:v90, b28:v107], kind=I64 } -> x12 - v98 LoadLocal { off=-8, kind=I64 } -> x0 - v99 Imm(0) -> x0 - terminator Bnz { cond=v97, target=b217, fall=b29 } (exit_acc=v97) - block 27 start_pc=0 + terminator Bz { cond=v94, target=b78, fall=b18 } (exit_acc=v94) + block 18 start_pc=0 v100 ImmData(1832) -> x0 v101 Load { addr=v100, disp=0, kind=I64 } -> x0 v102 BinopI { op=le, lhs=v101, rhs_imm=90 } -> x0 - v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x3 + v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x2 v104 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v103) - block 28 start_pc=0 - v105 Phi { incoming=[b216:v95, b27:v103], kind=I64 } -> x3 + terminator Jmp(b19) (exit_acc=v103) + block 19 start_pc=0 + v105 Phi { incoming=[b78:v95, b18:v103], kind=I64 } -> x2 v106 LoadLocal { off=-10, kind=I64 } -> x0 - v107 BinopI { op=ne, lhs=v105, rhs_imm=0 } -> x12 + v107 BinopI { op=ne, lhs=v105, rhs_imm=0 } -> x1 v108 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v107) - block 29 start_pc=0 + terminator Jmp(b20) (exit_acc=v107) + block 20 start_pc=0 + v97 Phi { incoming=[b79:v90, b19:v107], kind=I64 } -> x1 + v98 LoadLocal { off=-8, kind=I64 } -> x0 + v99 Imm(0) -> x0 + terminator Bnz { cond=v97, target=b77, fall=b21 } (exit_acc=v97) + block 21 start_pc=0 v109 ImmData(1832) -> x0 v110 Load { addr=v109, disp=0, kind=I64 } -> x0 - v111 BinopI { op=eq, lhs=v110, rhs_imm=95 } -> x12 + v111 BinopI { op=eq, lhs=v110, rhs_imm=95 } -> x1 v112 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v111) - block 30 start_pc=0 - v113 Phi { incoming=[b217:v97, b29:v111], kind=I64 } -> x12 + terminator Jmp(b22) (exit_acc=v111) + block 22 start_pc=0 + v113 Phi { incoming=[b77:v97, b21:v111], kind=I64 } -> x1 v114 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v113, target=b33, fall=b31 } (exit_acc=v113) - block 31 start_pc=0 - v115 ImmData(1776) -> x0 - v116 Load { addr=v115, disp=0, kind=I64 } -> x0 - v117 BinopI { op=sub, lhs=v116, rhs_imm=1 } -> x3 - v118 Imm(0) -> x0 - terminator Jmp(b34) (exit_acc=v117) - block 32 start_pc=0 - terminator Jmp(b16) - block 33 start_pc=0 + terminator Bnz { cond=v113, target=b179, fall=b23 } (exit_acc=v113) + block 23 start_pc=0 v119 ImmData(1832) -> x0 v120 Load { addr=v119, disp=0, kind=I64 } -> x0 v121 BinopI { op=ge, lhs=v120, rhs_imm=48 } -> x1 v122 Imm(0) -> x0 - terminator Bz { cond=v121, target=b218, fall=b56 } (exit_acc=v121) + terminator Bz { cond=v121, target=b76, fall=b24 } (exit_acc=v121) + block 24 start_pc=0 + v263 ImmData(1832) -> x0 + v264 Load { addr=v263, disp=0, kind=I64 } -> x0 + v265 BinopI { op=le, lhs=v264, rhs_imm=57 } -> x1 + v266 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v265) + block 25 start_pc=0 + v267 Phi { incoming=[b76:v121, b24:v265], kind=I64 } -> x1 + v268 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bnz { cond=v267, target=b140, fall=b26 } (exit_acc=v267) + block 26 start_pc=0 + v274 ImmData(1832) -> x0 + v275 Load { addr=v274, disp=0, kind=I64 } -> x0 + v276 BinopI { op=eq, lhs=v275, rhs_imm=47 } -> x0 + terminator Bz { cond=v276, target=b34, fall=b27 } (exit_acc=v276) + block 27 start_pc=0 + v415 ImmData(1776) -> x0 + v416 Load { addr=v415, disp=0, kind=I64 } -> x0 + v417 Load { addr=v416, disp=0, kind=I8 } -> x0 + v418 BinopI { op=eq, lhs=v417, rhs_imm=47 } -> x0 + terminator Bz { cond=v418, target=b139, fall=b28 } (exit_acc=v418) + block 28 start_pc=0 + v423 ImmData(1776) -> x0 + v424 Load { addr=v423, disp=0, kind=I64 } -> x1 + v425 BinopI { op=add, lhs=v424, rhs_imm=1 } -> x1 + v426 Store { addr=v423, disp=0, value=v425, kind=I64 } -> - + terminator Jmp(b29) (exit_acc=v426) + block 29 start_pc=0 + v431 ImmData(1776) -> x0 + v432 Load { addr=v431, disp=0, kind=I64 } -> x0 + v433 Load { addr=v432, disp=0, kind=I8 } -> x0 + v434 BinopI { op=ne, lhs=v433, rhs_imm=0 } -> x1 + v435 Imm(0) -> x0 + terminator Bz { cond=v434, target=b33, fall=b30 } (exit_acc=v434) + block 30 start_pc=0 + v440 ImmData(1776) -> x0 + v441 Load { addr=v440, disp=0, kind=I64 } -> x0 + v442 Load { addr=v441, disp=0, kind=I8 } -> x0 + v443 BinopI { op=ne, lhs=v442, rhs_imm=10 } -> x1 + v444 Imm(0) -> x0 + terminator Jmp(b31) (exit_acc=v443) + block 31 start_pc=0 + v445 Phi { incoming=[b33:v434, b30:v443], kind=I64 } -> x1 + v446 LoadLocal { off=-29, kind=I64 } -> x0 + terminator Bz { cond=v445, target=b82, fall=b32 } (exit_acc=v445) + block 32 start_pc=0 + v436 ImmData(1776) -> x0 + v437 Load { addr=v436, disp=0, kind=I64 } -> x1 + v438 BinopI { op=add, lhs=v437, rhs_imm=1 } -> x1 + v439 Store { addr=v436, disp=0, value=v438, kind=I64 } -> - + terminator Jmp(b29) (exit_acc=v439) + block 33 start_pc=0 + terminator Jmp(b31) block 34 start_pc=0 - v123 ImmData(1776) -> x0 - v124 Load { addr=v123, disp=0, kind=I64 } -> x0 - v125 Load { addr=v124, disp=0, kind=I8 } -> x0 - v126 BinopI { op=ge, lhs=v125, rhs_imm=97 } -> x0 - v127 Imm(0) -> x12 - v128 Imm(0) -> x1 - terminator Bz { cond=v126, target=b219, fall=b37 } (exit_acc=v126) + v419 ImmData(1832) -> x0 + v420 Load { addr=v419, disp=0, kind=I64 } -> x0 + v421 BinopI { op=eq, lhs=v420, rhs_imm=39 } -> x1 + v422 Imm(0) -> x0 + terminator Bnz { cond=v421, target=b75, fall=b35 } (exit_acc=v421) block 35 start_pc=0 - v129 ImmData(1832) -> x0 - v130 Load { addr=v129, disp=0, kind=I64 } -> x1 - v131 BinopI { op=mul, lhs=v130, rhs_imm=147 } -> x1 - v132 ImmData(1776) -> x2 - v133 Load { addr=v132, disp=0, kind=I64 } -> x6 - v134 BinopI { op=add, lhs=v133, rhs_imm=1 } -> x7 - v135 Store { addr=v132, disp=0, value=v134, kind=I64 } -> - - v136 Load { addr=v133, disp=0, kind=I8 } -> x2 - v137 Binop { op=add, lhs=v131, rhs=v136 } -> x1 - v138 Store { addr=v129, disp=0, value=v137, kind=I64 } -> - - terminator Jmp(b34) (exit_acc=v138) + v447 ImmData(1832) -> x0 + v448 Load { addr=v447, disp=0, kind=I64 } -> x0 + v449 BinopI { op=eq, lhs=v448, rhs_imm=34 } -> x1 + v450 Imm(0) -> x0 + terminator Jmp(b36) (exit_acc=v449) block 36 start_pc=0 - v139 ImmData(1832) -> x0 - v140 Load { addr=v139, disp=0, kind=I64 } -> x1 - v141 BinopI { op=shl, lhs=v140, rhs_imm=6 } -> x1 - v142 ImmData(1776) -> x2 - v143 Load { addr=v142, disp=0, kind=I64 } -> x2 - v144 LoadLocal { off=-1, kind=I64 } -> x6 - v145 Binop { op=sub, lhs=v143, rhs=v117 } -> x2 - v146 Binop { op=add, lhs=v141, rhs=v145 } -> x1 - v147 Store { addr=v139, disp=0, value=v146, kind=I64 } -> - - v148 ImmData(1816) -> x0 - v149 ImmData(1824) -> x1 - v150 Load { addr=v149, disp=0, kind=I64 } -> x1 - v151 Store { addr=v148, disp=0, value=v150, kind=I64 } -> - - terminator Jmp(b49) (exit_acc=v151) + v451 Phi { incoming=[b75:v421, b35:v449], kind=I64 } -> x1 + v452 LoadLocal { off=-30, kind=I64 } -> x0 + terminator Bnz { cond=v451, target=b125, fall=b37 } (exit_acc=v451) block 37 start_pc=0 - v152 ImmData(1776) -> x0 - v153 Load { addr=v152, disp=0, kind=I64 } -> x0 - v154 Load { addr=v153, disp=0, kind=I8 } -> x0 - v155 BinopI { op=le, lhs=v154, rhs_imm=122 } -> x0 - v156 BinopI { op=ne, lhs=v155, rhs_imm=0 } -> x12 - v157 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v156) + v456 ImmData(1832) -> x0 + v457 Load { addr=v456, disp=0, kind=I64 } -> x0 + v458 BinopI { op=eq, lhs=v457, rhs_imm=61 } -> x0 + terminator Bnz { cond=v458, target=b121, fall=b38 } (exit_acc=v458) block 38 start_pc=0 - v158 Phi { incoming=[b219:v127, b37:v156], kind=I64 } -> x12 - v159 LoadLocal { off=-14, kind=I64 } -> x0 - v160 Imm(1) -> x13 - v161 Imm(0) -> x0 - terminator Bnz { cond=v158, target=b220, fall=b39 } (exit_acc=v158) + v522 ImmData(1832) -> x0 + v523 Load { addr=v522, disp=0, kind=I64 } -> x0 + v524 BinopI { op=eq, lhs=v523, rhs_imm=43 } -> x0 + terminator Bnz { cond=v524, target=b117, fall=b39 } (exit_acc=v524) block 39 start_pc=0 - v162 ImmData(1776) -> x0 - v163 Load { addr=v162, disp=0, kind=I64 } -> x0 - v164 Load { addr=v163, disp=0, kind=I8 } -> x0 - v165 BinopI { op=ge, lhs=v164, rhs_imm=65 } -> x0 - v166 Imm(0) -> x12 - v167 Imm(0) -> x1 - terminator Bz { cond=v165, target=b221, fall=b41 } (exit_acc=v165) + v540 ImmData(1832) -> x0 + v541 Load { addr=v540, disp=0, kind=I64 } -> x0 + v542 BinopI { op=eq, lhs=v541, rhs_imm=45 } -> x0 + terminator Bnz { cond=v542, target=b113, fall=b40 } (exit_acc=v542) block 40 start_pc=0 - v168 Phi { incoming=[b220:v160, b42:v180], kind=I64 } -> x13 - v169 LoadLocal { off=-13, kind=I64 } -> x0 - v170 Imm(1) -> x12 - v171 Imm(0) -> x0 - terminator Bnz { cond=v168, target=b222, fall=b43 } (exit_acc=v168) + v558 ImmData(1832) -> x0 + v559 Load { addr=v558, disp=0, kind=I64 } -> x0 + v560 BinopI { op=eq, lhs=v559, rhs_imm=33 } -> x0 + terminator Bnz { cond=v560, target=b110, fall=b41 } (exit_acc=v560) block 41 start_pc=0 - v172 ImmData(1776) -> x0 - v173 Load { addr=v172, disp=0, kind=I64 } -> x0 - v174 Load { addr=v173, disp=0, kind=I8 } -> x0 - v175 BinopI { op=le, lhs=v174, rhs_imm=90 } -> x0 - v176 BinopI { op=ne, lhs=v175, rhs_imm=0 } -> x12 - v177 Imm(0) -> x0 - terminator Jmp(b42) (exit_acc=v176) + v576 ImmData(1832) -> x0 + v577 Load { addr=v576, disp=0, kind=I64 } -> x0 + v578 BinopI { op=eq, lhs=v577, rhs_imm=60 } -> x0 + terminator Bnz { cond=v578, target=b104, fall=b42 } (exit_acc=v578) block 42 start_pc=0 - v178 Phi { incoming=[b221:v166, b41:v176], kind=I64 } -> x12 - v179 LoadLocal { off=-15, kind=I64 } -> x0 - v180 BinopI { op=ne, lhs=v178, rhs_imm=0 } -> x13 - v181 Imm(0) -> x0 - terminator Jmp(b40) (exit_acc=v180) + v591 ImmData(1832) -> x0 + v592 Load { addr=v591, disp=0, kind=I64 } -> x0 + v593 BinopI { op=eq, lhs=v592, rhs_imm=62 } -> x0 + terminator Bnz { cond=v593, target=b98, fall=b43 } (exit_acc=v593) block 43 start_pc=0 - v182 ImmData(1776) -> x0 - v183 Load { addr=v182, disp=0, kind=I64 } -> x0 - v184 Load { addr=v183, disp=0, kind=I8 } -> x0 - v185 BinopI { op=ge, lhs=v184, rhs_imm=48 } -> x0 - v186 Imm(0) -> x12 - v187 Imm(0) -> x1 - terminator Bz { cond=v185, target=b223, fall=b45 } (exit_acc=v185) + v620 ImmData(1832) -> x0 + v621 Load { addr=v620, disp=0, kind=I64 } -> x0 + v622 BinopI { op=eq, lhs=v621, rhs_imm=124 } -> x0 + terminator Bnz { cond=v622, target=b94, fall=b44 } (exit_acc=v622) block 44 start_pc=0 - v188 Phi { incoming=[b222:v170, b46:v199], kind=I64 } -> x12 - v189 LoadLocal { off=-12, kind=I64 } -> x0 - v190 Imm(0) -> x0 - terminator Bnz { cond=v188, target=b224, fall=b47 } (exit_acc=v188) + v649 ImmData(1832) -> x0 + v650 Load { addr=v649, disp=0, kind=I64 } -> x0 + v651 BinopI { op=eq, lhs=v650, rhs_imm=38 } -> x0 + terminator Bnz { cond=v651, target=b90, fall=b45 } (exit_acc=v651) block 45 start_pc=0 - v191 ImmData(1776) -> x0 - v192 Load { addr=v191, disp=0, kind=I64 } -> x0 - v193 Load { addr=v192, disp=0, kind=I8 } -> x0 - v194 BinopI { op=le, lhs=v193, rhs_imm=57 } -> x0 - v195 BinopI { op=ne, lhs=v194, rhs_imm=0 } -> x12 - v196 Imm(0) -> x0 - terminator Jmp(b46) (exit_acc=v195) + v667 ImmData(1832) -> x0 + v668 Load { addr=v667, disp=0, kind=I64 } -> x0 + v669 BinopI { op=eq, lhs=v668, rhs_imm=94 } -> x0 + terminator Bnz { cond=v669, target=b89, fall=b46 } (exit_acc=v669) block 46 start_pc=0 - v197 Phi { incoming=[b223:v186, b45:v195], kind=I64 } -> x12 - v198 LoadLocal { off=-16, kind=I64 } -> x0 - v199 BinopI { op=ne, lhs=v197, rhs_imm=0 } -> x12 - v200 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v199) + v685 ImmData(1832) -> x0 + v686 Load { addr=v685, disp=0, kind=I64 } -> x0 + v687 BinopI { op=eq, lhs=v686, rhs_imm=37 } -> x0 + terminator Bnz { cond=v687, target=b88, fall=b47 } (exit_acc=v687) block 47 start_pc=0 - v201 ImmData(1776) -> x0 - v202 Load { addr=v201, disp=0, kind=I64 } -> x0 - v203 Load { addr=v202, disp=0, kind=I8 } -> x0 - v204 BinopI { op=eq, lhs=v203, rhs_imm=95 } -> x12 - v205 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v204) + v692 ImmData(1832) -> x0 + v693 Load { addr=v692, disp=0, kind=I64 } -> x0 + v694 BinopI { op=eq, lhs=v693, rhs_imm=42 } -> x0 + terminator Bnz { cond=v694, target=b87, fall=b48 } (exit_acc=v694) block 48 start_pc=0 - v206 Phi { incoming=[b224:v188, b47:v204], kind=I64 } -> x12 - v207 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v206, target=b36, fall=b35 } (exit_acc=v206) + v699 ImmData(1832) -> x0 + v700 Load { addr=v699, disp=0, kind=I64 } -> x0 + v701 BinopI { op=eq, lhs=v700, rhs_imm=91 } -> x0 + terminator Bnz { cond=v701, target=b86, fall=b49 } (exit_acc=v701) block 49 start_pc=0 - v208 ImmData(1816) -> x0 - v209 Load { addr=v208, disp=0, kind=I64 } -> x0 - v210 Imm(0) -> x1 - v211 Load { addr=v209, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v211, target=b51, fall=b50 } (exit_acc=v211) + v706 ImmData(1832) -> x0 + v707 Load { addr=v706, disp=0, kind=I64 } -> x0 + v708 BinopI { op=eq, lhs=v707, rhs_imm=63 } -> x0 + terminator Bnz { cond=v708, target=b85, fall=b50 } (exit_acc=v708) block 50 start_pc=0 - v212 ImmData(1832) -> x0 - v213 Load { addr=v212, disp=0, kind=I64 } -> x0 - v214 ImmData(1816) -> x1 - v215 Load { addr=v214, disp=0, kind=I64 } -> x1 - v216 Imm(8) -> x2 - v217 BinopI { op=add, lhs=v215, rhs_imm=8 } -> x2 - v218 Load { addr=v215, disp=8, kind=I64 } -> x1 - v219 Binop { op=eq, lhs=v213, rhs=v218 } -> x1 - v220 Imm(0) -> x0 - terminator Bz { cond=v219, target=b225, fall=b52 } (exit_acc=v219) + v713 ImmData(1832) -> x0 + v714 Load { addr=v713, disp=0, kind=I64 } -> x0 + v715 BinopI { op=eq, lhs=v714, rhs_imm=126 } -> x0 + v716 Imm(1) -> x2 + v717 Imm(0) -> x1 + terminator Bnz { cond=v715, target=b74, fall=b51 } (exit_acc=v715) block 51 start_pc=0 - v221 ImmData(1816) -> x0 - v222 Load { addr=v221, disp=0, kind=I64 } -> x1 - v223 Imm(16) -> x2 - v224 BinopI { op=add, lhs=v222, rhs_imm=16 } -> x2 - v225 LoadLocal { off=-1, kind=I64 } -> x2 - v226 Store { addr=v222, disp=16, value=v117, kind=I64 } -> - - v227 Load { addr=v221, disp=0, kind=I64 } -> x1 - v228 Imm(8) -> x2 - v229 BinopI { op=add, lhs=v227, rhs_imm=8 } -> x2 - v230 ImmData(1832) -> x2 - v231 Load { addr=v230, disp=0, kind=I64 } -> x6 - v232 Store { addr=v227, disp=8, value=v231, kind=I64 } -> - - v233 Load { addr=v221, disp=0, kind=I64 } -> x0 - v234 Imm(0) -> x1 - v235 Imm(133) -> x6 - v236 Store { addr=v233, disp=0, value=v235, kind=I64 } -> - - v237 Store { addr=v230, disp=0, value=v235, kind=I64 } -> - - terminator Return(v234) (exit_acc=v234) + v718 ImmData(1832) -> x0 + v719 Load { addr=v718, disp=0, kind=I64 } -> x0 + v720 BinopI { op=eq, lhs=v719, rhs_imm=59 } -> x0 + v721 BinopI { op=ne, lhs=v720, rhs_imm=0 } -> x2 + v722 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v721) block 52 start_pc=0 - v238 ImmData(1816) -> x0 - v239 Load { addr=v238, disp=0, kind=I64 } -> x0 - v240 Imm(16) -> x1 - v241 BinopI { op=add, lhs=v239, rhs_imm=16 } -> x1 - v242 Load { addr=v239, disp=16, kind=I64 } -> x7 - v243 LoadLocal { off=-1, kind=I64 } -> x0 - v244 ImmData(1776) -> x0 - v245 Load { addr=v244, disp=0, kind=I64 } -> x0 - v246 Binop { op=sub, lhs=v245, rhs=v117 } -> x2 - v247 CallExt { binding_idx=96, args=[v242, v117, v246], fp_arg_mask=0x0 } -> x0 - v248 BinopI { op=eq, lhs=v247, rhs_imm=0 } -> x1 - v249 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v248) + v723 Phi { incoming=[b74:v716, b51:v721], kind=I64 } -> x2 + v724 LoadLocal { off=-39, kind=I64 } -> x0 + v725 Imm(1) -> x1 + v726 Imm(0) -> x0 + terminator Bnz { cond=v723, target=b73, fall=b53 } (exit_acc=v723) block 53 start_pc=0 - v250 Phi { incoming=[b225:v219, b52:v248], kind=I64 } -> x1 - v251 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v250, target=b55, fall=b54 } (exit_acc=v250) + v727 ImmData(1832) -> x0 + v728 Load { addr=v727, disp=0, kind=I64 } -> x0 + v729 BinopI { op=eq, lhs=v728, rhs_imm=123 } -> x0 + v730 BinopI { op=ne, lhs=v729, rhs_imm=0 } -> x1 + v731 Imm(0) -> x0 + terminator Jmp(b54) (exit_acc=v730) block 54 start_pc=0 - v252 ImmData(1832) -> x0 - v253 ImmData(1816) -> x1 - v254 Load { addr=v253, disp=0, kind=I64 } -> x1 - v255 Imm(0) -> x2 - v256 Load { addr=v254, disp=0, kind=I64 } -> x1 - v257 Store { addr=v252, disp=0, value=v256, kind=I64 } -> - - terminator Return(v255) (exit_acc=v255) + v732 Phi { incoming=[b73:v725, b53:v730], kind=I64 } -> x1 + v733 LoadLocal { off=-38, kind=I64 } -> x0 + v734 Imm(1) -> x2 + v735 Imm(0) -> x0 + terminator Bnz { cond=v732, target=b72, fall=b55 } (exit_acc=v732) block 55 start_pc=0 - v258 ImmData(1816) -> x0 - v259 Load { addr=v258, disp=0, kind=I64 } -> x1 - v260 Imm(72) -> x2 - v261 BinopI { op=add, lhs=v259, rhs_imm=72 } -> x1 - v262 Store { addr=v258, disp=0, value=v261, kind=I64 } -> - - terminator Jmp(b49) (exit_acc=v262) + v736 ImmData(1832) -> x0 + v737 Load { addr=v736, disp=0, kind=I64 } -> x0 + v738 BinopI { op=eq, lhs=v737, rhs_imm=125 } -> x0 + v739 BinopI { op=ne, lhs=v738, rhs_imm=0 } -> x2 + v740 Imm(0) -> x0 + terminator Jmp(b56) (exit_acc=v739) block 56 start_pc=0 - v263 ImmData(1832) -> x0 - v264 Load { addr=v263, disp=0, kind=I64 } -> x0 - v265 BinopI { op=le, lhs=v264, rhs_imm=57 } -> x1 - v266 Imm(0) -> x0 - terminator Jmp(b57) (exit_acc=v265) + v741 Phi { incoming=[b72:v734, b55:v739], kind=I64 } -> x2 + v742 LoadLocal { off=-37, kind=I64 } -> x0 + v743 Imm(1) -> x1 + v744 Imm(0) -> x0 + terminator Bnz { cond=v741, target=b71, fall=b57 } (exit_acc=v741) block 57 start_pc=0 - v267 Phi { incoming=[b218:v121, b56:v265], kind=I64 } -> x1 - v268 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v267, target=b60, fall=b58 } (exit_acc=v267) + v745 ImmData(1832) -> x0 + v746 Load { addr=v745, disp=0, kind=I64 } -> x0 + v747 BinopI { op=eq, lhs=v746, rhs_imm=40 } -> x0 + v748 BinopI { op=ne, lhs=v747, rhs_imm=0 } -> x1 + v749 Imm(0) -> x0 + terminator Jmp(b58) (exit_acc=v748) block 58 start_pc=0 - v269 ImmData(1840) -> x0 - v270 ImmData(1832) -> x1 - v271 Load { addr=v270, disp=0, kind=I64 } -> x1 - v272 BinopI { op=sub, lhs=v271, rhs_imm=48 } -> x1 - v273 Store { addr=v269, disp=0, value=v272, kind=I64 } -> - - terminator Bz { cond=v272, target=b63, fall=b61 } (exit_acc=v272) + v750 Phi { incoming=[b71:v743, b57:v748], kind=I64 } -> x1 + v751 LoadLocal { off=-36, kind=I64 } -> x0 + v752 Imm(1) -> x2 + v753 Imm(0) -> x0 + terminator Bnz { cond=v750, target=b70, fall=b59 } (exit_acc=v750) block 59 start_pc=0 - terminator Jmp(b32) + v754 ImmData(1832) -> x0 + v755 Load { addr=v754, disp=0, kind=I64 } -> x0 + v756 BinopI { op=eq, lhs=v755, rhs_imm=41 } -> x0 + v757 BinopI { op=ne, lhs=v756, rhs_imm=0 } -> x2 + v758 Imm(0) -> x0 + terminator Jmp(b60) (exit_acc=v757) block 60 start_pc=0 - v274 ImmData(1832) -> x0 - v275 Load { addr=v274, disp=0, kind=I64 } -> x0 - v276 BinopI { op=eq, lhs=v275, rhs_imm=47 } -> x0 - terminator Bz { cond=v276, target=b99, fall=b97 } (exit_acc=v276) + v759 Phi { incoming=[b70:v752, b59:v757], kind=I64 } -> x2 + v760 LoadLocal { off=-35, kind=I64 } -> x0 + v761 Imm(1) -> x1 + v762 Imm(0) -> x0 + terminator Bnz { cond=v759, target=b69, fall=b61 } (exit_acc=v759) block 61 start_pc=0 - terminator Jmp(b64) + v763 ImmData(1832) -> x0 + v764 Load { addr=v763, disp=0, kind=I64 } -> x0 + v765 BinopI { op=eq, lhs=v764, rhs_imm=93 } -> x0 + v766 BinopI { op=ne, lhs=v765, rhs_imm=0 } -> x1 + v767 Imm(0) -> x0 + terminator Jmp(b62) (exit_acc=v766) block 62 start_pc=0 - v277 ImmData(1832) -> x0 - v278 Imm(128) -> x1 - v279 Store { addr=v277, disp=0, value=v278, kind=I64 } -> - - v280 Imm(0) -> x0 - terminator Return(v280) (exit_acc=v280) + v768 Phi { incoming=[b69:v761, b61:v766], kind=I64 } -> x1 + v769 LoadLocal { off=-34, kind=I64 } -> x0 + v770 Imm(1) -> x2 + v771 Imm(0) -> x0 + terminator Bnz { cond=v768, target=b68, fall=b63 } (exit_acc=v768) block 63 start_pc=0 - v281 ImmData(1776) -> x0 - v282 Load { addr=v281, disp=0, kind=I64 } -> x0 - v283 Load { addr=v282, disp=0, kind=I8 } -> x0 - v284 BinopI { op=eq, lhs=v283, rhs_imm=120 } -> x1 - v285 Imm(0) -> x0 - terminator Bnz { cond=v284, target=b226, fall=b69 } (exit_acc=v284) + v772 ImmData(1832) -> x0 + v773 Load { addr=v772, disp=0, kind=I64 } -> x0 + v774 BinopI { op=eq, lhs=v773, rhs_imm=44 } -> x0 + v775 BinopI { op=ne, lhs=v774, rhs_imm=0 } -> x2 + v776 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v775) block 64 start_pc=0 - v286 ImmData(1776) -> x0 - v287 Load { addr=v286, disp=0, kind=I64 } -> x0 - v288 Load { addr=v287, disp=0, kind=I8 } -> x0 - v289 BinopI { op=ge, lhs=v288, rhs_imm=48 } -> x1 - v290 Imm(0) -> x0 - terminator Bz { cond=v289, target=b227, fall=b67 } (exit_acc=v289) + v777 Phi { incoming=[b68:v770, b63:v775], kind=I64 } -> x2 + v778 LoadLocal { off=-33, kind=I64 } -> x0 + v779 Imm(0) -> x0 + terminator Bnz { cond=v777, target=b67, fall=b65 } (exit_acc=v777) block 65 start_pc=0 - v291 ImmData(1840) -> x0 - v292 Load { addr=v291, disp=0, kind=I64 } -> x1 - v293 BinopI { op=mul, lhs=v292, rhs_imm=10 } -> x1 - v294 ImmData(1776) -> x2 - v295 Load { addr=v294, disp=0, kind=I64 } -> x6 - v296 BinopI { op=add, lhs=v295, rhs_imm=1 } -> x7 - v297 Store { addr=v294, disp=0, value=v296, kind=I64 } -> - - v298 Load { addr=v295, disp=0, kind=I8 } -> x2 - v299 Binop { op=add, lhs=v293, rhs=v298 } -> x1 - v300 BinopI { op=sub, lhs=v299, rhs_imm=48 } -> x1 - v301 Store { addr=v291, disp=0, value=v300, kind=I64 } -> - - terminator Jmp(b64) (exit_acc=v301) + v780 ImmData(1832) -> x0 + v781 Load { addr=v780, disp=0, kind=I64 } -> x0 + v782 BinopI { op=eq, lhs=v781, rhs_imm=58 } -> x2 + v783 Imm(0) -> x0 + terminator Jmp(b66) (exit_acc=v782) block 66 start_pc=0 - terminator Jmp(b62) + v784 Phi { incoming=[b67:v777, b65:v782], kind=I64 } -> x2 + v785 LoadLocal { off=-32, kind=I64 } -> x0 + terminator Bz { cond=v784, target=b82, fall=b84 } (exit_acc=v784) block 67 start_pc=0 - v302 ImmData(1776) -> x0 - v303 Load { addr=v302, disp=0, kind=I64 } -> x0 - v304 Load { addr=v303, disp=0, kind=I8 } -> x0 - v305 BinopI { op=le, lhs=v304, rhs_imm=57 } -> x1 - v306 Imm(0) -> x0 - terminator Jmp(b68) (exit_acc=v305) + terminator Jmp(b66) block 68 start_pc=0 - v307 Phi { incoming=[b227:v289, b67:v305], kind=I64 } -> x1 - v308 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v307, target=b66, fall=b65 } (exit_acc=v307) + terminator Jmp(b64) block 69 start_pc=0 - v309 ImmData(1776) -> x0 - v310 Load { addr=v309, disp=0, kind=I64 } -> x0 - v311 Load { addr=v310, disp=0, kind=I8 } -> x0 - v312 BinopI { op=eq, lhs=v311, rhs_imm=88 } -> x1 - v313 Imm(0) -> x0 - terminator Jmp(b70) (exit_acc=v312) + terminator Jmp(b62) block 70 start_pc=0 - v314 Phi { incoming=[b226:v284, b69:v312], kind=I64 } -> x1 - v315 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v314, target=b73, fall=b71 } (exit_acc=v314) + terminator Jmp(b60) block 71 start_pc=0 - terminator Jmp(b74) + terminator Jmp(b58) block 72 start_pc=0 - terminator Jmp(b62) + terminator Jmp(b56) block 73 start_pc=0 - terminator Jmp(b92) + terminator Jmp(b54) block 74 start_pc=0 - v316 ImmData(1832) -> x0 - v317 ImmData(1776) -> x1 - v318 Load { addr=v317, disp=0, kind=I64 } -> x2 - v319 BinopI { op=add, lhs=v318, rhs_imm=1 } -> x2 - v320 Store { addr=v317, disp=0, value=v319, kind=I64 } -> - - v321 Load { addr=v319, disp=0, kind=I8 } -> x1 - v322 Store { addr=v316, disp=0, value=v321, kind=I64 } -> - - v323 Imm(0) -> x0 - terminator Bz { cond=v321, target=b228, fall=b77 } (exit_acc=v321) + terminator Jmp(b52) block 75 start_pc=0 - v324 ImmData(1840) -> x0 - v325 Load { addr=v324, disp=0, kind=I64 } -> x1 - v326 BinopI { op=shl, lhs=v325, rhs_imm=4 } -> x1 - v327 ImmData(1832) -> x2 - v328 Load { addr=v327, disp=0, kind=I64 } -> x6 - v329 BinopI { op=and, lhs=v328, rhs_imm=15 } -> x7 - v330 Binop { op=add, lhs=v326, rhs=v329 } -> x1 - v331 Load { addr=v327, disp=0, kind=I64 } -> x2 - v332 BinopI { op=ge, lhs=v328, rhs_imm=65 } -> x2 - terminator Bz { cond=v332, target=b90, fall=b89 } (exit_acc=v332) + terminator Jmp(b36) block 76 start_pc=0 - terminator Jmp(b72) + terminator Jmp(b25) block 77 start_pc=0 - v333 ImmData(1832) -> x0 - v334 Load { addr=v333, disp=0, kind=I64 } -> x0 - v335 BinopI { op=ge, lhs=v334, rhs_imm=48 } -> x0 - v336 Imm(0) -> x2 - v337 Imm(0) -> x1 - terminator Bz { cond=v335, target=b229, fall=b79 } (exit_acc=v335) + terminator Jmp(b22) block 78 start_pc=0 - v338 Phi { incoming=[b228:v321, b86:v372], kind=I64 } -> x1 - v339 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v338, target=b76, fall=b75 } (exit_acc=v338) + terminator Jmp(b19) block 79 start_pc=0 - v340 ImmData(1832) -> x0 - v341 Load { addr=v340, disp=0, kind=I64 } -> x0 - v342 BinopI { op=le, lhs=v341, rhs_imm=57 } -> x0 - v343 BinopI { op=ne, lhs=v342, rhs_imm=0 } -> x2 - v344 Imm(0) -> x0 - terminator Jmp(b80) (exit_acc=v343) + terminator Jmp(b20) block 80 start_pc=0 - v345 Phi { incoming=[b229:v336, b79:v343], kind=I64 } -> x2 - v346 LoadLocal { off=-24, kind=I64 } -> x0 - v347 Imm(1) -> x6 - v348 Imm(0) -> x0 - terminator Bnz { cond=v345, target=b230, fall=b81 } (exit_acc=v345) + terminator Jmp(b16) block 81 start_pc=0 - v349 ImmData(1832) -> x0 - v350 Load { addr=v349, disp=0, kind=I64 } -> x0 - v351 BinopI { op=ge, lhs=v350, rhs_imm=97 } -> x0 - v352 Imm(0) -> x2 - v353 Imm(0) -> x1 - terminator Bz { cond=v351, target=b231, fall=b83 } (exit_acc=v351) + v31 ImmData(1864) -> x0 + v32 Load { addr=v31, disp=0, kind=I64 } -> x1 + v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x1 + v34 Store { addr=v31, disp=0, value=v33, kind=I64 } -> - + terminator Jmp(b82) (exit_acc=v34) block 82 start_pc=0 - v354 Phi { incoming=[b230:v347, b84:v365], kind=I64 } -> x6 - v355 LoadLocal { off=-23, kind=I64 } -> x0 - v356 Imm(1) -> x1 - v357 Imm(0) -> x0 - terminator Bnz { cond=v354, target=b232, fall=b85 } (exit_acc=v354) + v1 ImmData(1832) -> x0 + v2 ImmData(1776) -> x1 + v3 Load { addr=v2, disp=0, kind=I64 } -> x1 + v4 Load { addr=v3, disp=0, kind=I8 } -> x1 + v5 Store { addr=v1, disp=0, value=v4, kind=I64 } -> - + terminator Bnz { cond=v4, target=b1, fall=b83 } (exit_acc=v4) block 83 start_pc=0 - v358 ImmData(1832) -> x0 - v359 Load { addr=v358, disp=0, kind=I64 } -> x0 - v360 BinopI { op=le, lhs=v359, rhs_imm=102 } -> x0 - v361 BinopI { op=ne, lhs=v360, rhs_imm=0 } -> x2 - v362 Imm(0) -> x0 - terminator Jmp(b84) (exit_acc=v361) + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) block 84 start_pc=0 - v363 Phi { incoming=[b231:v352, b83:v361], kind=I64 } -> x2 - v364 LoadLocal { off=-25, kind=I64 } -> x0 - v365 BinopI { op=ne, lhs=v363, rhs_imm=0 } -> x6 - v366 Imm(0) -> x0 - terminator Jmp(b82) (exit_acc=v365) + v786 Imm(0) -> x0 + terminator Return(v786) (exit_acc=v786) block 85 start_pc=0 - v367 ImmData(1832) -> x0 - v368 Load { addr=v367, disp=0, kind=I64 } -> x0 - v369 BinopI { op=ge, lhs=v368, rhs_imm=65 } -> x0 - v370 Imm(0) -> x2 - v371 Imm(0) -> x1 - terminator Bz { cond=v369, target=b233, fall=b87 } (exit_acc=v369) + v709 ImmData(1832) -> x0 + v710 Imm(143) -> x1 + v711 Store { addr=v709, disp=0, value=v710, kind=I64 } -> - + v712 Imm(0) -> x0 + terminator Return(v712) (exit_acc=v712) block 86 start_pc=0 - v372 Phi { incoming=[b232:v356, b88:v382], kind=I64 } -> x1 - v373 LoadLocal { off=-22, kind=I64 } -> x0 - v374 Imm(0) -> x0 - terminator Jmp(b78) (exit_acc=v372) + v702 ImmData(1832) -> x0 + v703 Imm(164) -> x1 + v704 Store { addr=v702, disp=0, value=v703, kind=I64 } -> - + v705 Imm(0) -> x0 + terminator Return(v705) (exit_acc=v705) block 87 start_pc=0 - v375 ImmData(1832) -> x0 - v376 Load { addr=v375, disp=0, kind=I64 } -> x0 - v377 BinopI { op=le, lhs=v376, rhs_imm=70 } -> x0 - v378 BinopI { op=ne, lhs=v377, rhs_imm=0 } -> x2 - v379 Imm(0) -> x0 - terminator Jmp(b88) (exit_acc=v378) + v695 ImmData(1832) -> x0 + v696 Imm(159) -> x1 + v697 Store { addr=v695, disp=0, value=v696, kind=I64 } -> - + v698 Imm(0) -> x0 + terminator Return(v698) (exit_acc=v698) block 88 start_pc=0 - v380 Phi { incoming=[b233:v370, b87:v378], kind=I64 } -> x2 - v381 LoadLocal { off=-26, kind=I64 } -> x0 - v382 BinopI { op=ne, lhs=v380, rhs_imm=0 } -> x1 - v383 Imm(0) -> x0 - terminator Jmp(b86) (exit_acc=v382) + v688 ImmData(1832) -> x0 + v689 Imm(161) -> x1 + v690 Store { addr=v688, disp=0, value=v689, kind=I64 } -> - + v691 Imm(0) -> x0 + terminator Return(v691) (exit_acc=v691) block 89 start_pc=0 - v384 Imm(9) -> x6 - v385 Imm(0) -> x2 - terminator Jmp(b91) (exit_acc=v384) + v681 ImmData(1832) -> x0 + v682 Imm(147) -> x1 + v683 Store { addr=v681, disp=0, value=v682, kind=I64 } -> - + v684 Imm(0) -> x0 + terminator Return(v684) (exit_acc=v684) block 90 start_pc=0 - v386 Imm(0) -> x6 - v387 Imm(0) -> x2 - terminator Jmp(b91) (exit_acc=v386) + v663 ImmData(1776) -> x0 + v664 Load { addr=v663, disp=0, kind=I64 } -> x0 + v665 Load { addr=v664, disp=0, kind=I8 } -> x0 + v666 BinopI { op=eq, lhs=v665, rhs_imm=38 } -> x0 + terminator Bz { cond=v666, target=b93, fall=b91 } (exit_acc=v666) block 91 start_pc=0 - v388 Phi { incoming=[b89:v384, b90:v386], kind=I64 } -> x6 - v389 LoadLocal { off=-27, kind=I64 } -> x2 - v390 Binop { op=add, lhs=v330, rhs=v388 } -> x1 - v391 Store { addr=v324, disp=0, value=v390, kind=I64 } -> - - terminator Jmp(b74) (exit_acc=v391) + v670 ImmData(1776) -> x0 + v671 Load { addr=v670, disp=0, kind=I64 } -> x1 + v672 BinopI { op=add, lhs=v671, rhs_imm=1 } -> x1 + v673 Store { addr=v670, disp=0, value=v672, kind=I64 } -> - + v674 ImmData(1832) -> x0 + v675 Imm(145) -> x1 + v676 Store { addr=v674, disp=0, value=v675, kind=I64 } -> - + terminator Jmp(b92) (exit_acc=v676) block 92 start_pc=0 - v392 ImmData(1776) -> x0 - v393 Load { addr=v392, disp=0, kind=I64 } -> x0 - v394 Load { addr=v393, disp=0, kind=I8 } -> x0 - v395 BinopI { op=ge, lhs=v394, rhs_imm=48 } -> x1 - v396 Imm(0) -> x0 - terminator Bz { cond=v395, target=b234, fall=b95 } (exit_acc=v395) + v677 Imm(0) -> x0 + terminator Return(v677) (exit_acc=v677) block 93 start_pc=0 - v397 ImmData(1840) -> x0 - v398 Load { addr=v397, disp=0, kind=I64 } -> x1 - v399 BinopI { op=shl, lhs=v398, rhs_imm=3 } -> x1 - v400 ImmData(1776) -> x2 - v401 Load { addr=v400, disp=0, kind=I64 } -> x6 - v402 BinopI { op=add, lhs=v401, rhs_imm=1 } -> x7 - v403 Store { addr=v400, disp=0, value=v402, kind=I64 } -> - - v404 Load { addr=v401, disp=0, kind=I8 } -> x2 - v405 Binop { op=add, lhs=v399, rhs=v404 } -> x1 - v406 BinopI { op=sub, lhs=v405, rhs_imm=48 } -> x1 - v407 Store { addr=v397, disp=0, value=v406, kind=I64 } -> - - terminator Jmp(b92) (exit_acc=v407) + v678 ImmData(1832) -> x0 + v679 Imm(148) -> x1 + v680 Store { addr=v678, disp=0, value=v679, kind=I64 } -> - + terminator Jmp(b92) (exit_acc=v680) block 94 start_pc=0 - terminator Jmp(b72) + v645 ImmData(1776) -> x0 + v646 Load { addr=v645, disp=0, kind=I64 } -> x0 + v647 Load { addr=v646, disp=0, kind=I8 } -> x0 + v648 BinopI { op=eq, lhs=v647, rhs_imm=124 } -> x0 + terminator Bz { cond=v648, target=b97, fall=b95 } (exit_acc=v648) block 95 start_pc=0 - v408 ImmData(1776) -> x0 - v409 Load { addr=v408, disp=0, kind=I64 } -> x0 - v410 Load { addr=v409, disp=0, kind=I8 } -> x0 - v411 BinopI { op=le, lhs=v410, rhs_imm=55 } -> x1 - v412 Imm(0) -> x0 - terminator Jmp(b96) (exit_acc=v411) + v652 ImmData(1776) -> x0 + v653 Load { addr=v652, disp=0, kind=I64 } -> x1 + v654 BinopI { op=add, lhs=v653, rhs_imm=1 } -> x1 + v655 Store { addr=v652, disp=0, value=v654, kind=I64 } -> - + v656 ImmData(1832) -> x0 + v657 Imm(144) -> x1 + v658 Store { addr=v656, disp=0, value=v657, kind=I64 } -> - + terminator Jmp(b96) (exit_acc=v658) block 96 start_pc=0 - v413 Phi { incoming=[b234:v395, b95:v411], kind=I64 } -> x1 - v414 LoadLocal { off=-28, kind=I64 } -> x0 - terminator Bz { cond=v413, target=b94, fall=b93 } (exit_acc=v413) + v659 Imm(0) -> x0 + terminator Return(v659) (exit_acc=v659) block 97 start_pc=0 - v415 ImmData(1776) -> x0 - v416 Load { addr=v415, disp=0, kind=I64 } -> x0 - v417 Load { addr=v416, disp=0, kind=I8 } -> x0 - v418 BinopI { op=eq, lhs=v417, rhs_imm=47 } -> x0 - terminator Bz { cond=v418, target=b102, fall=b100 } (exit_acc=v418) + v660 ImmData(1832) -> x0 + v661 Imm(146) -> x1 + v662 Store { addr=v660, disp=0, value=v661, kind=I64 } -> - + terminator Jmp(b96) (exit_acc=v662) block 98 start_pc=0 - terminator Jmp(b59) + v616 ImmData(1776) -> x0 + v617 Load { addr=v616, disp=0, kind=I64 } -> x0 + v618 Load { addr=v617, disp=0, kind=I8 } -> x0 + v619 BinopI { op=eq, lhs=v618, rhs_imm=61 } -> x0 + terminator Bz { cond=v619, target=b101, fall=b99 } (exit_acc=v619) block 99 start_pc=0 - v419 ImmData(1832) -> x0 - v420 Load { addr=v419, disp=0, kind=I64 } -> x0 - v421 BinopI { op=eq, lhs=v420, rhs_imm=39 } -> x1 - v422 Imm(0) -> x0 - terminator Bnz { cond=v421, target=b235, fall=b108 } (exit_acc=v421) + v623 ImmData(1776) -> x0 + v624 Load { addr=v623, disp=0, kind=I64 } -> x1 + v625 BinopI { op=add, lhs=v624, rhs_imm=1 } -> x1 + v626 Store { addr=v623, disp=0, value=v625, kind=I64 } -> - + v627 ImmData(1832) -> x0 + v628 Imm(154) -> x1 + v629 Store { addr=v627, disp=0, value=v628, kind=I64 } -> - + terminator Jmp(b100) (exit_acc=v629) block 100 start_pc=0 - v423 ImmData(1776) -> x0 - v424 Load { addr=v423, disp=0, kind=I64 } -> x1 - v425 BinopI { op=add, lhs=v424, rhs_imm=1 } -> x1 - v426 Store { addr=v423, disp=0, value=v425, kind=I64 } -> - - terminator Jmp(b103) (exit_acc=v426) + v630 Imm(0) -> x0 + terminator Return(v630) (exit_acc=v630) block 101 start_pc=0 - terminator Jmp(b98) + v631 ImmData(1776) -> x0 + v632 Load { addr=v631, disp=0, kind=I64 } -> x0 + v633 Load { addr=v632, disp=0, kind=I8 } -> x0 + v634 BinopI { op=eq, lhs=v633, rhs_imm=62 } -> x0 + terminator Bz { cond=v634, target=b103, fall=b102 } (exit_acc=v634) block 102 start_pc=0 - v427 ImmData(1832) -> x0 - v428 Imm(160) -> x1 - v429 Store { addr=v427, disp=0, value=v428, kind=I64 } -> - - v430 Imm(0) -> x0 - terminator Return(v430) (exit_acc=v430) + v635 ImmData(1776) -> x0 + v636 Load { addr=v635, disp=0, kind=I64 } -> x1 + v637 BinopI { op=add, lhs=v636, rhs_imm=1 } -> x1 + v638 Store { addr=v635, disp=0, value=v637, kind=I64 } -> - + v639 ImmData(1832) -> x0 + v640 Imm(156) -> x1 + v641 Store { addr=v639, disp=0, value=v640, kind=I64 } -> - + terminator Jmp(b100) (exit_acc=v641) block 103 start_pc=0 - v431 ImmData(1776) -> x0 - v432 Load { addr=v431, disp=0, kind=I64 } -> x0 - v433 Load { addr=v432, disp=0, kind=I8 } -> x0 - v434 BinopI { op=ne, lhs=v433, rhs_imm=0 } -> x1 - v435 Imm(0) -> x0 - terminator Bz { cond=v434, target=b236, fall=b106 } (exit_acc=v434) + v642 ImmData(1832) -> x0 + v643 Imm(152) -> x1 + v644 Store { addr=v642, disp=0, value=v643, kind=I64 } -> - + terminator Jmp(b100) (exit_acc=v644) block 104 start_pc=0 - v436 ImmData(1776) -> x0 - v437 Load { addr=v436, disp=0, kind=I64 } -> x1 - v438 BinopI { op=add, lhs=v437, rhs_imm=1 } -> x1 - v439 Store { addr=v436, disp=0, value=v438, kind=I64 } -> - - terminator Jmp(b103) (exit_acc=v439) + v587 ImmData(1776) -> x0 + v588 Load { addr=v587, disp=0, kind=I64 } -> x0 + v589 Load { addr=v588, disp=0, kind=I8 } -> x0 + v590 BinopI { op=eq, lhs=v589, rhs_imm=61 } -> x0 + terminator Bz { cond=v590, target=b107, fall=b105 } (exit_acc=v590) block 105 start_pc=0 - terminator Jmp(b101) + v594 ImmData(1776) -> x0 + v595 Load { addr=v594, disp=0, kind=I64 } -> x1 + v596 BinopI { op=add, lhs=v595, rhs_imm=1 } -> x1 + v597 Store { addr=v594, disp=0, value=v596, kind=I64 } -> - + v598 ImmData(1832) -> x0 + v599 Imm(153) -> x1 + v600 Store { addr=v598, disp=0, value=v599, kind=I64 } -> - + terminator Jmp(b106) (exit_acc=v600) block 106 start_pc=0 - v440 ImmData(1776) -> x0 - v441 Load { addr=v440, disp=0, kind=I64 } -> x0 - v442 Load { addr=v441, disp=0, kind=I8 } -> x0 - v443 BinopI { op=ne, lhs=v442, rhs_imm=10 } -> x1 - v444 Imm(0) -> x0 - terminator Jmp(b107) (exit_acc=v443) + v601 Imm(0) -> x0 + terminator Return(v601) (exit_acc=v601) block 107 start_pc=0 - v445 Phi { incoming=[b236:v434, b106:v443], kind=I64 } -> x1 - v446 LoadLocal { off=-29, kind=I64 } -> x0 - terminator Bz { cond=v445, target=b105, fall=b104 } (exit_acc=v445) + v602 ImmData(1776) -> x0 + v603 Load { addr=v602, disp=0, kind=I64 } -> x0 + v604 Load { addr=v603, disp=0, kind=I8 } -> x0 + v605 BinopI { op=eq, lhs=v604, rhs_imm=60 } -> x0 + terminator Bz { cond=v605, target=b109, fall=b108 } (exit_acc=v605) block 108 start_pc=0 - v447 ImmData(1832) -> x0 - v448 Load { addr=v447, disp=0, kind=I64 } -> x0 - v449 BinopI { op=eq, lhs=v448, rhs_imm=34 } -> x1 - v450 Imm(0) -> x0 - terminator Jmp(b109) (exit_acc=v449) + v606 ImmData(1776) -> x0 + v607 Load { addr=v606, disp=0, kind=I64 } -> x1 + v608 BinopI { op=add, lhs=v607, rhs_imm=1 } -> x1 + v609 Store { addr=v606, disp=0, value=v608, kind=I64 } -> - + v610 ImmData(1832) -> x0 + v611 Imm(155) -> x1 + v612 Store { addr=v610, disp=0, value=v611, kind=I64 } -> - + terminator Jmp(b106) (exit_acc=v612) block 109 start_pc=0 - v451 Phi { incoming=[b235:v421, b108:v449], kind=I64 } -> x1 - v452 LoadLocal { off=-30, kind=I64 } -> x0 - terminator Bz { cond=v451, target=b112, fall=b110 } (exit_acc=v451) + v613 ImmData(1832) -> x0 + v614 Imm(151) -> x1 + v615 Store { addr=v613, disp=0, value=v614, kind=I64 } -> - + terminator Jmp(b106) (exit_acc=v615) block 110 start_pc=0 - v453 ImmData(1792) -> x0 - v454 Load { addr=v453, disp=0, kind=I64 } -> x0 - v455 Imm(0) -> x1 - terminator Jmp(b113) (exit_acc=v454) + v572 ImmData(1776) -> x0 + v573 Load { addr=v572, disp=0, kind=I64 } -> x0 + v574 Load { addr=v573, disp=0, kind=I8 } -> x0 + v575 BinopI { op=eq, lhs=v574, rhs_imm=61 } -> x0 + terminator Bz { cond=v575, target=b112, fall=b111 } (exit_acc=v575) block 111 start_pc=0 - terminator Jmp(b98) + v579 ImmData(1776) -> x0 + v580 Load { addr=v579, disp=0, kind=I64 } -> x1 + v581 BinopI { op=add, lhs=v580, rhs_imm=1 } -> x1 + v582 Store { addr=v579, disp=0, value=v581, kind=I64 } -> - + v583 ImmData(1832) -> x0 + v584 Imm(150) -> x1 + v585 Store { addr=v583, disp=0, value=v584, kind=I64 } -> - + terminator Jmp(b112) (exit_acc=v585) block 112 start_pc=0 - v456 ImmData(1832) -> x0 - v457 Load { addr=v456, disp=0, kind=I64 } -> x0 - v458 BinopI { op=eq, lhs=v457, rhs_imm=61 } -> x0 - terminator Bz { cond=v458, target=b129, fall=b127 } (exit_acc=v458) + v586 Imm(0) -> x0 + terminator Return(v586) (exit_acc=v586) block 113 start_pc=0 - v459 ImmData(1776) -> x1 - v460 Load { addr=v459, disp=0, kind=I64 } -> x1 - v461 Load { addr=v460, disp=0, kind=I8 } -> x1 - v462 BinopI { op=ne, lhs=v461, rhs_imm=0 } -> x2 - v463 Imm(0) -> x1 - terminator Bz { cond=v462, target=b237, fall=b116 } (exit_acc=v462) + v554 ImmData(1776) -> x0 + v555 Load { addr=v554, disp=0, kind=I64 } -> x0 + v556 Load { addr=v555, disp=0, kind=I8 } -> x0 + v557 BinopI { op=eq, lhs=v556, rhs_imm=45 } -> x0 + terminator Bz { cond=v557, target=b116, fall=b114 } (exit_acc=v557) block 114 start_pc=0 - v464 ImmData(1840) -> x1 - v465 ImmData(1776) -> x2 - v466 Load { addr=v465, disp=0, kind=I64 } -> x6 - v467 BinopI { op=add, lhs=v466, rhs_imm=1 } -> x7 - v468 Store { addr=v465, disp=0, value=v467, kind=I64 } -> - - v469 Load { addr=v466, disp=0, kind=I8 } -> x2 - v470 Store { addr=v464, disp=0, value=v469, kind=I64 } -> - - v471 BinopI { op=eq, lhs=v469, rhs_imm=92 } -> x1 - terminator Bz { cond=v471, target=b119, fall=b118 } (exit_acc=v471) + v561 ImmData(1776) -> x0 + v562 Load { addr=v561, disp=0, kind=I64 } -> x1 + v563 BinopI { op=add, lhs=v562, rhs_imm=1 } -> x1 + v564 Store { addr=v561, disp=0, value=v563, kind=I64 } -> - + v565 ImmData(1832) -> x0 + v566 Imm(163) -> x1 + v567 Store { addr=v565, disp=0, value=v566, kind=I64 } -> - + terminator Jmp(b115) (exit_acc=v567) block 115 start_pc=0 - v472 ImmData(1776) -> x1 - v473 Load { addr=v472, disp=0, kind=I64 } -> x2 - v474 BinopI { op=add, lhs=v473, rhs_imm=1 } -> x2 - v475 Store { addr=v472, disp=0, value=v474, kind=I64 } -> - - v476 ImmData(1832) -> x1 - v477 Load { addr=v476, disp=0, kind=I64 } -> x1 - v478 BinopI { op=eq, lhs=v477, rhs_imm=34 } -> x1 - terminator Bz { cond=v478, target=b126, fall=b124 } (exit_acc=v478) + v568 Imm(0) -> x0 + terminator Return(v568) (exit_acc=v568) block 116 start_pc=0 - v479 ImmData(1776) -> x1 - v480 Load { addr=v479, disp=0, kind=I64 } -> x1 - v481 Load { addr=v480, disp=0, kind=I8 } -> x1 - v482 ImmData(1832) -> x2 - v483 Load { addr=v482, disp=0, kind=I64 } -> x2 - v484 Binop { op=ne, lhs=v481, rhs=v483 } -> x2 - v485 Imm(0) -> x1 - terminator Jmp(b117) (exit_acc=v484) + v569 ImmData(1832) -> x0 + v570 Imm(158) -> x1 + v571 Store { addr=v569, disp=0, value=v570, kind=I64 } -> - + terminator Jmp(b115) (exit_acc=v571) block 117 start_pc=0 - v486 Phi { incoming=[b237:v462, b116:v484], kind=I64 } -> x2 - v487 LoadLocal { off=-31, kind=I64 } -> x1 - terminator Bz { cond=v486, target=b115, fall=b114 } (exit_acc=v486) + v536 ImmData(1776) -> x0 + v537 Load { addr=v536, disp=0, kind=I64 } -> x0 + v538 Load { addr=v537, disp=0, kind=I8 } -> x0 + v539 BinopI { op=eq, lhs=v538, rhs_imm=43 } -> x0 + terminator Bz { cond=v539, target=b120, fall=b118 } (exit_acc=v539) block 118 start_pc=0 + v543 ImmData(1776) -> x0 + v544 Load { addr=v543, disp=0, kind=I64 } -> x1 + v545 BinopI { op=add, lhs=v544, rhs_imm=1 } -> x1 + v546 Store { addr=v543, disp=0, value=v545, kind=I64 } -> - + v547 ImmData(1832) -> x0 + v548 Imm(162) -> x1 + v549 Store { addr=v547, disp=0, value=v548, kind=I64 } -> - + terminator Jmp(b119) (exit_acc=v549) + block 119 start_pc=0 + v550 Imm(0) -> x0 + terminator Return(v550) (exit_acc=v550) + block 120 start_pc=0 + v551 ImmData(1832) -> x0 + v552 Imm(157) -> x1 + v553 Store { addr=v551, disp=0, value=v552, kind=I64 } -> - + terminator Jmp(b119) (exit_acc=v553) + block 121 start_pc=0 + v518 ImmData(1776) -> x0 + v519 Load { addr=v518, disp=0, kind=I64 } -> x0 + v520 Load { addr=v519, disp=0, kind=I8 } -> x0 + v521 BinopI { op=eq, lhs=v520, rhs_imm=61 } -> x0 + terminator Bz { cond=v521, target=b124, fall=b122 } (exit_acc=v521) + block 122 start_pc=0 + v525 ImmData(1776) -> x0 + v526 Load { addr=v525, disp=0, kind=I64 } -> x1 + v527 BinopI { op=add, lhs=v526, rhs_imm=1 } -> x1 + v528 Store { addr=v525, disp=0, value=v527, kind=I64 } -> - + v529 ImmData(1832) -> x0 + v530 Imm(149) -> x1 + v531 Store { addr=v529, disp=0, value=v530, kind=I64 } -> - + terminator Jmp(b123) (exit_acc=v531) + block 123 start_pc=0 + v532 Imm(0) -> x0 + terminator Return(v532) (exit_acc=v532) + block 124 start_pc=0 + v533 ImmData(1832) -> x0 + v534 Imm(142) -> x1 + v535 Store { addr=v533, disp=0, value=v534, kind=I64 } -> - + terminator Jmp(b123) (exit_acc=v535) + block 125 start_pc=0 + v453 ImmData(1792) -> x0 + v454 Load { addr=v453, disp=0, kind=I64 } -> x0 + v455 Imm(0) -> x1 + terminator Jmp(b126) (exit_acc=v454) + block 126 start_pc=0 + v459 ImmData(1776) -> x1 + v460 Load { addr=v459, disp=0, kind=I64 } -> x1 + v461 Load { addr=v460, disp=0, kind=I8 } -> x1 + v462 BinopI { op=ne, lhs=v461, rhs_imm=0 } -> x2 + v463 Imm(0) -> x1 + terminator Bz { cond=v462, target=b134, fall=b127 } (exit_acc=v462) + block 127 start_pc=0 + v479 ImmData(1776) -> x1 + v480 Load { addr=v479, disp=0, kind=I64 } -> x1 + v481 Load { addr=v480, disp=0, kind=I8 } -> x1 + v482 ImmData(1832) -> x2 + v483 Load { addr=v482, disp=0, kind=I64 } -> x2 + v484 Binop { op=ne, lhs=v481, rhs=v483 } -> x2 + v485 Imm(0) -> x1 + terminator Jmp(b128) (exit_acc=v484) + block 128 start_pc=0 + v486 Phi { incoming=[b134:v462, b127:v484], kind=I64 } -> x2 + v487 LoadLocal { off=-31, kind=I64 } -> x1 + terminator Bz { cond=v486, target=b135, fall=b129 } (exit_acc=v486) + block 129 start_pc=0 + v464 ImmData(1840) -> x1 + v465 ImmData(1776) -> x2 + v466 Load { addr=v465, disp=0, kind=I64 } -> x6 + v467 BinopI { op=add, lhs=v466, rhs_imm=1 } -> x7 + v468 Store { addr=v465, disp=0, value=v467, kind=I64 } -> - + v469 Load { addr=v466, disp=0, kind=I8 } -> x2 + v470 Store { addr=v464, disp=0, value=v469, kind=I64 } -> - + v471 BinopI { op=eq, lhs=v469, rhs_imm=92 } -> x1 + terminator Bz { cond=v471, target=b132, fall=b130 } (exit_acc=v471) + block 130 start_pc=0 v488 ImmData(1840) -> x1 v489 ImmData(1776) -> x2 v490 Load { addr=v489, disp=0, kind=I64 } -> x6 @@ -735,20 +730,18 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v493 Load { addr=v490, disp=0, kind=I8 } -> x2 v494 Store { addr=v488, disp=0, value=v493, kind=I64 } -> - v495 BinopI { op=eq, lhs=v493, rhs_imm=110 } -> x1 - terminator Bz { cond=v495, target=b121, fall=b120 } (exit_acc=v495) - block 119 start_pc=0 - v496 ImmData(1832) -> x1 - v497 Load { addr=v496, disp=0, kind=I64 } -> x1 - v498 BinopI { op=eq, lhs=v497, rhs_imm=34 } -> x1 - terminator Bz { cond=v498, target=b123, fall=b122 } (exit_acc=v498) - block 120 start_pc=0 + terminator Bz { cond=v495, target=b132, fall=b131 } (exit_acc=v495) + block 131 start_pc=0 v499 ImmData(1840) -> x1 v500 Imm(10) -> x2 v501 Store { addr=v499, disp=0, value=v500, kind=I64 } -> - - terminator Jmp(b121) (exit_acc=v501) - block 121 start_pc=0 - terminator Jmp(b119) - block 122 start_pc=0 + terminator Jmp(b132) (exit_acc=v501) + block 132 start_pc=0 + v496 ImmData(1832) -> x1 + v497 Load { addr=v496, disp=0, kind=I64 } -> x1 + v498 BinopI { op=eq, lhs=v497, rhs_imm=34 } -> x1 + terminator Bz { cond=v498, target=b126, fall=b133 } (exit_acc=v498) + block 133 start_pc=0 v502 ImmData(1792) -> x1 v503 Load { addr=v502, disp=0, kind=I64 } -> x2 v504 BinopI { op=add, lhs=v503, rhs_imm=1 } -> x6 @@ -758,529 +751,536 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v508 Store { addr=v503, disp=0, value=v507, kind=I8 } -> - v509 BinopI { op=shl, lhs=v507, rhs_imm=56 } -> x2 v510 Extend { value=v507, kind=I8 } -> x1 - terminator Jmp(b123) (exit_acc=v510) - block 123 start_pc=0 - terminator Jmp(b113) - block 124 start_pc=0 + terminator Jmp(b126) (exit_acc=v510) + block 134 start_pc=0 + terminator Jmp(b128) + block 135 start_pc=0 + v472 ImmData(1776) -> x1 + v473 Load { addr=v472, disp=0, kind=I64 } -> x2 + v474 BinopI { op=add, lhs=v473, rhs_imm=1 } -> x2 + v475 Store { addr=v472, disp=0, value=v474, kind=I64 } -> - + v476 ImmData(1832) -> x1 + v477 Load { addr=v476, disp=0, kind=I64 } -> x1 + v478 BinopI { op=eq, lhs=v477, rhs_imm=34 } -> x1 + terminator Bz { cond=v478, target=b138, fall=b136 } (exit_acc=v478) + block 136 start_pc=0 v511 ImmData(1840) -> x1 v512 LoadLocal { off=-1, kind=I64 } -> x2 v513 Store { addr=v511, disp=0, value=v454, kind=I64 } -> - - terminator Jmp(b125) (exit_acc=v513) - block 125 start_pc=0 + terminator Jmp(b137) (exit_acc=v513) + block 137 start_pc=0 v514 Imm(0) -> x0 terminator Return(v514) (exit_acc=v514) - block 126 start_pc=0 + block 138 start_pc=0 v515 ImmData(1832) -> x0 v516 Imm(128) -> x1 v517 Store { addr=v515, disp=0, value=v516, kind=I64 } -> - - terminator Jmp(b125) (exit_acc=v517) - block 127 start_pc=0 - v518 ImmData(1776) -> x0 - v519 Load { addr=v518, disp=0, kind=I64 } -> x0 - v520 Load { addr=v519, disp=0, kind=I8 } -> x0 - v521 BinopI { op=eq, lhs=v520, rhs_imm=61 } -> x0 - terminator Bz { cond=v521, target=b132, fall=b130 } (exit_acc=v521) - block 128 start_pc=0 - terminator Jmp(b111) - block 129 start_pc=0 - v522 ImmData(1832) -> x0 - v523 Load { addr=v522, disp=0, kind=I64 } -> x0 - v524 BinopI { op=eq, lhs=v523, rhs_imm=43 } -> x0 - terminator Bz { cond=v524, target=b135, fall=b133 } (exit_acc=v524) - block 130 start_pc=0 - v525 ImmData(1776) -> x0 - v526 Load { addr=v525, disp=0, kind=I64 } -> x1 - v527 BinopI { op=add, lhs=v526, rhs_imm=1 } -> x1 - v528 Store { addr=v525, disp=0, value=v527, kind=I64 } -> - - v529 ImmData(1832) -> x0 - v530 Imm(149) -> x1 - v531 Store { addr=v529, disp=0, value=v530, kind=I64 } -> - - terminator Jmp(b131) (exit_acc=v531) - block 131 start_pc=0 - v532 Imm(0) -> x0 - terminator Return(v532) (exit_acc=v532) - block 132 start_pc=0 - v533 ImmData(1832) -> x0 - v534 Imm(142) -> x1 - v535 Store { addr=v533, disp=0, value=v534, kind=I64 } -> - - terminator Jmp(b131) (exit_acc=v535) - block 133 start_pc=0 - v536 ImmData(1776) -> x0 - v537 Load { addr=v536, disp=0, kind=I64 } -> x0 - v538 Load { addr=v537, disp=0, kind=I8 } -> x0 - v539 BinopI { op=eq, lhs=v538, rhs_imm=43 } -> x0 - terminator Bz { cond=v539, target=b138, fall=b136 } (exit_acc=v539) - block 134 start_pc=0 - terminator Jmp(b128) - block 135 start_pc=0 - v540 ImmData(1832) -> x0 - v541 Load { addr=v540, disp=0, kind=I64 } -> x0 - v542 BinopI { op=eq, lhs=v541, rhs_imm=45 } -> x0 - terminator Bz { cond=v542, target=b141, fall=b139 } (exit_acc=v542) - block 136 start_pc=0 - v543 ImmData(1776) -> x0 - v544 Load { addr=v543, disp=0, kind=I64 } -> x1 - v545 BinopI { op=add, lhs=v544, rhs_imm=1 } -> x1 - v546 Store { addr=v543, disp=0, value=v545, kind=I64 } -> - - v547 ImmData(1832) -> x0 - v548 Imm(162) -> x1 - v549 Store { addr=v547, disp=0, value=v548, kind=I64 } -> - - terminator Jmp(b137) (exit_acc=v549) - block 137 start_pc=0 - v550 Imm(0) -> x0 - terminator Return(v550) (exit_acc=v550) - block 138 start_pc=0 - v551 ImmData(1832) -> x0 - v552 Imm(157) -> x1 - v553 Store { addr=v551, disp=0, value=v552, kind=I64 } -> - - terminator Jmp(b137) (exit_acc=v553) + terminator Jmp(b137) (exit_acc=v517) block 139 start_pc=0 - v554 ImmData(1776) -> x0 - v555 Load { addr=v554, disp=0, kind=I64 } -> x0 - v556 Load { addr=v555, disp=0, kind=I8 } -> x0 - v557 BinopI { op=eq, lhs=v556, rhs_imm=45 } -> x0 - terminator Bz { cond=v557, target=b144, fall=b142 } (exit_acc=v557) + v427 ImmData(1832) -> x0 + v428 Imm(160) -> x1 + v429 Store { addr=v427, disp=0, value=v428, kind=I64 } -> - + v430 Imm(0) -> x0 + terminator Return(v430) (exit_acc=v430) block 140 start_pc=0 - terminator Jmp(b134) + v269 ImmData(1840) -> x0 + v270 ImmData(1832) -> x1 + v271 Load { addr=v270, disp=0, kind=I64 } -> x1 + v272 BinopI { op=sub, lhs=v271, rhs_imm=48 } -> x1 + v273 Store { addr=v269, disp=0, value=v272, kind=I64 } -> - + terminator Bz { cond=v272, target=b147, fall=b141 } (exit_acc=v272) block 141 start_pc=0 - v558 ImmData(1832) -> x0 - v559 Load { addr=v558, disp=0, kind=I64 } -> x0 - v560 BinopI { op=eq, lhs=v559, rhs_imm=33 } -> x0 - terminator Bz { cond=v560, target=b147, fall=b145 } (exit_acc=v560) + v286 ImmData(1776) -> x0 + v287 Load { addr=v286, disp=0, kind=I64 } -> x0 + v288 Load { addr=v287, disp=0, kind=I8 } -> x0 + v289 BinopI { op=ge, lhs=v288, rhs_imm=48 } -> x1 + v290 Imm(0) -> x0 + terminator Bz { cond=v289, target=b145, fall=b142 } (exit_acc=v289) block 142 start_pc=0 - v561 ImmData(1776) -> x0 - v562 Load { addr=v561, disp=0, kind=I64 } -> x1 - v563 BinopI { op=add, lhs=v562, rhs_imm=1 } -> x1 - v564 Store { addr=v561, disp=0, value=v563, kind=I64 } -> - - v565 ImmData(1832) -> x0 - v566 Imm(163) -> x1 - v567 Store { addr=v565, disp=0, value=v566, kind=I64 } -> - - terminator Jmp(b143) (exit_acc=v567) + v302 ImmData(1776) -> x0 + v303 Load { addr=v302, disp=0, kind=I64 } -> x0 + v304 Load { addr=v303, disp=0, kind=I8 } -> x0 + v305 BinopI { op=le, lhs=v304, rhs_imm=57 } -> x1 + v306 Imm(0) -> x0 + terminator Jmp(b143) (exit_acc=v305) block 143 start_pc=0 - v568 Imm(0) -> x0 - terminator Return(v568) (exit_acc=v568) + v307 Phi { incoming=[b145:v289, b142:v305], kind=I64 } -> x1 + v308 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v307, target=b146, fall=b144 } (exit_acc=v307) block 144 start_pc=0 - v569 ImmData(1832) -> x0 - v570 Imm(158) -> x1 - v571 Store { addr=v569, disp=0, value=v570, kind=I64 } -> - - terminator Jmp(b143) (exit_acc=v571) + v291 ImmData(1840) -> x0 + v292 Load { addr=v291, disp=0, kind=I64 } -> x1 + v293 BinopI { op=mul, lhs=v292, rhs_imm=10 } -> x1 + v294 ImmData(1776) -> x2 + v295 Load { addr=v294, disp=0, kind=I64 } -> x6 + v296 BinopI { op=add, lhs=v295, rhs_imm=1 } -> x7 + v297 Store { addr=v294, disp=0, value=v296, kind=I64 } -> - + v298 Load { addr=v295, disp=0, kind=I8 } -> x2 + v299 Binop { op=add, lhs=v293, rhs=v298 } -> x1 + v300 BinopI { op=sub, lhs=v299, rhs_imm=48 } -> x1 + v301 Store { addr=v291, disp=0, value=v300, kind=I64 } -> - + terminator Jmp(b141) (exit_acc=v301) block 145 start_pc=0 - v572 ImmData(1776) -> x0 - v573 Load { addr=v572, disp=0, kind=I64 } -> x0 - v574 Load { addr=v573, disp=0, kind=I8 } -> x0 - v575 BinopI { op=eq, lhs=v574, rhs_imm=61 } -> x0 - terminator Bz { cond=v575, target=b149, fall=b148 } (exit_acc=v575) + terminator Jmp(b143) block 146 start_pc=0 - terminator Jmp(b140) + v277 ImmData(1832) -> x0 + v278 Imm(128) -> x1 + v279 Store { addr=v277, disp=0, value=v278, kind=I64 } -> - + v280 Imm(0) -> x0 + terminator Return(v280) (exit_acc=v280) block 147 start_pc=0 - v576 ImmData(1832) -> x0 - v577 Load { addr=v576, disp=0, kind=I64 } -> x0 - v578 BinopI { op=eq, lhs=v577, rhs_imm=60 } -> x0 - terminator Bz { cond=v578, target=b152, fall=b150 } (exit_acc=v578) + v281 ImmData(1776) -> x0 + v282 Load { addr=v281, disp=0, kind=I64 } -> x0 + v283 Load { addr=v282, disp=0, kind=I8 } -> x0 + v284 BinopI { op=eq, lhs=v283, rhs_imm=120 } -> x1 + v285 Imm(0) -> x0 + terminator Bnz { cond=v284, target=b178, fall=b148 } (exit_acc=v284) block 148 start_pc=0 - v579 ImmData(1776) -> x0 - v580 Load { addr=v579, disp=0, kind=I64 } -> x1 - v581 BinopI { op=add, lhs=v580, rhs_imm=1 } -> x1 - v582 Store { addr=v579, disp=0, value=v581, kind=I64 } -> - - v583 ImmData(1832) -> x0 - v584 Imm(150) -> x1 - v585 Store { addr=v583, disp=0, value=v584, kind=I64 } -> - - terminator Jmp(b149) (exit_acc=v585) + v309 ImmData(1776) -> x0 + v310 Load { addr=v309, disp=0, kind=I64 } -> x0 + v311 Load { addr=v310, disp=0, kind=I8 } -> x0 + v312 BinopI { op=eq, lhs=v311, rhs_imm=88 } -> x1 + v313 Imm(0) -> x0 + terminator Jmp(b149) (exit_acc=v312) block 149 start_pc=0 - v586 Imm(0) -> x0 - terminator Return(v586) (exit_acc=v586) + v314 Phi { incoming=[b178:v284, b148:v312], kind=I64 } -> x1 + v315 LoadLocal { off=-20, kind=I64 } -> x0 + terminator Bz { cond=v314, target=b173, fall=b150 } (exit_acc=v314) block 150 start_pc=0 - v587 ImmData(1776) -> x0 - v588 Load { addr=v587, disp=0, kind=I64 } -> x0 - v589 Load { addr=v588, disp=0, kind=I8 } -> x0 - v590 BinopI { op=eq, lhs=v589, rhs_imm=61 } -> x0 - terminator Bz { cond=v590, target=b155, fall=b153 } (exit_acc=v590) + v316 ImmData(1832) -> x0 + v317 ImmData(1776) -> x1 + v318 Load { addr=v317, disp=0, kind=I64 } -> x2 + v319 BinopI { op=add, lhs=v318, rhs_imm=1 } -> x2 + v320 Store { addr=v317, disp=0, value=v319, kind=I64 } -> - + v321 Load { addr=v319, disp=0, kind=I8 } -> x1 + v322 Store { addr=v316, disp=0, value=v321, kind=I64 } -> - + v323 Imm(0) -> x0 + terminator Bz { cond=v321, target=b172, fall=b151 } (exit_acc=v321) block 151 start_pc=0 - terminator Jmp(b146) + v333 ImmData(1832) -> x0 + v334 Load { addr=v333, disp=0, kind=I64 } -> x0 + v335 BinopI { op=ge, lhs=v334, rhs_imm=48 } -> x0 + v336 Imm(0) -> x2 + v337 Imm(0) -> x1 + terminator Bz { cond=v335, target=b171, fall=b152 } (exit_acc=v335) block 152 start_pc=0 - v591 ImmData(1832) -> x0 - v592 Load { addr=v591, disp=0, kind=I64 } -> x0 - v593 BinopI { op=eq, lhs=v592, rhs_imm=62 } -> x0 - terminator Bz { cond=v593, target=b161, fall=b159 } (exit_acc=v593) + v340 ImmData(1832) -> x0 + v341 Load { addr=v340, disp=0, kind=I64 } -> x0 + v342 BinopI { op=le, lhs=v341, rhs_imm=57 } -> x0 + v343 BinopI { op=ne, lhs=v342, rhs_imm=0 } -> x2 + v344 Imm(0) -> x0 + terminator Jmp(b153) (exit_acc=v343) block 153 start_pc=0 - v594 ImmData(1776) -> x0 - v595 Load { addr=v594, disp=0, kind=I64 } -> x1 - v596 BinopI { op=add, lhs=v595, rhs_imm=1 } -> x1 - v597 Store { addr=v594, disp=0, value=v596, kind=I64 } -> - - v598 ImmData(1832) -> x0 - v599 Imm(153) -> x1 - v600 Store { addr=v598, disp=0, value=v599, kind=I64 } -> - - terminator Jmp(b154) (exit_acc=v600) + v345 Phi { incoming=[b171:v336, b152:v343], kind=I64 } -> x2 + v346 LoadLocal { off=-24, kind=I64 } -> x0 + v347 Imm(1) -> x6 + v348 Imm(0) -> x0 + terminator Bnz { cond=v345, target=b170, fall=b154 } (exit_acc=v345) block 154 start_pc=0 - v601 Imm(0) -> x0 - terminator Return(v601) (exit_acc=v601) + v349 ImmData(1832) -> x0 + v350 Load { addr=v349, disp=0, kind=I64 } -> x0 + v351 BinopI { op=ge, lhs=v350, rhs_imm=97 } -> x0 + v352 Imm(0) -> x2 + v353 Imm(0) -> x1 + terminator Bz { cond=v351, target=b169, fall=b155 } (exit_acc=v351) block 155 start_pc=0 - v602 ImmData(1776) -> x0 - v603 Load { addr=v602, disp=0, kind=I64 } -> x0 - v604 Load { addr=v603, disp=0, kind=I8 } -> x0 - v605 BinopI { op=eq, lhs=v604, rhs_imm=60 } -> x0 - terminator Bz { cond=v605, target=b158, fall=b156 } (exit_acc=v605) + v358 ImmData(1832) -> x0 + v359 Load { addr=v358, disp=0, kind=I64 } -> x0 + v360 BinopI { op=le, lhs=v359, rhs_imm=102 } -> x0 + v361 BinopI { op=ne, lhs=v360, rhs_imm=0 } -> x2 + v362 Imm(0) -> x0 + terminator Jmp(b156) (exit_acc=v361) block 156 start_pc=0 - v606 ImmData(1776) -> x0 - v607 Load { addr=v606, disp=0, kind=I64 } -> x1 - v608 BinopI { op=add, lhs=v607, rhs_imm=1 } -> x1 - v609 Store { addr=v606, disp=0, value=v608, kind=I64 } -> - - v610 ImmData(1832) -> x0 - v611 Imm(155) -> x1 - v612 Store { addr=v610, disp=0, value=v611, kind=I64 } -> - - terminator Jmp(b157) (exit_acc=v612) + v363 Phi { incoming=[b169:v352, b155:v361], kind=I64 } -> x2 + v364 LoadLocal { off=-25, kind=I64 } -> x0 + v365 BinopI { op=ne, lhs=v363, rhs_imm=0 } -> x6 + v366 Imm(0) -> x0 + terminator Jmp(b157) (exit_acc=v365) block 157 start_pc=0 - terminator Jmp(b154) + v354 Phi { incoming=[b170:v347, b156:v365], kind=I64 } -> x6 + v355 LoadLocal { off=-23, kind=I64 } -> x0 + v356 Imm(1) -> x1 + v357 Imm(0) -> x0 + terminator Bnz { cond=v354, target=b168, fall=b158 } (exit_acc=v354) block 158 start_pc=0 - v613 ImmData(1832) -> x0 - v614 Imm(151) -> x1 - v615 Store { addr=v613, disp=0, value=v614, kind=I64 } -> - - terminator Jmp(b157) (exit_acc=v615) + v367 ImmData(1832) -> x0 + v368 Load { addr=v367, disp=0, kind=I64 } -> x0 + v369 BinopI { op=ge, lhs=v368, rhs_imm=65 } -> x0 + v370 Imm(0) -> x2 + v371 Imm(0) -> x1 + terminator Bz { cond=v369, target=b167, fall=b159 } (exit_acc=v369) block 159 start_pc=0 - v616 ImmData(1776) -> x0 - v617 Load { addr=v616, disp=0, kind=I64 } -> x0 - v618 Load { addr=v617, disp=0, kind=I8 } -> x0 - v619 BinopI { op=eq, lhs=v618, rhs_imm=61 } -> x0 - terminator Bz { cond=v619, target=b164, fall=b162 } (exit_acc=v619) + v375 ImmData(1832) -> x0 + v376 Load { addr=v375, disp=0, kind=I64 } -> x0 + v377 BinopI { op=le, lhs=v376, rhs_imm=70 } -> x0 + v378 BinopI { op=ne, lhs=v377, rhs_imm=0 } -> x2 + v379 Imm(0) -> x0 + terminator Jmp(b160) (exit_acc=v378) block 160 start_pc=0 - terminator Jmp(b151) + v380 Phi { incoming=[b167:v370, b159:v378], kind=I64 } -> x2 + v381 LoadLocal { off=-26, kind=I64 } -> x0 + v382 BinopI { op=ne, lhs=v380, rhs_imm=0 } -> x1 + v383 Imm(0) -> x0 + terminator Jmp(b161) (exit_acc=v382) block 161 start_pc=0 - v620 ImmData(1832) -> x0 - v621 Load { addr=v620, disp=0, kind=I64 } -> x0 - v622 BinopI { op=eq, lhs=v621, rhs_imm=124 } -> x0 - terminator Bz { cond=v622, target=b170, fall=b168 } (exit_acc=v622) + v372 Phi { incoming=[b168:v356, b160:v382], kind=I64 } -> x1 + v373 LoadLocal { off=-22, kind=I64 } -> x0 + v374 Imm(0) -> x0 + terminator Jmp(b162) (exit_acc=v372) block 162 start_pc=0 - v623 ImmData(1776) -> x0 - v624 Load { addr=v623, disp=0, kind=I64 } -> x1 - v625 BinopI { op=add, lhs=v624, rhs_imm=1 } -> x1 - v626 Store { addr=v623, disp=0, value=v625, kind=I64 } -> - - v627 ImmData(1832) -> x0 - v628 Imm(154) -> x1 - v629 Store { addr=v627, disp=0, value=v628, kind=I64 } -> - - terminator Jmp(b163) (exit_acc=v629) + v338 Phi { incoming=[b172:v321, b161:v372], kind=I64 } -> x1 + v339 LoadLocal { off=-21, kind=I64 } -> x0 + terminator Bz { cond=v338, target=b146, fall=b163 } (exit_acc=v338) block 163 start_pc=0 - v630 Imm(0) -> x0 - terminator Return(v630) (exit_acc=v630) + v324 ImmData(1840) -> x0 + v325 Load { addr=v324, disp=0, kind=I64 } -> x1 + v326 BinopI { op=shl, lhs=v325, rhs_imm=4 } -> x1 + v327 ImmData(1832) -> x2 + v328 Load { addr=v327, disp=0, kind=I64 } -> x6 + v329 BinopI { op=and, lhs=v328, rhs_imm=15 } -> x7 + v330 Binop { op=add, lhs=v326, rhs=v329 } -> x1 + v331 Load { addr=v327, disp=0, kind=I64 } -> x2 + v332 BinopI { op=ge, lhs=v328, rhs_imm=65 } -> x2 + terminator Bz { cond=v332, target=b166, fall=b164 } (exit_acc=v332) block 164 start_pc=0 - v631 ImmData(1776) -> x0 - v632 Load { addr=v631, disp=0, kind=I64 } -> x0 - v633 Load { addr=v632, disp=0, kind=I8 } -> x0 - v634 BinopI { op=eq, lhs=v633, rhs_imm=62 } -> x0 - terminator Bz { cond=v634, target=b167, fall=b165 } (exit_acc=v634) + v384 Imm(9) -> x6 + v385 Imm(0) -> x2 + terminator Jmp(b165) (exit_acc=v384) block 165 start_pc=0 - v635 ImmData(1776) -> x0 - v636 Load { addr=v635, disp=0, kind=I64 } -> x1 - v637 BinopI { op=add, lhs=v636, rhs_imm=1 } -> x1 - v638 Store { addr=v635, disp=0, value=v637, kind=I64 } -> - - v639 ImmData(1832) -> x0 - v640 Imm(156) -> x1 - v641 Store { addr=v639, disp=0, value=v640, kind=I64 } -> - - terminator Jmp(b166) (exit_acc=v641) + v388 Phi { incoming=[b164:v384, b166:v386], kind=I64 } -> x6 + v389 LoadLocal { off=-27, kind=I64 } -> x2 + v390 Binop { op=add, lhs=v330, rhs=v388 } -> x1 + v391 Store { addr=v324, disp=0, value=v390, kind=I64 } -> - + terminator Jmp(b150) (exit_acc=v391) block 166 start_pc=0 - terminator Jmp(b163) + v386 Imm(0) -> x6 + v387 Imm(0) -> x2 + terminator Jmp(b165) (exit_acc=v386) block 167 start_pc=0 - v642 ImmData(1832) -> x0 - v643 Imm(152) -> x1 - v644 Store { addr=v642, disp=0, value=v643, kind=I64 } -> - - terminator Jmp(b166) (exit_acc=v644) + terminator Jmp(b160) block 168 start_pc=0 - v645 ImmData(1776) -> x0 - v646 Load { addr=v645, disp=0, kind=I64 } -> x0 - v647 Load { addr=v646, disp=0, kind=I8 } -> x0 - v648 BinopI { op=eq, lhs=v647, rhs_imm=124 } -> x0 - terminator Bz { cond=v648, target=b173, fall=b171 } (exit_acc=v648) + terminator Jmp(b161) block 169 start_pc=0 - terminator Jmp(b160) + terminator Jmp(b156) block 170 start_pc=0 - v649 ImmData(1832) -> x0 - v650 Load { addr=v649, disp=0, kind=I64 } -> x0 - v651 BinopI { op=eq, lhs=v650, rhs_imm=38 } -> x0 - terminator Bz { cond=v651, target=b176, fall=b174 } (exit_acc=v651) + terminator Jmp(b157) block 171 start_pc=0 - v652 ImmData(1776) -> x0 - v653 Load { addr=v652, disp=0, kind=I64 } -> x1 - v654 BinopI { op=add, lhs=v653, rhs_imm=1 } -> x1 - v655 Store { addr=v652, disp=0, value=v654, kind=I64 } -> - - v656 ImmData(1832) -> x0 - v657 Imm(144) -> x1 - v658 Store { addr=v656, disp=0, value=v657, kind=I64 } -> - - terminator Jmp(b172) (exit_acc=v658) + terminator Jmp(b153) block 172 start_pc=0 - v659 Imm(0) -> x0 - terminator Return(v659) (exit_acc=v659) + terminator Jmp(b162) block 173 start_pc=0 - v660 ImmData(1832) -> x0 - v661 Imm(146) -> x1 - v662 Store { addr=v660, disp=0, value=v661, kind=I64 } -> - - terminator Jmp(b172) (exit_acc=v662) + v392 ImmData(1776) -> x0 + v393 Load { addr=v392, disp=0, kind=I64 } -> x0 + v394 Load { addr=v393, disp=0, kind=I8 } -> x0 + v395 BinopI { op=ge, lhs=v394, rhs_imm=48 } -> x1 + v396 Imm(0) -> x0 + terminator Bz { cond=v395, target=b177, fall=b174 } (exit_acc=v395) block 174 start_pc=0 - v663 ImmData(1776) -> x0 - v664 Load { addr=v663, disp=0, kind=I64 } -> x0 - v665 Load { addr=v664, disp=0, kind=I8 } -> x0 - v666 BinopI { op=eq, lhs=v665, rhs_imm=38 } -> x0 - terminator Bz { cond=v666, target=b179, fall=b177 } (exit_acc=v666) + v408 ImmData(1776) -> x0 + v409 Load { addr=v408, disp=0, kind=I64 } -> x0 + v410 Load { addr=v409, disp=0, kind=I8 } -> x0 + v411 BinopI { op=le, lhs=v410, rhs_imm=55 } -> x1 + v412 Imm(0) -> x0 + terminator Jmp(b175) (exit_acc=v411) block 175 start_pc=0 - terminator Jmp(b169) + v413 Phi { incoming=[b177:v395, b174:v411], kind=I64 } -> x1 + v414 LoadLocal { off=-28, kind=I64 } -> x0 + terminator Bz { cond=v413, target=b146, fall=b176 } (exit_acc=v413) block 176 start_pc=0 - v667 ImmData(1832) -> x0 - v668 Load { addr=v667, disp=0, kind=I64 } -> x0 - v669 BinopI { op=eq, lhs=v668, rhs_imm=94 } -> x0 - terminator Bz { cond=v669, target=b182, fall=b180 } (exit_acc=v669) + v397 ImmData(1840) -> x0 + v398 Load { addr=v397, disp=0, kind=I64 } -> x1 + v399 BinopI { op=shl, lhs=v398, rhs_imm=3 } -> x1 + v400 ImmData(1776) -> x2 + v401 Load { addr=v400, disp=0, kind=I64 } -> x6 + v402 BinopI { op=add, lhs=v401, rhs_imm=1 } -> x7 + v403 Store { addr=v400, disp=0, value=v402, kind=I64 } -> - + v404 Load { addr=v401, disp=0, kind=I8 } -> x2 + v405 Binop { op=add, lhs=v399, rhs=v404 } -> x1 + v406 BinopI { op=sub, lhs=v405, rhs_imm=48 } -> x1 + v407 Store { addr=v397, disp=0, value=v406, kind=I64 } -> - + terminator Jmp(b173) (exit_acc=v407) block 177 start_pc=0 - v670 ImmData(1776) -> x0 - v671 Load { addr=v670, disp=0, kind=I64 } -> x1 - v672 BinopI { op=add, lhs=v671, rhs_imm=1 } -> x1 - v673 Store { addr=v670, disp=0, value=v672, kind=I64 } -> - - v674 ImmData(1832) -> x0 - v675 Imm(145) -> x1 - v676 Store { addr=v674, disp=0, value=v675, kind=I64 } -> - - terminator Jmp(b178) (exit_acc=v676) + terminator Jmp(b175) block 178 start_pc=0 - v677 Imm(0) -> x0 - terminator Return(v677) (exit_acc=v677) + terminator Jmp(b149) block 179 start_pc=0 - v678 ImmData(1832) -> x0 - v679 Imm(148) -> x1 - v680 Store { addr=v678, disp=0, value=v679, kind=I64 } -> - - terminator Jmp(b178) (exit_acc=v680) + v115 ImmData(1776) -> x0 + v116 Load { addr=v115, disp=0, kind=I64 } -> x0 + v117 BinopI { op=sub, lhs=v116, rhs_imm=1 } -> x3 + v118 Imm(0) -> x0 + terminator Jmp(b180) (exit_acc=v117) block 180 start_pc=0 - v681 ImmData(1832) -> x0 - v682 Imm(147) -> x1 - v683 Store { addr=v681, disp=0, value=v682, kind=I64 } -> - - v684 Imm(0) -> x0 - terminator Return(v684) (exit_acc=v684) + v123 ImmData(1776) -> x0 + v124 Load { addr=v123, disp=0, kind=I64 } -> x0 + v125 Load { addr=v124, disp=0, kind=I8 } -> x0 + v126 BinopI { op=ge, lhs=v125, rhs_imm=97 } -> x0 + v127 Imm(0) -> x2 + v128 Imm(0) -> x1 + terminator Bz { cond=v126, target=b199, fall=b181 } (exit_acc=v126) block 181 start_pc=0 - terminator Jmp(b175) + v152 ImmData(1776) -> x0 + v153 Load { addr=v152, disp=0, kind=I64 } -> x0 + v154 Load { addr=v153, disp=0, kind=I8 } -> x0 + v155 BinopI { op=le, lhs=v154, rhs_imm=122 } -> x0 + v156 BinopI { op=ne, lhs=v155, rhs_imm=0 } -> x2 + v157 Imm(0) -> x0 + terminator Jmp(b182) (exit_acc=v156) block 182 start_pc=0 - v685 ImmData(1832) -> x0 - v686 Load { addr=v685, disp=0, kind=I64 } -> x0 - v687 BinopI { op=eq, lhs=v686, rhs_imm=37 } -> x0 - terminator Bz { cond=v687, target=b185, fall=b183 } (exit_acc=v687) + v158 Phi { incoming=[b199:v127, b181:v156], kind=I64 } -> x2 + v159 LoadLocal { off=-14, kind=I64 } -> x0 + v160 Imm(1) -> x1 + v161 Imm(0) -> x0 + terminator Bnz { cond=v158, target=b198, fall=b183 } (exit_acc=v158) block 183 start_pc=0 - v688 ImmData(1832) -> x0 - v689 Imm(161) -> x1 - v690 Store { addr=v688, disp=0, value=v689, kind=I64 } -> - - v691 Imm(0) -> x0 - terminator Return(v691) (exit_acc=v691) + v162 ImmData(1776) -> x0 + v163 Load { addr=v162, disp=0, kind=I64 } -> x0 + v164 Load { addr=v163, disp=0, kind=I8 } -> x0 + v165 BinopI { op=ge, lhs=v164, rhs_imm=65 } -> x0 + v166 Imm(0) -> x2 + v167 Imm(0) -> x1 + terminator Bz { cond=v165, target=b197, fall=b184 } (exit_acc=v165) block 184 start_pc=0 - terminator Jmp(b181) + v172 ImmData(1776) -> x0 + v173 Load { addr=v172, disp=0, kind=I64 } -> x0 + v174 Load { addr=v173, disp=0, kind=I8 } -> x0 + v175 BinopI { op=le, lhs=v174, rhs_imm=90 } -> x0 + v176 BinopI { op=ne, lhs=v175, rhs_imm=0 } -> x2 + v177 Imm(0) -> x0 + terminator Jmp(b185) (exit_acc=v176) block 185 start_pc=0 - v692 ImmData(1832) -> x0 - v693 Load { addr=v692, disp=0, kind=I64 } -> x0 - v694 BinopI { op=eq, lhs=v693, rhs_imm=42 } -> x0 - terminator Bz { cond=v694, target=b188, fall=b186 } (exit_acc=v694) + v178 Phi { incoming=[b197:v166, b184:v176], kind=I64 } -> x2 + v179 LoadLocal { off=-15, kind=I64 } -> x0 + v180 BinopI { op=ne, lhs=v178, rhs_imm=0 } -> x1 + v181 Imm(0) -> x0 + terminator Jmp(b186) (exit_acc=v180) block 186 start_pc=0 - v695 ImmData(1832) -> x0 - v696 Imm(159) -> x1 - v697 Store { addr=v695, disp=0, value=v696, kind=I64 } -> - - v698 Imm(0) -> x0 - terminator Return(v698) (exit_acc=v698) + v168 Phi { incoming=[b198:v160, b185:v180], kind=I64 } -> x1 + v169 LoadLocal { off=-13, kind=I64 } -> x0 + v170 Imm(1) -> x2 + v171 Imm(0) -> x0 + terminator Bnz { cond=v168, target=b196, fall=b187 } (exit_acc=v168) block 187 start_pc=0 - terminator Jmp(b184) + v182 ImmData(1776) -> x0 + v183 Load { addr=v182, disp=0, kind=I64 } -> x0 + v184 Load { addr=v183, disp=0, kind=I8 } -> x0 + v185 BinopI { op=ge, lhs=v184, rhs_imm=48 } -> x0 + v186 Imm(0) -> x2 + v187 Imm(0) -> x1 + terminator Bz { cond=v185, target=b195, fall=b188 } (exit_acc=v185) block 188 start_pc=0 - v699 ImmData(1832) -> x0 - v700 Load { addr=v699, disp=0, kind=I64 } -> x0 - v701 BinopI { op=eq, lhs=v700, rhs_imm=91 } -> x0 - terminator Bz { cond=v701, target=b191, fall=b189 } (exit_acc=v701) + v191 ImmData(1776) -> x0 + v192 Load { addr=v191, disp=0, kind=I64 } -> x0 + v193 Load { addr=v192, disp=0, kind=I8 } -> x0 + v194 BinopI { op=le, lhs=v193, rhs_imm=57 } -> x0 + v195 BinopI { op=ne, lhs=v194, rhs_imm=0 } -> x2 + v196 Imm(0) -> x0 + terminator Jmp(b189) (exit_acc=v195) block 189 start_pc=0 - v702 ImmData(1832) -> x0 - v703 Imm(164) -> x1 - v704 Store { addr=v702, disp=0, value=v703, kind=I64 } -> - - v705 Imm(0) -> x0 - terminator Return(v705) (exit_acc=v705) + v197 Phi { incoming=[b195:v186, b188:v195], kind=I64 } -> x2 + v198 LoadLocal { off=-16, kind=I64 } -> x0 + v199 BinopI { op=ne, lhs=v197, rhs_imm=0 } -> x2 + v200 Imm(0) -> x0 + terminator Jmp(b190) (exit_acc=v199) block 190 start_pc=0 - terminator Jmp(b187) + v188 Phi { incoming=[b196:v170, b189:v199], kind=I64 } -> x2 + v189 LoadLocal { off=-12, kind=I64 } -> x0 + v190 Imm(0) -> x0 + terminator Bnz { cond=v188, target=b194, fall=b191 } (exit_acc=v188) block 191 start_pc=0 - v706 ImmData(1832) -> x0 - v707 Load { addr=v706, disp=0, kind=I64 } -> x0 - v708 BinopI { op=eq, lhs=v707, rhs_imm=63 } -> x0 - terminator Bz { cond=v708, target=b194, fall=b192 } (exit_acc=v708) + v201 ImmData(1776) -> x0 + v202 Load { addr=v201, disp=0, kind=I64 } -> x0 + v203 Load { addr=v202, disp=0, kind=I8 } -> x0 + v204 BinopI { op=eq, lhs=v203, rhs_imm=95 } -> x2 + v205 Imm(0) -> x0 + terminator Jmp(b192) (exit_acc=v204) block 192 start_pc=0 - v709 ImmData(1832) -> x0 - v710 Imm(143) -> x1 - v711 Store { addr=v709, disp=0, value=v710, kind=I64 } -> - - v712 Imm(0) -> x0 - terminator Return(v712) (exit_acc=v712) + v206 Phi { incoming=[b194:v188, b191:v204], kind=I64 } -> x2 + v207 LoadLocal { off=-11, kind=I64 } -> x0 + terminator Bz { cond=v206, target=b200, fall=b193 } (exit_acc=v206) block 193 start_pc=0 - terminator Jmp(b190) + v129 ImmData(1832) -> x0 + v130 Load { addr=v129, disp=0, kind=I64 } -> x1 + v131 BinopI { op=mul, lhs=v130, rhs_imm=147 } -> x1 + v132 ImmData(1776) -> x2 + v133 Load { addr=v132, disp=0, kind=I64 } -> x6 + v134 BinopI { op=add, lhs=v133, rhs_imm=1 } -> x7 + v135 Store { addr=v132, disp=0, value=v134, kind=I64 } -> - + v136 Load { addr=v133, disp=0, kind=I8 } -> x2 + v137 Binop { op=add, lhs=v131, rhs=v136 } -> x1 + v138 Store { addr=v129, disp=0, value=v137, kind=I64 } -> - + terminator Jmp(b180) (exit_acc=v138) block 194 start_pc=0 - v713 ImmData(1832) -> x0 - v714 Load { addr=v713, disp=0, kind=I64 } -> x0 - v715 BinopI { op=eq, lhs=v714, rhs_imm=126 } -> x0 - v716 Imm(1) -> x2 - v717 Imm(0) -> x1 - terminator Bnz { cond=v715, target=b238, fall=b195 } (exit_acc=v715) + terminator Jmp(b192) block 195 start_pc=0 - v718 ImmData(1832) -> x0 - v719 Load { addr=v718, disp=0, kind=I64 } -> x0 - v720 BinopI { op=eq, lhs=v719, rhs_imm=59 } -> x0 - v721 BinopI { op=ne, lhs=v720, rhs_imm=0 } -> x2 - v722 Imm(0) -> x0 - terminator Jmp(b196) (exit_acc=v721) + terminator Jmp(b189) block 196 start_pc=0 - v723 Phi { incoming=[b238:v716, b195:v721], kind=I64 } -> x2 - v724 LoadLocal { off=-39, kind=I64 } -> x0 - v725 Imm(1) -> x1 - v726 Imm(0) -> x0 - terminator Bnz { cond=v723, target=b239, fall=b197 } (exit_acc=v723) + terminator Jmp(b190) block 197 start_pc=0 - v727 ImmData(1832) -> x0 - v728 Load { addr=v727, disp=0, kind=I64 } -> x0 - v729 BinopI { op=eq, lhs=v728, rhs_imm=123 } -> x0 - v730 BinopI { op=ne, lhs=v729, rhs_imm=0 } -> x1 - v731 Imm(0) -> x0 - terminator Jmp(b198) (exit_acc=v730) + terminator Jmp(b185) block 198 start_pc=0 - v732 Phi { incoming=[b239:v725, b197:v730], kind=I64 } -> x1 - v733 LoadLocal { off=-38, kind=I64 } -> x0 - v734 Imm(1) -> x2 - v735 Imm(0) -> x0 - terminator Bnz { cond=v732, target=b240, fall=b199 } (exit_acc=v732) + terminator Jmp(b186) block 199 start_pc=0 - v736 ImmData(1832) -> x0 - v737 Load { addr=v736, disp=0, kind=I64 } -> x0 - v738 BinopI { op=eq, lhs=v737, rhs_imm=125 } -> x0 - v739 BinopI { op=ne, lhs=v738, rhs_imm=0 } -> x2 - v740 Imm(0) -> x0 - terminator Jmp(b200) (exit_acc=v739) + terminator Jmp(b182) block 200 start_pc=0 - v741 Phi { incoming=[b240:v734, b199:v739], kind=I64 } -> x2 - v742 LoadLocal { off=-37, kind=I64 } -> x0 - v743 Imm(1) -> x1 - v744 Imm(0) -> x0 - terminator Bnz { cond=v741, target=b241, fall=b201 } (exit_acc=v741) + v139 ImmData(1832) -> x0 + v140 Load { addr=v139, disp=0, kind=I64 } -> x1 + v141 BinopI { op=shl, lhs=v140, rhs_imm=6 } -> x1 + v142 ImmData(1776) -> x2 + v143 Load { addr=v142, disp=0, kind=I64 } -> x2 + v144 LoadLocal { off=-1, kind=I64 } -> x6 + v145 Binop { op=sub, lhs=v143, rhs=v117 } -> x2 + v146 Binop { op=add, lhs=v141, rhs=v145 } -> x1 + v147 Store { addr=v139, disp=0, value=v146, kind=I64 } -> - + v148 ImmData(1816) -> x0 + v149 ImmData(1824) -> x1 + v150 Load { addr=v149, disp=0, kind=I64 } -> x1 + v151 Store { addr=v148, disp=0, value=v150, kind=I64 } -> - + terminator Jmp(b206) (exit_acc=v151) block 201 start_pc=0 - v745 ImmData(1832) -> x0 - v746 Load { addr=v745, disp=0, kind=I64 } -> x0 - v747 BinopI { op=eq, lhs=v746, rhs_imm=40 } -> x0 - v748 BinopI { op=ne, lhs=v747, rhs_imm=0 } -> x1 - v749 Imm(0) -> x0 - terminator Jmp(b202) (exit_acc=v748) + v212 ImmData(1832) -> x0 + v213 Load { addr=v212, disp=0, kind=I64 } -> x0 + v214 ImmData(1816) -> x1 + v215 Load { addr=v214, disp=0, kind=I64 } -> x1 + v216 Imm(8) -> x2 + v217 BinopI { op=add, lhs=v215, rhs_imm=8 } -> x2 + v218 Load { addr=v215, disp=8, kind=I64 } -> x1 + v219 Binop { op=eq, lhs=v213, rhs=v218 } -> x1 + v220 Imm(0) -> x0 + terminator Bz { cond=v219, target=b204, fall=b202 } (exit_acc=v219) block 202 start_pc=0 - v750 Phi { incoming=[b241:v743, b201:v748], kind=I64 } -> x1 - v751 LoadLocal { off=-36, kind=I64 } -> x0 - v752 Imm(1) -> x2 - v753 Imm(0) -> x0 - terminator Bnz { cond=v750, target=b242, fall=b203 } (exit_acc=v750) + v238 ImmData(1816) -> x0 + v239 Load { addr=v238, disp=0, kind=I64 } -> x0 + v240 Imm(16) -> x1 + v241 BinopI { op=add, lhs=v239, rhs_imm=16 } -> x1 + v242 Load { addr=v239, disp=16, kind=I64 } -> x7 + v243 LoadLocal { off=-1, kind=I64 } -> x0 + v244 ImmData(1776) -> x0 + v245 Load { addr=v244, disp=0, kind=I64 } -> x0 + v246 Binop { op=sub, lhs=v245, rhs=v117 } -> x2 + v247 CallExt { binding_idx=96, args=[v242, v117, v246], fp_arg_mask=0x0 } -> x0 + v248 BinopI { op=eq, lhs=v247, rhs_imm=0 } -> x1 + v249 Imm(0) -> x0 + terminator Jmp(b203) (exit_acc=v248) block 203 start_pc=0 - v754 ImmData(1832) -> x0 - v755 Load { addr=v754, disp=0, kind=I64 } -> x0 - v756 BinopI { op=eq, lhs=v755, rhs_imm=41 } -> x0 - v757 BinopI { op=ne, lhs=v756, rhs_imm=0 } -> x2 - v758 Imm(0) -> x0 - terminator Jmp(b204) (exit_acc=v757) + v250 Phi { incoming=[b204:v219, b202:v248], kind=I64 } -> x1 + v251 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v250, target=b205, fall=b208 } (exit_acc=v250) block 204 start_pc=0 - v759 Phi { incoming=[b242:v752, b203:v757], kind=I64 } -> x2 - v760 LoadLocal { off=-35, kind=I64 } -> x0 - v761 Imm(1) -> x1 - v762 Imm(0) -> x0 - terminator Bnz { cond=v759, target=b243, fall=b205 } (exit_acc=v759) + terminator Jmp(b203) block 205 start_pc=0 - v763 ImmData(1832) -> x0 - v764 Load { addr=v763, disp=0, kind=I64 } -> x0 - v765 BinopI { op=eq, lhs=v764, rhs_imm=93 } -> x0 - v766 BinopI { op=ne, lhs=v765, rhs_imm=0 } -> x1 - v767 Imm(0) -> x0 - terminator Jmp(b206) (exit_acc=v766) + v258 ImmData(1816) -> x0 + v259 Load { addr=v258, disp=0, kind=I64 } -> x1 + v260 Imm(72) -> x2 + v261 BinopI { op=add, lhs=v259, rhs_imm=72 } -> x1 + v262 Store { addr=v258, disp=0, value=v261, kind=I64 } -> - + terminator Jmp(b206) (exit_acc=v262) block 206 start_pc=0 - v768 Phi { incoming=[b243:v761, b205:v766], kind=I64 } -> x1 - v769 LoadLocal { off=-34, kind=I64 } -> x0 - v770 Imm(1) -> x2 - v771 Imm(0) -> x0 - terminator Bnz { cond=v768, target=b244, fall=b207 } (exit_acc=v768) + v208 ImmData(1816) -> x0 + v209 Load { addr=v208, disp=0, kind=I64 } -> x0 + v210 Imm(0) -> x1 + v211 Load { addr=v209, disp=0, kind=I64 } -> x0 + terminator Bnz { cond=v211, target=b201, fall=b207 } (exit_acc=v211) block 207 start_pc=0 - v772 ImmData(1832) -> x0 - v773 Load { addr=v772, disp=0, kind=I64 } -> x0 - v774 BinopI { op=eq, lhs=v773, rhs_imm=44 } -> x0 - v775 BinopI { op=ne, lhs=v774, rhs_imm=0 } -> x2 - v776 Imm(0) -> x0 - terminator Jmp(b208) (exit_acc=v775) + v221 ImmData(1816) -> x0 + v222 Load { addr=v221, disp=0, kind=I64 } -> x1 + v223 Imm(16) -> x2 + v224 BinopI { op=add, lhs=v222, rhs_imm=16 } -> x2 + v225 LoadLocal { off=-1, kind=I64 } -> x2 + v226 Store { addr=v222, disp=16, value=v117, kind=I64 } -> - + v227 Load { addr=v221, disp=0, kind=I64 } -> x1 + v228 Imm(8) -> x2 + v229 BinopI { op=add, lhs=v227, rhs_imm=8 } -> x2 + v230 ImmData(1832) -> x2 + v231 Load { addr=v230, disp=0, kind=I64 } -> x6 + v232 Store { addr=v227, disp=8, value=v231, kind=I64 } -> - + v233 Load { addr=v221, disp=0, kind=I64 } -> x0 + v234 Imm(0) -> x1 + v235 Imm(133) -> x6 + v236 Store { addr=v233, disp=0, value=v235, kind=I64 } -> - + v237 Store { addr=v230, disp=0, value=v235, kind=I64 } -> - + terminator Return(v234) (exit_acc=v234) block 208 start_pc=0 - v777 Phi { incoming=[b244:v770, b207:v775], kind=I64 } -> x2 - v778 LoadLocal { off=-33, kind=I64 } -> x0 - v779 Imm(0) -> x0 - terminator Bnz { cond=v777, target=b245, fall=b209 } (exit_acc=v777) + v252 ImmData(1832) -> x0 + v253 ImmData(1816) -> x1 + v254 Load { addr=v253, disp=0, kind=I64 } -> x1 + v255 Imm(0) -> x2 + v256 Load { addr=v254, disp=0, kind=I64 } -> x1 + v257 Store { addr=v252, disp=0, value=v256, kind=I64 } -> - + terminator Return(v255) (exit_acc=v255) block 209 start_pc=0 - v780 ImmData(1832) -> x0 - v781 Load { addr=v780, disp=0, kind=I64 } -> x0 - v782 BinopI { op=eq, lhs=v781, rhs_imm=58 } -> x2 - v783 Imm(0) -> x0 - terminator Jmp(b210) (exit_acc=v782) + terminator Jmp(b82) block 210 start_pc=0 - v784 Phi { incoming=[b245:v777, b209:v782], kind=I64 } -> x2 - v785 LoadLocal { off=-32, kind=I64 } -> x0 - terminator Bz { cond=v784, target=b212, fall=b211 } (exit_acc=v784) + terminator Jmp(b81) block 211 start_pc=0 - v786 Imm(0) -> x0 - terminator Return(v786) (exit_acc=v786) + terminator Jmp(b7) block 212 start_pc=0 - terminator Jmp(b193) + terminator Jmp(b9) block 213 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b82) block 214 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b82) block 215 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b82) block 216 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b82) block 217 start_pc=0 - terminator Jmp(b30) + terminator Jmp(b141) block 218 start_pc=0 - terminator Jmp(b57) + terminator Jmp(b146) block 219 start_pc=0 - terminator Jmp(b38) + terminator Jmp(b150) block 220 start_pc=0 - terminator Jmp(b40) + terminator Jmp(b146) block 221 start_pc=0 - terminator Jmp(b42) + terminator Jmp(b173) block 222 start_pc=0 - terminator Jmp(b44) + terminator Jmp(b146) block 223 start_pc=0 - terminator Jmp(b46) + terminator Jmp(b146) block 224 start_pc=0 - terminator Jmp(b48) + terminator Jmp(b82) block 225 start_pc=0 - terminator Jmp(b53) + terminator Jmp(b82) block 226 start_pc=0 - terminator Jmp(b70) + terminator Jmp(b82) block 227 start_pc=0 - terminator Jmp(b68) + terminator Jmp(b82) block 228 start_pc=0 - terminator Jmp(b78) + terminator Jmp(b132) block 229 start_pc=0 - terminator Jmp(b80) + terminator Jmp(b126) block 230 start_pc=0 terminator Jmp(b82) block 231 start_pc=0 - terminator Jmp(b84) + terminator Jmp(b82) block 232 start_pc=0 - terminator Jmp(b86) + terminator Jmp(b82) block 233 start_pc=0 - terminator Jmp(b88) + terminator Jmp(b82) block 234 start_pc=0 - terminator Jmp(b96) + terminator Jmp(b82) block 235 start_pc=0 - terminator Jmp(b109) + terminator Jmp(b106) block 236 start_pc=0 - terminator Jmp(b107) + terminator Jmp(b82) block 237 start_pc=0 - terminator Jmp(b117) + terminator Jmp(b100) block 238 start_pc=0 - terminator Jmp(b196) + terminator Jmp(b82) block 239 start_pc=0 - terminator Jmp(b198) + terminator Jmp(b82) block 240 start_pc=0 - terminator Jmp(b200) + terminator Jmp(b82) block 241 start_pc=0 - terminator Jmp(b202) + terminator Jmp(b82) block 242 start_pc=0 - terminator Jmp(b204) + terminator Jmp(b82) block 243 start_pc=0 - terminator Jmp(b206) + terminator Jmp(b82) block 244 start_pc=0 - terminator Jmp(b208) + terminator Jmp(b82) block 245 start_pc=0 - terminator Jmp(b210) + terminator Jmp(b82) ; --- SSA dump (ok=true) ent_pc=7 --- ; name=expr fn ent_pc=7 n_params=1 variadic=false locals=25 @@ -1292,7 +1292,7 @@ fn ent_pc=7 n_params=1 variadic=false locals=25 v3 ImmData(1832) -> x12 v4 Load { addr=v3, disp=0, kind=I64 } -> x0 v5 BinopI { op=eq, lhs=v4, rhs_imm=0 } -> x0 - terminator Bz { cond=v5, target=b3, fall=b1 } (exit_acc=v5) + terminator Bz { cond=v5, target=b103, fall=b1 } (exit_acc=v5) block 1 start_pc=0 v6 ImmData(250) -> x7 v7 ImmData(1864) -> x0 @@ -1300,1938 +1300,1938 @@ fn ent_pc=7 n_params=1 variadic=false locals=25 v9 CallExt { binding_idx=0, args=[v6, v8], fp_arg_mask=0x0 } -> x0 v10 Imm(-1) -> x7 v11 CallExt { binding_idx=69, args=[v10], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b2) (exit_acc=v11) + terminator Jmp(b101) (exit_acc=v11) block 2 start_pc=0 - terminator Jmp(b136) + v648 ImmData(1848) -> x0 + v649 Load { addr=v648, disp=0, kind=I64 } -> x13 + v650 Imm(0) -> x0 + v651 ImmData(1832) -> x0 + v652 Load { addr=v3, disp=0, kind=I64 } -> x0 + v653 BinopI { op=eq, lhs=v652, rhs_imm=142 } -> x0 + terminator Bz { cond=v653, target=b13, fall=b3 } (exit_acc=v653) block 3 start_pc=0 - v12 ImmData(1832) -> x0 - v13 Load { addr=v3, disp=0, kind=I64 } -> x0 - v14 BinopI { op=eq, lhs=v13, rhs_imm=128 } -> x0 - terminator Bz { cond=v14, target=b6, fall=b4 } (exit_acc=v14) + v655 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v656 ImmData(1800) -> x0 + v657 Load { addr=v656, disp=0, kind=I64 } -> x0 + v658 Load { addr=v657, disp=0, kind=I64 } -> x0 + v659 BinopI { op=eq, lhs=v658, rhs_imm=10 } -> x1 + v660 Imm(0) -> x0 + terminator Bnz { cond=v659, target=b12, fall=b4 } (exit_acc=v659) block 4 start_pc=0 - v15 ImmData(1800) -> x0 - v16 Load { addr=v15, disp=0, kind=I64 } -> x1 - v17 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x1 - v18 Store { addr=v15, disp=0, value=v17, kind=I64 } -> - - v19 Imm(1) -> x13 - v20 Store { addr=v17, disp=0, value=v19, kind=I64 } -> - - v21 Load { addr=v15, disp=0, kind=I64 } -> x1 - v22 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x1 - v23 Store { addr=v15, disp=0, value=v22, kind=I64 } -> - - v24 ImmData(1840) -> x0 - v25 Load { addr=v24, disp=0, kind=I64 } -> x0 - v26 Store { addr=v22, disp=0, value=v25, kind=I64 } -> - - v27 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v28 ImmData(1848) -> x0 - v29 Store { addr=v28, disp=0, value=v19, kind=I64 } -> - - terminator Jmp(b5) (exit_acc=v29) + v664 ImmData(1800) -> x0 + v665 Load { addr=v664, disp=0, kind=I64 } -> x0 + v666 Load { addr=v665, disp=0, kind=I64 } -> x0 + v667 BinopI { op=eq, lhs=v666, rhs_imm=9 } -> x1 + v668 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v667) block 5 start_pc=0 - terminator Jmp(b2) + v669 Phi { incoming=[b12:v659, b4:v667], kind=I64 } -> x1 + v670 LoadLocal { off=-16, kind=I64 } -> x0 + terminator Bz { cond=v669, target=b11, fall=b6 } (exit_acc=v669) block 6 start_pc=0 - v30 ImmData(1832) -> x0 - v31 Load { addr=v3, disp=0, kind=I64 } -> x0 - v32 BinopI { op=eq, lhs=v31, rhs_imm=34 } -> x0 - terminator Bz { cond=v32, target=b9, fall=b7 } (exit_acc=v32) + v671 ImmData(1800) -> x0 + v672 Load { addr=v671, disp=0, kind=I64 } -> x0 + v673 Imm(13) -> x1 + v674 Store { addr=v672, disp=0, value=v673, kind=I64 } -> - + terminator Jmp(b7) (exit_acc=v674) block 7 start_pc=0 - v33 ImmData(1800) -> x0 - v34 Load { addr=v33, disp=0, kind=I64 } -> x1 - v35 BinopI { op=add, lhs=v34, rhs_imm=8 } -> x1 - v36 Store { addr=v33, disp=0, value=v35, kind=I64 } -> - - v37 Imm(1) -> x2 - v38 Store { addr=v35, disp=0, value=v37, kind=I64 } -> - - v39 Load { addr=v33, disp=0, kind=I64 } -> x1 - v40 BinopI { op=add, lhs=v39, rhs_imm=8 } -> x1 - v41 Store { addr=v33, disp=0, value=v40, kind=I64 } -> - - v42 ImmData(1840) -> x0 - v43 Load { addr=v42, disp=0, kind=I64 } -> x0 - v44 Store { addr=v40, disp=0, value=v43, kind=I64 } -> - - v45 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b10) (exit_acc=v45) + v675 Imm(142) -> x7 + v676 Call { target_pc=7, args=[v675], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v677 ImmData(1800) -> x0 + v678 Load { addr=v677, disp=0, kind=I64 } -> x1 + v679 BinopI { op=add, lhs=v678, rhs_imm=8 } -> x1 + v680 Store { addr=v677, disp=0, value=v679, kind=I64 } -> - + v681 ImmData(1848) -> x0 + v682 LoadLocal { off=-1, kind=I64 } -> x2 + v683 Store { addr=v681, disp=0, value=v649, kind=I64 } -> - + v684 BinopI { op=eq, lhs=v649, rhs_imm=0 } -> x0 + terminator Bz { cond=v684, target=b10, fall=b8 } (exit_acc=v684) block 8 start_pc=0 - terminator Jmp(b5) + v691 Imm(12) -> x2 + v692 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v691) block 9 start_pc=0 - v46 ImmData(1832) -> x0 - v47 Load { addr=v3, disp=0, kind=I64 } -> x0 - v48 BinopI { op=eq, lhs=v47, rhs_imm=140 } -> x0 - terminator Bz { cond=v48, target=b15, fall=b13 } (exit_acc=v48) + v695 Phi { incoming=[b8:v691, b10:v693], kind=I64 } -> x2 + v696 LoadLocal { off=-17, kind=I64 } -> x0 + v697 Store { addr=v679, disp=0, value=v695, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v697) block 10 start_pc=0 - v49 ImmData(1832) -> x0 - v50 Load { addr=v3, disp=0, kind=I64 } -> x0 - v51 BinopI { op=eq, lhs=v50, rhs_imm=34 } -> x0 - terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) + v693 Imm(11) -> x2 + v694 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v693) block 11 start_pc=0 - v52 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b10) (exit_acc=v52) + v685 ImmData(536) -> x7 + v686 ImmData(1864) -> x0 + v687 Load { addr=v686, disp=0, kind=I64 } -> x6 + v688 CallExt { binding_idx=0, args=[v685, v687], fp_arg_mask=0x0 } -> x0 + v689 Imm(-1) -> x7 + v690 CallExt { binding_idx=69, args=[v689], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b7) (exit_acc=v690) block 12 start_pc=0 - v53 ImmData(1792) -> x0 - v54 Load { addr=v53, disp=0, kind=I64 } -> x1 - v55 BinopI { op=add, lhs=v54, rhs_imm=8 } -> x1 - v56 Imm(-8) -> x2 - v57 Imm(-34359738368) -> x2 - v58 BinopI { op=and, lhs=v55, rhs_imm=-8 } -> x1 - v59 Store { addr=v53, disp=0, value=v58, kind=I64 } -> - - v60 ImmData(1848) -> x0 - v61 Imm(2) -> x1 - v62 Store { addr=v60, disp=0, value=v61, kind=I64 } -> - - terminator Jmp(b8) (exit_acc=v62) + terminator Jmp(b5) block 13 start_pc=0 - v63 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v64 ImmData(1832) -> x0 - v65 Load { addr=v3, disp=0, kind=I64 } -> x0 - v66 BinopI { op=eq, lhs=v65, rhs_imm=40 } -> x0 - terminator Bz { cond=v66, target=b18, fall=b16 } (exit_acc=v66) + v661 ImmData(1832) -> x0 + v662 Load { addr=v3, disp=0, kind=I64 } -> x0 + v663 BinopI { op=eq, lhs=v662, rhs_imm=143 } -> x0 + terminator Bz { cond=v663, target=b18, fall=b14 } (exit_acc=v663) block 14 start_pc=0 - terminator Jmp(b8) + v698 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v699 ImmData(1800) -> x0 + v700 Load { addr=v699, disp=0, kind=I64 } -> x1 + v701 BinopI { op=add, lhs=v700, rhs_imm=8 } -> x1 + v702 Store { addr=v699, disp=0, value=v701, kind=I64 } -> - + v703 Imm(4) -> x2 + v704 Store { addr=v701, disp=0, value=v703, kind=I64 } -> - + v705 Load { addr=v699, disp=0, kind=I64 } -> x1 + v706 BinopI { op=add, lhs=v705, rhs_imm=8 } -> x13 + v707 Store { addr=v699, disp=0, value=v706, kind=I64 } -> - + v708 Imm(0) -> x0 + v709 Imm(142) -> x7 + v710 Call { target_pc=7, args=[v709], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v711 ImmData(1832) -> x0 + v712 Load { addr=v3, disp=0, kind=I64 } -> x0 + v713 BinopI { op=eq, lhs=v712, rhs_imm=58 } -> x0 + terminator Bz { cond=v713, target=b17, fall=b15 } (exit_acc=v713) block 15 start_pc=0 - v67 ImmData(1832) -> x0 - v68 Load { addr=v3, disp=0, kind=I64 } -> x0 - v69 BinopI { op=eq, lhs=v68, rhs_imm=133 } -> x0 - terminator Bz { cond=v69, target=b35, fall=b33 } (exit_acc=v69) + v717 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b16) (exit_acc=v717) block 16 start_pc=0 - v70 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b17) (exit_acc=v70) + v718 LoadLocal { off=-2, kind=I64 } -> x0 + v719 ImmData(1800) -> x14 + v720 Load { addr=v719, disp=0, kind=I64 } -> x0 + v721 Imm(24) -> x1 + v722 BinopI { op=add, lhs=v720, rhs_imm=24 } -> x0 + v723 Store { addr=v706, disp=0, value=v722, kind=I64 } -> - + v724 Load { addr=v719, disp=0, kind=I64 } -> x0 + v725 BinopI { op=add, lhs=v724, rhs_imm=8 } -> x0 + v726 Store { addr=v719, disp=0, value=v725, kind=I64 } -> - + v727 Imm(2) -> x1 + v728 Store { addr=v725, disp=0, value=v727, kind=I64 } -> - + v729 Load { addr=v719, disp=0, kind=I64 } -> x0 + v730 BinopI { op=add, lhs=v729, rhs_imm=8 } -> x13 + v731 Store { addr=v719, disp=0, value=v730, kind=I64 } -> - + v732 Imm(0) -> x0 + v733 Imm(143) -> x7 + v734 Call { target_pc=7, args=[v733], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v735 LoadLocal { off=-2, kind=I64 } -> x0 + v736 Load { addr=v719, disp=0, kind=I64 } -> x0 + v737 Imm(8) -> x1 + v738 BinopI { op=add, lhs=v736, rhs_imm=8 } -> x0 + v739 Store { addr=v730, disp=0, value=v738, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v739) block 17 start_pc=0 - v71 ImmData(1848) -> x0 - v72 Imm(1) -> x1 - v73 Store { addr=v71, disp=0, value=v72, kind=I64 } -> - - v74 ImmData(1832) -> x0 - v75 Load { addr=v3, disp=0, kind=I64 } -> x0 - v76 BinopI { op=eq, lhs=v75, rhs_imm=138 } -> x0 - terminator Bz { cond=v76, target=b21, fall=b19 } (exit_acc=v76) + v740 ImmData(566) -> x7 + v741 ImmData(1864) -> x0 + v742 Load { addr=v741, disp=0, kind=I64 } -> x6 + v743 CallExt { binding_idx=0, args=[v740, v742], fp_arg_mask=0x0 } -> x0 + v744 Imm(-1) -> x7 + v745 CallExt { binding_idx=69, args=[v744], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b16) (exit_acc=v745) block 18 start_pc=0 - v77 ImmData(284) -> x7 - v78 ImmData(1864) -> x0 - v79 Load { addr=v78, disp=0, kind=I64 } -> x6 - v80 CallExt { binding_idx=0, args=[v77, v79], fp_arg_mask=0x0 } -> x0 - v81 Imm(-1) -> x7 - v82 CallExt { binding_idx=69, args=[v81], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b17) (exit_acc=v82) + v714 ImmData(1832) -> x0 + v715 Load { addr=v3, disp=0, kind=I64 } -> x0 + v716 BinopI { op=eq, lhs=v715, rhs_imm=144 } -> x0 + terminator Bz { cond=v716, target=b20, fall=b19 } (exit_acc=v716) block 19 start_pc=0 - v83 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b20) (exit_acc=v83) + v746 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v747 ImmData(1800) -> x13 + v748 Load { addr=v747, disp=0, kind=I64 } -> x0 + v749 BinopI { op=add, lhs=v748, rhs_imm=8 } -> x0 + v750 Store { addr=v747, disp=0, value=v749, kind=I64 } -> - + v751 Imm(5) -> x1 + v752 Store { addr=v749, disp=0, value=v751, kind=I64 } -> - + v753 Load { addr=v747, disp=0, kind=I64 } -> x0 + v754 BinopI { op=add, lhs=v753, rhs_imm=8 } -> x14 + v755 Store { addr=v747, disp=0, value=v754, kind=I64 } -> - + v756 Imm(0) -> x0 + v757 Imm(145) -> x7 + v758 Call { target_pc=7, args=[v757], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v759 LoadLocal { off=-2, kind=I64 } -> x0 + v760 Load { addr=v747, disp=0, kind=I64 } -> x0 + v761 Imm(8) -> x1 + v762 BinopI { op=add, lhs=v760, rhs_imm=8 } -> x0 + v763 Store { addr=v754, disp=0, value=v762, kind=I64 } -> - + v764 ImmData(1848) -> x0 + v765 Imm(1) -> x1 + v766 Store { addr=v764, disp=0, value=v765, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v766) block 20 start_pc=0 - terminator Jmp(b24) + v767 ImmData(1832) -> x0 + v768 Load { addr=v3, disp=0, kind=I64 } -> x0 + v769 BinopI { op=eq, lhs=v768, rhs_imm=145 } -> x0 + terminator Bz { cond=v769, target=b22, fall=b21 } (exit_acc=v769) block 21 start_pc=0 - v84 ImmData(1832) -> x0 - v85 Load { addr=v3, disp=0, kind=I64 } -> x0 - v86 BinopI { op=eq, lhs=v85, rhs_imm=134 } -> x0 - terminator Bz { cond=v86, target=b23, fall=b22 } (exit_acc=v86) + v770 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v771 ImmData(1800) -> x13 + v772 Load { addr=v771, disp=0, kind=I64 } -> x0 + v773 BinopI { op=add, lhs=v772, rhs_imm=8 } -> x0 + v774 Store { addr=v771, disp=0, value=v773, kind=I64 } -> - + v775 Imm(4) -> x1 + v776 Store { addr=v773, disp=0, value=v775, kind=I64 } -> - + v777 Load { addr=v771, disp=0, kind=I64 } -> x0 + v778 BinopI { op=add, lhs=v777, rhs_imm=8 } -> x14 + v779 Store { addr=v771, disp=0, value=v778, kind=I64 } -> - + v780 Imm(0) -> x0 + v781 Imm(146) -> x7 + v782 Call { target_pc=7, args=[v781], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v783 LoadLocal { off=-2, kind=I64 } -> x0 + v784 Load { addr=v771, disp=0, kind=I64 } -> x0 + v785 Imm(8) -> x1 + v786 BinopI { op=add, lhs=v784, rhs_imm=8 } -> x0 + v787 Store { addr=v778, disp=0, value=v786, kind=I64 } -> - + v788 ImmData(1848) -> x0 + v789 Imm(1) -> x1 + v790 Store { addr=v788, disp=0, value=v789, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v790) block 22 start_pc=0 - v87 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v88 ImmData(1848) -> x0 - v89 Imm(0) -> x1 - v90 Store { addr=v88, disp=0, value=v89, kind=I64 } -> - - terminator Jmp(b23) (exit_acc=v90) + v791 ImmData(1832) -> x0 + v792 Load { addr=v3, disp=0, kind=I64 } -> x0 + v793 BinopI { op=eq, lhs=v792, rhs_imm=146 } -> x0 + terminator Bz { cond=v793, target=b24, fall=b23 } (exit_acc=v793) block 23 start_pc=0 - terminator Jmp(b20) + v794 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v795 ImmData(1800) -> x13 + v796 Load { addr=v795, disp=0, kind=I64 } -> x0 + v797 BinopI { op=add, lhs=v796, rhs_imm=8 } -> x0 + v798 Store { addr=v795, disp=0, value=v797, kind=I64 } -> - + v799 Imm(13) -> x1 + v800 Store { addr=v797, disp=0, value=v799, kind=I64 } -> - + v801 Imm(147) -> x7 + v802 Call { target_pc=7, args=[v801], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v803 Load { addr=v795, disp=0, kind=I64 } -> x0 + v804 BinopI { op=add, lhs=v803, rhs_imm=8 } -> x0 + v805 Store { addr=v795, disp=0, value=v804, kind=I64 } -> - + v806 Imm(14) -> x1 + v807 Store { addr=v804, disp=0, value=v806, kind=I64 } -> - + v808 ImmData(1848) -> x0 + v809 Imm(1) -> x1 + v810 Store { addr=v808, disp=0, value=v809, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v810) block 24 start_pc=0 - v91 ImmData(1832) -> x0 - v92 Load { addr=v3, disp=0, kind=I64 } -> x0 - v93 BinopI { op=eq, lhs=v92, rhs_imm=159 } -> x0 - terminator Bz { cond=v93, target=b26, fall=b25 } (exit_acc=v93) + v811 ImmData(1832) -> x0 + v812 Load { addr=v3, disp=0, kind=I64 } -> x0 + v813 BinopI { op=eq, lhs=v812, rhs_imm=147 } -> x0 + terminator Bz { cond=v813, target=b26, fall=b25 } (exit_acc=v813) block 25 start_pc=0 - v94 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v95 ImmData(1848) -> x0 - v96 Load { addr=v95, disp=0, kind=I64 } -> x1 - v97 BinopI { op=add, lhs=v96, rhs_imm=2 } -> x1 - v98 Store { addr=v95, disp=0, value=v97, kind=I64 } -> - - terminator Jmp(b24) (exit_acc=v98) + v814 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v815 ImmData(1800) -> x13 + v816 Load { addr=v815, disp=0, kind=I64 } -> x0 + v817 BinopI { op=add, lhs=v816, rhs_imm=8 } -> x0 + v818 Store { addr=v815, disp=0, value=v817, kind=I64 } -> - + v819 Imm(13) -> x1 + v820 Store { addr=v817, disp=0, value=v819, kind=I64 } -> - + v821 Imm(148) -> x7 + v822 Call { target_pc=7, args=[v821], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v823 Load { addr=v815, disp=0, kind=I64 } -> x0 + v824 BinopI { op=add, lhs=v823, rhs_imm=8 } -> x0 + v825 Store { addr=v815, disp=0, value=v824, kind=I64 } -> - + v826 Imm(15) -> x1 + v827 Store { addr=v824, disp=0, value=v826, kind=I64 } -> - + v828 ImmData(1848) -> x0 + v829 Imm(1) -> x1 + v830 Store { addr=v828, disp=0, value=v829, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v830) block 26 start_pc=0 - v99 ImmData(1832) -> x0 - v100 Load { addr=v3, disp=0, kind=I64 } -> x0 - v101 BinopI { op=eq, lhs=v100, rhs_imm=41 } -> x0 - terminator Bz { cond=v101, target=b29, fall=b27 } (exit_acc=v101) + v831 ImmData(1832) -> x0 + v832 Load { addr=v3, disp=0, kind=I64 } -> x0 + v833 BinopI { op=eq, lhs=v832, rhs_imm=148 } -> x0 + terminator Bz { cond=v833, target=b28, fall=b27 } (exit_acc=v833) block 27 start_pc=0 - v102 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b28) (exit_acc=v102) + v834 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v835 ImmData(1800) -> x13 + v836 Load { addr=v835, disp=0, kind=I64 } -> x0 + v837 BinopI { op=add, lhs=v836, rhs_imm=8 } -> x0 + v838 Store { addr=v835, disp=0, value=v837, kind=I64 } -> - + v839 Imm(13) -> x1 + v840 Store { addr=v837, disp=0, value=v839, kind=I64 } -> - + v841 Imm(149) -> x7 + v842 Call { target_pc=7, args=[v841], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v843 Load { addr=v835, disp=0, kind=I64 } -> x0 + v844 BinopI { op=add, lhs=v843, rhs_imm=8 } -> x0 + v845 Store { addr=v835, disp=0, value=v844, kind=I64 } -> - + v846 Imm(16) -> x1 + v847 Store { addr=v844, disp=0, value=v846, kind=I64 } -> - + v848 ImmData(1848) -> x0 + v849 Imm(1) -> x1 + v850 Store { addr=v848, disp=0, value=v849, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v850) block 28 start_pc=0 - v103 ImmData(1800) -> x0 - v104 Load { addr=v103, disp=0, kind=I64 } -> x1 - v105 BinopI { op=add, lhs=v104, rhs_imm=8 } -> x1 - v106 Store { addr=v103, disp=0, value=v105, kind=I64 } -> - - v107 Imm(1) -> x2 - v108 Store { addr=v105, disp=0, value=v107, kind=I64 } -> - - v109 Load { addr=v103, disp=0, kind=I64 } -> x1 - v110 BinopI { op=add, lhs=v109, rhs_imm=8 } -> x13 - v111 Store { addr=v103, disp=0, value=v110, kind=I64 } -> - - v112 ImmData(1848) -> x0 - v113 Load { addr=v112, disp=0, kind=I64 } -> x0 - v114 BinopI { op=eq, lhs=v113, rhs_imm=0 } -> x0 - terminator Bz { cond=v114, target=b31, fall=b30 } (exit_acc=v114) + v851 ImmData(1832) -> x0 + v852 Load { addr=v3, disp=0, kind=I64 } -> x0 + v853 BinopI { op=eq, lhs=v852, rhs_imm=149 } -> x0 + terminator Bz { cond=v853, target=b30, fall=b29 } (exit_acc=v853) block 29 start_pc=0 - v115 ImmData(319) -> x7 - v116 ImmData(1864) -> x0 - v117 Load { addr=v116, disp=0, kind=I64 } -> x6 - v118 CallExt { binding_idx=0, args=[v115, v117], fp_arg_mask=0x0 } -> x0 - v119 Imm(-1) -> x7 - v120 CallExt { binding_idx=69, args=[v119], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b28) (exit_acc=v120) + v854 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v855 ImmData(1800) -> x13 + v856 Load { addr=v855, disp=0, kind=I64 } -> x0 + v857 BinopI { op=add, lhs=v856, rhs_imm=8 } -> x0 + v858 Store { addr=v855, disp=0, value=v857, kind=I64 } -> - + v859 Imm(13) -> x1 + v860 Store { addr=v857, disp=0, value=v859, kind=I64 } -> - + v861 Imm(151) -> x7 + v862 Call { target_pc=7, args=[v861], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v863 Load { addr=v855, disp=0, kind=I64 } -> x0 + v864 BinopI { op=add, lhs=v863, rhs_imm=8 } -> x0 + v865 Store { addr=v855, disp=0, value=v864, kind=I64 } -> - + v866 Imm(17) -> x1 + v867 Store { addr=v864, disp=0, value=v866, kind=I64 } -> - + v868 ImmData(1848) -> x0 + v869 Imm(1) -> x1 + v870 Store { addr=v868, disp=0, value=v869, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v870) block 30 start_pc=0 - v121 Imm(1) -> x1 - v122 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v121) + v871 ImmData(1832) -> x0 + v872 Load { addr=v3, disp=0, kind=I64 } -> x0 + v873 BinopI { op=eq, lhs=v872, rhs_imm=150 } -> x0 + terminator Bz { cond=v873, target=b32, fall=b31 } (exit_acc=v873) block 31 start_pc=0 - v123 Imm(8) -> x1 - v124 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v123) + v874 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v875 ImmData(1800) -> x13 + v876 Load { addr=v875, disp=0, kind=I64 } -> x0 + v877 BinopI { op=add, lhs=v876, rhs_imm=8 } -> x0 + v878 Store { addr=v875, disp=0, value=v877, kind=I64 } -> - + v879 Imm(13) -> x1 + v880 Store { addr=v877, disp=0, value=v879, kind=I64 } -> - + v881 Imm(151) -> x7 + v882 Call { target_pc=7, args=[v881], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v883 Load { addr=v875, disp=0, kind=I64 } -> x0 + v884 BinopI { op=add, lhs=v883, rhs_imm=8 } -> x0 + v885 Store { addr=v875, disp=0, value=v884, kind=I64 } -> - + v886 Imm(18) -> x1 + v887 Store { addr=v884, disp=0, value=v886, kind=I64 } -> - + v888 ImmData(1848) -> x0 + v889 Imm(1) -> x1 + v890 Store { addr=v888, disp=0, value=v889, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v890) block 32 start_pc=0 - v125 Phi { incoming=[b30:v121, b31:v123], kind=I64 } -> x1 - v126 LoadLocal { off=-6, kind=I64 } -> x0 - v127 Store { addr=v110, disp=0, value=v125, kind=I64 } -> - - v128 ImmData(1848) -> x0 - v129 Imm(1) -> x1 - v130 Store { addr=v128, disp=0, value=v129, kind=I64 } -> - - terminator Jmp(b14) (exit_acc=v130) + v891 ImmData(1832) -> x0 + v892 Load { addr=v3, disp=0, kind=I64 } -> x0 + v893 BinopI { op=eq, lhs=v892, rhs_imm=151 } -> x0 + terminator Bz { cond=v893, target=b34, fall=b33 } (exit_acc=v893) block 33 start_pc=0 - v131 ImmData(1816) -> x0 - v132 Load { addr=v131, disp=0, kind=I64 } -> x13 - v133 Imm(0) -> x0 - v134 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v135 ImmData(1832) -> x0 - v136 Load { addr=v3, disp=0, kind=I64 } -> x0 - v137 BinopI { op=eq, lhs=v136, rhs_imm=40 } -> x0 - terminator Bz { cond=v137, target=b38, fall=b36 } (exit_acc=v137) + v894 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v895 ImmData(1800) -> x13 + v896 Load { addr=v895, disp=0, kind=I64 } -> x0 + v897 BinopI { op=add, lhs=v896, rhs_imm=8 } -> x0 + v898 Store { addr=v895, disp=0, value=v897, kind=I64 } -> - + v899 Imm(13) -> x1 + v900 Store { addr=v897, disp=0, value=v899, kind=I64 } -> - + v901 Imm(155) -> x7 + v902 Call { target_pc=7, args=[v901], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v903 Load { addr=v895, disp=0, kind=I64 } -> x0 + v904 BinopI { op=add, lhs=v903, rhs_imm=8 } -> x0 + v905 Store { addr=v895, disp=0, value=v904, kind=I64 } -> - + v906 Imm(19) -> x1 + v907 Store { addr=v904, disp=0, value=v906, kind=I64 } -> - + v908 ImmData(1848) -> x0 + v909 Imm(1) -> x1 + v910 Store { addr=v908, disp=0, value=v909, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v910) block 34 start_pc=0 - terminator Jmp(b14) + v911 ImmData(1832) -> x0 + v912 Load { addr=v3, disp=0, kind=I64 } -> x0 + v913 BinopI { op=eq, lhs=v912, rhs_imm=152 } -> x0 + terminator Bz { cond=v913, target=b36, fall=b35 } (exit_acc=v913) block 35 start_pc=0 - v138 ImmData(1832) -> x0 - v139 Load { addr=v3, disp=0, kind=I64 } -> x0 - v140 BinopI { op=eq, lhs=v139, rhs_imm=40 } -> x0 - terminator Bz { cond=v140, target=b66, fall=b64 } (exit_acc=v140) + v914 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v915 ImmData(1800) -> x13 + v916 Load { addr=v915, disp=0, kind=I64 } -> x0 + v917 BinopI { op=add, lhs=v916, rhs_imm=8 } -> x0 + v918 Store { addr=v915, disp=0, value=v917, kind=I64 } -> - + v919 Imm(13) -> x1 + v920 Store { addr=v917, disp=0, value=v919, kind=I64 } -> - + v921 Imm(155) -> x7 + v922 Call { target_pc=7, args=[v921], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v923 Load { addr=v915, disp=0, kind=I64 } -> x0 + v924 BinopI { op=add, lhs=v923, rhs_imm=8 } -> x0 + v925 Store { addr=v915, disp=0, value=v924, kind=I64 } -> - + v926 Imm(20) -> x1 + v927 Store { addr=v924, disp=0, value=v926, kind=I64 } -> - + v928 ImmData(1848) -> x0 + v929 Imm(1) -> x1 + v930 Store { addr=v928, disp=0, value=v929, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v930) block 36 start_pc=0 - v141 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v142 Imm(0) -> x14 - v143 Imm(0) -> x0 - terminator Jmp(b39) (exit_acc=v142) + v931 ImmData(1832) -> x0 + v932 Load { addr=v3, disp=0, kind=I64 } -> x0 + v933 BinopI { op=eq, lhs=v932, rhs_imm=153 } -> x0 + terminator Bz { cond=v933, target=b38, fall=b37 } (exit_acc=v933) block 37 start_pc=0 - terminator Jmp(b34) + v934 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v935 ImmData(1800) -> x13 + v936 Load { addr=v935, disp=0, kind=I64 } -> x0 + v937 BinopI { op=add, lhs=v936, rhs_imm=8 } -> x0 + v938 Store { addr=v935, disp=0, value=v937, kind=I64 } -> - + v939 Imm(13) -> x1 + v940 Store { addr=v937, disp=0, value=v939, kind=I64 } -> - + v941 Imm(155) -> x7 + v942 Call { target_pc=7, args=[v941], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v943 Load { addr=v935, disp=0, kind=I64 } -> x0 + v944 BinopI { op=add, lhs=v943, rhs_imm=8 } -> x0 + v945 Store { addr=v935, disp=0, value=v944, kind=I64 } -> - + v946 Imm(21) -> x1 + v947 Store { addr=v944, disp=0, value=v946, kind=I64 } -> - + v948 ImmData(1848) -> x0 + v949 Imm(1) -> x1 + v950 Store { addr=v948, disp=0, value=v949, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v950) block 38 start_pc=0 - v144 LoadLocal { off=-2, kind=I64 } -> x0 - v145 Imm(24) -> x0 - v146 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 - v147 Load { addr=v132, disp=24, kind=I64 } -> x0 - v148 BinopI { op=eq, lhs=v147, rhs_imm=128 } -> x0 - terminator Bz { cond=v148, target=b54, fall=b52 } (exit_acc=v148) + v951 ImmData(1832) -> x0 + v952 Load { addr=v3, disp=0, kind=I64 } -> x0 + v953 BinopI { op=eq, lhs=v952, rhs_imm=154 } -> x0 + terminator Bz { cond=v953, target=b40, fall=b39 } (exit_acc=v953) block 39 start_pc=0 - v149 Phi { incoming=[b36:v142, b43:v162], kind=I64 } -> x14 - v150 ImmData(1832) -> x0 - v151 Load { addr=v3, disp=0, kind=I64 } -> x0 - v152 BinopI { op=ne, lhs=v151, rhs_imm=41 } -> x0 - terminator Bz { cond=v152, target=b41, fall=b40 } (exit_acc=v152) + v954 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v955 ImmData(1800) -> x13 + v956 Load { addr=v955, disp=0, kind=I64 } -> x0 + v957 BinopI { op=add, lhs=v956, rhs_imm=8 } -> x0 + v958 Store { addr=v955, disp=0, value=v957, kind=I64 } -> - + v959 Imm(13) -> x1 + v960 Store { addr=v957, disp=0, value=v959, kind=I64 } -> - + v961 Imm(155) -> x7 + v962 Call { target_pc=7, args=[v961], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v963 Load { addr=v955, disp=0, kind=I64 } -> x0 + v964 BinopI { op=add, lhs=v963, rhs_imm=8 } -> x0 + v965 Store { addr=v955, disp=0, value=v964, kind=I64 } -> - + v966 Imm(22) -> x1 + v967 Store { addr=v964, disp=0, value=v966, kind=I64 } -> - + v968 ImmData(1848) -> x0 + v969 Imm(1) -> x1 + v970 Store { addr=v968, disp=0, value=v969, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v970) block 40 start_pc=0 - v153 Imm(142) -> x7 - v154 Call { target_pc=7, args=[v153], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v155 ImmData(1800) -> x0 - v156 Load { addr=v155, disp=0, kind=I64 } -> x1 - v157 BinopI { op=add, lhs=v156, rhs_imm=8 } -> x1 - v158 Store { addr=v155, disp=0, value=v157, kind=I64 } -> - - v159 Imm(13) -> x0 - v160 Store { addr=v157, disp=0, value=v159, kind=I64 } -> - - v161 LoadLocal { off=-1, kind=I64 } -> x0 - v162 BinopI { op=add, lhs=v149, rhs_imm=1 } -> x14 - v163 Imm(0) -> x0 - v164 ImmData(1832) -> x0 - v165 Load { addr=v3, disp=0, kind=I64 } -> x0 - v166 BinopI { op=eq, lhs=v165, rhs_imm=44 } -> x0 - terminator Bz { cond=v166, target=b43, fall=b42 } (exit_acc=v166) + v971 ImmData(1832) -> x0 + v972 Load { addr=v3, disp=0, kind=I64 } -> x0 + v973 BinopI { op=eq, lhs=v972, rhs_imm=155 } -> x0 + terminator Bz { cond=v973, target=b42, fall=b41 } (exit_acc=v973) block 41 start_pc=0 - v167 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v168 LoadLocal { off=-2, kind=I64 } -> x0 - v169 Imm(24) -> x0 - v170 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 - v171 Load { addr=v132, disp=24, kind=I64 } -> x0 - v172 BinopI { op=eq, lhs=v171, rhs_imm=130 } -> x0 - terminator Bz { cond=v172, target=b46, fall=b44 } (exit_acc=v172) + v974 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v975 ImmData(1800) -> x13 + v976 Load { addr=v975, disp=0, kind=I64 } -> x0 + v977 BinopI { op=add, lhs=v976, rhs_imm=8 } -> x0 + v978 Store { addr=v975, disp=0, value=v977, kind=I64 } -> - + v979 Imm(13) -> x1 + v980 Store { addr=v977, disp=0, value=v979, kind=I64 } -> - + v981 Imm(157) -> x7 + v982 Call { target_pc=7, args=[v981], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v983 Load { addr=v975, disp=0, kind=I64 } -> x0 + v984 BinopI { op=add, lhs=v983, rhs_imm=8 } -> x0 + v985 Store { addr=v975, disp=0, value=v984, kind=I64 } -> - + v986 Imm(23) -> x1 + v987 Store { addr=v984, disp=0, value=v986, kind=I64 } -> - + v988 ImmData(1848) -> x0 + v989 Imm(1) -> x1 + v990 Store { addr=v988, disp=0, value=v989, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v990) block 42 start_pc=0 - v173 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b43) (exit_acc=v173) + v991 ImmData(1832) -> x0 + v992 Load { addr=v3, disp=0, kind=I64 } -> x0 + v993 BinopI { op=eq, lhs=v992, rhs_imm=156 } -> x0 + terminator Bz { cond=v993, target=b44, fall=b43 } (exit_acc=v993) block 43 start_pc=0 - terminator Jmp(b39) + v994 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v995 ImmData(1800) -> x13 + v996 Load { addr=v995, disp=0, kind=I64 } -> x0 + v997 BinopI { op=add, lhs=v996, rhs_imm=8 } -> x0 + v998 Store { addr=v995, disp=0, value=v997, kind=I64 } -> - + v999 Imm(13) -> x1 + v1000 Store { addr=v997, disp=0, value=v999, kind=I64 } -> - + v1001 Imm(157) -> x7 + v1002 Call { target_pc=7, args=[v1001], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1003 Load { addr=v995, disp=0, kind=I64 } -> x0 + v1004 BinopI { op=add, lhs=v1003, rhs_imm=8 } -> x0 + v1005 Store { addr=v995, disp=0, value=v1004, kind=I64 } -> - + v1006 Imm(24) -> x1 + v1007 Store { addr=v1004, disp=0, value=v1006, kind=I64 } -> - + v1008 ImmData(1848) -> x0 + v1009 Imm(1) -> x1 + v1010 Store { addr=v1008, disp=0, value=v1009, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1010) block 44 start_pc=0 - v174 ImmData(1800) -> x0 - v175 Load { addr=v174, disp=0, kind=I64 } -> x1 - v176 BinopI { op=add, lhs=v175, rhs_imm=8 } -> x1 - v177 Store { addr=v174, disp=0, value=v176, kind=I64 } -> - - v178 LoadLocal { off=-2, kind=I64 } -> x0 - v179 Imm(40) -> x0 - v180 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 - v181 Load { addr=v132, disp=40, kind=I64 } -> x0 - v182 Store { addr=v176, disp=0, value=v181, kind=I64 } -> - - terminator Jmp(b45) (exit_acc=v182) + v1011 ImmData(1832) -> x0 + v1012 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1013 BinopI { op=eq, lhs=v1012, rhs_imm=157 } -> x0 + terminator Bz { cond=v1013, target=b48, fall=b45 } (exit_acc=v1013) block 45 start_pc=0 - v183 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v149, target=b51, fall=b50 } (exit_acc=v149) + v1014 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1015 ImmData(1800) -> x0 + v1016 Load { addr=v1015, disp=0, kind=I64 } -> x1 + v1017 BinopI { op=add, lhs=v1016, rhs_imm=8 } -> x1 + v1018 Store { addr=v1015, disp=0, value=v1017, kind=I64 } -> - + v1019 Imm(13) -> x0 + v1020 Store { addr=v1017, disp=0, value=v1019, kind=I64 } -> - + v1021 Imm(159) -> x7 + v1022 Call { target_pc=7, args=[v1021], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1023 ImmData(1848) -> x0 + v1024 LoadLocal { off=-1, kind=I64 } -> x1 + v1025 Store { addr=v1023, disp=0, value=v649, kind=I64 } -> - + v1026 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 + terminator Bz { cond=v1026, target=b47, fall=b46 } (exit_acc=v1026) block 46 start_pc=0 - v184 LoadLocal { off=-2, kind=I64 } -> x0 - v185 Imm(24) -> x0 - v186 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 - v187 Load { addr=v132, disp=24, kind=I64 } -> x0 - v188 BinopI { op=eq, lhs=v187, rhs_imm=129 } -> x0 - terminator Bz { cond=v188, target=b49, fall=b47 } (exit_acc=v188) + v1030 ImmData(1800) -> x0 + v1031 Load { addr=v1030, disp=0, kind=I64 } -> x1 + v1032 BinopI { op=add, lhs=v1031, rhs_imm=8 } -> x1 + v1033 Store { addr=v1030, disp=0, value=v1032, kind=I64 } -> - + v1034 Imm(13) -> x2 + v1035 Store { addr=v1032, disp=0, value=v1034, kind=I64 } -> - + v1036 Load { addr=v1030, disp=0, kind=I64 } -> x1 + v1037 BinopI { op=add, lhs=v1036, rhs_imm=8 } -> x1 + v1038 Store { addr=v1030, disp=0, value=v1037, kind=I64 } -> - + v1039 Imm(1) -> x2 + v1040 Store { addr=v1037, disp=0, value=v1039, kind=I64 } -> - + v1041 Load { addr=v1030, disp=0, kind=I64 } -> x1 + v1042 BinopI { op=add, lhs=v1041, rhs_imm=8 } -> x1 + v1043 Store { addr=v1030, disp=0, value=v1042, kind=I64 } -> - + v1044 Imm(8) -> x2 + v1045 Store { addr=v1042, disp=0, value=v1044, kind=I64 } -> - + v1046 Load { addr=v1030, disp=0, kind=I64 } -> x1 + v1047 BinopI { op=add, lhs=v1046, rhs_imm=8 } -> x1 + v1048 Store { addr=v1030, disp=0, value=v1047, kind=I64 } -> - + v1049 Imm(27) -> x0 + v1050 Store { addr=v1047, disp=0, value=v1049, kind=I64 } -> - + terminator Jmp(b47) (exit_acc=v1050) block 47 start_pc=0 - v189 ImmData(1800) -> x0 - v190 Load { addr=v189, disp=0, kind=I64 } -> x1 - v191 BinopI { op=add, lhs=v190, rhs_imm=8 } -> x1 - v192 Store { addr=v189, disp=0, value=v191, kind=I64 } -> - - v193 Imm(3) -> x2 - v194 Store { addr=v191, disp=0, value=v193, kind=I64 } -> - - v195 Load { addr=v189, disp=0, kind=I64 } -> x1 - v196 BinopI { op=add, lhs=v195, rhs_imm=8 } -> x1 - v197 Store { addr=v189, disp=0, value=v196, kind=I64 } -> - - v198 LoadLocal { off=-2, kind=I64 } -> x0 - v199 Imm(40) -> x0 - v200 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 - v201 Load { addr=v132, disp=40, kind=I64 } -> x0 - v202 Store { addr=v196, disp=0, value=v201, kind=I64 } -> - - terminator Jmp(b48) (exit_acc=v202) + v1051 ImmData(1800) -> x0 + v1052 Load { addr=v1051, disp=0, kind=I64 } -> x1 + v1053 BinopI { op=add, lhs=v1052, rhs_imm=8 } -> x1 + v1054 Store { addr=v1051, disp=0, value=v1053, kind=I64 } -> - + v1055 Imm(25) -> x0 + v1056 Store { addr=v1053, disp=0, value=v1055, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1056) block 48 start_pc=0 - terminator Jmp(b45) + v1027 ImmData(1832) -> x0 + v1028 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1029 BinopI { op=eq, lhs=v1028, rhs_imm=158 } -> x0 + terminator Bz { cond=v1029, target=b57, fall=b49 } (exit_acc=v1029) block 49 start_pc=0 - v203 ImmData(355) -> x7 - v204 ImmData(1864) -> x0 - v205 Load { addr=v204, disp=0, kind=I64 } -> x6 - v206 CallExt { binding_idx=0, args=[v203, v205], fp_arg_mask=0x0 } -> x0 - v207 Imm(-1) -> x7 - v208 CallExt { binding_idx=69, args=[v207], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b48) (exit_acc=v208) + v1057 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1058 ImmData(1800) -> x0 + v1059 Load { addr=v1058, disp=0, kind=I64 } -> x1 + v1060 BinopI { op=add, lhs=v1059, rhs_imm=8 } -> x1 + v1061 Store { addr=v1058, disp=0, value=v1060, kind=I64 } -> - + v1062 Imm(13) -> x0 + v1063 Store { addr=v1060, disp=0, value=v1062, kind=I64 } -> - + v1064 Imm(159) -> x7 + v1065 Call { target_pc=7, args=[v1064], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1066 LoadLocal { off=-1, kind=I64 } -> x0 + v1067 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x1 + v1068 Imm(0) -> x0 + terminator Bz { cond=v1067, target=b56, fall=b50 } (exit_acc=v1067) block 50 start_pc=0 - v209 ImmData(1800) -> x0 - v210 Load { addr=v209, disp=0, kind=I64 } -> x1 - v211 BinopI { op=add, lhs=v210, rhs_imm=8 } -> x1 - v212 Store { addr=v209, disp=0, value=v211, kind=I64 } -> - - v213 Imm(7) -> x2 - v214 Store { addr=v211, disp=0, value=v213, kind=I64 } -> - - v215 Load { addr=v209, disp=0, kind=I64 } -> x1 - v216 BinopI { op=add, lhs=v215, rhs_imm=8 } -> x1 - v217 Store { addr=v209, disp=0, value=v216, kind=I64 } -> - - v218 LoadLocal { off=-1, kind=I64 } -> x0 - v219 Store { addr=v216, disp=0, value=v149, kind=I64 } -> - - terminator Jmp(b51) (exit_acc=v219) + v1072 LoadLocal { off=-1, kind=I64 } -> x0 + v1073 ImmData(1848) -> x0 + v1074 Load { addr=v1073, disp=0, kind=I64 } -> x0 + v1075 Binop { op=eq, lhs=v649, rhs=v1074 } -> x1 + v1076 Imm(0) -> x0 + terminator Jmp(b51) (exit_acc=v1075) block 51 start_pc=0 - v220 ImmData(1848) -> x0 - v221 LoadLocal { off=-2, kind=I64 } -> x1 - v222 Imm(32) -> x1 - v223 BinopI { op=add, lhs=v132, rhs_imm=32 } -> x1 - v224 Load { addr=v132, disp=32, kind=I64 } -> x1 - v225 Store { addr=v220, disp=0, value=v224, kind=I64 } -> - - terminator Jmp(b37) (exit_acc=v225) + v1077 Phi { incoming=[b56:v1067, b50:v1075], kind=I64 } -> x1 + v1078 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v1077, target=b53, fall=b52 } (exit_acc=v1077) block 52 start_pc=0 - v226 ImmData(1800) -> x0 - v227 Load { addr=v226, disp=0, kind=I64 } -> x1 - v228 BinopI { op=add, lhs=v227, rhs_imm=8 } -> x1 - v229 Store { addr=v226, disp=0, value=v228, kind=I64 } -> - - v230 Imm(1) -> x2 - v231 Store { addr=v228, disp=0, value=v230, kind=I64 } -> - - v232 Load { addr=v226, disp=0, kind=I64 } -> x1 - v233 BinopI { op=add, lhs=v232, rhs_imm=8 } -> x1 - v234 Store { addr=v226, disp=0, value=v233, kind=I64 } -> - - v235 LoadLocal { off=-2, kind=I64 } -> x0 - v236 Imm(40) -> x0 - v237 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 - v238 Load { addr=v132, disp=40, kind=I64 } -> x0 - v239 Store { addr=v233, disp=0, value=v238, kind=I64 } -> - - v240 ImmData(1848) -> x0 - v241 Store { addr=v240, disp=0, value=v230, kind=I64 } -> - - terminator Jmp(b53) (exit_acc=v241) + v1079 ImmData(1800) -> x0 + v1080 Load { addr=v1079, disp=0, kind=I64 } -> x1 + v1081 BinopI { op=add, lhs=v1080, rhs_imm=8 } -> x1 + v1082 Store { addr=v1079, disp=0, value=v1081, kind=I64 } -> - + v1083 Imm(26) -> x2 + v1084 Store { addr=v1081, disp=0, value=v1083, kind=I64 } -> - + v1085 Load { addr=v1079, disp=0, kind=I64 } -> x1 + v1086 BinopI { op=add, lhs=v1085, rhs_imm=8 } -> x1 + v1087 Store { addr=v1079, disp=0, value=v1086, kind=I64 } -> - + v1088 Imm(13) -> x2 + v1089 Store { addr=v1086, disp=0, value=v1088, kind=I64 } -> - + v1090 Load { addr=v1079, disp=0, kind=I64 } -> x1 + v1091 BinopI { op=add, lhs=v1090, rhs_imm=8 } -> x1 + v1092 Store { addr=v1079, disp=0, value=v1091, kind=I64 } -> - + v1093 Imm(1) -> x2 + v1094 Store { addr=v1091, disp=0, value=v1093, kind=I64 } -> - + v1095 Load { addr=v1079, disp=0, kind=I64 } -> x1 + v1096 BinopI { op=add, lhs=v1095, rhs_imm=8 } -> x1 + v1097 Store { addr=v1079, disp=0, value=v1096, kind=I64 } -> - + v1098 Imm(8) -> x6 + v1099 Store { addr=v1096, disp=0, value=v1098, kind=I64 } -> - + v1100 Load { addr=v1079, disp=0, kind=I64 } -> x1 + v1101 BinopI { op=add, lhs=v1100, rhs_imm=8 } -> x1 + v1102 Store { addr=v1079, disp=0, value=v1101, kind=I64 } -> - + v1103 Imm(28) -> x0 + v1104 Store { addr=v1101, disp=0, value=v1103, kind=I64 } -> - + v1105 ImmData(1848) -> x0 + v1106 Store { addr=v1105, disp=0, value=v1093, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1106) block 53 start_pc=0 - terminator Jmp(b37) + v1107 ImmData(1848) -> x0 + v1108 LoadLocal { off=-1, kind=I64 } -> x1 + v1109 Store { addr=v1107, disp=0, value=v649, kind=I64 } -> - + v1110 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 + terminator Bz { cond=v1110, target=b55, fall=b54 } (exit_acc=v1110) block 54 start_pc=0 - v242 LoadLocal { off=-2, kind=I64 } -> x0 - v243 Imm(24) -> x0 - v244 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 - v245 Load { addr=v132, disp=24, kind=I64 } -> x0 - v246 BinopI { op=eq, lhs=v245, rhs_imm=132 } -> x0 - terminator Bz { cond=v246, target=b57, fall=b55 } (exit_acc=v246) + v1111 ImmData(1800) -> x0 + v1112 Load { addr=v1111, disp=0, kind=I64 } -> x1 + v1113 BinopI { op=add, lhs=v1112, rhs_imm=8 } -> x1 + v1114 Store { addr=v1111, disp=0, value=v1113, kind=I64 } -> - + v1115 Imm(13) -> x2 + v1116 Store { addr=v1113, disp=0, value=v1115, kind=I64 } -> - + v1117 Load { addr=v1111, disp=0, kind=I64 } -> x1 + v1118 BinopI { op=add, lhs=v1117, rhs_imm=8 } -> x1 + v1119 Store { addr=v1111, disp=0, value=v1118, kind=I64 } -> - + v1120 Imm(1) -> x2 + v1121 Store { addr=v1118, disp=0, value=v1120, kind=I64 } -> - + v1122 Load { addr=v1111, disp=0, kind=I64 } -> x1 + v1123 BinopI { op=add, lhs=v1122, rhs_imm=8 } -> x1 + v1124 Store { addr=v1111, disp=0, value=v1123, kind=I64 } -> - + v1125 Imm(8) -> x2 + v1126 Store { addr=v1123, disp=0, value=v1125, kind=I64 } -> - + v1127 Load { addr=v1111, disp=0, kind=I64 } -> x1 + v1128 BinopI { op=add, lhs=v1127, rhs_imm=8 } -> x1 + v1129 Store { addr=v1111, disp=0, value=v1128, kind=I64 } -> - + v1130 Imm(27) -> x2 + v1131 Store { addr=v1128, disp=0, value=v1130, kind=I64 } -> - + v1132 Load { addr=v1111, disp=0, kind=I64 } -> x1 + v1133 BinopI { op=add, lhs=v1132, rhs_imm=8 } -> x1 + v1134 Store { addr=v1111, disp=0, value=v1133, kind=I64 } -> - + v1135 Imm(26) -> x0 + v1136 Store { addr=v1133, disp=0, value=v1135, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1136) block 55 start_pc=0 - v247 ImmData(1800) -> x0 - v248 Load { addr=v247, disp=0, kind=I64 } -> x1 - v249 BinopI { op=add, lhs=v248, rhs_imm=8 } -> x1 - v250 Store { addr=v247, disp=0, value=v249, kind=I64 } -> - - v251 Imm(0) -> x2 - v252 Store { addr=v249, disp=0, value=v251, kind=I64 } -> - - v253 Load { addr=v247, disp=0, kind=I64 } -> x1 - v254 BinopI { op=add, lhs=v253, rhs_imm=8 } -> x1 - v255 Store { addr=v247, disp=0, value=v254, kind=I64 } -> - - v256 ImmData(1856) -> x0 - v257 Load { addr=v256, disp=0, kind=I64 } -> x0 - v258 LoadLocal { off=-2, kind=I64 } -> x2 - v259 Imm(40) -> x2 - v260 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x2 - v261 Load { addr=v132, disp=40, kind=I64 } -> x2 - v262 Binop { op=sub, lhs=v257, rhs=v261 } -> x0 - v263 Store { addr=v254, disp=0, value=v262, kind=I64 } -> - - terminator Jmp(b56) (exit_acc=v263) + v1137 ImmData(1800) -> x0 + v1138 Load { addr=v1137, disp=0, kind=I64 } -> x1 + v1139 BinopI { op=add, lhs=v1138, rhs_imm=8 } -> x1 + v1140 Store { addr=v1137, disp=0, value=v1139, kind=I64 } -> - + v1141 Imm(26) -> x0 + v1142 Store { addr=v1139, disp=0, value=v1141, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1142) block 56 start_pc=0 - v264 ImmData(1800) -> x0 - v265 Load { addr=v264, disp=0, kind=I64 } -> x1 - v266 BinopI { op=add, lhs=v265, rhs_imm=8 } -> x14 - v267 Store { addr=v264, disp=0, value=v266, kind=I64 } -> - - v268 ImmData(1848) -> x0 - v269 LoadLocal { off=-2, kind=I64 } -> x1 - v270 Imm(32) -> x1 - v271 BinopI { op=add, lhs=v132, rhs_imm=32 } -> x1 - v272 Load { addr=v132, disp=32, kind=I64 } -> x1 - v273 Store { addr=v268, disp=0, value=v272, kind=I64 } -> - - v274 BinopI { op=eq, lhs=v272, rhs_imm=0 } -> x0 - terminator Bz { cond=v274, target=b62, fall=b61 } (exit_acc=v274) + terminator Jmp(b51) block 57 start_pc=0 - v275 LoadLocal { off=-2, kind=I64 } -> x0 - v276 Imm(24) -> x0 - v277 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 - v278 Load { addr=v132, disp=24, kind=I64 } -> x0 - v279 BinopI { op=eq, lhs=v278, rhs_imm=131 } -> x0 - terminator Bz { cond=v279, target=b60, fall=b58 } (exit_acc=v279) + v1069 ImmData(1832) -> x0 + v1070 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1071 BinopI { op=eq, lhs=v1070, rhs_imm=159 } -> x0 + terminator Bz { cond=v1071, target=b59, fall=b58 } (exit_acc=v1071) block 58 start_pc=0 - v280 ImmData(1800) -> x0 - v281 Load { addr=v280, disp=0, kind=I64 } -> x1 - v282 BinopI { op=add, lhs=v281, rhs_imm=8 } -> x1 - v283 Store { addr=v280, disp=0, value=v282, kind=I64 } -> - - v284 Imm(1) -> x2 - v285 Store { addr=v282, disp=0, value=v284, kind=I64 } -> - - v286 Load { addr=v280, disp=0, kind=I64 } -> x1 - v287 BinopI { op=add, lhs=v286, rhs_imm=8 } -> x1 - v288 Store { addr=v280, disp=0, value=v287, kind=I64 } -> - - v289 LoadLocal { off=-2, kind=I64 } -> x0 - v290 Imm(40) -> x0 - v291 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 - v292 Load { addr=v132, disp=40, kind=I64 } -> x0 - v293 Store { addr=v287, disp=0, value=v292, kind=I64 } -> - - terminator Jmp(b59) (exit_acc=v293) + v1143 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1144 ImmData(1800) -> x13 + v1145 Load { addr=v1144, disp=0, kind=I64 } -> x0 + v1146 BinopI { op=add, lhs=v1145, rhs_imm=8 } -> x0 + v1147 Store { addr=v1144, disp=0, value=v1146, kind=I64 } -> - + v1148 Imm(13) -> x1 + v1149 Store { addr=v1146, disp=0, value=v1148, kind=I64 } -> - + v1150 Imm(162) -> x7 + v1151 Call { target_pc=7, args=[v1150], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1152 Load { addr=v1144, disp=0, kind=I64 } -> x0 + v1153 BinopI { op=add, lhs=v1152, rhs_imm=8 } -> x0 + v1154 Store { addr=v1144, disp=0, value=v1153, kind=I64 } -> - + v1155 Imm(27) -> x1 + v1156 Store { addr=v1153, disp=0, value=v1155, kind=I64 } -> - + v1157 ImmData(1848) -> x0 + v1158 Imm(1) -> x1 + v1159 Store { addr=v1157, disp=0, value=v1158, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1159) block 59 start_pc=0 - terminator Jmp(b56) + v1160 ImmData(1832) -> x0 + v1161 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1162 BinopI { op=eq, lhs=v1161, rhs_imm=160 } -> x0 + terminator Bz { cond=v1162, target=b61, fall=b60 } (exit_acc=v1162) block 60 start_pc=0 - v294 ImmData(378) -> x7 - v295 ImmData(1864) -> x0 - v296 Load { addr=v295, disp=0, kind=I64 } -> x6 - v297 CallExt { binding_idx=0, args=[v294, v296], fp_arg_mask=0x0 } -> x0 - v298 Imm(-1) -> x7 - v299 CallExt { binding_idx=69, args=[v298], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b59) (exit_acc=v299) + v1163 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1164 ImmData(1800) -> x13 + v1165 Load { addr=v1164, disp=0, kind=I64 } -> x0 + v1166 BinopI { op=add, lhs=v1165, rhs_imm=8 } -> x0 + v1167 Store { addr=v1164, disp=0, value=v1166, kind=I64 } -> - + v1168 Imm(13) -> x1 + v1169 Store { addr=v1166, disp=0, value=v1168, kind=I64 } -> - + v1170 Imm(162) -> x7 + v1171 Call { target_pc=7, args=[v1170], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1172 Load { addr=v1164, disp=0, kind=I64 } -> x0 + v1173 BinopI { op=add, lhs=v1172, rhs_imm=8 } -> x0 + v1174 Store { addr=v1164, disp=0, value=v1173, kind=I64 } -> - + v1175 Imm(28) -> x1 + v1176 Store { addr=v1173, disp=0, value=v1175, kind=I64 } -> - + v1177 ImmData(1848) -> x0 + v1178 Imm(1) -> x1 + v1179 Store { addr=v1177, disp=0, value=v1178, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1179) block 61 start_pc=0 - v300 Imm(10) -> x1 - v301 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v300) + v1180 ImmData(1832) -> x0 + v1181 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1182 BinopI { op=eq, lhs=v1181, rhs_imm=161 } -> x0 + terminator Bz { cond=v1182, target=b63, fall=b62 } (exit_acc=v1182) block 62 start_pc=0 - v302 Imm(9) -> x1 - v303 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v302) + v1183 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1184 ImmData(1800) -> x13 + v1185 Load { addr=v1184, disp=0, kind=I64 } -> x0 + v1186 BinopI { op=add, lhs=v1185, rhs_imm=8 } -> x0 + v1187 Store { addr=v1184, disp=0, value=v1186, kind=I64 } -> - + v1188 Imm(13) -> x1 + v1189 Store { addr=v1186, disp=0, value=v1188, kind=I64 } -> - + v1190 Imm(162) -> x7 + v1191 Call { target_pc=7, args=[v1190], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1192 Load { addr=v1184, disp=0, kind=I64 } -> x0 + v1193 BinopI { op=add, lhs=v1192, rhs_imm=8 } -> x0 + v1194 Store { addr=v1184, disp=0, value=v1193, kind=I64 } -> - + v1195 Imm(29) -> x1 + v1196 Store { addr=v1193, disp=0, value=v1195, kind=I64 } -> - + v1197 ImmData(1848) -> x0 + v1198 Imm(1) -> x1 + v1199 Store { addr=v1197, disp=0, value=v1198, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1199) block 63 start_pc=0 - v304 Phi { incoming=[b61:v300, b62:v302], kind=I64 } -> x1 - v305 LoadLocal { off=-7, kind=I64 } -> x0 - v306 Store { addr=v266, disp=0, value=v304, kind=I64 } -> - - terminator Jmp(b53) (exit_acc=v306) + v1200 ImmData(1832) -> x0 + v1201 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1202 BinopI { op=eq, lhs=v1201, rhs_imm=162 } -> x1 + v1203 Imm(0) -> x0 + terminator Bnz { cond=v1202, target=b99, fall=b64 } (exit_acc=v1202) block 64 start_pc=0 - v307 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v308 ImmData(1832) -> x0 - v309 Load { addr=v3, disp=0, kind=I64 } -> x0 - v310 BinopI { op=eq, lhs=v309, rhs_imm=138 } -> x13 - v311 Imm(0) -> x0 - terminator Bnz { cond=v310, target=b260, fall=b67 } (exit_acc=v310) + v1204 ImmData(1832) -> x0 + v1205 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1206 BinopI { op=eq, lhs=v1205, rhs_imm=163 } -> x1 + v1207 Imm(0) -> x0 + terminator Jmp(b65) (exit_acc=v1206) block 65 start_pc=0 - terminator Jmp(b34) + v1208 Phi { incoming=[b99:v1202, b64:v1206], kind=I64 } -> x1 + v1209 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v1208, target=b87, fall=b66 } (exit_acc=v1208) block 66 start_pc=0 - v312 ImmData(1832) -> x0 - v313 Load { addr=v3, disp=0, kind=I64 } -> x0 - v314 BinopI { op=eq, lhs=v313, rhs_imm=159 } -> x0 - terminator Bz { cond=v314, target=b86, fall=b84 } (exit_acc=v314) + v1210 ImmData(1800) -> x0 + v1211 Load { addr=v1210, disp=0, kind=I64 } -> x0 + v1212 Load { addr=v1211, disp=0, kind=I64 } -> x0 + v1213 BinopI { op=eq, lhs=v1212, rhs_imm=10 } -> x0 + terminator Bz { cond=v1213, target=b84, fall=b67 } (exit_acc=v1213) block 67 start_pc=0 - v315 ImmData(1832) -> x0 - v316 Load { addr=v3, disp=0, kind=I64 } -> x0 - v317 BinopI { op=eq, lhs=v316, rhs_imm=134 } -> x13 - v318 Imm(0) -> x0 - terminator Jmp(b68) (exit_acc=v317) + v1217 ImmData(1800) -> x0 + v1218 Load { addr=v1217, disp=0, kind=I64 } -> x1 + v1219 Imm(13) -> x2 + v1220 Store { addr=v1218, disp=0, value=v1219, kind=I64 } -> - + v1221 Load { addr=v1217, disp=0, kind=I64 } -> x1 + v1222 BinopI { op=add, lhs=v1221, rhs_imm=8 } -> x1 + v1223 Store { addr=v1217, disp=0, value=v1222, kind=I64 } -> - + v1224 Imm(10) -> x0 + v1225 Store { addr=v1222, disp=0, value=v1224, kind=I64 } -> - + terminator Jmp(b68) (exit_acc=v1225) block 68 start_pc=0 - v319 Phi { incoming=[b260:v310, b67:v317], kind=I64 } -> x13 - v320 LoadLocal { off=-8, kind=I64 } -> x0 - terminator Bz { cond=v319, target=b71, fall=b69 } (exit_acc=v319) + v1226 ImmData(1800) -> x0 + v1227 Load { addr=v1226, disp=0, kind=I64 } -> x1 + v1228 BinopI { op=add, lhs=v1227, rhs_imm=8 } -> x1 + v1229 Store { addr=v1226, disp=0, value=v1228, kind=I64 } -> - + v1230 Imm(13) -> x2 + v1231 Store { addr=v1228, disp=0, value=v1230, kind=I64 } -> - + v1232 Load { addr=v1226, disp=0, kind=I64 } -> x1 + v1233 BinopI { op=add, lhs=v1232, rhs_imm=8 } -> x1 + v1234 Store { addr=v1226, disp=0, value=v1233, kind=I64 } -> - + v1235 Imm(1) -> x2 + v1236 Store { addr=v1233, disp=0, value=v1235, kind=I64 } -> - + v1237 Load { addr=v1226, disp=0, kind=I64 } -> x1 + v1238 BinopI { op=add, lhs=v1237, rhs_imm=8 } -> x1 + v1239 Store { addr=v1226, disp=0, value=v1238, kind=I64 } -> - + v1240 ImmData(1848) -> x0 + v1241 Load { addr=v1240, disp=0, kind=I64 } -> x0 + v1242 BinopI { op=gt, lhs=v1241, rhs_imm=2 } -> x0 + terminator Bz { cond=v1242, target=b83, fall=b69 } (exit_acc=v1242) block 69 start_pc=0 - v321 ImmData(1832) -> x0 - v322 Load { addr=v3, disp=0, kind=I64 } -> x0 - v323 BinopI { op=eq, lhs=v322, rhs_imm=138 } -> x0 - terminator Bz { cond=v323, target=b73, fall=b72 } (exit_acc=v323) + v1262 Imm(8) -> x2 + v1263 Imm(0) -> x0 + terminator Jmp(b70) (exit_acc=v1262) block 70 start_pc=0 - terminator Jmp(b65) + v1266 Phi { incoming=[b69:v1262, b83:v1264], kind=I64 } -> x2 + v1267 LoadLocal { off=-20, kind=I64 } -> x0 + v1268 Store { addr=v1238, disp=0, value=v1266, kind=I64 } -> - + v1269 ImmData(1800) -> x0 + v1270 Load { addr=v1269, disp=0, kind=I64 } -> x1 + v1271 BinopI { op=add, lhs=v1270, rhs_imm=8 } -> x1 + v1272 Store { addr=v1269, disp=0, value=v1271, kind=I64 } -> - + v1273 ImmData(1832) -> x0 + v1274 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1275 BinopI { op=eq, lhs=v1274, rhs_imm=162 } -> x0 + terminator Bz { cond=v1275, target=b82, fall=b71 } (exit_acc=v1275) block 71 start_pc=0 - v324 Imm(142) -> x7 - v325 Call { target_pc=7, args=[v324], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v326 ImmData(1832) -> x0 - v327 Load { addr=v3, disp=0, kind=I64 } -> x0 - v328 BinopI { op=eq, lhs=v327, rhs_imm=41 } -> x0 - terminator Bz { cond=v328, target=b83, fall=b81 } (exit_acc=v328) + v1276 Imm(25) -> x2 + v1277 Imm(0) -> x0 + terminator Jmp(b72) (exit_acc=v1276) block 72 start_pc=0 - v329 Imm(1) -> x13 - v330 Imm(0) -> x0 - terminator Jmp(b74) (exit_acc=v329) + v1280 Phi { incoming=[b71:v1276, b82:v1278], kind=I64 } -> x2 + v1281 LoadLocal { off=-21, kind=I64 } -> x0 + v1282 Store { addr=v1271, disp=0, value=v1280, kind=I64 } -> - + v1283 ImmData(1800) -> x0 + v1284 Load { addr=v1283, disp=0, kind=I64 } -> x1 + v1285 BinopI { op=add, lhs=v1284, rhs_imm=8 } -> x1 + v1286 Store { addr=v1283, disp=0, value=v1285, kind=I64 } -> - + v1287 ImmData(1848) -> x0 + v1288 Load { addr=v1287, disp=0, kind=I64 } -> x0 + v1289 BinopI { op=eq, lhs=v1288, rhs_imm=0 } -> x0 + terminator Bz { cond=v1289, target=b81, fall=b73 } (exit_acc=v1289) block 73 start_pc=0 - v331 Imm(0) -> x13 - v332 Imm(0) -> x0 - terminator Jmp(b74) (exit_acc=v331) + v1290 Imm(12) -> x2 + v1291 Imm(0) -> x0 + terminator Jmp(b74) (exit_acc=v1290) block 74 start_pc=0 - v333 Phi { incoming=[b72:v329, b73:v331], kind=I64 } -> x13 - v334 LoadLocal { off=-9, kind=I64 } -> x0 - v335 Imm(0) -> x0 - v336 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b75) (exit_acc=v336) + v1294 Phi { incoming=[b73:v1290, b81:v1292], kind=I64 } -> x2 + v1295 LoadLocal { off=-22, kind=I64 } -> x0 + v1296 Store { addr=v1285, disp=0, value=v1294, kind=I64 } -> - + v1297 ImmData(1800) -> x0 + v1298 Load { addr=v1297, disp=0, kind=I64 } -> x1 + v1299 BinopI { op=add, lhs=v1298, rhs_imm=8 } -> x1 + v1300 Store { addr=v1297, disp=0, value=v1299, kind=I64 } -> - + v1301 Imm(13) -> x2 + v1302 Store { addr=v1299, disp=0, value=v1301, kind=I64 } -> - + v1303 Load { addr=v1297, disp=0, kind=I64 } -> x1 + v1304 BinopI { op=add, lhs=v1303, rhs_imm=8 } -> x1 + v1305 Store { addr=v1297, disp=0, value=v1304, kind=I64 } -> - + v1306 Imm(1) -> x2 + v1307 Store { addr=v1304, disp=0, value=v1306, kind=I64 } -> - + v1308 Load { addr=v1297, disp=0, kind=I64 } -> x1 + v1309 BinopI { op=add, lhs=v1308, rhs_imm=8 } -> x1 + v1310 Store { addr=v1297, disp=0, value=v1309, kind=I64 } -> - + v1311 ImmData(1848) -> x0 + v1312 Load { addr=v1311, disp=0, kind=I64 } -> x0 + v1313 BinopI { op=gt, lhs=v1312, rhs_imm=2 } -> x0 + terminator Bz { cond=v1313, target=b80, fall=b75 } (exit_acc=v1313) block 75 start_pc=0 - v337 Phi { incoming=[b74:v333, b76:v343], kind=I64 } -> x13 - v338 ImmData(1832) -> x0 - v339 Load { addr=v3, disp=0, kind=I64 } -> x0 - v340 BinopI { op=eq, lhs=v339, rhs_imm=159 } -> x0 - terminator Bz { cond=v340, target=b77, fall=b76 } (exit_acc=v340) + v1314 Imm(8) -> x2 + v1315 Imm(0) -> x0 + terminator Jmp(b76) (exit_acc=v1314) block 76 start_pc=0 - v341 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v342 LoadLocal { off=-1, kind=I64 } -> x0 - v343 BinopI { op=add, lhs=v337, rhs_imm=2 } -> x13 - v344 Imm(0) -> x0 - terminator Jmp(b75) (exit_acc=v343) + v1318 Phi { incoming=[b75:v1314, b80:v1316], kind=I64 } -> x2 + v1319 LoadLocal { off=-23, kind=I64 } -> x0 + v1320 Store { addr=v1309, disp=0, value=v1318, kind=I64 } -> - + v1321 ImmData(1800) -> x0 + v1322 Load { addr=v1321, disp=0, kind=I64 } -> x1 + v1323 BinopI { op=add, lhs=v1322, rhs_imm=8 } -> x1 + v1324 Store { addr=v1321, disp=0, value=v1323, kind=I64 } -> - + v1325 ImmData(1832) -> x0 + v1326 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1327 BinopI { op=eq, lhs=v1326, rhs_imm=162 } -> x0 + terminator Bz { cond=v1327, target=b79, fall=b77 } (exit_acc=v1327) block 77 start_pc=0 - v345 ImmData(1832) -> x0 - v346 Load { addr=v3, disp=0, kind=I64 } -> x0 - v347 BinopI { op=eq, lhs=v346, rhs_imm=41 } -> x0 - terminator Bz { cond=v347, target=b80, fall=b78 } (exit_acc=v347) + v1328 Imm(26) -> x2 + v1329 Imm(0) -> x0 + terminator Jmp(b78) (exit_acc=v1328) block 78 start_pc=0 - v348 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b79) (exit_acc=v348) + v1332 Phi { incoming=[b77:v1328, b79:v1330], kind=I64 } -> x2 + v1333 LoadLocal { off=-24, kind=I64 } -> x0 + v1334 Store { addr=v1323, disp=0, value=v1332, kind=I64 } -> - + v1335 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v1335) block 79 start_pc=0 - v349 Imm(162) -> x7 - v350 Call { target_pc=7, args=[v349], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v351 ImmData(1848) -> x0 - v352 LoadLocal { off=-1, kind=I64 } -> x1 - v353 Store { addr=v351, disp=0, value=v337, kind=I64 } -> - - terminator Jmp(b70) (exit_acc=v353) + v1330 Imm(25) -> x2 + v1331 Imm(0) -> x0 + terminator Jmp(b78) (exit_acc=v1330) block 80 start_pc=0 - v354 ImmData(402) -> x7 - v355 ImmData(1864) -> x0 - v356 Load { addr=v355, disp=0, kind=I64 } -> x6 - v357 CallExt { binding_idx=0, args=[v354, v356], fp_arg_mask=0x0 } -> x0 - v358 Imm(-1) -> x7 - v359 CallExt { binding_idx=69, args=[v358], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b79) (exit_acc=v359) + v1316 Imm(1) -> x2 + v1317 Imm(0) -> x0 + terminator Jmp(b76) (exit_acc=v1316) block 81 start_pc=0 - v360 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b82) (exit_acc=v360) + v1292 Imm(11) -> x2 + v1293 Imm(0) -> x0 + terminator Jmp(b74) (exit_acc=v1292) block 82 start_pc=0 - terminator Jmp(b70) + v1278 Imm(26) -> x2 + v1279 Imm(0) -> x0 + terminator Jmp(b72) (exit_acc=v1278) block 83 start_pc=0 - v361 ImmData(416) -> x7 - v362 ImmData(1864) -> x0 - v363 Load { addr=v362, disp=0, kind=I64 } -> x6 - v364 CallExt { binding_idx=0, args=[v361, v363], fp_arg_mask=0x0 } -> x0 - v365 Imm(-1) -> x7 - v366 CallExt { binding_idx=69, args=[v365], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b82) (exit_acc=v366) + v1264 Imm(1) -> x2 + v1265 Imm(0) -> x0 + terminator Jmp(b70) (exit_acc=v1264) block 84 start_pc=0 - v367 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v368 Imm(162) -> x7 - v369 Call { target_pc=7, args=[v368], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v370 ImmData(1848) -> x0 - v371 Load { addr=v370, disp=0, kind=I64 } -> x0 - v372 BinopI { op=gt, lhs=v371, rhs_imm=1 } -> x0 - terminator Bz { cond=v372, target=b89, fall=b87 } (exit_acc=v372) + v1243 ImmData(1800) -> x0 + v1244 Load { addr=v1243, disp=0, kind=I64 } -> x0 + v1245 Load { addr=v1244, disp=0, kind=I64 } -> x0 + v1246 BinopI { op=eq, lhs=v1245, rhs_imm=9 } -> x0 + terminator Bz { cond=v1246, target=b86, fall=b85 } (exit_acc=v1246) block 85 start_pc=0 - terminator Jmp(b65) + v1247 ImmData(1800) -> x0 + v1248 Load { addr=v1247, disp=0, kind=I64 } -> x1 + v1249 Imm(13) -> x2 + v1250 Store { addr=v1248, disp=0, value=v1249, kind=I64 } -> - + v1251 Load { addr=v1247, disp=0, kind=I64 } -> x1 + v1252 BinopI { op=add, lhs=v1251, rhs_imm=8 } -> x1 + v1253 Store { addr=v1247, disp=0, value=v1252, kind=I64 } -> - + v1254 Imm(9) -> x0 + v1255 Store { addr=v1252, disp=0, value=v1254, kind=I64 } -> - + terminator Jmp(b68) (exit_acc=v1255) block 86 start_pc=0 - v373 ImmData(1832) -> x0 - v374 Load { addr=v3, disp=0, kind=I64 } -> x0 - v375 BinopI { op=eq, lhs=v374, rhs_imm=148 } -> x0 - terminator Bz { cond=v375, target=b95, fall=b93 } (exit_acc=v375) + v1256 ImmData(597) -> x7 + v1257 ImmData(1864) -> x0 + v1258 Load { addr=v1257, disp=0, kind=I64 } -> x6 + v1259 CallExt { binding_idx=0, args=[v1256, v1258], fp_arg_mask=0x0 } -> x0 + v1260 Imm(-1) -> x7 + v1261 CallExt { binding_idx=69, args=[v1260], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b68) (exit_acc=v1261) block 87 start_pc=0 - v376 ImmData(1848) -> x0 - v377 Load { addr=v376, disp=0, kind=I64 } -> x1 - v378 BinopI { op=sub, lhs=v377, rhs_imm=2 } -> x1 - v379 Store { addr=v376, disp=0, value=v378, kind=I64 } -> - - terminator Jmp(b88) (exit_acc=v379) - block 88 start_pc=0 - v380 ImmData(1800) -> x0 - v381 Load { addr=v380, disp=0, kind=I64 } -> x1 - v382 BinopI { op=add, lhs=v381, rhs_imm=8 } -> x13 - v383 Store { addr=v380, disp=0, value=v382, kind=I64 } -> - - v384 ImmData(1848) -> x0 - v385 Load { addr=v384, disp=0, kind=I64 } -> x0 - v386 BinopI { op=eq, lhs=v385, rhs_imm=0 } -> x0 - terminator Bz { cond=v386, target=b91, fall=b90 } (exit_acc=v386) + v1214 ImmData(1832) -> x0 + v1215 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1216 BinopI { op=eq, lhs=v1215, rhs_imm=164 } -> x0 + terminator Bz { cond=v1216, target=b100, fall=b88 } (exit_acc=v1216) + block 88 start_pc=0 + v1336 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1337 ImmData(1800) -> x0 + v1338 Load { addr=v1337, disp=0, kind=I64 } -> x1 + v1339 BinopI { op=add, lhs=v1338, rhs_imm=8 } -> x1 + v1340 Store { addr=v1337, disp=0, value=v1339, kind=I64 } -> - + v1341 Imm(13) -> x0 + v1342 Store { addr=v1339, disp=0, value=v1341, kind=I64 } -> - + v1343 Imm(142) -> x7 + v1344 Call { target_pc=7, args=[v1343], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v1345 ImmData(1832) -> x0 + v1346 Load { addr=v3, disp=0, kind=I64 } -> x0 + v1347 BinopI { op=eq, lhs=v1346, rhs_imm=93 } -> x0 + terminator Bz { cond=v1347, target=b98, fall=b89 } (exit_acc=v1347) block 89 start_pc=0 - v387 ImmData(442) -> x7 - v388 ImmData(1864) -> x0 - v389 Load { addr=v388, disp=0, kind=I64 } -> x6 - v390 CallExt { binding_idx=0, args=[v387, v389], fp_arg_mask=0x0 } -> x0 - v391 Imm(-1) -> x7 - v392 CallExt { binding_idx=69, args=[v391], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b88) (exit_acc=v392) + v1356 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b90) (exit_acc=v1356) block 90 start_pc=0 - v393 Imm(10) -> x1 - v394 Imm(0) -> x0 - terminator Jmp(b92) (exit_acc=v393) + v1357 LoadLocal { off=-1, kind=I64 } -> x0 + v1358 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 + terminator Bz { cond=v1358, target=b96, fall=b91 } (exit_acc=v1358) block 91 start_pc=0 - v395 Imm(9) -> x1 - v396 Imm(0) -> x0 - terminator Jmp(b92) (exit_acc=v395) + v1365 ImmData(1800) -> x0 + v1366 Load { addr=v1365, disp=0, kind=I64 } -> x1 + v1367 BinopI { op=add, lhs=v1366, rhs_imm=8 } -> x1 + v1368 Store { addr=v1365, disp=0, value=v1367, kind=I64 } -> - + v1369 Imm(13) -> x2 + v1370 Store { addr=v1367, disp=0, value=v1369, kind=I64 } -> - + v1371 Load { addr=v1365, disp=0, kind=I64 } -> x1 + v1372 BinopI { op=add, lhs=v1371, rhs_imm=8 } -> x1 + v1373 Store { addr=v1365, disp=0, value=v1372, kind=I64 } -> - + v1374 Imm(1) -> x2 + v1375 Store { addr=v1372, disp=0, value=v1374, kind=I64 } -> - + v1376 Load { addr=v1365, disp=0, kind=I64 } -> x1 + v1377 BinopI { op=add, lhs=v1376, rhs_imm=8 } -> x1 + v1378 Store { addr=v1365, disp=0, value=v1377, kind=I64 } -> - + v1379 Imm(8) -> x2 + v1380 Store { addr=v1377, disp=0, value=v1379, kind=I64 } -> - + v1381 Load { addr=v1365, disp=0, kind=I64 } -> x1 + v1382 BinopI { op=add, lhs=v1381, rhs_imm=8 } -> x1 + v1383 Store { addr=v1365, disp=0, value=v1382, kind=I64 } -> - + v1384 Imm(27) -> x0 + v1385 Store { addr=v1382, disp=0, value=v1384, kind=I64 } -> - + terminator Jmp(b92) (exit_acc=v1385) block 92 start_pc=0 - v397 Phi { incoming=[b90:v393, b91:v395], kind=I64 } -> x1 - v398 LoadLocal { off=-10, kind=I64 } -> x0 - v399 Store { addr=v382, disp=0, value=v397, kind=I64 } -> - - terminator Jmp(b85) (exit_acc=v399) + v1386 ImmData(1800) -> x0 + v1387 Load { addr=v1386, disp=0, kind=I64 } -> x1 + v1388 BinopI { op=add, lhs=v1387, rhs_imm=8 } -> x1 + v1389 Store { addr=v1386, disp=0, value=v1388, kind=I64 } -> - + v1390 Imm(25) -> x2 + v1391 Store { addr=v1388, disp=0, value=v1390, kind=I64 } -> - + v1392 Load { addr=v1386, disp=0, kind=I64 } -> x1 + v1393 BinopI { op=add, lhs=v1392, rhs_imm=8 } -> x1 + v1394 Store { addr=v1386, disp=0, value=v1393, kind=I64 } -> - + v1395 ImmData(1848) -> x0 + v1396 LoadLocal { off=-1, kind=I64 } -> x2 + v1397 BinopI { op=sub, lhs=v649, rhs_imm=2 } -> x2 + v1398 Store { addr=v1395, disp=0, value=v1397, kind=I64 } -> - + v1399 BinopI { op=eq, lhs=v1397, rhs_imm=0 } -> x0 + terminator Bz { cond=v1399, target=b95, fall=b93 } (exit_acc=v1399) block 93 start_pc=0 - v400 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v401 Imm(162) -> x7 - v402 Call { target_pc=7, args=[v401], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v403 ImmData(1800) -> x0 - v404 Load { addr=v403, disp=0, kind=I64 } -> x0 - v405 Load { addr=v404, disp=0, kind=I64 } -> x0 - v406 BinopI { op=eq, lhs=v405, rhs_imm=10 } -> x13 - v407 Imm(0) -> x0 - terminator Bnz { cond=v406, target=b261, fall=b96 } (exit_acc=v406) + v1408 Imm(10) -> x2 + v1409 Imm(0) -> x0 + terminator Jmp(b94) (exit_acc=v1408) block 94 start_pc=0 - terminator Jmp(b85) + v1412 Phi { incoming=[b93:v1408, b95:v1410], kind=I64 } -> x2 + v1413 LoadLocal { off=-25, kind=I64 } -> x0 + v1414 Store { addr=v1393, disp=0, value=v1412, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v1414) block 95 start_pc=0 - v408 ImmData(1832) -> x0 - v409 Load { addr=v3, disp=0, kind=I64 } -> x0 - v410 BinopI { op=eq, lhs=v409, rhs_imm=33 } -> x0 - terminator Bz { cond=v410, target=b103, fall=b101 } (exit_acc=v410) + v1410 Imm(9) -> x2 + v1411 Imm(0) -> x0 + terminator Jmp(b94) (exit_acc=v1410) block 96 start_pc=0 - v411 ImmData(1800) -> x0 - v412 Load { addr=v411, disp=0, kind=I64 } -> x0 - v413 Load { addr=v412, disp=0, kind=I64 } -> x0 - v414 BinopI { op=eq, lhs=v413, rhs_imm=9 } -> x13 - v415 Imm(0) -> x0 - terminator Jmp(b97) (exit_acc=v414) + v1400 LoadLocal { off=-1, kind=I64 } -> x0 + v1401 BinopI { op=lt, lhs=v649, rhs_imm=2 } -> x0 + terminator Bz { cond=v1401, target=b92, fall=b97 } (exit_acc=v1401) block 97 start_pc=0 - v416 Phi { incoming=[b261:v406, b96:v414], kind=I64 } -> x13 - v417 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v416, target=b100, fall=b98 } (exit_acc=v416) + v1402 ImmData(659) -> x7 + v1403 ImmData(1864) -> x0 + v1404 Load { addr=v1403, disp=0, kind=I64 } -> x6 + v1405 CallExt { binding_idx=0, args=[v1402, v1404], fp_arg_mask=0x0 } -> x0 + v1406 Imm(-1) -> x7 + v1407 CallExt { binding_idx=69, args=[v1406], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b92) (exit_acc=v1407) block 98 start_pc=0 - v418 ImmData(1800) -> x0 - v419 Load { addr=v418, disp=0, kind=I64 } -> x1 - v420 BinopI { op=add, lhs=v419, rhs_imm=-8 } -> x1 - v421 Store { addr=v418, disp=0, value=v420, kind=I64 } -> - - terminator Jmp(b99) (exit_acc=v421) + v1359 ImmData(631) -> x7 + v1360 ImmData(1864) -> x0 + v1361 Load { addr=v1360, disp=0, kind=I64 } -> x6 + v1362 CallExt { binding_idx=0, args=[v1359, v1361], fp_arg_mask=0x0 } -> x0 + v1363 Imm(-1) -> x7 + v1364 CallExt { binding_idx=69, args=[v1363], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b90) (exit_acc=v1364) block 99 start_pc=0 - v422 ImmData(1848) -> x0 - v423 Load { addr=v422, disp=0, kind=I64 } -> x1 - v424 BinopI { op=add, lhs=v423, rhs_imm=2 } -> x1 - v425 Store { addr=v422, disp=0, value=v424, kind=I64 } -> - - terminator Jmp(b94) (exit_acc=v425) + terminator Jmp(b65) block 100 start_pc=0 - v426 ImmData(463) -> x7 - v427 ImmData(1864) -> x0 - v428 Load { addr=v427, disp=0, kind=I64 } -> x6 - v429 CallExt { binding_idx=0, args=[v426, v428], fp_arg_mask=0x0 } -> x0 - v430 Imm(-1) -> x7 - v431 CallExt { binding_idx=69, args=[v430], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b99) (exit_acc=v431) + v1348 ImmData(686) -> x7 + v1349 ImmData(1864) -> x0 + v1350 Load { addr=v1349, disp=0, kind=I64 } -> x6 + v1351 ImmData(1832) -> x0 + v1352 Load { addr=v3, disp=0, kind=I64 } -> x2 + v1353 CallExt { binding_idx=0, args=[v1348, v1350, v1352], fp_arg_mask=0x0 } -> x0 + v1354 Imm(-1) -> x7 + v1355 CallExt { binding_idx=69, args=[v1354], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v1355) block 101 start_pc=0 - v432 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v433 Imm(162) -> x7 - v434 Call { target_pc=7, args=[v433], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v435 ImmData(1800) -> x0 - v436 Load { addr=v435, disp=0, kind=I64 } -> x1 - v437 BinopI { op=add, lhs=v436, rhs_imm=8 } -> x1 - v438 Store { addr=v435, disp=0, value=v437, kind=I64 } -> - - v439 Imm(13) -> x2 - v440 Store { addr=v437, disp=0, value=v439, kind=I64 } -> - - v441 Load { addr=v435, disp=0, kind=I64 } -> x1 - v442 BinopI { op=add, lhs=v441, rhs_imm=8 } -> x1 - v443 Store { addr=v435, disp=0, value=v442, kind=I64 } -> - - v444 Imm(1) -> x2 - v445 Store { addr=v442, disp=0, value=v444, kind=I64 } -> - - v446 Load { addr=v435, disp=0, kind=I64 } -> x1 - v447 BinopI { op=add, lhs=v446, rhs_imm=8 } -> x1 - v448 Store { addr=v435, disp=0, value=v447, kind=I64 } -> - - v449 Imm(0) -> x6 - v450 Store { addr=v447, disp=0, value=v449, kind=I64 } -> - - v451 Load { addr=v435, disp=0, kind=I64 } -> x1 - v452 BinopI { op=add, lhs=v451, rhs_imm=8 } -> x1 - v453 Store { addr=v435, disp=0, value=v452, kind=I64 } -> - - v454 Imm(17) -> x0 - v455 Store { addr=v452, disp=0, value=v454, kind=I64 } -> - - v456 ImmData(1848) -> x0 - v457 Store { addr=v456, disp=0, value=v444, kind=I64 } -> - - terminator Jmp(b102) (exit_acc=v457) + v644 ImmData(1832) -> x0 + v645 Load { addr=v3, disp=0, kind=I64 } -> x0 + v646 LoadLocal { off=2, kind=I64 } -> x1 + v647 Binop { op=ge, lhs=v645, rhs=v1 } -> x0 + terminator Bnz { cond=v647, target=b2, fall=b102 } (exit_acc=v647) block 102 start_pc=0 - terminator Jmp(b94) + v654 Imm(0) -> x0 + terminator Return(v654) (exit_acc=v654) block 103 start_pc=0 - v458 ImmData(1832) -> x0 - v459 Load { addr=v3, disp=0, kind=I64 } -> x0 - v460 BinopI { op=eq, lhs=v459, rhs_imm=126 } -> x0 - terminator Bz { cond=v460, target=b106, fall=b104 } (exit_acc=v460) + v12 ImmData(1832) -> x0 + v13 Load { addr=v3, disp=0, kind=I64 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=128 } -> x0 + terminator Bz { cond=v14, target=b105, fall=b104 } (exit_acc=v14) block 104 start_pc=0 - v461 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v462 Imm(162) -> x7 - v463 Call { target_pc=7, args=[v462], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v464 ImmData(1800) -> x0 - v465 Load { addr=v464, disp=0, kind=I64 } -> x1 - v466 BinopI { op=add, lhs=v465, rhs_imm=8 } -> x1 - v467 Store { addr=v464, disp=0, value=v466, kind=I64 } -> - - v468 Imm(13) -> x2 - v469 Store { addr=v466, disp=0, value=v468, kind=I64 } -> - - v470 Load { addr=v464, disp=0, kind=I64 } -> x1 - v471 BinopI { op=add, lhs=v470, rhs_imm=8 } -> x1 - v472 Store { addr=v464, disp=0, value=v471, kind=I64 } -> - - v473 Imm(1) -> x2 - v474 Store { addr=v471, disp=0, value=v473, kind=I64 } -> - - v475 Load { addr=v464, disp=0, kind=I64 } -> x1 - v476 BinopI { op=add, lhs=v475, rhs_imm=8 } -> x1 - v477 Store { addr=v464, disp=0, value=v476, kind=I64 } -> - - v478 Imm(-1) -> x6 - v479 Store { addr=v476, disp=0, value=v478, kind=I64 } -> - - v480 Load { addr=v464, disp=0, kind=I64 } -> x1 - v481 BinopI { op=add, lhs=v480, rhs_imm=8 } -> x1 - v482 Store { addr=v464, disp=0, value=v481, kind=I64 } -> - - v483 Imm(15) -> x0 - v484 Store { addr=v481, disp=0, value=v483, kind=I64 } -> - - v485 ImmData(1848) -> x0 - v486 Store { addr=v485, disp=0, value=v473, kind=I64 } -> - - terminator Jmp(b105) (exit_acc=v486) + v15 ImmData(1800) -> x0 + v16 Load { addr=v15, disp=0, kind=I64 } -> x1 + v17 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x1 + v18 Store { addr=v15, disp=0, value=v17, kind=I64 } -> - + v19 Imm(1) -> x13 + v20 Store { addr=v17, disp=0, value=v19, kind=I64 } -> - + v21 Load { addr=v15, disp=0, kind=I64 } -> x1 + v22 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x1 + v23 Store { addr=v15, disp=0, value=v22, kind=I64 } -> - + v24 ImmData(1840) -> x0 + v25 Load { addr=v24, disp=0, kind=I64 } -> x0 + v26 Store { addr=v22, disp=0, value=v25, kind=I64 } -> - + v27 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v28 ImmData(1848) -> x0 + v29 Store { addr=v28, disp=0, value=v19, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v29) block 105 start_pc=0 - terminator Jmp(b102) + v30 ImmData(1832) -> x0 + v31 Load { addr=v3, disp=0, kind=I64 } -> x0 + v32 BinopI { op=eq, lhs=v31, rhs_imm=34 } -> x0 + terminator Bz { cond=v32, target=b110, fall=b106 } (exit_acc=v32) block 106 start_pc=0 - v487 ImmData(1832) -> x0 - v488 Load { addr=v3, disp=0, kind=I64 } -> x0 - v489 BinopI { op=eq, lhs=v488, rhs_imm=157 } -> x0 - terminator Bz { cond=v489, target=b109, fall=b107 } (exit_acc=v489) + v33 ImmData(1800) -> x0 + v34 Load { addr=v33, disp=0, kind=I64 } -> x1 + v35 BinopI { op=add, lhs=v34, rhs_imm=8 } -> x1 + v36 Store { addr=v33, disp=0, value=v35, kind=I64 } -> - + v37 Imm(1) -> x2 + v38 Store { addr=v35, disp=0, value=v37, kind=I64 } -> - + v39 Load { addr=v33, disp=0, kind=I64 } -> x1 + v40 BinopI { op=add, lhs=v39, rhs_imm=8 } -> x1 + v41 Store { addr=v33, disp=0, value=v40, kind=I64 } -> - + v42 ImmData(1840) -> x0 + v43 Load { addr=v42, disp=0, kind=I64 } -> x0 + v44 Store { addr=v40, disp=0, value=v43, kind=I64 } -> - + v45 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b108) (exit_acc=v45) block 107 start_pc=0 - v490 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v491 Imm(162) -> x7 - v492 Call { target_pc=7, args=[v491], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v493 ImmData(1848) -> x0 - v494 Imm(1) -> x1 - v495 Store { addr=v493, disp=0, value=v494, kind=I64 } -> - - terminator Jmp(b108) (exit_acc=v495) + v52 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b108) (exit_acc=v52) block 108 start_pc=0 - terminator Jmp(b105) + v49 ImmData(1832) -> x0 + v50 Load { addr=v3, disp=0, kind=I64 } -> x0 + v51 BinopI { op=eq, lhs=v50, rhs_imm=34 } -> x0 + terminator Bnz { cond=v51, target=b107, fall=b109 } (exit_acc=v51) block 109 start_pc=0 - v496 ImmData(1832) -> x0 - v497 Load { addr=v3, disp=0, kind=I64 } -> x0 - v498 BinopI { op=eq, lhs=v497, rhs_imm=158 } -> x0 - terminator Bz { cond=v498, target=b112, fall=b110 } (exit_acc=v498) + v53 ImmData(1792) -> x0 + v54 Load { addr=v53, disp=0, kind=I64 } -> x1 + v55 BinopI { op=add, lhs=v54, rhs_imm=8 } -> x1 + v56 Imm(-8) -> x2 + v57 Imm(-34359738368) -> x2 + v58 BinopI { op=and, lhs=v55, rhs_imm=-8 } -> x1 + v59 Store { addr=v53, disp=0, value=v58, kind=I64 } -> - + v60 ImmData(1848) -> x0 + v61 Imm(2) -> x1 + v62 Store { addr=v60, disp=0, value=v61, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v62) block 110 start_pc=0 - v499 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v500 ImmData(1800) -> x0 - v501 Load { addr=v500, disp=0, kind=I64 } -> x1 - v502 BinopI { op=add, lhs=v501, rhs_imm=8 } -> x1 - v503 Store { addr=v500, disp=0, value=v502, kind=I64 } -> - - v504 Imm(1) -> x0 - v505 Store { addr=v502, disp=0, value=v504, kind=I64 } -> - - v506 ImmData(1832) -> x0 - v507 Load { addr=v3, disp=0, kind=I64 } -> x0 - v508 BinopI { op=eq, lhs=v507, rhs_imm=128 } -> x0 - terminator Bz { cond=v508, target=b115, fall=b113 } (exit_acc=v508) + v46 ImmData(1832) -> x0 + v47 Load { addr=v3, disp=0, kind=I64 } -> x0 + v48 BinopI { op=eq, lhs=v47, rhs_imm=140 } -> x0 + terminator Bz { cond=v48, target=b127, fall=b111 } (exit_acc=v48) block 111 start_pc=0 - terminator Jmp(b108) - block 112 start_pc=0 - v509 ImmData(1832) -> x0 - v510 Load { addr=v3, disp=0, kind=I64 } -> x0 - v511 BinopI { op=eq, lhs=v510, rhs_imm=162 } -> x13 - v512 Imm(0) -> x0 - terminator Bnz { cond=v511, target=b262, fall=b116 } (exit_acc=v511) + v63 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v64 ImmData(1832) -> x0 + v65 Load { addr=v3, disp=0, kind=I64 } -> x0 + v66 BinopI { op=eq, lhs=v65, rhs_imm=40 } -> x0 + terminator Bz { cond=v66, target=b126, fall=b112 } (exit_acc=v66) + block 112 start_pc=0 + v70 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b113) (exit_acc=v70) block 113 start_pc=0 - v513 ImmData(1800) -> x0 - v514 Load { addr=v513, disp=0, kind=I64 } -> x1 - v515 BinopI { op=add, lhs=v514, rhs_imm=8 } -> x1 - v516 Store { addr=v513, disp=0, value=v515, kind=I64 } -> - - v517 ImmData(1840) -> x0 - v518 Load { addr=v517, disp=0, kind=I64 } -> x0 - v519 BinopI { op=mul, lhs=v518, rhs_imm=-1 } -> x0 - v520 Store { addr=v515, disp=0, value=v519, kind=I64 } -> - - v521 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b114) (exit_acc=v521) + v71 ImmData(1848) -> x0 + v72 Imm(1) -> x1 + v73 Store { addr=v71, disp=0, value=v72, kind=I64 } -> - + v74 ImmData(1832) -> x0 + v75 Load { addr=v3, disp=0, kind=I64 } -> x0 + v76 BinopI { op=eq, lhs=v75, rhs_imm=138 } -> x0 + terminator Bz { cond=v76, target=b124, fall=b114 } (exit_acc=v76) block 114 start_pc=0 - v522 ImmData(1848) -> x0 - v523 Imm(1) -> x1 - v524 Store { addr=v522, disp=0, value=v523, kind=I64 } -> - - terminator Jmp(b111) (exit_acc=v524) + v83 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b116) (exit_acc=v83) block 115 start_pc=0 - v525 ImmData(1800) -> x13 - v526 Load { addr=v525, disp=0, kind=I64 } -> x0 - v527 BinopI { op=add, lhs=v526, rhs_imm=8 } -> x0 - v528 Store { addr=v525, disp=0, value=v527, kind=I64 } -> - - v529 Imm(-1) -> x1 - v530 Store { addr=v527, disp=0, value=v529, kind=I64 } -> - - v531 Load { addr=v525, disp=0, kind=I64 } -> x0 - v532 BinopI { op=add, lhs=v531, rhs_imm=8 } -> x0 - v533 Store { addr=v525, disp=0, value=v532, kind=I64 } -> - - v534 Imm(13) -> x1 - v535 Store { addr=v532, disp=0, value=v534, kind=I64 } -> - - v536 Imm(162) -> x7 - v537 Call { target_pc=7, args=[v536], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v538 Load { addr=v525, disp=0, kind=I64 } -> x0 - v539 BinopI { op=add, lhs=v538, rhs_imm=8 } -> x0 - v540 Store { addr=v525, disp=0, value=v539, kind=I64 } -> - - v541 Imm(27) -> x1 - v542 Store { addr=v539, disp=0, value=v541, kind=I64 } -> - - terminator Jmp(b114) (exit_acc=v542) + v94 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v95 ImmData(1848) -> x0 + v96 Load { addr=v95, disp=0, kind=I64 } -> x1 + v97 BinopI { op=add, lhs=v96, rhs_imm=2 } -> x1 + v98 Store { addr=v95, disp=0, value=v97, kind=I64 } -> - + terminator Jmp(b116) (exit_acc=v98) block 116 start_pc=0 - v543 ImmData(1832) -> x0 - v544 Load { addr=v3, disp=0, kind=I64 } -> x0 - v545 BinopI { op=eq, lhs=v544, rhs_imm=163 } -> x13 - v546 Imm(0) -> x0 - terminator Jmp(b117) (exit_acc=v545) + v91 ImmData(1832) -> x0 + v92 Load { addr=v3, disp=0, kind=I64 } -> x0 + v93 BinopI { op=eq, lhs=v92, rhs_imm=159 } -> x0 + terminator Bnz { cond=v93, target=b115, fall=b117 } (exit_acc=v93) block 117 start_pc=0 - v547 Phi { incoming=[b262:v511, b116:v545], kind=I64 } -> x13 - v548 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Bz { cond=v547, target=b120, fall=b118 } (exit_acc=v547) + v99 ImmData(1832) -> x0 + v100 Load { addr=v3, disp=0, kind=I64 } -> x0 + v101 BinopI { op=eq, lhs=v100, rhs_imm=41 } -> x0 + terminator Bz { cond=v101, target=b123, fall=b118 } (exit_acc=v101) block 118 start_pc=0 - v549 ImmData(1832) -> x0 - v550 Load { addr=v3, disp=0, kind=I64 } -> x13 - v551 Imm(0) -> x0 - v552 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v553 Imm(162) -> x7 - v554 Call { target_pc=7, args=[v553], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v555 ImmData(1800) -> x0 - v556 Load { addr=v555, disp=0, kind=I64 } -> x0 - v557 Load { addr=v556, disp=0, kind=I64 } -> x0 - v558 BinopI { op=eq, lhs=v557, rhs_imm=10 } -> x0 - terminator Bz { cond=v558, target=b123, fall=b121 } (exit_acc=v558) + v102 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b119) (exit_acc=v102) block 119 start_pc=0 - terminator Jmp(b111) + v103 ImmData(1800) -> x0 + v104 Load { addr=v103, disp=0, kind=I64 } -> x1 + v105 BinopI { op=add, lhs=v104, rhs_imm=8 } -> x1 + v106 Store { addr=v103, disp=0, value=v105, kind=I64 } -> - + v107 Imm(1) -> x2 + v108 Store { addr=v105, disp=0, value=v107, kind=I64 } -> - + v109 Load { addr=v103, disp=0, kind=I64 } -> x1 + v110 BinopI { op=add, lhs=v109, rhs_imm=8 } -> x1 + v111 Store { addr=v103, disp=0, value=v110, kind=I64 } -> - + v112 ImmData(1848) -> x0 + v113 Load { addr=v112, disp=0, kind=I64 } -> x0 + v114 BinopI { op=eq, lhs=v113, rhs_imm=0 } -> x0 + terminator Bz { cond=v114, target=b122, fall=b120 } (exit_acc=v114) block 120 start_pc=0 - v559 ImmData(516) -> x7 - v560 ImmData(1864) -> x0 - v561 Load { addr=v560, disp=0, kind=I64 } -> x6 - v562 CallExt { binding_idx=0, args=[v559, v561], fp_arg_mask=0x0 } -> x0 - v563 Imm(-1) -> x7 - v564 CallExt { binding_idx=69, args=[v563], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b119) (exit_acc=v564) + v121 Imm(1) -> x2 + v122 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v121) block 121 start_pc=0 - v565 ImmData(1800) -> x0 - v566 Load { addr=v565, disp=0, kind=I64 } -> x1 - v567 Imm(13) -> x2 - v568 Store { addr=v566, disp=0, value=v567, kind=I64 } -> - - v569 Load { addr=v565, disp=0, kind=I64 } -> x1 - v570 BinopI { op=add, lhs=v569, rhs_imm=8 } -> x1 - v571 Store { addr=v565, disp=0, value=v570, kind=I64 } -> - - v572 Imm(10) -> x0 - v573 Store { addr=v570, disp=0, value=v572, kind=I64 } -> - - terminator Jmp(b122) (exit_acc=v573) + v125 Phi { incoming=[b120:v121, b122:v123], kind=I64 } -> x2 + v126 LoadLocal { off=-6, kind=I64 } -> x0 + v127 Store { addr=v110, disp=0, value=v125, kind=I64 } -> - + v128 ImmData(1848) -> x0 + v129 Imm(1) -> x1 + v130 Store { addr=v128, disp=0, value=v129, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v130) block 122 start_pc=0 - v574 ImmData(1800) -> x0 - v575 Load { addr=v574, disp=0, kind=I64 } -> x1 - v576 BinopI { op=add, lhs=v575, rhs_imm=8 } -> x1 - v577 Store { addr=v574, disp=0, value=v576, kind=I64 } -> - - v578 Imm(13) -> x2 - v579 Store { addr=v576, disp=0, value=v578, kind=I64 } -> - - v580 Load { addr=v574, disp=0, kind=I64 } -> x1 - v581 BinopI { op=add, lhs=v580, rhs_imm=8 } -> x1 - v582 Store { addr=v574, disp=0, value=v581, kind=I64 } -> - - v583 Imm(1) -> x2 - v584 Store { addr=v581, disp=0, value=v583, kind=I64 } -> - - v585 Load { addr=v574, disp=0, kind=I64 } -> x1 - v586 BinopI { op=add, lhs=v585, rhs_imm=8 } -> x14 - v587 Store { addr=v574, disp=0, value=v586, kind=I64 } -> - - v588 ImmData(1848) -> x0 - v589 Load { addr=v588, disp=0, kind=I64 } -> x0 - v590 BinopI { op=gt, lhs=v589, rhs_imm=2 } -> x0 - terminator Bz { cond=v590, target=b128, fall=b127 } (exit_acc=v590) + v123 Imm(8) -> x2 + v124 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v123) block 123 start_pc=0 - v591 ImmData(1800) -> x0 - v592 Load { addr=v591, disp=0, kind=I64 } -> x0 - v593 Load { addr=v592, disp=0, kind=I64 } -> x0 - v594 BinopI { op=eq, lhs=v593, rhs_imm=9 } -> x0 - terminator Bz { cond=v594, target=b126, fall=b124 } (exit_acc=v594) + v115 ImmData(319) -> x7 + v116 ImmData(1864) -> x0 + v117 Load { addr=v116, disp=0, kind=I64 } -> x6 + v118 CallExt { binding_idx=0, args=[v115, v117], fp_arg_mask=0x0 } -> x0 + v119 Imm(-1) -> x7 + v120 CallExt { binding_idx=69, args=[v119], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b119) (exit_acc=v120) block 124 start_pc=0 - v595 ImmData(1800) -> x0 - v596 Load { addr=v595, disp=0, kind=I64 } -> x1 - v597 Imm(13) -> x2 - v598 Store { addr=v596, disp=0, value=v597, kind=I64 } -> - - v599 Load { addr=v595, disp=0, kind=I64 } -> x1 - v600 BinopI { op=add, lhs=v599, rhs_imm=8 } -> x1 - v601 Store { addr=v595, disp=0, value=v600, kind=I64 } -> - - v602 Imm(9) -> x0 - v603 Store { addr=v600, disp=0, value=v602, kind=I64 } -> - - terminator Jmp(b125) (exit_acc=v603) + v84 ImmData(1832) -> x0 + v85 Load { addr=v3, disp=0, kind=I64 } -> x0 + v86 BinopI { op=eq, lhs=v85, rhs_imm=134 } -> x0 + terminator Bz { cond=v86, target=b116, fall=b125 } (exit_acc=v86) block 125 start_pc=0 - terminator Jmp(b122) + v87 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v88 ImmData(1848) -> x0 + v89 Imm(0) -> x1 + v90 Store { addr=v88, disp=0, value=v89, kind=I64 } -> - + terminator Jmp(b116) (exit_acc=v90) block 126 start_pc=0 - v604 ImmData(483) -> x7 - v605 ImmData(1864) -> x0 - v606 Load { addr=v605, disp=0, kind=I64 } -> x6 - v607 CallExt { binding_idx=0, args=[v604, v606], fp_arg_mask=0x0 } -> x0 - v608 Imm(-1) -> x7 - v609 CallExt { binding_idx=69, args=[v608], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b125) (exit_acc=v609) + v77 ImmData(284) -> x7 + v78 ImmData(1864) -> x0 + v79 Load { addr=v78, disp=0, kind=I64 } -> x6 + v80 CallExt { binding_idx=0, args=[v77, v79], fp_arg_mask=0x0 } -> x0 + v81 Imm(-1) -> x7 + v82 CallExt { binding_idx=69, args=[v81], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b113) (exit_acc=v82) block 127 start_pc=0 - v610 Imm(8) -> x1 - v611 Imm(0) -> x0 - terminator Jmp(b129) (exit_acc=v610) + v67 ImmData(1832) -> x0 + v68 Load { addr=v3, disp=0, kind=I64 } -> x0 + v69 BinopI { op=eq, lhs=v68, rhs_imm=133 } -> x0 + terminator Bz { cond=v69, target=b153, fall=b128 } (exit_acc=v69) block 128 start_pc=0 - v612 Imm(1) -> x1 - v613 Imm(0) -> x0 - terminator Jmp(b129) (exit_acc=v612) + v131 ImmData(1816) -> x0 + v132 Load { addr=v131, disp=0, kind=I64 } -> x13 + v133 Imm(0) -> x0 + v134 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v135 ImmData(1832) -> x0 + v136 Load { addr=v3, disp=0, kind=I64 } -> x0 + v137 BinopI { op=eq, lhs=v136, rhs_imm=40 } -> x0 + terminator Bz { cond=v137, target=b142, fall=b129 } (exit_acc=v137) block 129 start_pc=0 - v614 Phi { incoming=[b127:v610, b128:v612], kind=I64 } -> x1 - v615 LoadLocal { off=-13, kind=I64 } -> x0 - v616 Store { addr=v586, disp=0, value=v614, kind=I64 } -> - - v617 ImmData(1800) -> x0 - v618 Load { addr=v617, disp=0, kind=I64 } -> x1 - v619 BinopI { op=add, lhs=v618, rhs_imm=8 } -> x1 - v620 Store { addr=v617, disp=0, value=v619, kind=I64 } -> - - v621 LoadLocal { off=-1, kind=I64 } -> x0 - v622 BinopI { op=eq, lhs=v550, rhs_imm=162 } -> x0 - terminator Bz { cond=v622, target=b131, fall=b130 } (exit_acc=v622) + v141 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v142 Imm(0) -> x14 + v143 Imm(0) -> x0 + terminator Jmp(b133) (exit_acc=v142) block 130 start_pc=0 - v623 Imm(25) -> x2 - v624 Imm(0) -> x0 - terminator Jmp(b132) (exit_acc=v623) + v153 Imm(142) -> x7 + v154 Call { target_pc=7, args=[v153], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v155 ImmData(1800) -> x0 + v156 Load { addr=v155, disp=0, kind=I64 } -> x1 + v157 BinopI { op=add, lhs=v156, rhs_imm=8 } -> x1 + v158 Store { addr=v155, disp=0, value=v157, kind=I64 } -> - + v159 Imm(13) -> x0 + v160 Store { addr=v157, disp=0, value=v159, kind=I64 } -> - + v161 LoadLocal { off=-1, kind=I64 } -> x0 + v162 BinopI { op=add, lhs=v149, rhs_imm=1 } -> x14 + v163 Imm(0) -> x0 + v164 ImmData(1832) -> x0 + v165 Load { addr=v3, disp=0, kind=I64 } -> x0 + v166 BinopI { op=eq, lhs=v165, rhs_imm=44 } -> x0 + terminator Bz { cond=v166, target=b132, fall=b131 } (exit_acc=v166) block 131 start_pc=0 - v625 Imm(26) -> x2 - v626 Imm(0) -> x0 - terminator Jmp(b132) (exit_acc=v625) + v173 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b132) (exit_acc=v173) block 132 start_pc=0 - v627 Phi { incoming=[b130:v623, b131:v625], kind=I64 } -> x2 - v628 LoadLocal { off=-14, kind=I64 } -> x0 - v629 Store { addr=v619, disp=0, value=v627, kind=I64 } -> - - v630 ImmData(1800) -> x0 - v631 Load { addr=v630, disp=0, kind=I64 } -> x1 - v632 BinopI { op=add, lhs=v631, rhs_imm=8 } -> x1 - v633 Store { addr=v630, disp=0, value=v632, kind=I64 } -> - - v634 ImmData(1848) -> x0 - v635 Load { addr=v634, disp=0, kind=I64 } -> x0 - v636 BinopI { op=eq, lhs=v635, rhs_imm=0 } -> x0 - terminator Bz { cond=v636, target=b134, fall=b133 } (exit_acc=v636) + terminator Jmp(b133) block 133 start_pc=0 - v637 Imm(12) -> x2 - v638 Imm(0) -> x0 - terminator Jmp(b135) (exit_acc=v637) + v149 Phi { incoming=[b129:v142, b132:v162], kind=I64 } -> x14 + v150 ImmData(1832) -> x0 + v151 Load { addr=v3, disp=0, kind=I64 } -> x0 + v152 BinopI { op=ne, lhs=v151, rhs_imm=41 } -> x0 + terminator Bnz { cond=v152, target=b130, fall=b134 } (exit_acc=v152) block 134 start_pc=0 - v639 Imm(11) -> x2 - v640 Imm(0) -> x0 - terminator Jmp(b135) (exit_acc=v639) + v167 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v168 LoadLocal { off=-2, kind=I64 } -> x0 + v169 Imm(24) -> x0 + v170 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 + v171 Load { addr=v132, disp=24, kind=I64 } -> x0 + v172 BinopI { op=eq, lhs=v171, rhs_imm=130 } -> x0 + terminator Bz { cond=v172, target=b139, fall=b135 } (exit_acc=v172) block 135 start_pc=0 - v641 Phi { incoming=[b133:v637, b134:v639], kind=I64 } -> x2 - v642 LoadLocal { off=-15, kind=I64 } -> x0 - v643 Store { addr=v632, disp=0, value=v641, kind=I64 } -> - - terminator Jmp(b119) (exit_acc=v643) + v174 ImmData(1800) -> x0 + v175 Load { addr=v174, disp=0, kind=I64 } -> x1 + v176 BinopI { op=add, lhs=v175, rhs_imm=8 } -> x1 + v177 Store { addr=v174, disp=0, value=v176, kind=I64 } -> - + v178 LoadLocal { off=-2, kind=I64 } -> x0 + v179 Imm(40) -> x0 + v180 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 + v181 Load { addr=v132, disp=40, kind=I64 } -> x0 + v182 Store { addr=v176, disp=0, value=v181, kind=I64 } -> - + terminator Jmp(b136) (exit_acc=v182) block 136 start_pc=0 - v644 ImmData(1832) -> x0 - v645 Load { addr=v3, disp=0, kind=I64 } -> x0 - v646 LoadLocal { off=2, kind=I64 } -> x1 - v647 Binop { op=ge, lhs=v645, rhs=v1 } -> x0 - terminator Bz { cond=v647, target=b138, fall=b137 } (exit_acc=v647) + v183 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v149, target=b138, fall=b137 } (exit_acc=v149) block 137 start_pc=0 - v648 ImmData(1848) -> x0 - v649 Load { addr=v648, disp=0, kind=I64 } -> x13 - v650 Imm(0) -> x0 - v651 ImmData(1832) -> x0 - v652 Load { addr=v3, disp=0, kind=I64 } -> x0 - v653 BinopI { op=eq, lhs=v652, rhs_imm=142 } -> x0 - terminator Bz { cond=v653, target=b141, fall=b139 } (exit_acc=v653) + v209 ImmData(1800) -> x0 + v210 Load { addr=v209, disp=0, kind=I64 } -> x1 + v211 BinopI { op=add, lhs=v210, rhs_imm=8 } -> x1 + v212 Store { addr=v209, disp=0, value=v211, kind=I64 } -> - + v213 Imm(7) -> x2 + v214 Store { addr=v211, disp=0, value=v213, kind=I64 } -> - + v215 Load { addr=v209, disp=0, kind=I64 } -> x1 + v216 BinopI { op=add, lhs=v215, rhs_imm=8 } -> x1 + v217 Store { addr=v209, disp=0, value=v216, kind=I64 } -> - + v218 LoadLocal { off=-1, kind=I64 } -> x0 + v219 Store { addr=v216, disp=0, value=v149, kind=I64 } -> - + terminator Jmp(b138) (exit_acc=v219) block 138 start_pc=0 - v654 Imm(0) -> x0 - terminator Return(v654) (exit_acc=v654) + v220 ImmData(1848) -> x0 + v221 LoadLocal { off=-2, kind=I64 } -> x1 + v222 Imm(32) -> x1 + v223 BinopI { op=add, lhs=v132, rhs_imm=32 } -> x1 + v224 Load { addr=v132, disp=32, kind=I64 } -> x1 + v225 Store { addr=v220, disp=0, value=v224, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v225) block 139 start_pc=0 - v655 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v656 ImmData(1800) -> x0 - v657 Load { addr=v656, disp=0, kind=I64 } -> x0 - v658 Load { addr=v657, disp=0, kind=I64 } -> x0 - v659 BinopI { op=eq, lhs=v658, rhs_imm=10 } -> x14 - v660 Imm(0) -> x0 - terminator Bnz { cond=v659, target=b263, fall=b142 } (exit_acc=v659) + v184 LoadLocal { off=-2, kind=I64 } -> x0 + v185 Imm(24) -> x0 + v186 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 + v187 Load { addr=v132, disp=24, kind=I64 } -> x0 + v188 BinopI { op=eq, lhs=v187, rhs_imm=129 } -> x0 + terminator Bz { cond=v188, target=b141, fall=b140 } (exit_acc=v188) block 140 start_pc=0 - terminator Jmp(b136) + v189 ImmData(1800) -> x0 + v190 Load { addr=v189, disp=0, kind=I64 } -> x1 + v191 BinopI { op=add, lhs=v190, rhs_imm=8 } -> x1 + v192 Store { addr=v189, disp=0, value=v191, kind=I64 } -> - + v193 Imm(3) -> x2 + v194 Store { addr=v191, disp=0, value=v193, kind=I64 } -> - + v195 Load { addr=v189, disp=0, kind=I64 } -> x1 + v196 BinopI { op=add, lhs=v195, rhs_imm=8 } -> x1 + v197 Store { addr=v189, disp=0, value=v196, kind=I64 } -> - + v198 LoadLocal { off=-2, kind=I64 } -> x0 + v199 Imm(40) -> x0 + v200 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 + v201 Load { addr=v132, disp=40, kind=I64 } -> x0 + v202 Store { addr=v196, disp=0, value=v201, kind=I64 } -> - + terminator Jmp(b136) (exit_acc=v202) block 141 start_pc=0 - v661 ImmData(1832) -> x0 - v662 Load { addr=v3, disp=0, kind=I64 } -> x0 - v663 BinopI { op=eq, lhs=v662, rhs_imm=143 } -> x0 - terminator Bz { cond=v663, target=b152, fall=b150 } (exit_acc=v663) + v203 ImmData(355) -> x7 + v204 ImmData(1864) -> x0 + v205 Load { addr=v204, disp=0, kind=I64 } -> x6 + v206 CallExt { binding_idx=0, args=[v203, v205], fp_arg_mask=0x0 } -> x0 + v207 Imm(-1) -> x7 + v208 CallExt { binding_idx=69, args=[v207], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b136) (exit_acc=v208) block 142 start_pc=0 - v664 ImmData(1800) -> x0 - v665 Load { addr=v664, disp=0, kind=I64 } -> x0 - v666 Load { addr=v665, disp=0, kind=I64 } -> x0 - v667 BinopI { op=eq, lhs=v666, rhs_imm=9 } -> x14 - v668 Imm(0) -> x0 - terminator Jmp(b143) (exit_acc=v667) + v144 LoadLocal { off=-2, kind=I64 } -> x0 + v145 Imm(24) -> x0 + v146 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 + v147 Load { addr=v132, disp=24, kind=I64 } -> x0 + v148 BinopI { op=eq, lhs=v147, rhs_imm=128 } -> x0 + terminator Bz { cond=v148, target=b144, fall=b143 } (exit_acc=v148) block 143 start_pc=0 - v669 Phi { incoming=[b263:v659, b142:v667], kind=I64 } -> x14 - v670 LoadLocal { off=-16, kind=I64 } -> x0 - terminator Bz { cond=v669, target=b146, fall=b144 } (exit_acc=v669) + v226 ImmData(1800) -> x0 + v227 Load { addr=v226, disp=0, kind=I64 } -> x1 + v228 BinopI { op=add, lhs=v227, rhs_imm=8 } -> x1 + v229 Store { addr=v226, disp=0, value=v228, kind=I64 } -> - + v230 Imm(1) -> x2 + v231 Store { addr=v228, disp=0, value=v230, kind=I64 } -> - + v232 Load { addr=v226, disp=0, kind=I64 } -> x1 + v233 BinopI { op=add, lhs=v232, rhs_imm=8 } -> x1 + v234 Store { addr=v226, disp=0, value=v233, kind=I64 } -> - + v235 LoadLocal { off=-2, kind=I64 } -> x0 + v236 Imm(40) -> x0 + v237 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 + v238 Load { addr=v132, disp=40, kind=I64 } -> x0 + v239 Store { addr=v233, disp=0, value=v238, kind=I64 } -> - + v240 ImmData(1848) -> x0 + v241 Store { addr=v240, disp=0, value=v230, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v241) block 144 start_pc=0 - v671 ImmData(1800) -> x0 - v672 Load { addr=v671, disp=0, kind=I64 } -> x0 - v673 Imm(13) -> x1 - v674 Store { addr=v672, disp=0, value=v673, kind=I64 } -> - - terminator Jmp(b145) (exit_acc=v674) + v242 LoadLocal { off=-2, kind=I64 } -> x0 + v243 Imm(24) -> x0 + v244 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 + v245 Load { addr=v132, disp=24, kind=I64 } -> x0 + v246 BinopI { op=eq, lhs=v245, rhs_imm=132 } -> x0 + terminator Bz { cond=v246, target=b150, fall=b145 } (exit_acc=v246) block 145 start_pc=0 - v675 Imm(142) -> x7 - v676 Call { target_pc=7, args=[v675], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v677 ImmData(1800) -> x0 - v678 Load { addr=v677, disp=0, kind=I64 } -> x1 - v679 BinopI { op=add, lhs=v678, rhs_imm=8 } -> x14 - v680 Store { addr=v677, disp=0, value=v679, kind=I64 } -> - - v681 ImmData(1848) -> x0 - v682 LoadLocal { off=-1, kind=I64 } -> x1 - v683 Store { addr=v681, disp=0, value=v649, kind=I64 } -> - - v684 BinopI { op=eq, lhs=v649, rhs_imm=0 } -> x0 - terminator Bz { cond=v684, target=b148, fall=b147 } (exit_acc=v684) + v247 ImmData(1800) -> x0 + v248 Load { addr=v247, disp=0, kind=I64 } -> x1 + v249 BinopI { op=add, lhs=v248, rhs_imm=8 } -> x1 + v250 Store { addr=v247, disp=0, value=v249, kind=I64 } -> - + v251 Imm(0) -> x2 + v252 Store { addr=v249, disp=0, value=v251, kind=I64 } -> - + v253 Load { addr=v247, disp=0, kind=I64 } -> x1 + v254 BinopI { op=add, lhs=v253, rhs_imm=8 } -> x1 + v255 Store { addr=v247, disp=0, value=v254, kind=I64 } -> - + v256 ImmData(1856) -> x0 + v257 Load { addr=v256, disp=0, kind=I64 } -> x0 + v258 LoadLocal { off=-2, kind=I64 } -> x2 + v259 Imm(40) -> x2 + v260 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x2 + v261 Load { addr=v132, disp=40, kind=I64 } -> x2 + v262 Binop { op=sub, lhs=v257, rhs=v261 } -> x0 + v263 Store { addr=v254, disp=0, value=v262, kind=I64 } -> - + terminator Jmp(b146) (exit_acc=v263) block 146 start_pc=0 - v685 ImmData(536) -> x7 - v686 ImmData(1864) -> x0 - v687 Load { addr=v686, disp=0, kind=I64 } -> x6 - v688 CallExt { binding_idx=0, args=[v685, v687], fp_arg_mask=0x0 } -> x0 - v689 Imm(-1) -> x7 - v690 CallExt { binding_idx=69, args=[v689], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b145) (exit_acc=v690) + v264 ImmData(1800) -> x0 + v265 Load { addr=v264, disp=0, kind=I64 } -> x1 + v266 BinopI { op=add, lhs=v265, rhs_imm=8 } -> x1 + v267 Store { addr=v264, disp=0, value=v266, kind=I64 } -> - + v268 ImmData(1848) -> x0 + v269 LoadLocal { off=-2, kind=I64 } -> x2 + v270 Imm(32) -> x2 + v271 BinopI { op=add, lhs=v132, rhs_imm=32 } -> x2 + v272 Load { addr=v132, disp=32, kind=I64 } -> x2 + v273 Store { addr=v268, disp=0, value=v272, kind=I64 } -> - + v274 BinopI { op=eq, lhs=v272, rhs_imm=0 } -> x0 + terminator Bz { cond=v274, target=b149, fall=b147 } (exit_acc=v274) block 147 start_pc=0 - v691 Imm(12) -> x1 - v692 Imm(0) -> x0 - terminator Jmp(b149) (exit_acc=v691) + v300 Imm(10) -> x2 + v301 Imm(0) -> x0 + terminator Jmp(b148) (exit_acc=v300) block 148 start_pc=0 - v693 Imm(11) -> x1 - v694 Imm(0) -> x0 - terminator Jmp(b149) (exit_acc=v693) + v304 Phi { incoming=[b147:v300, b149:v302], kind=I64 } -> x2 + v305 LoadLocal { off=-7, kind=I64 } -> x0 + v306 Store { addr=v266, disp=0, value=v304, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v306) block 149 start_pc=0 - v695 Phi { incoming=[b147:v691, b148:v693], kind=I64 } -> x1 - v696 LoadLocal { off=-17, kind=I64 } -> x0 - v697 Store { addr=v679, disp=0, value=v695, kind=I64 } -> - - terminator Jmp(b140) (exit_acc=v697) + v302 Imm(9) -> x2 + v303 Imm(0) -> x0 + terminator Jmp(b148) (exit_acc=v302) block 150 start_pc=0 - v698 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v699 ImmData(1800) -> x0 - v700 Load { addr=v699, disp=0, kind=I64 } -> x1 - v701 BinopI { op=add, lhs=v700, rhs_imm=8 } -> x1 - v702 Store { addr=v699, disp=0, value=v701, kind=I64 } -> - - v703 Imm(4) -> x2 - v704 Store { addr=v701, disp=0, value=v703, kind=I64 } -> - - v705 Load { addr=v699, disp=0, kind=I64 } -> x1 - v706 BinopI { op=add, lhs=v705, rhs_imm=8 } -> x13 - v707 Store { addr=v699, disp=0, value=v706, kind=I64 } -> - - v708 Imm(0) -> x0 - v709 Imm(142) -> x7 - v710 Call { target_pc=7, args=[v709], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v711 ImmData(1832) -> x0 - v712 Load { addr=v3, disp=0, kind=I64 } -> x0 - v713 BinopI { op=eq, lhs=v712, rhs_imm=58 } -> x0 - terminator Bz { cond=v713, target=b155, fall=b153 } (exit_acc=v713) + v275 LoadLocal { off=-2, kind=I64 } -> x0 + v276 Imm(24) -> x0 + v277 BinopI { op=add, lhs=v132, rhs_imm=24 } -> x0 + v278 Load { addr=v132, disp=24, kind=I64 } -> x0 + v279 BinopI { op=eq, lhs=v278, rhs_imm=131 } -> x0 + terminator Bz { cond=v279, target=b152, fall=b151 } (exit_acc=v279) block 151 start_pc=0 - terminator Jmp(b140) + v280 ImmData(1800) -> x0 + v281 Load { addr=v280, disp=0, kind=I64 } -> x1 + v282 BinopI { op=add, lhs=v281, rhs_imm=8 } -> x1 + v283 Store { addr=v280, disp=0, value=v282, kind=I64 } -> - + v284 Imm(1) -> x2 + v285 Store { addr=v282, disp=0, value=v284, kind=I64 } -> - + v286 Load { addr=v280, disp=0, kind=I64 } -> x1 + v287 BinopI { op=add, lhs=v286, rhs_imm=8 } -> x1 + v288 Store { addr=v280, disp=0, value=v287, kind=I64 } -> - + v289 LoadLocal { off=-2, kind=I64 } -> x0 + v290 Imm(40) -> x0 + v291 BinopI { op=add, lhs=v132, rhs_imm=40 } -> x0 + v292 Load { addr=v132, disp=40, kind=I64 } -> x0 + v293 Store { addr=v287, disp=0, value=v292, kind=I64 } -> - + terminator Jmp(b146) (exit_acc=v293) block 152 start_pc=0 - v714 ImmData(1832) -> x0 - v715 Load { addr=v3, disp=0, kind=I64 } -> x0 - v716 BinopI { op=eq, lhs=v715, rhs_imm=144 } -> x0 - terminator Bz { cond=v716, target=b158, fall=b156 } (exit_acc=v716) + v294 ImmData(378) -> x7 + v295 ImmData(1864) -> x0 + v296 Load { addr=v295, disp=0, kind=I64 } -> x6 + v297 CallExt { binding_idx=0, args=[v294, v296], fp_arg_mask=0x0 } -> x0 + v298 Imm(-1) -> x7 + v299 CallExt { binding_idx=69, args=[v298], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b146) (exit_acc=v299) block 153 start_pc=0 - v717 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b154) (exit_acc=v717) + v138 ImmData(1832) -> x0 + v139 Load { addr=v3, disp=0, kind=I64 } -> x0 + v140 BinopI { op=eq, lhs=v139, rhs_imm=40 } -> x0 + terminator Bz { cond=v140, target=b171, fall=b154 } (exit_acc=v140) block 154 start_pc=0 - v718 LoadLocal { off=-2, kind=I64 } -> x0 - v719 ImmData(1800) -> x14 - v720 Load { addr=v719, disp=0, kind=I64 } -> x0 - v721 Imm(24) -> x1 - v722 BinopI { op=add, lhs=v720, rhs_imm=24 } -> x0 - v723 Store { addr=v706, disp=0, value=v722, kind=I64 } -> - - v724 Load { addr=v719, disp=0, kind=I64 } -> x0 - v725 BinopI { op=add, lhs=v724, rhs_imm=8 } -> x0 - v726 Store { addr=v719, disp=0, value=v725, kind=I64 } -> - - v727 Imm(2) -> x1 - v728 Store { addr=v725, disp=0, value=v727, kind=I64 } -> - - v729 Load { addr=v719, disp=0, kind=I64 } -> x0 - v730 BinopI { op=add, lhs=v729, rhs_imm=8 } -> x13 - v731 Store { addr=v719, disp=0, value=v730, kind=I64 } -> - - v732 Imm(0) -> x0 - v733 Imm(143) -> x7 - v734 Call { target_pc=7, args=[v733], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v735 LoadLocal { off=-2, kind=I64 } -> x0 - v736 Load { addr=v719, disp=0, kind=I64 } -> x0 - v737 Imm(8) -> x1 - v738 BinopI { op=add, lhs=v736, rhs_imm=8 } -> x0 - v739 Store { addr=v730, disp=0, value=v738, kind=I64 } -> - - terminator Jmp(b151) (exit_acc=v739) + v307 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v308 ImmData(1832) -> x0 + v309 Load { addr=v3, disp=0, kind=I64 } -> x0 + v310 BinopI { op=eq, lhs=v309, rhs_imm=138 } -> x1 + v311 Imm(0) -> x0 + terminator Bnz { cond=v310, target=b170, fall=b155 } (exit_acc=v310) block 155 start_pc=0 - v740 ImmData(566) -> x7 - v741 ImmData(1864) -> x0 - v742 Load { addr=v741, disp=0, kind=I64 } -> x6 - v743 CallExt { binding_idx=0, args=[v740, v742], fp_arg_mask=0x0 } -> x0 - v744 Imm(-1) -> x7 - v745 CallExt { binding_idx=69, args=[v744], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b154) (exit_acc=v745) + v315 ImmData(1832) -> x0 + v316 Load { addr=v3, disp=0, kind=I64 } -> x0 + v317 BinopI { op=eq, lhs=v316, rhs_imm=134 } -> x1 + v318 Imm(0) -> x0 + terminator Jmp(b156) (exit_acc=v317) block 156 start_pc=0 - v746 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v747 ImmData(1800) -> x13 - v748 Load { addr=v747, disp=0, kind=I64 } -> x0 - v749 BinopI { op=add, lhs=v748, rhs_imm=8 } -> x0 - v750 Store { addr=v747, disp=0, value=v749, kind=I64 } -> - - v751 Imm(5) -> x1 - v752 Store { addr=v749, disp=0, value=v751, kind=I64 } -> - - v753 Load { addr=v747, disp=0, kind=I64 } -> x0 - v754 BinopI { op=add, lhs=v753, rhs_imm=8 } -> x14 - v755 Store { addr=v747, disp=0, value=v754, kind=I64 } -> - - v756 Imm(0) -> x0 - v757 Imm(145) -> x7 - v758 Call { target_pc=7, args=[v757], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v759 LoadLocal { off=-2, kind=I64 } -> x0 - v760 Load { addr=v747, disp=0, kind=I64 } -> x0 - v761 Imm(8) -> x1 - v762 BinopI { op=add, lhs=v760, rhs_imm=8 } -> x0 - v763 Store { addr=v754, disp=0, value=v762, kind=I64 } -> - - v764 ImmData(1848) -> x0 - v765 Imm(1) -> x1 - v766 Store { addr=v764, disp=0, value=v765, kind=I64 } -> - - terminator Jmp(b157) (exit_acc=v766) + v319 Phi { incoming=[b170:v310, b155:v317], kind=I64 } -> x1 + v320 LoadLocal { off=-8, kind=I64 } -> x0 + terminator Bz { cond=v319, target=b167, fall=b157 } (exit_acc=v319) block 157 start_pc=0 - terminator Jmp(b151) + v321 ImmData(1832) -> x0 + v322 Load { addr=v3, disp=0, kind=I64 } -> x0 + v323 BinopI { op=eq, lhs=v322, rhs_imm=138 } -> x0 + terminator Bz { cond=v323, target=b166, fall=b158 } (exit_acc=v323) block 158 start_pc=0 - v767 ImmData(1832) -> x0 - v768 Load { addr=v3, disp=0, kind=I64 } -> x0 - v769 BinopI { op=eq, lhs=v768, rhs_imm=145 } -> x0 - terminator Bz { cond=v769, target=b161, fall=b159 } (exit_acc=v769) + v329 Imm(1) -> x13 + v330 Imm(0) -> x0 + terminator Jmp(b159) (exit_acc=v329) block 159 start_pc=0 - v770 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v771 ImmData(1800) -> x13 - v772 Load { addr=v771, disp=0, kind=I64 } -> x0 - v773 BinopI { op=add, lhs=v772, rhs_imm=8 } -> x0 - v774 Store { addr=v771, disp=0, value=v773, kind=I64 } -> - - v775 Imm(4) -> x1 - v776 Store { addr=v773, disp=0, value=v775, kind=I64 } -> - - v777 Load { addr=v771, disp=0, kind=I64 } -> x0 - v778 BinopI { op=add, lhs=v777, rhs_imm=8 } -> x14 - v779 Store { addr=v771, disp=0, value=v778, kind=I64 } -> - - v780 Imm(0) -> x0 - v781 Imm(146) -> x7 - v782 Call { target_pc=7, args=[v781], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v783 LoadLocal { off=-2, kind=I64 } -> x0 - v784 Load { addr=v771, disp=0, kind=I64 } -> x0 - v785 Imm(8) -> x1 - v786 BinopI { op=add, lhs=v784, rhs_imm=8 } -> x0 - v787 Store { addr=v778, disp=0, value=v786, kind=I64 } -> - - v788 ImmData(1848) -> x0 - v789 Imm(1) -> x1 - v790 Store { addr=v788, disp=0, value=v789, kind=I64 } -> - - terminator Jmp(b160) (exit_acc=v790) + v333 Phi { incoming=[b158:v329, b166:v331], kind=I64 } -> x13 + v334 LoadLocal { off=-9, kind=I64 } -> x0 + v335 Imm(0) -> x0 + v336 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b161) (exit_acc=v336) block 160 start_pc=0 - terminator Jmp(b157) + v341 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v342 LoadLocal { off=-1, kind=I64 } -> x0 + v343 BinopI { op=add, lhs=v337, rhs_imm=2 } -> x13 + v344 Imm(0) -> x0 + terminator Jmp(b161) (exit_acc=v343) block 161 start_pc=0 - v791 ImmData(1832) -> x0 - v792 Load { addr=v3, disp=0, kind=I64 } -> x0 - v793 BinopI { op=eq, lhs=v792, rhs_imm=146 } -> x0 - terminator Bz { cond=v793, target=b164, fall=b162 } (exit_acc=v793) + v337 Phi { incoming=[b159:v333, b160:v343], kind=I64 } -> x13 + v338 ImmData(1832) -> x0 + v339 Load { addr=v3, disp=0, kind=I64 } -> x0 + v340 BinopI { op=eq, lhs=v339, rhs_imm=159 } -> x0 + terminator Bnz { cond=v340, target=b160, fall=b162 } (exit_acc=v340) block 162 start_pc=0 - v794 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v795 ImmData(1800) -> x13 - v796 Load { addr=v795, disp=0, kind=I64 } -> x0 - v797 BinopI { op=add, lhs=v796, rhs_imm=8 } -> x0 - v798 Store { addr=v795, disp=0, value=v797, kind=I64 } -> - - v799 Imm(13) -> x1 - v800 Store { addr=v797, disp=0, value=v799, kind=I64 } -> - - v801 Imm(147) -> x7 - v802 Call { target_pc=7, args=[v801], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v803 Load { addr=v795, disp=0, kind=I64 } -> x0 - v804 BinopI { op=add, lhs=v803, rhs_imm=8 } -> x0 - v805 Store { addr=v795, disp=0, value=v804, kind=I64 } -> - - v806 Imm(14) -> x1 - v807 Store { addr=v804, disp=0, value=v806, kind=I64 } -> - - v808 ImmData(1848) -> x0 - v809 Imm(1) -> x1 - v810 Store { addr=v808, disp=0, value=v809, kind=I64 } -> - - terminator Jmp(b163) (exit_acc=v810) + v345 ImmData(1832) -> x0 + v346 Load { addr=v3, disp=0, kind=I64 } -> x0 + v347 BinopI { op=eq, lhs=v346, rhs_imm=41 } -> x0 + terminator Bz { cond=v347, target=b165, fall=b163 } (exit_acc=v347) block 163 start_pc=0 - terminator Jmp(b160) + v348 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b164) (exit_acc=v348) block 164 start_pc=0 - v811 ImmData(1832) -> x0 - v812 Load { addr=v3, disp=0, kind=I64 } -> x0 - v813 BinopI { op=eq, lhs=v812, rhs_imm=147 } -> x0 - terminator Bz { cond=v813, target=b167, fall=b165 } (exit_acc=v813) + v349 Imm(162) -> x7 + v350 Call { target_pc=7, args=[v349], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v351 ImmData(1848) -> x0 + v352 LoadLocal { off=-1, kind=I64 } -> x1 + v353 Store { addr=v351, disp=0, value=v337, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v353) block 165 start_pc=0 - v814 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v815 ImmData(1800) -> x13 - v816 Load { addr=v815, disp=0, kind=I64 } -> x0 - v817 BinopI { op=add, lhs=v816, rhs_imm=8 } -> x0 - v818 Store { addr=v815, disp=0, value=v817, kind=I64 } -> - - v819 Imm(13) -> x1 - v820 Store { addr=v817, disp=0, value=v819, kind=I64 } -> - - v821 Imm(148) -> x7 - v822 Call { target_pc=7, args=[v821], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v823 Load { addr=v815, disp=0, kind=I64 } -> x0 - v824 BinopI { op=add, lhs=v823, rhs_imm=8 } -> x0 - v825 Store { addr=v815, disp=0, value=v824, kind=I64 } -> - - v826 Imm(15) -> x1 - v827 Store { addr=v824, disp=0, value=v826, kind=I64 } -> - - v828 ImmData(1848) -> x0 - v829 Imm(1) -> x1 - v830 Store { addr=v828, disp=0, value=v829, kind=I64 } -> - - terminator Jmp(b166) (exit_acc=v830) + v354 ImmData(402) -> x7 + v355 ImmData(1864) -> x0 + v356 Load { addr=v355, disp=0, kind=I64 } -> x6 + v357 CallExt { binding_idx=0, args=[v354, v356], fp_arg_mask=0x0 } -> x0 + v358 Imm(-1) -> x7 + v359 CallExt { binding_idx=69, args=[v358], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b164) (exit_acc=v359) block 166 start_pc=0 - terminator Jmp(b163) + v331 Imm(0) -> x13 + v332 Imm(0) -> x0 + terminator Jmp(b159) (exit_acc=v331) block 167 start_pc=0 - v831 ImmData(1832) -> x0 - v832 Load { addr=v3, disp=0, kind=I64 } -> x0 - v833 BinopI { op=eq, lhs=v832, rhs_imm=148 } -> x0 - terminator Bz { cond=v833, target=b170, fall=b168 } (exit_acc=v833) + v324 Imm(142) -> x7 + v325 Call { target_pc=7, args=[v324], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v326 ImmData(1832) -> x0 + v327 Load { addr=v3, disp=0, kind=I64 } -> x0 + v328 BinopI { op=eq, lhs=v327, rhs_imm=41 } -> x0 + terminator Bz { cond=v328, target=b169, fall=b168 } (exit_acc=v328) block 168 start_pc=0 - v834 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v835 ImmData(1800) -> x13 - v836 Load { addr=v835, disp=0, kind=I64 } -> x0 - v837 BinopI { op=add, lhs=v836, rhs_imm=8 } -> x0 - v838 Store { addr=v835, disp=0, value=v837, kind=I64 } -> - - v839 Imm(13) -> x1 - v840 Store { addr=v837, disp=0, value=v839, kind=I64 } -> - - v841 Imm(149) -> x7 - v842 Call { target_pc=7, args=[v841], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v843 Load { addr=v835, disp=0, kind=I64 } -> x0 - v844 BinopI { op=add, lhs=v843, rhs_imm=8 } -> x0 - v845 Store { addr=v835, disp=0, value=v844, kind=I64 } -> - - v846 Imm(16) -> x1 - v847 Store { addr=v844, disp=0, value=v846, kind=I64 } -> - - v848 ImmData(1848) -> x0 - v849 Imm(1) -> x1 - v850 Store { addr=v848, disp=0, value=v849, kind=I64 } -> - - terminator Jmp(b169) (exit_acc=v850) + v360 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v360) block 169 start_pc=0 - terminator Jmp(b166) + v361 ImmData(416) -> x7 + v362 ImmData(1864) -> x0 + v363 Load { addr=v362, disp=0, kind=I64 } -> x6 + v364 CallExt { binding_idx=0, args=[v361, v363], fp_arg_mask=0x0 } -> x0 + v365 Imm(-1) -> x7 + v366 CallExt { binding_idx=69, args=[v365], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v366) block 170 start_pc=0 - v851 ImmData(1832) -> x0 - v852 Load { addr=v3, disp=0, kind=I64 } -> x0 - v853 BinopI { op=eq, lhs=v852, rhs_imm=149 } -> x0 - terminator Bz { cond=v853, target=b173, fall=b171 } (exit_acc=v853) + terminator Jmp(b156) block 171 start_pc=0 - v854 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v855 ImmData(1800) -> x13 - v856 Load { addr=v855, disp=0, kind=I64 } -> x0 - v857 BinopI { op=add, lhs=v856, rhs_imm=8 } -> x0 - v858 Store { addr=v855, disp=0, value=v857, kind=I64 } -> - - v859 Imm(13) -> x1 - v860 Store { addr=v857, disp=0, value=v859, kind=I64 } -> - - v861 Imm(151) -> x7 - v862 Call { target_pc=7, args=[v861], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v863 Load { addr=v855, disp=0, kind=I64 } -> x0 - v864 BinopI { op=add, lhs=v863, rhs_imm=8 } -> x0 - v865 Store { addr=v855, disp=0, value=v864, kind=I64 } -> - - v866 Imm(17) -> x1 - v867 Store { addr=v864, disp=0, value=v866, kind=I64 } -> - - v868 ImmData(1848) -> x0 - v869 Imm(1) -> x1 - v870 Store { addr=v868, disp=0, value=v869, kind=I64 } -> - - terminator Jmp(b172) (exit_acc=v870) + v312 ImmData(1832) -> x0 + v313 Load { addr=v3, disp=0, kind=I64 } -> x0 + v314 BinopI { op=eq, lhs=v313, rhs_imm=159 } -> x0 + terminator Bz { cond=v314, target=b179, fall=b172 } (exit_acc=v314) block 172 start_pc=0 - terminator Jmp(b169) + v367 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v368 Imm(162) -> x7 + v369 Call { target_pc=7, args=[v368], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v370 ImmData(1848) -> x0 + v371 Load { addr=v370, disp=0, kind=I64 } -> x0 + v372 BinopI { op=gt, lhs=v371, rhs_imm=1 } -> x0 + terminator Bz { cond=v372, target=b178, fall=b173 } (exit_acc=v372) block 173 start_pc=0 - v871 ImmData(1832) -> x0 - v872 Load { addr=v3, disp=0, kind=I64 } -> x0 - v873 BinopI { op=eq, lhs=v872, rhs_imm=150 } -> x0 - terminator Bz { cond=v873, target=b176, fall=b174 } (exit_acc=v873) + v376 ImmData(1848) -> x0 + v377 Load { addr=v376, disp=0, kind=I64 } -> x1 + v378 BinopI { op=sub, lhs=v377, rhs_imm=2 } -> x1 + v379 Store { addr=v376, disp=0, value=v378, kind=I64 } -> - + terminator Jmp(b174) (exit_acc=v379) block 174 start_pc=0 - v874 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v875 ImmData(1800) -> x13 - v876 Load { addr=v875, disp=0, kind=I64 } -> x0 - v877 BinopI { op=add, lhs=v876, rhs_imm=8 } -> x0 - v878 Store { addr=v875, disp=0, value=v877, kind=I64 } -> - - v879 Imm(13) -> x1 - v880 Store { addr=v877, disp=0, value=v879, kind=I64 } -> - - v881 Imm(151) -> x7 - v882 Call { target_pc=7, args=[v881], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v883 Load { addr=v875, disp=0, kind=I64 } -> x0 - v884 BinopI { op=add, lhs=v883, rhs_imm=8 } -> x0 - v885 Store { addr=v875, disp=0, value=v884, kind=I64 } -> - - v886 Imm(18) -> x1 - v887 Store { addr=v884, disp=0, value=v886, kind=I64 } -> - - v888 ImmData(1848) -> x0 - v889 Imm(1) -> x1 - v890 Store { addr=v888, disp=0, value=v889, kind=I64 } -> - - terminator Jmp(b175) (exit_acc=v890) + v380 ImmData(1800) -> x0 + v381 Load { addr=v380, disp=0, kind=I64 } -> x1 + v382 BinopI { op=add, lhs=v381, rhs_imm=8 } -> x1 + v383 Store { addr=v380, disp=0, value=v382, kind=I64 } -> - + v384 ImmData(1848) -> x0 + v385 Load { addr=v384, disp=0, kind=I64 } -> x0 + v386 BinopI { op=eq, lhs=v385, rhs_imm=0 } -> x0 + terminator Bz { cond=v386, target=b177, fall=b175 } (exit_acc=v386) block 175 start_pc=0 - terminator Jmp(b172) + v393 Imm(10) -> x2 + v394 Imm(0) -> x0 + terminator Jmp(b176) (exit_acc=v393) block 176 start_pc=0 - v891 ImmData(1832) -> x0 - v892 Load { addr=v3, disp=0, kind=I64 } -> x0 - v893 BinopI { op=eq, lhs=v892, rhs_imm=151 } -> x0 - terminator Bz { cond=v893, target=b179, fall=b177 } (exit_acc=v893) + v397 Phi { incoming=[b175:v393, b177:v395], kind=I64 } -> x2 + v398 LoadLocal { off=-10, kind=I64 } -> x0 + v399 Store { addr=v382, disp=0, value=v397, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v399) block 177 start_pc=0 - v894 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v895 ImmData(1800) -> x13 - v896 Load { addr=v895, disp=0, kind=I64 } -> x0 - v897 BinopI { op=add, lhs=v896, rhs_imm=8 } -> x0 - v898 Store { addr=v895, disp=0, value=v897, kind=I64 } -> - - v899 Imm(13) -> x1 - v900 Store { addr=v897, disp=0, value=v899, kind=I64 } -> - - v901 Imm(155) -> x7 - v902 Call { target_pc=7, args=[v901], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v903 Load { addr=v895, disp=0, kind=I64 } -> x0 - v904 BinopI { op=add, lhs=v903, rhs_imm=8 } -> x0 - v905 Store { addr=v895, disp=0, value=v904, kind=I64 } -> - - v906 Imm(19) -> x1 - v907 Store { addr=v904, disp=0, value=v906, kind=I64 } -> - - v908 ImmData(1848) -> x0 - v909 Imm(1) -> x1 - v910 Store { addr=v908, disp=0, value=v909, kind=I64 } -> - - terminator Jmp(b178) (exit_acc=v910) + v395 Imm(9) -> x2 + v396 Imm(0) -> x0 + terminator Jmp(b176) (exit_acc=v395) block 178 start_pc=0 - terminator Jmp(b175) + v387 ImmData(442) -> x7 + v388 ImmData(1864) -> x0 + v389 Load { addr=v388, disp=0, kind=I64 } -> x6 + v390 CallExt { binding_idx=0, args=[v387, v389], fp_arg_mask=0x0 } -> x0 + v391 Imm(-1) -> x7 + v392 CallExt { binding_idx=69, args=[v391], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b174) (exit_acc=v392) block 179 start_pc=0 - v911 ImmData(1832) -> x0 - v912 Load { addr=v3, disp=0, kind=I64 } -> x0 - v913 BinopI { op=eq, lhs=v912, rhs_imm=152 } -> x0 - terminator Bz { cond=v913, target=b182, fall=b180 } (exit_acc=v913) + v373 ImmData(1832) -> x0 + v374 Load { addr=v3, disp=0, kind=I64 } -> x0 + v375 BinopI { op=eq, lhs=v374, rhs_imm=148 } -> x0 + terminator Bz { cond=v375, target=b187, fall=b180 } (exit_acc=v375) block 180 start_pc=0 - v914 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v915 ImmData(1800) -> x13 - v916 Load { addr=v915, disp=0, kind=I64 } -> x0 - v917 BinopI { op=add, lhs=v916, rhs_imm=8 } -> x0 - v918 Store { addr=v915, disp=0, value=v917, kind=I64 } -> - - v919 Imm(13) -> x1 - v920 Store { addr=v917, disp=0, value=v919, kind=I64 } -> - - v921 Imm(155) -> x7 - v922 Call { target_pc=7, args=[v921], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v923 Load { addr=v915, disp=0, kind=I64 } -> x0 - v924 BinopI { op=add, lhs=v923, rhs_imm=8 } -> x0 - v925 Store { addr=v915, disp=0, value=v924, kind=I64 } -> - - v926 Imm(20) -> x1 - v927 Store { addr=v924, disp=0, value=v926, kind=I64 } -> - - v928 ImmData(1848) -> x0 - v929 Imm(1) -> x1 - v930 Store { addr=v928, disp=0, value=v929, kind=I64 } -> - - terminator Jmp(b181) (exit_acc=v930) + v400 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v401 Imm(162) -> x7 + v402 Call { target_pc=7, args=[v401], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v403 ImmData(1800) -> x0 + v404 Load { addr=v403, disp=0, kind=I64 } -> x0 + v405 Load { addr=v404, disp=0, kind=I64 } -> x0 + v406 BinopI { op=eq, lhs=v405, rhs_imm=10 } -> x1 + v407 Imm(0) -> x0 + terminator Bnz { cond=v406, target=b186, fall=b181 } (exit_acc=v406) block 181 start_pc=0 - terminator Jmp(b178) + v411 ImmData(1800) -> x0 + v412 Load { addr=v411, disp=0, kind=I64 } -> x0 + v413 Load { addr=v412, disp=0, kind=I64 } -> x0 + v414 BinopI { op=eq, lhs=v413, rhs_imm=9 } -> x1 + v415 Imm(0) -> x0 + terminator Jmp(b182) (exit_acc=v414) block 182 start_pc=0 - v931 ImmData(1832) -> x0 - v932 Load { addr=v3, disp=0, kind=I64 } -> x0 - v933 BinopI { op=eq, lhs=v932, rhs_imm=153 } -> x0 - terminator Bz { cond=v933, target=b185, fall=b183 } (exit_acc=v933) + v416 Phi { incoming=[b186:v406, b181:v414], kind=I64 } -> x1 + v417 LoadLocal { off=-11, kind=I64 } -> x0 + terminator Bz { cond=v416, target=b185, fall=b183 } (exit_acc=v416) block 183 start_pc=0 - v934 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v935 ImmData(1800) -> x13 - v936 Load { addr=v935, disp=0, kind=I64 } -> x0 - v937 BinopI { op=add, lhs=v936, rhs_imm=8 } -> x0 - v938 Store { addr=v935, disp=0, value=v937, kind=I64 } -> - - v939 Imm(13) -> x1 - v940 Store { addr=v937, disp=0, value=v939, kind=I64 } -> - - v941 Imm(155) -> x7 - v942 Call { target_pc=7, args=[v941], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v943 Load { addr=v935, disp=0, kind=I64 } -> x0 - v944 BinopI { op=add, lhs=v943, rhs_imm=8 } -> x0 - v945 Store { addr=v935, disp=0, value=v944, kind=I64 } -> - - v946 Imm(21) -> x1 - v947 Store { addr=v944, disp=0, value=v946, kind=I64 } -> - - v948 ImmData(1848) -> x0 - v949 Imm(1) -> x1 - v950 Store { addr=v948, disp=0, value=v949, kind=I64 } -> - - terminator Jmp(b184) (exit_acc=v950) + v418 ImmData(1800) -> x0 + v419 Load { addr=v418, disp=0, kind=I64 } -> x1 + v420 BinopI { op=add, lhs=v419, rhs_imm=-8 } -> x1 + v421 Store { addr=v418, disp=0, value=v420, kind=I64 } -> - + terminator Jmp(b184) (exit_acc=v421) block 184 start_pc=0 - terminator Jmp(b181) + v422 ImmData(1848) -> x0 + v423 Load { addr=v422, disp=0, kind=I64 } -> x1 + v424 BinopI { op=add, lhs=v423, rhs_imm=2 } -> x1 + v425 Store { addr=v422, disp=0, value=v424, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v425) block 185 start_pc=0 - v951 ImmData(1832) -> x0 - v952 Load { addr=v3, disp=0, kind=I64 } -> x0 - v953 BinopI { op=eq, lhs=v952, rhs_imm=154 } -> x0 - terminator Bz { cond=v953, target=b188, fall=b186 } (exit_acc=v953) + v426 ImmData(463) -> x7 + v427 ImmData(1864) -> x0 + v428 Load { addr=v427, disp=0, kind=I64 } -> x6 + v429 CallExt { binding_idx=0, args=[v426, v428], fp_arg_mask=0x0 } -> x0 + v430 Imm(-1) -> x7 + v431 CallExt { binding_idx=69, args=[v430], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b184) (exit_acc=v431) block 186 start_pc=0 - v954 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v955 ImmData(1800) -> x13 - v956 Load { addr=v955, disp=0, kind=I64 } -> x0 - v957 BinopI { op=add, lhs=v956, rhs_imm=8 } -> x0 - v958 Store { addr=v955, disp=0, value=v957, kind=I64 } -> - - v959 Imm(13) -> x1 - v960 Store { addr=v957, disp=0, value=v959, kind=I64 } -> - - v961 Imm(155) -> x7 - v962 Call { target_pc=7, args=[v961], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v963 Load { addr=v955, disp=0, kind=I64 } -> x0 - v964 BinopI { op=add, lhs=v963, rhs_imm=8 } -> x0 - v965 Store { addr=v955, disp=0, value=v964, kind=I64 } -> - - v966 Imm(22) -> x1 - v967 Store { addr=v964, disp=0, value=v966, kind=I64 } -> - - v968 ImmData(1848) -> x0 - v969 Imm(1) -> x1 - v970 Store { addr=v968, disp=0, value=v969, kind=I64 } -> - - terminator Jmp(b187) (exit_acc=v970) + terminator Jmp(b182) block 187 start_pc=0 - terminator Jmp(b184) + v408 ImmData(1832) -> x0 + v409 Load { addr=v3, disp=0, kind=I64 } -> x0 + v410 BinopI { op=eq, lhs=v409, rhs_imm=33 } -> x0 + terminator Bz { cond=v410, target=b189, fall=b188 } (exit_acc=v410) block 188 start_pc=0 - v971 ImmData(1832) -> x0 - v972 Load { addr=v3, disp=0, kind=I64 } -> x0 - v973 BinopI { op=eq, lhs=v972, rhs_imm=155 } -> x0 - terminator Bz { cond=v973, target=b191, fall=b189 } (exit_acc=v973) + v432 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v433 Imm(162) -> x7 + v434 Call { target_pc=7, args=[v433], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v435 ImmData(1800) -> x0 + v436 Load { addr=v435, disp=0, kind=I64 } -> x1 + v437 BinopI { op=add, lhs=v436, rhs_imm=8 } -> x1 + v438 Store { addr=v435, disp=0, value=v437, kind=I64 } -> - + v439 Imm(13) -> x2 + v440 Store { addr=v437, disp=0, value=v439, kind=I64 } -> - + v441 Load { addr=v435, disp=0, kind=I64 } -> x1 + v442 BinopI { op=add, lhs=v441, rhs_imm=8 } -> x1 + v443 Store { addr=v435, disp=0, value=v442, kind=I64 } -> - + v444 Imm(1) -> x2 + v445 Store { addr=v442, disp=0, value=v444, kind=I64 } -> - + v446 Load { addr=v435, disp=0, kind=I64 } -> x1 + v447 BinopI { op=add, lhs=v446, rhs_imm=8 } -> x1 + v448 Store { addr=v435, disp=0, value=v447, kind=I64 } -> - + v449 Imm(0) -> x6 + v450 Store { addr=v447, disp=0, value=v449, kind=I64 } -> - + v451 Load { addr=v435, disp=0, kind=I64 } -> x1 + v452 BinopI { op=add, lhs=v451, rhs_imm=8 } -> x1 + v453 Store { addr=v435, disp=0, value=v452, kind=I64 } -> - + v454 Imm(17) -> x0 + v455 Store { addr=v452, disp=0, value=v454, kind=I64 } -> - + v456 ImmData(1848) -> x0 + v457 Store { addr=v456, disp=0, value=v444, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v457) block 189 start_pc=0 - v974 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v975 ImmData(1800) -> x13 - v976 Load { addr=v975, disp=0, kind=I64 } -> x0 - v977 BinopI { op=add, lhs=v976, rhs_imm=8 } -> x0 - v978 Store { addr=v975, disp=0, value=v977, kind=I64 } -> - - v979 Imm(13) -> x1 - v980 Store { addr=v977, disp=0, value=v979, kind=I64 } -> - - v981 Imm(157) -> x7 - v982 Call { target_pc=7, args=[v981], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v983 Load { addr=v975, disp=0, kind=I64 } -> x0 - v984 BinopI { op=add, lhs=v983, rhs_imm=8 } -> x0 - v985 Store { addr=v975, disp=0, value=v984, kind=I64 } -> - - v986 Imm(23) -> x1 - v987 Store { addr=v984, disp=0, value=v986, kind=I64 } -> - - v988 ImmData(1848) -> x0 - v989 Imm(1) -> x1 - v990 Store { addr=v988, disp=0, value=v989, kind=I64 } -> - - terminator Jmp(b190) (exit_acc=v990) + v458 ImmData(1832) -> x0 + v459 Load { addr=v3, disp=0, kind=I64 } -> x0 + v460 BinopI { op=eq, lhs=v459, rhs_imm=126 } -> x0 + terminator Bz { cond=v460, target=b191, fall=b190 } (exit_acc=v460) block 190 start_pc=0 - terminator Jmp(b187) + v461 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v462 Imm(162) -> x7 + v463 Call { target_pc=7, args=[v462], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v464 ImmData(1800) -> x0 + v465 Load { addr=v464, disp=0, kind=I64 } -> x1 + v466 BinopI { op=add, lhs=v465, rhs_imm=8 } -> x1 + v467 Store { addr=v464, disp=0, value=v466, kind=I64 } -> - + v468 Imm(13) -> x2 + v469 Store { addr=v466, disp=0, value=v468, kind=I64 } -> - + v470 Load { addr=v464, disp=0, kind=I64 } -> x1 + v471 BinopI { op=add, lhs=v470, rhs_imm=8 } -> x1 + v472 Store { addr=v464, disp=0, value=v471, kind=I64 } -> - + v473 Imm(1) -> x2 + v474 Store { addr=v471, disp=0, value=v473, kind=I64 } -> - + v475 Load { addr=v464, disp=0, kind=I64 } -> x1 + v476 BinopI { op=add, lhs=v475, rhs_imm=8 } -> x1 + v477 Store { addr=v464, disp=0, value=v476, kind=I64 } -> - + v478 Imm(-1) -> x6 + v479 Store { addr=v476, disp=0, value=v478, kind=I64 } -> - + v480 Load { addr=v464, disp=0, kind=I64 } -> x1 + v481 BinopI { op=add, lhs=v480, rhs_imm=8 } -> x1 + v482 Store { addr=v464, disp=0, value=v481, kind=I64 } -> - + v483 Imm(15) -> x0 + v484 Store { addr=v481, disp=0, value=v483, kind=I64 } -> - + v485 ImmData(1848) -> x0 + v486 Store { addr=v485, disp=0, value=v473, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v486) block 191 start_pc=0 - v991 ImmData(1832) -> x0 - v992 Load { addr=v3, disp=0, kind=I64 } -> x0 - v993 BinopI { op=eq, lhs=v992, rhs_imm=156 } -> x0 - terminator Bz { cond=v993, target=b194, fall=b192 } (exit_acc=v993) + v487 ImmData(1832) -> x0 + v488 Load { addr=v3, disp=0, kind=I64 } -> x0 + v489 BinopI { op=eq, lhs=v488, rhs_imm=157 } -> x0 + terminator Bz { cond=v489, target=b193, fall=b192 } (exit_acc=v489) block 192 start_pc=0 - v994 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v995 ImmData(1800) -> x13 - v996 Load { addr=v995, disp=0, kind=I64 } -> x0 - v997 BinopI { op=add, lhs=v996, rhs_imm=8 } -> x0 - v998 Store { addr=v995, disp=0, value=v997, kind=I64 } -> - - v999 Imm(13) -> x1 - v1000 Store { addr=v997, disp=0, value=v999, kind=I64 } -> - - v1001 Imm(157) -> x7 - v1002 Call { target_pc=7, args=[v1001], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1003 Load { addr=v995, disp=0, kind=I64 } -> x0 - v1004 BinopI { op=add, lhs=v1003, rhs_imm=8 } -> x0 - v1005 Store { addr=v995, disp=0, value=v1004, kind=I64 } -> - - v1006 Imm(24) -> x1 - v1007 Store { addr=v1004, disp=0, value=v1006, kind=I64 } -> - - v1008 ImmData(1848) -> x0 - v1009 Imm(1) -> x1 - v1010 Store { addr=v1008, disp=0, value=v1009, kind=I64 } -> - - terminator Jmp(b193) (exit_acc=v1010) + v490 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v491 Imm(162) -> x7 + v492 Call { target_pc=7, args=[v491], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v493 ImmData(1848) -> x0 + v494 Imm(1) -> x1 + v495 Store { addr=v493, disp=0, value=v494, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v495) block 193 start_pc=0 - terminator Jmp(b190) + v496 ImmData(1832) -> x0 + v497 Load { addr=v3, disp=0, kind=I64 } -> x0 + v498 BinopI { op=eq, lhs=v497, rhs_imm=158 } -> x0 + terminator Bz { cond=v498, target=b198, fall=b194 } (exit_acc=v498) block 194 start_pc=0 - v1011 ImmData(1832) -> x0 - v1012 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1013 BinopI { op=eq, lhs=v1012, rhs_imm=157 } -> x0 - terminator Bz { cond=v1013, target=b197, fall=b195 } (exit_acc=v1013) + v499 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v500 ImmData(1800) -> x0 + v501 Load { addr=v500, disp=0, kind=I64 } -> x1 + v502 BinopI { op=add, lhs=v501, rhs_imm=8 } -> x1 + v503 Store { addr=v500, disp=0, value=v502, kind=I64 } -> - + v504 Imm(1) -> x0 + v505 Store { addr=v502, disp=0, value=v504, kind=I64 } -> - + v506 ImmData(1832) -> x0 + v507 Load { addr=v3, disp=0, kind=I64 } -> x0 + v508 BinopI { op=eq, lhs=v507, rhs_imm=128 } -> x0 + terminator Bz { cond=v508, target=b197, fall=b195 } (exit_acc=v508) block 195 start_pc=0 - v1014 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1015 ImmData(1800) -> x0 - v1016 Load { addr=v1015, disp=0, kind=I64 } -> x1 - v1017 BinopI { op=add, lhs=v1016, rhs_imm=8 } -> x1 - v1018 Store { addr=v1015, disp=0, value=v1017, kind=I64 } -> - - v1019 Imm(13) -> x0 - v1020 Store { addr=v1017, disp=0, value=v1019, kind=I64 } -> - - v1021 Imm(159) -> x7 - v1022 Call { target_pc=7, args=[v1021], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1023 ImmData(1848) -> x0 - v1024 LoadLocal { off=-1, kind=I64 } -> x1 - v1025 Store { addr=v1023, disp=0, value=v649, kind=I64 } -> - - v1026 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 - terminator Bz { cond=v1026, target=b199, fall=b198 } (exit_acc=v1026) + v513 ImmData(1800) -> x0 + v514 Load { addr=v513, disp=0, kind=I64 } -> x1 + v515 BinopI { op=add, lhs=v514, rhs_imm=8 } -> x1 + v516 Store { addr=v513, disp=0, value=v515, kind=I64 } -> - + v517 ImmData(1840) -> x0 + v518 Load { addr=v517, disp=0, kind=I64 } -> x0 + v519 BinopI { op=mul, lhs=v518, rhs_imm=-1 } -> x0 + v520 Store { addr=v515, disp=0, value=v519, kind=I64 } -> - + v521 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b196) (exit_acc=v521) block 196 start_pc=0 - terminator Jmp(b193) + v522 ImmData(1848) -> x0 + v523 Imm(1) -> x1 + v524 Store { addr=v522, disp=0, value=v523, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v524) block 197 start_pc=0 - v1027 ImmData(1832) -> x0 - v1028 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1029 BinopI { op=eq, lhs=v1028, rhs_imm=158 } -> x0 - terminator Bz { cond=v1029, target=b202, fall=b200 } (exit_acc=v1029) + v525 ImmData(1800) -> x13 + v526 Load { addr=v525, disp=0, kind=I64 } -> x0 + v527 BinopI { op=add, lhs=v526, rhs_imm=8 } -> x0 + v528 Store { addr=v525, disp=0, value=v527, kind=I64 } -> - + v529 Imm(-1) -> x1 + v530 Store { addr=v527, disp=0, value=v529, kind=I64 } -> - + v531 Load { addr=v525, disp=0, kind=I64 } -> x0 + v532 BinopI { op=add, lhs=v531, rhs_imm=8 } -> x0 + v533 Store { addr=v525, disp=0, value=v532, kind=I64 } -> - + v534 Imm(13) -> x1 + v535 Store { addr=v532, disp=0, value=v534, kind=I64 } -> - + v536 Imm(162) -> x7 + v537 Call { target_pc=7, args=[v536], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v538 Load { addr=v525, disp=0, kind=I64 } -> x0 + v539 BinopI { op=add, lhs=v538, rhs_imm=8 } -> x0 + v540 Store { addr=v525, disp=0, value=v539, kind=I64 } -> - + v541 Imm(27) -> x1 + v542 Store { addr=v539, disp=0, value=v541, kind=I64 } -> - + terminator Jmp(b196) (exit_acc=v542) block 198 start_pc=0 - v1030 ImmData(1800) -> x0 - v1031 Load { addr=v1030, disp=0, kind=I64 } -> x1 - v1032 BinopI { op=add, lhs=v1031, rhs_imm=8 } -> x1 - v1033 Store { addr=v1030, disp=0, value=v1032, kind=I64 } -> - - v1034 Imm(13) -> x2 - v1035 Store { addr=v1032, disp=0, value=v1034, kind=I64 } -> - - v1036 Load { addr=v1030, disp=0, kind=I64 } -> x1 - v1037 BinopI { op=add, lhs=v1036, rhs_imm=8 } -> x1 - v1038 Store { addr=v1030, disp=0, value=v1037, kind=I64 } -> - - v1039 Imm(1) -> x2 - v1040 Store { addr=v1037, disp=0, value=v1039, kind=I64 } -> - - v1041 Load { addr=v1030, disp=0, kind=I64 } -> x1 - v1042 BinopI { op=add, lhs=v1041, rhs_imm=8 } -> x1 - v1043 Store { addr=v1030, disp=0, value=v1042, kind=I64 } -> - - v1044 Imm(8) -> x2 - v1045 Store { addr=v1042, disp=0, value=v1044, kind=I64 } -> - - v1046 Load { addr=v1030, disp=0, kind=I64 } -> x1 - v1047 BinopI { op=add, lhs=v1046, rhs_imm=8 } -> x1 - v1048 Store { addr=v1030, disp=0, value=v1047, kind=I64 } -> - - v1049 Imm(27) -> x0 - v1050 Store { addr=v1047, disp=0, value=v1049, kind=I64 } -> - - terminator Jmp(b199) (exit_acc=v1050) + v509 ImmData(1832) -> x0 + v510 Load { addr=v3, disp=0, kind=I64 } -> x0 + v511 BinopI { op=eq, lhs=v510, rhs_imm=162 } -> x1 + v512 Imm(0) -> x0 + terminator Bnz { cond=v511, target=b217, fall=b199 } (exit_acc=v511) block 199 start_pc=0 - v1051 ImmData(1800) -> x0 - v1052 Load { addr=v1051, disp=0, kind=I64 } -> x1 - v1053 BinopI { op=add, lhs=v1052, rhs_imm=8 } -> x1 - v1054 Store { addr=v1051, disp=0, value=v1053, kind=I64 } -> - - v1055 Imm(25) -> x0 - v1056 Store { addr=v1053, disp=0, value=v1055, kind=I64 } -> - - terminator Jmp(b196) (exit_acc=v1056) + v543 ImmData(1832) -> x0 + v544 Load { addr=v3, disp=0, kind=I64 } -> x0 + v545 BinopI { op=eq, lhs=v544, rhs_imm=163 } -> x1 + v546 Imm(0) -> x0 + terminator Jmp(b200) (exit_acc=v545) block 200 start_pc=0 - v1057 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1058 ImmData(1800) -> x0 - v1059 Load { addr=v1058, disp=0, kind=I64 } -> x1 - v1060 BinopI { op=add, lhs=v1059, rhs_imm=8 } -> x1 - v1061 Store { addr=v1058, disp=0, value=v1060, kind=I64 } -> - - v1062 Imm(13) -> x0 - v1063 Store { addr=v1060, disp=0, value=v1062, kind=I64 } -> - - v1064 Imm(159) -> x7 - v1065 Call { target_pc=7, args=[v1064], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1066 LoadLocal { off=-1, kind=I64 } -> x0 - v1067 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x14 - v1068 Imm(0) -> x0 - terminator Bz { cond=v1067, target=b264, fall=b203 } (exit_acc=v1067) + v547 Phi { incoming=[b217:v511, b199:v545], kind=I64 } -> x1 + v548 LoadLocal { off=-12, kind=I64 } -> x0 + terminator Bz { cond=v547, target=b216, fall=b201 } (exit_acc=v547) block 201 start_pc=0 - terminator Jmp(b196) + v549 ImmData(1832) -> x0 + v550 Load { addr=v3, disp=0, kind=I64 } -> x13 + v551 Imm(0) -> x0 + v552 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v553 Imm(162) -> x7 + v554 Call { target_pc=7, args=[v553], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v555 ImmData(1800) -> x0 + v556 Load { addr=v555, disp=0, kind=I64 } -> x0 + v557 Load { addr=v556, disp=0, kind=I64 } -> x0 + v558 BinopI { op=eq, lhs=v557, rhs_imm=10 } -> x0 + terminator Bz { cond=v558, target=b213, fall=b202 } (exit_acc=v558) block 202 start_pc=0 - v1069 ImmData(1832) -> x0 - v1070 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1071 BinopI { op=eq, lhs=v1070, rhs_imm=159 } -> x0 - terminator Bz { cond=v1071, target=b213, fall=b211 } (exit_acc=v1071) + v565 ImmData(1800) -> x0 + v566 Load { addr=v565, disp=0, kind=I64 } -> x1 + v567 Imm(13) -> x2 + v568 Store { addr=v566, disp=0, value=v567, kind=I64 } -> - + v569 Load { addr=v565, disp=0, kind=I64 } -> x1 + v570 BinopI { op=add, lhs=v569, rhs_imm=8 } -> x1 + v571 Store { addr=v565, disp=0, value=v570, kind=I64 } -> - + v572 Imm(10) -> x0 + v573 Store { addr=v570, disp=0, value=v572, kind=I64 } -> - + terminator Jmp(b203) (exit_acc=v573) block 203 start_pc=0 - v1072 LoadLocal { off=-1, kind=I64 } -> x0 - v1073 ImmData(1848) -> x0 - v1074 Load { addr=v1073, disp=0, kind=I64 } -> x0 - v1075 Binop { op=eq, lhs=v649, rhs=v1074 } -> x14 - v1076 Imm(0) -> x0 - terminator Jmp(b204) (exit_acc=v1075) + v574 ImmData(1800) -> x0 + v575 Load { addr=v574, disp=0, kind=I64 } -> x1 + v576 BinopI { op=add, lhs=v575, rhs_imm=8 } -> x1 + v577 Store { addr=v574, disp=0, value=v576, kind=I64 } -> - + v578 Imm(13) -> x2 + v579 Store { addr=v576, disp=0, value=v578, kind=I64 } -> - + v580 Load { addr=v574, disp=0, kind=I64 } -> x1 + v581 BinopI { op=add, lhs=v580, rhs_imm=8 } -> x1 + v582 Store { addr=v574, disp=0, value=v581, kind=I64 } -> - + v583 Imm(1) -> x2 + v584 Store { addr=v581, disp=0, value=v583, kind=I64 } -> - + v585 Load { addr=v574, disp=0, kind=I64 } -> x1 + v586 BinopI { op=add, lhs=v585, rhs_imm=8 } -> x1 + v587 Store { addr=v574, disp=0, value=v586, kind=I64 } -> - + v588 ImmData(1848) -> x0 + v589 Load { addr=v588, disp=0, kind=I64 } -> x0 + v590 BinopI { op=gt, lhs=v589, rhs_imm=2 } -> x0 + terminator Bz { cond=v590, target=b212, fall=b204 } (exit_acc=v590) block 204 start_pc=0 - v1077 Phi { incoming=[b264:v1067, b203:v1075], kind=I64 } -> x14 - v1078 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v1077, target=b207, fall=b205 } (exit_acc=v1077) + v610 Imm(8) -> x2 + v611 Imm(0) -> x0 + terminator Jmp(b205) (exit_acc=v610) block 205 start_pc=0 - v1079 ImmData(1800) -> x0 - v1080 Load { addr=v1079, disp=0, kind=I64 } -> x1 - v1081 BinopI { op=add, lhs=v1080, rhs_imm=8 } -> x1 - v1082 Store { addr=v1079, disp=0, value=v1081, kind=I64 } -> - - v1083 Imm(26) -> x2 - v1084 Store { addr=v1081, disp=0, value=v1083, kind=I64 } -> - - v1085 Load { addr=v1079, disp=0, kind=I64 } -> x1 - v1086 BinopI { op=add, lhs=v1085, rhs_imm=8 } -> x1 - v1087 Store { addr=v1079, disp=0, value=v1086, kind=I64 } -> - - v1088 Imm(13) -> x2 - v1089 Store { addr=v1086, disp=0, value=v1088, kind=I64 } -> - - v1090 Load { addr=v1079, disp=0, kind=I64 } -> x1 - v1091 BinopI { op=add, lhs=v1090, rhs_imm=8 } -> x1 - v1092 Store { addr=v1079, disp=0, value=v1091, kind=I64 } -> - - v1093 Imm(1) -> x2 - v1094 Store { addr=v1091, disp=0, value=v1093, kind=I64 } -> - - v1095 Load { addr=v1079, disp=0, kind=I64 } -> x1 - v1096 BinopI { op=add, lhs=v1095, rhs_imm=8 } -> x1 - v1097 Store { addr=v1079, disp=0, value=v1096, kind=I64 } -> - - v1098 Imm(8) -> x6 - v1099 Store { addr=v1096, disp=0, value=v1098, kind=I64 } -> - - v1100 Load { addr=v1079, disp=0, kind=I64 } -> x1 - v1101 BinopI { op=add, lhs=v1100, rhs_imm=8 } -> x1 - v1102 Store { addr=v1079, disp=0, value=v1101, kind=I64 } -> - - v1103 Imm(28) -> x0 - v1104 Store { addr=v1101, disp=0, value=v1103, kind=I64 } -> - - v1105 ImmData(1848) -> x0 - v1106 Store { addr=v1105, disp=0, value=v1093, kind=I64 } -> - - terminator Jmp(b206) (exit_acc=v1106) + v614 Phi { incoming=[b204:v610, b212:v612], kind=I64 } -> x2 + v615 LoadLocal { off=-13, kind=I64 } -> x0 + v616 Store { addr=v586, disp=0, value=v614, kind=I64 } -> - + v617 ImmData(1800) -> x0 + v618 Load { addr=v617, disp=0, kind=I64 } -> x1 + v619 BinopI { op=add, lhs=v618, rhs_imm=8 } -> x1 + v620 Store { addr=v617, disp=0, value=v619, kind=I64 } -> - + v621 LoadLocal { off=-1, kind=I64 } -> x0 + v622 BinopI { op=eq, lhs=v550, rhs_imm=162 } -> x0 + terminator Bz { cond=v622, target=b211, fall=b206 } (exit_acc=v622) block 206 start_pc=0 - terminator Jmp(b201) + v623 Imm(25) -> x2 + v624 Imm(0) -> x0 + terminator Jmp(b207) (exit_acc=v623) block 207 start_pc=0 - v1107 ImmData(1848) -> x0 - v1108 LoadLocal { off=-1, kind=I64 } -> x1 - v1109 Store { addr=v1107, disp=0, value=v649, kind=I64 } -> - - v1110 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 - terminator Bz { cond=v1110, target=b210, fall=b208 } (exit_acc=v1110) + v627 Phi { incoming=[b206:v623, b211:v625], kind=I64 } -> x2 + v628 LoadLocal { off=-14, kind=I64 } -> x0 + v629 Store { addr=v619, disp=0, value=v627, kind=I64 } -> - + v630 ImmData(1800) -> x0 + v631 Load { addr=v630, disp=0, kind=I64 } -> x1 + v632 BinopI { op=add, lhs=v631, rhs_imm=8 } -> x1 + v633 Store { addr=v630, disp=0, value=v632, kind=I64 } -> - + v634 ImmData(1848) -> x0 + v635 Load { addr=v634, disp=0, kind=I64 } -> x0 + v636 BinopI { op=eq, lhs=v635, rhs_imm=0 } -> x0 + terminator Bz { cond=v636, target=b210, fall=b208 } (exit_acc=v636) block 208 start_pc=0 - v1111 ImmData(1800) -> x0 - v1112 Load { addr=v1111, disp=0, kind=I64 } -> x1 - v1113 BinopI { op=add, lhs=v1112, rhs_imm=8 } -> x1 - v1114 Store { addr=v1111, disp=0, value=v1113, kind=I64 } -> - - v1115 Imm(13) -> x2 - v1116 Store { addr=v1113, disp=0, value=v1115, kind=I64 } -> - - v1117 Load { addr=v1111, disp=0, kind=I64 } -> x1 - v1118 BinopI { op=add, lhs=v1117, rhs_imm=8 } -> x1 - v1119 Store { addr=v1111, disp=0, value=v1118, kind=I64 } -> - - v1120 Imm(1) -> x2 - v1121 Store { addr=v1118, disp=0, value=v1120, kind=I64 } -> - - v1122 Load { addr=v1111, disp=0, kind=I64 } -> x1 - v1123 BinopI { op=add, lhs=v1122, rhs_imm=8 } -> x1 - v1124 Store { addr=v1111, disp=0, value=v1123, kind=I64 } -> - - v1125 Imm(8) -> x2 - v1126 Store { addr=v1123, disp=0, value=v1125, kind=I64 } -> - - v1127 Load { addr=v1111, disp=0, kind=I64 } -> x1 - v1128 BinopI { op=add, lhs=v1127, rhs_imm=8 } -> x1 - v1129 Store { addr=v1111, disp=0, value=v1128, kind=I64 } -> - - v1130 Imm(27) -> x2 - v1131 Store { addr=v1128, disp=0, value=v1130, kind=I64 } -> - - v1132 Load { addr=v1111, disp=0, kind=I64 } -> x1 - v1133 BinopI { op=add, lhs=v1132, rhs_imm=8 } -> x1 - v1134 Store { addr=v1111, disp=0, value=v1133, kind=I64 } -> - - v1135 Imm(26) -> x0 - v1136 Store { addr=v1133, disp=0, value=v1135, kind=I64 } -> - - terminator Jmp(b209) (exit_acc=v1136) + v637 Imm(12) -> x2 + v638 Imm(0) -> x0 + terminator Jmp(b209) (exit_acc=v637) block 209 start_pc=0 - terminator Jmp(b206) + v641 Phi { incoming=[b208:v637, b210:v639], kind=I64 } -> x2 + v642 LoadLocal { off=-15, kind=I64 } -> x0 + v643 Store { addr=v632, disp=0, value=v641, kind=I64 } -> - + terminator Jmp(b101) (exit_acc=v643) block 210 start_pc=0 - v1137 ImmData(1800) -> x0 - v1138 Load { addr=v1137, disp=0, kind=I64 } -> x1 - v1139 BinopI { op=add, lhs=v1138, rhs_imm=8 } -> x1 - v1140 Store { addr=v1137, disp=0, value=v1139, kind=I64 } -> - - v1141 Imm(26) -> x0 - v1142 Store { addr=v1139, disp=0, value=v1141, kind=I64 } -> - - terminator Jmp(b209) (exit_acc=v1142) + v639 Imm(11) -> x2 + v640 Imm(0) -> x0 + terminator Jmp(b209) (exit_acc=v639) block 211 start_pc=0 - v1143 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1144 ImmData(1800) -> x13 - v1145 Load { addr=v1144, disp=0, kind=I64 } -> x0 - v1146 BinopI { op=add, lhs=v1145, rhs_imm=8 } -> x0 - v1147 Store { addr=v1144, disp=0, value=v1146, kind=I64 } -> - - v1148 Imm(13) -> x1 - v1149 Store { addr=v1146, disp=0, value=v1148, kind=I64 } -> - - v1150 Imm(162) -> x7 - v1151 Call { target_pc=7, args=[v1150], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1152 Load { addr=v1144, disp=0, kind=I64 } -> x0 - v1153 BinopI { op=add, lhs=v1152, rhs_imm=8 } -> x0 - v1154 Store { addr=v1144, disp=0, value=v1153, kind=I64 } -> - - v1155 Imm(27) -> x1 - v1156 Store { addr=v1153, disp=0, value=v1155, kind=I64 } -> - - v1157 ImmData(1848) -> x0 - v1158 Imm(1) -> x1 - v1159 Store { addr=v1157, disp=0, value=v1158, kind=I64 } -> - - terminator Jmp(b212) (exit_acc=v1159) + v625 Imm(26) -> x2 + v626 Imm(0) -> x0 + terminator Jmp(b207) (exit_acc=v625) block 212 start_pc=0 - terminator Jmp(b201) + v612 Imm(1) -> x2 + v613 Imm(0) -> x0 + terminator Jmp(b205) (exit_acc=v612) block 213 start_pc=0 - v1160 ImmData(1832) -> x0 - v1161 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1162 BinopI { op=eq, lhs=v1161, rhs_imm=160 } -> x0 - terminator Bz { cond=v1162, target=b216, fall=b214 } (exit_acc=v1162) + v591 ImmData(1800) -> x0 + v592 Load { addr=v591, disp=0, kind=I64 } -> x0 + v593 Load { addr=v592, disp=0, kind=I64 } -> x0 + v594 BinopI { op=eq, lhs=v593, rhs_imm=9 } -> x0 + terminator Bz { cond=v594, target=b215, fall=b214 } (exit_acc=v594) block 214 start_pc=0 - v1163 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1164 ImmData(1800) -> x13 - v1165 Load { addr=v1164, disp=0, kind=I64 } -> x0 - v1166 BinopI { op=add, lhs=v1165, rhs_imm=8 } -> x0 - v1167 Store { addr=v1164, disp=0, value=v1166, kind=I64 } -> - - v1168 Imm(13) -> x1 - v1169 Store { addr=v1166, disp=0, value=v1168, kind=I64 } -> - - v1170 Imm(162) -> x7 - v1171 Call { target_pc=7, args=[v1170], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1172 Load { addr=v1164, disp=0, kind=I64 } -> x0 - v1173 BinopI { op=add, lhs=v1172, rhs_imm=8 } -> x0 - v1174 Store { addr=v1164, disp=0, value=v1173, kind=I64 } -> - - v1175 Imm(28) -> x1 - v1176 Store { addr=v1173, disp=0, value=v1175, kind=I64 } -> - - v1177 ImmData(1848) -> x0 - v1178 Imm(1) -> x1 - v1179 Store { addr=v1177, disp=0, value=v1178, kind=I64 } -> - - terminator Jmp(b215) (exit_acc=v1179) + v595 ImmData(1800) -> x0 + v596 Load { addr=v595, disp=0, kind=I64 } -> x1 + v597 Imm(13) -> x2 + v598 Store { addr=v596, disp=0, value=v597, kind=I64 } -> - + v599 Load { addr=v595, disp=0, kind=I64 } -> x1 + v600 BinopI { op=add, lhs=v599, rhs_imm=8 } -> x1 + v601 Store { addr=v595, disp=0, value=v600, kind=I64 } -> - + v602 Imm(9) -> x0 + v603 Store { addr=v600, disp=0, value=v602, kind=I64 } -> - + terminator Jmp(b203) (exit_acc=v603) block 215 start_pc=0 - terminator Jmp(b212) + v604 ImmData(483) -> x7 + v605 ImmData(1864) -> x0 + v606 Load { addr=v605, disp=0, kind=I64 } -> x6 + v607 CallExt { binding_idx=0, args=[v604, v606], fp_arg_mask=0x0 } -> x0 + v608 Imm(-1) -> x7 + v609 CallExt { binding_idx=69, args=[v608], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b203) (exit_acc=v609) block 216 start_pc=0 - v1180 ImmData(1832) -> x0 - v1181 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1182 BinopI { op=eq, lhs=v1181, rhs_imm=161 } -> x0 - terminator Bz { cond=v1182, target=b219, fall=b217 } (exit_acc=v1182) + v559 ImmData(516) -> x7 + v560 ImmData(1864) -> x0 + v561 Load { addr=v560, disp=0, kind=I64 } -> x6 + v562 CallExt { binding_idx=0, args=[v559, v561], fp_arg_mask=0x0 } -> x0 + v563 Imm(-1) -> x7 + v564 CallExt { binding_idx=69, args=[v563], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v564) block 217 start_pc=0 - v1183 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1184 ImmData(1800) -> x13 - v1185 Load { addr=v1184, disp=0, kind=I64 } -> x0 - v1186 BinopI { op=add, lhs=v1185, rhs_imm=8 } -> x0 - v1187 Store { addr=v1184, disp=0, value=v1186, kind=I64 } -> - - v1188 Imm(13) -> x1 - v1189 Store { addr=v1186, disp=0, value=v1188, kind=I64 } -> - - v1190 Imm(162) -> x7 - v1191 Call { target_pc=7, args=[v1190], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1192 Load { addr=v1184, disp=0, kind=I64 } -> x0 - v1193 BinopI { op=add, lhs=v1192, rhs_imm=8 } -> x0 - v1194 Store { addr=v1184, disp=0, value=v1193, kind=I64 } -> - - v1195 Imm(29) -> x1 - v1196 Store { addr=v1193, disp=0, value=v1195, kind=I64 } -> - - v1197 ImmData(1848) -> x0 - v1198 Imm(1) -> x1 - v1199 Store { addr=v1197, disp=0, value=v1198, kind=I64 } -> - - terminator Jmp(b218) (exit_acc=v1199) + terminator Jmp(b200) block 218 start_pc=0 - terminator Jmp(b215) + terminator Jmp(b101) block 219 start_pc=0 - v1200 ImmData(1832) -> x0 - v1201 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1202 BinopI { op=eq, lhs=v1201, rhs_imm=162 } -> x14 - v1203 Imm(0) -> x0 - terminator Bnz { cond=v1202, target=b265, fall=b220 } (exit_acc=v1202) + terminator Jmp(b101) block 220 start_pc=0 - v1204 ImmData(1832) -> x0 - v1205 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1206 BinopI { op=eq, lhs=v1205, rhs_imm=163 } -> x14 - v1207 Imm(0) -> x0 - terminator Jmp(b221) (exit_acc=v1206) + terminator Jmp(b101) block 221 start_pc=0 - v1208 Phi { incoming=[b265:v1202, b220:v1206], kind=I64 } -> x14 - v1209 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v1208, target=b224, fall=b222 } (exit_acc=v1208) + terminator Jmp(b101) block 222 start_pc=0 - v1210 ImmData(1800) -> x0 - v1211 Load { addr=v1210, disp=0, kind=I64 } -> x0 - v1212 Load { addr=v1211, disp=0, kind=I64 } -> x0 - v1213 BinopI { op=eq, lhs=v1212, rhs_imm=10 } -> x0 - terminator Bz { cond=v1213, target=b227, fall=b225 } (exit_acc=v1213) - block 223 start_pc=0 - terminator Jmp(b218) - block 224 start_pc=0 - v1214 ImmData(1832) -> x0 - v1215 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1216 BinopI { op=eq, lhs=v1215, rhs_imm=164 } -> x0 - terminator Bz { cond=v1216, target=b248, fall=b246 } (exit_acc=v1216) - block 225 start_pc=0 - v1217 ImmData(1800) -> x0 - v1218 Load { addr=v1217, disp=0, kind=I64 } -> x1 - v1219 Imm(13) -> x2 - v1220 Store { addr=v1218, disp=0, value=v1219, kind=I64 } -> - - v1221 Load { addr=v1217, disp=0, kind=I64 } -> x1 - v1222 BinopI { op=add, lhs=v1221, rhs_imm=8 } -> x1 - v1223 Store { addr=v1217, disp=0, value=v1222, kind=I64 } -> - - v1224 Imm(10) -> x0 - v1225 Store { addr=v1222, disp=0, value=v1224, kind=I64 } -> - - terminator Jmp(b226) (exit_acc=v1225) - block 226 start_pc=0 - v1226 ImmData(1800) -> x0 - v1227 Load { addr=v1226, disp=0, kind=I64 } -> x1 - v1228 BinopI { op=add, lhs=v1227, rhs_imm=8 } -> x1 - v1229 Store { addr=v1226, disp=0, value=v1228, kind=I64 } -> - - v1230 Imm(13) -> x2 - v1231 Store { addr=v1228, disp=0, value=v1230, kind=I64 } -> - - v1232 Load { addr=v1226, disp=0, kind=I64 } -> x1 - v1233 BinopI { op=add, lhs=v1232, rhs_imm=8 } -> x1 - v1234 Store { addr=v1226, disp=0, value=v1233, kind=I64 } -> - - v1235 Imm(1) -> x2 - v1236 Store { addr=v1233, disp=0, value=v1235, kind=I64 } -> - - v1237 Load { addr=v1226, disp=0, kind=I64 } -> x1 - v1238 BinopI { op=add, lhs=v1237, rhs_imm=8 } -> x13 - v1239 Store { addr=v1226, disp=0, value=v1238, kind=I64 } -> - - v1240 ImmData(1848) -> x0 - v1241 Load { addr=v1240, disp=0, kind=I64 } -> x0 - v1242 BinopI { op=gt, lhs=v1241, rhs_imm=2 } -> x0 - terminator Bz { cond=v1242, target=b232, fall=b231 } (exit_acc=v1242) + terminator Jmp(b116) + block 223 start_pc=0 + terminator Jmp(b116) + block 224 start_pc=0 + terminator Jmp(b101) + block 225 start_pc=0 + terminator Jmp(b101) + block 226 start_pc=0 + terminator Jmp(b136) block 227 start_pc=0 - v1243 ImmData(1800) -> x0 - v1244 Load { addr=v1243, disp=0, kind=I64 } -> x0 - v1245 Load { addr=v1244, disp=0, kind=I64 } -> x0 - v1246 BinopI { op=eq, lhs=v1245, rhs_imm=9 } -> x0 - terminator Bz { cond=v1246, target=b230, fall=b228 } (exit_acc=v1246) + terminator Jmp(b101) block 228 start_pc=0 - v1247 ImmData(1800) -> x0 - v1248 Load { addr=v1247, disp=0, kind=I64 } -> x1 - v1249 Imm(13) -> x2 - v1250 Store { addr=v1248, disp=0, value=v1249, kind=I64 } -> - - v1251 Load { addr=v1247, disp=0, kind=I64 } -> x1 - v1252 BinopI { op=add, lhs=v1251, rhs_imm=8 } -> x1 - v1253 Store { addr=v1247, disp=0, value=v1252, kind=I64 } -> - - v1254 Imm(9) -> x0 - v1255 Store { addr=v1252, disp=0, value=v1254, kind=I64 } -> - - terminator Jmp(b229) (exit_acc=v1255) + terminator Jmp(b146) block 229 start_pc=0 - terminator Jmp(b226) + terminator Jmp(b101) block 230 start_pc=0 - v1256 ImmData(597) -> x7 - v1257 ImmData(1864) -> x0 - v1258 Load { addr=v1257, disp=0, kind=I64 } -> x6 - v1259 CallExt { binding_idx=0, args=[v1256, v1258], fp_arg_mask=0x0 } -> x0 - v1260 Imm(-1) -> x7 - v1261 CallExt { binding_idx=69, args=[v1260], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b229) (exit_acc=v1261) + terminator Jmp(b101) block 231 start_pc=0 - v1262 Imm(8) -> x1 - v1263 Imm(0) -> x0 - terminator Jmp(b233) (exit_acc=v1262) + terminator Jmp(b101) block 232 start_pc=0 - v1264 Imm(1) -> x1 - v1265 Imm(0) -> x0 - terminator Jmp(b233) (exit_acc=v1264) + terminator Jmp(b101) block 233 start_pc=0 - v1266 Phi { incoming=[b231:v1262, b232:v1264], kind=I64 } -> x1 - v1267 LoadLocal { off=-20, kind=I64 } -> x0 - v1268 Store { addr=v1238, disp=0, value=v1266, kind=I64 } -> - - v1269 ImmData(1800) -> x0 - v1270 Load { addr=v1269, disp=0, kind=I64 } -> x1 - v1271 BinopI { op=add, lhs=v1270, rhs_imm=8 } -> x1 - v1272 Store { addr=v1269, disp=0, value=v1271, kind=I64 } -> - - v1273 ImmData(1832) -> x0 - v1274 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1275 BinopI { op=eq, lhs=v1274, rhs_imm=162 } -> x0 - terminator Bz { cond=v1275, target=b235, fall=b234 } (exit_acc=v1275) + terminator Jmp(b101) block 234 start_pc=0 - v1276 Imm(25) -> x2 - v1277 Imm(0) -> x0 - terminator Jmp(b236) (exit_acc=v1276) + terminator Jmp(b101) block 235 start_pc=0 - v1278 Imm(26) -> x2 - v1279 Imm(0) -> x0 - terminator Jmp(b236) (exit_acc=v1278) + terminator Jmp(b101) block 236 start_pc=0 - v1280 Phi { incoming=[b234:v1276, b235:v1278], kind=I64 } -> x2 - v1281 LoadLocal { off=-21, kind=I64 } -> x0 - v1282 Store { addr=v1271, disp=0, value=v1280, kind=I64 } -> - - v1283 ImmData(1800) -> x0 - v1284 Load { addr=v1283, disp=0, kind=I64 } -> x1 - v1285 BinopI { op=add, lhs=v1284, rhs_imm=8 } -> x1 - v1286 Store { addr=v1283, disp=0, value=v1285, kind=I64 } -> - - v1287 ImmData(1848) -> x0 - v1288 Load { addr=v1287, disp=0, kind=I64 } -> x0 - v1289 BinopI { op=eq, lhs=v1288, rhs_imm=0 } -> x0 - terminator Bz { cond=v1289, target=b238, fall=b237 } (exit_acc=v1289) + terminator Jmp(b101) block 237 start_pc=0 - v1290 Imm(12) -> x2 - v1291 Imm(0) -> x0 - terminator Jmp(b239) (exit_acc=v1290) + terminator Jmp(b101) block 238 start_pc=0 - v1292 Imm(11) -> x2 - v1293 Imm(0) -> x0 - terminator Jmp(b239) (exit_acc=v1292) + terminator Jmp(b101) block 239 start_pc=0 - v1294 Phi { incoming=[b237:v1290, b238:v1292], kind=I64 } -> x2 - v1295 LoadLocal { off=-22, kind=I64 } -> x0 - v1296 Store { addr=v1285, disp=0, value=v1294, kind=I64 } -> - - v1297 ImmData(1800) -> x0 - v1298 Load { addr=v1297, disp=0, kind=I64 } -> x1 - v1299 BinopI { op=add, lhs=v1298, rhs_imm=8 } -> x1 - v1300 Store { addr=v1297, disp=0, value=v1299, kind=I64 } -> - - v1301 Imm(13) -> x2 - v1302 Store { addr=v1299, disp=0, value=v1301, kind=I64 } -> - - v1303 Load { addr=v1297, disp=0, kind=I64 } -> x1 - v1304 BinopI { op=add, lhs=v1303, rhs_imm=8 } -> x1 - v1305 Store { addr=v1297, disp=0, value=v1304, kind=I64 } -> - - v1306 Imm(1) -> x2 - v1307 Store { addr=v1304, disp=0, value=v1306, kind=I64 } -> - - v1308 Load { addr=v1297, disp=0, kind=I64 } -> x1 - v1309 BinopI { op=add, lhs=v1308, rhs_imm=8 } -> x1 - v1310 Store { addr=v1297, disp=0, value=v1309, kind=I64 } -> - - v1311 ImmData(1848) -> x0 - v1312 Load { addr=v1311, disp=0, kind=I64 } -> x0 - v1313 BinopI { op=gt, lhs=v1312, rhs_imm=2 } -> x0 - terminator Bz { cond=v1313, target=b241, fall=b240 } (exit_acc=v1313) + terminator Jmp(b203) block 240 start_pc=0 - v1314 Imm(8) -> x2 - v1315 Imm(0) -> x0 - terminator Jmp(b242) (exit_acc=v1314) + terminator Jmp(b101) block 241 start_pc=0 - v1316 Imm(1) -> x2 - v1317 Imm(0) -> x0 - terminator Jmp(b242) (exit_acc=v1316) + terminator Jmp(b101) block 242 start_pc=0 - v1318 Phi { incoming=[b240:v1314, b241:v1316], kind=I64 } -> x2 - v1319 LoadLocal { off=-23, kind=I64 } -> x0 - v1320 Store { addr=v1309, disp=0, value=v1318, kind=I64 } -> - - v1321 ImmData(1800) -> x0 - v1322 Load { addr=v1321, disp=0, kind=I64 } -> x1 - v1323 BinopI { op=add, lhs=v1322, rhs_imm=8 } -> x1 - v1324 Store { addr=v1321, disp=0, value=v1323, kind=I64 } -> - - v1325 ImmData(1832) -> x0 - v1326 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1327 BinopI { op=eq, lhs=v1326, rhs_imm=162 } -> x0 - terminator Bz { cond=v1327, target=b244, fall=b243 } (exit_acc=v1327) + terminator Jmp(b101) block 243 start_pc=0 - v1328 Imm(26) -> x2 - v1329 Imm(0) -> x0 - terminator Jmp(b245) (exit_acc=v1328) + terminator Jmp(b101) block 244 start_pc=0 - v1330 Imm(25) -> x2 - v1331 Imm(0) -> x0 - terminator Jmp(b245) (exit_acc=v1330) + terminator Jmp(b101) block 245 start_pc=0 - v1332 Phi { incoming=[b243:v1328, b244:v1330], kind=I64 } -> x2 - v1333 LoadLocal { off=-24, kind=I64 } -> x0 - v1334 Store { addr=v1323, disp=0, value=v1332, kind=I64 } -> - - v1335 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b223) (exit_acc=v1335) + terminator Jmp(b101) block 246 start_pc=0 - v1336 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1337 ImmData(1800) -> x0 - v1338 Load { addr=v1337, disp=0, kind=I64 } -> x1 - v1339 BinopI { op=add, lhs=v1338, rhs_imm=8 } -> x1 - v1340 Store { addr=v1337, disp=0, value=v1339, kind=I64 } -> - - v1341 Imm(13) -> x0 - v1342 Store { addr=v1339, disp=0, value=v1341, kind=I64 } -> - - v1343 Imm(142) -> x7 - v1344 Call { target_pc=7, args=[v1343], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v1345 ImmData(1832) -> x0 - v1346 Load { addr=v3, disp=0, kind=I64 } -> x0 - v1347 BinopI { op=eq, lhs=v1346, rhs_imm=93 } -> x0 - terminator Bz { cond=v1347, target=b251, fall=b249 } (exit_acc=v1347) + terminator Jmp(b101) block 247 start_pc=0 - terminator Jmp(b223) + terminator Jmp(b101) block 248 start_pc=0 - v1348 ImmData(686) -> x7 - v1349 ImmData(1864) -> x0 - v1350 Load { addr=v1349, disp=0, kind=I64 } -> x6 - v1351 ImmData(1832) -> x0 - v1352 Load { addr=v3, disp=0, kind=I64 } -> x2 - v1353 CallExt { binding_idx=0, args=[v1348, v1350, v1352], fp_arg_mask=0x0 } -> x0 - v1354 Imm(-1) -> x7 - v1355 CallExt { binding_idx=69, args=[v1354], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b247) (exit_acc=v1355) + terminator Jmp(b101) block 249 start_pc=0 - v1356 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b250) (exit_acc=v1356) + terminator Jmp(b101) block 250 start_pc=0 - v1357 LoadLocal { off=-1, kind=I64 } -> x0 - v1358 BinopI { op=gt, lhs=v649, rhs_imm=2 } -> x0 - terminator Bz { cond=v1358, target=b254, fall=b252 } (exit_acc=v1358) + terminator Jmp(b101) block 251 start_pc=0 - v1359 ImmData(631) -> x7 - v1360 ImmData(1864) -> x0 - v1361 Load { addr=v1360, disp=0, kind=I64 } -> x6 - v1362 CallExt { binding_idx=0, args=[v1359, v1361], fp_arg_mask=0x0 } -> x0 - v1363 Imm(-1) -> x7 - v1364 CallExt { binding_idx=69, args=[v1363], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b250) (exit_acc=v1364) + terminator Jmp(b101) block 252 start_pc=0 - v1365 ImmData(1800) -> x0 - v1366 Load { addr=v1365, disp=0, kind=I64 } -> x1 - v1367 BinopI { op=add, lhs=v1366, rhs_imm=8 } -> x1 - v1368 Store { addr=v1365, disp=0, value=v1367, kind=I64 } -> - - v1369 Imm(13) -> x2 - v1370 Store { addr=v1367, disp=0, value=v1369, kind=I64 } -> - - v1371 Load { addr=v1365, disp=0, kind=I64 } -> x1 - v1372 BinopI { op=add, lhs=v1371, rhs_imm=8 } -> x1 - v1373 Store { addr=v1365, disp=0, value=v1372, kind=I64 } -> - - v1374 Imm(1) -> x2 - v1375 Store { addr=v1372, disp=0, value=v1374, kind=I64 } -> - - v1376 Load { addr=v1365, disp=0, kind=I64 } -> x1 - v1377 BinopI { op=add, lhs=v1376, rhs_imm=8 } -> x1 - v1378 Store { addr=v1365, disp=0, value=v1377, kind=I64 } -> - - v1379 Imm(8) -> x2 - v1380 Store { addr=v1377, disp=0, value=v1379, kind=I64 } -> - - v1381 Load { addr=v1365, disp=0, kind=I64 } -> x1 - v1382 BinopI { op=add, lhs=v1381, rhs_imm=8 } -> x1 - v1383 Store { addr=v1365, disp=0, value=v1382, kind=I64 } -> - - v1384 Imm(27) -> x0 - v1385 Store { addr=v1382, disp=0, value=v1384, kind=I64 } -> - - terminator Jmp(b253) (exit_acc=v1385) + terminator Jmp(b101) block 253 start_pc=0 - v1386 ImmData(1800) -> x0 - v1387 Load { addr=v1386, disp=0, kind=I64 } -> x1 - v1388 BinopI { op=add, lhs=v1387, rhs_imm=8 } -> x1 - v1389 Store { addr=v1386, disp=0, value=v1388, kind=I64 } -> - - v1390 Imm(25) -> x2 - v1391 Store { addr=v1388, disp=0, value=v1390, kind=I64 } -> - - v1392 Load { addr=v1386, disp=0, kind=I64 } -> x1 - v1393 BinopI { op=add, lhs=v1392, rhs_imm=8 } -> x14 - v1394 Store { addr=v1386, disp=0, value=v1393, kind=I64 } -> - - v1395 ImmData(1848) -> x0 - v1396 LoadLocal { off=-1, kind=I64 } -> x1 - v1397 BinopI { op=sub, lhs=v649, rhs_imm=2 } -> x1 - v1398 Store { addr=v1395, disp=0, value=v1397, kind=I64 } -> - - v1399 BinopI { op=eq, lhs=v1397, rhs_imm=0 } -> x0 - terminator Bz { cond=v1399, target=b258, fall=b257 } (exit_acc=v1399) + terminator Jmp(b101) block 254 start_pc=0 - v1400 LoadLocal { off=-1, kind=I64 } -> x0 - v1401 BinopI { op=lt, lhs=v649, rhs_imm=2 } -> x0 - terminator Bz { cond=v1401, target=b256, fall=b255 } (exit_acc=v1401) + terminator Jmp(b101) block 255 start_pc=0 - v1402 ImmData(659) -> x7 - v1403 ImmData(1864) -> x0 - v1404 Load { addr=v1403, disp=0, kind=I64 } -> x6 - v1405 CallExt { binding_idx=0, args=[v1402, v1404], fp_arg_mask=0x0 } -> x0 - v1406 Imm(-1) -> x7 - v1407 CallExt { binding_idx=69, args=[v1406], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b256) (exit_acc=v1407) + terminator Jmp(b101) block 256 start_pc=0 - terminator Jmp(b253) + terminator Jmp(b101) block 257 start_pc=0 - v1408 Imm(10) -> x1 - v1409 Imm(0) -> x0 - terminator Jmp(b259) (exit_acc=v1408) + terminator Jmp(b101) block 258 start_pc=0 - v1410 Imm(9) -> x1 - v1411 Imm(0) -> x0 - terminator Jmp(b259) (exit_acc=v1410) + terminator Jmp(b101) block 259 start_pc=0 - v1412 Phi { incoming=[b257:v1408, b258:v1410], kind=I64 } -> x1 - v1413 LoadLocal { off=-25, kind=I64 } -> x0 - v1414 Store { addr=v1393, disp=0, value=v1412, kind=I64 } -> - - terminator Jmp(b247) (exit_acc=v1414) + terminator Jmp(b101) block 260 start_pc=0 - terminator Jmp(b68) + terminator Jmp(b101) block 261 start_pc=0 - terminator Jmp(b97) + terminator Jmp(b101) block 262 start_pc=0 - terminator Jmp(b117) + terminator Jmp(b101) block 263 start_pc=0 - terminator Jmp(b143) + terminator Jmp(b68) block 264 start_pc=0 - terminator Jmp(b204) + terminator Jmp(b101) block 265 start_pc=0 - terminator Jmp(b221) + terminator Jmp(b92) ; --- SSA dump (ok=true) ent_pc=8 --- ; name=stmt fn ent_pc=8 n_params=0 variadic=false locals=4 @@ -3241,43 +3241,27 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v1 ImmData(1832) -> x3 v2 Load { addr=v1, disp=0, kind=I64 } -> x0 v3 BinopI { op=eq, lhs=v2, rhs_imm=137 } -> x0 - terminator Bz { cond=v3, target=b3, fall=b1 } (exit_acc=v3) + terminator Bz { cond=v3, target=b12, fall=b1 } (exit_acc=v3) block 1 start_pc=0 v4 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 v5 ImmData(1832) -> x0 v6 Load { addr=v1, disp=0, kind=I64 } -> x0 v7 BinopI { op=eq, lhs=v6, rhs_imm=40 } -> x0 - terminator Bz { cond=v7, target=b6, fall=b4 } (exit_acc=v7) + terminator Bz { cond=v7, target=b11, fall=b2 } (exit_acc=v7) block 2 start_pc=0 - v8 Imm(0) -> x0 - terminator Return(v8) (exit_acc=v8) - block 3 start_pc=0 - v9 ImmData(1832) -> x0 - v10 Load { addr=v1, disp=0, kind=I64 } -> x0 - v11 BinopI { op=eq, lhs=v10, rhs_imm=141 } -> x0 - terminator Bz { cond=v11, target=b14, fall=b12 } (exit_acc=v11) - block 4 start_pc=0 v12 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b5) (exit_acc=v12) - block 5 start_pc=0 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 v13 Imm(142) -> x7 v14 Call { target_pc=7, args=[v13], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v15 ImmData(1832) -> x0 v16 Load { addr=v1, disp=0, kind=I64 } -> x0 v17 BinopI { op=eq, lhs=v16, rhs_imm=41 } -> x0 - terminator Bz { cond=v17, target=b9, fall=b7 } (exit_acc=v17) - block 6 start_pc=0 - v18 ImmData(712) -> x7 - v19 ImmData(1864) -> x0 - v20 Load { addr=v19, disp=0, kind=I64 } -> x6 - v21 CallExt { binding_idx=0, args=[v18, v20], fp_arg_mask=0x0 } -> x0 - v22 Imm(-1) -> x7 - v23 CallExt { binding_idx=69, args=[v22], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b5) (exit_acc=v23) - block 7 start_pc=0 + terminator Bz { cond=v17, target=b10, fall=b4 } (exit_acc=v17) + block 4 start_pc=0 v24 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b8) (exit_acc=v24) - block 8 start_pc=0 + terminator Jmp(b5) (exit_acc=v24) + block 5 start_pc=0 v25 ImmData(1800) -> x0 v26 Load { addr=v25, disp=0, kind=I64 } -> x1 v27 BinopI { op=add, lhs=v26, rhs_imm=8 } -> x1 @@ -3292,16 +3276,8 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v36 ImmData(1832) -> x0 v37 Load { addr=v1, disp=0, kind=I64 } -> x0 v38 BinopI { op=eq, lhs=v37, rhs_imm=135 } -> x0 - terminator Bz { cond=v38, target=b41, fall=b10 } (exit_acc=v38) - block 9 start_pc=0 - v39 ImmData(737) -> x7 - v40 ImmData(1864) -> x0 - v41 Load { addr=v40, disp=0, kind=I64 } -> x6 - v42 CallExt { binding_idx=0, args=[v39, v41], fp_arg_mask=0x0 } -> x0 - v43 Imm(-1) -> x7 - v44 CallExt { binding_idx=69, args=[v43], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b8) (exit_acc=v44) - block 10 start_pc=0 + terminator Bz { cond=v38, target=b9, fall=b6 } (exit_acc=v38) + block 6 start_pc=0 v45 LoadLocal { off=-2, kind=I64 } -> x0 v46 ImmData(1800) -> x0 v47 Load { addr=v46, disp=0, kind=I64 } -> x1 @@ -3319,17 +3295,43 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v59 Imm(0) -> x0 v60 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 v61 Call { target_pc=8, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b11) (exit_acc=v61) - block 11 start_pc=0 - v62 Phi { incoming=[b41:v32, b10:v57], kind=I64 } -> x12 + terminator Jmp(b7) (exit_acc=v61) + block 7 start_pc=0 + v62 Phi { incoming=[b9:v32, b6:v57], kind=I64 } -> x12 v63 LoadLocal { off=-2, kind=I64 } -> x0 v64 ImmData(1800) -> x0 v65 Load { addr=v64, disp=0, kind=I64 } -> x0 v66 Imm(8) -> x1 v67 BinopI { op=add, lhs=v65, rhs_imm=8 } -> x0 v68 Store { addr=v62, disp=0, value=v67, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v68) + terminator Jmp(b8) (exit_acc=v68) + block 8 start_pc=0 + v8 Imm(0) -> x0 + terminator Return(v8) (exit_acc=v8) + block 9 start_pc=0 + terminator Jmp(b7) + block 10 start_pc=0 + v39 ImmData(737) -> x7 + v40 ImmData(1864) -> x0 + v41 Load { addr=v40, disp=0, kind=I64 } -> x6 + v42 CallExt { binding_idx=0, args=[v39, v41], fp_arg_mask=0x0 } -> x0 + v43 Imm(-1) -> x7 + v44 CallExt { binding_idx=69, args=[v43], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b5) (exit_acc=v44) + block 11 start_pc=0 + v18 ImmData(712) -> x7 + v19 ImmData(1864) -> x0 + v20 Load { addr=v19, disp=0, kind=I64 } -> x6 + v21 CallExt { binding_idx=0, args=[v18, v20], fp_arg_mask=0x0 } -> x0 + v22 Imm(-1) -> x7 + v23 CallExt { binding_idx=69, args=[v22], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b3) (exit_acc=v23) block 12 start_pc=0 + v9 ImmData(1832) -> x0 + v10 Load { addr=v1, disp=0, kind=I64 } -> x0 + v11 BinopI { op=eq, lhs=v10, rhs_imm=141 } -> x0 + terminator Bz { cond=v11, target=b20, fall=b13 } (exit_acc=v11) + block 13 start_pc=0 v69 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 v70 ImmData(1800) -> x0 v71 Load { addr=v70, disp=0, kind=I64 } -> x0 @@ -3339,36 +3341,21 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v75 ImmData(1832) -> x0 v76 Load { addr=v1, disp=0, kind=I64 } -> x0 v77 BinopI { op=eq, lhs=v76, rhs_imm=40 } -> x0 - terminator Bz { cond=v77, target=b17, fall=b15 } (exit_acc=v77) - block 13 start_pc=0 - terminator Jmp(b2) + terminator Bz { cond=v77, target=b19, fall=b14 } (exit_acc=v77) block 14 start_pc=0 - v78 ImmData(1832) -> x0 - v79 Load { addr=v1, disp=0, kind=I64 } -> x0 - v80 BinopI { op=eq, lhs=v79, rhs_imm=139 } -> x0 - terminator Bz { cond=v80, target=b23, fall=b21 } (exit_acc=v80) - block 15 start_pc=0 v81 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b16) (exit_acc=v81) - block 16 start_pc=0 + terminator Jmp(b15) (exit_acc=v81) + block 15 start_pc=0 v82 Imm(142) -> x7 v83 Call { target_pc=7, args=[v82], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v84 ImmData(1832) -> x0 v85 Load { addr=v1, disp=0, kind=I64 } -> x0 v86 BinopI { op=eq, lhs=v85, rhs_imm=41 } -> x0 - terminator Bz { cond=v86, target=b20, fall=b18 } (exit_acc=v86) - block 17 start_pc=0 - v87 ImmData(763) -> x7 - v88 ImmData(1864) -> x0 - v89 Load { addr=v88, disp=0, kind=I64 } -> x6 - v90 CallExt { binding_idx=0, args=[v87, v89], fp_arg_mask=0x0 } -> x0 - v91 Imm(-1) -> x7 - v92 CallExt { binding_idx=69, args=[v91], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b16) (exit_acc=v92) - block 18 start_pc=0 + terminator Bz { cond=v86, target=b18, fall=b16 } (exit_acc=v86) + block 16 start_pc=0 v93 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b19) (exit_acc=v93) - block 19 start_pc=0 + terminator Jmp(b17) (exit_acc=v93) + block 17 start_pc=0 v94 ImmData(1800) -> x3 v95 Load { addr=v94, disp=0, kind=I64 } -> x0 v96 BinopI { op=add, lhs=v95, rhs_imm=8 } -> x0 @@ -3395,33 +3382,39 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v117 Imm(8) -> x1 v118 BinopI { op=add, lhs=v116, rhs_imm=8 } -> x0 v119 Store { addr=v101, disp=0, value=v118, kind=I64 } -> - - terminator Jmp(b13) (exit_acc=v119) - block 20 start_pc=0 + terminator Jmp(b8) (exit_acc=v119) + block 18 start_pc=0 v120 ImmData(788) -> x7 v121 ImmData(1864) -> x0 v122 Load { addr=v121, disp=0, kind=I64 } -> x6 v123 CallExt { binding_idx=0, args=[v120, v122], fp_arg_mask=0x0 } -> x0 v124 Imm(-1) -> x7 v125 CallExt { binding_idx=69, args=[v124], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b19) (exit_acc=v125) + terminator Jmp(b17) (exit_acc=v125) + block 19 start_pc=0 + v87 ImmData(763) -> x7 + v88 ImmData(1864) -> x0 + v89 Load { addr=v88, disp=0, kind=I64 } -> x6 + v90 CallExt { binding_idx=0, args=[v87, v89], fp_arg_mask=0x0 } -> x0 + v91 Imm(-1) -> x7 + v92 CallExt { binding_idx=69, args=[v91], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b15) (exit_acc=v92) + block 20 start_pc=0 + v78 ImmData(1832) -> x0 + v79 Load { addr=v1, disp=0, kind=I64 } -> x0 + v80 BinopI { op=eq, lhs=v79, rhs_imm=139 } -> x0 + terminator Bz { cond=v80, target=b26, fall=b21 } (exit_acc=v80) block 21 start_pc=0 v126 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 v127 ImmData(1832) -> x0 v128 Load { addr=v1, disp=0, kind=I64 } -> x0 v129 BinopI { op=ne, lhs=v128, rhs_imm=59 } -> x0 - terminator Bz { cond=v129, target=b25, fall=b24 } (exit_acc=v129) + terminator Bz { cond=v129, target=b23, fall=b22 } (exit_acc=v129) block 22 start_pc=0 - terminator Jmp(b13) - block 23 start_pc=0 - v130 ImmData(1832) -> x0 - v131 Load { addr=v1, disp=0, kind=I64 } -> x0 - v132 BinopI { op=eq, lhs=v131, rhs_imm=123 } -> x0 - terminator Bz { cond=v132, target=b31, fall=b29 } (exit_acc=v132) - block 24 start_pc=0 v133 Imm(142) -> x7 v134 Call { target_pc=7, args=[v133], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b25) (exit_acc=v134) - block 25 start_pc=0 + terminator Jmp(b23) (exit_acc=v134) + block 23 start_pc=0 v135 ImmData(1800) -> x0 v136 Load { addr=v135, disp=0, kind=I64 } -> x1 v137 BinopI { op=add, lhs=v136, rhs_imm=8 } -> x1 @@ -3431,68 +3424,75 @@ fn ent_pc=8 n_params=0 variadic=false locals=4 v141 ImmData(1832) -> x0 v142 Load { addr=v1, disp=0, kind=I64 } -> x0 v143 BinopI { op=eq, lhs=v142, rhs_imm=59 } -> x0 - terminator Bz { cond=v143, target=b28, fall=b26 } (exit_acc=v143) - block 26 start_pc=0 + terminator Bz { cond=v143, target=b25, fall=b24 } (exit_acc=v143) + block 24 start_pc=0 v144 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b27) (exit_acc=v144) - block 27 start_pc=0 - terminator Jmp(b22) - block 28 start_pc=0 + terminator Jmp(b8) (exit_acc=v144) + block 25 start_pc=0 v145 ImmData(814) -> x7 v146 ImmData(1864) -> x0 v147 Load { addr=v146, disp=0, kind=I64 } -> x6 v148 CallExt { binding_idx=0, args=[v145, v147], fp_arg_mask=0x0 } -> x0 v149 Imm(-1) -> x7 v150 CallExt { binding_idx=69, args=[v149], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b27) (exit_acc=v150) - block 29 start_pc=0 + terminator Jmp(b8) (exit_acc=v150) + block 26 start_pc=0 + v130 ImmData(1832) -> x0 + v131 Load { addr=v1, disp=0, kind=I64 } -> x0 + v132 BinopI { op=eq, lhs=v131, rhs_imm=123 } -> x0 + terminator Bz { cond=v132, target=b31, fall=b27 } (exit_acc=v132) + block 27 start_pc=0 v151 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b32) (exit_acc=v151) + terminator Jmp(b29) (exit_acc=v151) + block 28 start_pc=0 + v158 Call { target_pc=8, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b29) (exit_acc=v158) + block 29 start_pc=0 + v155 ImmData(1832) -> x0 + v156 Load { addr=v1, disp=0, kind=I64 } -> x0 + v157 BinopI { op=ne, lhs=v156, rhs_imm=125 } -> x0 + terminator Bnz { cond=v157, target=b28, fall=b30 } (exit_acc=v157) block 30 start_pc=0 - terminator Jmp(b22) + v159 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b8) (exit_acc=v159) block 31 start_pc=0 v152 ImmData(1832) -> x0 v153 Load { addr=v1, disp=0, kind=I64 } -> x0 v154 BinopI { op=eq, lhs=v153, rhs_imm=59 } -> x0 - terminator Bz { cond=v154, target=b37, fall=b35 } (exit_acc=v154) + terminator Bz { cond=v154, target=b33, fall=b32 } (exit_acc=v154) block 32 start_pc=0 - v155 ImmData(1832) -> x0 - v156 Load { addr=v1, disp=0, kind=I64 } -> x0 - v157 BinopI { op=ne, lhs=v156, rhs_imm=125 } -> x0 - terminator Bz { cond=v157, target=b34, fall=b33 } (exit_acc=v157) - block 33 start_pc=0 - v158 Call { target_pc=8, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b32) (exit_acc=v158) - block 34 start_pc=0 - v159 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b30) (exit_acc=v159) - block 35 start_pc=0 v160 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b36) (exit_acc=v160) - block 36 start_pc=0 - terminator Jmp(b30) - block 37 start_pc=0 + terminator Jmp(b8) (exit_acc=v160) + block 33 start_pc=0 v161 Imm(142) -> x7 v162 Call { target_pc=7, args=[v161], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v163 ImmData(1832) -> x0 v164 Load { addr=v1, disp=0, kind=I64 } -> x0 v165 BinopI { op=eq, lhs=v164, rhs_imm=59 } -> x0 - terminator Bz { cond=v165, target=b40, fall=b38 } (exit_acc=v165) - block 38 start_pc=0 + terminator Bz { cond=v165, target=b35, fall=b34 } (exit_acc=v165) + block 34 start_pc=0 v166 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b39) (exit_acc=v166) - block 39 start_pc=0 - terminator Jmp(b36) - block 40 start_pc=0 + terminator Jmp(b8) (exit_acc=v166) + block 35 start_pc=0 v167 ImmData(838) -> x7 v168 ImmData(1864) -> x0 v169 Load { addr=v168, disp=0, kind=I64 } -> x6 v170 CallExt { binding_idx=0, args=[v167, v169], fp_arg_mask=0x0 } -> x0 v171 Imm(-1) -> x7 v172 CallExt { binding_idx=69, args=[v171], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b39) (exit_acc=v172) + terminator Jmp(b8) (exit_acc=v172) + block 36 start_pc=0 + terminator Jmp(b8) + block 37 start_pc=0 + terminator Jmp(b8) + block 38 start_pc=0 + terminator Jmp(b8) + block 39 start_pc=0 + terminator Jmp(b8) + block 40 start_pc=0 + terminator Jmp(b8) block 41 start_pc=0 - terminator Jmp(b11) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=9 --- ; name=main fn ent_pc=9 n_params=2 variadic=false locals=27 @@ -3504,101 +3504,101 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v3 ParamRef(1, kind=I64) -> x6 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I64 } -> x0 - v6 BinopI { op=add, lhs=v1, rhs_imm=-1 } -> x12 + v6 BinopI { op=add, lhs=v1, rhs_imm=-1 } -> x3 v7 Imm(0) -> x0 v8 LoadLocal { off=3, kind=I64 } -> x0 - v9 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x13 + v9 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x12 v10 Imm(0) -> x0 v11 LoadLocal { off=2, kind=I64 } -> x0 v12 BinopI { op=gt, lhs=v6, rhs_imm=0 } -> x0 - v13 Imm(0) -> x3 + v13 Imm(0) -> x2 v14 Imm(0) -> x1 - terminator Bz { cond=v12, target=b260, fall=b1 } (exit_acc=v12) + terminator Bz { cond=v12, target=b256, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v15 LoadLocal { off=3, kind=I64 } -> x0 v16 Load { addr=v9, disp=0, kind=I64 } -> x0 v17 Load { addr=v16, disp=0, kind=I8 } -> x0 v18 BinopI { op=eq, lhs=v17, rhs_imm=45 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x3 + v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x2 v20 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v21 Phi { incoming=[b260:v13, b1:v19], kind=I64 } -> x3 + v21 Phi { incoming=[b256:v13, b1:v19], kind=I64 } -> x2 v22 LoadLocal { off=-20, kind=I64 } -> x0 v23 Imm(0) -> x0 - terminator Bz { cond=v21, target=b261, fall=b3 } (exit_acc=v21) + terminator Bz { cond=v21, target=b255, fall=b3 } (exit_acc=v21) block 3 start_pc=0 v24 LoadLocal { off=3, kind=I64 } -> x0 v25 Load { addr=v9, disp=0, kind=I64 } -> x0 v26 Imm(1) -> x1 v27 BinopI { op=add, lhs=v25, rhs_imm=1 } -> x1 v28 Load { addr=v25, disp=1, kind=I8 } -> x0 - v29 BinopI { op=eq, lhs=v28, rhs_imm=115 } -> x3 + v29 BinopI { op=eq, lhs=v28, rhs_imm=115 } -> x2 v30 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v29) block 4 start_pc=0 - v31 Phi { incoming=[b261:v21, b3:v29], kind=I64 } -> x3 + v31 Phi { incoming=[b255:v21, b3:v29], kind=I64 } -> x2 v32 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v31, target=b262, fall=b5 } (exit_acc=v31) + terminator Bz { cond=v31, target=b254, fall=b5 } (exit_acc=v31) block 5 start_pc=0 v33 ImmData(1872) -> x0 v34 Imm(1) -> x1 v35 Store { addr=v33, disp=0, value=v34, kind=I64 } -> - v36 LoadLocal { off=2, kind=I64 } -> x0 - v37 BinopI { op=add, lhs=v6, rhs_imm=-1 } -> x12 + v37 BinopI { op=add, lhs=v6, rhs_imm=-1 } -> x3 v38 Imm(0) -> x0 v39 LoadLocal { off=3, kind=I64 } -> x0 - v40 BinopI { op=add, lhs=v9, rhs_imm=8 } -> x13 + v40 BinopI { op=add, lhs=v9, rhs_imm=8 } -> x12 v41 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v40) block 6 start_pc=0 - v42 Phi { incoming=[b262:v6, b5:v37], kind=I64 } -> x12 - v43 Phi { incoming=[b262:v9, b5:v40], kind=I64 } -> x13 + v42 Phi { incoming=[b254:v6, b5:v37], kind=I64 } -> x3 + v43 Phi { incoming=[b254:v9, b5:v40], kind=I64 } -> x12 v44 LoadLocal { off=2, kind=I64 } -> x0 v45 BinopI { op=gt, lhs=v42, rhs_imm=0 } -> x0 - v46 Imm(0) -> x3 + v46 Imm(0) -> x2 v47 Imm(0) -> x1 - terminator Bz { cond=v45, target=b263, fall=b7 } (exit_acc=v45) + terminator Bz { cond=v45, target=b253, fall=b7 } (exit_acc=v45) block 7 start_pc=0 v48 LoadLocal { off=3, kind=I64 } -> x0 v49 Load { addr=v43, disp=0, kind=I64 } -> x0 v50 Load { addr=v49, disp=0, kind=I8 } -> x0 v51 BinopI { op=eq, lhs=v50, rhs_imm=45 } -> x0 - v52 BinopI { op=ne, lhs=v51, rhs_imm=0 } -> x3 + v52 BinopI { op=ne, lhs=v51, rhs_imm=0 } -> x2 v53 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v52) block 8 start_pc=0 - v54 Phi { incoming=[b263:v46, b7:v52], kind=I64 } -> x3 + v54 Phi { incoming=[b253:v46, b7:v52], kind=I64 } -> x2 v55 LoadLocal { off=-22, kind=I64 } -> x0 v56 Imm(0) -> x0 - terminator Bz { cond=v54, target=b264, fall=b9 } (exit_acc=v54) + terminator Bz { cond=v54, target=b252, fall=b9 } (exit_acc=v54) block 9 start_pc=0 v57 LoadLocal { off=3, kind=I64 } -> x0 v58 Load { addr=v43, disp=0, kind=I64 } -> x0 v59 Imm(1) -> x1 v60 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x1 v61 Load { addr=v58, disp=1, kind=I8 } -> x0 - v62 BinopI { op=eq, lhs=v61, rhs_imm=100 } -> x3 + v62 BinopI { op=eq, lhs=v61, rhs_imm=100 } -> x2 v63 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v62) block 10 start_pc=0 - v64 Phi { incoming=[b264:v54, b9:v62], kind=I64 } -> x3 + v64 Phi { incoming=[b252:v54, b9:v62], kind=I64 } -> x2 v65 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v64, target=b265, fall=b11 } (exit_acc=v64) + terminator Bz { cond=v64, target=b251, fall=b11 } (exit_acc=v64) block 11 start_pc=0 v66 ImmData(1880) -> x0 v67 Imm(1) -> x1 v68 Store { addr=v66, disp=0, value=v67, kind=I64 } -> - v69 LoadLocal { off=2, kind=I64 } -> x0 - v70 BinopI { op=add, lhs=v42, rhs_imm=-1 } -> x12 + v70 BinopI { op=add, lhs=v42, rhs_imm=-1 } -> x3 v71 Imm(0) -> x0 v72 LoadLocal { off=3, kind=I64 } -> x0 - v73 BinopI { op=add, lhs=v43, rhs_imm=8 } -> x13 + v73 BinopI { op=add, lhs=v43, rhs_imm=8 } -> x12 v74 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v73) block 12 start_pc=0 - v75 Phi { incoming=[b265:v42, b11:v70], kind=I64 } -> x12 - v76 Phi { incoming=[b265:v43, b11:v73], kind=I64 } -> x13 + v75 Phi { incoming=[b251:v42, b11:v70], kind=I64 } -> x3 + v76 Phi { incoming=[b251:v43, b11:v73], kind=I64 } -> x12 v77 LoadLocal { off=2, kind=I64 } -> x0 v78 BinopI { op=lt, lhs=v75, rhs_imm=1 } -> x0 terminator Bz { cond=v78, target=b14, fall=b13 } (exit_acc=v78) @@ -3611,7 +3611,7 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v82 LoadLocal { off=3, kind=I64 } -> x0 v83 Load { addr=v76, disp=0, kind=I64 } -> x7 v84 Imm(0) -> x6 - v85 CallExt { binding_idx=144, args=[v83, v84], fp_arg_mask=0x0 } -> x3 + v85 CallExt { binding_idx=144, args=[v83, v84], fp_arg_mask=0x0 } -> x13 v86 Imm(0) -> x0 v87 BinopI { op=lt, lhs=v85, rhs_imm=0 } -> x0 terminator Bz { cond=v87, target=b16, fall=b15 } (exit_acc=v87) @@ -3628,8 +3628,8 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v95 Imm(0) -> x0 v96 ImmData(1824) -> x15 v97 LoadLocal { off=-4, kind=I64 } -> x0 - v98 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v99 Extend { value=v93, kind=I32 } -> x7 + v98 Imm(1125899906842624) -> x0 + v99 Imm(262144) -> x7 v100 CallExt { binding_idx=54, args=[v99], fp_arg_mask=0x0 } -> x0 v101 Store { addr=v96, disp=0, value=v100, kind=I64 } -> - v102 BinopI { op=eq, lhs=v100, rhs_imm=0 } -> x0 @@ -3644,8 +3644,8 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v107 ImmData(1808) -> x15 v108 ImmData(1800) -> [spill 0] v109 LoadLocal { off=-4, kind=I64 } -> x0 - v110 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v111 Extend { value=v93, kind=I32 } -> x7 + v110 Imm(1125899906842624) -> x0 + v111 Imm(262144) -> x7 v112 CallExt { binding_idx=54, args=[v111], fp_arg_mask=0x0 } -> x0 v113 Store { addr=v108, disp=0, value=v112, kind=I64 } -> - v114 Store { addr=v107, disp=0, value=v112, kind=I64 } -> - @@ -3660,8 +3660,8 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 block 20 start_pc=0 v120 ImmData(1792) -> x15 v121 LoadLocal { off=-4, kind=I64 } -> x0 - v122 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v123 Extend { value=v93, kind=I32 } -> x7 + v122 Imm(1125899906842624) -> x0 + v123 Imm(262144) -> x7 v124 CallExt { binding_idx=54, args=[v123], fp_arg_mask=0x0 } -> x0 v125 Store { addr=v120, disp=0, value=v124, kind=I64 } -> - v126 BinopI { op=eq, lhs=v124, rhs_imm=0 } -> x0 @@ -3674,8 +3674,8 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 terminator Return(v130) (exit_acc=v130) block 22 start_pc=0 v131 LoadLocal { off=-4, kind=I64 } -> x0 - v132 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v133 Extend { value=v93, kind=I32 } -> x7 + v132 Imm(1125899906842624) -> x0 + v133 Imm(262144) -> x7 v134 CallExt { binding_idx=54, args=[v133], fp_arg_mask=0x0 } -> x15 v135 Imm(0) -> x0 v136 BinopI { op=eq, lhs=v134, rhs_imm=0 } -> x0 @@ -3691,20 +3691,20 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v142 Load { addr=v141, disp=0, kind=I64 } -> x7 v143 Imm(0) -> [spill 0] v144 LoadLocal { off=-4, kind=I64 } -> x0 - v145 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v146 Extend { value=v93, kind=I32 } -> x2 + v145 Imm(1125899906842624) -> x0 + v146 Imm(262144) -> x2 v147 CallExt { binding_idx=95, args=[v142, v143, v146], fp_arg_mask=0x0 } -> x0 v148 ImmData(1800) -> x0 v149 Load { addr=v148, disp=0, kind=I64 } -> x7 v150 LoadLocal { off=-4, kind=I64 } -> x0 - v151 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v152 Extend { value=v93, kind=I32 } -> x2 + v151 Imm(1125899906842624) -> x0 + v152 Imm(262144) -> x2 v153 CallExt { binding_idx=95, args=[v149, v143, v152], fp_arg_mask=0x0 } -> x0 v154 ImmData(1792) -> x0 v155 Load { addr=v154, disp=0, kind=I64 } -> x7 v156 LoadLocal { off=-4, kind=I64 } -> x0 - v157 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v158 Extend { value=v93, kind=I32 } -> x2 + v157 Imm(1125899906842624) -> x0 + v158 Imm(262144) -> x2 v159 CallExt { binding_idx=95, args=[v155, v143, v158], fp_arg_mask=0x0 } -> x0 v160 ImmData(1776) -> x0 v161 ImmData(1043) -> x1 @@ -3713,1554 +3713,1790 @@ fn ent_pc=9 n_params=2 variadic=false locals=27 v164 Imm(0) -> x0 terminator Jmp(b25) (exit_acc=v163) block 25 start_pc=0 - v165 Phi { incoming=[b24:v163, b26:v173], kind=I64 } -> [spill 0] - v166 LoadLocal { off=-11, kind=I64 } -> x0 - v167 BinopI { op=le, lhs=v165, rhs_imm=141 } -> x0 - terminator Bz { cond=v167, target=b27, fall=b26 } (exit_acc=v167) + v165 LoadLocal { off=-11, kind=I64 } -> x0 + v166 Imm(1) -> x0 + v167 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v168 ImmData(1816) -> x0 + v169 Load { addr=v168, disp=0, kind=I64 } -> x0 + v170 Imm(0) -> x1 + v171 LoadLocal { off=-11, kind=I64 } -> x1 + v172 Imm(135) -> [spill 1] + v173 Imm(0) -> x1 + v174 Store { addr=v169, disp=0, value=v163, kind=I64 } -> - + v175 LoadLocal { off=-11, kind=I64 } -> x0 + v176 Imm(1) -> x0 + v177 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v178 ImmData(1816) -> x0 + v179 Load { addr=v178, disp=0, kind=I64 } -> x0 + v180 Imm(0) -> x1 + v181 LoadLocal { off=-11, kind=I64 } -> x1 + v182 Imm(136) -> [spill 0] + v183 Imm(0) -> x1 + v184 Store { addr=v179, disp=0, value=v172, kind=I64 } -> - + v185 LoadLocal { off=-11, kind=I64 } -> x0 + v186 Imm(1) -> x0 + v187 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v188 ImmData(1816) -> x0 + v189 Load { addr=v188, disp=0, kind=I64 } -> x0 + v190 Imm(0) -> x1 + v191 LoadLocal { off=-11, kind=I64 } -> x1 + v192 Imm(137) -> [spill 1] + v193 Imm(0) -> x1 + v194 Store { addr=v189, disp=0, value=v182, kind=I64 } -> - + v195 LoadLocal { off=-11, kind=I64 } -> x0 + v196 Imm(1) -> x0 + v197 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v198 ImmData(1816) -> x0 + v199 Load { addr=v198, disp=0, kind=I64 } -> x0 + v200 Imm(0) -> x1 + v201 LoadLocal { off=-11, kind=I64 } -> x1 + v202 Imm(138) -> [spill 0] + v203 Imm(0) -> x1 + v204 Store { addr=v199, disp=0, value=v192, kind=I64 } -> - + v205 LoadLocal { off=-11, kind=I64 } -> x0 + v206 Imm(1) -> x0 + v207 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v208 ImmData(1816) -> x0 + v209 Load { addr=v208, disp=0, kind=I64 } -> x0 + v210 Imm(0) -> x1 + v211 LoadLocal { off=-11, kind=I64 } -> x1 + v212 Imm(139) -> [spill 1] + v213 Imm(0) -> x1 + v214 Store { addr=v209, disp=0, value=v202, kind=I64 } -> - + v215 LoadLocal { off=-11, kind=I64 } -> x0 + v216 Imm(1) -> x0 + v217 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v218 ImmData(1816) -> x0 + v219 Load { addr=v218, disp=0, kind=I64 } -> x0 + v220 Imm(0) -> x1 + v221 LoadLocal { off=-11, kind=I64 } -> x1 + v222 Imm(140) -> [spill 0] + v223 Imm(0) -> x1 + v224 Store { addr=v219, disp=0, value=v212, kind=I64 } -> - + v225 LoadLocal { off=-11, kind=I64 } -> x0 + v226 Imm(1) -> x0 + v227 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v228 ImmData(1816) -> x0 + v229 Load { addr=v228, disp=0, kind=I64 } -> x0 + v230 Imm(0) -> x1 + v231 LoadLocal { off=-11, kind=I64 } -> x1 + v232 Imm(141) -> [spill 1] + v233 Imm(0) -> x1 + v234 Store { addr=v229, disp=0, value=v222, kind=I64 } -> - + v235 LoadLocal { off=-11, kind=I64 } -> x0 + v236 Imm(1) -> x0 + v237 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v238 ImmData(1816) -> x0 + v239 Load { addr=v238, disp=0, kind=I64 } -> x0 + v240 Imm(0) -> x1 + v241 LoadLocal { off=-11, kind=I64 } -> x1 + v242 Imm(142) -> x1 + v243 Imm(0) -> x1 + v244 Store { addr=v239, disp=0, value=v232, kind=I64 } -> - + v245 LoadLocal { off=-11, kind=I64 } -> x0 + v246 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v246) block 26 start_pc=0 - v168 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v169 ImmData(1816) -> x0 - v170 Load { addr=v169, disp=0, kind=I64 } -> x0 - v171 Imm(0) -> x1 - v172 LoadLocal { off=-11, kind=I64 } -> x1 - v173 BinopI { op=add, lhs=v165, rhs_imm=1 } -> x1 - v174 Imm(0) -> x2 - v175 Store { addr=v170, disp=0, value=v165, kind=I64 } -> - - terminator Jmp(b25) (exit_acc=v175) + v247 Imm(30) -> [spill 0] + v248 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v247) block 27 start_pc=0 - v176 Imm(30) -> [spill 0] - v177 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v176) + v249 LoadLocal { off=-11, kind=I64 } -> x0 + v250 Imm(1) -> x0 + v251 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v252 ImmData(1816) -> x0 + v253 Load { addr=v252, disp=0, kind=I64 } -> x1 + v254 Imm(24) -> x2 + v255 BinopI { op=add, lhs=v253, rhs_imm=24 } -> x2 + v256 Imm(130) -> x2 + v257 Store { addr=v253, disp=24, value=v256, kind=I64 } -> - + v258 Load { addr=v252, disp=0, kind=I64 } -> x1 + v259 Imm(32) -> x2 + v260 BinopI { op=add, lhs=v258, rhs_imm=32 } -> x2 + v261 Imm(1) -> x2 + v262 Store { addr=v258, disp=32, value=v261, kind=I64 } -> - + v263 Load { addr=v252, disp=0, kind=I64 } -> x0 + v264 Imm(40) -> x1 + v265 BinopI { op=add, lhs=v263, rhs_imm=40 } -> x1 + v266 LoadLocal { off=-11, kind=I64 } -> x1 + v267 Imm(31) -> [spill 1] + v268 Imm(0) -> x1 + v269 Store { addr=v263, disp=40, value=v247, kind=I64 } -> - + v270 LoadLocal { off=-11, kind=I64 } -> x0 + v271 Imm(1) -> x0 + v272 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v273 ImmData(1816) -> x0 + v274 Load { addr=v273, disp=0, kind=I64 } -> x1 + v275 Imm(24) -> x2 + v276 BinopI { op=add, lhs=v274, rhs_imm=24 } -> x2 + v277 Imm(130) -> x2 + v278 Store { addr=v274, disp=24, value=v277, kind=I64 } -> - + v279 Load { addr=v273, disp=0, kind=I64 } -> x1 + v280 Imm(32) -> x2 + v281 BinopI { op=add, lhs=v279, rhs_imm=32 } -> x2 + v282 Imm(1) -> x2 + v283 Store { addr=v279, disp=32, value=v282, kind=I64 } -> - + v284 Load { addr=v273, disp=0, kind=I64 } -> x0 + v285 Imm(40) -> x1 + v286 BinopI { op=add, lhs=v284, rhs_imm=40 } -> x1 + v287 LoadLocal { off=-11, kind=I64 } -> x1 + v288 Imm(32) -> [spill 0] + v289 Imm(0) -> x1 + v290 Store { addr=v284, disp=40, value=v267, kind=I64 } -> - + v291 LoadLocal { off=-11, kind=I64 } -> x0 + v292 Imm(1) -> x0 + v293 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v294 ImmData(1816) -> x0 + v295 Load { addr=v294, disp=0, kind=I64 } -> x1 + v296 Imm(24) -> x2 + v297 BinopI { op=add, lhs=v295, rhs_imm=24 } -> x2 + v298 Imm(130) -> x2 + v299 Store { addr=v295, disp=24, value=v298, kind=I64 } -> - + v300 Load { addr=v294, disp=0, kind=I64 } -> x1 + v301 Imm(32) -> x2 + v302 BinopI { op=add, lhs=v300, rhs_imm=32 } -> x2 + v303 Imm(1) -> x2 + v304 Store { addr=v300, disp=32, value=v303, kind=I64 } -> - + v305 Load { addr=v294, disp=0, kind=I64 } -> x0 + v306 Imm(40) -> x1 + v307 BinopI { op=add, lhs=v305, rhs_imm=40 } -> x1 + v308 LoadLocal { off=-11, kind=I64 } -> x1 + v309 Imm(33) -> [spill 1] + v310 Imm(0) -> x1 + v311 Store { addr=v305, disp=40, value=v288, kind=I64 } -> - + v312 LoadLocal { off=-11, kind=I64 } -> x0 + v313 Imm(1) -> x0 + v314 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v315 ImmData(1816) -> x0 + v316 Load { addr=v315, disp=0, kind=I64 } -> x1 + v317 Imm(24) -> x2 + v318 BinopI { op=add, lhs=v316, rhs_imm=24 } -> x2 + v319 Imm(130) -> x2 + v320 Store { addr=v316, disp=24, value=v319, kind=I64 } -> - + v321 Load { addr=v315, disp=0, kind=I64 } -> x1 + v322 Imm(32) -> x2 + v323 BinopI { op=add, lhs=v321, rhs_imm=32 } -> x2 + v324 Imm(1) -> x2 + v325 Store { addr=v321, disp=32, value=v324, kind=I64 } -> - + v326 Load { addr=v315, disp=0, kind=I64 } -> x0 + v327 Imm(40) -> x1 + v328 BinopI { op=add, lhs=v326, rhs_imm=40 } -> x1 + v329 LoadLocal { off=-11, kind=I64 } -> x1 + v330 Imm(34) -> [spill 0] + v331 Imm(0) -> x1 + v332 Store { addr=v326, disp=40, value=v309, kind=I64 } -> - + v333 LoadLocal { off=-11, kind=I64 } -> x0 + v334 Imm(1) -> x0 + v335 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v336 ImmData(1816) -> x0 + v337 Load { addr=v336, disp=0, kind=I64 } -> x1 + v338 Imm(24) -> x2 + v339 BinopI { op=add, lhs=v337, rhs_imm=24 } -> x2 + v340 Imm(130) -> x2 + v341 Store { addr=v337, disp=24, value=v340, kind=I64 } -> - + v342 Load { addr=v336, disp=0, kind=I64 } -> x1 + v343 Imm(32) -> x2 + v344 BinopI { op=add, lhs=v342, rhs_imm=32 } -> x2 + v345 Imm(1) -> x2 + v346 Store { addr=v342, disp=32, value=v345, kind=I64 } -> - + v347 Load { addr=v336, disp=0, kind=I64 } -> x0 + v348 Imm(40) -> x1 + v349 BinopI { op=add, lhs=v347, rhs_imm=40 } -> x1 + v350 LoadLocal { off=-11, kind=I64 } -> x1 + v351 Imm(35) -> [spill 1] + v352 Imm(0) -> x1 + v353 Store { addr=v347, disp=40, value=v330, kind=I64 } -> - + v354 LoadLocal { off=-11, kind=I64 } -> x0 + v355 Imm(1) -> x0 + v356 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v357 ImmData(1816) -> x0 + v358 Load { addr=v357, disp=0, kind=I64 } -> x1 + v359 Imm(24) -> x2 + v360 BinopI { op=add, lhs=v358, rhs_imm=24 } -> x2 + v361 Imm(130) -> x2 + v362 Store { addr=v358, disp=24, value=v361, kind=I64 } -> - + v363 Load { addr=v357, disp=0, kind=I64 } -> x1 + v364 Imm(32) -> x2 + v365 BinopI { op=add, lhs=v363, rhs_imm=32 } -> x2 + v366 Imm(1) -> x2 + v367 Store { addr=v363, disp=32, value=v366, kind=I64 } -> - + v368 Load { addr=v357, disp=0, kind=I64 } -> x0 + v369 Imm(40) -> x1 + v370 BinopI { op=add, lhs=v368, rhs_imm=40 } -> x1 + v371 LoadLocal { off=-11, kind=I64 } -> x1 + v372 Imm(36) -> [spill 0] + v373 Imm(0) -> x1 + v374 Store { addr=v368, disp=40, value=v351, kind=I64 } -> - + v375 LoadLocal { off=-11, kind=I64 } -> x0 + v376 Imm(1) -> x0 + v377 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v378 ImmData(1816) -> x0 + v379 Load { addr=v378, disp=0, kind=I64 } -> x1 + v380 Imm(24) -> x2 + v381 BinopI { op=add, lhs=v379, rhs_imm=24 } -> x2 + v382 Imm(130) -> x2 + v383 Store { addr=v379, disp=24, value=v382, kind=I64 } -> - + v384 Load { addr=v378, disp=0, kind=I64 } -> x1 + v385 Imm(32) -> x2 + v386 BinopI { op=add, lhs=v384, rhs_imm=32 } -> x2 + v387 Imm(1) -> x2 + v388 Store { addr=v384, disp=32, value=v387, kind=I64 } -> - + v389 Load { addr=v378, disp=0, kind=I64 } -> x0 + v390 Imm(40) -> x1 + v391 BinopI { op=add, lhs=v389, rhs_imm=40 } -> x1 + v392 LoadLocal { off=-11, kind=I64 } -> x1 + v393 Imm(37) -> [spill 1] + v394 Imm(0) -> x1 + v395 Store { addr=v389, disp=40, value=v372, kind=I64 } -> - + v396 LoadLocal { off=-11, kind=I64 } -> x0 + v397 Imm(1) -> x0 + v398 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v399 ImmData(1816) -> x0 + v400 Load { addr=v399, disp=0, kind=I64 } -> x1 + v401 Imm(24) -> x2 + v402 BinopI { op=add, lhs=v400, rhs_imm=24 } -> x2 + v403 Imm(130) -> x2 + v404 Store { addr=v400, disp=24, value=v403, kind=I64 } -> - + v405 Load { addr=v399, disp=0, kind=I64 } -> x1 + v406 Imm(32) -> x2 + v407 BinopI { op=add, lhs=v405, rhs_imm=32 } -> x2 + v408 Imm(1) -> x2 + v409 Store { addr=v405, disp=32, value=v408, kind=I64 } -> - + v410 Load { addr=v399, disp=0, kind=I64 } -> x0 + v411 Imm(40) -> x1 + v412 BinopI { op=add, lhs=v410, rhs_imm=40 } -> x1 + v413 LoadLocal { off=-11, kind=I64 } -> x1 + v414 Imm(38) -> [spill 0] + v415 Imm(0) -> x1 + v416 Store { addr=v410, disp=40, value=v393, kind=I64 } -> - + v417 LoadLocal { off=-11, kind=I64 } -> x0 + v418 Imm(1) -> x0 + v419 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v420 ImmData(1816) -> x0 + v421 Load { addr=v420, disp=0, kind=I64 } -> x1 + v422 Imm(24) -> x2 + v423 BinopI { op=add, lhs=v421, rhs_imm=24 } -> x2 + v424 Imm(130) -> x2 + v425 Store { addr=v421, disp=24, value=v424, kind=I64 } -> - + v426 Load { addr=v420, disp=0, kind=I64 } -> x1 + v427 Imm(32) -> x2 + v428 BinopI { op=add, lhs=v426, rhs_imm=32 } -> x2 + v429 Imm(1) -> x2 + v430 Store { addr=v426, disp=32, value=v429, kind=I64 } -> - + v431 Load { addr=v420, disp=0, kind=I64 } -> x0 + v432 Imm(40) -> x1 + v433 BinopI { op=add, lhs=v431, rhs_imm=40 } -> x1 + v434 LoadLocal { off=-11, kind=I64 } -> x1 + v435 Imm(39) -> x1 + v436 Imm(0) -> x1 + v437 Store { addr=v431, disp=40, value=v414, kind=I64 } -> - + v438 LoadLocal { off=-11, kind=I64 } -> x0 + v439 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v439) block 28 start_pc=0 - v178 Phi { incoming=[b27:v176, b29:v197], kind=I64 } -> [spill 0] - v179 LoadLocal { off=-11, kind=I64 } -> x0 - v180 BinopI { op=le, lhs=v178, rhs_imm=38 } -> x0 - terminator Bz { cond=v180, target=b30, fall=b29 } (exit_acc=v180) + v440 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v441 ImmData(1816) -> [spill 0] + v442 Load { addr=v441, disp=0, kind=I64 } -> x0 + v443 Imm(0) -> x1 + v444 Imm(134) -> x1 + v445 Store { addr=v442, disp=0, value=v444, kind=I64 } -> - + v446 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v447 Load { addr=v441, disp=0, kind=I64 } -> [spill 0] + v448 Imm(0) -> x0 + v449 ImmData(1784) -> [spill 1] + v450 ImmData(1776) -> [spill 2] + v451 LoadLocal { off=-4, kind=I64 } -> x0 + v452 Imm(1125899906842624) -> x0 + v453 Imm(262144) -> x7 + v454 CallExt { binding_idx=54, args=[v453], fp_arg_mask=0x0 } -> x0 + v455 Store { addr=v450, disp=0, value=v454, kind=I64 } -> - + v456 Store { addr=v449, disp=0, value=v454, kind=I64 } -> - + v457 BinopI { op=eq, lhs=v454, rhs_imm=0 } -> x0 + terminator Bz { cond=v457, target=b30, fall=b29 } (exit_acc=v457) block 29 start_pc=0 - v181 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v182 ImmData(1816) -> x0 - v183 Load { addr=v182, disp=0, kind=I64 } -> x1 - v184 Imm(24) -> x2 - v185 BinopI { op=add, lhs=v183, rhs_imm=24 } -> x2 - v186 Imm(130) -> x2 - v187 Store { addr=v183, disp=24, value=v186, kind=I64 } -> - - v188 Load { addr=v182, disp=0, kind=I64 } -> x1 - v189 Imm(32) -> x2 - v190 BinopI { op=add, lhs=v188, rhs_imm=32 } -> x2 - v191 Imm(1) -> x2 - v192 Store { addr=v188, disp=32, value=v191, kind=I64 } -> - - v193 Load { addr=v182, disp=0, kind=I64 } -> x0 - v194 Imm(40) -> x1 - v195 BinopI { op=add, lhs=v193, rhs_imm=40 } -> x1 - v196 LoadLocal { off=-11, kind=I64 } -> x1 - v197 BinopI { op=add, lhs=v178, rhs_imm=1 } -> x1 - v198 Imm(0) -> x2 - v199 Store { addr=v193, disp=40, value=v178, kind=I64 } -> - - terminator Jmp(b28) (exit_acc=v199) + v458 ImmData(1149) -> x7 + v459 LoadLocal { off=-4, kind=I64 } -> x0 + v460 CallExt { binding_idx=0, args=[v458, v93], fp_arg_mask=0x0 } -> x0 + v461 Imm(-1) -> x0 + terminator Return(v461) (exit_acc=v461) block 30 start_pc=0 - v200 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v201 ImmData(1816) -> [spill 0] - v202 Load { addr=v201, disp=0, kind=I64 } -> x0 - v203 Imm(0) -> x1 - v204 Imm(134) -> x1 - v205 Store { addr=v202, disp=0, value=v204, kind=I64 } -> - - v206 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v207 Load { addr=v201, disp=0, kind=I64 } -> [spill 0] - v208 Imm(0) -> x0 - v209 ImmData(1784) -> [spill 1] - v210 ImmData(1776) -> [spill 2] - v211 LoadLocal { off=-4, kind=I64 } -> x0 - v212 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x0 - v213 Extend { value=v93, kind=I32 } -> x7 - v214 CallExt { binding_idx=54, args=[v213], fp_arg_mask=0x0 } -> x0 - v215 Store { addr=v210, disp=0, value=v214, kind=I64 } -> - - v216 Store { addr=v209, disp=0, value=v214, kind=I64 } -> - - v217 BinopI { op=eq, lhs=v214, rhs_imm=0 } -> x0 - terminator Bz { cond=v217, target=b32, fall=b31 } (exit_acc=v217) + v462 LoadLocal { off=-1, kind=I64 } -> x0 + v463 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x0 + v464 Extend { value=v85, kind=I32 } -> x7 + v465 ImmData(1776) -> x0 + v466 Load { addr=v465, disp=0, kind=I64 } -> x6 + v467 LoadLocal { off=-4, kind=I64 } -> x0 + v468 Imm(262143) -> x0 + v469 Imm(1125895611875328) -> x0 + v470 Imm(262143) -> x2 + v471 CallExt { binding_idx=145, args=[v464, v466, v470], fp_arg_mask=0x0 } -> x0 + v472 Imm(0) -> x1 + v473 BinopI { op=le, lhs=v471, rhs_imm=0 } -> x1 + terminator Bz { cond=v473, target=b32, fall=b31 } (exit_acc=v473) block 31 start_pc=0 - v218 ImmData(1149) -> x7 - v219 LoadLocal { off=-4, kind=I64 } -> x0 - v220 CallExt { binding_idx=0, args=[v218, v93], fp_arg_mask=0x0 } -> x0 - v221 Imm(-1) -> x0 - terminator Return(v221) (exit_acc=v221) + v474 ImmData(1183) -> x7 + v475 LoadLocal { off=-11, kind=I64 } -> x1 + v476 CallExt { binding_idx=0, args=[v474, v471], fp_arg_mask=0x0 } -> x0 + v477 Imm(-1) -> x0 + terminator Return(v477) (exit_acc=v477) block 32 start_pc=0 - v222 LoadLocal { off=-1, kind=I64 } -> x0 - v223 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x0 - v224 Extend { value=v85, kind=I32 } -> x7 - v225 ImmData(1776) -> x0 - v226 Load { addr=v225, disp=0, kind=I64 } -> x6 - v227 LoadLocal { off=-4, kind=I64 } -> x0 - v228 BinopI { op=sub, lhs=v93, rhs_imm=1 } -> x0 - v229 BinopI { op=shl, lhs=v228, rhs_imm=32 } -> x1 - v230 Extend { value=v228, kind=I32 } -> x2 - v231 CallExt { binding_idx=145, args=[v224, v226, v230], fp_arg_mask=0x0 } -> [spill 1] - v232 Imm(0) -> x0 - v233 BinopI { op=le, lhs=v231, rhs_imm=0 } -> x0 - terminator Bz { cond=v233, target=b34, fall=b33 } (exit_acc=v233) + v478 ImmData(1776) -> x1 + v479 Load { addr=v478, disp=0, kind=I64 } -> x1 + v480 LoadLocal { off=-11, kind=I64 } -> x2 + v481 Binop { op=add, lhs=v479, rhs=v471 } -> x0 + v482 Imm(0) -> x1 + v483 Store { addr=v481, disp=0, value=v482, kind=I8 } -> - + v484 LoadLocal { off=-1, kind=I64 } -> x0 + v485 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x0 + v486 Extend { value=v85, kind=I32 } -> x7 + v487 CallExt { binding_idx=148, args=[v486], fp_arg_mask=0x0 } -> x0 + v488 ImmData(1864) -> x0 + v489 Imm(1) -> x1 + v490 Store { addr=v488, disp=0, value=v489, kind=I64 } -> - + v491 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b115) (exit_acc=v491) block 33 start_pc=0 - v234 ImmData(1183) -> x7 - v235 LoadLocal { off=-11, kind=I64 } -> x0 - v236 CallExt { binding_idx=0, args=[v234, v231], fp_arg_mask=0x0 } -> x0 - v237 Imm(-1) -> x0 - terminator Return(v237) (exit_acc=v237) + v494 Imm(1) -> x13 + v495 Imm(0) -> x0 + v496 ImmData(1832) -> x0 + v497 Load { addr=v496, disp=0, kind=I64 } -> x0 + v498 BinopI { op=eq, lhs=v497, rhs_imm=138 } -> x0 + terminator Bz { cond=v498, target=b95, fall=b34 } (exit_acc=v498) block 34 start_pc=0 - v238 ImmData(1776) -> x0 - v239 Load { addr=v238, disp=0, kind=I64 } -> x0 - v240 LoadLocal { off=-11, kind=I64 } -> x1 - v241 Binop { op=add, lhs=v239, rhs=v231 } -> x0 - v242 Imm(0) -> x1 - v243 Store { addr=v241, disp=0, value=v242, kind=I8 } -> - - v244 LoadLocal { off=-1, kind=I64 } -> x0 - v245 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x0 - v246 Extend { value=v85, kind=I32 } -> x7 - v247 CallExt { binding_idx=148, args=[v246], fp_arg_mask=0x0 } -> x0 - v248 ImmData(1864) -> x0 - v249 Imm(1) -> x1 - v250 Store { addr=v248, disp=0, value=v249, kind=I64 } -> - - v251 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b35) (exit_acc=v251) + v505 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b35) (exit_acc=v505) block 35 start_pc=0 - v252 ImmData(1832) -> x0 - v253 Load { addr=v252, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v253, target=b37, fall=b36 } (exit_acc=v253) + v506 Phi { incoming=[b34:v494, b97:v513], kind=I64 } -> x13 + terminator Jmp(b36) block 36 start_pc=0 - v254 Imm(1) -> x3 - v255 Imm(0) -> x0 - v256 ImmData(1832) -> x0 - v257 Load { addr=v256, disp=0, kind=I64 } -> x0 - v258 BinopI { op=eq, lhs=v257, rhs_imm=138 } -> x0 - terminator Bz { cond=v258, target=b40, fall=b38 } (exit_acc=v258) + v583 Phi { incoming=[b35:v506, b92:v650], kind=I64 } -> x13 + v584 ImmData(1832) -> x0 + v585 Load { addr=v584, disp=0, kind=I64 } -> x0 + v586 BinopI { op=ne, lhs=v585, rhs_imm=59 } -> x1 + v587 Imm(0) -> x0 + terminator Bz { cond=v586, target=b94, fall=b37 } (exit_acc=v586) block 37 start_pc=0 - v259 LoadLocal { off=-5, kind=I64 } -> x0 - v260 Imm(40) -> x0 - v261 BinopI { op=add, lhs=v207, rhs_imm=40 } -> x0 - v262 Load { addr=v207, disp=40, kind=I64 } -> [spill 0] - v263 Imm(0) -> x0 - v264 BinopI { op=eq, lhs=v262, rhs_imm=0 } -> x0 - terminator Bz { cond=v264, target=b126, fall=b125 } (exit_acc=v264) + v591 ImmData(1832) -> x0 + v592 Load { addr=v591, disp=0, kind=I64 } -> x0 + v593 BinopI { op=ne, lhs=v592, rhs_imm=125 } -> x1 + v594 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v593) block 38 start_pc=0 - v265 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b39) (exit_acc=v265) + v595 Phi { incoming=[b94:v586, b37:v593], kind=I64 } -> x1 + v596 LoadLocal { off=-23, kind=I64 } -> x0 + terminator Bz { cond=v595, target=b114, fall=b39 } (exit_acc=v595) block 39 start_pc=0 - v266 Phi { incoming=[b38:v254, b42:v273], kind=I64 } -> x3 - terminator Jmp(b61) + v588 LoadLocal { off=-2, kind=I64 } -> x0 + v589 Imm(0) -> x0 + terminator Jmp(b41) (exit_acc=v583) block 40 start_pc=0 - v267 ImmData(1832) -> x0 - v268 Load { addr=v267, disp=0, kind=I64 } -> x0 - v269 BinopI { op=eq, lhs=v268, rhs_imm=134 } -> x0 - terminator Bz { cond=v269, target=b43, fall=b41 } (exit_acc=v269) + v601 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v602 LoadLocal { off=-3, kind=I64 } -> x0 + v603 BinopI { op=add, lhs=v597, rhs_imm=2 } -> [spill 1] + v604 Imm(0) -> x0 + terminator Jmp(b41) (exit_acc=v603) block 41 start_pc=0 - v270 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v271 Imm(0) -> x3 - v272 Imm(0) -> x0 - terminator Jmp(b42) (exit_acc=v271) + v597 Phi { incoming=[b39:v583, b40:v603], kind=I64 } -> [spill 1] + v598 ImmData(1832) -> x0 + v599 Load { addr=v598, disp=0, kind=I64 } -> x0 + v600 BinopI { op=eq, lhs=v599, rhs_imm=159 } -> x0 + terminator Bnz { cond=v600, target=b40, fall=b42 } (exit_acc=v600) block 42 start_pc=0 - v273 Phi { incoming=[b41:v271, b45:v254], kind=I64 } -> x3 - terminator Jmp(b39) + v605 ImmData(1832) -> x0 + v606 Load { addr=v605, disp=0, kind=I64 } -> x0 + v607 BinopI { op=ne, lhs=v606, rhs_imm=133 } -> x0 + terminator Bnz { cond=v607, target=b250, fall=b43 } (exit_acc=v607) block 43 start_pc=0 - v274 ImmData(1832) -> x0 - v275 Load { addr=v274, disp=0, kind=I64 } -> x0 - v276 BinopI { op=eq, lhs=v275, rhs_imm=136 } -> x0 - terminator Bz { cond=v276, target=b45, fall=b44 } (exit_acc=v276) + v613 ImmData(1816) -> x0 + v614 Load { addr=v613, disp=0, kind=I64 } -> x0 + v615 Imm(24) -> x1 + v616 BinopI { op=add, lhs=v614, rhs_imm=24 } -> x1 + v617 Load { addr=v614, disp=24, kind=I64 } -> x0 + terminator Bnz { cond=v617, target=b249, fall=b44 } (exit_acc=v617) block 44 start_pc=0 - v277 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v278 ImmData(1832) -> x0 - v279 Load { addr=v278, disp=0, kind=I64 } -> x0 - v280 BinopI { op=ne, lhs=v279, rhs_imm=123 } -> x0 - terminator Bz { cond=v280, target=b47, fall=b46 } (exit_acc=v280) + v623 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v624 ImmData(1816) -> x0 + v625 Load { addr=v624, disp=0, kind=I64 } -> x0 + v626 Imm(32) -> x1 + v627 BinopI { op=add, lhs=v625, rhs_imm=32 } -> x1 + v628 LoadLocal { off=-3, kind=I64 } -> x1 + v629 Store { addr=v625, disp=32, value=v597, kind=I64 } -> - + v630 ImmData(1832) -> x0 + v631 Load { addr=v630, disp=0, kind=I64 } -> x0 + v632 BinopI { op=eq, lhs=v631, rhs_imm=40 } -> x0 + terminator Bz { cond=v632, target=b93, fall=b45 } (exit_acc=v632) block 45 start_pc=0 - terminator Jmp(b42) + v633 ImmData(1816) -> x0 + v634 Load { addr=v633, disp=0, kind=I64 } -> x1 + v635 Imm(24) -> x2 + v636 BinopI { op=add, lhs=v634, rhs_imm=24 } -> x2 + v637 Imm(129) -> x2 + v638 Store { addr=v634, disp=24, value=v637, kind=I64 } -> - + v639 Load { addr=v633, disp=0, kind=I64 } -> x0 + v640 Imm(40) -> x1 + v641 BinopI { op=add, lhs=v639, rhs_imm=40 } -> x1 + v642 ImmData(1800) -> x1 + v643 Load { addr=v642, disp=0, kind=I64 } -> x1 + v644 Imm(8) -> x2 + v645 BinopI { op=add, lhs=v643, rhs_imm=8 } -> x1 + v646 Store { addr=v639, disp=40, value=v645, kind=I64 } -> - + v647 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v648 Imm(0) -> [spill 1] + v649 Imm(0) -> x0 + terminator Jmp(b60) (exit_acc=v648) block 46 start_pc=0 - v281 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b47) (exit_acc=v281) + v673 Imm(1) -> [spill 2] + v674 Imm(0) -> x0 + v675 ImmData(1832) -> x0 + v676 Load { addr=v675, disp=0, kind=I64 } -> x0 + v677 BinopI { op=eq, lhs=v676, rhs_imm=138 } -> x0 + terminator Bz { cond=v677, target=b55, fall=b47 } (exit_acc=v677) block 47 start_pc=0 - v282 ImmData(1832) -> x0 - v283 Load { addr=v282, disp=0, kind=I64 } -> x0 - v284 BinopI { op=eq, lhs=v283, rhs_imm=123 } -> x0 - terminator Bz { cond=v284, target=b49, fall=b48 } (exit_acc=v284) + v682 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b48) (exit_acc=v682) block 48 start_pc=0 - v285 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v286 Imm(0) -> [spill 1] - v287 Imm(0) -> x0 - terminator Jmp(b50) (exit_acc=v286) + v683 Phi { incoming=[b47:v673, b57:v690], kind=I64 } -> [spill 2] + terminator Jmp(b50) block 49 start_pc=0 - terminator Jmp(b45) + v695 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v696 LoadLocal { off=-3, kind=I64 } -> x0 + v697 BinopI { op=add, lhs=v691, rhs_imm=2 } -> [spill 2] + v698 Imm(0) -> x0 + terminator Jmp(b50) (exit_acc=v697) block 50 start_pc=0 - v288 Phi { incoming=[b48:v286, b60:v327], kind=I64 } -> [spill 1] - v289 ImmData(1832) -> x0 - v290 Load { addr=v289, disp=0, kind=I64 } -> x0 - v291 BinopI { op=ne, lhs=v290, rhs_imm=125 } -> x0 - terminator Bz { cond=v291, target=b52, fall=b51 } (exit_acc=v291) + v691 Phi { incoming=[b48:v683, b49:v697], kind=I64 } -> [spill 2] + v692 ImmData(1832) -> x0 + v693 Load { addr=v692, disp=0, kind=I64 } -> x0 + v694 BinopI { op=eq, lhs=v693, rhs_imm=159 } -> x0 + terminator Bnz { cond=v694, target=b49, fall=b51 } (exit_acc=v694) block 51 start_pc=0 - v292 ImmData(1832) -> x0 - v293 Load { addr=v292, disp=0, kind=I64 } -> x0 - v294 BinopI { op=ne, lhs=v293, rhs_imm=133 } -> x0 - terminator Bz { cond=v294, target=b54, fall=b53 } (exit_acc=v294) + v699 ImmData(1832) -> x0 + v700 Load { addr=v699, disp=0, kind=I64 } -> x0 + v701 BinopI { op=ne, lhs=v700, rhs_imm=133 } -> x0 + terminator Bnz { cond=v701, target=b248, fall=b52 } (exit_acc=v701) block 52 start_pc=0 - v295 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b49) (exit_acc=v295) + v707 ImmData(1816) -> x0 + v708 Load { addr=v707, disp=0, kind=I64 } -> x0 + v709 Imm(24) -> x1 + v710 BinopI { op=add, lhs=v708, rhs_imm=24 } -> x1 + v711 Load { addr=v708, disp=24, kind=I64 } -> x0 + v712 BinopI { op=eq, lhs=v711, rhs_imm=132 } -> x0 + terminator Bnz { cond=v712, target=b247, fall=b53 } (exit_acc=v712) block 53 start_pc=0 - v296 ImmData(1203) -> x7 - v297 ImmData(1864) -> x0 - v298 Load { addr=v297, disp=0, kind=I64 } -> x6 - v299 ImmData(1832) -> x0 - v300 Load { addr=v299, disp=0, kind=I64 } -> x2 - v301 CallExt { binding_idx=0, args=[v296, v298, v300], fp_arg_mask=0x0 } -> x0 - v302 Imm(-1) -> x0 - terminator Return(v302) (exit_acc=v302) + v718 ImmData(1816) -> x0 + v719 Load { addr=v718, disp=0, kind=I64 } -> x1 + v720 Imm(48) -> x2 + v721 BinopI { op=add, lhs=v719, rhs_imm=48 } -> x2 + v722 Load { addr=v718, disp=0, kind=I64 } -> x2 + v723 Imm(24) -> x2 + v724 BinopI { op=add, lhs=v719, rhs_imm=24 } -> x2 + v725 Load { addr=v719, disp=24, kind=I64 } -> x2 + v726 Store { addr=v719, disp=48, value=v725, kind=I64 } -> - + v727 Load { addr=v718, disp=0, kind=I64 } -> x1 + v728 BinopI { op=add, lhs=v727, rhs_imm=24 } -> x2 + v729 Imm(132) -> x2 + v730 Store { addr=v727, disp=24, value=v729, kind=I64 } -> - + v731 Load { addr=v718, disp=0, kind=I64 } -> x1 + v732 Imm(56) -> x2 + v733 BinopI { op=add, lhs=v731, rhs_imm=56 } -> x2 + v734 Load { addr=v718, disp=0, kind=I64 } -> x2 + v735 Imm(32) -> x2 + v736 BinopI { op=add, lhs=v731, rhs_imm=32 } -> x2 + v737 Load { addr=v731, disp=32, kind=I64 } -> x2 + v738 Store { addr=v731, disp=56, value=v737, kind=I64 } -> - + v739 Load { addr=v718, disp=0, kind=I64 } -> x1 + v740 BinopI { op=add, lhs=v739, rhs_imm=32 } -> x2 + v741 LoadLocal { off=-3, kind=I64 } -> x2 + v742 Store { addr=v739, disp=32, value=v691, kind=I64 } -> - + v743 Load { addr=v718, disp=0, kind=I64 } -> x1 + v744 Imm(64) -> x2 + v745 BinopI { op=add, lhs=v743, rhs_imm=64 } -> x2 + v746 Load { addr=v718, disp=0, kind=I64 } -> x2 + v747 Imm(40) -> x2 + v748 BinopI { op=add, lhs=v743, rhs_imm=40 } -> x2 + v749 Load { addr=v743, disp=40, kind=I64 } -> x2 + v750 Store { addr=v743, disp=64, value=v749, kind=I64 } -> - + v751 Load { addr=v718, disp=0, kind=I64 } -> x0 + v752 BinopI { op=add, lhs=v751, rhs_imm=40 } -> x1 + v753 LoadLocal { off=-11, kind=I64 } -> x1 + v754 BinopI { op=add, lhs=v669, rhs_imm=1 } -> [spill 2] + v755 Imm(0) -> x1 + v756 Store { addr=v751, disp=40, value=v669, kind=I64 } -> - + v757 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v758 ImmData(1832) -> x0 + v759 Load { addr=v758, disp=0, kind=I64 } -> x0 + v760 BinopI { op=eq, lhs=v759, rhs_imm=44 } -> x0 + terminator Bz { cond=v760, target=b59, fall=b54 } (exit_acc=v760) block 54 start_pc=0 - v303 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v304 ImmData(1832) -> x0 - v305 Load { addr=v304, disp=0, kind=I64 } -> x0 - v306 BinopI { op=eq, lhs=v305, rhs_imm=142 } -> x0 - terminator Bz { cond=v306, target=b266, fall=b55 } (exit_acc=v306) + v761 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b59) (exit_acc=v761) block 55 start_pc=0 - v307 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v308 ImmData(1832) -> x0 - v309 Load { addr=v308, disp=0, kind=I64 } -> x0 - v310 BinopI { op=ne, lhs=v309, rhs_imm=128 } -> x0 - terminator Bz { cond=v310, target=b58, fall=b57 } (exit_acc=v310) + v684 ImmData(1832) -> x0 + v685 Load { addr=v684, disp=0, kind=I64 } -> x0 + v686 BinopI { op=eq, lhs=v685, rhs_imm=134 } -> x0 + terminator Bz { cond=v686, target=b58, fall=b56 } (exit_acc=v686) block 56 start_pc=0 - v311 Phi { incoming=[b266:v288, b58:v339], kind=I64 } -> [spill 2] - v312 ImmData(1816) -> x0 - v313 Load { addr=v312, disp=0, kind=I64 } -> x1 - v314 Imm(24) -> x2 - v315 BinopI { op=add, lhs=v313, rhs_imm=24 } -> x2 - v316 Imm(128) -> x2 - v317 Store { addr=v313, disp=24, value=v316, kind=I64 } -> - - v318 Load { addr=v312, disp=0, kind=I64 } -> x1 - v319 Imm(32) -> x2 - v320 BinopI { op=add, lhs=v318, rhs_imm=32 } -> x2 - v321 Imm(1) -> x2 - v322 Store { addr=v318, disp=32, value=v321, kind=I64 } -> - - v323 Load { addr=v312, disp=0, kind=I64 } -> x0 - v324 Imm(40) -> x1 - v325 BinopI { op=add, lhs=v323, rhs_imm=40 } -> x1 - v326 LoadLocal { off=-11, kind=I64 } -> x1 - v327 BinopI { op=add, lhs=v311, rhs_imm=1 } -> [spill 1] - v328 Imm(0) -> x1 - v329 Store { addr=v323, disp=40, value=v311, kind=I64 } -> - - v330 ImmData(1832) -> x0 - v331 Load { addr=v330, disp=0, kind=I64 } -> x0 - v332 BinopI { op=eq, lhs=v331, rhs_imm=44 } -> x0 - terminator Bz { cond=v332, target=b60, fall=b59 } (exit_acc=v332) + v687 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v688 Imm(0) -> [spill 2] + v689 Imm(0) -> x0 + terminator Jmp(b57) (exit_acc=v688) block 57 start_pc=0 - v333 ImmData(1231) -> x7 - v334 ImmData(1864) -> x0 - v335 Load { addr=v334, disp=0, kind=I64 } -> x6 - v336 CallExt { binding_idx=0, args=[v333, v335], fp_arg_mask=0x0 } -> x0 - v337 Imm(-1) -> x0 - terminator Return(v337) (exit_acc=v337) + v690 Phi { incoming=[b58:v673, b56:v688], kind=I64 } -> [spill 2] + terminator Jmp(b48) block 58 start_pc=0 - v338 ImmData(1840) -> x0 - v339 Load { addr=v338, disp=0, kind=I64 } -> [spill 2] - v340 Imm(0) -> x0 - v341 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b56) (exit_acc=v341) + terminator Jmp(b57) block 59 start_pc=0 - v342 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b60) (exit_acc=v342) + terminator Jmp(b60) block 60 start_pc=0 - terminator Jmp(b50) + v669 Phi { incoming=[b45:v648, b59:v754], kind=I64 } -> [spill 1] + v670 ImmData(1832) -> x0 + v671 Load { addr=v670, disp=0, kind=I64 } -> x0 + v672 BinopI { op=ne, lhs=v671, rhs_imm=41 } -> x0 + terminator Bnz { cond=v672, target=b46, fall=b61 } (exit_acc=v672) block 61 start_pc=0 - v343 Phi { incoming=[b39:v266, b124:v410], kind=I64 } -> x3 - v344 ImmData(1832) -> x0 - v345 Load { addr=v344, disp=0, kind=I64 } -> x0 - v346 BinopI { op=ne, lhs=v345, rhs_imm=59 } -> [spill 1] - v347 Imm(0) -> x0 - terminator Bz { cond=v346, target=b267, fall=b64 } (exit_acc=v346) + v678 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v679 ImmData(1832) -> x0 + v680 Load { addr=v679, disp=0, kind=I64 } -> x0 + v681 BinopI { op=ne, lhs=v680, rhs_imm=123 } -> x0 + terminator Bnz { cond=v681, target=b246, fall=b62 } (exit_acc=v681) block 62 start_pc=0 - v348 LoadLocal { off=-2, kind=I64 } -> x0 - v349 Imm(0) -> x0 - terminator Jmp(b66) (exit_acc=v343) + v767 ImmData(1856) -> x0 + v768 LoadLocal { off=-11, kind=I64 } -> x1 + v769 BinopI { op=add, lhs=v669, rhs_imm=1 } -> [spill 1] + v770 Imm(0) -> x1 + v771 Store { addr=v767, disp=0, value=v769, kind=I64 } -> - + v772 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b63) (exit_acc=v772) block 63 start_pc=0 - v350 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b35) (exit_acc=v350) + v773 Phi { incoming=[b62:v769, b78:v810], kind=I64 } -> [spill 1] + v774 Phi { incoming=[b62:v583, b78:v806], kind=I64 } -> x13 + v775 ImmData(1832) -> x0 + v776 Load { addr=v775, disp=0, kind=I64 } -> x0 + v777 BinopI { op=eq, lhs=v776, rhs_imm=138 } -> x1 + v778 Imm(0) -> x0 + terminator Bnz { cond=v777, target=b80, fall=b64 } (exit_acc=v777) block 64 start_pc=0 - v351 ImmData(1832) -> x0 - v352 Load { addr=v351, disp=0, kind=I64 } -> x0 - v353 BinopI { op=ne, lhs=v352, rhs_imm=125 } -> [spill 1] - v354 Imm(0) -> x0 - terminator Jmp(b65) (exit_acc=v353) + v796 ImmData(1832) -> x0 + v797 Load { addr=v796, disp=0, kind=I64 } -> x0 + v798 BinopI { op=eq, lhs=v797, rhs_imm=134 } -> x1 + v799 Imm(0) -> x0 + terminator Jmp(b65) (exit_acc=v798) block 65 start_pc=0 - v355 Phi { incoming=[b267:v346, b64:v353], kind=I64 } -> [spill 1] - v356 LoadLocal { off=-23, kind=I64 } -> x0 - terminator Bz { cond=v355, target=b63, fall=b62 } (exit_acc=v355) + v800 Phi { incoming=[b80:v777, b64:v798], kind=I64 } -> x1 + v801 LoadLocal { off=-24, kind=I64 } -> x0 + terminator Bz { cond=v800, target=b81, fall=b66 } (exit_acc=v800) block 66 start_pc=0 - v357 Phi { incoming=[b62:v343, b67:v363], kind=I64 } -> [spill 1] - v358 ImmData(1832) -> x0 - v359 Load { addr=v358, disp=0, kind=I64 } -> x0 - v360 BinopI { op=eq, lhs=v359, rhs_imm=159 } -> x0 - terminator Bz { cond=v360, target=b68, fall=b67 } (exit_acc=v360) + v779 ImmData(1832) -> x0 + v780 Load { addr=v779, disp=0, kind=I64 } -> x0 + v781 BinopI { op=eq, lhs=v780, rhs_imm=138 } -> x0 + terminator Bz { cond=v781, target=b79, fall=b67 } (exit_acc=v781) block 67 start_pc=0 - v361 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v362 LoadLocal { off=-3, kind=I64 } -> x0 - v363 BinopI { op=add, lhs=v357, rhs_imm=2 } -> [spill 1] - v364 Imm(0) -> x0 - terminator Jmp(b66) (exit_acc=v363) + v802 Imm(1) -> x13 + v803 Imm(0) -> x0 + terminator Jmp(b68) (exit_acc=v802) block 68 start_pc=0 - v365 ImmData(1832) -> x0 - v366 Load { addr=v365, disp=0, kind=I64 } -> x0 - v367 BinopI { op=ne, lhs=v366, rhs_imm=133 } -> x0 - terminator Bz { cond=v367, target=b70, fall=b69 } (exit_acc=v367) + v806 Phi { incoming=[b67:v802, b79:v804], kind=I64 } -> x13 + v807 LoadLocal { off=-25, kind=I64 } -> x0 + v808 Imm(0) -> x0 + v809 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b77) (exit_acc=v809) block 69 start_pc=0 - v368 ImmData(1257) -> x7 - v369 ImmData(1864) -> x0 - v370 Load { addr=v369, disp=0, kind=I64 } -> x6 - v371 CallExt { binding_idx=0, args=[v368, v370], fp_arg_mask=0x0 } -> x0 - v372 Imm(-1) -> x0 - terminator Return(v372) (exit_acc=v372) + v814 LoadLocal { off=-2, kind=I64 } -> x0 + v815 Imm(0) -> x0 + terminator Jmp(b71) (exit_acc=v806) block 70 start_pc=0 - v373 ImmData(1816) -> x0 - v374 Load { addr=v373, disp=0, kind=I64 } -> x0 - v375 Imm(24) -> x1 - v376 BinopI { op=add, lhs=v374, rhs_imm=24 } -> x1 - v377 Load { addr=v374, disp=24, kind=I64 } -> x0 - terminator Bz { cond=v377, target=b72, fall=b71 } (exit_acc=v377) + v821 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v822 LoadLocal { off=-3, kind=I64 } -> x0 + v823 BinopI { op=add, lhs=v817, rhs_imm=2 } -> [spill 2] + v824 Imm(0) -> x0 + terminator Jmp(b71) (exit_acc=v823) block 71 start_pc=0 - v378 ImmData(1285) -> x7 - v379 ImmData(1864) -> x0 - v380 Load { addr=v379, disp=0, kind=I64 } -> x6 - v381 CallExt { binding_idx=0, args=[v378, v380], fp_arg_mask=0x0 } -> x0 - v382 Imm(-1) -> x0 - terminator Return(v382) (exit_acc=v382) + v817 Phi { incoming=[b69:v806, b70:v823], kind=I64 } -> [spill 2] + v818 ImmData(1832) -> x0 + v819 Load { addr=v818, disp=0, kind=I64 } -> x0 + v820 BinopI { op=eq, lhs=v819, rhs_imm=159 } -> x0 + terminator Bnz { cond=v820, target=b70, fall=b72 } (exit_acc=v820) block 72 start_pc=0 - v383 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v384 ImmData(1816) -> x0 - v385 Load { addr=v384, disp=0, kind=I64 } -> x0 - v386 Imm(32) -> x1 - v387 BinopI { op=add, lhs=v385, rhs_imm=32 } -> x1 - v388 LoadLocal { off=-3, kind=I64 } -> x1 - v389 Store { addr=v385, disp=32, value=v357, kind=I64 } -> - - v390 ImmData(1832) -> x0 - v391 Load { addr=v390, disp=0, kind=I64 } -> x0 - v392 BinopI { op=eq, lhs=v391, rhs_imm=40 } -> x0 - terminator Bz { cond=v392, target=b75, fall=b73 } (exit_acc=v392) + v825 ImmData(1832) -> x0 + v826 Load { addr=v825, disp=0, kind=I64 } -> x0 + v827 BinopI { op=ne, lhs=v826, rhs_imm=133 } -> x0 + terminator Bnz { cond=v827, target=b245, fall=b73 } (exit_acc=v827) block 73 start_pc=0 - v393 ImmData(1816) -> x0 - v394 Load { addr=v393, disp=0, kind=I64 } -> x1 - v395 Imm(24) -> x2 - v396 BinopI { op=add, lhs=v394, rhs_imm=24 } -> x2 - v397 Imm(129) -> x2 - v398 Store { addr=v394, disp=24, value=v397, kind=I64 } -> - - v399 Load { addr=v393, disp=0, kind=I64 } -> x0 - v400 Imm(40) -> x1 - v401 BinopI { op=add, lhs=v399, rhs_imm=40 } -> x1 - v402 ImmData(1800) -> x1 - v403 Load { addr=v402, disp=0, kind=I64 } -> x1 - v404 Imm(8) -> x2 - v405 BinopI { op=add, lhs=v403, rhs_imm=8 } -> x1 - v406 Store { addr=v399, disp=40, value=v405, kind=I64 } -> - - v407 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v408 Imm(0) -> [spill 1] - v409 Imm(0) -> x0 - terminator Jmp(b76) (exit_acc=v408) + v833 ImmData(1816) -> x0 + v834 Load { addr=v833, disp=0, kind=I64 } -> x0 + v835 Imm(24) -> x1 + v836 BinopI { op=add, lhs=v834, rhs_imm=24 } -> x1 + v837 Load { addr=v834, disp=24, kind=I64 } -> x0 + v838 BinopI { op=eq, lhs=v837, rhs_imm=132 } -> x0 + terminator Bnz { cond=v838, target=b244, fall=b74 } (exit_acc=v838) block 74 start_pc=0 - v410 Phi { incoming=[b120:v534, b75:v343], kind=I64 } -> x3 - v411 ImmData(1832) -> x0 - v412 Load { addr=v411, disp=0, kind=I64 } -> x0 - v413 BinopI { op=eq, lhs=v412, rhs_imm=44 } -> x0 - terminator Bz { cond=v413, target=b124, fall=b123 } (exit_acc=v413) + v844 ImmData(1816) -> x0 + v845 Load { addr=v844, disp=0, kind=I64 } -> x1 + v846 Imm(48) -> x2 + v847 BinopI { op=add, lhs=v845, rhs_imm=48 } -> x2 + v848 Load { addr=v844, disp=0, kind=I64 } -> x2 + v849 Imm(24) -> x2 + v850 BinopI { op=add, lhs=v845, rhs_imm=24 } -> x2 + v851 Load { addr=v845, disp=24, kind=I64 } -> x2 + v852 Store { addr=v845, disp=48, value=v851, kind=I64 } -> - + v853 Load { addr=v844, disp=0, kind=I64 } -> x1 + v854 BinopI { op=add, lhs=v853, rhs_imm=24 } -> x2 + v855 Imm(132) -> x2 + v856 Store { addr=v853, disp=24, value=v855, kind=I64 } -> - + v857 Load { addr=v844, disp=0, kind=I64 } -> x1 + v858 Imm(56) -> x2 + v859 BinopI { op=add, lhs=v857, rhs_imm=56 } -> x2 + v860 Load { addr=v844, disp=0, kind=I64 } -> x2 + v861 Imm(32) -> x2 + v862 BinopI { op=add, lhs=v857, rhs_imm=32 } -> x2 + v863 Load { addr=v857, disp=32, kind=I64 } -> x2 + v864 Store { addr=v857, disp=56, value=v863, kind=I64 } -> - + v865 Load { addr=v844, disp=0, kind=I64 } -> x1 + v866 BinopI { op=add, lhs=v865, rhs_imm=32 } -> x2 + v867 LoadLocal { off=-3, kind=I64 } -> x2 + v868 Store { addr=v865, disp=32, value=v817, kind=I64 } -> - + v869 Load { addr=v844, disp=0, kind=I64 } -> x1 + v870 Imm(64) -> x2 + v871 BinopI { op=add, lhs=v869, rhs_imm=64 } -> x2 + v872 Load { addr=v844, disp=0, kind=I64 } -> x2 + v873 Imm(40) -> x2 + v874 BinopI { op=add, lhs=v869, rhs_imm=40 } -> x2 + v875 Load { addr=v869, disp=40, kind=I64 } -> x2 + v876 Store { addr=v869, disp=64, value=v875, kind=I64 } -> - + v877 Load { addr=v844, disp=0, kind=I64 } -> x0 + v878 BinopI { op=add, lhs=v877, rhs_imm=40 } -> x1 + v879 LoadLocal { off=-11, kind=I64 } -> x1 + v880 BinopI { op=add, lhs=v810, rhs_imm=1 } -> [spill 1] + v881 Imm(0) -> x1 + v882 Store { addr=v877, disp=40, value=v880, kind=I64 } -> - + v883 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v884 ImmData(1832) -> x0 + v885 Load { addr=v884, disp=0, kind=I64 } -> x0 + v886 BinopI { op=eq, lhs=v885, rhs_imm=44 } -> x0 + terminator Bz { cond=v886, target=b76, fall=b75 } (exit_acc=v886) block 75 start_pc=0 - v414 ImmData(1816) -> x0 - v415 Load { addr=v414, disp=0, kind=I64 } -> x1 - v416 Imm(24) -> x2 - v417 BinopI { op=add, lhs=v415, rhs_imm=24 } -> x2 - v418 Imm(131) -> x2 - v419 Store { addr=v415, disp=24, value=v418, kind=I64 } -> - - v420 Load { addr=v414, disp=0, kind=I64 } -> x0 - v421 Imm(40) -> x1 - v422 BinopI { op=add, lhs=v420, rhs_imm=40 } -> x1 - v423 ImmData(1792) -> x1 - v424 Load { addr=v423, disp=0, kind=I64 } -> x2 - v425 Store { addr=v420, disp=40, value=v424, kind=I64 } -> - - v426 Load { addr=v423, disp=0, kind=I64 } -> x0 - v427 BinopI { op=add, lhs=v426, rhs_imm=8 } -> x0 - v428 Store { addr=v423, disp=0, value=v427, kind=I64 } -> - - terminator Jmp(b74) (exit_acc=v428) + v887 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b76) (exit_acc=v887) block 76 start_pc=0 - v429 Phi { incoming=[b73:v408, b92:v514], kind=I64 } -> [spill 1] - v430 ImmData(1832) -> x0 - v431 Load { addr=v430, disp=0, kind=I64 } -> x0 - v432 BinopI { op=ne, lhs=v431, rhs_imm=41 } -> x0 - terminator Bz { cond=v432, target=b78, fall=b77 } (exit_acc=v432) + terminator Jmp(b77) block 77 start_pc=0 - v433 Imm(1) -> [spill 2] - v434 Imm(0) -> x0 - v435 ImmData(1832) -> x0 - v436 Load { addr=v435, disp=0, kind=I64 } -> x0 - v437 BinopI { op=eq, lhs=v436, rhs_imm=138 } -> x0 - terminator Bz { cond=v437, target=b81, fall=b79 } (exit_acc=v437) + v810 Phi { incoming=[b68:v773, b76:v880], kind=I64 } -> [spill 1] + v811 ImmData(1832) -> x0 + v812 Load { addr=v811, disp=0, kind=I64 } -> x0 + v813 BinopI { op=ne, lhs=v812, rhs_imm=59 } -> x0 + terminator Bnz { cond=v813, target=b69, fall=b78 } (exit_acc=v813) block 78 start_pc=0 - v438 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v439 ImmData(1832) -> x0 - v440 Load { addr=v439, disp=0, kind=I64 } -> x0 - v441 BinopI { op=ne, lhs=v440, rhs_imm=123 } -> x0 - terminator Bz { cond=v441, target=b94, fall=b93 } (exit_acc=v441) + v816 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b63) (exit_acc=v816) block 79 start_pc=0 - v442 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b80) (exit_acc=v442) + v804 Imm(0) -> x13 + v805 Imm(0) -> x0 + terminator Jmp(b68) (exit_acc=v804) block 80 start_pc=0 - v443 Phi { incoming=[b79:v433, b83:v450], kind=I64 } -> [spill 2] - terminator Jmp(b84) + terminator Jmp(b65) block 81 start_pc=0 - v444 ImmData(1832) -> x0 - v445 Load { addr=v444, disp=0, kind=I64 } -> x0 - v446 BinopI { op=eq, lhs=v445, rhs_imm=134 } -> x0 - terminator Bz { cond=v446, target=b268, fall=b82 } (exit_acc=v446) + v782 ImmData(1800) -> x0 + v783 Load { addr=v782, disp=0, kind=I64 } -> x1 + v784 BinopI { op=add, lhs=v783, rhs_imm=8 } -> x1 + v785 Store { addr=v782, disp=0, value=v784, kind=I64 } -> - + v786 Imm(6) -> x2 + v787 Store { addr=v784, disp=0, value=v786, kind=I64 } -> - + v788 Load { addr=v782, disp=0, kind=I64 } -> x1 + v789 BinopI { op=add, lhs=v788, rhs_imm=8 } -> x1 + v790 Store { addr=v782, disp=0, value=v789, kind=I64 } -> - + v791 LoadLocal { off=-11, kind=I64 } -> x0 + v792 ImmData(1856) -> x0 + v793 Load { addr=v792, disp=0, kind=I64 } -> x0 + v794 Binop { op=sub, lhs=v773, rhs=v793 } -> x0 + v795 Store { addr=v789, disp=0, value=v794, kind=I64 } -> - + terminator Jmp(b83) (exit_acc=v795) block 82 start_pc=0 - v447 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v448 Imm(0) -> [spill 2] - v449 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v448) + v891 Call { target_pc=8, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b83) (exit_acc=v891) block 83 start_pc=0 - v450 Phi { incoming=[b268:v433, b82:v448], kind=I64 } -> [spill 2] - terminator Jmp(b80) + v888 ImmData(1832) -> x0 + v889 Load { addr=v888, disp=0, kind=I64 } -> x0 + v890 BinopI { op=ne, lhs=v889, rhs_imm=125 } -> x0 + terminator Bnz { cond=v890, target=b82, fall=b84 } (exit_acc=v890) block 84 start_pc=0 - v451 Phi { incoming=[b80:v443, b85:v457], kind=I64 } -> [spill 2] - v452 ImmData(1832) -> x0 - v453 Load { addr=v452, disp=0, kind=I64 } -> x0 - v454 BinopI { op=eq, lhs=v453, rhs_imm=159 } -> x0 - terminator Bz { cond=v454, target=b86, fall=b85 } (exit_acc=v454) + v892 ImmData(1800) -> x0 + v893 Load { addr=v892, disp=0, kind=I64 } -> x1 + v894 BinopI { op=add, lhs=v893, rhs_imm=8 } -> x1 + v895 Store { addr=v892, disp=0, value=v894, kind=I64 } -> - + v896 Imm(8) -> x0 + v897 Store { addr=v894, disp=0, value=v896, kind=I64 } -> - + v898 ImmData(1816) -> x0 + v899 ImmData(1824) -> x1 + v900 Load { addr=v899, disp=0, kind=I64 } -> x1 + v901 Store { addr=v898, disp=0, value=v900, kind=I64 } -> - + terminator Jmp(b88) (exit_acc=v901) block 85 start_pc=0 - v455 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v456 LoadLocal { off=-3, kind=I64 } -> x0 - v457 BinopI { op=add, lhs=v451, rhs_imm=2 } -> [spill 2] - v458 Imm(0) -> x0 - terminator Jmp(b84) (exit_acc=v457) + v906 ImmData(1816) -> x0 + v907 Load { addr=v906, disp=0, kind=I64 } -> x0 + v908 Imm(24) -> x1 + v909 BinopI { op=add, lhs=v907, rhs_imm=24 } -> x1 + v910 Load { addr=v907, disp=24, kind=I64 } -> x0 + v911 BinopI { op=eq, lhs=v910, rhs_imm=132 } -> x0 + terminator Bz { cond=v911, target=b87, fall=b86 } (exit_acc=v911) block 86 start_pc=0 - v459 ImmData(1832) -> x0 - v460 Load { addr=v459, disp=0, kind=I64 } -> x0 - v461 BinopI { op=ne, lhs=v460, rhs_imm=133 } -> x0 - terminator Bz { cond=v461, target=b88, fall=b87 } (exit_acc=v461) + v912 ImmData(1816) -> x0 + v913 Load { addr=v912, disp=0, kind=I64 } -> x1 + v914 Imm(24) -> x2 + v915 BinopI { op=add, lhs=v913, rhs_imm=24 } -> x2 + v916 Load { addr=v912, disp=0, kind=I64 } -> x2 + v917 Imm(48) -> x2 + v918 BinopI { op=add, lhs=v913, rhs_imm=48 } -> x2 + v919 Load { addr=v913, disp=48, kind=I64 } -> x2 + v920 Store { addr=v913, disp=24, value=v919, kind=I64 } -> - + v921 Load { addr=v912, disp=0, kind=I64 } -> x1 + v922 Imm(32) -> x2 + v923 BinopI { op=add, lhs=v921, rhs_imm=32 } -> x2 + v924 Load { addr=v912, disp=0, kind=I64 } -> x2 + v925 Imm(56) -> x2 + v926 BinopI { op=add, lhs=v921, rhs_imm=56 } -> x2 + v927 Load { addr=v921, disp=56, kind=I64 } -> x2 + v928 Store { addr=v921, disp=32, value=v927, kind=I64 } -> - + v929 Load { addr=v912, disp=0, kind=I64 } -> x1 + v930 Imm(40) -> x2 + v931 BinopI { op=add, lhs=v929, rhs_imm=40 } -> x2 + v932 Load { addr=v912, disp=0, kind=I64 } -> x0 + v933 Imm(64) -> x0 + v934 BinopI { op=add, lhs=v929, rhs_imm=64 } -> x0 + v935 Load { addr=v929, disp=64, kind=I64 } -> x0 + v936 Store { addr=v929, disp=40, value=v935, kind=I64 } -> - + terminator Jmp(b87) (exit_acc=v936) block 87 start_pc=0 - v462 ImmData(1318) -> x7 - v463 ImmData(1864) -> x0 - v464 Load { addr=v463, disp=0, kind=I64 } -> x6 - v465 CallExt { binding_idx=0, args=[v462, v464], fp_arg_mask=0x0 } -> x0 - v466 Imm(-1) -> x0 - terminator Return(v466) (exit_acc=v466) + v937 ImmData(1816) -> x0 + v938 Load { addr=v937, disp=0, kind=I64 } -> x1 + v939 Imm(72) -> x2 + v940 BinopI { op=add, lhs=v938, rhs_imm=72 } -> x1 + v941 Store { addr=v937, disp=0, value=v940, kind=I64 } -> - + terminator Jmp(b88) (exit_acc=v941) block 88 start_pc=0 - v467 ImmData(1816) -> x0 - v468 Load { addr=v467, disp=0, kind=I64 } -> x0 - v469 Imm(24) -> x1 - v470 BinopI { op=add, lhs=v468, rhs_imm=24 } -> x1 - v471 Load { addr=v468, disp=24, kind=I64 } -> x0 - v472 BinopI { op=eq, lhs=v471, rhs_imm=132 } -> x0 - terminator Bz { cond=v472, target=b90, fall=b89 } (exit_acc=v472) + v902 ImmData(1816) -> x0 + v903 Load { addr=v902, disp=0, kind=I64 } -> x0 + v904 Imm(0) -> x1 + v905 Load { addr=v903, disp=0, kind=I64 } -> x0 + terminator Bnz { cond=v905, target=b85, fall=b89 } (exit_acc=v905) block 89 start_pc=0 - v473 ImmData(1349) -> x7 - v474 ImmData(1864) -> x0 - v475 Load { addr=v474, disp=0, kind=I64 } -> x6 - v476 CallExt { binding_idx=0, args=[v473, v475], fp_arg_mask=0x0 } -> x0 - v477 Imm(-1) -> x0 - terminator Return(v477) (exit_acc=v477) + terminator Jmp(b90) block 90 start_pc=0 - v478 ImmData(1816) -> x0 - v479 Load { addr=v478, disp=0, kind=I64 } -> x1 - v480 Imm(48) -> x2 - v481 BinopI { op=add, lhs=v479, rhs_imm=48 } -> x2 - v482 Load { addr=v478, disp=0, kind=I64 } -> x2 - v483 Imm(24) -> x2 - v484 BinopI { op=add, lhs=v479, rhs_imm=24 } -> x2 - v485 Load { addr=v479, disp=24, kind=I64 } -> x2 - v486 Store { addr=v479, disp=48, value=v485, kind=I64 } -> - - v487 Load { addr=v478, disp=0, kind=I64 } -> x1 - v488 BinopI { op=add, lhs=v487, rhs_imm=24 } -> x2 - v489 Imm(132) -> x2 - v490 Store { addr=v487, disp=24, value=v489, kind=I64 } -> - - v491 Load { addr=v478, disp=0, kind=I64 } -> x1 - v492 Imm(56) -> x2 - v493 BinopI { op=add, lhs=v491, rhs_imm=56 } -> x2 - v494 Load { addr=v478, disp=0, kind=I64 } -> x2 - v495 Imm(32) -> x2 - v496 BinopI { op=add, lhs=v491, rhs_imm=32 } -> x2 - v497 Load { addr=v491, disp=32, kind=I64 } -> x2 - v498 Store { addr=v491, disp=56, value=v497, kind=I64 } -> - - v499 Load { addr=v478, disp=0, kind=I64 } -> x1 - v500 BinopI { op=add, lhs=v499, rhs_imm=32 } -> x2 - v501 LoadLocal { off=-3, kind=I64 } -> x2 - v502 Store { addr=v499, disp=32, value=v451, kind=I64 } -> - - v503 Load { addr=v478, disp=0, kind=I64 } -> x1 - v504 Imm(64) -> x2 - v505 BinopI { op=add, lhs=v503, rhs_imm=64 } -> x2 - v506 Load { addr=v478, disp=0, kind=I64 } -> x2 - v507 Imm(40) -> x2 - v508 BinopI { op=add, lhs=v503, rhs_imm=40 } -> x2 - v509 Load { addr=v503, disp=40, kind=I64 } -> x2 - v510 Store { addr=v503, disp=64, value=v509, kind=I64 } -> - - v511 Load { addr=v478, disp=0, kind=I64 } -> x0 - v512 BinopI { op=add, lhs=v511, rhs_imm=40 } -> x1 - v513 LoadLocal { off=-11, kind=I64 } -> x1 - v514 BinopI { op=add, lhs=v429, rhs_imm=1 } -> [spill 2] - v515 Imm(0) -> x1 - v516 Store { addr=v511, disp=40, value=v429, kind=I64 } -> - - v517 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v518 ImmData(1832) -> x0 - v519 Load { addr=v518, disp=0, kind=I64 } -> x0 - v520 BinopI { op=eq, lhs=v519, rhs_imm=44 } -> x0 - terminator Bz { cond=v520, target=b92, fall=b91 } (exit_acc=v520) + v650 Phi { incoming=[b89:v774, b93:v583], kind=I64 } -> x13 + v651 ImmData(1832) -> x0 + v652 Load { addr=v651, disp=0, kind=I64 } -> x0 + v653 BinopI { op=eq, lhs=v652, rhs_imm=44 } -> x0 + terminator Bz { cond=v653, target=b92, fall=b91 } (exit_acc=v653) block 91 start_pc=0 - v521 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b92) (exit_acc=v521) + v942 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b92) (exit_acc=v942) block 92 start_pc=0 - terminator Jmp(b76) + terminator Jmp(b36) block 93 start_pc=0 - v522 ImmData(1385) -> x7 - v523 ImmData(1864) -> x0 - v524 Load { addr=v523, disp=0, kind=I64 } -> x6 - v525 CallExt { binding_idx=0, args=[v522, v524], fp_arg_mask=0x0 } -> x0 - v526 Imm(-1) -> x0 - terminator Return(v526) (exit_acc=v526) + v654 ImmData(1816) -> x0 + v655 Load { addr=v654, disp=0, kind=I64 } -> x1 + v656 Imm(24) -> x2 + v657 BinopI { op=add, lhs=v655, rhs_imm=24 } -> x2 + v658 Imm(131) -> x2 + v659 Store { addr=v655, disp=24, value=v658, kind=I64 } -> - + v660 Load { addr=v654, disp=0, kind=I64 } -> x0 + v661 Imm(40) -> x1 + v662 BinopI { op=add, lhs=v660, rhs_imm=40 } -> x1 + v663 ImmData(1792) -> x1 + v664 Load { addr=v663, disp=0, kind=I64 } -> x2 + v665 Store { addr=v660, disp=40, value=v664, kind=I64 } -> - + v666 Load { addr=v663, disp=0, kind=I64 } -> x0 + v667 BinopI { op=add, lhs=v666, rhs_imm=8 } -> x0 + v668 Store { addr=v663, disp=0, value=v667, kind=I64 } -> - + terminator Jmp(b90) (exit_acc=v668) block 94 start_pc=0 - v527 ImmData(1856) -> x0 - v528 LoadLocal { off=-11, kind=I64 } -> x1 - v529 BinopI { op=add, lhs=v429, rhs_imm=1 } -> [spill 1] - v530 Imm(0) -> x1 - v531 Store { addr=v527, disp=0, value=v529, kind=I64 } -> - - v532 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b95) (exit_acc=v532) + terminator Jmp(b38) block 95 start_pc=0 - v533 Phi { incoming=[b94:v529, b105:v570], kind=I64 } -> [spill 1] - v534 Phi { incoming=[b94:v343, b105:v566], kind=I64 } -> x3 - v535 ImmData(1832) -> x0 - v536 Load { addr=v535, disp=0, kind=I64 } -> x0 - v537 BinopI { op=eq, lhs=v536, rhs_imm=138 } -> [spill 2] - v538 Imm(0) -> x0 - terminator Bnz { cond=v537, target=b269, fall=b98 } (exit_acc=v537) + v507 ImmData(1832) -> x0 + v508 Load { addr=v507, disp=0, kind=I64 } -> x0 + v509 BinopI { op=eq, lhs=v508, rhs_imm=134 } -> x0 + terminator Bz { cond=v509, target=b98, fall=b96 } (exit_acc=v509) block 96 start_pc=0 - v539 ImmData(1832) -> x0 - v540 Load { addr=v539, disp=0, kind=I64 } -> x0 - v541 BinopI { op=eq, lhs=v540, rhs_imm=138 } -> x0 - terminator Bz { cond=v541, target=b101, fall=b100 } (exit_acc=v541) + v510 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v511 Imm(0) -> x13 + v512 Imm(0) -> x0 + terminator Jmp(b97) (exit_acc=v511) block 97 start_pc=0 - v542 ImmData(1800) -> x0 - v543 Load { addr=v542, disp=0, kind=I64 } -> x1 - v544 BinopI { op=add, lhs=v543, rhs_imm=8 } -> x1 - v545 Store { addr=v542, disp=0, value=v544, kind=I64 } -> - - v546 Imm(6) -> x2 - v547 Store { addr=v544, disp=0, value=v546, kind=I64 } -> - - v548 Load { addr=v542, disp=0, kind=I64 } -> x1 - v549 BinopI { op=add, lhs=v548, rhs_imm=8 } -> x1 - v550 Store { addr=v542, disp=0, value=v549, kind=I64 } -> - - v551 LoadLocal { off=-11, kind=I64 } -> x0 - v552 ImmData(1856) -> x0 - v553 Load { addr=v552, disp=0, kind=I64 } -> x0 - v554 Binop { op=sub, lhs=v533, rhs=v553 } -> x0 - v555 Store { addr=v549, disp=0, value=v554, kind=I64 } -> - - terminator Jmp(b115) (exit_acc=v555) + v513 Phi { incoming=[b96:v511, b113:v494], kind=I64 } -> x13 + terminator Jmp(b35) block 98 start_pc=0 - v556 ImmData(1832) -> x0 - v557 Load { addr=v556, disp=0, kind=I64 } -> x0 - v558 BinopI { op=eq, lhs=v557, rhs_imm=134 } -> [spill 2] - v559 Imm(0) -> x0 - terminator Jmp(b99) (exit_acc=v558) + v514 ImmData(1832) -> x0 + v515 Load { addr=v514, disp=0, kind=I64 } -> x0 + v516 BinopI { op=eq, lhs=v515, rhs_imm=136 } -> x0 + terminator Bz { cond=v516, target=b113, fall=b99 } (exit_acc=v516) block 99 start_pc=0 - v560 Phi { incoming=[b269:v537, b98:v558], kind=I64 } -> [spill 2] - v561 LoadLocal { off=-24, kind=I64 } -> x0 - terminator Bz { cond=v560, target=b97, fall=b96 } (exit_acc=v560) + v517 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v518 ImmData(1832) -> x0 + v519 Load { addr=v518, disp=0, kind=I64 } -> x0 + v520 BinopI { op=ne, lhs=v519, rhs_imm=123 } -> x0 + terminator Bz { cond=v520, target=b101, fall=b100 } (exit_acc=v520) block 100 start_pc=0 - v562 Imm(1) -> x3 - v563 Imm(0) -> x0 - terminator Jmp(b102) (exit_acc=v562) + v521 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b101) (exit_acc=v521) block 101 start_pc=0 - v564 Imm(0) -> x3 - v565 Imm(0) -> x0 - terminator Jmp(b102) (exit_acc=v564) + v522 ImmData(1832) -> x0 + v523 Load { addr=v522, disp=0, kind=I64 } -> x0 + v524 BinopI { op=eq, lhs=v523, rhs_imm=123 } -> x0 + terminator Bz { cond=v524, target=b113, fall=b102 } (exit_acc=v524) block 102 start_pc=0 - v566 Phi { incoming=[b100:v562, b101:v564], kind=I64 } -> x3 - v567 LoadLocal { off=-25, kind=I64 } -> x0 - v568 Imm(0) -> x0 - v569 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b103) (exit_acc=v569) + v525 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v526 Imm(0) -> [spill 1] + v527 Imm(0) -> x0 + terminator Jmp(b111) (exit_acc=v526) block 103 start_pc=0 - v570 Phi { incoming=[b102:v533, b114:v640], kind=I64 } -> [spill 1] - v571 ImmData(1832) -> x0 - v572 Load { addr=v571, disp=0, kind=I64 } -> x0 - v573 BinopI { op=ne, lhs=v572, rhs_imm=59 } -> x0 - terminator Bz { cond=v573, target=b105, fall=b104 } (exit_acc=v573) + v532 ImmData(1832) -> x0 + v533 Load { addr=v532, disp=0, kind=I64 } -> x0 + v534 BinopI { op=ne, lhs=v533, rhs_imm=133 } -> x0 + terminator Bnz { cond=v534, target=b243, fall=b104 } (exit_acc=v534) block 104 start_pc=0 - v574 LoadLocal { off=-2, kind=I64 } -> x0 - v575 Imm(0) -> x0 - terminator Jmp(b106) (exit_acc=v566) + v543 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v544 ImmData(1832) -> x0 + v545 Load { addr=v544, disp=0, kind=I64 } -> x0 + v546 BinopI { op=eq, lhs=v545, rhs_imm=142 } -> x0 + terminator Bz { cond=v546, target=b109, fall=b105 } (exit_acc=v546) block 105 start_pc=0 - v576 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b95) (exit_acc=v576) + v547 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + v548 ImmData(1832) -> x0 + v549 Load { addr=v548, disp=0, kind=I64 } -> x0 + v550 BinopI { op=ne, lhs=v549, rhs_imm=128 } -> x0 + terminator Bnz { cond=v550, target=b242, fall=b106 } (exit_acc=v550) block 106 start_pc=0 - v577 Phi { incoming=[b104:v566, b107:v583], kind=I64 } -> [spill 2] - v578 ImmData(1832) -> x0 - v579 Load { addr=v578, disp=0, kind=I64 } -> x0 - v580 BinopI { op=eq, lhs=v579, rhs_imm=159 } -> x0 - terminator Bz { cond=v580, target=b108, fall=b107 } (exit_acc=v580) - block 107 start_pc=0 + v578 ImmData(1840) -> x0 + v579 Load { addr=v578, disp=0, kind=I64 } -> [spill 2] + v580 Imm(0) -> x0 v581 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v582 LoadLocal { off=-3, kind=I64 } -> x0 - v583 BinopI { op=add, lhs=v577, rhs_imm=2 } -> [spill 2] - v584 Imm(0) -> x0 - terminator Jmp(b106) (exit_acc=v583) + terminator Jmp(b107) (exit_acc=v581) + block 107 start_pc=0 + v551 Phi { incoming=[b109:v528, b106:v579], kind=I64 } -> [spill 2] + v552 ImmData(1816) -> x0 + v553 Load { addr=v552, disp=0, kind=I64 } -> x1 + v554 Imm(24) -> x2 + v555 BinopI { op=add, lhs=v553, rhs_imm=24 } -> x2 + v556 Imm(128) -> x2 + v557 Store { addr=v553, disp=24, value=v556, kind=I64 } -> - + v558 Load { addr=v552, disp=0, kind=I64 } -> x1 + v559 Imm(32) -> x2 + v560 BinopI { op=add, lhs=v558, rhs_imm=32 } -> x2 + v561 Imm(1) -> x2 + v562 Store { addr=v558, disp=32, value=v561, kind=I64 } -> - + v563 Load { addr=v552, disp=0, kind=I64 } -> x0 + v564 Imm(40) -> x1 + v565 BinopI { op=add, lhs=v563, rhs_imm=40 } -> x1 + v566 LoadLocal { off=-11, kind=I64 } -> x1 + v567 BinopI { op=add, lhs=v551, rhs_imm=1 } -> [spill 1] + v568 Imm(0) -> x1 + v569 Store { addr=v563, disp=40, value=v551, kind=I64 } -> - + v570 ImmData(1832) -> x0 + v571 Load { addr=v570, disp=0, kind=I64 } -> x0 + v572 BinopI { op=eq, lhs=v571, rhs_imm=44 } -> x0 + terminator Bz { cond=v572, target=b110, fall=b108 } (exit_acc=v572) block 108 start_pc=0 - v585 ImmData(1832) -> x0 - v586 Load { addr=v585, disp=0, kind=I64 } -> x0 - v587 BinopI { op=ne, lhs=v586, rhs_imm=133 } -> x0 - terminator Bz { cond=v587, target=b110, fall=b109 } (exit_acc=v587) + v582 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b110) (exit_acc=v582) block 109 start_pc=0 - v588 ImmData(1414) -> x7 - v589 ImmData(1864) -> x0 - v590 Load { addr=v589, disp=0, kind=I64 } -> x6 - v591 CallExt { binding_idx=0, args=[v588, v590], fp_arg_mask=0x0 } -> x0 - v592 Imm(-1) -> x0 - terminator Return(v592) (exit_acc=v592) + terminator Jmp(b107) block 110 start_pc=0 - v593 ImmData(1816) -> x0 - v594 Load { addr=v593, disp=0, kind=I64 } -> x0 - v595 Imm(24) -> x1 - v596 BinopI { op=add, lhs=v594, rhs_imm=24 } -> x1 - v597 Load { addr=v594, disp=24, kind=I64 } -> x0 - v598 BinopI { op=eq, lhs=v597, rhs_imm=132 } -> x0 - terminator Bz { cond=v598, target=b112, fall=b111 } (exit_acc=v598) + terminator Jmp(b111) block 111 start_pc=0 - v599 ImmData(1441) -> x7 - v600 ImmData(1864) -> x0 - v601 Load { addr=v600, disp=0, kind=I64 } -> x6 - v602 CallExt { binding_idx=0, args=[v599, v601], fp_arg_mask=0x0 } -> x0 - v603 Imm(-1) -> x0 - terminator Return(v603) (exit_acc=v603) + v528 Phi { incoming=[b102:v526, b110:v567], kind=I64 } -> [spill 1] + v529 ImmData(1832) -> x0 + v530 Load { addr=v529, disp=0, kind=I64 } -> x0 + v531 BinopI { op=ne, lhs=v530, rhs_imm=125 } -> x0 + terminator Bnz { cond=v531, target=b103, fall=b112 } (exit_acc=v531) block 112 start_pc=0 - v604 ImmData(1816) -> x0 - v605 Load { addr=v604, disp=0, kind=I64 } -> x1 - v606 Imm(48) -> x2 - v607 BinopI { op=add, lhs=v605, rhs_imm=48 } -> x2 - v608 Load { addr=v604, disp=0, kind=I64 } -> x2 - v609 Imm(24) -> x2 - v610 BinopI { op=add, lhs=v605, rhs_imm=24 } -> x2 - v611 Load { addr=v605, disp=24, kind=I64 } -> x2 - v612 Store { addr=v605, disp=48, value=v611, kind=I64 } -> - - v613 Load { addr=v604, disp=0, kind=I64 } -> x1 - v614 BinopI { op=add, lhs=v613, rhs_imm=24 } -> x2 - v615 Imm(132) -> x2 - v616 Store { addr=v613, disp=24, value=v615, kind=I64 } -> - - v617 Load { addr=v604, disp=0, kind=I64 } -> x1 - v618 Imm(56) -> x2 - v619 BinopI { op=add, lhs=v617, rhs_imm=56 } -> x2 - v620 Load { addr=v604, disp=0, kind=I64 } -> x2 - v621 Imm(32) -> x2 - v622 BinopI { op=add, lhs=v617, rhs_imm=32 } -> x2 - v623 Load { addr=v617, disp=32, kind=I64 } -> x2 - v624 Store { addr=v617, disp=56, value=v623, kind=I64 } -> - - v625 Load { addr=v604, disp=0, kind=I64 } -> x1 - v626 BinopI { op=add, lhs=v625, rhs_imm=32 } -> x2 - v627 LoadLocal { off=-3, kind=I64 } -> x2 - v628 Store { addr=v625, disp=32, value=v577, kind=I64 } -> - - v629 Load { addr=v604, disp=0, kind=I64 } -> x1 - v630 Imm(64) -> x2 - v631 BinopI { op=add, lhs=v629, rhs_imm=64 } -> x2 - v632 Load { addr=v604, disp=0, kind=I64 } -> x2 - v633 Imm(40) -> x2 - v634 BinopI { op=add, lhs=v629, rhs_imm=40 } -> x2 - v635 Load { addr=v629, disp=40, kind=I64 } -> x2 - v636 Store { addr=v629, disp=64, value=v635, kind=I64 } -> - - v637 Load { addr=v604, disp=0, kind=I64 } -> x0 - v638 BinopI { op=add, lhs=v637, rhs_imm=40 } -> x1 - v639 LoadLocal { off=-11, kind=I64 } -> x1 - v640 BinopI { op=add, lhs=v570, rhs_imm=1 } -> [spill 1] - v641 Imm(0) -> x1 - v642 Store { addr=v637, disp=40, value=v640, kind=I64 } -> - - v643 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v644 ImmData(1832) -> x0 - v645 Load { addr=v644, disp=0, kind=I64 } -> x0 - v646 BinopI { op=eq, lhs=v645, rhs_imm=44 } -> x0 - terminator Bz { cond=v646, target=b114, fall=b113 } (exit_acc=v646) + v535 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b113) (exit_acc=v535) block 113 start_pc=0 - v647 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b114) (exit_acc=v647) + terminator Jmp(b97) block 114 start_pc=0 - terminator Jmp(b103) + v590 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b115) (exit_acc=v590) block 115 start_pc=0 - v648 ImmData(1832) -> x0 - v649 Load { addr=v648, disp=0, kind=I64 } -> x0 - v650 BinopI { op=ne, lhs=v649, rhs_imm=125 } -> x0 - terminator Bz { cond=v650, target=b117, fall=b116 } (exit_acc=v650) + v492 ImmData(1832) -> x0 + v493 Load { addr=v492, disp=0, kind=I64 } -> x0 + terminator Bnz { cond=v493, target=b33, fall=b116 } (exit_acc=v493) block 116 start_pc=0 - v651 Call { target_pc=8, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b115) (exit_acc=v651) + v499 LoadLocal { off=-5, kind=I64 } -> x0 + v500 Imm(40) -> x0 + v501 BinopI { op=add, lhs=v447, rhs_imm=40 } -> x0 + v502 Load { addr=v447, disp=40, kind=I64 } -> x6 + v503 Imm(0) -> x0 + v504 BinopI { op=eq, lhs=v502, rhs_imm=0 } -> x0 + terminator Bz { cond=v504, target=b118, fall=b117 } (exit_acc=v504) block 117 start_pc=0 - v652 ImmData(1800) -> x0 - v653 Load { addr=v652, disp=0, kind=I64 } -> x1 - v654 BinopI { op=add, lhs=v653, rhs_imm=8 } -> x1 - v655 Store { addr=v652, disp=0, value=v654, kind=I64 } -> - - v656 Imm(8) -> x0 - v657 Store { addr=v654, disp=0, value=v656, kind=I64 } -> - - v658 ImmData(1816) -> x0 - v659 ImmData(1824) -> x1 - v660 Load { addr=v659, disp=0, kind=I64 } -> x1 - v661 Store { addr=v658, disp=0, value=v660, kind=I64 } -> - - terminator Jmp(b118) (exit_acc=v661) + v943 ImmData(1473) -> x7 + v944 CallExt { binding_idx=0, args=[v943], fp_arg_mask=0x0 } -> x0 + v945 Imm(-1) -> x0 + terminator Return(v945) (exit_acc=v945) block 118 start_pc=0 - v662 ImmData(1816) -> x0 - v663 Load { addr=v662, disp=0, kind=I64 } -> x0 - v664 Imm(0) -> x1 - v665 Load { addr=v663, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v665, target=b120, fall=b119 } (exit_acc=v665) + v946 ImmData(1872) -> x0 + v947 Load { addr=v946, disp=0, kind=I64 } -> x0 + terminator Bz { cond=v947, target=b120, fall=b119 } (exit_acc=v947) block 119 start_pc=0 - v666 ImmData(1816) -> x0 - v667 Load { addr=v666, disp=0, kind=I64 } -> x0 - v668 Imm(24) -> x1 - v669 BinopI { op=add, lhs=v667, rhs_imm=24 } -> x1 - v670 Load { addr=v667, disp=24, kind=I64 } -> x0 - v671 BinopI { op=eq, lhs=v670, rhs_imm=132 } -> x0 - terminator Bz { cond=v671, target=b122, fall=b121 } (exit_acc=v671) + v948 Imm(0) -> x0 + terminator Return(v948) (exit_acc=v948) block 120 start_pc=0 - terminator Jmp(b74) + v949 LoadLocal { off=-7, kind=I64 } -> x0 + v950 LoadLocal { off=-4, kind=I64 } -> x0 + v951 Binop { op=add, lhs=v134, rhs=v93 } -> x13 + v952 Imm(0) -> x0 + v953 Imm(0) -> x0 + v954 LoadLocal { off=-7, kind=I64 } -> x0 + v955 BinopI { op=add, lhs=v951, rhs_imm=-8 } -> x0 + v956 Imm(0) -> x1 + v957 Imm(38) -> x1 + v958 Store { addr=v955, disp=0, value=v957, kind=I64 } -> - + v959 LoadLocal { off=-7, kind=I64 } -> x1 + v960 BinopI { op=add, lhs=v955, rhs_imm=-8 } -> x0 + v961 Imm(0) -> x1 + v962 Imm(13) -> x1 + v963 Store { addr=v960, disp=0, value=v962, kind=I64 } -> - + v964 LoadLocal { off=-7, kind=I64 } -> x1 + v965 Imm(0) -> x1 + v966 BinopI { op=add, lhs=v960, rhs_imm=-8 } -> x1 + v967 Imm(0) -> x2 + v968 LoadLocal { off=2, kind=I64 } -> x2 + v969 Store { addr=v966, disp=0, value=v75, kind=I64 } -> - + v970 LoadLocal { off=-7, kind=I64 } -> x2 + v971 BinopI { op=add, lhs=v966, rhs_imm=-8 } -> x1 + v972 Imm(0) -> x2 + v973 LoadLocal { off=3, kind=I64 } -> x2 + v974 Store { addr=v971, disp=0, value=v76, kind=I64 } -> - + v975 LoadLocal { off=-7, kind=I64 } -> x2 + v976 BinopI { op=add, lhs=v971, rhs_imm=-8 } -> x12 + v977 Imm(0) -> x1 + v978 LoadLocal { off=-12, kind=I64 } -> x1 + v979 Store { addr=v976, disp=0, value=v960, kind=I64 } -> - + v980 Imm(0) -> x3 + v981 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v980) block 121 start_pc=0 - v672 ImmData(1816) -> x0 - v673 Load { addr=v672, disp=0, kind=I64 } -> x1 - v674 Imm(24) -> x2 - v675 BinopI { op=add, lhs=v673, rhs_imm=24 } -> x2 - v676 Load { addr=v672, disp=0, kind=I64 } -> x2 - v677 Imm(48) -> x2 - v678 BinopI { op=add, lhs=v673, rhs_imm=48 } -> x2 - v679 Load { addr=v673, disp=48, kind=I64 } -> x2 - v680 Store { addr=v673, disp=24, value=v679, kind=I64 } -> - - v681 Load { addr=v672, disp=0, kind=I64 } -> x1 - v682 Imm(32) -> x2 - v683 BinopI { op=add, lhs=v681, rhs_imm=32 } -> x2 - v684 Load { addr=v672, disp=0, kind=I64 } -> x2 - v685 Imm(56) -> x2 - v686 BinopI { op=add, lhs=v681, rhs_imm=56 } -> x2 - v687 Load { addr=v681, disp=56, kind=I64 } -> x2 - v688 Store { addr=v681, disp=32, value=v687, kind=I64 } -> - - v689 Load { addr=v672, disp=0, kind=I64 } -> x1 - v690 Imm(40) -> x2 - v691 BinopI { op=add, lhs=v689, rhs_imm=40 } -> x2 - v692 Load { addr=v672, disp=0, kind=I64 } -> x0 - v693 Imm(64) -> x0 - v694 BinopI { op=add, lhs=v689, rhs_imm=64 } -> x0 - v695 Load { addr=v689, disp=64, kind=I64 } -> x0 - v696 Store { addr=v689, disp=40, value=v695, kind=I64 } -> - - terminator Jmp(b122) (exit_acc=v696) + v982 Phi { incoming=[b120:v980, b127:v993], kind=I64 } -> x3 + v983 Phi { incoming=[b120:v951, b127:v1023], kind=I64 } -> x13 + v984 Phi { incoming=[b120:v976, b127:v1024], kind=I64 } -> x12 + v985 Phi { incoming=[b120:v502, b127:v1025], kind=I64 } -> x6 + v986 Imm(1) -> x0 + terminator Jmp(b122) (exit_acc=v986) block 122 start_pc=0 - v697 ImmData(1816) -> x0 - v698 Load { addr=v697, disp=0, kind=I64 } -> x1 - v699 Imm(72) -> x2 - v700 BinopI { op=add, lhs=v698, rhs_imm=72 } -> x1 - v701 Store { addr=v697, disp=0, value=v700, kind=I64 } -> - - terminator Jmp(b118) (exit_acc=v701) + v987 LoadLocal { off=-6, kind=I64 } -> x0 + v988 BinopI { op=add, lhs=v985, rhs_imm=8 } -> x14 + v989 Imm(0) -> x0 + v990 Load { addr=v985, disp=0, kind=I64 } -> x15 + v991 Imm(0) -> x0 + v992 LoadLocal { off=-10, kind=I64 } -> x0 + v993 BinopI { op=add, lhs=v982, rhs_imm=1 } -> x3 + v994 Imm(0) -> x0 + v995 ImmData(1880) -> x0 + v996 Load { addr=v995, disp=0, kind=I64 } -> x0 + terminator Bz { cond=v996, target=b125, fall=b123 } (exit_acc=v996) block 123 start_pc=0 - v702 Call { target_pc=6, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b124) (exit_acc=v702) + v998 ImmData(1493) -> x7 + v999 LoadLocal { off=-10, kind=I64 } -> x0 + v1000 ImmData(1502) -> x0 + v1001 LoadLocal { off=-11, kind=I64 } -> x1 + v1002 BinopI { op=mul, lhs=v990, rhs_imm=5 } -> x1 + v1003 Binop { op=add, lhs=v1000, rhs=v1002 } -> x2 + v1004 CallExt { binding_idx=0, args=[v998, v993, v1003], fp_arg_mask=0x0 } -> x0 + v1005 LoadLocal { off=-11, kind=I64 } -> x0 + v1006 BinopI { op=le, lhs=v990, rhs_imm=7 } -> x0 + terminator Bz { cond=v1006, target=b238, fall=b124 } (exit_acc=v1006) block 124 start_pc=0 - terminator Jmp(b61) + v1009 ImmData(1698) -> x7 + v1010 LoadLocal { off=-6, kind=I64 } -> x0 + v1011 Load { addr=v988, disp=0, kind=I64 } -> x6 + v1012 CallExt { binding_idx=0, args=[v1009, v1011], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b125) (exit_acc=v1012) block 125 start_pc=0 - v703 ImmData(1473) -> x7 - v704 CallExt { binding_idx=0, args=[v703], fp_arg_mask=0x0 } -> x0 - v705 Imm(-1) -> x0 - terminator Return(v705) (exit_acc=v705) + v1007 LoadLocal { off=-11, kind=I64 } -> x0 + v1008 BinopI { op=eq, lhs=v990, rhs_imm=0 } -> x0 + terminator Bz { cond=v1008, target=b128, fall=b126 } (exit_acc=v1008) block 126 start_pc=0 - v706 ImmData(1872) -> x0 - v707 Load { addr=v706, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v707, target=b128, fall=b127 } (exit_acc=v707) + v1015 LoadLocal { off=-8, kind=I64 } -> x0 + v1016 LoadLocal { off=-6, kind=I64 } -> x0 + v1017 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1018 Imm(0) -> x0 + v1019 Load { addr=v988, disp=0, kind=I64 } -> x0 + v1020 BinopI { op=shl, lhs=v1019, rhs_imm=3 } -> x0 + v1021 Binop { op=add, lhs=v983, rhs=v1020 } -> x0 + v1022 StoreLocal { off=-9, value=v1021, kind=I64 } -> - + terminator Jmp(b127) (exit_acc=v1022) block 127 start_pc=0 - v708 Imm(0) -> x0 - terminator Return(v708) (exit_acc=v708) + v1023 Phi { incoming=[b126:v983, b130:v1033], kind=I64 } -> x13 + v1024 Phi { incoming=[b126:v984, b130:v1034], kind=I64 } -> x12 + v1025 Phi { incoming=[b126:v1017, b130:v1035], kind=I64 } -> x6 + terminator Jmp(b121) block 128 start_pc=0 - v709 LoadLocal { off=-7, kind=I64 } -> x0 - v710 LoadLocal { off=-4, kind=I64 } -> x0 - v711 Binop { op=add, lhs=v134, rhs=v93 } -> x14 - v712 Imm(0) -> x0 - v713 Imm(0) -> x0 - v714 LoadLocal { off=-7, kind=I64 } -> x0 - v715 BinopI { op=add, lhs=v711, rhs_imm=-8 } -> x0 - v716 Imm(0) -> x1 - v717 Imm(38) -> x1 - v718 Store { addr=v715, disp=0, value=v717, kind=I64 } -> - - v719 LoadLocal { off=-7, kind=I64 } -> x1 - v720 BinopI { op=add, lhs=v715, rhs_imm=-8 } -> x0 - v721 Imm(0) -> x1 - v722 Imm(13) -> x1 - v723 Store { addr=v720, disp=0, value=v722, kind=I64 } -> - - v724 LoadLocal { off=-7, kind=I64 } -> x1 - v725 Imm(0) -> x1 - v726 BinopI { op=add, lhs=v720, rhs_imm=-8 } -> x1 - v727 Imm(0) -> x2 - v728 LoadLocal { off=2, kind=I64 } -> x2 - v729 Store { addr=v726, disp=0, value=v75, kind=I64 } -> - - v730 LoadLocal { off=-7, kind=I64 } -> x2 - v731 BinopI { op=add, lhs=v726, rhs_imm=-8 } -> x1 - v732 Imm(0) -> x2 - v733 LoadLocal { off=3, kind=I64 } -> x2 - v734 Store { addr=v731, disp=0, value=v76, kind=I64 } -> - - v735 LoadLocal { off=-7, kind=I64 } -> x2 - v736 BinopI { op=add, lhs=v731, rhs_imm=-8 } -> x12 - v737 Imm(0) -> x1 - v738 LoadLocal { off=-12, kind=I64 } -> x1 - v739 Store { addr=v736, disp=0, value=v720, kind=I64 } -> - - v740 Imm(0) -> x3 - v741 Imm(0) -> x0 - terminator Jmp(b129) (exit_acc=v740) + v1026 LoadLocal { off=-11, kind=I64 } -> x0 + v1027 BinopI { op=eq, lhs=v990, rhs_imm=1 } -> x0 + terminator Bz { cond=v1027, target=b131, fall=b129 } (exit_acc=v1027) block 129 start_pc=0 - v742 Phi { incoming=[b128:v740, b138:v753], kind=I64 } -> x3 - v743 Phi { incoming=[b128:v711, b138:v783], kind=I64 } -> x14 - v744 Phi { incoming=[b128:v736, b138:v784], kind=I64 } -> x12 - v745 Phi { incoming=[b128:v262, b138:v785], kind=I64 } -> [spill 0] - v746 Imm(1) -> x0 - terminator Jmp(b130) (exit_acc=v746) + v1028 LoadLocal { off=-6, kind=I64 } -> x0 + v1029 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1030 Imm(0) -> x0 + v1031 Load { addr=v988, disp=0, kind=I64 } -> x0 + v1032 StoreLocal { off=-9, value=v1031, kind=I64 } -> - + terminator Jmp(b130) (exit_acc=v1032) block 130 start_pc=0 - v747 LoadLocal { off=-6, kind=I64 } -> x0 - v748 BinopI { op=add, lhs=v745, rhs_imm=8 } -> x13 - v749 Imm(0) -> x0 - v750 Load { addr=v745, disp=0, kind=I64 } -> x15 - v751 Imm(0) -> x0 - v752 LoadLocal { off=-10, kind=I64 } -> x0 - v753 BinopI { op=add, lhs=v742, rhs_imm=1 } -> x3 - v754 Imm(0) -> x0 - v755 ImmData(1880) -> x0 - v756 Load { addr=v755, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v756, target=b133, fall=b132 } (exit_acc=v756) + v1033 Phi { incoming=[b129:v983, b133:v1041], kind=I64 } -> x13 + v1034 Phi { incoming=[b129:v984, b133:v1042], kind=I64 } -> x12 + v1035 Phi { incoming=[b129:v1029, b133:v1043], kind=I64 } -> x6 + terminator Jmp(b127) block 131 start_pc=0 - v757 Imm(0) -> x0 - terminator Return(v757) (exit_acc=v757) + v1036 LoadLocal { off=-11, kind=I64 } -> x0 + v1037 BinopI { op=eq, lhs=v990, rhs_imm=2 } -> x0 + terminator Bz { cond=v1037, target=b134, fall=b132 } (exit_acc=v1037) block 132 start_pc=0 - v758 ImmData(1493) -> x7 - v759 LoadLocal { off=-10, kind=I64 } -> x0 - v760 ImmData(1502) -> x0 - v761 LoadLocal { off=-11, kind=I64 } -> x1 - v762 BinopI { op=mul, lhs=v750, rhs_imm=5 } -> x1 - v763 Binop { op=add, lhs=v760, rhs=v762 } -> x2 - v764 CallExt { binding_idx=0, args=[v758, v753, v763], fp_arg_mask=0x0 } -> x0 - v765 LoadLocal { off=-11, kind=I64 } -> x0 - v766 BinopI { op=le, lhs=v750, rhs_imm=7 } -> x0 - terminator Bz { cond=v766, target=b136, fall=b134 } (exit_acc=v766) + v1038 LoadLocal { off=-6, kind=I64 } -> x0 + v1039 Load { addr=v988, disp=0, kind=I64 } -> x6 + v1040 Imm(0) -> x0 + terminator Jmp(b133) (exit_acc=v1039) block 133 start_pc=0 - v767 LoadLocal { off=-11, kind=I64 } -> x0 - v768 BinopI { op=eq, lhs=v750, rhs_imm=0 } -> x0 - terminator Bz { cond=v768, target=b139, fall=b137 } (exit_acc=v768) + v1041 Phi { incoming=[b132:v983, b136:v1056], kind=I64 } -> x13 + v1042 Phi { incoming=[b132:v984, b136:v1057], kind=I64 } -> x12 + v1043 Phi { incoming=[b132:v1039, b136:v1058], kind=I64 } -> x6 + terminator Jmp(b130) block 134 start_pc=0 - v769 ImmData(1698) -> x7 - v770 LoadLocal { off=-6, kind=I64 } -> x0 - v771 Load { addr=v748, disp=0, kind=I64 } -> x6 - v772 CallExt { binding_idx=0, args=[v769, v771], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b135) (exit_acc=v772) + v1044 LoadLocal { off=-11, kind=I64 } -> x0 + v1045 BinopI { op=eq, lhs=v990, rhs_imm=3 } -> x0 + terminator Bz { cond=v1045, target=b137, fall=b135 } (exit_acc=v1045) block 135 start_pc=0 - terminator Jmp(b133) + v1046 LoadLocal { off=-7, kind=I64 } -> x0 + v1047 BinopI { op=add, lhs=v984, rhs_imm=-8 } -> x12 + v1048 Imm(0) -> x0 + v1049 LoadLocal { off=-6, kind=I64 } -> x0 + v1050 Imm(8) -> x0 + v1051 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x0 + v1052 Store { addr=v1047, disp=0, value=v1051, kind=I64 } -> - + v1053 LoadLocal { off=-6, kind=I64 } -> x0 + v1054 Load { addr=v988, disp=0, kind=I64 } -> x6 + v1055 Imm(0) -> x0 + terminator Jmp(b136) (exit_acc=v1054) block 136 start_pc=0 - v773 ImmData(1703) -> x7 - v774 CallExt { binding_idx=0, args=[v773], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b135) (exit_acc=v774) + v1056 Phi { incoming=[b135:v983, b141:v1062], kind=I64 } -> x13 + v1057 Phi { incoming=[b135:v1047, b141:v1063], kind=I64 } -> x12 + v1058 Phi { incoming=[b135:v1054, b141:v1064], kind=I64 } -> x6 + terminator Jmp(b133) block 137 start_pc=0 - v775 LoadLocal { off=-8, kind=I64 } -> x0 - v776 LoadLocal { off=-6, kind=I64 } -> x0 - v777 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v778 Imm(0) -> x0 - v779 Load { addr=v748, disp=0, kind=I64 } -> x0 - v780 BinopI { op=shl, lhs=v779, rhs_imm=3 } -> x0 - v781 Binop { op=add, lhs=v743, rhs=v780 } -> x0 - v782 StoreLocal { off=-9, value=v781, kind=I64 } -> - - terminator Jmp(b138) (exit_acc=v782) + v1059 LoadLocal { off=-11, kind=I64 } -> x0 + v1060 BinopI { op=eq, lhs=v990, rhs_imm=4 } -> x0 + terminator Bz { cond=v1060, target=b143, fall=b138 } (exit_acc=v1060) block 138 start_pc=0 - v783 Phi { incoming=[b137:v743, b141:v793], kind=I64 } -> x14 - v784 Phi { incoming=[b137:v744, b141:v794], kind=I64 } -> x12 - v785 Phi { incoming=[b137:v777, b141:v795], kind=I64 } -> [spill 0] - terminator Jmp(b129) + v1061 LoadLocal { off=-9, kind=I64 } -> x0 + terminator Bz { cond=v1061, target=b142, fall=b139 } (exit_acc=v1061) block 139 start_pc=0 - v786 LoadLocal { off=-11, kind=I64 } -> x0 - v787 BinopI { op=eq, lhs=v750, rhs_imm=1 } -> x0 - terminator Bz { cond=v787, target=b142, fall=b140 } (exit_acc=v787) + v1067 LoadLocal { off=-6, kind=I64 } -> x0 + v1068 Imm(8) -> x0 + v1069 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1070 Imm(0) -> x0 + terminator Jmp(b140) (exit_acc=v1069) block 140 start_pc=0 - v788 LoadLocal { off=-6, kind=I64 } -> x0 - v789 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v790 Imm(0) -> x0 - v791 Load { addr=v748, disp=0, kind=I64 } -> x0 - v792 StoreLocal { off=-9, value=v791, kind=I64 } -> - - terminator Jmp(b141) (exit_acc=v792) + v1074 Phi { incoming=[b139:v1069, b142:v1072], kind=I64 } -> x6 + v1075 LoadLocal { off=-26, kind=I64 } -> x0 + v1076 Imm(0) -> x0 + terminator Jmp(b141) (exit_acc=v1074) block 141 start_pc=0 - v793 Phi { incoming=[b140:v743, b144:v801], kind=I64 } -> x14 - v794 Phi { incoming=[b140:v744, b144:v802], kind=I64 } -> x12 - v795 Phi { incoming=[b140:v789, b144:v803], kind=I64 } -> [spill 0] - terminator Jmp(b138) + v1062 Phi { incoming=[b140:v983, b147:v1078], kind=I64 } -> x13 + v1063 Phi { incoming=[b140:v984, b147:v1079], kind=I64 } -> x12 + v1064 Phi { incoming=[b140:v1074, b147:v1080], kind=I64 } -> x6 + terminator Jmp(b136) block 142 start_pc=0 - v796 LoadLocal { off=-11, kind=I64 } -> x0 - v797 BinopI { op=eq, lhs=v750, rhs_imm=2 } -> x0 - terminator Bz { cond=v797, target=b145, fall=b143 } (exit_acc=v797) + v1071 LoadLocal { off=-6, kind=I64 } -> x0 + v1072 Load { addr=v988, disp=0, kind=I64 } -> x6 + v1073 Imm(0) -> x0 + terminator Jmp(b140) (exit_acc=v1072) block 143 start_pc=0 - v798 LoadLocal { off=-6, kind=I64 } -> x0 - v799 Load { addr=v748, disp=0, kind=I64 } -> [spill 0] - v800 Imm(0) -> x0 - terminator Jmp(b144) (exit_acc=v799) + v1065 LoadLocal { off=-11, kind=I64 } -> x0 + v1066 BinopI { op=eq, lhs=v990, rhs_imm=5 } -> x0 + terminator Bz { cond=v1066, target=b149, fall=b144 } (exit_acc=v1066) block 144 start_pc=0 - v801 Phi { incoming=[b143:v743, b147:v816], kind=I64 } -> x14 - v802 Phi { incoming=[b143:v744, b147:v817], kind=I64 } -> x12 - v803 Phi { incoming=[b143:v799, b147:v818], kind=I64 } -> [spill 0] - terminator Jmp(b141) + v1077 LoadLocal { off=-9, kind=I64 } -> x0 + terminator Bz { cond=v1077, target=b148, fall=b145 } (exit_acc=v1077) block 145 start_pc=0 - v804 LoadLocal { off=-11, kind=I64 } -> x0 - v805 BinopI { op=eq, lhs=v750, rhs_imm=3 } -> x0 - terminator Bz { cond=v805, target=b148, fall=b146 } (exit_acc=v805) + v1083 LoadLocal { off=-6, kind=I64 } -> x0 + v1084 Load { addr=v988, disp=0, kind=I64 } -> x6 + v1085 Imm(0) -> x0 + terminator Jmp(b146) (exit_acc=v1084) block 146 start_pc=0 - v806 LoadLocal { off=-7, kind=I64 } -> x0 - v807 BinopI { op=add, lhs=v744, rhs_imm=-8 } -> x12 - v808 Imm(0) -> x0 - v809 LoadLocal { off=-6, kind=I64 } -> x0 - v810 Imm(8) -> x0 - v811 BinopI { op=add, lhs=v748, rhs_imm=8 } -> x0 - v812 Store { addr=v807, disp=0, value=v811, kind=I64 } -> - - v813 LoadLocal { off=-6, kind=I64 } -> x0 - v814 Load { addr=v748, disp=0, kind=I64 } -> [spill 0] - v815 Imm(0) -> x0 - terminator Jmp(b147) (exit_acc=v814) + v1090 Phi { incoming=[b145:v1084, b148:v1088], kind=I64 } -> x6 + v1091 LoadLocal { off=-27, kind=I64 } -> x0 + v1092 Imm(0) -> x0 + terminator Jmp(b147) (exit_acc=v1090) block 147 start_pc=0 - v816 Phi { incoming=[b146:v743, b150:v822], kind=I64 } -> x14 - v817 Phi { incoming=[b146:v807, b150:v823], kind=I64 } -> x12 - v818 Phi { incoming=[b146:v814, b150:v824], kind=I64 } -> [spill 0] - terminator Jmp(b144) + v1078 Phi { incoming=[b146:v983, b151:v1107], kind=I64 } -> x13 + v1079 Phi { incoming=[b146:v984, b151:v1108], kind=I64 } -> x12 + v1080 Phi { incoming=[b146:v1090, b151:v1109], kind=I64 } -> x6 + terminator Jmp(b141) block 148 start_pc=0 - v819 LoadLocal { off=-11, kind=I64 } -> x0 - v820 BinopI { op=eq, lhs=v750, rhs_imm=4 } -> x0 - terminator Bz { cond=v820, target=b151, fall=b149 } (exit_acc=v820) + v1086 LoadLocal { off=-6, kind=I64 } -> x0 + v1087 Imm(8) -> x0 + v1088 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1089 Imm(0) -> x0 + terminator Jmp(b146) (exit_acc=v1088) block 149 start_pc=0 - v821 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v821, target=b153, fall=b152 } (exit_acc=v821) + v1081 LoadLocal { off=-11, kind=I64 } -> x0 + v1082 BinopI { op=eq, lhs=v990, rhs_imm=6 } -> x0 + terminator Bz { cond=v1082, target=b152, fall=b150 } (exit_acc=v1082) block 150 start_pc=0 - v822 Phi { incoming=[b154:v743, b156:v838], kind=I64 } -> x14 - v823 Phi { incoming=[b154:v744, b156:v839], kind=I64 } -> x12 - v824 Phi { incoming=[b154:v834, b156:v840], kind=I64 } -> [spill 0] - terminator Jmp(b147) + v1093 LoadLocal { off=-7, kind=I64 } -> x0 + v1094 BinopI { op=add, lhs=v984, rhs_imm=-8 } -> x0 + v1095 Imm(0) -> x1 + v1096 LoadLocal { off=-8, kind=I64 } -> x1 + v1097 Store { addr=v1094, disp=0, value=v983, kind=I64 } -> - + v1098 LoadLocal { off=-7, kind=I64 } -> x1 + v1099 Imm(0) -> x1 + v1100 LoadLocal { off=-6, kind=I64 } -> x1 + v1101 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1102 Imm(0) -> x1 + v1103 Load { addr=v988, disp=0, kind=I64 } -> x1 + v1104 BinopI { op=shl, lhs=v1103, rhs_imm=3 } -> x1 + v1105 Binop { op=sub, lhs=v1094, rhs=v1104 } -> x12 + v1106 Imm(0) -> x1 + terminator Jmp(b151) (exit_acc=v1105) block 151 start_pc=0 - v825 LoadLocal { off=-11, kind=I64 } -> x0 - v826 BinopI { op=eq, lhs=v750, rhs_imm=5 } -> x0 - terminator Bz { cond=v826, target=b157, fall=b155 } (exit_acc=v826) + v1107 Phi { incoming=[b150:v1094, b154:v1120], kind=I64 } -> x13 + v1108 Phi { incoming=[b150:v1105, b154:v1121], kind=I64 } -> x12 + v1109 Phi { incoming=[b150:v1101, b154:v1122], kind=I64 } -> x6 + terminator Jmp(b147) block 152 start_pc=0 - v827 LoadLocal { off=-6, kind=I64 } -> x0 - v828 Imm(8) -> x0 - v829 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v830 Imm(0) -> x0 - terminator Jmp(b154) (exit_acc=v829) + v1110 LoadLocal { off=-11, kind=I64 } -> x0 + v1111 BinopI { op=eq, lhs=v990, rhs_imm=7 } -> x0 + terminator Bz { cond=v1111, target=b155, fall=b153 } (exit_acc=v1111) block 153 start_pc=0 - v831 LoadLocal { off=-6, kind=I64 } -> x0 - v832 Load { addr=v748, disp=0, kind=I64 } -> [spill 0] - v833 Imm(0) -> x0 - terminator Jmp(b154) (exit_acc=v832) + v1112 LoadLocal { off=-7, kind=I64 } -> x0 + v1113 LoadLocal { off=-6, kind=I64 } -> x0 + v1114 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x6 + v1115 Imm(0) -> x0 + v1116 Load { addr=v988, disp=0, kind=I64 } -> x0 + v1117 BinopI { op=shl, lhs=v1116, rhs_imm=3 } -> x0 + v1118 Binop { op=add, lhs=v984, rhs=v1117 } -> x12 + v1119 Imm(0) -> x0 + terminator Jmp(b154) (exit_acc=v1118) block 154 start_pc=0 - v834 Phi { incoming=[b152:v829, b153:v832], kind=I64 } -> [spill 0] - v835 LoadLocal { off=-26, kind=I64 } -> x0 - v836 Imm(0) -> x0 - terminator Jmp(b150) (exit_acc=v834) + v1120 Phi { incoming=[b153:v983, b157:v1137], kind=I64 } -> x13 + v1121 Phi { incoming=[b153:v1118, b157:v1138], kind=I64 } -> x12 + v1122 Phi { incoming=[b153:v1114, b157:v1139], kind=I64 } -> x6 + terminator Jmp(b151) block 155 start_pc=0 - v837 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v837, target=b159, fall=b158 } (exit_acc=v837) + v1123 LoadLocal { off=-11, kind=I64 } -> x0 + v1124 BinopI { op=eq, lhs=v990, rhs_imm=8 } -> x0 + terminator Bz { cond=v1124, target=b158, fall=b156 } (exit_acc=v1124) block 156 start_pc=0 - v838 Phi { incoming=[b160:v743, b162:v867], kind=I64 } -> x14 - v839 Phi { incoming=[b160:v744, b162:v868], kind=I64 } -> x12 - v840 Phi { incoming=[b160:v850, b162:v869], kind=I64 } -> [spill 0] - terminator Jmp(b150) + v1125 LoadLocal { off=-8, kind=I64 } -> x0 + v1126 Imm(0) -> x0 + v1127 LoadLocal { off=-7, kind=I64 } -> x0 + v1128 BinopI { op=add, lhs=v983, rhs_imm=8 } -> x0 + v1129 Imm(0) -> x1 + v1130 Load { addr=v983, disp=0, kind=I64 } -> x13 + v1131 Imm(0) -> x1 + v1132 LoadLocal { off=-7, kind=I64 } -> x1 + v1133 BinopI { op=add, lhs=v1128, rhs_imm=8 } -> x12 + v1134 Imm(0) -> x1 + v1135 Load { addr=v1128, disp=0, kind=I64 } -> x6 + v1136 Imm(0) -> x0 + terminator Jmp(b157) (exit_acc=v1135) block 157 start_pc=0 - v841 LoadLocal { off=-11, kind=I64 } -> x0 - v842 BinopI { op=eq, lhs=v750, rhs_imm=6 } -> x0 - terminator Bz { cond=v842, target=b163, fall=b161 } (exit_acc=v842) + v1137 Phi { incoming=[b156:v1130, b160:v983], kind=I64 } -> x13 + v1138 Phi { incoming=[b156:v1133, b160:v1145], kind=I64 } -> x12 + v1139 Phi { incoming=[b156:v1135, b160:v988], kind=I64 } -> x6 + terminator Jmp(b154) block 158 start_pc=0 - v843 LoadLocal { off=-6, kind=I64 } -> x0 - v844 Load { addr=v748, disp=0, kind=I64 } -> [spill 0] - v845 Imm(0) -> x0 - terminator Jmp(b160) (exit_acc=v844) + v1140 LoadLocal { off=-11, kind=I64 } -> x0 + v1141 BinopI { op=eq, lhs=v990, rhs_imm=9 } -> x0 + terminator Bz { cond=v1141, target=b161, fall=b159 } (exit_acc=v1141) block 159 start_pc=0 - v846 LoadLocal { off=-6, kind=I64 } -> x0 - v847 Imm(8) -> x0 - v848 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v849 Imm(0) -> x0 - terminator Jmp(b160) (exit_acc=v848) + v1142 LoadLocal { off=-9, kind=I64 } -> x0 + v1143 Load { addr=v1142, disp=0, kind=I64 } -> x0 + v1144 StoreLocal { off=-9, value=v1143, kind=I64 } -> - + terminator Jmp(b160) (exit_acc=v1144) block 160 start_pc=0 - v850 Phi { incoming=[b158:v844, b159:v848], kind=I64 } -> [spill 0] - v851 LoadLocal { off=-27, kind=I64 } -> x0 - v852 Imm(0) -> x0 - terminator Jmp(b156) (exit_acc=v850) + v1145 Phi { incoming=[b159:v984, b163:v1151], kind=I64 } -> x12 + terminator Jmp(b157) block 161 start_pc=0 - v853 LoadLocal { off=-7, kind=I64 } -> x0 - v854 BinopI { op=add, lhs=v744, rhs_imm=-8 } -> x0 - v855 Imm(0) -> x1 - v856 LoadLocal { off=-8, kind=I64 } -> x1 - v857 Store { addr=v854, disp=0, value=v743, kind=I64 } -> - - v858 LoadLocal { off=-7, kind=I64 } -> x1 - v859 Imm(0) -> x1 - v860 LoadLocal { off=-6, kind=I64 } -> x1 - v861 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v862 Imm(0) -> x1 - v863 Load { addr=v748, disp=0, kind=I64 } -> x1 - v864 BinopI { op=shl, lhs=v863, rhs_imm=3 } -> x1 - v865 Binop { op=sub, lhs=v854, rhs=v864 } -> x12 - v866 Imm(0) -> x1 - terminator Jmp(b162) (exit_acc=v865) + v1146 LoadLocal { off=-11, kind=I64 } -> x0 + v1147 BinopI { op=eq, lhs=v990, rhs_imm=10 } -> x0 + terminator Bz { cond=v1147, target=b164, fall=b162 } (exit_acc=v1147) block 162 start_pc=0 - v867 Phi { incoming=[b161:v854, b165:v880], kind=I64 } -> x14 - v868 Phi { incoming=[b161:v865, b165:v881], kind=I64 } -> x12 - v869 Phi { incoming=[b161:v861, b165:v882], kind=I64 } -> [spill 0] - terminator Jmp(b156) + v1148 LoadLocal { off=-9, kind=I64 } -> x0 + v1149 Load { addr=v1148, disp=0, kind=I8 } -> x0 + v1150 StoreLocal { off=-9, value=v1149, kind=I64 } -> - + terminator Jmp(b163) (exit_acc=v1150) block 163 start_pc=0 - v870 LoadLocal { off=-11, kind=I64 } -> x0 - v871 BinopI { op=eq, lhs=v750, rhs_imm=7 } -> x0 - terminator Bz { cond=v871, target=b166, fall=b164 } (exit_acc=v871) + v1151 Phi { incoming=[b162:v984, b166:v1160], kind=I64 } -> x12 + terminator Jmp(b160) block 164 start_pc=0 - v872 LoadLocal { off=-7, kind=I64 } -> x0 - v873 LoadLocal { off=-6, kind=I64 } -> x0 - v874 BinopI { op=add, lhs=v748, rhs_imm=8 } -> [spill 0] - v875 Imm(0) -> x0 - v876 Load { addr=v748, disp=0, kind=I64 } -> x0 - v877 BinopI { op=shl, lhs=v876, rhs_imm=3 } -> x0 - v878 Binop { op=add, lhs=v744, rhs=v877 } -> x12 - v879 Imm(0) -> x0 - terminator Jmp(b165) (exit_acc=v878) + v1152 LoadLocal { off=-11, kind=I64 } -> x0 + v1153 BinopI { op=eq, lhs=v990, rhs_imm=11 } -> x0 + terminator Bz { cond=v1153, target=b167, fall=b165 } (exit_acc=v1153) block 165 start_pc=0 - v880 Phi { incoming=[b164:v743, b168:v897], kind=I64 } -> x14 - v881 Phi { incoming=[b164:v878, b168:v898], kind=I64 } -> x12 - v882 Phi { incoming=[b164:v874, b168:v899], kind=I64 } -> [spill 0] - terminator Jmp(b162) + v1154 LoadLocal { off=-7, kind=I64 } -> x0 + v1155 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1156 Imm(0) -> x1 + v1157 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1158 LoadLocal { off=-9, kind=I64 } -> x2 + v1159 Store { addr=v1157, disp=0, value=v1158, kind=I64 } -> - + terminator Jmp(b166) (exit_acc=v1159) block 166 start_pc=0 - v883 LoadLocal { off=-11, kind=I64 } -> x0 - v884 BinopI { op=eq, lhs=v750, rhs_imm=8 } -> x0 - terminator Bz { cond=v884, target=b169, fall=b167 } (exit_acc=v884) + v1160 Phi { incoming=[b165:v1155, b169:v1172], kind=I64 } -> x12 + terminator Jmp(b163) block 167 start_pc=0 - v885 LoadLocal { off=-8, kind=I64 } -> x0 - v886 Imm(0) -> x0 - v887 LoadLocal { off=-7, kind=I64 } -> x0 - v888 BinopI { op=add, lhs=v743, rhs_imm=8 } -> x0 - v889 Imm(0) -> x1 - v890 Load { addr=v743, disp=0, kind=I64 } -> x14 - v891 Imm(0) -> x1 - v892 LoadLocal { off=-7, kind=I64 } -> x1 - v893 BinopI { op=add, lhs=v888, rhs_imm=8 } -> x12 - v894 Imm(0) -> x1 - v895 Load { addr=v888, disp=0, kind=I64 } -> [spill 0] - v896 Imm(0) -> x0 - terminator Jmp(b168) (exit_acc=v895) + v1161 LoadLocal { off=-11, kind=I64 } -> x0 + v1162 BinopI { op=eq, lhs=v990, rhs_imm=12 } -> x0 + terminator Bz { cond=v1162, target=b170, fall=b168 } (exit_acc=v1162) block 168 start_pc=0 - v897 Phi { incoming=[b167:v890, b171:v743], kind=I64 } -> x14 - v898 Phi { incoming=[b167:v893, b171:v905], kind=I64 } -> x12 - v899 Phi { incoming=[b167:v895, b171:v748], kind=I64 } -> [spill 0] - terminator Jmp(b165) + v1163 LoadLocal { off=-7, kind=I64 } -> x0 + v1164 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1165 Imm(0) -> x1 + v1166 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1167 LoadLocal { off=-9, kind=I64 } -> x2 + v1168 Store { addr=v1166, disp=0, value=v1167, kind=I8 } -> - + v1169 BinopI { op=shl, lhs=v1167, rhs_imm=56 } -> x1 + v1170 Extend { value=v1167, kind=I8 } -> x1 + v1171 StoreLocal { off=-9, value=v1170, kind=I64 } -> - + terminator Jmp(b169) (exit_acc=v1171) block 169 start_pc=0 - v900 LoadLocal { off=-11, kind=I64 } -> x0 - v901 BinopI { op=eq, lhs=v750, rhs_imm=9 } -> x0 - terminator Bz { cond=v901, target=b172, fall=b170 } (exit_acc=v901) + v1172 Phi { incoming=[b168:v1164, b172:v1180], kind=I64 } -> x12 + terminator Jmp(b166) block 170 start_pc=0 - v902 LoadLocal { off=-9, kind=I64 } -> x0 - v903 Load { addr=v902, disp=0, kind=I64 } -> x0 - v904 StoreLocal { off=-9, value=v903, kind=I64 } -> - - terminator Jmp(b171) (exit_acc=v904) + v1173 LoadLocal { off=-11, kind=I64 } -> x0 + v1174 BinopI { op=eq, lhs=v990, rhs_imm=13 } -> x0 + terminator Bz { cond=v1174, target=b173, fall=b171 } (exit_acc=v1174) block 171 start_pc=0 - v905 Phi { incoming=[b170:v744, b174:v911], kind=I64 } -> x12 - terminator Jmp(b168) + v1175 LoadLocal { off=-7, kind=I64 } -> x0 + v1176 BinopI { op=add, lhs=v984, rhs_imm=-8 } -> x12 + v1177 Imm(0) -> x0 + v1178 LoadLocal { off=-9, kind=I64 } -> x0 + v1179 Store { addr=v1176, disp=0, value=v1178, kind=I64 } -> - + terminator Jmp(b172) (exit_acc=v1179) block 172 start_pc=0 - v906 LoadLocal { off=-11, kind=I64 } -> x0 - v907 BinopI { op=eq, lhs=v750, rhs_imm=10 } -> x0 - terminator Bz { cond=v907, target=b175, fall=b173 } (exit_acc=v907) + v1180 Phi { incoming=[b171:v1176, b175:v1190], kind=I64 } -> x12 + terminator Jmp(b169) block 173 start_pc=0 - v908 LoadLocal { off=-9, kind=I64 } -> x0 - v909 Load { addr=v908, disp=0, kind=I8 } -> x0 - v910 StoreLocal { off=-9, value=v909, kind=I64 } -> - - terminator Jmp(b174) (exit_acc=v910) + v1181 LoadLocal { off=-11, kind=I64 } -> x0 + v1182 BinopI { op=eq, lhs=v990, rhs_imm=14 } -> x0 + terminator Bz { cond=v1182, target=b176, fall=b174 } (exit_acc=v1182) block 174 start_pc=0 - v911 Phi { incoming=[b173:v744, b177:v920], kind=I64 } -> x12 - terminator Jmp(b171) + v1183 LoadLocal { off=-7, kind=I64 } -> x0 + v1184 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1185 Imm(0) -> x1 + v1186 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1187 LoadLocal { off=-9, kind=I64 } -> x2 + v1188 Binop { op=or, lhs=v1186, rhs=v1187 } -> x1 + v1189 StoreLocal { off=-9, value=v1188, kind=I64 } -> - + terminator Jmp(b175) (exit_acc=v1189) block 175 start_pc=0 - v912 LoadLocal { off=-11, kind=I64 } -> x0 - v913 BinopI { op=eq, lhs=v750, rhs_imm=11 } -> x0 - terminator Bz { cond=v913, target=b178, fall=b176 } (exit_acc=v913) + v1190 Phi { incoming=[b174:v1184, b178:v1200], kind=I64 } -> x12 + terminator Jmp(b172) block 176 start_pc=0 - v914 LoadLocal { off=-7, kind=I64 } -> x0 - v915 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v916 Imm(0) -> x1 - v917 Load { addr=v744, disp=0, kind=I64 } -> x1 - v918 LoadLocal { off=-9, kind=I64 } -> x2 - v919 Store { addr=v917, disp=0, value=v918, kind=I64 } -> - - terminator Jmp(b177) (exit_acc=v919) + v1191 LoadLocal { off=-11, kind=I64 } -> x0 + v1192 BinopI { op=eq, lhs=v990, rhs_imm=15 } -> x0 + terminator Bz { cond=v1192, target=b179, fall=b177 } (exit_acc=v1192) block 177 start_pc=0 - v920 Phi { incoming=[b176:v915, b180:v932], kind=I64 } -> x12 - terminator Jmp(b174) + v1193 LoadLocal { off=-7, kind=I64 } -> x0 + v1194 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1195 Imm(0) -> x1 + v1196 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1197 LoadLocal { off=-9, kind=I64 } -> x2 + v1198 Binop { op=xor, lhs=v1196, rhs=v1197 } -> x1 + v1199 StoreLocal { off=-9, value=v1198, kind=I64 } -> - + terminator Jmp(b178) (exit_acc=v1199) block 178 start_pc=0 - v921 LoadLocal { off=-11, kind=I64 } -> x0 - v922 BinopI { op=eq, lhs=v750, rhs_imm=12 } -> x0 - terminator Bz { cond=v922, target=b181, fall=b179 } (exit_acc=v922) + v1200 Phi { incoming=[b177:v1194, b181:v1210], kind=I64 } -> x12 + terminator Jmp(b175) block 179 start_pc=0 - v923 LoadLocal { off=-7, kind=I64 } -> x0 - v924 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v925 Imm(0) -> x1 - v926 Load { addr=v744, disp=0, kind=I64 } -> x1 - v927 LoadLocal { off=-9, kind=I64 } -> x2 - v928 Store { addr=v926, disp=0, value=v927, kind=I8 } -> - - v929 BinopI { op=shl, lhs=v927, rhs_imm=56 } -> x1 - v930 Extend { value=v927, kind=I8 } -> x1 - v931 StoreLocal { off=-9, value=v930, kind=I64 } -> - - terminator Jmp(b180) (exit_acc=v931) + v1201 LoadLocal { off=-11, kind=I64 } -> x0 + v1202 BinopI { op=eq, lhs=v990, rhs_imm=16 } -> x0 + terminator Bz { cond=v1202, target=b182, fall=b180 } (exit_acc=v1202) block 180 start_pc=0 - v932 Phi { incoming=[b179:v924, b183:v940], kind=I64 } -> x12 - terminator Jmp(b177) + v1203 LoadLocal { off=-7, kind=I64 } -> x0 + v1204 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1205 Imm(0) -> x1 + v1206 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1207 LoadLocal { off=-9, kind=I64 } -> x2 + v1208 Binop { op=and, lhs=v1206, rhs=v1207 } -> x1 + v1209 StoreLocal { off=-9, value=v1208, kind=I64 } -> - + terminator Jmp(b181) (exit_acc=v1209) block 181 start_pc=0 - v933 LoadLocal { off=-11, kind=I64 } -> x0 - v934 BinopI { op=eq, lhs=v750, rhs_imm=13 } -> x0 - terminator Bz { cond=v934, target=b184, fall=b182 } (exit_acc=v934) + v1210 Phi { incoming=[b180:v1204, b184:v1220], kind=I64 } -> x12 + terminator Jmp(b178) block 182 start_pc=0 - v935 LoadLocal { off=-7, kind=I64 } -> x0 - v936 BinopI { op=add, lhs=v744, rhs_imm=-8 } -> x12 - v937 Imm(0) -> x0 - v938 LoadLocal { off=-9, kind=I64 } -> x0 - v939 Store { addr=v936, disp=0, value=v938, kind=I64 } -> - - terminator Jmp(b183) (exit_acc=v939) + v1211 LoadLocal { off=-11, kind=I64 } -> x0 + v1212 BinopI { op=eq, lhs=v990, rhs_imm=17 } -> x0 + terminator Bz { cond=v1212, target=b185, fall=b183 } (exit_acc=v1212) block 183 start_pc=0 - v940 Phi { incoming=[b182:v936, b186:v950], kind=I64 } -> x12 - terminator Jmp(b180) + v1213 LoadLocal { off=-7, kind=I64 } -> x0 + v1214 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1215 Imm(0) -> x1 + v1216 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1217 LoadLocal { off=-9, kind=I64 } -> x2 + v1218 Binop { op=eq, lhs=v1216, rhs=v1217 } -> x1 + v1219 StoreLocal { off=-9, value=v1218, kind=I64 } -> - + terminator Jmp(b184) (exit_acc=v1219) block 184 start_pc=0 - v941 LoadLocal { off=-11, kind=I64 } -> x0 - v942 BinopI { op=eq, lhs=v750, rhs_imm=14 } -> x0 - terminator Bz { cond=v942, target=b187, fall=b185 } (exit_acc=v942) + v1220 Phi { incoming=[b183:v1214, b187:v1230], kind=I64 } -> x12 + terminator Jmp(b181) block 185 start_pc=0 - v943 LoadLocal { off=-7, kind=I64 } -> x0 - v944 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v945 Imm(0) -> x1 - v946 Load { addr=v744, disp=0, kind=I64 } -> x1 - v947 LoadLocal { off=-9, kind=I64 } -> x2 - v948 Binop { op=or, lhs=v946, rhs=v947 } -> x1 - v949 StoreLocal { off=-9, value=v948, kind=I64 } -> - - terminator Jmp(b186) (exit_acc=v949) + v1221 LoadLocal { off=-11, kind=I64 } -> x0 + v1222 BinopI { op=eq, lhs=v990, rhs_imm=18 } -> x0 + terminator Bz { cond=v1222, target=b188, fall=b186 } (exit_acc=v1222) block 186 start_pc=0 - v950 Phi { incoming=[b185:v944, b189:v960], kind=I64 } -> x12 - terminator Jmp(b183) + v1223 LoadLocal { off=-7, kind=I64 } -> x0 + v1224 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1225 Imm(0) -> x1 + v1226 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1227 LoadLocal { off=-9, kind=I64 } -> x2 + v1228 Binop { op=ne, lhs=v1226, rhs=v1227 } -> x1 + v1229 StoreLocal { off=-9, value=v1228, kind=I64 } -> - + terminator Jmp(b187) (exit_acc=v1229) block 187 start_pc=0 - v951 LoadLocal { off=-11, kind=I64 } -> x0 - v952 BinopI { op=eq, lhs=v750, rhs_imm=15 } -> x0 - terminator Bz { cond=v952, target=b190, fall=b188 } (exit_acc=v952) + v1230 Phi { incoming=[b186:v1224, b190:v1240], kind=I64 } -> x12 + terminator Jmp(b184) block 188 start_pc=0 - v953 LoadLocal { off=-7, kind=I64 } -> x0 - v954 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v955 Imm(0) -> x1 - v956 Load { addr=v744, disp=0, kind=I64 } -> x1 - v957 LoadLocal { off=-9, kind=I64 } -> x2 - v958 Binop { op=xor, lhs=v956, rhs=v957 } -> x1 - v959 StoreLocal { off=-9, value=v958, kind=I64 } -> - - terminator Jmp(b189) (exit_acc=v959) + v1231 LoadLocal { off=-11, kind=I64 } -> x0 + v1232 BinopI { op=eq, lhs=v990, rhs_imm=19 } -> x0 + terminator Bz { cond=v1232, target=b191, fall=b189 } (exit_acc=v1232) block 189 start_pc=0 - v960 Phi { incoming=[b188:v954, b192:v970], kind=I64 } -> x12 - terminator Jmp(b186) + v1233 LoadLocal { off=-7, kind=I64 } -> x0 + v1234 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1235 Imm(0) -> x1 + v1236 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1237 LoadLocal { off=-9, kind=I64 } -> x2 + v1238 Binop { op=lt, lhs=v1236, rhs=v1237 } -> x1 + v1239 StoreLocal { off=-9, value=v1238, kind=I64 } -> - + terminator Jmp(b190) (exit_acc=v1239) block 190 start_pc=0 - v961 LoadLocal { off=-11, kind=I64 } -> x0 - v962 BinopI { op=eq, lhs=v750, rhs_imm=16 } -> x0 - terminator Bz { cond=v962, target=b193, fall=b191 } (exit_acc=v962) + v1240 Phi { incoming=[b189:v1234, b193:v1250], kind=I64 } -> x12 + terminator Jmp(b187) block 191 start_pc=0 - v963 LoadLocal { off=-7, kind=I64 } -> x0 - v964 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v965 Imm(0) -> x1 - v966 Load { addr=v744, disp=0, kind=I64 } -> x1 - v967 LoadLocal { off=-9, kind=I64 } -> x2 - v968 Binop { op=and, lhs=v966, rhs=v967 } -> x1 - v969 StoreLocal { off=-9, value=v968, kind=I64 } -> - - terminator Jmp(b192) (exit_acc=v969) + v1241 LoadLocal { off=-11, kind=I64 } -> x0 + v1242 BinopI { op=eq, lhs=v990, rhs_imm=20 } -> x0 + terminator Bz { cond=v1242, target=b194, fall=b192 } (exit_acc=v1242) block 192 start_pc=0 - v970 Phi { incoming=[b191:v964, b195:v980], kind=I64 } -> x12 - terminator Jmp(b189) + v1243 LoadLocal { off=-7, kind=I64 } -> x0 + v1244 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1245 Imm(0) -> x1 + v1246 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1247 LoadLocal { off=-9, kind=I64 } -> x2 + v1248 Binop { op=gt, lhs=v1246, rhs=v1247 } -> x1 + v1249 StoreLocal { off=-9, value=v1248, kind=I64 } -> - + terminator Jmp(b193) (exit_acc=v1249) block 193 start_pc=0 - v971 LoadLocal { off=-11, kind=I64 } -> x0 - v972 BinopI { op=eq, lhs=v750, rhs_imm=17 } -> x0 - terminator Bz { cond=v972, target=b196, fall=b194 } (exit_acc=v972) + v1250 Phi { incoming=[b192:v1244, b196:v1260], kind=I64 } -> x12 + terminator Jmp(b190) block 194 start_pc=0 - v973 LoadLocal { off=-7, kind=I64 } -> x0 - v974 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v975 Imm(0) -> x1 - v976 Load { addr=v744, disp=0, kind=I64 } -> x1 - v977 LoadLocal { off=-9, kind=I64 } -> x2 - v978 Binop { op=eq, lhs=v976, rhs=v977 } -> x1 - v979 StoreLocal { off=-9, value=v978, kind=I64 } -> - - terminator Jmp(b195) (exit_acc=v979) + v1251 LoadLocal { off=-11, kind=I64 } -> x0 + v1252 BinopI { op=eq, lhs=v990, rhs_imm=21 } -> x0 + terminator Bz { cond=v1252, target=b197, fall=b195 } (exit_acc=v1252) block 195 start_pc=0 - v980 Phi { incoming=[b194:v974, b198:v990], kind=I64 } -> x12 - terminator Jmp(b192) + v1253 LoadLocal { off=-7, kind=I64 } -> x0 + v1254 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1255 Imm(0) -> x1 + v1256 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1257 LoadLocal { off=-9, kind=I64 } -> x2 + v1258 Binop { op=le, lhs=v1256, rhs=v1257 } -> x1 + v1259 StoreLocal { off=-9, value=v1258, kind=I64 } -> - + terminator Jmp(b196) (exit_acc=v1259) block 196 start_pc=0 - v981 LoadLocal { off=-11, kind=I64 } -> x0 - v982 BinopI { op=eq, lhs=v750, rhs_imm=18 } -> x0 - terminator Bz { cond=v982, target=b199, fall=b197 } (exit_acc=v982) + v1260 Phi { incoming=[b195:v1254, b199:v1270], kind=I64 } -> x12 + terminator Jmp(b193) block 197 start_pc=0 - v983 LoadLocal { off=-7, kind=I64 } -> x0 - v984 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v985 Imm(0) -> x1 - v986 Load { addr=v744, disp=0, kind=I64 } -> x1 - v987 LoadLocal { off=-9, kind=I64 } -> x2 - v988 Binop { op=ne, lhs=v986, rhs=v987 } -> x1 - v989 StoreLocal { off=-9, value=v988, kind=I64 } -> - - terminator Jmp(b198) (exit_acc=v989) + v1261 LoadLocal { off=-11, kind=I64 } -> x0 + v1262 BinopI { op=eq, lhs=v990, rhs_imm=22 } -> x0 + terminator Bz { cond=v1262, target=b200, fall=b198 } (exit_acc=v1262) block 198 start_pc=0 - v990 Phi { incoming=[b197:v984, b201:v1000], kind=I64 } -> x12 - terminator Jmp(b195) + v1263 LoadLocal { off=-7, kind=I64 } -> x0 + v1264 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1265 Imm(0) -> x1 + v1266 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1267 LoadLocal { off=-9, kind=I64 } -> x2 + v1268 Binop { op=ge, lhs=v1266, rhs=v1267 } -> x1 + v1269 StoreLocal { off=-9, value=v1268, kind=I64 } -> - + terminator Jmp(b199) (exit_acc=v1269) block 199 start_pc=0 - v991 LoadLocal { off=-11, kind=I64 } -> x0 - v992 BinopI { op=eq, lhs=v750, rhs_imm=19 } -> x0 - terminator Bz { cond=v992, target=b202, fall=b200 } (exit_acc=v992) + v1270 Phi { incoming=[b198:v1264, b202:v1280], kind=I64 } -> x12 + terminator Jmp(b196) block 200 start_pc=0 - v993 LoadLocal { off=-7, kind=I64 } -> x0 - v994 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v995 Imm(0) -> x1 - v996 Load { addr=v744, disp=0, kind=I64 } -> x1 - v997 LoadLocal { off=-9, kind=I64 } -> x2 - v998 Binop { op=lt, lhs=v996, rhs=v997 } -> x1 - v999 StoreLocal { off=-9, value=v998, kind=I64 } -> - - terminator Jmp(b201) (exit_acc=v999) + v1271 LoadLocal { off=-11, kind=I64 } -> x0 + v1272 BinopI { op=eq, lhs=v990, rhs_imm=23 } -> x0 + terminator Bz { cond=v1272, target=b203, fall=b201 } (exit_acc=v1272) block 201 start_pc=0 - v1000 Phi { incoming=[b200:v994, b204:v1010], kind=I64 } -> x12 - terminator Jmp(b198) + v1273 LoadLocal { off=-7, kind=I64 } -> x0 + v1274 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1275 Imm(0) -> x1 + v1276 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1277 LoadLocal { off=-9, kind=I64 } -> x2 + v1278 Binop { op=shl, lhs=v1276, rhs=v1277 } -> x1 + v1279 StoreLocal { off=-9, value=v1278, kind=I64 } -> - + terminator Jmp(b202) (exit_acc=v1279) block 202 start_pc=0 - v1001 LoadLocal { off=-11, kind=I64 } -> x0 - v1002 BinopI { op=eq, lhs=v750, rhs_imm=20 } -> x0 - terminator Bz { cond=v1002, target=b205, fall=b203 } (exit_acc=v1002) + v1280 Phi { incoming=[b201:v1274, b205:v1290], kind=I64 } -> x12 + terminator Jmp(b199) block 203 start_pc=0 - v1003 LoadLocal { off=-7, kind=I64 } -> x0 - v1004 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1005 Imm(0) -> x1 - v1006 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1007 LoadLocal { off=-9, kind=I64 } -> x2 - v1008 Binop { op=gt, lhs=v1006, rhs=v1007 } -> x1 - v1009 StoreLocal { off=-9, value=v1008, kind=I64 } -> - - terminator Jmp(b204) (exit_acc=v1009) + v1281 LoadLocal { off=-11, kind=I64 } -> x0 + v1282 BinopI { op=eq, lhs=v990, rhs_imm=24 } -> x0 + terminator Bz { cond=v1282, target=b206, fall=b204 } (exit_acc=v1282) block 204 start_pc=0 - v1010 Phi { incoming=[b203:v1004, b207:v1020], kind=I64 } -> x12 - terminator Jmp(b201) + v1283 LoadLocal { off=-7, kind=I64 } -> x0 + v1284 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1285 Imm(0) -> x1 + v1286 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1287 LoadLocal { off=-9, kind=I64 } -> x2 + v1288 Binop { op=shr, lhs=v1286, rhs=v1287 } -> x1 + v1289 StoreLocal { off=-9, value=v1288, kind=I64 } -> - + terminator Jmp(b205) (exit_acc=v1289) block 205 start_pc=0 - v1011 LoadLocal { off=-11, kind=I64 } -> x0 - v1012 BinopI { op=eq, lhs=v750, rhs_imm=21 } -> x0 - terminator Bz { cond=v1012, target=b208, fall=b206 } (exit_acc=v1012) + v1290 Phi { incoming=[b204:v1284, b208:v1300], kind=I64 } -> x12 + terminator Jmp(b202) block 206 start_pc=0 - v1013 LoadLocal { off=-7, kind=I64 } -> x0 - v1014 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1015 Imm(0) -> x1 - v1016 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1017 LoadLocal { off=-9, kind=I64 } -> x2 - v1018 Binop { op=le, lhs=v1016, rhs=v1017 } -> x1 - v1019 StoreLocal { off=-9, value=v1018, kind=I64 } -> - - terminator Jmp(b207) (exit_acc=v1019) + v1291 LoadLocal { off=-11, kind=I64 } -> x0 + v1292 BinopI { op=eq, lhs=v990, rhs_imm=25 } -> x0 + terminator Bz { cond=v1292, target=b209, fall=b207 } (exit_acc=v1292) block 207 start_pc=0 - v1020 Phi { incoming=[b206:v1014, b210:v1030], kind=I64 } -> x12 - terminator Jmp(b204) + v1293 LoadLocal { off=-7, kind=I64 } -> x0 + v1294 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1295 Imm(0) -> x1 + v1296 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1297 LoadLocal { off=-9, kind=I64 } -> x2 + v1298 Binop { op=add, lhs=v1296, rhs=v1297 } -> x1 + v1299 StoreLocal { off=-9, value=v1298, kind=I64 } -> - + terminator Jmp(b208) (exit_acc=v1299) block 208 start_pc=0 - v1021 LoadLocal { off=-11, kind=I64 } -> x0 - v1022 BinopI { op=eq, lhs=v750, rhs_imm=22 } -> x0 - terminator Bz { cond=v1022, target=b211, fall=b209 } (exit_acc=v1022) + v1300 Phi { incoming=[b207:v1294, b211:v1310], kind=I64 } -> x12 + terminator Jmp(b205) block 209 start_pc=0 - v1023 LoadLocal { off=-7, kind=I64 } -> x0 - v1024 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1025 Imm(0) -> x1 - v1026 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1027 LoadLocal { off=-9, kind=I64 } -> x2 - v1028 Binop { op=ge, lhs=v1026, rhs=v1027 } -> x1 - v1029 StoreLocal { off=-9, value=v1028, kind=I64 } -> - - terminator Jmp(b210) (exit_acc=v1029) + v1301 LoadLocal { off=-11, kind=I64 } -> x0 + v1302 BinopI { op=eq, lhs=v990, rhs_imm=26 } -> x0 + terminator Bz { cond=v1302, target=b212, fall=b210 } (exit_acc=v1302) block 210 start_pc=0 - v1030 Phi { incoming=[b209:v1024, b213:v1040], kind=I64 } -> x12 - terminator Jmp(b207) + v1303 LoadLocal { off=-7, kind=I64 } -> x0 + v1304 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1305 Imm(0) -> x1 + v1306 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1307 LoadLocal { off=-9, kind=I64 } -> x2 + v1308 Binop { op=sub, lhs=v1306, rhs=v1307 } -> x1 + v1309 StoreLocal { off=-9, value=v1308, kind=I64 } -> - + terminator Jmp(b211) (exit_acc=v1309) block 211 start_pc=0 - v1031 LoadLocal { off=-11, kind=I64 } -> x0 - v1032 BinopI { op=eq, lhs=v750, rhs_imm=23 } -> x0 - terminator Bz { cond=v1032, target=b214, fall=b212 } (exit_acc=v1032) + v1310 Phi { incoming=[b210:v1304, b214:v1320], kind=I64 } -> x12 + terminator Jmp(b208) block 212 start_pc=0 - v1033 LoadLocal { off=-7, kind=I64 } -> x0 - v1034 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1035 Imm(0) -> x1 - v1036 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1037 LoadLocal { off=-9, kind=I64 } -> x2 - v1038 Binop { op=shl, lhs=v1036, rhs=v1037 } -> x1 - v1039 StoreLocal { off=-9, value=v1038, kind=I64 } -> - - terminator Jmp(b213) (exit_acc=v1039) + v1311 LoadLocal { off=-11, kind=I64 } -> x0 + v1312 BinopI { op=eq, lhs=v990, rhs_imm=27 } -> x0 + terminator Bz { cond=v1312, target=b215, fall=b213 } (exit_acc=v1312) block 213 start_pc=0 - v1040 Phi { incoming=[b212:v1034, b216:v1050], kind=I64 } -> x12 - terminator Jmp(b210) + v1313 LoadLocal { off=-7, kind=I64 } -> x0 + v1314 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1315 Imm(0) -> x1 + v1316 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1317 LoadLocal { off=-9, kind=I64 } -> x2 + v1318 Binop { op=mul, lhs=v1316, rhs=v1317 } -> x1 + v1319 StoreLocal { off=-9, value=v1318, kind=I64 } -> - + terminator Jmp(b214) (exit_acc=v1319) block 214 start_pc=0 - v1041 LoadLocal { off=-11, kind=I64 } -> x0 - v1042 BinopI { op=eq, lhs=v750, rhs_imm=24 } -> x0 - terminator Bz { cond=v1042, target=b217, fall=b215 } (exit_acc=v1042) + v1320 Phi { incoming=[b213:v1314, b217:v1330], kind=I64 } -> x12 + terminator Jmp(b211) block 215 start_pc=0 - v1043 LoadLocal { off=-7, kind=I64 } -> x0 - v1044 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1045 Imm(0) -> x1 - v1046 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1047 LoadLocal { off=-9, kind=I64 } -> x2 - v1048 Binop { op=shr, lhs=v1046, rhs=v1047 } -> x1 - v1049 StoreLocal { off=-9, value=v1048, kind=I64 } -> - - terminator Jmp(b216) (exit_acc=v1049) + v1321 LoadLocal { off=-11, kind=I64 } -> x0 + v1322 BinopI { op=eq, lhs=v990, rhs_imm=28 } -> x0 + terminator Bz { cond=v1322, target=b218, fall=b216 } (exit_acc=v1322) block 216 start_pc=0 - v1050 Phi { incoming=[b215:v1044, b219:v1060], kind=I64 } -> x12 - terminator Jmp(b213) + v1323 LoadLocal { off=-7, kind=I64 } -> x0 + v1324 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1325 Imm(0) -> x1 + v1326 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1327 LoadLocal { off=-9, kind=I64 } -> x2 + v1328 Binop { op=div, lhs=v1326, rhs=v1327 } -> x1 + v1329 StoreLocal { off=-9, value=v1328, kind=I64 } -> - + terminator Jmp(b217) (exit_acc=v1329) block 217 start_pc=0 - v1051 LoadLocal { off=-11, kind=I64 } -> x0 - v1052 BinopI { op=eq, lhs=v750, rhs_imm=25 } -> x0 - terminator Bz { cond=v1052, target=b220, fall=b218 } (exit_acc=v1052) + v1330 Phi { incoming=[b216:v1324, b220:v1340], kind=I64 } -> x12 + terminator Jmp(b214) block 218 start_pc=0 - v1053 LoadLocal { off=-7, kind=I64 } -> x0 - v1054 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1055 Imm(0) -> x1 - v1056 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1057 LoadLocal { off=-9, kind=I64 } -> x2 - v1058 Binop { op=add, lhs=v1056, rhs=v1057 } -> x1 - v1059 StoreLocal { off=-9, value=v1058, kind=I64 } -> - - terminator Jmp(b219) (exit_acc=v1059) + v1331 LoadLocal { off=-11, kind=I64 } -> x0 + v1332 BinopI { op=eq, lhs=v990, rhs_imm=29 } -> x0 + terminator Bz { cond=v1332, target=b221, fall=b219 } (exit_acc=v1332) block 219 start_pc=0 - v1060 Phi { incoming=[b218:v1054, b222:v1070], kind=I64 } -> x12 - terminator Jmp(b216) + v1333 LoadLocal { off=-7, kind=I64 } -> x0 + v1334 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1335 Imm(0) -> x1 + v1336 Load { addr=v984, disp=0, kind=I64 } -> x1 + v1337 LoadLocal { off=-9, kind=I64 } -> x2 + v1338 Binop { op=mod, lhs=v1336, rhs=v1337 } -> x1 + v1339 StoreLocal { off=-9, value=v1338, kind=I64 } -> - + terminator Jmp(b220) (exit_acc=v1339) block 220 start_pc=0 - v1061 LoadLocal { off=-11, kind=I64 } -> x0 - v1062 BinopI { op=eq, lhs=v750, rhs_imm=26 } -> x0 - terminator Bz { cond=v1062, target=b223, fall=b221 } (exit_acc=v1062) + v1340 Phi { incoming=[b219:v1334, b223:v984], kind=I64 } -> x12 + terminator Jmp(b217) block 221 start_pc=0 - v1063 LoadLocal { off=-7, kind=I64 } -> x0 - v1064 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1065 Imm(0) -> x1 - v1066 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1067 LoadLocal { off=-9, kind=I64 } -> x2 - v1068 Binop { op=sub, lhs=v1066, rhs=v1067 } -> x1 - v1069 StoreLocal { off=-9, value=v1068, kind=I64 } -> - - terminator Jmp(b222) (exit_acc=v1069) + v1341 LoadLocal { off=-11, kind=I64 } -> x0 + v1342 BinopI { op=eq, lhs=v990, rhs_imm=30 } -> x0 + terminator Bz { cond=v1342, target=b224, fall=b222 } (exit_acc=v1342) block 222 start_pc=0 - v1070 Phi { incoming=[b221:v1064, b225:v1080], kind=I64 } -> x12 - terminator Jmp(b219) + v1343 LoadLocal { off=-7, kind=I64 } -> x0 + v1344 Imm(8) -> x0 + v1345 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1346 Load { addr=v984, disp=8, kind=I64 } -> x7 + v1347 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1348 BinopI { op=shl, lhs=v1347, rhs_imm=32 } -> x1 + v1349 Extend { value=v1347, kind=I32 } -> x6 + v1350 CallExt { binding_idx=144, args=[v1346, v1349], fp_arg_mask=0x0 } -> x0 + v1351 StoreLocal { off=-9, value=v1350, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1351) block 223 start_pc=0 - v1071 LoadLocal { off=-11, kind=I64 } -> x0 - v1072 BinopI { op=eq, lhs=v750, rhs_imm=27 } -> x0 - terminator Bz { cond=v1072, target=b226, fall=b224 } (exit_acc=v1072) + terminator Jmp(b220) block 224 start_pc=0 - v1073 LoadLocal { off=-7, kind=I64 } -> x0 - v1074 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1075 Imm(0) -> x1 - v1076 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1077 LoadLocal { off=-9, kind=I64 } -> x2 - v1078 Binop { op=mul, lhs=v1076, rhs=v1077 } -> x1 - v1079 StoreLocal { off=-9, value=v1078, kind=I64 } -> - - terminator Jmp(b225) (exit_acc=v1079) + v1352 LoadLocal { off=-11, kind=I64 } -> x0 + v1353 BinopI { op=eq, lhs=v990, rhs_imm=31 } -> x0 + terminator Bz { cond=v1353, target=b226, fall=b225 } (exit_acc=v1353) block 225 start_pc=0 - v1080 Phi { incoming=[b224:v1074, b228:v1090], kind=I64 } -> x12 - terminator Jmp(b222) + v1354 LoadLocal { off=-7, kind=I64 } -> x0 + v1355 Imm(16) -> x0 + v1356 BinopI { op=add, lhs=v984, rhs_imm=16 } -> x0 + v1357 Load { addr=v984, disp=16, kind=I64 } -> x0 + v1358 BinopI { op=shl, lhs=v1357, rhs_imm=32 } -> x1 + v1359 Extend { value=v1357, kind=I32 } -> x7 + v1360 Imm(8) -> x0 + v1361 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1362 Load { addr=v984, disp=8, kind=I64 } -> x6 + v1363 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1364 BinopI { op=shl, lhs=v1363, rhs_imm=32 } -> x1 + v1365 Extend { value=v1363, kind=I32 } -> x2 + v1366 CallExt { binding_idx=145, args=[v1359, v1362, v1365], fp_arg_mask=0x0 } -> x0 + v1367 StoreLocal { off=-9, value=v1366, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1367) block 226 start_pc=0 - v1081 LoadLocal { off=-11, kind=I64 } -> x0 - v1082 BinopI { op=eq, lhs=v750, rhs_imm=28 } -> x0 - terminator Bz { cond=v1082, target=b229, fall=b227 } (exit_acc=v1082) + v1368 LoadLocal { off=-11, kind=I64 } -> x0 + v1369 BinopI { op=eq, lhs=v990, rhs_imm=32 } -> x0 + terminator Bz { cond=v1369, target=b228, fall=b227 } (exit_acc=v1369) block 227 start_pc=0 - v1083 LoadLocal { off=-7, kind=I64 } -> x0 - v1084 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1085 Imm(0) -> x1 - v1086 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1087 LoadLocal { off=-9, kind=I64 } -> x2 - v1088 Binop { op=div, lhs=v1086, rhs=v1087 } -> x1 - v1089 StoreLocal { off=-9, value=v1088, kind=I64 } -> - - terminator Jmp(b228) (exit_acc=v1089) + v1370 LoadLocal { off=-7, kind=I64 } -> x0 + v1371 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1372 BinopI { op=shl, lhs=v1371, rhs_imm=32 } -> x1 + v1373 Extend { value=v1371, kind=I32 } -> x7 + v1374 CallExt { binding_idx=148, args=[v1373], fp_arg_mask=0x0 } -> x0 + v1375 StoreLocal { off=-9, value=v1374, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1375) block 228 start_pc=0 - v1090 Phi { incoming=[b227:v1084, b231:v1100], kind=I64 } -> x12 - terminator Jmp(b225) + v1376 LoadLocal { off=-11, kind=I64 } -> x0 + v1377 BinopI { op=eq, lhs=v990, rhs_imm=33 } -> x0 + terminator Bz { cond=v1377, target=b230, fall=b229 } (exit_acc=v1377) block 229 start_pc=0 - v1091 LoadLocal { off=-11, kind=I64 } -> x0 - v1092 BinopI { op=eq, lhs=v750, rhs_imm=29 } -> x0 - terminator Bz { cond=v1092, target=b232, fall=b230 } (exit_acc=v1092) + v1378 LoadLocal { off=-7, kind=I64 } -> x0 + v1379 LoadLocal { off=-6, kind=I64 } -> x0 + v1380 Imm(8) -> x0 + v1381 BinopI { op=add, lhs=v988, rhs_imm=8 } -> x0 + v1382 Load { addr=v988, disp=8, kind=I64 } -> x0 + v1383 BinopI { op=shl, lhs=v1382, rhs_imm=3 } -> x0 + v1384 Binop { op=add, lhs=v984, rhs=v1383 } -> x0 + v1385 Imm(0) -> x1 + v1386 LoadLocal { off=-12, kind=I64 } -> x1 + v1387 Imm(-8) -> x1 + v1388 BinopI { op=add, lhs=v1384, rhs_imm=-8 } -> x1 + v1389 Load { addr=v1388, disp=0, kind=I64 } -> x7 + v1390 Imm(-16) -> x1 + v1391 BinopI { op=add, lhs=v1384, rhs_imm=-16 } -> x1 + v1392 Load { addr=v1391, disp=0, kind=I64 } -> x6 + v1393 Imm(-24) -> x1 + v1394 BinopI { op=add, lhs=v1384, rhs_imm=-24 } -> x1 + v1395 Load { addr=v1394, disp=0, kind=I64 } -> x2 + v1396 Imm(-32) -> x1 + v1397 BinopI { op=add, lhs=v1384, rhs_imm=-32 } -> x1 + v1398 Load { addr=v1397, disp=0, kind=I64 } -> x1 + v1399 Imm(-40) -> x8 + v1400 BinopI { op=add, lhs=v1384, rhs_imm=-40 } -> x8 + v1401 Load { addr=v1400, disp=0, kind=I64 } -> x8 + v1402 Imm(-48) -> x9 + v1403 BinopI { op=add, lhs=v1384, rhs_imm=-48 } -> x0 + v1404 Load { addr=v1403, disp=0, kind=I64 } -> x9 + v1405 CallExt { binding_idx=0, args=[v1389, v1392, v1395, v1398, v1401, v1404], fp_arg_mask=0x0 } -> x0 + v1406 StoreLocal { off=-9, value=v1405, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1406) block 230 start_pc=0 - v1093 LoadLocal { off=-7, kind=I64 } -> x0 - v1094 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1095 Imm(0) -> x1 - v1096 Load { addr=v744, disp=0, kind=I64 } -> x1 - v1097 LoadLocal { off=-9, kind=I64 } -> x2 - v1098 Binop { op=mod, lhs=v1096, rhs=v1097 } -> x1 - v1099 StoreLocal { off=-9, value=v1098, kind=I64 } -> - - terminator Jmp(b231) (exit_acc=v1099) + v1407 LoadLocal { off=-11, kind=I64 } -> x0 + v1408 BinopI { op=eq, lhs=v990, rhs_imm=34 } -> x0 + terminator Bz { cond=v1408, target=b232, fall=b231 } (exit_acc=v1408) block 231 start_pc=0 - v1100 Phi { incoming=[b230:v1094, b234:v744], kind=I64 } -> x12 - terminator Jmp(b228) + v1409 LoadLocal { off=-7, kind=I64 } -> x0 + v1410 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1411 BinopI { op=shl, lhs=v1410, rhs_imm=32 } -> x1 + v1412 Extend { value=v1410, kind=I32 } -> x7 + v1413 CallExt { binding_idx=54, args=[v1412], fp_arg_mask=0x0 } -> x0 + v1414 StoreLocal { off=-9, value=v1413, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1414) block 232 start_pc=0 - v1101 LoadLocal { off=-11, kind=I64 } -> x0 - v1102 BinopI { op=eq, lhs=v750, rhs_imm=30 } -> x0 - terminator Bz { cond=v1102, target=b235, fall=b233 } (exit_acc=v1102) + v1415 LoadLocal { off=-11, kind=I64 } -> x0 + v1416 BinopI { op=eq, lhs=v990, rhs_imm=35 } -> x0 + terminator Bz { cond=v1416, target=b234, fall=b233 } (exit_acc=v1416) block 233 start_pc=0 - v1103 LoadLocal { off=-7, kind=I64 } -> x0 - v1104 Imm(8) -> x0 - v1105 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1106 Load { addr=v744, disp=8, kind=I64 } -> x7 - v1107 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1108 BinopI { op=shl, lhs=v1107, rhs_imm=32 } -> x1 - v1109 Extend { value=v1107, kind=I32 } -> x6 - v1110 CallExt { binding_idx=144, args=[v1106, v1109], fp_arg_mask=0x0 } -> x0 - v1111 StoreLocal { off=-9, value=v1110, kind=I64 } -> - - terminator Jmp(b234) (exit_acc=v1111) + v1417 LoadLocal { off=-7, kind=I64 } -> x0 + v1418 Load { addr=v984, disp=0, kind=I64 } -> x7 + v1419 CallExt { binding_idx=57, args=[v1418], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b223) (exit_acc=v1419) block 234 start_pc=0 - terminator Jmp(b231) + v1420 LoadLocal { off=-11, kind=I64 } -> x0 + v1421 BinopI { op=eq, lhs=v990, rhs_imm=36 } -> x0 + terminator Bz { cond=v1421, target=b236, fall=b235 } (exit_acc=v1421) block 235 start_pc=0 - v1112 LoadLocal { off=-11, kind=I64 } -> x0 - v1113 BinopI { op=eq, lhs=v750, rhs_imm=31 } -> x0 - terminator Bz { cond=v1113, target=b238, fall=b236 } (exit_acc=v1113) + v1422 LoadLocal { off=-7, kind=I64 } -> x0 + v1423 Imm(16) -> x0 + v1424 BinopI { op=add, lhs=v984, rhs_imm=16 } -> x0 + v1425 Load { addr=v984, disp=16, kind=I64 } -> x7 + v1426 Imm(8) -> x0 + v1427 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1428 Load { addr=v984, disp=8, kind=I64 } -> x0 + v1429 BinopI { op=shl, lhs=v1428, rhs_imm=32 } -> x1 + v1430 Extend { value=v1428, kind=I32 } -> x6 + v1431 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1432 BinopI { op=shl, lhs=v1431, rhs_imm=32 } -> x1 + v1433 Extend { value=v1431, kind=I32 } -> x2 + v1434 CallExt { binding_idx=95, args=[v1425, v1430, v1433], fp_arg_mask=0x0 } -> x0 + v1435 StoreLocal { off=-9, value=v1434, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1435) block 236 start_pc=0 - v1114 LoadLocal { off=-7, kind=I64 } -> x0 - v1115 Imm(16) -> x0 - v1116 BinopI { op=add, lhs=v744, rhs_imm=16 } -> x0 - v1117 Load { addr=v744, disp=16, kind=I64 } -> x0 - v1118 BinopI { op=shl, lhs=v1117, rhs_imm=32 } -> x1 - v1119 Extend { value=v1117, kind=I32 } -> x7 - v1120 Imm(8) -> x0 - v1121 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1122 Load { addr=v744, disp=8, kind=I64 } -> x6 - v1123 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1124 BinopI { op=shl, lhs=v1123, rhs_imm=32 } -> x1 - v1125 Extend { value=v1123, kind=I32 } -> x2 - v1126 CallExt { binding_idx=145, args=[v1119, v1122, v1125], fp_arg_mask=0x0 } -> x0 - v1127 StoreLocal { off=-9, value=v1126, kind=I64 } -> - - terminator Jmp(b237) (exit_acc=v1127) + v1436 LoadLocal { off=-11, kind=I64 } -> x0 + v1437 BinopI { op=eq, lhs=v990, rhs_imm=37 } -> x0 + terminator Bz { cond=v1437, target=b239, fall=b237 } (exit_acc=v1437) block 237 start_pc=0 - terminator Jmp(b234) + v1438 LoadLocal { off=-7, kind=I64 } -> x0 + v1439 Imm(16) -> x0 + v1440 BinopI { op=add, lhs=v984, rhs_imm=16 } -> x0 + v1441 Load { addr=v984, disp=16, kind=I64 } -> x7 + v1442 Imm(8) -> x0 + v1443 BinopI { op=add, lhs=v984, rhs_imm=8 } -> x0 + v1444 Load { addr=v984, disp=8, kind=I64 } -> x6 + v1445 Load { addr=v984, disp=0, kind=I64 } -> x0 + v1446 BinopI { op=shl, lhs=v1445, rhs_imm=32 } -> x1 + v1447 Extend { value=v1445, kind=I32 } -> x2 + v1448 CallExt { binding_idx=96, args=[v1441, v1444, v1447], fp_arg_mask=0x0 } -> x0 + v1449 StoreLocal { off=-9, value=v1448, kind=I64 } -> - + terminator Jmp(b223) (exit_acc=v1449) block 238 start_pc=0 - v1128 LoadLocal { off=-11, kind=I64 } -> x0 - v1129 BinopI { op=eq, lhs=v750, rhs_imm=32 } -> x0 - terminator Bz { cond=v1129, target=b241, fall=b239 } (exit_acc=v1129) + v1013 ImmData(1703) -> x7 + v1014 CallExt { binding_idx=0, args=[v1013], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b125) (exit_acc=v1014) block 239 start_pc=0 - v1130 LoadLocal { off=-7, kind=I64 } -> x0 - v1131 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1132 BinopI { op=shl, lhs=v1131, rhs_imm=32 } -> x1 - v1133 Extend { value=v1131, kind=I32 } -> x7 - v1134 CallExt { binding_idx=148, args=[v1133], fp_arg_mask=0x0 } -> x0 - v1135 StoreLocal { off=-9, value=v1134, kind=I64 } -> - - terminator Jmp(b240) (exit_acc=v1135) + v1450 LoadLocal { off=-11, kind=I64 } -> x0 + v1451 BinopI { op=eq, lhs=v990, rhs_imm=38 } -> x0 + terminator Bz { cond=v1451, target=b241, fall=b240 } (exit_acc=v1451) block 240 start_pc=0 - terminator Jmp(b237) + v1452 ImmData(1705) -> x7 + v1453 LoadLocal { off=-7, kind=I64 } -> x0 + v1454 Load { addr=v984, disp=0, kind=I64 } -> x6 + v1455 LoadLocal { off=-10, kind=I64 } -> x0 + v1456 CallExt { binding_idx=0, args=[v1452, v1454, v993], fp_arg_mask=0x0 } -> x0 + v1457 LoadLocal { off=-7, kind=I64 } -> x0 + v1458 Load { addr=v984, disp=0, kind=I64 } -> x0 + terminator Return(v1458) (exit_acc=v1458) block 241 start_pc=0 - v1136 LoadLocal { off=-11, kind=I64 } -> x0 - v1137 BinopI { op=eq, lhs=v750, rhs_imm=33 } -> x0 - terminator Bz { cond=v1137, target=b244, fall=b242 } (exit_acc=v1137) + v1459 ImmData(1726) -> x7 + v1460 LoadLocal { off=-11, kind=I64 } -> x0 + v1461 LoadLocal { off=-10, kind=I64 } -> x0 + v1462 CallExt { binding_idx=0, args=[v1459, v990, v993], fp_arg_mask=0x0 } -> x0 + v1463 Imm(-1) -> x0 + terminator Return(v1463) (exit_acc=v1463) block 242 start_pc=0 - v1138 LoadLocal { off=-7, kind=I64 } -> x0 - v1139 LoadLocal { off=-6, kind=I64 } -> x0 - v1140 Imm(8) -> x0 - v1141 BinopI { op=add, lhs=v748, rhs_imm=8 } -> x0 - v1142 Load { addr=v748, disp=8, kind=I64 } -> x0 - v1143 BinopI { op=shl, lhs=v1142, rhs_imm=3 } -> x0 - v1144 Binop { op=add, lhs=v744, rhs=v1143 } -> x0 - v1145 Imm(0) -> x1 - v1146 LoadLocal { off=-12, kind=I64 } -> x1 - v1147 Imm(-8) -> x1 - v1148 BinopI { op=add, lhs=v1144, rhs_imm=-8 } -> x1 - v1149 Load { addr=v1148, disp=0, kind=I64 } -> x7 - v1150 Imm(-16) -> x1 - v1151 BinopI { op=add, lhs=v1144, rhs_imm=-16 } -> x1 - v1152 Load { addr=v1151, disp=0, kind=I64 } -> x6 - v1153 Imm(-24) -> x1 - v1154 BinopI { op=add, lhs=v1144, rhs_imm=-24 } -> x1 - v1155 Load { addr=v1154, disp=0, kind=I64 } -> x2 - v1156 Imm(-32) -> x1 - v1157 BinopI { op=add, lhs=v1144, rhs_imm=-32 } -> x1 - v1158 Load { addr=v1157, disp=0, kind=I64 } -> x1 - v1159 Imm(-40) -> x8 - v1160 BinopI { op=add, lhs=v1144, rhs_imm=-40 } -> x8 - v1161 Load { addr=v1160, disp=0, kind=I64 } -> x8 - v1162 Imm(-48) -> x9 - v1163 BinopI { op=add, lhs=v1144, rhs_imm=-48 } -> x0 - v1164 Load { addr=v1163, disp=0, kind=I64 } -> x9 - v1165 CallExt { binding_idx=0, args=[v1149, v1152, v1155, v1158, v1161, v1164], fp_arg_mask=0x0 } -> x0 - v1166 StoreLocal { off=-9, value=v1165, kind=I64 } -> - - terminator Jmp(b243) (exit_acc=v1166) + v573 ImmData(1231) -> x7 + v574 ImmData(1864) -> x0 + v575 Load { addr=v574, disp=0, kind=I64 } -> x6 + v576 CallExt { binding_idx=0, args=[v573, v575], fp_arg_mask=0x0 } -> x0 + v577 Imm(-1) -> x0 + terminator Return(v577) (exit_acc=v577) block 243 start_pc=0 - terminator Jmp(b240) + v536 ImmData(1203) -> x7 + v537 ImmData(1864) -> x0 + v538 Load { addr=v537, disp=0, kind=I64 } -> x6 + v539 ImmData(1832) -> x0 + v540 Load { addr=v539, disp=0, kind=I64 } -> x2 + v541 CallExt { binding_idx=0, args=[v536, v538, v540], fp_arg_mask=0x0 } -> x0 + v542 Imm(-1) -> x0 + terminator Return(v542) (exit_acc=v542) block 244 start_pc=0 - v1167 LoadLocal { off=-11, kind=I64 } -> x0 - v1168 BinopI { op=eq, lhs=v750, rhs_imm=34 } -> x0 - terminator Bz { cond=v1168, target=b247, fall=b245 } (exit_acc=v1168) + v839 ImmData(1441) -> x7 + v840 ImmData(1864) -> x0 + v841 Load { addr=v840, disp=0, kind=I64 } -> x6 + v842 CallExt { binding_idx=0, args=[v839, v841], fp_arg_mask=0x0 } -> x0 + v843 Imm(-1) -> x0 + terminator Return(v843) (exit_acc=v843) block 245 start_pc=0 - v1169 LoadLocal { off=-7, kind=I64 } -> x0 - v1170 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1171 BinopI { op=shl, lhs=v1170, rhs_imm=32 } -> x1 - v1172 Extend { value=v1170, kind=I32 } -> x7 - v1173 CallExt { binding_idx=54, args=[v1172], fp_arg_mask=0x0 } -> x0 - v1174 StoreLocal { off=-9, value=v1173, kind=I64 } -> - - terminator Jmp(b246) (exit_acc=v1174) + v828 ImmData(1414) -> x7 + v829 ImmData(1864) -> x0 + v830 Load { addr=v829, disp=0, kind=I64 } -> x6 + v831 CallExt { binding_idx=0, args=[v828, v830], fp_arg_mask=0x0 } -> x0 + v832 Imm(-1) -> x0 + terminator Return(v832) (exit_acc=v832) block 246 start_pc=0 - terminator Jmp(b243) + v762 ImmData(1385) -> x7 + v763 ImmData(1864) -> x0 + v764 Load { addr=v763, disp=0, kind=I64 } -> x6 + v765 CallExt { binding_idx=0, args=[v762, v764], fp_arg_mask=0x0 } -> x0 + v766 Imm(-1) -> x0 + terminator Return(v766) (exit_acc=v766) block 247 start_pc=0 - v1175 LoadLocal { off=-11, kind=I64 } -> x0 - v1176 BinopI { op=eq, lhs=v750, rhs_imm=35 } -> x0 - terminator Bz { cond=v1176, target=b250, fall=b248 } (exit_acc=v1176) + v713 ImmData(1349) -> x7 + v714 ImmData(1864) -> x0 + v715 Load { addr=v714, disp=0, kind=I64 } -> x6 + v716 CallExt { binding_idx=0, args=[v713, v715], fp_arg_mask=0x0 } -> x0 + v717 Imm(-1) -> x0 + terminator Return(v717) (exit_acc=v717) block 248 start_pc=0 - v1177 LoadLocal { off=-7, kind=I64 } -> x0 - v1178 Load { addr=v744, disp=0, kind=I64 } -> x7 - v1179 CallExt { binding_idx=57, args=[v1178], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b249) (exit_acc=v1179) + v702 ImmData(1318) -> x7 + v703 ImmData(1864) -> x0 + v704 Load { addr=v703, disp=0, kind=I64 } -> x6 + v705 CallExt { binding_idx=0, args=[v702, v704], fp_arg_mask=0x0 } -> x0 + v706 Imm(-1) -> x0 + terminator Return(v706) (exit_acc=v706) block 249 start_pc=0 - terminator Jmp(b246) + v618 ImmData(1285) -> x7 + v619 ImmData(1864) -> x0 + v620 Load { addr=v619, disp=0, kind=I64 } -> x6 + v621 CallExt { binding_idx=0, args=[v618, v620], fp_arg_mask=0x0 } -> x0 + v622 Imm(-1) -> x0 + terminator Return(v622) (exit_acc=v622) block 250 start_pc=0 - v1180 LoadLocal { off=-11, kind=I64 } -> x0 - v1181 BinopI { op=eq, lhs=v750, rhs_imm=36 } -> x0 - terminator Bz { cond=v1181, target=b253, fall=b251 } (exit_acc=v1181) + v608 ImmData(1257) -> x7 + v609 ImmData(1864) -> x0 + v610 Load { addr=v609, disp=0, kind=I64 } -> x6 + v611 CallExt { binding_idx=0, args=[v608, v610], fp_arg_mask=0x0 } -> x0 + v612 Imm(-1) -> x0 + terminator Return(v612) (exit_acc=v612) block 251 start_pc=0 - v1182 LoadLocal { off=-7, kind=I64 } -> x0 - v1183 Imm(16) -> x0 - v1184 BinopI { op=add, lhs=v744, rhs_imm=16 } -> x0 - v1185 Load { addr=v744, disp=16, kind=I64 } -> x7 - v1186 Imm(8) -> x0 - v1187 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1188 Load { addr=v744, disp=8, kind=I64 } -> x0 - v1189 BinopI { op=shl, lhs=v1188, rhs_imm=32 } -> x1 - v1190 Extend { value=v1188, kind=I32 } -> x6 - v1191 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1192 BinopI { op=shl, lhs=v1191, rhs_imm=32 } -> x1 - v1193 Extend { value=v1191, kind=I32 } -> x2 - v1194 CallExt { binding_idx=95, args=[v1185, v1190, v1193], fp_arg_mask=0x0 } -> x0 - v1195 StoreLocal { off=-9, value=v1194, kind=I64 } -> - - terminator Jmp(b252) (exit_acc=v1195) + terminator Jmp(b12) block 252 start_pc=0 - terminator Jmp(b249) + terminator Jmp(b10) block 253 start_pc=0 - v1196 LoadLocal { off=-11, kind=I64 } -> x0 - v1197 BinopI { op=eq, lhs=v750, rhs_imm=37 } -> x0 - terminator Bz { cond=v1197, target=b256, fall=b254 } (exit_acc=v1197) + terminator Jmp(b8) block 254 start_pc=0 - v1198 LoadLocal { off=-7, kind=I64 } -> x0 - v1199 Imm(16) -> x0 - v1200 BinopI { op=add, lhs=v744, rhs_imm=16 } -> x0 - v1201 Load { addr=v744, disp=16, kind=I64 } -> x7 - v1202 Imm(8) -> x0 - v1203 BinopI { op=add, lhs=v744, rhs_imm=8 } -> x0 - v1204 Load { addr=v744, disp=8, kind=I64 } -> x6 - v1205 Load { addr=v744, disp=0, kind=I64 } -> x0 - v1206 BinopI { op=shl, lhs=v1205, rhs_imm=32 } -> x1 - v1207 Extend { value=v1205, kind=I32 } -> x2 - v1208 CallExt { binding_idx=96, args=[v1201, v1204, v1207], fp_arg_mask=0x0 } -> x0 - v1209 StoreLocal { off=-9, value=v1208, kind=I64 } -> - - terminator Jmp(b255) (exit_acc=v1209) + terminator Jmp(b6) block 255 start_pc=0 - terminator Jmp(b252) + terminator Jmp(b4) block 256 start_pc=0 - v1210 LoadLocal { off=-11, kind=I64 } -> x0 - v1211 BinopI { op=eq, lhs=v750, rhs_imm=38 } -> x0 - terminator Bz { cond=v1211, target=b259, fall=b257 } (exit_acc=v1211) + terminator Jmp(b2) block 257 start_pc=0 - v1212 ImmData(1705) -> x7 - v1213 LoadLocal { off=-7, kind=I64 } -> x0 - v1214 Load { addr=v744, disp=0, kind=I64 } -> x6 - v1215 LoadLocal { off=-10, kind=I64 } -> x0 - v1216 CallExt { binding_idx=0, args=[v1212, v1214, v753], fp_arg_mask=0x0 } -> x0 - v1217 LoadLocal { off=-7, kind=I64 } -> x0 - v1218 Load { addr=v744, disp=0, kind=I64 } -> x0 - terminator Return(v1218) (exit_acc=v1218) + terminator Jmp(b113) block 258 start_pc=0 - terminator Jmp(b255) + v997 Imm(0) -> x0 + terminator Return(v997) (exit_acc=v997) block 259 start_pc=0 - v1219 ImmData(1726) -> x7 - v1220 LoadLocal { off=-11, kind=I64 } -> x0 - v1221 LoadLocal { off=-10, kind=I64 } -> x0 - v1222 CallExt { binding_idx=0, args=[v1219, v750, v753], fp_arg_mask=0x0 } -> x0 - v1223 Imm(-1) -> x0 - terminator Return(v1223) (exit_acc=v1223) + terminator Jmp(b125) block 260 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b223) block 261 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b223) block 262 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b223) block 263 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b223) block 264 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b223) block 265 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b223) block 266 start_pc=0 - terminator Jmp(b56) + terminator Jmp(b223) block 267 start_pc=0 - terminator Jmp(b65) - block 268 start_pc=0 - terminator Jmp(b83) - block 269 start_pc=0 - terminator Jmp(b99) + terminator Jmp(b223) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/c99_arith_common_width.ssa b/tests/snapshots/ssa/c99_arith_common_width.ssa index 991b49cae..f798d05fa 100644 --- a/tests/snapshots/ssa/c99_arith_common_width.ssa +++ b/tests/snapshots/ssa/c99_arith_common_width.ssa @@ -66,29 +66,157 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294967295) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(4294967296) -> x0 + v5 Imm(0) -> x0 v6 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v7 BinopI { op=and, lhs=v5, rhs_imm=4294967295 } -> x0 - v8 BinopI { op=eq, lhs=v7, rhs_imm=0 } -> x0 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x0 - terminator Bz { cond=v9, target=b5, fall=b4 } (exit_acc=v9) + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 v18 Imm(0) -> x0 terminator Jmp(b3) (exit_acc=v18) block 3 start_pc=0 v19 Imm(0) -> x0 - v20 Imm(0) -> x1 - v21 LoadLocal { off=-3, kind=U32 } -> x1 - v22 BinopI { op=sub, lhs=v19, rhs_imm=1 } -> x0 - v23 BinopI { op=and, lhs=v22, rhs_imm=4294967295 } -> x0 + v20 Imm(0) -> x0 + v21 LoadLocal { off=-3, kind=U32 } -> x0 + v22 Imm(-1) -> x0 + v23 Imm(4294967295) -> x0 v24 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v23) + terminator Jmp(b4) (exit_acc=v23) block 4 start_pc=0 + v25 Imm(4294967295) -> x0 + v26 Imm(1) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v27) + block 5 start_pc=0 + v35 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) + block 6 start_pc=0 + v36 Imm(-1) -> x0 + v37 Imm(0) -> x0 + v38 Imm(1) -> x0 + v39 Imm(0) -> x0 + v40 LoadLocal { off=-5, kind=I32 } -> x0 + v41 LoadLocal { off=-6, kind=U32 } -> x0 + v42 Imm(-2) -> x0 + v43 Imm(4294967294) -> x0 + v44 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v43) + block 7 start_pc=0 + v45 Imm(4294967294) -> x0 + v46 Imm(1) -> x0 + v47 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v47) + block 8 start_pc=0 + v56 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v56) + block 9 start_pc=0 + v57 Imm(-1) -> x0 + v58 Imm(0) -> x0 + v59 Imm(1) -> x0 + v60 Imm(0) -> x0 + v61 LoadLocal { off=-8, kind=I32 } -> x0 + v62 LoadLocal { off=-9, kind=U32 } -> x0 + v63 Imm(-1) -> x0 + v64 Imm(4294967295) -> x0 + v65 Imm(0) -> x1 + terminator Jmp(b10) (exit_acc=v64) + block 10 start_pc=0 + v66 Imm(4294967295) -> x0 + v67 Imm(1) -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v68) + block 11 start_pc=0 + v77 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v77) + block 12 start_pc=0 + v78 Imm(50000) -> x0 + v79 Imm(0) -> x0 + v80 LoadLocal { off=-11, kind=U16 } -> x0 + v81 Imm(2500000000) -> x0 + v82 Imm(-7709325833709551616) -> x0 + v83 Imm(-1794967296) -> x0 + v84 Imm(0) -> x1 + terminator Jmp(b13) (exit_acc=v83) + block 13 start_pc=0 + v85 LoadLocal { off=-12, kind=I64 } -> x0 + v86 Imm(1) -> x0 + v87 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v87) + block 14 start_pc=0 + v96 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v96) + block 15 start_pc=0 + v97 Imm(-1) -> x0 + v98 Imm(0) -> x0 + v99 Imm(1) -> x0 + v100 Imm(0) -> x0 + v101 LoadLocal { off=-13, kind=I32 } -> x0 + v102 LoadLocal { off=-14, kind=U32 } -> x0 + v103 Imm(0) -> x0 + v104 Imm(0) -> x0 + v105 Imm(0) -> x1 + terminator Jmp(b16) (exit_acc=v104) + block 16 start_pc=0 + v106 Imm(0) -> x0 + v107 Imm(1) -> x0 + v108 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v108) + block 17 start_pc=0 + v117 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v117) + block 18 start_pc=0 + v118 Imm(-1) -> x0 + v119 Imm(0) -> x0 + v120 Imm(1) -> x0 + v121 Imm(0) -> x1 + terminator Jmp(b19) (exit_acc=v120) + block 19 start_pc=0 + v122 LoadLocal { off=-16, kind=I64 } -> x0 + v123 LoadLocal { off=-17, kind=U32 } -> x0 + v124 Imm(1) -> x0 + v125 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v125) + block 20 start_pc=0 + v134 Imm(0) -> x0 + terminator Jmp(b21) (exit_acc=v134) + block 21 start_pc=0 + v135 Imm(-1) -> x0 + v136 Imm(0) -> x0 + v137 Imm(4294967295) -> x0 + v138 Imm(0) -> x1 + terminator Jmp(b22) (exit_acc=v137) + block 22 start_pc=0 + v139 LoadLocal { off=-18, kind=I32 } -> x0 + v140 LoadLocal { off=-19, kind=U32 } -> x0 + v141 Imm(-4294967296) -> x0 + v142 Imm(0) -> x0 + v143 Imm(1) -> x0 + v144 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v144) + block 23 start_pc=0 + v153 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v153) + block 24 start_pc=0 + v154 ImmData(264) -> x0 + v155 Load { addr=v154, disp=0, kind=I32 } -> x0 + v156 BinopI { op=eq, lhs=v155, rhs_imm=0 } -> x0 + terminator Bz { cond=v156, target=b26, fall=b25 } (exit_acc=v156) + block 25 start_pc=0 + v157 ImmData(240) -> x7 + v158 CallExt { binding_idx=0, args=[v157], fp_arg_mask=0x0 } -> x0 + v159 Imm(0) -> x0 + terminator Return(v159) (exit_acc=v159) + block 26 start_pc=0 + v160 ImmData(264) -> x0 + v161 Load { addr=v160, disp=0, kind=I32 } -> x0 + terminator Return(v161) (exit_acc=v161) + block 27 start_pc=0 v10 ImmData(264) -> x0 v11 Imm(1) -> x3 v12 Store { addr=v10, disp=0, value=v11, kind=I32 } -> - @@ -97,29 +225,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v15 ImmData(64) -> x6 v16 Imm(26) -> x2 v17 CallExt { binding_idx=1, args=[v14, v15, v16, v11], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b5) (exit_acc=v17) - block 5 start_pc=0 + terminator Jmp(b2) (exit_acc=v17) + block 28 start_pc=0 terminator Jmp(b2) - block 6 start_pc=0 - v25 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x0 - v26 BinopI { op=eq, lhs=v25, rhs_imm=4294967295 } -> x0 - v27 BinopI { op=eq, lhs=v26, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) - block 7 start_pc=0 - v35 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v35) - block 8 start_pc=0 - v36 Imm(-1) -> x0 - v37 Imm(0) -> x1 - v38 Imm(1) -> x1 - v39 Imm(0) -> x2 - v40 LoadLocal { off=-5, kind=I32 } -> x2 - v41 LoadLocal { off=-6, kind=U32 } -> x2 - v42 Binop { op=sub, lhs=v36, rhs=v38 } -> x0 - v43 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x0 - v44 Imm(0) -> x1 - terminator Jmp(b11) (exit_acc=v43) - block 9 start_pc=0 + block 29 start_pc=0 v28 ImmData(264) -> x0 v29 Imm(2) -> x3 v30 Store { addr=v28, disp=0, value=v29, kind=I32 } -> - @@ -127,29 +236,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v32 ImmData(86) -> x6 v33 Imm(33) -> x2 v34 CallExt { binding_idx=1, args=[v31, v32, v33, v29], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b10) (exit_acc=v34) - block 10 start_pc=0 - terminator Jmp(b7) - block 11 start_pc=0 - v45 BinopI { op=and, lhs=v43, rhs_imm=4294967295 } -> x0 - v46 BinopI { op=eq, lhs=v45, rhs_imm=4294967294 } -> x0 - v47 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x0 - terminator Bz { cond=v47, target=b15, fall=b14 } (exit_acc=v47) - block 12 start_pc=0 - v56 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v56) - block 13 start_pc=0 - v57 Imm(-1) -> x0 - v58 Imm(0) -> x1 - v59 Imm(1) -> x1 - v60 Imm(0) -> x2 - v61 LoadLocal { off=-8, kind=I32 } -> x2 - v62 LoadLocal { off=-9, kind=U32 } -> x2 - v63 Binop { op=mul, lhs=v57, rhs=v59 } -> x0 - v64 BinopI { op=and, lhs=v63, rhs_imm=4294967295 } -> x0 - v65 Imm(0) -> x1 - terminator Jmp(b16) (exit_acc=v64) - block 14 start_pc=0 + terminator Jmp(b5) (exit_acc=v34) + block 30 start_pc=0 + terminator Jmp(b5) + block 31 start_pc=0 v48 ImmData(264) -> x0 v49 Imm(3) -> x3 v50 Store { addr=v48, disp=0, value=v49, kind=I32 } -> - @@ -158,27 +248,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v53 ImmData(108) -> x6 v54 Imm(41) -> x2 v55 CallExt { binding_idx=1, args=[v52, v53, v54, v49], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b15) (exit_acc=v55) - block 15 start_pc=0 - terminator Jmp(b12) - block 16 start_pc=0 - v66 BinopI { op=and, lhs=v64, rhs_imm=4294967295 } -> x0 - v67 BinopI { op=eq, lhs=v66, rhs_imm=4294967295 } -> x0 - v68 BinopI { op=eq, lhs=v67, rhs_imm=0 } -> x0 - terminator Bz { cond=v68, target=b20, fall=b19 } (exit_acc=v68) - block 17 start_pc=0 - v77 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v77) - block 18 start_pc=0 - v78 Imm(50000) -> x0 - v79 Imm(0) -> x1 - v80 LoadLocal { off=-11, kind=U16 } -> x1 - v81 Binop { op=mul, lhs=v78, rhs=v78 } -> x0 - v82 BinopI { op=shl, lhs=v81, rhs_imm=32 } -> x1 - v83 Extend { value=v81, kind=I32 } -> x0 - v84 Imm(0) -> x1 - terminator Jmp(b21) (exit_acc=v83) - block 19 start_pc=0 + terminator Jmp(b8) (exit_acc=v55) + block 32 start_pc=0 + terminator Jmp(b8) + block 33 start_pc=0 v69 ImmData(264) -> x0 v70 Imm(4) -> x3 v71 Store { addr=v69, disp=0, value=v70, kind=I32 } -> - @@ -187,29 +260,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v74 ImmData(130) -> x6 v75 Imm(49) -> x2 v76 CallExt { binding_idx=1, args=[v73, v74, v75, v70], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b20) (exit_acc=v76) - block 20 start_pc=0 - terminator Jmp(b17) - block 21 start_pc=0 - v85 LoadLocal { off=-12, kind=I64 } -> x1 - v86 BinopI { op=eq, lhs=v83, rhs_imm=-1794967296 } -> x0 - v87 BinopI { op=eq, lhs=v86, rhs_imm=0 } -> x0 - terminator Bz { cond=v87, target=b25, fall=b24 } (exit_acc=v87) - block 22 start_pc=0 - v96 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v96) - block 23 start_pc=0 - v97 Imm(-1) -> x0 - v98 Imm(0) -> x1 - v99 Imm(1) -> x1 - v100 Imm(0) -> x2 - v101 LoadLocal { off=-13, kind=I32 } -> x2 - v102 LoadLocal { off=-14, kind=U32 } -> x2 - v103 Binop { op=add, lhs=v97, rhs=v99 } -> x0 - v104 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x0 - v105 Imm(0) -> x1 - terminator Jmp(b26) (exit_acc=v104) - block 24 start_pc=0 + terminator Jmp(b11) (exit_acc=v76) + block 34 start_pc=0 + terminator Jmp(b11) + block 35 start_pc=0 v88 ImmData(264) -> x0 v89 Imm(5) -> x3 v90 Store { addr=v88, disp=0, value=v89, kind=I32 } -> - @@ -218,24 +272,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v93 ImmData(152) -> x6 v94 Imm(62) -> x2 v95 CallExt { binding_idx=1, args=[v92, v93, v94, v89], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b25) (exit_acc=v95) - block 25 start_pc=0 - terminator Jmp(b22) - block 26 start_pc=0 - v106 BinopI { op=and, lhs=v104, rhs_imm=4294967295 } -> x0 - v107 BinopI { op=eq, lhs=v106, rhs_imm=0 } -> x0 - v108 BinopI { op=eq, lhs=v107, rhs_imm=0 } -> x0 - terminator Bz { cond=v108, target=b30, fall=b29 } (exit_acc=v108) - block 27 start_pc=0 - v117 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v117) - block 28 start_pc=0 - v118 Imm(-1) -> x0 - v119 Imm(0) -> x1 - v120 Imm(1) -> x1 - v121 Imm(0) -> x2 - terminator Jmp(b31) (exit_acc=v120) - block 29 start_pc=0 + terminator Jmp(b14) (exit_acc=v95) + block 36 start_pc=0 + terminator Jmp(b14) + block 37 start_pc=0 v109 ImmData(264) -> x0 v110 Imm(100) -> x3 v111 Store { addr=v109, disp=0, value=v110, kind=I32 } -> - @@ -244,25 +284,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v114 ImmData(174) -> x6 v115 Imm(75) -> x2 v116 CallExt { binding_idx=1, args=[v113, v114, v115, v110], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b30) (exit_acc=v116) - block 30 start_pc=0 - terminator Jmp(b27) - block 31 start_pc=0 - v122 LoadLocal { off=-16, kind=I64 } -> x2 - v123 LoadLocal { off=-17, kind=U32 } -> x2 - v124 Binop { op=lt, lhs=v118, rhs=v120 } -> x0 - v125 BinopI { op=eq, lhs=v124, rhs_imm=0 } -> x0 - terminator Bz { cond=v125, target=b35, fall=b34 } (exit_acc=v125) - block 32 start_pc=0 - v134 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v134) - block 33 start_pc=0 - v135 Imm(-1) -> x0 - v136 Imm(0) -> x1 - v137 Imm(4294967295) -> x1 - v138 Imm(0) -> x2 - terminator Jmp(b36) (exit_acc=v137) - block 34 start_pc=0 + terminator Jmp(b17) (exit_acc=v116) + block 38 start_pc=0 + terminator Jmp(b17) + block 39 start_pc=0 v126 ImmData(264) -> x0 v127 Imm(101) -> x3 v128 Store { addr=v126, disp=0, value=v127, kind=I32 } -> - @@ -271,26 +296,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v131 ImmData(196) -> x6 v132 Imm(84) -> x2 v133 CallExt { binding_idx=1, args=[v130, v131, v132, v127], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b35) (exit_acc=v133) - block 35 start_pc=0 - terminator Jmp(b32) - block 36 start_pc=0 - v139 LoadLocal { off=-18, kind=I32 } -> x2 - v140 LoadLocal { off=-19, kind=U32 } -> x2 - v141 Binop { op=xor, lhs=v135, rhs=v137 } -> x0 - v142 BinopI { op=and, lhs=v141, rhs_imm=4294967295 } -> x0 - v143 BinopI { op=eq, lhs=v142, rhs_imm=0 } -> x0 - v144 BinopI { op=eq, lhs=v143, rhs_imm=0 } -> x0 - terminator Bz { cond=v144, target=b40, fall=b39 } (exit_acc=v144) - block 37 start_pc=0 - v153 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v153) - block 38 start_pc=0 - v154 ImmData(264) -> x0 - v155 Load { addr=v154, disp=0, kind=I32 } -> x0 - v156 BinopI { op=eq, lhs=v155, rhs_imm=0 } -> x0 - terminator Bz { cond=v156, target=b42, fall=b41 } (exit_acc=v156) - block 39 start_pc=0 + terminator Jmp(b20) (exit_acc=v133) + block 40 start_pc=0 + terminator Jmp(b20) + block 41 start_pc=0 v145 ImmData(264) -> x0 v146 Imm(102) -> x3 v147 Store { addr=v145, disp=0, value=v146, kind=I32 } -> - @@ -299,18 +308,9 @@ fn ent_pc=6 n_params=0 variadic=false locals=23 v150 ImmData(218) -> x6 v151 Imm(93) -> x2 v152 CallExt { binding_idx=1, args=[v149, v150, v151, v146], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b40) (exit_acc=v152) - block 40 start_pc=0 - terminator Jmp(b37) - block 41 start_pc=0 - v157 ImmData(240) -> x7 - v158 CallExt { binding_idx=0, args=[v157], fp_arg_mask=0x0 } -> x0 - v159 Imm(0) -> x0 - terminator Return(v159) (exit_acc=v159) + terminator Jmp(b23) (exit_acc=v152) block 42 start_pc=0 - v160 ImmData(264) -> x0 - v161 Load { addr=v160, disp=0, kind=I32 } -> x0 - terminator Return(v161) (exit_acc=v161) + terminator Jmp(b23) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/c99_qualifiers.ssa b/tests/snapshots/ssa/c99_qualifiers.ssa index 62e7c4499..53f931372 100644 --- a/tests/snapshots/ssa/c99_qualifiers.ssa +++ b/tests/snapshots/ssa/c99_qualifiers.ssa @@ -29,15 +29,8 @@ fn ent_pc=1 n_params=2 variadic=false locals=2 v5 Imm(0) -> x1 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b2) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v21], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v16], kind=I64 } -> x0 - v10 LoadLocal { off=-2, kind=I64 } -> x2 - v11 LoadLocal { off=3, kind=I64 } -> x2 - v12 Binop { op=ult, lhs=v8, rhs=v3 } -> x2 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) - block 2 start_pc=0 v13 Extend { value=v9, kind=I32 } -> x2 v14 LoadLocal { off=2, kind=I64 } -> x2 v15 Load { addr=v1, disp=0, kind=I32 } -> x2 @@ -48,7 +41,14 @@ fn ent_pc=1 n_params=2 variadic=false locals=2 v20 LoadLocal { off=-2, kind=I64 } -> x2 v21 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 v22 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v21) + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v8 Phi { incoming=[b0:v5, b1:v21], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b1:v16], kind=I64 } -> x0 + v10 LoadLocal { off=-2, kind=I64 } -> x2 + v11 LoadLocal { off=3, kind=I64 } -> x2 + v12 Binop { op=ult, lhs=v8, rhs=v3 } -> x2 + terminator Bnz { cond=v12, target=b1, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v23 Extend { value=v9, kind=I32 } -> x0 terminator Return(v23) (exit_acc=v23) @@ -63,57 +63,45 @@ fn ent_pc=2 n_params=0 variadic=false locals=9 v3 LocalAddr(-5) -> x7 v4 Imm(0) -> x0 v5 Imm(1) -> x0 - v6 Imm(2) -> x1 - v7 Extend { value=v5, kind=I32 } -> x0 - v8 Imm(0) -> x2 - v9 Imm(0) -> x2 - v10 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x1 - v11 Binop { op=add, lhs=v7, rhs=v10 } -> x0 - v12 BinopI { op=and, lhs=v11, rhs_imm=4294967295 } -> x0 - v13 BinopI { op=ne, lhs=v12, rhs_imm=3 } -> x0 - terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) + v6 Imm(2) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(2) -> x0 + v11 Imm(3) -> x0 + v12 Imm(3) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v13) block 1 start_pc=0 - v14 Imm(1) -> x0 - terminator Return(v14) (exit_acc=v14) - block 2 start_pc=0 v15 LoadLocal { off=-6, kind=I64 } -> x0 v16 Imm(1) -> x6 v17 Call { target_pc=1, args=[v3, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v18 BinopI { op=ne, lhs=v17, rhs_imm=7 } -> x0 - terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) - block 3 start_pc=0 + terminator Bz { cond=v18, target=b3, fall=b2 } (exit_acc=v18) + block 2 start_pc=0 v19 Imm(2) -> x0 terminator Return(v19) (exit_acc=v19) - block 4 start_pc=0 + block 3 start_pc=0 v20 ImmData(16) -> x0 v21 Imm(0) -> x1 v22 LoadLocal { off=-7, kind=I64 } -> x1 v23 Imm(0) -> x1 v24 Load { addr=v20, disp=0, kind=I8 } -> x0 v25 BinopI { op=ne, lhs=v24, rhs_imm=98 } -> x0 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) - block 5 start_pc=0 + terminator Bz { cond=v25, target=b5, fall=b4 } (exit_acc=v25) + block 4 start_pc=0 v26 Imm(3) -> x0 terminator Return(v26) (exit_acc=v26) - block 6 start_pc=0 + block 5 start_pc=0 v27 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v27) - block 7 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) - block 8 start_pc=0 + terminator Jmp(b6) (exit_acc=v27) + block 6 start_pc=0 v29 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v29) - block 9 start_pc=0 - v30 Imm(5) -> x0 - terminator Return(v30) (exit_acc=v30) - block 10 start_pc=0 + terminator Jmp(b7) (exit_acc=v29) + block 7 start_pc=0 v31 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v31) - block 11 start_pc=0 - v32 Imm(6) -> x0 - terminator Return(v32) (exit_acc=v32) - block 12 start_pc=0 + terminator Jmp(b8) (exit_acc=v31) + block 8 start_pc=0 v33 ImmData(32) -> x0 v34 Imm(1) -> x1 v35 Store { addr=v33, disp=0, value=v34, kind=I32 } -> - @@ -121,13 +109,25 @@ fn ent_pc=2 n_params=0 variadic=false locals=9 v37 BinopI { op=xor, lhs=v36, rhs_imm=1 } -> x0 v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x0 - terminator Bz { cond=v39, target=b14, fall=b13 } (exit_acc=v39) - block 13 start_pc=0 + terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) + block 9 start_pc=0 v40 Imm(7) -> x0 terminator Return(v40) (exit_acc=v40) - block 14 start_pc=0 + block 10 start_pc=0 v41 Imm(0) -> x0 terminator Return(v41) (exit_acc=v41) + block 11 start_pc=0 + v14 Imm(1) -> x0 + terminator Return(v14) (exit_acc=v14) + block 12 start_pc=0 + v28 Imm(4) -> x0 + terminator Return(v28) (exit_acc=v28) + block 13 start_pc=0 + v30 Imm(5) -> x0 + terminator Return(v30) (exit_acc=v30) + block 14 start_pc=0 + v32 Imm(6) -> x0 + terminator Return(v32) (exit_acc=v32) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/call_arg_extend_drop.ssa b/tests/snapshots/ssa/call_arg_extend_drop.ssa new file mode 100644 index 000000000..48ccc4db6 --- /dev/null +++ b/tests/snapshots/ssa/call_arg_extend_drop.ssa @@ -0,0 +1,208 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=addv +fn ent_pc=0 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I32 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=add, lhs=v1, rhs=v3 } -> x0 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 + v9 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v9) (exit_acc=v9) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=fib +fn ent_pc=1 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[3, 12] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x3 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 + terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + block 1 start_pc=0 + v5 LoadLocal { off=2, kind=I32 } -> x0 + terminator Return(v1) (exit_acc=v1) + block 2 start_pc=0 + v6 LoadLocal { off=2, kind=I32 } -> x0 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=1, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 + v11 LoadLocal { off=2, kind=I32 } -> x0 + v12 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x7 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x0 + v14 Extend { value=v12, kind=I32 } -> x0 + v15 Call { target_pc=1, args=[v12], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v16 Binop { op=add, lhs=v10, rhs=v15 } -> x0 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 + v18 Extend { value=v16, kind=I32 } -> x0 + terminator Return(v18) (exit_acc=v18) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=cell_escapes +fn ent_pc=2 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 LocalAddr(2) -> x0 + v4 Imm(0) -> x1 + v5 LoadLocal { off=-1, kind=I64 } -> x1 + v6 Load { addr=v3, disp=0, kind=I32 } -> x0 + v7 BinopI { op=mul, lhs=v6, rhs_imm=3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=3 --- +; name=narrow +fn ent_pc=3 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I8) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I16) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I8 } -> x0 + v6 BinopI { op=mul, lhs=v1, rhs_imm=100 } -> x0 + v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 + v8 Extend { value=v6, kind=I32 } -> x1 + v9 LoadLocal { off=3, kind=I16 } -> x1 + v10 Binop { op=add, lhs=v6, rhs=v3 } -> x0 + v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x1 + v12 Extend { value=v10, kind=I32 } -> x0 + terminator Return(v12) (exit_acc=v12) +; --- SSA dump (ok=true) ent_pc=4 --- +; name=main +fn ent_pc=4 n_params=0 variadic=false locals=4 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(9223372032559808517) -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(21474836480) -> x0 + v5 Imm(5) -> x0 + v6 Imm(0) -> x0 + v7 LoadLocal { off=-2, kind=I32 } -> x0 + v8 Imm(4) -> x0 + v9 Imm(17179869184) -> x0 + v10 Imm(4) -> x0 + v11 Imm(6) -> x0 + v12 Imm(25769803776) -> x0 + v13 Imm(6) -> x0 + v14 Imm(4) -> x0 + v15 Imm(0) -> x0 + v16 Imm(6) -> x0 + v17 Imm(0) -> x0 + v18 Imm(10) -> x0 + v19 Imm(42949672960) -> x0 + v20 Imm(10) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v21) + block 1 start_pc=0 + v23 LoadLocal { off=-2, kind=I32 } -> x0 + v24 Imm(20) -> x0 + v25 Imm(85899345920) -> x0 + v26 Imm(20) -> x7 + v27 Call { target_pc=1, args=[v26], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v28 BinopI { op=ne, lhs=v27, rhs_imm=6765 } -> x0 + terminator Bz { cond=v28, target=b3, fall=b2 } (exit_acc=v28) + block 2 start_pc=0 + v29 Imm(2) -> x0 + terminator Return(v29) (exit_acc=v29) + block 3 start_pc=0 + v30 LoadLocal { off=-2, kind=I32 } -> x0 + v31 Imm(-7) -> x0 + v32 Imm(-30064771072) -> x0 + v33 Imm(-7) -> x7 + v34 Call { target_pc=2, args=[v33], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v35 BinopI { op=ne, lhs=v34, rhs_imm=-21 } -> x0 + terminator Bz { cond=v35, target=b5, fall=b4 } (exit_acc=v35) + block 4 start_pc=0 + v36 Imm(3) -> x0 + terminator Return(v36) (exit_acc=v36) + block 5 start_pc=0 + v37 LoadLocal { off=-2, kind=I32 } -> x0 + v38 Imm(240) -> x0 + v39 Imm(1030792151040) -> x0 + v40 Imm(240) -> x0 + v41 Imm(-1152921504606846976) -> x0 + v42 Imm(-16) -> x0 + v43 Imm(-4075) -> x0 + v44 Imm(-17501991731200) -> x0 + v45 Imm(-4075) -> x0 + v46 Imm(-1147010530095923200) -> x0 + v47 Imm(-4075) -> x0 + v48 Imm(-16) -> x0 + v49 Imm(0) -> x0 + v50 Imm(-4075) -> x0 + v51 Imm(0) -> x0 + v52 Imm(-1600) -> x0 + v53 Imm(-6871947673600) -> x0 + v54 Imm(-1600) -> x0 + v55 Imm(-5675) -> x0 + v56 Imm(-24373939404800) -> x0 + v57 Imm(-5675) -> x0 + v58 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v58) + block 6 start_pc=0 + v60 Imm(0) -> x0 + terminator Return(v60) (exit_acc=v60) + block 7 start_pc=0 + v22 Imm(1) -> x0 + terminator Return(v22) (exit_acc=v22) + block 8 start_pc=0 + v59 Imm(4) -> x0 + terminator Return(v59) (exit_acc=v59) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/call_indirect_target_scratch_collision.ssa b/tests/snapshots/ssa/call_indirect_target_scratch_collision.ssa index c17494172..b6ed398e7 100644 --- a/tests/snapshots/ssa/call_indirect_target_scratch_collision.ssa +++ b/tests/snapshots/ssa/call_indirect_target_scratch_collision.ssa @@ -88,19 +88,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=10 block 2 start_pc=0 v22 Phi { incoming=[b6:v17, b1:v20], kind=I64 } -> x1 v23 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) + terminator Bz { cond=v22, target=b5, fall=b3 } (exit_acc=v22) block 3 start_pc=0 v24 Imm(0) -> x1 v25 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v24) + terminator Jmp(b4) (exit_acc=v24) block 4 start_pc=0 - v26 Imm(1) -> x1 - v27 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v26) - block 5 start_pc=0 - v28 Phi { incoming=[b3:v24, b4:v26], kind=I64 } -> x1 + v28 Phi { incoming=[b3:v24, b5:v26], kind=I64 } -> x1 v29 LoadLocal { off=-10, kind=I64 } -> x0 terminator Return(v28) (exit_acc=v28) + block 5 start_pc=0 + v26 Imm(1) -> x1 + v27 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v26) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/call_sp_adjust_imm12_overflow.ssa b/tests/snapshots/ssa/call_sp_adjust_imm12_overflow.ssa index f1e940f47..7aa187602 100644 --- a/tests/snapshots/ssa/call_sp_adjust_imm12_overflow.ssa +++ b/tests/snapshots/ssa/call_sp_adjust_imm12_overflow.ssa @@ -5,15 +5,15 @@ fn ent_pc=0 n_params=261 variadic=false locals=523 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-523, kind=I64 } -> x1 - v4 LocalAddr(-2) -> x1 - v5 Load { addr=v4, disp=0, kind=I64 } -> x1 - v6 LocalAddr(-2) -> x2 - v7 BinopI { op=add, lhs=v6, rhs_imm=8 } -> x6 - v8 Load { addr=v6, disp=8, kind=I64 } -> x2 - v9 Binop { op=add, lhs=v5, rhs=v8 } -> x1 - v10 Binop { op=add, lhs=v1, rhs=v9 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-523, kind=I64 } -> x0 + v4 LocalAddr(-2) -> x0 + v5 Load { addr=v4, disp=0, kind=I64 } -> x0 + v6 LocalAddr(-2) -> x1 + v7 BinopI { op=add, lhs=v6, rhs_imm=8 } -> x2 + v8 Load { addr=v6, disp=8, kind=I64 } -> x1 + v9 Binop { op=add, lhs=v5, rhs=v8 } -> x0 + v10 BinopI { op=add, lhs=v9, rhs_imm=0 } -> x0 v11 Imm(0) -> x1 v12 LoadLocal { off=-523, kind=I64 } -> x1 v13 LocalAddr(-4) -> x1 @@ -2360,7 +2360,7 @@ fn ent_pc=0 n_params=261 variadic=false locals=523 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=sum_longs fn ent_pc=1 n_params=260 variadic=false locals=1 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -2376,10 +2376,10 @@ fn ent_pc=1 n_params=260 variadic=false locals=1 v11 ParamRef(5, kind=I64) -> x9 v12 Imm(0) -> x0 v13 Imm(0) -> x0 - v14 Imm(0) -> x3 - v15 LoadLocal { off=-1, kind=I64 } -> x3 - v16 LoadLocal { off=2, kind=I64 } -> x3 - v17 Binop { op=add, lhs=v13, rhs=v1 } -> x0 + v14 Imm(0) -> x0 + v15 LoadLocal { off=-1, kind=I64 } -> x0 + v16 LoadLocal { off=2, kind=I64 } -> x0 + v17 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 v18 Imm(0) -> x7 v19 LoadLocal { off=-1, kind=I64 } -> x7 v20 LoadLocal { off=3, kind=I64 } -> x7 @@ -3431,18 +3431,8 @@ fn ent_pc=2 n_params=0 variadic=false locals=264 v4 Imm(0) -> x0 v5 Imm(0) -> x1 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v7 Phi { incoming=[b0:v5, b2:v11], kind=I64 } -> x1 - v8 LoadLocal { off=-3, kind=I64 } -> x0 - v9 BinopI { op=lt, lhs=v7, rhs_imm=261 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) - block 2 start_pc=0 - v10 LoadLocal { off=-3, kind=I64 } -> x0 - v11 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 - v12 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 v13 ImmData(24) -> x0 v14 LoadLocal { off=-3, kind=I64 } -> x2 v15 BinopI { op=shl, lhs=v7, rhs_imm=4 } -> x2 @@ -3456,6 +3446,16 @@ fn ent_pc=2 n_params=0 variadic=false locals=264 v23 BinopI { op=shl, lhs=v7, rhs_imm=1 } -> x2 v24 Store { addr=v20, disp=8, value=v23, kind=I64 } -> - terminator Jmp(b2) (exit_acc=v24) + block 2 start_pc=0 + v10 LoadLocal { off=-3, kind=I64 } -> x0 + v11 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v12 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v11) + block 3 start_pc=0 + v7 Phi { incoming=[b0:v5, b2:v11], kind=I64 } -> x1 + v8 LoadLocal { off=-3, kind=I64 } -> x0 + v9 BinopI { op=lt, lhs=v7, rhs_imm=261 } -> x0 + terminator Bnz { cond=v9, target=b1, fall=b4 } (exit_acc=v9) block 4 start_pc=0 v25 ImmData(24) -> x7 v26 Imm(0) -> x0 diff --git a/tests/snapshots/ssa/callee_save_pair_fold.ssa b/tests/snapshots/ssa/callee_save_pair_fold.ssa new file mode 100644 index 000000000..bc5b8511f --- /dev/null +++ b/tests/snapshots/ssa/callee_save_pair_fold.ssa @@ -0,0 +1,125 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=sink +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x3 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 BinopI { op=le, lhs=v1, rhs_imm=0 } -> x0 + terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + block 1 start_pc=0 + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) + block 2 start_pc=0 + v6 LoadLocal { off=2, kind=I32 } -> x0 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 Binop { op=add, lhs=v1, rhs=v10 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=quad +fn ent_pc=1 n_params=5 variadic=false locals=2 + spill_count=0 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x3 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x12 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x13 + v6 Imm(0) -> x0 + v7 ParamRef(3, kind=I32) -> x14 + v8 Imm(0) -> x0 + v9 ParamRef(4, kind=I32) -> x15 + v10 Imm(0) -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x0 + v12 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v13 Imm(0) -> x1 + v14 Extend { value=v12, kind=I32 } -> x1 + v15 LoadLocal { off=2, kind=I32 } -> x1 + v16 Binop { op=add, lhs=v12, rhs=v1 } -> x0 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 + v18 Extend { value=v16, kind=I32 } -> x1 + v19 LoadLocal { off=3, kind=I32 } -> x1 + v20 Binop { op=add, lhs=v16, rhs=v3 } -> x0 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x1 + v22 Extend { value=v20, kind=I32 } -> x1 + v23 LoadLocal { off=4, kind=I32 } -> x1 + v24 Binop { op=add, lhs=v20, rhs=v5 } -> x0 + v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x1 + v26 Extend { value=v24, kind=I32 } -> x1 + v27 LoadLocal { off=5, kind=I32 } -> x1 + v28 Binop { op=add, lhs=v24, rhs=v7 } -> x0 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 + v30 Extend { value=v28, kind=I32 } -> x1 + v31 LoadLocal { off=6, kind=I32 } -> x1 + v32 Binop { op=add, lhs=v28, rhs=v9 } -> x0 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 + v34 Extend { value=v32, kind=I32 } -> x0 + terminator Return(v34) (exit_acc=v34) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1) -> x7 + v2 Imm(2) -> x6 + v3 Imm(3) -> x2 + v4 Imm(4) -> x1 + v5 Imm(5) -> x8 + v6 Call { target_pc=1, args=[v1, v2, v3, v4, v5], fixed_args=5, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v6) (exit_acc=v6) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/callee_save_pair_large_frame.ssa b/tests/snapshots/ssa/callee_save_pair_large_frame.ssa new file mode 100644 index 000000000..0421a0f91 --- /dev/null +++ b/tests/snapshots/ssa/callee_save_pair_large_frame.ssa @@ -0,0 +1,120 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=sink +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x3 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 BinopI { op=le, lhs=v1, rhs_imm=0 } -> x0 + terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + block 1 start_pc=0 + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) + block 2 start_pc=0 + v6 LoadLocal { off=2, kind=I32 } -> x0 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 Binop { op=add, lhs=v1, rhs=v10 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=bigframe +fn ent_pc=1 n_params=2 variadic=false locals=102 + spill_count=0 gpr_used=[3, 12] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x3 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x12 + v4 Imm(0) -> x0 + v5 LocalAddr(-100) -> x0 + v6 Imm(0) -> x1 + v7 LoadLocal { off=2, kind=I32 } -> x1 + v8 Store { addr=v5, disp=0, value=v1, kind=I32 } -> - + v9 LocalAddr(-100) -> x0 + v10 Imm(796) -> x1 + v11 BinopI { op=add, lhs=v9, rhs_imm=796 } -> x1 + v12 LoadLocal { off=3, kind=I32 } -> x1 + v13 Store { addr=v9, disp=796, value=v3, kind=I32 } -> - + v14 LocalAddr(-100) -> x0 + v15 Load { addr=v14, disp=0, kind=I32 } -> x7 + v16 Call { target_pc=0, args=[v15], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v17 Imm(0) -> x1 + v18 Extend { value=v16, kind=I32 } -> x1 + v19 LocalAddr(-100) -> x1 + v20 BinopI { op=add, lhs=v19, rhs_imm=796 } -> x2 + v21 Load { addr=v19, disp=796, kind=I32 } -> x1 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x0 + v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x1 + v24 Extend { value=v22, kind=I32 } -> x1 + v25 LoadLocal { off=2, kind=I32 } -> x1 + v26 Binop { op=add, lhs=v22, rhs=v1 } -> x0 + v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x1 + v28 Extend { value=v26, kind=I32 } -> x1 + v29 LoadLocal { off=3, kind=I32 } -> x1 + v30 Binop { op=add, lhs=v26, rhs=v3 } -> x0 + v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x1 + v32 Extend { value=v30, kind=I32 } -> x0 + terminator Return(v32) (exit_acc=v32) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(3) -> x7 + v2 Imm(4) -> x6 + v3 Call { target_pc=1, args=[v1, v2], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v3) (exit_acc=v3) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/case_label_declaration.ssa b/tests/snapshots/ssa/case_label_declaration.ssa index 3572af377..c2fe0b57b 100644 --- a/tests/snapshots/ssa/case_label_declaration.ssa +++ b/tests/snapshots/ssa/case_label_declaration.ssa @@ -7,49 +7,49 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=2, kind=I32 } -> x1 - v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x1 - terminator Bnz { cond=v6, target=b5, fall=b6 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I32 } -> x0 + v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v6, target=b5, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b4:v27, b2:v13, b3:v20], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v8) (exit_acc=v8) + v31 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v31, target=b4, fall=b2 } (exit_acc=v31) block 2 start_pc=0 - v9 Imm(10) -> x1 - v10 Imm(0) -> x2 - v11 LoadLocal { off=-1, kind=I32 } -> x2 - v12 LoadLocal { off=-2, kind=I32 } -> x2 - v13 Binop { op=add, lhs=v3, rhs=v9 } -> x0 - v14 Imm(0) -> x1 - v15 Extend { value=v13, kind=I32 } -> x1 - terminator Jmp(b1) (exit_acc=v15) + v23 Imm(30) -> x0 + v24 Imm(0) -> x0 + v25 LoadLocal { off=-1, kind=I32 } -> x0 + v26 LoadLocal { off=-4, kind=I32 } -> x0 + v27 Imm(30) -> x0 + v28 Imm(0) -> x1 + v29 Imm(30) -> x1 + terminator Jmp(b3) (exit_acc=v29) block 3 start_pc=0 - v16 Imm(20) -> x1 - v17 Imm(0) -> x2 - v18 LoadLocal { off=-1, kind=I32 } -> x2 - v19 LoadLocal { off=-3, kind=I32 } -> x2 - v20 Binop { op=add, lhs=v3, rhs=v16 } -> x0 - v21 Imm(0) -> x1 - v22 Extend { value=v20, kind=I32 } -> x1 - terminator Jmp(b1) (exit_acc=v22) + v7 Phi { incoming=[b2:v27, b6:v13, b4:v20], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v8) (exit_acc=v8) block 4 start_pc=0 - v23 Imm(30) -> x1 - v24 Imm(0) -> x2 - v25 LoadLocal { off=-1, kind=I32 } -> x2 - v26 LoadLocal { off=-4, kind=I32 } -> x2 - v27 Binop { op=add, lhs=v3, rhs=v23 } -> x0 - v28 Imm(0) -> x1 - v29 Extend { value=v27, kind=I32 } -> x1 - terminator Jmp(b1) (exit_acc=v29) + v16 Imm(20) -> x0 + v17 Imm(0) -> x0 + v18 LoadLocal { off=-1, kind=I32 } -> x0 + v19 LoadLocal { off=-3, kind=I32 } -> x0 + v20 Imm(20) -> x0 + v21 Imm(0) -> x1 + v22 Imm(20) -> x1 + terminator Jmp(b3) (exit_acc=v22) block 5 start_pc=0 - v30 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x1 - terminator Bnz { cond=v30, target=b2, fall=b4 } (exit_acc=v30) + v30 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v30, target=b2, fall=b6 } (exit_acc=v30) block 6 start_pc=0 - v31 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x1 - terminator Bnz { cond=v31, target=b3, fall=b4 } (exit_acc=v31) + v9 Imm(10) -> x0 + v10 Imm(0) -> x0 + v11 LoadLocal { off=-1, kind=I32 } -> x0 + v12 LoadLocal { off=-2, kind=I32 } -> x0 + v13 Imm(10) -> x0 + v14 Imm(0) -> x1 + v15 Imm(10) -> x1 + terminator Jmp(b3) (exit_acc=v15) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/cast_abstract_fn_ptr.ssa b/tests/snapshots/ssa/cast_abstract_fn_ptr.ssa index 1e114c401..a40626e3a 100644 --- a/tests/snapshots/ssa/cast_abstract_fn_ptr.ssa +++ b/tests/snapshots/ssa/cast_abstract_fn_ptr.ssa @@ -8,32 +8,32 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v2 ImmData(32) -> x1 v3 Mcpy { dst=v1, src=v2, size=8 } -> x0 v4 Imm(0) -> x0 - v5 Imm(0) -> x1 - v6 LocalAddr(-1) -> x1 - v7 Load { addr=v6, disp=0, kind=I64 } -> x1 - v8 BinopI { op=ne, lhs=v7, rhs_imm=0 } -> x1 + v5 Imm(0) -> x0 + v6 LocalAddr(-1) -> x0 + v7 Load { addr=v6, disp=0, kind=I64 } -> x0 + v8 BinopI { op=ne, lhs=v7, rhs_imm=0 } -> x0 terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v9 Imm(1) -> x0 terminator Return(v9) (exit_acc=v9) block 2 start_pc=0 - v10 ImmData(24) -> x1 - v11 Load { addr=v10, disp=0, kind=I64 } -> x1 - v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x1 + v10 ImmData(24) -> x0 + v11 Load { addr=v10, disp=0, kind=I64 } -> x0 + v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v13 Imm(2) -> x0 terminator Return(v13) (exit_acc=v13) block 4 start_pc=0 - v14 LoadLocal { off=-2, kind=I64 } -> x1 - v15 BinopI { op=ne, lhs=v4, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) + v14 LoadLocal { off=-2, kind=I64 } -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v15) block 5 start_pc=0 - v16 Imm(3) -> x0 - terminator Return(v16) (exit_acc=v16) - block 6 start_pc=0 v17 Imm(0) -> x0 terminator Return(v17) (exit_acc=v17) + block 6 start_pc=0 + v16 Imm(3) -> x0 + terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/char_constant_signedness.ssa b/tests/snapshots/ssa/char_constant_signedness.ssa index 1f0222a63..82b6f680a 100644 --- a/tests/snapshots/ssa/char_constant_signedness.ssa +++ b/tests/snapshots/ssa/char_constant_signedness.ssa @@ -10,36 +10,36 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 v4 Imm(0) -> x0 v5 Load { addr=v1, disp=0, kind=I8 } -> x0 v6 BinopI { op=lt, lhs=v5, rhs_imm=-1 } -> x1 - terminator Bnz { cond=v6, target=b6, fall=b7 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b7, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v15 Imm(0) -> x0 - terminator Return(v15) (exit_acc=v15) + v8 BinopI { op=lt, lhs=v5, rhs_imm=40 } -> x1 + terminator Bnz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) + v10 BinopI { op=eq, lhs=v5, rhs_imm=40 } -> x0 + terminator Bnz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v12 Imm(2) -> x0 - terminator Return(v12) (exit_acc=v12) + v14 Imm(0) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 v13 Imm(3) -> x0 terminator Return(v13) (exit_acc=v13) block 5 start_pc=0 - v14 Imm(0) -> x0 - terminator Return(v14) (exit_acc=v14) + v9 BinopI { op=eq, lhs=v5, rhs_imm=-1 } -> x0 + terminator Bz { cond=v9, target=b3, fall=b6 } (exit_acc=v9) block 6 start_pc=0 - v7 BinopI { op=eq, lhs=v5, rhs_imm=-128 } -> x0 - terminator Bnz { cond=v7, target=b2, fall=b5 } (exit_acc=v7) + v12 Imm(2) -> x0 + terminator Return(v12) (exit_acc=v12) block 7 start_pc=0 - v8 BinopI { op=lt, lhs=v5, rhs_imm=40 } -> x1 - terminator Bnz { cond=v8, target=b8, fall=b9 } (exit_acc=v8) + v7 BinopI { op=eq, lhs=v5, rhs_imm=-128 } -> x0 + terminator Bz { cond=v7, target=b3, fall=b8 } (exit_acc=v7) block 8 start_pc=0 - v9 BinopI { op=eq, lhs=v5, rhs_imm=-1 } -> x0 - terminator Bnz { cond=v9, target=b3, fall=b5 } (exit_acc=v9) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 9 start_pc=0 - v10 BinopI { op=eq, lhs=v5, rhs_imm=40 } -> x0 - terminator Bnz { cond=v10, target=b4, fall=b5 } (exit_acc=v10) + v15 Imm(0) -> x0 + terminator Return(v15) (exit_acc=v15) block 10 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=4 @@ -49,25 +49,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v1 Imm(128) -> x0 v2 Imm(-9223372036854775808) -> x0 v3 Imm(-128) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I8 } -> x1 - v6 BinopI { op=ne, lhs=v3, rhs_imm=-128 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I8 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 Imm(255) -> x0 v9 Imm(-72057594037927936) -> x0 v10 Imm(-1) -> x0 - v11 Imm(0) -> x1 - v12 LoadLocal { off=-2, kind=I8 } -> x1 - v13 BinopI { op=ne, lhs=v10, rhs_imm=-1 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) - block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) - block 4 start_pc=0 + v11 Imm(0) -> x0 + v12 LoadLocal { off=-2, kind=I8 } -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) + block 2 start_pc=0 v15 LocalAddr(-3) -> x0 v16 Imm(0) -> x1 v17 Imm(128) -> x1 @@ -77,11 +71,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v21 LocalAddr(-3) -> x7 v22 Call { target_pc=0, args=[v21], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v23 BinopI { op=ne, lhs=v22, rhs_imm=1 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) - block 5 start_pc=0 + terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + block 3 start_pc=0 v24 Imm(3) -> x0 terminator Return(v24) (exit_acc=v24) - block 6 start_pc=0 + block 4 start_pc=0 v25 LocalAddr(-3) -> x0 v26 Imm(0) -> x1 v27 Imm(255) -> x1 @@ -91,13 +85,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v31 LocalAddr(-3) -> x7 v32 Call { target_pc=0, args=[v31], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=2 } -> x0 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) - block 7 start_pc=0 + terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + block 5 start_pc=0 v34 Imm(4) -> x0 terminator Return(v34) (exit_acc=v34) - block 8 start_pc=0 + block 6 start_pc=0 v35 Imm(0) -> x0 terminator Return(v35) (exit_acc=v35) + block 7 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 8 start_pc=0 + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/char_limits_consistency.ssa b/tests/snapshots/ssa/char_limits_consistency.ssa index bcb4578d9..081fe1f87 100644 --- a/tests/snapshots/ssa/char_limits_consistency.ssa +++ b/tests/snapshots/ssa/char_limits_consistency.ssa @@ -7,55 +7,55 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v1 Imm(255) -> x0 v2 Imm(-72057594037927936) -> x0 v3 Imm(-1) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I8 } -> x1 - v6 BinopI { op=lt, lhs=v3, rhs_imm=0 } -> x0 - terminator Bz { cond=v6, target=b3, fall=b1 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I8 } -> x0 + v6 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 v7 Imm(0) -> x1 v8 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) + terminator Jmp(b2) (exit_acc=v7) block 2 start_pc=0 - v9 Imm(0) -> x0 - terminator Return(v9) (exit_acc=v9) - block 3 start_pc=0 - v10 Imm(1) -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v10) - block 4 start_pc=0 v12 Imm(0) -> x1 v13 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v12) - block 5 start_pc=0 - v14 Phi { incoming=[b1:v7, b4:v12], kind=I64 } -> x1 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 + v14 Phi { incoming=[b1:v7, b2:v12], kind=I64 } -> x1 v15 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v14, target=b7, fall=b6 } (exit_acc=v14) - block 6 start_pc=0 + terminator Bz { cond=v14, target=b5, fall=b4 } (exit_acc=v14) + block 4 start_pc=0 v16 Imm(1) -> x0 terminator Return(v16) (exit_acc=v16) - block 7 start_pc=0 + block 5 start_pc=0 v17 Imm(0) -> x1 v18 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v17) - block 8 start_pc=0 + terminator Jmp(b6) (exit_acc=v17) + block 6 start_pc=0 v19 Imm(0) -> x1 v20 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v19) - block 9 start_pc=0 - v21 Phi { incoming=[b7:v17, b8:v19], kind=I64 } -> x1 + terminator Jmp(b7) (exit_acc=v19) + block 7 start_pc=0 + v21 Phi { incoming=[b5:v17, b6:v19], kind=I64 } -> x1 v22 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b11, fall=b10 } (exit_acc=v21) - block 10 start_pc=0 + terminator Bz { cond=v21, target=b9, fall=b8 } (exit_acc=v21) + block 8 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) + block 9 start_pc=0 + v9 Imm(0) -> x0 + terminator Return(v9) (exit_acc=v9) + block 10 start_pc=0 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v10) block 11 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b9) block 12 start_pc=0 v24 Imm(1) -> x1 v25 Imm(0) -> x0 terminator Jmp(b13) (exit_acc=v24) block 13 start_pc=0 - v26 Phi { incoming=[b3:v10, b12:v24], kind=I64 } -> x1 + v26 Phi { incoming=[b10:v10, b12:v24], kind=I64 } -> x1 v27 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v26, target=b15, fall=b14 } (exit_acc=v26) block 14 start_pc=0 @@ -72,12 +72,12 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 block 17 start_pc=0 v33 Phi { incoming=[b15:v29, b16:v31], kind=I64 } -> x1 v34 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v33, target=b19, fall=b18 } (exit_acc=v33) + terminator Bz { cond=v33, target=b9, fall=b18 } (exit_acc=v33) block 18 start_pc=0 v35 Imm(4) -> x0 terminator Return(v35) (exit_acc=v35) block 19 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b9) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/clock_monotonic_advances.ssa b/tests/snapshots/ssa/clock_monotonic_advances.ssa index 0a14025a6..15521bb71 100644 --- a/tests/snapshots/ssa/clock_monotonic_advances.ssa +++ b/tests/snapshots/ssa/clock_monotonic_advances.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=5 --- ; name=main fn ent_pc=5 n_params=0 variadic=false locals=11 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-2) -> x0 @@ -21,18 +21,18 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 block 2 start_pc=0 v12 LocalAddr(-2) -> x0 v13 Load { addr=v12, disp=0, kind=I64 } -> x0 - v14 BinopI { op=eq, lhs=v13, rhs_imm=-1 } -> x3 + v14 BinopI { op=eq, lhs=v13, rhs_imm=-1 } -> x1 v15 Imm(0) -> x0 - terminator Bz { cond=v14, target=b25, fall=b3 } (exit_acc=v14) + terminator Bz { cond=v14, target=b27, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v16 LocalAddr(-2) -> x0 v17 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x1 v18 Load { addr=v16, disp=8, kind=I64 } -> x0 - v19 BinopI { op=eq, lhs=v18, rhs_imm=-1 } -> x3 + v19 BinopI { op=eq, lhs=v18, rhs_imm=-1 } -> x1 v20 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v19) block 4 start_pc=0 - v21 Phi { incoming=[b25:v14, b3:v19], kind=I64 } -> x3 + v21 Phi { incoming=[b27:v14, b3:v19], kind=I64 } -> x1 v22 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) block 5 start_pc=0 @@ -50,18 +50,18 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 v28 LocalAddr(-2) -> x0 v29 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x1 v30 Load { addr=v28, disp=8, kind=I64 } -> x0 - v31 BinopI { op=lt, lhs=v30, rhs_imm=0 } -> x3 + v31 BinopI { op=lt, lhs=v30, rhs_imm=0 } -> x1 v32 Imm(0) -> x0 terminator Bnz { cond=v31, target=b26, fall=b9 } (exit_acc=v31) block 9 start_pc=0 v33 LocalAddr(-2) -> x0 v34 BinopI { op=add, lhs=v33, rhs_imm=8 } -> x1 v35 Load { addr=v33, disp=8, kind=I64 } -> x0 - v36 BinopI { op=ge, lhs=v35, rhs_imm=1000000000 } -> x3 + v36 BinopI { op=ge, lhs=v35, rhs_imm=1000000000 } -> x1 v37 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v36) block 10 start_pc=0 - v38 Phi { incoming=[b26:v31, b9:v36], kind=I64 } -> x3 + v38 Phi { incoming=[b26:v31, b9:v36], kind=I64 } -> x1 v39 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v38, target=b12, fall=b11 } (exit_acc=v38) block 11 start_pc=0 @@ -71,24 +71,24 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 v41 Imm(0) -> x1 v42 StoreLocal { off=-5, value=v41, kind=I32, volatile } -> - v43 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v41) + terminator Jmp(b15) (exit_acc=v41) block 13 start_pc=0 - v44 Phi { incoming=[b12:v41, b14:v48], kind=I64 } -> x1 - v45 Extend { value=v44, kind=I32 } -> x0 - v46 BinopI { op=lt, lhs=v45, rhs_imm=1000000 } -> x0 - terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) + v50 LoadLocal { off=-5, kind=I32, volatile } -> x2 + v51 BinopI { op=add, lhs=v50, rhs_imm=1 } -> x2 + v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x6 + v53 Extend { value=v51, kind=I32 } -> x6 + v54 StoreLocal { off=-5, value=v51, kind=I32, volatile } -> - + terminator Jmp(b14) (exit_acc=v54) block 14 start_pc=0 - v47 Extend { value=v44, kind=I32 } -> x0 - v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x1 + v47 Extend { value=v44, kind=I32 } -> x1 + v48 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x1 v49 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v48) + terminator Jmp(b15) (exit_acc=v48) block 15 start_pc=0 - v50 LoadLocal { off=-5, kind=I32, volatile } -> x0 - v51 BinopI { op=add, lhs=v50, rhs_imm=1 } -> x0 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x2 - v53 Extend { value=v51, kind=I32 } -> x2 - v54 StoreLocal { off=-5, value=v51, kind=I32, volatile } -> - - terminator Jmp(b14) (exit_acc=v54) + v44 Phi { incoming=[b12:v41, b14:v48], kind=I64 } -> x1 + v45 Extend { value=v44, kind=I32 } -> x0 + v46 BinopI { op=lt, lhs=v45, rhs_imm=1000000 } -> x2 + terminator Bnz { cond=v46, target=b13, fall=b16 } (exit_acc=v46) block 16 start_pc=0 v55 Imm(1) -> x7 v56 LocalAddr(-4) -> x6 @@ -115,7 +115,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 v69 Load { addr=v68, disp=0, kind=I64 } -> x1 v70 Binop { op=eq, lhs=v67, rhs=v69 } -> x1 v71 Imm(0) -> x0 - terminator Bz { cond=v70, target=b27, fall=b21 } (exit_acc=v70) + terminator Bz { cond=v70, target=b25, fall=b21 } (exit_acc=v70) block 21 start_pc=0 v72 LocalAddr(-4) -> x0 v73 BinopI { op=add, lhs=v72, rhs_imm=8 } -> x1 @@ -127,7 +127,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 v79 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v78) block 22 start_pc=0 - v80 Phi { incoming=[b27:v70, b21:v78], kind=I64 } -> x1 + v80 Phi { incoming=[b25:v70, b21:v78], kind=I64 } -> x1 v81 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v80, target=b24, fall=b23 } (exit_acc=v80) block 23 start_pc=0 @@ -137,11 +137,11 @@ fn ent_pc=5 n_params=0 variadic=false locals=11 v83 Imm(0) -> x0 terminator Return(v83) (exit_acc=v83) block 25 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b22) block 26 start_pc=0 terminator Jmp(b10) block 27 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/comma_operator_in_loops.ssa b/tests/snapshots/ssa/comma_operator_in_loops.ssa index d901b7092..502d806bf 100644 --- a/tests/snapshots/ssa/comma_operator_in_loops.ssa +++ b/tests/snapshots/ssa/comma_operator_in_loops.ssa @@ -50,71 +50,91 @@ fn ent_pc=7 n_params=0 variadic=false locals=3 v20 Call { target_pc=6, args=[v19], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v21 Imm(2) -> x0 v22 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v22) + terminator Jmp(b6) (exit_acc=v22) block 6 start_pc=0 - v23 Phi { incoming=[b9:v35, b7:v27, b8:v31], kind=I64 } -> x3 - v24 Imm(0) -> x12 - v25 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v24) + v39 Imm(1) -> x0 + terminator Jmp(b7) (exit_acc=v39) block 7 start_pc=0 - v26 Extend { value=v18, kind=I32 } -> x0 - v27 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x3 - v28 Imm(0) -> x0 - v29 Extend { value=v27, kind=I32 } -> x0 - terminator Jmp(b6) (exit_acc=v29) - block 8 start_pc=0 v30 Extend { value=v18, kind=I32 } -> x0 v31 BinopI { op=add, lhs=v18, rhs_imm=1000 } -> x3 v32 Imm(0) -> x0 v33 Extend { value=v31, kind=I32 } -> x0 - terminator Jmp(b6) (exit_acc=v33) + terminator Jmp(b8) (exit_acc=v33) + block 8 start_pc=0 + v23 Phi { incoming=[b14:v35, b13:v27, b7:v31], kind=I64 } -> x3 + v24 Imm(0) -> x0 + v25 Imm(0) -> x1 + terminator Jmp(b9) (exit_acc=v24) block 9 start_pc=0 - v34 Extend { value=v18, kind=I32 } -> x0 - v35 BinopI { op=add, lhs=v18, rhs_imm=99999 } -> x3 - v36 Imm(0) -> x0 - v37 Extend { value=v35, kind=I32 } -> x0 - terminator Jmp(b6) (exit_acc=v37) + v40 Imm(0) -> x7 + v41 Call { target_pc=6, args=[v40], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v42 Imm(0) -> x0 + v43 Imm(1) -> x0 + v44 Extend { value=v23, kind=I32 } -> x0 + v45 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x3 + v46 Imm(0) -> x0 + v47 Extend { value=v45, kind=I32 } -> x0 + v48 Imm(0) -> x0 + v49 Imm(1) -> x0 + v50 Imm(0) -> x0 + v51 Imm(0) -> x7 + v52 Call { target_pc=6, args=[v51], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v53 Imm(1) -> x0 + v54 Imm(1) -> x0 + v55 Extend { value=v45, kind=I32 } -> x0 + v56 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x3 + v57 Imm(0) -> x0 + v58 Extend { value=v56, kind=I32 } -> x0 + v59 Imm(1) -> x0 + v60 Imm(2) -> x0 + v61 Imm(0) -> x0 + v62 Imm(0) -> x7 + v63 Call { target_pc=6, args=[v62], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v64 Imm(2) -> x0 + v65 Imm(1) -> x0 + v66 Extend { value=v56, kind=I32 } -> x0 + v67 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x3 + v68 Imm(0) -> x0 + v69 Extend { value=v67, kind=I32 } -> x0 + v70 Imm(2) -> x0 + v71 Imm(3) -> x0 + v72 Imm(0) -> x0 + v73 Imm(0) -> x7 + v74 Call { target_pc=6, args=[v73], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v75 Imm(3) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v76) block 10 start_pc=0 - v38 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v38) + v77 ImmData(40) -> x0 + v78 Load { addr=v77, disp=0, kind=I32 } -> x0 + v79 BinopI { op=ne, lhs=v78, rhs_imm=7 } -> x0 + terminator Bz { cond=v79, target=b12, fall=b11 } (exit_acc=v79) block 11 start_pc=0 - v39 Imm(1) -> x0 - terminator Jmp(b8) (exit_acc=v39) + v80 Imm(1) -> x0 + terminator Return(v80) (exit_acc=v80) block 12 start_pc=0 - terminator Jmp(b7) + v81 Extend { value=v67, kind=I32 } -> x0 + v82 BinopI { op=sub, lhs=v67, rhs_imm=1110 } -> x0 + v83 BinopI { op=shl, lhs=v82, rhs_imm=32 } -> x1 + v84 Extend { value=v82, kind=I32 } -> x0 + terminator Return(v84) (exit_acc=v84) block 13 start_pc=0 - v40 Phi { incoming=[b6:v23, b14:v50], kind=I64 } -> x3 - v41 Phi { incoming=[b6:v24, b14:v47], kind=I64 } -> x12 - v42 Imm(0) -> x7 - v43 Call { target_pc=6, args=[v42], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v44 Extend { value=v41, kind=I32 } -> x0 - v45 BinopI { op=lt, lhs=v44, rhs_imm=3 } -> x0 - terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) + v26 Extend { value=v18, kind=I32 } -> x0 + v27 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x3 + v28 Imm(0) -> x0 + v29 Extend { value=v27, kind=I32 } -> x0 + terminator Jmp(b8) (exit_acc=v29) block 14 start_pc=0 - v46 Extend { value=v41, kind=I32 } -> x0 - v47 BinopI { op=add, lhs=v46, rhs_imm=1 } -> x12 - v48 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v47) + v34 Extend { value=v18, kind=I32 } -> x0 + v35 BinopI { op=add, lhs=v18, rhs_imm=99999 } -> x3 + v36 Imm(0) -> x0 + v37 Extend { value=v35, kind=I32 } -> x0 + terminator Jmp(b8) (exit_acc=v37) block 15 start_pc=0 - v49 Extend { value=v40, kind=I32 } -> x0 - v50 BinopI { op=add, lhs=v40, rhs_imm=1 } -> x3 - v51 Imm(0) -> x0 - v52 Extend { value=v50, kind=I32 } -> x0 - terminator Jmp(b14) (exit_acc=v52) + v38 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v38) block 16 start_pc=0 - v53 ImmData(40) -> x0 - v54 Load { addr=v53, disp=0, kind=I32 } -> x0 - v55 BinopI { op=ne, lhs=v54, rhs_imm=7 } -> x0 - terminator Bz { cond=v55, target=b18, fall=b17 } (exit_acc=v55) - block 17 start_pc=0 - v56 Imm(1) -> x0 - terminator Return(v56) (exit_acc=v56) - block 18 start_pc=0 - v57 Extend { value=v40, kind=I32 } -> x0 - v58 BinopI { op=sub, lhs=v40, rhs_imm=1110 } -> x0 - v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x1 - v60 Extend { value=v58, kind=I32 } -> x0 - terminator Return(v60) (exit_acc=v60) + terminator Jmp(b13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/commutative_imm_lhs_swap.ssa b/tests/snapshots/ssa/commutative_imm_lhs_swap.ssa index 89a6ef5c3..ff699c3c9 100644 --- a/tests/snapshots/ssa/commutative_imm_lhs_swap.ssa +++ b/tests/snapshots/ssa/commutative_imm_lhs_swap.ssa @@ -5,96 +5,96 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Imm(0) -> x1 - v3 Imm(4) -> x1 - v4 LoadLocal { off=-1, kind=I32 } -> x1 - v5 BinopI { op=shl, lhs=v1, rhs_imm=2 } -> x1 - v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x2 - v7 Extend { value=v5, kind=I32 } -> x1 - v8 BinopI { op=ne, lhs=v7, rhs_imm=28 } -> x1 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v2 Imm(0) -> x0 + v3 Imm(4) -> x0 + v4 LoadLocal { off=-1, kind=I32 } -> x0 + v5 Imm(28) -> x0 + v6 Imm(120259084288) -> x0 + v7 Imm(28) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 - v9 Imm(1) -> x0 - terminator Return(v9) (exit_acc=v9) + v10 Imm(3) -> x0 + v11 LoadLocal { off=-1, kind=I32 } -> x0 + v12 Imm(10) -> x0 + v13 Imm(42949672960) -> x0 + v14 Imm(10) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v10 Imm(3) -> x1 - v11 LoadLocal { off=-1, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v1, rhs_imm=3 } -> x1 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x2 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 BinopI { op=ne, lhs=v14, rhs_imm=10 } -> x1 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v17 Imm(240) -> x0 + v18 LoadLocal { off=-1, kind=I32 } -> x0 + v19 Imm(0) -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v20) block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v22 Imm(16) -> x0 + v23 LoadLocal { off=-1, kind=I32 } -> x0 + v24 Imm(23) -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v25) block 4 start_pc=0 - v17 Imm(240) -> x1 - v18 LoadLocal { off=-1, kind=I32 } -> x1 - v19 BinopI { op=and, lhs=v1, rhs_imm=240 } -> x1 - v20 BinopI { op=ne, lhs=v19, rhs_imm=0 } -> x1 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) + v27 Imm(255) -> x0 + v28 LoadLocal { off=-1, kind=I32 } -> x0 + v29 Imm(248) -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v30) block 5 start_pc=0 - v21 Imm(3) -> x0 - terminator Return(v21) (exit_acc=v21) + v32 Imm(1) -> x0 + v33 LoadLocal { off=-1, kind=I32 } -> x0 + v34 Imm(0) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v22 Imm(16) -> x1 - v23 LoadLocal { off=-1, kind=I32 } -> x1 - v24 BinopI { op=or, lhs=v1, rhs_imm=16 } -> x1 - v25 BinopI { op=ne, lhs=v24, rhs_imm=23 } -> x1 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) + v37 Imm(1) -> x0 + v38 LoadLocal { off=-1, kind=I32 } -> x0 + v39 Imm(1) -> x0 + v40 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v40) block 7 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) + v42 Imm(10) -> x0 + v43 LoadLocal { off=-1, kind=I32 } -> x0 + v44 Imm(3) -> x0 + v45 Imm(12884901888) -> x0 + v46 Imm(3) -> x0 + v47 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v47) block 8 start_pc=0 - v27 Imm(255) -> x1 - v28 LoadLocal { off=-1, kind=I32 } -> x1 - v29 BinopI { op=xor, lhs=v1, rhs_imm=255 } -> x1 - v30 BinopI { op=ne, lhs=v29, rhs_imm=248 } -> x1 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v49 Imm(8) -> x0 + v50 LoadLocal { off=-1, kind=I32 } -> x0 + v51 Imm(1) -> x0 + v52 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v52) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v54 Imm(0) -> x0 + terminator Return(v54) (exit_acc=v54) block 10 start_pc=0 - v32 Imm(1) -> x1 - v33 LoadLocal { off=-1, kind=I32 } -> x1 - v34 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x1 - v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x1 - terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 11 start_pc=0 - v36 Imm(6) -> x0 - terminator Return(v36) (exit_acc=v36) + v16 Imm(2) -> x0 + terminator Return(v16) (exit_acc=v16) block 12 start_pc=0 - v37 Imm(1) -> x1 - v38 LoadLocal { off=-1, kind=I32 } -> x1 - v39 BinopI { op=ne, lhs=v1, rhs_imm=1 } -> x1 - v40 BinopI { op=ne, lhs=v39, rhs_imm=1 } -> x1 - terminator Bz { cond=v40, target=b14, fall=b13 } (exit_acc=v40) + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) block 13 start_pc=0 - v41 Imm(7) -> x0 - terminator Return(v41) (exit_acc=v41) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) block 14 start_pc=0 - v42 Imm(10) -> x1 - v43 LoadLocal { off=-1, kind=I32 } -> x2 - v44 Binop { op=sub, lhs=v42, rhs=v1 } -> x1 - v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x2 - v46 Extend { value=v44, kind=I32 } -> x1 - v47 BinopI { op=ne, lhs=v46, rhs_imm=3 } -> x1 - terminator Bz { cond=v47, target=b16, fall=b15 } (exit_acc=v47) + v31 Imm(5) -> x0 + terminator Return(v31) (exit_acc=v31) block 15 start_pc=0 - v48 Imm(8) -> x0 - terminator Return(v48) (exit_acc=v48) + v36 Imm(6) -> x0 + terminator Return(v36) (exit_acc=v36) block 16 start_pc=0 - v49 Imm(8) -> x1 - v50 LoadLocal { off=-1, kind=I32 } -> x1 - v51 BinopI { op=lt, lhs=v1, rhs_imm=8 } -> x0 - v52 BinopI { op=eq, lhs=v51, rhs_imm=0 } -> x0 - terminator Bz { cond=v52, target=b18, fall=b17 } (exit_acc=v52) + v41 Imm(7) -> x0 + terminator Return(v41) (exit_acc=v41) block 17 start_pc=0 + v48 Imm(8) -> x0 + terminator Return(v48) (exit_acc=v48) + block 18 start_pc=0 v53 Imm(9) -> x0 terminator Return(v53) (exit_acc=v53) - block 18 start_pc=0 - v54 Imm(0) -> x0 - terminator Return(v54) (exit_acc=v54) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/comparison_imm_lhs_swap.ssa b/tests/snapshots/ssa/comparison_imm_lhs_swap.ssa index c25633920..e34c46895 100644 --- a/tests/snapshots/ssa/comparison_imm_lhs_swap.ssa +++ b/tests/snapshots/ssa/comparison_imm_lhs_swap.ssa @@ -1,167 +1,151 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(5) -> x3 + v1 Imm(5) -> x0 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - v4 Imm(0) -> x12 + v4 Imm(0) -> x3 v5 Imm(0) -> x0 v6 LoadLocal { off=-1, kind=I32 } -> x0 - v7 BinopI { op=gt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v7, target=b24, fall=b1 } (exit_acc=v7) + v7 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 v8 LoadLocal { off=-3, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x0 - v10 BinopI { op=shl, lhs=v9, rhs_imm=32 } -> x1 - v11 Extend { value=v9, kind=I32 } -> x12 + v9 Imm(1) -> x0 + v10 Imm(4294967296) -> x0 + v11 Imm(1) -> x3 v12 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v13 Phi { incoming=[b24:v4, b1:v11], kind=I64 } -> x12 + v13 Phi { incoming=[b0:v4, b1:v11], kind=I64 } -> x3 v14 Imm(0) -> x0 v15 LoadLocal { off=-1, kind=I32 } -> x0 - v16 BinopI { op=ge, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v16, target=b25, fall=b3 } (exit_acc=v16) + v16 Imm(1) -> x0 + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 v17 Extend { value=v13, kind=I32 } -> x0 v18 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x0 v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x12 + v20 Extend { value=v18, kind=I32 } -> x3 v21 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v20) block 4 start_pc=0 - v22 Phi { incoming=[b25:v13, b3:v20], kind=I64 } -> x12 + v22 Phi { incoming=[b2:v13, b3:v20], kind=I64 } -> x3 v23 Imm(10) -> x0 v24 LoadLocal { off=-1, kind=I32 } -> x0 - v25 BinopI { op=lt, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v25, target=b26, fall=b5 } (exit_acc=v25) + v25 Imm(1) -> x0 + terminator Jmp(b5) (exit_acc=v25) block 5 start_pc=0 v26 Extend { value=v22, kind=I32 } -> x0 v27 BinopI { op=add, lhs=v22, rhs_imm=1 } -> x0 v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 - v29 Extend { value=v27, kind=I32 } -> x12 + v29 Extend { value=v27, kind=I32 } -> x3 v30 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v29) block 6 start_pc=0 - v31 Phi { incoming=[b26:v22, b5:v29], kind=I64 } -> x12 + v31 Phi { incoming=[b4:v22, b5:v29], kind=I64 } -> x3 v32 Imm(10) -> x0 v33 LoadLocal { off=-1, kind=I32 } -> x0 - v34 BinopI { op=le, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v34, target=b27, fall=b7 } (exit_acc=v34) + v34 Imm(1) -> x0 + terminator Jmp(b7) (exit_acc=v34) block 7 start_pc=0 v35 Extend { value=v31, kind=I32 } -> x0 v36 BinopI { op=add, lhs=v31, rhs_imm=1 } -> x0 v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 - v38 Extend { value=v36, kind=I32 } -> x12 + v38 Extend { value=v36, kind=I32 } -> x3 v39 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v38) block 8 start_pc=0 - v40 Phi { incoming=[b27:v31, b7:v38], kind=I64 } -> x12 + v40 Phi { incoming=[b6:v31, b7:v38], kind=I64 } -> x3 v41 Imm(0) -> x0 v42 LoadLocal { off=-2, kind=U32 } -> x0 - v43 BinopI { op=ugt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b28, fall=b9 } (exit_acc=v43) + v43 Imm(1) -> x0 + terminator Jmp(b9) (exit_acc=v43) block 9 start_pc=0 v44 Extend { value=v40, kind=I32 } -> x0 v45 BinopI { op=add, lhs=v40, rhs_imm=1 } -> x0 v46 BinopI { op=shl, lhs=v45, rhs_imm=32 } -> x1 - v47 Extend { value=v45, kind=I32 } -> x12 + v47 Extend { value=v45, kind=I32 } -> x3 v48 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v47) block 10 start_pc=0 - v49 Phi { incoming=[b28:v40, b9:v47], kind=I64 } -> x12 + v49 Phi { incoming=[b8:v40, b9:v47], kind=I64 } -> x3 v50 Imm(0) -> x0 v51 LoadLocal { off=-2, kind=U32 } -> x0 - v52 BinopI { op=uge, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v52, target=b29, fall=b11 } (exit_acc=v52) + v52 Imm(1) -> x0 + terminator Jmp(b11) (exit_acc=v52) block 11 start_pc=0 v53 Extend { value=v49, kind=I32 } -> x0 v54 BinopI { op=add, lhs=v49, rhs_imm=1 } -> x0 v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x1 - v56 Extend { value=v54, kind=I32 } -> x12 + v56 Extend { value=v54, kind=I32 } -> x3 v57 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v56) block 12 start_pc=0 - v58 Phi { incoming=[b29:v49, b11:v56], kind=I64 } -> x12 + v58 Phi { incoming=[b10:v49, b11:v56], kind=I64 } -> x3 v59 Imm(10) -> x0 v60 LoadLocal { off=-2, kind=U32 } -> x0 - v61 BinopI { op=ult, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v61, target=b30, fall=b13 } (exit_acc=v61) + v61 Imm(1) -> x0 + terminator Jmp(b13) (exit_acc=v61) block 13 start_pc=0 v62 Extend { value=v58, kind=I32 } -> x0 v63 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x0 v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x1 - v65 Extend { value=v63, kind=I32 } -> x12 + v65 Extend { value=v63, kind=I32 } -> x3 v66 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v65) block 14 start_pc=0 - v67 Phi { incoming=[b30:v58, b13:v65], kind=I64 } -> x12 + v67 Phi { incoming=[b12:v58, b13:v65], kind=I64 } -> x3 v68 Imm(10) -> x0 v69 LoadLocal { off=-2, kind=U32 } -> x0 - v70 BinopI { op=ule, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v70, target=b31, fall=b15 } (exit_acc=v70) + v70 Imm(1) -> x0 + terminator Jmp(b15) (exit_acc=v70) block 15 start_pc=0 v71 Extend { value=v67, kind=I32 } -> x0 v72 BinopI { op=add, lhs=v67, rhs_imm=1 } -> x0 v73 BinopI { op=shl, lhs=v72, rhs_imm=32 } -> x1 - v74 Extend { value=v72, kind=I32 } -> x12 + v74 Extend { value=v72, kind=I32 } -> x3 v75 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v74) block 16 start_pc=0 - v76 Phi { incoming=[b31:v67, b15:v74], kind=I64 } -> x12 + v76 Phi { incoming=[b14:v67, b15:v74], kind=I64 } -> x3 v77 Imm(10) -> x0 v78 LoadLocal { off=-1, kind=I32 } -> x0 - v79 BinopI { op=gt, lhs=v1, rhs_imm=10 } -> x0 - terminator Bz { cond=v79, target=b18, fall=b17 } (exit_acc=v79) + v79 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v79) block 17 start_pc=0 - v80 Imm(1) -> x0 - terminator Return(v80) (exit_acc=v80) - block 18 start_pc=0 v81 Imm(0) -> x0 v82 LoadLocal { off=-1, kind=I32 } -> x0 - v83 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v83, target=b20, fall=b19 } (exit_acc=v83) - block 19 start_pc=0 - v84 Imm(2) -> x0 - terminator Return(v84) (exit_acc=v84) - block 20 start_pc=0 + v83 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v83) + block 18 start_pc=0 v85 ImmData(36) -> x7 v86 Extend { value=v76, kind=I32 } -> x6 v87 CallExt { binding_idx=0, args=[v85, v86], fp_arg_mask=0x0 } -> x0 v88 Extend { value=v76, kind=I32 } -> x0 v89 BinopI { op=eq, lhs=v88, rhs_imm=8 } -> x0 - terminator Bz { cond=v89, target=b22, fall=b21 } (exit_acc=v89) - block 21 start_pc=0 + terminator Bz { cond=v89, target=b21, fall=b19 } (exit_acc=v89) + block 19 start_pc=0 v90 Imm(0) -> x1 v91 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v90) - block 22 start_pc=0 + terminator Jmp(b20) (exit_acc=v90) + block 20 start_pc=0 + v94 Phi { incoming=[b19:v90, b21:v92], kind=I64 } -> x1 + v95 LoadLocal { off=-6, kind=I64 } -> x0 + terminator Return(v94) (exit_acc=v94) + block 21 start_pc=0 v92 Imm(3) -> x1 v93 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v92) + terminator Jmp(b20) (exit_acc=v92) + block 22 start_pc=0 + v80 Imm(1) -> x0 + terminator Return(v80) (exit_acc=v80) block 23 start_pc=0 - v94 Phi { incoming=[b21:v90, b22:v92], kind=I64 } -> x1 - v95 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Return(v94) (exit_acc=v94) - block 24 start_pc=0 - terminator Jmp(b2) - block 25 start_pc=0 - terminator Jmp(b4) - block 26 start_pc=0 - terminator Jmp(b6) - block 27 start_pc=0 - terminator Jmp(b8) - block 28 start_pc=0 - terminator Jmp(b10) - block 29 start_pc=0 - terminator Jmp(b12) - block 30 start_pc=0 - terminator Jmp(b14) - block 31 start_pc=0 - terminator Jmp(b16) + v84 Imm(2) -> x0 + terminator Return(v84) (exit_acc=v84) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/complement_preserves_type.ssa b/tests/snapshots/ssa/complement_preserves_type.ssa index 96c9042b3..9ec71e7d5 100644 --- a/tests/snapshots/ssa/complement_preserves_type.ssa +++ b/tests/snapshots/ssa/complement_preserves_type.ssa @@ -7,81 +7,79 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v1 Imm(0) -> x0 v2 Imm(-1) -> x0 v3 Imm(9223372036854775807) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I64 } -> x1 - v6 BinopI { op=ne, lhs=v3, rhs_imm=9223372036854775807 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I64 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 Imm(0) -> x0 - v9 Imm(0) -> x1 - v10 LoadLocal { off=-2, kind=I64 } -> x1 - v11 BinopI { op=xor, lhs=v8, rhs_imm=-1 } -> x0 - v12 BinopI { op=shru, lhs=v11, rhs_imm=1 } -> x0 - v13 BinopI { op=ne, lhs=v12, rhs_imm=9223372036854775807 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v9 Imm(0) -> x0 + v10 LoadLocal { off=-2, kind=I64 } -> x0 + v11 Imm(-1) -> x0 + v12 Imm(9223372036854775807) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) + block 2 start_pc=0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + v17 LoadLocal { off=-3, kind=U32 } -> x0 + v18 Imm(-1) -> x0 + v19 Imm(4294967295) -> x0 + v20 Imm(2147483647) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v21) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v23 Imm(0) -> x0 + v24 Imm(-1) -> x1 + terminator Jmp(b4) (exit_acc=v23) block 4 start_pc=0 - v15 Imm(0) -> x0 - v16 Imm(0) -> x1 - v17 LoadLocal { off=-3, kind=U32 } -> x1 - v18 BinopI { op=xor, lhs=v15, rhs_imm=-1 } -> x0 - v19 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 - v20 BinopI { op=shru, lhs=v19, rhs_imm=1 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=2147483647 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) + v26 Imm(-1) -> x0 + v27 Imm(0) -> x0 + v28 LoadLocal { off=-4, kind=I64 } -> x0 + v29 Imm(0) -> x1 + v30 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v29) block 5 start_pc=0 - v22 Imm(3) -> x0 - terminator Return(v22) (exit_acc=v22) + v31 LoadLocal { off=-4, kind=I64 } -> x0 + v32 Imm(-1) -> x0 + v33 Imm(0) -> x1 + v34 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v33) block 6 start_pc=0 - v23 Imm(0) -> x0 - v24 Imm(-1) -> x1 - terminator Jmp(b8) (exit_acc=v23) + v35 Phi { incoming=[b4:v29, b5:v33], kind=I64 } -> x1 + v36 LoadLocal { off=-6, kind=I64 } -> x0 + terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) block 7 start_pc=0 - v25 Imm(4) -> x0 - terminator Return(v25) (exit_acc=v25) + v37 Imm(5) -> x0 + terminator Return(v37) (exit_acc=v37) block 8 start_pc=0 - v26 Imm(-1) -> x0 - v27 Imm(0) -> x1 - v28 LoadLocal { off=-4, kind=I64 } -> x1 - v29 BinopI { op=ne, lhs=v26, rhs_imm=-1 } -> x2 - v30 Imm(0) -> x1 - terminator Bnz { cond=v29, target=b15, fall=b9 } (exit_acc=v29) + v38 Imm(-9223372036854775808) -> x0 + v39 Imm(0) -> x0 + v40 LoadLocal { off=-5, kind=I64 } -> x0 + v41 Imm(0) -> x0 + v42 Imm(-1) -> x0 + v43 Imm(9223372036854775807) -> x0 + v44 Imm(1) -> x0 + v45 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v45) block 9 start_pc=0 - v31 LoadLocal { off=-4, kind=I64 } -> x1 - v32 BinopI { op=shr, lhs=v26, rhs_imm=1 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=-1 } -> x2 - v34 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v33) + v47 Imm(0) -> x0 + terminator Return(v47) (exit_acc=v47) block 10 start_pc=0 - v35 Phi { incoming=[b15:v29, b9:v33], kind=I64 } -> x2 - v36 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 11 start_pc=0 - v37 Imm(5) -> x0 - terminator Return(v37) (exit_acc=v37) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 12 start_pc=0 - v38 Imm(-9223372036854775808) -> x0 - v39 Imm(0) -> x1 - v40 LoadLocal { off=-5, kind=I64 } -> x1 - v41 Imm(0) -> x1 - v42 Imm(-1) -> x1 - v43 Imm(9223372036854775807) -> x1 - v44 BinopI { op=ugt, lhs=v38, rhs_imm=9223372036854775807 } -> x0 - v45 BinopI { op=eq, lhs=v44, rhs_imm=0 } -> x0 - terminator Bz { cond=v45, target=b14, fall=b13 } (exit_acc=v45) + v22 Imm(3) -> x0 + terminator Return(v22) (exit_acc=v22) block 13 start_pc=0 + v25 Imm(4) -> x0 + terminator Return(v25) (exit_acc=v25) + block 14 start_pc=0 v46 Imm(6) -> x0 terminator Return(v46) (exit_acc=v46) - block 14 start_pc=0 - v47 Imm(0) -> x0 - terminator Return(v47) (exit_acc=v47) - block 15 start_pc=0 - terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/compound_assign_float_register_resident.ssa b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa new file mode 100644 index 000000000..ca794fa11 --- /dev/null +++ b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa @@ -0,0 +1,271 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1120403456) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(1065353216) -> x0 [f32] + v4 StoreLocal { off=-2, value=v3, kind=F32 } -> - + v5 Imm(0) -> x0 + v6 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v5) + block 1 start_pc=0 + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v10 Imm(1073741824) -> x0 [f32] + v11 Binop { op=fsub, lhs=v9, rhs=v10 } -> d0 [f32] + v12 StoreLocal { off=-1, value=v11, kind=F32 } -> - + v13 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v14 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v15 Binop { op=fadd, lhs=v13, rhs=v14 } -> d0 [f32] + v16 StoreLocal { off=-1, value=v15, kind=F32 } -> - + v17 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v18 Imm(4607182418800017408) -> x0 + v19 FpCast { kind=F32ToF64, value=v14 } -> d1 + v20 Binop { op=fadd, lhs=v19, rhs=v18 } -> d1 + v21 FpCast { kind=F64ToF32, value=v20 } -> d1 [f32] + v22 StoreLocal { off=-2, value=v21, kind=F32 } -> - + v23 Imm(0) -> x0 + v24 Imm(1) -> x0 + v25 Imm(0) -> x0 + v26 Imm(1) -> x0 + v27 Imm(1) -> x0 + v28 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v29 Imm(1073741824) -> x0 [f32] + v30 Binop { op=fsub, lhs=v17, rhs=v29 } -> d0 [f32] + v31 StoreLocal { off=-1, value=v30, kind=F32 } -> - + v32 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v33 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v34 Binop { op=fadd, lhs=v32, rhs=v33 } -> d0 [f32] + v35 StoreLocal { off=-1, value=v34, kind=F32 } -> - + v36 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v37 Imm(4607182418800017408) -> x0 + v38 FpCast { kind=F32ToF64, value=v33 } -> d1 + v39 Binop { op=fadd, lhs=v38, rhs=v37 } -> d1 + v40 FpCast { kind=F64ToF32, value=v39 } -> d1 [f32] + v41 StoreLocal { off=-2, value=v40, kind=F32 } -> - + v42 Imm(1) -> x0 + v43 Imm(2) -> x0 + v44 Imm(0) -> x0 + v45 Imm(2) -> x0 + v46 Imm(1) -> x0 + v47 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v48 Imm(1073741824) -> x0 [f32] + v49 Binop { op=fsub, lhs=v36, rhs=v48 } -> d0 [f32] + v50 StoreLocal { off=-1, value=v49, kind=F32 } -> - + v51 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v52 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v53 Binop { op=fadd, lhs=v51, rhs=v52 } -> d0 [f32] + v54 StoreLocal { off=-1, value=v53, kind=F32 } -> - + v55 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v56 Imm(4607182418800017408) -> x0 + v57 FpCast { kind=F32ToF64, value=v52 } -> d1 + v58 Binop { op=fadd, lhs=v57, rhs=v56 } -> d1 + v59 FpCast { kind=F64ToF32, value=v58 } -> d1 [f32] + v60 StoreLocal { off=-2, value=v59, kind=F32 } -> - + v61 Imm(2) -> x0 + v62 Imm(3) -> x0 + v63 Imm(0) -> x0 + v64 Imm(3) -> x0 + v65 Imm(1) -> x0 + v66 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v67 Imm(1073741824) -> x0 [f32] + v68 Binop { op=fsub, lhs=v55, rhs=v67 } -> d0 [f32] + v69 StoreLocal { off=-1, value=v68, kind=F32 } -> - + v70 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v71 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v72 Binop { op=fadd, lhs=v70, rhs=v71 } -> d0 [f32] + v73 StoreLocal { off=-1, value=v72, kind=F32 } -> - + v74 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v75 Imm(4607182418800017408) -> x0 + v76 FpCast { kind=F32ToF64, value=v71 } -> d1 + v77 Binop { op=fadd, lhs=v76, rhs=v75 } -> d1 + v78 FpCast { kind=F64ToF32, value=v77 } -> d1 [f32] + v79 StoreLocal { off=-2, value=v78, kind=F32 } -> - + v80 Imm(3) -> x0 + v81 Imm(4) -> x0 + v82 Imm(0) -> x0 + v83 Imm(4) -> x0 + v84 Imm(1) -> x0 + v85 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v86 Imm(1073741824) -> x0 [f32] + v87 Binop { op=fsub, lhs=v74, rhs=v86 } -> d0 [f32] + v88 StoreLocal { off=-1, value=v87, kind=F32 } -> - + v89 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v90 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v91 Binop { op=fadd, lhs=v89, rhs=v90 } -> d0 [f32] + v92 StoreLocal { off=-1, value=v91, kind=F32 } -> - + v93 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v94 Imm(4607182418800017408) -> x0 + v95 FpCast { kind=F32ToF64, value=v90 } -> d1 + v96 Binop { op=fadd, lhs=v95, rhs=v94 } -> d1 + v97 FpCast { kind=F64ToF32, value=v96 } -> d1 [f32] + v98 StoreLocal { off=-2, value=v97, kind=F32 } -> - + v99 Imm(4) -> x0 + v100 Imm(5) -> x0 + v101 Imm(0) -> x0 + v102 Imm(5) -> x0 + v103 Imm(1) -> x0 + v104 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v105 Imm(1073741824) -> x0 [f32] + v106 Binop { op=fsub, lhs=v93, rhs=v105 } -> d0 [f32] + v107 StoreLocal { off=-1, value=v106, kind=F32 } -> - + v108 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v109 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v110 Binop { op=fadd, lhs=v108, rhs=v109 } -> d0 [f32] + v111 StoreLocal { off=-1, value=v110, kind=F32 } -> - + v112 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v113 Imm(4607182418800017408) -> x0 + v114 FpCast { kind=F32ToF64, value=v109 } -> d1 + v115 Binop { op=fadd, lhs=v114, rhs=v113 } -> d1 + v116 FpCast { kind=F64ToF32, value=v115 } -> d1 [f32] + v117 StoreLocal { off=-2, value=v116, kind=F32 } -> - + v118 Imm(5) -> x0 + v119 Imm(6) -> x0 + v120 Imm(0) -> x0 + v121 Imm(6) -> x0 + v122 Imm(1) -> x0 + v123 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v124 Imm(1073741824) -> x0 [f32] + v125 Binop { op=fsub, lhs=v112, rhs=v124 } -> d0 [f32] + v126 StoreLocal { off=-1, value=v125, kind=F32 } -> - + v127 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v128 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v129 Binop { op=fadd, lhs=v127, rhs=v128 } -> d0 [f32] + v130 StoreLocal { off=-1, value=v129, kind=F32 } -> - + v131 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v132 Imm(4607182418800017408) -> x0 + v133 FpCast { kind=F32ToF64, value=v128 } -> d1 + v134 Binop { op=fadd, lhs=v133, rhs=v132 } -> d1 + v135 FpCast { kind=F64ToF32, value=v134 } -> d1 [f32] + v136 StoreLocal { off=-2, value=v135, kind=F32 } -> - + v137 Imm(6) -> x0 + v138 Imm(7) -> x0 + v139 Imm(0) -> x0 + v140 Imm(7) -> x0 + v141 Imm(1) -> x0 + v142 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v143 Imm(1073741824) -> x0 [f32] + v144 Binop { op=fsub, lhs=v131, rhs=v143 } -> d0 [f32] + v145 StoreLocal { off=-1, value=v144, kind=F32 } -> - + v146 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v147 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v148 Binop { op=fadd, lhs=v146, rhs=v147 } -> d0 [f32] + v149 StoreLocal { off=-1, value=v148, kind=F32 } -> - + v150 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v151 Imm(4607182418800017408) -> x0 + v152 FpCast { kind=F32ToF64, value=v147 } -> d0 + v153 Binop { op=fadd, lhs=v152, rhs=v151 } -> d0 + v154 FpCast { kind=F64ToF32, value=v153 } -> d0 [f32] + v155 StoreLocal { off=-2, value=v154, kind=F32 } -> - + v156 Imm(7) -> x0 + v157 Imm(8) -> x0 + v158 Imm(0) -> x0 + v159 Imm(8) -> x0 + v160 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v160) + block 2 start_pc=0 + v161 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v162 Imm(1123024896) -> x0 [f32] + v163 Binop { op=fne, lhs=v161, rhs=v162 } -> x0 + terminator Bz { cond=v163, target=b4, fall=b3 } (exit_acc=v163) + block 3 start_pc=0 + v164 Imm(1) -> x0 + terminator Return(v164) (exit_acc=v164) + block 4 start_pc=0 + v165 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v166 Imm(1091567616) -> x0 [f32] + v167 Binop { op=fne, lhs=v165, rhs=v166 } -> x0 + terminator Bz { cond=v167, target=b6, fall=b5 } (exit_acc=v167) + block 5 start_pc=0 + v168 Imm(2) -> x0 + terminator Return(v168) (exit_acc=v168) + block 6 start_pc=0 + v169 Imm(1056964608) -> x0 [f32] + v170 StoreLocal { off=-4, value=v169, kind=F32 } -> - + v171 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v172 Imm(-4616189618054758400) -> x1 + v173 FpCast { kind=F32ToF64, value=v171 } -> d0 + v174 Binop { op=fadd, lhs=v173, rhs=v172 } -> d0 + v175 FpCast { kind=F64ToF32, value=v174 } -> d0 [f32] + v176 StoreLocal { off=-4, value=v175, kind=F32 } -> - + v177 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v178 Fneg(v169) -> d1 [f32] + v179 Binop { op=fne, lhs=v177, rhs=v178 } -> x0 + terminator Bz { cond=v179, target=b8, fall=b7 } (exit_acc=v179) + block 7 start_pc=0 + v180 Imm(3) -> x0 + terminator Return(v180) (exit_acc=v180) + block 8 start_pc=0 + v181 Imm(1077936128) -> x0 [f32] + v182 StoreLocal { off=-5, value=v181, kind=F32 } -> - + v183 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v184 Imm(4616189618054758400) -> x0 + v185 FpCast { kind=F32ToF64, value=v183 } -> d0 + v186 Binop { op=fmul, lhs=v185, rhs=v184 } -> d0 + v187 FpCast { kind=F64ToF32, value=v186 } -> d0 [f32] + v188 StoreLocal { off=-5, value=v187, kind=F32 } -> - + v189 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v190 Imm(1073741824) -> x0 [f32] + v191 Binop { op=fdiv, lhs=v189, rhs=v190 } -> d0 [f32] + v192 StoreLocal { off=-5, value=v191, kind=F32 } -> - + v193 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v194 Imm(1086324736) -> x0 [f32] + v195 Binop { op=fne, lhs=v193, rhs=v194 } -> x0 + terminator Bz { cond=v195, target=b10, fall=b9 } (exit_acc=v195) + block 9 start_pc=0 + v196 Imm(4) -> x0 + terminator Return(v196) (exit_acc=v196) + block 10 start_pc=0 + v197 Imm(0) -> x0 + terminator Return(v197) (exit_acc=v197) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/compound_assign_int_fp.ssa b/tests/snapshots/ssa/compound_assign_int_fp.ssa index 47eabbacf..83a53b2d9 100644 --- a/tests/snapshots/ssa/compound_assign_int_fp.ssa +++ b/tests/snapshots/ssa/compound_assign_int_fp.ssa @@ -68,106 +68,107 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v46 Imm(0) -> x1 v47 LoadLocal { off=-5, kind=I32 } -> x1 v48 FpCast { kind=IntToFp, value=v45 } -> d0 - v49 Imm(4613712638259704627) -> x0 - v50 Binop { op=fadd, lhs=v48, rhs=v49 } -> d0 - v51 FpCast { kind=FpToInt, value=v50 } -> x0 - v52 Imm(0) -> x1 - v53 Extend { value=v51, kind=I32 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=9 } -> x0 - terminator Bz { cond=v54, target=b10, fall=b9 } (exit_acc=v54) + v49 Imm(1077516698) -> x0 [f32] + v50 FpCast { kind=F32ToF64, value=v49 } -> d1 + v51 Binop { op=fadd, lhs=v48, rhs=v50 } -> d0 + v52 FpCast { kind=FpToInt, value=v51 } -> x0 + v53 Imm(0) -> x1 + v54 Extend { value=v52, kind=I32 } -> x0 + v55 BinopI { op=ne, lhs=v54, rhs_imm=9 } -> x0 + terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) block 9 start_pc=0 - v55 Imm(5) -> x0 - terminator Return(v55) (exit_acc=v55) + v56 Imm(5) -> x0 + terminator Return(v56) (exit_acc=v56) block 10 start_pc=0 - v56 Imm(-10) -> x0 - v57 Imm(0) -> x1 - v58 LoadLocal { off=-6, kind=I64 } -> x1 - v59 FpCast { kind=IntToFp, value=v56 } -> d0 - v60 Imm(4636786549475560653) -> x0 - v61 Binop { op=fadd, lhs=v59, rhs=v60 } -> d0 - v62 FpCast { kind=FpToInt, value=v61 } -> x0 - v63 Imm(0) -> x1 - v64 LoadLocal { off=-6, kind=I64 } -> x1 - v65 BinopI { op=ne, lhs=v62, rhs_imm=90 } -> x0 - terminator Bz { cond=v65, target=b12, fall=b11 } (exit_acc=v65) + v57 Imm(-10) -> x0 + v58 Imm(0) -> x1 + v59 LoadLocal { off=-6, kind=I64 } -> x1 + v60 FpCast { kind=IntToFp, value=v57 } -> d0 + v61 Imm(4636786549475560653) -> x0 + v62 Binop { op=fadd, lhs=v60, rhs=v61 } -> d0 + v63 FpCast { kind=FpToInt, value=v62 } -> x0 + v64 Imm(0) -> x1 + v65 LoadLocal { off=-6, kind=I64 } -> x1 + v66 BinopI { op=ne, lhs=v63, rhs_imm=90 } -> x0 + terminator Bz { cond=v66, target=b12, fall=b11 } (exit_acc=v66) block 11 start_pc=0 - v66 Imm(6) -> x0 - terminator Return(v66) (exit_acc=v66) + v67 Imm(6) -> x0 + terminator Return(v67) (exit_acc=v67) block 12 start_pc=0 - v67 Imm(5) -> x0 - v68 Imm(0) -> x1 - v69 LoadLocal { off=-7, kind=I64 } -> x1 - v70 FpCast { kind=IntToFp, value=v67 } -> d0 - v71 Imm(4615063718147915776) -> x0 - v72 Binop { op=fmul, lhs=v70, rhs=v71 } -> d0 - v73 FpCast { kind=FpToInt, value=v72 } -> x0 - v74 Imm(0) -> x1 - v75 LoadLocal { off=-7, kind=I64 } -> x1 - v76 BinopI { op=ne, lhs=v73, rhs_imm=17 } -> x0 - terminator Bz { cond=v76, target=b14, fall=b13 } (exit_acc=v76) + v68 Imm(5) -> x0 + v69 Imm(0) -> x1 + v70 LoadLocal { off=-7, kind=I64 } -> x1 + v71 FpCast { kind=IntToFp, value=v68 } -> d0 + v72 Imm(4615063718147915776) -> x0 + v73 Binop { op=fmul, lhs=v71, rhs=v72 } -> d0 + v74 FpCast { kind=FpToInt, value=v73 } -> x0 + v75 Imm(0) -> x1 + v76 LoadLocal { off=-7, kind=I64 } -> x1 + v77 BinopI { op=ne, lhs=v74, rhs_imm=17 } -> x0 + terminator Bz { cond=v77, target=b14, fall=b13 } (exit_acc=v77) block 13 start_pc=0 - v77 Imm(7) -> x0 - terminator Return(v77) (exit_acc=v77) + v78 Imm(7) -> x0 + terminator Return(v78) (exit_acc=v78) block 14 start_pc=0 - v78 Imm(100) -> x0 - v79 Imm(0) -> x1 - v80 LoadLocal { off=-8, kind=I16 } -> x1 - v81 FpCast { kind=IntToFp, value=v78 } -> d0 - v82 Imm(4632318134220278989) -> x0 - v83 Binop { op=fadd, lhs=v81, rhs=v82 } -> d0 - v84 FpCast { kind=FpToInt, value=v83 } -> x0 - v85 Imm(0) -> x1 - v86 Extend { value=v84, kind=I16 } -> x0 - v87 BinopI { op=ne, lhs=v86, rhs_imm=150 } -> x0 - terminator Bz { cond=v87, target=b16, fall=b15 } (exit_acc=v87) + v79 Imm(100) -> x0 + v80 Imm(0) -> x1 + v81 LoadLocal { off=-8, kind=I16 } -> x1 + v82 FpCast { kind=IntToFp, value=v79 } -> d0 + v83 Imm(4632318134220278989) -> x0 + v84 Binop { op=fadd, lhs=v82, rhs=v83 } -> d0 + v85 FpCast { kind=FpToInt, value=v84 } -> x0 + v86 Imm(0) -> x1 + v87 Extend { value=v85, kind=I16 } -> x0 + v88 BinopI { op=ne, lhs=v87, rhs_imm=150 } -> x0 + terminator Bz { cond=v88, target=b16, fall=b15 } (exit_acc=v88) block 15 start_pc=0 - v88 Imm(8) -> x0 - terminator Return(v88) (exit_acc=v88) + v89 Imm(8) -> x0 + terminator Return(v89) (exit_acc=v89) block 16 start_pc=0 - v89 Imm(100) -> x0 - v90 Imm(0) -> x1 - v91 Imm(4613937818241073152) -> x1 - v92 StoreLocal { off=-10, value=v91, kind=F64 } -> - - v93 LoadLocal { off=-9, kind=I64 } -> x1 - v94 FpCast { kind=IntToFp, value=v89 } -> d0 - v95 Imm(1) -> x0 - v96 FpCast { kind=IntToFp, value=v95 } -> d1 - v97 LoadLocal { off=-10, kind=F64 } -> d2 - v98 Binop { op=fdiv, lhs=v96, rhs=v97 } -> d1 - v99 Binop { op=fadd, lhs=v94, rhs=v98 } -> d0 - v100 FpCast { kind=FpToInt, value=v99 } -> x0 - v101 Imm(0) -> x1 - v102 LoadLocal { off=-9, kind=I64 } -> x1 - v103 BinopI { op=ne, lhs=v100, rhs_imm=100 } -> x0 - terminator Bz { cond=v103, target=b18, fall=b17 } (exit_acc=v103) + v90 Imm(100) -> x0 + v91 Imm(0) -> x1 + v92 Imm(4613937818241073152) -> x1 + v93 StoreLocal { off=-10, value=v92, kind=F64 } -> - + v94 LoadLocal { off=-9, kind=I64 } -> x1 + v95 FpCast { kind=IntToFp, value=v90 } -> d0 + v96 Imm(1) -> x0 + v97 FpCast { kind=IntToFp, value=v96 } -> d1 + v98 LoadLocal { off=-10, kind=F64 } -> d2 + v99 Binop { op=fdiv, lhs=v97, rhs=v98 } -> d1 + v100 Binop { op=fadd, lhs=v95, rhs=v99 } -> d0 + v101 FpCast { kind=FpToInt, value=v100 } -> x0 + v102 Imm(0) -> x1 + v103 LoadLocal { off=-9, kind=I64 } -> x1 + v104 BinopI { op=ne, lhs=v101, rhs_imm=100 } -> x0 + terminator Bz { cond=v104, target=b18, fall=b17 } (exit_acc=v104) block 17 start_pc=0 - v104 Imm(9) -> x0 - terminator Return(v104) (exit_acc=v104) + v105 Imm(9) -> x0 + terminator Return(v105) (exit_acc=v105) block 18 start_pc=0 - v105 Imm(4609434218613702656) -> x0 - v106 StoreLocal { off=-12, value=v105, kind=F64 } -> - - v107 Imm(3) -> x0 - v108 Imm(0) -> x1 - v109 LoadLocal { off=-12, kind=F64 } -> d0 - v110 LoadLocal { off=-13, kind=I32 } -> x1 - v111 FpCast { kind=IntToFp, value=v107 } -> d1 - v112 Binop { op=fadd, lhs=v109, rhs=v111 } -> d0 - v113 StoreLocal { off=-12, value=v112, kind=F64 } -> - - v114 LoadLocal { off=-12, kind=F64 } -> d0 - v115 Imm(2) -> x0 - v116 FpCast { kind=IntToFp, value=v115 } -> d1 - v117 Binop { op=fmul, lhs=v114, rhs=v116 } -> d0 - v118 StoreLocal { off=-12, value=v117, kind=F64 } -> - - v119 LoadLocal { off=-12, kind=F64 } -> d0 - v120 Imm(4621256167635550208) -> x0 - v121 Binop { op=fne, lhs=v119, rhs=v120 } -> x0 - terminator Bz { cond=v121, target=b20, fall=b19 } (exit_acc=v121) + v106 Imm(4609434218613702656) -> x0 + v107 StoreLocal { off=-12, value=v106, kind=F64 } -> - + v108 Imm(3) -> x0 + v109 Imm(0) -> x1 + v110 LoadLocal { off=-12, kind=F64 } -> d0 + v111 LoadLocal { off=-13, kind=I32 } -> x1 + v112 FpCast { kind=IntToFp, value=v108 } -> d1 + v113 Binop { op=fadd, lhs=v110, rhs=v112 } -> d0 + v114 StoreLocal { off=-12, value=v113, kind=F64 } -> - + v115 LoadLocal { off=-12, kind=F64 } -> d0 + v116 Imm(2) -> x0 + v117 FpCast { kind=IntToFp, value=v116 } -> d1 + v118 Binop { op=fmul, lhs=v115, rhs=v117 } -> d0 + v119 StoreLocal { off=-12, value=v118, kind=F64 } -> - + v120 LoadLocal { off=-12, kind=F64 } -> d0 + v121 Imm(4621256167635550208) -> x0 + v122 Binop { op=fne, lhs=v120, rhs=v121 } -> x0 + terminator Bz { cond=v122, target=b20, fall=b19 } (exit_acc=v122) block 19 start_pc=0 - v122 Imm(10) -> x0 - terminator Return(v122) (exit_acc=v122) - block 20 start_pc=0 - v123 Imm(0) -> x0 + v123 Imm(10) -> x0 terminator Return(v123) (exit_acc=v123) + block 20 start_pc=0 + v124 Imm(0) -> x0 + terminator Return(v124) (exit_acc=v124) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/compound_assign_unsigned_div.ssa b/tests/snapshots/ssa/compound_assign_unsigned_div.ssa index c57e699fb..50f7846e9 100644 --- a/tests/snapshots/ssa/compound_assign_unsigned_div.ssa +++ b/tests/snapshots/ssa/compound_assign_unsigned_div.ssa @@ -5,94 +5,94 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294967295) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 Imm(-2) -> x1 - v5 Imm(4294967294) -> x1 - v6 Binop { op=divu, lhs=v1, rhs=v5 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 - v9 BinopI { op=xor, lhs=v8, rhs_imm=1 } -> x0 - v10 BinopI { op=and, lhs=v9, rhs_imm=4294967295 } -> x0 - v11 BinopI { op=ne, lhs=v10, rhs_imm=0 } -> x0 - terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(-2) -> x0 + v5 Imm(4294967294) -> x0 + v6 Imm(1) -> x0 + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v11) block 1 start_pc=0 - v12 Imm(1) -> x0 - terminator Return(v12) (exit_acc=v12) - block 2 start_pc=0 v13 Imm(4294967295) -> x0 - v14 Imm(0) -> x1 - v15 LoadLocal { off=-2, kind=U32 } -> x1 - v16 Imm(-2) -> x1 - v17 Imm(4294967294) -> x1 - v18 Binop { op=modu, lhs=v13, rhs=v17 } -> x0 - v19 Imm(0) -> x1 - v20 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 - v21 BinopI { op=xor, lhs=v20, rhs_imm=1 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v14 Imm(0) -> x0 + v15 LoadLocal { off=-2, kind=U32 } -> x0 + v16 Imm(-2) -> x0 + v17 Imm(4294967294) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v25 Imm(-2) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-3, kind=I32 } -> x0 + v28 Imm(2) -> x0 + v29 Imm(4294967294) -> x0 + v30 Imm(2147483647) -> x0 + v31 Imm(0) -> x0 + v32 Imm(2147483647) -> x0 + v33 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v33) block 3 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v35 Imm(-7) -> x0 + v36 Imm(0) -> x0 + v37 LoadLocal { off=-4, kind=I32 } -> x0 + v38 Imm(3) -> x0 + v39 Imm(-1) -> x0 + v40 Imm(0) -> x0 + v41 Imm(-1) -> x0 + v42 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v42) block 4 start_pc=0 - v25 Imm(-2) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-3, kind=I32 } -> x1 - v28 Imm(2) -> x1 - v29 BinopI { op=and, lhs=v25, rhs_imm=4294967295 } -> x0 - v30 Binop { op=divu, lhs=v29, rhs=v28 } -> x0 - v31 Imm(0) -> x1 - v32 Extend { value=v30, kind=I32 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=2147483647 } -> x0 - terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + v44 Imm(-1) -> x0 + v45 Imm(0) -> x0 + v46 LoadLocal { off=-5, kind=I64 } -> x0 + v47 Imm(3) -> x0 + v48 Imm(6148914691236517205) -> x0 + v49 Imm(0) -> x0 + v50 LoadLocal { off=-5, kind=I64 } -> x0 + v51 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v51) block 5 start_pc=0 - v34 Imm(3) -> x0 - terminator Return(v34) (exit_acc=v34) + v53 Imm(255) -> x0 + v54 Imm(0) -> x0 + v55 LoadLocal { off=-6, kind=U8 } -> x0 + v56 Imm(-2) -> x0 + v57 Imm(-127) -> x0 + v58 Imm(0) -> x0 + v59 Imm(129) -> x0 + v60 Imm(0) -> x0 + v61 Imm(0) -> x0 + v62 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v62) block 6 start_pc=0 - v35 Imm(-7) -> x0 - v36 Imm(0) -> x1 - v37 LoadLocal { off=-4, kind=I32 } -> x1 - v38 Imm(3) -> x1 - v39 Binop { op=mod, lhs=v35, rhs=v38 } -> x0 - v40 Imm(0) -> x1 - v41 Extend { value=v39, kind=I32 } -> x0 - v42 BinopI { op=ne, lhs=v41, rhs_imm=-1 } -> x0 - terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) + v64 Imm(0) -> x0 + terminator Return(v64) (exit_acc=v64) block 7 start_pc=0 - v43 Imm(4) -> x0 - terminator Return(v43) (exit_acc=v43) + v12 Imm(1) -> x0 + terminator Return(v12) (exit_acc=v12) block 8 start_pc=0 - v44 Imm(-1) -> x0 - v45 Imm(0) -> x1 - v46 LoadLocal { off=-5, kind=I64 } -> x1 - v47 Imm(3) -> x1 - v48 Binop { op=divu, lhs=v44, rhs=v47 } -> x0 - v49 Imm(0) -> x1 - v50 LoadLocal { off=-5, kind=I64 } -> x1 - v51 BinopI { op=ne, lhs=v48, rhs_imm=6148914691236517205 } -> x0 - terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) + v24 Imm(2) -> x0 + terminator Return(v24) (exit_acc=v24) block 9 start_pc=0 - v52 Imm(5) -> x0 - terminator Return(v52) (exit_acc=v52) + v34 Imm(3) -> x0 + terminator Return(v34) (exit_acc=v34) block 10 start_pc=0 - v53 Imm(255) -> x0 - v54 Imm(0) -> x1 - v55 LoadLocal { off=-6, kind=U8 } -> x1 - v56 Imm(-2) -> x1 - v57 Binop { op=div, lhs=v53, rhs=v56 } -> x0 - v58 Imm(0) -> x1 - v59 BinopI { op=and, lhs=v57, rhs_imm=255 } -> x0 - v60 BinopI { op=xor, lhs=v59, rhs_imm=129 } -> x0 - v61 BinopI { op=and, lhs=v60, rhs_imm=4294967295 } -> x0 - v62 BinopI { op=ne, lhs=v61, rhs_imm=0 } -> x0 - terminator Bz { cond=v62, target=b12, fall=b11 } (exit_acc=v62) + v43 Imm(4) -> x0 + terminator Return(v43) (exit_acc=v43) block 11 start_pc=0 + v52 Imm(5) -> x0 + terminator Return(v52) (exit_acc=v52) + block 12 start_pc=0 v63 Imm(6) -> x0 terminator Return(v63) (exit_acc=v63) - block 12 start_pc=0 - v64 Imm(0) -> x0 - terminator Return(v64) (exit_acc=v64) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/compound_literal_block.ssa b/tests/snapshots/ssa/compound_literal_block.ssa index 150c3bbc3..2cad18e0a 100644 --- a/tests/snapshots/ssa/compound_literal_block.ssa +++ b/tests/snapshots/ssa/compound_literal_block.ssa @@ -27,7 +27,7 @@ fn ent_pc=1 n_params=1 variadic=false locals=3 v5 Load { addr=v1, disp=0, kind=I32 } -> x0 v6 BinopI { op=eq, lhs=v5, rhs_imm=1 } -> x0 v7 Imm(0) -> x1 - terminator Bz { cond=v6, target=b7, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b9, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v8 LoadLocal { off=2, kind=I64 } -> x0 v9 Imm(4) -> x0 @@ -38,7 +38,7 @@ fn ent_pc=1 n_params=1 variadic=false locals=3 v14 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Phi { incoming=[b7:v4, b1:v13], kind=I64 } -> x2 + v15 Phi { incoming=[b9:v4, b1:v13], kind=I64 } -> x2 v16 LoadLocal { off=-3, kind=I64 } -> x0 v17 Imm(0) -> x1 v18 Imm(0) -> x0 @@ -57,7 +57,7 @@ fn ent_pc=1 n_params=1 variadic=false locals=3 v27 LoadLocal { off=-2, kind=I64 } -> x0 v28 Imm(0) -> x2 v29 Imm(0) -> x0 - terminator Bz { cond=v26, target=b9, fall=b5 } (exit_acc=v26) + terminator Bz { cond=v26, target=b7, fall=b5 } (exit_acc=v26) block 5 start_pc=0 v30 LoadLocal { off=2, kind=I64 } -> x0 v31 Imm(12) -> x0 @@ -68,15 +68,15 @@ fn ent_pc=1 n_params=1 variadic=false locals=3 v36 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v37 Phi { incoming=[b9:v28, b5:v35], kind=I64 } -> x2 + v37 Phi { incoming=[b7:v28, b5:v35], kind=I64 } -> x2 v38 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v37) (exit_acc=v37) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) block 8 start_pc=0 terminator Jmp(b4) block 9 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=two_strings fn ent_pc=2 n_params=1 variadic=false locals=3 @@ -91,7 +91,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v6 Load { addr=v5, disp=0, kind=I8 } -> x0 v7 BinopI { op=eq, lhs=v6, rhs_imm=115 } -> x0 v8 Imm(0) -> x1 - terminator Bz { cond=v7, target=b7, fall=b1 } (exit_acc=v7) + terminator Bz { cond=v7, target=b9, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v9 LoadLocal { off=2, kind=I64 } -> x0 v10 Imm(0) -> x0 @@ -104,7 +104,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v17 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v18 Phi { incoming=[b7:v4, b1:v16], kind=I64 } -> x2 + v18 Phi { incoming=[b9:v4, b1:v16], kind=I64 } -> x2 v19 LoadLocal { off=-3, kind=I64 } -> x0 v20 Imm(0) -> x1 v21 Imm(0) -> x0 @@ -125,7 +125,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v32 LoadLocal { off=-2, kind=I64 } -> x0 v33 Imm(0) -> x2 v34 Imm(0) -> x0 - terminator Bz { cond=v31, target=b9, fall=b5 } (exit_acc=v31) + terminator Bz { cond=v31, target=b7, fall=b5 } (exit_acc=v31) block 5 start_pc=0 v35 LoadLocal { off=2, kind=I64 } -> x0 v36 Imm(8) -> x0 @@ -138,15 +138,15 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v43 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v42) block 6 start_pc=0 - v44 Phi { incoming=[b9:v33, b5:v42], kind=I64 } -> x2 + v44 Phi { incoming=[b7:v33, b5:v42], kind=I64 } -> x2 v45 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v44) (exit_acc=v44) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) block 8 start_pc=0 terminator Jmp(b4) block 9 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=14 @@ -222,7 +222,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=14 v55 BinopI { op=ne, lhs=v54, rhs_imm=7 } -> x1 v56 Imm(1) -> x6 v57 Imm(0) -> x2 - terminator Bnz { cond=v55, target=b21, fall=b7 } (exit_acc=v55) + terminator Bnz { cond=v55, target=b23, fall=b7 } (exit_acc=v55) block 7 start_pc=0 v58 LoadLocal { off=-6, kind=I64 } -> x1 v59 Imm(4) -> x1 @@ -233,7 +233,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=14 v64 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v63) block 8 start_pc=0 - v65 Phi { incoming=[b21:v56, b7:v63], kind=I64 } -> x6 + v65 Phi { incoming=[b23:v56, b7:v63], kind=I64 } -> x6 v66 LoadLocal { off=-14, kind=I64 } -> x1 v67 Imm(1) -> x2 v68 Imm(0) -> x1 @@ -251,7 +251,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=14 v76 Phi { incoming=[b22:v67, b9:v74], kind=I64 } -> x2 v77 LoadLocal { off=-13, kind=I64 } -> x1 v78 Imm(0) -> x1 - terminator Bnz { cond=v76, target=b23, fall=b11 } (exit_acc=v76) + terminator Bnz { cond=v76, target=b21, fall=b11 } (exit_acc=v76) block 11 start_pc=0 v79 LoadLocal { off=-6, kind=I64 } -> x1 v80 Imm(12) -> x1 @@ -261,7 +261,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=14 v84 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v83) block 12 start_pc=0 - v85 Phi { incoming=[b23:v76, b11:v83], kind=I64 } -> x2 + v85 Phi { incoming=[b21:v76, b11:v83], kind=I64 } -> x2 v86 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v85, target=b14, fall=b13 } (exit_acc=v85) block 13 start_pc=0 @@ -323,11 +323,11 @@ fn ent_pc=3 n_params=0 variadic=false locals=14 v128 Imm(0) -> x0 terminator Return(v128) (exit_acc=v128) block 21 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b12) block 22 start_pc=0 terminator Jmp(b10) block 23 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/compound_literal_file_scope.ssa b/tests/snapshots/ssa/compound_literal_file_scope.ssa index 2a3a77dec..bb5ab3b33 100644 --- a/tests/snapshots/ssa/compound_literal_file_scope.ssa +++ b/tests/snapshots/ssa/compound_literal_file_scope.ssa @@ -10,7 +10,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v4 BinopI { op=ne, lhs=v3, rhs_imm=1 } -> x1 v5 Imm(1) -> x6 v6 Imm(0) -> x2 - terminator Bnz { cond=v4, target=b27, fall=b1 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b33, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v7 ImmData(40) -> x1 v8 Load { addr=v1, disp=0, kind=I64 } -> x1 @@ -21,10 +21,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v13 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v14 Phi { incoming=[b27:v5, b1:v12], kind=I64 } -> x6 + v14 Phi { incoming=[b33:v5, b1:v12], kind=I64 } -> x6 v15 LoadLocal { off=-2, kind=I64 } -> x1 v16 Imm(0) -> x1 - terminator Bnz { cond=v14, target=b28, fall=b3 } (exit_acc=v14) + terminator Bnz { cond=v14, target=b32, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v17 ImmData(40) -> x1 v18 Load { addr=v1, disp=0, kind=I64 } -> x0 @@ -34,7 +34,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v22 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v21) block 4 start_pc=0 - v23 Phi { incoming=[b28:v14, b3:v21], kind=I64 } -> x6 + v23 Phi { incoming=[b32:v14, b3:v21], kind=I64 } -> x6 v24 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) block 5 start_pc=0 @@ -47,7 +47,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v29 BinopI { op=ne, lhs=v28, rhs_imm=2 } -> x0 v30 Imm(1) -> x2 v31 Imm(0) -> x1 - terminator Bnz { cond=v29, target=b29, fall=b7 } (exit_acc=v29) + terminator Bnz { cond=v29, target=b31, fall=b7 } (exit_acc=v29) block 7 start_pc=0 v32 ImmData(64) -> x0 v33 Load { addr=v32, disp=0, kind=I64 } -> x0 @@ -58,7 +58,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v38 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Phi { incoming=[b29:v30, b7:v37], kind=I64 } -> x2 + v39 Phi { incoming=[b31:v30, b7:v37], kind=I64 } -> x2 v40 LoadLocal { off=-4, kind=I64 } -> x0 v41 Imm(0) -> x0 terminator Bnz { cond=v39, target=b30, fall=b9 } (exit_acc=v39) @@ -95,7 +95,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v61 Load { addr=v59, disp=0, kind=I8 } -> x0 v62 BinopI { op=ne, lhs=v61, rhs_imm=114 } -> x1 v63 Imm(0) -> x0 - terminator Bnz { cond=v62, target=b31, fall=b15 } (exit_acc=v62) + terminator Bnz { cond=v62, target=b29, fall=b15 } (exit_acc=v62) block 15 start_pc=0 v64 ImmData(88) -> x0 v65 Load { addr=v64, disp=0, kind=I64 } -> x0 @@ -108,7 +108,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v72 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v71) block 16 start_pc=0 - v73 Phi { incoming=[b31:v62, b15:v71], kind=I64 } -> x1 + v73 Phi { incoming=[b29:v62, b15:v71], kind=I64 } -> x1 v74 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v73, target=b18, fall=b17 } (exit_acc=v73) block 17 start_pc=0 @@ -131,7 +131,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v85 BinopI { op=ne, lhs=v84, rhs_imm=0 } -> x0 v86 Imm(1) -> x2 v87 Imm(0) -> x1 - terminator Bnz { cond=v85, target=b32, fall=b21 } (exit_acc=v85) + terminator Bnz { cond=v85, target=b28, fall=b21 } (exit_acc=v85) block 21 start_pc=0 v88 ImmData(128) -> x0 v89 Load { addr=v88, disp=0, kind=I64 } -> x0 @@ -142,10 +142,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v94 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v93) block 22 start_pc=0 - v95 Phi { incoming=[b32:v86, b21:v93], kind=I64 } -> x2 + v95 Phi { incoming=[b28:v86, b21:v93], kind=I64 } -> x2 v96 LoadLocal { off=-7, kind=I64 } -> x0 v97 Imm(0) -> x0 - terminator Bnz { cond=v95, target=b33, fall=b23 } (exit_acc=v95) + terminator Bnz { cond=v95, target=b27, fall=b23 } (exit_acc=v95) block 23 start_pc=0 v98 ImmData(128) -> x0 v99 Load { addr=v98, disp=0, kind=I64 } -> x0 @@ -155,7 +155,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v103 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v102) block 24 start_pc=0 - v104 Phi { incoming=[b33:v95, b23:v102], kind=I64 } -> x2 + v104 Phi { incoming=[b27:v95, b23:v102], kind=I64 } -> x2 v105 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v104, target=b26, fall=b25 } (exit_acc=v104) block 25 start_pc=0 @@ -165,19 +165,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v107 Imm(0) -> x0 terminator Return(v107) (exit_acc=v107) block 27 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b24) block 28 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b22) block 29 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b16) block 30 start_pc=0 terminator Jmp(b10) block 31 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b8) block 32 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b4) block 33 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/computed_goto.ssa b/tests/snapshots/ssa/computed_goto.ssa index f2937d62a..3f22c8491 100644 --- a/tests/snapshots/ssa/computed_goto.ssa +++ b/tests/snapshots/ssa/computed_goto.ssa @@ -6,7 +6,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - - v3 LoadLocal { off=2, kind=I32 } -> x0 + v3 Extend { value=v1, kind=I32 } -> x0 v4 BinopI { op=eq, lhs=v3, rhs_imm=0 } -> x0 terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) block 1 start_pc=0 @@ -20,8 +20,8 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 block 3 start_pc=0 v9 LoadLocal { off=-2, kind=I64 } -> x0 v10 StoreLocal { off=-1, value=v9, kind=I64 } -> - - v11 LoadLocal { off=-1, kind=I64 } -> x0 - terminator GotoIndirect(v11) (exit_acc=v11) + v11 LoadLocal { off=-1, kind=I64 } -> x1 + terminator GotoIndirect(v9) (exit_acc=v9) block 4 start_pc=0 v12 Imm(10) -> x0 terminator Return(v12) (exit_acc=v12) @@ -53,8 +53,8 @@ fn ent_pc=1 n_params=1 variadic=false locals=5 v17 StoreLocal { off=-4, value=v4, kind=I32 } -> - v18 StoreLocal { off=-5, value=v4, kind=I32 } -> - v19 LocalAddr(-3) -> x0 - v20 LoadLocal { off=2, kind=I64 } -> x1 - v21 LoadLocal { off=-5, kind=I32 } -> x2 + v20 LoadLocal { off=2, kind=I64 } -> x2 + v21 Extend { value=v4, kind=I32 } -> x1 v22 BinopI { op=add, lhs=v21, rhs_imm=1 } -> x6 v23 StoreLocal { off=-5, value=v22, kind=I32 } -> - v24 BinopI { op=shl, lhs=v21, rhs_imm=2 } -> x6 @@ -70,20 +70,20 @@ fn ent_pc=1 n_params=1 variadic=false locals=5 v32 LoadLocal { off=-5, kind=I32 } -> x2 v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x6 v34 StoreLocal { off=-5, value=v33, kind=I32 } -> - - v35 BinopI { op=shl, lhs=v32, rhs_imm=2 } -> x6 - v36 Binop { op=add, lhs=v31, rhs=v35 } -> x6 - v37 LoadIndexed { base=v31, index=v32, scale=4, kind=I32 } -> x1 + v35 BinopI { op=shl, lhs=v32, rhs_imm=2 } -> x7 + v36 Binop { op=add, lhs=v31, rhs=v35 } -> x7 + v37 LoadIndexed { base=v31, index=v32, scale=4, kind=I32 } -> x2 v38 Binop { op=add, lhs=v30, rhs=v37 } -> x0 v39 StoreLocal { off=-4, value=v38, kind=I32 } -> - - v40 LoadLocal { off=-4, kind=I32 } -> x0 + v40 Extend { value=v38, kind=I32 } -> x0 v41 LocalAddr(-3) -> x0 - v42 LoadLocal { off=2, kind=I64 } -> x1 - v43 LoadLocal { off=-5, kind=I32 } -> x2 + v42 LoadLocal { off=2, kind=I64 } -> x2 + v43 Extend { value=v33, kind=I32 } -> x2 v44 BinopI { op=add, lhs=v43, rhs_imm=1 } -> x6 v45 StoreLocal { off=-5, value=v44, kind=I32 } -> - v46 BinopI { op=shl, lhs=v43, rhs_imm=2 } -> x6 - v47 Binop { op=add, lhs=v42, rhs=v46 } -> x6 - v48 LoadIndexed { base=v42, index=v43, scale=4, kind=I32 } -> x1 + v47 Binop { op=add, lhs=v31, rhs=v46 } -> x6 + v48 LoadIndexed { base=v31, index=v43, scale=4, kind=I32 } -> x1 v49 BinopI { op=shl, lhs=v48, rhs_imm=3 } -> x2 v50 Binop { op=add, lhs=v41, rhs=v49 } -> x2 v51 LoadIndexed { base=v41, index=v48, scale=8, kind=I64 } -> x0 @@ -94,20 +94,20 @@ fn ent_pc=1 n_params=1 variadic=false locals=5 v54 LoadLocal { off=-5, kind=I32 } -> x2 v55 BinopI { op=add, lhs=v54, rhs_imm=1 } -> x6 v56 StoreLocal { off=-5, value=v55, kind=I32 } -> - - v57 BinopI { op=shl, lhs=v54, rhs_imm=2 } -> x6 - v58 Binop { op=add, lhs=v53, rhs=v57 } -> x6 - v59 LoadIndexed { base=v53, index=v54, scale=4, kind=I32 } -> x1 + v57 BinopI { op=shl, lhs=v54, rhs_imm=2 } -> x7 + v58 Binop { op=add, lhs=v53, rhs=v57 } -> x7 + v59 LoadIndexed { base=v53, index=v54, scale=4, kind=I32 } -> x2 v60 Binop { op=sub, lhs=v52, rhs=v59 } -> x0 v61 StoreLocal { off=-4, value=v60, kind=I32 } -> - - v62 LoadLocal { off=-4, kind=I32 } -> x0 + v62 Extend { value=v60, kind=I32 } -> x0 v63 LocalAddr(-3) -> x0 - v64 LoadLocal { off=2, kind=I64 } -> x1 - v65 LoadLocal { off=-5, kind=I32 } -> x2 + v64 LoadLocal { off=2, kind=I64 } -> x2 + v65 Extend { value=v55, kind=I32 } -> x2 v66 BinopI { op=add, lhs=v65, rhs_imm=1 } -> x6 v67 StoreLocal { off=-5, value=v66, kind=I32 } -> - v68 BinopI { op=shl, lhs=v65, rhs_imm=2 } -> x6 - v69 Binop { op=add, lhs=v64, rhs=v68 } -> x6 - v70 LoadIndexed { base=v64, index=v65, scale=4, kind=I32 } -> x1 + v69 Binop { op=add, lhs=v53, rhs=v68 } -> x6 + v70 LoadIndexed { base=v53, index=v65, scale=4, kind=I32 } -> x1 v71 BinopI { op=shl, lhs=v70, rhs_imm=3 } -> x2 v72 Binop { op=add, lhs=v63, rhs=v71 } -> x2 v73 LoadIndexed { base=v63, index=v70, scale=8, kind=I64 } -> x0 @@ -138,25 +138,25 @@ fn ent_pc=2 n_params=1 variadic=false locals=4 v13 LoadLocal { off=-3, kind=I32 } -> x0 v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x0 v15 StoreLocal { off=-3, value=v14, kind=I32 } -> - - v16 LoadLocal { off=-3, kind=I32 } -> x0 - v17 LocalAddr(-2) -> x0 - v18 LoadLocal { off=-3, kind=I32 } -> x1 + v16 Extend { value=v14, kind=I32 } -> x1 + v17 LocalAddr(-2) -> x1 + v18 Extend { value=v14, kind=I32 } -> x0 v19 LoadLocal { off=2, kind=I32 } -> x2 - v20 Binop { op=lt, lhs=v18, rhs=v19 } -> x1 + v20 Binop { op=lt, lhs=v18, rhs=v19 } -> x0 terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) block 2 start_pc=0 v29 LoadLocal { off=-3, kind=I32 } -> x0 terminator Return(v29) (exit_acc=v29) block 3 start_pc=0 - v21 Imm(0) -> x1 + v21 Imm(0) -> x0 v22 StoreLocal { off=-4, value=v21, kind=I64 } -> - terminator Jmp(b5) (exit_acc=v22) block 4 start_pc=0 - v23 Imm(1) -> x1 + v23 Imm(1) -> x0 v24 StoreLocal { off=-4, value=v23, kind=I64 } -> - terminator Jmp(b5) (exit_acc=v24) block 5 start_pc=0 - v25 LoadLocal { off=-4, kind=I64 } -> x1 + v25 LoadLocal { off=-4, kind=I64 } -> x0 v26 BinopI { op=shl, lhs=v25, rhs_imm=3 } -> x2 v27 Binop { op=add, lhs=v17, rhs=v26 } -> x2 v28 LoadIndexed { base=v17, index=v25, scale=8, kind=I64 } -> x0 diff --git a/tests/snapshots/ssa/computed_goto_static_table.ssa b/tests/snapshots/ssa/computed_goto_static_table.ssa new file mode 100644 index 000000000..5d6b27158 --- /dev/null +++ b/tests/snapshots/ssa/computed_goto_static_table.ssa @@ -0,0 +1,197 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=interp +fn ent_pc=0 n_params=1 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I64 } -> - + v3 ImmData(8) -> x0 + v4 Imm(32) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v6 Load { addr=v3, disp=32, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(0) -> x1 + v8 StoreLocal { off=-3, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) + block 2 start_pc=0 + v9 ImmData(8) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 BlockAddr(block=7) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I64 } -> - + v25 Imm(32) -> x1 + v26 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v27 Imm(1) -> x1 + v28 Store { addr=v3, disp=32, value=v27, kind=I8 } -> - + v29 Imm(72057594037927936) -> x2 + v30 StoreLocal { off=-3, value=v27, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v30) + block 3 start_pc=0 + v31 LoadLocal { off=-3, kind=I64 } -> x1 + v32 Imm(0) -> x1 + v33 StoreLocal { off=-1, value=v32, kind=I32 } -> - + v34 StoreLocal { off=-2, value=v32, kind=I32 } -> - + v35 ImmData(8) -> x2 + v36 LoadLocal { off=2, kind=I64 } -> x2 + v37 Extend { value=v32, kind=I32 } -> x1 + v38 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x6 + v39 StoreLocal { off=-2, value=v38, kind=I32 } -> - + v40 Binop { op=add, lhs=v36, rhs=v37 } -> x1 + v41 Load { addr=v40, disp=0, kind=U8 } -> x1 + v42 BinopI { op=shl, lhs=v41, rhs_imm=3 } -> x2 + v43 Binop { op=add, lhs=v3, rhs=v42 } -> x2 + v44 LoadIndexed { base=v3, index=v41, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v44) (exit_acc=v44) + block 4 start_pc=0 + v45 LoadLocal { off=-1, kind=I32 } -> x1 + v46 LoadLocal { off=2, kind=I64 } -> x2 + v47 LoadLocal { off=-2, kind=I32 } -> x6 + v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x7 + v49 StoreLocal { off=-2, value=v48, kind=I32 } -> - + v50 Binop { op=add, lhs=v46, rhs=v47 } -> x6 + v51 Load { addr=v50, disp=0, kind=U8 } -> x6 + v52 Binop { op=add, lhs=v45, rhs=v51 } -> x1 + v53 StoreLocal { off=-1, value=v52, kind=I32 } -> - + v54 Extend { value=v52, kind=I32 } -> x1 + v55 ImmData(8) -> x1 + v56 Extend { value=v48, kind=I32 } -> x1 + v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x6 + v58 StoreLocal { off=-2, value=v57, kind=I32 } -> - + v59 Binop { op=add, lhs=v46, rhs=v56 } -> x1 + v60 Load { addr=v59, disp=0, kind=U8 } -> x1 + v61 BinopI { op=shl, lhs=v60, rhs_imm=3 } -> x2 + v62 Binop { op=add, lhs=v3, rhs=v61 } -> x2 + v63 LoadIndexed { base=v3, index=v60, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v63) (exit_acc=v63) + block 5 start_pc=0 + v64 LoadLocal { off=-1, kind=I32 } -> x1 + v65 LoadLocal { off=2, kind=I64 } -> x2 + v66 LoadLocal { off=-2, kind=I32 } -> x6 + v67 BinopI { op=add, lhs=v66, rhs_imm=1 } -> x7 + v68 StoreLocal { off=-2, value=v67, kind=I32 } -> - + v69 Binop { op=add, lhs=v65, rhs=v66 } -> x6 + v70 Load { addr=v69, disp=0, kind=U8 } -> x6 + v71 Binop { op=sub, lhs=v64, rhs=v70 } -> x1 + v72 StoreLocal { off=-1, value=v71, kind=I32 } -> - + v73 Extend { value=v71, kind=I32 } -> x1 + v74 ImmData(8) -> x1 + v75 Extend { value=v67, kind=I32 } -> x1 + v76 BinopI { op=add, lhs=v75, rhs_imm=1 } -> x6 + v77 StoreLocal { off=-2, value=v76, kind=I32 } -> - + v78 Binop { op=add, lhs=v65, rhs=v75 } -> x1 + v79 Load { addr=v78, disp=0, kind=U8 } -> x1 + v80 BinopI { op=shl, lhs=v79, rhs_imm=3 } -> x2 + v81 Binop { op=add, lhs=v3, rhs=v80 } -> x2 + v82 LoadIndexed { base=v3, index=v79, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v82) (exit_acc=v82) + block 6 start_pc=0 + v83 LoadLocal { off=-1, kind=I32 } -> x1 + v84 Binop { op=add, lhs=v83, rhs=v83 } -> x1 + v85 StoreLocal { off=-1, value=v84, kind=I32 } -> - + v86 Extend { value=v84, kind=I32 } -> x1 + v87 ImmData(8) -> x1 + v88 LoadLocal { off=2, kind=I64 } -> x1 + v89 LoadLocal { off=-2, kind=I32 } -> x2 + v90 BinopI { op=add, lhs=v89, rhs_imm=1 } -> x6 + v91 StoreLocal { off=-2, value=v90, kind=I32 } -> - + v92 Binop { op=add, lhs=v88, rhs=v89 } -> x1 + v93 Load { addr=v92, disp=0, kind=U8 } -> x1 + v94 BinopI { op=shl, lhs=v93, rhs_imm=3 } -> x2 + v95 Binop { op=add, lhs=v3, rhs=v94 } -> x2 + v96 LoadIndexed { base=v3, index=v93, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v96) (exit_acc=v96) + block 7 start_pc=0 + v97 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v97) (exit_acc=v97) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=1 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmData(48) -> x3 + v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v3 BinopI { op=ne, lhs=v2, rhs_imm=7 } -> x0 + terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + block 1 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) + block 2 start_pc=0 + v5 ImmData(56) -> x7 + v6 Call { target_pc=0, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=ne, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + block 3 start_pc=0 + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + v9 ImmData(48) -> x0 + v10 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x0 + terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + block 5 start_pc=0 + v12 Imm(3) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/const_expr_arithmetic.ssa b/tests/snapshots/ssa/const_expr_arithmetic.ssa index c0c0bcc3a..f27394974 100644 --- a/tests/snapshots/ssa/const_expr_arithmetic.ssa +++ b/tests/snapshots/ssa/const_expr_arithmetic.ssa @@ -7,159 +7,145 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 v1 Imm(0) -> x3 v2 Imm(0) -> x0 v3 Imm(32) -> x0 - v4 Imm(4) -> x1 - v5 Binop { op=add, lhs=v3, rhs=v1 } -> x0 - v6 BinopI { op=shr, lhs=v5, rhs_imm=2 } -> x0 - v7 BinopI { op=ne, lhs=v6, rhs_imm=8 } -> x0 - terminator Bz { cond=v7, target=b15, fall=b1 } (exit_acc=v7) + v4 Imm(4) -> x0 + v5 Imm(32) -> x0 + v6 Imm(8) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 + v17 Phi { incoming=[b0:v1, b8:v15], kind=I64 } -> x3 + v18 Imm(24) -> x0 + v19 Imm(4) -> x0 + v20 Imm(0) -> x0 + v21 Imm(24) -> x0 + v22 Imm(6) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v33 Phi { incoming=[b1:v17, b9:v31], kind=I64 } -> x3 + v34 Imm(64) -> x0 + v35 Imm(4) -> x0 + v36 Imm(0) -> x0 + v37 Imm(64) -> x0 + v38 Imm(16) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v39) + block 3 start_pc=0 + v49 Phi { incoming=[b2:v33, b10:v47], kind=I64 } -> x3 + v50 Imm(64) -> x0 + v51 Imm(4) -> x0 + v52 Imm(0) -> x0 + v53 Imm(64) -> x0 + v54 Imm(16) -> x0 + v55 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v55) + block 4 start_pc=0 + v64 Phi { incoming=[b3:v49, b11:v58], kind=I64 } -> x3 + v65 Imm(24) -> x0 + v66 Imm(4) -> x0 + v67 Imm(0) -> x0 + v68 Imm(24) -> x0 + v69 Imm(6) -> x0 + v70 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v70) + block 5 start_pc=0 + v80 Phi { incoming=[b4:v64, b12:v78], kind=I64 } -> x3 + v81 Imm(32) -> x0 + v82 Imm(4) -> x0 + v83 Imm(0) -> x0 + v84 Imm(32) -> x0 + v85 Imm(8) -> x0 + v86 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v86) + block 6 start_pc=0 + v96 Phi { incoming=[b5:v80, b13:v94], kind=I64 } -> x3 + v97 Imm(24) -> x0 + v98 Imm(4) -> x0 + v99 Imm(0) -> x0 + v100 Imm(24) -> x0 + v101 Imm(6) -> x0 + v102 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v102) + block 7 start_pc=0 + v112 Phi { incoming=[b6:v96, b14:v110], kind=I64 } -> x3 + v113 Extend { value=v112, kind=I32 } -> x0 + terminator Return(v113) (exit_acc=v113) + block 8 start_pc=0 v8 ImmData(32) -> x7 v9 Imm(32) -> x0 - v10 Imm(4) -> x1 - v11 Imm(0) -> x1 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x0 - v13 BinopI { op=shr, lhs=v12, rhs_imm=2 } -> x6 + v10 Imm(4) -> x0 + v11 Imm(0) -> x0 + v12 Imm(32) -> x0 + v13 Imm(8) -> x6 v14 CallExt { binding_idx=0, args=[v8, v13], fp_arg_mask=0x0 } -> x0 v15 Imm(1) -> x3 v16 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v15) - block 2 start_pc=0 - v17 Phi { incoming=[b15:v1, b1:v15], kind=I64 } -> x3 - v18 Imm(24) -> x0 - v19 Imm(4) -> x1 - v20 Imm(0) -> x1 - v21 Binop { op=add, lhs=v18, rhs=v20 } -> x0 - v22 BinopI { op=shr, lhs=v21, rhs_imm=2 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=6 } -> x0 - terminator Bz { cond=v23, target=b16, fall=b3 } (exit_acc=v23) - block 3 start_pc=0 + terminator Jmp(b1) (exit_acc=v15) + block 9 start_pc=0 v24 ImmData(51) -> x7 v25 Imm(24) -> x0 - v26 Imm(4) -> x1 - v27 Imm(0) -> x1 - v28 Binop { op=add, lhs=v25, rhs=v27 } -> x0 - v29 BinopI { op=shr, lhs=v28, rhs_imm=2 } -> x6 + v26 Imm(4) -> x0 + v27 Imm(0) -> x0 + v28 Imm(24) -> x0 + v29 Imm(6) -> x6 v30 CallExt { binding_idx=0, args=[v24, v29], fp_arg_mask=0x0 } -> x0 v31 Imm(2) -> x3 v32 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v31) - block 4 start_pc=0 - v33 Phi { incoming=[b16:v17, b3:v31], kind=I64 } -> x3 - v34 Imm(64) -> x0 - v35 Imm(4) -> x1 - v36 Imm(0) -> x1 - v37 Binop { op=add, lhs=v34, rhs=v36 } -> x0 - v38 BinopI { op=shr, lhs=v37, rhs_imm=2 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=16 } -> x0 - terminator Bz { cond=v39, target=b17, fall=b5 } (exit_acc=v39) - block 5 start_pc=0 + terminator Jmp(b2) (exit_acc=v31) + block 10 start_pc=0 v40 ImmData(70) -> x7 v41 Imm(64) -> x0 - v42 Imm(4) -> x1 - v43 Imm(0) -> x1 - v44 Binop { op=add, lhs=v41, rhs=v43 } -> x0 - v45 BinopI { op=shr, lhs=v44, rhs_imm=2 } -> x6 + v42 Imm(4) -> x0 + v43 Imm(0) -> x0 + v44 Imm(64) -> x0 + v45 Imm(16) -> x6 v46 CallExt { binding_idx=0, args=[v40, v45], fp_arg_mask=0x0 } -> x0 v47 Imm(3) -> x3 v48 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v47) - block 6 start_pc=0 - v49 Phi { incoming=[b17:v33, b5:v47], kind=I64 } -> x3 - v50 Imm(64) -> x0 - v51 Imm(4) -> x1 - v52 Imm(0) -> x1 - v53 Binop { op=add, lhs=v50, rhs=v52 } -> x0 - v54 BinopI { op=shr, lhs=v53, rhs_imm=2 } -> x0 - v55 BinopI { op=ne, lhs=v54, rhs_imm=16 } -> x0 - terminator Bz { cond=v55, target=b18, fall=b7 } (exit_acc=v55) - block 7 start_pc=0 + terminator Jmp(b3) (exit_acc=v47) + block 11 start_pc=0 v56 ImmData(89) -> x7 v57 Imm(64) -> x0 v58 Imm(4) -> x3 - v59 Imm(0) -> x1 - v60 Binop { op=add, lhs=v57, rhs=v59 } -> x0 - v61 BinopI { op=shr, lhs=v60, rhs_imm=2 } -> x6 + v59 Imm(0) -> x0 + v60 Imm(64) -> x0 + v61 Imm(16) -> x6 v62 CallExt { binding_idx=0, args=[v56, v61], fp_arg_mask=0x0 } -> x0 v63 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v58) - block 8 start_pc=0 - v64 Phi { incoming=[b18:v49, b7:v58], kind=I64 } -> x3 - v65 Imm(24) -> x0 - v66 Imm(4) -> x1 - v67 Imm(0) -> x1 - v68 Binop { op=add, lhs=v65, rhs=v67 } -> x0 - v69 BinopI { op=shr, lhs=v68, rhs_imm=2 } -> x0 - v70 BinopI { op=ne, lhs=v69, rhs_imm=6 } -> x0 - terminator Bz { cond=v70, target=b19, fall=b9 } (exit_acc=v70) - block 9 start_pc=0 + terminator Jmp(b4) (exit_acc=v58) + block 12 start_pc=0 v71 ImmData(108) -> x7 v72 Imm(24) -> x0 - v73 Imm(4) -> x1 - v74 Imm(0) -> x1 - v75 Binop { op=add, lhs=v72, rhs=v74 } -> x0 - v76 BinopI { op=shr, lhs=v75, rhs_imm=2 } -> x6 + v73 Imm(4) -> x0 + v74 Imm(0) -> x0 + v75 Imm(24) -> x0 + v76 Imm(6) -> x6 v77 CallExt { binding_idx=0, args=[v71, v76], fp_arg_mask=0x0 } -> x0 v78 Imm(5) -> x3 v79 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v78) - block 10 start_pc=0 - v80 Phi { incoming=[b19:v64, b9:v78], kind=I64 } -> x3 - v81 Imm(32) -> x0 - v82 Imm(4) -> x1 - v83 Imm(0) -> x1 - v84 Binop { op=add, lhs=v81, rhs=v83 } -> x0 - v85 BinopI { op=shr, lhs=v84, rhs_imm=2 } -> x0 - v86 BinopI { op=ne, lhs=v85, rhs_imm=8 } -> x0 - terminator Bz { cond=v86, target=b20, fall=b11 } (exit_acc=v86) - block 11 start_pc=0 + terminator Jmp(b5) (exit_acc=v78) + block 13 start_pc=0 v87 ImmData(127) -> x7 v88 Imm(32) -> x0 - v89 Imm(4) -> x1 - v90 Imm(0) -> x1 - v91 Binop { op=add, lhs=v88, rhs=v90 } -> x0 - v92 BinopI { op=shr, lhs=v91, rhs_imm=2 } -> x6 + v89 Imm(4) -> x0 + v90 Imm(0) -> x0 + v91 Imm(32) -> x0 + v92 Imm(8) -> x6 v93 CallExt { binding_idx=0, args=[v87, v92], fp_arg_mask=0x0 } -> x0 v94 Imm(6) -> x3 v95 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v94) - block 12 start_pc=0 - v96 Phi { incoming=[b20:v80, b11:v94], kind=I64 } -> x3 - v97 Imm(24) -> x0 - v98 Imm(4) -> x1 - v99 Imm(0) -> x1 - v100 Binop { op=add, lhs=v97, rhs=v99 } -> x0 - v101 BinopI { op=shr, lhs=v100, rhs_imm=2 } -> x0 - v102 BinopI { op=ne, lhs=v101, rhs_imm=6 } -> x0 - terminator Bz { cond=v102, target=b21, fall=b13 } (exit_acc=v102) - block 13 start_pc=0 + terminator Jmp(b6) (exit_acc=v94) + block 14 start_pc=0 v103 ImmData(150) -> x7 v104 Imm(24) -> x0 - v105 Imm(4) -> x1 - v106 Imm(0) -> x1 - v107 Binop { op=add, lhs=v104, rhs=v106 } -> x0 - v108 BinopI { op=shr, lhs=v107, rhs_imm=2 } -> x6 + v105 Imm(4) -> x0 + v106 Imm(0) -> x0 + v107 Imm(24) -> x0 + v108 Imm(6) -> x6 v109 CallExt { binding_idx=0, args=[v103, v108], fp_arg_mask=0x0 } -> x0 v110 Imm(7) -> x3 v111 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v110) - block 14 start_pc=0 - v112 Phi { incoming=[b21:v96, b13:v110], kind=I64 } -> x3 - v113 Extend { value=v112, kind=I32 } -> x0 - terminator Return(v113) (exit_acc=v113) - block 15 start_pc=0 - terminator Jmp(b2) - block 16 start_pc=0 - terminator Jmp(b4) - block 17 start_pc=0 - terminator Jmp(b6) - block 18 start_pc=0 - terminator Jmp(b8) - block 19 start_pc=0 - terminator Jmp(b10) - block 20 start_pc=0 - terminator Jmp(b12) - block 21 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b7) (exit_acc=v110) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/const_expr_cast_narrowing.ssa b/tests/snapshots/ssa/const_expr_cast_narrowing.ssa index 2500a0fde..54397bd53 100644 --- a/tests/snapshots/ssa/const_expr_cast_narrowing.ssa +++ b/tests/snapshots/ssa/const_expr_cast_narrowing.ssa @@ -5,30 +5,30 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(4294967295) -> x0 + v6 Imm(0) -> x0 + v7 LoadLocal { off=-1, kind=U32 } -> x0 + v8 Imm(-4294967296) -> x0 + v9 Imm(-1) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v10) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v12 Imm(0) -> x0 + terminator Return(v12) (exit_acc=v12) block 4 start_pc=0 - v5 Imm(4294967295) -> x0 - v6 Imm(0) -> x1 - v7 LoadLocal { off=-1, kind=U32 } -> x1 - v8 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x1 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=-1 } -> x0 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 5 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 6 start_pc=0 v11 Imm(3) -> x0 terminator Return(v11) (exit_acc=v11) - block 6 start_pc=0 - v12 Imm(0) -> x0 - terminator Return(v12) (exit_acc=v12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/const_expr_unsigned_fold.ssa b/tests/snapshots/ssa/const_expr_unsigned_fold.ssa index f21f6019a..d90a135ad 100644 --- a/tests/snapshots/ssa/const_expr_unsigned_fold.ssa +++ b/tests/snapshots/ssa/const_expr_unsigned_fold.ssa @@ -54,42 +54,40 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 terminator Return(v25) (exit_acc=v25) block 12 start_pc=0 v26 Imm(16) -> x0 - v27 Imm(4) -> x1 - v28 Imm(0) -> x1 - v29 Binop { op=add, lhs=v26, rhs=v28 } -> x0 - v30 BinopI { op=shr, lhs=v29, rhs_imm=2 } -> x0 - v31 BinopI { op=ne, lhs=v30, rhs_imm=4 } -> x0 - terminator Bz { cond=v31, target=b14, fall=b13 } (exit_acc=v31) + v27 Imm(4) -> x0 + v28 Imm(0) -> x0 + v29 Imm(16) -> x0 + v30 Imm(4) -> x0 + v31 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v31) block 13 start_pc=0 - v32 Imm(7) -> x0 - terminator Return(v32) (exit_acc=v32) - block 14 start_pc=0 v33 Imm(12) -> x0 - v34 Imm(4) -> x1 - v35 Imm(0) -> x1 - v36 Binop { op=add, lhs=v33, rhs=v35 } -> x0 - v37 BinopI { op=shr, lhs=v36, rhs_imm=2 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=3 } -> x1 + v34 Imm(4) -> x0 + v35 Imm(0) -> x0 + v36 Imm(12) -> x0 + v37 Imm(3) -> x0 + v38 Imm(0) -> x1 v39 Imm(0) -> x0 - terminator Bnz { cond=v38, target=b19, fall=b15 } (exit_acc=v38) - block 15 start_pc=0 + terminator Jmp(b14) (exit_acc=v38) + block 14 start_pc=0 v40 ImmData(88) -> x0 v41 Load { addr=v40, disp=0, kind=I32 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=0 } -> x1 v43 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v42) - block 16 start_pc=0 - v44 Phi { incoming=[b19:v38, b15:v42], kind=I64 } -> x1 + terminator Jmp(b15) (exit_acc=v42) + block 15 start_pc=0 + v44 Phi { incoming=[b13:v38, b14:v42], kind=I64 } -> x1 v45 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v44, target=b18, fall=b17 } (exit_acc=v44) - block 17 start_pc=0 + terminator Bz { cond=v44, target=b17, fall=b16 } (exit_acc=v44) + block 16 start_pc=0 v46 Imm(8) -> x0 terminator Return(v46) (exit_acc=v46) - block 18 start_pc=0 + block 17 start_pc=0 v47 Imm(0) -> x0 terminator Return(v47) (exit_acc=v47) - block 19 start_pc=0 - terminator Jmp(b16) + block 18 start_pc=0 + v32 Imm(7) -> x0 + terminator Return(v32) (exit_acc=v32) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/const_float_init_int_lead.ssa b/tests/snapshots/ssa/const_float_init_int_lead.ssa index 596275ffc..605067f2d 100644 --- a/tests/snapshots/ssa/const_float_init_int_lead.ssa +++ b/tests/snapshots/ssa/const_float_init_int_lead.ssa @@ -26,17 +26,16 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 4 start_pc=0 v13 ImmData(24) -> x0 v14 Load { addr=v13, disp=0, kind=F32 } -> d0 [f32] - v15 Imm(4609434218613702656) -> x0 - v16 FpCast { kind=F32ToF64, value=v14 } -> d0 - v17 Binop { op=feq, lhs=v16, rhs=v15 } -> x0 - v18 BinopI { op=eq, lhs=v17, rhs_imm=0 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v15 Imm(1069547520) -> x0 [f32] + v16 Binop { op=feq, lhs=v14, rhs=v15 } -> x0 + v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x0 + terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) block 5 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v18 Imm(3) -> x0 + terminator Return(v18) (exit_acc=v18) block 6 start_pc=0 - v20 Imm(0) -> x0 - terminator Return(v20) (exit_acc=v20) + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/constfold_post_inline.ssa b/tests/snapshots/ssa/constfold_post_inline.ssa new file mode 100644 index 000000000..ea4b7a785 --- /dev/null +++ b/tests/snapshots/ssa/constfold_post_inline.ssa @@ -0,0 +1,987 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=add_u +fn ent_pc=0 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=add, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=mul_u +fn ent_pc=1 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=mul, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=sub_i +fn ent_pc=2 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=sub, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=3 --- +; name=shl_u +fn ent_pc=3 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=shl, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=4 --- +; name=shr_u +fn ent_pc=4 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=shru, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=5 --- +; name=shr_i +fn ent_pc=5 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=shr, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=6 --- +; name=div_u +fn ent_pc=6 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=divu, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=7 --- +; name=mod_u +fn ent_pc=7 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=modu, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=8 --- +; name=div_i +fn ent_pc=8 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=div, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=9 --- +; name=mod_i +fn ent_pc=9 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=mod, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=10 --- +; name=ror_u +fn ent_pc=10 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=shru, lhs=v1, rhs=v3 } -> x0 + v8 Imm(64) -> x0 + v9 Binop { op=sub, lhs=v8, rhs=v3 } -> x0 + v10 BinopI { op=shl, lhs=v9, rhs_imm=32 } -> x1 + v11 Extend { value=v9, kind=I32 } -> x0 + v12 Binop { op=shl, lhs=v1, rhs=v11 } -> x0 + v13 Binop { op=ror, lhs=v1, rhs=v3 } -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=11 --- +; name=lt_i +fn ent_pc=11 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=lt, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=12 --- +; name=gt_i +fn ent_pc=12 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=gt, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=13 --- +; name=le_i +fn ent_pc=13 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=le, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=14 --- +; name=ge_i +fn ent_pc=14 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=ge, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=15 --- +; name=lt_u +fn ent_pc=15 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=ult, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=16 --- +; name=gt_u +fn ent_pc=16 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=ugt, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=17 --- +; name=le_u +fn ent_pc=17 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=ule, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=18 --- +; name=ge_u +fn ent_pc=18 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=uge, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=19 --- +; name=eq_i +fn ent_pc=19 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=eq, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=20 --- +; name=ne_i +fn ent_pc=20 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I64 } -> x0 + v7 Binop { op=ne, lhs=v1, rhs=v3 } -> x0 + terminator Return(v7) (exit_acc=v7) +; --- SSA dump (ok=true) ent_pc=21 --- +; name=sext8 +fn ent_pc=21 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I8) -> x0 + v2 Imm(0) -> x1 + v3 LoadLocal { off=2, kind=I8 } -> x1 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=22 --- +; name=sext16 +fn ent_pc=22 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I16) -> x0 + v2 Imm(0) -> x1 + v3 LoadLocal { off=2, kind=I16 } -> x1 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=23 --- +; name=sext32 +fn ent_pc=23 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x0 + v2 Imm(0) -> x1 + v3 LoadLocal { off=2, kind=I32 } -> x1 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=24 --- +; name=main +fn ent_pc=24 n_params=0 variadic=false locals=15 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(-1) -> x0 + v2 Imm(2) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) + block 1 start_pc=0 + v8 Imm(-1) -> x0 + v9 Imm(3) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(-3) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) + block 2 start_pc=0 + v15 Imm(-5) -> x0 + v16 Imm(9223372036854775807) -> x0 + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + v19 Imm(9223372036854775804) -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v20) + block 3 start_pc=0 + v22 Imm(81985529216486895) -> x0 + v23 Imm(4) -> x0 + v24 Imm(0) -> x0 + v25 Imm(4) -> x0 + v26 Imm(0) -> x0 + v27 Imm(1311768467463790320) -> x0 + v28 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v28) + block 4 start_pc=0 + v30 Imm(81985529216486895) -> x0 + v31 Imm(64) -> x0 + v32 Imm(0) -> x0 + v33 Imm(64) -> x0 + v34 Imm(0) -> x0 + v35 Imm(81985529216486895) -> x0 + v36 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v36) + block 5 start_pc=0 + v38 Imm(81985529216486895) -> x0 + v39 Imm(65) -> x0 + v40 Imm(0) -> x0 + v41 Imm(65) -> x0 + v42 Imm(0) -> x0 + v43 Imm(163971058432973790) -> x0 + v44 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v44) + block 6 start_pc=0 + v46 Imm(81985529216486895) -> x0 + v47 Imm(3) -> x0 + v48 Imm(0) -> x0 + v49 Imm(3) -> x0 + v50 Imm(0) -> x0 + v51 Imm(10248191152060861) -> x0 + v52 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v52) + block 7 start_pc=0 + v54 Imm(-9223372036854775808) -> x0 + v55 Imm(63) -> x0 + v56 Imm(0) -> x0 + v57 Imm(63) -> x0 + v58 Imm(0) -> x0 + v59 Imm(1) -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v60) + block 8 start_pc=0 + v62 Imm(-8) -> x0 + v63 Imm(1) -> x0 + v64 Imm(0) -> x0 + v65 Imm(1) -> x0 + v66 Imm(0) -> x0 + v67 Imm(-4) -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v68) + block 9 start_pc=0 + v70 Imm(-1) -> x0 + v71 Imm(63) -> x0 + v72 Imm(0) -> x0 + v73 Imm(63) -> x0 + v74 Imm(0) -> x0 + v75 Imm(-1) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v76) + block 10 start_pc=0 + v78 Imm(-1) -> x0 + v79 Imm(3) -> x0 + v80 Imm(0) -> x0 + v81 Imm(0) -> x0 + v82 Imm(6148914691236517205) -> x0 + v83 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v83) + block 11 start_pc=0 + v85 Imm(-1) -> x0 + v86 Imm(7) -> x0 + v87 Imm(0) -> x0 + v88 Imm(0) -> x0 + v89 Imm(1) -> x0 + v90 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v90) + block 12 start_pc=0 + v92 Imm(-9223372036854775808) -> x0 + v93 Imm(-1) -> x0 + v94 Imm(0) -> x0 + v95 Imm(0) -> x0 + v96 Imm(0) -> x0 + v97 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v97) + block 13 start_pc=0 + v99 Imm(-9223372036854775808) -> x0 + v100 Imm(-1) -> x0 + v101 Imm(0) -> x0 + v102 Imm(0) -> x0 + v103 Imm(-9223372036854775808) -> x0 + v104 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v104) + block 14 start_pc=0 + v106 Imm(-7) -> x0 + v107 Imm(2) -> x0 + v108 Imm(0) -> x0 + v109 Imm(0) -> x0 + v110 Imm(-3) -> x0 + v111 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v111) + block 15 start_pc=0 + v113 Imm(-7) -> x0 + v114 Imm(2) -> x0 + v115 Imm(0) -> x0 + v116 Imm(0) -> x0 + v117 Imm(-1) -> x0 + v118 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v118) + block 16 start_pc=0 + v120 Imm(7) -> x0 + v121 Imm(-2) -> x0 + v122 Imm(0) -> x0 + v123 Imm(0) -> x0 + v124 Imm(-3) -> x0 + v125 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v125) + block 17 start_pc=0 + v127 Imm(7) -> x0 + v128 Imm(-2) -> x0 + v129 Imm(0) -> x0 + v130 Imm(0) -> x0 + v131 Imm(1) -> x0 + v132 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v132) + block 18 start_pc=0 + v134 Imm(81985529216486895) -> x0 + v135 Imm(7) -> x0 + v136 Imm(0) -> x0 + v137 Imm(7) -> x0 + v138 Imm(0) -> x0 + v139 Imm(640511947003803) -> x0 + v140 Imm(64) -> x0 + v141 Imm(57) -> x0 + v142 Imm(244813135872) -> x0 + v143 Imm(57) -> x0 + v144 Imm(-2449958197289549824) -> x0 + v145 Imm(-2449317685342546021) -> x0 + v146 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v146) + block 19 start_pc=0 + v148 Imm(-2) -> x0 + v149 Imm(1) -> x0 + v150 Imm(0) -> x0 + v151 Imm(0) -> x0 + v152 Imm(1) -> x0 + v153 Imm(0) -> x1 + v154 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v153) + block 20 start_pc=0 + v155 Imm(1) -> x0 + v156 Imm(-2) -> x0 + v157 Imm(0) -> x0 + v158 Imm(0) -> x0 + v159 Imm(0) -> x1 + v160 Imm(0) -> x0 + terminator Jmp(b21) (exit_acc=v159) + block 21 start_pc=0 + v161 Phi { incoming=[b19:v153, b20:v159], kind=I64 } -> x1 + v162 LoadLocal { off=-6, kind=I64 } -> x0 + terminator Bz { cond=v161, target=b23, fall=b22 } (exit_acc=v161) + block 22 start_pc=0 + v163 Imm(20) -> x0 + terminator Return(v163) (exit_acc=v163) + block 23 start_pc=0 + v164 Imm(1) -> x0 + v165 Imm(-2) -> x0 + v166 Imm(0) -> x0 + v167 Imm(0) -> x0 + v168 Imm(1) -> x0 + v169 Imm(0) -> x1 + v170 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v169) + block 24 start_pc=0 + v171 Imm(-2) -> x0 + v172 Imm(1) -> x0 + v173 Imm(0) -> x0 + v174 Imm(0) -> x0 + v175 Imm(0) -> x1 + v176 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v175) + block 25 start_pc=0 + v177 Phi { incoming=[b23:v169, b24:v175], kind=I64 } -> x1 + v178 LoadLocal { off=-7, kind=I64 } -> x0 + terminator Bz { cond=v177, target=b27, fall=b26 } (exit_acc=v177) + block 26 start_pc=0 + v179 Imm(21) -> x0 + terminator Return(v179) (exit_acc=v179) + block 27 start_pc=0 + v180 Imm(3) -> x0 + v181 Imm(0) -> x0 + v182 Imm(0) -> x0 + v183 Imm(1) -> x0 + v184 Imm(0) -> x1 + v185 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v184) + block 28 start_pc=0 + v186 Imm(4) -> x0 + v187 Imm(3) -> x0 + v188 Imm(0) -> x0 + v189 Imm(0) -> x0 + v190 Imm(0) -> x1 + v191 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v190) + block 29 start_pc=0 + v192 Phi { incoming=[b27:v184, b28:v190], kind=I64 } -> x1 + v193 LoadLocal { off=-8, kind=I64 } -> x0 + terminator Bz { cond=v192, target=b31, fall=b30 } (exit_acc=v192) + block 30 start_pc=0 + v194 Imm(22) -> x0 + terminator Return(v194) (exit_acc=v194) + block 31 start_pc=0 + v195 Imm(3) -> x0 + v196 Imm(0) -> x0 + v197 Imm(0) -> x0 + v198 Imm(1) -> x0 + v199 Imm(0) -> x1 + v200 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v199) + block 32 start_pc=0 + v201 Imm(3) -> x0 + v202 Imm(4) -> x0 + v203 Imm(0) -> x0 + v204 Imm(0) -> x0 + v205 Imm(0) -> x1 + v206 Imm(0) -> x0 + terminator Jmp(b33) (exit_acc=v205) + block 33 start_pc=0 + v207 Phi { incoming=[b31:v199, b32:v205], kind=I64 } -> x1 + v208 LoadLocal { off=-9, kind=I64 } -> x0 + terminator Bz { cond=v207, target=b35, fall=b34 } (exit_acc=v207) + block 34 start_pc=0 + v209 Imm(23) -> x0 + terminator Return(v209) (exit_acc=v209) + block 35 start_pc=0 + v210 Imm(1) -> x0 + v211 Imm(-1) -> x0 + v212 Imm(0) -> x0 + v213 Imm(0) -> x0 + v214 Imm(1) -> x0 + v215 Imm(0) -> x1 + v216 Imm(0) -> x0 + terminator Jmp(b36) (exit_acc=v215) + block 36 start_pc=0 + v217 Imm(-1) -> x0 + v218 Imm(1) -> x0 + v219 Imm(0) -> x0 + v220 Imm(0) -> x0 + v221 Imm(0) -> x1 + v222 Imm(0) -> x0 + terminator Jmp(b37) (exit_acc=v221) + block 37 start_pc=0 + v223 Phi { incoming=[b35:v215, b36:v221], kind=I64 } -> x1 + v224 LoadLocal { off=-10, kind=I64 } -> x0 + terminator Bz { cond=v223, target=b39, fall=b38 } (exit_acc=v223) + block 38 start_pc=0 + v225 Imm(24) -> x0 + terminator Return(v225) (exit_acc=v225) + block 39 start_pc=0 + v226 Imm(-1) -> x0 + v227 Imm(1) -> x0 + v228 Imm(0) -> x0 + v229 Imm(0) -> x0 + v230 Imm(1) -> x0 + v231 Imm(0) -> x1 + v232 Imm(0) -> x0 + terminator Jmp(b40) (exit_acc=v231) + block 40 start_pc=0 + v233 Imm(1) -> x0 + v234 Imm(-1) -> x0 + v235 Imm(0) -> x0 + v236 Imm(0) -> x0 + v237 Imm(0) -> x1 + v238 Imm(0) -> x0 + terminator Jmp(b41) (exit_acc=v237) + block 41 start_pc=0 + v239 Phi { incoming=[b39:v231, b40:v237], kind=I64 } -> x1 + v240 LoadLocal { off=-11, kind=I64 } -> x0 + terminator Bz { cond=v239, target=b43, fall=b42 } (exit_acc=v239) + block 42 start_pc=0 + v241 Imm(25) -> x0 + terminator Return(v241) (exit_acc=v241) + block 43 start_pc=0 + v242 Imm(5) -> x0 + v243 Imm(0) -> x0 + v244 Imm(0) -> x0 + v245 Imm(1) -> x0 + v246 Imm(0) -> x1 + v247 Imm(0) -> x0 + terminator Jmp(b44) (exit_acc=v246) + block 44 start_pc=0 + v248 Imm(6) -> x0 + v249 Imm(5) -> x0 + v250 Imm(0) -> x0 + v251 Imm(0) -> x0 + v252 Imm(0) -> x1 + v253 Imm(0) -> x0 + terminator Jmp(b45) (exit_acc=v252) + block 45 start_pc=0 + v254 Phi { incoming=[b43:v246, b44:v252], kind=I64 } -> x1 + v255 LoadLocal { off=-12, kind=I64 } -> x0 + terminator Bz { cond=v254, target=b47, fall=b46 } (exit_acc=v254) + block 46 start_pc=0 + v256 Imm(26) -> x0 + terminator Return(v256) (exit_acc=v256) + block 47 start_pc=0 + v257 Imm(5) -> x0 + v258 Imm(0) -> x0 + v259 Imm(0) -> x0 + v260 Imm(1) -> x0 + v261 Imm(0) -> x1 + v262 Imm(0) -> x0 + terminator Jmp(b48) (exit_acc=v261) + block 48 start_pc=0 + v263 Imm(5) -> x0 + v264 Imm(6) -> x0 + v265 Imm(0) -> x0 + v266 Imm(0) -> x0 + v267 Imm(0) -> x1 + v268 Imm(0) -> x0 + terminator Jmp(b49) (exit_acc=v267) + block 49 start_pc=0 + v269 Phi { incoming=[b47:v261, b48:v267], kind=I64 } -> x1 + v270 LoadLocal { off=-13, kind=I64 } -> x0 + terminator Bz { cond=v269, target=b51, fall=b50 } (exit_acc=v269) + block 50 start_pc=0 + v271 Imm(27) -> x0 + terminator Return(v271) (exit_acc=v271) + block 51 start_pc=0 + v272 Imm(-1) -> x0 + v273 Imm(0) -> x0 + v274 Imm(0) -> x0 + v275 Imm(1) -> x0 + v276 Imm(0) -> x1 + v277 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v276) + block 52 start_pc=0 + v278 Imm(-1) -> x0 + v279 Imm(1) -> x0 + v280 Imm(0) -> x0 + v281 Imm(0) -> x0 + v282 Imm(0) -> x1 + v283 Imm(0) -> x0 + terminator Jmp(b53) (exit_acc=v282) + block 53 start_pc=0 + v284 Phi { incoming=[b51:v276, b52:v282], kind=I64 } -> x1 + v285 LoadLocal { off=-14, kind=I64 } -> x0 + terminator Bz { cond=v284, target=b55, fall=b54 } (exit_acc=v284) + block 54 start_pc=0 + v286 Imm(28) -> x0 + terminator Return(v286) (exit_acc=v286) + block 55 start_pc=0 + v287 Imm(-1) -> x0 + v288 Imm(1) -> x0 + v289 Imm(0) -> x0 + v290 Imm(0) -> x0 + v291 Imm(1) -> x0 + v292 Imm(0) -> x1 + v293 Imm(0) -> x0 + terminator Jmp(b56) (exit_acc=v292) + block 56 start_pc=0 + v294 Imm(-1) -> x0 + v295 Imm(0) -> x0 + v296 Imm(0) -> x0 + v297 Imm(0) -> x1 + v298 Imm(0) -> x0 + terminator Jmp(b57) (exit_acc=v297) + block 57 start_pc=0 + v299 Phi { incoming=[b55:v292, b56:v297], kind=I64 } -> x1 + v300 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Bz { cond=v299, target=b59, fall=b58 } (exit_acc=v299) + block 58 start_pc=0 + v301 Imm(29) -> x0 + terminator Return(v301) (exit_acc=v301) + block 59 start_pc=0 + v302 Imm(-100) -> x0 + v303 Imm(-100) -> x0 + v304 Imm(0) -> x0 + v305 Imm(0) -> x0 + terminator Jmp(b60) (exit_acc=v305) + block 60 start_pc=0 + v307 Imm(511) -> x0 + v308 Imm(-1) -> x0 + v309 Imm(0) -> x0 + v310 Imm(0) -> x0 + terminator Jmp(b61) (exit_acc=v310) + block 61 start_pc=0 + v312 Imm(-30000) -> x0 + v313 Imm(-30000) -> x0 + v314 Imm(0) -> x0 + v315 Imm(0) -> x0 + terminator Jmp(b62) (exit_acc=v315) + block 62 start_pc=0 + v317 Imm(98304) -> x0 + v318 Imm(-32768) -> x0 + v319 Imm(0) -> x0 + v320 Imm(0) -> x0 + terminator Jmp(b63) (exit_acc=v320) + block 63 start_pc=0 + v322 Imm(-2000000000) -> x0 + v323 Imm(-2000000000) -> x0 + v324 Imm(0) -> x0 + v325 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v325) + block 64 start_pc=0 + v327 Imm(66571993088) -> x0 + v328 Imm(-2147483648) -> x0 + v329 Imm(0) -> x0 + v330 Imm(0) -> x0 + terminator Jmp(b65) (exit_acc=v330) + block 65 start_pc=0 + v332 Imm(81985529216486895) -> x0 + v333 StoreLocal { off=-1, value=v332, kind=I64, volatile } -> - + v334 LoadLocal { off=-1, kind=I64, volatile } -> x0 + v335 Imm(0) -> x1 + v336 Imm(5) -> x1 + v337 LoadLocal { off=-2, kind=I64 } -> x1 + v338 BinopI { op=add, lhs=v334, rhs_imm=5 } -> x1 + v339 BinopI { op=ne, lhs=v338, rhs_imm=81985529216486900 } -> x1 + terminator Bz { cond=v339, target=b67, fall=b66 } (exit_acc=v339) + block 66 start_pc=0 + v340 Imm(36) -> x0 + terminator Return(v340) (exit_acc=v340) + block 67 start_pc=0 + v341 LoadLocal { off=-2, kind=I64 } -> x1 + v342 BinopI { op=add, lhs=v334, rhs_imm=5 } -> x1 + v343 BinopI { op=ne, lhs=v342, rhs_imm=81985529216486900 } -> x1 + terminator Bz { cond=v343, target=b69, fall=b68 } (exit_acc=v343) + block 68 start_pc=0 + v344 Imm(37) -> x0 + terminator Return(v344) (exit_acc=v344) + block 69 start_pc=0 + v345 Imm(100) -> x1 + v346 LoadLocal { off=-2, kind=I64 } -> x1 + v347 BinopI { op=ugt, lhs=v334, rhs_imm=100 } -> x1 + v348 BinopI { op=eq, lhs=v347, rhs_imm=0 } -> x1 + terminator Bz { cond=v348, target=b71, fall=b70 } (exit_acc=v348) + block 70 start_pc=0 + v349 Imm(38) -> x0 + terminator Return(v349) (exit_acc=v349) + block 71 start_pc=0 + v350 Imm(100) -> x1 + v351 LoadLocal { off=-2, kind=I64 } -> x1 + v352 BinopI { op=ult, lhs=v334, rhs_imm=100 } -> x1 + terminator Bz { cond=v352, target=b73, fall=b72 } (exit_acc=v352) + block 72 start_pc=0 + v353 Imm(39) -> x0 + terminator Return(v353) (exit_acc=v353) + block 73 start_pc=0 + v354 Imm(-1) -> x1 + v355 LoadLocal { off=-2, kind=I64 } -> x1 + v356 BinopI { op=ule, lhs=v334, rhs_imm=-1 } -> x1 + v357 BinopI { op=eq, lhs=v356, rhs_imm=0 } -> x1 + terminator Bz { cond=v357, target=b75, fall=b74 } (exit_acc=v357) + block 74 start_pc=0 + v358 Imm(40) -> x0 + terminator Return(v358) (exit_acc=v358) + block 75 start_pc=0 + v359 LoadLocal { off=-2, kind=I64 } -> x1 + v360 Imm(7) -> x1 + v361 Imm(0) -> x1 + v362 Imm(7) -> x1 + v363 Imm(0) -> x1 + v364 BinopI { op=shru, lhs=v334, rhs_imm=7 } -> x1 + v365 Imm(64) -> x1 + v366 Imm(57) -> x1 + v367 Imm(244813135872) -> x1 + v368 Imm(57) -> x1 + v369 BinopI { op=shl, lhs=v334, rhs_imm=57 } -> x1 + v370 BinopI { op=ror, lhs=v334, rhs_imm=7 } -> x1 + v371 BinopI { op=ne, lhs=v370, rhs_imm=-2449317685342546021 } -> x1 + terminator Bz { cond=v371, target=b77, fall=b76 } (exit_acc=v371) + block 76 start_pc=0 + v372 Imm(41) -> x0 + terminator Return(v372) (exit_acc=v372) + block 77 start_pc=0 + v373 LoadLocal { off=-2, kind=I64 } -> x1 + v374 Imm(65) -> x1 + v375 Imm(0) -> x1 + v376 Imm(65) -> x1 + v377 Imm(0) -> x1 + v378 BinopI { op=shl, lhs=v334, rhs_imm=65 } -> x0 + v379 BinopI { op=ne, lhs=v378, rhs_imm=163971058432973790 } -> x0 + terminator Bz { cond=v379, target=b79, fall=b78 } (exit_acc=v379) + block 78 start_pc=0 + v380 Imm(42) -> x0 + terminator Return(v380) (exit_acc=v380) + block 79 start_pc=0 + v381 Imm(-8) -> x0 + v382 StoreLocal { off=-3, value=v381, kind=I64, volatile } -> - + v383 LoadLocal { off=-3, kind=I64, volatile } -> x0 + v384 Imm(1) -> x1 + v385 Imm(0) -> x1 + v386 Imm(1) -> x1 + v387 Imm(0) -> x1 + v388 BinopI { op=shr, lhs=v383, rhs_imm=1 } -> x0 + v389 BinopI { op=ne, lhs=v388, rhs_imm=-4 } -> x0 + terminator Bz { cond=v389, target=b81, fall=b80 } (exit_acc=v389) + block 80 start_pc=0 + v390 Imm(43) -> x0 + terminator Return(v390) (exit_acc=v390) + block 81 start_pc=0 + v391 Imm(0) -> x0 + terminator Return(v391) (exit_acc=v391) + block 82 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 83 start_pc=0 + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) + block 84 start_pc=0 + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) + block 85 start_pc=0 + v29 Imm(4) -> x0 + terminator Return(v29) (exit_acc=v29) + block 86 start_pc=0 + v37 Imm(5) -> x0 + terminator Return(v37) (exit_acc=v37) + block 87 start_pc=0 + v45 Imm(6) -> x0 + terminator Return(v45) (exit_acc=v45) + block 88 start_pc=0 + v53 Imm(7) -> x0 + terminator Return(v53) (exit_acc=v53) + block 89 start_pc=0 + v61 Imm(8) -> x0 + terminator Return(v61) (exit_acc=v61) + block 90 start_pc=0 + v69 Imm(9) -> x0 + terminator Return(v69) (exit_acc=v69) + block 91 start_pc=0 + v77 Imm(10) -> x0 + terminator Return(v77) (exit_acc=v77) + block 92 start_pc=0 + v84 Imm(11) -> x0 + terminator Return(v84) (exit_acc=v84) + block 93 start_pc=0 + v91 Imm(12) -> x0 + terminator Return(v91) (exit_acc=v91) + block 94 start_pc=0 + v98 Imm(13) -> x0 + terminator Return(v98) (exit_acc=v98) + block 95 start_pc=0 + v105 Imm(14) -> x0 + terminator Return(v105) (exit_acc=v105) + block 96 start_pc=0 + v112 Imm(15) -> x0 + terminator Return(v112) (exit_acc=v112) + block 97 start_pc=0 + v119 Imm(16) -> x0 + terminator Return(v119) (exit_acc=v119) + block 98 start_pc=0 + v126 Imm(17) -> x0 + terminator Return(v126) (exit_acc=v126) + block 99 start_pc=0 + v133 Imm(18) -> x0 + terminator Return(v133) (exit_acc=v133) + block 100 start_pc=0 + v147 Imm(19) -> x0 + terminator Return(v147) (exit_acc=v147) + block 101 start_pc=0 + v306 Imm(30) -> x0 + terminator Return(v306) (exit_acc=v306) + block 102 start_pc=0 + v311 Imm(31) -> x0 + terminator Return(v311) (exit_acc=v311) + block 103 start_pc=0 + v316 Imm(32) -> x0 + terminator Return(v316) (exit_acc=v316) + block 104 start_pc=0 + v321 Imm(33) -> x0 + terminator Return(v321) (exit_acc=v321) + block 105 start_pc=0 + v326 Imm(34) -> x0 + terminator Return(v326) (exit_acc=v326) + block 106 start_pc=0 + v331 Imm(35) -> x0 + terminator Return(v331) (exit_acc=v331) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/control_flow.ssa b/tests/snapshots/ssa/control_flow.ssa index 2979352a7..e91cd9b8c 100644 --- a/tests/snapshots/ssa/control_flow.ssa +++ b/tests/snapshots/ssa/control_flow.ssa @@ -4,31 +4,58 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=5 } -> x0 - terminator Bz { cond=v5, target=b3, fall=b2 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 Imm(0) -> x0 + v6 Imm(1) -> x0 + v7 Imm(4294967296) -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + v10 Imm(1) -> x0 + v11 Imm(1) -> x0 + v12 Imm(1) -> x0 + v13 Imm(2) -> x0 + v14 Imm(8589934592) -> x0 + v15 Imm(2) -> x0 + v16 Imm(0) -> x0 + v17 Imm(2) -> x0 + v18 Imm(1) -> x0 + v19 Imm(2) -> x0 + v20 Imm(3) -> x0 + v21 Imm(12884901888) -> x0 + v22 Imm(3) -> x0 + v23 Imm(0) -> x0 + v24 Imm(3) -> x0 + v25 Imm(1) -> x0 + v26 Imm(3) -> x0 + v27 Imm(4) -> x0 + v28 Imm(17179869184) -> x0 + v29 Imm(4) -> x0 + v30 Imm(0) -> x0 + v31 Imm(4) -> x0 + v32 Imm(1) -> x0 + v33 Imm(4) -> x0 + v34 Imm(5) -> x0 + v35 Imm(21474836480) -> x0 + v36 Imm(5) -> x0 + v37 Imm(0) -> x0 + v38 Imm(5) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v39) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + v40 Imm(5) -> x0 + v41 Imm(1) -> x0 + terminator Jmp(b3) (exit_acc=v41) block 3 start_pc=0 - v11 Extend { value=v3, kind=I32 } -> x0 - v12 BinopI { op=eq, lhs=v11, rhs_imm=5 } -> x0 - terminator Bz { cond=v12, target=b5, fall=b4 } (exit_acc=v12) + v42 Imm(1) -> x0 + terminator Return(v42) (exit_acc=v42) block 4 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) - block 5 start_pc=0 - v14 Imm(0) -> x0 - terminator Return(v14) (exit_acc=v14) + v43 Imm(0) -> x0 + terminator Return(v43) (exit_acc=v43) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/data_reloc_one_past_end.ssa b/tests/snapshots/ssa/data_reloc_one_past_end.ssa index d78ef6ed1..70c3ebd18 100644 --- a/tests/snapshots/ssa/data_reloc_one_past_end.ssa +++ b/tests/snapshots/ssa/data_reloc_one_past_end.ssa @@ -8,16 +8,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v2 Imm(0) -> x0 v3 ImmData(8) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v3, b2:v16], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x2 - v7 LoadLocal { off=-2, kind=I64 } -> x0 - v8 ImmData(40) -> x0 - v9 Load { addr=v8, disp=0, kind=I64 } -> x0 - v10 Binop { op=ne, lhs=v5, rhs=v9 } -> x0 - terminator Bz { cond=v10, target=b3, fall=b2 } (exit_acc=v10) - block 2 start_pc=0 v11 LoadLocal { off=-1, kind=I64 } -> x0 v12 LoadLocal { off=-2, kind=I64 } -> x0 v13 Load { addr=v5, disp=0, kind=I64 } -> x0 @@ -25,7 +17,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v15 Imm(0) -> x0 v16 BinopI { op=add, lhs=v5, rhs_imm=8 } -> x1 v17 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v16) + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v5 Phi { incoming=[b0:v3, b1:v16], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b1:v14], kind=I64 } -> x2 + v7 LoadLocal { off=-2, kind=I64 } -> x0 + v8 ImmData(40) -> x0 + v9 Load { addr=v8, disp=0, kind=I64 } -> x0 + v10 Binop { op=ne, lhs=v5, rhs=v9 } -> x0 + terminator Bnz { cond=v10, target=b1, fall=b3 } (exit_acc=v10) block 3 start_pc=0 v18 LoadLocal { off=-1, kind=I64 } -> x0 v19 ImmData(56) -> x0 diff --git a/tests/snapshots/ssa/dead_local_load_frame_elide.ssa b/tests/snapshots/ssa/dead_local_load_frame_elide.ssa new file mode 100644 index 000000000..19586a938 --- /dev/null +++ b/tests/snapshots/ssa/dead_local_load_frame_elide.ssa @@ -0,0 +1,308 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=fold +fn ent_pc=0 n_params=1 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x1 + v5 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v3) + block 1 start_pc=0 + v6 LoadLocal { off=-1, kind=I64 } -> x0 + v7 Imm(1) -> x0 + v8 LoadLocal { off=-2, kind=I64 } -> x0 + v9 Imm(0) -> x0 + v10 LoadLocal { off=2, kind=I64 } -> x0 + v11 LoadLocal { off=-1, kind=I64 } -> x0 + v12 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 + v13 Load { addr=v12, disp=0, kind=U8 } -> x0 + v14 BinopI { op=or, lhs=v13, rhs_imm=0 } -> x0 + v15 Imm(0) -> x1 + v16 LoadLocal { off=-1, kind=I64 } -> x1 + v17 Imm(1) -> x1 + v18 Imm(0) -> x1 + v19 LoadLocal { off=-1, kind=I64 } -> x1 + v20 Imm(1) -> x1 + v21 LoadLocal { off=-2, kind=I64 } -> x1 + v22 BinopI { op=shl, lhs=v14, rhs_imm=8 } -> x0 + v23 LoadLocal { off=2, kind=I64 } -> x1 + v24 LoadLocal { off=-1, kind=I64 } -> x1 + v25 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x1 + v26 Load { addr=v1, disp=1, kind=U8 } -> x1 + v27 Binop { op=or, lhs=v22, rhs=v26 } -> x0 + v28 Imm(0) -> x1 + v29 LoadLocal { off=-1, kind=I64 } -> x1 + v30 Imm(2) -> x1 + v31 Imm(0) -> x1 + v32 LoadLocal { off=-1, kind=I64 } -> x1 + v33 Imm(1) -> x1 + v34 LoadLocal { off=-2, kind=I64 } -> x1 + v35 BinopI { op=shl, lhs=v27, rhs_imm=8 } -> x0 + v36 LoadLocal { off=2, kind=I64 } -> x1 + v37 LoadLocal { off=-1, kind=I64 } -> x1 + v38 BinopI { op=add, lhs=v1, rhs_imm=2 } -> x1 + v39 Load { addr=v1, disp=2, kind=U8 } -> x1 + v40 Binop { op=or, lhs=v35, rhs=v39 } -> x0 + v41 Imm(0) -> x1 + v42 LoadLocal { off=-1, kind=I64 } -> x1 + v43 Imm(3) -> x1 + v44 Imm(0) -> x1 + v45 LoadLocal { off=-1, kind=I64 } -> x1 + v46 Imm(1) -> x1 + v47 LoadLocal { off=-2, kind=I64 } -> x1 + v48 BinopI { op=shl, lhs=v40, rhs_imm=8 } -> x0 + v49 LoadLocal { off=2, kind=I64 } -> x1 + v50 LoadLocal { off=-1, kind=I64 } -> x1 + v51 BinopI { op=add, lhs=v1, rhs_imm=3 } -> x1 + v52 Load { addr=v1, disp=3, kind=U8 } -> x1 + v53 Binop { op=or, lhs=v48, rhs=v52 } -> x0 + v54 Imm(0) -> x1 + v55 LoadLocal { off=-1, kind=I64 } -> x1 + v56 Imm(4) -> x1 + v57 Imm(0) -> x1 + v58 LoadLocal { off=-1, kind=I64 } -> x1 + v59 Imm(1) -> x1 + v60 LoadLocal { off=-2, kind=I64 } -> x1 + v61 BinopI { op=shl, lhs=v53, rhs_imm=8 } -> x0 + v62 LoadLocal { off=2, kind=I64 } -> x1 + v63 LoadLocal { off=-1, kind=I64 } -> x1 + v64 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 + v65 Load { addr=v1, disp=4, kind=U8 } -> x1 + v66 Binop { op=or, lhs=v61, rhs=v65 } -> x0 + v67 Imm(0) -> x1 + v68 LoadLocal { off=-1, kind=I64 } -> x1 + v69 Imm(5) -> x1 + v70 Imm(0) -> x1 + v71 LoadLocal { off=-1, kind=I64 } -> x1 + v72 Imm(1) -> x1 + v73 LoadLocal { off=-2, kind=I64 } -> x1 + v74 BinopI { op=shl, lhs=v66, rhs_imm=8 } -> x0 + v75 LoadLocal { off=2, kind=I64 } -> x1 + v76 LoadLocal { off=-1, kind=I64 } -> x1 + v77 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x1 + v78 Load { addr=v1, disp=5, kind=U8 } -> x1 + v79 Binop { op=or, lhs=v74, rhs=v78 } -> x0 + v80 Imm(0) -> x1 + v81 LoadLocal { off=-1, kind=I64 } -> x1 + v82 Imm(6) -> x1 + v83 Imm(0) -> x1 + v84 LoadLocal { off=-1, kind=I64 } -> x1 + v85 Imm(1) -> x1 + v86 LoadLocal { off=-2, kind=I64 } -> x1 + v87 BinopI { op=shl, lhs=v79, rhs_imm=8 } -> x0 + v88 LoadLocal { off=2, kind=I64 } -> x1 + v89 LoadLocal { off=-1, kind=I64 } -> x1 + v90 BinopI { op=add, lhs=v1, rhs_imm=6 } -> x1 + v91 Load { addr=v1, disp=6, kind=U8 } -> x1 + v92 Binop { op=or, lhs=v87, rhs=v91 } -> x0 + v93 Imm(0) -> x1 + v94 LoadLocal { off=-1, kind=I64 } -> x1 + v95 Imm(7) -> x1 + v96 Imm(0) -> x1 + v97 LoadLocal { off=-1, kind=I64 } -> x1 + v98 Imm(1) -> x1 + v99 LoadLocal { off=-2, kind=I64 } -> x1 + v100 BinopI { op=shl, lhs=v92, rhs_imm=8 } -> x0 + v101 LoadLocal { off=2, kind=I64 } -> x1 + v102 LoadLocal { off=-1, kind=I64 } -> x1 + v103 BinopI { op=add, lhs=v1, rhs_imm=7 } -> x1 + v104 Load { addr=v1, disp=7, kind=U8 } -> x1 + v105 Binop { op=or, lhs=v100, rhs=v104 } -> x0 + v106 Imm(0) -> x1 + v107 LoadLocal { off=-1, kind=I64 } -> x1 + v108 Imm(8) -> x1 + v109 Imm(0) -> x1 + v110 LoadLocal { off=-1, kind=I64 } -> x1 + v111 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v111) + block 2 start_pc=0 + v112 LoadLocal { off=-2, kind=I64 } -> x1 + terminator Return(v105) (exit_acc=v105) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=vol_keep +fn ent_pc=1 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I64 } -> x0 + v4 Imm(0) -> x0 + v5 Load { addr=v1, disp=0, kind=U8 } -> x0 + v6 StoreLocal { off=-1, value=v5, kind=I64, volatile } -> - + v7 LoadLocal { off=-1, kind=I64, volatile } -> x0 + v8 Imm(9) -> x0 + terminator Return(v8) (exit_acc=v8) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v3 LoadLocal { off=-2, kind=I64 } -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-1) -> x0 + v6 LoadLocal { off=-2, kind=I64 } -> x1 + v7 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v8 Imm(1) -> x1 + v9 Imm(1) -> x1 + v10 Store { addr=v7, disp=0, value=v9, kind=I8 } -> - + v11 LoadLocal { off=-2, kind=I64 } -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 LoadLocal { off=-2, kind=I64 } -> x0 + v15 Imm(1) -> x0 + v16 LocalAddr(-1) -> x0 + v17 LoadLocal { off=-2, kind=I64 } -> x1 + v18 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x1 + v19 Imm(2) -> x1 + v20 Imm(2) -> x1 + v21 Store { addr=v16, disp=1, value=v20, kind=I8 } -> - + v22 LoadLocal { off=-2, kind=I64 } -> x0 + v23 Imm(2) -> x0 + v24 Imm(0) -> x0 + v25 LoadLocal { off=-2, kind=I64 } -> x0 + v26 Imm(1) -> x0 + v27 LocalAddr(-1) -> x0 + v28 LoadLocal { off=-2, kind=I64 } -> x1 + v29 BinopI { op=add, lhs=v27, rhs_imm=2 } -> x1 + v30 Imm(3) -> x1 + v31 Imm(3) -> x1 + v32 Store { addr=v27, disp=2, value=v31, kind=I8 } -> - + v33 LoadLocal { off=-2, kind=I64 } -> x0 + v34 Imm(3) -> x0 + v35 Imm(0) -> x0 + v36 LoadLocal { off=-2, kind=I64 } -> x0 + v37 Imm(1) -> x0 + v38 LocalAddr(-1) -> x0 + v39 LoadLocal { off=-2, kind=I64 } -> x1 + v40 BinopI { op=add, lhs=v38, rhs_imm=3 } -> x1 + v41 Imm(4) -> x1 + v42 Imm(4) -> x1 + v43 Store { addr=v38, disp=3, value=v42, kind=I8 } -> - + v44 LoadLocal { off=-2, kind=I64 } -> x0 + v45 Imm(4) -> x0 + v46 Imm(0) -> x0 + v47 LoadLocal { off=-2, kind=I64 } -> x0 + v48 Imm(1) -> x0 + v49 LocalAddr(-1) -> x0 + v50 LoadLocal { off=-2, kind=I64 } -> x1 + v51 BinopI { op=add, lhs=v49, rhs_imm=4 } -> x1 + v52 Imm(5) -> x1 + v53 Imm(5) -> x1 + v54 Store { addr=v49, disp=4, value=v53, kind=I8 } -> - + v55 LoadLocal { off=-2, kind=I64 } -> x0 + v56 Imm(5) -> x0 + v57 Imm(0) -> x0 + v58 LoadLocal { off=-2, kind=I64 } -> x0 + v59 Imm(1) -> x0 + v60 LocalAddr(-1) -> x0 + v61 LoadLocal { off=-2, kind=I64 } -> x1 + v62 BinopI { op=add, lhs=v60, rhs_imm=5 } -> x1 + v63 Imm(6) -> x1 + v64 Imm(6) -> x1 + v65 Store { addr=v60, disp=5, value=v64, kind=I8 } -> - + v66 LoadLocal { off=-2, kind=I64 } -> x0 + v67 Imm(6) -> x0 + v68 Imm(0) -> x0 + v69 LoadLocal { off=-2, kind=I64 } -> x0 + v70 Imm(1) -> x0 + v71 LocalAddr(-1) -> x0 + v72 LoadLocal { off=-2, kind=I64 } -> x1 + v73 BinopI { op=add, lhs=v71, rhs_imm=6 } -> x1 + v74 Imm(7) -> x1 + v75 Imm(7) -> x1 + v76 Store { addr=v71, disp=6, value=v75, kind=I8 } -> - + v77 LoadLocal { off=-2, kind=I64 } -> x0 + v78 Imm(7) -> x0 + v79 Imm(0) -> x0 + v80 LoadLocal { off=-2, kind=I64 } -> x0 + v81 Imm(1) -> x0 + v82 LocalAddr(-1) -> x0 + v83 LoadLocal { off=-2, kind=I64 } -> x1 + v84 BinopI { op=add, lhs=v82, rhs_imm=7 } -> x1 + v85 Imm(8) -> x1 + v86 Imm(8) -> x1 + v87 Store { addr=v82, disp=7, value=v86, kind=I8 } -> - + v88 LoadLocal { off=-2, kind=I64 } -> x0 + v89 Imm(8) -> x0 + v90 Imm(0) -> x0 + v91 LoadLocal { off=-2, kind=I64 } -> x0 + v92 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v92) + block 2 start_pc=0 + v93 LocalAddr(-1) -> x7 + v94 Call { target_pc=0, args=[v93], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v95 BinopI { op=ne, lhs=v94, rhs_imm=72623859790382856 } -> x0 + terminator Bz { cond=v95, target=b4, fall=b3 } (exit_acc=v95) + block 3 start_pc=0 + v96 Imm(1) -> x0 + terminator Return(v96) (exit_acc=v96) + block 4 start_pc=0 + v97 LocalAddr(-1) -> x0 + v98 Imm(0) -> x1 + v99 Imm(0) -> x1 + v100 Load { addr=v97, disp=0, kind=U8 } -> x0 + v101 Imm(9) -> x0 + v102 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v102) + block 5 start_pc=0 + v104 Imm(0) -> x0 + terminator Return(v104) (exit_acc=v104) + block 6 start_pc=0 + v103 Imm(2) -> x0 + terminator Return(v103) (exit_acc=v103) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/decimal_literal_over_signed_max.ssa b/tests/snapshots/ssa/decimal_literal_over_signed_max.ssa index 8f3394bf7..aba2e5ebc 100644 --- a/tests/snapshots/ssa/decimal_literal_over_signed_max.ssa +++ b/tests/snapshots/ssa/decimal_literal_over_signed_max.ssa @@ -6,40 +6,40 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 v2 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v2) + terminator Jmp(b1) (exit_acc=v2) block 1 start_pc=0 - v3 Imm(1) -> x0 - terminator Return(v3) (exit_acc=v3) - block 2 start_pc=0 v4 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v4) - block 3 start_pc=0 - v5 Imm(2) -> x0 - terminator Return(v5) (exit_acc=v5) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v4) + block 2 start_pc=0 v6 Imm(1) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v7) - block 5 start_pc=0 - v8 Imm(3) -> x0 - terminator Return(v8) (exit_acc=v8) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 v9 Imm(1) -> x0 v10 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v10) - block 7 start_pc=0 - v11 Imm(4) -> x0 - terminator Return(v11) (exit_acc=v11) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v10) + block 4 start_pc=0 v12 Imm(1) -> x0 v13 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v13) + terminator Jmp(b5) (exit_acc=v13) + block 5 start_pc=0 + v15 Imm(0) -> x0 + terminator Return(v15) (exit_acc=v15) + block 6 start_pc=0 + v3 Imm(1) -> x0 + terminator Return(v3) (exit_acc=v3) + block 7 start_pc=0 + v5 Imm(2) -> x0 + terminator Return(v5) (exit_acc=v5) + block 8 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) block 9 start_pc=0 + v11 Imm(4) -> x0 + terminator Return(v11) (exit_acc=v11) + block 10 start_pc=0 v14 Imm(5) -> x0 terminator Return(v14) (exit_acc=v14) - block 10 start_pc=0 - v15 Imm(0) -> x0 - terminator Return(v15) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/decl_specifier_any_order.ssa b/tests/snapshots/ssa/decl_specifier_any_order.ssa index b296295ce..e02692043 100644 --- a/tests/snapshots/ssa/decl_specifier_any_order.ssa +++ b/tests/snapshots/ssa/decl_specifier_any_order.ssa @@ -6,64 +6,43 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(4294967296) -> x0 - v6 Imm(0) -> x1 - v7 LoadLocal { off=-1, kind=I64 } -> x1 - v8 BinopI { op=shr, lhs=v5, rhs_imm=32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=1 } -> x0 - terminator Bz { cond=v9, target=b6, fall=b5 } (exit_acc=v9) - block 5 start_pc=0 - v10 Imm(3) -> x0 - terminator Return(v10) (exit_acc=v10) - block 6 start_pc=0 + v6 Imm(0) -> x0 + v7 LoadLocal { off=-1, kind=I64 } -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v9) + block 3 start_pc=0 v11 Imm(-1) -> x0 - v12 Imm(0) -> x1 - v13 BinopI { op=and, lhs=v11, rhs_imm=4294967295 } -> x0 - v14 BinopI { op=ugt, lhs=v13, rhs_imm=0 } -> x0 - v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) - block 7 start_pc=0 - v16 Imm(4) -> x0 - terminator Return(v16) (exit_acc=v16) - block 8 start_pc=0 + v12 Imm(0) -> x0 + v13 Imm(4294967295) -> x0 + v14 Imm(1) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v15) + block 4 start_pc=0 v17 Imm(-1) -> x0 - v18 Imm(0) -> x1 - v19 BinopI { op=and, lhs=v17, rhs_imm=255 } -> x0 - v20 BinopI { op=xor, lhs=v19, rhs_imm=255 } -> x0 - v21 BinopI { op=and, lhs=v20, rhs_imm=4294967295 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=0 } -> x0 - terminator Bz { cond=v22, target=b10, fall=b9 } (exit_acc=v22) - block 9 start_pc=0 - v23 Imm(5) -> x0 - terminator Return(v23) (exit_acc=v23) - block 10 start_pc=0 + v18 Imm(0) -> x0 + v19 Imm(255) -> x0 + v20 Imm(0) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 v24 Imm(-1) -> x0 v25 Imm(0) -> x0 v26 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v26) - block 11 start_pc=0 - v27 Imm(6) -> x0 - terminator Return(v27) (exit_acc=v27) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v26) + block 6 start_pc=0 v28 Imm(16) -> x0 v29 Imm(68719476736) -> x0 v30 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v30) - block 13 start_pc=0 - v31 Imm(7) -> x0 - terminator Return(v31) (exit_acc=v31) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v30) + block 7 start_pc=0 v32 LocalAddr(-6) -> x0 v33 BinopI { op=add, lhs=v32, rhs_imm=8 } -> x1 v34 Imm(-5) -> x1 @@ -72,13 +51,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v37 BinopI { op=add, lhs=v36, rhs_imm=8 } -> x1 v38 Load { addr=v36, disp=8, kind=I64 } -> x0 v39 BinopI { op=ge, lhs=v38, rhs_imm=0 } -> x0 - terminator Bz { cond=v39, target=b16, fall=b15 } (exit_acc=v39) - block 15 start_pc=0 + terminator Bz { cond=v39, target=b9, fall=b8 } (exit_acc=v39) + block 8 start_pc=0 v40 Imm(8) -> x0 terminator Return(v40) (exit_acc=v40) - block 16 start_pc=0 + block 9 start_pc=0 v41 Imm(0) -> x0 terminator Return(v41) (exit_acc=v41) + block 10 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 11 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 12 start_pc=0 + v10 Imm(3) -> x0 + terminator Return(v10) (exit_acc=v10) + block 13 start_pc=0 + v16 Imm(4) -> x0 + terminator Return(v16) (exit_acc=v16) + block 14 start_pc=0 + v23 Imm(5) -> x0 + terminator Return(v23) (exit_acc=v23) + block 15 start_pc=0 + v27 Imm(6) -> x0 + terminator Return(v27) (exit_acc=v27) + block 16 start_pc=0 + v31 Imm(7) -> x0 + terminator Return(v31) (exit_acc=v31) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/deferred_outer_2d_array_stride.ssa b/tests/snapshots/ssa/deferred_outer_2d_array_stride.ssa index 2eeb4c396..84405ae98 100644 --- a/tests/snapshots/ssa/deferred_outer_2d_array_stride.ssa +++ b/tests/snapshots/ssa/deferred_outer_2d_array_stride.ssa @@ -6,36 +6,27 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v0 AllocaInit(0) -> - v1 Imm(48) -> x0 v2 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v2) + terminator Jmp(b1) (exit_acc=v2) block 1 start_pc=0 - v3 Imm(1) -> x0 - terminator Return(v3) (exit_acc=v3) - block 2 start_pc=0 v4 Imm(16) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v5) - block 3 start_pc=0 - v6 Imm(2) -> x0 - terminator Return(v6) (exit_acc=v6) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v5) + block 2 start_pc=0 v7 Imm(16) -> x0 v8 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v8) - block 5 start_pc=0 - v9 Imm(3) -> x0 - terminator Return(v9) (exit_acc=v9) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v8) + block 3 start_pc=0 v10 ImmData(64) -> x0 v11 Imm(16) -> x1 v12 BinopI { op=add, lhs=v10, rhs_imm=16 } -> x1 v13 Imm(0) -> x2 v14 Binop { op=sub, lhs=v12, rhs=v10 } -> x0 v15 BinopI { op=ne, lhs=v14, rhs_imm=16 } -> x0 - terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) - block 7 start_pc=0 + terminator Bz { cond=v15, target=b5, fall=b4 } (exit_acc=v15) + block 4 start_pc=0 v16 Imm(4) -> x0 terminator Return(v16) (exit_acc=v16) - block 8 start_pc=0 + block 5 start_pc=0 v17 ImmData(64) -> x0 v18 Imm(32) -> x1 v19 BinopI { op=add, lhs=v17, rhs_imm=32 } -> x1 @@ -43,19 +34,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v21 BinopI { op=add, lhs=v17, rhs_imm=16 } -> x0 v22 Binop { op=sub, lhs=v19, rhs=v21 } -> x0 v23 BinopI { op=ne, lhs=v22, rhs_imm=16 } -> x0 - terminator Bz { cond=v23, target=b10, fall=b9 } (exit_acc=v23) - block 9 start_pc=0 + terminator Bz { cond=v23, target=b7, fall=b6 } (exit_acc=v23) + block 6 start_pc=0 v24 Imm(5) -> x0 terminator Return(v24) (exit_acc=v24) - block 10 start_pc=0 + block 7 start_pc=0 v25 ImmData(64) -> x0 v26 Imm(0) -> x1 v27 Load { addr=v25, disp=0, kind=I64 } -> x0 v28 Load { addr=v27, disp=0, kind=I8 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=65 } -> x1 v30 Imm(0) -> x0 - terminator Bnz { cond=v29, target=b31, fall=b11 } (exit_acc=v29) - block 11 start_pc=0 + terminator Bnz { cond=v29, target=b28, fall=b8 } (exit_acc=v29) + block 8 start_pc=0 v31 ImmData(64) -> x0 v32 Imm(0) -> x1 v33 Imm(8) -> x1 @@ -64,15 +55,15 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v36 Load { addr=v35, disp=0, kind=I8 } -> x0 v37 BinopI { op=ne, lhs=v36, rhs_imm=66 } -> x1 v38 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v37) - block 12 start_pc=0 - v39 Phi { incoming=[b31:v29, b11:v37], kind=I64 } -> x1 + terminator Jmp(b9) (exit_acc=v37) + block 9 start_pc=0 + v39 Phi { incoming=[b28:v29, b8:v37], kind=I64 } -> x1 v40 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v39, target=b14, fall=b13 } (exit_acc=v39) - block 13 start_pc=0 + terminator Bz { cond=v39, target=b11, fall=b10 } (exit_acc=v39) + block 10 start_pc=0 v41 Imm(6) -> x0 terminator Return(v41) (exit_acc=v41) - block 14 start_pc=0 + block 11 start_pc=0 v42 ImmData(64) -> x0 v43 Imm(16) -> x1 v44 BinopI { op=add, lhs=v42, rhs_imm=16 } -> x1 @@ -81,8 +72,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v47 Load { addr=v46, disp=0, kind=I8 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=67 } -> x1 v49 Imm(0) -> x0 - terminator Bnz { cond=v48, target=b32, fall=b15 } (exit_acc=v48) - block 15 start_pc=0 + terminator Bnz { cond=v48, target=b27, fall=b12 } (exit_acc=v48) + block 12 start_pc=0 v50 ImmData(64) -> x0 v51 Imm(16) -> x1 v52 BinopI { op=add, lhs=v50, rhs_imm=16 } -> x1 @@ -91,15 +82,15 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v55 Load { addr=v50, disp=24, kind=I64 } -> x0 v56 BinopI { op=ne, lhs=v55, rhs_imm=0 } -> x1 v57 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v56) - block 16 start_pc=0 - v58 Phi { incoming=[b32:v48, b15:v56], kind=I64 } -> x1 + terminator Jmp(b13) (exit_acc=v56) + block 13 start_pc=0 + v58 Phi { incoming=[b27:v48, b12:v56], kind=I64 } -> x1 v59 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v58, target=b18, fall=b17 } (exit_acc=v58) - block 17 start_pc=0 + terminator Bz { cond=v58, target=b15, fall=b14 } (exit_acc=v58) + block 14 start_pc=0 v60 Imm(7) -> x0 terminator Return(v60) (exit_acc=v60) - block 18 start_pc=0 + block 15 start_pc=0 v61 ImmData(64) -> x0 v62 Imm(32) -> x1 v63 BinopI { op=add, lhs=v61, rhs_imm=32 } -> x1 @@ -107,8 +98,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v65 Load { addr=v61, disp=32, kind=I64 } -> x0 v66 BinopI { op=ne, lhs=v65, rhs_imm=0 } -> x1 v67 Imm(0) -> x0 - terminator Bnz { cond=v66, target=b33, fall=b19 } (exit_acc=v66) - block 19 start_pc=0 + terminator Bnz { cond=v66, target=b26, fall=b16 } (exit_acc=v66) + block 16 start_pc=0 v68 ImmData(64) -> x0 v69 Imm(32) -> x1 v70 BinopI { op=add, lhs=v68, rhs_imm=32 } -> x1 @@ -119,29 +110,23 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v75 Load { addr=v73, disp=0, kind=I8 } -> x0 v76 BinopI { op=ne, lhs=v75, rhs_imm=68 } -> x1 v77 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v76) - block 20 start_pc=0 - v78 Phi { incoming=[b33:v66, b19:v76], kind=I64 } -> x1 + terminator Jmp(b17) (exit_acc=v76) + block 17 start_pc=0 + v78 Phi { incoming=[b26:v66, b16:v76], kind=I64 } -> x1 v79 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v78, target=b22, fall=b21 } (exit_acc=v78) - block 21 start_pc=0 + terminator Bz { cond=v78, target=b19, fall=b18 } (exit_acc=v78) + block 18 start_pc=0 v80 Imm(8) -> x0 terminator Return(v80) (exit_acc=v80) - block 22 start_pc=0 + block 19 start_pc=0 v81 Imm(48) -> x0 v82 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v82) - block 23 start_pc=0 - v83 Imm(9) -> x0 - terminator Return(v83) (exit_acc=v83) - block 24 start_pc=0 + terminator Jmp(b20) (exit_acc=v82) + block 20 start_pc=0 v84 Imm(12) -> x0 v85 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v85) - block 25 start_pc=0 - v86 Imm(10) -> x0 - terminator Return(v86) (exit_acc=v86) - block 26 start_pc=0 + terminator Jmp(b21) (exit_acc=v85) + block 21 start_pc=0 v87 ImmData(112) -> x0 v88 Imm(36) -> x1 v89 BinopI { op=add, lhs=v87, rhs_imm=36 } -> x1 @@ -149,11 +134,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v91 BinopI { op=add, lhs=v87, rhs_imm=44 } -> x1 v92 Load { addr=v87, disp=44, kind=I32 } -> x0 v93 BinopI { op=ne, lhs=v92, rhs_imm=12 } -> x0 - terminator Bz { cond=v93, target=b28, fall=b27 } (exit_acc=v93) - block 27 start_pc=0 + terminator Bz { cond=v93, target=b23, fall=b22 } (exit_acc=v93) + block 22 start_pc=0 v94 Imm(11) -> x0 terminator Return(v94) (exit_acc=v94) - block 28 start_pc=0 + block 23 start_pc=0 v95 ImmData(112) -> x0 v96 Imm(12) -> x1 v97 BinopI { op=add, lhs=v95, rhs_imm=12 } -> x1 @@ -161,19 +146,34 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v99 BinopI { op=add, lhs=v95, rhs_imm=16 } -> x1 v100 Load { addr=v95, disp=16, kind=I32 } -> x0 v101 BinopI { op=ne, lhs=v100, rhs_imm=5 } -> x0 - terminator Bz { cond=v101, target=b30, fall=b29 } (exit_acc=v101) - block 29 start_pc=0 + terminator Bz { cond=v101, target=b25, fall=b24 } (exit_acc=v101) + block 24 start_pc=0 v102 Imm(12) -> x0 terminator Return(v102) (exit_acc=v102) - block 30 start_pc=0 + block 25 start_pc=0 v103 Imm(0) -> x0 terminator Return(v103) (exit_acc=v103) + block 26 start_pc=0 + terminator Jmp(b17) + block 27 start_pc=0 + terminator Jmp(b13) + block 28 start_pc=0 + terminator Jmp(b9) + block 29 start_pc=0 + v3 Imm(1) -> x0 + terminator Return(v3) (exit_acc=v3) + block 30 start_pc=0 + v6 Imm(2) -> x0 + terminator Return(v6) (exit_acc=v6) block 31 start_pc=0 - terminator Jmp(b12) + v9 Imm(3) -> x0 + terminator Return(v9) (exit_acc=v9) block 32 start_pc=0 - terminator Jmp(b16) + v83 Imm(9) -> x0 + terminator Return(v83) (exit_acc=v83) block 33 start_pc=0 - terminator Jmp(b20) + v86 Imm(10) -> x0 + terminator Return(v86) (exit_acc=v86) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/des_ct_fconf_wide_imm_scratch.ssa b/tests/snapshots/ssa/des_ct_fconf_wide_imm_scratch.ssa index 5734d41d8..03f29cb70 100644 --- a/tests/snapshots/ssa/des_ct_fconf_wide_imm_scratch.ssa +++ b/tests/snapshots/ssa/des_ct_fconf_wide_imm_scratch.ssa @@ -22,7 +22,7 @@ fn ent_pc=0 n_params=2 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=Fconf fn ent_pc=1 n_params=2 variadic=false locals=40 - spill_count=25 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + spill_count=24 gpr_used=[3, 12, 13, 14, 15] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -102,20 +102,20 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v75 BinopI { op=and, lhs=v73, rhs_imm=4294967295 } -> x2 v76 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x7 v77 Imm(12) -> x3 - v78 BinopI { op=add, lhs=v3, rhs_imm=12 } -> x12 - v79 Load { addr=v3, disp=12, kind=U32 } -> x12 + v78 BinopI { op=add, lhs=v3, rhs_imm=12 } -> x3 + v79 Load { addr=v3, disp=12, kind=U32 } -> x3 v80 Binop { op=xor, lhs=v76, rhs=v79 } -> x7 - v81 Imm(0) -> x12 + v81 Imm(0) -> x3 v82 BinopI { op=and, lhs=v80, rhs_imm=4294967295 } -> x7 - v83 Imm(16) -> x12 - v84 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x12 - v85 Load { addr=v3, disp=16, kind=U32 } -> x12 + v83 Imm(16) -> x3 + v84 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x3 + v85 Load { addr=v3, disp=16, kind=U32 } -> x3 v86 Binop { op=xor, lhs=v42, rhs=v85 } -> x0 - v87 Imm(0) -> x12 + v87 Imm(0) -> x3 v88 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x0 v89 BinopI { op=and, lhs=v53, rhs_imm=4294967295 } -> x9 - v90 Imm(20) -> x12 - v91 BinopI { op=add, lhs=v3, rhs_imm=20 } -> x12 + v90 Imm(20) -> x3 + v91 BinopI { op=add, lhs=v3, rhs_imm=20 } -> x3 v92 Load { addr=v3, disp=20, kind=U32 } -> x6 v93 Binop { op=xor, lhs=v89, rhs=v92 } -> x6 v94 Imm(0) -> x9 @@ -124,312 +124,312 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v97 Imm(3967469212) -> x9 v98 BinopI { op=and, lhs=v62, rhs_imm=3967469212 } -> x9 v99 BinopI { op=xor, lhs=v98, rhs_imm=4020710477 } -> x9 - v100 Imm(0) -> x12 - v101 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x12 - v102 Imm(2930437631) -> x12 - v103 Imm(1343207457) -> x12 - v104 BinopI { op=and, lhs=v62, rhs_imm=1343207457 } -> x12 - v105 BinopI { op=xor, lhs=v104, rhs_imm=2930437631 } -> x12 - v106 Imm(0) -> x13 - v107 BinopI { op=and, lhs=v105, rhs_imm=4294967295 } -> x13 - v108 Imm(926508645) -> x13 - v109 Imm(1089447945) -> x13 - v110 BinopI { op=and, lhs=v62, rhs_imm=1089447945 } -> x13 - v111 BinopI { op=xor, lhs=v110, rhs_imm=926508645 } -> x13 - v112 Imm(0) -> x14 - v113 BinopI { op=and, lhs=v111, rhs_imm=4294967295 } -> x14 - v114 Imm(1758967859) -> x14 - v115 Imm(2783709992) -> x14 - v116 BinopI { op=and, lhs=v62, rhs_imm=2783709992 } -> x14 - v117 BinopI { op=xor, lhs=v116, rhs_imm=1758967859 } -> x14 - v118 Imm(0) -> x15 - v119 BinopI { op=and, lhs=v117, rhs_imm=4294967295 } -> x15 - v120 Imm(3385284027) -> x15 - v121 Imm(623704096) -> x15 - v122 BinopI { op=and, lhs=v62, rhs_imm=623704096 } -> x15 - v123 BinopI { op=xor, lhs=v122, rhs_imm=3385284027 } -> x15 - v124 Imm(0) -> [spill 0] - v125 BinopI { op=and, lhs=v123, rhs_imm=4294967295 } -> [spill 0] - v126 Imm(1945908742) -> [spill 0] - v127 Imm(1075861505) -> [spill 0] - v128 BinopI { op=and, lhs=v62, rhs_imm=1075861505 } -> [spill 0] - v129 BinopI { op=xor, lhs=v128, rhs_imm=1945908742 } -> [spill 0] - v130 Imm(0) -> [spill 1] - v131 BinopI { op=and, lhs=v129, rhs_imm=4294967295 } -> [spill 1] - v132 Imm(2728438040) -> [spill 1] - v133 Imm(3793811753) -> [spill 1] - v134 BinopI { op=and, lhs=v62, rhs_imm=3793811753 } -> [spill 1] - v135 BinopI { op=xor, lhs=v134, rhs_imm=2728438040 } -> [spill 1] - v136 Imm(0) -> [spill 2] - v137 BinopI { op=and, lhs=v135, rhs_imm=4294967295 } -> [spill 2] - v138 Imm(2183314832) -> [spill 2] - v139 Imm(1151597025) -> [spill 2] - v140 BinopI { op=and, lhs=v62, rhs_imm=1151597025 } -> [spill 2] - v141 BinopI { op=xor, lhs=v140, rhs_imm=2183314832 } -> [spill 2] - v142 Imm(0) -> [spill 3] - v143 BinopI { op=and, lhs=v141, rhs_imm=4294967295 } -> [spill 3] - v144 Imm(3602295927) -> [spill 3] - v145 Imm(2035224650) -> [spill 3] - v146 BinopI { op=and, lhs=v62, rhs_imm=2035224650 } -> [spill 3] - v147 BinopI { op=xor, lhs=v146, rhs_imm=3602295927 } -> [spill 3] - v148 Imm(0) -> [spill 4] - v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> [spill 4] - v150 Imm(812199948) -> [spill 4] - v151 Imm(40841739) -> [spill 4] - v152 BinopI { op=and, lhs=v62, rhs_imm=40841739 } -> [spill 4] - v153 BinopI { op=xor, lhs=v152, rhs_imm=812199948 } -> [spill 4] - v154 Imm(0) -> [spill 5] - v155 BinopI { op=and, lhs=v153, rhs_imm=4294967295 } -> [spill 5] - v156 Imm(1826674124) -> [spill 5] - v157 Imm(1983950874) -> [spill 5] - v158 BinopI { op=and, lhs=v62, rhs_imm=1983950874 } -> [spill 5] - v159 BinopI { op=xor, lhs=v158, rhs_imm=1826674124 } -> [spill 5] - v160 Imm(0) -> [spill 6] - v161 BinopI { op=and, lhs=v159, rhs_imm=4294967295 } -> [spill 6] - v162 Imm(1504289325) -> [spill 6] - v163 Imm(596579698) -> [spill 6] - v164 BinopI { op=and, lhs=v62, rhs_imm=596579698 } -> [spill 6] - v165 BinopI { op=xor, lhs=v164, rhs_imm=1504289325 } -> [spill 6] - v166 Imm(0) -> [spill 7] - v167 BinopI { op=and, lhs=v165, rhs_imm=4294967295 } -> [spill 7] - v168 Imm(2892827604) -> [spill 7] - v169 Imm(2053357699) -> [spill 7] - v170 BinopI { op=and, lhs=v62, rhs_imm=2053357699 } -> [spill 7] - v171 BinopI { op=xor, lhs=v170, rhs_imm=2892827604 } -> [spill 7] - v172 Imm(0) -> [spill 8] - v173 BinopI { op=and, lhs=v171, rhs_imm=4294967295 } -> [spill 8] - v174 Imm(566768128) -> [spill 8] - v175 Imm(298622976) -> [spill 8] - v176 BinopI { op=and, lhs=v62, rhs_imm=298622976 } -> [spill 8] - v177 BinopI { op=xor, lhs=v176, rhs_imm=566768128 } -> [spill 8] - v178 Imm(0) -> [spill 9] - v179 BinopI { op=and, lhs=v177, rhs_imm=4294967295 } -> [spill 9] - v180 Imm(2699436424) -> [spill 9] - v181 Imm(539978154) -> [spill 9] - v182 BinopI { op=and, lhs=v62, rhs_imm=539978154 } -> [spill 9] - v183 BinopI { op=xor, lhs=v182, rhs_imm=2699436424 } -> [spill 9] - v184 Imm(0) -> [spill 10] - v185 BinopI { op=and, lhs=v183, rhs_imm=4294967295 } -> [spill 10] - v186 Imm(2944230746) -> [spill 10] - v187 Imm(1370700777) -> [spill 10] - v188 BinopI { op=and, lhs=v62, rhs_imm=1370700777 } -> [spill 10] - v189 BinopI { op=xor, lhs=v188, rhs_imm=2944230746 } -> [spill 10] - v190 Imm(0) -> [spill 11] - v191 BinopI { op=and, lhs=v189, rhs_imm=4294967295 } -> [spill 11] - v192 Imm(4028009123) -> [spill 11] - v193 Imm(990898350) -> [spill 11] - v194 BinopI { op=and, lhs=v62, rhs_imm=990898350 } -> [spill 11] - v195 BinopI { op=xor, lhs=v194, rhs_imm=4028009123 } -> [spill 11] - v196 Imm(0) -> [spill 12] - v197 BinopI { op=and, lhs=v195, rhs_imm=4294967295 } -> [spill 12] - v198 Imm(2427072710) -> [spill 12] - v199 Imm(2428471318) -> [spill 12] - v200 BinopI { op=and, lhs=v62, rhs_imm=2428471318 } -> [spill 12] - v201 BinopI { op=xor, lhs=v200, rhs_imm=2427072710 } -> [spill 12] - v202 Imm(0) -> [spill 13] - v203 BinopI { op=and, lhs=v201, rhs_imm=4294967295 } -> [spill 13] - v204 Imm(1521644810) -> [spill 13] - v205 Imm(165891995) -> [spill 13] - v206 BinopI { op=and, lhs=v62, rhs_imm=165891995 } -> [spill 13] - v207 BinopI { op=xor, lhs=v206, rhs_imm=1521644810 } -> [spill 13] - v208 Imm(0) -> [spill 14] - v209 BinopI { op=and, lhs=v207, rhs_imm=4294967295 } -> [spill 14] - v210 Imm(1402060389) -> [spill 14] - v211 Imm(17022600) -> [spill 14] - v212 BinopI { op=and, lhs=v62, rhs_imm=17022600 } -> [spill 14] - v213 BinopI { op=xor, lhs=v212, rhs_imm=1402060389 } -> [spill 14] - v214 Imm(0) -> [spill 15] - v215 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> [spill 15] - v216 Imm(2469866415) -> [spill 15] - v217 Imm(1236045349) -> [spill 15] - v218 BinopI { op=and, lhs=v62, rhs_imm=1236045349 } -> [spill 15] - v219 BinopI { op=xor, lhs=v218, rhs_imm=2469866415 } -> [spill 15] - v220 Imm(0) -> [spill 16] - v221 BinopI { op=and, lhs=v219, rhs_imm=4294967295 } -> [spill 16] - v222 Imm(4069007628) -> [spill 16] - v223 Imm(2452369725) -> [spill 16] - v224 BinopI { op=and, lhs=v62, rhs_imm=2452369725 } -> [spill 16] - v225 BinopI { op=xor, lhs=v224, rhs_imm=4069007628 } -> [spill 16] - v226 Imm(0) -> [spill 17] - v227 BinopI { op=and, lhs=v225, rhs_imm=4294967295 } -> [spill 17] - v228 Imm(2450191808) -> [spill 17] - v229 Imm(1894724016) -> [spill 17] - v230 BinopI { op=and, lhs=v62, rhs_imm=1894724016 } -> [spill 17] - v231 BinopI { op=xor, lhs=v230, rhs_imm=2450191808 } -> [spill 17] - v232 Imm(0) -> [spill 18] - v233 BinopI { op=and, lhs=v231, rhs_imm=4294967295 } -> [spill 18] - v234 Imm(1674777280) -> [spill 18] - v235 Imm(1785753856) -> [spill 18] - v236 BinopI { op=and, lhs=v62, rhs_imm=1785753856 } -> [spill 18] - v237 BinopI { op=xor, lhs=v236, rhs_imm=1674777280 } -> [spill 18] - v238 Imm(0) -> [spill 19] - v239 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> [spill 19] - v240 Imm(1400582150) -> [spill 19] - v241 Imm(3111948305) -> [spill 19] - v242 BinopI { op=and, lhs=v62, rhs_imm=3111948305 } -> [spill 19] - v243 BinopI { op=xor, lhs=v242, rhs_imm=1400582150 } -> [spill 19] - v244 Imm(0) -> [spill 20] - v245 BinopI { op=and, lhs=v243, rhs_imm=4294967295 } -> [spill 20] - v246 Imm(2733617317) -> [spill 20] - v247 Imm(2736834905) -> [spill 20] - v248 BinopI { op=and, lhs=v62, rhs_imm=2736834905 } -> [spill 20] - v249 BinopI { op=xor, lhs=v248, rhs_imm=2733617317 } -> [spill 20] - v250 Imm(0) -> [spill 21] - v251 BinopI { op=and, lhs=v249, rhs_imm=4294967295 } -> [spill 21] - v252 Imm(3163526821) -> [spill 21] - v253 Imm(1856023370) -> [spill 21] - v254 BinopI { op=and, lhs=v62, rhs_imm=1856023370 } -> [spill 21] - v255 BinopI { op=xor, lhs=v254, rhs_imm=3163526821 } -> [spill 21] - v256 Imm(0) -> [spill 22] - v257 BinopI { op=and, lhs=v255, rhs_imm=4294967295 } -> [spill 22] - v258 Imm(4208031397) -> [spill 22] - v259 Imm(1767103992) -> [spill 22] - v260 BinopI { op=and, lhs=v62, rhs_imm=1767103992 } -> [spill 22] - v261 BinopI { op=xor, lhs=v260, rhs_imm=4208031397 } -> [spill 22] - v262 Imm(0) -> [spill 23] - v263 BinopI { op=and, lhs=v261, rhs_imm=4294967295 } -> [spill 23] - v264 Imm(1717179555) -> [spill 23] - v265 Imm(4149165611) -> [spill 23] - v266 BinopI { op=and, lhs=v62, rhs_imm=4149165611 } -> [spill 23] - v267 BinopI { op=xor, lhs=v266, rhs_imm=1717179555 } -> [spill 23] - v268 Imm(0) -> [spill 24] - v269 BinopI { op=and, lhs=v267, rhs_imm=4294967295 } -> [spill 24] - v270 Imm(4075811020) -> [spill 24] - v271 Imm(4029705389) -> [spill 24] + v100 Imm(0) -> x3 + v101 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x3 + v102 Imm(2930437631) -> x3 + v103 Imm(1343207457) -> x3 + v104 BinopI { op=and, lhs=v62, rhs_imm=1343207457 } -> x3 + v105 BinopI { op=xor, lhs=v104, rhs_imm=2930437631 } -> x3 + v106 Imm(0) -> x12 + v107 BinopI { op=and, lhs=v105, rhs_imm=4294967295 } -> x12 + v108 Imm(926508645) -> x12 + v109 Imm(1089447945) -> x12 + v110 BinopI { op=and, lhs=v62, rhs_imm=1089447945 } -> x12 + v111 BinopI { op=xor, lhs=v110, rhs_imm=926508645 } -> x12 + v112 Imm(0) -> x13 + v113 BinopI { op=and, lhs=v111, rhs_imm=4294967295 } -> x13 + v114 Imm(1758967859) -> x13 + v115 Imm(2783709992) -> x13 + v116 BinopI { op=and, lhs=v62, rhs_imm=2783709992 } -> x13 + v117 BinopI { op=xor, lhs=v116, rhs_imm=1758967859 } -> x13 + v118 Imm(0) -> x14 + v119 BinopI { op=and, lhs=v117, rhs_imm=4294967295 } -> x14 + v120 Imm(3385284027) -> x14 + v121 Imm(623704096) -> x14 + v122 BinopI { op=and, lhs=v62, rhs_imm=623704096 } -> x14 + v123 BinopI { op=xor, lhs=v122, rhs_imm=3385284027 } -> x14 + v124 Imm(0) -> x15 + v125 BinopI { op=and, lhs=v123, rhs_imm=4294967295 } -> x15 + v126 Imm(1945908742) -> x15 + v127 Imm(1075861505) -> x15 + v128 BinopI { op=and, lhs=v62, rhs_imm=1075861505 } -> x15 + v129 BinopI { op=xor, lhs=v128, rhs_imm=1945908742 } -> x15 + v130 Imm(0) -> [spill 0] + v131 BinopI { op=and, lhs=v129, rhs_imm=4294967295 } -> [spill 0] + v132 Imm(2728438040) -> [spill 0] + v133 Imm(3793811753) -> [spill 0] + v134 BinopI { op=and, lhs=v62, rhs_imm=3793811753 } -> [spill 0] + v135 BinopI { op=xor, lhs=v134, rhs_imm=2728438040 } -> [spill 0] + v136 Imm(0) -> [spill 1] + v137 BinopI { op=and, lhs=v135, rhs_imm=4294967295 } -> [spill 1] + v138 Imm(2183314832) -> [spill 1] + v139 Imm(1151597025) -> [spill 1] + v140 BinopI { op=and, lhs=v62, rhs_imm=1151597025 } -> [spill 1] + v141 BinopI { op=xor, lhs=v140, rhs_imm=2183314832 } -> [spill 1] + v142 Imm(0) -> [spill 2] + v143 BinopI { op=and, lhs=v141, rhs_imm=4294967295 } -> [spill 2] + v144 Imm(3602295927) -> [spill 2] + v145 Imm(2035224650) -> [spill 2] + v146 BinopI { op=and, lhs=v62, rhs_imm=2035224650 } -> [spill 2] + v147 BinopI { op=xor, lhs=v146, rhs_imm=3602295927 } -> [spill 2] + v148 Imm(0) -> [spill 3] + v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> [spill 3] + v150 Imm(812199948) -> [spill 3] + v151 Imm(40841739) -> [spill 3] + v152 BinopI { op=and, lhs=v62, rhs_imm=40841739 } -> [spill 3] + v153 BinopI { op=xor, lhs=v152, rhs_imm=812199948 } -> [spill 3] + v154 Imm(0) -> [spill 4] + v155 BinopI { op=and, lhs=v153, rhs_imm=4294967295 } -> [spill 4] + v156 Imm(1826674124) -> [spill 4] + v157 Imm(1983950874) -> [spill 4] + v158 BinopI { op=and, lhs=v62, rhs_imm=1983950874 } -> [spill 4] + v159 BinopI { op=xor, lhs=v158, rhs_imm=1826674124 } -> [spill 4] + v160 Imm(0) -> [spill 5] + v161 BinopI { op=and, lhs=v159, rhs_imm=4294967295 } -> [spill 5] + v162 Imm(1504289325) -> [spill 5] + v163 Imm(596579698) -> [spill 5] + v164 BinopI { op=and, lhs=v62, rhs_imm=596579698 } -> [spill 5] + v165 BinopI { op=xor, lhs=v164, rhs_imm=1504289325 } -> [spill 5] + v166 Imm(0) -> [spill 6] + v167 BinopI { op=and, lhs=v165, rhs_imm=4294967295 } -> [spill 6] + v168 Imm(2892827604) -> [spill 6] + v169 Imm(2053357699) -> [spill 6] + v170 BinopI { op=and, lhs=v62, rhs_imm=2053357699 } -> [spill 6] + v171 BinopI { op=xor, lhs=v170, rhs_imm=2892827604 } -> [spill 6] + v172 Imm(0) -> [spill 7] + v173 BinopI { op=and, lhs=v171, rhs_imm=4294967295 } -> [spill 7] + v174 Imm(566768128) -> [spill 7] + v175 Imm(298622976) -> [spill 7] + v176 BinopI { op=and, lhs=v62, rhs_imm=298622976 } -> [spill 7] + v177 BinopI { op=xor, lhs=v176, rhs_imm=566768128 } -> [spill 7] + v178 Imm(0) -> [spill 8] + v179 BinopI { op=and, lhs=v177, rhs_imm=4294967295 } -> [spill 8] + v180 Imm(2699436424) -> [spill 8] + v181 Imm(539978154) -> [spill 8] + v182 BinopI { op=and, lhs=v62, rhs_imm=539978154 } -> [spill 8] + v183 BinopI { op=xor, lhs=v182, rhs_imm=2699436424 } -> [spill 8] + v184 Imm(0) -> [spill 9] + v185 BinopI { op=and, lhs=v183, rhs_imm=4294967295 } -> [spill 9] + v186 Imm(2944230746) -> [spill 9] + v187 Imm(1370700777) -> [spill 9] + v188 BinopI { op=and, lhs=v62, rhs_imm=1370700777 } -> [spill 9] + v189 BinopI { op=xor, lhs=v188, rhs_imm=2944230746 } -> [spill 9] + v190 Imm(0) -> [spill 10] + v191 BinopI { op=and, lhs=v189, rhs_imm=4294967295 } -> [spill 10] + v192 Imm(4028009123) -> [spill 10] + v193 Imm(990898350) -> [spill 10] + v194 BinopI { op=and, lhs=v62, rhs_imm=990898350 } -> [spill 10] + v195 BinopI { op=xor, lhs=v194, rhs_imm=4028009123 } -> [spill 10] + v196 Imm(0) -> [spill 11] + v197 BinopI { op=and, lhs=v195, rhs_imm=4294967295 } -> [spill 11] + v198 Imm(2427072710) -> [spill 11] + v199 Imm(2428471318) -> [spill 11] + v200 BinopI { op=and, lhs=v62, rhs_imm=2428471318 } -> [spill 11] + v201 BinopI { op=xor, lhs=v200, rhs_imm=2427072710 } -> [spill 11] + v202 Imm(0) -> [spill 12] + v203 BinopI { op=and, lhs=v201, rhs_imm=4294967295 } -> [spill 12] + v204 Imm(1521644810) -> [spill 12] + v205 Imm(165891995) -> [spill 12] + v206 BinopI { op=and, lhs=v62, rhs_imm=165891995 } -> [spill 12] + v207 BinopI { op=xor, lhs=v206, rhs_imm=1521644810 } -> [spill 12] + v208 Imm(0) -> [spill 13] + v209 BinopI { op=and, lhs=v207, rhs_imm=4294967295 } -> [spill 13] + v210 Imm(1402060389) -> [spill 13] + v211 Imm(17022600) -> [spill 13] + v212 BinopI { op=and, lhs=v62, rhs_imm=17022600 } -> [spill 13] + v213 BinopI { op=xor, lhs=v212, rhs_imm=1402060389 } -> [spill 13] + v214 Imm(0) -> [spill 14] + v215 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> [spill 14] + v216 Imm(2469866415) -> [spill 14] + v217 Imm(1236045349) -> [spill 14] + v218 BinopI { op=and, lhs=v62, rhs_imm=1236045349 } -> [spill 14] + v219 BinopI { op=xor, lhs=v218, rhs_imm=2469866415 } -> [spill 14] + v220 Imm(0) -> [spill 15] + v221 BinopI { op=and, lhs=v219, rhs_imm=4294967295 } -> [spill 15] + v222 Imm(4069007628) -> [spill 15] + v223 Imm(2452369725) -> [spill 15] + v224 BinopI { op=and, lhs=v62, rhs_imm=2452369725 } -> [spill 15] + v225 BinopI { op=xor, lhs=v224, rhs_imm=4069007628 } -> [spill 15] + v226 Imm(0) -> [spill 16] + v227 BinopI { op=and, lhs=v225, rhs_imm=4294967295 } -> [spill 16] + v228 Imm(2450191808) -> [spill 16] + v229 Imm(1894724016) -> [spill 16] + v230 BinopI { op=and, lhs=v62, rhs_imm=1894724016 } -> [spill 16] + v231 BinopI { op=xor, lhs=v230, rhs_imm=2450191808 } -> [spill 16] + v232 Imm(0) -> [spill 17] + v233 BinopI { op=and, lhs=v231, rhs_imm=4294967295 } -> [spill 17] + v234 Imm(1674777280) -> [spill 17] + v235 Imm(1785753856) -> [spill 17] + v236 BinopI { op=and, lhs=v62, rhs_imm=1785753856 } -> [spill 17] + v237 BinopI { op=xor, lhs=v236, rhs_imm=1674777280 } -> [spill 17] + v238 Imm(0) -> [spill 18] + v239 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> [spill 18] + v240 Imm(1400582150) -> [spill 18] + v241 Imm(3111948305) -> [spill 18] + v242 BinopI { op=and, lhs=v62, rhs_imm=3111948305 } -> [spill 18] + v243 BinopI { op=xor, lhs=v242, rhs_imm=1400582150 } -> [spill 18] + v244 Imm(0) -> [spill 19] + v245 BinopI { op=and, lhs=v243, rhs_imm=4294967295 } -> [spill 19] + v246 Imm(2733617317) -> [spill 19] + v247 Imm(2736834905) -> [spill 19] + v248 BinopI { op=and, lhs=v62, rhs_imm=2736834905 } -> [spill 19] + v249 BinopI { op=xor, lhs=v248, rhs_imm=2733617317 } -> [spill 19] + v250 Imm(0) -> [spill 20] + v251 BinopI { op=and, lhs=v249, rhs_imm=4294967295 } -> [spill 20] + v252 Imm(3163526821) -> [spill 20] + v253 Imm(1856023370) -> [spill 20] + v254 BinopI { op=and, lhs=v62, rhs_imm=1856023370 } -> [spill 20] + v255 BinopI { op=xor, lhs=v254, rhs_imm=3163526821 } -> [spill 20] + v256 Imm(0) -> [spill 21] + v257 BinopI { op=and, lhs=v255, rhs_imm=4294967295 } -> [spill 21] + v258 Imm(4208031397) -> [spill 21] + v259 Imm(1767103992) -> [spill 21] + v260 BinopI { op=and, lhs=v62, rhs_imm=1767103992 } -> [spill 21] + v261 BinopI { op=xor, lhs=v260, rhs_imm=4208031397 } -> [spill 21] + v262 Imm(0) -> [spill 22] + v263 BinopI { op=and, lhs=v261, rhs_imm=4294967295 } -> [spill 22] + v264 Imm(1717179555) -> [spill 22] + v265 Imm(4149165611) -> [spill 22] + v266 BinopI { op=and, lhs=v62, rhs_imm=4149165611 } -> [spill 22] + v267 BinopI { op=xor, lhs=v266, rhs_imm=1717179555 } -> [spill 22] + v268 Imm(0) -> [spill 23] + v269 BinopI { op=and, lhs=v267, rhs_imm=4294967295 } -> [spill 23] + v270 Imm(4075811020) -> [spill 23] + v271 Imm(4029705389) -> [spill 23] v272 BinopI { op=and, lhs=v62, rhs_imm=4029705389 } -> x8 v273 BinopI { op=xor, lhs=v272, rhs_imm=4075811020 } -> x8 - v274 Imm(0) -> [spill 24] - v275 BinopI { op=and, lhs=v273, rhs_imm=4294967295 } -> [spill 24] + v274 Imm(0) -> [spill 23] + v275 BinopI { op=and, lhs=v273, rhs_imm=4294967295 } -> [spill 23] v276 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x9 - v277 BinopI { op=and, lhs=v105, rhs_imm=4294967295 } -> x12 - v278 Binop { op=and, lhs=v68, rhs=v277 } -> x12 + v277 BinopI { op=and, lhs=v105, rhs_imm=4294967295 } -> x3 + v278 Binop { op=and, lhs=v68, rhs=v277 } -> x3 v279 Binop { op=xor, lhs=v276, rhs=v278 } -> x9 - v280 Imm(0) -> x12 - v281 BinopI { op=and, lhs=v279, rhs_imm=4294967295 } -> x12 - v282 BinopI { op=and, lhs=v111, rhs_imm=4294967295 } -> x12 - v283 BinopI { op=and, lhs=v117, rhs_imm=4294967295 } -> x13 - v284 Binop { op=and, lhs=v68, rhs=v283 } -> x13 - v285 Binop { op=xor, lhs=v282, rhs=v284 } -> x12 - v286 Imm(0) -> x13 - v287 BinopI { op=and, lhs=v285, rhs_imm=4294967295 } -> x13 - v288 BinopI { op=and, lhs=v123, rhs_imm=4294967295 } -> x13 - v289 BinopI { op=and, lhs=v129, rhs_imm=4294967295 } -> x14 - v290 Binop { op=and, lhs=v68, rhs=v289 } -> x14 - v291 Binop { op=xor, lhs=v288, rhs=v290 } -> x13 - v292 Imm(0) -> x14 - v293 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x14 - v294 BinopI { op=and, lhs=v135, rhs_imm=4294967295 } -> x14 - v295 BinopI { op=and, lhs=v141, rhs_imm=4294967295 } -> x15 - v296 Binop { op=and, lhs=v68, rhs=v295 } -> x15 - v297 Binop { op=xor, lhs=v294, rhs=v296 } -> x14 - v298 Imm(0) -> x15 - v299 BinopI { op=and, lhs=v297, rhs_imm=4294967295 } -> x15 - v300 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x15 - v301 BinopI { op=and, lhs=v153, rhs_imm=4294967295 } -> [spill 0] - v302 Binop { op=and, lhs=v68, rhs=v301 } -> [spill 0] - v303 Binop { op=xor, lhs=v300, rhs=v302 } -> x15 - v304 Imm(0) -> [spill 0] - v305 BinopI { op=and, lhs=v303, rhs_imm=4294967295 } -> [spill 0] - v306 BinopI { op=and, lhs=v159, rhs_imm=4294967295 } -> [spill 0] - v307 BinopI { op=and, lhs=v165, rhs_imm=4294967295 } -> [spill 1] - v308 Binop { op=and, lhs=v68, rhs=v307 } -> [spill 1] - v309 Binop { op=xor, lhs=v306, rhs=v308 } -> [spill 0] - v310 Imm(0) -> [spill 1] - v311 BinopI { op=and, lhs=v309, rhs_imm=4294967295 } -> [spill 1] - v312 BinopI { op=and, lhs=v171, rhs_imm=4294967295 } -> [spill 1] - v313 BinopI { op=and, lhs=v177, rhs_imm=4294967295 } -> [spill 2] - v314 Binop { op=and, lhs=v68, rhs=v313 } -> [spill 2] - v315 Binop { op=xor, lhs=v312, rhs=v314 } -> [spill 1] - v316 Imm(0) -> [spill 2] - v317 BinopI { op=and, lhs=v315, rhs_imm=4294967295 } -> [spill 2] - v318 BinopI { op=and, lhs=v183, rhs_imm=4294967295 } -> [spill 2] - v319 Imm(0) -> [spill 3] - v320 BinopI { op=and, lhs=v189, rhs_imm=4294967295 } -> [spill 3] - v321 BinopI { op=and, lhs=v195, rhs_imm=4294967295 } -> [spill 4] - v322 Binop { op=and, lhs=v68, rhs=v321 } -> [spill 4] - v323 Binop { op=xor, lhs=v320, rhs=v322 } -> [spill 3] - v324 Imm(0) -> [spill 4] - v325 BinopI { op=and, lhs=v323, rhs_imm=4294967295 } -> [spill 4] - v326 BinopI { op=and, lhs=v201, rhs_imm=4294967295 } -> [spill 4] - v327 BinopI { op=and, lhs=v207, rhs_imm=4294967295 } -> [spill 5] - v328 Binop { op=and, lhs=v68, rhs=v327 } -> [spill 5] - v329 Binop { op=xor, lhs=v326, rhs=v328 } -> [spill 4] - v330 Imm(0) -> [spill 5] - v331 BinopI { op=and, lhs=v329, rhs_imm=4294967295 } -> [spill 5] - v332 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> [spill 5] - v333 BinopI { op=and, lhs=v219, rhs_imm=4294967295 } -> [spill 6] - v334 Binop { op=and, lhs=v68, rhs=v333 } -> [spill 6] - v335 Binop { op=xor, lhs=v332, rhs=v334 } -> [spill 5] - v336 Imm(0) -> [spill 6] - v337 BinopI { op=and, lhs=v335, rhs_imm=4294967295 } -> [spill 6] - v338 BinopI { op=and, lhs=v225, rhs_imm=4294967295 } -> [spill 6] - v339 BinopI { op=and, lhs=v231, rhs_imm=4294967295 } -> [spill 7] - v340 Binop { op=and, lhs=v68, rhs=v339 } -> [spill 7] - v341 Binop { op=xor, lhs=v338, rhs=v340 } -> [spill 6] - v342 Imm(0) -> [spill 7] - v343 BinopI { op=and, lhs=v341, rhs_imm=4294967295 } -> [spill 7] - v344 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> [spill 7] - v345 BinopI { op=and, lhs=v243, rhs_imm=4294967295 } -> [spill 8] - v346 Binop { op=and, lhs=v68, rhs=v345 } -> [spill 8] - v347 Binop { op=xor, lhs=v344, rhs=v346 } -> [spill 7] - v348 Imm(0) -> [spill 8] - v349 BinopI { op=and, lhs=v347, rhs_imm=4294967295 } -> [spill 8] - v350 BinopI { op=and, lhs=v249, rhs_imm=4294967295 } -> [spill 8] - v351 BinopI { op=and, lhs=v255, rhs_imm=4294967295 } -> [spill 9] - v352 Binop { op=and, lhs=v68, rhs=v351 } -> [spill 9] - v353 Binop { op=xor, lhs=v350, rhs=v352 } -> [spill 8] - v354 Imm(0) -> [spill 9] - v355 BinopI { op=and, lhs=v353, rhs_imm=4294967295 } -> [spill 9] - v356 BinopI { op=and, lhs=v261, rhs_imm=4294967295 } -> [spill 9] - v357 BinopI { op=and, lhs=v267, rhs_imm=4294967295 } -> [spill 10] + v280 Imm(0) -> x3 + v281 BinopI { op=and, lhs=v279, rhs_imm=4294967295 } -> x3 + v282 BinopI { op=and, lhs=v111, rhs_imm=4294967295 } -> x3 + v283 BinopI { op=and, lhs=v117, rhs_imm=4294967295 } -> x12 + v284 Binop { op=and, lhs=v68, rhs=v283 } -> x12 + v285 Binop { op=xor, lhs=v282, rhs=v284 } -> x3 + v286 Imm(0) -> x12 + v287 BinopI { op=and, lhs=v285, rhs_imm=4294967295 } -> x12 + v288 BinopI { op=and, lhs=v123, rhs_imm=4294967295 } -> x12 + v289 BinopI { op=and, lhs=v129, rhs_imm=4294967295 } -> x13 + v290 Binop { op=and, lhs=v68, rhs=v289 } -> x13 + v291 Binop { op=xor, lhs=v288, rhs=v290 } -> x12 + v292 Imm(0) -> x13 + v293 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x13 + v294 BinopI { op=and, lhs=v135, rhs_imm=4294967295 } -> x13 + v295 BinopI { op=and, lhs=v141, rhs_imm=4294967295 } -> x14 + v296 Binop { op=and, lhs=v68, rhs=v295 } -> x14 + v297 Binop { op=xor, lhs=v294, rhs=v296 } -> x13 + v298 Imm(0) -> x14 + v299 BinopI { op=and, lhs=v297, rhs_imm=4294967295 } -> x14 + v300 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x14 + v301 BinopI { op=and, lhs=v153, rhs_imm=4294967295 } -> x15 + v302 Binop { op=and, lhs=v68, rhs=v301 } -> x15 + v303 Binop { op=xor, lhs=v300, rhs=v302 } -> x14 + v304 Imm(0) -> x15 + v305 BinopI { op=and, lhs=v303, rhs_imm=4294967295 } -> x15 + v306 BinopI { op=and, lhs=v159, rhs_imm=4294967295 } -> x15 + v307 BinopI { op=and, lhs=v165, rhs_imm=4294967295 } -> [spill 0] + v308 Binop { op=and, lhs=v68, rhs=v307 } -> [spill 0] + v309 Binop { op=xor, lhs=v306, rhs=v308 } -> x15 + v310 Imm(0) -> [spill 0] + v311 BinopI { op=and, lhs=v309, rhs_imm=4294967295 } -> [spill 0] + v312 BinopI { op=and, lhs=v171, rhs_imm=4294967295 } -> [spill 0] + v313 BinopI { op=and, lhs=v177, rhs_imm=4294967295 } -> [spill 1] + v314 Binop { op=and, lhs=v68, rhs=v313 } -> [spill 1] + v315 Binop { op=xor, lhs=v312, rhs=v314 } -> [spill 0] + v316 Imm(0) -> [spill 1] + v317 BinopI { op=and, lhs=v315, rhs_imm=4294967295 } -> [spill 1] + v318 BinopI { op=and, lhs=v183, rhs_imm=4294967295 } -> [spill 1] + v319 Imm(0) -> [spill 2] + v320 BinopI { op=and, lhs=v189, rhs_imm=4294967295 } -> [spill 2] + v321 BinopI { op=and, lhs=v195, rhs_imm=4294967295 } -> [spill 3] + v322 Binop { op=and, lhs=v68, rhs=v321 } -> [spill 3] + v323 Binop { op=xor, lhs=v320, rhs=v322 } -> [spill 2] + v324 Imm(0) -> [spill 3] + v325 BinopI { op=and, lhs=v323, rhs_imm=4294967295 } -> [spill 3] + v326 BinopI { op=and, lhs=v201, rhs_imm=4294967295 } -> [spill 3] + v327 BinopI { op=and, lhs=v207, rhs_imm=4294967295 } -> [spill 4] + v328 Binop { op=and, lhs=v68, rhs=v327 } -> [spill 4] + v329 Binop { op=xor, lhs=v326, rhs=v328 } -> [spill 3] + v330 Imm(0) -> [spill 4] + v331 BinopI { op=and, lhs=v329, rhs_imm=4294967295 } -> [spill 4] + v332 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> [spill 4] + v333 BinopI { op=and, lhs=v219, rhs_imm=4294967295 } -> [spill 5] + v334 Binop { op=and, lhs=v68, rhs=v333 } -> [spill 5] + v335 Binop { op=xor, lhs=v332, rhs=v334 } -> [spill 4] + v336 Imm(0) -> [spill 5] + v337 BinopI { op=and, lhs=v335, rhs_imm=4294967295 } -> [spill 5] + v338 BinopI { op=and, lhs=v225, rhs_imm=4294967295 } -> [spill 5] + v339 BinopI { op=and, lhs=v231, rhs_imm=4294967295 } -> [spill 6] + v340 Binop { op=and, lhs=v68, rhs=v339 } -> [spill 6] + v341 Binop { op=xor, lhs=v338, rhs=v340 } -> [spill 5] + v342 Imm(0) -> [spill 6] + v343 BinopI { op=and, lhs=v341, rhs_imm=4294967295 } -> [spill 6] + v344 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> [spill 6] + v345 BinopI { op=and, lhs=v243, rhs_imm=4294967295 } -> [spill 7] + v346 Binop { op=and, lhs=v68, rhs=v345 } -> [spill 7] + v347 Binop { op=xor, lhs=v344, rhs=v346 } -> [spill 6] + v348 Imm(0) -> [spill 7] + v349 BinopI { op=and, lhs=v347, rhs_imm=4294967295 } -> [spill 7] + v350 BinopI { op=and, lhs=v249, rhs_imm=4294967295 } -> [spill 7] + v351 BinopI { op=and, lhs=v255, rhs_imm=4294967295 } -> [spill 8] + v352 Binop { op=and, lhs=v68, rhs=v351 } -> [spill 8] + v353 Binop { op=xor, lhs=v350, rhs=v352 } -> [spill 7] + v354 Imm(0) -> [spill 8] + v355 BinopI { op=and, lhs=v353, rhs_imm=4294967295 } -> [spill 8] + v356 BinopI { op=and, lhs=v261, rhs_imm=4294967295 } -> [spill 8] + v357 BinopI { op=and, lhs=v267, rhs_imm=4294967295 } -> [spill 9] v358 Binop { op=and, lhs=v68, rhs=v357 } -> x1 v359 Binop { op=xor, lhs=v356, rhs=v358 } -> x1 - v360 Imm(0) -> [spill 9] - v361 BinopI { op=and, lhs=v359, rhs_imm=4294967295 } -> [spill 9] + v360 Imm(0) -> [spill 8] + v361 BinopI { op=and, lhs=v359, rhs_imm=4294967295 } -> [spill 8] v362 BinopI { op=and, lhs=v273, rhs_imm=4294967295 } -> x8 - v363 Imm(0) -> [spill 9] + v363 Imm(0) -> [spill 8] v364 BinopI { op=and, lhs=v279, rhs_imm=4294967295 } -> x9 - v365 BinopI { op=and, lhs=v285, rhs_imm=4294967295 } -> x12 - v366 Binop { op=and, lhs=v75, rhs=v365 } -> x12 + v365 BinopI { op=and, lhs=v285, rhs_imm=4294967295 } -> x3 + v366 Binop { op=and, lhs=v75, rhs=v365 } -> x3 v367 Binop { op=xor, lhs=v364, rhs=v366 } -> x9 - v368 Imm(0) -> x12 - v369 BinopI { op=and, lhs=v367, rhs_imm=4294967295 } -> x12 - v370 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x12 - v371 BinopI { op=and, lhs=v297, rhs_imm=4294967295 } -> x13 - v372 Binop { op=and, lhs=v75, rhs=v371 } -> x13 - v373 Binop { op=xor, lhs=v370, rhs=v372 } -> x12 - v374 Imm(0) -> x13 - v375 BinopI { op=and, lhs=v373, rhs_imm=4294967295 } -> x13 - v376 BinopI { op=and, lhs=v303, rhs_imm=4294967295 } -> x13 - v377 BinopI { op=and, lhs=v309, rhs_imm=4294967295 } -> x14 - v378 Binop { op=and, lhs=v75, rhs=v377 } -> x14 - v379 Binop { op=xor, lhs=v376, rhs=v378 } -> x13 - v380 Imm(0) -> x14 - v381 BinopI { op=and, lhs=v379, rhs_imm=4294967295 } -> x14 - v382 BinopI { op=and, lhs=v315, rhs_imm=4294967295 } -> x14 - v383 BinopI { op=and, lhs=v318, rhs_imm=4294967295 } -> x15 - v384 Binop { op=and, lhs=v75, rhs=v383 } -> x15 - v385 Binop { op=xor, lhs=v382, rhs=v384 } -> x14 - v386 Imm(0) -> x15 - v387 BinopI { op=and, lhs=v385, rhs_imm=4294967295 } -> x15 - v388 BinopI { op=and, lhs=v323, rhs_imm=4294967295 } -> x15 - v389 BinopI { op=and, lhs=v329, rhs_imm=4294967295 } -> [spill 0] - v390 Binop { op=and, lhs=v75, rhs=v389 } -> [spill 0] - v391 Binop { op=xor, lhs=v388, rhs=v390 } -> x15 - v392 Imm(0) -> [spill 0] - v393 BinopI { op=and, lhs=v391, rhs_imm=4294967295 } -> [spill 0] - v394 BinopI { op=and, lhs=v335, rhs_imm=4294967295 } -> [spill 0] - v395 BinopI { op=and, lhs=v341, rhs_imm=4294967295 } -> [spill 1] - v396 Binop { op=and, lhs=v75, rhs=v395 } -> [spill 1] - v397 Binop { op=xor, lhs=v394, rhs=v396 } -> [spill 0] - v398 Imm(0) -> [spill 1] - v399 BinopI { op=and, lhs=v397, rhs_imm=4294967295 } -> [spill 1] - v400 BinopI { op=and, lhs=v347, rhs_imm=4294967295 } -> [spill 1] - v401 BinopI { op=and, lhs=v353, rhs_imm=4294967295 } -> [spill 2] - v402 Binop { op=and, lhs=v75, rhs=v401 } -> [spill 2] - v403 Binop { op=xor, lhs=v400, rhs=v402 } -> [spill 1] - v404 Imm(0) -> [spill 2] - v405 BinopI { op=and, lhs=v403, rhs_imm=4294967295 } -> [spill 2] + v368 Imm(0) -> x3 + v369 BinopI { op=and, lhs=v367, rhs_imm=4294967295 } -> x3 + v370 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x3 + v371 BinopI { op=and, lhs=v297, rhs_imm=4294967295 } -> x12 + v372 Binop { op=and, lhs=v75, rhs=v371 } -> x12 + v373 Binop { op=xor, lhs=v370, rhs=v372 } -> x3 + v374 Imm(0) -> x12 + v375 BinopI { op=and, lhs=v373, rhs_imm=4294967295 } -> x12 + v376 BinopI { op=and, lhs=v303, rhs_imm=4294967295 } -> x12 + v377 BinopI { op=and, lhs=v309, rhs_imm=4294967295 } -> x13 + v378 Binop { op=and, lhs=v75, rhs=v377 } -> x13 + v379 Binop { op=xor, lhs=v376, rhs=v378 } -> x12 + v380 Imm(0) -> x13 + v381 BinopI { op=and, lhs=v379, rhs_imm=4294967295 } -> x13 + v382 BinopI { op=and, lhs=v315, rhs_imm=4294967295 } -> x13 + v383 BinopI { op=and, lhs=v318, rhs_imm=4294967295 } -> x14 + v384 Binop { op=and, lhs=v75, rhs=v383 } -> x14 + v385 Binop { op=xor, lhs=v382, rhs=v384 } -> x13 + v386 Imm(0) -> x14 + v387 BinopI { op=and, lhs=v385, rhs_imm=4294967295 } -> x14 + v388 BinopI { op=and, lhs=v323, rhs_imm=4294967295 } -> x14 + v389 BinopI { op=and, lhs=v329, rhs_imm=4294967295 } -> x15 + v390 Binop { op=and, lhs=v75, rhs=v389 } -> x15 + v391 Binop { op=xor, lhs=v388, rhs=v390 } -> x14 + v392 Imm(0) -> x15 + v393 BinopI { op=and, lhs=v391, rhs_imm=4294967295 } -> x15 + v394 BinopI { op=and, lhs=v335, rhs_imm=4294967295 } -> x15 + v395 BinopI { op=and, lhs=v341, rhs_imm=4294967295 } -> [spill 0] + v396 Binop { op=and, lhs=v75, rhs=v395 } -> [spill 0] + v397 Binop { op=xor, lhs=v394, rhs=v396 } -> x15 + v398 Imm(0) -> [spill 0] + v399 BinopI { op=and, lhs=v397, rhs_imm=4294967295 } -> [spill 0] + v400 BinopI { op=and, lhs=v347, rhs_imm=4294967295 } -> [spill 0] + v401 BinopI { op=and, lhs=v353, rhs_imm=4294967295 } -> [spill 1] + v402 Binop { op=and, lhs=v75, rhs=v401 } -> [spill 1] + v403 Binop { op=xor, lhs=v400, rhs=v402 } -> [spill 0] + v404 Imm(0) -> [spill 1] + v405 BinopI { op=and, lhs=v403, rhs_imm=4294967295 } -> [spill 1] v406 BinopI { op=and, lhs=v359, rhs_imm=4294967295 } -> x1 v407 BinopI { op=and, lhs=v362, rhs_imm=4294967295 } -> x8 v408 Binop { op=and, lhs=v75, rhs=v407 } -> x2 @@ -449,12 +449,12 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v422 Imm(0) -> x9 v423 BinopI { op=and, lhs=v421, rhs_imm=4294967295 } -> x9 v424 BinopI { op=and, lhs=v391, rhs_imm=4294967295 } -> x9 - v425 BinopI { op=and, lhs=v397, rhs_imm=4294967295 } -> x12 - v426 Binop { op=and, lhs=v82, rhs=v425 } -> x12 + v425 BinopI { op=and, lhs=v397, rhs_imm=4294967295 } -> x3 + v426 Binop { op=and, lhs=v82, rhs=v425 } -> x3 v427 Binop { op=xor, lhs=v424, rhs=v426 } -> x9 - v428 Imm(0) -> x12 - v429 BinopI { op=and, lhs=v427, rhs_imm=4294967295 } -> x12 - v430 BinopI { op=and, lhs=v403, rhs_imm=4294967295 } -> x12 + v428 Imm(0) -> x3 + v429 BinopI { op=and, lhs=v427, rhs_imm=4294967295 } -> x3 + v430 BinopI { op=and, lhs=v403, rhs_imm=4294967295 } -> x3 v431 BinopI { op=and, lhs=v409, rhs_imm=4294967295 } -> x1 v432 Binop { op=and, lhs=v82, rhs=v431 } -> x1 v433 Binop { op=xor, lhs=v430, rhs=v432 } -> x1 @@ -493,17 +493,17 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v466 BinopI { op=and, lhs=v464, rhs_imm=4294967295 } -> x2 v467 BinopI { op=and, lhs=v454, rhs_imm=302121248 } -> x1 v468 Imm(5) -> x6 - v469 Imm(0) -> x7 - v470 Extend { value=v468, kind=I32 } -> x6 - v471 Imm(0) -> x7 + v469 Imm(0) -> x6 + v470 Imm(5) -> x6 + v471 Imm(0) -> x6 v472 BinopI { op=and, lhs=v467, rhs_imm=4294967295 } -> x1 - v473 Binop { op=shl, lhs=v472, rhs=v470 } -> x7 - v474 BinopI { op=and, lhs=v473, rhs_imm=4294967295 } -> x7 - v475 Imm(32) -> x8 - v476 Binop { op=sub, lhs=v475, rhs=v470 } -> x6 - v477 BinopI { op=shl, lhs=v476, rhs_imm=32 } -> x8 - v478 Extend { value=v476, kind=I32 } -> x6 - v479 Binop { op=shru, lhs=v472, rhs=v478 } -> x1 + v473 BinopI { op=shl, lhs=v472, rhs_imm=5 } -> x6 + v474 BinopI { op=and, lhs=v473, rhs_imm=4294967295 } -> x6 + v475 Imm(32) -> x7 + v476 Imm(27) -> x7 + v477 Imm(115964116992) -> x7 + v478 Imm(27) -> x7 + v479 BinopI { op=shru, lhs=v472, rhs_imm=27 } -> x1 v480 Binop { op=or, lhs=v474, rhs=v479 } -> x1 v481 Binop { op=or, lhs=v466, rhs=v480 } -> x1 v482 Imm(0) -> x2 @@ -538,16 +538,16 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v511 BinopI { op=and, lhs=v509, rhs_imm=4294967295 } -> x1 v512 BinopI { op=and, lhs=v484, rhs_imm=536871424 } -> x2 v513 Imm(0) -> x6 - v514 Extend { value=v77, kind=I32 } -> x6 - v515 Imm(0) -> x7 + v514 Imm(12) -> x6 + v515 Imm(0) -> x6 v516 BinopI { op=and, lhs=v512, rhs_imm=4294967295 } -> x2 - v517 Binop { op=shl, lhs=v516, rhs=v514 } -> x7 - v518 BinopI { op=and, lhs=v517, rhs_imm=4294967295 } -> x7 - v519 Imm(32) -> x8 - v520 Binop { op=sub, lhs=v519, rhs=v514 } -> x6 - v521 BinopI { op=shl, lhs=v520, rhs_imm=32 } -> x8 - v522 Extend { value=v520, kind=I32 } -> x6 - v523 Binop { op=shru, lhs=v516, rhs=v522 } -> x2 + v517 BinopI { op=shl, lhs=v516, rhs_imm=12 } -> x6 + v518 BinopI { op=and, lhs=v517, rhs_imm=4294967295 } -> x6 + v519 Imm(32) -> x7 + v520 Imm(20) -> x7 + v521 Imm(85899345920) -> x7 + v522 Imm(20) -> x7 + v523 BinopI { op=shru, lhs=v516, rhs_imm=20 } -> x2 v524 Binop { op=or, lhs=v518, rhs=v523 } -> x2 v525 Binop { op=or, lhs=v511, rhs=v524 } -> x1 v526 Imm(0) -> x2 @@ -582,17 +582,17 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v555 BinopI { op=and, lhs=v553, rhs_imm=4294967295 } -> x1 v556 BinopI { op=and, lhs=v528, rhs_imm=1082136576 } -> x2 v557 Imm(17) -> x6 - v558 Imm(0) -> x7 - v559 Extend { value=v557, kind=I32 } -> x6 - v560 Imm(0) -> x7 + v558 Imm(0) -> x6 + v559 Imm(17) -> x6 + v560 Imm(0) -> x6 v561 BinopI { op=and, lhs=v556, rhs_imm=4294967295 } -> x2 - v562 Binop { op=shl, lhs=v561, rhs=v559 } -> x7 - v563 BinopI { op=and, lhs=v562, rhs_imm=4294967295 } -> x7 - v564 Imm(32) -> x8 - v565 Binop { op=sub, lhs=v564, rhs=v559 } -> x6 - v566 BinopI { op=shl, lhs=v565, rhs_imm=32 } -> x8 - v567 Extend { value=v565, kind=I32 } -> x6 - v568 Binop { op=shru, lhs=v561, rhs=v567 } -> x2 + v562 BinopI { op=shl, lhs=v561, rhs_imm=17 } -> x6 + v563 BinopI { op=and, lhs=v562, rhs_imm=4294967295 } -> x6 + v564 Imm(32) -> x7 + v565 Imm(15) -> x7 + v566 Imm(64424509440) -> x7 + v567 Imm(15) -> x7 + v568 BinopI { op=shru, lhs=v561, rhs_imm=15 } -> x2 v569 Binop { op=or, lhs=v563, rhs=v568 } -> x2 v570 Binop { op=or, lhs=v555, rhs=v569 } -> x1 v571 Imm(0) -> x2 @@ -618,17 +618,17 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 v591 BinopI { op=and, lhs=v589, rhs_imm=4294967295 } -> x1 v592 BinopI { op=and, lhs=v573, rhs_imm=2281701384 } -> x2 v593 Imm(24) -> x6 - v594 Imm(0) -> x7 - v595 Extend { value=v593, kind=I32 } -> x6 - v596 Imm(0) -> x7 + v594 Imm(0) -> x6 + v595 Imm(24) -> x6 + v596 Imm(0) -> x6 v597 BinopI { op=and, lhs=v592, rhs_imm=4294967295 } -> x2 - v598 Binop { op=shl, lhs=v597, rhs=v595 } -> x7 - v599 BinopI { op=and, lhs=v598, rhs_imm=4294967295 } -> x7 - v600 Imm(32) -> x8 - v601 Binop { op=sub, lhs=v600, rhs=v595 } -> x6 - v602 BinopI { op=shl, lhs=v601, rhs_imm=32 } -> x8 - v603 Extend { value=v601, kind=I32 } -> x6 - v604 Binop { op=shru, lhs=v597, rhs=v603 } -> x2 + v598 BinopI { op=shl, lhs=v597, rhs_imm=24 } -> x6 + v599 BinopI { op=and, lhs=v598, rhs_imm=4294967295 } -> x6 + v600 Imm(32) -> x7 + v601 Imm(8) -> x7 + v602 Imm(34359738368) -> x7 + v603 Imm(8) -> x7 + v604 BinopI { op=shru, lhs=v597, rhs_imm=8 } -> x2 v605 Binop { op=or, lhs=v599, rhs=v604 } -> x2 v606 Binop { op=or, lhs=v591, rhs=v605 } -> x1 v607 Imm(0) -> x2 @@ -650,54 +650,319 @@ fn ent_pc=1 n_params=2 variadic=false locals=40 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=5 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x3 - v2 Imm(0) -> x0 - v3 Imm(2779096485) -> x12 - v4 Imm(0) -> x0 - v5 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(2779096485) -> x1 + v4 Imm(0) -> x1 + v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v6 Phi { incoming=[b0:v1, b2:v12], kind=I64 } -> x3 - v7 Phi { incoming=[b0:v3, b2:v25], kind=I64 } -> x12 - v8 Phi { incoming=[b0:v1, b2:v18], kind=I64 } -> x13 - v9 Extend { value=v6, kind=I32 } -> x0 - v10 BinopI { op=lt, lhs=v9, rhs_imm=16 } -> x0 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 Imm(2779096485) -> x7 + v10 ImmData(8) -> x6 + v11 Call { target_pc=1, args=[v9, v10], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v12 BinopI { op=xor, lhs=v11, rhs_imm=0 } -> x0 + v13 Imm(0) -> x1 + v14 BinopI { op=and, lhs=v12, rhs_imm=4294967295 } -> x1 + v15 Imm(2779096485) -> x1 + v16 Imm(4625875576694625) -> x1 + v17 Imm(2525374305) -> x1 + v18 Imm(3539278528) -> x1 + v19 Imm(3539278528) -> x1 + v20 Imm(0) -> x1 + v21 Imm(0) -> x1 + v22 Imm(1) -> x1 + v23 Imm(0) -> x1 + v24 Imm(1) -> x1 + v25 Imm(1) -> x1 + v26 BinopI { op=and, lhs=v12, rhs_imm=4294967295 } -> x3 + v27 Imm(3539278528) -> x7 + v28 ImmData(8) -> x6 + v29 Call { target_pc=1, args=[v27, v28], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v30 Binop { op=xor, lhs=v26, rhs=v29 } -> x0 + v31 Imm(0) -> x1 + v32 BinopI { op=and, lhs=v30, rhs_imm=4294967295 } -> x1 + v33 Imm(3539278528) -> x1 + v34 Imm(5891217591819200) -> x1 + v35 Imm(4225424320) -> x1 + v36 Imm(5239328543) -> x1 + v37 Imm(944361247) -> x1 + v38 Imm(0) -> x1 + v39 Imm(1) -> x1 + v40 Imm(2) -> x1 + v41 Imm(0) -> x1 + v42 Imm(2) -> x1 + v43 Imm(1) -> x1 + v44 BinopI { op=and, lhs=v30, rhs_imm=4294967295 } -> x3 + v45 Imm(944361247) -> x7 + v46 ImmData(8) -> x6 + v47 Call { target_pc=1, args=[v45, v46], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v48 Binop { op=xor, lhs=v44, rhs=v47 } -> x0 + v49 Imm(0) -> x1 + v50 BinopI { op=and, lhs=v48, rhs_imm=4294967295 } -> x1 + v51 Imm(944361247) -> x1 + v52 Imm(1571912904662675) -> x1 + v53 Imm(2118966931) -> x1 + v54 Imm(3132871154) -> x1 + v55 Imm(3132871154) -> x1 + v56 Imm(0) -> x1 + v57 Imm(2) -> x1 + v58 Imm(3) -> x1 + v59 Imm(0) -> x1 + v60 Imm(3) -> x1 + v61 Imm(1) -> x1 + v62 BinopI { op=and, lhs=v48, rhs_imm=4294967295 } -> x3 + v63 Imm(3132871154) -> x7 + v64 ImmData(8) -> x6 + v65 Call { target_pc=1, args=[v63, v64], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v66 Binop { op=xor, lhs=v62, rhs=v65 } -> x0 + v67 Imm(0) -> x1 + v68 BinopI { op=and, lhs=v66, rhs_imm=4294967295 } -> x1 + v69 Imm(3132871154) -> x1 + v70 Imm(5214742357611850) -> x1 + v71 Imm(3520206154) -> x1 + v72 Imm(4534110377) -> x1 + v73 Imm(239143081) -> x1 + v74 Imm(0) -> x1 + v75 Imm(3) -> x1 + v76 Imm(4) -> x1 + v77 Imm(0) -> x1 + v78 Imm(4) -> x1 + v79 Imm(1) -> x1 + v80 BinopI { op=and, lhs=v66, rhs_imm=4294967295 } -> x3 + v81 Imm(239143081) -> x7 + v82 ImmData(8) -> x6 + v83 Call { target_pc=1, args=[v81, v82], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v84 Binop { op=xor, lhs=v80, rhs=v83 } -> x0 + v85 Imm(0) -> x1 + v86 BinopI { op=and, lhs=v84, rhs_imm=4294967295 } -> x1 + v87 Imm(239143081) -> x1 + v88 Imm(398059636901525) -> x1 + v89 Imm(2067908245) -> x1 + v90 Imm(3081812468) -> x1 + v91 Imm(3081812468) -> x1 + v92 Imm(0) -> x1 + v93 Imm(4) -> x1 + v94 Imm(5) -> x1 + v95 Imm(0) -> x1 + v96 Imm(5) -> x1 + v97 Imm(1) -> x1 + v98 BinopI { op=and, lhs=v84, rhs_imm=4294967295 } -> x3 + v99 Imm(3081812468) -> x7 + v100 ImmData(8) -> x6 + v101 Call { target_pc=1, args=[v99, v100], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v102 Binop { op=xor, lhs=v98, rhs=v101 } -> x0 + v103 Imm(0) -> x1 + v104 BinopI { op=and, lhs=v102, rhs_imm=4294967295 } -> x1 + v105 Imm(3081812468) -> x1 + v106 Imm(5129753898297700) -> x1 + v107 Imm(3873745252) -> x1 + v108 Imm(4887649475) -> x1 + v109 Imm(592682179) -> x1 + v110 Imm(0) -> x1 + v111 Imm(5) -> x1 + v112 Imm(6) -> x1 + v113 Imm(0) -> x1 + v114 Imm(6) -> x1 + v115 Imm(1) -> x1 + v116 BinopI { op=and, lhs=v102, rhs_imm=4294967295 } -> x3 + v117 Imm(592682179) -> x7 + v118 ImmData(8) -> x6 + v119 Call { target_pc=1, args=[v117, v118], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v120 Binop { op=xor, lhs=v116, rhs=v119 } -> x0 + v121 Imm(0) -> x1 + v122 BinopI { op=and, lhs=v120, rhs_imm=4294967295 } -> x1 + v123 Imm(592682179) -> x1 + v124 Imm(986534303999975) -> x1 + v125 Imm(1790945255) -> x1 + v126 Imm(2804849478) -> x1 + v127 Imm(2804849478) -> x1 + v128 Imm(0) -> x1 + v129 Imm(6) -> x1 + v130 Imm(7) -> x1 + v131 Imm(0) -> x1 + v132 Imm(7) -> x1 + v133 Imm(1) -> x1 + v134 BinopI { op=and, lhs=v120, rhs_imm=4294967295 } -> x3 + v135 Imm(2804849478) -> x7 + v136 ImmData(8) -> x6 + v137 Call { target_pc=1, args=[v135, v136], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v138 Binop { op=xor, lhs=v134, rhs=v137 } -> x0 + v139 Imm(0) -> x1 + v140 BinopI { op=and, lhs=v138, rhs_imm=4294967295 } -> x1 + v141 Imm(2804849478) -> x1 + v142 Imm(4668742077367950) -> x1 + v143 Imm(957466254) -> x1 + v144 Imm(1971370477) -> x1 + v145 Imm(1971370477) -> x1 + v146 Imm(0) -> x1 + v147 Imm(7) -> x1 + v148 Imm(8) -> x1 + v149 Imm(0) -> x1 + v150 Imm(8) -> x1 + v151 Imm(1) -> x1 + v152 BinopI { op=and, lhs=v138, rhs_imm=4294967295 } -> x3 + v153 Imm(1971370477) -> x7 + v154 ImmData(8) -> x6 + v155 Call { target_pc=1, args=[v153, v154], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v156 Binop { op=xor, lhs=v152, rhs=v155 } -> x0 + v157 Imm(0) -> x1 + v158 BinopI { op=and, lhs=v156, rhs_imm=4294967295 } -> x1 + v159 Imm(1971370477) -> x1 + v160 Imm(3281395443228425) -> x1 + v161 Imm(1774378761) -> x1 + v162 Imm(2788282984) -> x1 + v163 Imm(2788282984) -> x1 + v164 Imm(0) -> x1 + v165 Imm(8) -> x1 + v166 Imm(9) -> x1 + v167 Imm(0) -> x1 + v168 Imm(9) -> x1 + v169 Imm(1) -> x1 + v170 BinopI { op=and, lhs=v156, rhs_imm=4294967295 } -> x3 + v171 Imm(2788282984) -> x7 + v172 ImmData(8) -> x6 + v173 Call { target_pc=1, args=[v171, v172], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v174 Binop { op=xor, lhs=v170, rhs=v173 } -> x0 + v175 Imm(0) -> x1 + v176 BinopI { op=and, lhs=v174, rhs_imm=4294967295 } -> x1 + v177 Imm(2788282984) -> x1 + v178 Imm(4641166733942600) -> x1 + v179 Imm(3599048520) -> x1 + v180 Imm(4612952743) -> x1 + v181 Imm(317985447) -> x1 + v182 Imm(0) -> x1 + v183 Imm(9) -> x1 + v184 Imm(10) -> x1 + v185 Imm(0) -> x1 + v186 Imm(10) -> x1 + v187 Imm(1) -> x1 + v188 BinopI { op=and, lhs=v174, rhs_imm=4294967295 } -> x3 + v189 Imm(317985447) -> x7 + v190 ImmData(8) -> x6 + v191 Call { target_pc=1, args=[v189, v190], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v192 Binop { op=xor, lhs=v188, rhs=v191 } -> x0 + v193 Imm(0) -> x1 + v194 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x1 + v195 Imm(317985447) -> x1 + v196 Imm(529294726167675) -> x1 + v197 Imm(136477819) -> x1 + v198 Imm(1150382042) -> x1 + v199 Imm(1150382042) -> x1 + v200 Imm(0) -> x1 + v201 Imm(10) -> x1 + v202 Imm(11) -> x1 + v203 Imm(0) -> x1 + v204 Imm(11) -> x1 + v205 Imm(1) -> x1 + v206 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x3 + v207 Imm(1150382042) -> x7 + v208 ImmData(8) -> x6 + v209 Call { target_pc=1, args=[v207, v208], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v210 Binop { op=xor, lhs=v206, rhs=v209 } -> x0 + v211 Imm(0) -> x1 + v212 BinopI { op=and, lhs=v210, rhs_imm=4294967295 } -> x1 + v213 Imm(1150382042) -> x1 + v214 Imm(1914839668460050) -> x1 + v215 Imm(1513982482) -> x1 + v216 Imm(2527886705) -> x1 + v217 Imm(2527886705) -> x1 + v218 Imm(0) -> x1 + v219 Imm(11) -> x1 + v220 Imm(12) -> x1 + v221 Imm(0) -> x1 + v222 Imm(12) -> x1 + v223 Imm(1) -> x1 + v224 BinopI { op=and, lhs=v210, rhs_imm=4294967295 } -> x3 + v225 Imm(2527886705) -> x7 + v226 ImmData(8) -> x6 + v227 Call { target_pc=1, args=[v225, v226], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v228 Binop { op=xor, lhs=v224, rhs=v227 } -> x0 + v229 Imm(0) -> x1 + v230 BinopI { op=and, lhs=v228, rhs_imm=4294967295 } -> x1 + v231 Imm(2527886705) -> x1 + v232 Imm(4207730617640125) -> x1 + v233 Imm(2697356477) -> x1 + v234 Imm(3711260700) -> x1 + v235 Imm(3711260700) -> x1 + v236 Imm(0) -> x1 + v237 Imm(12) -> x1 + v238 Imm(13) -> x1 + v239 Imm(0) -> x1 + v240 Imm(13) -> x1 + v241 Imm(1) -> x1 + v242 BinopI { op=and, lhs=v228, rhs_imm=4294967295 } -> x3 + v243 Imm(3711260700) -> x7 + v244 ImmData(8) -> x6 + v245 Call { target_pc=1, args=[v243, v244], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v246 Binop { op=xor, lhs=v242, rhs=v245 } -> x0 + v247 Imm(0) -> x1 + v248 BinopI { op=and, lhs=v246, rhs_imm=4294967295 } -> x1 + v249 Imm(3711260700) -> x1 + v250 Imm(6177486216667500) -> x1 + v251 Imm(395092332) -> x1 + v252 Imm(1408996555) -> x1 + v253 Imm(1408996555) -> x1 + v254 Imm(0) -> x1 + v255 Imm(13) -> x1 + v256 Imm(14) -> x1 + v257 Imm(0) -> x1 + v258 Imm(14) -> x1 + v259 Imm(1) -> x1 + v260 BinopI { op=and, lhs=v246, rhs_imm=4294967295 } -> x3 + v261 Imm(1408996555) -> x7 + v262 ImmData(8) -> x6 + v263 Call { target_pc=1, args=[v261, v262], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v264 Binop { op=xor, lhs=v260, rhs=v263 } -> x0 + v265 Imm(0) -> x1 + v266 BinopI { op=and, lhs=v264, rhs_imm=4294967295 } -> x1 + v267 Imm(1408996555) -> x1 + v268 Imm(2345309990711375) -> x1 + v269 Imm(149057615) -> x1 + v270 Imm(1162961838) -> x1 + v271 Imm(1162961838) -> x1 + v272 Imm(0) -> x1 + v273 Imm(14) -> x1 + v274 Imm(15) -> x1 + v275 Imm(0) -> x1 + v276 Imm(15) -> x1 + v277 Imm(1) -> x1 + v278 BinopI { op=and, lhs=v264, rhs_imm=4294967295 } -> x3 + v279 Imm(1162961838) -> x7 + v280 ImmData(8) -> x6 + v281 Call { target_pc=1, args=[v279, v280], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v282 Binop { op=xor, lhs=v278, rhs=v281 } -> x0 + v283 Imm(0) -> x1 + v284 BinopI { op=and, lhs=v282, rhs_imm=4294967295 } -> x1 + v285 Imm(1162961838) -> x1 + v286 Imm(1935779053396950) -> x1 + v287 Imm(2933351382) -> x1 + v288 Imm(3947255605) -> x1 + v289 Imm(3947255605) -> x1 + v290 Imm(0) -> x1 + v291 Imm(15) -> x1 + v292 Imm(16) -> x1 + v293 Imm(0) -> x1 + v294 Imm(16) -> x1 + v295 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v295) block 2 start_pc=0 - v11 Extend { value=v6, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x3 - v13 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v12) - block 3 start_pc=0 - v14 BinopI { op=and, lhs=v8, rhs_imm=4294967295 } -> x13 - v15 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x7 - v16 ImmData(8) -> x6 - v17 Call { target_pc=1, args=[v15, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v18 Binop { op=xor, lhs=v14, rhs=v17 } -> x13 - v19 Imm(0) -> x0 - v20 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 - v21 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x0 - v22 BinopI { op=mul, lhs=v21, rhs_imm=1664525 } -> x0 - v23 BinopI { op=and, lhs=v22, rhs_imm=4294967295 } -> x0 - v24 BinopI { op=add, lhs=v23, rhs_imm=1013904223 } -> x0 - v25 BinopI { op=and, lhs=v24, rhs_imm=4294967295 } -> x12 - v26 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v25) - block 4 start_pc=0 - v27 BinopI { op=and, lhs=v8, rhs_imm=4294967295 } -> x0 - v28 BinopI { op=shru, lhs=v27, rhs_imm=8 } -> x1 - v29 Binop { op=xor, lhs=v27, rhs=v28 } -> x1 - v30 BinopI { op=shru, lhs=v27, rhs_imm=16 } -> x2 - v31 Binop { op=xor, lhs=v29, rhs=v30 } -> x1 - v32 BinopI { op=shru, lhs=v27, rhs_imm=24 } -> x0 - v33 Binop { op=xor, lhs=v31, rhs=v32 } -> x0 - v34 BinopI { op=and, lhs=v33, rhs_imm=255 } -> x0 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x1 - v36 Extend { value=v34, kind=I32 } -> x0 - terminator Return(v36) (exit_acc=v36) + v296 BinopI { op=and, lhs=v282, rhs_imm=4294967295 } -> x0 + v297 BinopI { op=shru, lhs=v296, rhs_imm=8 } -> x1 + v298 Binop { op=xor, lhs=v296, rhs=v297 } -> x1 + v299 BinopI { op=shru, lhs=v296, rhs_imm=16 } -> x2 + v300 Binop { op=xor, lhs=v298, rhs=v299 } -> x1 + v301 BinopI { op=shru, lhs=v296, rhs_imm=24 } -> x0 + v302 Binop { op=xor, lhs=v300, rhs=v301 } -> x0 + v303 BinopI { op=and, lhs=v302, rhs_imm=255 } -> x0 + v304 BinopI { op=shl, lhs=v303, rhs_imm=32 } -> x1 + v305 Extend { value=v303, kind=I32 } -> x0 + terminator Return(v305) (exit_acc=v305) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/designated_initializers.ssa b/tests/snapshots/ssa/designated_initializers.ssa index a4d8732c4..baa9b8933 100644 --- a/tests/snapshots/ssa/designated_initializers.ssa +++ b/tests/snapshots/ssa/designated_initializers.ssa @@ -11,7 +11,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v5 Load { addr=v4, disp=0, kind=I32 } -> x0 v6 BinopI { op=ne, lhs=v5, rhs_imm=1 } -> x1 v7 Imm(0) -> x0 - terminator Bnz { cond=v6, target=b57, fall=b1 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b62, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v8 LocalAddr(-1) -> x0 v9 BinopI { op=add, lhs=v8, rhs_imm=4 } -> x1 @@ -20,7 +20,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v12 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v13 Phi { incoming=[b57:v6, b1:v11], kind=I64 } -> x1 + v13 Phi { incoming=[b62:v6, b1:v11], kind=I64 } -> x1 v14 LoadLocal { off=-18, kind=I64 } -> x0 terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 @@ -34,7 +34,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v20 Load { addr=v19, disp=0, kind=I32 } -> x0 v21 BinopI { op=ne, lhs=v20, rhs_imm=10 } -> x1 v22 Imm(0) -> x0 - terminator Bnz { cond=v21, target=b58, fall=b5 } (exit_acc=v21) + terminator Bnz { cond=v21, target=b61, fall=b5 } (exit_acc=v21) block 5 start_pc=0 v23 LocalAddr(-2) -> x0 v24 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x1 @@ -43,7 +43,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v27 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v28 Phi { incoming=[b58:v21, b5:v26], kind=I64 } -> x1 + v28 Phi { incoming=[b61:v21, b5:v26], kind=I64 } -> x1 v29 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) block 7 start_pc=0 @@ -57,7 +57,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v35 Load { addr=v34, disp=0, kind=I32 } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x1 v37 Imm(0) -> x0 - terminator Bnz { cond=v36, target=b59, fall=b9 } (exit_acc=v36) + terminator Bnz { cond=v36, target=b60, fall=b9 } (exit_acc=v36) block 9 start_pc=0 v38 LocalAddr(-3) -> x0 v39 BinopI { op=add, lhs=v38, rhs_imm=4 } -> x1 @@ -66,7 +66,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v42 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v41) block 10 start_pc=0 - v43 Phi { incoming=[b59:v36, b9:v41], kind=I64 } -> x1 + v43 Phi { incoming=[b60:v36, b9:v41], kind=I64 } -> x1 v44 LoadLocal { off=-20, kind=I64 } -> x0 terminator Bz { cond=v43, target=b12, fall=b11 } (exit_acc=v43) block 11 start_pc=0 @@ -81,7 +81,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v51 BinopI { op=ne, lhs=v50, rhs_imm=1 } -> x0 v52 Imm(1) -> x2 v53 Imm(0) -> x1 - terminator Bnz { cond=v51, target=b60, fall=b13 } (exit_acc=v51) + terminator Bnz { cond=v51, target=b59, fall=b13 } (exit_acc=v51) block 13 start_pc=0 v54 LocalAddr(-5) -> x0 v55 BinopI { op=add, lhs=v54, rhs_imm=4 } -> x1 @@ -91,10 +91,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v59 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v58) block 14 start_pc=0 - v60 Phi { incoming=[b60:v52, b13:v58], kind=I64 } -> x2 + v60 Phi { incoming=[b59:v52, b13:v58], kind=I64 } -> x2 v61 LoadLocal { off=-22, kind=I64 } -> x0 v62 Imm(0) -> x0 - terminator Bnz { cond=v60, target=b61, fall=b15 } (exit_acc=v60) + terminator Bnz { cond=v60, target=b58, fall=b15 } (exit_acc=v60) block 15 start_pc=0 v63 LocalAddr(-5) -> x0 v64 BinopI { op=add, lhs=v63, rhs_imm=8 } -> x1 @@ -103,7 +103,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v67 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v66) block 16 start_pc=0 - v68 Phi { incoming=[b61:v60, b15:v66], kind=I64 } -> x2 + v68 Phi { incoming=[b58:v60, b15:v66], kind=I64 } -> x2 v69 LoadLocal { off=-21, kind=I64 } -> x0 terminator Bz { cond=v68, target=b18, fall=b17 } (exit_acc=v68) block 17 start_pc=0 @@ -117,7 +117,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v75 Load { addr=v74, disp=0, kind=I32 } -> x0 v76 BinopI { op=ne, lhs=v75, rhs_imm=7 } -> x1 v77 Imm(0) -> x0 - terminator Bnz { cond=v76, target=b62, fall=b19 } (exit_acc=v76) + terminator Bnz { cond=v76, target=b57, fall=b19 } (exit_acc=v76) block 19 start_pc=0 v78 LocalAddr(-6) -> x0 v79 BinopI { op=add, lhs=v78, rhs_imm=4 } -> x1 @@ -126,7 +126,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v82 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v81) block 20 start_pc=0 - v83 Phi { incoming=[b62:v76, b19:v81], kind=I64 } -> x1 + v83 Phi { incoming=[b57:v76, b19:v81], kind=I64 } -> x1 v84 LoadLocal { off=-23, kind=I64 } -> x0 terminator Bz { cond=v83, target=b22, fall=b21 } (exit_acc=v83) block 21 start_pc=0 @@ -312,17 +312,17 @@ fn ent_pc=1 n_params=0 variadic=false locals=23 v194 Imm(0) -> x0 terminator Return(v194) (exit_acc=v194) block 57 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b20) block 58 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 59 start_pc=0 - terminator Jmp(b10) - block 60 start_pc=0 terminator Jmp(b14) + block 60 start_pc=0 + terminator Jmp(b10) block 61 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 62 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/designator_override_and_braced_string.ssa b/tests/snapshots/ssa/designator_override_and_braced_string.ssa index 4f2e0550e..cdbde8404 100644 --- a/tests/snapshots/ssa/designator_override_and_braced_string.ssa +++ b/tests/snapshots/ssa/designator_override_and_braced_string.ssa @@ -11,7 +11,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v5 Load { addr=v1, disp=0, kind=I8 } -> x0 v6 BinopI { op=eq, lhs=v5, rhs_imm=97 } -> x0 v7 Imm(0) -> x1 - terminator Bz { cond=v6, target=b10, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b12, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v8 LoadLocal { off=2, kind=I64 } -> x0 v9 Imm(1) -> x0 @@ -22,7 +22,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v14 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Phi { incoming=[b10:v4, b1:v13], kind=I64 } -> x2 + v15 Phi { incoming=[b12:v4, b1:v13], kind=I64 } -> x2 v16 LoadLocal { off=-3, kind=I64 } -> x0 v17 Imm(0) -> x1 v18 Imm(0) -> x0 @@ -40,7 +40,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v26 Phi { incoming=[b11:v17, b3:v24], kind=I64 } -> x1 v27 LoadLocal { off=-2, kind=I64 } -> x0 v28 Imm(0) -> x0 - terminator Bz { cond=v26, target=b12, fall=b5 } (exit_acc=v26) + terminator Bz { cond=v26, target=b10, fall=b5 } (exit_acc=v26) block 5 start_pc=0 v29 LoadLocal { off=2, kind=I64 } -> x0 v30 Imm(3) -> x0 @@ -50,87 +50,87 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v34 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v33) block 6 start_pc=0 - v35 Phi { incoming=[b12:v26, b5:v33], kind=I64 } -> x1 + v35 Phi { incoming=[b10:v26, b5:v33], kind=I64 } -> x1 v36 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) + terminator Bz { cond=v35, target=b9, fall=b7 } (exit_acc=v35) block 7 start_pc=0 v37 Imm(0) -> x1 v38 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v37) + terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Imm(1) -> x1 - v40 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v39) - block 9 start_pc=0 - v41 Phi { incoming=[b7:v37, b8:v39], kind=I64 } -> x1 + v41 Phi { incoming=[b7:v37, b9:v39], kind=I64 } -> x1 v42 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v41) (exit_acc=v41) + block 9 start_pc=0 + v39 Imm(1) -> x1 + v40 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v39) block 10 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) block 11 start_pc=0 terminator Jmp(b4) block 12 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=12 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 ImmData(8) -> x3 - v2 Load { addr=v1, disp=0, kind=I32 } -> x0 - v3 BinopI { op=ne, lhs=v2, rhs_imm=1 } -> x12 - v4 Imm(0) -> x0 - terminator Bnz { cond=v3, target=b33, fall=b1 } (exit_acc=v3) + v1 ImmData(8) -> x0 + v2 Load { addr=v1, disp=0, kind=I32 } -> x1 + v3 BinopI { op=ne, lhs=v2, rhs_imm=1 } -> x2 + v4 Imm(0) -> x1 + terminator Bnz { cond=v3, target=b39, fall=b1 } (exit_acc=v3) block 1 start_pc=0 - v5 ImmData(8) -> x0 - v6 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x0 - v7 Load { addr=v1, disp=4, kind=I32 } -> x0 - v8 BinopI { op=ne, lhs=v7, rhs_imm=2 } -> x12 - v9 Imm(0) -> x0 + v5 ImmData(8) -> x1 + v6 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 + v7 Load { addr=v1, disp=4, kind=I32 } -> x1 + v8 BinopI { op=ne, lhs=v7, rhs_imm=2 } -> x2 + v9 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v8) block 2 start_pc=0 - v10 Phi { incoming=[b33:v3, b1:v8], kind=I64 } -> x12 - v11 LoadLocal { off=-4, kind=I64 } -> x0 + v10 Phi { incoming=[b39:v3, b1:v8], kind=I64 } -> x2 + v11 LoadLocal { off=-4, kind=I64 } -> x1 terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 v12 Imm(1) -> x0 terminator Return(v12) (exit_acc=v12) block 4 start_pc=0 - v13 ImmData(8) -> x0 - v14 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x0 - v15 Imm(0) -> x0 - v16 Load { addr=v1, disp=12, kind=I8 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=4 } -> x0 - v18 Imm(1) -> x12 - v19 Imm(0) -> x1 - terminator Bnz { cond=v17, target=b34, fall=b5 } (exit_acc=v17) + v13 ImmData(8) -> x1 + v14 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x1 + v15 Imm(0) -> x1 + v16 Load { addr=v1, disp=12, kind=I8 } -> x1 + v17 BinopI { op=ne, lhs=v16, rhs_imm=4 } -> x1 + v18 Imm(1) -> x6 + v19 Imm(0) -> x2 + terminator Bnz { cond=v17, target=b38, fall=b5 } (exit_acc=v17) block 5 start_pc=0 - v20 ImmData(8) -> x0 - v21 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x0 - v22 Imm(1) -> x0 - v23 BinopI { op=add, lhs=v1, rhs_imm=13 } -> x0 - v24 Load { addr=v1, disp=13, kind=I8 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=6 } -> x0 - v26 BinopI { op=ne, lhs=v25, rhs_imm=0 } -> x12 - v27 Imm(0) -> x0 + v20 ImmData(8) -> x1 + v21 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x1 + v22 Imm(1) -> x1 + v23 BinopI { op=add, lhs=v1, rhs_imm=13 } -> x1 + v24 Load { addr=v1, disp=13, kind=I8 } -> x1 + v25 BinopI { op=ne, lhs=v24, rhs_imm=6 } -> x1 + v26 BinopI { op=ne, lhs=v25, rhs_imm=0 } -> x6 + v27 Imm(0) -> x1 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v28 Phi { incoming=[b34:v18, b5:v26], kind=I64 } -> x12 - v29 LoadLocal { off=-6, kind=I64 } -> x0 - v30 Imm(0) -> x0 - terminator Bnz { cond=v28, target=b35, fall=b7 } (exit_acc=v28) + v28 Phi { incoming=[b38:v18, b5:v26], kind=I64 } -> x6 + v29 LoadLocal { off=-6, kind=I64 } -> x1 + v30 Imm(0) -> x1 + terminator Bnz { cond=v28, target=b37, fall=b7 } (exit_acc=v28) block 7 start_pc=0 - v31 ImmData(8) -> x0 - v32 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x0 - v33 Imm(2) -> x0 - v34 BinopI { op=add, lhs=v1, rhs_imm=14 } -> x0 + v31 ImmData(8) -> x1 + v32 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x1 + v33 Imm(2) -> x1 + v34 BinopI { op=add, lhs=v1, rhs_imm=14 } -> x1 v35 Load { addr=v1, disp=14, kind=I8 } -> x0 - v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x12 + v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x6 v37 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v36) block 8 start_pc=0 - v38 Phi { incoming=[b35:v28, b7:v36], kind=I64 } -> x12 + v38 Phi { incoming=[b37:v28, b7:v36], kind=I64 } -> x6 v39 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v38, target=b10, fall=b9 } (exit_acc=v38) block 9 start_pc=0 @@ -138,81 +138,78 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 terminator Return(v40) (exit_acc=v40) block 10 start_pc=0 v41 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v41) + terminator Jmp(b11) (exit_acc=v41) block 11 start_pc=0 - v42 Imm(3) -> x0 - terminator Return(v42) (exit_acc=v42) - block 12 start_pc=0 v43 ImmData(38) -> x0 v44 Imm(0) -> x1 v45 Load { addr=v43, disp=0, kind=I8 } -> x0 v46 BinopI { op=ne, lhs=v45, rhs_imm=104 } -> x0 - v47 Imm(1) -> x3 + v47 Imm(1) -> x2 v48 Imm(0) -> x1 - terminator Bnz { cond=v46, target=b36, fall=b13 } (exit_acc=v46) - block 13 start_pc=0 + terminator Bnz { cond=v46, target=b36, fall=b12 } (exit_acc=v46) + block 12 start_pc=0 v49 ImmData(38) -> x0 v50 Imm(4) -> x1 v51 BinopI { op=add, lhs=v49, rhs_imm=4 } -> x1 v52 Load { addr=v49, disp=4, kind=I8 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=111 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x3 + v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x2 v55 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v54) - block 14 start_pc=0 - v56 Phi { incoming=[b36:v47, b13:v54], kind=I64 } -> x3 + terminator Jmp(b13) (exit_acc=v54) + block 13 start_pc=0 + v56 Phi { incoming=[b36:v47, b12:v54], kind=I64 } -> x2 v57 LoadLocal { off=-8, kind=I64 } -> x0 v58 Imm(0) -> x0 - terminator Bnz { cond=v56, target=b37, fall=b15 } (exit_acc=v56) - block 15 start_pc=0 + terminator Bnz { cond=v56, target=b35, fall=b14 } (exit_acc=v56) + block 14 start_pc=0 v59 ImmData(38) -> x0 v60 Imm(5) -> x1 v61 BinopI { op=add, lhs=v59, rhs_imm=5 } -> x1 v62 Load { addr=v59, disp=5, kind=I8 } -> x0 - v63 BinopI { op=ne, lhs=v62, rhs_imm=0 } -> x3 + v63 BinopI { op=ne, lhs=v62, rhs_imm=0 } -> x2 v64 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v63) - block 16 start_pc=0 - v65 Phi { incoming=[b37:v56, b15:v63], kind=I64 } -> x3 + terminator Jmp(b15) (exit_acc=v63) + block 15 start_pc=0 + v65 Phi { incoming=[b35:v56, b14:v63], kind=I64 } -> x2 v66 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v65, target=b18, fall=b17 } (exit_acc=v65) - block 17 start_pc=0 + terminator Bz { cond=v65, target=b17, fall=b16 } (exit_acc=v65) + block 16 start_pc=0 v67 Imm(4) -> x0 terminator Return(v67) (exit_acc=v67) - block 18 start_pc=0 + block 17 start_pc=0 v68 Imm(0) -> x0 - v69 Imm(1) -> x3 + v69 Imm(1) -> x2 v70 Imm(0) -> x1 - terminator Jmp(b19) (exit_acc=v68) - block 19 start_pc=0 + terminator Jmp(b18) (exit_acc=v68) + block 18 start_pc=0 v71 ImmData(46) -> x0 v72 Imm(0) -> x1 v73 Load { addr=v71, disp=0, kind=I8 } -> x0 v74 BinopI { op=ne, lhs=v73, rhs_imm=104 } -> x0 - v75 BinopI { op=ne, lhs=v74, rhs_imm=0 } -> x3 + v75 BinopI { op=ne, lhs=v74, rhs_imm=0 } -> x2 v76 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v75) - block 20 start_pc=0 - v77 Phi { incoming=[b18:v69, b19:v75], kind=I64 } -> x3 + terminator Jmp(b19) (exit_acc=v75) + block 19 start_pc=0 + v77 Phi { incoming=[b17:v69, b18:v75], kind=I64 } -> x2 v78 LoadLocal { off=-10, kind=I64 } -> x0 v79 Imm(0) -> x0 - terminator Bnz { cond=v77, target=b38, fall=b21 } (exit_acc=v77) - block 21 start_pc=0 + terminator Bnz { cond=v77, target=b34, fall=b20 } (exit_acc=v77) + block 20 start_pc=0 v80 ImmData(46) -> x0 v81 Imm(2) -> x1 v82 BinopI { op=add, lhs=v80, rhs_imm=2 } -> x1 v83 Load { addr=v80, disp=2, kind=I8 } -> x0 - v84 BinopI { op=ne, lhs=v83, rhs_imm=0 } -> x3 + v84 BinopI { op=ne, lhs=v83, rhs_imm=0 } -> x2 v85 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v84) - block 22 start_pc=0 - v86 Phi { incoming=[b38:v77, b21:v84], kind=I64 } -> x3 + terminator Jmp(b21) (exit_acc=v84) + block 21 start_pc=0 + v86 Phi { incoming=[b34:v77, b20:v84], kind=I64 } -> x2 v87 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v86, target=b24, fall=b23 } (exit_acc=v86) - block 23 start_pc=0 + terminator Bz { cond=v86, target=b23, fall=b22 } (exit_acc=v86) + block 22 start_pc=0 v88 Imm(5) -> x0 terminator Return(v88) (exit_acc=v88) - block 24 start_pc=0 + block 23 start_pc=0 v89 LocalAddr(-1) -> x0 v90 ImmData(68) -> x1 v91 Mcpy { dst=v89, src=v90, size=6 } -> x0 @@ -220,68 +217,71 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v93 Imm(0) -> x1 v94 Load { addr=v92, disp=0, kind=I8 } -> x0 v95 BinopI { op=ne, lhs=v94, rhs_imm=119 } -> x0 - v96 Imm(1) -> x3 + v96 Imm(1) -> x2 v97 Imm(0) -> x1 - terminator Bnz { cond=v95, target=b39, fall=b25 } (exit_acc=v95) - block 25 start_pc=0 + terminator Bnz { cond=v95, target=b33, fall=b24 } (exit_acc=v95) + block 24 start_pc=0 v98 LocalAddr(-1) -> x0 v99 Imm(4) -> x1 v100 BinopI { op=add, lhs=v98, rhs_imm=4 } -> x1 v101 Load { addr=v98, disp=4, kind=I8 } -> x0 v102 BinopI { op=ne, lhs=v101, rhs_imm=100 } -> x0 - v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x3 + v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x2 v104 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v103) - block 26 start_pc=0 - v105 Phi { incoming=[b39:v96, b25:v103], kind=I64 } -> x3 + terminator Jmp(b25) (exit_acc=v103) + block 25 start_pc=0 + v105 Phi { incoming=[b33:v96, b24:v103], kind=I64 } -> x2 v106 LoadLocal { off=-12, kind=I64 } -> x0 v107 Imm(0) -> x0 - terminator Bnz { cond=v105, target=b40, fall=b27 } (exit_acc=v105) - block 27 start_pc=0 + terminator Bnz { cond=v105, target=b32, fall=b26 } (exit_acc=v105) + block 26 start_pc=0 v108 LocalAddr(-1) -> x0 v109 Imm(5) -> x1 v110 BinopI { op=add, lhs=v108, rhs_imm=5 } -> x1 v111 Load { addr=v108, disp=5, kind=I8 } -> x0 - v112 BinopI { op=ne, lhs=v111, rhs_imm=0 } -> x3 + v112 BinopI { op=ne, lhs=v111, rhs_imm=0 } -> x2 v113 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v112) - block 28 start_pc=0 - v114 Phi { incoming=[b40:v105, b27:v112], kind=I64 } -> x3 + terminator Jmp(b27) (exit_acc=v112) + block 27 start_pc=0 + v114 Phi { incoming=[b32:v105, b26:v112], kind=I64 } -> x2 v115 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v114, target=b30, fall=b29 } (exit_acc=v114) - block 29 start_pc=0 + terminator Bz { cond=v114, target=b29, fall=b28 } (exit_acc=v114) + block 28 start_pc=0 v116 Imm(6) -> x0 terminator Return(v116) (exit_acc=v116) - block 30 start_pc=0 + block 29 start_pc=0 v117 LocalAddr(-3) -> x0 v118 ImmData(81) -> x1 v119 Mcpy { dst=v117, src=v118, size=6 } -> x0 v120 LocalAddr(-3) -> x7 v121 Call { target_pc=0, args=[v120], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v122 BinopI { op=ne, lhs=v121, rhs_imm=0 } -> x0 - terminator Bz { cond=v122, target=b32, fall=b31 } (exit_acc=v122) - block 31 start_pc=0 + terminator Bz { cond=v122, target=b31, fall=b30 } (exit_acc=v122) + block 30 start_pc=0 v123 Imm(7) -> x0 terminator Return(v123) (exit_acc=v123) - block 32 start_pc=0 + block 31 start_pc=0 v124 Imm(0) -> x0 terminator Return(v124) (exit_acc=v124) + block 32 start_pc=0 + terminator Jmp(b27) block 33 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b25) block 34 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b21) block 35 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b15) block 36 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b13) block 37 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b8) block 38 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b6) block 39 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b2) block 40 start_pc=0 - terminator Jmp(b28) + v42 Imm(3) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/dev_t_width.ssa b/tests/snapshots/ssa/dev_t_width.ssa index 963cdb033..f558d5203 100644 --- a/tests/snapshots/ssa/dev_t_width.ssa +++ b/tests/snapshots/ssa/dev_t_width.ssa @@ -5,19 +5,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) block 3 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 4 start_pc=0 v4 Imm(2) -> x0 terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/directive_in_macro_argument.ssa b/tests/snapshots/ssa/directive_in_macro_argument.ssa index c3e3b9273..8a3924fb3 100644 --- a/tests/snapshots/ssa/directive_in_macro_argument.ssa +++ b/tests/snapshots/ssa/directive_in_macro_argument.ssa @@ -39,11 +39,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v19 Extend { value=v17, kind=I32 } -> x0 terminator Jmp(b8) (exit_acc=v19) block 8 start_pc=0 - v20 Imm(0) -> x0 + v20 Imm(0) -> x2 terminator Jmp(b9) (exit_acc=v20) block 9 start_pc=0 - v21 Extend { value=v17, kind=I32 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=7 } -> x0 + v21 Extend { value=v17, kind=I32 } -> x2 + v22 BinopI { op=ne, lhs=v19, rhs_imm=7 } -> x0 terminator Bz { cond=v22, target=b11, fall=b10 } (exit_acc=v22) block 10 start_pc=0 v23 ImmData(36) -> x7 diff --git a/tests/snapshots/ssa/dirent_readdir.ssa b/tests/snapshots/ssa/dirent_readdir.ssa index 0ff163512..7d3eec3b0 100644 --- a/tests/snapshots/ssa/dirent_readdir.ssa +++ b/tests/snapshots/ssa/dirent_readdir.ssa @@ -17,17 +17,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v7 Imm(0) -> x12 v8 Imm(0) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v7) + terminator Jmp(b7) (exit_acc=v7) block 3 start_pc=0 - v10 Phi { incoming=[b2:v7, b7:v32], kind=I64 } -> x12 - v11 Phi { incoming=[b2:v7, b7:v18], kind=I64 } -> x13 - v12 LoadLocal { off=-1, kind=I64 } -> x0 - v13 CallExt { binding_idx=2, args=[v2], fp_arg_mask=0x0 } -> x0 - v14 Imm(0) -> x1 - v15 Imm(0) -> x1 - v16 BinopI { op=ne, lhs=v13, rhs_imm=0 } -> x1 - terminator Bz { cond=v16, target=b5, fall=b4 } (exit_acc=v16) - block 4 start_pc=0 v17 Extend { value=v11, kind=I32 } -> x1 v18 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x13 v19 Imm(0) -> x1 @@ -36,45 +27,54 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v22 ImmData(10) -> x6 v23 CallExt { binding_idx=15, args=[v21, v22], fp_arg_mask=0x0 } -> x0 v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x0 - terminator Bz { cond=v24, target=b13, fall=b6 } (exit_acc=v24) + terminator Bz { cond=v24, target=b5, fall=b4 } (exit_acc=v24) + block 4 start_pc=0 + v30 Imm(1) -> x12 + v31 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v30) block 5 start_pc=0 + terminator Jmp(b6) + block 6 start_pc=0 + v32 Phi { incoming=[b5:v10, b4:v30], kind=I64 } -> x12 + terminator Jmp(b7) + block 7 start_pc=0 + v10 Phi { incoming=[b2:v7, b6:v32], kind=I64 } -> x12 + v11 Phi { incoming=[b2:v7, b6:v18], kind=I64 } -> x13 + v12 LoadLocal { off=-1, kind=I64 } -> x0 + v13 CallExt { binding_idx=2, args=[v2], fp_arg_mask=0x0 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(0) -> x1 + v16 BinopI { op=ne, lhs=v13, rhs_imm=0 } -> x1 + terminator Bnz { cond=v16, target=b3, fall=b8 } (exit_acc=v16) + block 8 start_pc=0 v25 LoadLocal { off=-1, kind=I64 } -> x0 v26 CallExt { binding_idx=3, args=[v2], fp_arg_mask=0x0 } -> x0 v27 Extend { value=v11, kind=I32 } -> x0 v28 BinopI { op=gt, lhs=v27, rhs_imm=2 } -> x1 v29 Imm(0) -> x0 - terminator Bz { cond=v28, target=b14, fall=b8 } (exit_acc=v28) - block 6 start_pc=0 - v30 Imm(1) -> x12 - v31 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v30) - block 7 start_pc=0 - v32 Phi { incoming=[b13:v10, b6:v30], kind=I64 } -> x12 - terminator Jmp(b3) - block 8 start_pc=0 + terminator Bz { cond=v28, target=b14, fall=b9 } (exit_acc=v28) + block 9 start_pc=0 v33 Extend { value=v10, kind=I32 } -> x1 v34 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v33) - block 9 start_pc=0 - v35 Phi { incoming=[b14:v28, b8:v33], kind=I64 } -> x1 - v36 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v35, target=b11, fall=b10 } (exit_acc=v35) + terminator Jmp(b10) (exit_acc=v33) block 10 start_pc=0 + v35 Phi { incoming=[b14:v28, b9:v33], kind=I64 } -> x1 + v36 LoadLocal { off=-7, kind=I64 } -> x0 + terminator Bz { cond=v35, target=b13, fall=b11 } (exit_acc=v35) + block 11 start_pc=0 v37 Imm(0) -> x1 v38 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v37) - block 11 start_pc=0 - v39 Imm(2) -> x1 - v40 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v39) block 12 start_pc=0 - v41 Phi { incoming=[b10:v37, b11:v39], kind=I64 } -> x1 + v41 Phi { incoming=[b11:v37, b13:v39], kind=I64 } -> x1 v42 LoadLocal { off=-8, kind=I64 } -> x0 terminator Return(v41) (exit_acc=v41) block 13 start_pc=0 - terminator Jmp(b7) + v39 Imm(2) -> x1 + v40 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v39) block 14 start_pc=0 - terminator Jmp(b9) + terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/divmod_preserves_rdx.ssa b/tests/snapshots/ssa/divmod_preserves_rdx.ssa index 62ad18310..37efdbef0 100644 --- a/tests/snapshots/ssa/divmod_preserves_rdx.ssa +++ b/tests/snapshots/ssa/divmod_preserves_rdx.ssa @@ -1,74 +1,74 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=12 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(100) -> x0 - v2 Imm(0) -> x1 - v3 Imm(50) -> x1 - v4 Imm(0) -> x2 - v5 Imm(25) -> x2 - v6 Imm(0) -> x6 - v7 Imm(12) -> x6 - v8 Imm(0) -> x7 - v9 LoadLocal { off=-1, kind=I32 } -> x7 - v10 Imm(7) -> x7 - v11 Binop { op=div, lhs=v1, rhs=v10 } -> x8 - v12 Imm(0) -> x9 - v13 LoadLocal { off=-2, kind=I32 } -> x9 - v14 Binop { op=div, lhs=v3, rhs=v10 } -> x9 - v15 Imm(0) -> x3 - v16 LoadLocal { off=-3, kind=I32 } -> x3 - v17 Binop { op=div, lhs=v5, rhs=v10 } -> x3 - v18 Imm(0) -> x12 - v19 LoadLocal { off=-4, kind=I32 } -> x12 - v20 Binop { op=div, lhs=v7, rhs=v10 } -> x7 - v21 Imm(0) -> x12 - v22 Extend { value=v11, kind=I32 } -> x12 - v23 Extend { value=v14, kind=I32 } -> x12 - v24 Binop { op=add, lhs=v11, rhs=v14 } -> x8 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x9 - v26 Extend { value=v24, kind=I32 } -> x9 - v27 Extend { value=v17, kind=I32 } -> x9 - v28 Binop { op=add, lhs=v24, rhs=v17 } -> x8 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x9 - v30 Extend { value=v28, kind=I32 } -> x9 - v31 Extend { value=v20, kind=I32 } -> x9 - v32 Binop { op=add, lhs=v28, rhs=v20 } -> x7 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x8 - v34 Extend { value=v32, kind=I32 } -> x8 - v35 Binop { op=add, lhs=v32, rhs=v1 } -> x0 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x7 - v37 Extend { value=v35, kind=I32 } -> x7 - v38 Binop { op=add, lhs=v35, rhs=v3 } -> x0 - v39 BinopI { op=shl, lhs=v38, rhs_imm=32 } -> x1 - v40 Extend { value=v38, kind=I32 } -> x1 - v41 Binop { op=add, lhs=v38, rhs=v5 } -> x0 - v42 BinopI { op=shl, lhs=v41, rhs_imm=32 } -> x1 - v43 Extend { value=v41, kind=I32 } -> x1 - v44 Binop { op=add, lhs=v41, rhs=v7 } -> x0 - v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x1 - v46 Extend { value=v44, kind=I32 } -> x3 + v2 Imm(0) -> x0 + v3 Imm(50) -> x0 + v4 Imm(0) -> x0 + v5 Imm(25) -> x0 + v6 Imm(0) -> x0 + v7 Imm(12) -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I32 } -> x0 + v10 Imm(7) -> x0 + v11 Imm(14) -> x0 + v12 Imm(0) -> x0 + v13 LoadLocal { off=-2, kind=I32 } -> x0 + v14 Imm(7) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-3, kind=I32 } -> x0 + v17 Imm(3) -> x0 + v18 Imm(0) -> x0 + v19 LoadLocal { off=-4, kind=I32 } -> x0 + v20 Imm(1) -> x0 + v21 Imm(0) -> x0 + v22 Imm(14) -> x0 + v23 Imm(7) -> x0 + v24 Imm(21) -> x0 + v25 Imm(90194313216) -> x0 + v26 Imm(21) -> x0 + v27 Imm(3) -> x0 + v28 Imm(24) -> x0 + v29 Imm(103079215104) -> x0 + v30 Imm(24) -> x0 + v31 Imm(1) -> x0 + v32 Imm(25) -> x0 + v33 Imm(107374182400) -> x0 + v34 Imm(25) -> x0 + v35 Imm(125) -> x0 + v36 Imm(536870912000) -> x0 + v37 Imm(125) -> x0 + v38 Imm(175) -> x0 + v39 Imm(751619276800) -> x0 + v40 Imm(175) -> x0 + v41 Imm(200) -> x0 + v42 Imm(858993459200) -> x0 + v43 Imm(200) -> x0 + v44 Imm(212) -> x0 + v45 Imm(910533066752) -> x0 + v46 Imm(212) -> x6 v47 Imm(0) -> x0 v48 ImmData(36) -> x7 v49 LoadLocal { off=-9, kind=I32 } -> x0 v50 CallExt { binding_idx=0, args=[v48, v46], fp_arg_mask=0x0 } -> x0 v51 LoadLocal { off=-9, kind=I32 } -> x0 - v52 BinopI { op=eq, lhs=v46, rhs_imm=212 } -> x0 - terminator Bz { cond=v52, target=b2, fall=b1 } (exit_acc=v52) + v52 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v52) block 1 start_pc=0 v53 Imm(0) -> x1 v54 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v53) + terminator Jmp(b2) (exit_acc=v53) block 2 start_pc=0 - v55 Imm(1) -> x1 - v56 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v55) - block 3 start_pc=0 - v57 Phi { incoming=[b1:v53, b2:v55], kind=I64 } -> x1 + v57 Phi { incoming=[b1:v53, b3:v55], kind=I64 } -> x1 v58 LoadLocal { off=-12, kind=I64 } -> x0 terminator Return(v57) (exit_acc=v57) + block 3 start_pc=0 + v55 Imm(1) -> x1 + v56 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/dlopen_atoi.ssa b/tests/snapshots/ssa/dlopen_atoi.ssa index b01389618..b20443d94 100644 --- a/tests/snapshots/ssa/dlopen_atoi.ssa +++ b/tests/snapshots/ssa/dlopen_atoi.ssa @@ -17,10 +17,10 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 block 2 start_pc=0 v8 LoadLocal { off=-1, kind=I64 } -> x0 v9 ImmData(48) -> x6 - v10 CallExt { binding_idx=222, args=[v3, v9], fp_arg_mask=0x0 } -> x12 - v11 Imm(0) -> x0 - v12 LoadLocal { off=-2, kind=I64 } -> x0 - v13 BinopI { op=eq, lhs=v10, rhs_imm=0 } -> x0 + v10 CallExt { binding_idx=222, args=[v3, v9], fp_arg_mask=0x0 } -> x0 + v11 Imm(0) -> x1 + v12 LoadLocal { off=-2, kind=I64 } -> x1 + v13 BinopI { op=eq, lhs=v10, rhs_imm=0 } -> x1 terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 v14 LoadLocal { off=-1, kind=I64 } -> x0 @@ -29,7 +29,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 terminator Return(v16) (exit_acc=v16) block 4 start_pc=0 v17 ImmData(53) -> x7 - v18 LoadLocal { off=-2, kind=I64 } -> x0 + v18 LoadLocal { off=-2, kind=I64 } -> x1 v19 CallIndirect { target=v10, args=[v17], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x1 v21 Extend { value=v19, kind=I32 } -> x12 diff --git a/tests/snapshots/ssa/do_while.ssa b/tests/snapshots/ssa/do_while.ssa index 5ed263d4c..8a83ce002 100644 --- a/tests/snapshots/ssa/do_while.ssa +++ b/tests/snapshots/ssa/do_while.ssa @@ -8,7 +8,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 v2 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b4:v7], kind=I64 } -> x1 + v3 Phi { incoming=[b0:v1, b3:v7], kind=I64 } -> x1 v4 Extend { value=v3, kind=I32 } -> x0 v5 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x1 @@ -18,12 +18,12 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 2 start_pc=0 v9 LoadLocal { off=-1, kind=I32 } -> x0 v10 BinopI { op=lt, lhs=v7, rhs_imm=5 } -> x0 - terminator Bnz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 + terminator Jmp(b1) + block 4 start_pc=0 v11 LoadLocal { off=-1, kind=I32 } -> x0 terminator Return(v7) (exit_acc=v7) - block 4 start_pc=0 - terminator Jmp(b1) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/do_while_zero_returns.ssa b/tests/snapshots/ssa/do_while_zero_returns.ssa index e9b97bcb6..88f907369 100644 --- a/tests/snapshots/ssa/do_while_zero_returns.ssa +++ b/tests/snapshots/ssa/do_while_zero_returns.ssa @@ -10,25 +10,25 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 block 1 start_pc=0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v4, target=b5, fall=b4 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b2 } (exit_acc=v4) block 2 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v13) - block 3 start_pc=0 - v14 Imm(0) -> x0 - terminator Return(v14) (exit_acc=v14) - block 4 start_pc=0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x0 v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 v8 Extend { value=v6, kind=I32 } -> x0 terminator Return(v8) (exit_acc=v8) - block 5 start_pc=0 + block 3 start_pc=0 v9 LoadLocal { off=2, kind=I32 } -> x0 v10 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x1 v12 Extend { value=v10, kind=I32 } -> x0 terminator Return(v12) (exit_acc=v12) + block 4 start_pc=0 + v13 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v13) + block 5 start_pc=0 + v14 Imm(0) -> x0 + terminator Return(v14) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=classify fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -41,34 +41,34 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 block 1 start_pc=0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v4, target=b6, fall=b4 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b2 } (exit_acc=v4) block 2 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 3 start_pc=0 - v6 Imm(0) -> x0 - terminator Return(v6) (exit_acc=v6) - block 4 start_pc=0 v7 Imm(0) -> x0 terminator Return(v7) (exit_acc=v7) - block 5 start_pc=0 - terminator Jmp(b2) - block 6 start_pc=0 + block 3 start_pc=0 v8 LoadLocal { off=2, kind=I32 } -> x0 v9 BinopI { op=gt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v9, target=b8, fall=b7 } (exit_acc=v9) - block 7 start_pc=0 + terminator Bz { cond=v9, target=b6, fall=b4 } (exit_acc=v9) + block 4 start_pc=0 v10 Imm(1) -> x1 v11 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v10) - block 8 start_pc=0 + terminator Jmp(b5) (exit_acc=v10) + block 5 start_pc=0 + v14 Phi { incoming=[b4:v10, b6:v12], kind=I64 } -> x1 + v15 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Return(v14) (exit_acc=v14) + block 6 start_pc=0 v12 Imm(-1) -> x1 v13 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v12) + terminator Jmp(b5) (exit_acc=v12) + block 7 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v5) + block 8 start_pc=0 + v6 Imm(0) -> x0 + terminator Return(v6) (exit_acc=v6) block 9 start_pc=0 - v14 Phi { incoming=[b7:v10, b8:v12], kind=I64 } -> x1 - v15 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Return(v14) (exit_acc=v14) + terminator Jmp(b7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/duff_switch_into_loop.ssa b/tests/snapshots/ssa/duff_switch_into_loop.ssa index e6c924625..94346fa8e 100644 --- a/tests/snapshots/ssa/duff_switch_into_loop.ssa +++ b/tests/snapshots/ssa/duff_switch_into_loop.ssa @@ -25,95 +25,95 @@ fn ent_pc=0 n_params=3 variadic=false locals=1 v19 Binop { op=add, lhs=v5, rhs=v18 } -> x1 v20 BinopI { op=and, lhs=v19, rhs_imm=7 } -> x1 v21 Binop { op=sub, lhs=v20, rhs=v18 } -> x0 - v22 BinopI { op=lt, lhs=v21, rhs_imm=4 } -> x1 - terminator Bnz { cond=v22, target=b10, fall=b11 } (exit_acc=v22) + v22 BinopI { op=ult, lhs=v21, rhs_imm=8 } -> x1 + terminator Bz { cond=v22, target=b1, fall=b10 } (exit_acc=v22) block 1 start_pc=0 v23 Imm(0) -> x0 terminator Return(v23) (exit_acc=v23) block 2 start_pc=0 - terminator Jmp(b25) + terminator Jmp(b12) block 3 start_pc=0 - v24 Phi { incoming=[b34:v15, b25:v115], kind=I64 } -> x6 - v25 Phi { incoming=[b34:v1, b25:v119], kind=I64 } -> x7 - v26 Phi { incoming=[b34:v3, b25:v122], kind=I64 } -> x8 + v24 Phi { incoming=[b21:v15, b12:v101], kind=I64 } -> x6 + v25 Phi { incoming=[b21:v1, b12:v105], kind=I64 } -> x7 + v26 Phi { incoming=[b21:v3, b12:v108], kind=I64 } -> x8 v27 LoadLocal { off=2, kind=I64 } -> x0 - v28 BinopI { op=add, lhs=v25, rhs_imm=1 } -> x1 - v29 Imm(0) -> x0 - v30 LoadLocal { off=3, kind=I64 } -> x0 - v31 BinopI { op=add, lhs=v26, rhs_imm=1 } -> x2 - v32 Imm(0) -> x0 - v33 Load { addr=v26, disp=0, kind=I8 } -> x0 + v28 BinopI { op=add, lhs=v25, rhs_imm=1 } -> x0 + v29 Imm(0) -> x1 + v30 LoadLocal { off=3, kind=I64 } -> x1 + v31 BinopI { op=add, lhs=v26, rhs_imm=1 } -> x1 + v32 Imm(0) -> x2 + v33 Load { addr=v26, disp=0, kind=I8 } -> x2 v34 Store { addr=v25, disp=0, value=v33, kind=I8 } -> - terminator Jmp(b4) (exit_acc=v34) block 4 start_pc=0 - v35 Phi { incoming=[b3:v24, b33:v15], kind=I64 } -> x6 - v36 Phi { incoming=[b3:v28, b33:v1], kind=I64 } -> x1 - v37 Phi { incoming=[b3:v31, b33:v3], kind=I64 } -> x2 + v35 Phi { incoming=[b20:v15, b3:v24], kind=I64 } -> x6 + v36 Phi { incoming=[b20:v1, b3:v28], kind=I64 } -> x7 + v37 Phi { incoming=[b20:v3, b3:v31], kind=I64 } -> x8 v38 LoadLocal { off=2, kind=I64 } -> x0 - v39 BinopI { op=add, lhs=v36, rhs_imm=1 } -> x7 - v40 Imm(0) -> x0 - v41 LoadLocal { off=3, kind=I64 } -> x0 - v42 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x8 - v43 Imm(0) -> x0 - v44 Load { addr=v37, disp=0, kind=I8 } -> x0 + v39 BinopI { op=add, lhs=v36, rhs_imm=1 } -> x0 + v40 Imm(0) -> x1 + v41 LoadLocal { off=3, kind=I64 } -> x1 + v42 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x1 + v43 Imm(0) -> x2 + v44 Load { addr=v37, disp=0, kind=I8 } -> x2 v45 Store { addr=v36, disp=0, value=v44, kind=I8 } -> - terminator Jmp(b5) (exit_acc=v45) block 5 start_pc=0 - v46 Phi { incoming=[b4:v35, b32:v15], kind=I64 } -> x6 - v47 Phi { incoming=[b4:v39, b32:v1], kind=I64 } -> x7 - v48 Phi { incoming=[b4:v42, b32:v3], kind=I64 } -> x8 + v46 Phi { incoming=[b19:v15, b4:v35], kind=I64 } -> x6 + v47 Phi { incoming=[b19:v1, b4:v39], kind=I64 } -> x7 + v48 Phi { incoming=[b19:v3, b4:v42], kind=I64 } -> x8 v49 LoadLocal { off=2, kind=I64 } -> x0 - v50 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x1 - v51 Imm(0) -> x0 - v52 LoadLocal { off=3, kind=I64 } -> x0 - v53 BinopI { op=add, lhs=v48, rhs_imm=1 } -> x2 - v54 Imm(0) -> x0 - v55 Load { addr=v48, disp=0, kind=I8 } -> x0 + v50 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x0 + v51 Imm(0) -> x1 + v52 LoadLocal { off=3, kind=I64 } -> x1 + v53 BinopI { op=add, lhs=v48, rhs_imm=1 } -> x1 + v54 Imm(0) -> x2 + v55 Load { addr=v48, disp=0, kind=I8 } -> x2 v56 Store { addr=v47, disp=0, value=v55, kind=I8 } -> - terminator Jmp(b6) (exit_acc=v56) block 6 start_pc=0 - v57 Phi { incoming=[b5:v46, b31:v15], kind=I64 } -> x6 - v58 Phi { incoming=[b5:v50, b31:v1], kind=I64 } -> x1 - v59 Phi { incoming=[b5:v53, b31:v3], kind=I64 } -> x2 + v57 Phi { incoming=[b18:v15, b5:v46], kind=I64 } -> x6 + v58 Phi { incoming=[b18:v1, b5:v50], kind=I64 } -> x7 + v59 Phi { incoming=[b18:v3, b5:v53], kind=I64 } -> x8 v60 LoadLocal { off=2, kind=I64 } -> x0 - v61 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x7 - v62 Imm(0) -> x0 - v63 LoadLocal { off=3, kind=I64 } -> x0 - v64 BinopI { op=add, lhs=v59, rhs_imm=1 } -> x8 - v65 Imm(0) -> x0 - v66 Load { addr=v59, disp=0, kind=I8 } -> x0 + v61 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x0 + v62 Imm(0) -> x1 + v63 LoadLocal { off=3, kind=I64 } -> x1 + v64 BinopI { op=add, lhs=v59, rhs_imm=1 } -> x1 + v65 Imm(0) -> x2 + v66 Load { addr=v59, disp=0, kind=I8 } -> x2 v67 Store { addr=v58, disp=0, value=v66, kind=I8 } -> - terminator Jmp(b7) (exit_acc=v67) block 7 start_pc=0 - v68 Phi { incoming=[b6:v57, b30:v15], kind=I64 } -> x6 - v69 Phi { incoming=[b6:v61, b30:v1], kind=I64 } -> x7 - v70 Phi { incoming=[b6:v64, b30:v3], kind=I64 } -> x8 + v68 Phi { incoming=[b17:v15, b6:v57], kind=I64 } -> x6 + v69 Phi { incoming=[b17:v1, b6:v61], kind=I64 } -> x7 + v70 Phi { incoming=[b17:v3, b6:v64], kind=I64 } -> x8 v71 LoadLocal { off=2, kind=I64 } -> x0 - v72 BinopI { op=add, lhs=v69, rhs_imm=1 } -> x1 - v73 Imm(0) -> x0 - v74 LoadLocal { off=3, kind=I64 } -> x0 - v75 BinopI { op=add, lhs=v70, rhs_imm=1 } -> x2 - v76 Imm(0) -> x0 - v77 Load { addr=v70, disp=0, kind=I8 } -> x0 + v72 BinopI { op=add, lhs=v69, rhs_imm=1 } -> x0 + v73 Imm(0) -> x1 + v74 LoadLocal { off=3, kind=I64 } -> x1 + v75 BinopI { op=add, lhs=v70, rhs_imm=1 } -> x1 + v76 Imm(0) -> x2 + v77 Load { addr=v70, disp=0, kind=I8 } -> x2 v78 Store { addr=v69, disp=0, value=v77, kind=I8 } -> - terminator Jmp(b8) (exit_acc=v78) block 8 start_pc=0 - v79 Phi { incoming=[b7:v68, b29:v15], kind=I64 } -> x6 - v80 Phi { incoming=[b7:v72, b29:v1], kind=I64 } -> x1 - v81 Phi { incoming=[b7:v75, b29:v3], kind=I64 } -> x2 + v79 Phi { incoming=[b16:v15, b7:v68], kind=I64 } -> x6 + v80 Phi { incoming=[b16:v1, b7:v72], kind=I64 } -> x7 + v81 Phi { incoming=[b16:v3, b7:v75], kind=I64 } -> x8 v82 LoadLocal { off=2, kind=I64 } -> x0 - v83 BinopI { op=add, lhs=v80, rhs_imm=1 } -> x7 - v84 Imm(0) -> x0 - v85 LoadLocal { off=3, kind=I64 } -> x0 - v86 BinopI { op=add, lhs=v81, rhs_imm=1 } -> x8 - v87 Imm(0) -> x0 - v88 Load { addr=v81, disp=0, kind=I8 } -> x0 + v83 BinopI { op=add, lhs=v80, rhs_imm=1 } -> x0 + v84 Imm(0) -> x1 + v85 LoadLocal { off=3, kind=I64 } -> x1 + v86 BinopI { op=add, lhs=v81, rhs_imm=1 } -> x1 + v87 Imm(0) -> x2 + v88 Load { addr=v81, disp=0, kind=I8 } -> x2 v89 Store { addr=v80, disp=0, value=v88, kind=I8 } -> - terminator Jmp(b9) (exit_acc=v89) block 9 start_pc=0 - v90 Phi { incoming=[b8:v79, b28:v15], kind=I64 } -> x6 - v91 Phi { incoming=[b8:v83, b28:v1], kind=I64 } -> x7 - v92 Phi { incoming=[b8:v86, b28:v3], kind=I64 } -> x8 + v90 Phi { incoming=[b15:v15, b8:v79], kind=I64 } -> x6 + v91 Phi { incoming=[b15:v1, b8:v83], kind=I64 } -> x7 + v92 Phi { incoming=[b15:v3, b8:v86], kind=I64 } -> x8 v93 LoadLocal { off=2, kind=I64 } -> x0 v94 BinopI { op=add, lhs=v91, rhs_imm=1 } -> x1 v95 Imm(0) -> x0 @@ -122,89 +122,49 @@ fn ent_pc=0 n_params=3 variadic=false locals=1 v98 Imm(0) -> x0 v99 Load { addr=v92, disp=0, kind=I8 } -> x0 v100 Store { addr=v91, disp=0, value=v99, kind=I8 } -> - - terminator Jmp(b26) (exit_acc=v100) + terminator Jmp(b13) (exit_acc=v100) block 10 start_pc=0 - v101 BinopI { op=lt, lhs=v21, rhs_imm=2 } -> x1 - terminator Bnz { cond=v101, target=b12, fall=b13 } (exit_acc=v101) + terminator JumpTable { idx=v21, table=0 } [b2, b15, b16, b17, b18, b19, b20, b21] (exit_acc=v21) block 11 start_pc=0 - v102 BinopI { op=lt, lhs=v21, rhs_imm=6 } -> x1 - terminator Bnz { cond=v102, target=b18, fall=b19 } (exit_acc=v102) + terminator Jmp(b2) block 12 start_pc=0 - v103 BinopI { op=lt, lhs=v21, rhs_imm=1 } -> x1 - terminator Bnz { cond=v103, target=b14, fall=b15 } (exit_acc=v103) + v101 Phi { incoming=[b2:v15, b22:v113], kind=I64 } -> x6 + v102 Phi { incoming=[b2:v1, b22:v94], kind=I64 } -> x1 + v103 Phi { incoming=[b2:v3, b22:v97], kind=I64 } -> x2 + v104 LoadLocal { off=2, kind=I64 } -> x0 + v105 BinopI { op=add, lhs=v102, rhs_imm=1 } -> x7 + v106 Imm(0) -> x0 + v107 LoadLocal { off=3, kind=I64 } -> x0 + v108 BinopI { op=add, lhs=v103, rhs_imm=1 } -> x8 + v109 Imm(0) -> x0 + v110 Load { addr=v103, disp=0, kind=I8 } -> x0 + v111 Store { addr=v102, disp=0, value=v110, kind=I8 } -> - + terminator Jmp(b3) (exit_acc=v111) block 13 start_pc=0 - v104 BinopI { op=lt, lhs=v21, rhs_imm=3 } -> x1 - terminator Bnz { cond=v104, target=b16, fall=b17 } (exit_acc=v104) + v112 Extend { value=v90, kind=I32 } -> x0 + v113 BinopI { op=add, lhs=v90, rhs_imm=-1 } -> x6 + v114 Imm(0) -> x0 + v115 Extend { value=v113, kind=I32 } -> x0 + v116 BinopI { op=gt, lhs=v115, rhs_imm=0 } -> x0 + terminator Bnz { cond=v116, target=b22, fall=b1 } (exit_acc=v116) block 14 start_pc=0 - v105 BinopI { op=eq, lhs=v21, rhs_imm=0 } -> x0 - terminator Bnz { cond=v105, target=b2, fall=b1 } (exit_acc=v105) - block 15 start_pc=0 - v106 BinopI { op=eq, lhs=v21, rhs_imm=1 } -> x0 - terminator Bnz { cond=v106, target=b28, fall=b1 } (exit_acc=v106) - block 16 start_pc=0 - v107 BinopI { op=eq, lhs=v21, rhs_imm=2 } -> x0 - terminator Bnz { cond=v107, target=b29, fall=b1 } (exit_acc=v107) - block 17 start_pc=0 - v108 BinopI { op=eq, lhs=v21, rhs_imm=3 } -> x0 - terminator Bnz { cond=v108, target=b30, fall=b1 } (exit_acc=v108) - block 18 start_pc=0 - v109 BinopI { op=lt, lhs=v21, rhs_imm=5 } -> x1 - terminator Bnz { cond=v109, target=b20, fall=b21 } (exit_acc=v109) - block 19 start_pc=0 - v110 BinopI { op=lt, lhs=v21, rhs_imm=7 } -> x1 - terminator Bnz { cond=v110, target=b22, fall=b23 } (exit_acc=v110) - block 20 start_pc=0 - v111 BinopI { op=eq, lhs=v21, rhs_imm=4 } -> x0 - terminator Bnz { cond=v111, target=b31, fall=b1 } (exit_acc=v111) - block 21 start_pc=0 - v112 BinopI { op=eq, lhs=v21, rhs_imm=5 } -> x0 - terminator Bnz { cond=v112, target=b32, fall=b1 } (exit_acc=v112) - block 22 start_pc=0 - v113 BinopI { op=eq, lhs=v21, rhs_imm=6 } -> x0 - terminator Bnz { cond=v113, target=b33, fall=b1 } (exit_acc=v113) - block 23 start_pc=0 - v114 BinopI { op=eq, lhs=v21, rhs_imm=7 } -> x0 - terminator Bnz { cond=v114, target=b34, fall=b1 } (exit_acc=v114) - block 24 start_pc=0 - terminator Jmp(b2) - block 25 start_pc=0 - v115 Phi { incoming=[b35:v127, b2:v15], kind=I64 } -> x6 - v116 Phi { incoming=[b35:v94, b2:v1], kind=I64 } -> x1 - v117 Phi { incoming=[b35:v97, b2:v3], kind=I64 } -> x2 - v118 LoadLocal { off=2, kind=I64 } -> x0 - v119 BinopI { op=add, lhs=v116, rhs_imm=1 } -> x7 - v120 Imm(0) -> x0 - v121 LoadLocal { off=3, kind=I64 } -> x0 - v122 BinopI { op=add, lhs=v117, rhs_imm=1 } -> x8 - v123 Imm(0) -> x0 - v124 Load { addr=v117, disp=0, kind=I8 } -> x0 - v125 Store { addr=v116, disp=0, value=v124, kind=I8 } -> - - terminator Jmp(b3) (exit_acc=v125) - block 26 start_pc=0 - v126 Extend { value=v90, kind=I32 } -> x0 - v127 BinopI { op=add, lhs=v90, rhs_imm=-1 } -> x6 - v128 Imm(0) -> x0 - v129 Extend { value=v127, kind=I32 } -> x0 - v130 BinopI { op=gt, lhs=v129, rhs_imm=0 } -> x0 - terminator Bnz { cond=v130, target=b35, fall=b27 } (exit_acc=v130) - block 27 start_pc=0 terminator Jmp(b1) - block 28 start_pc=0 + block 15 start_pc=0 terminator Jmp(b9) - block 29 start_pc=0 + block 16 start_pc=0 terminator Jmp(b8) - block 30 start_pc=0 + block 17 start_pc=0 terminator Jmp(b7) - block 31 start_pc=0 + block 18 start_pc=0 terminator Jmp(b6) - block 32 start_pc=0 + block 19 start_pc=0 terminator Jmp(b5) - block 33 start_pc=0 + block 20 start_pc=0 terminator Jmp(b4) - block 34 start_pc=0 + block 21 start_pc=0 terminator Jmp(b3) - block 35 start_pc=0 - terminator Jmp(b25) + block 22 start_pc=0 + terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=14 @@ -213,30 +173,30 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=39 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) - block 3 start_pc=0 - v9 LocalAddr(-5) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 Binop { op=add, lhs=v9, rhs=v10 } -> x0 - v12 BinopI { op=shl, lhs=v10, rhs_imm=56 } -> x6 - v13 Extend { value=v10, kind=I8 } -> x6 + v9 LocalAddr(-5) -> x2 + v10 Extend { value=v3, kind=I32 } -> x6 + v11 Binop { op=add, lhs=v9, rhs=v4 } -> x2 + v12 BinopI { op=shl, lhs=v4, rhs_imm=56 } -> x7 + v13 Extend { value=v10, kind=I8 } -> x7 v14 Store { addr=v11, disp=0, value=v10, kind=I8 } -> - - v15 LocalAddr(-10) -> x0 - v16 Extend { value=v3, kind=I32 } -> x2 - v17 Binop { op=add, lhs=v15, rhs=v16 } -> x0 - v18 Imm(0) -> x2 + v15 LocalAddr(-10) -> x2 + v16 Extend { value=v3, kind=I32 } -> x6 + v17 Binop { op=add, lhs=v15, rhs=v4 } -> x2 + v18 Imm(0) -> x6 v19 Store { addr=v17, disp=0, value=v18, kind=I8 } -> - terminator Jmp(b2) (exit_acc=v19) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=39 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) block 4 start_pc=0 v20 LocalAddr(-10) -> x7 v21 LocalAddr(-5) -> x6 @@ -244,28 +204,28 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v23 Call { target_pc=0, args=[v20, v21, v22], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 v24 Imm(0) -> x1 v25 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v24) + terminator Jmp(b7) (exit_acc=v24) block 5 start_pc=0 - v26 Phi { incoming=[b4:v24, b6:v30], kind=I64 } -> x1 - v27 Extend { value=v26, kind=I32 } -> x0 - v28 BinopI { op=lt, lhs=v27, rhs_imm=39 } -> x0 - terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) + v32 LocalAddr(-10) -> x2 + v33 Extend { value=v26, kind=I32 } -> x6 + v34 Binop { op=add, lhs=v32, rhs=v27 } -> x2 + v35 Load { addr=v34, disp=0, kind=I8 } -> x2 + v36 LocalAddr(-5) -> x6 + v37 Extend { value=v26, kind=I32 } -> x7 + v38 Binop { op=add, lhs=v36, rhs=v27 } -> x6 + v39 Load { addr=v38, disp=0, kind=I8 } -> x6 + v40 Binop { op=ne, lhs=v35, rhs=v39 } -> x2 + terminator Bnz { cond=v40, target=b9, fall=b6 } (exit_acc=v40) block 6 start_pc=0 - v29 Extend { value=v26, kind=I32 } -> x0 - v30 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x1 + v29 Extend { value=v26, kind=I32 } -> x1 + v30 BinopI { op=add, lhs=v27, rhs_imm=1 } -> x1 v31 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v30) + terminator Jmp(b7) (exit_acc=v30) block 7 start_pc=0 - v32 LocalAddr(-10) -> x0 - v33 Extend { value=v26, kind=I32 } -> x2 - v34 Binop { op=add, lhs=v32, rhs=v33 } -> x0 - v35 Load { addr=v34, disp=0, kind=I8 } -> x0 - v36 LocalAddr(-5) -> x2 - v37 Extend { value=v26, kind=I32 } -> x6 - v38 Binop { op=add, lhs=v36, rhs=v37 } -> x2 - v39 Load { addr=v38, disp=0, kind=I8 } -> x2 - v40 Binop { op=ne, lhs=v35, rhs=v39 } -> x0 - terminator Bz { cond=v40, target=b10, fall=b9 } (exit_acc=v40) + v26 Phi { incoming=[b4:v24, b6:v30], kind=I64 } -> x1 + v27 Extend { value=v26, kind=I32 } -> x0 + v28 BinopI { op=lt, lhs=v27, rhs_imm=39 } -> x2 + terminator Bnz { cond=v28, target=b5, fall=b8 } (exit_acc=v28) block 8 start_pc=0 v41 Imm(0) -> x0 terminator Return(v41) (exit_acc=v41) diff --git a/tests/snapshots/ssa/empty_macro_arg_and_string_rows.ssa b/tests/snapshots/ssa/empty_macro_arg_and_string_rows.ssa index e817fa370..bf28cb031 100644 --- a/tests/snapshots/ssa/empty_macro_arg_and_string_rows.ssa +++ b/tests/snapshots/ssa/empty_macro_arg_and_string_rows.ssa @@ -5,24 +5,21 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(16) -> x0 - v2 Imm(4) -> x1 - v3 Imm(0) -> x1 - v4 Binop { op=add, lhs=v1, rhs=v3 } -> x0 - v5 BinopI { op=shr, lhs=v4, rhs_imm=2 } -> x0 - v6 BinopI { op=ne, lhs=v5, rhs_imm=4 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(4) -> x0 + v3 Imm(0) -> x0 + v4 Imm(16) -> x0 + v5 Imm(4) -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 ImmData(8) -> x0 v9 Imm(0) -> x1 v10 Load { addr=v8, disp=0, kind=I32 } -> x0 v11 BinopI { op=ne, lhs=v10, rhs_imm=1 } -> x0 v12 Imm(1) -> x2 v13 Imm(0) -> x1 - terminator Bnz { cond=v11, target=b19, fall=b3 } (exit_acc=v11) - block 3 start_pc=0 + terminator Bnz { cond=v11, target=b22, fall=b2 } (exit_acc=v11) + block 2 start_pc=0 v14 ImmData(8) -> x0 v15 Imm(4) -> x1 v16 BinopI { op=add, lhs=v14, rhs_imm=4 } -> x1 @@ -30,14 +27,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v18 BinopI { op=ne, lhs=v17, rhs_imm=23 } -> x0 v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x2 v20 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v19) - block 4 start_pc=0 - v21 Phi { incoming=[b19:v12, b3:v19], kind=I64 } -> x2 + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v21 Phi { incoming=[b22:v12, b2:v19], kind=I64 } -> x2 v22 LoadLocal { off=-3, kind=I64 } -> x0 v23 Imm(1) -> x1 v24 Imm(0) -> x0 - terminator Bnz { cond=v21, target=b20, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bnz { cond=v21, target=b21, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v25 ImmData(8) -> x0 v26 Imm(8) -> x1 v27 BinopI { op=add, lhs=v25, rhs_imm=8 } -> x1 @@ -45,36 +42,36 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v29 BinopI { op=ne, lhs=v28, rhs_imm=4 } -> x0 v30 BinopI { op=ne, lhs=v29, rhs_imm=0 } -> x1 v31 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v30) - block 6 start_pc=0 - v32 Phi { incoming=[b20:v23, b5:v30], kind=I64 } -> x1 + terminator Jmp(b5) (exit_acc=v30) + block 5 start_pc=0 + v32 Phi { incoming=[b21:v23, b4:v30], kind=I64 } -> x1 v33 LoadLocal { off=-2, kind=I64 } -> x0 v34 Imm(0) -> x0 - terminator Bnz { cond=v32, target=b21, fall=b7 } (exit_acc=v32) - block 7 start_pc=0 + terminator Bnz { cond=v32, target=b20, fall=b6 } (exit_acc=v32) + block 6 start_pc=0 v35 ImmData(8) -> x0 v36 Imm(12) -> x1 v37 BinopI { op=add, lhs=v35, rhs_imm=12 } -> x1 v38 Load { addr=v35, disp=12, kind=I32 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=5 } -> x1 v40 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v39) - block 8 start_pc=0 - v41 Phi { incoming=[b21:v32, b7:v39], kind=I64 } -> x1 + terminator Jmp(b7) (exit_acc=v39) + block 7 start_pc=0 + v41 Phi { incoming=[b20:v32, b6:v39], kind=I64 } -> x1 v42 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) - block 9 start_pc=0 + terminator Bz { cond=v41, target=b9, fall=b8 } (exit_acc=v41) + block 8 start_pc=0 v43 Imm(2) -> x0 terminator Return(v43) (exit_acc=v43) - block 10 start_pc=0 + block 9 start_pc=0 v44 ImmData(24) -> x0 v45 Imm(0) -> x1 v46 Load { addr=v44, disp=0, kind=I8 } -> x0 v47 BinopI { op=ne, lhs=v46, rhs_imm=104 } -> x0 v48 Imm(1) -> x2 v49 Imm(0) -> x1 - terminator Bnz { cond=v47, target=b22, fall=b11 } (exit_acc=v47) - block 11 start_pc=0 + terminator Bnz { cond=v47, target=b19, fall=b10 } (exit_acc=v47) + block 10 start_pc=0 v50 ImmData(24) -> x0 v51 Imm(0) -> x1 v52 Imm(4) -> x1 @@ -83,13 +80,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v55 BinopI { op=ne, lhs=v54, rhs_imm=111 } -> x0 v56 BinopI { op=ne, lhs=v55, rhs_imm=0 } -> x2 v57 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v56) - block 12 start_pc=0 - v58 Phi { incoming=[b22:v48, b11:v56], kind=I64 } -> x2 + terminator Jmp(b11) (exit_acc=v56) + block 11 start_pc=0 + v58 Phi { incoming=[b19:v48, b10:v56], kind=I64 } -> x2 v59 LoadLocal { off=-5, kind=I64 } -> x0 v60 Imm(0) -> x0 - terminator Bnz { cond=v58, target=b23, fall=b13 } (exit_acc=v58) - block 13 start_pc=0 + terminator Bnz { cond=v58, target=b18, fall=b12 } (exit_acc=v58) + block 12 start_pc=0 v61 ImmData(24) -> x0 v62 Imm(0) -> x1 v63 Imm(5) -> x1 @@ -97,38 +94,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v65 Load { addr=v61, disp=5, kind=I8 } -> x0 v66 BinopI { op=ne, lhs=v65, rhs_imm=0 } -> x2 v67 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v66) - block 14 start_pc=0 - v68 Phi { incoming=[b23:v58, b13:v66], kind=I64 } -> x2 + terminator Jmp(b13) (exit_acc=v66) + block 13 start_pc=0 + v68 Phi { incoming=[b18:v58, b12:v66], kind=I64 } -> x2 v69 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v68, target=b16, fall=b15 } (exit_acc=v68) - block 15 start_pc=0 + terminator Bz { cond=v68, target=b15, fall=b14 } (exit_acc=v68) + block 14 start_pc=0 v70 Imm(3) -> x0 terminator Return(v70) (exit_acc=v70) - block 16 start_pc=0 + block 15 start_pc=0 v71 ImmData(24) -> x0 v72 Imm(6) -> x1 v73 BinopI { op=add, lhs=v71, rhs_imm=6 } -> x1 v74 Imm(0) -> x1 v75 Load { addr=v71, disp=6, kind=I8 } -> x0 v76 BinopI { op=ne, lhs=v75, rhs_imm=0 } -> x0 - terminator Bz { cond=v76, target=b18, fall=b17 } (exit_acc=v76) - block 17 start_pc=0 + terminator Bz { cond=v76, target=b17, fall=b16 } (exit_acc=v76) + block 16 start_pc=0 v77 Imm(4) -> x0 terminator Return(v77) (exit_acc=v77) - block 18 start_pc=0 + block 17 start_pc=0 v78 Imm(0) -> x0 terminator Return(v78) (exit_acc=v78) + block 18 start_pc=0 + terminator Jmp(b13) block 19 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b11) block 20 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b7) block 21 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b5) block 22 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b3) block 23 start_pc=0 - terminator Jmp(b14) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/enum_bitfield_unsigned.ssa b/tests/snapshots/ssa/enum_bitfield_unsigned.ssa index 12d1b47ea..63f51ca35 100644 --- a/tests/snapshots/ssa/enum_bitfield_unsigned.ssa +++ b/tests/snapshots/ssa/enum_bitfield_unsigned.ssa @@ -8,45 +8,45 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=5 } -> x0 - terminator Bnz { cond=v4, target=b7, fall=b8 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b7, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v16 Imm(0) -> x0 - terminator Return(v16) (exit_acc=v16) + v8 BinopI { op=lt, lhs=v1, rhs_imm=6 } -> x0 + terminator Bnz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 - v11 Imm(0) -> x0 - terminator Return(v11) (exit_acc=v11) + v10 BinopI { op=eq, lhs=v1, rhs_imm=6 } -> x0 + terminator Bnz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v12 Imm(40) -> x0 - terminator Return(v12) (exit_acc=v12) + v15 Imm(-1) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v13 Imm(50) -> x0 - terminator Return(v13) (exit_acc=v13) - block 5 start_pc=0 v14 Imm(60) -> x0 terminator Return(v14) (exit_acc=v14) + block 5 start_pc=0 + v9 BinopI { op=eq, lhs=v1, rhs_imm=5 } -> x0 + terminator Bz { cond=v9, target=b3, fall=b6 } (exit_acc=v9) block 6 start_pc=0 - v15 Imm(-1) -> x0 - terminator Return(v15) (exit_acc=v15) + v13 Imm(50) -> x0 + terminator Return(v13) (exit_acc=v13) block 7 start_pc=0 v5 BinopI { op=lt, lhs=v1, rhs_imm=4 } -> x0 - terminator Bnz { cond=v5, target=b9, fall=b10 } (exit_acc=v5) + terminator Bnz { cond=v5, target=b10, fall=b8 } (exit_acc=v5) block 8 start_pc=0 - v8 BinopI { op=lt, lhs=v1, rhs_imm=6 } -> x0 - terminator Bnz { cond=v8, target=b11, fall=b12 } (exit_acc=v8) + v7 BinopI { op=eq, lhs=v1, rhs_imm=4 } -> x0 + terminator Bz { cond=v7, target=b3, fall=b9 } (exit_acc=v7) block 9 start_pc=0 - v6 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b6 } (exit_acc=v6) + v12 Imm(40) -> x0 + terminator Return(v12) (exit_acc=v12) block 10 start_pc=0 - v7 BinopI { op=eq, lhs=v1, rhs_imm=4 } -> x0 - terminator Bnz { cond=v7, target=b3, fall=b6 } (exit_acc=v7) + v6 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 + terminator Bz { cond=v6, target=b3, fall=b11 } (exit_acc=v6) block 11 start_pc=0 - v9 BinopI { op=eq, lhs=v1, rhs_imm=5 } -> x0 - terminator Bnz { cond=v9, target=b4, fall=b6 } (exit_acc=v9) + v11 Imm(0) -> x0 + terminator Return(v11) (exit_acc=v11) block 12 start_pc=0 - v10 BinopI { op=eq, lhs=v1, rhs_imm=6 } -> x0 - terminator Bnz { cond=v10, target=b5, fall=b6 } (exit_acc=v10) + v16 Imm(0) -> x0 + terminator Return(v16) (exit_acc=v16) block 13 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b11) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=3 @@ -55,9 +55,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 v2 Imm(6) -> x1 - v3 Load { addr=v1, disp=0, kind=U32 } -> x2 - v4 BinopI { op=and, lhs=v3, rhs_imm=-8 } -> x2 - v5 Binop { op=or, lhs=v4, rhs=v2 } -> x1 + v3 Load { addr=v1, disp=0, kind=U32 } -> x1 + v4 BinopI { op=and, lhs=v3, rhs_imm=-8 } -> x1 + v5 BinopI { op=or, lhs=v4, rhs_imm=6 } -> x1 v6 Store { addr=v1, disp=0, value=v5, kind=I32 } -> - v7 LocalAddr(-1) -> x0 v8 Load { addr=v7, disp=0, kind=U32 } -> x0 @@ -72,9 +72,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 block 2 start_pc=0 v14 LocalAddr(-1) -> x0 v15 Imm(4) -> x1 - v16 Load { addr=v14, disp=0, kind=U32 } -> x2 - v17 BinopI { op=and, lhs=v16, rhs_imm=-8 } -> x2 - v18 Binop { op=or, lhs=v17, rhs=v15 } -> x1 + v16 Load { addr=v14, disp=0, kind=U32 } -> x1 + v17 BinopI { op=and, lhs=v16, rhs_imm=-8 } -> x1 + v18 BinopI { op=or, lhs=v17, rhs_imm=4 } -> x1 v19 Store { addr=v14, disp=0, value=v18, kind=I32 } -> - v20 LocalAddr(-1) -> x0 v21 Load { addr=v20, disp=0, kind=U32 } -> x0 @@ -89,9 +89,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 block 4 start_pc=0 v27 LocalAddr(-1) -> x0 v28 Imm(2) -> x1 - v29 Load { addr=v27, disp=0, kind=U32 } -> x2 - v30 BinopI { op=and, lhs=v29, rhs_imm=-8 } -> x2 - v31 Binop { op=or, lhs=v30, rhs=v28 } -> x1 + v29 Load { addr=v27, disp=0, kind=U32 } -> x1 + v30 BinopI { op=and, lhs=v29, rhs_imm=-8 } -> x1 + v31 BinopI { op=or, lhs=v30, rhs_imm=2 } -> x1 v32 Store { addr=v27, disp=0, value=v31, kind=I32 } -> - v33 LocalAddr(-1) -> x0 v34 Load { addr=v33, disp=0, kind=U32 } -> x0 @@ -106,9 +106,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 block 6 start_pc=0 v40 LocalAddr(-2) -> x0 v41 Imm(5) -> x1 - v42 Load { addr=v40, disp=0, kind=U32 } -> x2 - v43 BinopI { op=and, lhs=v42, rhs_imm=-8 } -> x2 - v44 Binop { op=or, lhs=v43, rhs=v41 } -> x1 + v42 Load { addr=v40, disp=0, kind=U32 } -> x1 + v43 BinopI { op=and, lhs=v42, rhs_imm=-8 } -> x1 + v44 BinopI { op=or, lhs=v43, rhs_imm=5 } -> x1 v45 Store { addr=v40, disp=0, value=v44, kind=I32 } -> - v46 LocalAddr(-2) -> x0 v47 Load { addr=v46, disp=0, kind=U32 } -> x0 diff --git a/tests/snapshots/ssa/enum_tag_types.ssa b/tests/snapshots/ssa/enum_tag_types.ssa index fc99fdbb4..d2c678bb7 100644 --- a/tests/snapshots/ssa/enum_tag_types.ssa +++ b/tests/snapshots/ssa/enum_tag_types.ssa @@ -19,91 +19,91 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=ne, lhs=v1, rhs_imm=1 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) + block 2 start_pc=0 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v8) block 3 start_pc=0 - v7 Imm(2) -> x0 - terminator Return(v7) (exit_acc=v7) + v10 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v10) block 4 start_pc=0 - v8 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v8) + v12 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v12) block 5 start_pc=0 - v9 Imm(3) -> x0 - terminator Return(v9) (exit_acc=v9) + v14 Imm(1) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-2, kind=I32 } -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v17) block 6 start_pc=0 - v10 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v10) + v19 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v19) block 7 start_pc=0 - v11 Imm(4) -> x0 - terminator Return(v11) (exit_acc=v11) + v21 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v21) block 8 start_pc=0 - v12 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v12) + v23 Imm(2) -> x0 + v24 Imm(2) -> x0 + v25 Imm(0) -> x0 + v26 Imm(102) -> x0 + v27 Imm(438086664192) -> x0 + v28 Imm(102) -> x0 + v29 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v29) block 9 start_pc=0 - v13 Imm(5) -> x0 - terminator Return(v13) (exit_acc=v13) + v31 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v31) block 10 start_pc=0 - v14 Imm(1) -> x0 - v15 Imm(0) -> x1 - v16 LoadLocal { off=-2, kind=I32 } -> x1 - v17 BinopI { op=ne, lhs=v14, rhs_imm=1 } -> x0 - terminator Bz { cond=v17, target=b12, fall=b11 } (exit_acc=v17) + v33 Imm(42) -> x0 + v34 Imm(42) -> x0 + v35 Imm(0) -> x0 + v36 Imm(142) -> x0 + v37 Imm(609885356032) -> x0 + v38 Imm(142) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v39) block 11 start_pc=0 - v18 Imm(6) -> x0 - terminator Return(v18) (exit_acc=v18) + v41 Imm(0) -> x0 + terminator Return(v41) (exit_acc=v41) block 12 start_pc=0 - v19 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v19) + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) block 13 start_pc=0 - v20 Imm(7) -> x0 - terminator Return(v20) (exit_acc=v20) + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) block 14 start_pc=0 - v21 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v21) + v9 Imm(3) -> x0 + terminator Return(v9) (exit_acc=v9) block 15 start_pc=0 - v22 Imm(8) -> x0 - terminator Return(v22) (exit_acc=v22) + v11 Imm(4) -> x0 + terminator Return(v11) (exit_acc=v11) block 16 start_pc=0 - v23 Imm(2) -> x0 - v24 Extend { value=v23, kind=I32 } -> x1 - v25 Imm(0) -> x1 - v26 BinopI { op=add, lhs=v23, rhs_imm=100 } -> x0 - v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x1 - v28 Extend { value=v26, kind=I32 } -> x0 - v29 BinopI { op=ne, lhs=v28, rhs_imm=102 } -> x0 - terminator Bz { cond=v29, target=b18, fall=b17 } (exit_acc=v29) + v13 Imm(5) -> x0 + terminator Return(v13) (exit_acc=v13) block 17 start_pc=0 - v30 Imm(9) -> x0 - terminator Return(v30) (exit_acc=v30) + v18 Imm(6) -> x0 + terminator Return(v18) (exit_acc=v18) block 18 start_pc=0 - v31 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v31) + v20 Imm(7) -> x0 + terminator Return(v20) (exit_acc=v20) block 19 start_pc=0 - v32 Imm(10) -> x0 - terminator Return(v32) (exit_acc=v32) + v22 Imm(8) -> x0 + terminator Return(v22) (exit_acc=v22) block 20 start_pc=0 - v33 Imm(42) -> x0 - v34 Extend { value=v33, kind=I32 } -> x1 - v35 Imm(0) -> x1 - v36 BinopI { op=add, lhs=v33, rhs_imm=100 } -> x0 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 - v38 Extend { value=v36, kind=I32 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=142 } -> x0 - terminator Bz { cond=v39, target=b22, fall=b21 } (exit_acc=v39) + v30 Imm(9) -> x0 + terminator Return(v30) (exit_acc=v30) block 21 start_pc=0 + v32 Imm(10) -> x0 + terminator Return(v32) (exit_acc=v32) + block 22 start_pc=0 v40 Imm(11) -> x0 terminator Return(v40) (exit_acc=v40) - block 22 start_pc=0 - v41 Imm(0) -> x0 - terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/environ_single_tu.ssa b/tests/snapshots/ssa/environ_single_tu.ssa index e0e6c2f2b..a8ff1e12c 100644 --- a/tests/snapshots/ssa/environ_single_tu.ssa +++ b/tests/snapshots/ssa/environ_single_tu.ssa @@ -13,39 +13,39 @@ fn ent_pc=5 n_params=0 variadic=false locals=4 v7 ImmData(0) -> x0 v8 Load { addr=v7, disp=0, kind=I64 } -> x1 v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v8) + terminator Jmp(b3) (exit_acc=v8) block 1 start_pc=0 - v10 Phi { incoming=[b0:v8, b2:v15], kind=I64 } -> x1 - v11 Phi { incoming=[b0:v5, b2:v18], kind=I64 } -> x2 - v12 LoadLocal { off=-2, kind=I64 } -> x0 - v13 Load { addr=v10, disp=0, kind=I64 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v17 Extend { value=v11, kind=I32 } -> x0 + v18 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x2 + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 v14 LoadLocal { off=-2, kind=I64 } -> x0 v15 BinopI { op=add, lhs=v10, rhs_imm=8 } -> x1 v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) + terminator Jmp(b3) (exit_acc=v15) block 3 start_pc=0 - v17 Extend { value=v11, kind=I32 } -> x0 - v18 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x2 - v19 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v18) + v10 Phi { incoming=[b0:v8, b2:v15], kind=I64 } -> x1 + v11 Phi { incoming=[b0:v5, b2:v18], kind=I64 } -> x2 + v12 LoadLocal { off=-2, kind=I64 } -> x0 + v13 Load { addr=v10, disp=0, kind=I64 } -> x0 + terminator Bnz { cond=v13, target=b1, fall=b4 } (exit_acc=v13) block 4 start_pc=0 v20 Extend { value=v11, kind=I32 } -> x0 v21 BinopI { op=gt, lhs=v20, rhs_imm=0 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) + terminator Bz { cond=v21, target=b7, fall=b5 } (exit_acc=v21) block 5 start_pc=0 v22 Imm(0) -> x1 v23 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v22) + terminator Jmp(b6) (exit_acc=v22) block 6 start_pc=0 - v24 Imm(1) -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v24) - block 7 start_pc=0 - v26 Phi { incoming=[b5:v22, b6:v24], kind=I64 } -> x1 + v26 Phi { incoming=[b5:v22, b7:v24], kind=I64 } -> x1 v27 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v26) (exit_acc=v26) + block 7 start_pc=0 + v24 Imm(1) -> x1 + v25 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v24) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/errno_socket_constants.ssa b/tests/snapshots/ssa/errno_socket_constants.ssa index 868479e47..008cd7e52 100644 --- a/tests/snapshots/ssa/errno_socket_constants.ssa +++ b/tests/snapshots/ssa/errno_socket_constants.ssa @@ -8,76 +8,76 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 v2 ImmData(8) -> x1 v3 Mcpy { dst=v1, src=v2, size=64 } -> x0 v4 Imm(64) -> x0 - v5 Imm(4) -> x1 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v4, rhs=v6 } -> x0 - v8 BinopI { op=shr, lhs=v7, rhs_imm=2 } -> x0 - v9 Imm(0) -> x1 - v10 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v6) + v5 Imm(4) -> x0 + v6 Imm(0) -> x1 + v7 Imm(64) -> x0 + v8 Imm(16) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v6) block 1 start_pc=0 - v11 Phi { incoming=[b0:v6, b2:v16], kind=I64 } -> x2 - v12 Extend { value=v11, kind=I32 } -> x1 - v13 Extend { value=v8, kind=I32 } -> x6 - v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x1 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v18 LocalAddr(-8) -> x2 + v19 Extend { value=v11, kind=I32 } -> x6 + v20 BinopI { op=shl, lhs=v12, rhs_imm=2 } -> x6 + v21 Binop { op=add, lhs=v18, rhs=v20 } -> x6 + v22 LoadIndexed { base=v18, index=v12, scale=4, kind=I32 } -> x2 + v23 BinopI { op=le, lhs=v22, rhs_imm=0 } -> x2 + terminator Bnz { cond=v23, target=b10, fall=b2 } (exit_acc=v23) block 2 start_pc=0 - v15 Extend { value=v11, kind=I32 } -> x1 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x2 - v17 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v16) + v26 Extend { value=v11, kind=I32 } -> x2 + v27 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x2 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x6 + v29 Extend { value=v27, kind=I32 } -> x6 + v30 Imm(0) -> x2 + terminator Jmp(b5) (exit_acc=v29) block 3 start_pc=0 - v18 LocalAddr(-8) -> x1 - v19 Extend { value=v11, kind=I32 } -> x6 - v20 BinopI { op=shl, lhs=v19, rhs_imm=2 } -> x7 - v21 Binop { op=add, lhs=v18, rhs=v20 } -> x7 - v22 LoadIndexed { base=v18, index=v19, scale=4, kind=I32 } -> x1 - v23 BinopI { op=le, lhs=v22, rhs_imm=0 } -> x1 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) + v38 LocalAddr(-8) -> x7 + v39 Extend { value=v11, kind=I32 } -> x8 + v40 BinopI { op=shl, lhs=v12, rhs_imm=2 } -> x8 + v41 Binop { op=add, lhs=v38, rhs=v40 } -> x8 + v42 LoadIndexed { base=v38, index=v12, scale=4, kind=I32 } -> x7 + v43 LocalAddr(-8) -> x8 + v44 Extend { value=v31, kind=I32 } -> x9 + v45 BinopI { op=shl, lhs=v32, rhs_imm=2 } -> x9 + v46 Binop { op=add, lhs=v43, rhs=v45 } -> x9 + v47 LoadIndexed { base=v43, index=v32, scale=4, kind=I32 } -> x8 + v48 Binop { op=eq, lhs=v42, rhs=v47 } -> x7 + terminator Bnz { cond=v48, target=b9, fall=b4 } (exit_acc=v48) block 4 start_pc=0 - v24 Imm(0) -> x0 - terminator Return(v24) (exit_acc=v24) + v35 Extend { value=v31, kind=I32 } -> x6 + v36 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x6 + v37 Imm(0) -> x2 + terminator Jmp(b5) (exit_acc=v36) block 5 start_pc=0 - v25 Imm(1) -> x0 - terminator Return(v25) (exit_acc=v25) + v31 Phi { incoming=[b2:v29, b4:v36], kind=I64 } -> x6 + v32 Extend { value=v31, kind=I32 } -> x2 + v33 Imm(16) -> x7 + v34 BinopI { op=lt, lhs=v32, rhs_imm=16 } -> x7 + terminator Bnz { cond=v34, target=b3, fall=b6 } (exit_acc=v34) block 6 start_pc=0 - v26 Extend { value=v11, kind=I32 } -> x1 - v27 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x6 - v29 Extend { value=v27, kind=I32 } -> x6 - v30 Imm(0) -> x1 - terminator Jmp(b7) (exit_acc=v29) + v15 Extend { value=v11, kind=I32 } -> x1 + v16 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v16) block 7 start_pc=0 - v31 Phi { incoming=[b6:v29, b8:v36], kind=I64 } -> x6 - v32 Extend { value=v31, kind=I32 } -> x1 - v33 Extend { value=v8, kind=I32 } -> x7 - v34 Binop { op=lt, lhs=v32, rhs=v33 } -> x1 - terminator Bz { cond=v34, target=b10, fall=b9 } (exit_acc=v34) + v11 Phi { incoming=[b0:v6, b6:v16], kind=I64 } -> x1 + v12 Extend { value=v11, kind=I32 } -> x0 + v13 Imm(16) -> x2 + v14 BinopI { op=lt, lhs=v12, rhs_imm=16 } -> x2 + terminator Bnz { cond=v14, target=b1, fall=b8 } (exit_acc=v14) block 8 start_pc=0 - v35 Extend { value=v31, kind=I32 } -> x1 - v36 BinopI { op=add, lhs=v35, rhs_imm=1 } -> x6 - v37 Imm(0) -> x1 - terminator Jmp(b7) (exit_acc=v36) + v24 Imm(0) -> x0 + terminator Return(v24) (exit_acc=v24) block 9 start_pc=0 - v38 LocalAddr(-8) -> x1 - v39 Extend { value=v11, kind=I32 } -> x7 - v40 BinopI { op=shl, lhs=v39, rhs_imm=2 } -> x8 - v41 Binop { op=add, lhs=v38, rhs=v40 } -> x8 - v42 LoadIndexed { base=v38, index=v39, scale=4, kind=I32 } -> x1 - v43 LocalAddr(-8) -> x7 - v44 Extend { value=v31, kind=I32 } -> x8 - v45 BinopI { op=shl, lhs=v44, rhs_imm=2 } -> x9 - v46 Binop { op=add, lhs=v43, rhs=v45 } -> x9 - v47 LoadIndexed { base=v43, index=v44, scale=4, kind=I32 } -> x7 - v48 Binop { op=eq, lhs=v42, rhs=v47 } -> x1 - terminator Bz { cond=v48, target=b12, fall=b11 } (exit_acc=v48) - block 10 start_pc=0 - terminator Jmp(b2) - block 11 start_pc=0 v49 Imm(2) -> x0 terminator Return(v49) (exit_acc=v49) + block 10 start_pc=0 + v25 Imm(1) -> x0 + terminator Return(v25) (exit_acc=v25) + block 11 start_pc=0 + terminator Jmp(b6) block 12 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/extern_in_function.ssa b/tests/snapshots/ssa/extern_in_function.ssa index 242c677f2..201c41630 100644 --- a/tests/snapshots/ssa/extern_in_function.ssa +++ b/tests/snapshots/ssa/extern_in_function.ssa @@ -33,66 +33,66 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-5) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x2 - v4 Extend { value=v2, kind=I32 } -> x1 - v5 Imm(0) -> x1 - v6 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x0 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=5 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v2 Imm(-5) -> x0 + v3 Imm(0) -> x0 + v4 Imm(-5) -> x0 + v5 Imm(0) -> x0 + v6 Imm(5) -> x0 + v7 Imm(21474836480) -> x0 + v8 Imm(5) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(11) -> x0 - terminator Return(v10) (exit_acc=v10) - block 2 start_pc=0 v11 Imm(7) -> x0 - v12 Extend { value=v11, kind=I32 } -> x1 - v13 Imm(0) -> x2 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 Imm(0) -> x1 - v16 BinopI { op=mul, lhs=v11, rhs_imm=-1 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 - v18 Extend { value=v16, kind=I32 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=-7 } -> x0 - terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) + v12 Imm(7) -> x0 + v13 Imm(0) -> x0 + v14 Imm(7) -> x0 + v15 Imm(0) -> x0 + v16 Imm(-7) -> x0 + v17 Imm(-30064771072) -> x0 + v18 Imm(-7) -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v19) + block 2 start_pc=0 + v21 Imm(3) -> x0 + v22 Imm(3) -> x0 + v23 Imm(0) -> x0 + v24 Imm(-3) -> x0 + v25 Imm(-12884901888) -> x0 + v26 Imm(-3) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v27) block 3 start_pc=0 - v20 Imm(12) -> x0 - terminator Return(v20) (exit_acc=v20) + v29 Imm(-1) -> x0 + v30 Imm(-1) -> x0 + v31 Imm(0) -> x0 + v32 Imm(-1) -> x0 + v33 Imm(0) -> x0 + v34 Imm(1) -> x0 + v35 Imm(4294967296) -> x0 + v36 Imm(1) -> x0 + v37 Imm(-1) -> x0 + v38 Imm(0) -> x0 + v39 Imm(1) -> x0 + v40 Imm(4294967296) -> x0 + v41 Imm(1) -> x0 + v42 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v42) block 4 start_pc=0 - v21 Imm(3) -> x0 - v22 Extend { value=v21, kind=I32 } -> x1 - v23 Imm(0) -> x1 - v24 BinopI { op=mul, lhs=v21, rhs_imm=-1 } -> x0 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x1 - v26 Extend { value=v24, kind=I32 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=-3 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) block 5 start_pc=0 - v28 Imm(13) -> x0 - terminator Return(v28) (exit_acc=v28) + v10 Imm(11) -> x0 + terminator Return(v10) (exit_acc=v10) block 6 start_pc=0 - v29 Imm(-1) -> x0 - v30 Extend { value=v29, kind=I32 } -> x1 - v31 Imm(0) -> x2 - v32 Extend { value=v30, kind=I32 } -> x1 - v33 Imm(0) -> x1 - v34 BinopI { op=mul, lhs=v29, rhs_imm=-1 } -> x1 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x2 - v36 Extend { value=v34, kind=I32 } -> x1 - v37 Extend { value=v29, kind=I32 } -> x2 - v38 Imm(0) -> x2 - v39 BinopI { op=mul, lhs=v29, rhs_imm=-1 } -> x0 - v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x2 - v41 Extend { value=v39, kind=I32 } -> x0 - v42 Binop { op=ne, lhs=v36, rhs=v41 } -> x0 - terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) + v20 Imm(12) -> x0 + terminator Return(v20) (exit_acc=v20) block 7 start_pc=0 + v28 Imm(13) -> x0 + terminator Return(v28) (exit_acc=v28) + block 8 start_pc=0 v43 Imm(14) -> x0 terminator Return(v43) (exit_acc=v43) - block 8 start_pc=0 - v44 Imm(0) -> x0 - terminator Return(v44) (exit_acc=v44) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fcntl_lock_via_cast_fnptr.ssa b/tests/snapshots/ssa/fcntl_lock_via_cast_fnptr.ssa index da62f8815..88def3d5d 100644 --- a/tests/snapshots/ssa/fcntl_lock_via_cast_fnptr.ssa +++ b/tests/snapshots/ssa/fcntl_lock_via_cast_fnptr.ssa @@ -78,19 +78,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 block 6 start_pc=0 v61 LoadLocal { off=-24, kind=I32 } -> x0 v62 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x0 - terminator Bz { cond=v62, target=b8, fall=b7 } (exit_acc=v62) + terminator Bz { cond=v62, target=b9, fall=b7 } (exit_acc=v62) block 7 start_pc=0 v63 Imm(0) -> x1 v64 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v63) + terminator Jmp(b8) (exit_acc=v63) block 8 start_pc=0 - v65 Imm(1) -> x1 - v66 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v65) - block 9 start_pc=0 - v67 Phi { incoming=[b7:v63, b8:v65], kind=I64 } -> x1 + v67 Phi { incoming=[b7:v63, b9:v65], kind=I64 } -> x1 v68 LoadLocal { off=-31, kind=I64 } -> x0 terminator Return(v67) (exit_acc=v67) + block 9 start_pc=0 + v65 Imm(1) -> x1 + v66 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v65) block 10 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=2 --- diff --git a/tests/snapshots/ssa/fd_set_macros.ssa b/tests/snapshots/ssa/fd_set_macros.ssa index c711f1924..4a0d43067 100644 --- a/tests/snapshots/ssa/fd_set_macros.ssa +++ b/tests/snapshots/ssa/fd_set_macros.ssa @@ -10,23 +10,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v2 Imm(0) -> x1 v3 Imm(0) -> x2 v4 Imm(0) -> x1 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 2 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 3 start_pc=0 - v6 Imm(0) -> x1 - v7 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v6) - block 4 start_pc=0 - v8 Phi { incoming=[b1:v3, b5:v19], kind=I64 } -> x2 - v9 Extend { value=v8, kind=I32 } -> x1 - v10 BinopI { op=lt, lhs=v9, rhs_imm=128 } -> x1 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) - block 5 start_pc=0 - v11 LoadLocal { off=-17, kind=I64 } -> x1 - v12 Extend { value=v8, kind=I32 } -> x1 - v13 Binop { op=add, lhs=v1, rhs=v12 } -> x1 + v11 LoadLocal { off=-17, kind=I64 } -> x6 + v12 Extend { value=v8, kind=I32 } -> x6 + v13 Binop { op=add, lhs=v1, rhs=v9 } -> x1 v14 Imm(0) -> x6 v15 Store { addr=v13, disp=0, value=v14, kind=I8 } -> - v16 Extend { value=v8, kind=I32 } -> x1 @@ -34,64 +22,67 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x2 v19 Extend { value=v17, kind=I32 } -> x2 v20 Imm(0) -> x1 - terminator Jmp(b4) (exit_acc=v19) + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v8 Phi { incoming=[b1:v3, b2:v19], kind=I64 } -> x2 + v9 Extend { value=v8, kind=I32 } -> x1 + v10 BinopI { op=lt, lhs=v9, rhs_imm=128 } -> x6 + terminator Bnz { cond=v10, target=b2, fall=b4 } (exit_acc=v10) + block 4 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v5) + block 5 start_pc=0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v6) block 6 start_pc=0 - terminator Jmp(b2) - block 7 start_pc=0 - v21 Phi { incoming=[b3:v6, b11:v33], kind=I64 } -> x1 - v22 Extend { value=v21, kind=I32 } -> x0 - v23 BinopI { op=lt, lhs=v22, rhs_imm=128 } -> x0 - terminator Bz { cond=v23, target=b9, fall=b8 } (exit_acc=v23) - block 8 start_pc=0 - v24 LocalAddr(-16) -> x0 - v25 Extend { value=v21, kind=I32 } -> x2 - v26 Binop { op=add, lhs=v24, rhs=v25 } -> x0 + v24 LocalAddr(-16) -> x2 + v25 Extend { value=v21, kind=I32 } -> x6 + v26 Binop { op=add, lhs=v24, rhs=v22 } -> x0 v27 Load { addr=v26, disp=0, kind=I8 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=0 } -> x0 - terminator Bz { cond=v28, target=b11, fall=b10 } (exit_acc=v28) - block 9 start_pc=0 - terminator Jmp(b12) - block 10 start_pc=0 - v29 Imm(1) -> x0 - terminator Return(v29) (exit_acc=v29) - block 11 start_pc=0 + terminator Bnz { cond=v28, target=b56, fall=b7 } (exit_acc=v28) + block 7 start_pc=0 v30 Extend { value=v21, kind=I32 } -> x0 v31 BinopI { op=add, lhs=v21, rhs_imm=1 } -> x0 v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x1 v33 Extend { value=v31, kind=I32 } -> x1 v34 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v33) - block 12 start_pc=0 + terminator Jmp(b8) (exit_acc=v33) + block 8 start_pc=0 + v21 Phi { incoming=[b5:v6, b7:v33], kind=I64 } -> x1 + v22 Extend { value=v21, kind=I32 } -> x0 + v23 BinopI { op=lt, lhs=v22, rhs_imm=128 } -> x2 + terminator Bnz { cond=v23, target=b6, fall=b9 } (exit_acc=v23) + block 9 start_pc=0 v35 LocalAddr(-16) -> x0 v36 Imm(0) -> x1 v37 LoadLocal { off=-20, kind=I64 } -> x1 v38 Imm(0) -> x1 - v39 Imm(8) -> x2 - v40 Binop { op=add, lhs=v38, rhs=v38 } -> x1 - v41 BinopI { op=shr, lhs=v40, rhs_imm=3 } -> x1 - v42 Binop { op=add, lhs=v35, rhs=v41 } -> x0 + v39 Imm(8) -> x1 + v40 Imm(0) -> x1 + v41 Imm(0) -> x1 + v42 BinopI { op=add, lhs=v35, rhs_imm=0 } -> x0 v43 Load { addr=v42, disp=0, kind=U8 } -> x1 v44 Imm(1) -> x2 v45 Imm(4294967296) -> x2 v46 BinopI { op=or, lhs=v43, rhs_imm=1 } -> x1 v47 Store { addr=v42, disp=0, value=v46, kind=I8 } -> - v48 BinopI { op=and, lhs=v46, rhs_imm=255 } -> x0 - terminator Jmp(b13) (exit_acc=v48) - block 13 start_pc=0 + terminator Jmp(b10) (exit_acc=v48) + block 10 start_pc=0 v49 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v49) - block 14 start_pc=0 - terminator Jmp(b15) - block 15 start_pc=0 + terminator Jmp(b11) (exit_acc=v49) + block 11 start_pc=0 v50 LocalAddr(-16) -> x0 v51 Imm(0) -> x1 v52 LoadLocal { off=-21, kind=I64 } -> x1 v53 Imm(7) -> x1 - v54 Imm(8) -> x2 - v55 Imm(0) -> x2 - v56 Binop { op=add, lhs=v53, rhs=v55 } -> x1 - v57 BinopI { op=shr, lhs=v56, rhs_imm=3 } -> x1 - v58 Binop { op=add, lhs=v50, rhs=v57 } -> x0 + v54 Imm(8) -> x1 + v55 Imm(0) -> x1 + v56 Imm(7) -> x1 + v57 Imm(0) -> x1 + v58 BinopI { op=add, lhs=v50, rhs_imm=0 } -> x0 v59 Load { addr=v58, disp=0, kind=U8 } -> x1 v60 Imm(1) -> x2 v61 Imm(128) -> x2 @@ -99,159 +90,155 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v63 BinopI { op=or, lhs=v59, rhs_imm=128 } -> x1 v64 Store { addr=v58, disp=0, value=v63, kind=I8 } -> - v65 BinopI { op=and, lhs=v63, rhs_imm=255 } -> x0 - terminator Jmp(b16) (exit_acc=v65) - block 16 start_pc=0 + terminator Jmp(b12) (exit_acc=v65) + block 12 start_pc=0 v66 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v66) - block 17 start_pc=0 - terminator Jmp(b18) - block 18 start_pc=0 + terminator Jmp(b13) (exit_acc=v66) + block 13 start_pc=0 v67 LocalAddr(-16) -> x0 v68 Imm(0) -> x1 v69 LoadLocal { off=-22, kind=I64 } -> x1 v70 Imm(8) -> x1 - v71 Imm(0) -> x2 - v72 Binop { op=add, lhs=v70, rhs=v71 } -> x1 - v73 BinopI { op=shr, lhs=v72, rhs_imm=3 } -> x1 - v74 Binop { op=add, lhs=v67, rhs=v73 } -> x0 - v75 Load { addr=v74, disp=0, kind=U8 } -> x1 + v71 Imm(0) -> x1 + v72 Imm(8) -> x1 + v73 Imm(1) -> x1 + v74 BinopI { op=add, lhs=v67, rhs_imm=1 } -> x1 + v75 Load { addr=v67, disp=1, kind=U8 } -> x1 v76 Imm(1) -> x2 v77 Imm(4294967296) -> x2 v78 BinopI { op=or, lhs=v75, rhs_imm=1 } -> x1 - v79 Store { addr=v74, disp=0, value=v78, kind=I8 } -> - + v79 Store { addr=v67, disp=1, value=v78, kind=I8 } -> - v80 BinopI { op=and, lhs=v78, rhs_imm=255 } -> x0 - terminator Jmp(b19) (exit_acc=v80) - block 19 start_pc=0 + terminator Jmp(b14) (exit_acc=v80) + block 14 start_pc=0 v81 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v81) - block 20 start_pc=0 - terminator Jmp(b21) - block 21 start_pc=0 + terminator Jmp(b15) (exit_acc=v81) + block 15 start_pc=0 v82 LocalAddr(-16) -> x0 v83 Imm(0) -> x1 v84 LoadLocal { off=-23, kind=I64 } -> x1 v85 Imm(100) -> x1 - v86 Imm(8) -> x2 - v87 Imm(0) -> x2 - v88 Binop { op=add, lhs=v85, rhs=v87 } -> x1 - v89 BinopI { op=shr, lhs=v88, rhs_imm=3 } -> x1 - v90 Binop { op=add, lhs=v82, rhs=v89 } -> x0 - v91 Load { addr=v90, disp=0, kind=U8 } -> x1 + v86 Imm(8) -> x1 + v87 Imm(0) -> x1 + v88 Imm(100) -> x1 + v89 Imm(12) -> x1 + v90 BinopI { op=add, lhs=v82, rhs_imm=12 } -> x1 + v91 Load { addr=v82, disp=12, kind=U8 } -> x1 v92 Imm(1) -> x2 v93 Imm(4) -> x2 v94 Imm(16) -> x2 v95 Imm(68719476736) -> x2 v96 BinopI { op=or, lhs=v91, rhs_imm=16 } -> x1 - v97 Store { addr=v90, disp=0, value=v96, kind=I8 } -> - + v97 Store { addr=v82, disp=12, value=v96, kind=I8 } -> - v98 BinopI { op=and, lhs=v96, rhs_imm=255 } -> x0 - terminator Jmp(b22) (exit_acc=v98) - block 22 start_pc=0 + terminator Jmp(b16) (exit_acc=v98) + block 16 start_pc=0 v99 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v99) - block 23 start_pc=0 + terminator Jmp(b17) (exit_acc=v99) + block 17 start_pc=0 v100 LocalAddr(-16) -> x0 v101 Imm(0) -> x1 - v102 Imm(8) -> x2 - v103 Binop { op=add, lhs=v101, rhs=v101 } -> x1 - v104 BinopI { op=shr, lhs=v103, rhs_imm=3 } -> x1 - v105 Binop { op=add, lhs=v100, rhs=v104 } -> x0 + v102 Imm(8) -> x1 + v103 Imm(0) -> x1 + v104 Imm(0) -> x1 + v105 BinopI { op=add, lhs=v100, rhs_imm=0 } -> x0 v106 Load { addr=v105, disp=0, kind=U8 } -> x0 v107 Imm(1) -> x1 v108 Imm(4294967296) -> x1 v109 BinopI { op=and, lhs=v106, rhs_imm=1 } -> x0 v110 BinopI { op=eq, lhs=v109, rhs_imm=0 } -> x0 - terminator Bz { cond=v110, target=b25, fall=b24 } (exit_acc=v110) - block 24 start_pc=0 + terminator Bz { cond=v110, target=b19, fall=b18 } (exit_acc=v110) + block 18 start_pc=0 v111 Imm(2) -> x0 terminator Return(v111) (exit_acc=v111) - block 25 start_pc=0 + block 19 start_pc=0 v112 LocalAddr(-16) -> x0 v113 Imm(7) -> x1 - v114 Imm(8) -> x2 - v115 Imm(0) -> x2 - v116 Binop { op=add, lhs=v113, rhs=v115 } -> x1 - v117 BinopI { op=shr, lhs=v116, rhs_imm=3 } -> x1 - v118 Binop { op=add, lhs=v112, rhs=v117 } -> x0 + v114 Imm(8) -> x1 + v115 Imm(0) -> x1 + v116 Imm(7) -> x1 + v117 Imm(0) -> x1 + v118 BinopI { op=add, lhs=v112, rhs_imm=0 } -> x0 v119 Load { addr=v118, disp=0, kind=U8 } -> x0 v120 Imm(1) -> x1 v121 Imm(128) -> x1 v122 Imm(549755813888) -> x1 v123 BinopI { op=and, lhs=v119, rhs_imm=128 } -> x0 v124 BinopI { op=eq, lhs=v123, rhs_imm=0 } -> x0 - terminator Bz { cond=v124, target=b27, fall=b26 } (exit_acc=v124) - block 26 start_pc=0 + terminator Bz { cond=v124, target=b21, fall=b20 } (exit_acc=v124) + block 20 start_pc=0 v125 Imm(3) -> x0 terminator Return(v125) (exit_acc=v125) - block 27 start_pc=0 + block 21 start_pc=0 v126 LocalAddr(-16) -> x0 v127 Imm(8) -> x1 - v128 Imm(0) -> x2 - v129 Binop { op=add, lhs=v127, rhs=v128 } -> x1 - v130 BinopI { op=shr, lhs=v129, rhs_imm=3 } -> x1 - v131 Binop { op=add, lhs=v126, rhs=v130 } -> x0 - v132 Load { addr=v131, disp=0, kind=U8 } -> x0 + v128 Imm(0) -> x1 + v129 Imm(8) -> x1 + v130 Imm(1) -> x1 + v131 BinopI { op=add, lhs=v126, rhs_imm=1 } -> x1 + v132 Load { addr=v126, disp=1, kind=U8 } -> x0 v133 Imm(1) -> x1 v134 Imm(4294967296) -> x1 v135 BinopI { op=and, lhs=v132, rhs_imm=1 } -> x0 v136 BinopI { op=eq, lhs=v135, rhs_imm=0 } -> x0 - terminator Bz { cond=v136, target=b29, fall=b28 } (exit_acc=v136) - block 28 start_pc=0 + terminator Bz { cond=v136, target=b23, fall=b22 } (exit_acc=v136) + block 22 start_pc=0 v137 Imm(4) -> x0 terminator Return(v137) (exit_acc=v137) - block 29 start_pc=0 + block 23 start_pc=0 v138 LocalAddr(-16) -> x0 v139 Imm(100) -> x1 - v140 Imm(8) -> x2 - v141 Imm(0) -> x2 - v142 Binop { op=add, lhs=v139, rhs=v141 } -> x1 - v143 BinopI { op=shr, lhs=v142, rhs_imm=3 } -> x1 - v144 Binop { op=add, lhs=v138, rhs=v143 } -> x0 - v145 Load { addr=v144, disp=0, kind=U8 } -> x0 + v140 Imm(8) -> x1 + v141 Imm(0) -> x1 + v142 Imm(100) -> x1 + v143 Imm(12) -> x1 + v144 BinopI { op=add, lhs=v138, rhs_imm=12 } -> x1 + v145 Load { addr=v138, disp=12, kind=U8 } -> x0 v146 Imm(1) -> x1 v147 Imm(4) -> x1 v148 Imm(16) -> x1 v149 Imm(68719476736) -> x1 v150 BinopI { op=and, lhs=v145, rhs_imm=16 } -> x0 v151 BinopI { op=eq, lhs=v150, rhs_imm=0 } -> x0 - terminator Bz { cond=v151, target=b31, fall=b30 } (exit_acc=v151) - block 30 start_pc=0 + terminator Bz { cond=v151, target=b25, fall=b24 } (exit_acc=v151) + block 24 start_pc=0 v152 Imm(5) -> x0 terminator Return(v152) (exit_acc=v152) - block 31 start_pc=0 + block 25 start_pc=0 v153 LocalAddr(-16) -> x0 v154 Imm(1) -> x1 - v155 Imm(8) -> x2 - v156 Imm(0) -> x2 - v157 Binop { op=add, lhs=v154, rhs=v156 } -> x1 - v158 BinopI { op=shr, lhs=v157, rhs_imm=3 } -> x1 - v159 Binop { op=add, lhs=v153, rhs=v158 } -> x0 + v155 Imm(8) -> x1 + v156 Imm(0) -> x1 + v157 Imm(1) -> x1 + v158 Imm(0) -> x1 + v159 BinopI { op=add, lhs=v153, rhs_imm=0 } -> x0 v160 Load { addr=v159, disp=0, kind=U8 } -> x0 v161 Imm(2) -> x1 v162 Imm(8589934592) -> x1 v163 BinopI { op=and, lhs=v160, rhs_imm=2 } -> x0 - terminator Bz { cond=v163, target=b33, fall=b32 } (exit_acc=v163) - block 32 start_pc=0 + terminator Bz { cond=v163, target=b27, fall=b26 } (exit_acc=v163) + block 26 start_pc=0 v164 Imm(6) -> x0 terminator Return(v164) (exit_acc=v164) - block 33 start_pc=0 + block 27 start_pc=0 v165 LocalAddr(-16) -> x0 v166 Imm(50) -> x1 - v167 Imm(8) -> x2 - v168 Imm(0) -> x2 - v169 Binop { op=add, lhs=v166, rhs=v168 } -> x1 - v170 BinopI { op=shr, lhs=v169, rhs_imm=3 } -> x1 - v171 Binop { op=add, lhs=v165, rhs=v170 } -> x0 - v172 Load { addr=v171, disp=0, kind=U8 } -> x0 + v167 Imm(8) -> x1 + v168 Imm(0) -> x1 + v169 Imm(50) -> x1 + v170 Imm(6) -> x1 + v171 BinopI { op=add, lhs=v165, rhs_imm=6 } -> x1 + v172 Load { addr=v165, disp=6, kind=U8 } -> x0 v173 Imm(1) -> x1 v174 Imm(2) -> x1 v175 Imm(4) -> x1 v176 Imm(17179869184) -> x1 v177 BinopI { op=and, lhs=v172, rhs_imm=4 } -> x0 - terminator Bz { cond=v177, target=b35, fall=b34 } (exit_acc=v177) - block 34 start_pc=0 + terminator Bz { cond=v177, target=b29, fall=b28 } (exit_acc=v177) + block 28 start_pc=0 v178 Imm(7) -> x0 terminator Return(v178) (exit_acc=v178) - block 35 start_pc=0 + block 29 start_pc=0 v179 LocalAddr(-16) -> x0 v180 Imm(0) -> x1 v181 LoadLocal { off=-24, kind=I64 } -> x1 @@ -260,11 +247,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v184 BinopI { op=xor, lhs=v183, rhs_imm=129 } -> x1 v185 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x1 v186 BinopI { op=ne, lhs=v185, rhs_imm=0 } -> x1 - terminator Bz { cond=v186, target=b37, fall=b36 } (exit_acc=v186) - block 36 start_pc=0 + terminator Bz { cond=v186, target=b31, fall=b30 } (exit_acc=v186) + block 30 start_pc=0 v187 Imm(11) -> x0 terminator Return(v187) (exit_acc=v187) - block 37 start_pc=0 + block 31 start_pc=0 v188 LoadLocal { off=-24, kind=I64 } -> x1 v189 Imm(1) -> x1 v190 BinopI { op=add, lhs=v179, rhs_imm=1 } -> x1 @@ -272,11 +259,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v192 BinopI { op=xor, lhs=v191, rhs_imm=1 } -> x1 v193 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x1 v194 BinopI { op=ne, lhs=v193, rhs_imm=0 } -> x1 - terminator Bz { cond=v194, target=b39, fall=b38 } (exit_acc=v194) - block 38 start_pc=0 + terminator Bz { cond=v194, target=b33, fall=b32 } (exit_acc=v194) + block 32 start_pc=0 v195 Imm(12) -> x0 terminator Return(v195) (exit_acc=v195) - block 39 start_pc=0 + block 33 start_pc=0 v196 LoadLocal { off=-24, kind=I64 } -> x1 v197 Imm(12) -> x1 v198 BinopI { op=add, lhs=v179, rhs_imm=12 } -> x1 @@ -284,22 +271,20 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v200 BinopI { op=xor, lhs=v199, rhs_imm=16 } -> x0 v201 BinopI { op=and, lhs=v200, rhs_imm=4294967295 } -> x0 v202 BinopI { op=ne, lhs=v201, rhs_imm=0 } -> x0 - terminator Bz { cond=v202, target=b41, fall=b40 } (exit_acc=v202) - block 40 start_pc=0 + terminator Bz { cond=v202, target=b35, fall=b34 } (exit_acc=v202) + block 34 start_pc=0 v203 Imm(13) -> x0 terminator Return(v203) (exit_acc=v203) - block 41 start_pc=0 - terminator Jmp(b42) - block 42 start_pc=0 + block 35 start_pc=0 v204 LocalAddr(-16) -> x0 v205 Imm(0) -> x1 v206 LoadLocal { off=-25, kind=I64 } -> x1 v207 Imm(7) -> x1 - v208 Imm(8) -> x2 - v209 Imm(0) -> x2 - v210 Binop { op=add, lhs=v207, rhs=v209 } -> x1 - v211 BinopI { op=shr, lhs=v210, rhs_imm=3 } -> x1 - v212 Binop { op=add, lhs=v204, rhs=v211 } -> x0 + v208 Imm(8) -> x1 + v209 Imm(0) -> x1 + v210 Imm(7) -> x1 + v211 Imm(0) -> x1 + v212 BinopI { op=add, lhs=v204, rhs_imm=0 } -> x0 v213 Load { addr=v212, disp=0, kind=U8 } -> x1 v214 Imm(1) -> x2 v215 Imm(128) -> x2 @@ -308,128 +293,104 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v218 BinopI { op=and, lhs=v213, rhs_imm=-129 } -> x2 v219 Store { addr=v212, disp=0, value=v218, kind=I8 } -> - v220 BinopI { op=and, lhs=v213, rhs_imm=127 } -> x0 - terminator Jmp(b43) (exit_acc=v220) - block 43 start_pc=0 + terminator Jmp(b36) (exit_acc=v220) + block 36 start_pc=0 v221 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v221) - block 44 start_pc=0 + terminator Jmp(b37) (exit_acc=v221) + block 37 start_pc=0 v222 LocalAddr(-16) -> x0 v223 Imm(7) -> x1 - v224 Imm(8) -> x2 - v225 Imm(0) -> x2 - v226 Binop { op=add, lhs=v223, rhs=v225 } -> x1 - v227 BinopI { op=shr, lhs=v226, rhs_imm=3 } -> x1 - v228 Binop { op=add, lhs=v222, rhs=v227 } -> x0 + v224 Imm(8) -> x1 + v225 Imm(0) -> x1 + v226 Imm(7) -> x1 + v227 Imm(0) -> x1 + v228 BinopI { op=add, lhs=v222, rhs_imm=0 } -> x0 v229 Load { addr=v228, disp=0, kind=U8 } -> x0 v230 Imm(1) -> x1 v231 Imm(128) -> x1 v232 Imm(549755813888) -> x1 v233 BinopI { op=and, lhs=v229, rhs_imm=128 } -> x0 - terminator Bz { cond=v233, target=b46, fall=b45 } (exit_acc=v233) - block 45 start_pc=0 + terminator Bz { cond=v233, target=b39, fall=b38 } (exit_acc=v233) + block 38 start_pc=0 v234 Imm(21) -> x0 terminator Return(v234) (exit_acc=v234) - block 46 start_pc=0 + block 39 start_pc=0 v235 LocalAddr(-16) -> x0 v236 Imm(0) -> x1 - v237 Imm(8) -> x2 - v238 Binop { op=add, lhs=v236, rhs=v236 } -> x1 - v239 BinopI { op=shr, lhs=v238, rhs_imm=3 } -> x1 - v240 Binop { op=add, lhs=v235, rhs=v239 } -> x0 + v237 Imm(8) -> x1 + v238 Imm(0) -> x1 + v239 Imm(0) -> x1 + v240 BinopI { op=add, lhs=v235, rhs_imm=0 } -> x0 v241 Load { addr=v240, disp=0, kind=U8 } -> x0 v242 Imm(1) -> x1 v243 Imm(4294967296) -> x1 v244 BinopI { op=and, lhs=v241, rhs_imm=1 } -> x0 v245 BinopI { op=eq, lhs=v244, rhs_imm=0 } -> x0 - terminator Bz { cond=v245, target=b48, fall=b47 } (exit_acc=v245) - block 47 start_pc=0 + terminator Bz { cond=v245, target=b41, fall=b40 } (exit_acc=v245) + block 40 start_pc=0 v246 Imm(22) -> x0 terminator Return(v246) (exit_acc=v246) - block 48 start_pc=0 + block 41 start_pc=0 v247 LocalAddr(-16) -> x0 v248 Imm(8) -> x1 - v249 Imm(0) -> x2 - v250 Binop { op=add, lhs=v248, rhs=v249 } -> x1 - v251 BinopI { op=shr, lhs=v250, rhs_imm=3 } -> x1 - v252 Binop { op=add, lhs=v247, rhs=v251 } -> x0 - v253 Load { addr=v252, disp=0, kind=U8 } -> x0 + v249 Imm(0) -> x1 + v250 Imm(8) -> x1 + v251 Imm(1) -> x1 + v252 BinopI { op=add, lhs=v247, rhs_imm=1 } -> x1 + v253 Load { addr=v247, disp=1, kind=U8 } -> x0 v254 Imm(1) -> x1 v255 Imm(4294967296) -> x1 v256 BinopI { op=and, lhs=v253, rhs_imm=1 } -> x0 v257 BinopI { op=eq, lhs=v256, rhs_imm=0 } -> x0 - terminator Bz { cond=v257, target=b50, fall=b49 } (exit_acc=v257) - block 49 start_pc=0 + terminator Bz { cond=v257, target=b43, fall=b42 } (exit_acc=v257) + block 42 start_pc=0 v258 Imm(23) -> x0 terminator Return(v258) (exit_acc=v258) - block 50 start_pc=0 - terminator Jmp(b51) - block 51 start_pc=0 + block 43 start_pc=0 v259 LocalAddr(-16) -> x0 v260 Imm(0) -> x1 v261 LoadLocal { off=-26, kind=I64 } -> x1 v262 Imm(0) -> x1 - v263 Imm(8) -> x2 - v264 Binop { op=add, lhs=v262, rhs=v262 } -> x1 - v265 BinopI { op=shr, lhs=v264, rhs_imm=3 } -> x1 - v266 Binop { op=add, lhs=v259, rhs=v265 } -> x0 + v263 Imm(8) -> x1 + v264 Imm(0) -> x1 + v265 Imm(0) -> x1 + v266 BinopI { op=add, lhs=v259, rhs_imm=0 } -> x0 v267 Load { addr=v266, disp=0, kind=U8 } -> x1 v268 Imm(1) -> x2 v269 Imm(4294967296) -> x2 v270 BinopI { op=or, lhs=v267, rhs_imm=1 } -> x1 v271 Store { addr=v266, disp=0, value=v270, kind=I8 } -> - v272 BinopI { op=and, lhs=v270, rhs_imm=255 } -> x0 - terminator Jmp(b52) (exit_acc=v272) - block 52 start_pc=0 + terminator Jmp(b44) (exit_acc=v272) + block 44 start_pc=0 v273 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v273) - block 53 start_pc=0 + terminator Jmp(b45) (exit_acc=v273) + block 45 start_pc=0 v274 LocalAddr(-16) -> x0 v275 Imm(0) -> x1 - v276 Imm(8) -> x2 - v277 Binop { op=add, lhs=v275, rhs=v275 } -> x1 - v278 BinopI { op=shr, lhs=v277, rhs_imm=3 } -> x1 - v279 Binop { op=add, lhs=v274, rhs=v278 } -> x0 + v276 Imm(8) -> x1 + v277 Imm(0) -> x1 + v278 Imm(0) -> x1 + v279 BinopI { op=add, lhs=v274, rhs_imm=0 } -> x0 v280 Load { addr=v279, disp=0, kind=U8 } -> x0 v281 Imm(1) -> x1 v282 Imm(4294967296) -> x1 v283 BinopI { op=and, lhs=v280, rhs_imm=1 } -> x0 v284 BinopI { op=eq, lhs=v283, rhs_imm=0 } -> x0 - terminator Bz { cond=v284, target=b55, fall=b54 } (exit_acc=v284) - block 54 start_pc=0 + terminator Bz { cond=v284, target=b47, fall=b46 } (exit_acc=v284) + block 46 start_pc=0 v285 Imm(24) -> x0 terminator Return(v285) (exit_acc=v285) - block 55 start_pc=0 - terminator Jmp(b56) - block 56 start_pc=0 + block 47 start_pc=0 v286 LocalAddr(-16) -> x0 v287 Imm(0) -> x1 v288 Imm(0) -> x2 v289 Imm(0) -> x1 - terminator Jmp(b59) (exit_acc=v288) - block 57 start_pc=0 - v290 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v290) - block 58 start_pc=0 - v291 LocalAddr(-16) -> x0 - v292 Imm(0) -> x1 - v293 Imm(8) -> x2 - v294 Binop { op=add, lhs=v292, rhs=v292 } -> x1 - v295 BinopI { op=shr, lhs=v294, rhs_imm=3 } -> x1 - v296 Binop { op=add, lhs=v291, rhs=v295 } -> x0 - v297 Load { addr=v296, disp=0, kind=U8 } -> x0 - v298 Imm(1) -> x1 - v299 Imm(4294967296) -> x1 - v300 BinopI { op=and, lhs=v297, rhs_imm=1 } -> x0 - terminator Bz { cond=v300, target=b63, fall=b62 } (exit_acc=v300) - block 59 start_pc=0 - v301 Phi { incoming=[b56:v288, b60:v312], kind=I64 } -> x2 - v302 Extend { value=v301, kind=I32 } -> x1 - v303 BinopI { op=lt, lhs=v302, rhs_imm=128 } -> x1 - terminator Bz { cond=v303, target=b61, fall=b60 } (exit_acc=v303) - block 60 start_pc=0 - v304 LoadLocal { off=-27, kind=I64 } -> x1 - v305 Extend { value=v301, kind=I32 } -> x1 - v306 Binop { op=add, lhs=v286, rhs=v305 } -> x1 + terminator Jmp(b49) (exit_acc=v288) + block 48 start_pc=0 + v304 LoadLocal { off=-27, kind=I64 } -> x6 + v305 Extend { value=v301, kind=I32 } -> x6 + v306 Binop { op=add, lhs=v286, rhs=v302 } -> x1 v307 Imm(0) -> x6 v308 Store { addr=v306, disp=0, value=v307, kind=I8 } -> - v309 Extend { value=v301, kind=I32 } -> x1 @@ -437,35 +398,74 @@ fn ent_pc=1 n_params=0 variadic=false locals=29 v311 BinopI { op=shl, lhs=v310, rhs_imm=32 } -> x2 v312 Extend { value=v310, kind=I32 } -> x2 v313 Imm(0) -> x1 - terminator Jmp(b59) (exit_acc=v312) - block 61 start_pc=0 - terminator Jmp(b57) - block 62 start_pc=0 + terminator Jmp(b49) (exit_acc=v312) + block 49 start_pc=0 + v301 Phi { incoming=[b47:v288, b48:v312], kind=I64 } -> x2 + v302 Extend { value=v301, kind=I32 } -> x1 + v303 BinopI { op=lt, lhs=v302, rhs_imm=128 } -> x6 + terminator Bnz { cond=v303, target=b48, fall=b50 } (exit_acc=v303) + block 50 start_pc=0 + v290 Imm(0) -> x0 + terminator Jmp(b51) (exit_acc=v290) + block 51 start_pc=0 + v291 LocalAddr(-16) -> x0 + v292 Imm(0) -> x1 + v293 Imm(8) -> x1 + v294 Imm(0) -> x1 + v295 Imm(0) -> x1 + v296 BinopI { op=add, lhs=v291, rhs_imm=0 } -> x0 + v297 Load { addr=v296, disp=0, kind=U8 } -> x0 + v298 Imm(1) -> x1 + v299 Imm(4294967296) -> x1 + v300 BinopI { op=and, lhs=v297, rhs_imm=1 } -> x0 + terminator Bz { cond=v300, target=b53, fall=b52 } (exit_acc=v300) + block 52 start_pc=0 v314 Imm(25) -> x0 terminator Return(v314) (exit_acc=v314) - block 63 start_pc=0 + block 53 start_pc=0 v315 LocalAddr(-16) -> x0 v316 Imm(100) -> x1 - v317 Imm(8) -> x2 - v318 Imm(0) -> x2 - v319 Binop { op=add, lhs=v316, rhs=v318 } -> x1 - v320 BinopI { op=shr, lhs=v319, rhs_imm=3 } -> x1 - v321 Binop { op=add, lhs=v315, rhs=v320 } -> x0 - v322 Load { addr=v321, disp=0, kind=U8 } -> x0 + v317 Imm(8) -> x1 + v318 Imm(0) -> x1 + v319 Imm(100) -> x1 + v320 Imm(12) -> x1 + v321 BinopI { op=add, lhs=v315, rhs_imm=12 } -> x1 + v322 Load { addr=v315, disp=12, kind=U8 } -> x0 v323 Imm(1) -> x1 v324 Imm(4) -> x1 v325 Imm(16) -> x1 v326 Imm(68719476736) -> x1 v327 BinopI { op=and, lhs=v322, rhs_imm=16 } -> x0 - terminator Bz { cond=v327, target=b65, fall=b64 } (exit_acc=v327) - block 64 start_pc=0 + terminator Bz { cond=v327, target=b55, fall=b54 } (exit_acc=v327) + block 54 start_pc=0 v328 Imm(26) -> x0 terminator Return(v328) (exit_acc=v328) - block 65 start_pc=0 + block 55 start_pc=0 v329 ImmData(36) -> x7 v330 CallExt { binding_idx=0, args=[v329], fp_arg_mask=0x0 } -> x0 v331 Imm(0) -> x0 terminator Return(v331) (exit_acc=v331) + block 56 start_pc=0 + v29 Imm(1) -> x0 + terminator Return(v29) (exit_acc=v29) + block 57 start_pc=0 + terminator Jmp(b4) + block 58 start_pc=0 + terminator Jmp(b9) + block 59 start_pc=0 + terminator Jmp(b11) + block 60 start_pc=0 + terminator Jmp(b13) + block 61 start_pc=0 + terminator Jmp(b15) + block 62 start_pc=0 + terminator Jmp(b35) + block 63 start_pc=0 + terminator Jmp(b43) + block 64 start_pc=0 + terminator Jmp(b47) + block 65 start_pc=0 + terminator Jmp(b50) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fib.ssa b/tests/snapshots/ssa/fib.ssa index ad25dccba..0433ca47b 100644 --- a/tests/snapshots/ssa/fib.ssa +++ b/tests/snapshots/ssa/fib.ssa @@ -14,15 +14,15 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 terminator Return(v1) (exit_acc=v1) block 2 start_pc=0 v6 LoadLocal { off=2, kind=I32 } -> x0 - v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x7 - v10 Call { target_pc=0, args=[v9], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 v11 LoadLocal { off=2, kind=I32 } -> x0 - v12 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x7 - v15 Call { target_pc=0, args=[v14], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v12 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x7 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x0 + v14 Extend { value=v12, kind=I32 } -> x0 + v15 Call { target_pc=0, args=[v12], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v16 Binop { op=add, lhs=v10, rhs=v15 } -> x0 terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=1 --- diff --git a/tests/snapshots/ssa/flex_array_member_sizing.ssa b/tests/snapshots/ssa/flex_array_member_sizing.ssa index 7822dcc52..d2485deb3 100644 --- a/tests/snapshots/ssa/flex_array_member_sizing.ssa +++ b/tests/snapshots/ssa/flex_array_member_sizing.ssa @@ -5,23 +5,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 LocalAddr(-2) -> x0 v8 Imm(0) -> x1 v9 LoadLocal { off=-1, kind=I64 } -> x1 @@ -37,11 +28,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v19 BinopI { op=xor, lhs=v18, rhs_imm=287454020 } -> x1 v20 BinopI { op=and, lhs=v19, rhs_imm=4294967295 } -> x1 v21 BinopI { op=ne, lhs=v20, rhs_imm=0 } -> x1 - terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) - block 7 start_pc=0 + terminator Bz { cond=v21, target=b5, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v22 Imm(4) -> x0 terminator Return(v22) (exit_acc=v22) - block 8 start_pc=0 + block 5 start_pc=0 v23 LoadLocal { off=-1, kind=I64 } -> x1 v24 BinopI { op=add, lhs=v7, rhs_imm=4 } -> x1 v25 Imm(0) -> x1 @@ -49,24 +40,33 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v27 BinopI { op=xor, lhs=v26, rhs_imm=48879 } -> x0 v28 BinopI { op=and, lhs=v27, rhs_imm=4294967295 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=0 } -> x0 - terminator Bz { cond=v29, target=b10, fall=b9 } (exit_acc=v29) - block 9 start_pc=0 + terminator Bz { cond=v29, target=b7, fall=b6 } (exit_acc=v29) + block 6 start_pc=0 v30 Imm(5) -> x0 terminator Return(v30) (exit_acc=v30) - block 10 start_pc=0 + block 7 start_pc=0 v31 LocalAddr(-2) -> x0 v32 BinopI { op=add, lhs=v31, rhs_imm=4 } -> x1 v33 Load { addr=v31, disp=4, kind=U16 } -> x0 v34 BinopI { op=xor, lhs=v33, rhs_imm=48879 } -> x0 v35 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) - block 11 start_pc=0 + terminator Bz { cond=v36, target=b9, fall=b8 } (exit_acc=v36) + block 8 start_pc=0 v37 Imm(6) -> x0 terminator Return(v37) (exit_acc=v37) - block 12 start_pc=0 + block 9 start_pc=0 v38 Imm(0) -> x0 terminator Return(v38) (exit_acc=v38) + block 10 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 11 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 12 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/flex_array_member_static_init.ssa b/tests/snapshots/ssa/flex_array_member_static_init.ssa index 4c75789ca..1feae0a50 100644 --- a/tests/snapshots/ssa/flex_array_member_static_init.ssa +++ b/tests/snapshots/ssa/flex_array_member_static_init.ssa @@ -26,78 +26,75 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v12 Mcpy { dst=v10, src=v11, size=8 } -> x1 v13 Imm(0) -> x2 v14 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v13) + terminator Jmp(b7) (exit_acc=v13) block 5 start_pc=0 - v15 Phi { incoming=[b4:v13, b6:v19], kind=I64 } -> x2 - v16 Extend { value=v15, kind=I32 } -> x1 - v17 BinopI { op=lt, lhs=v16, rhs_imm=8 } -> x1 - terminator Bz { cond=v17, target=b8, fall=b7 } (exit_acc=v17) + v21 ImmData(8) -> x6 + v22 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x6 + v23 Extend { value=v15, kind=I32 } -> x7 + v24 Binop { op=add, lhs=v22, rhs=v16 } -> x6 + v25 Load { addr=v24, disp=0, kind=I8 } -> x6 + v26 LocalAddr(-1) -> x7 + v27 Extend { value=v15, kind=I32 } -> x8 + v28 Binop { op=add, lhs=v26, rhs=v16 } -> x7 + v29 Load { addr=v28, disp=0, kind=I8 } -> x7 + v30 Binop { op=ne, lhs=v25, rhs=v29 } -> x6 + terminator Bnz { cond=v30, target=b18, fall=b6 } (exit_acc=v30) block 6 start_pc=0 - v18 Extend { value=v15, kind=I32 } -> x1 - v19 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x2 + v18 Extend { value=v15, kind=I32 } -> x2 + v19 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x2 v20 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v19) + terminator Jmp(b7) (exit_acc=v19) block 7 start_pc=0 - v21 ImmData(8) -> x1 - v22 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x1 - v23 Extend { value=v15, kind=I32 } -> x6 - v24 Binop { op=add, lhs=v22, rhs=v23 } -> x1 - v25 Load { addr=v24, disp=0, kind=I8 } -> x1 - v26 LocalAddr(-1) -> x6 - v27 Extend { value=v15, kind=I32 } -> x7 - v28 Binop { op=add, lhs=v26, rhs=v27 } -> x6 - v29 Load { addr=v28, disp=0, kind=I8 } -> x6 - v30 Binop { op=ne, lhs=v25, rhs=v29 } -> x1 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v15 Phi { incoming=[b4:v13, b6:v19], kind=I64 } -> x2 + v16 Extend { value=v15, kind=I32 } -> x1 + v17 BinopI { op=lt, lhs=v16, rhs_imm=8 } -> x6 + terminator Bnz { cond=v17, target=b5, fall=b8 } (exit_acc=v17) block 8 start_pc=0 v31 ImmData(40) -> x0 v32 Load { addr=v31, disp=0, kind=I32 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=5 } -> x0 - terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) + terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) block 9 start_pc=0 - v34 Imm(10) -> x0 - v35 Extend { value=v15, kind=I32 } -> x0 - v36 BinopI { op=add, lhs=v15, rhs_imm=10 } -> x0 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 - v38 Extend { value=v36, kind=I32 } -> x0 - terminator Return(v38) (exit_acc=v38) - block 10 start_pc=0 - terminator Jmp(b6) - block 11 start_pc=0 v39 Imm(20) -> x0 terminator Return(v39) (exit_acc=v39) - block 12 start_pc=0 + block 10 start_pc=0 v40 ImmData(72) -> x0 v41 Imm(0) -> x1 v42 Imm(0) -> x2 v43 Imm(0) -> x1 terminator Jmp(b13) (exit_acc=v42) + block 11 start_pc=0 + v50 ImmData(40) -> x6 + v51 BinopI { op=add, lhs=v50, rhs_imm=4 } -> x6 + v52 Extend { value=v44, kind=I32 } -> x7 + v53 Binop { op=add, lhs=v51, rhs=v45 } -> x6 + v54 Load { addr=v53, disp=0, kind=I8 } -> x6 + v55 LoadLocal { off=-3, kind=I64 } -> x7 + v56 Binop { op=add, lhs=v40, rhs=v45 } -> x7 + v57 Load { addr=v56, disp=0, kind=I8 } -> x7 + v58 Binop { op=ne, lhs=v54, rhs=v57 } -> x6 + terminator Bnz { cond=v58, target=b17, fall=b12 } (exit_acc=v58) + block 12 start_pc=0 + v47 Extend { value=v44, kind=I32 } -> x2 + v48 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x2 + v49 Imm(0) -> x1 + terminator Jmp(b13) (exit_acc=v48) block 13 start_pc=0 - v44 Phi { incoming=[b12:v42, b14:v48], kind=I64 } -> x2 + v44 Phi { incoming=[b10:v42, b12:v48], kind=I64 } -> x2 v45 Extend { value=v44, kind=I32 } -> x1 - v46 BinopI { op=lt, lhs=v45, rhs_imm=6 } -> x1 - terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) + v46 BinopI { op=lt, lhs=v45, rhs_imm=6 } -> x6 + terminator Bnz { cond=v46, target=b11, fall=b14 } (exit_acc=v46) block 14 start_pc=0 - v47 Extend { value=v44, kind=I32 } -> x1 - v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x2 - v49 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v48) - block 15 start_pc=0 - v50 ImmData(40) -> x1 - v51 BinopI { op=add, lhs=v50, rhs_imm=4 } -> x1 - v52 Extend { value=v44, kind=I32 } -> x6 - v53 Binop { op=add, lhs=v51, rhs=v52 } -> x1 - v54 Load { addr=v53, disp=0, kind=I8 } -> x1 - v55 LoadLocal { off=-3, kind=I64 } -> x7 - v56 Binop { op=add, lhs=v40, rhs=v52 } -> x6 - v57 Load { addr=v56, disp=0, kind=I8 } -> x6 - v58 Binop { op=ne, lhs=v54, rhs=v57 } -> x1 - terminator Bz { cond=v58, target=b18, fall=b17 } (exit_acc=v58) - block 16 start_pc=0 v59 ImmData(56) -> x0 v60 Load { addr=v59, disp=0, kind=I32 } -> x0 v61 BinopI { op=ne, lhs=v60, rhs_imm=305419896 } -> x0 - terminator Bz { cond=v61, target=b20, fall=b19 } (exit_acc=v61) + terminator Bz { cond=v61, target=b16, fall=b15 } (exit_acc=v61) + block 15 start_pc=0 + v67 Imm(40) -> x0 + terminator Return(v67) (exit_acc=v67) + block 16 start_pc=0 + v68 Imm(0) -> x0 + terminator Return(v68) (exit_acc=v68) block 17 start_pc=0 v62 Imm(30) -> x0 v63 Extend { value=v44, kind=I32 } -> x0 @@ -106,13 +103,16 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v66 Extend { value=v64, kind=I32 } -> x0 terminator Return(v66) (exit_acc=v66) block 18 start_pc=0 - terminator Jmp(b14) + v34 Imm(10) -> x0 + v35 Extend { value=v15, kind=I32 } -> x0 + v36 BinopI { op=add, lhs=v15, rhs_imm=10 } -> x0 + v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 + v38 Extend { value=v36, kind=I32 } -> x0 + terminator Return(v38) (exit_acc=v38) block 19 start_pc=0 - v67 Imm(40) -> x0 - terminator Return(v67) (exit_acc=v67) + terminator Jmp(b6) block 20 start_pc=0 - v68 Imm(0) -> x0 - terminator Return(v68) (exit_acc=v68) + terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/flexible_array_member.ssa b/tests/snapshots/ssa/flexible_array_member.ssa index e096da6aa..a4352ddbc 100644 --- a/tests/snapshots/ssa/flexible_array_member.ssa +++ b/tests/snapshots/ssa/flexible_array_member.ssa @@ -5,17 +5,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 LocalAddr(-10) -> x0 v6 Imm(0) -> x1 v7 LoadLocal { off=-11, kind=I64 } -> x1 @@ -37,43 +31,49 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 v23 LoadLocal { off=-11, kind=I64 } -> x2 v24 Extend { value=v8, kind=I32 } -> x1 v25 BinopI { op=ne, lhs=v24, rhs_imm=2 } -> x1 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) - block 5 start_pc=0 + terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + block 3 start_pc=0 v26 Imm(3) -> x0 terminator Return(v26) (exit_acc=v26) - block 6 start_pc=0 + block 4 start_pc=0 v27 LoadLocal { off=-11, kind=I64 } -> x1 v28 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 v29 Imm(0) -> x1 v30 Load { addr=v5, disp=4, kind=I8 } -> x1 v31 BinopI { op=ne, lhs=v30, rhs_imm=1 } -> x1 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) - block 7 start_pc=0 + terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) + block 5 start_pc=0 v32 Imm(4) -> x0 terminator Return(v32) (exit_acc=v32) - block 8 start_pc=0 + block 6 start_pc=0 v33 LoadLocal { off=-11, kind=I64 } -> x1 v34 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 v35 Imm(3) -> x1 v36 BinopI { op=add, lhs=v5, rhs_imm=7 } -> x1 v37 Load { addr=v5, disp=7, kind=I8 } -> x1 v38 BinopI { op=ne, lhs=v37, rhs_imm=9 } -> x1 - terminator Bz { cond=v38, target=b10, fall=b9 } (exit_acc=v38) - block 9 start_pc=0 + terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + block 7 start_pc=0 v39 Imm(5) -> x0 terminator Return(v39) (exit_acc=v39) - block 10 start_pc=0 + block 8 start_pc=0 v40 LoadLocal { off=-11, kind=I64 } -> x1 v41 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 v42 Binop { op=sub, lhs=v41, rhs=v5 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=4 } -> x0 - terminator Bz { cond=v43, target=b12, fall=b11 } (exit_acc=v43) - block 11 start_pc=0 + terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) + block 9 start_pc=0 v44 Imm(6) -> x0 terminator Return(v44) (exit_acc=v44) - block 12 start_pc=0 + block 10 start_pc=0 v45 Imm(0) -> x0 terminator Return(v45) (exit_acc=v45) + block 11 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 12 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_arg_single_precision.ssa b/tests/snapshots/ssa/float_arg_single_precision.ssa index d1bd069b6..eeaae9d5d 100644 --- a/tests/snapshots/ssa/float_arg_single_precision.ssa +++ b/tests/snapshots/ssa/float_arg_single_precision.ssa @@ -36,86 +36,73 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4609434218613702656) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4598175219545276416) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d1 [f32] - v5 Imm(0) -> x0 + v1 Imm(1069547520) -> x0 [f32] + v2 Imm(1048576000) -> x1 [f32] + v3 Imm(0) -> x2 + v4 Imm(0) -> x2 + v5 Binop { op=fmul, lhs=v1, rhs=v2 } -> d0 [f32] v6 Imm(0) -> x0 - v7 Binop { op=fmul, lhs=v2, rhs=v4 } -> d0 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v10 Imm(4600427019358961664) -> x0 - v11 FpCast { kind=F32ToF64, value=v7 } -> d0 - v12 Binop { op=fne, lhs=v11, rhs=v10 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v7 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v8 Imm(1052770304) -> x0 [f32] + v9 Binop { op=fne, lhs=v5, rhs=v8 } -> x0 + terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v10 Imm(1) -> x0 + terminator Return(v10) (exit_acc=v10) block 2 start_pc=0 - v14 Imm(4612811918334230528) -> x0 - v15 Fneg(v14) -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Imm(4616189618054758400) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Imm(0) -> x0 - v20 Imm(0) -> x0 - v21 Binop { op=fmul, lhs=v16, rhs=v18 } -> d0 [f32] - v22 Imm(0) -> x0 - v23 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v24 Imm(4621819117588971520) -> x0 - v25 Fneg(v24) -> d1 - v26 FpCast { kind=F32ToF64, value=v21 } -> d0 - v27 Binop { op=fne, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v11 Imm(1075838976) -> x0 [f32] + v12 Fneg(v11) -> d0 [f32] + v13 Imm(1082130432) -> x0 [f32] + v14 Imm(0) -> x1 + v15 Imm(0) -> x1 + v16 Binop { op=fmul, lhs=v12, rhs=v13 } -> d0 [f32] + v17 Imm(0) -> x0 + v18 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v19 Imm(1092616192) -> x0 [f32] + v20 Fneg(v19) -> d1 [f32] + v21 Binop { op=fne, lhs=v16, rhs=v20 } -> x0 + terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) block 3 start_pc=0 - v28 Imm(2) -> x0 - terminator Return(v28) (exit_acc=v28) + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) block 4 start_pc=0 - v29 Imm(4602678819172646912) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 Imm(4598175219545276416) -> x0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 Imm(4593671619917905920) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d2 [f32] - v35 Imm(0) -> x0 - v36 Imm(0) -> x0 - v37 Imm(0) -> x0 - v38 Binop { op=fadd, lhs=v30, rhs=v32 } -> d0 [f32] - v39 Binop { op=fadd, lhs=v38, rhs=v34 } -> d0 [f32] - v40 Imm(0) -> x0 - v41 LoadLocal { off=-3, kind=F32 } -> d1 [f32] - v42 Imm(4606056518893174784) -> x0 - v43 FpCast { kind=F32ToF64, value=v39 } -> d0 - v44 Binop { op=fne, lhs=v43, rhs=v42 } -> x0 - terminator Bz { cond=v44, target=b6, fall=b5 } (exit_acc=v44) + v23 Imm(1056964608) -> x0 [f32] + v24 Imm(1048576000) -> x1 [f32] + v25 Imm(1040187392) -> x2 [f32] + v26 Imm(0) -> x6 + v27 Imm(0) -> x6 + v28 Imm(0) -> x6 + v29 Binop { op=fadd, lhs=v23, rhs=v24 } -> d0 [f32] + v30 Binop { op=fadd, lhs=v29, rhs=v25 } -> d0 [f32] + v31 Imm(0) -> x0 + v32 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v33 Imm(1063256064) -> x0 [f32] + v34 Binop { op=fne, lhs=v30, rhs=v33 } -> x0 + terminator Bz { cond=v34, target=b6, fall=b5 } (exit_acc=v34) block 5 start_pc=0 - v45 Imm(3) -> x0 - terminator Return(v45) (exit_acc=v45) + v35 Imm(3) -> x0 + terminator Return(v35) (exit_acc=v35) block 6 start_pc=0 - v46 Imm(4607182418800017408) -> x0 - v47 Imm(4620693217682128896) -> x1 - v48 Binop { op=fdiv, lhs=v46, rhs=v47 } -> d0 - v49 FpCast { kind=F64ToF32, value=v48 } -> d0 [f32] - v50 Imm(0) -> x0 - v51 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v52 Imm(4625196817309499392) -> x0 - v53 FpCast { kind=F64ToF32, value=v52 } -> d1 [f32] - v54 Imm(0) -> x0 - v55 Imm(0) -> x0 - v56 Binop { op=fmul, lhs=v49, rhs=v53 } -> d0 [f32] - v57 Imm(0) -> x0 - v58 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v59 Imm(4611686018427387904) -> x0 - v60 FpCast { kind=F32ToF64, value=v56 } -> d0 - v61 Binop { op=fne, lhs=v60, rhs=v59 } -> x0 - terminator Bz { cond=v61, target=b8, fall=b7 } (exit_acc=v61) + v36 Imm(1065353216) -> x0 [f32] + v37 Imm(1090519040) -> x1 [f32] + v38 Binop { op=fdiv, lhs=v36, rhs=v37 } -> d0 [f32] + v39 Imm(0) -> x0 + v40 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v41 Imm(1098907648) -> x0 [f32] + v42 Imm(0) -> x1 + v43 Imm(0) -> x1 + v44 Binop { op=fmul, lhs=v38, rhs=v41 } -> d0 [f32] + v45 Imm(0) -> x0 + v46 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v47 Imm(1073741824) -> x0 [f32] + v48 Binop { op=fne, lhs=v44, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b8, fall=b7 } (exit_acc=v48) block 7 start_pc=0 - v62 Imm(4) -> x0 - terminator Return(v62) (exit_acc=v62) + v49 Imm(4) -> x0 + terminator Return(v49) (exit_acc=v49) block 8 start_pc=0 - v63 Imm(0) -> x0 - terminator Return(v63) (exit_acc=v63) + v50 Imm(0) -> x0 + terminator Return(v50) (exit_acc=v50) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_arith_in_static_init.ssa b/tests/snapshots/ssa/float_arith_in_static_init.ssa index 02f921fd9..f41bed584 100644 --- a/tests/snapshots/ssa/float_arith_in_static_init.ssa +++ b/tests/snapshots/ssa/float_arith_in_static_init.ssa @@ -7,76 +7,73 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 v1 ImmData(40) -> x0 v2 Imm(0) -> x1 v3 Load { addr=v1, disp=0, kind=F32 } -> d0 [f32] - v4 Imm(4611686018427387904) -> x1 - v5 FpCast { kind=F32ToF64, value=v3 } -> d0 - v6 Binop { op=fne, lhs=v5, rhs=v4 } -> x1 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(1073741824) -> x1 [f32] + v5 Binop { op=fne, lhs=v3, rhs=v4 } -> x1 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v8 ImmData(40) -> x1 - v9 Imm(4) -> x1 - v10 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 - v11 Load { addr=v1, disp=4, kind=F32 } -> d0 [f32] - v12 Imm(4612811918334230528) -> x1 - v13 Fneg(v12) -> d1 - v14 FpCast { kind=F32ToF64, value=v11 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v13 } -> x1 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v7 ImmData(40) -> x1 + v8 Imm(4) -> x1 + v9 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 + v10 Load { addr=v1, disp=4, kind=F32 } -> d0 [f32] + v11 Imm(1075838976) -> x1 [f32] + v12 Fneg(v11) -> d1 [f32] + v13 Binop { op=fne, lhs=v10, rhs=v12 } -> x1 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v17 ImmData(40) -> x1 - v18 Imm(8) -> x1 - v19 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 - v20 Load { addr=v1, disp=8, kind=F32 } -> d0 [f32] - v21 Imm(4622945017495814144) -> x0 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) + v15 ImmData(40) -> x1 + v16 Imm(8) -> x1 + v17 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 + v18 Load { addr=v1, disp=8, kind=F32 } -> d0 [f32] + v19 Imm(1094713344) -> x0 [f32] + v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x0 + terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) block 5 start_pc=0 - v24 Imm(3) -> x0 - terminator Return(v24) (exit_acc=v24) + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) block 6 start_pc=0 - v25 ImmData(56) -> x0 - v26 Imm(0) -> x1 - v27 Load { addr=v25, disp=0, kind=F64 } -> d0 - v28 Imm(4616009474069663580) -> x0 - v29 Binop { op=flt, lhs=v27, rhs=v28 } -> x1 - v30 Imm(0) -> x0 - terminator Bnz { cond=v29, target=b13, fall=b7 } (exit_acc=v29) + v22 ImmData(56) -> x0 + v23 Imm(0) -> x1 + v24 Load { addr=v22, disp=0, kind=F64 } -> d0 + v25 Imm(4616009474069663580) -> x0 + v26 Binop { op=flt, lhs=v24, rhs=v25 } -> x1 + v27 Imm(0) -> x0 + terminator Bnz { cond=v26, target=b13, fall=b7 } (exit_acc=v26) block 7 start_pc=0 - v31 ImmData(56) -> x0 - v32 Imm(0) -> x1 - v33 Load { addr=v31, disp=0, kind=F64 } -> d0 - v34 Imm(4616031992067800433) -> x0 - v35 Binop { op=fgt, lhs=v33, rhs=v34 } -> x1 - v36 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v35) + v28 ImmData(56) -> x0 + v29 Imm(0) -> x1 + v30 Load { addr=v28, disp=0, kind=F64 } -> d0 + v31 Imm(4616031992067800433) -> x0 + v32 Binop { op=fgt, lhs=v30, rhs=v31 } -> x1 + v33 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v32) block 8 start_pc=0 - v37 Phi { incoming=[b13:v29, b7:v35], kind=I64 } -> x1 - v38 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) + v34 Phi { incoming=[b13:v26, b7:v32], kind=I64 } -> x1 + v35 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v34, target=b10, fall=b9 } (exit_acc=v34) block 9 start_pc=0 - v39 Imm(4) -> x0 - terminator Return(v39) (exit_acc=v39) + v36 Imm(4) -> x0 + terminator Return(v36) (exit_acc=v36) block 10 start_pc=0 - v40 ImmData(56) -> x0 - v41 Imm(8) -> x1 - v42 BinopI { op=add, lhs=v40, rhs_imm=8 } -> x1 - v43 Load { addr=v40, disp=8, kind=F64 } -> d0 - v44 Imm(4604930618986332160) -> x0 - v45 Fneg(v44) -> d1 - v46 Binop { op=fne, lhs=v43, rhs=v45 } -> x0 - terminator Bz { cond=v46, target=b12, fall=b11 } (exit_acc=v46) + v37 ImmData(56) -> x0 + v38 Imm(8) -> x1 + v39 BinopI { op=add, lhs=v37, rhs_imm=8 } -> x1 + v40 Load { addr=v37, disp=8, kind=F64 } -> d0 + v41 Imm(4604930618986332160) -> x0 + v42 Fneg(v41) -> d1 + v43 Binop { op=fne, lhs=v40, rhs=v42 } -> x0 + terminator Bz { cond=v43, target=b12, fall=b11 } (exit_acc=v43) block 11 start_pc=0 - v47 Imm(5) -> x0 - terminator Return(v47) (exit_acc=v47) + v44 Imm(5) -> x0 + terminator Return(v44) (exit_acc=v44) block 12 start_pc=0 - v48 Imm(0) -> x0 - terminator Return(v48) (exit_acc=v48) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) block 13 start_pc=0 terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/float_condition_negative_zero.ssa b/tests/snapshots/ssa/float_condition_negative_zero.ssa index 9a09be4bc..acb11655e 100644 --- a/tests/snapshots/ssa/float_condition_negative_zero.ssa +++ b/tests/snapshots/ssa/float_condition_negative_zero.ssa @@ -1,189 +1,189 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=10 - spill_count=1 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x3 - v2 Fneg(v1) -> [spill 0] + v1 Imm(0) -> x1 + v2 Fneg(v1) -> d0 v3 Imm(0) -> x0 v4 StoreLocal { off=-2, value=v1, kind=F64 } -> - v5 Imm(0) -> x0 - v6 LoadLocal { off=-1, kind=F64 } -> d0 + v6 LoadLocal { off=-1, kind=F64 } -> d1 v7 Binop { op=fne, lhs=v2, rhs=v1 } -> x0 - terminator Bz { cond=v7, target=b31, fall=b1 } (exit_acc=v7) + terminator Bz { cond=v7, target=b39, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v8 LoadLocal { off=-3, kind=I32 } -> x0 - v9 BinopI { op=or, lhs=v1, rhs_imm=1 } -> x3 + v9 Imm(1) -> x1 v10 Imm(0) -> x0 - v11 Extend { value=v9, kind=I32 } -> x0 + v11 Imm(1) -> x0 terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v12 Phi { incoming=[b31:v1, b1:v9], kind=I64 } -> x3 - v13 LoadLocal { off=-2, kind=F64 } -> d0 - v14 LoadLocal { off=-1, kind=F64 } -> d1 + v12 Phi { incoming=[b39:v1, b1:v9], kind=I64 } -> x1 + v13 LoadLocal { off=-2, kind=F64 } -> d1 + v14 LoadLocal { off=-1, kind=F64 } -> d2 v15 Binop { op=feq, lhs=v13, rhs=v2 } -> x0 v16 BinopI { op=eq, lhs=v15, rhs_imm=0 } -> x0 - terminator Bz { cond=v16, target=b32, fall=b3 } (exit_acc=v16) + terminator Bz { cond=v16, target=b38, fall=b3 } (exit_acc=v16) block 3 start_pc=0 v17 Extend { value=v12, kind=I32 } -> x0 - v18 BinopI { op=or, lhs=v12, rhs_imm=2 } -> x3 + v18 BinopI { op=or, lhs=v12, rhs_imm=2 } -> x1 v19 Imm(0) -> x0 v20 Extend { value=v18, kind=I32 } -> x0 terminator Jmp(b4) (exit_acc=v20) block 4 start_pc=0 - v21 Phi { incoming=[b32:v12, b3:v18], kind=I64 } -> x3 - v22 Imm(0) -> x12 + v21 Phi { incoming=[b38:v12, b3:v18], kind=I64 } -> x1 + v22 Imm(0) -> x2 v23 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v22) + terminator Jmp(b7) (exit_acc=v22) block 5 start_pc=0 - v24 Phi { incoming=[b4:v22, b9:v29], kind=I64 } -> x12 - v25 LoadLocal { off=-1, kind=F64 } -> d0 - v26 Imm(0) -> x0 - v27 Binop { op=fne, lhs=v2, rhs=v26 } -> x0 - terminator Bz { cond=v27, target=b33, fall=b6 } (exit_acc=v27) - block 6 start_pc=0 v28 Extend { value=v24, kind=I32 } -> x0 - v29 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x12 + v29 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x2 v30 Imm(0) -> x0 v31 Extend { value=v29, kind=I32 } -> x0 v32 BinopI { op=gt, lhs=v31, rhs_imm=2 } -> x0 - terminator Bz { cond=v32, target=b9, fall=b8 } (exit_acc=v32) + terminator Bnz { cond=v32, target=b37, fall=b6 } (exit_acc=v32) + block 6 start_pc=0 + terminator Jmp(b7) block 7 start_pc=0 - v33 Phi { incoming=[b33:v24, b8:v29], kind=I64 } -> x12 - v34 Extend { value=v33, kind=I32 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x0 - terminator Bz { cond=v35, target=b34, fall=b10 } (exit_acc=v35) + v24 Phi { incoming=[b4:v22, b6:v29], kind=I64 } -> x2 + v25 LoadLocal { off=-1, kind=F64 } -> d1 + v26 Imm(0) -> x0 + v27 Binop { op=fne, lhs=v2, rhs=v26 } -> x0 + terminator Bnz { cond=v27, target=b5, fall=b8 } (exit_acc=v27) block 8 start_pc=0 - terminator Jmp(b7) + terminator Jmp(b9) block 9 start_pc=0 - terminator Jmp(b5) + v33 Phi { incoming=[b8:v24, b37:v29], kind=I64 } -> x2 + v34 Extend { value=v33, kind=I32 } -> x0 + v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x0 + terminator Bz { cond=v35, target=b36, fall=b10 } (exit_acc=v35) block 10 start_pc=0 v36 Extend { value=v21, kind=I32 } -> x0 - v37 BinopI { op=or, lhs=v21, rhs_imm=4 } -> x3 + v37 BinopI { op=or, lhs=v21, rhs_imm=4 } -> x1 v38 Imm(0) -> x0 v39 Extend { value=v37, kind=I32 } -> x0 terminator Jmp(b11) (exit_acc=v39) block 11 start_pc=0 - v40 Phi { incoming=[b34:v21, b10:v37], kind=I64 } -> x3 + v40 Phi { incoming=[b36:v21, b10:v37], kind=I64 } -> x1 terminator Jmp(b12) block 12 start_pc=0 - v41 LoadLocal { off=-1, kind=F64 } -> d0 + v41 LoadLocal { off=-1, kind=F64 } -> d1 v42 Imm(0) -> x0 v43 Binop { op=fne, lhs=v2, rhs=v42 } -> x0 - terminator Bz { cond=v43, target=b35, fall=b14 } (exit_acc=v43) + terminator Bz { cond=v43, target=b35, fall=b13 } (exit_acc=v43) block 13 start_pc=0 - terminator Jmp(b12) - block 14 start_pc=0 v44 Extend { value=v40, kind=I32 } -> x0 - v45 BinopI { op=or, lhs=v40, rhs_imm=8 } -> x3 + v45 BinopI { op=or, lhs=v40, rhs_imm=8 } -> x1 v46 Imm(0) -> x0 v47 Extend { value=v45, kind=I32 } -> x0 - terminator Jmp(b15) (exit_acc=v47) - block 15 start_pc=0 - v48 Phi { incoming=[b35:v40, b14:v45], kind=I64 } -> x3 - v49 LoadLocal { off=-1, kind=F64 } -> d0 + terminator Jmp(b14) (exit_acc=v47) + block 14 start_pc=0 + v48 Phi { incoming=[b35:v40, b13:v45], kind=I64 } -> x1 + v49 LoadLocal { off=-1, kind=F64 } -> d1 v50 Imm(0) -> x0 v51 Binop { op=fne, lhs=v2, rhs=v50 } -> x0 - terminator Bz { cond=v51, target=b17, fall=b16 } (exit_acc=v51) - block 16 start_pc=0 - v52 Imm(1) -> x1 + terminator Bz { cond=v51, target=b34, fall=b15 } (exit_acc=v51) + block 15 start_pc=0 + v52 Imm(1) -> x2 v53 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v52) - block 17 start_pc=0 - v54 Imm(0) -> x1 - v55 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v54) - block 18 start_pc=0 - v56 Phi { incoming=[b16:v52, b17:v54], kind=I64 } -> x1 + terminator Jmp(b16) (exit_acc=v52) + block 16 start_pc=0 + v56 Phi { incoming=[b15:v52, b34:v54], kind=I64 } -> x2 v57 LoadLocal { off=-8, kind=I64 } -> x0 v58 Imm(0) -> x0 v59 Extend { value=v56, kind=I32 } -> x0 v60 BinopI { op=ne, lhs=v59, rhs_imm=0 } -> x0 - terminator Bz { cond=v60, target=b36, fall=b19 } (exit_acc=v60) - block 19 start_pc=0 + terminator Bz { cond=v60, target=b33, fall=b17 } (exit_acc=v60) + block 17 start_pc=0 v61 Extend { value=v48, kind=I32 } -> x0 - v62 BinopI { op=or, lhs=v48, rhs_imm=16 } -> x3 + v62 BinopI { op=or, lhs=v48, rhs_imm=16 } -> x1 v63 Imm(0) -> x0 v64 Extend { value=v62, kind=I32 } -> x0 - terminator Jmp(b20) (exit_acc=v64) - block 20 start_pc=0 - v65 Phi { incoming=[b36:v48, b19:v62], kind=I64 } -> x3 - v66 LoadLocal { off=-1, kind=F64 } -> d0 + terminator Jmp(b18) (exit_acc=v64) + block 18 start_pc=0 + v65 Phi { incoming=[b33:v48, b17:v62], kind=I64 } -> x1 + v66 LoadLocal { off=-1, kind=F64 } -> d1 v67 Imm(0) -> x0 - v68 Binop { op=fne, lhs=v2, rhs=v67 } -> x12 + v68 Binop { op=fne, lhs=v2, rhs=v67 } -> x2 v69 Imm(0) -> x0 - terminator Bz { cond=v68, target=b37, fall=b21 } (exit_acc=v68) - block 21 start_pc=0 - v70 Imm(1) -> x12 + terminator Bz { cond=v68, target=b32, fall=b19 } (exit_acc=v68) + block 19 start_pc=0 + v70 Imm(1) -> x2 v71 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v70) - block 22 start_pc=0 - v72 Phi { incoming=[b37:v68, b21:v70], kind=I64 } -> x12 + terminator Jmp(b20) (exit_acc=v70) + block 20 start_pc=0 + v72 Phi { incoming=[b32:v68, b19:v70], kind=I64 } -> x2 v73 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v72, target=b38, fall=b23 } (exit_acc=v72) - block 23 start_pc=0 + terminator Bz { cond=v72, target=b31, fall=b21 } (exit_acc=v72) + block 21 start_pc=0 v74 Extend { value=v65, kind=I32 } -> x0 - v75 BinopI { op=or, lhs=v65, rhs_imm=32 } -> x3 + v75 BinopI { op=or, lhs=v65, rhs_imm=32 } -> x1 v76 Imm(0) -> x0 v77 Extend { value=v75, kind=I32 } -> x0 - terminator Jmp(b24) (exit_acc=v77) - block 24 start_pc=0 - v78 Phi { incoming=[b38:v65, b23:v75], kind=I64 } -> x3 - v79 LoadLocal { off=-1, kind=F64 } -> d0 + terminator Jmp(b22) (exit_acc=v77) + block 22 start_pc=0 + v78 Phi { incoming=[b31:v65, b21:v75], kind=I64 } -> x1 + v79 LoadLocal { off=-1, kind=F64 } -> d1 v80 Imm(0) -> x0 - v81 Binop { op=fne, lhs=v2, rhs=v80 } -> x12 + v81 Binop { op=fne, lhs=v2, rhs=v80 } -> x2 v82 Imm(0) -> x0 - terminator Bnz { cond=v81, target=b39, fall=b25 } (exit_acc=v81) - block 25 start_pc=0 - v83 Imm(0) -> x12 + terminator Bnz { cond=v81, target=b30, fall=b23 } (exit_acc=v81) + block 23 start_pc=0 + v83 Imm(0) -> x2 v84 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v83) - block 26 start_pc=0 - v85 Phi { incoming=[b39:v81, b25:v83], kind=I64 } -> x12 + terminator Jmp(b24) (exit_acc=v83) + block 24 start_pc=0 + v85 Phi { incoming=[b30:v81, b23:v83], kind=I64 } -> x2 v86 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v85, target=b40, fall=b27 } (exit_acc=v85) - block 27 start_pc=0 + terminator Bz { cond=v85, target=b29, fall=b25 } (exit_acc=v85) + block 25 start_pc=0 v87 Extend { value=v78, kind=I32 } -> x0 - v88 BinopI { op=or, lhs=v78, rhs_imm=64 } -> x3 + v88 BinopI { op=or, lhs=v78, rhs_imm=64 } -> x1 v89 Imm(0) -> x0 v90 Extend { value=v88, kind=I32 } -> x0 - terminator Jmp(b28) (exit_acc=v90) - block 28 start_pc=0 - v91 Phi { incoming=[b40:v78, b27:v88], kind=I64 } -> x3 + terminator Jmp(b26) (exit_acc=v90) + block 26 start_pc=0 + v91 Phi { incoming=[b29:v78, b25:v88], kind=I64 } -> x1 v92 Extend { value=v91, kind=I32 } -> x0 - terminator Bz { cond=v92, target=b30, fall=b29 } (exit_acc=v92) - block 29 start_pc=0 + terminator Bz { cond=v92, target=b28, fall=b27 } (exit_acc=v92) + block 27 start_pc=0 v93 ImmData(36) -> x7 v94 Extend { value=v91, kind=I32 } -> x6 v95 CallExt { binding_idx=0, args=[v93, v94], fp_arg_mask=0x0 } -> x0 v96 Imm(1) -> x0 terminator Return(v96) (exit_acc=v96) - block 30 start_pc=0 + block 28 start_pc=0 v97 ImmData(50) -> x7 v98 CallExt { binding_idx=0, args=[v97], fp_arg_mask=0x0 } -> x0 v99 Imm(0) -> x0 terminator Return(v99) (exit_acc=v99) + block 29 start_pc=0 + terminator Jmp(b26) + block 30 start_pc=0 + terminator Jmp(b24) block 31 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b22) block 32 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b20) block 33 start_pc=0 - terminator Jmp(b7) + terminator Jmp(b18) block 34 start_pc=0 - terminator Jmp(b11) + v54 Imm(0) -> x2 + v55 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v54) block 35 start_pc=0 - terminator Jmp(b15) + terminator Jmp(b14) block 36 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b11) block 37 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b9) block 38 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b4) block 39 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b2) block 40 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_double_mix.ssa b/tests/snapshots/ssa/float_double_mix.ssa index 6f5e7c228..a33700624 100644 --- a/tests/snapshots/ssa/float_double_mix.ssa +++ b/tests/snapshots/ssa/float_double_mix.ssa @@ -4,42 +4,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4591870180066957722) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 Imm(4596373779694328218) -> x0 - v5 StoreLocal { off=-2, value=v4, kind=F64 } -> - - v6 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 FpCast { kind=F32ToF64, value=v2 } -> d0 - v9 Binop { op=fadd, lhs=v8, rhs=v7 } -> d0 - v10 Imm(0) -> x0 - v11 LoadLocal { off=-3, kind=F64 } -> d1 - v12 Imm(4599075939497594061) -> x0 - v13 Binop { op=fsub, lhs=v9, rhs=v12 } -> d1 - v14 Imm(0) -> x0 - v15 LoadLocal { off=-4, kind=F64 } -> d0 - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 Binop { op=flt, lhs=v13, rhs=v17 } -> x0 - terminator Bz { cond=v18, target=b5, fall=b1 } (exit_acc=v18) + v1 Imm(1036831949) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(4596373779694328218) -> x0 + v4 StoreLocal { off=-2, value=v3, kind=F64 } -> - + v5 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v6 LoadLocal { off=-2, kind=F64 } -> d1 + v7 FpCast { kind=F32ToF64, value=v5 } -> d0 + v8 Binop { op=fadd, lhs=v7, rhs=v6 } -> d0 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-3, kind=F64 } -> d1 + v11 Imm(4599075939497594061) -> x0 + v12 Binop { op=fsub, lhs=v8, rhs=v11 } -> d1 + v13 Imm(0) -> x0 + v14 LoadLocal { off=-4, kind=F64 } -> d0 + v15 Imm(0) -> x0 + v16 FpCast { kind=IntToFp, value=v15 } -> d0 + v17 Binop { op=flt, lhs=v12, rhs=v16 } -> x0 + terminator Bz { cond=v17, target=b5, fall=b1 } (exit_acc=v17) block 1 start_pc=0 - v19 LoadLocal { off=-4, kind=F64 } -> d0 - v20 Fneg(v13) -> d1 - v21 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v20) + v18 LoadLocal { off=-4, kind=F64 } -> d0 + v19 Fneg(v12) -> d1 + v20 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v22 Phi { incoming=[b5:v13, b1:v20], kind=F64 } -> d1 - v23 LoadLocal { off=-4, kind=F64 } -> d0 - v24 Imm(4382569440205035030) -> x0 - v25 Binop { op=fgt, lhs=v22, rhs=v24 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v21 Phi { incoming=[b5:v12, b1:v19], kind=F64 } -> d1 + v22 LoadLocal { off=-4, kind=F64 } -> d0 + v23 Imm(4382569440205035030) -> x0 + v24 Binop { op=fgt, lhs=v21, rhs=v23 } -> x0 + terminator Bz { cond=v24, target=b4, fall=b3 } (exit_acc=v24) block 3 start_pc=0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v25 Imm(1) -> x0 + terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v26 Imm(0) -> x0 + terminator Return(v26) (exit_acc=v26) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -48,38 +47,37 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4591870180066957722) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v5 FpCast { kind=F32ToF64, value=v2 } -> d0 - v6 Imm(0) -> x0 - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 Imm(4591870180174331904) -> x0 - v9 Binop { op=fsub, lhs=v5, rhs=v8 } -> d1 - v10 Imm(0) -> x0 - v11 LoadLocal { off=-3, kind=F64 } -> d0 - v12 Imm(0) -> x0 - v13 FpCast { kind=IntToFp, value=v12 } -> d0 - v14 Binop { op=flt, lhs=v9, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b5, fall=b1 } (exit_acc=v14) + v1 Imm(1036831949) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 FpCast { kind=F32ToF64, value=v3 } -> d0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-2, kind=F64 } -> d1 + v7 Imm(4591870180174331904) -> x0 + v8 Binop { op=fsub, lhs=v4, rhs=v7 } -> d1 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-3, kind=F64 } -> d0 + v11 Imm(0) -> x0 + v12 FpCast { kind=IntToFp, value=v11 } -> d0 + v13 Binop { op=flt, lhs=v8, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b5, fall=b1 } (exit_acc=v13) block 1 start_pc=0 - v15 LoadLocal { off=-3, kind=F64 } -> d0 - v16 Fneg(v9) -> d1 - v17 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v16) + v14 LoadLocal { off=-3, kind=F64 } -> d0 + v15 Fneg(v8) -> d1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v18 Phi { incoming=[b5:v9, b1:v16], kind=F64 } -> d1 - v19 LoadLocal { off=-3, kind=F64 } -> d0 - v20 Imm(4352464011485697175) -> x0 - v21 Binop { op=fgt, lhs=v18, rhs=v20 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) + v17 Phi { incoming=[b5:v8, b1:v15], kind=F64 } -> d1 + v18 LoadLocal { off=-3, kind=F64 } -> d0 + v19 Imm(4352464011485697175) -> x0 + v20 Binop { op=fgt, lhs=v17, rhs=v19 } -> x0 + terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) + v21 Imm(2) -> x0 + terminator Return(v21) (exit_acc=v21) block 4 start_pc=0 - v23 Imm(0) -> x0 - terminator Return(v23) (exit_acc=v23) + v22 Imm(0) -> x0 + terminator Return(v22) (exit_acc=v22) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -93,68 +91,66 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 v3 LoadLocal { off=-1, kind=F64 } -> d0 v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] v5 Imm(0) -> x0 - v6 Imm(4593560419918210649) -> x0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v10 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v11 Binop { op=fsub, lhs=v4, rhs=v7 } -> d2 [f32] - v12 Imm(0) -> x0 - v13 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 FpCast { kind=IntToFp, value=v14 } -> d1 - v16 FpCast { kind=F64ToF32, value=v15 } -> d1 [f32] - v17 Binop { op=flt, lhs=v11, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b9, fall=b1 } (exit_acc=v17) + v6 Imm(1039980266) -> x0 [f32] + v7 StoreLocal { off=-3, value=v6, kind=F32 } -> - + v8 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v9 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v10 Binop { op=fsub, lhs=v4, rhs=v9 } -> d2 [f32] + v11 Imm(0) -> x0 + v12 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v13 Imm(0) -> x0 + v14 FpCast { kind=IntToFp, value=v13 } -> d1 + v15 FpCast { kind=F64ToF32, value=v14 } -> d1 [f32] + v16 Binop { op=flt, lhs=v10, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b10, fall=b1 } (exit_acc=v16) block 1 start_pc=0 - v18 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v19 Fneg(v11) -> d2 [f32] - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v17 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v18 Fneg(v10) -> d2 [f32] + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v21 Phi { incoming=[b9:v11, b1:v19], kind=F32 } -> d2 [f32] - v22 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v23 Imm(4487126258331716666) -> x0 - v24 FpCast { kind=F32ToF64, value=v21 } -> d1 - v25 Binop { op=fgt, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v20 Phi { incoming=[b10:v10, b1:v18], kind=F32 } -> d2 [f32] + v21 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v22 Imm(841731191) -> x0 [f32] + v23 Binop { op=fgt, lhs=v20, rhs=v22 } -> x0 + terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) + v24 Imm(3) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v27 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v28 FpCast { kind=F32ToF64, value=v4 } -> d0 - v29 Imm(0) -> x0 - v30 LoadLocal { off=-5, kind=F64 } -> d1 - v31 LoadLocal { off=-1, kind=F64 } -> d1 - v32 Binop { op=fsub, lhs=v28, rhs=v31 } -> d1 + v25 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v26 FpCast { kind=F32ToF64, value=v4 } -> d0 + v27 Imm(0) -> x0 + v28 LoadLocal { off=-5, kind=F64 } -> d1 + v29 LoadLocal { off=-1, kind=F64 } -> d1 + v30 Binop { op=fsub, lhs=v26, rhs=v29 } -> d1 + v31 Imm(0) -> x0 + v32 LoadLocal { off=-6, kind=F64 } -> d0 v33 Imm(0) -> x0 - v34 LoadLocal { off=-6, kind=F64 } -> d0 - v35 Imm(0) -> x0 - v36 FpCast { kind=IntToFp, value=v35 } -> d0 - v37 Binop { op=flt, lhs=v32, rhs=v36 } -> x0 - terminator Bz { cond=v37, target=b10, fall=b5 } (exit_acc=v37) + v34 FpCast { kind=IntToFp, value=v33 } -> d0 + v35 Binop { op=flt, lhs=v30, rhs=v34 } -> x0 + terminator Bz { cond=v35, target=b9, fall=b5 } (exit_acc=v35) block 5 start_pc=0 - v38 LoadLocal { off=-6, kind=F64 } -> d0 - v39 Fneg(v32) -> d1 - v40 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v39) + v36 LoadLocal { off=-6, kind=F64 } -> d0 + v37 Fneg(v30) -> d1 + v38 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v37) block 6 start_pc=0 - v41 Phi { incoming=[b10:v32, b5:v39], kind=F64 } -> d1 - v42 LoadLocal { off=-6, kind=F64 } -> d0 - v43 Imm(4472406533629990549) -> x0 - v44 Binop { op=flt, lhs=v41, rhs=v43 } -> x0 - terminator Bz { cond=v44, target=b8, fall=b7 } (exit_acc=v44) + v39 Phi { incoming=[b9:v30, b5:v37], kind=F64 } -> d1 + v40 LoadLocal { off=-6, kind=F64 } -> d0 + v41 Imm(4472406533629990549) -> x0 + v42 Binop { op=flt, lhs=v39, rhs=v41 } -> x0 + terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) block 7 start_pc=0 - v45 Imm(4) -> x0 - terminator Return(v45) (exit_acc=v45) + v43 Imm(4) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v46 Imm(0) -> x0 - terminator Return(v46) (exit_acc=v46) + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) block 9 start_pc=0 - terminator Jmp(b2) - block 10 start_pc=0 terminator Jmp(b6) + block 10 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=assign_double_to_float_narrows fn ent_pc=3 n_params=0 variadic=false locals=4 @@ -168,37 +164,35 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v5 LoadLocal { off=-1, kind=F64 } -> d1 v6 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] v7 Imm(0) -> x0 - v8 Imm(4599676419595205767) -> x0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d1 [f32] - v10 Imm(0) -> x0 - v11 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v12 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v13 Binop { op=fsub, lhs=v6, rhs=v9 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Binop { op=flt, lhs=v13, rhs=v18 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b1 } (exit_acc=v19) + v8 Imm(1051372203) -> x0 [f32] + v9 StoreLocal { off=-3, value=v8, kind=F32 } -> - + v10 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v11 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v12 Binop { op=fsub, lhs=v6, rhs=v11 } -> d1 [f32] + v13 Imm(0) -> x0 + v14 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v15 Imm(0) -> x0 + v16 FpCast { kind=IntToFp, value=v15 } -> d0 + v17 FpCast { kind=F64ToF32, value=v16 } -> d0 [f32] + v18 Binop { op=flt, lhs=v12, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b5, fall=b1 } (exit_acc=v18) block 1 start_pc=0 - v20 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v21 Fneg(v13) -> d1 [f32] - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v21) + v19 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v20 Fneg(v12) -> d1 [f32] + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 - v23 Phi { incoming=[b5:v13, b1:v21], kind=F32 } -> d1 [f32] - v24 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v25 Imm(4502148214488346440) -> x0 - v26 FpCast { kind=F32ToF64, value=v23 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v22 Phi { incoming=[b5:v12, b1:v20], kind=F32 } -> d1 [f32] + v23 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v24 Imm(869711765) -> x0 [f32] + v25 Binop { op=fgt, lhs=v22, rhs=v24 } -> x0 + terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) block 3 start_pc=0 - v28 Imm(5) -> x0 - terminator Return(v28) (exit_acc=v28) + v26 Imm(5) -> x0 + terminator Return(v26) (exit_acc=v26) block 4 start_pc=0 - v29 Imm(0) -> x0 - terminator Return(v29) (exit_acc=v29) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=4 --- diff --git a/tests/snapshots/ssa/float_increment_decrement.ssa b/tests/snapshots/ssa/float_increment_decrement.ssa index 971b50493..863894264 100644 --- a/tests/snapshots/ssa/float_increment_decrement.ssa +++ b/tests/snapshots/ssa/float_increment_decrement.ssa @@ -4,274 +4,261 @@ fn ent_pc=0 n_params=0 variadic=false locals=22 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4609434218613702656) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 StoreLocal { off=-1, value=v2, kind=F32 } -> - - v4 LocalAddr(-1) -> x1 - v5 Load { addr=v4, disp=0, kind=F32 } -> d0 [f32] - v6 Imm(4607182418800017408) -> x2 - v7 FpCast { kind=F32ToF64, value=v5 } -> d1 - v8 Binop { op=fadd, lhs=v7, rhs=v6 } -> d1 - v9 FpCast { kind=F64ToF32, value=v8 } -> d1 [f32] - v10 Store { addr=v4, disp=0, value=v9, kind=F32 } -> - - v11 Imm(0) -> x1 - v12 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v13 FpCast { kind=F32ToF64, value=v5 } -> d0 - v14 Binop { op=fne, lhs=v13, rhs=v1 } -> x1 - v15 Imm(0) -> x0 - terminator Bnz { cond=v14, target=b31, fall=b1 } (exit_acc=v14) + v1 Imm(1069547520) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 Imm(4607182418800017408) -> x1 + v5 FpCast { kind=F32ToF64, value=v3 } -> d1 + v6 Binop { op=fadd, lhs=v5, rhs=v4 } -> d1 + v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] + v8 StoreLocal { off=-1, value=v7, kind=F32 } -> - + v9 Imm(0) -> x1 + v10 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v11 Binop { op=fne, lhs=v3, rhs=v1 } -> x1 + v12 Imm(0) -> x0 + terminator Bnz { cond=v11, target=b36, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v16 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v17 Imm(4612811918334230528) -> x0 - v18 FpCast { kind=F32ToF64, value=v16 } -> d0 - v19 Binop { op=fne, lhs=v18, rhs=v17 } -> x1 - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v13 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v14 Imm(1075838976) -> x0 [f32] + v15 Binop { op=fne, lhs=v13, rhs=v14 } -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v21 Phi { incoming=[b31:v14, b1:v19], kind=I64 } -> x1 - v22 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) + v17 Phi { incoming=[b36:v11, b1:v15], kind=I64 } -> x1 + v18 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) block 3 start_pc=0 - v23 Imm(1) -> x0 - terminator Return(v23) (exit_acc=v23) + v19 Imm(1) -> x0 + terminator Return(v19) (exit_acc=v19) block 4 start_pc=0 - v24 Imm(4609434218613702656) -> x0 - v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] - v26 StoreLocal { off=-3, value=v25, kind=F32 } -> - - v27 LocalAddr(-3) -> x0 - v28 Load { addr=v27, disp=0, kind=F32 } -> d0 [f32] - v29 Imm(4607182418800017408) -> x1 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fadd, lhs=v30, rhs=v29 } -> d0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d0 [f32] - v33 Store { addr=v27, disp=0, value=v32, kind=F32 } -> - - v34 Imm(0) -> x0 - v35 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v36 Imm(4612811918334230528) -> x0 - v37 FpCast { kind=F32ToF64, value=v32 } -> d0 - v38 Binop { op=fne, lhs=v37, rhs=v36 } -> x1 - v39 Imm(0) -> x0 - terminator Bnz { cond=v38, target=b32, fall=b5 } (exit_acc=v38) + v20 Imm(1069547520) -> x0 [f32] + v21 StoreLocal { off=-3, value=v20, kind=F32 } -> - + v22 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v23 Imm(4607182418800017408) -> x0 + v24 FpCast { kind=F32ToF64, value=v22 } -> d0 + v25 Binop { op=fadd, lhs=v24, rhs=v23 } -> d0 + v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] + v27 StoreLocal { off=-3, value=v26, kind=F32 } -> - + v28 Imm(0) -> x0 + v29 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v30 Imm(1075838976) -> x0 [f32] + v31 Binop { op=fne, lhs=v26, rhs=v30 } -> x1 + v32 Imm(0) -> x0 + terminator Bnz { cond=v31, target=b35, fall=b5 } (exit_acc=v31) block 5 start_pc=0 - v40 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v41 Imm(4612811918334230528) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 - v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x1 - v44 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v43) + v33 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v34 Imm(1075838976) -> x0 [f32] + v35 Binop { op=fne, lhs=v33, rhs=v34 } -> x1 + v36 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v45 Phi { incoming=[b32:v38, b5:v43], kind=I64 } -> x1 - v46 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) + v37 Phi { incoming=[b35:v31, b5:v35], kind=I64 } -> x1 + v38 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) block 7 start_pc=0 - v47 Imm(2) -> x0 - terminator Return(v47) (exit_acc=v47) + v39 Imm(2) -> x0 + terminator Return(v39) (exit_acc=v39) block 8 start_pc=0 - v48 Imm(4614500768194494464) -> x0 - v49 StoreLocal { off=-5, value=v48, kind=F64 } -> - - v50 LoadLocal { off=-5, kind=F64 } -> d0 - v51 Imm(-4616189618054758400) -> x1 - v52 Binop { op=fadd, lhs=v50, rhs=v51 } -> d1 - v53 StoreLocal { off=-5, value=v52, kind=F64 } -> - - v54 Imm(0) -> x1 - v55 LoadLocal { off=-6, kind=F64 } -> d1 - v56 Binop { op=fne, lhs=v50, rhs=v48 } -> x1 - v57 Imm(0) -> x0 - terminator Bnz { cond=v56, target=b33, fall=b9 } (exit_acc=v56) + v40 Imm(4614500768194494464) -> x0 + v41 StoreLocal { off=-5, value=v40, kind=F64 } -> - + v42 LoadLocal { off=-5, kind=F64 } -> d0 + v43 Imm(-4616189618054758400) -> x1 + v44 Binop { op=fadd, lhs=v42, rhs=v43 } -> d1 + v45 StoreLocal { off=-5, value=v44, kind=F64 } -> - + v46 Imm(0) -> x1 + v47 LoadLocal { off=-6, kind=F64 } -> d1 + v48 Binop { op=fne, lhs=v42, rhs=v40 } -> x1 + v49 Imm(0) -> x0 + terminator Bnz { cond=v48, target=b34, fall=b9 } (exit_acc=v48) block 9 start_pc=0 - v58 LoadLocal { off=-5, kind=F64 } -> d0 - v59 Imm(4612248968380809216) -> x0 - v60 Binop { op=fne, lhs=v58, rhs=v59 } -> x1 - v61 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v60) + v50 LoadLocal { off=-5, kind=F64 } -> d0 + v51 Imm(4612248968380809216) -> x0 + v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x1 + v53 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v52) block 10 start_pc=0 - v62 Phi { incoming=[b33:v56, b9:v60], kind=I64 } -> x1 - v63 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v62, target=b12, fall=b11 } (exit_acc=v62) + v54 Phi { incoming=[b34:v48, b9:v52], kind=I64 } -> x1 + v55 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v54, target=b12, fall=b11 } (exit_acc=v54) block 11 start_pc=0 - v64 Imm(3) -> x0 - terminator Return(v64) (exit_acc=v64) + v56 Imm(3) -> x0 + terminator Return(v56) (exit_acc=v56) block 12 start_pc=0 - v65 Imm(4614500768194494464) -> x0 - v66 StoreLocal { off=-7, value=v65, kind=F64 } -> - - v67 LoadLocal { off=-7, kind=F64 } -> d0 - v68 Imm(-4616189618054758400) -> x0 - v69 Binop { op=fadd, lhs=v67, rhs=v68 } -> d0 - v70 StoreLocal { off=-7, value=v69, kind=F64 } -> - - v71 Imm(0) -> x0 - v72 LoadLocal { off=-8, kind=F64 } -> d1 - v73 Imm(4612248968380809216) -> x0 - v74 Binop { op=fne, lhs=v69, rhs=v73 } -> x1 - v75 Imm(0) -> x0 - terminator Bnz { cond=v74, target=b34, fall=b13 } (exit_acc=v74) + v57 Imm(4614500768194494464) -> x0 + v58 StoreLocal { off=-7, value=v57, kind=F64 } -> - + v59 LoadLocal { off=-7, kind=F64 } -> d0 + v60 Imm(-4616189618054758400) -> x0 + v61 Binop { op=fadd, lhs=v59, rhs=v60 } -> d0 + v62 StoreLocal { off=-7, value=v61, kind=F64 } -> - + v63 Imm(0) -> x0 + v64 LoadLocal { off=-8, kind=F64 } -> d1 + v65 Imm(4612248968380809216) -> x0 + v66 Binop { op=fne, lhs=v61, rhs=v65 } -> x1 + v67 Imm(0) -> x0 + terminator Bnz { cond=v66, target=b33, fall=b13 } (exit_acc=v66) block 13 start_pc=0 - v76 LoadLocal { off=-7, kind=F64 } -> d0 - v77 Imm(4612248968380809216) -> x0 - v78 Binop { op=fne, lhs=v76, rhs=v77 } -> x1 - v79 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v78) + v68 LoadLocal { off=-7, kind=F64 } -> d0 + v69 Imm(4612248968380809216) -> x0 + v70 Binop { op=fne, lhs=v68, rhs=v69 } -> x1 + v71 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v70) block 14 start_pc=0 - v80 Phi { incoming=[b34:v74, b13:v78], kind=I64 } -> x1 - v81 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v80, target=b16, fall=b15 } (exit_acc=v80) + v72 Phi { incoming=[b33:v66, b13:v70], kind=I64 } -> x1 + v73 LoadLocal { off=-20, kind=I64 } -> x0 + terminator Bz { cond=v72, target=b16, fall=b15 } (exit_acc=v72) block 15 start_pc=0 - v82 Imm(4) -> x0 - terminator Return(v82) (exit_acc=v82) + v74 Imm(4) -> x0 + terminator Return(v74) (exit_acc=v74) block 16 start_pc=0 - v83 Imm(4607182418800017408) -> x0 + v75 Imm(1065353216) -> x0 [f32] + v76 StoreLocal { off=-9, value=v75, kind=F32 } -> - + v77 LocalAddr(-9) -> x0 + v78 Imm(0) -> x1 + v79 LoadLocal { off=-10, kind=I64 } -> x1 + v80 Load { addr=v77, disp=0, kind=F32 } -> d0 [f32] + v81 Imm(4607182418800017408) -> x1 + v82 FpCast { kind=F32ToF64, value=v80 } -> d0 + v83 Binop { op=fadd, lhs=v82, rhs=v81 } -> d0 v84 FpCast { kind=F64ToF32, value=v83 } -> d0 [f32] - v85 StoreLocal { off=-9, value=v84, kind=F32 } -> - - v86 LocalAddr(-9) -> x1 - v87 Imm(0) -> x2 - v88 LoadLocal { off=-10, kind=I64 } -> x2 - v89 Load { addr=v86, disp=0, kind=F32 } -> d0 [f32] - v90 FpCast { kind=F32ToF64, value=v89 } -> d0 - v91 Binop { op=fadd, lhs=v90, rhs=v83 } -> d0 - v92 FpCast { kind=F64ToF32, value=v91 } -> d0 [f32] - v93 Store { addr=v86, disp=0, value=v92, kind=F32 } -> - - v94 LoadLocal { off=-10, kind=I64 } -> x2 - v95 Load { addr=v86, disp=0, kind=F32 } -> d0 [f32] - v96 FpCast { kind=F32ToF64, value=v95 } -> d0 - v97 Binop { op=fadd, lhs=v96, rhs=v83 } -> d0 - v98 FpCast { kind=F64ToF32, value=v97 } -> d0 [f32] - v99 Store { addr=v86, disp=0, value=v98, kind=F32 } -> - - v100 LoadLocal { off=-9, kind=F32 } -> d0 [f32] - v101 Imm(4613937818241073152) -> x0 - v102 FpCast { kind=F32ToF64, value=v100 } -> d0 - v103 Binop { op=fne, lhs=v102, rhs=v101 } -> x0 - terminator Bz { cond=v103, target=b18, fall=b17 } (exit_acc=v103) + v85 Store { addr=v77, disp=0, value=v84, kind=F32 } -> - + v86 LoadLocal { off=-10, kind=I64 } -> x2 + v87 Load { addr=v77, disp=0, kind=F32 } -> d0 [f32] + v88 FpCast { kind=F32ToF64, value=v87 } -> d0 + v89 Binop { op=fadd, lhs=v88, rhs=v81 } -> d0 + v90 FpCast { kind=F64ToF32, value=v89 } -> d0 [f32] + v91 Store { addr=v77, disp=0, value=v90, kind=F32 } -> - + v92 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v93 Imm(1077936128) -> x0 [f32] + v94 Binop { op=fne, lhs=v92, rhs=v93 } -> x0 + terminator Bz { cond=v94, target=b18, fall=b17 } (exit_acc=v94) block 17 start_pc=0 - v104 Imm(5) -> x0 - terminator Return(v104) (exit_acc=v104) + v95 Imm(5) -> x0 + terminator Return(v95) (exit_acc=v95) block 18 start_pc=0 - v105 LocalAddr(-12) -> x0 - v106 ImmData(16) -> x1 - v107 Mcpy { dst=v105, src=v106, size=16 } -> x0 - v108 LocalAddr(-12) -> x0 - v109 Load { addr=v108, disp=0, kind=F32 } -> d0 [f32] - v110 Imm(4607182418800017408) -> x1 - v111 FpCast { kind=F32ToF64, value=v109 } -> d0 - v112 Binop { op=fadd, lhs=v111, rhs=v110 } -> d0 - v113 FpCast { kind=F64ToF32, value=v112 } -> d0 [f32] - v114 Store { addr=v108, disp=0, value=v113, kind=F32 } -> - - v115 LocalAddr(-12) -> x0 - v116 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x1 - v117 Load { addr=v115, disp=8, kind=F64 } -> d0 - v118 Imm(-4616189618054758400) -> x1 - v119 Binop { op=fadd, lhs=v117, rhs=v118 } -> d0 - v120 Store { addr=v115, disp=8, value=v119, kind=F64 } -> - - v121 LocalAddr(-12) -> x0 - v122 Load { addr=v121, disp=0, kind=F32 } -> d0 [f32] - v123 Imm(4612811918334230528) -> x0 - v124 FpCast { kind=F32ToF64, value=v122 } -> d0 - v125 Binop { op=fne, lhs=v124, rhs=v123 } -> x1 - v126 Imm(0) -> x0 - terminator Bnz { cond=v125, target=b35, fall=b19 } (exit_acc=v125) + v96 LocalAddr(-12) -> x0 + v97 ImmData(16) -> x1 + v98 Mcpy { dst=v96, src=v97, size=16 } -> x0 + v99 LocalAddr(-12) -> x0 + v100 Load { addr=v99, disp=0, kind=F32 } -> d0 [f32] + v101 Imm(4607182418800017408) -> x1 + v102 FpCast { kind=F32ToF64, value=v100 } -> d0 + v103 Binop { op=fadd, lhs=v102, rhs=v101 } -> d0 + v104 FpCast { kind=F64ToF32, value=v103 } -> d0 [f32] + v105 Store { addr=v99, disp=0, value=v104, kind=F32 } -> - + v106 LocalAddr(-12) -> x0 + v107 BinopI { op=add, lhs=v106, rhs_imm=8 } -> x1 + v108 Load { addr=v106, disp=8, kind=F64 } -> d0 + v109 Imm(-4616189618054758400) -> x1 + v110 Binop { op=fadd, lhs=v108, rhs=v109 } -> d0 + v111 Store { addr=v106, disp=8, value=v110, kind=F64 } -> - + v112 LocalAddr(-12) -> x0 + v113 Load { addr=v112, disp=0, kind=F32 } -> d0 [f32] + v114 Imm(1075838976) -> x0 [f32] + v115 Binop { op=fne, lhs=v113, rhs=v114 } -> x1 + v116 Imm(0) -> x0 + terminator Bnz { cond=v115, target=b32, fall=b19 } (exit_acc=v115) block 19 start_pc=0 - v127 LocalAddr(-12) -> x0 - v128 BinopI { op=add, lhs=v127, rhs_imm=8 } -> x1 - v129 Load { addr=v127, disp=8, kind=F64 } -> d0 - v130 Imm(4609434218613702656) -> x0 - v131 Binop { op=fne, lhs=v129, rhs=v130 } -> x1 - v132 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v131) + v117 LocalAddr(-12) -> x0 + v118 BinopI { op=add, lhs=v117, rhs_imm=8 } -> x1 + v119 Load { addr=v117, disp=8, kind=F64 } -> d0 + v120 Imm(4609434218613702656) -> x0 + v121 Binop { op=fne, lhs=v119, rhs=v120 } -> x1 + v122 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v121) block 20 start_pc=0 - v133 Phi { incoming=[b35:v125, b19:v131], kind=I64 } -> x1 - v134 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v133, target=b22, fall=b21 } (exit_acc=v133) + v123 Phi { incoming=[b32:v115, b19:v121], kind=I64 } -> x1 + v124 LoadLocal { off=-21, kind=I64 } -> x0 + terminator Bz { cond=v123, target=b22, fall=b21 } (exit_acc=v123) block 21 start_pc=0 - v135 Imm(6) -> x0 - terminator Return(v135) (exit_acc=v135) + v125 Imm(6) -> x0 + terminator Return(v125) (exit_acc=v125) block 22 start_pc=0 - v136 ImmData(8) -> x0 - v137 Load { addr=v136, disp=0, kind=F64 } -> d0 - v138 Imm(4607182418800017408) -> x1 - v139 Binop { op=fadd, lhs=v137, rhs=v138 } -> d0 - v140 Store { addr=v136, disp=0, value=v139, kind=F64 } -> - - v141 Load { addr=v136, disp=0, kind=F64 } -> d0 - v142 Binop { op=fadd, lhs=v141, rhs=v138 } -> d0 - v143 Store { addr=v136, disp=0, value=v142, kind=F64 } -> - - v144 Load { addr=v136, disp=0, kind=F64 } -> d0 - v145 Imm(4619567317775286272) -> x0 - v146 Binop { op=fne, lhs=v144, rhs=v145 } -> x0 - terminator Bz { cond=v146, target=b24, fall=b23 } (exit_acc=v146) + v126 ImmData(8) -> x0 + v127 Load { addr=v126, disp=0, kind=F64 } -> d0 + v128 Imm(4607182418800017408) -> x1 + v129 Binop { op=fadd, lhs=v127, rhs=v128 } -> d0 + v130 Store { addr=v126, disp=0, value=v129, kind=F64 } -> - + v131 Load { addr=v126, disp=0, kind=F64 } -> d0 + v132 Binop { op=fadd, lhs=v131, rhs=v128 } -> d0 + v133 Store { addr=v126, disp=0, value=v132, kind=F64 } -> - + v134 Load { addr=v126, disp=0, kind=F64 } -> d0 + v135 Imm(4619567317775286272) -> x0 + v136 Binop { op=fne, lhs=v134, rhs=v135 } -> x0 + terminator Bz { cond=v136, target=b24, fall=b23 } (exit_acc=v136) block 23 start_pc=0 - v147 Imm(7) -> x0 - terminator Return(v147) (exit_acc=v147) + v137 Imm(7) -> x0 + terminator Return(v137) (exit_acc=v137) block 24 start_pc=0 + v138 LocalAddr(-15) -> x0 + v139 ImmData(32) -> x1 + v140 Mcpy { dst=v138, src=v139, size=24 } -> x0 + v141 LocalAddr(-15) -> x0 + v142 Imm(8) -> x1 + v143 BinopI { op=add, lhs=v141, rhs_imm=8 } -> x1 + v144 Load { addr=v141, disp=8, kind=F64 } -> d0 + v145 Imm(4607182418800017408) -> x1 + v146 Binop { op=fadd, lhs=v144, rhs=v145 } -> d0 + v147 Store { addr=v141, disp=8, value=v146, kind=F64 } -> - v148 LocalAddr(-15) -> x0 - v149 ImmData(32) -> x1 - v150 Mcpy { dst=v148, src=v149, size=24 } -> x0 - v151 LocalAddr(-15) -> x0 - v152 Imm(8) -> x1 - v153 BinopI { op=add, lhs=v151, rhs_imm=8 } -> x1 - v154 Load { addr=v151, disp=8, kind=F64 } -> d0 - v155 Imm(4607182418800017408) -> x1 - v156 Binop { op=fadd, lhs=v154, rhs=v155 } -> d0 - v157 Store { addr=v151, disp=8, value=v156, kind=F64 } -> - - v158 LocalAddr(-15) -> x0 - v159 Imm(16) -> x1 - v160 BinopI { op=add, lhs=v158, rhs_imm=16 } -> x1 - v161 Load { addr=v158, disp=16, kind=F64 } -> d0 - v162 Imm(-4616189618054758400) -> x1 - v163 Binop { op=fadd, lhs=v161, rhs=v162 } -> d0 - v164 Store { addr=v158, disp=16, value=v163, kind=F64 } -> - - v165 LocalAddr(-15) -> x0 - v166 BinopI { op=add, lhs=v165, rhs_imm=8 } -> x1 - v167 Load { addr=v165, disp=8, kind=F64 } -> d0 - v168 Imm(4611686018427387904) -> x0 - v169 Binop { op=fne, lhs=v167, rhs=v168 } -> x1 - v170 Imm(0) -> x0 - terminator Bnz { cond=v169, target=b36, fall=b25 } (exit_acc=v169) + v149 Imm(16) -> x1 + v150 BinopI { op=add, lhs=v148, rhs_imm=16 } -> x1 + v151 Load { addr=v148, disp=16, kind=F64 } -> d0 + v152 Imm(-4616189618054758400) -> x1 + v153 Binop { op=fadd, lhs=v151, rhs=v152 } -> d0 + v154 Store { addr=v148, disp=16, value=v153, kind=F64 } -> - + v155 LocalAddr(-15) -> x0 + v156 BinopI { op=add, lhs=v155, rhs_imm=8 } -> x1 + v157 Load { addr=v155, disp=8, kind=F64 } -> d0 + v158 Imm(4611686018427387904) -> x0 + v159 Binop { op=fne, lhs=v157, rhs=v158 } -> x1 + v160 Imm(0) -> x0 + terminator Bnz { cond=v159, target=b31, fall=b25 } (exit_acc=v159) block 25 start_pc=0 - v171 LocalAddr(-15) -> x0 - v172 Imm(16) -> x1 - v173 BinopI { op=add, lhs=v171, rhs_imm=16 } -> x1 - v174 Load { addr=v171, disp=16, kind=F64 } -> d0 - v175 Imm(4607182418800017408) -> x0 - v176 Binop { op=fne, lhs=v174, rhs=v175 } -> x1 - v177 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v176) + v161 LocalAddr(-15) -> x0 + v162 Imm(16) -> x1 + v163 BinopI { op=add, lhs=v161, rhs_imm=16 } -> x1 + v164 Load { addr=v161, disp=16, kind=F64 } -> d0 + v165 Imm(4607182418800017408) -> x0 + v166 Binop { op=fne, lhs=v164, rhs=v165 } -> x1 + v167 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v166) block 26 start_pc=0 - v178 Phi { incoming=[b36:v169, b25:v176], kind=I64 } -> x1 - v179 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v178, target=b28, fall=b27 } (exit_acc=v178) + v168 Phi { incoming=[b31:v159, b25:v166], kind=I64 } -> x1 + v169 LoadLocal { off=-22, kind=I64 } -> x0 + terminator Bz { cond=v168, target=b28, fall=b27 } (exit_acc=v168) block 27 start_pc=0 - v180 Imm(8) -> x0 - terminator Return(v180) (exit_acc=v180) + v170 Imm(8) -> x0 + terminator Return(v170) (exit_acc=v170) block 28 start_pc=0 - v181 Imm(4715268809856909312) -> x0 - v182 FpCast { kind=F64ToF32, value=v181 } -> d0 [f32] - v183 StoreLocal { off=-16, value=v182, kind=F32 } -> - - v184 LocalAddr(-16) -> x1 - v185 Load { addr=v184, disp=0, kind=F32 } -> d0 [f32] - v186 Imm(4607182418800017408) -> x2 - v187 FpCast { kind=F32ToF64, value=v185 } -> d0 - v188 Binop { op=fadd, lhs=v187, rhs=v186 } -> d0 - v189 FpCast { kind=F64ToF32, value=v188 } -> d0 [f32] - v190 Store { addr=v184, disp=0, value=v189, kind=F32 } -> - - v191 LoadLocal { off=-16, kind=F32 } -> d0 [f32] - v192 FpCast { kind=F32ToF64, value=v191 } -> d0 - v193 Binop { op=fne, lhs=v192, rhs=v181 } -> x0 - terminator Bz { cond=v193, target=b30, fall=b29 } (exit_acc=v193) + v171 Imm(1266679808) -> x0 [f32] + v172 StoreLocal { off=-16, value=v171, kind=F32 } -> - + v173 LoadLocal { off=-16, kind=F32 } -> d0 [f32] + v174 Imm(4607182418800017408) -> x1 + v175 FpCast { kind=F32ToF64, value=v173 } -> d0 + v176 Binop { op=fadd, lhs=v175, rhs=v174 } -> d0 + v177 FpCast { kind=F64ToF32, value=v176 } -> d0 [f32] + v178 StoreLocal { off=-16, value=v177, kind=F32 } -> - + v179 LoadLocal { off=-16, kind=F32 } -> d0 [f32] + v180 Binop { op=fne, lhs=v179, rhs=v171 } -> x0 + terminator Bz { cond=v180, target=b30, fall=b29 } (exit_acc=v180) block 29 start_pc=0 - v194 Imm(9) -> x0 - terminator Return(v194) (exit_acc=v194) + v181 Imm(9) -> x0 + terminator Return(v181) (exit_acc=v181) block 30 start_pc=0 - v195 Imm(0) -> x0 - terminator Return(v195) (exit_acc=v195) + v182 Imm(0) -> x0 + terminator Return(v182) (exit_acc=v182) block 31 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b26) block 32 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b20) block 33 start_pc=0 - terminator Jmp(b10) - block 34 start_pc=0 terminator Jmp(b14) + block 34 start_pc=0 + terminator Jmp(b10) block 35 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b6) block 36 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_is_four_bytes.ssa b/tests/snapshots/ssa/float_is_four_bytes.ssa index 7eb9e802f..86046f27f 100644 --- a/tests/snapshots/ssa/float_is_four_bytes.ssa +++ b/tests/snapshots/ssa/float_is_four_bytes.ssa @@ -35,341 +35,316 @@ fn ent_pc=3 n_params=0 variadic=false locals=13 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 v2 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 ImmData(56) -> x7 - v4 Imm(4) -> x6 - v5 CallExt { binding_idx=0, args=[v3, v4], fp_arg_mask=0x0 } -> x0 - v6 Imm(1) -> x3 - v7 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v6) - block 2 start_pc=0 - v8 Phi { incoming=[b0:v1, b1:v6], kind=I64 } -> x3 + v8 Phi { incoming=[b0:v1, b43:v6], kind=I64 } -> x3 v9 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v9) + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 + v15 Phi { incoming=[b1:v8, b44:v13], kind=I64 } -> x3 + v16 Imm(0) -> x0 [f32] + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v18) block 3 start_pc=0 - v10 ImmData(80) -> x7 - v11 Imm(8) -> x6 - v12 CallExt { binding_idx=0, args=[v10, v11], fp_arg_mask=0x0 } -> x0 - v13 Imm(2) -> x3 - v14 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v13) + v24 Phi { incoming=[b2:v15, b45:v22], kind=I64 } -> x3 + v25 LocalAddr(-3) -> x0 + v26 Imm(1069547520) -> x1 [f32] + v27 Store { addr=v25, disp=0, value=v26, kind=F32 } -> - + v28 LocalAddr(-3) -> x0 + v29 BinopI { op=add, lhs=v28, rhs_imm=4 } -> x1 + v30 Imm(305419896) -> x1 + v31 Store { addr=v28, disp=4, value=v30, kind=I32 } -> - + v32 LocalAddr(-3) -> x0 + v33 Imm(0) -> x1 + v34 LoadLocal { off=-4, kind=I64 } -> x1 + v35 Imm(4) -> x1 + v36 BinopI { op=add, lhs=v32, rhs_imm=4 } -> x1 + v37 Load { addr=v32, disp=4, kind=I32 } -> x1 + v38 BinopI { op=ne, lhs=v37, rhs_imm=305419896 } -> x1 + terminator Bz { cond=v38, target=b42, fall=b4 } (exit_acc=v38) block 4 start_pc=0 - v15 Phi { incoming=[b2:v8, b3:v13], kind=I64 } -> x3 - v16 Imm(0) -> x0 - v17 FpCast { kind=F64ToF32, value=v16 } -> d0 [f32] - v18 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v16) + v39 ImmData(126) -> x7 + v40 LoadLocal { off=-4, kind=I64 } -> x1 + v41 Imm(4) -> x3 + v42 BinopI { op=add, lhs=v32, rhs_imm=4 } -> x1 + v43 Load { addr=v32, disp=4, kind=I32 } -> x6 + v44 CallExt { binding_idx=0, args=[v39, v43], fp_arg_mask=0x0 } -> x0 + v45 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v41) block 5 start_pc=0 - v19 ImmData(105) -> x7 - v20 Imm(4) -> x6 - v21 CallExt { binding_idx=0, args=[v19, v20], fp_arg_mask=0x0 } -> x0 - v22 Imm(3) -> x3 - v23 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v22) + v46 Phi { incoming=[b42:v24, b4:v41], kind=I64 } -> x3 + v47 LocalAddr(-3) -> x0 + v48 Load { addr=v47, disp=0, kind=F32 } -> d0 [f32] + v49 Imm(1069547520) -> x0 [f32] + v50 Binop { op=fne, lhs=v48, rhs=v49 } -> x0 + terminator Bz { cond=v50, target=b41, fall=b6 } (exit_acc=v50) block 6 start_pc=0 - v24 Phi { incoming=[b4:v15, b5:v22], kind=I64 } -> x3 - v25 LocalAddr(-3) -> x0 - v26 Imm(4609434218613702656) -> x1 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Store { addr=v25, disp=0, value=v27, kind=F32 } -> - - v29 LocalAddr(-3) -> x0 - v30 BinopI { op=add, lhs=v29, rhs_imm=4 } -> x1 - v31 Imm(305419896) -> x1 - v32 Store { addr=v29, disp=4, value=v31, kind=I32 } -> - - v33 LocalAddr(-3) -> x0 - v34 Imm(0) -> x1 - v35 LoadLocal { off=-4, kind=I64 } -> x1 - v36 Imm(4) -> x1 - v37 BinopI { op=add, lhs=v33, rhs_imm=4 } -> x1 - v38 Load { addr=v33, disp=4, kind=I32 } -> x1 - v39 BinopI { op=ne, lhs=v38, rhs_imm=305419896 } -> x1 - terminator Bz { cond=v39, target=b33, fall=b7 } (exit_acc=v39) + v51 ImmData(163) -> x7 + v52 CallExt { binding_idx=0, args=[v51], fp_arg_mask=0x0 } -> x0 + v53 Imm(5) -> x3 + v54 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v53) block 7 start_pc=0 - v40 ImmData(126) -> x7 - v41 LoadLocal { off=-4, kind=I64 } -> x1 - v42 Imm(4) -> x3 - v43 BinopI { op=add, lhs=v33, rhs_imm=4 } -> x1 - v44 Load { addr=v33, disp=4, kind=I32 } -> x6 - v45 CallExt { binding_idx=0, args=[v40, v44], fp_arg_mask=0x0 } -> x0 - v46 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v42) + v55 Phi { incoming=[b41:v46, b6:v53], kind=I64 } -> x3 + v56 ImmData(40) -> x0 + v57 Imm(0) -> x1 + v58 Imm(4) -> x1 + v59 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x1 + v60 LoadLocal { off=-5, kind=I64 } -> x2 + v61 Binop { op=sub, lhs=v59, rhs=v56 } -> x1 + v62 BinopI { op=ne, lhs=v61, rhs_imm=4 } -> x1 + terminator Bz { cond=v62, target=b40, fall=b8 } (exit_acc=v62) block 8 start_pc=0 - v47 Phi { incoming=[b33:v24, b7:v42], kind=I64 } -> x3 - v48 LocalAddr(-3) -> x0 - v49 Load { addr=v48, disp=0, kind=F32 } -> d0 [f32] - v50 Imm(4609434218613702656) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b34, fall=b9 } (exit_acc=v52) + v63 ImmData(189) -> x7 + v64 ImmData(40) -> x1 + v65 Imm(4) -> x2 + v66 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x1 + v67 LoadLocal { off=-5, kind=I64 } -> x2 + v68 Binop { op=sub, lhs=v66, rhs=v56 } -> x6 + v69 CallExt { binding_idx=0, args=[v63, v68], fp_arg_mask=0x0 } -> x0 + v70 Imm(6) -> x3 + v71 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v70) block 9 start_pc=0 - v53 ImmData(163) -> x7 - v54 CallExt { binding_idx=0, args=[v53], fp_arg_mask=0x0 } -> x0 - v55 Imm(5) -> x3 - v56 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v55) + v72 Phi { incoming=[b40:v55, b8:v70], kind=I64 } -> x3 + v73 ImmData(40) -> x0 + v74 Imm(0) -> x1 + v75 Load { addr=v73, disp=0, kind=F32 } -> d0 [f32] + v76 Imm(1069547520) -> x0 [f32] + v77 Binop { op=fne, lhs=v75, rhs=v76 } -> x0 + terminator Bz { cond=v77, target=b39, fall=b10 } (exit_acc=v77) block 10 start_pc=0 - v57 Phi { incoming=[b34:v47, b9:v55], kind=I64 } -> x3 - v58 ImmData(40) -> x0 - v59 Imm(0) -> x1 - v60 Imm(4) -> x1 - v61 BinopI { op=add, lhs=v58, rhs_imm=4 } -> x1 - v62 LoadLocal { off=-5, kind=I64 } -> x2 - v63 Binop { op=sub, lhs=v61, rhs=v58 } -> x1 - v64 BinopI { op=ne, lhs=v63, rhs_imm=4 } -> x1 - terminator Bz { cond=v64, target=b35, fall=b11 } (exit_acc=v64) + v78 ImmData(212) -> x7 + v79 ImmData(40) -> x0 + v80 Imm(0) -> x1 + v81 Load { addr=v79, disp=0, kind=F32 } -> d0 [f32] + v82 FpCast { kind=F32ToF64, value=v81 } -> d0 + v83 CallExt { binding_idx=0, args=[v78, v82], fp_arg_mask=0x2 } -> x0 + v84 Imm(7) -> x3 + v85 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v84) block 11 start_pc=0 - v65 ImmData(189) -> x7 - v66 ImmData(40) -> x1 - v67 Imm(4) -> x2 - v68 BinopI { op=add, lhs=v66, rhs_imm=4 } -> x1 - v69 LoadLocal { off=-5, kind=I64 } -> x2 - v70 Binop { op=sub, lhs=v68, rhs=v58 } -> x6 - v71 CallExt { binding_idx=0, args=[v65, v70], fp_arg_mask=0x0 } -> x0 - v72 Imm(6) -> x3 - v73 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v72) + v86 Phi { incoming=[b39:v72, b10:v84], kind=I64 } -> x3 + v87 ImmData(40) -> x0 + v88 Imm(4) -> x1 + v89 BinopI { op=add, lhs=v87, rhs_imm=4 } -> x1 + v90 Load { addr=v87, disp=4, kind=F32 } -> d0 [f32] + v91 Imm(1075838976) -> x0 [f32] + v92 Binop { op=fne, lhs=v90, rhs=v91 } -> x0 + terminator Bz { cond=v92, target=b38, fall=b12 } (exit_acc=v92) block 12 start_pc=0 - v74 Phi { incoming=[b35:v57, b11:v72], kind=I64 } -> x3 - v75 ImmData(40) -> x0 - v76 Imm(0) -> x1 - v77 Load { addr=v75, disp=0, kind=F32 } -> d0 [f32] - v78 Imm(4609434218613702656) -> x0 - v79 FpCast { kind=F32ToF64, value=v77 } -> d0 - v80 Binop { op=fne, lhs=v79, rhs=v78 } -> x0 - terminator Bz { cond=v80, target=b36, fall=b13 } (exit_acc=v80) + v93 ImmData(232) -> x7 + v94 ImmData(40) -> x0 + v95 Imm(4) -> x1 + v96 BinopI { op=add, lhs=v94, rhs_imm=4 } -> x1 + v97 Load { addr=v94, disp=4, kind=F32 } -> d0 [f32] + v98 FpCast { kind=F32ToF64, value=v97 } -> d0 + v99 CallExt { binding_idx=0, args=[v93, v98], fp_arg_mask=0x2 } -> x0 + v100 Imm(8) -> x3 + v101 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v100) block 13 start_pc=0 - v81 ImmData(212) -> x7 - v82 ImmData(40) -> x0 - v83 Imm(0) -> x1 - v84 Load { addr=v82, disp=0, kind=F32 } -> d0 [f32] - v85 FpCast { kind=F32ToF64, value=v84 } -> d0 - v86 CallExt { binding_idx=0, args=[v81, v85], fp_arg_mask=0x2 } -> x0 - v87 Imm(7) -> x3 - v88 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v87) + v102 Phi { incoming=[b38:v86, b12:v100], kind=I64 } -> x3 + v103 ImmData(40) -> x0 + v104 Imm(8) -> x1 + v105 BinopI { op=add, lhs=v103, rhs_imm=8 } -> x1 + v106 Load { addr=v103, disp=8, kind=F32 } -> d0 [f32] + v107 Imm(1080033280) -> x0 [f32] + v108 Binop { op=fne, lhs=v106, rhs=v107 } -> x0 + terminator Bz { cond=v108, target=b37, fall=b14 } (exit_acc=v108) block 14 start_pc=0 - v89 Phi { incoming=[b36:v74, b13:v87], kind=I64 } -> x3 - v90 ImmData(40) -> x0 - v91 Imm(4) -> x1 - v92 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x1 - v93 Load { addr=v90, disp=4, kind=F32 } -> d0 [f32] - v94 Imm(4612811918334230528) -> x0 - v95 FpCast { kind=F32ToF64, value=v93 } -> d0 - v96 Binop { op=fne, lhs=v95, rhs=v94 } -> x0 - terminator Bz { cond=v96, target=b37, fall=b15 } (exit_acc=v96) + v109 ImmData(252) -> x7 + v110 ImmData(40) -> x0 + v111 Imm(8) -> x1 + v112 BinopI { op=add, lhs=v110, rhs_imm=8 } -> x1 + v113 Load { addr=v110, disp=8, kind=F32 } -> d0 [f32] + v114 FpCast { kind=F32ToF64, value=v113 } -> d0 + v115 CallExt { binding_idx=0, args=[v109, v114], fp_arg_mask=0x2 } -> x0 + v116 Imm(9) -> x3 + v117 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v116) block 15 start_pc=0 - v97 ImmData(232) -> x7 - v98 ImmData(40) -> x0 - v99 Imm(4) -> x1 - v100 BinopI { op=add, lhs=v98, rhs_imm=4 } -> x1 - v101 Load { addr=v98, disp=4, kind=F32 } -> d0 [f32] - v102 FpCast { kind=F32ToF64, value=v101 } -> d0 - v103 CallExt { binding_idx=0, args=[v97, v102], fp_arg_mask=0x2 } -> x0 - v104 Imm(8) -> x3 - v105 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v104) + v118 Phi { incoming=[b37:v102, b14:v116], kind=I64 } -> x3 + v119 ImmData(40) -> x0 + v120 Imm(12) -> x1 + v121 BinopI { op=add, lhs=v119, rhs_imm=12 } -> x1 + v122 Load { addr=v119, disp=12, kind=F32 } -> d0 [f32] + v123 Imm(1083179008) -> x0 [f32] + v124 Binop { op=fne, lhs=v122, rhs=v123 } -> x0 + terminator Bz { cond=v124, target=b36, fall=b16 } (exit_acc=v124) block 16 start_pc=0 - v106 Phi { incoming=[b37:v89, b15:v104], kind=I64 } -> x3 - v107 ImmData(40) -> x0 - v108 Imm(8) -> x1 - v109 BinopI { op=add, lhs=v107, rhs_imm=8 } -> x1 - v110 Load { addr=v107, disp=8, kind=F32 } -> d0 [f32] - v111 Imm(4615063718147915776) -> x0 - v112 FpCast { kind=F32ToF64, value=v110 } -> d0 - v113 Binop { op=fne, lhs=v112, rhs=v111 } -> x0 - terminator Bz { cond=v113, target=b38, fall=b17 } (exit_acc=v113) + v125 ImmData(272) -> x7 + v126 ImmData(40) -> x0 + v127 Imm(12) -> x1 + v128 BinopI { op=add, lhs=v126, rhs_imm=12 } -> x1 + v129 Load { addr=v126, disp=12, kind=F32 } -> d0 [f32] + v130 FpCast { kind=F32ToF64, value=v129 } -> d0 + v131 CallExt { binding_idx=0, args=[v125, v130], fp_arg_mask=0x2 } -> x0 + v132 Imm(10) -> x3 + v133 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v132) block 17 start_pc=0 - v114 ImmData(252) -> x7 - v115 ImmData(40) -> x0 - v116 Imm(8) -> x1 - v117 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x1 - v118 Load { addr=v115, disp=8, kind=F32 } -> d0 [f32] - v119 FpCast { kind=F32ToF64, value=v118 } -> d0 - v120 CallExt { binding_idx=0, args=[v114, v119], fp_arg_mask=0x2 } -> x0 - v121 Imm(9) -> x3 - v122 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v121) + v134 Phi { incoming=[b36:v118, b16:v132], kind=I64 } -> x3 + v135 Imm(1069547520) -> x0 [f32] + v136 Imm(0) -> x1 + v137 Binop { op=fne, lhs=v135, rhs=v135 } -> x0 + terminator Bz { cond=v137, target=b35, fall=b18 } (exit_acc=v137) block 18 start_pc=0 - v123 Phi { incoming=[b38:v106, b17:v121], kind=I64 } -> x3 - v124 ImmData(40) -> x0 - v125 Imm(12) -> x1 - v126 BinopI { op=add, lhs=v124, rhs_imm=12 } -> x1 - v127 Load { addr=v124, disp=12, kind=F32 } -> d0 [f32] - v128 Imm(4616752568008179712) -> x0 - v129 FpCast { kind=F32ToF64, value=v127 } -> d0 - v130 Binop { op=fne, lhs=v129, rhs=v128 } -> x0 - terminator Bz { cond=v130, target=b39, fall=b19 } (exit_acc=v130) + v138 ImmData(292) -> x7 + v139 CallExt { binding_idx=0, args=[v138], fp_arg_mask=0x0 } -> x0 + v140 Imm(11) -> x3 + v141 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v140) block 19 start_pc=0 - v131 ImmData(272) -> x7 - v132 ImmData(40) -> x0 - v133 Imm(12) -> x1 - v134 BinopI { op=add, lhs=v132, rhs_imm=12 } -> x1 - v135 Load { addr=v132, disp=12, kind=F32 } -> d0 [f32] - v136 FpCast { kind=F32ToF64, value=v135 } -> d0 - v137 CallExt { binding_idx=0, args=[v131, v136], fp_arg_mask=0x2 } -> x0 - v138 Imm(10) -> x3 - v139 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v138) + v142 Phi { incoming=[b35:v134, b18:v140], kind=I64 } -> x3 + v143 Imm(1075838976) -> x0 [f32] + v144 Imm(0) -> x1 + v145 Binop { op=fne, lhs=v143, rhs=v143 } -> x0 + terminator Bz { cond=v145, target=b34, fall=b20 } (exit_acc=v145) block 20 start_pc=0 - v140 Phi { incoming=[b39:v123, b19:v138], kind=I64 } -> x3 - v141 Imm(4609434218613702656) -> x0 - v142 FpCast { kind=F64ToF32, value=v141 } -> d0 [f32] - v143 Imm(0) -> x1 - v144 FpCast { kind=F32ToF64, value=v142 } -> d0 - v145 Binop { op=fne, lhs=v144, rhs=v141 } -> x0 - terminator Bz { cond=v145, target=b40, fall=b21 } (exit_acc=v145) - block 21 start_pc=0 - v146 ImmData(292) -> x7 + v146 ImmData(315) -> x7 v147 CallExt { binding_idx=0, args=[v146], fp_arg_mask=0x0 } -> x0 - v148 Imm(11) -> x3 + v148 Imm(12) -> x3 v149 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v148) + terminator Jmp(b21) (exit_acc=v148) + block 21 start_pc=0 + v150 Phi { incoming=[b34:v142, b20:v148], kind=I64 } -> x3 + v151 Imm(1069547520) -> x0 [f32] + v152 Imm(0) -> x1 + v153 Imm(1075838976) -> x1 [f32] + v154 Imm(0) -> x2 + v155 Binop { op=feq, lhs=v151, rhs=v153 } -> x0 + terminator Bz { cond=v155, target=b33, fall=b22 } (exit_acc=v155) block 22 start_pc=0 - v150 Phi { incoming=[b40:v140, b21:v148], kind=I64 } -> x3 - v151 Imm(4612811918334230528) -> x0 - v152 FpCast { kind=F64ToF32, value=v151 } -> d0 [f32] - v153 Imm(0) -> x1 - v154 FpCast { kind=F32ToF64, value=v152 } -> d0 - v155 Binop { op=fne, lhs=v154, rhs=v151 } -> x0 - terminator Bz { cond=v155, target=b41, fall=b23 } (exit_acc=v155) - block 23 start_pc=0 - v156 ImmData(315) -> x7 + v156 ImmData(338) -> x7 v157 CallExt { binding_idx=0, args=[v156], fp_arg_mask=0x0 } -> x0 - v158 Imm(12) -> x3 + v158 Imm(13) -> x3 v159 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v158) + terminator Jmp(b23) (exit_acc=v158) + block 23 start_pc=0 + v160 Phi { incoming=[b33:v150, b22:v158], kind=I64 } -> x3 + v161 Imm(1065353216) -> x0 [f32] + v162 Imm(1073741824) -> x1 [f32] + v163 Imm(1080033280) -> x2 [f32] + v164 Imm(0) -> x6 + v165 Imm(0) -> x6 + v166 Imm(0) -> x6 + v167 Binop { op=fadd, lhs=v161, rhs=v162 } -> d0 [f32] + v168 Binop { op=fadd, lhs=v167, rhs=v163 } -> d0 [f32] + v169 Imm(1087373312) -> x0 [f32] + v170 Binop { op=fne, lhs=v168, rhs=v169 } -> x0 + terminator Bz { cond=v170, target=b32, fall=b24 } (exit_acc=v170) block 24 start_pc=0 - v160 Phi { incoming=[b41:v150, b23:v158], kind=I64 } -> x3 - v161 Imm(4609434218613702656) -> x0 - v162 FpCast { kind=F64ToF32, value=v161 } -> d0 [f32] - v163 Imm(0) -> x0 - v164 Imm(4612811918334230528) -> x0 - v165 FpCast { kind=F64ToF32, value=v164 } -> d1 [f32] - v166 Imm(0) -> x0 - v167 Binop { op=feq, lhs=v162, rhs=v165 } -> x0 - terminator Bz { cond=v167, target=b42, fall=b25 } (exit_acc=v167) + v171 ImmData(380) -> x7 + v172 Imm(1065353216) -> x0 [f32] + v173 Imm(1073741824) -> x1 [f32] + v174 Imm(1080033280) -> x2 [f32] + v175 Imm(0) -> x6 + v176 Imm(0) -> x6 + v177 Imm(0) -> x6 + v178 Binop { op=fadd, lhs=v172, rhs=v173 } -> d0 [f32] + v179 Binop { op=fadd, lhs=v178, rhs=v174 } -> d0 [f32] + v180 FpCast { kind=F32ToF64, value=v179 } -> d0 + v181 CallExt { binding_idx=0, args=[v171, v180], fp_arg_mask=0x2 } -> x0 + v182 Imm(14) -> x3 + v183 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v182) block 25 start_pc=0 - v168 ImmData(338) -> x7 - v169 CallExt { binding_idx=0, args=[v168], fp_arg_mask=0x0 } -> x0 - v170 Imm(13) -> x3 - v171 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v170) + v184 Phi { incoming=[b32:v160, b24:v182], kind=I64 } -> x3 + v185 Imm(1069547520) -> x0 [f32] + v186 StoreLocal { off=-6, value=v185, kind=F32 } -> - + v187 Imm(1073741824) -> x0 [f32] + v188 StoreLocal { off=-7, value=v187, kind=F32 } -> - + v189 LoadLocal { off=-6, kind=F32 } -> d0 [f32] + v190 LoadLocal { off=-7, kind=F32 } -> d1 [f32] + v191 Binop { op=fmul, lhs=v189, rhs=v190 } -> d2 [f32] + v192 Imm(1048576000) -> x0 [f32] + v193 Fma { a=v189, b=v190, c=v192, neg_product=false, neg_addend=false } -> d0 [f32] + v194 Imm(0) -> x0 + v195 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v196 Imm(1078984704) -> x0 [f32] + v197 Binop { op=fne, lhs=v193, rhs=v196 } -> x0 + terminator Bz { cond=v197, target=b31, fall=b26 } (exit_acc=v197) block 26 start_pc=0 - v172 Phi { incoming=[b42:v160, b25:v170], kind=I64 } -> x3 - v173 Imm(4607182418800017408) -> x0 - v174 FpCast { kind=F64ToF32, value=v173 } -> d0 [f32] - v175 Imm(4611686018427387904) -> x0 - v176 FpCast { kind=F64ToF32, value=v175 } -> d1 [f32] - v177 Imm(4615063718147915776) -> x0 - v178 FpCast { kind=F64ToF32, value=v177 } -> d2 [f32] - v179 Imm(0) -> x0 - v180 Imm(0) -> x0 - v181 Imm(0) -> x0 - v182 Binop { op=fadd, lhs=v174, rhs=v176 } -> d0 [f32] - v183 Binop { op=fadd, lhs=v182, rhs=v178 } -> d0 [f32] - v184 Imm(4619004367821864960) -> x0 - v185 FpCast { kind=F32ToF64, value=v183 } -> d0 - v186 Binop { op=fne, lhs=v185, rhs=v184 } -> x0 - terminator Bz { cond=v186, target=b43, fall=b27 } (exit_acc=v186) + v198 ImmData(396) -> x7 + v199 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v200 FpCast { kind=F32ToF64, value=v193 } -> d0 + v201 CallExt { binding_idx=0, args=[v198, v200], fp_arg_mask=0x2 } -> x0 + v202 Imm(15) -> x3 + v203 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v202) block 27 start_pc=0 - v187 ImmData(380) -> x7 - v188 Imm(4607182418800017408) -> x0 - v189 FpCast { kind=F64ToF32, value=v188 } -> d0 [f32] - v190 Imm(4611686018427387904) -> x0 - v191 FpCast { kind=F64ToF32, value=v190 } -> d1 [f32] - v192 Imm(4615063718147915776) -> x0 - v193 FpCast { kind=F64ToF32, value=v192 } -> d2 [f32] - v194 Imm(0) -> x0 - v195 Imm(0) -> x0 - v196 Imm(0) -> x0 - v197 Binop { op=fadd, lhs=v189, rhs=v191 } -> d0 [f32] - v198 Binop { op=fadd, lhs=v197, rhs=v193 } -> d0 [f32] - v199 FpCast { kind=F32ToF64, value=v198 } -> d0 - v200 CallExt { binding_idx=0, args=[v187, v199], fp_arg_mask=0x2 } -> x0 - v201 Imm(14) -> x3 - v202 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v201) + v204 Phi { incoming=[b31:v184, b26:v202], kind=I64 } -> x3 + v205 Imm(1065353216) -> x0 [f32] + v206 StoreLocal { off=-9, value=v205, kind=F32 } -> - + v207 LocalAddr(-10) -> x7 + v208 LocalAddr(-9) -> x6 + v209 Imm(4) -> x2 + v210 CallExt { binding_idx=56, args=[v207, v208, v209], fp_arg_mask=0x0 } -> x0 + v211 LoadLocal { off=-10, kind=U32 } -> x0 + v212 BinopI { op=xor, lhs=v211, rhs_imm=1065353216 } -> x0 + v213 BinopI { op=and, lhs=v212, rhs_imm=4294967295 } -> x0 + v214 BinopI { op=ne, lhs=v213, rhs_imm=0 } -> x0 + terminator Bz { cond=v214, target=b30, fall=b28 } (exit_acc=v214) block 28 start_pc=0 - v203 Phi { incoming=[b43:v172, b27:v201], kind=I64 } -> x3 - v204 Imm(4609434218613702656) -> x0 - v205 FpCast { kind=F64ToF32, value=v204 } -> d0 [f32] - v206 Imm(0) -> x0 - v207 Imm(4611686018427387904) -> x0 - v208 FpCast { kind=F64ToF32, value=v207 } -> d1 [f32] - v209 Imm(0) -> x0 - v210 LoadLocal { off=-6, kind=F32 } -> d2 [f32] - v211 LoadLocal { off=-7, kind=F32 } -> d2 [f32] - v212 Binop { op=fmul, lhs=v205, rhs=v208 } -> d0 [f32] - v213 Imm(4598175219545276416) -> x0 - v214 FpCast { kind=F32ToF64, value=v212 } -> d0 - v215 Binop { op=fadd, lhs=v214, rhs=v213 } -> d0 - v216 FpCast { kind=F64ToF32, value=v215 } -> d0 [f32] - v217 Imm(0) -> x0 - v218 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v219 Imm(4614500768194494464) -> x0 - v220 FpCast { kind=F32ToF64, value=v216 } -> d1 - v221 Binop { op=fne, lhs=v220, rhs=v219 } -> x0 - terminator Bz { cond=v221, target=b44, fall=b29 } (exit_acc=v221) + v215 ImmData(417) -> x7 + v216 LoadLocal { off=-10, kind=U32 } -> x6 + v217 CallExt { binding_idx=0, args=[v215, v216], fp_arg_mask=0x0 } -> x0 + v218 Imm(16) -> x3 + v219 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v218) block 29 start_pc=0 - v222 ImmData(396) -> x7 - v223 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v224 FpCast { kind=F32ToF64, value=v216 } -> d0 - v225 CallExt { binding_idx=0, args=[v222, v224], fp_arg_mask=0x2 } -> x0 - v226 Imm(15) -> x3 - v227 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v226) + v220 Phi { incoming=[b30:v204, b28:v218], kind=I64 } -> x3 + v221 Extend { value=v220, kind=I32 } -> x0 + terminator Return(v221) (exit_acc=v221) block 30 start_pc=0 - v228 Phi { incoming=[b44:v203, b29:v226], kind=I64 } -> x3 - v229 Imm(4607182418800017408) -> x0 - v230 FpCast { kind=F64ToF32, value=v229 } -> d0 [f32] - v231 StoreLocal { off=-9, value=v230, kind=F32 } -> - - v232 LocalAddr(-10) -> x7 - v233 LocalAddr(-9) -> x6 - v234 Imm(4) -> x2 - v235 CallExt { binding_idx=56, args=[v232, v233, v234], fp_arg_mask=0x0 } -> x0 - v236 LoadLocal { off=-10, kind=U32 } -> x0 - v237 BinopI { op=xor, lhs=v236, rhs_imm=1065353216 } -> x0 - v238 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> x0 - v239 BinopI { op=ne, lhs=v238, rhs_imm=0 } -> x0 - terminator Bz { cond=v239, target=b45, fall=b31 } (exit_acc=v239) + terminator Jmp(b29) block 31 start_pc=0 - v240 ImmData(417) -> x7 - v241 LoadLocal { off=-10, kind=U32 } -> x6 - v242 CallExt { binding_idx=0, args=[v240, v241], fp_arg_mask=0x0 } -> x0 - v243 Imm(16) -> x3 - v244 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v243) + terminator Jmp(b27) block 32 start_pc=0 - v245 Phi { incoming=[b45:v228, b31:v243], kind=I64 } -> x3 - v246 Extend { value=v245, kind=I32 } -> x0 - terminator Return(v246) (exit_acc=v246) + terminator Jmp(b25) block 33 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b23) block 34 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b21) block 35 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b19) block 36 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b17) block 37 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b15) block 38 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b13) block 39 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b11) block 40 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b9) block 41 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b7) block 42 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b5) block 43 start_pc=0 - terminator Jmp(b28) + v3 ImmData(56) -> x7 + v4 Imm(4) -> x6 + v5 CallExt { binding_idx=0, args=[v3, v4], fp_arg_mask=0x0 } -> x0 + v6 Imm(1) -> x3 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 44 start_pc=0 - terminator Jmp(b30) + v10 ImmData(80) -> x7 + v11 Imm(8) -> x6 + v12 CallExt { binding_idx=0, args=[v10, v11], fp_arg_mask=0x0 } -> x0 + v13 Imm(2) -> x3 + v14 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) block 45 start_pc=0 - terminator Jmp(b32) + v19 ImmData(105) -> x7 + v20 Imm(4) -> x6 + v21 CallExt { binding_idx=0, args=[v19, v20], fp_arg_mask=0x0 } -> x0 + v22 Imm(3) -> x3 + v23 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v22) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_literal_arith_single_precision.ssa b/tests/snapshots/ssa/float_literal_arith_single_precision.ssa new file mode 100644 index 000000000..ab5db1713 --- /dev/null +++ b/tests/snapshots/ssa/float_literal_arith_single_precision.ssa @@ -0,0 +1,228 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=step +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=F32) -> d0 [f32] + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v4 Imm(1065353216) -> x0 [f32] + v5 Binop { op=fsub, lhs=v1, rhs=v4 } -> d0 [f32] + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=blend +fn ent_pc=1 n_params=2 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=F32) -> d0 [f32] + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=F32) -> d1 [f32] + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v6 Imm(1056964608) -> x0 [f32] + v7 Binop { op=fmul, lhs=v1, rhs=v6 } -> d2 [f32] + v8 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v9 Imm(1048576000) -> x1 [f32] + v10 Binop { op=fmul, lhs=v3, rhs=v9 } -> d1 [f32] + v11 Fma { a=v1, b=v6, c=v10, neg_product=false, neg_addend=false } -> d0 [f32] + terminator Return(v11) (exit_acc=v11) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1075838976) -> x0 [f32] + v2 Imm(0) -> x1 + v3 Imm(1065353216) -> x1 [f32] + v4 Binop { op=fsub, lhs=v1, rhs=v3 } -> d0 [f32] + v5 Imm(1069547520) -> x0 [f32] + v6 Binop { op=fne, lhs=v4, rhs=v5 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 2 start_pc=0 + v8 Imm(1077936128) -> x0 [f32] + v9 Imm(1090519040) -> x1 [f32] + v10 Imm(0) -> x2 + v11 Imm(0) -> x2 + v12 Imm(1056964608) -> x2 [f32] + v13 Binop { op=fmul, lhs=v8, rhs=v12 } -> d0 [f32] + v14 Imm(1048576000) -> x6 [f32] + v15 Binop { op=fmul, lhs=v9, rhs=v14 } -> d0 [f32] + v16 Fma { a=v8, b=v12, c=v15, neg_product=false, neg_addend=false } -> d0 [f32] + v17 Imm(1080033280) -> x0 [f32] + v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) + block 3 start_pc=0 + v19 Imm(2) -> x0 + terminator Return(v19) (exit_acc=v19) + block 4 start_pc=0 + v20 Imm(0) -> x0 [f32] + v21 StoreLocal { off=-1, value=v20, kind=F32 } -> - + v22 Imm(0) -> x0 + v23 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 + v24 Imm(0) -> x0 + v25 Imm(1) -> x0 + v26 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v27 Imm(1036831949) -> x0 [f32] + v28 Binop { op=fadd, lhs=v26, rhs=v27 } -> d0 [f32] + v29 StoreLocal { off=-1, value=v28, kind=F32 } -> - + v30 Imm(0) -> x0 + v31 Imm(1) -> x0 + v32 Imm(0) -> x0 + v33 Imm(1) -> x0 + v34 Imm(1) -> x0 + v35 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v36 Imm(1036831949) -> x0 [f32] + v37 Binop { op=fadd, lhs=v35, rhs=v36 } -> d0 [f32] + v38 StoreLocal { off=-1, value=v37, kind=F32 } -> - + v39 Imm(1) -> x0 + v40 Imm(2) -> x0 + v41 Imm(0) -> x0 + v42 Imm(2) -> x0 + v43 Imm(1) -> x0 + v44 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v45 Imm(1036831949) -> x0 [f32] + v46 Binop { op=fadd, lhs=v44, rhs=v45 } -> d0 [f32] + v47 StoreLocal { off=-1, value=v46, kind=F32 } -> - + v48 Imm(2) -> x0 + v49 Imm(3) -> x0 + v50 Imm(0) -> x0 + v51 Imm(3) -> x0 + v52 Imm(1) -> x0 + v53 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v54 Imm(1036831949) -> x0 [f32] + v55 Binop { op=fadd, lhs=v53, rhs=v54 } -> d0 [f32] + v56 StoreLocal { off=-1, value=v55, kind=F32 } -> - + v57 Imm(3) -> x0 + v58 Imm(4) -> x0 + v59 Imm(0) -> x0 + v60 Imm(4) -> x0 + v61 Imm(1) -> x0 + v62 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v63 Imm(1036831949) -> x0 [f32] + v64 Binop { op=fadd, lhs=v62, rhs=v63 } -> d0 [f32] + v65 StoreLocal { off=-1, value=v64, kind=F32 } -> - + v66 Imm(4) -> x0 + v67 Imm(5) -> x0 + v68 Imm(0) -> x0 + v69 Imm(5) -> x0 + v70 Imm(1) -> x0 + v71 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v72 Imm(1036831949) -> x0 [f32] + v73 Binop { op=fadd, lhs=v71, rhs=v72 } -> d0 [f32] + v74 StoreLocal { off=-1, value=v73, kind=F32 } -> - + v75 Imm(5) -> x0 + v76 Imm(6) -> x0 + v77 Imm(0) -> x0 + v78 Imm(6) -> x0 + v79 Imm(1) -> x0 + v80 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v81 Imm(1036831949) -> x0 [f32] + v82 Binop { op=fadd, lhs=v80, rhs=v81 } -> d0 [f32] + v83 StoreLocal { off=-1, value=v82, kind=F32 } -> - + v84 Imm(6) -> x0 + v85 Imm(7) -> x0 + v86 Imm(0) -> x0 + v87 Imm(7) -> x0 + v88 Imm(1) -> x0 + v89 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v90 Imm(1036831949) -> x0 [f32] + v91 Binop { op=fadd, lhs=v89, rhs=v90 } -> d0 [f32] + v92 StoreLocal { off=-1, value=v91, kind=F32 } -> - + v93 Imm(7) -> x0 + v94 Imm(8) -> x0 + v95 Imm(0) -> x0 + v96 Imm(8) -> x0 + v97 Imm(1) -> x0 + v98 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v99 Imm(1036831949) -> x0 [f32] + v100 Binop { op=fadd, lhs=v98, rhs=v99 } -> d0 [f32] + v101 StoreLocal { off=-1, value=v100, kind=F32 } -> - + v102 Imm(8) -> x0 + v103 Imm(9) -> x0 + v104 Imm(0) -> x0 + v105 Imm(9) -> x0 + v106 Imm(1) -> x0 + v107 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v108 Imm(1036831949) -> x0 [f32] + v109 Binop { op=fadd, lhs=v107, rhs=v108 } -> d0 [f32] + v110 StoreLocal { off=-1, value=v109, kind=F32 } -> - + v111 Imm(9) -> x0 + v112 Imm(10) -> x0 + v113 Imm(0) -> x0 + v114 Imm(10) -> x0 + v115 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v115) + block 6 start_pc=0 + v116 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v117 Imm(1065353216) -> x0 [f32] + v118 Binop { op=feq, lhs=v116, rhs=v117 } -> x0 + terminator Bz { cond=v118, target=b8, fall=b7 } (exit_acc=v118) + block 7 start_pc=0 + v119 Imm(3) -> x0 + terminator Return(v119) (exit_acc=v119) + block 8 start_pc=0 + v120 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v121 Imm(1065353217) -> x0 [f32] + v122 Binop { op=fne, lhs=v120, rhs=v121 } -> x0 + terminator Bz { cond=v122, target=b10, fall=b9 } (exit_acc=v122) + block 9 start_pc=0 + v123 Imm(4) -> x0 + terminator Return(v123) (exit_acc=v123) + block 10 start_pc=0 + v124 Imm(0) -> x0 + terminator Return(v124) (exit_acc=v124) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_literal_f_suffix.ssa b/tests/snapshots/ssa/float_literal_f_suffix.ssa new file mode 100644 index 000000000..00f1aa479 --- /dev/null +++ b/tests/snapshots/ssa/float_literal_f_suffix.ssa @@ -0,0 +1,219 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=vsum +fn ent_pc=0 n_params=1 variadic=true locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-3) -> x0 + v2 LocalAddr(2) -> x1 + v3 Intrinsic { kind=4, args=[v1, v2] } -> x0 + v4 Imm(0) -> x1 + v5 FpCast { kind=IntToFp, value=v4 } -> d0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v4) + block 1 start_pc=0 + v16 LoadLocal { off=-4, kind=F64 } -> d1 + v17 LocalAddr(-3) -> x2 + v18 Imm(65544) -> x6 + v19 Intrinsic { kind=5, args=[v17, v18] } -> x2 + v20 Load { addr=v19, disp=0, kind=F64 } -> d1 + v21 Binop { op=fadd, lhs=v9, rhs=v20 } -> d0 + v22 Imm(0) -> x2 + v23 LoadLocal { off=-4, kind=F64 } -> d1 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x2 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x2 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) + block 4 start_pc=0 + v24 LocalAddr(-3) -> x0 + v25 Intrinsic { kind=6, args=[v24] } -> x0 + v26 LoadLocal { off=-4, kind=F64 } -> d1 + terminator Return(v9) (exit_acc=v9) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v3 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) + block 5 start_pc=0 + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) + block 6 start_pc=0 + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) + block 7 start_pc=0 + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) + block 8 start_pc=0 + v17 Imm(1266679808) -> x0 [f32] + v18 Binop { op=fne, lhs=v17, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b10, fall=b9 } (exit_acc=v18) + block 9 start_pc=0 + v19 Imm(9) -> x0 + terminator Return(v19) (exit_acc=v19) + block 10 start_pc=0 + v20 Imm(4715268810125344768) -> x0 + v21 Imm(4715268809856909312) -> x1 + v22 Binop { op=feq, lhs=v20, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b12, fall=b11 } (exit_acc=v22) + block 11 start_pc=0 + v23 Imm(10) -> x0 + terminator Return(v23) (exit_acc=v23) + block 12 start_pc=0 + v24 Imm(1036831949) -> x0 [f32] + v25 Imm(4591870180066957722) -> x1 + v26 FpCast { kind=F32ToF64, value=v24 } -> d0 + v27 Binop { op=feq, lhs=v26, rhs=v25 } -> x0 + terminator Bz { cond=v27, target=b14, fall=b13 } (exit_acc=v27) + block 13 start_pc=0 + v28 Imm(11) -> x0 + terminator Return(v28) (exit_acc=v28) + block 14 start_pc=0 + v29 Imm(1036831949) -> x0 [f32] + v30 Imm(4591870180174331904) -> x1 + v31 FpCast { kind=F32ToF64, value=v29 } -> d0 + v32 Binop { op=fne, lhs=v31, rhs=v30 } -> x0 + terminator Bz { cond=v32, target=b16, fall=b15 } (exit_acc=v32) + block 15 start_pc=0 + v33 Imm(12) -> x0 + terminator Return(v33) (exit_acc=v33) + block 16 start_pc=0 + v34 Imm(1036831949) -> x0 [f32] + v35 Fneg(v34) -> d0 [f32] + v36 Imm(4591870180174331904) -> x0 + v37 Fneg(v36) -> d1 + v38 FpCast { kind=F32ToF64, value=v35 } -> d0 + v39 Binop { op=fne, lhs=v38, rhs=v37 } -> x0 + terminator Bz { cond=v39, target=b18, fall=b17 } (exit_acc=v39) + block 17 start_pc=0 + v40 Imm(13) -> x0 + terminator Return(v40) (exit_acc=v40) + block 18 start_pc=0 + v41 Imm(2) -> x7 + v42 Imm(1069547520) -> x0 [f32] + v43 FpCast { kind=F32ToF64, value=v42 } -> d0 + v44 Imm(1048576000) -> x0 [f32] + v45 FpCast { kind=F32ToF64, value=v44 } -> d1 + v46 Call { target_pc=0, args=[v41, v43, v45], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 + v47 Imm(4610560118520545280) -> x0 + v48 Binop { op=fne, lhs=v46, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b20, fall=b19 } (exit_acc=v48) + block 19 start_pc=0 + v49 Imm(14) -> x0 + terminator Return(v49) (exit_acc=v49) + block 20 start_pc=0 + v50 Imm(1) -> x7 + v51 Imm(1036831949) -> x0 [f32] + v52 FpCast { kind=F32ToF64, value=v51 } -> d0 + v53 Call { target_pc=0, args=[v50, v52], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v54 Imm(4591870180174331904) -> x0 + v55 Binop { op=fne, lhs=v53, rhs=v54 } -> x0 + terminator Bz { cond=v55, target=b22, fall=b21 } (exit_acc=v55) + block 21 start_pc=0 + v56 Imm(16) -> x0 + terminator Return(v56) (exit_acc=v56) + block 22 start_pc=0 + v57 Imm(1266679809) -> x0 [f32] + v58 Binop { op=fne, lhs=v57, rhs=v57 } -> x0 + terminator Bz { cond=v58, target=b24, fall=b23 } (exit_acc=v58) + block 23 start_pc=0 + v59 Imm(15) -> x0 + terminator Return(v59) (exit_acc=v59) + block 24 start_pc=0 + v60 Imm(0) -> x0 + terminator Return(v60) (exit_acc=v60) + block 25 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 26 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 27 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 28 start_pc=0 + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) + block 29 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 30 start_pc=0 + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) + block 31 start_pc=0 + v14 Imm(7) -> x0 + terminator Return(v14) (exit_acc=v14) + block 32 start_pc=0 + v16 Imm(8) -> x0 + terminator Return(v16) (exit_acc=v16) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_literal_variadic_printf.ssa b/tests/snapshots/ssa/float_literal_variadic_printf.ssa new file mode 100644 index 000000000..7483cabab --- /dev/null +++ b/tests/snapshots/ssa/float_literal_variadic_printf.ssa @@ -0,0 +1,72 @@ +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=13 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-8) -> x7 + v2 Imm(64) -> x6 + v3 ImmData(36) -> x2 + v4 Imm(1069547520) -> x0 [f32] + v5 FpCast { kind=F32ToF64, value=v4 } -> d0 + v6 Imm(1036831949) -> x0 [f32] + v7 FpCast { kind=F32ToF64, value=v6 } -> d1 + v8 CallExt { binding_idx=3, args=[v1, v2, v3, v5, v7], fp_arg_mask=0x18 } -> x0 + v9 LocalAddr(-8) -> x7 + v10 ImmData(46) -> x6 + v11 CallExt { binding_idx=62, args=[v9, v10], fp_arg_mask=0x0 } -> x0 + v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 + terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + block 1 start_pc=0 + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) + block 2 start_pc=0 + v14 Imm(0) -> x0 + terminator Return(v14) (exit_acc=v14) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_long_double_suffix.ssa b/tests/snapshots/ssa/float_long_double_suffix.ssa index d873f207a..2d47aa7df 100644 --- a/tests/snapshots/ssa/float_long_double_suffix.ssa +++ b/tests/snapshots/ssa/float_long_double_suffix.ssa @@ -4,63 +4,65 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x0 - v2 StoreLocal { off=-1, value=v1, kind=F64 } -> - - v3 StoreLocal { off=-2, value=v1, kind=F64 } -> - - v4 StoreLocal { off=-3, value=v1, kind=F64 } -> - - v5 StoreLocal { off=-4, value=v1, kind=F64 } -> - - v6 LoadLocal { off=-1, kind=F64 } -> d0 - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 Binop { op=fne, lhs=v6, rhs=v7 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v1 Imm(1065353216) -> x0 [f32] + v2 FpCast { kind=F32ToF64, value=v1 } -> d0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(4607182418800017408) -> x0 + v6 StoreLocal { off=-3, value=v5, kind=F64 } -> - + v7 StoreLocal { off=-4, value=v5, kind=F64 } -> - + v8 LoadLocal { off=-1, kind=F64 } -> d1 + v9 LoadLocal { off=-2, kind=F64 } -> d1 + v10 Binop { op=fne, lhs=v2, rhs=v2 } -> x0 + terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) block 1 start_pc=0 - v9 Imm(11) -> x0 - terminator Return(v9) (exit_acc=v9) + v11 Imm(11) -> x0 + terminator Return(v11) (exit_acc=v11) block 2 start_pc=0 - v10 LoadLocal { off=-1, kind=F64 } -> d0 - v11 LoadLocal { off=-3, kind=F64 } -> d1 - v12 Binop { op=fne, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v12 LoadLocal { off=-1, kind=F64 } -> d1 + v13 LoadLocal { off=-3, kind=F64 } -> d1 + v14 Binop { op=fne, lhs=v2, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v13 Imm(12) -> x0 - terminator Return(v13) (exit_acc=v13) + v15 Imm(12) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v14 LoadLocal { off=-1, kind=F64 } -> d0 - v15 LoadLocal { off=-4, kind=F64 } -> d1 - v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x0 - terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) + v16 LoadLocal { off=-1, kind=F64 } -> d1 + v17 LoadLocal { off=-4, kind=F64 } -> d1 + v18 Binop { op=fne, lhs=v2, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) block 5 start_pc=0 - v17 Imm(13) -> x0 - terminator Return(v17) (exit_acc=v17) + v19 Imm(13) -> x0 + terminator Return(v19) (exit_acc=v19) block 6 start_pc=0 - v18 LoadLocal { off=-1, kind=F64 } -> d0 - v19 Imm(4607182418800017408) -> x0 - v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x0 - terminator Bz { cond=v20, target=b8, fall=b7 } (exit_acc=v20) + v20 LoadLocal { off=-1, kind=F64 } -> d1 + v21 Imm(4607182418800017408) -> x0 + v22 Binop { op=fne, lhs=v2, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) block 7 start_pc=0 - v21 Imm(14) -> x0 - terminator Return(v21) (exit_acc=v21) + v23 Imm(14) -> x0 + terminator Return(v23) (exit_acc=v23) block 8 start_pc=0 - v22 Imm(4759161926875873280) -> x0 - v23 StoreLocal { off=-5, value=v22, kind=F64 } -> - - v24 LoadLocal { off=-5, kind=F64 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v22 } -> x0 - terminator Bz { cond=v25, target=b10, fall=b9 } (exit_acc=v25) + v24 Imm(4759161926875873280) -> x0 + v25 StoreLocal { off=-5, value=v24, kind=F64 } -> - + v26 LoadLocal { off=-5, kind=F64 } -> d0 + v27 Binop { op=fne, lhs=v26, rhs=v24 } -> x0 + terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) block 9 start_pc=0 - v26 Imm(15) -> x0 - terminator Return(v26) (exit_acc=v26) + v28 Imm(15) -> x0 + terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v27 Imm(7) -> x0 - v28 Imm(0) -> x1 - v29 LoadLocal { off=-6, kind=I64 } -> x1 - v30 BinopI { op=ne, lhs=v27, rhs_imm=7 } -> x0 - terminator Bz { cond=v30, target=b12, fall=b11 } (exit_acc=v30) + v29 Imm(7) -> x0 + v30 Imm(0) -> x0 + v31 LoadLocal { off=-6, kind=I64 } -> x0 + v32 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v32) block 11 start_pc=0 - v31 Imm(16) -> x0 - terminator Return(v31) (exit_acc=v31) + v34 Imm(0) -> x0 + terminator Return(v34) (exit_acc=v34) block 12 start_pc=0 - v32 Imm(0) -> x0 - terminator Return(v32) (exit_acc=v32) + v33 Imm(16) -> x0 + terminator Return(v33) (exit_acc=v33) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_param_stack_overflow.ssa b/tests/snapshots/ssa/float_param_stack_overflow.ssa new file mode 100644 index 000000000..2dd231b59 --- /dev/null +++ b/tests/snapshots/ssa/float_param_stack_overflow.ssa @@ -0,0 +1,153 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=wsum +fn ent_pc=0 n_params=10 variadic=false locals=10 + spill_count=3 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=F32) -> d0 [f32] + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=F32) -> d1 [f32] + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=F32) -> d2 [f32] + v6 Imm(0) -> x0 + v7 ParamRef(3, kind=F32) -> d3 [f32] + v8 Imm(0) -> x0 + v9 ParamRef(4, kind=F32) -> d4 [f32] + v10 Imm(0) -> x0 + v11 ParamRef(5, kind=F32) -> d5 [f32] + v12 Imm(0) -> x0 + v13 ParamRef(6, kind=F32) -> d6 [f32] + v14 Imm(0) -> x0 + v15 ParamRef(7, kind=F32) -> d7 [f32] + v16 Imm(0) -> x0 + v17 LoadLocal { off=10, kind=F32 } -> [spill 0] [f32] + v18 Imm(0) -> x0 + v19 LoadLocal { off=11, kind=F32 } -> [spill 1] [f32] + v20 Imm(0) -> x0 + v21 LoadLocal { off=-1, kind=F32 } -> [spill 2] [f32] + v22 Imm(1065353216) -> x0 [f32] + v23 Binop { op=fmul, lhs=v1, rhs=v22 } -> [spill 2] [f32] + v24 LoadLocal { off=-2, kind=F32 } -> [spill 2] [f32] + v25 Imm(1073741824) -> x1 [f32] + v26 Binop { op=fmul, lhs=v3, rhs=v25 } -> d1 [f32] + v27 Fma { a=v1, b=v22, c=v26, neg_product=false, neg_addend=false } -> d0 [f32] + v28 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v29 Imm(1082130432) -> x0 [f32] + v30 Binop { op=fmul, lhs=v5, rhs=v29 } -> d1 [f32] + v31 Fma { a=v5, b=v29, c=v27, neg_product=false, neg_addend=false } -> d0 [f32] + v32 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v33 Imm(1090519040) -> x0 [f32] + v34 Binop { op=fmul, lhs=v7, rhs=v33 } -> d1 [f32] + v35 Fma { a=v7, b=v33, c=v31, neg_product=false, neg_addend=false } -> d0 [f32] + v36 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v37 Imm(1098907648) -> x0 [f32] + v38 Binop { op=fmul, lhs=v9, rhs=v37 } -> d1 [f32] + v39 Fma { a=v9, b=v37, c=v35, neg_product=false, neg_addend=false } -> d0 [f32] + v40 LoadLocal { off=-6, kind=F32 } -> d1 [f32] + v41 Imm(1107296256) -> x0 [f32] + v42 Binop { op=fmul, lhs=v11, rhs=v41 } -> d1 [f32] + v43 Fma { a=v11, b=v41, c=v39, neg_product=false, neg_addend=false } -> d0 [f32] + v44 LoadLocal { off=-7, kind=F32 } -> d1 [f32] + v45 Imm(1115684864) -> x0 [f32] + v46 Binop { op=fmul, lhs=v13, rhs=v45 } -> d1 [f32] + v47 Fma { a=v13, b=v45, c=v43, neg_product=false, neg_addend=false } -> d0 [f32] + v48 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v49 Imm(1124073472) -> x0 [f32] + v50 Binop { op=fmul, lhs=v15, rhs=v49 } -> d1 [f32] + v51 Fma { a=v15, b=v49, c=v47, neg_product=false, neg_addend=false } -> d0 [f32] + v52 LoadLocal { off=-9, kind=F32 } -> d1 [f32] + v53 Imm(1132462080) -> x0 [f32] + v54 Binop { op=fmul, lhs=v17, rhs=v53 } -> d1 [f32] + v55 Fma { a=v17, b=v53, c=v51, neg_product=false, neg_addend=false } -> d0 [f32] + v56 LoadLocal { off=-10, kind=F32 } -> d1 [f32] + v57 Imm(1140850688) -> x0 [f32] + v58 Binop { op=fmul, lhs=v19, rhs=v57 } -> d1 [f32] + v59 Fma { a=v19, b=v57, c=v55, neg_product=false, neg_addend=false } -> d0 [f32] + v60 FpCast { kind=F32ToF64, value=v59 } -> d0 + v61 FpCast { kind=FpToInt, value=v60 } -> x0 + terminator Return(v61) (exit_acc=v61) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=14 + spill_count=1 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmData(8) -> x0 + v2 Load { addr=v1, disp=0, kind=F32, volatile } -> [spill 0] [f32] + v3 Imm(0) -> x0 + v4 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v5 Call { target_pc=0, args=[v2, v2, v2, v2, v2, v2, v2, v2, v2, v2], fixed_args=10, fp_return=false, fp_arg_mask=0x3ff } -> x0 + v6 Imm(0) -> x1 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=ne, lhs=v7, rhs_imm=1023 } -> x0 + terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + block 1 start_pc=0 + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) + block 2 start_pc=0 + v10 ImmCode(ent_pc=0) -> x0 + v11 Imm(0) -> x1 + v12 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v13 Imm(1069547520) -> x7 [f32] + v14 Imm(1056964608) -> x6 [f32] + v15 LoadLocal { off=-3, kind=I64 } -> x1 + v16 CallIndirect { target=v10, args=[v2, v2, v2, v2, v2, v2, v2, v2, v13, v14], callee_variadic=false, fixed_args=10, fp_return=false, fp_arg_mask=0x3ff } -> x0 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 + v18 Extend { value=v16, kind=I32 } -> x0 + v19 Imm(0) -> x1 + v20 LoadLocal { off=-4, kind=I32 } -> x1 + v21 BinopI { op=ne, lhs=v18, rhs_imm=895 } -> x0 + terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) + block 3 start_pc=0 + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) + block 4 start_pc=0 + v23 Imm(0) -> x0 + terminator Return(v23) (exit_acc=v23) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_pointer_basics.ssa b/tests/snapshots/ssa/float_pointer_basics.ssa index 156b130fb..195d27bbd 100644 --- a/tests/snapshots/ssa/float_pointer_basics.ssa +++ b/tests/snapshots/ssa/float_pointer_basics.ssa @@ -5,36 +5,30 @@ fn ent_pc=5 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4) -> x0 - v2 Imm(0) -> x1 - v3 Imm(8) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-4, kind=I32 } -> x2 - v6 BinopI { op=ne, lhs=v1, rhs_imm=4 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(8) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-4, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 LoadLocal { off=-5, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v3, rhs_imm=8 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) - block 3 start_pc=0 - v10 Imm(2) -> x0 - terminator Return(v10) (exit_acc=v10) - block 4 start_pc=0 - v11 Imm(4) -> x3 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 + v11 Imm(4) -> x0 v12 Imm(0) -> x0 v13 LoadLocal { off=-3, kind=I32 } -> x0 - v14 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x0 - v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 - v16 Extend { value=v14, kind=I32 } -> x7 - v17 CallExt { binding_idx=0, args=[v16], fp_arg_mask=0x0 } -> x12 + v14 Imm(16) -> x0 + v15 Imm(68719476736) -> x0 + v16 Imm(16) -> x7 + v17 CallExt { binding_idx=0, args=[v16], fp_arg_mask=0x0 } -> x3 v18 Imm(0) -> x0 v19 LoadLocal { off=-3, kind=I32 } -> x0 - v20 BinopI { op=shl, lhs=v11, rhs_imm=3 } -> x0 - v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x1 - v22 Extend { value=v20, kind=I32 } -> x7 - v23 CallExt { binding_idx=0, args=[v22], fp_arg_mask=0x0 } -> x3 + v20 Imm(32) -> x0 + v21 Imm(137438953472) -> x0 + v22 Imm(32) -> x7 + v23 CallExt { binding_idx=0, args=[v22], fp_arg_mask=0x0 } -> x12 v24 Imm(0) -> x0 v25 LoadLocal { off=-1, kind=I64 } -> x0 v26 Imm(0) -> x0 @@ -55,46 +49,52 @@ fn ent_pc=5 n_params=0 variadic=false locals=6 v41 LoadLocal { off=-1, kind=I64 } -> x0 v42 Load { addr=v17, disp=0, kind=I32 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=1065353216 } -> x0 - terminator Bz { cond=v43, target=b6, fall=b5 } (exit_acc=v43) - block 5 start_pc=0 + terminator Bz { cond=v43, target=b4, fall=b3 } (exit_acc=v43) + block 3 start_pc=0 v44 Imm(3) -> x0 terminator Return(v44) (exit_acc=v44) - block 6 start_pc=0 + block 4 start_pc=0 v45 LoadLocal { off=-1, kind=I64 } -> x0 v46 Imm(4) -> x0 v47 BinopI { op=add, lhs=v17, rhs_imm=4 } -> x0 v48 Load { addr=v17, disp=4, kind=I32 } -> x0 v49 BinopI { op=ne, lhs=v48, rhs_imm=1073741824 } -> x0 - terminator Bz { cond=v49, target=b8, fall=b7 } (exit_acc=v49) - block 7 start_pc=0 + terminator Bz { cond=v49, target=b6, fall=b5 } (exit_acc=v49) + block 5 start_pc=0 v50 Imm(4) -> x0 terminator Return(v50) (exit_acc=v50) - block 8 start_pc=0 + block 6 start_pc=0 v51 LoadLocal { off=-2, kind=I64 } -> x0 v52 Imm(0) -> x0 v53 Load { addr=v23, disp=0, kind=I64 } -> x0 v54 BinopI { op=ne, lhs=v53, rhs_imm=4607182418800017408 } -> x0 - terminator Bz { cond=v54, target=b10, fall=b9 } (exit_acc=v54) - block 9 start_pc=0 + terminator Bz { cond=v54, target=b8, fall=b7 } (exit_acc=v54) + block 7 start_pc=0 v55 Imm(5) -> x0 terminator Return(v55) (exit_acc=v55) - block 10 start_pc=0 + block 8 start_pc=0 v56 LoadLocal { off=-2, kind=I64 } -> x0 v57 Imm(8) -> x0 v58 BinopI { op=add, lhs=v23, rhs_imm=8 } -> x0 v59 Load { addr=v23, disp=8, kind=I64 } -> x0 v60 BinopI { op=ne, lhs=v59, rhs_imm=4611686018427387904 } -> x0 - terminator Bz { cond=v60, target=b12, fall=b11 } (exit_acc=v60) - block 11 start_pc=0 + terminator Bz { cond=v60, target=b10, fall=b9 } (exit_acc=v60) + block 9 start_pc=0 v61 Imm(6) -> x0 terminator Return(v61) (exit_acc=v61) - block 12 start_pc=0 + block 10 start_pc=0 v62 LoadLocal { off=-1, kind=I64 } -> x0 v63 CallExt { binding_idx=3, args=[v17], fp_arg_mask=0x0 } -> x0 v64 LoadLocal { off=-2, kind=I64 } -> x0 v65 CallExt { binding_idx=3, args=[v23], fp_arg_mask=0x0 } -> x0 v66 Imm(0) -> x0 terminator Return(v66) (exit_acc=v66) + block 11 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 12 start_pc=0 + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_register_resident.ssa b/tests/snapshots/ssa/float_register_resident.ssa index 6da90bfc7..66f867eca 100644 --- a/tests/snapshots/ssa/float_register_resident.ssa +++ b/tests/snapshots/ssa/float_register_resident.ssa @@ -22,47 +22,220 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] + v1 Imm(0) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - v3 Imm(0) -> x0 - v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + v4 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v2, b2:v28], kind=F32 } -> d0 [f32] - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=10 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) - block 2 start_pc=0 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) - block 3 start_pc=0 - v12 Extend { value=v5, kind=I32 } -> x0 - v13 FpCast { kind=IntToFp, value=v12 } -> d1 - v14 FpCast { kind=F64ToF32, value=v13 } -> d1 [f32] - v15 Imm(4602678819172646912) -> x0 - v16 FpCast { kind=F32ToF64, value=v14 } -> d1 - v17 Binop { op=fmul, lhs=v16, rhs=v15 } -> d1 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Imm(0) -> x0 - v20 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v21 Imm(4611686018427387904) -> x0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d2 [f32] - v23 LoadLocal { off=-1, kind=F32 } -> d3 [f32] + v5 Imm(0) -> x0 + v6 Imm(1) -> x0 + v7 Imm(0) -> x0 + v8 FpCast { kind=IntToFp, value=v7 } -> d0 + v9 FpCast { kind=F64ToF32, value=v8 } -> d0 [f32] + v10 Imm(1056964608) -> x0 [f32] + v11 Binop { op=fmul, lhs=v9, rhs=v10 } -> d0 [f32] + v12 Imm(0) -> x0 + v13 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v14 Imm(1073741824) -> x0 [f32] + v15 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v16 Imm(0) -> x1 + v17 Imm(0) -> x1 + v18 Imm(0) -> x1 + v19 Binop { op=fmul, lhs=v11, rhs=v14 } -> d2 [f32] + v20 Fma { a=v11, b=v14, c=v15, neg_product=false, neg_addend=false } -> d0 [f32] + v21 StoreLocal { off=-1, value=v20, kind=F32 } -> - + v22 Imm(0) -> x0 + v23 Imm(1) -> x0 v24 Imm(0) -> x0 - v25 Imm(0) -> x0 - v26 Imm(0) -> x0 - v27 Binop { op=fmul, lhs=v18, rhs=v22 } -> d3 [f32] - v28 Fma { a=v18, b=v22, c=v6, neg_product=false, neg_addend=false } -> d0 [f32] - v29 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v28) - block 4 start_pc=0 - v30 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v31 FpCast { kind=F32ToF64, value=v6 } -> d0 - v32 FpCast { kind=FpToInt, value=v31 } -> x0 - terminator Return(v32) (exit_acc=v32) + v25 Imm(1) -> x0 + v26 Imm(1) -> x0 + v27 Imm(1) -> x0 + v28 FpCast { kind=IntToFp, value=v27 } -> d0 + v29 FpCast { kind=F64ToF32, value=v28 } -> d0 [f32] + v30 Imm(1056964608) -> x0 [f32] + v31 Binop { op=fmul, lhs=v29, rhs=v30 } -> d0 [f32] + v32 Imm(0) -> x0 + v33 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v34 Imm(1073741824) -> x0 [f32] + v35 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v36 Imm(0) -> x1 + v37 Imm(0) -> x1 + v38 Imm(0) -> x1 + v39 Binop { op=fmul, lhs=v31, rhs=v34 } -> d2 [f32] + v40 Fma { a=v31, b=v34, c=v35, neg_product=false, neg_addend=false } -> d0 [f32] + v41 StoreLocal { off=-1, value=v40, kind=F32 } -> - + v42 Imm(1) -> x0 + v43 Imm(2) -> x0 + v44 Imm(0) -> x0 + v45 Imm(2) -> x0 + v46 Imm(1) -> x0 + v47 Imm(2) -> x0 + v48 FpCast { kind=IntToFp, value=v47 } -> d0 + v49 FpCast { kind=F64ToF32, value=v48 } -> d0 [f32] + v50 Imm(1056964608) -> x0 [f32] + v51 Binop { op=fmul, lhs=v49, rhs=v50 } -> d0 [f32] + v52 Imm(0) -> x0 + v53 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v54 Imm(1073741824) -> x0 [f32] + v55 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v56 Imm(0) -> x1 + v57 Imm(0) -> x1 + v58 Imm(0) -> x1 + v59 Binop { op=fmul, lhs=v51, rhs=v54 } -> d2 [f32] + v60 Fma { a=v51, b=v54, c=v55, neg_product=false, neg_addend=false } -> d0 [f32] + v61 StoreLocal { off=-1, value=v60, kind=F32 } -> - + v62 Imm(2) -> x0 + v63 Imm(3) -> x0 + v64 Imm(0) -> x0 + v65 Imm(3) -> x0 + v66 Imm(1) -> x0 + v67 Imm(3) -> x0 + v68 FpCast { kind=IntToFp, value=v67 } -> d0 + v69 FpCast { kind=F64ToF32, value=v68 } -> d0 [f32] + v70 Imm(1056964608) -> x0 [f32] + v71 Binop { op=fmul, lhs=v69, rhs=v70 } -> d0 [f32] + v72 Imm(0) -> x0 + v73 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v74 Imm(1073741824) -> x0 [f32] + v75 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v76 Imm(0) -> x1 + v77 Imm(0) -> x1 + v78 Imm(0) -> x1 + v79 Binop { op=fmul, lhs=v71, rhs=v74 } -> d2 [f32] + v80 Fma { a=v71, b=v74, c=v75, neg_product=false, neg_addend=false } -> d0 [f32] + v81 StoreLocal { off=-1, value=v80, kind=F32 } -> - + v82 Imm(3) -> x0 + v83 Imm(4) -> x0 + v84 Imm(0) -> x0 + v85 Imm(4) -> x0 + v86 Imm(1) -> x0 + v87 Imm(4) -> x0 + v88 FpCast { kind=IntToFp, value=v87 } -> d0 + v89 FpCast { kind=F64ToF32, value=v88 } -> d0 [f32] + v90 Imm(1056964608) -> x0 [f32] + v91 Binop { op=fmul, lhs=v89, rhs=v90 } -> d0 [f32] + v92 Imm(0) -> x0 + v93 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v94 Imm(1073741824) -> x0 [f32] + v95 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v96 Imm(0) -> x1 + v97 Imm(0) -> x1 + v98 Imm(0) -> x1 + v99 Binop { op=fmul, lhs=v91, rhs=v94 } -> d2 [f32] + v100 Fma { a=v91, b=v94, c=v95, neg_product=false, neg_addend=false } -> d0 [f32] + v101 StoreLocal { off=-1, value=v100, kind=F32 } -> - + v102 Imm(4) -> x0 + v103 Imm(5) -> x0 + v104 Imm(0) -> x0 + v105 Imm(5) -> x0 + v106 Imm(1) -> x0 + v107 Imm(5) -> x0 + v108 FpCast { kind=IntToFp, value=v107 } -> d0 + v109 FpCast { kind=F64ToF32, value=v108 } -> d0 [f32] + v110 Imm(1056964608) -> x0 [f32] + v111 Binop { op=fmul, lhs=v109, rhs=v110 } -> d0 [f32] + v112 Imm(0) -> x0 + v113 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v114 Imm(1073741824) -> x0 [f32] + v115 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v116 Imm(0) -> x1 + v117 Imm(0) -> x1 + v118 Imm(0) -> x1 + v119 Binop { op=fmul, lhs=v111, rhs=v114 } -> d2 [f32] + v120 Fma { a=v111, b=v114, c=v115, neg_product=false, neg_addend=false } -> d0 [f32] + v121 StoreLocal { off=-1, value=v120, kind=F32 } -> - + v122 Imm(5) -> x0 + v123 Imm(6) -> x0 + v124 Imm(0) -> x0 + v125 Imm(6) -> x0 + v126 Imm(1) -> x0 + v127 Imm(6) -> x0 + v128 FpCast { kind=IntToFp, value=v127 } -> d0 + v129 FpCast { kind=F64ToF32, value=v128 } -> d0 [f32] + v130 Imm(1056964608) -> x0 [f32] + v131 Binop { op=fmul, lhs=v129, rhs=v130 } -> d0 [f32] + v132 Imm(0) -> x0 + v133 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v134 Imm(1073741824) -> x0 [f32] + v135 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v136 Imm(0) -> x1 + v137 Imm(0) -> x1 + v138 Imm(0) -> x1 + v139 Binop { op=fmul, lhs=v131, rhs=v134 } -> d2 [f32] + v140 Fma { a=v131, b=v134, c=v135, neg_product=false, neg_addend=false } -> d0 [f32] + v141 StoreLocal { off=-1, value=v140, kind=F32 } -> - + v142 Imm(6) -> x0 + v143 Imm(7) -> x0 + v144 Imm(0) -> x0 + v145 Imm(7) -> x0 + v146 Imm(1) -> x0 + v147 Imm(7) -> x0 + v148 FpCast { kind=IntToFp, value=v147 } -> d0 + v149 FpCast { kind=F64ToF32, value=v148 } -> d0 [f32] + v150 Imm(1056964608) -> x0 [f32] + v151 Binop { op=fmul, lhs=v149, rhs=v150 } -> d0 [f32] + v152 Imm(0) -> x0 + v153 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v154 Imm(1073741824) -> x0 [f32] + v155 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v156 Imm(0) -> x1 + v157 Imm(0) -> x1 + v158 Imm(0) -> x1 + v159 Binop { op=fmul, lhs=v151, rhs=v154 } -> d2 [f32] + v160 Fma { a=v151, b=v154, c=v155, neg_product=false, neg_addend=false } -> d0 [f32] + v161 StoreLocal { off=-1, value=v160, kind=F32 } -> - + v162 Imm(7) -> x0 + v163 Imm(8) -> x0 + v164 Imm(0) -> x0 + v165 Imm(8) -> x0 + v166 Imm(1) -> x0 + v167 Imm(8) -> x0 + v168 FpCast { kind=IntToFp, value=v167 } -> d0 + v169 FpCast { kind=F64ToF32, value=v168 } -> d0 [f32] + v170 Imm(1056964608) -> x0 [f32] + v171 Binop { op=fmul, lhs=v169, rhs=v170 } -> d0 [f32] + v172 Imm(0) -> x0 + v173 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v174 Imm(1073741824) -> x0 [f32] + v175 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v176 Imm(0) -> x1 + v177 Imm(0) -> x1 + v178 Imm(0) -> x1 + v179 Binop { op=fmul, lhs=v171, rhs=v174 } -> d2 [f32] + v180 Fma { a=v171, b=v174, c=v175, neg_product=false, neg_addend=false } -> d0 [f32] + v181 StoreLocal { off=-1, value=v180, kind=F32 } -> - + v182 Imm(8) -> x0 + v183 Imm(9) -> x0 + v184 Imm(0) -> x0 + v185 Imm(9) -> x0 + v186 Imm(1) -> x0 + v187 Imm(9) -> x0 + v188 FpCast { kind=IntToFp, value=v187 } -> d0 + v189 FpCast { kind=F64ToF32, value=v188 } -> d0 [f32] + v190 Imm(1056964608) -> x0 [f32] + v191 Binop { op=fmul, lhs=v189, rhs=v190 } -> d0 [f32] + v192 Imm(0) -> x0 + v193 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v194 Imm(1073741824) -> x0 [f32] + v195 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v196 Imm(0) -> x1 + v197 Imm(0) -> x1 + v198 Imm(0) -> x1 + v199 Binop { op=fmul, lhs=v191, rhs=v194 } -> d2 [f32] + v200 Fma { a=v191, b=v194, c=v195, neg_product=false, neg_addend=false } -> d0 [f32] + v201 StoreLocal { off=-1, value=v200, kind=F32 } -> - + v202 Imm(9) -> x0 + v203 Imm(10) -> x0 + v204 Imm(0) -> x0 + v205 Imm(10) -> x0 + v206 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v206) + block 2 start_pc=0 + v207 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v208 FpCast { kind=F32ToF64, value=v207 } -> d0 + v209 FpCast { kind=FpToInt, value=v208 } -> x0 + terminator Return(v209) (exit_acc=v209) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_single_precision.ssa b/tests/snapshots/ssa/float_single_precision.ssa index 28e982dde..9ad752830 100644 --- a/tests/snapshots/ssa/float_single_precision.ssa +++ b/tests/snapshots/ssa/float_single_precision.ssa @@ -4,42 +4,39 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x0 - v2 Imm(4613937818241073152) -> x1 - v3 Binop { op=fdiv, lhs=v1, rhs=v2 } -> d0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 Imm(0) -> x0 - v6 Imm(4599676419595205767) -> x0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v10 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v11 Binop { op=fsub, lhs=v4, rhs=v7 } -> d1 [f32] + v1 Imm(1065353216) -> x0 [f32] + v2 Imm(1077936128) -> x1 [f32] + v3 Binop { op=fdiv, lhs=v1, rhs=v2 } -> d0 [f32] + v4 Imm(0) -> x0 + v5 Imm(1051372203) -> x0 [f32] + v6 StoreLocal { off=-2, value=v5, kind=F32 } -> - + v7 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v8 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v9 Binop { op=fsub, lhs=v3, rhs=v8 } -> d1 [f32] + v10 Imm(0) -> x0 + v11 LoadLocal { off=-3, kind=F32 } -> d0 [f32] v12 Imm(0) -> x0 - v13 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v14 Imm(0) -> x0 - v15 FpCast { kind=IntToFp, value=v14 } -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Binop { op=flt, lhs=v11, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b5, fall=b1 } (exit_acc=v17) + v13 FpCast { kind=IntToFp, value=v12 } -> d0 + v14 FpCast { kind=F64ToF32, value=v13 } -> d0 [f32] + v15 Binop { op=flt, lhs=v9, rhs=v14 } -> x0 + terminator Bz { cond=v15, target=b5, fall=b1 } (exit_acc=v15) block 1 start_pc=0 - v18 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v19 Fneg(v11) -> d1 [f32] - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v16 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v17 Fneg(v9) -> d1 [f32] + v18 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 - v21 Phi { incoming=[b5:v11, b1:v19], kind=F32 } -> d1 [f32] - v22 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v23 Imm(4502148214488346440) -> x0 - v24 FpCast { kind=F32ToF64, value=v21 } -> d0 - v25 Binop { op=fgt, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v19 Phi { incoming=[b5:v9, b1:v17], kind=F32 } -> d1 [f32] + v20 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v21 Imm(869711765) -> x0 [f32] + v22 Binop { op=fgt, lhs=v19, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v23 Imm(1) -> x0 + terminator Return(v23) (exit_acc=v23) block 4 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v24 Imm(0) -> x0 + terminator Return(v24) (exit_acc=v24) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -48,118 +45,195 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 StoreLocal { off=-1, value=v2, kind=F32 } -> - - v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + v1 Imm(0) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(0) -> x0 + v4 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v6 Extend { value=v5, kind=I32 } -> x0 - v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x0 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v5 Imm(0) -> x0 + v6 Imm(1) -> x0 + v7 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v8 Imm(1036831949) -> x0 [f32] + v9 Binop { op=fadd, lhs=v7, rhs=v8 } -> d0 [f32] + v10 StoreLocal { off=-1, value=v9, kind=F32 } -> - + v11 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(1) -> x0 + v17 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v18 Imm(1036831949) -> x0 [f32] + v19 Binop { op=fadd, lhs=v11, rhs=v18 } -> d0 [f32] + v20 StoreLocal { off=-1, value=v19, kind=F32 } -> - + v21 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v22 Imm(1) -> x0 + v23 Imm(2) -> x0 + v24 Imm(0) -> x0 + v25 Imm(2) -> x0 + v26 Imm(1) -> x0 + v27 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v28 Imm(1036831949) -> x0 [f32] + v29 Binop { op=fadd, lhs=v21, rhs=v28 } -> d0 [f32] + v30 StoreLocal { off=-1, value=v29, kind=F32 } -> - + v31 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v32 Imm(2) -> x0 + v33 Imm(3) -> x0 + v34 Imm(0) -> x0 + v35 Imm(3) -> x0 + v36 Imm(1) -> x0 + v37 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v38 Imm(1036831949) -> x0 [f32] + v39 Binop { op=fadd, lhs=v31, rhs=v38 } -> d0 [f32] + v40 StoreLocal { off=-1, value=v39, kind=F32 } -> - + v41 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v42 Imm(3) -> x0 + v43 Imm(4) -> x0 + v44 Imm(0) -> x0 + v45 Imm(4) -> x0 + v46 Imm(1) -> x0 + v47 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v48 Imm(1036831949) -> x0 [f32] + v49 Binop { op=fadd, lhs=v41, rhs=v48 } -> d0 [f32] + v50 StoreLocal { off=-1, value=v49, kind=F32 } -> - + v51 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v52 Imm(4) -> x0 + v53 Imm(5) -> x0 + v54 Imm(0) -> x0 + v55 Imm(5) -> x0 + v56 Imm(1) -> x0 + v57 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v58 Imm(1036831949) -> x0 [f32] + v59 Binop { op=fadd, lhs=v51, rhs=v58 } -> d0 [f32] + v60 StoreLocal { off=-1, value=v59, kind=F32 } -> - + v61 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v62 Imm(5) -> x0 + v63 Imm(6) -> x0 + v64 Imm(0) -> x0 + v65 Imm(6) -> x0 + v66 Imm(1) -> x0 + v67 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v68 Imm(1036831949) -> x0 [f32] + v69 Binop { op=fadd, lhs=v61, rhs=v68 } -> d0 [f32] + v70 StoreLocal { off=-1, value=v69, kind=F32 } -> - + v71 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v72 Imm(6) -> x0 + v73 Imm(7) -> x0 + v74 Imm(0) -> x0 + v75 Imm(7) -> x0 + v76 Imm(1) -> x0 + v77 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v78 Imm(1036831949) -> x0 [f32] + v79 Binop { op=fadd, lhs=v71, rhs=v78 } -> d0 [f32] + v80 StoreLocal { off=-1, value=v79, kind=F32 } -> - + v81 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v82 Imm(7) -> x0 + v83 Imm(8) -> x0 + v84 Imm(0) -> x0 + v85 Imm(8) -> x0 + v86 Imm(1) -> x0 + v87 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v88 Imm(1036831949) -> x0 [f32] + v89 Binop { op=fadd, lhs=v81, rhs=v88 } -> d0 [f32] + v90 StoreLocal { off=-1, value=v89, kind=F32 } -> - + v91 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v92 Imm(8) -> x0 + v93 Imm(9) -> x0 + v94 Imm(0) -> x0 + v95 Imm(9) -> x0 + v96 Imm(1) -> x0 + v97 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v98 Imm(1036831949) -> x0 [f32] + v99 Binop { op=fadd, lhs=v91, rhs=v98 } -> d0 [f32] + v100 StoreLocal { off=-1, value=v99, kind=F32 } -> - + v101 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v102 Imm(9) -> x0 + v103 Imm(10) -> x0 + v104 Imm(0) -> x0 + v105 Imm(10) -> x0 + v106 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v106) block 2 start_pc=0 - v8 Extend { value=v5, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + v107 Imm(1065353217) -> x0 [f32] + v108 StoreLocal { off=-3, value=v107, kind=F32 } -> - + v109 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v110 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v111 Binop { op=fsub, lhs=v109, rhs=v110 } -> d1 [f32] + v112 Imm(0) -> x0 + v113 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v114 Imm(0) -> x0 + v115 FpCast { kind=IntToFp, value=v114 } -> d0 + v116 FpCast { kind=F64ToF32, value=v115 } -> d0 [f32] + v117 Binop { op=flt, lhs=v111, rhs=v116 } -> x0 + terminator Bz { cond=v117, target=b9, fall=b3 } (exit_acc=v117) block 3 start_pc=0 - v11 LocalAddr(-1) -> x0 - v12 Load { addr=v11, disp=0, kind=F32 } -> d0 [f32] - v13 Imm(4591870180066957722) -> x2 - v14 FpCast { kind=F32ToF64, value=v12 } -> d0 - v15 Binop { op=fadd, lhs=v14, rhs=v13 } -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Store { addr=v11, disp=0, value=v16, kind=F32 } -> - - v18 Load { addr=v11, disp=0, kind=F32 } -> d0 [f32] - terminator Jmp(b2) (exit_acc=v18) + v118 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v119 Fneg(v111) -> d1 [f32] + v120 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v119) block 4 start_pc=0 - v19 Imm(4607182419250377371) -> x0 - v20 FpCast { kind=F64ToF32, value=v19 } -> d0 [f32] - v21 Imm(0) -> x0 - v22 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v23 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v24 Binop { op=fsub, lhs=v22, rhs=v20 } -> d1 [f32] - v25 Imm(0) -> x0 - v26 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v27 Imm(0) -> x0 - v28 FpCast { kind=IntToFp, value=v27 } -> d0 - v29 FpCast { kind=F64ToF32, value=v28 } -> d0 [f32] - v30 Binop { op=flt, lhs=v24, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b11, fall=b5 } (exit_acc=v30) + v121 Phi { incoming=[b9:v111, b3:v119], kind=F32 } -> d1 [f32] + v122 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v123 Imm(897988541) -> x0 [f32] + v124 Binop { op=fgt, lhs=v121, rhs=v123 } -> x0 + terminator Bz { cond=v124, target=b6, fall=b5 } (exit_acc=v124) block 5 start_pc=0 - v31 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v32 Fneg(v24) -> d1 [f32] - v33 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v32) + v125 Imm(2) -> x0 + terminator Return(v125) (exit_acc=v125) block 6 start_pc=0 - v34 Phi { incoming=[b11:v24, b5:v32], kind=F32 } -> d1 [f32] - v35 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v36 Imm(4517329193108106637) -> x0 - v37 FpCast { kind=F32ToF64, value=v34 } -> d0 - v38 Binop { op=fgt, lhs=v37, rhs=v36 } -> x0 - terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + v126 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v127 Imm(1065353216) -> x0 [f32] + v128 Binop { op=feq, lhs=v126, rhs=v127 } -> x0 + terminator Bz { cond=v128, target=b8, fall=b7 } (exit_acc=v128) block 7 start_pc=0 - v39 Imm(2) -> x0 - terminator Return(v39) (exit_acc=v39) + v129 Imm(3) -> x0 + terminator Return(v129) (exit_acc=v129) block 8 start_pc=0 - v40 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v41 Imm(4607182418800017408) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 - v43 Binop { op=feq, lhs=v42, rhs=v41 } -> x0 - terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) + v130 Imm(0) -> x0 + terminator Return(v130) (exit_acc=v130) block 9 start_pc=0 - v44 Imm(3) -> x0 - terminator Return(v44) (exit_acc=v44) - block 10 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) - block 11 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=chained_mul_is_single_precision fn ent_pc=2 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607632778762754458) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v5 Binop { op=fmul, lhs=v2, rhs=v2 } -> d1 [f32] - v6 Binop { op=fmul, lhs=v5, rhs=v2 } -> d1 [f32] - v7 Binop { op=fmul, lhs=v6, rhs=v2 } -> d0 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v10 Imm(4609272539837440018) -> x0 - v11 FpCast { kind=F32ToF64, value=v7 } -> d0 - v12 Binop { op=fsub, lhs=v11, rhs=v10 } -> d0 - v13 FpCast { kind=F64ToF32, value=v12 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Binop { op=flt, lhs=v13, rhs=v18 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b1 } (exit_acc=v19) + v1 Imm(1066192077) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 Binop { op=fmul, lhs=v3, rhs=v3 } -> d1 [f32] + v5 Binop { op=fmul, lhs=v4, rhs=v3 } -> d1 [f32] + v6 Binop { op=fmul, lhs=v5, rhs=v3 } -> d2 [f32] + v7 Imm(0) -> x0 + v8 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v9 Imm(1069246370) -> x0 [f32] + v10 Fma { a=v5, b=v3, c=v9, neg_product=false, neg_addend=true } -> d1 [f32] + v11 Imm(0) -> x0 + v12 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v13 Imm(0) -> x0 + v14 FpCast { kind=IntToFp, value=v13 } -> d0 + v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] + v16 Binop { op=flt, lhs=v10, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b5, fall=b1 } (exit_acc=v16) block 1 start_pc=0 - v20 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v21 Fneg(v13) -> d1 [f32] - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v21) + v17 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v18 Fneg(v10) -> d1 [f32] + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v23 Phi { incoming=[b5:v13, b1:v21], kind=F32 } -> d1 [f32] - v24 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v25 Imm(4532020583610935537) -> x0 - v26 FpCast { kind=F32ToF64, value=v23 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v20 Phi { incoming=[b5:v10, b1:v18], kind=F32 } -> d1 [f32] + v21 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v22 Imm(925353388) -> x0 [f32] + v23 Binop { op=fgt, lhs=v20, rhs=v22 } -> x0 + terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) + v24 Imm(4) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v29 Imm(0) -> x0 - terminator Return(v29) (exit_acc=v29) + v25 Imm(0) -> x0 + terminator Return(v25) (exit_acc=v25) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=3 --- diff --git a/tests/snapshots/ssa/float_ternary_promote.ssa b/tests/snapshots/ssa/float_ternary_promote.ssa index 4d9fc570f..a27fabca2 100644 --- a/tests/snapshots/ssa/float_ternary_promote.ssa +++ b/tests/snapshots/ssa/float_ternary_promote.ssa @@ -11,21 +11,21 @@ fn ent_pc=0 n_params=3 variadic=false locals=4 v5 ParamRef(2, kind=F32) -> d1 [f32] v6 Imm(0) -> x0 v7 LoadLocal { off=2, kind=I32 } -> x0 - terminator Bz { cond=v1, target=b2, fall=b1 } (exit_acc=v1) + terminator Bz { cond=v1, target=b3, fall=b1 } (exit_acc=v1) block 1 start_pc=0 v8 LoadLocal { off=-1, kind=F32 } -> d0 [f32] v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) block 2 start_pc=0 - v10 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 3 start_pc=0 - v12 Phi { incoming=[b1:v3, b2:v5], kind=F32 } -> d2 [f32] + v12 Phi { incoming=[b1:v3, b3:v5], kind=F32 } -> d2 [f32] v13 LoadLocal { off=-4, kind=F32 } -> d0 [f32] v14 Imm(0) -> x0 v15 LoadLocal { off=-3, kind=F32 } -> d0 [f32] terminator Return(v12) (exit_acc=v12) + block 3 start_pc=0 + v10 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v11 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=8 @@ -33,121 +33,109 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x7 - v2 Imm(4609434218613702656) -> x3 - v3 FpCast { kind=F64ToF32, value=v2 } -> d0 [f32] - v4 Imm(4612811918334230528) -> x0 - v5 Fneg(v4) -> d1 - v6 FpCast { kind=F64ToF32, value=v5 } -> d1 [f32] - v7 Call { target_pc=0, args=[v1, v3, v6], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v8 FpCast { kind=F32ToF64, value=v7 } -> d0 - v9 Binop { op=fne, lhs=v8, rhs=v2 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v2 Imm(1069547520) -> x3 [f32] + v3 Imm(1075838976) -> x0 [f32] + v4 Fneg(v3) -> d0 [f32] + v5 Call { target_pc=0, args=[v1, v2, v4], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v6 Binop { op=fne, lhs=v5, rhs=v2 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 2 start_pc=0 - v11 Imm(0) -> x7 - v12 Imm(4609434218613702656) -> x0 - v13 FpCast { kind=F64ToF32, value=v12 } -> d0 [f32] - v14 Imm(4612811918334230528) -> x0 - v15 Fneg(v14) -> [spill 0] - v16 FpCast { kind=F64ToF32, value=v15 } -> d1 [f32] - v17 Call { target_pc=0, args=[v11, v13, v16], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v18 FpCast { kind=F32ToF64, value=v17 } -> d0 - v19 Binop { op=fne, lhs=v18, rhs=v15 } -> x0 - terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) + v8 Imm(0) -> x7 + v9 Imm(1069547520) -> x6 [f32] + v10 Imm(1075838976) -> x0 [f32] + v11 Fneg(v10) -> [spill 0] [f32] + v12 Call { target_pc=0, args=[v8, v9, v11], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v13 Binop { op=fne, lhs=v12, rhs=v11 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v20 Imm(2) -> x0 - terminator Return(v20) (exit_acc=v20) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v21 Imm(4614500768194494464) -> x0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d2 [f32] - v23 Imm(0) -> x0 - v24 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v25 Imm(0) -> x0 - v26 FpCast { kind=F32ToF64, value=v22 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v15 Imm(1078984704) -> x0 [f32] + v16 StoreLocal { off=-1, value=v15, kind=F32 } -> - + v17 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v18 Imm(0) -> x0 [f32] + v19 Binop { op=fgt, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b18, fall=b5 } (exit_acc=v19) block 5 start_pc=0 - v28 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v29 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v22) + v20 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v21 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v20) block 6 start_pc=0 - v30 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v31 Fneg(v22) -> d0 [f32] - v32 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v31) + v25 Phi { incoming=[b5:v20, b18:v23], kind=F32 } -> d0 [f32] + v26 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v27 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v28 Imm(0) -> x0 [f32] + v29 Binop { op=flt, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b17, fall=b7 } (exit_acc=v29) block 7 start_pc=0 - v33 Phi { incoming=[b5:v22, b6:v31], kind=F32 } -> d0 [f32] - v34 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v35 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v36 Imm(0) -> x0 - v37 FpCast { kind=F32ToF64, value=v22 } -> d1 - v38 Binop { op=flt, lhs=v37, rhs=v36 } -> x0 - terminator Bz { cond=v38, target=b9, fall=b8 } (exit_acc=v38) + v30 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v31 Fneg(v30) -> d1 [f32] + v32 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v31) block 8 start_pc=0 - v39 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v40 Fneg(v22) -> d2 [f32] - v41 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v40) + v35 Phi { incoming=[b7:v31, b17:v33], kind=F32 } -> d1 [f32] + v36 LoadLocal { off=-6, kind=F32 } -> d2 [f32] + v37 Binop { op=fadd, lhs=v25, rhs=v35 } -> d0 [f32] + v38 Imm(0) -> x0 + v39 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v40 Imm(1087373312) -> x0 [f32] + v41 Binop { op=fne, lhs=v37, rhs=v40 } -> x0 + terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) block 9 start_pc=0 - v42 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v43 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v22) + v42 Imm(3) -> x0 + terminator Return(v42) (exit_acc=v42) block 10 start_pc=0 - v44 Phi { incoming=[b8:v40, b9:v22], kind=F32 } -> d2 [f32] - v45 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v46 Binop { op=fadd, lhs=v33, rhs=v44 } -> d0 [f32] - v47 Imm(0) -> x0 - v48 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v49 Imm(4619004367821864960) -> x0 - v50 FpCast { kind=F32ToF64, value=v46 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) + v43 Imm(2) -> x0 + v44 Imm(0) -> x0 + v45 LoadLocal { off=-3, kind=I32 } -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v46) block 11 start_pc=0 - v52 Imm(3) -> x0 - terminator Return(v52) (exit_acc=v52) + v49 LoadLocal { off=-3, kind=I32 } -> x0 + v50 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v50) block 12 start_pc=0 - v53 Imm(2) -> x0 - v54 Imm(0) -> x1 - v55 LoadLocal { off=-3, kind=I32 } -> x1 - v56 BinopI { op=eq, lhs=v53, rhs_imm=0 } -> x1 - terminator Bz { cond=v56, target=b14, fall=b13 } (exit_acc=v56) + v58 Imm(1101004800) -> x0 [f32] + v59 StoreLocal { off=-8, value=v58, kind=F32 } -> - + terminator Jmp(b13) (exit_acc=v59) block 13 start_pc=0 - v57 Imm(0) -> x0 - v58 StoreLocal { off=-7, value=v57, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v58) + v60 LoadLocal { off=-8, kind=F32 } -> d0 [f32] + v61 StoreLocal { off=-7, value=v60, kind=F32 } -> - + terminator Jmp(b14) (exit_acc=v61) block 14 start_pc=0 - v59 LoadLocal { off=-3, kind=I32 } -> x1 - v60 BinopI { op=eq, lhs=v53, rhs_imm=1 } -> x0 - terminator Bz { cond=v60, target=b17, fall=b16 } (exit_acc=v60) + v51 LoadLocal { off=-7, kind=F32 } -> d0 [f32] + v52 Imm(0) -> x0 + v53 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v54 Imm(1101004800) -> x0 [f32] + v55 Binop { op=fne, lhs=v51, rhs=v54 } -> x0 + terminator Bz { cond=v55, target=b16, fall=b15 } (exit_acc=v55) block 15 start_pc=0 - v61 LoadLocal { off=-7, kind=F64 } -> d0 - v62 FpCast { kind=F64ToF32, value=v61 } -> d0 [f32] - v63 Imm(0) -> x0 - v64 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v65 Imm(4626322717216342016) -> x0 - v66 FpCast { kind=F32ToF64, value=v62 } -> d0 - v67 Binop { op=fne, lhs=v66, rhs=v65 } -> x0 - terminator Bz { cond=v67, target=b20, fall=b19 } (exit_acc=v67) + v62 Imm(4) -> x0 + terminator Return(v62) (exit_acc=v62) block 16 start_pc=0 - v68 Imm(4621819117588971520) -> x0 - v69 StoreLocal { off=-8, value=v68, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v69) + v63 Imm(0) -> x0 + terminator Return(v63) (exit_acc=v63) block 17 start_pc=0 - v70 Imm(4626322717216342016) -> x0 - v71 StoreLocal { off=-8, value=v70, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v71) + v33 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v34 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v33) block 18 start_pc=0 - v72 LoadLocal { off=-8, kind=F64 } -> d0 - v73 StoreLocal { off=-7, value=v72, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v73) + v22 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v23 Fneg(v22) -> d0 [f32] + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 19 start_pc=0 - v74 Imm(4) -> x0 - terminator Return(v74) (exit_acc=v74) + v47 Imm(0) -> x0 [f32] + v48 StoreLocal { off=-7, value=v47, kind=F32 } -> - + terminator Jmp(b14) (exit_acc=v48) block 20 start_pc=0 - v75 Imm(0) -> x0 - terminator Return(v75) (exit_acc=v75) + v56 Imm(1092616192) -> x0 [f32] + v57 StoreLocal { off=-8, value=v56, kind=F32 } -> - + terminator Jmp(b13) (exit_acc=v57) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_variadic_promotion.ssa b/tests/snapshots/ssa/float_variadic_promotion.ssa index 38b4ff1ea..6dac050cf 100644 --- a/tests/snapshots/ssa/float_variadic_promotion.ssa +++ b/tests/snapshots/ssa/float_variadic_promotion.ssa @@ -43,29 +43,29 @@ fn ent_pc=1 n_params=1 variadic=true locals=5 v5 FpCast { kind=IntToFp, value=v4 } -> d0 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 LoadLocal { off=2, kind=I32 } -> x2 - v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) - block 2 start_pc=0 - v13 Extend { value=v8, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 v16 LoadLocal { off=-4, kind=F64 } -> d1 - v17 LocalAddr(-3) -> x0 - v18 Imm(65544) -> x2 - v19 Intrinsic { kind=5, args=[v17, v18] } -> x0 + v17 LocalAddr(-3) -> x2 + v18 Imm(65544) -> x6 + v19 Intrinsic { kind=5, args=[v17, v18] } -> x2 v20 Load { addr=v19, disp=0, kind=F64 } -> d1 v21 Binop { op=fadd, lhs=v9, rhs=v20 } -> d0 - v22 Imm(0) -> x0 + v22 Imm(0) -> x2 v23 LoadLocal { off=-4, kind=F64 } -> d1 terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x2 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x2 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v24 LocalAddr(-3) -> x0 v25 Intrinsic { kind=6, args=[v24] } -> x0 @@ -74,70 +74,69 @@ fn ent_pc=1 n_params=1 variadic=true locals=5 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=7 - spill_count=2 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4634564304534430024) -> x3 - v2 FpCast { kind=F64ToF32, value=v1 } -> [spill 0] [f32] - v3 Imm(0) -> x0 - v4 Imm(4609434218613702656) -> x0 - v5 FpCast { kind=F64ToF32, value=v4 } -> [spill 1] [f32] - v6 Imm(0) -> x0 - v7 Imm(1) -> x7 - v8 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v9 FpCast { kind=F32ToF64, value=v2 } -> d0 - v10 Call { target_pc=1, args=[v7, v9], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 - v11 Call { target_pc=0, args=[v10, v1], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v12 BinopI { op=eq, lhs=v11, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v1 Imm(1116355953) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(1069547520) -> x0 [f32] + v4 StoreLocal { off=-2, value=v3, kind=F32 } -> - + v5 Imm(1) -> x7 + v6 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v7 FpCast { kind=F32ToF64, value=v6 } -> d0 + v8 Call { target_pc=1, args=[v5, v7], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v9 Imm(4634564304534430024) -> x7 + v10 Call { target_pc=0, args=[v8, v9], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v11 BinopI { op=eq, lhs=v10, rhs_imm=0 } -> x0 + terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v12 Imm(1) -> x0 + terminator Return(v12) (exit_acc=v12) block 2 start_pc=0 - v14 Imm(1) -> x7 - v15 Imm(4612811918334230528) -> x3 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 FpCast { kind=F32ToF64, value=v16 } -> d0 - v18 Call { target_pc=1, args=[v14, v17], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 - v19 Call { target_pc=0, args=[v18, v15], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v20 BinopI { op=eq, lhs=v19, rhs_imm=0 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v13 Imm(1) -> x7 + v14 Imm(4612811918334230528) -> x3 + v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] + v16 FpCast { kind=F32ToF64, value=v15 } -> d0 + v17 Call { target_pc=1, args=[v13, v16], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v18 Call { target_pc=0, args=[v17, v14], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v21 Imm(2) -> x0 - terminator Return(v21) (exit_acc=v21) + v20 Imm(2) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v22 Imm(2) -> x7 - v23 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v2 } -> d0 - v25 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v26 FpCast { kind=F32ToF64, value=v5 } -> d1 - v27 Call { target_pc=1, args=[v22, v24, v26], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 - v28 Imm(4634669857650696520) -> x7 - v29 Call { target_pc=0, args=[v27, v28], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v30 BinopI { op=eq, lhs=v29, rhs_imm=0 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + v21 Imm(2) -> x7 + v22 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v23 FpCast { kind=F32ToF64, value=v22 } -> d0 + v24 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v25 FpCast { kind=F32ToF64, value=v24 } -> d1 + v26 Call { target_pc=1, args=[v21, v23, v25], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 + v27 Imm(4634669857650696520) -> x7 + v28 Call { target_pc=0, args=[v26, v27], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v29 BinopI { op=eq, lhs=v28, rhs_imm=0 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v31 Imm(3) -> x0 - terminator Return(v31) (exit_acc=v31) + v30 Imm(3) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v32 Imm(3) -> x7 - v33 Imm(10) -> x0 - v34 FpCast { kind=IntToFp, value=v33 } -> d0 - v35 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v36 FpCast { kind=F32ToF64, value=v2 } -> d1 - v37 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v38 FpCast { kind=F32ToF64, value=v5 } -> d2 - v39 Call { target_pc=1, args=[v32, v34, v36, v38], fixed_args=1, fp_return=true, fp_arg_mask=0xe } -> d0 - v40 Imm(4635373545092473160) -> x7 - v41 Call { target_pc=0, args=[v39, v40], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v42 BinopI { op=eq, lhs=v41, rhs_imm=0 } -> x0 - terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) + v31 Imm(3) -> x7 + v32 Imm(10) -> x0 + v33 FpCast { kind=IntToFp, value=v32 } -> d0 + v34 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v35 FpCast { kind=F32ToF64, value=v34 } -> d1 + v36 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v37 FpCast { kind=F32ToF64, value=v36 } -> d2 + v38 Call { target_pc=1, args=[v31, v33, v35, v37], fixed_args=1, fp_return=true, fp_arg_mask=0xe } -> d0 + v39 Imm(4635373545092473160) -> x7 + v40 Call { target_pc=0, args=[v38, v39], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v41 BinopI { op=eq, lhs=v40, rhs_imm=0 } -> x0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) block 7 start_pc=0 - v43 Imm(4) -> x0 - terminator Return(v43) (exit_acc=v43) + v42 Imm(4) -> x0 + terminator Return(v42) (exit_acc=v42) block 8 start_pc=0 - v44 Imm(0) -> x0 - terminator Return(v44) (exit_acc=v44) + v43 Imm(0) -> x0 + terminator Return(v43) (exit_acc=v43) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fma_contraction.ssa b/tests/snapshots/ssa/fma_contraction.ssa index fd47422c1..57b4996d5 100644 --- a/tests/snapshots/ssa/fma_contraction.ssa +++ b/tests/snapshots/ssa/fma_contraction.ssa @@ -156,146 +156,126 @@ fn ent_pc=6 n_params=0 variadic=false locals=3 v32 Imm(3) -> x0 terminator Return(v32) (exit_acc=v32) block 6 start_pc=0 - v33 Imm(4611686018427387904) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d0 [f32] - v35 Imm(4613937818241073152) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d1 [f32] - v37 Imm(4616189618054758400) -> x0 - v38 FpCast { kind=F64ToF32, value=v37 } -> d2 [f32] - v39 Imm(0) -> x0 - v40 Imm(0) -> x0 - v41 Imm(0) -> x0 - v42 Binop { op=fmul, lhs=v34, rhs=v36 } -> d3 [f32] - v43 Fma { a=v34, b=v36, c=v38, neg_product=false, neg_addend=false } -> d0 [f32] - v44 Imm(4621819117588971520) -> x0 - v45 FpCast { kind=F32ToF64, value=v43 } -> d0 - v46 Binop { op=fne, lhs=v45, rhs=v44 } -> x0 - terminator Bz { cond=v46, target=b8, fall=b7 } (exit_acc=v46) + v33 Imm(1073741824) -> x0 [f32] + v34 Imm(1077936128) -> x1 [f32] + v35 Imm(1082130432) -> x2 [f32] + v36 Imm(0) -> x6 + v37 Imm(0) -> x6 + v38 Imm(0) -> x6 + v39 Binop { op=fmul, lhs=v33, rhs=v34 } -> d0 [f32] + v40 Fma { a=v33, b=v34, c=v35, neg_product=false, neg_addend=false } -> d0 [f32] + v41 Imm(1092616192) -> x0 [f32] + v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 + terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) block 7 start_pc=0 - v47 Imm(4) -> x0 - terminator Return(v47) (exit_acc=v47) + v43 Imm(4) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v48 Imm(4611686018427387904) -> x0 - v49 FpCast { kind=F64ToF32, value=v48 } -> d0 [f32] - v50 Imm(4613937818241073152) -> x1 - v51 FpCast { kind=F64ToF32, value=v50 } -> d1 [f32] - v52 Imm(4616189618054758400) -> x1 - v53 FpCast { kind=F64ToF32, value=v52 } -> d2 [f32] - v54 Imm(0) -> x1 - v55 Imm(0) -> x1 - v56 Imm(0) -> x1 - v57 Binop { op=fmul, lhs=v49, rhs=v51 } -> d3 [f32] - v58 Fma { a=v49, b=v51, c=v53, neg_product=false, neg_addend=true } -> d0 [f32] - v59 FpCast { kind=F32ToF64, value=v58 } -> d0 - v60 Binop { op=fne, lhs=v59, rhs=v48 } -> x0 - terminator Bz { cond=v60, target=b10, fall=b9 } (exit_acc=v60) + v44 Imm(1073741824) -> x0 [f32] + v45 Imm(1077936128) -> x1 [f32] + v46 Imm(1082130432) -> x2 [f32] + v47 Imm(0) -> x6 + v48 Imm(0) -> x6 + v49 Imm(0) -> x6 + v50 Binop { op=fmul, lhs=v44, rhs=v45 } -> d0 [f32] + v51 Fma { a=v44, b=v45, c=v46, neg_product=false, neg_addend=true } -> d0 [f32] + v52 Binop { op=fne, lhs=v51, rhs=v44 } -> x0 + terminator Bz { cond=v52, target=b10, fall=b9 } (exit_acc=v52) block 9 start_pc=0 - v61 Imm(5) -> x0 - terminator Return(v61) (exit_acc=v61) + v53 Imm(5) -> x0 + terminator Return(v53) (exit_acc=v53) block 10 start_pc=0 - v62 Imm(4611686018427387904) -> x0 - v63 FpCast { kind=F64ToF32, value=v62 } -> d0 [f32] - v64 Imm(4613937818241073152) -> x1 - v65 FpCast { kind=F64ToF32, value=v64 } -> d1 [f32] - v66 Imm(4616189618054758400) -> x1 - v67 FpCast { kind=F64ToF32, value=v66 } -> d2 [f32] - v68 Imm(0) -> x1 - v69 Imm(0) -> x1 - v70 Imm(0) -> x1 - v71 Binop { op=fmul, lhs=v63, rhs=v65 } -> d3 [f32] - v72 Fma { a=v63, b=v65, c=v67, neg_product=true, neg_addend=false } -> d0 [f32] - v73 Fneg(v62) -> d1 - v74 FpCast { kind=F32ToF64, value=v72 } -> d0 - v75 Binop { op=fne, lhs=v74, rhs=v73 } -> x0 - terminator Bz { cond=v75, target=b12, fall=b11 } (exit_acc=v75) + v54 Imm(1073741824) -> x0 [f32] + v55 Imm(1077936128) -> x1 [f32] + v56 Imm(1082130432) -> x2 [f32] + v57 Imm(0) -> x6 + v58 Imm(0) -> x6 + v59 Imm(0) -> x6 + v60 Binop { op=fmul, lhs=v54, rhs=v55 } -> d0 [f32] + v61 Fma { a=v54, b=v55, c=v56, neg_product=true, neg_addend=false } -> d0 [f32] + v62 Fneg(v54) -> d1 [f32] + v63 Binop { op=fne, lhs=v61, rhs=v62 } -> x0 + terminator Bz { cond=v63, target=b12, fall=b11 } (exit_acc=v63) block 11 start_pc=0 - v76 Imm(6) -> x0 - terminator Return(v76) (exit_acc=v76) + v64 Imm(6) -> x0 + terminator Return(v64) (exit_acc=v64) block 12 start_pc=0 - v77 Imm(4602678819172646912) -> x0 - v78 Imm(4598175219545276416) -> x1 - v79 Imm(4593671619917905920) -> x2 - v80 Imm(0) -> x6 - v81 Imm(0) -> x6 - v82 Imm(0) -> x6 - v83 Binop { op=fmul, lhs=v77, rhs=v78 } -> d0 - v84 Fma { a=v77, b=v78, c=v79, neg_product=false, neg_addend=false } -> d0 - v85 Binop { op=fne, lhs=v84, rhs=v78 } -> x0 - terminator Bz { cond=v85, target=b14, fall=b13 } (exit_acc=v85) + v65 Imm(4602678819172646912) -> x0 + v66 Imm(4598175219545276416) -> x1 + v67 Imm(4593671619917905920) -> x2 + v68 Imm(0) -> x6 + v69 Imm(0) -> x6 + v70 Imm(0) -> x6 + v71 Binop { op=fmul, lhs=v65, rhs=v66 } -> d0 + v72 Fma { a=v65, b=v66, c=v67, neg_product=false, neg_addend=false } -> d0 + v73 Binop { op=fne, lhs=v72, rhs=v66 } -> x0 + terminator Bz { cond=v73, target=b14, fall=b13 } (exit_acc=v73) block 13 start_pc=0 - v86 Imm(7) -> x0 - terminator Return(v86) (exit_acc=v86) + v74 Imm(7) -> x0 + terminator Return(v74) (exit_acc=v74) block 14 start_pc=0 - v87 Imm(4602678819172646912) -> x0 - v88 FpCast { kind=F64ToF32, value=v87 } -> d0 [f32] - v89 Imm(4598175219545276416) -> x0 - v90 FpCast { kind=F64ToF32, value=v89 } -> d1 [f32] - v91 Imm(4593671619917905920) -> x1 - v92 FpCast { kind=F64ToF32, value=v91 } -> d2 [f32] - v93 Imm(0) -> x1 - v94 Imm(0) -> x1 - v95 Imm(0) -> x1 - v96 Binop { op=fmul, lhs=v88, rhs=v90 } -> d3 [f32] - v97 Fma { a=v88, b=v90, c=v92, neg_product=false, neg_addend=false } -> d0 [f32] - v98 FpCast { kind=F32ToF64, value=v97 } -> d0 - v99 Binop { op=fne, lhs=v98, rhs=v89 } -> x0 - terminator Bz { cond=v99, target=b16, fall=b15 } (exit_acc=v99) + v75 Imm(1056964608) -> x0 [f32] + v76 Imm(1048576000) -> x1 [f32] + v77 Imm(1040187392) -> x2 [f32] + v78 Imm(0) -> x6 + v79 Imm(0) -> x6 + v80 Imm(0) -> x6 + v81 Binop { op=fmul, lhs=v75, rhs=v76 } -> d0 [f32] + v82 Fma { a=v75, b=v76, c=v77, neg_product=false, neg_addend=false } -> d0 [f32] + v83 Binop { op=fne, lhs=v82, rhs=v76 } -> x0 + terminator Bz { cond=v83, target=b16, fall=b15 } (exit_acc=v83) block 15 start_pc=0 - v100 Imm(8) -> x0 - terminator Return(v100) (exit_acc=v100) + v84 Imm(8) -> x0 + terminator Return(v84) (exit_acc=v84) block 16 start_pc=0 - v101 Imm(4611686018427387904) -> x0 - v102 Imm(4613937818241073152) -> x1 - v103 Imm(4616189618054758400) -> x2 - v104 Fma { a=v101, b=v102, c=v103, neg_product=false, neg_addend=false } -> d0 - v105 Imm(4621819117588971520) -> x0 - v106 Binop { op=fne, lhs=v104, rhs=v105 } -> x0 - terminator Bz { cond=v106, target=b18, fall=b17 } (exit_acc=v106) + v85 Imm(4611686018427387904) -> x0 + v86 Imm(4613937818241073152) -> x1 + v87 Imm(4616189618054758400) -> x2 + v88 Fma { a=v85, b=v86, c=v87, neg_product=false, neg_addend=false } -> d0 + v89 Imm(4621819117588971520) -> x0 + v90 Binop { op=fne, lhs=v88, rhs=v89 } -> x0 + terminator Bz { cond=v90, target=b18, fall=b17 } (exit_acc=v90) block 17 start_pc=0 - v107 Imm(9) -> x0 - terminator Return(v107) (exit_acc=v107) + v91 Imm(9) -> x0 + terminator Return(v91) (exit_acc=v91) block 18 start_pc=0 - v108 Imm(4602678819172646912) -> x0 - v109 Imm(4598175219545276416) -> x1 - v110 Imm(4593671619917905920) -> x2 - v111 Fma { a=v108, b=v109, c=v110, neg_product=false, neg_addend=false } -> d0 - v112 Binop { op=fne, lhs=v111, rhs=v109 } -> x0 - terminator Bz { cond=v112, target=b20, fall=b19 } (exit_acc=v112) + v92 Imm(4602678819172646912) -> x0 + v93 Imm(4598175219545276416) -> x1 + v94 Imm(4593671619917905920) -> x2 + v95 Fma { a=v92, b=v93, c=v94, neg_product=false, neg_addend=false } -> d0 + v96 Binop { op=fne, lhs=v95, rhs=v93 } -> x0 + terminator Bz { cond=v96, target=b20, fall=b19 } (exit_acc=v96) block 19 start_pc=0 - v113 Imm(10) -> x0 - terminator Return(v113) (exit_acc=v113) + v97 Imm(10) -> x0 + terminator Return(v97) (exit_acc=v97) block 20 start_pc=0 - v114 Imm(4611686018427387904) -> x0 - v115 FpCast { kind=F64ToF32, value=v114 } -> d0 [f32] - v116 Imm(4613937818241073152) -> x0 - v117 FpCast { kind=F64ToF32, value=v116 } -> d1 [f32] - v118 Imm(4616189618054758400) -> x0 - v119 FpCast { kind=F64ToF32, value=v118 } -> d2 [f32] - v120 Fma { a=v115, b=v117, c=v119, neg_product=false, neg_addend=false } -> d0 [f32] - v121 Imm(4621819117588971520) -> x0 - v122 FpCast { kind=F32ToF64, value=v120 } -> d0 - v123 Binop { op=fne, lhs=v122, rhs=v121 } -> x0 - terminator Bz { cond=v123, target=b22, fall=b21 } (exit_acc=v123) + v98 Imm(1073741824) -> x0 [f32] + v99 Imm(1077936128) -> x1 [f32] + v100 Imm(1082130432) -> x2 [f32] + v101 Fma { a=v98, b=v99, c=v100, neg_product=false, neg_addend=false } -> d0 [f32] + v102 Imm(1092616192) -> x0 [f32] + v103 Binop { op=fne, lhs=v101, rhs=v102 } -> x0 + terminator Bz { cond=v103, target=b22, fall=b21 } (exit_acc=v103) block 21 start_pc=0 - v124 Imm(11) -> x0 - terminator Return(v124) (exit_acc=v124) + v104 Imm(11) -> x0 + terminator Return(v104) (exit_acc=v104) block 22 start_pc=0 - v125 Imm(2) -> x0 - v126 FpCast { kind=IntToFp, value=v125 } -> d0 - v127 Imm(3) -> x0 - v128 FpCast { kind=IntToFp, value=v127 } -> d1 - v129 Imm(4) -> x0 - v130 FpCast { kind=IntToFp, value=v129 } -> d2 - v131 Fma { a=v126, b=v128, c=v130, neg_product=false, neg_addend=false } -> d0 - v132 Imm(4621819117588971520) -> x0 - v133 Binop { op=fne, lhs=v131, rhs=v132 } -> x0 - terminator Bz { cond=v133, target=b24, fall=b23 } (exit_acc=v133) + v105 Imm(2) -> x0 + v106 FpCast { kind=IntToFp, value=v105 } -> d0 + v107 Imm(3) -> x0 + v108 FpCast { kind=IntToFp, value=v107 } -> d1 + v109 Imm(4) -> x0 + v110 FpCast { kind=IntToFp, value=v109 } -> d2 + v111 Fma { a=v106, b=v108, c=v110, neg_product=false, neg_addend=false } -> d0 + v112 Imm(4621819117588971520) -> x0 + v113 Binop { op=fne, lhs=v111, rhs=v112 } -> x0 + terminator Bz { cond=v113, target=b24, fall=b23 } (exit_acc=v113) block 23 start_pc=0 - v134 Imm(12) -> x0 - terminator Return(v134) (exit_acc=v134) + v114 Imm(12) -> x0 + terminator Return(v114) (exit_acc=v114) block 24 start_pc=0 - v135 Imm(0) -> x0 - terminator Return(v135) (exit_acc=v135) + v115 Imm(0) -> x0 + terminator Return(v115) (exit_acc=v115) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fma_numeric_kernels.ssa b/tests/snapshots/ssa/fma_numeric_kernels.ssa index 7ae3d438f..20c4df370 100644 --- a/tests/snapshots/ssa/fma_numeric_kernels.ssa +++ b/tests/snapshots/ssa/fma_numeric_kernels.ssa @@ -54,37 +54,37 @@ fn ent_pc=1 n_params=3 variadic=false locals=2 v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 v18 Extend { value=v16, kind=I32 } -> x1 v19 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v18) + terminator Jmp(b3) (exit_acc=v18) block 1 start_pc=0 - v20 Phi { incoming=[b0:v18, b2:v25], kind=I64 } -> x1 - v21 Phi { incoming=[b0:v14, b2:v35], kind=F64 } -> d1 - v22 Extend { value=v20, kind=I32 } -> x0 - v23 BinopI { op=ge, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) - block 2 start_pc=0 - v24 Extend { value=v20, kind=I32 } -> x0 - v25 BinopI { op=add, lhs=v24, rhs_imm=-1 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v25) - block 3 start_pc=0 v27 LoadLocal { off=-1, kind=F64 } -> d2 v28 LoadLocal { off=4, kind=F64 } -> d2 v29 Binop { op=fmul, lhs=v21, rhs=v5 } -> d2 - v30 LoadLocal { off=2, kind=I64 } -> x0 - v31 Extend { value=v20, kind=I32 } -> x0 - v32 BinopI { op=shl, lhs=v31, rhs_imm=3 } -> x0 - v33 Binop { op=add, lhs=v1, rhs=v32 } -> x0 + v30 LoadLocal { off=2, kind=I64 } -> x2 + v31 Extend { value=v20, kind=I32 } -> x2 + v32 BinopI { op=shl, lhs=v22, rhs_imm=3 } -> x2 + v33 Binop { op=add, lhs=v1, rhs=v32 } -> x2 v34 Load { addr=v33, disp=0, kind=F64 } -> d2 v35 Fma { a=v21, b=v5, c=v34, neg_product=false, neg_addend=false } -> d1 - v36 Imm(0) -> x0 + v36 Imm(0) -> x2 terminator Jmp(b2) (exit_acc=v35) + block 2 start_pc=0 + v24 Extend { value=v20, kind=I32 } -> x1 + v25 BinopI { op=add, lhs=v22, rhs_imm=-1 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v20 Phi { incoming=[b0:v18, b2:v25], kind=I64 } -> x1 + v21 Phi { incoming=[b0:v14, b2:v35], kind=F64 } -> d1 + v22 Extend { value=v20, kind=I32 } -> x0 + v23 BinopI { op=ge, lhs=v22, rhs_imm=0 } -> x2 + terminator Bnz { cond=v23, target=b1, fall=b4 } (exit_acc=v23) block 4 start_pc=0 v37 LoadLocal { off=-1, kind=F64 } -> d0 terminator Return(v21) (exit_acc=v21) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=dot3 fn ent_pc=2 n_params=4 variadic=false locals=2 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -95,44 +95,89 @@ fn ent_pc=2 n_params=4 variadic=false locals=2 v6 Imm(0) -> x0 v7 ParamRef(3, kind=I32) -> x1 v8 Imm(0) -> x0 - v9 Imm(0) -> x8 + v9 Imm(0) -> x0 v10 StoreLocal { off=-1, value=v9, kind=F64 } -> - - v11 Imm(0) -> x0 + v11 Imm(0) -> x8 terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v12 Phi { incoming=[b0:v9, b2:v16], kind=I64 } -> x8 - v13 Extend { value=v12, kind=I32 } -> x0 - v14 BinopI { op=lt, lhs=v13, rhs_imm=3 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 LoadLocal { off=-1, kind=F64 } -> d0 + v15 LoadLocal { off=2, kind=I64 } -> x0 + v16 LoadLocal { off=4, kind=I32 } -> x0 + v17 BinopI { op=mul, lhs=v5, rhs_imm=24 } -> x0 + v18 Binop { op=add, lhs=v1, rhs=v17 } -> x0 + v19 Imm(0) -> x8 + v20 Imm(0) -> x8 + v21 BinopI { op=add, lhs=v18, rhs_imm=0 } -> x0 + v22 Load { addr=v21, disp=0, kind=F64 } -> d1 + v23 LoadLocal { off=3, kind=I64 } -> x0 + v24 Imm(0) -> x0 + v25 BinopI { op=add, lhs=v3, rhs_imm=0 } -> x0 + v26 LoadLocal { off=5, kind=I32 } -> x8 + v27 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x8 + v28 Binop { op=add, lhs=v25, rhs=v27 } -> x0 + v29 Load { addr=v28, disp=0, kind=F64 } -> d2 + v30 Binop { op=fmul, lhs=v22, rhs=v29 } -> d3 + v31 Fma { a=v22, b=v29, c=v14, neg_product=false, neg_addend=false } -> d0 + v32 StoreLocal { off=-1, value=v31, kind=F64 } -> - + v33 Imm(0) -> x0 + v34 Imm(1) -> x0 + v35 Imm(0) -> x0 + v36 Imm(1) -> x0 + v37 Imm(1) -> x0 + v38 LoadLocal { off=-1, kind=F64 } -> d0 + v39 LoadLocal { off=2, kind=I64 } -> x0 + v40 LoadLocal { off=4, kind=I32 } -> x0 + v41 BinopI { op=mul, lhs=v5, rhs_imm=24 } -> x0 + v42 Binop { op=add, lhs=v1, rhs=v41 } -> x0 + v43 Imm(1) -> x8 + v44 Imm(8) -> x8 + v45 BinopI { op=add, lhs=v42, rhs_imm=8 } -> x8 + v46 Load { addr=v42, disp=8, kind=F64 } -> d1 + v47 LoadLocal { off=3, kind=I64 } -> x0 + v48 Imm(24) -> x0 + v49 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x0 + v50 LoadLocal { off=5, kind=I32 } -> x8 + v51 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x8 + v52 Binop { op=add, lhs=v49, rhs=v51 } -> x0 + v53 Load { addr=v52, disp=0, kind=F64 } -> d2 + v54 Binop { op=fmul, lhs=v46, rhs=v53 } -> d3 + v55 Fma { a=v46, b=v53, c=v38, neg_product=false, neg_addend=false } -> d0 + v56 StoreLocal { off=-1, value=v55, kind=F64 } -> - + v57 Imm(1) -> x0 + v58 Imm(2) -> x0 + v59 Imm(0) -> x0 + v60 Imm(2) -> x0 + v61 Imm(1) -> x0 + v62 LoadLocal { off=-1, kind=F64 } -> d0 + v63 LoadLocal { off=2, kind=I64 } -> x0 + v64 LoadLocal { off=4, kind=I32 } -> x0 + v65 BinopI { op=mul, lhs=v5, rhs_imm=24 } -> x0 + v66 Binop { op=add, lhs=v1, rhs=v65 } -> x0 + v67 Imm(2) -> x2 + v68 Imm(16) -> x2 + v69 BinopI { op=add, lhs=v66, rhs_imm=16 } -> x2 + v70 Load { addr=v66, disp=16, kind=F64 } -> d1 + v71 LoadLocal { off=3, kind=I64 } -> x0 + v72 Imm(48) -> x0 + v73 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x0 + v74 LoadLocal { off=5, kind=I32 } -> x2 + v75 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x1 + v76 Binop { op=add, lhs=v73, rhs=v75 } -> x0 + v77 Load { addr=v76, disp=0, kind=F64 } -> d2 + v78 Binop { op=fmul, lhs=v70, rhs=v77 } -> d3 + v79 Fma { a=v70, b=v77, c=v62, neg_product=false, neg_addend=false } -> d0 + v80 StoreLocal { off=-1, value=v79, kind=F64 } -> - + v81 Imm(2) -> x0 + v82 Imm(3) -> x0 + v83 Imm(0) -> x0 + v84 Imm(3) -> x0 + v85 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v85) block 2 start_pc=0 - v15 Extend { value=v12, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x8 - v17 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v16) - block 3 start_pc=0 - v18 LoadLocal { off=-1, kind=F64 } -> d0 - v19 LoadLocal { off=2, kind=I64 } -> x0 - v20 LoadLocal { off=4, kind=I32 } -> x0 - v21 BinopI { op=mul, lhs=v5, rhs_imm=24 } -> x0 - v22 Binop { op=add, lhs=v1, rhs=v21 } -> x0 - v23 Extend { value=v12, kind=I32 } -> x9 - v24 BinopI { op=shl, lhs=v23, rhs_imm=3 } -> x3 - v25 Binop { op=add, lhs=v22, rhs=v24 } -> x0 - v26 Load { addr=v25, disp=0, kind=F64 } -> d1 - v27 LoadLocal { off=3, kind=I64 } -> x0 - v28 BinopI { op=mul, lhs=v23, rhs_imm=24 } -> x0 - v29 Binop { op=add, lhs=v3, rhs=v28 } -> x0 - v30 LoadLocal { off=5, kind=I32 } -> x9 - v31 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x9 - v32 Binop { op=add, lhs=v29, rhs=v31 } -> x0 - v33 Load { addr=v32, disp=0, kind=F64 } -> d2 - v34 Binop { op=fmul, lhs=v26, rhs=v33 } -> d3 - v35 Fma { a=v26, b=v33, c=v18, neg_product=false, neg_addend=false } -> d0 - v36 StoreLocal { off=-1, value=v35, kind=F64 } -> - - terminator Jmp(b2) (exit_acc=v36) - block 4 start_pc=0 - v37 LoadLocal { off=-1, kind=F64 } -> d0 - terminator Return(v37) (exit_acc=v37) + v86 LoadLocal { off=-1, kind=F64 } -> d0 + terminator Return(v86) (exit_acc=v86) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=rk4_step fn ent_pc=3 n_params=2 variadic=false locals=4 @@ -227,117 +272,85 @@ fn ent_pc=4 n_params=0 variadic=false locals=31 block 4 start_pc=0 v40 Imm(0) -> x1 v41 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v40) + terminator Jmp(b13) (exit_acc=v40) block 5 start_pc=0 - v42 Phi { incoming=[b4:v40, b6:v46], kind=I64 } -> x1 - v43 Extend { value=v42, kind=I32 } -> x0 - v44 BinopI { op=lt, lhs=v43, rhs_imm=3 } -> x0 - terminator Bz { cond=v44, target=b8, fall=b7 } (exit_acc=v44) + v48 Imm(0) -> x6 + v49 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v48) block 6 start_pc=0 - v45 Extend { value=v42, kind=I32 } -> x0 - v46 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x1 - v47 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v46) + v58 LocalAddr(-14) -> x7 + v59 Extend { value=v42, kind=I32 } -> x8 + v60 BinopI { op=mul, lhs=v43, rhs_imm=24 } -> x8 + v61 Binop { op=add, lhs=v58, rhs=v60 } -> x7 + v62 Extend { value=v52, kind=I32 } -> x8 + v63 BinopI { op=shl, lhs=v53, rhs_imm=3 } -> x8 + v64 Binop { op=add, lhs=v61, rhs=v63 } -> x7 + v65 BinopI { op=mul, lhs=v43, rhs_imm=3 } -> x8 + v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x9 + v67 Extend { value=v65, kind=I32 } -> x9 + v68 Binop { op=add, lhs=v65, rhs=v53 } -> x8 + v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x9 + v70 Extend { value=v68, kind=I32 } -> x9 + v71 BinopI { op=add, lhs=v68, rhs_imm=1 } -> x8 + v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x9 + v73 Extend { value=v71, kind=I32 } -> x8 + v74 FpCast { kind=IntToFp, value=v73 } -> d0 + v75 Store { addr=v64, disp=0, value=v74, kind=F64 } -> - + v76 LocalAddr(-23) -> x7 + v77 Extend { value=v42, kind=I32 } -> x8 + v78 BinopI { op=mul, lhs=v43, rhs_imm=24 } -> x8 + v79 Binop { op=add, lhs=v76, rhs=v78 } -> x7 + v80 Extend { value=v52, kind=I32 } -> x8 + v81 BinopI { op=shl, lhs=v53, rhs_imm=3 } -> x8 + v82 Binop { op=add, lhs=v79, rhs=v81 } -> x7 + v83 Binop { op=eq, lhs=v43, rhs=v53 } -> x8 + terminator Bz { cond=v83, target=b9, fall=b7 } (exit_acc=v83) block 7 start_pc=0 - v48 Imm(0) -> x2 - v49 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v48) + v84 Imm(4607182418800017408) -> x8 + v85 StoreLocal { off=-31, value=v84, kind=F64 } -> - + terminator Jmp(b8) (exit_acc=v85) block 8 start_pc=0 - v50 Imm(0) -> x3 - v51 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v50) + v88 LoadLocal { off=-31, kind=F64 } -> d0 + v89 Store { addr=v82, disp=0, value=v88, kind=F64 } -> - + terminator Jmp(b10) (exit_acc=v89) block 9 start_pc=0 - v52 Phi { incoming=[b7:v48, b10:v56], kind=I64 } -> x2 - v53 Extend { value=v52, kind=I32 } -> x0 - v54 BinopI { op=lt, lhs=v53, rhs_imm=3 } -> x0 - terminator Bz { cond=v54, target=b12, fall=b11 } (exit_acc=v54) + v86 Imm(0) -> x8 + v87 StoreLocal { off=-31, value=v86, kind=F64 } -> - + terminator Jmp(b8) (exit_acc=v87) block 10 start_pc=0 - v55 Extend { value=v52, kind=I32 } -> x0 - v56 BinopI { op=add, lhs=v55, rhs_imm=1 } -> x2 - v57 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v56) + v55 Extend { value=v52, kind=I32 } -> x6 + v56 BinopI { op=add, lhs=v53, rhs_imm=1 } -> x6 + v57 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v56) block 11 start_pc=0 - v58 LocalAddr(-14) -> x0 - v59 Extend { value=v42, kind=I32 } -> x6 - v60 BinopI { op=mul, lhs=v59, rhs_imm=24 } -> x7 - v61 Binop { op=add, lhs=v58, rhs=v60 } -> x0 - v62 Extend { value=v52, kind=I32 } -> x7 - v63 BinopI { op=shl, lhs=v62, rhs_imm=3 } -> x8 - v64 Binop { op=add, lhs=v61, rhs=v63 } -> x0 - v65 BinopI { op=mul, lhs=v59, rhs_imm=3 } -> x6 - v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x8 - v67 Extend { value=v65, kind=I32 } -> x8 - v68 Binop { op=add, lhs=v65, rhs=v62 } -> x6 - v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x7 - v70 Extend { value=v68, kind=I32 } -> x7 - v71 BinopI { op=add, lhs=v68, rhs_imm=1 } -> x6 - v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x7 - v73 Extend { value=v71, kind=I32 } -> x6 - v74 FpCast { kind=IntToFp, value=v73 } -> d0 - v75 Store { addr=v64, disp=0, value=v74, kind=F64 } -> - - v76 LocalAddr(-23) -> x0 - v77 Extend { value=v42, kind=I32 } -> x6 - v78 BinopI { op=mul, lhs=v77, rhs_imm=24 } -> x7 - v79 Binop { op=add, lhs=v76, rhs=v78 } -> x0 - v80 Extend { value=v52, kind=I32 } -> x7 - v81 BinopI { op=shl, lhs=v80, rhs_imm=3 } -> x8 - v82 Binop { op=add, lhs=v79, rhs=v81 } -> x0 - v83 Binop { op=eq, lhs=v77, rhs=v80 } -> x6 - terminator Bz { cond=v83, target=b14, fall=b13 } (exit_acc=v83) + v52 Phi { incoming=[b5:v48, b10:v56], kind=I64 } -> x6 + v53 Extend { value=v52, kind=I32 } -> x2 + v54 BinopI { op=lt, lhs=v53, rhs_imm=3 } -> x7 + terminator Bnz { cond=v54, target=b6, fall=b12 } (exit_acc=v54) block 12 start_pc=0 - terminator Jmp(b6) + v45 Extend { value=v42, kind=I32 } -> x1 + v46 BinopI { op=add, lhs=v43, rhs_imm=1 } -> x1 + v47 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v46) block 13 start_pc=0 - v84 Imm(4607182418800017408) -> x6 - v85 StoreLocal { off=-31, value=v84, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v85) + v42 Phi { incoming=[b4:v40, b12:v46], kind=I64 } -> x1 + v43 Extend { value=v42, kind=I32 } -> x0 + v44 BinopI { op=lt, lhs=v43, rhs_imm=3 } -> x2 + terminator Bnz { cond=v44, target=b5, fall=b14 } (exit_acc=v44) block 14 start_pc=0 - v86 Imm(0) -> x6 - v87 StoreLocal { off=-31, value=v86, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v87) + v50 Imm(0) -> x3 + v51 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v50) block 15 start_pc=0 - v88 LoadLocal { off=-31, kind=F64 } -> d0 - v89 Store { addr=v82, disp=0, value=v88, kind=F64 } -> - - terminator Jmp(b10) (exit_acc=v89) - block 16 start_pc=0 - v90 Phi { incoming=[b8:v50, b17:v94], kind=I64 } -> x3 - v91 Extend { value=v90, kind=I32 } -> x0 - v92 BinopI { op=lt, lhs=v91, rhs_imm=3 } -> x0 - terminator Bz { cond=v92, target=b19, fall=b18 } (exit_acc=v92) - block 17 start_pc=0 - v93 Extend { value=v90, kind=I32 } -> x0 - v94 BinopI { op=add, lhs=v93, rhs_imm=1 } -> x3 - v95 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v94) - block 18 start_pc=0 v96 Imm(0) -> x12 v97 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v96) - block 19 start_pc=0 - v98 LocalAddr(-14) -> x7 - v99 LocalAddr(-14) -> x6 - v100 Imm(1) -> x2 - v101 Imm(2) -> x1 - v102 Call { target_pc=2, args=[v98, v99, v100, v101], fixed_args=4, fp_return=true, fp_arg_mask=0x0 } -> d0 - v103 Imm(4636455816377925632) -> x7 - v104 Call { target_pc=0, args=[v102, v103], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v105 BinopI { op=eq, lhs=v104, rhs_imm=0 } -> x0 - terminator Bz { cond=v105, target=b27, fall=b26 } (exit_acc=v105) - block 20 start_pc=0 - v106 Phi { incoming=[b18:v96, b21:v110], kind=I64 } -> x12 - v107 Extend { value=v106, kind=I32 } -> x0 - v108 BinopI { op=lt, lhs=v107, rhs_imm=3 } -> x0 - terminator Bz { cond=v108, target=b23, fall=b22 } (exit_acc=v108) - block 21 start_pc=0 - v109 Extend { value=v106, kind=I32 } -> x0 - v110 BinopI { op=add, lhs=v109, rhs_imm=1 } -> x12 - v111 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v110) - block 22 start_pc=0 + terminator Jmp(b18) (exit_acc=v96) + block 16 start_pc=0 v112 LocalAddr(-14) -> x7 v113 LocalAddr(-23) -> x6 - v114 Extend { value=v90, kind=I32 } -> x2 - v115 Extend { value=v106, kind=I32 } -> x1 - v116 Call { target_pc=2, args=[v112, v113, v114, v115], fixed_args=4, fp_return=true, fp_arg_mask=0x0 } -> d0 + v114 Extend { value=v90, kind=I32 } -> x0 + v115 Extend { value=v106, kind=I32 } -> x0 + v116 Call { target_pc=2, args=[v112, v113, v90, v106], fixed_args=4, fp_return=true, fp_arg_mask=0x0 } -> d0 v117 LocalAddr(-14) -> x0 v118 Extend { value=v90, kind=I32 } -> x1 v119 BinopI { op=mul, lhs=v118, rhs_imm=24 } -> x1 @@ -348,95 +361,604 @@ fn ent_pc=4 n_params=0 variadic=false locals=31 v124 Load { addr=v123, disp=0, kind=F64 } -> d1 v125 Call { target_pc=0, args=[v116, v124], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v126 BinopI { op=eq, lhs=v125, rhs_imm=0 } -> x0 - terminator Bz { cond=v126, target=b25, fall=b24 } (exit_acc=v126) - block 23 start_pc=0 - terminator Jmp(b17) - block 24 start_pc=0 - v127 Imm(3) -> x0 - terminator Return(v127) (exit_acc=v127) - block 25 start_pc=0 - terminator Jmp(b21) - block 26 start_pc=0 + terminator Bnz { cond=v126, target=b31, fall=b17 } (exit_acc=v126) + block 17 start_pc=0 + v109 Extend { value=v106, kind=I32 } -> x0 + v110 BinopI { op=add, lhs=v109, rhs_imm=1 } -> x12 + v111 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v110) + block 18 start_pc=0 + v106 Phi { incoming=[b15:v96, b17:v110], kind=I64 } -> x12 + v107 Extend { value=v106, kind=I32 } -> x0 + v108 BinopI { op=lt, lhs=v107, rhs_imm=3 } -> x0 + terminator Bnz { cond=v108, target=b16, fall=b19 } (exit_acc=v108) + block 19 start_pc=0 + v93 Extend { value=v90, kind=I32 } -> x0 + v94 BinopI { op=add, lhs=v93, rhs_imm=1 } -> x3 + v95 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v94) + block 20 start_pc=0 + v90 Phi { incoming=[b14:v50, b19:v94], kind=I64 } -> x3 + v91 Extend { value=v90, kind=I32 } -> x0 + v92 BinopI { op=lt, lhs=v91, rhs_imm=3 } -> x0 + terminator Bnz { cond=v92, target=b15, fall=b21 } (exit_acc=v92) + block 21 start_pc=0 + v98 LocalAddr(-14) -> x7 + v99 LocalAddr(-14) -> x6 + v100 Imm(1) -> x2 + v101 Imm(2) -> x1 + v102 Call { target_pc=2, args=[v98, v99, v100, v101], fixed_args=4, fp_return=true, fp_arg_mask=0x0 } -> d0 + v103 Imm(4636455816377925632) -> x7 + v104 Call { target_pc=0, args=[v102, v103], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v105 BinopI { op=eq, lhs=v104, rhs_imm=0 } -> x0 + terminator Bz { cond=v105, target=b23, fall=b22 } (exit_acc=v105) + block 22 start_pc=0 v128 Imm(4) -> x0 terminator Return(v128) (exit_acc=v128) - block 27 start_pc=0 + block 23 start_pc=0 v129 Imm(4607182418800017408) -> x0 v130 StoreLocal { off=-26, value=v129, kind=F64 } -> - v131 Imm(4625196817309499392) -> x1 v132 Binop { op=fdiv, lhs=v129, rhs=v131 } -> d0 v133 Imm(0) -> x0 - v134 Imm(0) -> x1 - v135 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v134) + v134 Imm(0) -> x0 + v135 Imm(0) -> x1 + terminator Jmp(b24) (exit_acc=v134) + block 24 start_pc=0 + v136 Imm(0) -> x0 + v137 Imm(1) -> x0 + v138 LoadLocal { off=-26, kind=F64 } -> d1 + v139 LoadLocal { off=-27, kind=F64 } -> d2 + v140 Imm(0) -> x0 + v141 Imm(0) -> x0 + v142 Imm(0) -> x0 + v143 Imm(4602678819172646912) -> x0 + v144 Binop { op=fmul, lhs=v132, rhs=v143 } -> d2 + v145 Binop { op=fmul, lhs=v144, rhs=v138 } -> d3 + v146 Fma { a=v144, b=v138, c=v138, neg_product=false, neg_addend=false } -> d3 + v147 Imm(0) -> x0 + v148 Binop { op=fmul, lhs=v144, rhs=v146 } -> d4 + v149 Fma { a=v144, b=v146, c=v138, neg_product=false, neg_addend=false } -> d2 + v150 Imm(0) -> x0 + v151 Binop { op=fmul, lhs=v132, rhs=v149 } -> d4 + v152 Fma { a=v132, b=v149, c=v138, neg_product=false, neg_addend=false } -> d4 + v153 Imm(0) -> x0 + v154 Imm(4618441417868443648) -> x0 + v155 Binop { op=fdiv, lhs=v132, rhs=v154 } -> d5 + v156 Imm(4611686018427387904) -> x0 + v157 Binop { op=fmul, lhs=v156, rhs=v146 } -> d6 + v158 Fma { a=v156, b=v146, c=v138, neg_product=false, neg_addend=false } -> d3 + v159 Binop { op=fmul, lhs=v156, rhs=v149 } -> d6 + v160 Fma { a=v156, b=v149, c=v158, neg_product=false, neg_addend=false } -> d2 + v161 Binop { op=fadd, lhs=v160, rhs=v152 } -> d2 + v162 Binop { op=fmul, lhs=v155, rhs=v161 } -> d3 + v163 Fma { a=v155, b=v161, c=v138, neg_product=false, neg_addend=false } -> d1 + v164 StoreLocal { off=-26, value=v163, kind=F64 } -> - + v165 Imm(0) -> x0 + v166 Imm(1) -> x0 + v167 Imm(0) -> x0 + v168 Imm(1) -> x0 + v169 Imm(1) -> x0 + v170 LoadLocal { off=-26, kind=F64 } -> d1 + v171 LoadLocal { off=-27, kind=F64 } -> d2 + v172 Imm(0) -> x0 + v173 Imm(0) -> x0 + v174 Imm(0) -> x0 + v175 Imm(4602678819172646912) -> x0 + v176 Binop { op=fmul, lhs=v132, rhs=v175 } -> d2 + v177 Binop { op=fmul, lhs=v176, rhs=v170 } -> d3 + v178 Fma { a=v176, b=v170, c=v170, neg_product=false, neg_addend=false } -> d3 + v179 Imm(0) -> x0 + v180 Binop { op=fmul, lhs=v176, rhs=v178 } -> d4 + v181 Fma { a=v176, b=v178, c=v170, neg_product=false, neg_addend=false } -> d2 + v182 Imm(0) -> x0 + v183 Binop { op=fmul, lhs=v132, rhs=v181 } -> d4 + v184 Fma { a=v132, b=v181, c=v170, neg_product=false, neg_addend=false } -> d4 + v185 Imm(0) -> x0 + v186 Imm(4618441417868443648) -> x0 + v187 Binop { op=fdiv, lhs=v132, rhs=v186 } -> d5 + v188 Imm(4611686018427387904) -> x0 + v189 Binop { op=fmul, lhs=v188, rhs=v178 } -> d6 + v190 Fma { a=v188, b=v178, c=v170, neg_product=false, neg_addend=false } -> d3 + v191 Binop { op=fmul, lhs=v188, rhs=v181 } -> d6 + v192 Fma { a=v188, b=v181, c=v190, neg_product=false, neg_addend=false } -> d2 + v193 Binop { op=fadd, lhs=v192, rhs=v184 } -> d2 + v194 Binop { op=fmul, lhs=v187, rhs=v193 } -> d3 + v195 Fma { a=v187, b=v193, c=v170, neg_product=false, neg_addend=false } -> d1 + v196 StoreLocal { off=-26, value=v195, kind=F64 } -> - + v197 Imm(1) -> x0 + v198 Imm(2) -> x0 + v199 Imm(0) -> x0 + v200 Imm(2) -> x0 + v201 Imm(1) -> x0 + v202 LoadLocal { off=-26, kind=F64 } -> d1 + v203 LoadLocal { off=-27, kind=F64 } -> d2 + v204 Imm(0) -> x0 + v205 Imm(0) -> x0 + v206 Imm(0) -> x0 + v207 Imm(4602678819172646912) -> x0 + v208 Binop { op=fmul, lhs=v132, rhs=v207 } -> d2 + v209 Binop { op=fmul, lhs=v208, rhs=v202 } -> d3 + v210 Fma { a=v208, b=v202, c=v202, neg_product=false, neg_addend=false } -> d3 + v211 Imm(0) -> x0 + v212 Binop { op=fmul, lhs=v208, rhs=v210 } -> d4 + v213 Fma { a=v208, b=v210, c=v202, neg_product=false, neg_addend=false } -> d2 + v214 Imm(0) -> x0 + v215 Binop { op=fmul, lhs=v132, rhs=v213 } -> d4 + v216 Fma { a=v132, b=v213, c=v202, neg_product=false, neg_addend=false } -> d4 + v217 Imm(0) -> x0 + v218 Imm(4618441417868443648) -> x0 + v219 Binop { op=fdiv, lhs=v132, rhs=v218 } -> d5 + v220 Imm(4611686018427387904) -> x0 + v221 Binop { op=fmul, lhs=v220, rhs=v210 } -> d6 + v222 Fma { a=v220, b=v210, c=v202, neg_product=false, neg_addend=false } -> d3 + v223 Binop { op=fmul, lhs=v220, rhs=v213 } -> d6 + v224 Fma { a=v220, b=v213, c=v222, neg_product=false, neg_addend=false } -> d2 + v225 Binop { op=fadd, lhs=v224, rhs=v216 } -> d2 + v226 Binop { op=fmul, lhs=v219, rhs=v225 } -> d3 + v227 Fma { a=v219, b=v225, c=v202, neg_product=false, neg_addend=false } -> d1 + v228 StoreLocal { off=-26, value=v227, kind=F64 } -> - + v229 Imm(2) -> x0 + v230 Imm(3) -> x0 + v231 Imm(0) -> x0 + v232 Imm(3) -> x0 + v233 Imm(1) -> x0 + v234 LoadLocal { off=-26, kind=F64 } -> d1 + v235 LoadLocal { off=-27, kind=F64 } -> d2 + v236 Imm(0) -> x0 + v237 Imm(0) -> x0 + v238 Imm(0) -> x0 + v239 Imm(4602678819172646912) -> x0 + v240 Binop { op=fmul, lhs=v132, rhs=v239 } -> d2 + v241 Binop { op=fmul, lhs=v240, rhs=v234 } -> d3 + v242 Fma { a=v240, b=v234, c=v234, neg_product=false, neg_addend=false } -> d3 + v243 Imm(0) -> x0 + v244 Binop { op=fmul, lhs=v240, rhs=v242 } -> d4 + v245 Fma { a=v240, b=v242, c=v234, neg_product=false, neg_addend=false } -> d2 + v246 Imm(0) -> x0 + v247 Binop { op=fmul, lhs=v132, rhs=v245 } -> d4 + v248 Fma { a=v132, b=v245, c=v234, neg_product=false, neg_addend=false } -> d4 + v249 Imm(0) -> x0 + v250 Imm(4618441417868443648) -> x0 + v251 Binop { op=fdiv, lhs=v132, rhs=v250 } -> d5 + v252 Imm(4611686018427387904) -> x0 + v253 Binop { op=fmul, lhs=v252, rhs=v242 } -> d6 + v254 Fma { a=v252, b=v242, c=v234, neg_product=false, neg_addend=false } -> d3 + v255 Binop { op=fmul, lhs=v252, rhs=v245 } -> d6 + v256 Fma { a=v252, b=v245, c=v254, neg_product=false, neg_addend=false } -> d2 + v257 Binop { op=fadd, lhs=v256, rhs=v248 } -> d2 + v258 Binop { op=fmul, lhs=v251, rhs=v257 } -> d3 + v259 Fma { a=v251, b=v257, c=v234, neg_product=false, neg_addend=false } -> d1 + v260 StoreLocal { off=-26, value=v259, kind=F64 } -> - + v261 Imm(3) -> x0 + v262 Imm(4) -> x0 + v263 Imm(0) -> x0 + v264 Imm(4) -> x0 + v265 Imm(1) -> x0 + v266 LoadLocal { off=-26, kind=F64 } -> d1 + v267 LoadLocal { off=-27, kind=F64 } -> d2 + v268 Imm(0) -> x0 + v269 Imm(0) -> x0 + v270 Imm(0) -> x0 + v271 Imm(4602678819172646912) -> x0 + v272 Binop { op=fmul, lhs=v132, rhs=v271 } -> d2 + v273 Binop { op=fmul, lhs=v272, rhs=v266 } -> d3 + v274 Fma { a=v272, b=v266, c=v266, neg_product=false, neg_addend=false } -> d3 + v275 Imm(0) -> x0 + v276 Binop { op=fmul, lhs=v272, rhs=v274 } -> d4 + v277 Fma { a=v272, b=v274, c=v266, neg_product=false, neg_addend=false } -> d2 + v278 Imm(0) -> x0 + v279 Binop { op=fmul, lhs=v132, rhs=v277 } -> d4 + v280 Fma { a=v132, b=v277, c=v266, neg_product=false, neg_addend=false } -> d4 + v281 Imm(0) -> x0 + v282 Imm(4618441417868443648) -> x0 + v283 Binop { op=fdiv, lhs=v132, rhs=v282 } -> d5 + v284 Imm(4611686018427387904) -> x0 + v285 Binop { op=fmul, lhs=v284, rhs=v274 } -> d6 + v286 Fma { a=v284, b=v274, c=v266, neg_product=false, neg_addend=false } -> d3 + v287 Binop { op=fmul, lhs=v284, rhs=v277 } -> d6 + v288 Fma { a=v284, b=v277, c=v286, neg_product=false, neg_addend=false } -> d2 + v289 Binop { op=fadd, lhs=v288, rhs=v280 } -> d2 + v290 Binop { op=fmul, lhs=v283, rhs=v289 } -> d3 + v291 Fma { a=v283, b=v289, c=v266, neg_product=false, neg_addend=false } -> d1 + v292 StoreLocal { off=-26, value=v291, kind=F64 } -> - + v293 Imm(4) -> x0 + v294 Imm(5) -> x0 + v295 Imm(0) -> x0 + v296 Imm(5) -> x0 + v297 Imm(1) -> x0 + v298 LoadLocal { off=-26, kind=F64 } -> d1 + v299 LoadLocal { off=-27, kind=F64 } -> d2 + v300 Imm(0) -> x0 + v301 Imm(0) -> x0 + v302 Imm(0) -> x0 + v303 Imm(4602678819172646912) -> x0 + v304 Binop { op=fmul, lhs=v132, rhs=v303 } -> d2 + v305 Binop { op=fmul, lhs=v304, rhs=v298 } -> d3 + v306 Fma { a=v304, b=v298, c=v298, neg_product=false, neg_addend=false } -> d3 + v307 Imm(0) -> x0 + v308 Binop { op=fmul, lhs=v304, rhs=v306 } -> d4 + v309 Fma { a=v304, b=v306, c=v298, neg_product=false, neg_addend=false } -> d2 + v310 Imm(0) -> x0 + v311 Binop { op=fmul, lhs=v132, rhs=v309 } -> d4 + v312 Fma { a=v132, b=v309, c=v298, neg_product=false, neg_addend=false } -> d4 + v313 Imm(0) -> x0 + v314 Imm(4618441417868443648) -> x0 + v315 Binop { op=fdiv, lhs=v132, rhs=v314 } -> d5 + v316 Imm(4611686018427387904) -> x0 + v317 Binop { op=fmul, lhs=v316, rhs=v306 } -> d6 + v318 Fma { a=v316, b=v306, c=v298, neg_product=false, neg_addend=false } -> d3 + v319 Binop { op=fmul, lhs=v316, rhs=v309 } -> d6 + v320 Fma { a=v316, b=v309, c=v318, neg_product=false, neg_addend=false } -> d2 + v321 Binop { op=fadd, lhs=v320, rhs=v312 } -> d2 + v322 Binop { op=fmul, lhs=v315, rhs=v321 } -> d3 + v323 Fma { a=v315, b=v321, c=v298, neg_product=false, neg_addend=false } -> d1 + v324 StoreLocal { off=-26, value=v323, kind=F64 } -> - + v325 Imm(5) -> x0 + v326 Imm(6) -> x0 + v327 Imm(0) -> x0 + v328 Imm(6) -> x0 + v329 Imm(1) -> x0 + v330 LoadLocal { off=-26, kind=F64 } -> d1 + v331 LoadLocal { off=-27, kind=F64 } -> d2 + v332 Imm(0) -> x0 + v333 Imm(0) -> x0 + v334 Imm(0) -> x0 + v335 Imm(4602678819172646912) -> x0 + v336 Binop { op=fmul, lhs=v132, rhs=v335 } -> d2 + v337 Binop { op=fmul, lhs=v336, rhs=v330 } -> d3 + v338 Fma { a=v336, b=v330, c=v330, neg_product=false, neg_addend=false } -> d3 + v339 Imm(0) -> x0 + v340 Binop { op=fmul, lhs=v336, rhs=v338 } -> d4 + v341 Fma { a=v336, b=v338, c=v330, neg_product=false, neg_addend=false } -> d2 + v342 Imm(0) -> x0 + v343 Binop { op=fmul, lhs=v132, rhs=v341 } -> d4 + v344 Fma { a=v132, b=v341, c=v330, neg_product=false, neg_addend=false } -> d4 + v345 Imm(0) -> x0 + v346 Imm(4618441417868443648) -> x0 + v347 Binop { op=fdiv, lhs=v132, rhs=v346 } -> d5 + v348 Imm(4611686018427387904) -> x0 + v349 Binop { op=fmul, lhs=v348, rhs=v338 } -> d6 + v350 Fma { a=v348, b=v338, c=v330, neg_product=false, neg_addend=false } -> d3 + v351 Binop { op=fmul, lhs=v348, rhs=v341 } -> d6 + v352 Fma { a=v348, b=v341, c=v350, neg_product=false, neg_addend=false } -> d2 + v353 Binop { op=fadd, lhs=v352, rhs=v344 } -> d2 + v354 Binop { op=fmul, lhs=v347, rhs=v353 } -> d3 + v355 Fma { a=v347, b=v353, c=v330, neg_product=false, neg_addend=false } -> d1 + v356 StoreLocal { off=-26, value=v355, kind=F64 } -> - + v357 Imm(6) -> x0 + v358 Imm(7) -> x0 + v359 Imm(0) -> x0 + v360 Imm(7) -> x0 + v361 Imm(1) -> x0 + v362 LoadLocal { off=-26, kind=F64 } -> d1 + v363 LoadLocal { off=-27, kind=F64 } -> d2 + v364 Imm(0) -> x0 + v365 Imm(0) -> x0 + v366 Imm(0) -> x0 + v367 Imm(4602678819172646912) -> x0 + v368 Binop { op=fmul, lhs=v132, rhs=v367 } -> d2 + v369 Binop { op=fmul, lhs=v368, rhs=v362 } -> d3 + v370 Fma { a=v368, b=v362, c=v362, neg_product=false, neg_addend=false } -> d3 + v371 Imm(0) -> x0 + v372 Binop { op=fmul, lhs=v368, rhs=v370 } -> d4 + v373 Fma { a=v368, b=v370, c=v362, neg_product=false, neg_addend=false } -> d2 + v374 Imm(0) -> x0 + v375 Binop { op=fmul, lhs=v132, rhs=v373 } -> d4 + v376 Fma { a=v132, b=v373, c=v362, neg_product=false, neg_addend=false } -> d4 + v377 Imm(0) -> x0 + v378 Imm(4618441417868443648) -> x0 + v379 Binop { op=fdiv, lhs=v132, rhs=v378 } -> d5 + v380 Imm(4611686018427387904) -> x0 + v381 Binop { op=fmul, lhs=v380, rhs=v370 } -> d6 + v382 Fma { a=v380, b=v370, c=v362, neg_product=false, neg_addend=false } -> d3 + v383 Binop { op=fmul, lhs=v380, rhs=v373 } -> d6 + v384 Fma { a=v380, b=v373, c=v382, neg_product=false, neg_addend=false } -> d2 + v385 Binop { op=fadd, lhs=v384, rhs=v376 } -> d2 + v386 Binop { op=fmul, lhs=v379, rhs=v385 } -> d3 + v387 Fma { a=v379, b=v385, c=v362, neg_product=false, neg_addend=false } -> d1 + v388 StoreLocal { off=-26, value=v387, kind=F64 } -> - + v389 Imm(7) -> x0 + v390 Imm(8) -> x0 + v391 Imm(0) -> x0 + v392 Imm(8) -> x0 + v393 Imm(1) -> x0 + v394 LoadLocal { off=-26, kind=F64 } -> d1 + v395 LoadLocal { off=-27, kind=F64 } -> d2 + v396 Imm(0) -> x0 + v397 Imm(0) -> x0 + v398 Imm(0) -> x0 + v399 Imm(4602678819172646912) -> x0 + v400 Binop { op=fmul, lhs=v132, rhs=v399 } -> d2 + v401 Binop { op=fmul, lhs=v400, rhs=v394 } -> d3 + v402 Fma { a=v400, b=v394, c=v394, neg_product=false, neg_addend=false } -> d3 + v403 Imm(0) -> x0 + v404 Binop { op=fmul, lhs=v400, rhs=v402 } -> d4 + v405 Fma { a=v400, b=v402, c=v394, neg_product=false, neg_addend=false } -> d2 + v406 Imm(0) -> x0 + v407 Binop { op=fmul, lhs=v132, rhs=v405 } -> d4 + v408 Fma { a=v132, b=v405, c=v394, neg_product=false, neg_addend=false } -> d4 + v409 Imm(0) -> x0 + v410 Imm(4618441417868443648) -> x0 + v411 Binop { op=fdiv, lhs=v132, rhs=v410 } -> d5 + v412 Imm(4611686018427387904) -> x0 + v413 Binop { op=fmul, lhs=v412, rhs=v402 } -> d6 + v414 Fma { a=v412, b=v402, c=v394, neg_product=false, neg_addend=false } -> d3 + v415 Binop { op=fmul, lhs=v412, rhs=v405 } -> d6 + v416 Fma { a=v412, b=v405, c=v414, neg_product=false, neg_addend=false } -> d2 + v417 Binop { op=fadd, lhs=v416, rhs=v408 } -> d2 + v418 Binop { op=fmul, lhs=v411, rhs=v417 } -> d3 + v419 Fma { a=v411, b=v417, c=v394, neg_product=false, neg_addend=false } -> d1 + v420 StoreLocal { off=-26, value=v419, kind=F64 } -> - + v421 Imm(8) -> x0 + v422 Imm(9) -> x0 + v423 Imm(0) -> x0 + v424 Imm(9) -> x0 + v425 Imm(1) -> x0 + v426 LoadLocal { off=-26, kind=F64 } -> d1 + v427 LoadLocal { off=-27, kind=F64 } -> d2 + v428 Imm(0) -> x0 + v429 Imm(0) -> x0 + v430 Imm(0) -> x0 + v431 Imm(4602678819172646912) -> x0 + v432 Binop { op=fmul, lhs=v132, rhs=v431 } -> d2 + v433 Binop { op=fmul, lhs=v432, rhs=v426 } -> d3 + v434 Fma { a=v432, b=v426, c=v426, neg_product=false, neg_addend=false } -> d3 + v435 Imm(0) -> x0 + v436 Binop { op=fmul, lhs=v432, rhs=v434 } -> d4 + v437 Fma { a=v432, b=v434, c=v426, neg_product=false, neg_addend=false } -> d2 + v438 Imm(0) -> x0 + v439 Binop { op=fmul, lhs=v132, rhs=v437 } -> d4 + v440 Fma { a=v132, b=v437, c=v426, neg_product=false, neg_addend=false } -> d4 + v441 Imm(0) -> x0 + v442 Imm(4618441417868443648) -> x0 + v443 Binop { op=fdiv, lhs=v132, rhs=v442 } -> d5 + v444 Imm(4611686018427387904) -> x0 + v445 Binop { op=fmul, lhs=v444, rhs=v434 } -> d6 + v446 Fma { a=v444, b=v434, c=v426, neg_product=false, neg_addend=false } -> d3 + v447 Binop { op=fmul, lhs=v444, rhs=v437 } -> d6 + v448 Fma { a=v444, b=v437, c=v446, neg_product=false, neg_addend=false } -> d2 + v449 Binop { op=fadd, lhs=v448, rhs=v440 } -> d2 + v450 Binop { op=fmul, lhs=v443, rhs=v449 } -> d3 + v451 Fma { a=v443, b=v449, c=v426, neg_product=false, neg_addend=false } -> d1 + v452 StoreLocal { off=-26, value=v451, kind=F64 } -> - + v453 Imm(9) -> x0 + v454 Imm(10) -> x0 + v455 Imm(0) -> x0 + v456 Imm(10) -> x0 + v457 Imm(1) -> x0 + v458 LoadLocal { off=-26, kind=F64 } -> d1 + v459 LoadLocal { off=-27, kind=F64 } -> d2 + v460 Imm(0) -> x0 + v461 Imm(0) -> x0 + v462 Imm(0) -> x0 + v463 Imm(4602678819172646912) -> x0 + v464 Binop { op=fmul, lhs=v132, rhs=v463 } -> d2 + v465 Binop { op=fmul, lhs=v464, rhs=v458 } -> d3 + v466 Fma { a=v464, b=v458, c=v458, neg_product=false, neg_addend=false } -> d3 + v467 Imm(0) -> x0 + v468 Binop { op=fmul, lhs=v464, rhs=v466 } -> d4 + v469 Fma { a=v464, b=v466, c=v458, neg_product=false, neg_addend=false } -> d2 + v470 Imm(0) -> x0 + v471 Binop { op=fmul, lhs=v132, rhs=v469 } -> d4 + v472 Fma { a=v132, b=v469, c=v458, neg_product=false, neg_addend=false } -> d4 + v473 Imm(0) -> x0 + v474 Imm(4618441417868443648) -> x0 + v475 Binop { op=fdiv, lhs=v132, rhs=v474 } -> d5 + v476 Imm(4611686018427387904) -> x0 + v477 Binop { op=fmul, lhs=v476, rhs=v466 } -> d6 + v478 Fma { a=v476, b=v466, c=v458, neg_product=false, neg_addend=false } -> d3 + v479 Binop { op=fmul, lhs=v476, rhs=v469 } -> d6 + v480 Fma { a=v476, b=v469, c=v478, neg_product=false, neg_addend=false } -> d2 + v481 Binop { op=fadd, lhs=v480, rhs=v472 } -> d2 + v482 Binop { op=fmul, lhs=v475, rhs=v481 } -> d3 + v483 Fma { a=v475, b=v481, c=v458, neg_product=false, neg_addend=false } -> d1 + v484 StoreLocal { off=-26, value=v483, kind=F64 } -> - + v485 Imm(10) -> x0 + v486 Imm(11) -> x0 + v487 Imm(0) -> x0 + v488 Imm(11) -> x0 + v489 Imm(1) -> x0 + v490 LoadLocal { off=-26, kind=F64 } -> d1 + v491 LoadLocal { off=-27, kind=F64 } -> d2 + v492 Imm(0) -> x0 + v493 Imm(0) -> x0 + v494 Imm(0) -> x0 + v495 Imm(4602678819172646912) -> x0 + v496 Binop { op=fmul, lhs=v132, rhs=v495 } -> d2 + v497 Binop { op=fmul, lhs=v496, rhs=v490 } -> d3 + v498 Fma { a=v496, b=v490, c=v490, neg_product=false, neg_addend=false } -> d3 + v499 Imm(0) -> x0 + v500 Binop { op=fmul, lhs=v496, rhs=v498 } -> d4 + v501 Fma { a=v496, b=v498, c=v490, neg_product=false, neg_addend=false } -> d2 + v502 Imm(0) -> x0 + v503 Binop { op=fmul, lhs=v132, rhs=v501 } -> d4 + v504 Fma { a=v132, b=v501, c=v490, neg_product=false, neg_addend=false } -> d4 + v505 Imm(0) -> x0 + v506 Imm(4618441417868443648) -> x0 + v507 Binop { op=fdiv, lhs=v132, rhs=v506 } -> d5 + v508 Imm(4611686018427387904) -> x0 + v509 Binop { op=fmul, lhs=v508, rhs=v498 } -> d6 + v510 Fma { a=v508, b=v498, c=v490, neg_product=false, neg_addend=false } -> d3 + v511 Binop { op=fmul, lhs=v508, rhs=v501 } -> d6 + v512 Fma { a=v508, b=v501, c=v510, neg_product=false, neg_addend=false } -> d2 + v513 Binop { op=fadd, lhs=v512, rhs=v504 } -> d2 + v514 Binop { op=fmul, lhs=v507, rhs=v513 } -> d3 + v515 Fma { a=v507, b=v513, c=v490, neg_product=false, neg_addend=false } -> d1 + v516 StoreLocal { off=-26, value=v515, kind=F64 } -> - + v517 Imm(11) -> x0 + v518 Imm(12) -> x0 + v519 Imm(0) -> x0 + v520 Imm(12) -> x0 + v521 Imm(1) -> x0 + v522 LoadLocal { off=-26, kind=F64 } -> d1 + v523 LoadLocal { off=-27, kind=F64 } -> d2 + v524 Imm(0) -> x0 + v525 Imm(0) -> x0 + v526 Imm(0) -> x0 + v527 Imm(4602678819172646912) -> x0 + v528 Binop { op=fmul, lhs=v132, rhs=v527 } -> d2 + v529 Binop { op=fmul, lhs=v528, rhs=v522 } -> d3 + v530 Fma { a=v528, b=v522, c=v522, neg_product=false, neg_addend=false } -> d3 + v531 Imm(0) -> x0 + v532 Binop { op=fmul, lhs=v528, rhs=v530 } -> d4 + v533 Fma { a=v528, b=v530, c=v522, neg_product=false, neg_addend=false } -> d2 + v534 Imm(0) -> x0 + v535 Binop { op=fmul, lhs=v132, rhs=v533 } -> d4 + v536 Fma { a=v132, b=v533, c=v522, neg_product=false, neg_addend=false } -> d4 + v537 Imm(0) -> x0 + v538 Imm(4618441417868443648) -> x0 + v539 Binop { op=fdiv, lhs=v132, rhs=v538 } -> d5 + v540 Imm(4611686018427387904) -> x0 + v541 Binop { op=fmul, lhs=v540, rhs=v530 } -> d6 + v542 Fma { a=v540, b=v530, c=v522, neg_product=false, neg_addend=false } -> d3 + v543 Binop { op=fmul, lhs=v540, rhs=v533 } -> d6 + v544 Fma { a=v540, b=v533, c=v542, neg_product=false, neg_addend=false } -> d2 + v545 Binop { op=fadd, lhs=v544, rhs=v536 } -> d2 + v546 Binop { op=fmul, lhs=v539, rhs=v545 } -> d3 + v547 Fma { a=v539, b=v545, c=v522, neg_product=false, neg_addend=false } -> d1 + v548 StoreLocal { off=-26, value=v547, kind=F64 } -> - + v549 Imm(12) -> x0 + v550 Imm(13) -> x0 + v551 Imm(0) -> x0 + v552 Imm(13) -> x0 + v553 Imm(1) -> x0 + v554 LoadLocal { off=-26, kind=F64 } -> d1 + v555 LoadLocal { off=-27, kind=F64 } -> d2 + v556 Imm(0) -> x0 + v557 Imm(0) -> x0 + v558 Imm(0) -> x0 + v559 Imm(4602678819172646912) -> x0 + v560 Binop { op=fmul, lhs=v132, rhs=v559 } -> d2 + v561 Binop { op=fmul, lhs=v560, rhs=v554 } -> d3 + v562 Fma { a=v560, b=v554, c=v554, neg_product=false, neg_addend=false } -> d3 + v563 Imm(0) -> x0 + v564 Binop { op=fmul, lhs=v560, rhs=v562 } -> d4 + v565 Fma { a=v560, b=v562, c=v554, neg_product=false, neg_addend=false } -> d2 + v566 Imm(0) -> x0 + v567 Binop { op=fmul, lhs=v132, rhs=v565 } -> d4 + v568 Fma { a=v132, b=v565, c=v554, neg_product=false, neg_addend=false } -> d4 + v569 Imm(0) -> x0 + v570 Imm(4618441417868443648) -> x0 + v571 Binop { op=fdiv, lhs=v132, rhs=v570 } -> d5 + v572 Imm(4611686018427387904) -> x0 + v573 Binop { op=fmul, lhs=v572, rhs=v562 } -> d6 + v574 Fma { a=v572, b=v562, c=v554, neg_product=false, neg_addend=false } -> d3 + v575 Binop { op=fmul, lhs=v572, rhs=v565 } -> d6 + v576 Fma { a=v572, b=v565, c=v574, neg_product=false, neg_addend=false } -> d2 + v577 Binop { op=fadd, lhs=v576, rhs=v568 } -> d2 + v578 Binop { op=fmul, lhs=v571, rhs=v577 } -> d3 + v579 Fma { a=v571, b=v577, c=v554, neg_product=false, neg_addend=false } -> d1 + v580 StoreLocal { off=-26, value=v579, kind=F64 } -> - + v581 Imm(13) -> x0 + v582 Imm(14) -> x0 + v583 Imm(0) -> x0 + v584 Imm(14) -> x0 + v585 Imm(1) -> x0 + v586 LoadLocal { off=-26, kind=F64 } -> d1 + v587 LoadLocal { off=-27, kind=F64 } -> d2 + v588 Imm(0) -> x0 + v589 Imm(0) -> x0 + v590 Imm(0) -> x0 + v591 Imm(4602678819172646912) -> x0 + v592 Binop { op=fmul, lhs=v132, rhs=v591 } -> d2 + v593 Binop { op=fmul, lhs=v592, rhs=v586 } -> d3 + v594 Fma { a=v592, b=v586, c=v586, neg_product=false, neg_addend=false } -> d3 + v595 Imm(0) -> x0 + v596 Binop { op=fmul, lhs=v592, rhs=v594 } -> d4 + v597 Fma { a=v592, b=v594, c=v586, neg_product=false, neg_addend=false } -> d2 + v598 Imm(0) -> x0 + v599 Binop { op=fmul, lhs=v132, rhs=v597 } -> d4 + v600 Fma { a=v132, b=v597, c=v586, neg_product=false, neg_addend=false } -> d4 + v601 Imm(0) -> x0 + v602 Imm(4618441417868443648) -> x0 + v603 Binop { op=fdiv, lhs=v132, rhs=v602 } -> d5 + v604 Imm(4611686018427387904) -> x0 + v605 Binop { op=fmul, lhs=v604, rhs=v594 } -> d6 + v606 Fma { a=v604, b=v594, c=v586, neg_product=false, neg_addend=false } -> d3 + v607 Binop { op=fmul, lhs=v604, rhs=v597 } -> d6 + v608 Fma { a=v604, b=v597, c=v606, neg_product=false, neg_addend=false } -> d2 + v609 Binop { op=fadd, lhs=v608, rhs=v600 } -> d2 + v610 Binop { op=fmul, lhs=v603, rhs=v609 } -> d3 + v611 Fma { a=v603, b=v609, c=v586, neg_product=false, neg_addend=false } -> d1 + v612 StoreLocal { off=-26, value=v611, kind=F64 } -> - + v613 Imm(14) -> x0 + v614 Imm(15) -> x0 + v615 Imm(0) -> x0 + v616 Imm(15) -> x0 + v617 Imm(1) -> x0 + v618 LoadLocal { off=-26, kind=F64 } -> d1 + v619 LoadLocal { off=-27, kind=F64 } -> d2 + v620 Imm(0) -> x0 + v621 Imm(0) -> x0 + v622 Imm(0) -> x0 + v623 Imm(4602678819172646912) -> x0 + v624 Binop { op=fmul, lhs=v132, rhs=v623 } -> d2 + v625 Binop { op=fmul, lhs=v624, rhs=v618 } -> d3 + v626 Fma { a=v624, b=v618, c=v618, neg_product=false, neg_addend=false } -> d3 + v627 Imm(0) -> x0 + v628 Binop { op=fmul, lhs=v624, rhs=v626 } -> d4 + v629 Fma { a=v624, b=v626, c=v618, neg_product=false, neg_addend=false } -> d2 + v630 Imm(0) -> x0 + v631 Binop { op=fmul, lhs=v132, rhs=v629 } -> d4 + v632 Fma { a=v132, b=v629, c=v618, neg_product=false, neg_addend=false } -> d4 + v633 Imm(0) -> x0 + v634 Imm(4618441417868443648) -> x0 + v635 Binop { op=fdiv, lhs=v132, rhs=v634 } -> d0 + v636 Imm(4611686018427387904) -> x0 + v637 Binop { op=fmul, lhs=v636, rhs=v626 } -> d5 + v638 Fma { a=v636, b=v626, c=v618, neg_product=false, neg_addend=false } -> d3 + v639 Binop { op=fmul, lhs=v636, rhs=v629 } -> d5 + v640 Fma { a=v636, b=v629, c=v638, neg_product=false, neg_addend=false } -> d2 + v641 Binop { op=fadd, lhs=v640, rhs=v632 } -> d2 + v642 Binop { op=fmul, lhs=v635, rhs=v641 } -> d3 + v643 Fma { a=v635, b=v641, c=v618, neg_product=false, neg_addend=false } -> d0 + v644 StoreLocal { off=-26, value=v643, kind=F64 } -> - + v645 Imm(15) -> x0 + v646 Imm(16) -> x0 + v647 Imm(0) -> x0 + v648 Imm(16) -> x0 + v649 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v649) + block 25 start_pc=0 + v650 Imm(4613303445314885481) -> x0 + v651 StoreLocal { off=-29, value=v650, kind=F64 } -> - + v652 LoadLocal { off=-26, kind=F64 } -> d0 + v653 LoadLocal { off=-29, kind=F64 } -> d1 + v654 Binop { op=fsub, lhs=v652, rhs=v653 } -> d1 + v655 Imm(0) -> x0 + v656 LoadLocal { off=-30, kind=F64 } -> d0 + v657 Imm(0) -> x0 + v658 Binop { op=flt, lhs=v654, rhs=v657 } -> x0 + terminator Bz { cond=v658, target=b30, fall=b26 } (exit_acc=v658) + block 26 start_pc=0 + v659 LoadLocal { off=-30, kind=F64 } -> d0 + v660 Fneg(v654) -> d1 + v661 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v660) + block 27 start_pc=0 + v662 Phi { incoming=[b30:v654, b26:v660], kind=F64 } -> d1 + v663 LoadLocal { off=-30, kind=F64 } -> d0 + v664 Imm(4517329193108106637) -> x0 + v665 Binop { op=fgt, lhs=v662, rhs=v664 } -> x0 + terminator Bz { cond=v665, target=b29, fall=b28 } (exit_acc=v665) block 28 start_pc=0 - v136 Phi { incoming=[b27:v134, b29:v140], kind=I64 } -> x1 - v137 Extend { value=v136, kind=I32 } -> x0 - v138 BinopI { op=lt, lhs=v137, rhs_imm=16 } -> x0 - terminator Bz { cond=v138, target=b31, fall=b30 } (exit_acc=v138) + v666 Imm(5) -> x0 + terminator Return(v666) (exit_acc=v666) block 29 start_pc=0 - v139 Extend { value=v136, kind=I32 } -> x0 - v140 BinopI { op=add, lhs=v139, rhs_imm=1 } -> x1 - v141 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v140) + v667 Imm(0) -> x0 + terminator Return(v667) (exit_acc=v667) block 30 start_pc=0 - v142 LoadLocal { off=-26, kind=F64 } -> d1 - v143 LoadLocal { off=-27, kind=F64 } -> d2 - v144 Imm(0) -> x0 - v145 Imm(0) -> x0 - v146 Imm(0) -> x0 - v147 Imm(4602678819172646912) -> x0 - v148 Binop { op=fmul, lhs=v132, rhs=v147 } -> d2 - v149 Binop { op=fmul, lhs=v148, rhs=v142 } -> d3 - v150 Fma { a=v148, b=v142, c=v142, neg_product=false, neg_addend=false } -> d3 - v151 Imm(0) -> x0 - v152 Binop { op=fmul, lhs=v148, rhs=v150 } -> d4 - v153 Fma { a=v148, b=v150, c=v142, neg_product=false, neg_addend=false } -> d2 - v154 Imm(0) -> x0 - v155 Binop { op=fmul, lhs=v132, rhs=v153 } -> d4 - v156 Fma { a=v132, b=v153, c=v142, neg_product=false, neg_addend=false } -> d4 - v157 Imm(0) -> x0 - v158 Imm(4618441417868443648) -> x0 - v159 Binop { op=fdiv, lhs=v132, rhs=v158 } -> d5 - v160 Imm(4611686018427387904) -> x0 - v161 Binop { op=fmul, lhs=v160, rhs=v150 } -> d6 - v162 Fma { a=v160, b=v150, c=v142, neg_product=false, neg_addend=false } -> d3 - v163 Binop { op=fmul, lhs=v160, rhs=v153 } -> d6 - v164 Fma { a=v160, b=v153, c=v162, neg_product=false, neg_addend=false } -> d2 - v165 Binop { op=fadd, lhs=v164, rhs=v156 } -> d2 - v166 Binop { op=fmul, lhs=v159, rhs=v165 } -> d3 - v167 Fma { a=v159, b=v165, c=v142, neg_product=false, neg_addend=false } -> d1 - v168 StoreLocal { off=-26, value=v167, kind=F64 } -> - - terminator Jmp(b29) (exit_acc=v168) + terminator Jmp(b27) block 31 start_pc=0 - v169 Imm(4613303445314885481) -> x0 - v170 StoreLocal { off=-29, value=v169, kind=F64 } -> - - v171 LoadLocal { off=-26, kind=F64 } -> d0 - v172 LoadLocal { off=-29, kind=F64 } -> d1 - v173 Binop { op=fsub, lhs=v171, rhs=v172 } -> d1 - v174 Imm(0) -> x0 - v175 LoadLocal { off=-30, kind=F64 } -> d0 - v176 Imm(0) -> x0 - v177 Binop { op=flt, lhs=v173, rhs=v176 } -> x0 - terminator Bz { cond=v177, target=b36, fall=b32 } (exit_acc=v177) + v127 Imm(3) -> x0 + terminator Return(v127) (exit_acc=v127) block 32 start_pc=0 - v178 LoadLocal { off=-30, kind=F64 } -> d0 - v179 Fneg(v173) -> d1 - v180 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v179) + terminator Jmp(b12) block 33 start_pc=0 - v181 Phi { incoming=[b36:v173, b32:v179], kind=F64 } -> d1 - v182 LoadLocal { off=-30, kind=F64 } -> d0 - v183 Imm(4517329193108106637) -> x0 - v184 Binop { op=fgt, lhs=v181, rhs=v183 } -> x0 - terminator Bz { cond=v184, target=b35, fall=b34 } (exit_acc=v184) + terminator Jmp(b19) block 34 start_pc=0 - v185 Imm(5) -> x0 - terminator Return(v185) (exit_acc=v185) - block 35 start_pc=0 - v186 Imm(0) -> x0 - terminator Return(v186) (exit_acc=v186) - block 36 start_pc=0 - terminator Jmp(b33) + terminator Jmp(b17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_arg_decay_then_deref_assign.ssa b/tests/snapshots/ssa/fn_arg_decay_then_deref_assign.ssa index 240520022..132f9a5e7 100644 --- a/tests/snapshots/ssa/fn_arg_decay_then_deref_assign.ssa +++ b/tests/snapshots/ssa/fn_arg_decay_then_deref_assign.ssa @@ -63,19 +63,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=2 v6 ImmData(24) -> x0 v7 Load { addr=v6, disp=0, kind=I32 } -> x0 v8 BinopI { op=eq, lhs=v7, rhs_imm=42 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + terminator Bz { cond=v8, target=b3, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v9 Imm(0) -> x1 v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v9) + terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v11 Imm(1) -> x1 - v12 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v11) - block 3 start_pc=0 - v13 Phi { incoming=[b1:v9, b2:v11], kind=I64 } -> x1 + v13 Phi { incoming=[b1:v9, b3:v11], kind=I64 } -> x1 v14 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v13) (exit_acc=v13) + block 3 start_pc=0 + v11 Imm(1) -> x1 + v12 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v11) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_decay_inside_block.ssa b/tests/snapshots/ssa/fn_ptr_decay_inside_block.ssa index e09c1c7c0..cba207e7e 100644 --- a/tests/snapshots/ssa/fn_ptr_decay_inside_block.ssa +++ b/tests/snapshots/ssa/fn_ptr_decay_inside_block.ssa @@ -17,22 +17,15 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x3 + v1 Imm(0) -> x0 v2 Imm(0) -> x0 v3 Imm(1) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-2, kind=I32 } -> x1 - v6 BinopI { op=eq, lhs=v3, rhs_imm=0 } -> x0 - terminator Bz { cond=v6, target=b3, fall=b1 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-2, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 - v8 ImmCode(ent_pc=0) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v8) - block 3 start_pc=0 - v10 ImmCode(ent_pc=0) -> x12 + v10 ImmCode(ent_pc=0) -> x3 v11 Imm(0) -> x0 v12 LoadLocal { off=-1, kind=I32 } -> x0 v13 Imm(1) -> x7 @@ -40,7 +33,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v15 CallIndirect { target=v10, args=[v13], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 v17 Extend { value=v15, kind=I32 } -> x1 - v18 Binop { op=add, lhs=v1, rhs=v15 } -> x3 + v18 BinopI { op=add, lhs=v15, rhs_imm=0 } -> x12 v19 Imm(0) -> x0 v20 Extend { value=v18, kind=I32 } -> x0 v21 Imm(2) -> x7 @@ -52,17 +45,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v27 Imm(0) -> x0 v28 Extend { value=v26, kind=I32 } -> x0 terminator Jmp(b2) (exit_acc=v28) - block 4 start_pc=0 - v29 Phi { incoming=[b2:v8, b5:v33], kind=I64 } -> x1 - v30 Phi { incoming=[b2:v26, b5:v41], kind=I64 } -> x3 - v31 LoadLocal { off=-6, kind=I64 } -> x0 - v32 BinopI { op=ne, lhs=v29, rhs_imm=0 } -> x0 - terminator Bz { cond=v32, target=b7, fall=b6 } (exit_acc=v32) - block 5 start_pc=0 - v33 Imm(0) -> x1 - v34 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v33) - block 6 start_pc=0 + block 2 start_pc=0 + v8 ImmCode(ent_pc=0) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v8) + block 3 start_pc=0 v35 Extend { value=v30, kind=I32 } -> x0 v36 Imm(3) -> x7 v37 LoadLocal { off=-6, kind=I64 } -> x0 @@ -72,8 +59,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v41 Binop { op=add, lhs=v30, rhs=v38 } -> x3 v42 Imm(0) -> x0 v43 Extend { value=v41, kind=I32 } -> x0 - terminator Jmp(b5) (exit_acc=v43) - block 7 start_pc=0 + terminator Jmp(b4) (exit_acc=v43) + block 4 start_pc=0 + v33 Imm(0) -> x1 + v34 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v33) + block 5 start_pc=0 + v29 Phi { incoming=[b2:v8, b4:v33], kind=I64 } -> x1 + v30 Phi { incoming=[b2:v26, b4:v41], kind=I64 } -> x3 + v31 LoadLocal { off=-6, kind=I64 } -> x0 + v32 BinopI { op=ne, lhs=v29, rhs_imm=0 } -> x0 + terminator Bnz { cond=v32, target=b3, fall=b6 } (exit_acc=v32) + block 6 start_pc=0 v44 ImmCode(ent_pc=0) -> x0 v45 StoreLocal { off=-9, value=v44, kind=I64 } -> - v46 Extend { value=v30, kind=I32 } -> x0 @@ -87,19 +84,22 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v54 Imm(0) -> x1 v55 Extend { value=v53, kind=I32 } -> x0 v56 BinopI { op=eq, lhs=v55, rhs_imm=410 } -> x0 - terminator Bz { cond=v56, target=b9, fall=b8 } (exit_acc=v56) - block 8 start_pc=0 + terminator Bz { cond=v56, target=b9, fall=b7 } (exit_acc=v56) + block 7 start_pc=0 v57 Imm(0) -> x1 v58 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v57) + terminator Jmp(b8) (exit_acc=v57) + block 8 start_pc=0 + v61 Phi { incoming=[b7:v57, b9:v59], kind=I64 } -> x1 + v62 LoadLocal { off=-12, kind=I64 } -> x0 + terminator Return(v61) (exit_acc=v61) block 9 start_pc=0 v59 Imm(2) -> x1 v60 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v59) + terminator Jmp(b8) (exit_acc=v59) block 10 start_pc=0 - v61 Phi { incoming=[b8:v57, b9:v59], kind=I64 } -> x1 - v62 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Return(v61) (exit_acc=v61) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_arg.ssa b/tests/snapshots/ssa/fn_ptr_float_arg.ssa index 5a1c5f3d7..a8c5b282c 100644 --- a/tests/snapshots/ssa/fn_ptr_float_arg.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_arg.ssa @@ -7,9 +7,9 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v1 ParamRef(0, kind=F32) -> d0 [f32] v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v1 } -> d0 - v6 Binop { op=fmul, lhs=v5, rhs=v4 } -> d0 + v4 Imm(1073741824) -> x0 [f32] + v5 Binop { op=fmul, lhs=v1, rhs=v4 } -> d0 [f32] + v6 FpCast { kind=F32ToF64, value=v5 } -> d0 v7 FpCast { kind=FpToInt, value=v6 } -> x0 terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -75,58 +75,54 @@ fn ent_pc=4 n_params=0 variadic=false locals=5 v0 AllocaInit(0) -> - v1 ImmCode(ent_pc=0) -> x3 v2 Imm(0) -> x0 - v3 Imm(4612811918334230528) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 LoadLocal { off=-1, kind=I64 } -> x0 - v6 CallIndirect { target=v1, args=[v4], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=5 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v3 Imm(1075838976) -> x7 [f32] + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 CallIndirect { target=v1, args=[v3], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x1 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=ne, lhs=v7, rhs_imm=5 } -> x0 + terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 2 start_pc=0 - v11 ImmCode(ent_pc=1) -> x0 - v12 Imm(0) -> x1 - v13 Imm(3) -> x7 - v14 Imm(4616752568008179712) -> x1 - v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] - v16 LoadLocal { off=-2, kind=I64 } -> x1 - v17 CallIndirect { target=v11, args=[v13, v15], callee_variadic=false, fixed_args=2, fp_return=false, fp_arg_mask=0x2 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x0 - v20 BinopI { op=ne, lhs=v19, rhs_imm=7 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v10 ImmCode(ent_pc=1) -> x0 + v11 Imm(0) -> x1 + v12 Imm(3) -> x7 + v13 Imm(1083179008) -> x6 [f32] + v14 LoadLocal { off=-2, kind=I64 } -> x1 + v15 CallIndirect { target=v10, args=[v12, v13], callee_variadic=false, fixed_args=2, fp_return=false, fp_arg_mask=0x2 } -> x0 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 + v17 Extend { value=v15, kind=I32 } -> x0 + v18 BinopI { op=ne, lhs=v17, rhs_imm=7 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v21 Imm(2) -> x0 - terminator Return(v21) (exit_acc=v21) + v19 Imm(2) -> x0 + terminator Return(v19) (exit_acc=v19) block 4 start_pc=0 - v22 Imm(10) -> x7 - v23 ImmCode(ent_pc=3) -> x6 - v24 Imm(4612811918334230528) -> x0 - v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] - v26 Call { target_pc=2, args=[v22, v23, v25], fixed_args=3, fp_return=false, fp_arg_mask=0x4 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=12 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v20 Imm(10) -> x7 + v21 ImmCode(ent_pc=3) -> x6 + v22 Imm(1075838976) -> x2 [f32] + v23 Call { target_pc=2, args=[v20, v21, v22], fixed_args=3, fp_return=false, fp_arg_mask=0x4 } -> x0 + v24 BinopI { op=ne, lhs=v23, rhs_imm=12 } -> x0 + terminator Bz { cond=v24, target=b6, fall=b5 } (exit_acc=v24) block 5 start_pc=0 - v28 Imm(3) -> x0 - terminator Return(v28) (exit_acc=v28) + v25 Imm(3) -> x0 + terminator Return(v25) (exit_acc=v25) block 6 start_pc=0 - v29 Imm(4615063718147915776) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 LoadLocal { off=-1, kind=I64 } -> x0 - v32 CallIndirect { target=v1, args=[v30], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 - v34 Extend { value=v32, kind=I32 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=7 } -> x0 - terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) + v26 Imm(1080033280) -> x7 [f32] + v27 LoadLocal { off=-1, kind=I64 } -> x0 + v28 CallIndirect { target=v1, args=[v26], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 + v30 Extend { value=v28, kind=I32 } -> x0 + v31 BinopI { op=ne, lhs=v30, rhs_imm=7 } -> x0 + terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v36 Imm(4) -> x0 - terminator Return(v36) (exit_acc=v36) + v32 Imm(4) -> x0 + terminator Return(v32) (exit_acc=v32) block 8 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) + v33 Imm(0) -> x0 + terminator Return(v33) (exit_acc=v33) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa b/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa index eed53e27e..297f6c814 100644 --- a/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa @@ -7,11 +7,9 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v1 ParamRef(0, kind=F32) -> d0 [f32] v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v1 } -> d0 - v6 Binop { op=fmul, lhs=v5, rhs=v4 } -> d0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] - terminator Return(v7) (exit_acc=v7) + v4 Imm(1073741824) -> x0 [f32] + v5 Binop { op=fmul, lhs=v1, rhs=v4 } -> d0 [f32] + terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=negf fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -49,148 +47,128 @@ fn ent_pc=3 n_params=0 variadic=false locals=29 v4 LocalAddr(-2) -> x0 v5 Imm(0) -> x1 v6 Load { addr=v4, disp=0, kind=I64 } -> x0 - v7 Imm(4613937818241073152) -> x1 - v8 FpCast { kind=F64ToF32, value=v7 } -> d0 [f32] - v9 CallIndirect { target=v6, args=[v8], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v10 Imm(4618441417868443648) -> x0 - v11 FpCast { kind=F32ToF64, value=v9 } -> d0 - v12 Binop { op=fne, lhs=v11, rhs=v10 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v7 Imm(1077936128) -> x7 [f32] + v8 CallIndirect { target=v6, args=[v7], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v9 Imm(1086324736) -> x0 [f32] + v10 Binop { op=fne, lhs=v8, rhs=v9 } -> x0 + terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 2 start_pc=0 - v14 LocalAddr(-2) -> x0 - v15 Imm(8) -> x1 - v16 BinopI { op=add, lhs=v14, rhs_imm=8 } -> x1 - v17 Load { addr=v14, disp=8, kind=I64 } -> x0 - v18 Imm(4613937818241073152) -> x3 - v19 FpCast { kind=F64ToF32, value=v18 } -> d0 [f32] - v20 CallIndirect { target=v17, args=[v19], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v21 Fneg(v18) -> d1 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v12 LocalAddr(-2) -> x0 + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v12, rhs_imm=8 } -> x1 + v15 Load { addr=v12, disp=8, kind=I64 } -> x0 + v16 Imm(1077936128) -> x3 [f32] + v17 CallIndirect { target=v15, args=[v16], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v18 Fneg(v16) -> d1 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v20 Imm(2) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v25 Imm(0) -> x0 - v26 Imm(0) -> x1 - v27 LocalAddr(-2) -> x1 - v28 LoadLocal { off=-7, kind=I32 } -> x2 - v29 BinopI { op=shl, lhs=v25, rhs_imm=3 } -> x2 - v30 Binop { op=add, lhs=v27, rhs=v29 } -> x2 - v31 LoadIndexed { base=v27, index=v25, scale=8, kind=I64 } -> x0 - v32 Imm(4616189618054758400) -> x1 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 CallIndirect { target=v31, args=[v33], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v35 Imm(4620693217682128896) -> x0 - v36 FpCast { kind=F32ToF64, value=v34 } -> d0 - v37 Binop { op=fne, lhs=v36, rhs=v35 } -> x0 - terminator Bz { cond=v37, target=b6, fall=b5 } (exit_acc=v37) + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 LocalAddr(-2) -> x0 + v24 LoadLocal { off=-7, kind=I32 } -> x1 + v25 Imm(0) -> x1 + v26 BinopI { op=add, lhs=v23, rhs_imm=0 } -> x0 + v27 Load { addr=v26, disp=0, kind=I64 } -> x0 + v28 Imm(1082130432) -> x7 [f32] + v29 CallIndirect { target=v27, args=[v28], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v30 Imm(1090519040) -> x0 [f32] + v31 Binop { op=fne, lhs=v29, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) block 5 start_pc=0 - v38 Imm(3) -> x0 - terminator Return(v38) (exit_acc=v38) + v32 Imm(3) -> x0 + terminator Return(v32) (exit_acc=v32) block 6 start_pc=0 - v39 LocalAddr(-10) -> x0 - v40 ImmData(24) -> x1 - v41 Mcpy { dst=v39, src=v40, size=8 } -> x0 - v42 LocalAddr(-10) -> x0 - v43 Imm(0) -> x1 - v44 Load { addr=v42, disp=0, kind=I64 } -> x0 - v45 Imm(4609434218613702656) -> x1 - v46 FpCast { kind=F64ToF32, value=v45 } -> d0 [f32] - v47 Imm(4611686018427387904) -> x1 - v48 FpCast { kind=F64ToF32, value=v47 } -> d1 [f32] - v49 CallIndirect { target=v44, args=[v46, v48], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v50 Imm(4615063718147915776) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b8, fall=b7 } (exit_acc=v52) + v33 LocalAddr(-10) -> x0 + v34 ImmData(24) -> x1 + v35 Mcpy { dst=v33, src=v34, size=8 } -> x0 + v36 LocalAddr(-10) -> x0 + v37 Imm(0) -> x1 + v38 Load { addr=v36, disp=0, kind=I64 } -> x0 + v39 Imm(1069547520) -> x7 [f32] + v40 Imm(1073741824) -> x6 [f32] + v41 CallIndirect { target=v38, args=[v39, v40], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v42 Imm(1080033280) -> x0 [f32] + v43 Binop { op=fne, lhs=v41, rhs=v42 } -> x0 + terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) block 7 start_pc=0 - v53 Imm(4) -> x0 - terminator Return(v53) (exit_acc=v53) + v44 Imm(4) -> x0 + terminator Return(v44) (exit_acc=v44) block 8 start_pc=0 - v54 ImmCode(ent_pc=0) -> x0 - v55 Imm(0) -> x1 - v56 Imm(4617315517961601024) -> x1 - v57 FpCast { kind=F64ToF32, value=v56 } -> d0 [f32] - v58 LoadLocal { off=-14, kind=I64 } -> x1 - v59 CallIndirect { target=v54, args=[v57], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v60 Imm(4621819117588971520) -> x0 - v61 FpCast { kind=F32ToF64, value=v59 } -> d0 - v62 Binop { op=fne, lhs=v61, rhs=v60 } -> x0 - terminator Bz { cond=v62, target=b10, fall=b9 } (exit_acc=v62) + v45 ImmCode(ent_pc=0) -> x0 + v46 Imm(0) -> x1 + v47 Imm(1084227584) -> x7 [f32] + v48 LoadLocal { off=-14, kind=I64 } -> x1 + v49 CallIndirect { target=v45, args=[v47], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v50 Imm(1092616192) -> x0 [f32] + v51 Binop { op=fne, lhs=v49, rhs=v50 } -> x0 + terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) block 9 start_pc=0 - v63 Imm(5) -> x0 - terminator Return(v63) (exit_acc=v63) + v52 Imm(5) -> x0 + terminator Return(v52) (exit_acc=v52) block 10 start_pc=0 - v64 Imm(4619567317775286272) -> x0 - v65 FpCast { kind=F64ToF32, value=v64 } -> d0 [f32] - v66 Imm(0) -> x0 - v67 LocalAddr(-2) -> x0 - v68 Imm(0) -> x1 - v69 Load { addr=v67, disp=0, kind=I64 } -> x0 - v70 LoadLocal { off=-17, kind=F32 } -> d1 [f32] - v71 CallIndirect { target=v69, args=[v65], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v72 Imm(4624070917402656768) -> x0 - v73 FpCast { kind=F32ToF64, value=v71 } -> d0 - v74 Binop { op=fne, lhs=v73, rhs=v72 } -> x0 - terminator Bz { cond=v74, target=b12, fall=b11 } (exit_acc=v74) + v53 Imm(1088421888) -> x0 [f32] + v54 StoreLocal { off=-17, value=v53, kind=F32 } -> - + v55 LocalAddr(-2) -> x0 + v56 Imm(0) -> x1 + v57 Load { addr=v55, disp=0, kind=I64 } -> x0 + v58 LoadLocal { off=-17, kind=F32 } -> d0 [f32] + v59 CallIndirect { target=v57, args=[v58], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v60 Imm(1096810496) -> x0 [f32] + v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x0 + terminator Bz { cond=v61, target=b12, fall=b11 } (exit_acc=v61) block 11 start_pc=0 - v75 Imm(6) -> x0 - terminator Return(v75) (exit_acc=v75) + v62 Imm(6) -> x0 + terminator Return(v62) (exit_acc=v62) block 12 start_pc=0 - v76 LocalAddr(-21) -> x0 - v77 ImmData(32) -> x1 - v78 Mcpy { dst=v76, src=v77, size=16 } -> x0 - v79 LocalAddr(-21) -> x3 - v80 Imm(0) -> x0 - v81 LocalAddr(-21) -> x0 - v82 Load { addr=v81, disp=0, kind=I64 } -> x0 - v83 Imm(4613937818241073152) -> x1 - v84 FpCast { kind=F64ToF32, value=v83 } -> d0 [f32] - v85 CallIndirect { target=v82, args=[v84], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v86 Imm(4618441417868443648) -> x0 - v87 FpCast { kind=F32ToF64, value=v85 } -> d0 - v88 Binop { op=fne, lhs=v87, rhs=v86 } -> x0 - terminator Bz { cond=v88, target=b14, fall=b13 } (exit_acc=v88) + v63 LocalAddr(-21) -> x0 + v64 ImmData(32) -> x1 + v65 Mcpy { dst=v63, src=v64, size=16 } -> x0 + v66 LocalAddr(-21) -> x3 + v67 Imm(0) -> x0 + v68 LocalAddr(-21) -> x0 + v69 Load { addr=v68, disp=0, kind=I64 } -> x0 + v70 Imm(1077936128) -> x7 [f32] + v71 CallIndirect { target=v69, args=[v70], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v72 Imm(1086324736) -> x0 [f32] + v73 Binop { op=fne, lhs=v71, rhs=v72 } -> x0 + terminator Bz { cond=v73, target=b14, fall=b13 } (exit_acc=v73) block 13 start_pc=0 - v89 Imm(7) -> x0 - terminator Return(v89) (exit_acc=v89) + v74 Imm(7) -> x0 + terminator Return(v74) (exit_acc=v74) block 14 start_pc=0 - v90 LoadLocal { off=-22, kind=I64 } -> x0 - v91 Load { addr=v79, disp=0, kind=I64 } -> x0 - v92 Imm(4613937818241073152) -> x1 - v93 FpCast { kind=F64ToF32, value=v92 } -> d0 [f32] - v94 CallIndirect { target=v91, args=[v93], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v95 Imm(4618441417868443648) -> x0 - v96 FpCast { kind=F32ToF64, value=v94 } -> d0 - v97 Binop { op=fne, lhs=v96, rhs=v95 } -> x0 - terminator Bz { cond=v97, target=b16, fall=b15 } (exit_acc=v97) + v75 LoadLocal { off=-22, kind=I64 } -> x0 + v76 Load { addr=v66, disp=0, kind=I64 } -> x0 + v77 Imm(1077936128) -> x7 [f32] + v78 CallIndirect { target=v76, args=[v77], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v79 Imm(1086324736) -> x0 [f32] + v80 Binop { op=fne, lhs=v78, rhs=v79 } -> x0 + terminator Bz { cond=v80, target=b16, fall=b15 } (exit_acc=v80) block 15 start_pc=0 - v98 Imm(8) -> x0 - terminator Return(v98) (exit_acc=v98) + v81 Imm(8) -> x0 + terminator Return(v81) (exit_acc=v81) block 16 start_pc=0 - v99 LoadLocal { off=-22, kind=I64 } -> x0 - v100 BinopI { op=add, lhs=v79, rhs_imm=8 } -> x0 - v101 Load { addr=v79, disp=8, kind=I64 } -> x0 - v102 Imm(4609434218613702656) -> x1 - v103 FpCast { kind=F64ToF32, value=v102 } -> d0 [f32] - v104 Imm(4611686018427387904) -> x1 - v105 FpCast { kind=F64ToF32, value=v104 } -> d1 [f32] - v106 CallIndirect { target=v101, args=[v103, v105], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v107 Imm(4615063718147915776) -> x0 - v108 FpCast { kind=F32ToF64, value=v106 } -> d0 - v109 Binop { op=fne, lhs=v108, rhs=v107 } -> x0 - terminator Bz { cond=v109, target=b18, fall=b17 } (exit_acc=v109) + v82 LoadLocal { off=-22, kind=I64 } -> x0 + v83 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x0 + v84 Load { addr=v66, disp=8, kind=I64 } -> x0 + v85 Imm(1069547520) -> x7 [f32] + v86 Imm(1073741824) -> x6 [f32] + v87 CallIndirect { target=v84, args=[v85, v86], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v88 Imm(1080033280) -> x0 [f32] + v89 Binop { op=fne, lhs=v87, rhs=v88 } -> x0 + terminator Bz { cond=v89, target=b18, fall=b17 } (exit_acc=v89) block 17 start_pc=0 - v110 Imm(9) -> x0 - terminator Return(v110) (exit_acc=v110) + v90 Imm(9) -> x0 + terminator Return(v90) (exit_acc=v90) block 18 start_pc=0 - v111 Imm(0) -> x0 - terminator Return(v111) (exit_acc=v111) + v91 Imm(0) -> x0 + terminator Return(v91) (exit_acc=v91) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_return.ssa b/tests/snapshots/ssa/fn_ptr_float_return.ssa index cccfbf012..e2474327c 100644 --- a/tests/snapshots/ssa/fn_ptr_float_return.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_return.ssa @@ -4,9 +4,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4612811918334230528) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - terminator Return(v2) (exit_acc=v2) + v1 Imm(1075838976) -> x0 [f32] + terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=f_int fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -17,9 +16,9 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 FpCast { kind=IntToFp, value=v1 } -> d0 - v5 Imm(4602678819172646912) -> x0 - v6 Binop { op=fmul, lhs=v4, rhs=v5 } -> d0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] + v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] + v6 Imm(1056964608) -> x0 [f32] + v7 Binop { op=fmul, lhs=v5, rhs=v6 } -> d0 [f32] terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=f_double @@ -57,64 +56,60 @@ fn ent_pc=4 n_params=0 variadic=false locals=5 v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=I64 } -> x0 v4 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v5 Imm(4612811918334230528) -> x0 - v6 FpCast { kind=F32ToF64, value=v4 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v5 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Imm(1075838976) -> x0 [f32] + v6 Binop { op=fne, lhs=v4, rhs=v5 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 2 start_pc=0 - v9 ImmCode(ent_pc=1) -> x0 - v10 Imm(0) -> x1 - v11 Imm(10) -> x7 - v12 LoadLocal { off=-2, kind=I64 } -> x1 - v13 CallIndirect { target=v9, args=[v11], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v14 Imm(4617315517961601024) -> x0 - v15 FpCast { kind=F32ToF64, value=v13 } -> d0 - v16 Binop { op=fne, lhs=v15, rhs=v14 } -> x0 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + v8 ImmCode(ent_pc=1) -> x0 + v9 Imm(0) -> x1 + v10 Imm(10) -> x7 + v11 LoadLocal { off=-2, kind=I64 } -> x1 + v12 CallIndirect { target=v8, args=[v10], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v13 Imm(1084227584) -> x0 [f32] + v14 Binop { op=fne, lhs=v12, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v18 ImmCode(ent_pc=2) -> x0 - v19 Imm(0) -> x1 - v20 Imm(4611686018427387904) -> x7 - v21 LoadLocal { off=-3, kind=I64 } -> x1 - v22 CallIndirect { target=v18, args=[v20], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v23 Imm(4613937818241073152) -> x0 - v24 FpCast { kind=F32ToF64, value=v22 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) + v16 ImmCode(ent_pc=2) -> x0 + v17 Imm(0) -> x1 + v18 Imm(4611686018427387904) -> x7 + v19 LoadLocal { off=-3, kind=I64 } -> x1 + v20 CallIndirect { target=v16, args=[v18], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v21 Imm(1077936128) -> x0 [f32] + v22 Binop { op=fne, lhs=v20, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) block 5 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) + v23 Imm(3) -> x0 + terminator Return(v23) (exit_acc=v23) block 6 start_pc=0 - v27 LoadLocal { off=-1, kind=I64 } -> x0 - v28 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v29 Imm(4612811918334230528) -> x0 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fne, lhs=v30, rhs=v29 } -> x0 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) + v24 LoadLocal { off=-1, kind=I64 } -> x0 + v25 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v26 Imm(1075838976) -> x0 [f32] + v27 Binop { op=fne, lhs=v25, rhs=v26 } -> x0 + terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) block 7 start_pc=0 - v32 Imm(4) -> x0 - terminator Return(v32) (exit_acc=v32) + v28 Imm(4) -> x0 + terminator Return(v28) (exit_acc=v28) block 8 start_pc=0 - v33 ImmCode(ent_pc=3) -> x0 - v34 Imm(0) -> x1 - v35 Imm(8) -> x7 - v36 LoadLocal { off=-4, kind=I64 } -> x1 - v37 CallIndirect { target=v33, args=[v35], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v38 Imm(4611686018427387904) -> x0 - v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 - terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) + v29 ImmCode(ent_pc=3) -> x0 + v30 Imm(0) -> x1 + v31 Imm(8) -> x7 + v32 LoadLocal { off=-4, kind=I64 } -> x1 + v33 CallIndirect { target=v29, args=[v31], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v34 Imm(4611686018427387904) -> x0 + v35 Binop { op=fne, lhs=v33, rhs=v34 } -> x0 + terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) block 9 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v36 Imm(5) -> x0 + terminator Return(v36) (exit_acc=v36) block 10 start_pc=0 - v41 Imm(0) -> x0 - terminator Return(v41) (exit_acc=v41) + v37 Imm(0) -> x0 + terminator Return(v37) (exit_acc=v37) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_multi_deref.ssa b/tests/snapshots/ssa/fn_ptr_multi_deref.ssa index 4868e7980..c18ba42f6 100644 --- a/tests/snapshots/ssa/fn_ptr_multi_deref.ssa +++ b/tests/snapshots/ssa/fn_ptr_multi_deref.ssa @@ -21,20 +21,17 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(3) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=5 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(3) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 Imm(3) -> x0 + v6 Imm(0) -> x0 + v7 Imm(5) -> x0 + v8 Imm(21474836480) -> x0 + v9 Imm(5) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 ImmCode(ent_pc=0) -> x0 v13 Imm(0) -> x1 v14 ImmCode(ent_pc=0) -> x3 @@ -46,11 +43,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x1 v21 Extend { value=v19, kind=I32 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=9 } -> x0 - terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) - block 3 start_pc=0 + terminator Bz { cond=v22, target=b3, fall=b2 } (exit_acc=v22) + block 2 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) - block 4 start_pc=0 + block 3 start_pc=0 v24 Imm(6) -> x7 v25 Imm(7) -> x6 v26 LoadLocal { off=-5, kind=I64 } -> x0 @@ -58,11 +55,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 v29 Extend { value=v27, kind=I32 } -> x0 v30 BinopI { op=ne, lhs=v29, rhs_imm=13 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) - block 5 start_pc=0 + terminator Bz { cond=v30, target=b5, fall=b4 } (exit_acc=v30) + block 4 start_pc=0 v31 Imm(3) -> x0 terminator Return(v31) (exit_acc=v31) - block 6 start_pc=0 + block 5 start_pc=0 v32 LocalAddr(-13) -> x0 v33 Imm(0) -> x1 v34 LocalAddr(-13) -> x1 @@ -77,23 +74,26 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v43 LoadLocal { off=-14, kind=I64 } -> x1 v44 Load { addr=v32, disp=0, kind=I32 } -> x1 v45 BinopI { op=ne, lhs=v44, rhs_imm=10 } -> x1 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) - block 7 start_pc=0 + terminator Bz { cond=v45, target=b7, fall=b6 } (exit_acc=v45) + block 6 start_pc=0 v46 Imm(4) -> x0 terminator Return(v46) (exit_acc=v46) - block 8 start_pc=0 + block 7 start_pc=0 v47 LoadLocal { off=-14, kind=I64 } -> x1 v48 Imm(8) -> x1 v49 BinopI { op=add, lhs=v32, rhs_imm=8 } -> x1 v50 Load { addr=v32, disp=8, kind=I32 } -> x0 v51 BinopI { op=ne, lhs=v50, rhs_imm=30 } -> x0 - terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) - block 9 start_pc=0 + terminator Bz { cond=v51, target=b9, fall=b8 } (exit_acc=v51) + block 8 start_pc=0 v52 Imm(5) -> x0 terminator Return(v52) (exit_acc=v52) - block 10 start_pc=0 + block 9 start_pc=0 v53 Imm(0) -> x0 terminator Return(v53) (exit_acc=v53) + block 10 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_ternary_call_return.ssa b/tests/snapshots/ssa/fn_ptr_ternary_call_return.ssa index e19c728c9..51265ce80 100644 --- a/tests/snapshots/ssa/fn_ptr_ternary_call_return.ssa +++ b/tests/snapshots/ssa/fn_ptr_ternary_call_return.ssa @@ -55,60 +55,60 @@ fn ent_pc=5 n_params=0 variadic=false locals=13 block 1 start_pc=0 v6 ImmCode(ent_pc=1) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 ImmCode(ent_pc=2) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v8], kind=I64 } -> x1 + v10 Phi { incoming=[b1:v6, b9:v8], kind=I64 } -> x1 v11 LoadLocal { off=-12, kind=I64 } -> x0 v12 LoadLocal { off=-1, kind=I64 } -> x0 v13 CallIndirect { target=v10, args=[v1], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x13 v14 Imm(0) -> x0 v15 LoadLocal { off=-2, kind=I32 } -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 4 start_pc=0 + terminator Jmp(b3) (exit_acc=v3) + block 3 start_pc=0 v16 ImmCode(ent_pc=3) -> x1 v17 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v16) - block 5 start_pc=0 - v18 ImmCode(ent_pc=4) -> x1 - v19 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v18) - block 6 start_pc=0 - v20 Phi { incoming=[b4:v16, b5:v18], kind=I64 } -> x1 + terminator Jmp(b4) (exit_acc=v16) + block 4 start_pc=0 + v20 Phi { incoming=[b3:v16, b10:v18], kind=I64 } -> x1 v21 LoadLocal { off=-13, kind=I64 } -> x0 v22 Imm(78187493520) -> x7 - v23 CallIndirect { target=v20, args=[v22], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 + v23 CallIndirect { target=v20, args=[v22], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x2 v24 Imm(0) -> x0 v25 LoadLocal { off=-3, kind=I64 } -> x0 v26 LoadLocal { off=-1, kind=I64 } -> x0 v27 Binop { op=ne, lhs=v13, rhs=v1 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) - block 7 start_pc=0 + terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + block 5 start_pc=0 v28 ImmData(36) -> x7 v29 LoadLocal { off=-3, kind=I64 } -> x0 v30 CallExt { binding_idx=0, args=[v28, v13], fp_arg_mask=0x0 } -> x0 v31 Imm(1) -> x0 terminator Return(v31) (exit_acc=v31) - block 8 start_pc=0 + block 6 start_pc=0 v32 LoadLocal { off=-6, kind=I64 } -> x0 v33 BinopI { op=ne, lhs=v23, rhs_imm=78187493521 } -> x0 - terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) - block 9 start_pc=0 + terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) + block 7 start_pc=0 v34 ImmData(47) -> x7 v35 LoadLocal { off=-6, kind=I64 } -> x0 v36 CallExt { binding_idx=0, args=[v34, v23], fp_arg_mask=0x0 } -> x0 v37 Imm(2) -> x0 terminator Return(v37) (exit_acc=v37) - block 10 start_pc=0 + block 8 start_pc=0 v38 ImmData(59) -> x7 v39 LoadLocal { off=-3, kind=I64 } -> x0 v40 LoadLocal { off=-6, kind=I64 } -> x0 v41 CallExt { binding_idx=0, args=[v38, v13, v23], fp_arg_mask=0x0 } -> x0 v42 Imm(0) -> x0 terminator Return(v42) (exit_acc=v42) + block 9 start_pc=0 + v8 ImmCode(ent_pc=2) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) + block 10 start_pc=0 + v18 ImmCode(ent_pc=4) -> x1 + v19 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v18) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_returning_fn_ptr.ssa b/tests/snapshots/ssa/fn_returning_fn_ptr.ssa index dd1281550..eff751fa9 100644 --- a/tests/snapshots/ssa/fn_returning_fn_ptr.ssa +++ b/tests/snapshots/ssa/fn_returning_fn_ptr.ssa @@ -23,19 +23,19 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 - terminator Bz { cond=v1, target=b2, fall=b1 } (exit_acc=v1) + terminator Bz { cond=v1, target=b3, fall=b1 } (exit_acc=v1) block 1 start_pc=0 v4 ImmCode(ent_pc=0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v4) + terminator Jmp(b2) (exit_acc=v4) block 2 start_pc=0 - v6 Imm(0) -> x1 - v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) - block 3 start_pc=0 - v8 Phi { incoming=[b1:v4, b2:v6], kind=I64 } -> x1 + v8 Phi { incoming=[b1:v4, b3:v6], kind=I64 } -> x1 v9 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v8) (exit_acc=v8) + block 3 start_pc=0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=9 diff --git a/tests/snapshots/ssa/fn_type_typedef_cast.ssa b/tests/snapshots/ssa/fn_type_typedef_cast.ssa index 27f039aea..71075bc17 100644 --- a/tests/snapshots/ssa/fn_type_typedef_cast.ssa +++ b/tests/snapshots/ssa/fn_type_typedef_cast.ssa @@ -18,7 +18,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 v2 Imm(0) -> x1 - v3 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x1 + v3 Imm(0) -> x1 v4 Imm(0) -> x1 terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -47,8 +47,8 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 v4 Imm(0) -> x0 v5 Imm(5) -> x6 v6 StoreLocal { off=-1, value=v5, kind=I32 } -> - @@ -56,19 +56,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v8 Call { target_pc=2, args=[v7, v5], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v9 LocalAddr(-1) -> x1 v10 Binop { op=eq, lhs=v8, rhs=v9 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + terminator Bz { cond=v10, target=b3, fall=b1 } (exit_acc=v10) block 1 start_pc=0 v11 Imm(0) -> x1 v12 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v11) + terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v13 Imm(1) -> x1 - v14 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v13) - block 3 start_pc=0 - v15 Phi { incoming=[b1:v11, b2:v13], kind=I64 } -> x1 + v15 Phi { incoming=[b1:v11, b3:v13], kind=I64 } -> x1 v16 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v15) (exit_acc=v15) + block 3 start_pc=0 + v13 Imm(1) -> x1 + v14 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_type_typedef_field.ssa b/tests/snapshots/ssa/fn_type_typedef_field.ssa index 587f33f73..409dff597 100644 --- a/tests/snapshots/ssa/fn_type_typedef_field.ssa +++ b/tests/snapshots/ssa/fn_type_typedef_field.ssa @@ -41,18 +41,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v12 Mcpy { dst=v6, src=v11, size=16 } -> x0 v13 LocalAddr(-4) -> x0 v14 Load { addr=v13, disp=0, kind=I64 } -> x0 - v15 BinopI { op=ne, lhs=v14, rhs_imm=7 } -> x12 + v15 BinopI { op=ne, lhs=v14, rhs_imm=7 } -> x1 v16 Imm(0) -> x0 - terminator Bnz { cond=v15, target=b9, fall=b1 } (exit_acc=v15) + terminator Bnz { cond=v15, target=b10, fall=b1 } (exit_acc=v15) block 1 start_pc=0 v17 LocalAddr(-4) -> x0 v18 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x1 v19 Load { addr=v17, disp=8, kind=I64 } -> x0 - v20 BinopI { op=ne, lhs=v19, rhs_imm=14 } -> x12 + v20 BinopI { op=ne, lhs=v19, rhs_imm=14 } -> x1 v21 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 - v22 Phi { incoming=[b9:v15, b1:v20], kind=I64 } -> x12 + v22 Phi { incoming=[b10:v15, b1:v20], kind=I64 } -> x1 v23 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 @@ -70,7 +70,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v33 Load { addr=v32, disp=0, kind=I64 } -> x0 v34 BinopI { op=ne, lhs=v33, rhs_imm=5 } -> x1 v35 Imm(0) -> x0 - terminator Bnz { cond=v34, target=b10, fall=b5 } (exit_acc=v34) + terminator Bnz { cond=v34, target=b9, fall=b5 } (exit_acc=v34) block 5 start_pc=0 v36 LocalAddr(-1) -> x0 v37 Load { addr=v36, disp=0, kind=I64 } -> x0 @@ -83,7 +83,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v44 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v43) block 6 start_pc=0 - v45 Phi { incoming=[b10:v34, b5:v43], kind=I64 } -> x1 + v45 Phi { incoming=[b9:v34, b5:v43], kind=I64 } -> x1 v46 LoadLocal { off=-14, kind=I64 } -> x0 terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) block 7 start_pc=0 @@ -93,9 +93,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v48 Imm(0) -> x0 terminator Return(v48) (exit_acc=v48) block 9 start_pc=0 - terminator Jmp(b2) - block 10 start_pc=0 terminator Jmp(b6) + block 10 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_type_typedef_local.ssa b/tests/snapshots/ssa/fn_type_typedef_local.ssa index 43531948a..ce0640b90 100644 --- a/tests/snapshots/ssa/fn_type_typedef_local.ssa +++ b/tests/snapshots/ssa/fn_type_typedef_local.ssa @@ -24,7 +24,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=17 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ImmCode(ent_pc=0) -> x3 @@ -37,18 +37,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=17 v8 Mcpy { dst=v7, src=v6, size=16 } -> x0 v9 LocalAddr(-3) -> x0 v10 Load { addr=v9, disp=0, kind=I64 } -> x0 - v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x12 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x1 v12 Imm(0) -> x0 terminator Bnz { cond=v11, target=b11, fall=b1 } (exit_acc=v11) block 1 start_pc=0 v13 LocalAddr(-3) -> x0 v14 BinopI { op=add, lhs=v13, rhs_imm=8 } -> x1 v15 Load { addr=v13, disp=8, kind=I64 } -> x0 - v16 BinopI { op=ne, lhs=v15, rhs_imm=14 } -> x12 + v16 BinopI { op=ne, lhs=v15, rhs_imm=14 } -> x1 v17 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v18 Phi { incoming=[b11:v11, b1:v16], kind=I64 } -> x12 + v18 Phi { incoming=[b11:v11, b1:v16], kind=I64 } -> x1 v19 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 diff --git a/tests/snapshots/ssa/fnptr_typedef_return_proto.ssa b/tests/snapshots/ssa/fnptr_typedef_return_proto.ssa index c89eb4cfa..7bd264622 100644 --- a/tests/snapshots/ssa/fnptr_typedef_return_proto.ssa +++ b/tests/snapshots/ssa/fnptr_typedef_return_proto.ssa @@ -21,9 +21,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 + v2 Imm(7) -> x0 + v3 Imm(0) -> x0 + v4 Imm(7) -> x0 v5 ImmCode(ent_pc=0) -> x0 terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -45,9 +45,9 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 + v2 Imm(7) -> x0 + v3 Imm(0) -> x0 + v4 Imm(7) -> x0 v5 ImmCode(ent_pc=0) -> x0 v6 Imm(0) -> x1 v7 Imm(20) -> x7 @@ -57,19 +57,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x1 v12 Extend { value=v10, kind=I32 } -> x0 v13 BinopI { op=eq, lhs=v12, rhs_imm=42 } -> x0 - terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) + terminator Bz { cond=v13, target=b3, fall=b1 } (exit_acc=v13) block 1 start_pc=0 v14 Imm(0) -> x1 v15 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v14) + terminator Jmp(b2) (exit_acc=v14) block 2 start_pc=0 - v16 Imm(1) -> x1 - v17 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v16) - block 3 start_pc=0 - v18 Phi { incoming=[b1:v14, b2:v16], kind=I64 } -> x1 + v18 Phi { incoming=[b1:v14, b3:v16], kind=I64 } -> x1 v19 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v18) (exit_acc=v18) + block 3 start_pc=0 + v16 Imm(1) -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/for_init_decl_in_loop.ssa b/tests/snapshots/ssa/for_init_decl_in_loop.ssa index c5941b4d4..ade03b0f6 100644 --- a/tests/snapshots/ssa/for_init_decl_in_loop.ssa +++ b/tests/snapshots/ssa/for_init_decl_in_loop.ssa @@ -8,52 +8,303 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v2 Imm(0) -> x0 v3 Imm(1) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b4) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v3, b2:v10], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x2 - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=5 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v12 Imm(0) -> x6 + v13 Imm(0) -> x7 + terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + v15 Imm(0) -> x6 + v16 Imm(1) -> x6 + v17 Extend { value=v6, kind=I32 } -> x6 + v18 Extend { value=v5, kind=I32 } -> x6 + v19 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x7 + v21 Extend { value=v19, kind=I32 } -> x7 + v22 Imm(0) -> x7 + v23 BinopI { op=add, lhs=v19, rhs_imm=0 } -> x6 + v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x7 + v25 Extend { value=v23, kind=I32 } -> x7 + v26 Binop { op=add, lhs=v6, rhs=v23 } -> x2 + v27 Imm(0) -> x6 + v28 Extend { value=v26, kind=I32 } -> x6 + v29 Imm(0) -> x6 + v30 Imm(1) -> x6 + v31 Imm(0) -> x6 + v32 Imm(1) -> x6 + v33 Imm(1) -> x6 + v34 Extend { value=v26, kind=I32 } -> x6 + v35 Extend { value=v5, kind=I32 } -> x6 + v36 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x7 + v38 Extend { value=v36, kind=I32 } -> x7 + v39 Imm(1) -> x7 + v40 BinopI { op=add, lhs=v36, rhs_imm=1 } -> x6 + v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x7 + v42 Extend { value=v40, kind=I32 } -> x7 + v43 Binop { op=add, lhs=v26, rhs=v40 } -> x2 + v44 Imm(0) -> x6 + v45 Extend { value=v43, kind=I32 } -> x6 + v46 Imm(1) -> x6 + v47 Imm(2) -> x6 + v48 Imm(0) -> x6 + v49 Imm(2) -> x6 + v50 Imm(1) -> x6 + v51 Extend { value=v43, kind=I32 } -> x6 + v52 Extend { value=v5, kind=I32 } -> x6 + v53 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v54 BinopI { op=shl, lhs=v53, rhs_imm=32 } -> x7 + v55 Extend { value=v53, kind=I32 } -> x7 + v56 Imm(2) -> x7 + v57 BinopI { op=add, lhs=v53, rhs_imm=2 } -> x6 + v58 BinopI { op=shl, lhs=v57, rhs_imm=32 } -> x7 + v59 Extend { value=v57, kind=I32 } -> x7 + v60 Binop { op=add, lhs=v43, rhs=v57 } -> x2 + v61 Imm(0) -> x6 + v62 Extend { value=v60, kind=I32 } -> x6 + v63 Imm(2) -> x6 + v64 Imm(3) -> x6 + v65 Imm(0) -> x6 + v66 Imm(3) -> x6 + v67 Imm(1) -> x6 + v68 Extend { value=v60, kind=I32 } -> x6 + v69 Extend { value=v5, kind=I32 } -> x6 + v70 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v71 BinopI { op=shl, lhs=v70, rhs_imm=32 } -> x7 + v72 Extend { value=v70, kind=I32 } -> x7 + v73 Imm(3) -> x7 + v74 BinopI { op=add, lhs=v70, rhs_imm=3 } -> x6 + v75 BinopI { op=shl, lhs=v74, rhs_imm=32 } -> x7 + v76 Extend { value=v74, kind=I32 } -> x7 + v77 Binop { op=add, lhs=v60, rhs=v74 } -> x2 + v78 Imm(0) -> x6 + v79 Extend { value=v77, kind=I32 } -> x6 + v80 Imm(3) -> x6 + v81 Imm(4) -> x6 + v82 Imm(0) -> x6 + v83 Imm(4) -> x6 + v84 Imm(1) -> x6 + v85 Extend { value=v77, kind=I32 } -> x6 + v86 Extend { value=v5, kind=I32 } -> x6 + v87 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v88 BinopI { op=shl, lhs=v87, rhs_imm=32 } -> x7 + v89 Extend { value=v87, kind=I32 } -> x7 + v90 Imm(4) -> x7 + v91 BinopI { op=add, lhs=v87, rhs_imm=4 } -> x6 + v92 BinopI { op=shl, lhs=v91, rhs_imm=32 } -> x7 + v93 Extend { value=v91, kind=I32 } -> x7 + v94 Binop { op=add, lhs=v77, rhs=v91 } -> x2 + v95 Imm(0) -> x6 + v96 Extend { value=v94, kind=I32 } -> x6 + v97 Imm(4) -> x6 + v98 Imm(5) -> x6 + v99 Imm(0) -> x6 + v100 Imm(5) -> x6 + v101 Imm(1) -> x6 + v102 Extend { value=v94, kind=I32 } -> x6 + v103 Extend { value=v5, kind=I32 } -> x6 + v104 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v105 BinopI { op=shl, lhs=v104, rhs_imm=32 } -> x7 + v106 Extend { value=v104, kind=I32 } -> x7 + v107 Imm(5) -> x7 + v108 BinopI { op=add, lhs=v104, rhs_imm=5 } -> x6 + v109 BinopI { op=shl, lhs=v108, rhs_imm=32 } -> x7 + v110 Extend { value=v108, kind=I32 } -> x7 + v111 Binop { op=add, lhs=v94, rhs=v108 } -> x2 + v112 Imm(0) -> x6 + v113 Extend { value=v111, kind=I32 } -> x6 + v114 Imm(5) -> x6 + v115 Imm(6) -> x6 + v116 Imm(0) -> x6 + v117 Imm(6) -> x6 + v118 Imm(1) -> x6 + v119 Extend { value=v111, kind=I32 } -> x6 + v120 Extend { value=v5, kind=I32 } -> x6 + v121 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v122 BinopI { op=shl, lhs=v121, rhs_imm=32 } -> x7 + v123 Extend { value=v121, kind=I32 } -> x7 + v124 Imm(6) -> x7 + v125 BinopI { op=add, lhs=v121, rhs_imm=6 } -> x6 + v126 BinopI { op=shl, lhs=v125, rhs_imm=32 } -> x7 + v127 Extend { value=v125, kind=I32 } -> x7 + v128 Binop { op=add, lhs=v111, rhs=v125 } -> x2 + v129 Imm(0) -> x6 + v130 Extend { value=v128, kind=I32 } -> x6 + v131 Imm(6) -> x6 + v132 Imm(7) -> x6 + v133 Imm(0) -> x6 + v134 Imm(7) -> x6 + v135 Imm(1) -> x6 + v136 Extend { value=v128, kind=I32 } -> x6 + v137 Extend { value=v5, kind=I32 } -> x6 + v138 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v139 BinopI { op=shl, lhs=v138, rhs_imm=32 } -> x7 + v140 Extend { value=v138, kind=I32 } -> x7 + v141 Imm(7) -> x7 + v142 BinopI { op=add, lhs=v138, rhs_imm=7 } -> x6 + v143 BinopI { op=shl, lhs=v142, rhs_imm=32 } -> x7 + v144 Extend { value=v142, kind=I32 } -> x7 + v145 Binop { op=add, lhs=v128, rhs=v142 } -> x2 + v146 Imm(0) -> x6 + v147 Extend { value=v145, kind=I32 } -> x6 + v148 Imm(7) -> x6 + v149 Imm(8) -> x6 + v150 Imm(0) -> x6 + v151 Imm(8) -> x6 + v152 Imm(1) -> x6 + v153 Extend { value=v145, kind=I32 } -> x6 + v154 Extend { value=v5, kind=I32 } -> x6 + v155 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v156 BinopI { op=shl, lhs=v155, rhs_imm=32 } -> x7 + v157 Extend { value=v155, kind=I32 } -> x7 + v158 Imm(8) -> x7 + v159 BinopI { op=add, lhs=v155, rhs_imm=8 } -> x6 + v160 BinopI { op=shl, lhs=v159, rhs_imm=32 } -> x7 + v161 Extend { value=v159, kind=I32 } -> x7 + v162 Binop { op=add, lhs=v145, rhs=v159 } -> x2 + v163 Imm(0) -> x6 + v164 Extend { value=v162, kind=I32 } -> x6 + v165 Imm(8) -> x6 + v166 Imm(9) -> x6 + v167 Imm(0) -> x6 + v168 Imm(9) -> x6 + v169 Imm(1) -> x6 + v170 Extend { value=v162, kind=I32 } -> x6 + v171 Extend { value=v5, kind=I32 } -> x6 + v172 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v173 BinopI { op=shl, lhs=v172, rhs_imm=32 } -> x7 + v174 Extend { value=v172, kind=I32 } -> x7 + v175 Imm(9) -> x7 + v176 BinopI { op=add, lhs=v172, rhs_imm=9 } -> x6 + v177 BinopI { op=shl, lhs=v176, rhs_imm=32 } -> x7 + v178 Extend { value=v176, kind=I32 } -> x7 + v179 Binop { op=add, lhs=v162, rhs=v176 } -> x2 + v180 Imm(0) -> x6 + v181 Extend { value=v179, kind=I32 } -> x6 + v182 Imm(9) -> x6 + v183 Imm(10) -> x6 + v184 Imm(0) -> x6 + v185 Imm(10) -> x6 + v186 Imm(1) -> x6 + v187 Extend { value=v179, kind=I32 } -> x6 + v188 Extend { value=v5, kind=I32 } -> x6 + v189 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v190 BinopI { op=shl, lhs=v189, rhs_imm=32 } -> x7 + v191 Extend { value=v189, kind=I32 } -> x7 + v192 Imm(10) -> x7 + v193 BinopI { op=add, lhs=v189, rhs_imm=10 } -> x6 + v194 BinopI { op=shl, lhs=v193, rhs_imm=32 } -> x7 + v195 Extend { value=v193, kind=I32 } -> x7 + v196 Binop { op=add, lhs=v179, rhs=v193 } -> x2 + v197 Imm(0) -> x6 + v198 Extend { value=v196, kind=I32 } -> x6 + v199 Imm(10) -> x6 + v200 Imm(11) -> x6 + v201 Imm(0) -> x6 + v202 Imm(11) -> x6 + v203 Imm(1) -> x6 + v204 Extend { value=v196, kind=I32 } -> x6 + v205 Extend { value=v5, kind=I32 } -> x6 + v206 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v207 BinopI { op=shl, lhs=v206, rhs_imm=32 } -> x7 + v208 Extend { value=v206, kind=I32 } -> x7 + v209 Imm(11) -> x7 + v210 BinopI { op=add, lhs=v206, rhs_imm=11 } -> x6 + v211 BinopI { op=shl, lhs=v210, rhs_imm=32 } -> x7 + v212 Extend { value=v210, kind=I32 } -> x7 + v213 Binop { op=add, lhs=v196, rhs=v210 } -> x2 + v214 Imm(0) -> x6 + v215 Extend { value=v213, kind=I32 } -> x6 + v216 Imm(11) -> x6 + v217 Imm(12) -> x6 + v218 Imm(0) -> x6 + v219 Imm(12) -> x6 + v220 Imm(1) -> x6 + v221 Extend { value=v213, kind=I32 } -> x6 + v222 Extend { value=v5, kind=I32 } -> x6 + v223 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v224 BinopI { op=shl, lhs=v223, rhs_imm=32 } -> x7 + v225 Extend { value=v223, kind=I32 } -> x7 + v226 Imm(12) -> x7 + v227 BinopI { op=add, lhs=v223, rhs_imm=12 } -> x6 + v228 BinopI { op=shl, lhs=v227, rhs_imm=32 } -> x7 + v229 Extend { value=v227, kind=I32 } -> x7 + v230 Binop { op=add, lhs=v213, rhs=v227 } -> x2 + v231 Imm(0) -> x6 + v232 Extend { value=v230, kind=I32 } -> x6 + v233 Imm(12) -> x6 + v234 Imm(13) -> x6 + v235 Imm(0) -> x6 + v236 Imm(13) -> x6 + v237 Imm(1) -> x6 + v238 Extend { value=v230, kind=I32 } -> x6 + v239 Extend { value=v5, kind=I32 } -> x6 + v240 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v241 BinopI { op=shl, lhs=v240, rhs_imm=32 } -> x7 + v242 Extend { value=v240, kind=I32 } -> x7 + v243 Imm(13) -> x7 + v244 BinopI { op=add, lhs=v240, rhs_imm=13 } -> x6 + v245 BinopI { op=shl, lhs=v244, rhs_imm=32 } -> x7 + v246 Extend { value=v244, kind=I32 } -> x7 + v247 Binop { op=add, lhs=v230, rhs=v244 } -> x2 + v248 Imm(0) -> x6 + v249 Extend { value=v247, kind=I32 } -> x6 + v250 Imm(13) -> x6 + v251 Imm(14) -> x6 + v252 Imm(0) -> x6 + v253 Imm(14) -> x6 + v254 Imm(1) -> x6 + v255 Extend { value=v247, kind=I32 } -> x6 + v256 Extend { value=v5, kind=I32 } -> x6 + v257 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v258 BinopI { op=shl, lhs=v257, rhs_imm=32 } -> x7 + v259 Extend { value=v257, kind=I32 } -> x7 + v260 Imm(14) -> x7 + v261 BinopI { op=add, lhs=v257, rhs_imm=14 } -> x6 + v262 BinopI { op=shl, lhs=v261, rhs_imm=32 } -> x7 + v263 Extend { value=v261, kind=I32 } -> x7 + v264 Binop { op=add, lhs=v247, rhs=v261 } -> x2 + v265 Imm(0) -> x6 + v266 Extend { value=v264, kind=I32 } -> x6 + v267 Imm(14) -> x6 + v268 Imm(15) -> x6 + v269 Imm(0) -> x6 + v270 Imm(15) -> x6 + v271 Imm(1) -> x6 + v272 Extend { value=v264, kind=I32 } -> x6 + v273 Extend { value=v5, kind=I32 } -> x6 + v274 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x6 + v275 BinopI { op=shl, lhs=v274, rhs_imm=32 } -> x7 + v276 Extend { value=v274, kind=I32 } -> x7 + v277 Imm(15) -> x7 + v278 BinopI { op=add, lhs=v274, rhs_imm=15 } -> x6 + v279 BinopI { op=shl, lhs=v278, rhs_imm=32 } -> x7 + v280 Extend { value=v278, kind=I32 } -> x7 + v281 Binop { op=add, lhs=v264, rhs=v278 } -> x2 + v282 Imm(0) -> x6 + v283 Extend { value=v281, kind=I32 } -> x6 + v284 Imm(15) -> x6 + v285 Imm(16) -> x6 + v286 Imm(0) -> x6 + v287 Imm(16) -> x6 + v288 Imm(0) -> x6 + terminator Jmp(b3) (exit_acc=v288) block 3 start_pc=0 - v12 Imm(0) -> x6 - v13 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v12) + v9 Extend { value=v5, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v10) block 4 start_pc=0 + v5 Phi { incoming=[b0:v3, b3:v10], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b3:v281], kind=I64 } -> x2 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=5 } -> x6 + terminator Bnz { cond=v8, target=b1, fall=b5 } (exit_acc=v8) + block 5 start_pc=0 v14 Extend { value=v6, kind=I32 } -> x0 terminator Return(v14) (exit_acc=v14) - block 5 start_pc=0 - v15 Phi { incoming=[b3:v12, b6:v20], kind=I64 } -> x6 - v16 Phi { incoming=[b3:v6, b6:v31], kind=I64 } -> x2 - v17 Extend { value=v15, kind=I32 } -> x0 - v18 BinopI { op=lt, lhs=v17, rhs_imm=16 } -> x0 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) block 6 start_pc=0 - v19 Extend { value=v15, kind=I32 } -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x6 - v21 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v20) - block 7 start_pc=0 - v22 Extend { value=v16, kind=I32 } -> x0 - v23 Extend { value=v5, kind=I32 } -> x0 - v24 BinopI { op=mul, lhs=v5, rhs_imm=100 } -> x0 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x7 - v26 Extend { value=v24, kind=I32 } -> x7 - v27 Extend { value=v15, kind=I32 } -> x7 - v28 Binop { op=add, lhs=v24, rhs=v15 } -> x0 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x7 - v30 Extend { value=v28, kind=I32 } -> x7 - v31 Binop { op=add, lhs=v16, rhs=v28 } -> x2 - v32 Imm(0) -> x0 - v33 Extend { value=v31, kind=I32 } -> x0 - terminator Jmp(b6) (exit_acc=v33) - block 8 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=0 diff --git a/tests/snapshots/ssa/for_init_declaration.ssa b/tests/snapshots/ssa/for_init_declaration.ssa index 400408437..67bd7a023 100644 --- a/tests/snapshots/ssa/for_init_declaration.ssa +++ b/tests/snapshots/ssa/for_init_declaration.ssa @@ -4,73 +4,227 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x0 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(1) -> x0 + v22 Imm(2) -> x0 + v23 Imm(0) -> x0 + v24 Imm(2) -> x0 + v25 Imm(1) -> x0 + v26 Imm(1) -> x0 + v27 Imm(2) -> x0 + v28 Imm(3) -> x0 + v29 Imm(0) -> x0 + v30 Imm(3) -> x0 + v31 Imm(2) -> x0 + v32 Imm(3) -> x0 + v33 Imm(0) -> x0 + v34 Imm(3) -> x0 + v35 Imm(1) -> x0 + v36 Imm(3) -> x0 + v37 Imm(3) -> x0 + v38 Imm(6) -> x0 + v39 Imm(0) -> x0 + v40 Imm(6) -> x0 + v41 Imm(3) -> x0 + v42 Imm(4) -> x0 + v43 Imm(0) -> x0 + v44 Imm(4) -> x0 + v45 Imm(1) -> x0 + v46 Imm(6) -> x0 + v47 Imm(4) -> x0 + v48 Imm(10) -> x0 + v49 Imm(0) -> x0 + v50 Imm(10) -> x0 + v51 Imm(4) -> x0 + v52 Imm(5) -> x0 + v53 Imm(0) -> x0 + v54 Imm(5) -> x0 + v55 Imm(1) -> x0 + v56 Imm(10) -> x0 + v57 Imm(5) -> x0 + v58 Imm(15) -> x0 + v59 Imm(0) -> x0 + v60 Imm(15) -> x0 + v61 Imm(5) -> x0 + v62 Imm(6) -> x0 + v63 Imm(0) -> x0 + v64 Imm(6) -> x0 + v65 Imm(1) -> x0 + v66 Imm(15) -> x0 + v67 Imm(6) -> x0 + v68 Imm(21) -> x0 + v69 Imm(0) -> x0 + v70 Imm(21) -> x0 + v71 Imm(6) -> x0 + v72 Imm(7) -> x0 + v73 Imm(0) -> x0 + v74 Imm(7) -> x0 + v75 Imm(1) -> x0 + v76 Imm(21) -> x0 + v77 Imm(7) -> x0 + v78 Imm(28) -> x0 + v79 Imm(0) -> x0 + v80 Imm(28) -> x0 + v81 Imm(7) -> x0 + v82 Imm(8) -> x0 + v83 Imm(0) -> x0 + v84 Imm(8) -> x0 + v85 Imm(1) -> x0 + v86 Imm(28) -> x0 + v87 Imm(8) -> x0 + v88 Imm(36) -> x0 + v89 Imm(0) -> x0 + v90 Imm(36) -> x0 + v91 Imm(8) -> x0 + v92 Imm(9) -> x0 + v93 Imm(0) -> x0 + v94 Imm(9) -> x0 + v95 Imm(1) -> x0 + v96 Imm(36) -> x0 + v97 Imm(9) -> x0 + v98 Imm(45) -> x0 + v99 Imm(0) -> x0 + v100 Imm(45) -> x0 + v101 Imm(9) -> x0 + v102 Imm(10) -> x0 + v103 Imm(0) -> x0 + v104 Imm(10) -> x0 + v105 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v105) block 2 start_pc=0 - v8 Extend { value=v4, kind=I32 } -> x1 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 - v11 Extend { value=v5, kind=I32 } -> x2 - v12 Extend { value=v4, kind=I32 } -> x2 - v13 Binop { op=add, lhs=v5, rhs=v4 } -> x0 - v14 Imm(0) -> x2 - v15 Extend { value=v13, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v15) - block 4 start_pc=0 - v16 Extend { value=v5, kind=I32 } -> x0 - terminator Return(v16) (exit_acc=v16) + v106 Imm(45) -> x0 + terminator Return(v106) (exit_acc=v106) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=multi_decl fn ent_pc=2 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x2 + v1 Imm(0) -> x0 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - v4 Imm(10) -> x1 - v5 Imm(0) -> x0 + v4 Imm(10) -> x0 + v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v4, b2:v16], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x2 - v8 Phi { incoming=[b0:v1, b2:v24], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x6 - v10 Extend { value=v6, kind=I32 } -> x7 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v6 Imm(0) -> x0 + v7 Imm(10) -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(10) -> x0 + v12 Imm(10) -> x0 + v13 Imm(42949672960) -> x0 + v14 Imm(10) -> x0 + v15 Imm(10) -> x0 + v16 Imm(0) -> x0 + v17 Imm(10) -> x0 + v18 Imm(0) -> x0 + v19 Imm(1) -> x0 + v20 Imm(0) -> x0 + v21 Imm(10) -> x0 + v22 Imm(9) -> x0 + v23 Imm(0) -> x0 + v24 Imm(1) -> x0 + v25 Imm(9) -> x0 + v26 Imm(1) -> x0 + v27 Imm(10) -> x0 + v28 Imm(1) -> x0 + v29 Imm(9) -> x0 + v30 Imm(10) -> x0 + v31 Imm(42949672960) -> x0 + v32 Imm(10) -> x0 + v33 Imm(20) -> x0 + v34 Imm(0) -> x0 + v35 Imm(20) -> x0 + v36 Imm(1) -> x0 + v37 Imm(2) -> x0 + v38 Imm(0) -> x0 + v39 Imm(9) -> x0 + v40 Imm(8) -> x0 + v41 Imm(0) -> x0 + v42 Imm(2) -> x0 + v43 Imm(8) -> x0 + v44 Imm(1) -> x0 + v45 Imm(20) -> x0 + v46 Imm(2) -> x0 + v47 Imm(8) -> x0 + v48 Imm(10) -> x0 + v49 Imm(42949672960) -> x0 + v50 Imm(10) -> x0 + v51 Imm(30) -> x0 + v52 Imm(0) -> x0 + v53 Imm(30) -> x0 + v54 Imm(2) -> x0 + v55 Imm(3) -> x0 + v56 Imm(0) -> x0 + v57 Imm(8) -> x0 + v58 Imm(7) -> x0 + v59 Imm(0) -> x0 + v60 Imm(3) -> x0 + v61 Imm(7) -> x0 + v62 Imm(1) -> x0 + v63 Imm(30) -> x0 + v64 Imm(3) -> x0 + v65 Imm(7) -> x0 + v66 Imm(10) -> x0 + v67 Imm(42949672960) -> x0 + v68 Imm(10) -> x0 + v69 Imm(40) -> x0 + v70 Imm(0) -> x0 + v71 Imm(40) -> x0 + v72 Imm(3) -> x0 + v73 Imm(4) -> x0 + v74 Imm(0) -> x0 + v75 Imm(7) -> x0 + v76 Imm(6) -> x0 + v77 Imm(0) -> x0 + v78 Imm(4) -> x0 + v79 Imm(6) -> x0 + v80 Imm(1) -> x0 + v81 Imm(40) -> x0 + v82 Imm(4) -> x0 + v83 Imm(6) -> x0 + v84 Imm(10) -> x0 + v85 Imm(42949672960) -> x0 + v86 Imm(10) -> x0 + v87 Imm(50) -> x0 + v88 Imm(0) -> x0 + v89 Imm(50) -> x0 + v90 Imm(4) -> x0 + v91 Imm(5) -> x0 + v92 Imm(0) -> x0 + v93 Imm(6) -> x0 + v94 Imm(5) -> x0 + v95 Imm(0) -> x0 + v96 Imm(5) -> x0 + v97 Imm(5) -> x0 + v98 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v98) block 2 start_pc=0 - v12 Extend { value=v7, kind=I32 } -> x6 - v13 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x2 - v14 Imm(0) -> x6 - v15 Extend { value=v6, kind=I32 } -> x1 - v16 BinopI { op=add, lhs=v15, rhs_imm=-1 } -> x1 - v17 Imm(0) -> x6 - terminator Jmp(b1) (exit_acc=v16) - block 3 start_pc=0 - v18 Extend { value=v8, kind=I32 } -> x6 - v19 Extend { value=v7, kind=I32 } -> x6 - v20 Extend { value=v6, kind=I32 } -> x6 - v21 Binop { op=add, lhs=v7, rhs=v6 } -> x6 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x7 - v23 Extend { value=v21, kind=I32 } -> x7 - v24 Binop { op=add, lhs=v8, rhs=v21 } -> x0 - v25 Imm(0) -> x6 - v26 Extend { value=v24, kind=I32 } -> x6 - terminator Jmp(b2) (exit_acc=v26) - block 4 start_pc=0 - v27 Extend { value=v8, kind=I32 } -> x0 - terminator Return(v27) (exit_acc=v27) + v99 Imm(50) -> x0 + terminator Return(v99) (exit_acc=v99) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=shadowing fn ent_pc=3 n_params=0 variadic=false locals=2 @@ -79,23 +233,30 @@ fn ent_pc=3 n_params=0 variadic=false locals=2 v0 AllocaInit(0) -> - v1 Imm(42) -> x0 v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 + v3 Imm(0) -> x1 + v4 Imm(0) -> x2 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v3, b2:v9], kind=I64 } -> x2 - v6 Extend { value=v5, kind=I32 } -> x1 - v7 BinopI { op=lt, lhs=v6, rhs_imm=3 } -> x1 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v5 Imm(0) -> x1 + v6 Imm(1) -> x1 + v7 Imm(0) -> x1 + v8 Imm(1) -> x1 + v9 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(1) -> x1 + v12 Imm(1) -> x1 + v13 Imm(2) -> x1 + v14 Imm(0) -> x1 + v15 Imm(2) -> x1 + v16 Imm(1) -> x1 + v17 Imm(2) -> x1 + v18 Imm(3) -> x1 + v19 Imm(0) -> x1 + v20 Imm(3) -> x1 + v21 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 - v8 Extend { value=v5, kind=I32 } -> x1 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x2 - v10 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 - terminator Jmp(b2) - block 4 start_pc=0 - v11 LoadLocal { off=-1, kind=I32 } -> x1 + v22 LoadLocal { off=-1, kind=I32 } -> x1 terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=4 --- ; name=adjacent_fors @@ -103,53 +264,105 @@ fn ent_pc=4 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x0 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=5 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(1) -> x0 + v22 Imm(2) -> x0 + v23 Imm(0) -> x0 + v24 Imm(2) -> x0 + v25 Imm(1) -> x0 + v26 Imm(1) -> x0 + v27 Imm(2) -> x0 + v28 Imm(3) -> x0 + v29 Imm(0) -> x0 + v30 Imm(3) -> x0 + v31 Imm(2) -> x0 + v32 Imm(3) -> x0 + v33 Imm(0) -> x0 + v34 Imm(3) -> x0 + v35 Imm(1) -> x0 + v36 Imm(3) -> x0 + v37 Imm(3) -> x0 + v38 Imm(6) -> x0 + v39 Imm(0) -> x0 + v40 Imm(6) -> x0 + v41 Imm(3) -> x0 + v42 Imm(4) -> x0 + v43 Imm(0) -> x0 + v44 Imm(4) -> x0 + v45 Imm(1) -> x0 + v46 Imm(6) -> x0 + v47 Imm(4) -> x0 + v48 Imm(10) -> x0 + v49 Imm(0) -> x0 + v50 Imm(10) -> x0 + v51 Imm(4) -> x0 + v52 Imm(5) -> x0 + v53 Imm(0) -> x0 + v54 Imm(5) -> x0 + v55 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v55) block 2 start_pc=0 - v8 Extend { value=v4, kind=I32 } -> x1 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v9) + v56 Imm(10) -> x0 + v57 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v56) block 3 start_pc=0 - v11 Extend { value=v5, kind=I32 } -> x2 - v12 Extend { value=v4, kind=I32 } -> x2 - v13 Binop { op=add, lhs=v5, rhs=v4 } -> x0 - v14 Imm(0) -> x2 - v15 Extend { value=v13, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v15) + v58 Imm(10) -> x0 + v59 Imm(1) -> x0 + v60 Imm(10) -> x0 + v61 Imm(10) -> x0 + v62 Imm(20) -> x0 + v63 Imm(0) -> x0 + v64 Imm(20) -> x0 + v65 Imm(10) -> x0 + v66 Imm(11) -> x0 + v67 Imm(0) -> x0 + v68 Imm(11) -> x0 + v69 Imm(1) -> x0 + v70 Imm(20) -> x0 + v71 Imm(11) -> x0 + v72 Imm(31) -> x0 + v73 Imm(0) -> x0 + v74 Imm(31) -> x0 + v75 Imm(11) -> x0 + v76 Imm(12) -> x0 + v77 Imm(0) -> x0 + v78 Imm(12) -> x0 + v79 Imm(1) -> x0 + v80 Imm(31) -> x0 + v81 Imm(12) -> x0 + v82 Imm(43) -> x0 + v83 Imm(0) -> x0 + v84 Imm(43) -> x0 + v85 Imm(12) -> x0 + v86 Imm(13) -> x0 + v87 Imm(0) -> x0 + v88 Imm(13) -> x0 + v89 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v89) block 4 start_pc=0 - v16 Imm(10) -> x2 - v17 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v16) - block 5 start_pc=0 - v18 Phi { incoming=[b4:v16, b6:v23], kind=I64 } -> x2 - v19 Phi { incoming=[b4:v5, b6:v27], kind=I64 } -> x0 - v20 Extend { value=v18, kind=I32 } -> x1 - v21 BinopI { op=lt, lhs=v20, rhs_imm=13 } -> x1 - terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) - block 6 start_pc=0 - v22 Extend { value=v18, kind=I32 } -> x1 - v23 BinopI { op=add, lhs=v22, rhs_imm=1 } -> x2 - v24 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v23) - block 7 start_pc=0 - v25 Extend { value=v19, kind=I32 } -> x1 - v26 Extend { value=v18, kind=I32 } -> x1 - v27 Binop { op=add, lhs=v19, rhs=v18 } -> x0 - v28 Imm(0) -> x1 - v29 Extend { value=v27, kind=I32 } -> x1 - terminator Jmp(b6) (exit_acc=v29) - block 8 start_pc=0 - v30 Extend { value=v19, kind=I32 } -> x0 - terminator Return(v30) (exit_acc=v30) + v90 Imm(43) -> x0 + terminator Return(v90) (exit_acc=v90) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=struct_ptr_init fn ent_pc=5 n_params=0 variadic=false locals=2 @@ -169,22 +382,8 @@ fn ent_pc=5 n_params=0 variadic=false locals=2 v11 Store { addr=v1, disp=8, value=v5, kind=I32 } -> - v12 Imm(0) -> x1 v13 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v14 Phi { incoming=[b0:v1, b2:v22], kind=I64 } -> x1 - v15 Phi { incoming=[b0:v2, b2:v27], kind=I64 } -> x6 - v16 LoadLocal { off=-2, kind=I64 } -> x2 - v17 ImmData(56) -> x2 - v18 Imm(12) -> x2 - v19 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x2 - v20 Binop { op=lt, lhs=v14, rhs=v19 } -> x2 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) - block 2 start_pc=0 - v21 LoadLocal { off=-2, kind=I64 } -> x2 - v22 BinopI { op=add, lhs=v14, rhs_imm=4 } -> x1 - v23 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v22) - block 3 start_pc=0 v24 Extend { value=v15, kind=I32 } -> x2 v25 LoadLocal { off=-2, kind=I64 } -> x2 v26 Load { addr=v14, disp=0, kind=I32 } -> x2 @@ -192,6 +391,20 @@ fn ent_pc=5 n_params=0 variadic=false locals=2 v28 Imm(0) -> x2 v29 Extend { value=v27, kind=I32 } -> x2 terminator Jmp(b2) (exit_acc=v29) + block 2 start_pc=0 + v21 LoadLocal { off=-2, kind=I64 } -> x2 + v22 BinopI { op=add, lhs=v14, rhs_imm=4 } -> x1 + v23 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v22) + block 3 start_pc=0 + v14 Phi { incoming=[b0:v1, b2:v22], kind=I64 } -> x1 + v15 Phi { incoming=[b0:v2, b2:v27], kind=I64 } -> x6 + v16 LoadLocal { off=-2, kind=I64 } -> x2 + v17 ImmData(56) -> x2 + v18 Imm(12) -> x2 + v19 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x2 + v20 Binop { op=lt, lhs=v14, rhs=v19 } -> x2 + terminator Bnz { cond=v20, target=b1, fall=b4 } (exit_acc=v20) block 4 start_pc=0 v30 Extend { value=v15, kind=I32 } -> x0 terminator Return(v30) (exit_acc=v30) diff --git a/tests/snapshots/ssa/for_init_multiple_declarators.ssa b/tests/snapshots/ssa/for_init_multiple_declarators.ssa index b4ddc2f6c..d791a14ad 100644 --- a/tests/snapshots/ssa/for_init_multiple_declarators.ssa +++ b/tests/snapshots/ssa/for_init_multiple_declarators.ssa @@ -4,141 +4,238 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x2 + v1 Imm(0) -> x0 v2 Imm(0) -> x0 v3 Imm(0) -> x0 v4 Imm(3) -> x0 v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v1, b2:v12], kind=I64 } -> x2 - v7 Phi { incoming=[b0:v1, b2:v15], kind=I64 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x6 - v9 LoadLocal { off=-3, kind=I32 } -> x7 - v10 Binop { op=lt, lhs=v8, rhs=v4 } -> x6 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v6 Imm(0) -> x0 + v7 LoadLocal { off=-3, kind=I32 } -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + v10 Imm(1) -> x0 + v11 Imm(0) -> x0 + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 LoadLocal { off=-3, kind=I32 } -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 Imm(2) -> x0 + v20 Imm(0) -> x0 + v21 Imm(1) -> x0 + v22 Imm(2) -> x0 + v23 Imm(0) -> x0 + v24 Imm(2) -> x0 + v25 LoadLocal { off=-3, kind=I32 } -> x0 + v26 Imm(1) -> x0 + v27 Imm(2) -> x0 + v28 Imm(3) -> x0 + v29 Imm(0) -> x0 + v30 Imm(2) -> x0 + v31 Imm(3) -> x0 + v32 Imm(0) -> x0 + v33 Imm(3) -> x0 + v34 LoadLocal { off=-3, kind=I32 } -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v35) block 2 start_pc=0 - v11 Extend { value=v6, kind=I32 } -> x2 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x2 - v13 Imm(0) -> x6 - terminator Jmp(b1) (exit_acc=v12) + v36 Imm(3) -> x0 + v37 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v37) block 3 start_pc=0 - v14 Extend { value=v7, kind=I32 } -> x1 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x1 - v16 Imm(0) -> x6 - terminator Jmp(b2) (exit_acc=v15) + v39 Imm(0) -> x0 + v40 Imm(0) -> x0 + v41 Imm(0) -> x0 + v42 Imm(4) -> x0 + v43 Imm(0) -> x0 + v44 Imm(2) -> x0 + v45 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v44) block 4 start_pc=0 - v17 Extend { value=v7, kind=I32 } -> x0 - v18 BinopI { op=ne, lhs=v17, rhs_imm=3 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v46 Imm(0) -> x0 + v47 LoadLocal { off=-6, kind=I32 } -> x0 + v48 Imm(1) -> x0 + v49 Imm(0) -> x0 + v50 LoadLocal { off=-7, kind=I32 } -> x0 + v51 Imm(2) -> x0 + v52 Imm(0) -> x0 + v53 Imm(2) -> x0 + v54 Imm(0) -> x0 + v55 Imm(1) -> x0 + v56 Imm(0) -> x0 + v57 Imm(1) -> x0 + v58 LoadLocal { off=-6, kind=I32 } -> x0 + v59 Imm(1) -> x0 + v60 Imm(2) -> x0 + v61 LoadLocal { off=-7, kind=I32 } -> x0 + v62 Imm(4) -> x0 + v63 Imm(0) -> x0 + v64 Imm(4) -> x0 + v65 Imm(1) -> x0 + v66 Imm(2) -> x0 + v67 Imm(0) -> x0 + v68 Imm(2) -> x0 + v69 LoadLocal { off=-6, kind=I32 } -> x0 + v70 Imm(1) -> x0 + v71 Imm(4) -> x0 + v72 LoadLocal { off=-7, kind=I32 } -> x0 + v73 Imm(6) -> x0 + v74 Imm(0) -> x0 + v75 Imm(6) -> x0 + v76 Imm(2) -> x0 + v77 Imm(3) -> x0 + v78 Imm(0) -> x0 + v79 Imm(3) -> x0 + v80 LoadLocal { off=-6, kind=I32 } -> x0 + v81 Imm(1) -> x0 + v82 Imm(6) -> x0 + v83 LoadLocal { off=-7, kind=I32 } -> x0 + v84 Imm(8) -> x0 + v85 Imm(0) -> x0 + v86 Imm(8) -> x0 + v87 Imm(3) -> x0 + v88 Imm(4) -> x0 + v89 Imm(0) -> x0 + v90 Imm(4) -> x0 + v91 LoadLocal { off=-6, kind=I32 } -> x0 + v92 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v92) block 5 start_pc=0 - v19 Imm(1) -> x0 - terminator Return(v19) (exit_acc=v19) + v93 Imm(8) -> x0 + v94 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v94) block 6 start_pc=0 - v20 Imm(0) -> x6 - v21 Imm(0) -> x0 - v22 Imm(0) -> x0 - v23 Imm(4) -> x0 - v24 Imm(0) -> x1 - v25 Imm(2) -> x1 - v26 Imm(0) -> x2 - terminator Jmp(b7) (exit_acc=v25) + v96 Imm(1) -> x0 + v97 Imm(0) -> x0 + v98 Imm(0) -> x0 + v99 Imm(5) -> x0 + v100 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v99) block 7 start_pc=0 - v27 Phi { incoming=[b6:v20, b8:v33], kind=I64 } -> x6 - v28 Phi { incoming=[b6:v20, b8:v37], kind=I64 } -> x2 - v29 Extend { value=v27, kind=I32 } -> x7 - v30 LoadLocal { off=-6, kind=I32 } -> x8 - v31 Binop { op=lt, lhs=v29, rhs=v23 } -> x7 - terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) + v101 LoadLocal { off=-9, kind=I64 } -> x0 + v102 LoadLocal { off=-10, kind=I64 } -> x0 + v103 Imm(1) -> x0 + v104 LoadLocal { off=-8, kind=I64 } -> x0 + v105 LoadLocal { off=-9, kind=I64 } -> x0 + v106 Imm(1) -> x0 + v107 Imm(0) -> x0 + v108 LoadLocal { off=-9, kind=I64 } -> x0 + v109 Imm(2) -> x0 + v110 Imm(0) -> x0 + v111 LoadLocal { off=-9, kind=I64 } -> x0 + v112 LoadLocal { off=-10, kind=I64 } -> x0 + v113 Imm(1) -> x0 + v114 LoadLocal { off=-8, kind=I64 } -> x0 + v115 LoadLocal { off=-9, kind=I64 } -> x0 + v116 Imm(2) -> x0 + v117 Imm(0) -> x0 + v118 LoadLocal { off=-9, kind=I64 } -> x0 + v119 Imm(3) -> x0 + v120 Imm(0) -> x0 + v121 LoadLocal { off=-9, kind=I64 } -> x0 + v122 LoadLocal { off=-10, kind=I64 } -> x0 + v123 Imm(1) -> x0 + v124 LoadLocal { off=-8, kind=I64 } -> x0 + v125 LoadLocal { off=-9, kind=I64 } -> x0 + v126 Imm(6) -> x0 + v127 Imm(0) -> x0 + v128 LoadLocal { off=-9, kind=I64 } -> x0 + v129 Imm(4) -> x0 + v130 Imm(0) -> x0 + v131 LoadLocal { off=-9, kind=I64 } -> x0 + v132 LoadLocal { off=-10, kind=I64 } -> x0 + v133 Imm(1) -> x0 + v134 LoadLocal { off=-8, kind=I64 } -> x0 + v135 LoadLocal { off=-9, kind=I64 } -> x0 + v136 Imm(24) -> x0 + v137 Imm(0) -> x0 + v138 LoadLocal { off=-9, kind=I64 } -> x0 + v139 Imm(5) -> x0 + v140 Imm(0) -> x0 + v141 LoadLocal { off=-9, kind=I64 } -> x0 + v142 LoadLocal { off=-10, kind=I64 } -> x0 + v143 Imm(1) -> x0 + v144 LoadLocal { off=-8, kind=I64 } -> x0 + v145 LoadLocal { off=-9, kind=I64 } -> x0 + v146 Imm(120) -> x0 + v147 Imm(0) -> x0 + v148 LoadLocal { off=-9, kind=I64 } -> x0 + v149 Imm(6) -> x0 + v150 Imm(0) -> x0 + v151 LoadLocal { off=-9, kind=I64 } -> x0 + v152 LoadLocal { off=-10, kind=I64 } -> x0 + v153 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v153) block 8 start_pc=0 - v32 Extend { value=v27, kind=I32 } -> x6 - v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x6 - v34 Imm(0) -> x7 - terminator Jmp(b7) (exit_acc=v33) + v154 LoadLocal { off=-8, kind=I64 } -> x0 + v155 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v155) block 9 start_pc=0 - v35 Extend { value=v28, kind=I32 } -> x7 - v36 LoadLocal { off=-7, kind=I32 } -> x7 - v37 Binop { op=add, lhs=v28, rhs=v25 } -> x2 - v38 Imm(0) -> x7 - v39 Extend { value=v37, kind=I32 } -> x7 - terminator Jmp(b8) (exit_acc=v39) + v157 Imm(0) -> x0 + v158 Imm(0) -> x0 + v159 Imm(2) -> x0 + v160 Imm(0) -> x0 + v161 LoadLocal { off=-12, kind=I32 } -> x0 + v162 Imm(5) -> x0 + v163 Imm(21474836480) -> x0 + v164 Imm(5) -> x0 + v165 Imm(0) -> x1 + terminator Jmp(b10) (exit_acc=v164) block 10 start_pc=0 - v40 Extend { value=v28, kind=I32 } -> x0 - v41 BinopI { op=ne, lhs=v40, rhs_imm=8 } -> x0 - terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) + v166 Imm(2) -> x0 + v167 LoadLocal { off=-13, kind=I32 } -> x0 + v168 Imm(1) -> x0 + v169 Imm(0) -> x0 + v170 Imm(1) -> x0 + v171 Imm(0) -> x0 + v172 Imm(2) -> x0 + v173 Imm(3) -> x0 + v174 Imm(0) -> x0 + v175 Imm(3) -> x0 + v176 LoadLocal { off=-13, kind=I32 } -> x0 + v177 Imm(1) -> x0 + v178 Imm(1) -> x0 + v179 Imm(2) -> x0 + v180 Imm(0) -> x0 + v181 Imm(3) -> x0 + v182 Imm(4) -> x0 + v183 Imm(0) -> x0 + v184 Imm(4) -> x0 + v185 LoadLocal { off=-13, kind=I32 } -> x0 + v186 Imm(1) -> x0 + v187 Imm(2) -> x0 + v188 Imm(3) -> x0 + v189 Imm(0) -> x0 + v190 Imm(4) -> x0 + v191 Imm(5) -> x0 + v192 Imm(0) -> x0 + v193 Imm(5) -> x0 + v194 LoadLocal { off=-13, kind=I32 } -> x0 + v195 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v195) block 11 start_pc=0 - v42 Imm(2) -> x0 - terminator Return(v42) (exit_acc=v42) + v196 Imm(3) -> x0 + v197 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v197) block 12 start_pc=0 - v43 Imm(1) -> x2 - v44 Imm(0) -> x0 - v45 Imm(0) -> x0 - v46 Imm(5) -> x0 - v47 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v46) + v199 Imm(0) -> x0 + terminator Return(v199) (exit_acc=v199) block 13 start_pc=0 - v48 Phi { incoming=[b12:v43, b14:v54], kind=I64 } -> x2 - v49 Phi { incoming=[b12:v43, b14:v58], kind=I64 } -> x1 - v50 LoadLocal { off=-9, kind=I64 } -> x6 - v51 LoadLocal { off=-10, kind=I64 } -> x6 - v52 Binop { op=le, lhs=v48, rhs=v46 } -> x6 - terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) + v38 Imm(1) -> x0 + terminator Return(v38) (exit_acc=v38) block 14 start_pc=0 - v53 LoadLocal { off=-9, kind=I64 } -> x6 - v54 BinopI { op=add, lhs=v48, rhs_imm=1 } -> x2 - v55 Imm(0) -> x6 - terminator Jmp(b13) (exit_acc=v54) + v95 Imm(2) -> x0 + terminator Return(v95) (exit_acc=v95) block 15 start_pc=0 - v56 LoadLocal { off=-8, kind=I64 } -> x6 - v57 LoadLocal { off=-9, kind=I64 } -> x6 - v58 Binop { op=mul, lhs=v49, rhs=v48 } -> x1 - v59 Imm(0) -> x6 - terminator Jmp(b14) (exit_acc=v58) + v156 Imm(3) -> x0 + terminator Return(v156) (exit_acc=v156) block 16 start_pc=0 - v60 LoadLocal { off=-8, kind=I64 } -> x0 - v61 BinopI { op=ne, lhs=v49, rhs_imm=120 } -> x0 - terminator Bz { cond=v61, target=b18, fall=b17 } (exit_acc=v61) - block 17 start_pc=0 - v62 Imm(3) -> x0 - terminator Return(v62) (exit_acc=v62) - block 18 start_pc=0 - v63 Imm(0) -> x6 - v64 Imm(0) -> x0 - v65 Imm(2) -> x2 - v66 Imm(0) -> x0 - v67 LoadLocal { off=-12, kind=I32 } -> x0 - v68 BinopI { op=add, lhs=v65, rhs_imm=3 } -> x0 - v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x1 - v70 Extend { value=v68, kind=I32 } -> x0 - v71 Imm(0) -> x1 - terminator Jmp(b19) (exit_acc=v70) - block 19 start_pc=0 - v72 Phi { incoming=[b18:v65, b20:v78], kind=I64 } -> x2 - v73 Phi { incoming=[b18:v63, b20:v81], kind=I64 } -> x6 - v74 Extend { value=v72, kind=I32 } -> x1 - v75 LoadLocal { off=-13, kind=I32 } -> x7 - v76 Binop { op=lt, lhs=v74, rhs=v70 } -> x1 - terminator Bz { cond=v76, target=b22, fall=b21 } (exit_acc=v76) - block 20 start_pc=0 - v77 Extend { value=v72, kind=I32 } -> x1 - v78 BinopI { op=add, lhs=v77, rhs_imm=1 } -> x2 - v79 Imm(0) -> x1 - terminator Jmp(b19) (exit_acc=v78) - block 21 start_pc=0 - v80 Extend { value=v73, kind=I32 } -> x1 - v81 BinopI { op=add, lhs=v80, rhs_imm=1 } -> x6 - v82 Imm(0) -> x1 - terminator Jmp(b20) (exit_acc=v81) - block 22 start_pc=0 - v83 Extend { value=v73, kind=I32 } -> x0 - v84 BinopI { op=ne, lhs=v83, rhs_imm=3 } -> x0 - terminator Bz { cond=v84, target=b24, fall=b23 } (exit_acc=v84) - block 23 start_pc=0 - v85 Imm(4) -> x0 - terminator Return(v85) (exit_acc=v85) - block 24 start_pc=0 - v86 Imm(0) -> x0 - terminator Return(v86) (exit_acc=v86) + v198 Imm(4) -> x0 + terminator Return(v198) (exit_acc=v198) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/for_loop.ssa b/tests/snapshots/ssa/for_loop.ssa index 2a5cae1c4..1b3fc645b 100644 --- a/tests/snapshots/ssa/for_loop.ssa +++ b/tests/snapshots/ssa/for_loop.ssa @@ -4,32 +4,72 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v15], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x0 - v6 Extend { value=v5, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=5 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(1) -> x0 + v17 Imm(0) -> x0 + v18 Imm(1) -> x0 + v19 Imm(1) -> x0 + v20 Imm(4294967296) -> x0 + v21 Imm(1) -> x0 + v22 Imm(0) -> x0 + v23 Imm(1) -> x0 + v24 Imm(2) -> x0 + v25 Imm(0) -> x0 + v26 Imm(2) -> x0 + v27 Imm(1) -> x0 + v28 Imm(1) -> x0 + v29 Imm(2) -> x0 + v30 Imm(3) -> x0 + v31 Imm(12884901888) -> x0 + v32 Imm(3) -> x0 + v33 Imm(0) -> x0 + v34 Imm(2) -> x0 + v35 Imm(3) -> x0 + v36 Imm(0) -> x0 + v37 Imm(3) -> x0 + v38 Imm(1) -> x0 + v39 Imm(3) -> x0 + v40 Imm(3) -> x0 + v41 Imm(6) -> x0 + v42 Imm(25769803776) -> x0 + v43 Imm(6) -> x0 + v44 Imm(0) -> x0 + v45 Imm(3) -> x0 + v46 Imm(4) -> x0 + v47 Imm(0) -> x0 + v48 Imm(4) -> x0 + v49 Imm(1) -> x0 + v50 Imm(6) -> x0 + v51 Imm(4) -> x0 + v52 Imm(10) -> x0 + v53 Imm(42949672960) -> x0 + v54 Imm(10) -> x0 + v55 Imm(0) -> x0 + v56 Imm(4) -> x0 + v57 Imm(5) -> x0 + v58 Imm(0) -> x0 + v59 Imm(5) -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v60) block 2 start_pc=0 - v8 Extend { value=v5, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x0 - v10 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 - v11 Extend { value=v4, kind=I32 } -> x2 - v12 Extend { value=v5, kind=I32 } -> x2 - v13 Binop { op=add, lhs=v4, rhs=v5 } -> x1 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x2 - v15 Extend { value=v13, kind=I32 } -> x1 - v16 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v15) - block 4 start_pc=0 - v17 Extend { value=v4, kind=I32 } -> x0 - terminator Return(v17) (exit_acc=v17) + v61 Imm(10) -> x0 + terminator Return(v61) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/for_loop_call_body_and_step.ssa b/tests/snapshots/ssa/for_loop_call_body_and_step.ssa index 1921aaf02..8184b6e2a 100644 --- a/tests/snapshots/ssa/for_loop_call_body_and_step.ssa +++ b/tests/snapshots/ssa/for_loop_call_body_and_step.ssa @@ -33,13 +33,16 @@ fn ent_pc=2 n_params=0 variadic=false locals=3 v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v20], kind=I64 } -> x0 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=7 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v15 Extend { value=v5, kind=I32 } -> x2 + v16 Extend { value=v15, kind=I32 } -> x2 + v17 Imm(0) -> x2 + v18 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x0 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x2 + v20 Extend { value=v18, kind=I32 } -> x0 + v21 Imm(0) -> x2 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 v8 Extend { value=v4, kind=I32 } -> x2 v9 Extend { value=v8, kind=I32 } -> x2 @@ -48,16 +51,13 @@ fn ent_pc=2 n_params=0 variadic=false locals=3 v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x2 v13 Extend { value=v11, kind=I32 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 Extend { value=v5, kind=I32 } -> x2 - v16 Extend { value=v15, kind=I32 } -> x2 - v17 Imm(0) -> x2 - v18 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x2 - v20 Extend { value=v18, kind=I32 } -> x0 - v21 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v20) + v4 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x1 + v5 Phi { incoming=[b0:v1, b2:v20], kind=I64 } -> x0 + v6 Extend { value=v4, kind=I32 } -> x2 + v7 BinopI { op=lt, lhs=v6, rhs_imm=7 } -> x2 + terminator Bnz { cond=v7, target=b1, fall=b4 } (exit_acc=v7) block 4 start_pc=0 v22 Extend { value=v5, kind=I32 } -> x1 v23 BinopI { op=mul, lhs=v5, rhs_imm=6 } -> x0 diff --git a/tests/snapshots/ssa/fp_arg_passed_in_fp_reg.ssa b/tests/snapshots/ssa/fp_arg_passed_in_fp_reg.ssa index c5317ceac..7373f62b8 100644 --- a/tests/snapshots/ssa/fp_arg_passed_in_fp_reg.ssa +++ b/tests/snapshots/ssa/fp_arg_passed_in_fp_reg.ssa @@ -59,13 +59,13 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 terminator Return(v11) (exit_acc=v11) block 2 start_pc=0 v12 Imm(3) -> x0 - v13 Imm(4609434218613702656) -> x1 - v14 Imm(4) -> x2 - v15 Imm(4612811918334230528) -> x6 - v16 Extend { value=v12, kind=I32 } -> x0 - v17 Imm(0) -> x7 - v18 Imm(0) -> x7 - v19 Extend { value=v14, kind=I32 } -> x2 + v13 Imm(4609434218613702656) -> x0 + v14 Imm(4) -> x1 + v15 Imm(4612811918334230528) -> x1 + v16 Imm(3) -> x2 + v17 Imm(0) -> x6 + v18 Imm(0) -> x6 + v19 Imm(4) -> x6 v20 Imm(0) -> x7 v21 Imm(0) -> x7 v22 FpCast { kind=IntToFp, value=v16 } -> d0 diff --git a/tests/snapshots/ssa/fp_const_return.ssa b/tests/snapshots/ssa/fp_const_return.ssa index 3d6d810e7..1cb9bacb1 100644 --- a/tests/snapshots/ssa/fp_const_return.ssa +++ b/tests/snapshots/ssa/fp_const_return.ssa @@ -12,26 +12,26 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 v5 Imm(0) -> x1 v6 StoreLocal { off=-1, value=v5, kind=F64 } -> - v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v13], kind=I64 } -> x1 - v9 Extend { value=v8, kind=I32 } -> x0 - v10 LoadLocal { off=3, kind=I32 } -> x2 - v11 Binop { op=lt, lhs=v9, rhs=v3 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 Extend { value=v8, kind=I32 } -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 - v14 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v13) - block 3 start_pc=0 - v15 LoadLocal { off=2, kind=I64 } -> x0 - v16 Extend { value=v8, kind=I32 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=3 } -> x0 - v18 Binop { op=add, lhs=v1, rhs=v17 } -> x0 + v15 LoadLocal { off=2, kind=I64 } -> x2 + v16 Extend { value=v8, kind=I32 } -> x2 + v17 BinopI { op=shl, lhs=v9, rhs_imm=3 } -> x2 + v18 Binop { op=add, lhs=v1, rhs=v17 } -> x2 v19 Load { addr=v18, disp=0, kind=F64 } -> d0 v20 StoreLocal { off=-1, value=v19, kind=F64 } -> - terminator Jmp(b2) (exit_acc=v20) + block 2 start_pc=0 + v12 Extend { value=v8, kind=I32 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v14 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v5, b2:v13], kind=I64 } -> x1 + v9 Extend { value=v8, kind=I32 } -> x0 + v10 LoadLocal { off=3, kind=I32 } -> x2 + v11 Binop { op=lt, lhs=v9, rhs=v3 } -> x2 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v21 LoadLocal { off=-1, kind=F64 } -> d0 terminator Return(v21) (exit_acc=v21) @@ -67,9 +67,8 @@ fn ent_pc=4 n_params=0 variadic=false locals=0 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4598175219545276416) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - terminator Return(v2) (exit_acc=v2) + v1 Imm(1048576000) -> x0 [f32] + terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=sum_zero fn ent_pc=5 n_params=2 variadic=false locals=2 @@ -84,40 +83,42 @@ fn ent_pc=5 n_params=2 variadic=false locals=2 v6 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v7 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x6 + v7 Phi { incoming=[b0:v3, b4:v12], kind=I64 } -> x6 v8 Extend { value=v7, kind=I32 } -> x0 - v9 BinopI { op=gt, lhs=v8, rhs_imm=0 } -> x1 - v10 Imm(0) -> x0 - terminator Bz { cond=v9, target=b8, fall=b4 } (exit_acc=v9) + v9 BinopI { op=gt, lhs=v8, rhs_imm=0 } -> x2 + v10 Imm(0) -> x1 + terminator Bz { cond=v9, target=b5, fall=b2 } (exit_acc=v9) block 2 start_pc=0 - v11 Extend { value=v7, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=-1 } -> x6 - v13 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v12) + v16 LoadLocal { off=2, kind=I64 } -> x1 + v17 Extend { value=v7, kind=I32 } -> x1 + v18 BinopI { op=sub, lhs=v7, rhs_imm=1 } -> x1 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x2 + v20 Extend { value=v18, kind=I32 } -> x1 + v21 BinopI { op=shl, lhs=v20, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v1, rhs=v21 } -> x2 + v23 LoadIndexed { base=v1, index=v20, scale=8, kind=I64 } -> x1 + v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x2 + v25 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v24) block 3 start_pc=0 - v14 Extend { value=v7, kind=I32 } -> x0 - v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b7, fall=b6 } (exit_acc=v15) + v26 Phi { incoming=[b5:v9, b2:v24], kind=I64 } -> x2 + v27 LoadLocal { off=-2, kind=I64 } -> x1 + terminator Bz { cond=v26, target=b6, fall=b4 } (exit_acc=v26) block 4 start_pc=0 - v16 LoadLocal { off=2, kind=I64 } -> x0 - v17 Extend { value=v7, kind=I32 } -> x0 - v18 BinopI { op=sub, lhs=v7, rhs_imm=1 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x0 - v21 BinopI { op=shl, lhs=v20, rhs_imm=3 } -> x1 - v22 Binop { op=add, lhs=v1, rhs=v21 } -> x1 - v23 LoadIndexed { base=v1, index=v20, scale=8, kind=I64 } -> x0 - v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v24) + v11 Extend { value=v7, kind=I32 } -> x1 + v12 BinopI { op=add, lhs=v8, rhs_imm=-1 } -> x6 + v13 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v12) block 5 start_pc=0 - v26 Phi { incoming=[b8:v9, b4:v24], kind=I64 } -> x1 - v27 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v26, target=b3, fall=b2 } (exit_acc=v26) + terminator Jmp(b3) block 6 start_pc=0 + v14 Extend { value=v7, kind=I32 } -> x1 + v15 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x0 + terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) + block 7 start_pc=0 v28 Imm(0) -> x0 terminator Return(v28) (exit_acc=v28) - block 7 start_pc=0 + block 8 start_pc=0 v29 LoadLocal { off=2, kind=I64 } -> x0 v30 Extend { value=v7, kind=I32 } -> x0 v31 BinopI { op=sub, lhs=v7, rhs_imm=1 } -> x0 @@ -128,8 +129,6 @@ fn ent_pc=5 n_params=2 variadic=false locals=2 v36 LoadIndexed { base=v1, index=v33, scale=8, kind=I64 } -> x0 v37 FpCast { kind=IntToFp, value=v36 } -> d0 terminator Return(v37) (exit_acc=v37) - block 8 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=6 --- ; name=main fn ent_pc=6 n_params=0 variadic=false locals=12 @@ -168,7 +167,7 @@ fn ent_pc=6 n_params=0 variadic=false locals=12 v22 Imm(2) -> x6 v23 Call { target_pc=0, args=[v21, v22], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 v24 Imm(7) -> x0 - v25 Extend { value=v24, kind=I32 } -> x0 + v25 Imm(7) -> x0 v26 Imm(0) -> x0 v27 Imm(4602678819172646912) -> x0 v28 Imm(4602678819172646912) -> x1 @@ -181,31 +180,30 @@ fn ent_pc=6 n_params=0 variadic=false locals=12 v31 LocalAddr(-2) -> x7 v32 Imm(2) -> x6 v33 Call { target_pc=0, args=[v31, v32], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v34 Imm(4598175219545276416) -> x0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 FpCast { kind=F32ToF64, value=v35 } -> d0 - v37 Imm(4598175219545276416) -> x0 - v38 Binop { op=fne, lhs=v36, rhs=v37 } -> x0 - terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + v34 Imm(1048576000) -> x0 [f32] + v35 FpCast { kind=F32ToF64, value=v34 } -> d0 + v36 Imm(4598175219545276416) -> x0 + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) block 7 start_pc=0 - v39 Imm(4) -> x0 - terminator Return(v39) (exit_acc=v39) + v38 Imm(4) -> x0 + terminator Return(v38) (exit_acc=v38) block 8 start_pc=0 - v40 LocalAddr(-2) -> x7 - v41 Imm(2) -> x6 - v42 Call { target_pc=0, args=[v40, v41], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v43 LocalAddr(-10) -> x7 - v44 Imm(8) -> x6 - v45 Call { target_pc=5, args=[v43, v44], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v46 Imm(0) -> x0 - v47 Binop { op=fne, lhs=v45, rhs=v46 } -> x0 - terminator Bz { cond=v47, target=b10, fall=b9 } (exit_acc=v47) + v39 LocalAddr(-2) -> x7 + v40 Imm(2) -> x6 + v41 Call { target_pc=0, args=[v39, v40], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 + v42 LocalAddr(-10) -> x7 + v43 Imm(8) -> x6 + v44 Call { target_pc=5, args=[v42, v43], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 + v45 Imm(0) -> x0 + v46 Binop { op=fne, lhs=v44, rhs=v45 } -> x0 + terminator Bz { cond=v46, target=b10, fall=b9 } (exit_acc=v46) block 9 start_pc=0 - v48 Imm(5) -> x0 - terminator Return(v48) (exit_acc=v48) + v47 Imm(5) -> x0 + terminator Return(v47) (exit_acc=v47) block 10 start_pc=0 - v49 Imm(0) -> x0 - terminator Return(v49) (exit_acc=v49) + v48 Imm(0) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_load_folded_disp.ssa b/tests/snapshots/ssa/fp_load_folded_disp.ssa index 6a6ed4450..d98c17ffb 100644 --- a/tests/snapshots/ssa/fp_load_folded_disp.ssa +++ b/tests/snapshots/ssa/fp_load_folded_disp.ssa @@ -63,80 +63,76 @@ fn ent_pc=4 n_params=0 variadic=false locals=6 v3 Store { addr=v1, disp=0, value=v2, kind=I64 } -> - v4 LocalAddr(-5) -> x0 v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x1 - v6 Imm(4608308318706860032) -> x1 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] - v8 Store { addr=v4, disp=8, value=v7, kind=F32 } -> - - v9 LocalAddr(-5) -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x2 - v11 Imm(4612811918334230528) -> x2 - v12 Store { addr=v9, disp=16, value=v11, kind=F64 } -> - - v13 LocalAddr(-5) -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=24 } -> x2 - v15 Imm(0) -> x2 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Store { addr=v13, disp=24, value=v16, kind=F32 } -> - - v18 LocalAddr(-5) -> x0 - v19 BinopI { op=add, lhs=v18, rhs_imm=24 } -> x2 - v20 Imm(4) -> x2 - v21 BinopI { op=add, lhs=v18, rhs_imm=28 } -> x2 - v22 Store { addr=v18, disp=28, value=v16, kind=F32 } -> - - v23 LocalAddr(-5) -> x0 - v24 BinopI { op=add, lhs=v23, rhs_imm=24 } -> x2 - v25 Imm(8) -> x2 - v26 BinopI { op=add, lhs=v23, rhs_imm=32 } -> x2 - v27 Imm(4617034042984890368) -> x2 - v28 FpCast { kind=F64ToF32, value=v27 } -> d0 [f32] - v29 Store { addr=v23, disp=32, value=v28, kind=F32 } -> - - v30 LocalAddr(-5) -> x0 - v31 Imm(0) -> x2 - v32 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x2 - v33 Load { addr=v30, disp=8, kind=F32 } -> d0 [f32] - v34 FpCast { kind=F32ToF64, value=v33 } -> d0 - v35 Binop { op=fne, lhs=v34, rhs=v6 } -> x0 - terminator Bz { cond=v35, target=b2, fall=b1 } (exit_acc=v35) + v6 Imm(1067450368) -> x1 [f32] + v7 Store { addr=v4, disp=8, value=v6, kind=F32 } -> - + v8 LocalAddr(-5) -> x0 + v9 BinopI { op=add, lhs=v8, rhs_imm=16 } -> x2 + v10 Imm(4612811918334230528) -> x2 + v11 Store { addr=v8, disp=16, value=v10, kind=F64 } -> - + v12 LocalAddr(-5) -> x0 + v13 BinopI { op=add, lhs=v12, rhs_imm=24 } -> x2 + v14 Imm(0) -> x2 + v15 Imm(0) -> x2 [f32] + v16 Store { addr=v12, disp=24, value=v15, kind=F32 } -> - + v17 LocalAddr(-5) -> x0 + v18 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x6 + v19 Imm(4) -> x6 + v20 BinopI { op=add, lhs=v17, rhs_imm=28 } -> x6 + v21 Store { addr=v17, disp=28, value=v15, kind=F32 } -> - + v22 LocalAddr(-5) -> x0 + v23 BinopI { op=add, lhs=v22, rhs_imm=24 } -> x2 + v24 Imm(8) -> x2 + v25 BinopI { op=add, lhs=v22, rhs_imm=32 } -> x2 + v26 Imm(1083703296) -> x2 [f32] + v27 Store { addr=v22, disp=32, value=v26, kind=F32 } -> - + v28 LocalAddr(-5) -> x0 + v29 Imm(0) -> x2 + v30 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x2 + v31 Load { addr=v28, disp=8, kind=F32 } -> d0 [f32] + v32 Binop { op=fne, lhs=v31, rhs=v6 } -> x0 + terminator Bz { cond=v32, target=b2, fall=b1 } (exit_acc=v32) block 1 start_pc=0 - v36 Imm(1) -> x0 - terminator Return(v36) (exit_acc=v36) + v33 Imm(1) -> x0 + terminator Return(v33) (exit_acc=v33) block 2 start_pc=0 - v37 LocalAddr(-5) -> x0 - v38 Imm(0) -> x1 - v39 BinopI { op=add, lhs=v37, rhs_imm=16 } -> x1 - v40 Load { addr=v37, disp=16, kind=F64 } -> d0 - v41 Imm(4612811918334230528) -> x0 - v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 - terminator Bz { cond=v42, target=b4, fall=b3 } (exit_acc=v42) + v34 LocalAddr(-5) -> x0 + v35 Imm(0) -> x1 + v36 BinopI { op=add, lhs=v34, rhs_imm=16 } -> x1 + v37 Load { addr=v34, disp=16, kind=F64 } -> d0 + v38 Imm(4612811918334230528) -> x0 + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 + terminator Bz { cond=v39, target=b4, fall=b3 } (exit_acc=v39) block 3 start_pc=0 - v43 Imm(2) -> x0 - terminator Return(v43) (exit_acc=v43) + v40 Imm(2) -> x0 + terminator Return(v40) (exit_acc=v40) block 4 start_pc=0 - v44 LocalAddr(-5) -> x0 - v45 Imm(0) -> x1 - v46 BinopI { op=add, lhs=v44, rhs_imm=24 } -> x1 - v47 Imm(8) -> x1 - v48 BinopI { op=add, lhs=v44, rhs_imm=32 } -> x1 - v49 Load { addr=v44, disp=32, kind=F32 } -> d0 [f32] - v50 Imm(4617034042984890368) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b6, fall=b5 } (exit_acc=v52) + v41 LocalAddr(-5) -> x0 + v42 Imm(0) -> x1 + v43 BinopI { op=add, lhs=v41, rhs_imm=24 } -> x1 + v44 Imm(8) -> x1 + v45 BinopI { op=add, lhs=v41, rhs_imm=32 } -> x1 + v46 Load { addr=v41, disp=32, kind=F32 } -> d0 [f32] + v47 Imm(1083703296) -> x0 [f32] + v48 Binop { op=fne, lhs=v46, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b6, fall=b5 } (exit_acc=v48) block 5 start_pc=0 - v53 Imm(3) -> x0 - terminator Return(v53) (exit_acc=v53) + v49 Imm(3) -> x0 + terminator Return(v49) (exit_acc=v49) block 6 start_pc=0 - v54 LocalAddr(-5) -> x7 - v55 Call { target_pc=3, args=[v54], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v56 LocalAddr(-5) -> x0 - v57 BinopI { op=add, lhs=v56, rhs_imm=16 } -> x1 - v58 Load { addr=v56, disp=16, kind=F64 } -> d0 - v59 Imm(4613937818241073152) -> x0 - v60 Binop { op=fne, lhs=v58, rhs=v59 } -> x0 - terminator Bz { cond=v60, target=b8, fall=b7 } (exit_acc=v60) + v50 LocalAddr(-5) -> x7 + v51 Call { target_pc=3, args=[v50], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v52 LocalAddr(-5) -> x0 + v53 BinopI { op=add, lhs=v52, rhs_imm=16 } -> x1 + v54 Load { addr=v52, disp=16, kind=F64 } -> d0 + v55 Imm(4613937818241073152) -> x0 + v56 Binop { op=fne, lhs=v54, rhs=v55 } -> x0 + terminator Bz { cond=v56, target=b8, fall=b7 } (exit_acc=v56) block 7 start_pc=0 - v61 Imm(4) -> x0 - terminator Return(v61) (exit_acc=v61) + v57 Imm(4) -> x0 + terminator Return(v57) (exit_acc=v57) block 8 start_pc=0 - v62 Imm(0) -> x0 - terminator Return(v62) (exit_acc=v62) + v58 Imm(0) -> x0 + terminator Return(v58) (exit_acc=v58) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_param_float_before_double.ssa b/tests/snapshots/ssa/fp_param_float_before_double.ssa index 201e45d43..59e52a562 100644 --- a/tests/snapshots/ssa/fp_param_float_before_double.ssa +++ b/tests/snapshots/ssa/fp_param_float_before_double.ssa @@ -71,70 +71,65 @@ fn ent_pc=4 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4612811918334230528) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4616752568008179712) -> x1 + v1 Imm(1075838976) -> x0 [f32] + v2 Imm(4616752568008179712) -> x1 + v3 Imm(0) -> x1 v4 Imm(0) -> x1 - v5 Imm(0) -> x1 - v6 FpCast { kind=F32ToF64, value=v2 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v1 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Binop { op=fne, lhs=v1, rhs=v1 } -> x0 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v9 Imm(4620974692658839552) -> x0 - v10 Imm(4619004367821864960) -> x0 - v11 FpCast { kind=F64ToF32, value=v10 } -> d0 [f32] - v12 Imm(0) -> x1 - v13 Imm(0) -> x1 - v14 FpCast { kind=F32ToF64, value=v11 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v10 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v7 Imm(4620974692658839552) -> x0 + v8 Imm(1087373312) -> x0 [f32] + v9 Imm(0) -> x1 + v10 Imm(0) -> x1 + v11 FpCast { kind=F32ToF64, value=v8 } -> d0 + v12 FpCast { kind=F32ToF64, value=v8 } -> d1 + v13 Binop { op=fne, lhs=v11, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v17 Imm(4607182418800017408) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Imm(4611686018427387904) -> x0 - v20 Imm(4613937818241073152) -> x1 - v21 FpCast { kind=F64ToF32, value=v20 } -> d1 [f32] - v22 Imm(4616189618054758400) -> x1 - v23 Imm(0) -> x2 - v24 Imm(0) -> x2 - v25 Imm(0) -> x2 - v26 Imm(0) -> x2 - v27 FpCast { kind=F32ToF64, value=v18 } -> d0 - v28 Binop { op=fadd, lhs=v27, rhs=v19 } -> d0 - v29 FpCast { kind=F32ToF64, value=v21 } -> d1 - v30 Binop { op=fadd, lhs=v28, rhs=v29 } -> d0 - v31 Binop { op=fadd, lhs=v30, rhs=v22 } -> d0 - v32 Imm(4621819117588971520) -> x0 - v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x0 - terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + v15 Imm(1065353216) -> x0 [f32] + v16 Imm(4611686018427387904) -> x1 + v17 Imm(1077936128) -> x2 [f32] + v18 Imm(4616189618054758400) -> x6 + v19 Imm(0) -> x7 + v20 Imm(0) -> x7 + v21 Imm(0) -> x7 + v22 Imm(0) -> x7 + v23 FpCast { kind=F32ToF64, value=v15 } -> d0 + v24 Binop { op=fadd, lhs=v23, rhs=v16 } -> d0 + v25 FpCast { kind=F32ToF64, value=v17 } -> d1 + v26 Binop { op=fadd, lhs=v24, rhs=v25 } -> d0 + v27 Binop { op=fadd, lhs=v26, rhs=v18 } -> d0 + v28 Imm(4621819117588971520) -> x0 + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v34 Imm(3) -> x0 - terminator Return(v34) (exit_acc=v34) + v30 Imm(3) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v35 Imm(4617315517961601024) -> x0 - v36 Imm(4618441417868443648) -> x1 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 Imm(0) -> x1 - v39 Imm(0) -> x1 - v40 Imm(4621819117588971520) -> x1 - v41 Binop { op=fmul, lhs=v35, rhs=v40 } -> d1 - v42 FpCast { kind=F32ToF64, value=v37 } -> d0 - v43 Fma { a=v35, b=v40, c=v42, neg_product=false, neg_addend=false } -> d0 - v44 Imm(4633078116657397760) -> x0 - v45 Binop { op=fne, lhs=v43, rhs=v44 } -> x0 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) + v31 Imm(4617315517961601024) -> x0 + v32 Imm(1086324736) -> x1 [f32] + v33 Imm(0) -> x2 + v34 Imm(0) -> x2 + v35 Imm(4621819117588971520) -> x2 + v36 Binop { op=fmul, lhs=v31, rhs=v35 } -> d0 + v37 FpCast { kind=F32ToF64, value=v32 } -> d0 + v38 Fma { a=v31, b=v35, c=v37, neg_product=false, neg_addend=false } -> d0 + v39 Imm(4633078116657397760) -> x0 + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b8, fall=b7 } (exit_acc=v40) block 7 start_pc=0 - v46 Imm(4) -> x0 - terminator Return(v46) (exit_acc=v46) + v41 Imm(4) -> x0 + terminator Return(v41) (exit_acc=v41) block 8 start_pc=0 - v47 Imm(0) -> x0 - terminator Return(v47) (exit_acc=v47) + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_param_ternary.ssa b/tests/snapshots/ssa/fp_param_ternary.ssa index c239b7da6..79973474e 100644 --- a/tests/snapshots/ssa/fp_param_ternary.ssa +++ b/tests/snapshots/ssa/fp_param_ternary.ssa @@ -10,20 +10,20 @@ fn ent_pc=1 n_params=2 variadic=false locals=2 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=and, lhs=v1, rhs_imm=1 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b3, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v7 LoadLocal { off=-1, kind=F32 } -> d0 [f32] v8 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) block 2 start_pc=0 + v12 Phi { incoming=[b1:v3, b3:v10], kind=F32 } -> d1 [f32] + v13 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + terminator Return(v12) (exit_acc=v12) + block 3 start_pc=0 v9 LoadLocal { off=-1, kind=F32 } -> d0 [f32] v10 Fneg(v3) -> d1 [f32] v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v10) - block 3 start_pc=0 - v12 Phi { incoming=[b1:v3, b2:v10], kind=F32 } -> d1 [f32] - v13 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - terminator Return(v12) (exit_acc=v12) + terminator Jmp(b2) (exit_acc=v10) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=grad_dot fn ent_pc=2 n_params=3 variadic=false locals=6 @@ -38,40 +38,40 @@ fn ent_pc=2 n_params=3 variadic=false locals=6 v6 Imm(0) -> x0 v7 LoadLocal { off=2, kind=I32 } -> x0 v8 BinopI { op=and, lhs=v1, rhs_imm=1 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + terminator Bz { cond=v8, target=b6, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v9 LoadLocal { off=-1, kind=F32 } -> d0 [f32] v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) block 2 start_pc=0 - v11 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v12 Fneg(v3) -> d2 [f32] - v13 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v12) - block 3 start_pc=0 - v14 Phi { incoming=[b1:v3, b2:v12], kind=F32 } -> d2 [f32] + v14 Phi { incoming=[b1:v3, b6:v12], kind=F32 } -> d2 [f32] v15 LoadLocal { off=-5, kind=F32 } -> d0 [f32] v16 Imm(0) -> x0 v17 LoadLocal { off=2, kind=I32 } -> x0 v18 BinopI { op=and, lhs=v1, rhs_imm=2 } -> x0 - terminator Bz { cond=v18, target=b5, fall=b4 } (exit_acc=v18) - block 4 start_pc=0 + terminator Bz { cond=v18, target=b5, fall=b3 } (exit_acc=v18) + block 3 start_pc=0 v19 LoadLocal { off=-2, kind=F32 } -> d0 [f32] v20 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v21 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v22 Fneg(v5) -> d1 [f32] - v23 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v22) - block 6 start_pc=0 - v24 Phi { incoming=[b4:v5, b5:v22], kind=F32 } -> d1 [f32] + terminator Jmp(b4) (exit_acc=v5) + block 4 start_pc=0 + v24 Phi { incoming=[b3:v5, b5:v22], kind=F32 } -> d1 [f32] v25 LoadLocal { off=-6, kind=F32 } -> d0 [f32] v26 Imm(0) -> x0 v27 LoadLocal { off=-3, kind=F32 } -> d0 [f32] v28 LoadLocal { off=-4, kind=F32 } -> d0 [f32] v29 Binop { op=fadd, lhs=v14, rhs=v24 } -> d0 [f32] terminator Return(v29) (exit_acc=v29) + block 5 start_pc=0 + v21 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v22 Fneg(v5) -> d1 [f32] + v23 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v22) + block 6 start_pc=0 + v11 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v12 Fneg(v3) -> d2 [f32] + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v12) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=3 @@ -79,97 +79,80 @@ fn ent_pc=3 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x7 - v2 Imm(4617315517961601024) -> x3 - v3 FpCast { kind=F64ToF32, value=v2 } -> d0 [f32] - v4 Call { target_pc=1, args=[v1, v3], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v5 Fneg(v2) -> d1 - v6 FpCast { kind=F32ToF64, value=v4 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v5 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(1084227584) -> x3 [f32] + v3 Call { target_pc=1, args=[v1, v2], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v4 Fneg(v2) -> d1 [f32] + v5 Binop { op=fne, lhs=v3, rhs=v4 } -> x0 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v9 Imm(1) -> x7 - v10 Imm(4617315517961601024) -> x3 - v11 FpCast { kind=F64ToF32, value=v10 } -> d0 [f32] - v12 Call { target_pc=1, args=[v9, v11], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v13 FpCast { kind=F32ToF64, value=v12 } -> d0 - v14 Binop { op=fne, lhs=v13, rhs=v10 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v7 Imm(1) -> x7 + v8 Imm(1084227584) -> x3 [f32] + v9 Call { target_pc=1, args=[v7, v8], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v10 Binop { op=fne, lhs=v9, rhs=v8 } -> x0 + terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) + v11 Imm(2) -> x0 + terminator Return(v11) (exit_acc=v11) block 4 start_pc=0 - v16 Imm(2) -> x7 - v17 Imm(4617315517961601024) -> x3 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Call { target_pc=1, args=[v16, v18], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v20 Fneg(v17) -> d1 - v21 FpCast { kind=F32ToF64, value=v19 } -> d0 - v22 Binop { op=fne, lhs=v21, rhs=v20 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v12 Imm(2) -> x7 + v13 Imm(1084227584) -> x3 [f32] + v14 Call { target_pc=1, args=[v12, v13], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v15 Fneg(v13) -> d1 [f32] + v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v17 Imm(3) -> x0 + terminator Return(v17) (exit_acc=v17) block 6 start_pc=0 - v24 Imm(3) -> x7 - v25 Imm(4617315517961601024) -> x3 - v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] - v27 Call { target_pc=1, args=[v24, v26], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v28 FpCast { kind=F32ToF64, value=v27 } -> d0 - v29 Binop { op=fne, lhs=v28, rhs=v25 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) + v18 Imm(3) -> x7 + v19 Imm(1084227584) -> x3 [f32] + v20 Call { target_pc=1, args=[v18, v19], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v21 Binop { op=fne, lhs=v20, rhs=v19 } -> x0 + terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) block 7 start_pc=0 - v30 Imm(4) -> x0 - terminator Return(v30) (exit_acc=v30) + v22 Imm(4) -> x0 + terminator Return(v22) (exit_acc=v22) block 8 start_pc=0 - v31 Imm(1) -> x7 - v32 Imm(4609434218613702656) -> x3 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 Imm(4612811918334230528) -> x12 - v35 FpCast { kind=F64ToF32, value=v34 } -> d1 [f32] - v36 Call { target_pc=2, args=[v31, v33, v35], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v37 Fneg(v34) -> d1 - v38 Binop { op=fadd, lhs=v32, rhs=v37 } -> d1 - v39 FpCast { kind=F32ToF64, value=v36 } -> d0 - v40 Binop { op=fne, lhs=v39, rhs=v38 } -> x0 - terminator Bz { cond=v40, target=b10, fall=b9 } (exit_acc=v40) + v23 Imm(1) -> x7 + v24 Imm(1069547520) -> x3 [f32] + v25 Imm(1075838976) -> x12 [f32] + v26 Call { target_pc=2, args=[v23, v24, v25], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v27 Fneg(v25) -> d1 [f32] + v28 Binop { op=fadd, lhs=v24, rhs=v27 } -> d1 [f32] + v29 Binop { op=fne, lhs=v26, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b10, fall=b9 } (exit_acc=v29) block 9 start_pc=0 - v41 Imm(5) -> x0 - terminator Return(v41) (exit_acc=v41) + v30 Imm(5) -> x0 + terminator Return(v30) (exit_acc=v30) block 10 start_pc=0 - v42 Imm(2) -> x7 - v43 Imm(4619848792751996928) -> x3 - v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] - v45 Imm(4593671619917905920) -> x12 - v46 FpCast { kind=F64ToF32, value=v45 } -> d1 [f32] - v47 Call { target_pc=2, args=[v42, v44, v46], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v48 Fneg(v43) -> d1 - v49 Binop { op=fadd, lhs=v48, rhs=v45 } -> d1 - v50 FpCast { kind=F32ToF64, value=v47 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) + v31 Imm(2) -> x7 + v32 Imm(1088946176) -> x3 [f32] + v33 Imm(1040187392) -> x12 [f32] + v34 Call { target_pc=2, args=[v31, v32, v33], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v35 Fneg(v32) -> d1 [f32] + v36 Binop { op=fadd, lhs=v35, rhs=v33 } -> d1 [f32] + v37 Binop { op=fne, lhs=v34, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) block 11 start_pc=0 - v52 Imm(6) -> x0 - terminator Return(v52) (exit_acc=v52) + v38 Imm(6) -> x0 + terminator Return(v38) (exit_acc=v38) block 12 start_pc=0 - v53 Imm(3) -> x7 - v54 Imm(4613937818241073152) -> x3 - v55 FpCast { kind=F64ToF32, value=v54 } -> d0 [f32] - v56 Imm(4616189618054758400) -> x12 - v57 FpCast { kind=F64ToF32, value=v56 } -> d1 [f32] - v58 Call { target_pc=2, args=[v53, v55, v57], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v59 Binop { op=fadd, lhs=v54, rhs=v56 } -> d1 - v60 FpCast { kind=F32ToF64, value=v58 } -> d0 - v61 Binop { op=fne, lhs=v60, rhs=v59 } -> x0 - terminator Bz { cond=v61, target=b14, fall=b13 } (exit_acc=v61) + v39 Imm(3) -> x7 + v40 Imm(1077936128) -> x3 [f32] + v41 Imm(1082130432) -> x12 [f32] + v42 Call { target_pc=2, args=[v39, v40, v41], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v43 Binop { op=fadd, lhs=v40, rhs=v41 } -> d1 [f32] + v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) block 13 start_pc=0 - v62 Imm(7) -> x0 - terminator Return(v62) (exit_acc=v62) + v45 Imm(7) -> x0 + terminator Return(v45) (exit_acc=v45) block 14 start_pc=0 - v63 Imm(0) -> x0 - terminator Return(v63) (exit_acc=v63) + v46 Imm(0) -> x0 + terminator Return(v46) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_return_value.ssa b/tests/snapshots/ssa/fp_return_value.ssa index 5b8af9f28..9eacac707 100644 --- a/tests/snapshots/ssa/fp_return_value.ssa +++ b/tests/snapshots/ssa/fp_return_value.ssa @@ -22,11 +22,9 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 FpCast { kind=IntToFp, value=v1 } -> d0 v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] - v6 Imm(4616189618054758400) -> x0 - v7 FpCast { kind=F32ToF64, value=v5 } -> d0 - v8 Binop { op=fdiv, lhs=v7, rhs=v6 } -> d0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d0 [f32] - terminator Return(v9) (exit_acc=v9) + v6 Imm(1082130432) -> x0 [f32] + v7 Binop { op=fdiv, lhs=v5, rhs=v6 } -> d0 [f32] + terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=4 @@ -34,13 +32,13 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Extend { value=v1, kind=I32 } -> x0 + v2 Imm(7) -> x0 v3 Imm(0) -> x1 v4 FpCast { kind=IntToFp, value=v2 } -> d0 v5 Imm(4602678819172646912) -> x0 v6 Binop { op=fadd, lhs=v4, rhs=v5 } -> d0 v7 Imm(2) -> x0 - v8 Extend { value=v7, kind=I32 } -> x0 + v8 Imm(2) -> x0 v9 Imm(0) -> x1 v10 FpCast { kind=IntToFp, value=v8 } -> d1 v11 Imm(4602678819172646912) -> x0 @@ -56,64 +54,57 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 terminator Return(v18) (exit_acc=v18) block 2 start_pc=0 v19 Imm(3) -> x0 - v20 Extend { value=v19, kind=I32 } -> x0 + v20 Imm(3) -> x0 v21 Imm(0) -> x1 v22 FpCast { kind=IntToFp, value=v20 } -> d0 v23 FpCast { kind=F64ToF32, value=v22 } -> d0 [f32] - v24 Imm(4616189618054758400) -> x0 - v25 FpCast { kind=F32ToF64, value=v23 } -> d0 - v26 Binop { op=fdiv, lhs=v25, rhs=v24 } -> d0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Imm(5) -> x0 - v29 Extend { value=v28, kind=I32 } -> x0 - v30 Imm(0) -> x1 - v31 FpCast { kind=IntToFp, value=v29 } -> d1 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 Imm(4616189618054758400) -> x0 - v34 FpCast { kind=F32ToF64, value=v32 } -> d1 - v35 Binop { op=fdiv, lhs=v34, rhs=v33 } -> d1 - v36 FpCast { kind=F64ToF32, value=v35 } -> d1 [f32] - v37 Binop { op=fadd, lhs=v27, rhs=v36 } -> d0 [f32] - v38 Imm(0) -> x0 - v39 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v40 Imm(4611686018427387904) -> x0 - v41 FpCast { kind=F32ToF64, value=v37 } -> d0 - v42 Binop { op=fne, lhs=v41, rhs=v40 } -> x0 - terminator Bz { cond=v42, target=b4, fall=b3 } (exit_acc=v42) + v24 Imm(1082130432) -> x0 [f32] + v25 Binop { op=fdiv, lhs=v23, rhs=v24 } -> d0 [f32] + v26 Imm(5) -> x0 + v27 Imm(5) -> x0 + v28 Imm(0) -> x1 + v29 FpCast { kind=IntToFp, value=v27 } -> d1 + v30 FpCast { kind=F64ToF32, value=v29 } -> d1 [f32] + v31 Imm(1082130432) -> x0 [f32] + v32 Binop { op=fdiv, lhs=v30, rhs=v31 } -> d1 [f32] + v33 Binop { op=fadd, lhs=v25, rhs=v32 } -> d0 [f32] + v34 Imm(0) -> x0 + v35 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v36 Imm(1073741824) -> x0 [f32] + v37 Binop { op=fne, lhs=v33, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b4, fall=b3 } (exit_acc=v37) block 3 start_pc=0 - v43 Imm(2) -> x0 - terminator Return(v43) (exit_acc=v43) + v38 Imm(2) -> x0 + terminator Return(v38) (exit_acc=v38) block 4 start_pc=0 - v44 Imm(1) -> x0 - v45 Extend { value=v44, kind=I32 } -> x0 - v46 Imm(0) -> x1 - v47 FpCast { kind=IntToFp, value=v45 } -> d0 - v48 Imm(4602678819172646912) -> x0 - v49 Binop { op=fadd, lhs=v47, rhs=v48 } -> d0 - v50 Imm(4611686018427387904) -> x0 - v51 Binop { op=fmul, lhs=v49, rhs=v50 } -> d1 - v52 Imm(6) -> x1 - v53 Extend { value=v52, kind=I32 } -> x1 - v54 Imm(0) -> x2 - v55 FpCast { kind=IntToFp, value=v53 } -> d1 - v56 FpCast { kind=F64ToF32, value=v55 } -> d1 [f32] - v57 Imm(4616189618054758400) -> x1 - v58 FpCast { kind=F32ToF64, value=v56 } -> d1 - v59 Binop { op=fdiv, lhs=v58, rhs=v57 } -> d1 - v60 FpCast { kind=F64ToF32, value=v59 } -> d1 [f32] - v61 FpCast { kind=F32ToF64, value=v60 } -> d1 - v62 Fma { a=v49, b=v50, c=v61, neg_product=false, neg_addend=false } -> d0 - v63 Imm(0) -> x0 - v64 LoadLocal { off=-3, kind=F64 } -> d1 - v65 Imm(4616752568008179712) -> x0 - v66 Binop { op=fne, lhs=v62, rhs=v65 } -> x0 - terminator Bz { cond=v66, target=b6, fall=b5 } (exit_acc=v66) + v39 Imm(1) -> x0 + v40 Imm(1) -> x0 + v41 Imm(0) -> x1 + v42 FpCast { kind=IntToFp, value=v40 } -> d0 + v43 Imm(4602678819172646912) -> x0 + v44 Binop { op=fadd, lhs=v42, rhs=v43 } -> d0 + v45 Imm(4611686018427387904) -> x0 + v46 Binop { op=fmul, lhs=v44, rhs=v45 } -> d1 + v47 Imm(6) -> x1 + v48 Imm(6) -> x1 + v49 Imm(0) -> x2 + v50 FpCast { kind=IntToFp, value=v48 } -> d1 + v51 FpCast { kind=F64ToF32, value=v50 } -> d1 [f32] + v52 Imm(1082130432) -> x1 [f32] + v53 Binop { op=fdiv, lhs=v51, rhs=v52 } -> d1 [f32] + v54 FpCast { kind=F32ToF64, value=v53 } -> d1 + v55 Fma { a=v44, b=v45, c=v54, neg_product=false, neg_addend=false } -> d0 + v56 Imm(0) -> x0 + v57 LoadLocal { off=-3, kind=F64 } -> d1 + v58 Imm(4616752568008179712) -> x0 + v59 Binop { op=fne, lhs=v55, rhs=v58 } -> x0 + terminator Bz { cond=v59, target=b6, fall=b5 } (exit_acc=v59) block 5 start_pc=0 - v67 Imm(3) -> x0 - terminator Return(v67) (exit_acc=v67) + v60 Imm(3) -> x0 + terminator Return(v60) (exit_acc=v60) block 6 start_pc=0 - v68 Imm(0) -> x0 - terminator Return(v68) (exit_acc=v68) + v61 Imm(0) -> x0 + terminator Return(v61) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_unary_intrinsic.ssa b/tests/snapshots/ssa/fp_unary_intrinsic.ssa index 4152438ec..3c5c297b3 100644 --- a/tests/snapshots/ssa/fp_unary_intrinsic.ssa +++ b/tests/snapshots/ssa/fp_unary_intrinsic.ssa @@ -4,185 +4,166 @@ fn ent_pc=13 n_params=0 variadic=false locals=5 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4616189618054758400) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Intrinsic { kind=12, args=[v2] } -> d0 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v3 } -> d0 - v6 Binop { op=fne, lhs=v5, rhs=v4 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v1 Imm(1082130432) -> x0 [f32] + v2 Intrinsic { kind=12, args=[v1] } -> d0 [f32] + v3 Imm(1073741824) -> x0 [f32] + v4 Binop { op=fne, lhs=v2, rhs=v3 } -> x0 + terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) block 2 start_pc=0 - v8 Imm(4598175219545276416) -> x0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d0 [f32] - v10 Intrinsic { kind=12, args=[v9] } -> d0 [f32] - v11 Imm(4602678819172646912) -> x0 - v12 FpCast { kind=F32ToF64, value=v10 } -> d0 - v13 Binop { op=fne, lhs=v12, rhs=v11 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v6 Imm(1048576000) -> x0 [f32] + v7 Intrinsic { kind=12, args=[v6] } -> d0 [f32] + v8 Imm(1056964608) -> x0 [f32] + v9 Binop { op=fne, lhs=v7, rhs=v8 } -> x0 + terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) block 4 start_pc=0 - v15 Imm(4621256167635550208) -> x0 - v16 Intrinsic { kind=11, args=[v15] } -> d0 - v17 Imm(4613937818241073152) -> x0 - v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v11 Imm(4621256167635550208) -> x0 + v12 Intrinsic { kind=11, args=[v11] } -> d0 + v13 Imm(4613937818241073152) -> x0 + v14 Binop { op=fne, lhs=v12, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) block 5 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v15 Imm(3) -> x0 + terminator Return(v15) (exit_acc=v15) block 6 start_pc=0 - v20 Imm(4615063718147915776) -> x0 - v21 Fneg(v20) -> d0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d0 [f32] - v23 Intrinsic { kind=14, args=[v22] } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v23 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v20 } -> x0 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) + v16 Imm(1080033280) -> x0 [f32] + v17 Fneg(v16) -> d0 [f32] + v18 Intrinsic { kind=14, args=[v17] } -> d0 [f32] + v19 Binop { op=fne, lhs=v18, rhs=v16 } -> x0 + terminator Bz { cond=v19, target=b8, fall=b7 } (exit_acc=v19) block 7 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) + v20 Imm(4) -> x0 + terminator Return(v20) (exit_acc=v20) block 8 start_pc=0 - v27 Imm(4615063718147915776) -> x0 - v28 Fneg(v27) -> d0 - v29 Intrinsic { kind=13, args=[v28] } -> d0 - v30 Binop { op=fne, lhs=v29, rhs=v27 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v21 Imm(4615063718147915776) -> x0 + v22 Fneg(v21) -> d0 + v23 Intrinsic { kind=13, args=[v22] } -> d0 + v24 Binop { op=fne, lhs=v23, rhs=v21 } -> x0 + terminator Bz { cond=v24, target=b10, fall=b9 } (exit_acc=v24) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v25 Imm(5) -> x0 + terminator Return(v25) (exit_acc=v25) block 10 start_pc=0 - v32 Imm(4625196817309499392) -> x0 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 Intrinsic { kind=12, args=[v33] } -> d0 [f32] - v35 FpCast { kind=F32ToF64, value=v34 } -> d0 - v36 Imm(0) -> x0 - v37 LoadLocal { off=-1, kind=F64 } -> d1 - v38 Imm(4616189618054758400) -> x0 - v39 Binop { op=fne, lhs=v35, rhs=v38 } -> x0 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) + v26 Imm(1098907648) -> x0 [f32] + v27 Intrinsic { kind=12, args=[v26] } -> d0 [f32] + v28 FpCast { kind=F32ToF64, value=v27 } -> d0 + v29 Imm(0) -> x0 + v30 LoadLocal { off=-1, kind=F64 } -> d1 + v31 Imm(4616189618054758400) -> x0 + v32 Binop { op=fne, lhs=v28, rhs=v31 } -> x0 + terminator Bz { cond=v32, target=b12, fall=b11 } (exit_acc=v32) block 11 start_pc=0 - v40 Imm(6) -> x0 - terminator Return(v40) (exit_acc=v40) + v33 Imm(6) -> x0 + terminator Return(v33) (exit_acc=v33) block 12 start_pc=0 - v41 Imm(4613262278296967578) -> x0 - v42 Intrinsic { kind=15, args=[v41] } -> d0 - v43 Imm(4611686018427387904) -> x0 - v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x1 - v45 Imm(0) -> x0 - terminator Bnz { cond=v44, target=b29, fall=b13 } (exit_acc=v44) + v34 Imm(4613262278296967578) -> x0 + v35 Intrinsic { kind=15, args=[v34] } -> d0 + v36 Imm(4611686018427387904) -> x0 + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x1 + v38 Imm(0) -> x0 + terminator Bnz { cond=v37, target=b31, fall=b13 } (exit_acc=v37) block 13 start_pc=0 - v46 Imm(4612361558371493478) -> x0 - v47 Fneg(v46) -> d0 - v48 FpCast { kind=F64ToF32, value=v47 } -> d0 [f32] - v49 Intrinsic { kind=16, args=[v48] } -> d0 [f32] - v50 Imm(4613937818241073152) -> x0 - v51 Fneg(v50) -> d1 - v52 FpCast { kind=F32ToF64, value=v49 } -> d0 - v53 Binop { op=fne, lhs=v52, rhs=v51 } -> x1 - v54 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v53) + v39 Imm(1075000115) -> x0 [f32] + v40 Fneg(v39) -> d0 [f32] + v41 Intrinsic { kind=16, args=[v40] } -> d0 [f32] + v42 Imm(1077936128) -> x0 [f32] + v43 Fneg(v42) -> d1 [f32] + v44 Binop { op=fne, lhs=v41, rhs=v43 } -> x1 + v45 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v44) block 14 start_pc=0 - v55 Phi { incoming=[b29:v44, b13:v53], kind=I64 } -> x1 - v56 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v55, target=b16, fall=b15 } (exit_acc=v55) + v46 Phi { incoming=[b31:v37, b13:v44], kind=I64 } -> x1 + v47 LoadLocal { off=-3, kind=I64 } -> x0 + terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) block 15 start_pc=0 - v57 Imm(7) -> x0 - terminator Return(v57) (exit_acc=v57) + v48 Imm(7) -> x0 + terminator Return(v48) (exit_acc=v48) block 16 start_pc=0 - v58 Imm(4612361558371493478) -> x0 - v59 Intrinsic { kind=17, args=[v58] } -> d0 - v60 Imm(4613937818241073152) -> x0 - v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x1 - v62 Imm(0) -> x0 - terminator Bnz { cond=v61, target=b30, fall=b17 } (exit_acc=v61) + v49 Imm(4612361558371493478) -> x0 + v50 Intrinsic { kind=17, args=[v49] } -> d0 + v51 Imm(4613937818241073152) -> x0 + v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x1 + v53 Imm(0) -> x0 + terminator Bnz { cond=v52, target=b30, fall=b17 } (exit_acc=v52) block 17 start_pc=0 - v63 Imm(4613262278296967578) -> x0 - v64 Fneg(v63) -> d0 - v65 FpCast { kind=F64ToF32, value=v64 } -> d0 [f32] - v66 Intrinsic { kind=18, args=[v65] } -> d0 [f32] - v67 Imm(4611686018427387904) -> x0 - v68 Fneg(v67) -> d1 - v69 FpCast { kind=F32ToF64, value=v66 } -> d0 - v70 Binop { op=fne, lhs=v69, rhs=v68 } -> x1 - v71 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v70) + v54 Imm(1076677837) -> x0 [f32] + v55 Fneg(v54) -> d0 [f32] + v56 Intrinsic { kind=18, args=[v55] } -> d0 [f32] + v57 Imm(1073741824) -> x0 [f32] + v58 Fneg(v57) -> d1 [f32] + v59 Binop { op=fne, lhs=v56, rhs=v58 } -> x1 + v60 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v59) block 18 start_pc=0 - v72 Phi { incoming=[b30:v61, b17:v70], kind=I64 } -> x1 - v73 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v72, target=b20, fall=b19 } (exit_acc=v72) + v61 Phi { incoming=[b30:v52, b17:v59], kind=I64 } -> x1 + v62 LoadLocal { off=-4, kind=I64 } -> x0 + terminator Bz { cond=v61, target=b20, fall=b19 } (exit_acc=v61) block 19 start_pc=0 - v74 Imm(8) -> x0 - terminator Return(v74) (exit_acc=v74) + v63 Imm(8) -> x0 + terminator Return(v63) (exit_acc=v63) block 20 start_pc=0 - v75 Imm(4613262278296967578) -> x0 - v76 Fneg(v75) -> d0 - v77 Intrinsic { kind=19, args=[v76] } -> d0 - v78 Imm(4611686018427387904) -> x0 - v79 Fneg(v78) -> d1 - v80 Binop { op=fne, lhs=v77, rhs=v79 } -> x1 - v81 Imm(0) -> x0 - terminator Bnz { cond=v80, target=b31, fall=b21 } (exit_acc=v80) + v64 Imm(4613262278296967578) -> x0 + v65 Fneg(v64) -> d0 + v66 Intrinsic { kind=19, args=[v65] } -> d0 + v67 Imm(4611686018427387904) -> x0 + v68 Fneg(v67) -> d1 + v69 Binop { op=fne, lhs=v66, rhs=v68 } -> x1 + v70 Imm(0) -> x0 + terminator Bnz { cond=v69, target=b29, fall=b21 } (exit_acc=v69) block 21 start_pc=0 - v82 Imm(4613712638259704627) -> x0 - v83 FpCast { kind=F64ToF32, value=v82 } -> d0 [f32] - v84 Intrinsic { kind=20, args=[v83] } -> d0 [f32] - v85 Imm(4611686018427387904) -> x0 - v86 FpCast { kind=F32ToF64, value=v84 } -> d0 - v87 Binop { op=fne, lhs=v86, rhs=v85 } -> x1 - v88 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v87) + v71 Imm(1077516698) -> x0 [f32] + v72 Intrinsic { kind=20, args=[v71] } -> d0 [f32] + v73 Imm(1073741824) -> x0 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x1 + v75 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v74) block 22 start_pc=0 - v89 Phi { incoming=[b31:v80, b21:v87], kind=I64 } -> x1 - v90 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v89, target=b24, fall=b23 } (exit_acc=v89) + v76 Phi { incoming=[b29:v69, b21:v74], kind=I64 } -> x1 + v77 LoadLocal { off=-5, kind=I64 } -> x0 + terminator Bz { cond=v76, target=b24, fall=b23 } (exit_acc=v76) block 23 start_pc=0 - v91 Imm(9) -> x0 - terminator Return(v91) (exit_acc=v91) + v78 Imm(9) -> x0 + terminator Return(v78) (exit_acc=v78) block 24 start_pc=0 - v92 Imm(4611686018427387904) -> x0 - v93 FpCast { kind=F64ToF32, value=v92 } -> d0 [f32] - v94 Imm(0) -> x0 - v95 Imm(4625196817309499392) -> x0 - v96 Fneg(v95) -> d1 - v97 FpCast { kind=F64ToF32, value=v96 } -> d1 [f32] - v98 Intrinsic { kind=14, args=[v97] } -> d1 [f32] - v99 Intrinsic { kind=12, args=[v98] } -> d1 [f32] - v100 Imm(4616189618054758400) -> x0 - v101 FpCast { kind=F32ToF64, value=v99 } -> d1 - v102 Binop { op=fne, lhs=v101, rhs=v100 } -> x0 - terminator Bz { cond=v102, target=b26, fall=b25 } (exit_acc=v102) + v79 Imm(1073741824) -> x0 [f32] + v80 StoreLocal { off=-2, value=v79, kind=F32 } -> - + v81 Imm(1098907648) -> x0 [f32] + v82 Fneg(v81) -> d0 [f32] + v83 Intrinsic { kind=14, args=[v82] } -> d0 [f32] + v84 Intrinsic { kind=12, args=[v83] } -> d0 [f32] + v85 Imm(1082130432) -> x0 [f32] + v86 Binop { op=fne, lhs=v84, rhs=v85 } -> x0 + terminator Bz { cond=v86, target=b26, fall=b25 } (exit_acc=v86) block 25 start_pc=0 - v103 Imm(10) -> x0 - terminator Return(v103) (exit_acc=v103) + v87 Imm(10) -> x0 + terminator Return(v87) (exit_acc=v87) block 26 start_pc=0 - v104 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v105 Binop { op=fmul, lhs=v93, rhs=v93 } -> d0 [f32] - v106 Intrinsic { kind=12, args=[v105] } -> d0 [f32] - v107 Imm(4606281698874543309) -> x0 - v108 FpCast { kind=F32ToF64, value=v106 } -> d0 - v109 Binop { op=fadd, lhs=v108, rhs=v107 } -> d0 - v110 FpCast { kind=F64ToF32, value=v109 } -> d0 [f32] - v111 Intrinsic { kind=16, args=[v110] } -> d0 [f32] - v112 Imm(4611686018427387904) -> x0 - v113 FpCast { kind=F32ToF64, value=v111 } -> d0 - v114 Binop { op=fne, lhs=v113, rhs=v112 } -> x0 - terminator Bz { cond=v114, target=b28, fall=b27 } (exit_acc=v114) + v88 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v89 Binop { op=fmul, lhs=v88, rhs=v88 } -> d0 [f32] + v90 Intrinsic { kind=12, args=[v89] } -> d0 [f32] + v91 Imm(1063675494) -> x0 [f32] + v92 Binop { op=fadd, lhs=v90, rhs=v91 } -> d0 [f32] + v93 Intrinsic { kind=16, args=[v92] } -> d0 [f32] + v94 Imm(1073741824) -> x0 [f32] + v95 Binop { op=fne, lhs=v93, rhs=v94 } -> x0 + terminator Bz { cond=v95, target=b28, fall=b27 } (exit_acc=v95) block 27 start_pc=0 - v115 Imm(11) -> x0 - terminator Return(v115) (exit_acc=v115) + v96 Imm(11) -> x0 + terminator Return(v96) (exit_acc=v96) block 28 start_pc=0 - v116 Imm(0) -> x0 - terminator Return(v116) (exit_acc=v116) + v97 Imm(0) -> x0 + terminator Return(v97) (exit_acc=v97) block 29 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b22) block 30 start_pc=0 terminator Jmp(b18) block 31 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fts_and_fd_set_headers.ssa b/tests/snapshots/ssa/fts_and_fd_set_headers.ssa index a4e07363c..0bec7c3fb 100644 --- a/tests/snapshots/ssa/fts_and_fd_set_headers.ssa +++ b/tests/snapshots/ssa/fts_and_fd_set_headers.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=25 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-16) -> x0 @@ -31,53 +31,53 @@ fn ent_pc=0 n_params=0 variadic=false locals=25 terminator Return(v22) (exit_acc=v22) block 2 start_pc=0 v23 LoadLocal { off=-21, kind=I64 } -> x0 - v24 CallExt { binding_idx=23, args=[v18], fp_arg_mask=0x0 } -> x12 - v25 Imm(0) -> x0 - v26 LoadLocal { off=-22, kind=I64 } -> x0 - v27 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x0 + v24 CallExt { binding_idx=23, args=[v18], fp_arg_mask=0x0 } -> x0 + v25 Imm(0) -> x1 + v26 LoadLocal { off=-22, kind=I64 } -> x1 + v27 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x1 terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) block 3 start_pc=0 v28 Imm(2) -> x0 terminator Return(v28) (exit_acc=v28) block 4 start_pc=0 - v29 LoadLocal { off=-22, kind=I64 } -> x0 - v30 BinopI { op=add, lhs=v24, rhs_imm=98 } -> x0 - v31 Load { addr=v24, disp=98, kind=U16 } -> x0 - v32 BinopI { op=xor, lhs=v31, rhs_imm=1 } -> x0 - v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x0 - v34 BinopI { op=ne, lhs=v33, rhs_imm=0 } -> x0 + v29 LoadLocal { off=-22, kind=I64 } -> x1 + v30 BinopI { op=add, lhs=v24, rhs_imm=98 } -> x1 + v31 Load { addr=v24, disp=98, kind=U16 } -> x1 + v32 BinopI { op=xor, lhs=v31, rhs_imm=1 } -> x1 + v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x1 + v34 BinopI { op=ne, lhs=v33, rhs_imm=0 } -> x1 terminator Bz { cond=v34, target=b6, fall=b5 } (exit_acc=v34) block 5 start_pc=0 v35 Imm(3) -> x0 terminator Return(v35) (exit_acc=v35) block 6 start_pc=0 - v36 LoadLocal { off=-22, kind=I64 } -> x0 - v37 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x0 - v38 Load { addr=v24, disp=48, kind=I64 } -> x0 - v39 BinopI { op=eq, lhs=v38, rhs_imm=0 } -> x13 - v40 Imm(0) -> x0 + v36 LoadLocal { off=-22, kind=I64 } -> x1 + v37 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x1 + v38 Load { addr=v24, disp=48, kind=I64 } -> x1 + v39 BinopI { op=eq, lhs=v38, rhs_imm=0 } -> x2 + v40 Imm(0) -> x1 terminator Bnz { cond=v39, target=b13, fall=b7 } (exit_acc=v39) block 7 start_pc=0 - v41 LoadLocal { off=-22, kind=I64 } -> x0 - v42 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x0 - v43 Load { addr=v24, disp=48, kind=I64 } -> x0 - v44 Imm(0) -> x1 - v45 Load { addr=v43, disp=0, kind=I8 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=46 } -> x13 - v47 Imm(0) -> x0 + v41 LoadLocal { off=-22, kind=I64 } -> x1 + v42 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x1 + v43 Load { addr=v24, disp=48, kind=I64 } -> x1 + v44 Imm(0) -> x2 + v45 Load { addr=v43, disp=0, kind=I8 } -> x1 + v46 BinopI { op=ne, lhs=v45, rhs_imm=46 } -> x2 + v47 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v46) block 8 start_pc=0 - v48 Phi { incoming=[b13:v39, b7:v46], kind=I64 } -> x13 - v49 LoadLocal { off=-25, kind=I64 } -> x0 + v48 Phi { incoming=[b13:v39, b7:v46], kind=I64 } -> x2 + v49 LoadLocal { off=-25, kind=I64 } -> x1 terminator Bz { cond=v48, target=b10, fall=b9 } (exit_acc=v48) block 9 start_pc=0 v50 Imm(4) -> x0 terminator Return(v50) (exit_acc=v50) block 10 start_pc=0 - v51 LoadLocal { off=-22, kind=I64 } -> x0 - v52 BinopI { op=add, lhs=v24, rhs_imm=64 } -> x0 - v53 Load { addr=v24, disp=64, kind=U16 } -> x13 - v54 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x0 + v51 LoadLocal { off=-22, kind=I64 } -> x1 + v52 BinopI { op=add, lhs=v24, rhs_imm=64 } -> x1 + v53 Load { addr=v24, disp=64, kind=U16 } -> x12 + v54 BinopI { op=add, lhs=v24, rhs_imm=48 } -> x1 v55 Load { addr=v24, disp=48, kind=I64 } -> x7 v56 CallExt { binding_idx=30, args=[v55], fp_arg_mask=0x0 } -> x0 v57 BinopI { op=and, lhs=v56, rhs_imm=65535 } -> x0 diff --git a/tests/snapshots/ssa/ftw_walk.ssa b/tests/snapshots/ssa/ftw_walk.ssa index 1a4261b17..d3efaf863 100644 --- a/tests/snapshots/ssa/ftw_walk.ssa +++ b/tests/snapshots/ssa/ftw_walk.ssa @@ -28,7 +28,7 @@ fn ent_pc=6 n_params=3 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=7 --- ; name=main fn ent_pc=7 n_params=0 variadic=false locals=43 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-3) -> x0 @@ -44,18 +44,8 @@ fn ent_pc=7 n_params=0 variadic=false locals=43 block 2 start_pc=0 v8 Imm(0) -> x3 v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) + terminator Jmp(b6) (exit_acc=v8) block 3 start_pc=0 - v10 Phi { incoming=[b2:v8, b4:v14], kind=I64 } -> x3 - v11 Extend { value=v10, kind=I32 } -> x0 - v12 BinopI { op=lt, lhs=v11, rhs_imm=3 } -> x0 - terminator Bz { cond=v12, target=b6, fall=b5 } (exit_acc=v12) - block 4 start_pc=0 - v13 Extend { value=v10, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x3 - v15 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v14) - block 5 start_pc=0 v16 LocalAddr(-35) -> x7 v17 Imm(256) -> x6 v18 ImmData(120) -> x2 @@ -64,12 +54,26 @@ fn ent_pc=7 n_params=0 variadic=false locals=43 v21 CallExt { binding_idx=25, args=[v16, v17, v18, v19, v20], fp_arg_mask=0x0 } -> x0 v22 LocalAddr(-35) -> x7 v23 ImmData(127) -> x6 - v24 CallExt { binding_idx=33, args=[v22, v23], fp_arg_mask=0x0 } -> x12 + v24 CallExt { binding_idx=33, args=[v22, v23], fp_arg_mask=0x0 } -> x7 v25 Imm(0) -> x0 v26 LoadLocal { off=-37, kind=I64 } -> x0 v27 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + terminator Bnz { cond=v27, target=b14, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 + v37 LoadLocal { off=-37, kind=I64 } -> x0 + v38 CallExt { binding_idx=35, args=[v24], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b5) (exit_acc=v38) + block 5 start_pc=0 + v13 Extend { value=v10, kind=I32 } -> x0 + v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x3 + v15 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v14) block 6 start_pc=0 + v10 Phi { incoming=[b2:v8, b5:v14], kind=I64 } -> x3 + v11 Extend { value=v10, kind=I32 } -> x0 + v12 BinopI { op=lt, lhs=v11, rhs_imm=3 } -> x0 + terminator Bnz { cond=v12, target=b3, fall=b7 } (exit_acc=v12) + block 7 start_pc=0 v28 LocalAddr(-3) -> x7 v29 ImmCode(ent_pc=6) -> x6 v30 Imm(16) -> x2 @@ -78,38 +82,34 @@ fn ent_pc=7 n_params=0 variadic=false locals=43 v33 Extend { value=v31, kind=I32 } -> x0 v34 BinopI { op=eq, lhs=v33, rhs_imm=0 } -> x1 v35 Imm(0) -> x0 - terminator Bz { cond=v34, target=b14, fall=b9 } (exit_acc=v34) - block 7 start_pc=0 - v36 Imm(2) -> x0 - terminator Return(v36) (exit_acc=v36) + terminator Bz { cond=v34, target=b13, fall=b8 } (exit_acc=v34) block 8 start_pc=0 - v37 LoadLocal { off=-37, kind=I64 } -> x0 - v38 CallExt { binding_idx=35, args=[v24], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b4) (exit_acc=v38) - block 9 start_pc=0 v39 ImmData(72) -> x0 v40 Load { addr=v39, disp=0, kind=I32 } -> x0 v41 BinopI { op=ge, lhs=v40, rhs_imm=4 } -> x1 v42 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v41) - block 10 start_pc=0 - v43 Phi { incoming=[b14:v34, b9:v41], kind=I64 } -> x1 + terminator Jmp(b9) (exit_acc=v41) + block 9 start_pc=0 + v43 Phi { incoming=[b13:v34, b8:v41], kind=I64 } -> x1 v44 LoadLocal { off=-42, kind=I64 } -> x0 - terminator Bz { cond=v43, target=b12, fall=b11 } (exit_acc=v43) - block 11 start_pc=0 + terminator Bz { cond=v43, target=b12, fall=b10 } (exit_acc=v43) + block 10 start_pc=0 v45 Imm(0) -> x1 v46 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v45) + terminator Jmp(b11) (exit_acc=v45) + block 11 start_pc=0 + v49 Phi { incoming=[b10:v45, b12:v47], kind=I64 } -> x1 + v50 LoadLocal { off=-43, kind=I64 } -> x0 + terminator Return(v49) (exit_acc=v49) block 12 start_pc=0 v47 Imm(3) -> x1 v48 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v47) + terminator Jmp(b11) (exit_acc=v47) block 13 start_pc=0 - v49 Phi { incoming=[b11:v45, b12:v47], kind=I64 } -> x1 - v50 LoadLocal { off=-43, kind=I64 } -> x0 - terminator Return(v49) (exit_acc=v49) + terminator Jmp(b9) block 14 start_pc=0 - terminator Jmp(b10) + v36 Imm(2) -> x0 + terminator Return(v36) (exit_acc=v36) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/func_name_array.ssa b/tests/snapshots/ssa/func_name_array.ssa index 58ec2ff52..4512e824b 100644 --- a/tests/snapshots/ssa/func_name_array.ssa +++ b/tests/snapshots/ssa/func_name_array.ssa @@ -7,43 +7,43 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v1 ImmData(8) -> x0 v2 Imm(0) -> x1 v3 Imm(0) -> x1 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(0) -> x2 v6 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v5) + terminator Jmp(b4) (exit_acc=v5) + block 2 start_pc=0 + v14 LoadLocal { off=-1, kind=I64 } -> x6 + v15 Extend { value=v7, kind=I32 } -> x6 + v16 Binop { op=add, lhs=v1, rhs=v8 } -> x6 + v17 Load { addr=v16, disp=0, kind=I8 } -> x6 + v18 ImmData(23) -> x7 + v19 Binop { op=add, lhs=v18, rhs=v8 } -> x7 + v20 Load { addr=v19, disp=0, kind=I8 } -> x7 + v21 Binop { op=ne, lhs=v17, rhs=v20 } -> x6 + terminator Bnz { cond=v21, target=b6, fall=b3 } (exit_acc=v21) block 3 start_pc=0 - v7 Phi { incoming=[b2:v5, b4:v12], kind=I64 } -> x2 + v11 Extend { value=v7, kind=I32 } -> x2 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x2 + v13 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v12) + block 4 start_pc=0 + v7 Phi { incoming=[b1:v5, b3:v12], kind=I64 } -> x2 v8 Extend { value=v7, kind=I32 } -> x1 v9 Imm(5) -> x6 - v10 BinopI { op=lt, lhs=v8, rhs_imm=5 } -> x1 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) - block 4 start_pc=0 - v11 Extend { value=v7, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x2 - v13 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v12) + v10 BinopI { op=lt, lhs=v8, rhs_imm=5 } -> x6 + terminator Bnz { cond=v10, target=b2, fall=b5 } (exit_acc=v10) block 5 start_pc=0 - v14 LoadLocal { off=-1, kind=I64 } -> x1 - v15 Extend { value=v7, kind=I32 } -> x1 - v16 Binop { op=add, lhs=v1, rhs=v15 } -> x6 - v17 Load { addr=v16, disp=0, kind=I8 } -> x6 - v18 ImmData(23) -> x7 - v19 Binop { op=add, lhs=v18, rhs=v15 } -> x1 - v20 Load { addr=v19, disp=0, kind=I8 } -> x1 - v21 Binop { op=ne, lhs=v17, rhs=v20 } -> x1 - terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) - block 6 start_pc=0 v22 Imm(0) -> x0 terminator Return(v22) (exit_acc=v22) - block 7 start_pc=0 + block 6 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) + block 7 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 8 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/func_name_in_initializer.ssa b/tests/snapshots/ssa/func_name_in_initializer.ssa index ea2792728..3f35f37a5 100644 --- a/tests/snapshots/ssa/func_name_in_initializer.ssa +++ b/tests/snapshots/ssa/func_name_in_initializer.ssa @@ -10,13 +10,25 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b6, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -24,27 +36,15 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 LoadLocal { off=3, kind=I64 } -> x1 v19 Load { addr=v6, disp=0, kind=I8 } -> x1 v20 Binop { op=eq, lhs=v17, rhs=v19 } -> x0 terminator Return(v20) (exit_acc=v20) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b6:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=direct fn ent_pc=1 n_params=0 variadic=false locals=0 diff --git a/tests/snapshots/ssa/function_macro.ssa b/tests/snapshots/ssa/function_macro.ssa index dfae0a469..639f63228 100644 --- a/tests/snapshots/ssa/function_macro.ssa +++ b/tests/snapshots/ssa/function_macro.ssa @@ -10,13 +10,25 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b8, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -24,40 +36,28 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 BinopI { op=eq, lhs=v17, rhs_imm=0 } -> x0 v19 Imm(0) -> x2 v20 Imm(0) -> x1 - terminator Bz { cond=v18, target=b9, fall=b6 } (exit_acc=v18) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b8:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 + terminator Bz { cond=v18, target=b9, fall=b7 } (exit_acc=v18) + block 7 start_pc=0 v29 LoadLocal { off=3, kind=I64 } -> x0 v30 Load { addr=v6, disp=0, kind=I8 } -> x0 v31 BinopI { op=eq, lhs=v30, rhs_imm=0 } -> x0 v32 BinopI { op=ne, lhs=v31, rhs_imm=0 } -> x2 v33 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v32) - block 7 start_pc=0 - v34 Phi { incoming=[b9:v19, b6:v32], kind=I64 } -> x2 + terminator Jmp(b8) (exit_acc=v32) + block 8 start_pc=0 + v34 Phi { incoming=[b9:v19, b7:v32], kind=I64 } -> x2 v35 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v34) (exit_acc=v34) - block 8 start_pc=0 - terminator Jmp(b5) block 9 start_pc=0 - terminator Jmp(b7) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=helper_one fn ent_pc=1 n_params=0 variadic=false locals=5 diff --git a/tests/snapshots/ssa/function_type_typedef_declaration.ssa b/tests/snapshots/ssa/function_type_typedef_declaration.ssa index 240d65677..4a2d5262e 100644 --- a/tests/snapshots/ssa/function_type_typedef_declaration.ssa +++ b/tests/snapshots/ssa/function_type_typedef_declaration.ssa @@ -56,35 +56,29 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(3) -> x0 - v2 Imm(4) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=7 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(4) -> x0 + v3 Imm(3) -> x0 + v4 Imm(0) -> x0 + v5 Imm(4) -> x0 + v6 Imm(0) -> x0 + v7 Imm(7) -> x0 + v8 Imm(30064771072) -> x0 + v9 Imm(7) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(10) -> x0 - v13 Imm(4) -> x1 - v14 Extend { value=v12, kind=I32 } -> x2 - v15 Imm(0) -> x2 - v16 Extend { value=v13, kind=I32 } -> x2 - v17 Imm(0) -> x2 - v18 Binop { op=sub, lhs=v12, rhs=v13 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=6 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) - block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) - block 4 start_pc=0 + v13 Imm(4) -> x0 + v14 Imm(10) -> x0 + v15 Imm(0) -> x0 + v16 Imm(4) -> x0 + v17 Imm(0) -> x0 + v18 Imm(6) -> x0 + v19 Imm(25769803776) -> x0 + v20 Imm(6) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 v23 ImmCode(ent_pc=0) -> x0 v24 Imm(0) -> x1 v25 Imm(2) -> x7 @@ -94,21 +88,21 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 v30 Extend { value=v28, kind=I32 } -> x0 v31 BinopI { op=ne, lhs=v30, rhs_imm=7 } -> x0 - terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) - block 5 start_pc=0 + terminator Bz { cond=v31, target=b4, fall=b3 } (exit_acc=v31) + block 3 start_pc=0 v32 Imm(3) -> x0 terminator Return(v32) (exit_acc=v32) - block 6 start_pc=0 + block 4 start_pc=0 v33 ImmCode(ent_pc=1) -> x7 v34 Imm(9) -> x6 v35 Imm(2) -> x2 v36 Call { target_pc=2, args=[v33, v34, v35], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 v37 BinopI { op=ne, lhs=v36, rhs_imm=7 } -> x0 - terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) - block 7 start_pc=0 + terminator Bz { cond=v37, target=b6, fall=b5 } (exit_acc=v37) + block 5 start_pc=0 v38 Imm(4) -> x0 terminator Return(v38) (exit_acc=v38) - block 8 start_pc=0 + block 6 start_pc=0 v39 ImmCode(ent_pc=1) -> x0 v40 Imm(0) -> x1 v41 Imm(8) -> x7 @@ -118,13 +112,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x1 v46 Extend { value=v44, kind=I32 } -> x0 v47 BinopI { op=ne, lhs=v46, rhs_imm=5 } -> x0 - terminator Bz { cond=v47, target=b10, fall=b9 } (exit_acc=v47) - block 9 start_pc=0 + terminator Bz { cond=v47, target=b8, fall=b7 } (exit_acc=v47) + block 7 start_pc=0 v48 Imm(5) -> x0 terminator Return(v48) (exit_acc=v48) - block 10 start_pc=0 + block 8 start_pc=0 v49 Imm(0) -> x0 terminator Return(v49) (exit_acc=v49) + block 9 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 10 start_pc=0 + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/gcc_atomics.ssa b/tests/snapshots/ssa/gcc_atomics.ssa index b1bc10deb..5f95268ff 100644 --- a/tests/snapshots/ssa/gcc_atomics.ssa +++ b/tests/snapshots/ssa/gcc_atomics.ssa @@ -13,62 +13,56 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v5 BinopI { op=eq, lhs=v4, rhs_imm=10 } -> x0 v6 BinopI { op=eq, lhs=v5, rhs_imm=0 } -> x1 v7 Imm(0) -> x0 - terminator Bz { cond=v6, target=b230, fall=b4 } (exit_acc=v6) + terminator Bz { cond=v6, target=b234, fall=b2 } (exit_acc=v6) block 2 start_pc=0 - v8 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) - block 3 start_pc=0 - v9 LocalAddr(-1) -> x0 - v10 Imm(20) -> x1 - v11 Store { addr=v9, disp=0, value=v10, kind=I32 } -> - - v12 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v12) - block 4 start_pc=0 v13 ImmData(24) -> x0 v14 Load { addr=v13, disp=0, kind=I32 } -> x0 v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x1 v16 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v15) - block 5 start_pc=0 - v17 Phi { incoming=[b230:v6, b4:v15], kind=I64 } -> x1 + terminator Jmp(b3) (exit_acc=v15) + block 3 start_pc=0 + v17 Phi { incoming=[b234:v6, b2:v15], kind=I64 } -> x1 v18 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v17, target=b7, fall=b6 } (exit_acc=v17) - block 6 start_pc=0 + terminator Bz { cond=v17, target=b5, fall=b4 } (exit_acc=v17) + block 4 start_pc=0 v19 ImmData(24) -> x0 v20 Imm(1) -> x1 v21 Store { addr=v19, disp=0, value=v20, kind=I32 } -> - - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b5) (exit_acc=v21) + block 5 start_pc=0 + v8 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v8) + block 6 start_pc=0 + v9 LocalAddr(-1) -> x0 + v10 Imm(20) -> x1 + v11 Store { addr=v9, disp=0, value=v10, kind=I32 } -> - + v12 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v12) block 7 start_pc=0 - terminator Jmp(b2) - block 8 start_pc=0 v22 LoadLocal { off=-1, kind=I32 } -> x0 v23 BinopI { op=eq, lhs=v22, rhs_imm=20 } -> x0 v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x1 v25 Imm(0) -> x0 - terminator Bz { cond=v24, target=b231, fall=b11 } (exit_acc=v24) - block 9 start_pc=0 - v26 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v26) - block 10 start_pc=0 - terminator Jmp(b15) - block 11 start_pc=0 + terminator Bz { cond=v24, target=b233, fall=b8 } (exit_acc=v24) + block 8 start_pc=0 v27 ImmData(24) -> x0 v28 Load { addr=v27, disp=0, kind=I32 } -> x0 v29 BinopI { op=eq, lhs=v28, rhs_imm=0 } -> x1 v30 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v29) - block 12 start_pc=0 - v31 Phi { incoming=[b231:v24, b11:v29], kind=I64 } -> x1 + terminator Jmp(b9) (exit_acc=v29) + block 9 start_pc=0 + v31 Phi { incoming=[b233:v24, b8:v29], kind=I64 } -> x1 v32 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v31, target=b14, fall=b13 } (exit_acc=v31) - block 13 start_pc=0 + terminator Bz { cond=v31, target=b11, fall=b10 } (exit_acc=v31) + block 10 start_pc=0 v33 ImmData(24) -> x0 v34 Imm(2) -> x1 v35 Store { addr=v33, disp=0, value=v34, kind=I32 } -> - - terminator Jmp(b14) (exit_acc=v35) - block 14 start_pc=0 - terminator Jmp(b9) - block 15 start_pc=0 + terminator Jmp(b11) (exit_acc=v35) + block 11 start_pc=0 + v26 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v26) + block 12 start_pc=0 v36 LocalAddr(-1) -> x0 v37 Imm(30) -> x1 v38 AtomicRmw { op=Xchg, addr=v36, value=v37, width=4 } -> x0 @@ -77,60 +71,54 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v41 BinopI { op=eq, lhs=v40, rhs_imm=20 } -> x0 v42 BinopI { op=eq, lhs=v41, rhs_imm=0 } -> x1 v43 Imm(0) -> x0 - terminator Bz { cond=v42, target=b232, fall=b18 } (exit_acc=v42) - block 16 start_pc=0 - v44 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v44) - block 17 start_pc=0 - terminator Jmp(b22) - block 18 start_pc=0 + terminator Bz { cond=v42, target=b232, fall=b13 } (exit_acc=v42) + block 13 start_pc=0 v45 ImmData(24) -> x0 v46 Load { addr=v45, disp=0, kind=I32 } -> x0 v47 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x1 v48 Imm(0) -> x0 - terminator Jmp(b19) (exit_acc=v47) - block 19 start_pc=0 - v49 Phi { incoming=[b232:v42, b18:v47], kind=I64 } -> x1 + terminator Jmp(b14) (exit_acc=v47) + block 14 start_pc=0 + v49 Phi { incoming=[b232:v42, b13:v47], kind=I64 } -> x1 v50 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v49, target=b21, fall=b20 } (exit_acc=v49) - block 20 start_pc=0 + terminator Bz { cond=v49, target=b16, fall=b15 } (exit_acc=v49) + block 15 start_pc=0 v51 ImmData(24) -> x0 v52 Imm(3) -> x1 v53 Store { addr=v51, disp=0, value=v52, kind=I32 } -> - - terminator Jmp(b21) (exit_acc=v53) - block 21 start_pc=0 - terminator Jmp(b16) - block 22 start_pc=0 + terminator Jmp(b16) (exit_acc=v53) + block 16 start_pc=0 + v44 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v44) + block 17 start_pc=0 v54 LoadLocal { off=-1, kind=I32 } -> x0 v55 BinopI { op=eq, lhs=v54, rhs_imm=30 } -> x0 v56 BinopI { op=eq, lhs=v55, rhs_imm=0 } -> x1 v57 Imm(0) -> x0 - terminator Bz { cond=v56, target=b233, fall=b25 } (exit_acc=v56) - block 23 start_pc=0 - v58 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v58) - block 24 start_pc=0 - v59 Imm(100) -> x0 - v60 StoreLocal { off=-1, value=v59, kind=I32 } -> - - terminator Jmp(b29) (exit_acc=v60) - block 25 start_pc=0 + terminator Bz { cond=v56, target=b231, fall=b18 } (exit_acc=v56) + block 18 start_pc=0 v61 ImmData(24) -> x0 v62 Load { addr=v61, disp=0, kind=I32 } -> x0 v63 BinopI { op=eq, lhs=v62, rhs_imm=0 } -> x1 v64 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v63) - block 26 start_pc=0 - v65 Phi { incoming=[b233:v56, b25:v63], kind=I64 } -> x1 + terminator Jmp(b19) (exit_acc=v63) + block 19 start_pc=0 + v65 Phi { incoming=[b231:v56, b18:v63], kind=I64 } -> x1 v66 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v65, target=b28, fall=b27 } (exit_acc=v65) - block 27 start_pc=0 + terminator Bz { cond=v65, target=b21, fall=b20 } (exit_acc=v65) + block 20 start_pc=0 v67 ImmData(24) -> x0 v68 Imm(4) -> x1 v69 Store { addr=v67, disp=0, value=v68, kind=I32 } -> - - terminator Jmp(b28) (exit_acc=v69) - block 28 start_pc=0 - terminator Jmp(b23) - block 29 start_pc=0 + terminator Jmp(b21) (exit_acc=v69) + block 21 start_pc=0 + v58 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v58) + block 22 start_pc=0 + v59 Imm(100) -> x0 + v60 StoreLocal { off=-1, value=v59, kind=I32 } -> - + terminator Jmp(b23) (exit_acc=v60) + block 23 start_pc=0 v70 LocalAddr(-1) -> x0 v71 Imm(5) -> x1 v72 AtomicRmw { op=Add, addr=v70, value=v71, width=4 } -> x0 @@ -139,42 +127,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v75 BinopI { op=eq, lhs=v74, rhs_imm=100 } -> x0 v76 Imm(0) -> x2 v77 Imm(0) -> x1 - terminator Bz { cond=v75, target=b234, fall=b32 } (exit_acc=v75) - block 30 start_pc=0 - v78 Imm(0) -> x0 - terminator Jmp(b31) (exit_acc=v78) - block 31 start_pc=0 - terminator Jmp(b38) - block 32 start_pc=0 + terminator Bz { cond=v75, target=b230, fall=b24 } (exit_acc=v75) + block 24 start_pc=0 v79 LoadLocal { off=-1, kind=I32 } -> x0 v80 BinopI { op=eq, lhs=v79, rhs_imm=105 } -> x0 v81 BinopI { op=ne, lhs=v80, rhs_imm=0 } -> x2 v82 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v81) - block 33 start_pc=0 - v83 Phi { incoming=[b234:v76, b32:v81], kind=I64 } -> x2 + terminator Jmp(b25) (exit_acc=v81) + block 25 start_pc=0 + v83 Phi { incoming=[b230:v76, b24:v81], kind=I64 } -> x2 v84 LoadLocal { off=-9, kind=I64 } -> x0 v85 BinopI { op=eq, lhs=v83, rhs_imm=0 } -> x1 v86 Imm(0) -> x0 - terminator Bz { cond=v85, target=b235, fall=b34 } (exit_acc=v85) - block 34 start_pc=0 + terminator Bz { cond=v85, target=b229, fall=b26 } (exit_acc=v85) + block 26 start_pc=0 v87 ImmData(24) -> x0 v88 Load { addr=v87, disp=0, kind=I32 } -> x0 v89 BinopI { op=eq, lhs=v88, rhs_imm=0 } -> x1 v90 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v89) - block 35 start_pc=0 - v91 Phi { incoming=[b235:v85, b34:v89], kind=I64 } -> x1 + terminator Jmp(b27) (exit_acc=v89) + block 27 start_pc=0 + v91 Phi { incoming=[b229:v85, b26:v89], kind=I64 } -> x1 v92 LoadLocal { off=-8, kind=I64 } -> x0 - terminator Bz { cond=v91, target=b37, fall=b36 } (exit_acc=v91) - block 36 start_pc=0 + terminator Bz { cond=v91, target=b29, fall=b28 } (exit_acc=v91) + block 28 start_pc=0 v93 ImmData(24) -> x0 v94 Imm(5) -> x1 v95 Store { addr=v93, disp=0, value=v94, kind=I32 } -> - - terminator Jmp(b37) (exit_acc=v95) - block 37 start_pc=0 - terminator Jmp(b30) - block 38 start_pc=0 + terminator Jmp(b29) (exit_acc=v95) + block 29 start_pc=0 + v78 Imm(0) -> x0 + terminator Jmp(b30) (exit_acc=v78) + block 30 start_pc=0 v96 LocalAddr(-1) -> x0 v97 Imm(5) -> x1 v98 AtomicRmw { op=Sub, addr=v96, value=v97, width=4 } -> x0 @@ -183,44 +167,42 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v101 BinopI { op=eq, lhs=v100, rhs_imm=105 } -> x0 v102 Imm(0) -> x2 v103 Imm(0) -> x1 - terminator Bz { cond=v101, target=b236, fall=b41 } (exit_acc=v101) - block 39 start_pc=0 - v104 Imm(0) -> x0 - terminator Jmp(b40) (exit_acc=v104) - block 40 start_pc=0 - v105 Imm(240) -> x0 - v106 StoreLocal { off=-1, value=v105, kind=I32 } -> - - terminator Jmp(b47) (exit_acc=v106) - block 41 start_pc=0 + terminator Bz { cond=v101, target=b228, fall=b31 } (exit_acc=v101) + block 31 start_pc=0 v107 LoadLocal { off=-1, kind=I32 } -> x0 v108 BinopI { op=eq, lhs=v107, rhs_imm=100 } -> x0 v109 BinopI { op=ne, lhs=v108, rhs_imm=0 } -> x2 v110 Imm(0) -> x0 - terminator Jmp(b42) (exit_acc=v109) - block 42 start_pc=0 - v111 Phi { incoming=[b236:v102, b41:v109], kind=I64 } -> x2 + terminator Jmp(b32) (exit_acc=v109) + block 32 start_pc=0 + v111 Phi { incoming=[b228:v102, b31:v109], kind=I64 } -> x2 v112 LoadLocal { off=-11, kind=I64 } -> x0 v113 BinopI { op=eq, lhs=v111, rhs_imm=0 } -> x1 v114 Imm(0) -> x0 - terminator Bz { cond=v113, target=b237, fall=b43 } (exit_acc=v113) - block 43 start_pc=0 + terminator Bz { cond=v113, target=b227, fall=b33 } (exit_acc=v113) + block 33 start_pc=0 v115 ImmData(24) -> x0 v116 Load { addr=v115, disp=0, kind=I32 } -> x0 v117 BinopI { op=eq, lhs=v116, rhs_imm=0 } -> x1 v118 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v117) - block 44 start_pc=0 - v119 Phi { incoming=[b237:v113, b43:v117], kind=I64 } -> x1 + terminator Jmp(b34) (exit_acc=v117) + block 34 start_pc=0 + v119 Phi { incoming=[b227:v113, b33:v117], kind=I64 } -> x1 v120 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v119, target=b46, fall=b45 } (exit_acc=v119) - block 45 start_pc=0 + terminator Bz { cond=v119, target=b36, fall=b35 } (exit_acc=v119) + block 35 start_pc=0 v121 ImmData(24) -> x0 v122 Imm(6) -> x1 v123 Store { addr=v121, disp=0, value=v122, kind=I32 } -> - - terminator Jmp(b46) (exit_acc=v123) - block 46 start_pc=0 - terminator Jmp(b39) - block 47 start_pc=0 + terminator Jmp(b36) (exit_acc=v123) + block 36 start_pc=0 + v104 Imm(0) -> x0 + terminator Jmp(b37) (exit_acc=v104) + block 37 start_pc=0 + v105 Imm(240) -> x0 + v106 StoreLocal { off=-1, value=v105, kind=I32 } -> - + terminator Jmp(b38) (exit_acc=v106) + block 38 start_pc=0 v124 LocalAddr(-1) -> x0 v125 Imm(60) -> x1 v126 AtomicRmw { op=And, addr=v124, value=v125, width=4 } -> x0 @@ -229,42 +211,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v129 BinopI { op=eq, lhs=v128, rhs_imm=240 } -> x0 v130 Imm(0) -> x2 v131 Imm(0) -> x1 - terminator Bz { cond=v129, target=b238, fall=b50 } (exit_acc=v129) - block 48 start_pc=0 - v132 Imm(0) -> x0 - terminator Jmp(b49) (exit_acc=v132) - block 49 start_pc=0 - terminator Jmp(b56) - block 50 start_pc=0 + terminator Bz { cond=v129, target=b226, fall=b39 } (exit_acc=v129) + block 39 start_pc=0 v133 LoadLocal { off=-1, kind=I32 } -> x0 v134 BinopI { op=eq, lhs=v133, rhs_imm=48 } -> x0 v135 BinopI { op=ne, lhs=v134, rhs_imm=0 } -> x2 v136 Imm(0) -> x0 - terminator Jmp(b51) (exit_acc=v135) - block 51 start_pc=0 - v137 Phi { incoming=[b238:v130, b50:v135], kind=I64 } -> x2 + terminator Jmp(b40) (exit_acc=v135) + block 40 start_pc=0 + v137 Phi { incoming=[b226:v130, b39:v135], kind=I64 } -> x2 v138 LoadLocal { off=-13, kind=I64 } -> x0 v139 BinopI { op=eq, lhs=v137, rhs_imm=0 } -> x1 v140 Imm(0) -> x0 - terminator Bz { cond=v139, target=b239, fall=b52 } (exit_acc=v139) - block 52 start_pc=0 + terminator Bz { cond=v139, target=b225, fall=b41 } (exit_acc=v139) + block 41 start_pc=0 v141 ImmData(24) -> x0 v142 Load { addr=v141, disp=0, kind=I32 } -> x0 v143 BinopI { op=eq, lhs=v142, rhs_imm=0 } -> x1 v144 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v143) - block 53 start_pc=0 - v145 Phi { incoming=[b239:v139, b52:v143], kind=I64 } -> x1 + terminator Jmp(b42) (exit_acc=v143) + block 42 start_pc=0 + v145 Phi { incoming=[b225:v139, b41:v143], kind=I64 } -> x1 v146 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Bz { cond=v145, target=b55, fall=b54 } (exit_acc=v145) - block 54 start_pc=0 + terminator Bz { cond=v145, target=b44, fall=b43 } (exit_acc=v145) + block 43 start_pc=0 v147 ImmData(24) -> x0 v148 Imm(7) -> x1 v149 Store { addr=v147, disp=0, value=v148, kind=I32 } -> - - terminator Jmp(b55) (exit_acc=v149) - block 55 start_pc=0 - terminator Jmp(b48) - block 56 start_pc=0 + terminator Jmp(b44) (exit_acc=v149) + block 44 start_pc=0 + v132 Imm(0) -> x0 + terminator Jmp(b45) (exit_acc=v132) + block 45 start_pc=0 v150 LocalAddr(-1) -> x0 v151 Imm(15) -> x1 v152 AtomicRmw { op=Or, addr=v150, value=v151, width=4 } -> x0 @@ -273,42 +251,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v155 BinopI { op=eq, lhs=v154, rhs_imm=48 } -> x0 v156 Imm(0) -> x2 v157 Imm(0) -> x1 - terminator Bz { cond=v155, target=b240, fall=b59 } (exit_acc=v155) - block 57 start_pc=0 - v158 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v158) - block 58 start_pc=0 - terminator Jmp(b65) - block 59 start_pc=0 + terminator Bz { cond=v155, target=b224, fall=b46 } (exit_acc=v155) + block 46 start_pc=0 v159 LoadLocal { off=-1, kind=I32 } -> x0 v160 BinopI { op=eq, lhs=v159, rhs_imm=63 } -> x0 v161 BinopI { op=ne, lhs=v160, rhs_imm=0 } -> x2 v162 Imm(0) -> x0 - terminator Jmp(b60) (exit_acc=v161) - block 60 start_pc=0 - v163 Phi { incoming=[b240:v156, b59:v161], kind=I64 } -> x2 + terminator Jmp(b47) (exit_acc=v161) + block 47 start_pc=0 + v163 Phi { incoming=[b224:v156, b46:v161], kind=I64 } -> x2 v164 LoadLocal { off=-15, kind=I64 } -> x0 v165 BinopI { op=eq, lhs=v163, rhs_imm=0 } -> x1 v166 Imm(0) -> x0 - terminator Bz { cond=v165, target=b241, fall=b61 } (exit_acc=v165) - block 61 start_pc=0 + terminator Bz { cond=v165, target=b223, fall=b48 } (exit_acc=v165) + block 48 start_pc=0 v167 ImmData(24) -> x0 v168 Load { addr=v167, disp=0, kind=I32 } -> x0 v169 BinopI { op=eq, lhs=v168, rhs_imm=0 } -> x1 v170 Imm(0) -> x0 - terminator Jmp(b62) (exit_acc=v169) - block 62 start_pc=0 - v171 Phi { incoming=[b241:v165, b61:v169], kind=I64 } -> x1 + terminator Jmp(b49) (exit_acc=v169) + block 49 start_pc=0 + v171 Phi { incoming=[b223:v165, b48:v169], kind=I64 } -> x1 v172 LoadLocal { off=-14, kind=I64 } -> x0 - terminator Bz { cond=v171, target=b64, fall=b63 } (exit_acc=v171) - block 63 start_pc=0 + terminator Bz { cond=v171, target=b51, fall=b50 } (exit_acc=v171) + block 50 start_pc=0 v173 ImmData(24) -> x0 v174 Imm(8) -> x1 v175 Store { addr=v173, disp=0, value=v174, kind=I32 } -> - - terminator Jmp(b64) (exit_acc=v175) - block 64 start_pc=0 - terminator Jmp(b57) - block 65 start_pc=0 + terminator Jmp(b51) (exit_acc=v175) + block 51 start_pc=0 + v158 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v158) + block 52 start_pc=0 v176 LocalAddr(-1) -> x0 v177 Imm(255) -> x1 v178 AtomicRmw { op=Xor, addr=v176, value=v177, width=4 } -> x0 @@ -317,45 +291,43 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v181 BinopI { op=eq, lhs=v180, rhs_imm=63 } -> x0 v182 Imm(0) -> x2 v183 Imm(0) -> x1 - terminator Bz { cond=v181, target=b242, fall=b68 } (exit_acc=v181) - block 66 start_pc=0 - v184 Imm(0) -> x0 - terminator Jmp(b67) (exit_acc=v184) - block 67 start_pc=0 - v185 Imm(7) -> x0 - v186 StoreLocal { off=-1, value=v185, kind=I32 } -> - - v187 StoreLocal { off=-2, value=v185, kind=I32 } -> - - terminator Jmp(b74) (exit_acc=v187) - block 68 start_pc=0 + terminator Bz { cond=v181, target=b222, fall=b53 } (exit_acc=v181) + block 53 start_pc=0 v188 LoadLocal { off=-1, kind=I32 } -> x0 v189 BinopI { op=eq, lhs=v188, rhs_imm=192 } -> x0 v190 BinopI { op=ne, lhs=v189, rhs_imm=0 } -> x2 v191 Imm(0) -> x0 - terminator Jmp(b69) (exit_acc=v190) - block 69 start_pc=0 - v192 Phi { incoming=[b242:v182, b68:v190], kind=I64 } -> x2 + terminator Jmp(b54) (exit_acc=v190) + block 54 start_pc=0 + v192 Phi { incoming=[b222:v182, b53:v190], kind=I64 } -> x2 v193 LoadLocal { off=-17, kind=I64 } -> x0 v194 BinopI { op=eq, lhs=v192, rhs_imm=0 } -> x1 v195 Imm(0) -> x0 - terminator Bz { cond=v194, target=b243, fall=b70 } (exit_acc=v194) - block 70 start_pc=0 + terminator Bz { cond=v194, target=b221, fall=b55 } (exit_acc=v194) + block 55 start_pc=0 v196 ImmData(24) -> x0 v197 Load { addr=v196, disp=0, kind=I32 } -> x0 v198 BinopI { op=eq, lhs=v197, rhs_imm=0 } -> x1 v199 Imm(0) -> x0 - terminator Jmp(b71) (exit_acc=v198) - block 71 start_pc=0 - v200 Phi { incoming=[b243:v194, b70:v198], kind=I64 } -> x1 + terminator Jmp(b56) (exit_acc=v198) + block 56 start_pc=0 + v200 Phi { incoming=[b221:v194, b55:v198], kind=I64 } -> x1 v201 LoadLocal { off=-16, kind=I64 } -> x0 - terminator Bz { cond=v200, target=b73, fall=b72 } (exit_acc=v200) - block 72 start_pc=0 + terminator Bz { cond=v200, target=b58, fall=b57 } (exit_acc=v200) + block 57 start_pc=0 v202 ImmData(24) -> x0 v203 Imm(9) -> x1 v204 Store { addr=v202, disp=0, value=v203, kind=I32 } -> - - terminator Jmp(b73) (exit_acc=v204) - block 73 start_pc=0 - terminator Jmp(b66) - block 74 start_pc=0 + terminator Jmp(b58) (exit_acc=v204) + block 58 start_pc=0 + v184 Imm(0) -> x0 + terminator Jmp(b59) (exit_acc=v184) + block 59 start_pc=0 + v185 Imm(7) -> x0 + v186 StoreLocal { off=-1, value=v185, kind=I32 } -> - + v187 StoreLocal { off=-2, value=v185, kind=I32 } -> - + terminator Jmp(b60) (exit_acc=v187) + block 60 start_pc=0 v205 LocalAddr(-1) -> x0 v206 LocalAddr(-2) -> x1 v207 Imm(8) -> x2 @@ -363,44 +335,42 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v209 BinopI { op=eq, lhs=v208, rhs_imm=1 } -> x0 v210 Imm(0) -> x2 v211 Imm(0) -> x1 - terminator Bz { cond=v209, target=b244, fall=b77 } (exit_acc=v209) - block 75 start_pc=0 - v212 Imm(0) -> x0 - terminator Jmp(b76) (exit_acc=v212) - block 76 start_pc=0 - v213 Imm(7) -> x0 - v214 StoreLocal { off=-2, value=v213, kind=I32 } -> - - terminator Jmp(b83) (exit_acc=v214) - block 77 start_pc=0 + terminator Bz { cond=v209, target=b220, fall=b61 } (exit_acc=v209) + block 61 start_pc=0 v215 LoadLocal { off=-1, kind=I32 } -> x0 v216 BinopI { op=eq, lhs=v215, rhs_imm=8 } -> x0 v217 BinopI { op=ne, lhs=v216, rhs_imm=0 } -> x2 v218 Imm(0) -> x0 - terminator Jmp(b78) (exit_acc=v217) - block 78 start_pc=0 - v219 Phi { incoming=[b244:v210, b77:v217], kind=I64 } -> x2 + terminator Jmp(b62) (exit_acc=v217) + block 62 start_pc=0 + v219 Phi { incoming=[b220:v210, b61:v217], kind=I64 } -> x2 v220 LoadLocal { off=-19, kind=I64 } -> x0 v221 BinopI { op=eq, lhs=v219, rhs_imm=0 } -> x1 v222 Imm(0) -> x0 - terminator Bz { cond=v221, target=b245, fall=b79 } (exit_acc=v221) - block 79 start_pc=0 + terminator Bz { cond=v221, target=b219, fall=b63 } (exit_acc=v221) + block 63 start_pc=0 v223 ImmData(24) -> x0 v224 Load { addr=v223, disp=0, kind=I32 } -> x0 v225 BinopI { op=eq, lhs=v224, rhs_imm=0 } -> x1 v226 Imm(0) -> x0 - terminator Jmp(b80) (exit_acc=v225) - block 80 start_pc=0 - v227 Phi { incoming=[b245:v221, b79:v225], kind=I64 } -> x1 + terminator Jmp(b64) (exit_acc=v225) + block 64 start_pc=0 + v227 Phi { incoming=[b219:v221, b63:v225], kind=I64 } -> x1 v228 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v227, target=b82, fall=b81 } (exit_acc=v227) - block 81 start_pc=0 + terminator Bz { cond=v227, target=b66, fall=b65 } (exit_acc=v227) + block 65 start_pc=0 v229 ImmData(24) -> x0 v230 Imm(10) -> x1 v231 Store { addr=v229, disp=0, value=v230, kind=I32 } -> - - terminator Jmp(b82) (exit_acc=v231) - block 82 start_pc=0 - terminator Jmp(b75) - block 83 start_pc=0 + terminator Jmp(b66) (exit_acc=v231) + block 66 start_pc=0 + v212 Imm(0) -> x0 + terminator Jmp(b67) (exit_acc=v212) + block 67 start_pc=0 + v213 Imm(7) -> x0 + v214 StoreLocal { off=-2, value=v213, kind=I32 } -> - + terminator Jmp(b68) (exit_acc=v214) + block 68 start_pc=0 v232 LocalAddr(-1) -> x0 v233 LocalAddr(-2) -> x1 v234 Imm(9) -> x2 @@ -408,56 +378,54 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v236 BinopI { op=eq, lhs=v235, rhs_imm=0 } -> x0 v237 Imm(0) -> x2 v238 Imm(0) -> x1 - terminator Bz { cond=v236, target=b246, fall=b86 } (exit_acc=v236) - block 84 start_pc=0 - v239 Imm(0) -> x0 - terminator Jmp(b85) (exit_acc=v239) - block 85 start_pc=0 - v240 Imm(100) -> x0 - v241 StoreLocal { off=-1, value=v240, kind=I32 } -> - - terminator Jmp(b94) (exit_acc=v241) - block 86 start_pc=0 + terminator Bz { cond=v236, target=b218, fall=b69 } (exit_acc=v236) + block 69 start_pc=0 v242 LoadLocal { off=-1, kind=I32 } -> x0 v243 BinopI { op=eq, lhs=v242, rhs_imm=8 } -> x0 v244 BinopI { op=ne, lhs=v243, rhs_imm=0 } -> x2 v245 Imm(0) -> x0 - terminator Jmp(b87) (exit_acc=v244) - block 87 start_pc=0 - v246 Phi { incoming=[b246:v237, b86:v244], kind=I64 } -> x2 + terminator Jmp(b70) (exit_acc=v244) + block 70 start_pc=0 + v246 Phi { incoming=[b218:v237, b69:v244], kind=I64 } -> x2 v247 LoadLocal { off=-22, kind=I64 } -> x0 v248 Imm(0) -> x1 v249 Imm(0) -> x0 - terminator Bz { cond=v246, target=b247, fall=b88 } (exit_acc=v246) - block 88 start_pc=0 + terminator Bz { cond=v246, target=b217, fall=b71 } (exit_acc=v246) + block 71 start_pc=0 v250 LoadLocal { off=-2, kind=I32 } -> x0 v251 BinopI { op=eq, lhs=v250, rhs_imm=8 } -> x0 v252 BinopI { op=ne, lhs=v251, rhs_imm=0 } -> x1 v253 Imm(0) -> x0 - terminator Jmp(b89) (exit_acc=v252) - block 89 start_pc=0 - v254 Phi { incoming=[b247:v248, b88:v252], kind=I64 } -> x1 + terminator Jmp(b72) (exit_acc=v252) + block 72 start_pc=0 + v254 Phi { incoming=[b217:v248, b71:v252], kind=I64 } -> x1 v255 LoadLocal { off=-21, kind=I64 } -> x0 v256 BinopI { op=eq, lhs=v254, rhs_imm=0 } -> x1 v257 Imm(0) -> x0 - terminator Bz { cond=v256, target=b248, fall=b90 } (exit_acc=v256) - block 90 start_pc=0 + terminator Bz { cond=v256, target=b216, fall=b73 } (exit_acc=v256) + block 73 start_pc=0 v258 ImmData(24) -> x0 v259 Load { addr=v258, disp=0, kind=I32 } -> x0 v260 BinopI { op=eq, lhs=v259, rhs_imm=0 } -> x1 v261 Imm(0) -> x0 - terminator Jmp(b91) (exit_acc=v260) - block 91 start_pc=0 - v262 Phi { incoming=[b248:v256, b90:v260], kind=I64 } -> x1 + terminator Jmp(b74) (exit_acc=v260) + block 74 start_pc=0 + v262 Phi { incoming=[b216:v256, b73:v260], kind=I64 } -> x1 v263 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v262, target=b93, fall=b92 } (exit_acc=v262) - block 92 start_pc=0 + terminator Bz { cond=v262, target=b76, fall=b75 } (exit_acc=v262) + block 75 start_pc=0 v264 ImmData(24) -> x0 v265 Imm(11) -> x1 v266 Store { addr=v264, disp=0, value=v265, kind=I32 } -> - - terminator Jmp(b93) (exit_acc=v266) - block 93 start_pc=0 - terminator Jmp(b84) - block 94 start_pc=0 + terminator Jmp(b76) (exit_acc=v266) + block 76 start_pc=0 + v239 Imm(0) -> x0 + terminator Jmp(b77) (exit_acc=v239) + block 77 start_pc=0 + v240 Imm(100) -> x0 + v241 StoreLocal { off=-1, value=v240, kind=I32 } -> - + terminator Jmp(b78) (exit_acc=v241) + block 78 start_pc=0 v267 LocalAddr(-1) -> x0 v268 Imm(7) -> x1 v269 AtomicRmw { op=Add, addr=v267, value=v268, width=4 } -> x0 @@ -466,138 +434,128 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v272 BinopI { op=eq, lhs=v271, rhs_imm=100 } -> x0 v273 Imm(0) -> x2 v274 Imm(0) -> x1 - terminator Bz { cond=v272, target=b249, fall=b97 } (exit_acc=v272) - block 95 start_pc=0 - v275 Imm(0) -> x0 - terminator Jmp(b96) (exit_acc=v275) - block 96 start_pc=0 - terminator Jmp(b103) - block 97 start_pc=0 + terminator Bz { cond=v272, target=b215, fall=b79 } (exit_acc=v272) + block 79 start_pc=0 v276 LoadLocal { off=-1, kind=I32 } -> x0 v277 BinopI { op=eq, lhs=v276, rhs_imm=107 } -> x0 v278 BinopI { op=ne, lhs=v277, rhs_imm=0 } -> x2 v279 Imm(0) -> x0 - terminator Jmp(b98) (exit_acc=v278) - block 98 start_pc=0 - v280 Phi { incoming=[b249:v273, b97:v278], kind=I64 } -> x2 + terminator Jmp(b80) (exit_acc=v278) + block 80 start_pc=0 + v280 Phi { incoming=[b215:v273, b79:v278], kind=I64 } -> x2 v281 LoadLocal { off=-24, kind=I64 } -> x0 v282 BinopI { op=eq, lhs=v280, rhs_imm=0 } -> x1 v283 Imm(0) -> x0 - terminator Bz { cond=v282, target=b250, fall=b99 } (exit_acc=v282) - block 99 start_pc=0 + terminator Bz { cond=v282, target=b214, fall=b81 } (exit_acc=v282) + block 81 start_pc=0 v284 ImmData(24) -> x0 v285 Load { addr=v284, disp=0, kind=I32 } -> x0 v286 BinopI { op=eq, lhs=v285, rhs_imm=0 } -> x1 v287 Imm(0) -> x0 - terminator Jmp(b100) (exit_acc=v286) - block 100 start_pc=0 - v288 Phi { incoming=[b250:v282, b99:v286], kind=I64 } -> x1 + terminator Jmp(b82) (exit_acc=v286) + block 82 start_pc=0 + v288 Phi { incoming=[b214:v282, b81:v286], kind=I64 } -> x1 v289 LoadLocal { off=-23, kind=I64 } -> x0 - terminator Bz { cond=v288, target=b102, fall=b101 } (exit_acc=v288) - block 101 start_pc=0 + terminator Bz { cond=v288, target=b84, fall=b83 } (exit_acc=v288) + block 83 start_pc=0 v290 ImmData(24) -> x0 v291 Imm(12) -> x1 v292 Store { addr=v290, disp=0, value=v291, kind=I32 } -> - - terminator Jmp(b102) (exit_acc=v292) - block 102 start_pc=0 - terminator Jmp(b95) - block 103 start_pc=0 + terminator Jmp(b84) (exit_acc=v292) + block 84 start_pc=0 + v275 Imm(0) -> x0 + terminator Jmp(b85) (exit_acc=v275) + block 85 start_pc=0 v293 LocalAddr(-1) -> x0 v294 Imm(7) -> x1 v295 AtomicRmw { op=Sub, addr=v293, value=v294, width=4 } -> x0 - v296 BinopI { op=shl, lhs=v295, rhs_imm=32 } -> x2 - v297 Extend { value=v295, kind=I32 } -> x2 - v298 Binop { op=sub, lhs=v295, rhs=v294 } -> x0 + v296 BinopI { op=shl, lhs=v295, rhs_imm=32 } -> x1 + v297 Extend { value=v295, kind=I32 } -> x1 + v298 BinopI { op=sub, lhs=v295, rhs_imm=7 } -> x0 v299 BinopI { op=shl, lhs=v298, rhs_imm=32 } -> x1 v300 Extend { value=v298, kind=I32 } -> x0 v301 BinopI { op=eq, lhs=v300, rhs_imm=100 } -> x0 v302 Imm(0) -> x2 v303 Imm(0) -> x1 - terminator Bz { cond=v301, target=b251, fall=b106 } (exit_acc=v301) - block 104 start_pc=0 - v304 Imm(0) -> x0 - terminator Jmp(b105) (exit_acc=v304) - block 105 start_pc=0 - terminator Jmp(b112) - block 106 start_pc=0 + terminator Bz { cond=v301, target=b213, fall=b86 } (exit_acc=v301) + block 86 start_pc=0 v305 LoadLocal { off=-1, kind=I32 } -> x0 v306 BinopI { op=eq, lhs=v305, rhs_imm=100 } -> x0 v307 BinopI { op=ne, lhs=v306, rhs_imm=0 } -> x2 v308 Imm(0) -> x0 - terminator Jmp(b107) (exit_acc=v307) - block 107 start_pc=0 - v309 Phi { incoming=[b251:v302, b106:v307], kind=I64 } -> x2 + terminator Jmp(b87) (exit_acc=v307) + block 87 start_pc=0 + v309 Phi { incoming=[b213:v302, b86:v307], kind=I64 } -> x2 v310 LoadLocal { off=-26, kind=I64 } -> x0 v311 BinopI { op=eq, lhs=v309, rhs_imm=0 } -> x1 v312 Imm(0) -> x0 - terminator Bz { cond=v311, target=b252, fall=b108 } (exit_acc=v311) - block 108 start_pc=0 + terminator Bz { cond=v311, target=b212, fall=b88 } (exit_acc=v311) + block 88 start_pc=0 v313 ImmData(24) -> x0 v314 Load { addr=v313, disp=0, kind=I32 } -> x0 v315 BinopI { op=eq, lhs=v314, rhs_imm=0 } -> x1 v316 Imm(0) -> x0 - terminator Jmp(b109) (exit_acc=v315) - block 109 start_pc=0 - v317 Phi { incoming=[b252:v311, b108:v315], kind=I64 } -> x1 + terminator Jmp(b89) (exit_acc=v315) + block 89 start_pc=0 + v317 Phi { incoming=[b212:v311, b88:v315], kind=I64 } -> x1 v318 LoadLocal { off=-25, kind=I64 } -> x0 - terminator Bz { cond=v317, target=b111, fall=b110 } (exit_acc=v317) - block 110 start_pc=0 + terminator Bz { cond=v317, target=b91, fall=b90 } (exit_acc=v317) + block 90 start_pc=0 v319 ImmData(24) -> x0 v320 Imm(13) -> x1 v321 Store { addr=v319, disp=0, value=v320, kind=I32 } -> - - terminator Jmp(b111) (exit_acc=v321) - block 111 start_pc=0 - terminator Jmp(b104) - block 112 start_pc=0 + terminator Jmp(b91) (exit_acc=v321) + block 91 start_pc=0 + v304 Imm(0) -> x0 + terminator Jmp(b92) (exit_acc=v304) + block 92 start_pc=0 v322 LocalAddr(-1) -> x0 v323 Imm(1) -> x1 v324 AtomicRmw { op=Add, addr=v322, value=v323, width=4 } -> x0 - v325 BinopI { op=shl, lhs=v324, rhs_imm=32 } -> x2 - v326 Extend { value=v324, kind=I32 } -> x2 - v327 Binop { op=add, lhs=v324, rhs=v323 } -> x0 + v325 BinopI { op=shl, lhs=v324, rhs_imm=32 } -> x1 + v326 Extend { value=v324, kind=I32 } -> x1 + v327 BinopI { op=add, lhs=v324, rhs_imm=1 } -> x0 v328 BinopI { op=shl, lhs=v327, rhs_imm=32 } -> x1 v329 Extend { value=v327, kind=I32 } -> x0 v330 BinopI { op=eq, lhs=v329, rhs_imm=101 } -> x0 v331 Imm(0) -> x2 v332 Imm(0) -> x1 - terminator Bz { cond=v330, target=b253, fall=b115 } (exit_acc=v330) - block 113 start_pc=0 - v333 Imm(0) -> x0 - terminator Jmp(b114) (exit_acc=v333) - block 114 start_pc=0 - v334 Imm(204) -> x0 - v335 StoreLocal { off=-1, value=v334, kind=I32 } -> - - terminator Jmp(b121) (exit_acc=v335) - block 115 start_pc=0 + terminator Bz { cond=v330, target=b211, fall=b93 } (exit_acc=v330) + block 93 start_pc=0 v336 LoadLocal { off=-1, kind=I32 } -> x0 v337 BinopI { op=eq, lhs=v336, rhs_imm=101 } -> x0 v338 BinopI { op=ne, lhs=v337, rhs_imm=0 } -> x2 v339 Imm(0) -> x0 - terminator Jmp(b116) (exit_acc=v338) - block 116 start_pc=0 - v340 Phi { incoming=[b253:v331, b115:v338], kind=I64 } -> x2 + terminator Jmp(b94) (exit_acc=v338) + block 94 start_pc=0 + v340 Phi { incoming=[b211:v331, b93:v338], kind=I64 } -> x2 v341 LoadLocal { off=-28, kind=I64 } -> x0 v342 BinopI { op=eq, lhs=v340, rhs_imm=0 } -> x1 v343 Imm(0) -> x0 - terminator Bz { cond=v342, target=b254, fall=b117 } (exit_acc=v342) - block 117 start_pc=0 + terminator Bz { cond=v342, target=b210, fall=b95 } (exit_acc=v342) + block 95 start_pc=0 v344 ImmData(24) -> x0 v345 Load { addr=v344, disp=0, kind=I32 } -> x0 v346 BinopI { op=eq, lhs=v345, rhs_imm=0 } -> x1 v347 Imm(0) -> x0 - terminator Jmp(b118) (exit_acc=v346) - block 118 start_pc=0 - v348 Phi { incoming=[b254:v342, b117:v346], kind=I64 } -> x1 + terminator Jmp(b96) (exit_acc=v346) + block 96 start_pc=0 + v348 Phi { incoming=[b210:v342, b95:v346], kind=I64 } -> x1 v349 LoadLocal { off=-27, kind=I64 } -> x0 - terminator Bz { cond=v348, target=b120, fall=b119 } (exit_acc=v348) - block 119 start_pc=0 + terminator Bz { cond=v348, target=b98, fall=b97 } (exit_acc=v348) + block 97 start_pc=0 v350 ImmData(24) -> x0 v351 Imm(14) -> x1 v352 Store { addr=v350, disp=0, value=v351, kind=I32 } -> - - terminator Jmp(b120) (exit_acc=v352) - block 120 start_pc=0 - terminator Jmp(b113) - block 121 start_pc=0 + terminator Jmp(b98) (exit_acc=v352) + block 98 start_pc=0 + v333 Imm(0) -> x0 + terminator Jmp(b99) (exit_acc=v333) + block 99 start_pc=0 + v334 Imm(204) -> x0 + v335 StoreLocal { off=-1, value=v334, kind=I32 } -> - + terminator Jmp(b100) (exit_acc=v335) + block 100 start_pc=0 v353 LocalAddr(-1) -> x0 v354 Imm(51) -> x1 v355 AtomicRmw { op=Or, addr=v353, value=v354, width=4 } -> x0 @@ -606,42 +564,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v358 BinopI { op=eq, lhs=v357, rhs_imm=204 } -> x0 v359 Imm(0) -> x2 v360 Imm(0) -> x1 - terminator Bz { cond=v358, target=b255, fall=b124 } (exit_acc=v358) - block 122 start_pc=0 - v361 Imm(0) -> x0 - terminator Jmp(b123) (exit_acc=v361) - block 123 start_pc=0 - terminator Jmp(b130) - block 124 start_pc=0 + terminator Bz { cond=v358, target=b209, fall=b101 } (exit_acc=v358) + block 101 start_pc=0 v362 LoadLocal { off=-1, kind=I32 } -> x0 v363 BinopI { op=eq, lhs=v362, rhs_imm=255 } -> x0 v364 BinopI { op=ne, lhs=v363, rhs_imm=0 } -> x2 v365 Imm(0) -> x0 - terminator Jmp(b125) (exit_acc=v364) - block 125 start_pc=0 - v366 Phi { incoming=[b255:v359, b124:v364], kind=I64 } -> x2 + terminator Jmp(b102) (exit_acc=v364) + block 102 start_pc=0 + v366 Phi { incoming=[b209:v359, b101:v364], kind=I64 } -> x2 v367 LoadLocal { off=-30, kind=I64 } -> x0 v368 BinopI { op=eq, lhs=v366, rhs_imm=0 } -> x1 v369 Imm(0) -> x0 - terminator Bz { cond=v368, target=b256, fall=b126 } (exit_acc=v368) - block 126 start_pc=0 + terminator Bz { cond=v368, target=b208, fall=b103 } (exit_acc=v368) + block 103 start_pc=0 v370 ImmData(24) -> x0 v371 Load { addr=v370, disp=0, kind=I32 } -> x0 v372 BinopI { op=eq, lhs=v371, rhs_imm=0 } -> x1 v373 Imm(0) -> x0 - terminator Jmp(b127) (exit_acc=v372) - block 127 start_pc=0 - v374 Phi { incoming=[b256:v368, b126:v372], kind=I64 } -> x1 + terminator Jmp(b104) (exit_acc=v372) + block 104 start_pc=0 + v374 Phi { incoming=[b208:v368, b103:v372], kind=I64 } -> x1 v375 LoadLocal { off=-29, kind=I64 } -> x0 - terminator Bz { cond=v374, target=b129, fall=b128 } (exit_acc=v374) - block 128 start_pc=0 + terminator Bz { cond=v374, target=b106, fall=b105 } (exit_acc=v374) + block 105 start_pc=0 v376 ImmData(24) -> x0 v377 Imm(15) -> x1 v378 Store { addr=v376, disp=0, value=v377, kind=I32 } -> - - terminator Jmp(b129) (exit_acc=v378) - block 129 start_pc=0 - terminator Jmp(b122) - block 130 start_pc=0 + terminator Jmp(b106) (exit_acc=v378) + block 106 start_pc=0 + v361 Imm(0) -> x0 + terminator Jmp(b107) (exit_acc=v361) + block 107 start_pc=0 v379 LocalAddr(-1) -> x0 v380 Imm(15) -> x1 v381 AtomicRmw { op=And, addr=v379, value=v380, width=4 } -> x0 @@ -653,42 +607,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v387 BinopI { op=eq, lhs=v386, rhs_imm=15 } -> x0 v388 Imm(0) -> x2 v389 Imm(0) -> x1 - terminator Bz { cond=v387, target=b257, fall=b133 } (exit_acc=v387) - block 131 start_pc=0 - v390 Imm(0) -> x0 - terminator Jmp(b132) (exit_acc=v390) - block 132 start_pc=0 - terminator Jmp(b139) - block 133 start_pc=0 + terminator Bz { cond=v387, target=b207, fall=b108 } (exit_acc=v387) + block 108 start_pc=0 v391 LoadLocal { off=-1, kind=I32 } -> x0 v392 BinopI { op=eq, lhs=v391, rhs_imm=15 } -> x0 v393 BinopI { op=ne, lhs=v392, rhs_imm=0 } -> x2 v394 Imm(0) -> x0 - terminator Jmp(b134) (exit_acc=v393) - block 134 start_pc=0 - v395 Phi { incoming=[b257:v388, b133:v393], kind=I64 } -> x2 + terminator Jmp(b109) (exit_acc=v393) + block 109 start_pc=0 + v395 Phi { incoming=[b207:v388, b108:v393], kind=I64 } -> x2 v396 LoadLocal { off=-32, kind=I64 } -> x0 v397 BinopI { op=eq, lhs=v395, rhs_imm=0 } -> x1 v398 Imm(0) -> x0 - terminator Bz { cond=v397, target=b258, fall=b135 } (exit_acc=v397) - block 135 start_pc=0 + terminator Bz { cond=v397, target=b206, fall=b110 } (exit_acc=v397) + block 110 start_pc=0 v399 ImmData(24) -> x0 v400 Load { addr=v399, disp=0, kind=I32 } -> x0 v401 BinopI { op=eq, lhs=v400, rhs_imm=0 } -> x1 v402 Imm(0) -> x0 - terminator Jmp(b136) (exit_acc=v401) - block 136 start_pc=0 - v403 Phi { incoming=[b258:v397, b135:v401], kind=I64 } -> x1 + terminator Jmp(b111) (exit_acc=v401) + block 111 start_pc=0 + v403 Phi { incoming=[b206:v397, b110:v401], kind=I64 } -> x1 v404 LoadLocal { off=-31, kind=I64 } -> x0 - terminator Bz { cond=v403, target=b138, fall=b137 } (exit_acc=v403) - block 137 start_pc=0 + terminator Bz { cond=v403, target=b113, fall=b112 } (exit_acc=v403) + block 112 start_pc=0 v405 ImmData(24) -> x0 v406 Imm(16) -> x1 v407 Store { addr=v405, disp=0, value=v406, kind=I32 } -> - - terminator Jmp(b138) (exit_acc=v407) - block 138 start_pc=0 - terminator Jmp(b131) - block 139 start_pc=0 + terminator Jmp(b113) (exit_acc=v407) + block 113 start_pc=0 + v390 Imm(0) -> x0 + terminator Jmp(b114) (exit_acc=v390) + block 114 start_pc=0 v408 LocalAddr(-1) -> x0 v409 Imm(255) -> x1 v410 AtomicRmw { op=Xor, addr=v408, value=v409, width=4 } -> x0 @@ -700,44 +650,42 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v416 BinopI { op=eq, lhs=v415, rhs_imm=240 } -> x0 v417 Imm(0) -> x2 v418 Imm(0) -> x1 - terminator Bz { cond=v416, target=b259, fall=b142 } (exit_acc=v416) - block 140 start_pc=0 - v419 Imm(0) -> x0 - terminator Jmp(b141) (exit_acc=v419) - block 141 start_pc=0 - v420 Imm(5) -> x0 - v421 StoreLocal { off=-1, value=v420, kind=I32 } -> - - terminator Jmp(b148) (exit_acc=v421) - block 142 start_pc=0 + terminator Bz { cond=v416, target=b205, fall=b115 } (exit_acc=v416) + block 115 start_pc=0 v422 LoadLocal { off=-1, kind=I32 } -> x0 v423 BinopI { op=eq, lhs=v422, rhs_imm=240 } -> x0 v424 BinopI { op=ne, lhs=v423, rhs_imm=0 } -> x2 v425 Imm(0) -> x0 - terminator Jmp(b143) (exit_acc=v424) - block 143 start_pc=0 - v426 Phi { incoming=[b259:v417, b142:v424], kind=I64 } -> x2 + terminator Jmp(b116) (exit_acc=v424) + block 116 start_pc=0 + v426 Phi { incoming=[b205:v417, b115:v424], kind=I64 } -> x2 v427 LoadLocal { off=-34, kind=I64 } -> x0 v428 BinopI { op=eq, lhs=v426, rhs_imm=0 } -> x1 v429 Imm(0) -> x0 - terminator Bz { cond=v428, target=b260, fall=b144 } (exit_acc=v428) - block 144 start_pc=0 + terminator Bz { cond=v428, target=b204, fall=b117 } (exit_acc=v428) + block 117 start_pc=0 v430 ImmData(24) -> x0 v431 Load { addr=v430, disp=0, kind=I32 } -> x0 v432 BinopI { op=eq, lhs=v431, rhs_imm=0 } -> x1 v433 Imm(0) -> x0 - terminator Jmp(b145) (exit_acc=v432) - block 145 start_pc=0 - v434 Phi { incoming=[b260:v428, b144:v432], kind=I64 } -> x1 + terminator Jmp(b118) (exit_acc=v432) + block 118 start_pc=0 + v434 Phi { incoming=[b204:v428, b117:v432], kind=I64 } -> x1 v435 LoadLocal { off=-33, kind=I64 } -> x0 - terminator Bz { cond=v434, target=b147, fall=b146 } (exit_acc=v434) - block 146 start_pc=0 + terminator Bz { cond=v434, target=b120, fall=b119 } (exit_acc=v434) + block 119 start_pc=0 v436 ImmData(24) -> x0 v437 Imm(17) -> x1 v438 Store { addr=v436, disp=0, value=v437, kind=I32 } -> - - terminator Jmp(b147) (exit_acc=v438) - block 147 start_pc=0 - terminator Jmp(b140) - block 148 start_pc=0 + terminator Jmp(b120) (exit_acc=v438) + block 120 start_pc=0 + v419 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v419) + block 121 start_pc=0 + v420 Imm(5) -> x0 + v421 StoreLocal { off=-1, value=v420, kind=I32 } -> - + terminator Jmp(b122) (exit_acc=v421) + block 122 start_pc=0 v439 LocalAddr(-1) -> x0 v440 Imm(5) -> x1 v441 Imm(6) -> x2 @@ -748,42 +696,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v446 BinopI { op=eq, lhs=v445, rhs_imm=5 } -> x0 v447 Imm(0) -> x2 v448 Imm(0) -> x1 - terminator Bz { cond=v446, target=b261, fall=b151 } (exit_acc=v446) - block 149 start_pc=0 - v449 Imm(0) -> x0 - terminator Jmp(b150) (exit_acc=v449) - block 150 start_pc=0 - terminator Jmp(b157) - block 151 start_pc=0 + terminator Bz { cond=v446, target=b203, fall=b123 } (exit_acc=v446) + block 123 start_pc=0 v450 LoadLocal { off=-1, kind=I32 } -> x0 v451 BinopI { op=eq, lhs=v450, rhs_imm=6 } -> x0 v452 BinopI { op=ne, lhs=v451, rhs_imm=0 } -> x2 v453 Imm(0) -> x0 - terminator Jmp(b152) (exit_acc=v452) - block 152 start_pc=0 - v454 Phi { incoming=[b261:v447, b151:v452], kind=I64 } -> x2 + terminator Jmp(b124) (exit_acc=v452) + block 124 start_pc=0 + v454 Phi { incoming=[b203:v447, b123:v452], kind=I64 } -> x2 v455 LoadLocal { off=-36, kind=I64 } -> x0 v456 BinopI { op=eq, lhs=v454, rhs_imm=0 } -> x1 v457 Imm(0) -> x0 - terminator Bz { cond=v456, target=b262, fall=b153 } (exit_acc=v456) - block 153 start_pc=0 + terminator Bz { cond=v456, target=b202, fall=b125 } (exit_acc=v456) + block 125 start_pc=0 v458 ImmData(24) -> x0 v459 Load { addr=v458, disp=0, kind=I32 } -> x0 v460 BinopI { op=eq, lhs=v459, rhs_imm=0 } -> x1 v461 Imm(0) -> x0 - terminator Jmp(b154) (exit_acc=v460) - block 154 start_pc=0 - v462 Phi { incoming=[b262:v456, b153:v460], kind=I64 } -> x1 + terminator Jmp(b126) (exit_acc=v460) + block 126 start_pc=0 + v462 Phi { incoming=[b202:v456, b125:v460], kind=I64 } -> x1 v463 LoadLocal { off=-35, kind=I64 } -> x0 - terminator Bz { cond=v462, target=b156, fall=b155 } (exit_acc=v462) - block 155 start_pc=0 + terminator Bz { cond=v462, target=b128, fall=b127 } (exit_acc=v462) + block 127 start_pc=0 v464 ImmData(24) -> x0 v465 Imm(18) -> x1 v466 Store { addr=v464, disp=0, value=v465, kind=I32 } -> - - terminator Jmp(b156) (exit_acc=v466) - block 156 start_pc=0 - terminator Jmp(b149) - block 157 start_pc=0 + terminator Jmp(b128) (exit_acc=v466) + block 128 start_pc=0 + v449 Imm(0) -> x0 + terminator Jmp(b129) (exit_acc=v449) + block 129 start_pc=0 v467 LocalAddr(-1) -> x0 v468 Imm(5) -> x1 v469 Imm(7) -> x2 @@ -794,42 +738,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v474 BinopI { op=eq, lhs=v473, rhs_imm=6 } -> x0 v475 Imm(0) -> x2 v476 Imm(0) -> x1 - terminator Bz { cond=v474, target=b263, fall=b160 } (exit_acc=v474) - block 158 start_pc=0 - v477 Imm(0) -> x0 - terminator Jmp(b159) (exit_acc=v477) - block 159 start_pc=0 - terminator Jmp(b166) - block 160 start_pc=0 + terminator Bz { cond=v474, target=b201, fall=b130 } (exit_acc=v474) + block 130 start_pc=0 v478 LoadLocal { off=-1, kind=I32 } -> x0 v479 BinopI { op=eq, lhs=v478, rhs_imm=6 } -> x0 v480 BinopI { op=ne, lhs=v479, rhs_imm=0 } -> x2 v481 Imm(0) -> x0 - terminator Jmp(b161) (exit_acc=v480) - block 161 start_pc=0 - v482 Phi { incoming=[b263:v475, b160:v480], kind=I64 } -> x2 + terminator Jmp(b131) (exit_acc=v480) + block 131 start_pc=0 + v482 Phi { incoming=[b201:v475, b130:v480], kind=I64 } -> x2 v483 LoadLocal { off=-39, kind=I64 } -> x0 v484 BinopI { op=eq, lhs=v482, rhs_imm=0 } -> x1 v485 Imm(0) -> x0 - terminator Bz { cond=v484, target=b264, fall=b162 } (exit_acc=v484) - block 162 start_pc=0 + terminator Bz { cond=v484, target=b200, fall=b132 } (exit_acc=v484) + block 132 start_pc=0 v486 ImmData(24) -> x0 v487 Load { addr=v486, disp=0, kind=I32 } -> x0 v488 BinopI { op=eq, lhs=v487, rhs_imm=0 } -> x1 v489 Imm(0) -> x0 - terminator Jmp(b163) (exit_acc=v488) - block 163 start_pc=0 - v490 Phi { incoming=[b264:v484, b162:v488], kind=I64 } -> x1 + terminator Jmp(b133) (exit_acc=v488) + block 133 start_pc=0 + v490 Phi { incoming=[b200:v484, b132:v488], kind=I64 } -> x1 v491 LoadLocal { off=-38, kind=I64 } -> x0 - terminator Bz { cond=v490, target=b165, fall=b164 } (exit_acc=v490) - block 164 start_pc=0 + terminator Bz { cond=v490, target=b135, fall=b134 } (exit_acc=v490) + block 134 start_pc=0 v492 ImmData(24) -> x0 v493 Imm(19) -> x1 v494 Store { addr=v492, disp=0, value=v493, kind=I32 } -> - - terminator Jmp(b165) (exit_acc=v494) - block 165 start_pc=0 - terminator Jmp(b158) - block 166 start_pc=0 + terminator Jmp(b135) (exit_acc=v494) + block 135 start_pc=0 + v477 Imm(0) -> x0 + terminator Jmp(b136) (exit_acc=v477) + block 136 start_pc=0 v495 LocalAddr(-1) -> x0 v496 Imm(6) -> x1 v497 Imm(8) -> x2 @@ -839,42 +779,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v501 BinopI { op=eq, lhs=v500, rhs_imm=1 } -> x0 v502 Imm(0) -> x2 v503 Imm(0) -> x1 - terminator Bz { cond=v501, target=b265, fall=b169 } (exit_acc=v501) - block 167 start_pc=0 - v504 Imm(0) -> x0 - terminator Jmp(b168) (exit_acc=v504) - block 168 start_pc=0 - terminator Jmp(b175) - block 169 start_pc=0 + terminator Bz { cond=v501, target=b199, fall=b137 } (exit_acc=v501) + block 137 start_pc=0 v505 LoadLocal { off=-1, kind=I32 } -> x0 v506 BinopI { op=eq, lhs=v505, rhs_imm=8 } -> x0 v507 BinopI { op=ne, lhs=v506, rhs_imm=0 } -> x2 v508 Imm(0) -> x0 - terminator Jmp(b170) (exit_acc=v507) - block 170 start_pc=0 - v509 Phi { incoming=[b265:v502, b169:v507], kind=I64 } -> x2 + terminator Jmp(b138) (exit_acc=v507) + block 138 start_pc=0 + v509 Phi { incoming=[b199:v502, b137:v507], kind=I64 } -> x2 v510 LoadLocal { off=-42, kind=I64 } -> x0 v511 BinopI { op=eq, lhs=v509, rhs_imm=0 } -> x1 v512 Imm(0) -> x0 - terminator Bz { cond=v511, target=b266, fall=b171 } (exit_acc=v511) - block 171 start_pc=0 + terminator Bz { cond=v511, target=b198, fall=b139 } (exit_acc=v511) + block 139 start_pc=0 v513 ImmData(24) -> x0 v514 Load { addr=v513, disp=0, kind=I32 } -> x0 v515 BinopI { op=eq, lhs=v514, rhs_imm=0 } -> x1 v516 Imm(0) -> x0 - terminator Jmp(b172) (exit_acc=v515) - block 172 start_pc=0 - v517 Phi { incoming=[b266:v511, b171:v515], kind=I64 } -> x1 + terminator Jmp(b140) (exit_acc=v515) + block 140 start_pc=0 + v517 Phi { incoming=[b198:v511, b139:v515], kind=I64 } -> x1 v518 LoadLocal { off=-41, kind=I64 } -> x0 - terminator Bz { cond=v517, target=b174, fall=b173 } (exit_acc=v517) - block 173 start_pc=0 + terminator Bz { cond=v517, target=b142, fall=b141 } (exit_acc=v517) + block 141 start_pc=0 v519 ImmData(24) -> x0 v520 Imm(20) -> x1 v521 Store { addr=v519, disp=0, value=v520, kind=I32 } -> - - terminator Jmp(b174) (exit_acc=v521) - block 174 start_pc=0 - terminator Jmp(b167) - block 175 start_pc=0 + terminator Jmp(b142) (exit_acc=v521) + block 142 start_pc=0 + v504 Imm(0) -> x0 + terminator Jmp(b143) (exit_acc=v504) + block 143 start_pc=0 v522 LocalAddr(-1) -> x0 v523 Imm(6) -> x1 v524 Imm(9) -> x2 @@ -884,44 +820,42 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v528 BinopI { op=eq, lhs=v527, rhs_imm=0 } -> x0 v529 Imm(0) -> x2 v530 Imm(0) -> x1 - terminator Bz { cond=v528, target=b267, fall=b178 } (exit_acc=v528) - block 176 start_pc=0 - v531 Imm(0) -> x0 - terminator Jmp(b177) (exit_acc=v531) - block 177 start_pc=0 - v532 Imm(1) -> x0 - v533 StoreLocal { off=-1, value=v532, kind=I32 } -> - - terminator Jmp(b184) (exit_acc=v533) - block 178 start_pc=0 + terminator Bz { cond=v528, target=b197, fall=b144 } (exit_acc=v528) + block 144 start_pc=0 v534 LoadLocal { off=-1, kind=I32 } -> x0 v535 BinopI { op=eq, lhs=v534, rhs_imm=8 } -> x0 v536 BinopI { op=ne, lhs=v535, rhs_imm=0 } -> x2 v537 Imm(0) -> x0 - terminator Jmp(b179) (exit_acc=v536) - block 179 start_pc=0 - v538 Phi { incoming=[b267:v529, b178:v536], kind=I64 } -> x2 + terminator Jmp(b145) (exit_acc=v536) + block 145 start_pc=0 + v538 Phi { incoming=[b197:v529, b144:v536], kind=I64 } -> x2 v539 LoadLocal { off=-45, kind=I64 } -> x0 v540 BinopI { op=eq, lhs=v538, rhs_imm=0 } -> x1 v541 Imm(0) -> x0 - terminator Bz { cond=v540, target=b268, fall=b180 } (exit_acc=v540) - block 180 start_pc=0 + terminator Bz { cond=v540, target=b196, fall=b146 } (exit_acc=v540) + block 146 start_pc=0 v542 ImmData(24) -> x0 v543 Load { addr=v542, disp=0, kind=I32 } -> x0 v544 BinopI { op=eq, lhs=v543, rhs_imm=0 } -> x1 v545 Imm(0) -> x0 - terminator Jmp(b181) (exit_acc=v544) - block 181 start_pc=0 - v546 Phi { incoming=[b268:v540, b180:v544], kind=I64 } -> x1 + terminator Jmp(b147) (exit_acc=v544) + block 147 start_pc=0 + v546 Phi { incoming=[b196:v540, b146:v544], kind=I64 } -> x1 v547 LoadLocal { off=-44, kind=I64 } -> x0 - terminator Bz { cond=v546, target=b183, fall=b182 } (exit_acc=v546) - block 182 start_pc=0 + terminator Bz { cond=v546, target=b149, fall=b148 } (exit_acc=v546) + block 148 start_pc=0 v548 ImmData(24) -> x0 v549 Imm(21) -> x1 v550 Store { addr=v548, disp=0, value=v549, kind=I32 } -> - - terminator Jmp(b183) (exit_acc=v550) - block 183 start_pc=0 - terminator Jmp(b176) - block 184 start_pc=0 + terminator Jmp(b149) (exit_acc=v550) + block 149 start_pc=0 + v531 Imm(0) -> x0 + terminator Jmp(b150) (exit_acc=v531) + block 150 start_pc=0 + v532 Imm(1) -> x0 + v533 StoreLocal { off=-1, value=v532, kind=I32 } -> - + terminator Jmp(b151) (exit_acc=v533) + block 151 start_pc=0 v551 LocalAddr(-1) -> x0 v552 Imm(2) -> x1 v553 AtomicRmw { op=Xchg, addr=v551, value=v552, width=4 } -> x0 @@ -930,75 +864,71 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v556 BinopI { op=eq, lhs=v555, rhs_imm=1 } -> x0 v557 Imm(0) -> x2 v558 Imm(0) -> x1 - terminator Bz { cond=v556, target=b269, fall=b187 } (exit_acc=v556) - block 185 start_pc=0 - v559 Imm(0) -> x0 - terminator Jmp(b186) (exit_acc=v559) - block 186 start_pc=0 - v560 LocalAddr(-1) -> x0 - v561 Imm(0) -> x1 - v562 Store { addr=v560, disp=0, value=v561, kind=I32 } -> - - terminator Jmp(b193) (exit_acc=v562) - block 187 start_pc=0 + terminator Bz { cond=v556, target=b195, fall=b152 } (exit_acc=v556) + block 152 start_pc=0 v563 LoadLocal { off=-1, kind=I32 } -> x0 v564 BinopI { op=eq, lhs=v563, rhs_imm=2 } -> x0 v565 BinopI { op=ne, lhs=v564, rhs_imm=0 } -> x2 v566 Imm(0) -> x0 - terminator Jmp(b188) (exit_acc=v565) - block 188 start_pc=0 - v567 Phi { incoming=[b269:v557, b187:v565], kind=I64 } -> x2 + terminator Jmp(b153) (exit_acc=v565) + block 153 start_pc=0 + v567 Phi { incoming=[b195:v557, b152:v565], kind=I64 } -> x2 v568 LoadLocal { off=-48, kind=I64 } -> x0 v569 BinopI { op=eq, lhs=v567, rhs_imm=0 } -> x1 v570 Imm(0) -> x0 - terminator Bz { cond=v569, target=b270, fall=b189 } (exit_acc=v569) - block 189 start_pc=0 + terminator Bz { cond=v569, target=b194, fall=b154 } (exit_acc=v569) + block 154 start_pc=0 v571 ImmData(24) -> x0 v572 Load { addr=v571, disp=0, kind=I32 } -> x0 v573 BinopI { op=eq, lhs=v572, rhs_imm=0 } -> x1 v574 Imm(0) -> x0 - terminator Jmp(b190) (exit_acc=v573) - block 190 start_pc=0 - v575 Phi { incoming=[b270:v569, b189:v573], kind=I64 } -> x1 + terminator Jmp(b155) (exit_acc=v573) + block 155 start_pc=0 + v575 Phi { incoming=[b194:v569, b154:v573], kind=I64 } -> x1 v576 LoadLocal { off=-47, kind=I64 } -> x0 - terminator Bz { cond=v575, target=b192, fall=b191 } (exit_acc=v575) - block 191 start_pc=0 + terminator Bz { cond=v575, target=b157, fall=b156 } (exit_acc=v575) + block 156 start_pc=0 v577 ImmData(24) -> x0 v578 Imm(22) -> x1 v579 Store { addr=v577, disp=0, value=v578, kind=I32 } -> - - terminator Jmp(b192) (exit_acc=v579) - block 192 start_pc=0 - terminator Jmp(b185) - block 193 start_pc=0 + terminator Jmp(b157) (exit_acc=v579) + block 157 start_pc=0 + v559 Imm(0) -> x0 + terminator Jmp(b158) (exit_acc=v559) + block 158 start_pc=0 + v560 LocalAddr(-1) -> x0 + v561 Imm(0) -> x1 + v562 Store { addr=v560, disp=0, value=v561, kind=I32 } -> - + terminator Jmp(b159) (exit_acc=v562) + block 159 start_pc=0 v580 LoadLocal { off=-1, kind=I32 } -> x0 v581 BinopI { op=eq, lhs=v580, rhs_imm=0 } -> x0 v582 BinopI { op=eq, lhs=v581, rhs_imm=0 } -> x1 v583 Imm(0) -> x0 - terminator Bz { cond=v582, target=b271, fall=b196 } (exit_acc=v582) - block 194 start_pc=0 - v584 Imm(0) -> x0 - terminator Jmp(b195) (exit_acc=v584) - block 195 start_pc=0 - v585 Imm(0) -> x0 - v586 StoreLocal { off=-3, value=v585, kind=I8 } -> - - terminator Jmp(b200) (exit_acc=v586) - block 196 start_pc=0 + terminator Bz { cond=v582, target=b193, fall=b160 } (exit_acc=v582) + block 160 start_pc=0 v587 ImmData(24) -> x0 v588 Load { addr=v587, disp=0, kind=I32 } -> x0 v589 BinopI { op=eq, lhs=v588, rhs_imm=0 } -> x1 v590 Imm(0) -> x0 - terminator Jmp(b197) (exit_acc=v589) - block 197 start_pc=0 - v591 Phi { incoming=[b271:v582, b196:v589], kind=I64 } -> x1 + terminator Jmp(b161) (exit_acc=v589) + block 161 start_pc=0 + v591 Phi { incoming=[b193:v582, b160:v589], kind=I64 } -> x1 v592 LoadLocal { off=-49, kind=I64 } -> x0 - terminator Bz { cond=v591, target=b199, fall=b198 } (exit_acc=v591) - block 198 start_pc=0 + terminator Bz { cond=v591, target=b163, fall=b162 } (exit_acc=v591) + block 162 start_pc=0 v593 ImmData(24) -> x0 v594 Imm(23) -> x1 v595 Store { addr=v593, disp=0, value=v594, kind=I32 } -> - - terminator Jmp(b199) (exit_acc=v595) - block 199 start_pc=0 - terminator Jmp(b194) - block 200 start_pc=0 + terminator Jmp(b163) (exit_acc=v595) + block 163 start_pc=0 + v584 Imm(0) -> x0 + terminator Jmp(b164) (exit_acc=v584) + block 164 start_pc=0 + v585 Imm(0) -> x0 + v586 StoreLocal { off=-3, value=v585, kind=I8 } -> - + terminator Jmp(b165) (exit_acc=v586) + block 165 start_pc=0 v596 LocalAddr(-3) -> x0 v597 Imm(1) -> x1 v598 AtomicRmw { op=Xchg, addr=v596, value=v597, width=1 } -> x0 @@ -1006,42 +936,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v600 BinopI { op=eq, lhs=v599, rhs_imm=0 } -> x0 v601 Imm(0) -> x2 v602 Imm(0) -> x1 - terminator Bz { cond=v600, target=b272, fall=b203 } (exit_acc=v600) - block 201 start_pc=0 - v603 Imm(0) -> x0 - terminator Jmp(b202) (exit_acc=v603) - block 202 start_pc=0 - terminator Jmp(b209) - block 203 start_pc=0 + terminator Bz { cond=v600, target=b192, fall=b166 } (exit_acc=v600) + block 166 start_pc=0 v604 LoadLocal { off=-3, kind=U8 } -> x0 v605 BinopI { op=ne, lhs=v604, rhs_imm=0 } -> x0 v606 BinopI { op=ne, lhs=v605, rhs_imm=0 } -> x2 v607 Imm(0) -> x0 - terminator Jmp(b204) (exit_acc=v606) - block 204 start_pc=0 - v608 Phi { incoming=[b272:v601, b203:v606], kind=I64 } -> x2 + terminator Jmp(b167) (exit_acc=v606) + block 167 start_pc=0 + v608 Phi { incoming=[b192:v601, b166:v606], kind=I64 } -> x2 v609 LoadLocal { off=-51, kind=I64 } -> x0 v610 BinopI { op=eq, lhs=v608, rhs_imm=0 } -> x1 v611 Imm(0) -> x0 - terminator Bz { cond=v610, target=b273, fall=b205 } (exit_acc=v610) - block 205 start_pc=0 + terminator Bz { cond=v610, target=b191, fall=b168 } (exit_acc=v610) + block 168 start_pc=0 v612 ImmData(24) -> x0 v613 Load { addr=v612, disp=0, kind=I32 } -> x0 v614 BinopI { op=eq, lhs=v613, rhs_imm=0 } -> x1 v615 Imm(0) -> x0 - terminator Jmp(b206) (exit_acc=v614) - block 206 start_pc=0 - v616 Phi { incoming=[b273:v610, b205:v614], kind=I64 } -> x1 + terminator Jmp(b169) (exit_acc=v614) + block 169 start_pc=0 + v616 Phi { incoming=[b191:v610, b168:v614], kind=I64 } -> x1 v617 LoadLocal { off=-50, kind=I64 } -> x0 - terminator Bz { cond=v616, target=b208, fall=b207 } (exit_acc=v616) - block 207 start_pc=0 + terminator Bz { cond=v616, target=b171, fall=b170 } (exit_acc=v616) + block 170 start_pc=0 v618 ImmData(24) -> x0 v619 Imm(24) -> x1 v620 Store { addr=v618, disp=0, value=v619, kind=I32 } -> - - terminator Jmp(b208) (exit_acc=v620) - block 208 start_pc=0 - terminator Jmp(b201) - block 209 start_pc=0 + terminator Jmp(b171) (exit_acc=v620) + block 171 start_pc=0 + v603 Imm(0) -> x0 + terminator Jmp(b172) (exit_acc=v603) + block 172 start_pc=0 v621 LocalAddr(-3) -> x0 v622 Imm(1) -> x1 v623 AtomicRmw { op=Xchg, addr=v621, value=v622, width=1 } -> x0 @@ -1049,184 +975,258 @@ fn ent_pc=0 n_params=0 variadic=false locals=54 v625 BinopI { op=ne, lhs=v624, rhs_imm=0 } -> x0 v626 BinopI { op=eq, lhs=v625, rhs_imm=0 } -> x1 v627 Imm(0) -> x0 - terminator Bz { cond=v626, target=b274, fall=b212 } (exit_acc=v626) - block 210 start_pc=0 - v628 Imm(0) -> x0 - terminator Jmp(b211) (exit_acc=v628) - block 211 start_pc=0 - v629 LocalAddr(-3) -> x0 - v630 Imm(0) -> x1 - v631 Store { addr=v629, disp=0, value=v630, kind=I8 } -> - - terminator Jmp(b216) (exit_acc=v631) - block 212 start_pc=0 + terminator Bz { cond=v626, target=b190, fall=b173 } (exit_acc=v626) + block 173 start_pc=0 v632 ImmData(24) -> x0 v633 Load { addr=v632, disp=0, kind=I32 } -> x0 v634 BinopI { op=eq, lhs=v633, rhs_imm=0 } -> x1 v635 Imm(0) -> x0 - terminator Jmp(b213) (exit_acc=v634) - block 213 start_pc=0 - v636 Phi { incoming=[b274:v626, b212:v634], kind=I64 } -> x1 + terminator Jmp(b174) (exit_acc=v634) + block 174 start_pc=0 + v636 Phi { incoming=[b190:v626, b173:v634], kind=I64 } -> x1 v637 LoadLocal { off=-52, kind=I64 } -> x0 - terminator Bz { cond=v636, target=b215, fall=b214 } (exit_acc=v636) - block 214 start_pc=0 + terminator Bz { cond=v636, target=b176, fall=b175 } (exit_acc=v636) + block 175 start_pc=0 v638 ImmData(24) -> x0 v639 Imm(25) -> x1 v640 Store { addr=v638, disp=0, value=v639, kind=I32 } -> - - terminator Jmp(b215) (exit_acc=v640) - block 215 start_pc=0 - terminator Jmp(b210) - block 216 start_pc=0 + terminator Jmp(b176) (exit_acc=v640) + block 176 start_pc=0 + v628 Imm(0) -> x0 + terminator Jmp(b177) (exit_acc=v628) + block 177 start_pc=0 + v629 LocalAddr(-3) -> x0 + v630 Imm(0) -> x1 + v631 Store { addr=v629, disp=0, value=v630, kind=I8 } -> - + terminator Jmp(b178) (exit_acc=v631) + block 178 start_pc=0 v641 LoadLocal { off=-3, kind=U8 } -> x0 v642 BinopI { op=eq, lhs=v641, rhs_imm=0 } -> x0 v643 BinopI { op=eq, lhs=v642, rhs_imm=0 } -> x1 v644 Imm(0) -> x0 - terminator Bz { cond=v643, target=b275, fall=b219 } (exit_acc=v643) - block 217 start_pc=0 - v645 Imm(0) -> x0 - terminator Jmp(b218) (exit_acc=v645) - block 218 start_pc=0 - v646 Intrinsic { kind=43, args=[] } -> x0 - v647 Intrinsic { kind=43, args=[] } -> x0 - v648 Intrinsic { kind=43, args=[] } -> x0 - terminator Jmp(b223) (exit_acc=v648) - block 219 start_pc=0 + terminator Bz { cond=v643, target=b189, fall=b179 } (exit_acc=v643) + block 179 start_pc=0 v649 ImmData(24) -> x0 v650 Load { addr=v649, disp=0, kind=I32 } -> x0 v651 BinopI { op=eq, lhs=v650, rhs_imm=0 } -> x1 v652 Imm(0) -> x0 - terminator Jmp(b220) (exit_acc=v651) - block 220 start_pc=0 - v653 Phi { incoming=[b275:v643, b219:v651], kind=I64 } -> x1 + terminator Jmp(b180) (exit_acc=v651) + block 180 start_pc=0 + v653 Phi { incoming=[b189:v643, b179:v651], kind=I64 } -> x1 v654 LoadLocal { off=-53, kind=I64 } -> x0 - terminator Bz { cond=v653, target=b222, fall=b221 } (exit_acc=v653) - block 221 start_pc=0 + terminator Bz { cond=v653, target=b182, fall=b181 } (exit_acc=v653) + block 181 start_pc=0 v655 ImmData(24) -> x0 v656 Imm(26) -> x1 v657 Store { addr=v655, disp=0, value=v656, kind=I32 } -> - - terminator Jmp(b222) (exit_acc=v657) - block 222 start_pc=0 - terminator Jmp(b217) - block 223 start_pc=0 + terminator Jmp(b182) (exit_acc=v657) + block 182 start_pc=0 + v645 Imm(0) -> x0 + terminator Jmp(b183) (exit_acc=v645) + block 183 start_pc=0 + v646 Intrinsic { kind=43, args=[] } -> x0 + v647 Intrinsic { kind=43, args=[] } -> x0 + v648 Intrinsic { kind=43, args=[] } -> x0 + terminator Jmp(b184) (exit_acc=v648) + block 184 start_pc=0 v658 Imm(1) -> x0 v659 Imm(0) -> x1 v660 Imm(0) -> x0 - terminator Jmp(b227) (exit_acc=v659) - block 224 start_pc=0 + terminator Jmp(b185) (exit_acc=v659) + block 185 start_pc=0 + v668 Phi { incoming=[b184:v659, b274:v666], kind=I64 } -> x1 + v669 LoadLocal { off=-54, kind=I64 } -> x0 + terminator Bz { cond=v668, target=b187, fall=b186 } (exit_acc=v668) + block 186 start_pc=0 + v670 ImmData(24) -> x0 + v671 Imm(27) -> x1 + v672 Store { addr=v670, disp=0, value=v671, kind=I32 } -> - + terminator Jmp(b187) (exit_acc=v672) + block 187 start_pc=0 v661 Imm(0) -> x0 - terminator Jmp(b225) (exit_acc=v661) - block 225 start_pc=0 + terminator Jmp(b188) (exit_acc=v661) + block 188 start_pc=0 v662 ImmData(24) -> x0 v663 Load { addr=v662, disp=0, kind=I32 } -> x0 terminator Return(v663) (exit_acc=v663) + block 189 start_pc=0 + terminator Jmp(b180) + block 190 start_pc=0 + terminator Jmp(b174) + block 191 start_pc=0 + terminator Jmp(b169) + block 192 start_pc=0 + terminator Jmp(b167) + block 193 start_pc=0 + terminator Jmp(b161) + block 194 start_pc=0 + terminator Jmp(b155) + block 195 start_pc=0 + terminator Jmp(b153) + block 196 start_pc=0 + terminator Jmp(b147) + block 197 start_pc=0 + terminator Jmp(b145) + block 198 start_pc=0 + terminator Jmp(b140) + block 199 start_pc=0 + terminator Jmp(b138) + block 200 start_pc=0 + terminator Jmp(b133) + block 201 start_pc=0 + terminator Jmp(b131) + block 202 start_pc=0 + terminator Jmp(b126) + block 203 start_pc=0 + terminator Jmp(b124) + block 204 start_pc=0 + terminator Jmp(b118) + block 205 start_pc=0 + terminator Jmp(b116) + block 206 start_pc=0 + terminator Jmp(b111) + block 207 start_pc=0 + terminator Jmp(b109) + block 208 start_pc=0 + terminator Jmp(b104) + block 209 start_pc=0 + terminator Jmp(b102) + block 210 start_pc=0 + terminator Jmp(b96) + block 211 start_pc=0 + terminator Jmp(b94) + block 212 start_pc=0 + terminator Jmp(b89) + block 213 start_pc=0 + terminator Jmp(b87) + block 214 start_pc=0 + terminator Jmp(b82) + block 215 start_pc=0 + terminator Jmp(b80) + block 216 start_pc=0 + terminator Jmp(b74) + block 217 start_pc=0 + terminator Jmp(b72) + block 218 start_pc=0 + terminator Jmp(b70) + block 219 start_pc=0 + terminator Jmp(b64) + block 220 start_pc=0 + terminator Jmp(b62) + block 221 start_pc=0 + terminator Jmp(b56) + block 222 start_pc=0 + terminator Jmp(b54) + block 223 start_pc=0 + terminator Jmp(b49) + block 224 start_pc=0 + terminator Jmp(b47) + block 225 start_pc=0 + terminator Jmp(b42) block 226 start_pc=0 - v664 ImmData(24) -> x0 - v665 Load { addr=v664, disp=0, kind=I32 } -> x0 - v666 BinopI { op=eq, lhs=v665, rhs_imm=0 } -> x1 - v667 Imm(0) -> x0 - terminator Jmp(b227) (exit_acc=v666) + terminator Jmp(b40) block 227 start_pc=0 - v668 Phi { incoming=[b223:v659, b226:v666], kind=I64 } -> x1 - v669 LoadLocal { off=-54, kind=I64 } -> x0 - terminator Bz { cond=v668, target=b229, fall=b228 } (exit_acc=v668) + terminator Jmp(b34) block 228 start_pc=0 - v670 ImmData(24) -> x0 - v671 Imm(27) -> x1 - v672 Store { addr=v670, disp=0, value=v671, kind=I32 } -> - - terminator Jmp(b229) (exit_acc=v672) + terminator Jmp(b32) block 229 start_pc=0 - terminator Jmp(b224) + terminator Jmp(b27) block 230 start_pc=0 - terminator Jmp(b5) + terminator Jmp(b25) block 231 start_pc=0 - terminator Jmp(b12) - block 232 start_pc=0 terminator Jmp(b19) + block 232 start_pc=0 + terminator Jmp(b14) block 233 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b9) block 234 start_pc=0 - terminator Jmp(b33) + terminator Jmp(b3) block 235 start_pc=0 - terminator Jmp(b35) + terminator Jmp(b5) block 236 start_pc=0 - terminator Jmp(b42) + terminator Jmp(b12) block 237 start_pc=0 - terminator Jmp(b44) + terminator Jmp(b11) block 238 start_pc=0 - terminator Jmp(b51) + terminator Jmp(b17) block 239 start_pc=0 - terminator Jmp(b53) + terminator Jmp(b16) block 240 start_pc=0 - terminator Jmp(b60) + terminator Jmp(b21) block 241 start_pc=0 - terminator Jmp(b62) + terminator Jmp(b30) block 242 start_pc=0 - terminator Jmp(b69) + terminator Jmp(b29) block 243 start_pc=0 - terminator Jmp(b71) + terminator Jmp(b36) block 244 start_pc=0 - terminator Jmp(b78) + terminator Jmp(b45) block 245 start_pc=0 - terminator Jmp(b80) + terminator Jmp(b44) block 246 start_pc=0 - terminator Jmp(b87) + terminator Jmp(b52) block 247 start_pc=0 - terminator Jmp(b89) + terminator Jmp(b51) block 248 start_pc=0 - terminator Jmp(b91) + terminator Jmp(b58) block 249 start_pc=0 - terminator Jmp(b98) + terminator Jmp(b66) block 250 start_pc=0 - terminator Jmp(b100) + terminator Jmp(b76) block 251 start_pc=0 - terminator Jmp(b107) + terminator Jmp(b85) block 252 start_pc=0 - terminator Jmp(b109) + terminator Jmp(b84) block 253 start_pc=0 - terminator Jmp(b116) + terminator Jmp(b92) block 254 start_pc=0 - terminator Jmp(b118) + terminator Jmp(b91) block 255 start_pc=0 - terminator Jmp(b125) + terminator Jmp(b98) block 256 start_pc=0 - terminator Jmp(b127) + terminator Jmp(b107) block 257 start_pc=0 - terminator Jmp(b134) + terminator Jmp(b106) block 258 start_pc=0 - terminator Jmp(b136) + terminator Jmp(b114) block 259 start_pc=0 - terminator Jmp(b143) + terminator Jmp(b113) block 260 start_pc=0 - terminator Jmp(b145) + terminator Jmp(b120) block 261 start_pc=0 - terminator Jmp(b152) + terminator Jmp(b129) block 262 start_pc=0 - terminator Jmp(b154) + terminator Jmp(b128) block 263 start_pc=0 - terminator Jmp(b161) + terminator Jmp(b136) block 264 start_pc=0 - terminator Jmp(b163) + terminator Jmp(b135) block 265 start_pc=0 - terminator Jmp(b170) + terminator Jmp(b143) block 266 start_pc=0 - terminator Jmp(b172) + terminator Jmp(b142) block 267 start_pc=0 - terminator Jmp(b179) + terminator Jmp(b149) block 268 start_pc=0 - terminator Jmp(b181) + terminator Jmp(b157) block 269 start_pc=0 - terminator Jmp(b188) + terminator Jmp(b163) block 270 start_pc=0 - terminator Jmp(b190) + terminator Jmp(b172) block 271 start_pc=0 - terminator Jmp(b197) + terminator Jmp(b171) block 272 start_pc=0 - terminator Jmp(b204) + terminator Jmp(b176) block 273 start_pc=0 - terminator Jmp(b206) + terminator Jmp(b182) block 274 start_pc=0 - terminator Jmp(b213) + v664 ImmData(24) -> x0 + v665 Load { addr=v664, disp=0, kind=I32 } -> x0 + v666 BinopI { op=eq, lhs=v665, rhs_imm=0 } -> x1 + v667 Imm(0) -> x0 + terminator Jmp(b185) (exit_acc=v666) block 275 start_pc=0 - terminator Jmp(b220) + terminator Jmp(b187) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/gettimeofday_usec_range.ssa b/tests/snapshots/ssa/gettimeofday_usec_range.ssa index 8c28818a7..bc80976d9 100644 --- a/tests/snapshots/ssa/gettimeofday_usec_range.ssa +++ b/tests/snapshots/ssa/gettimeofday_usec_range.ssa @@ -6,62 +6,62 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b8) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x3 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=100 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) - block 3 start_pc=0 v9 LocalAddr(-2) -> x7 v10 Imm(0) -> x6 v11 CallExt { binding_idx=6, args=[v9, v10], fp_arg_mask=0x0 } -> x0 v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b6, fall=b5 } (exit_acc=v12) - block 4 start_pc=0 - v13 Imm(0) -> x0 - terminator Return(v13) (exit_acc=v13) - block 5 start_pc=0 - v14 Imm(1) -> x0 - terminator Return(v14) (exit_acc=v14) - block 6 start_pc=0 + terminator Bnz { cond=v12, target=b12, fall=b2 } (exit_acc=v12) + block 2 start_pc=0 v15 LocalAddr(-2) -> x0 v16 BinopI { op=add, lhs=v15, rhs_imm=8 } -> x1 v17 Load { addr=v15, disp=8, kind=I64 } -> x0 v18 BinopI { op=lt, lhs=v17, rhs_imm=0 } -> x1 v19 Imm(0) -> x0 - terminator Bnz { cond=v18, target=b13, fall=b7 } (exit_acc=v18) - block 7 start_pc=0 + terminator Bnz { cond=v18, target=b6, fall=b3 } (exit_acc=v18) + block 3 start_pc=0 v20 LocalAddr(-2) -> x0 v21 BinopI { op=add, lhs=v20, rhs_imm=8 } -> x1 v22 Load { addr=v20, disp=8, kind=I64 } -> x0 v23 BinopI { op=ge, lhs=v22, rhs_imm=1000000 } -> x1 v24 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v23) - block 8 start_pc=0 - v25 Phi { incoming=[b13:v18, b7:v23], kind=I64 } -> x1 + terminator Jmp(b4) (exit_acc=v23) + block 4 start_pc=0 + v25 Phi { incoming=[b6:v18, b3:v23], kind=I64 } -> x1 v26 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v25, target=b10, fall=b9 } (exit_acc=v25) - block 9 start_pc=0 - v27 Imm(2) -> x0 - terminator Return(v27) (exit_acc=v27) - block 10 start_pc=0 + terminator Bnz { cond=v25, target=b11, fall=b5 } (exit_acc=v25) + block 5 start_pc=0 v28 LocalAddr(-2) -> x0 v29 Load { addr=v28, disp=0, kind=I64 } -> x0 v30 BinopI { op=le, lhs=v29, rhs_imm=0 } -> x0 - terminator Bz { cond=v30, target=b12, fall=b11 } (exit_acc=v30) - block 11 start_pc=0 + terminator Bz { cond=v30, target=b7, fall=b10 } (exit_acc=v30) + block 6 start_pc=0 + terminator Jmp(b4) + block 7 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 + v8 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v7) + block 8 start_pc=0 + v3 Phi { incoming=[b0:v1, b7:v7], kind=I64 } -> x3 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=100 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b9 } (exit_acc=v5) + block 9 start_pc=0 + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) + block 10 start_pc=0 v31 Imm(3) -> x0 terminator Return(v31) (exit_acc=v31) + block 11 start_pc=0 + v27 Imm(2) -> x0 + terminator Return(v27) (exit_acc=v27) block 12 start_pc=0 - terminator Jmp(b2) + v14 Imm(1) -> x0 + terminator Return(v14) (exit_acc=v14) block 13 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/global_init_midexpr_cast_narrow.ssa b/tests/snapshots/ssa/global_init_midexpr_cast_narrow.ssa index b7b0424b1..cf8943995 100644 --- a/tests/snapshots/ssa/global_init_midexpr_cast_narrow.ssa +++ b/tests/snapshots/ssa/global_init_midexpr_cast_narrow.ssa @@ -9,7 +9,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ImmData(32) -> x0 @@ -57,18 +57,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 v23 ImmData(16) -> x0 v24 Load { addr=v23, disp=0, kind=I64 } -> x0 v25 ImmData(8) -> x1 - v26 Binop { op=ne, lhs=v24, rhs=v25 } -> x3 + v26 Binop { op=ne, lhs=v24, rhs=v25 } -> x1 v27 Imm(0) -> x0 terminator Bnz { cond=v26, target=b17, fall=b11 } (exit_acc=v26) block 11 start_pc=0 v28 ImmData(16) -> x0 v29 Load { addr=v28, disp=0, kind=I64 } -> x0 v30 Load { addr=v29, disp=0, kind=I32 } -> x0 - v31 BinopI { op=ne, lhs=v30, rhs_imm=99 } -> x3 + v31 BinopI { op=ne, lhs=v30, rhs_imm=99 } -> x1 v32 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v31) block 12 start_pc=0 - v33 Phi { incoming=[b17:v26, b11:v31], kind=I64 } -> x3 + v33 Phi { incoming=[b17:v26, b11:v31], kind=I64 } -> x1 v34 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v33, target=b14, fall=b13 } (exit_acc=v33) block 13 start_pc=0 diff --git a/tests/snapshots/ssa/global_struct_return_indirect.ssa b/tests/snapshots/ssa/global_struct_return_indirect.ssa index 7e8b742db..e3a2b9573 100644 --- a/tests/snapshots/ssa/global_struct_return_indirect.ssa +++ b/tests/snapshots/ssa/global_struct_return_indirect.ssa @@ -26,31 +26,31 @@ fn ent_pc=1 n_params=0 variadic=false locals=27 v10 BinopI { op=xor, lhs=v9, rhs_imm=1 } -> x0 v11 BinopI { op=and, lhs=v10, rhs_imm=4294967295 } -> x0 v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 - v13 Imm(1) -> x3 + v13 Imm(1) -> x2 v14 Imm(0) -> x1 - terminator Bnz { cond=v12, target=b9, fall=b1 } (exit_acc=v12) + terminator Bnz { cond=v12, target=b10, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v15 LocalAddr(-3) -> x0 v16 BinopI { op=add, lhs=v15, rhs_imm=4 } -> x1 v17 Load { addr=v15, disp=4, kind=I32 } -> x0 v18 BinopI { op=ne, lhs=v17, rhs_imm=2 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x3 + v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x2 v20 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v21 Phi { incoming=[b9:v13, b1:v19], kind=I64 } -> x3 + v21 Phi { incoming=[b10:v13, b1:v19], kind=I64 } -> x2 v22 LoadLocal { off=-19, kind=I64 } -> x0 v23 Imm(0) -> x0 - terminator Bnz { cond=v21, target=b10, fall=b3 } (exit_acc=v21) + terminator Bnz { cond=v21, target=b9, fall=b3 } (exit_acc=v21) block 3 start_pc=0 v24 LocalAddr(-3) -> x0 v25 BinopI { op=add, lhs=v24, rhs_imm=16 } -> x1 v26 Load { addr=v24, disp=16, kind=I32 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=5 } -> x3 + v27 BinopI { op=ne, lhs=v26, rhs_imm=5 } -> x2 v28 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v27) block 4 start_pc=0 - v29 Phi { incoming=[b10:v21, b3:v27], kind=I64 } -> x3 + v29 Phi { incoming=[b9:v21, b3:v27], kind=I64 } -> x2 v30 LoadLocal { off=-18, kind=I64 } -> x0 terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 @@ -83,9 +83,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=27 v51 Imm(0) -> x0 terminator Return(v51) (exit_acc=v51) block 9 start_pc=0 - terminator Jmp(b2) - block 10 start_pc=0 terminator Jmp(b4) + block 10 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/gnu_extension_keyword.ssa b/tests/snapshots/ssa/gnu_extension_keyword.ssa index 37e700170..4d77616bf 100644 --- a/tests/snapshots/ssa/gnu_extension_keyword.ssa +++ b/tests/snapshots/ssa/gnu_extension_keyword.ssa @@ -5,41 +5,41 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 Imm(0) -> x1 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(0) -> x0 v5 Imm(5) -> x6 - v6 Imm(0) -> x1 + v6 Imm(0) -> x0 v7 Imm(7) -> x2 - v8 Imm(30064771072) -> x1 - v9 Imm(0) -> x1 - v10 LoadLocal { off=-2, kind=I64 } -> x1 - v11 BinopI { op=ne, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) + v8 Imm(30064771072) -> x0 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-2, kind=I64 } -> x0 + v11 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v11) block 1 start_pc=0 - v12 Imm(1) -> x0 - terminator Return(v12) (exit_acc=v12) - block 2 start_pc=0 v13 LoadLocal { off=-3, kind=I64 } -> x0 - v14 BinopI { op=ne, lhs=v5, rhs_imm=5 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) - block 4 start_pc=0 + v14 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v14) + block 2 start_pc=0 v16 LoadLocal { off=-4, kind=I32 } -> x0 - v17 BinopI { op=ne, lhs=v7, rhs_imm=7 } -> x0 - terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) - block 5 start_pc=0 - v18 Imm(3) -> x0 - terminator Return(v18) (exit_acc=v18) - block 6 start_pc=0 + v17 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v17) + block 3 start_pc=0 v19 ImmData(36) -> x7 v20 LoadLocal { off=-3, kind=I64 } -> x0 v21 LoadLocal { off=-4, kind=I32 } -> x0 v22 CallExt { binding_idx=0, args=[v19, v5, v7], fp_arg_mask=0x0 } -> x0 v23 Imm(0) -> x0 terminator Return(v23) (exit_acc=v23) + block 4 start_pc=0 + v12 Imm(1) -> x0 + terminator Return(v12) (exit_acc=v12) + block 5 start_pc=0 + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) + block 6 start_pc=0 + v18 Imm(3) -> x0 + terminator Return(v18) (exit_acc=v18) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/goto.ssa b/tests/snapshots/ssa/goto.ssa index 5ffc40ec1..a1ee2beb2 100644 --- a/tests/snapshots/ssa/goto.ssa +++ b/tests/snapshots/ssa/goto.ssa @@ -4,33 +4,58 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x1 - v7 Extend { value=v5, kind=I32 } -> x1 - v8 Imm(0) -> x0 - v9 LoadLocal { off=-1, kind=I32 } -> x0 - v10 BinopI { op=lt, lhs=v7, rhs_imm=5 } -> x0 - terminator Bz { cond=v10, target=b3, fall=b2 } (exit_acc=v10) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 Imm(4294967296) -> x0 + v6 Imm(1) -> x0 + v7 Imm(0) -> x0 + v8 LoadLocal { off=-1, kind=I32 } -> x0 + v9 Imm(1) -> x0 + v10 Imm(1) -> x0 + v11 Imm(2) -> x0 + v12 Imm(8589934592) -> x0 + v13 Imm(2) -> x0 + v14 Imm(0) -> x0 + v15 LoadLocal { off=-1, kind=I32 } -> x0 + v16 Imm(1) -> x0 + v17 Imm(2) -> x0 + v18 Imm(3) -> x0 + v19 Imm(12884901888) -> x0 + v20 Imm(3) -> x0 + v21 Imm(0) -> x0 + v22 LoadLocal { off=-1, kind=I32 } -> x0 + v23 Imm(1) -> x0 + v24 Imm(3) -> x0 + v25 Imm(4) -> x0 + v26 Imm(17179869184) -> x0 + v27 Imm(4) -> x0 + v28 Imm(0) -> x0 + v29 LoadLocal { off=-1, kind=I32 } -> x0 + v30 Imm(1) -> x0 + v31 Imm(4) -> x0 + v32 Imm(5) -> x0 + v33 Imm(21474836480) -> x0 + v34 Imm(5) -> x0 + v35 Imm(0) -> x1 + v36 LoadLocal { off=-1, kind=I32 } -> x1 + v37 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v37) block 2 start_pc=0 - terminator Jmp(b1) + v38 LoadLocal { off=-1, kind=I32 } -> x1 + terminator Return(v34) (exit_acc=v34) block 3 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b2) block 4 start_pc=0 - v11 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v7) (exit_acc=v7) - block 5 start_pc=0 - v12 LoadLocal { off=-1, kind=I32 } -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=100 } -> x0 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x2 - v15 Extend { value=v13, kind=I32 } -> x2 - v16 StoreLocal { off=-1, value=v13, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v16) + v39 LoadLocal { off=-1, kind=I32 } -> x1 + v40 BinopI { op=add, lhs=v39, rhs_imm=100 } -> x1 + v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x2 + v42 Extend { value=v40, kind=I32 } -> x2 + v43 StoreLocal { off=-1, value=v40, kind=I32 } -> - + terminator Jmp(b2) (exit_acc=v43) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hex_constant_unsigned_type.ssa b/tests/snapshots/ssa/hex_constant_unsigned_type.ssa index 4ba8770e0..dedace0bc 100644 --- a/tests/snapshots/ssa/hex_constant_unsigned_type.ssa +++ b/tests/snapshots/ssa/hex_constant_unsigned_type.ssa @@ -5,35 +5,35 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-1) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=xor, lhs=v1, rhs_imm=4294967295 } -> x1 - v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x1 - v6 BinopI { op=ne, lhs=v5, rhs_imm=0 } -> x1 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(-4294967296) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v8 LoadLocal { off=-1, kind=I32 } -> x0 + v9 Imm(-4294967296) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v8 LoadLocal { off=-1, kind=I32 } -> x1 - v9 BinopI { op=xor, lhs=v1, rhs_imm=4294967295 } -> x1 - v10 BinopI { op=and, lhs=v9, rhs_imm=4294967295 } -> x1 - v11 BinopI { op=ne, lhs=v10, rhs_imm=0 } -> x1 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v13 LoadLocal { off=-1, kind=I32 } -> x0 + v14 Imm(1) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) block 3 start_pc=0 - v12 Imm(2) -> x0 - terminator Return(v12) (exit_acc=v12) + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) block 4 start_pc=0 - v13 LoadLocal { off=-1, kind=I32 } -> x1 - v14 BinopI { op=ne, lhs=v1, rhs_imm=4294967295 } -> x0 - v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 5 start_pc=0 + v12 Imm(2) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 v16 Imm(3) -> x0 terminator Return(v16) (exit_acc=v16) - block 6 start_pc=0 - v17 Imm(0) -> x0 - terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hex_float_literal.ssa b/tests/snapshots/ssa/hex_float_literal.ssa index 86d20e9a1..8b5445b1f 100644 --- a/tests/snapshots/ssa/hex_float_literal.ssa +++ b/tests/snapshots/ssa/hex_float_literal.ssa @@ -53,39 +53,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 v21 Imm(7) -> x0 terminator Return(v21) (exit_acc=v21) block 14 start_pc=0 - v22 Imm(4607182418800017408) -> x0 - v23 Binop { op=fne, lhs=v22, rhs=v22 } -> x0 - terminator Bz { cond=v23, target=b16, fall=b15 } (exit_acc=v23) + v22 Imm(1065353216) -> x0 [f32] + v23 Imm(4607182418800017408) -> x1 + v24 FpCast { kind=F32ToF64, value=v22 } -> d0 + v25 Binop { op=fne, lhs=v24, rhs=v23 } -> x0 + terminator Bz { cond=v25, target=b16, fall=b15 } (exit_acc=v25) block 15 start_pc=0 - v24 Imm(8) -> x0 - terminator Return(v24) (exit_acc=v24) + v26 Imm(8) -> x0 + terminator Return(v26) (exit_acc=v26) block 16 start_pc=0 - v25 Imm(4614254477589872640) -> x0 - v26 Binop { op=fne, lhs=v25, rhs=v25 } -> x0 - terminator Bz { cond=v26, target=b18, fall=b17 } (exit_acc=v26) + v27 Imm(4614254477589872640) -> x0 + v28 Binop { op=fne, lhs=v27, rhs=v27 } -> x0 + terminator Bz { cond=v28, target=b18, fall=b17 } (exit_acc=v28) block 17 start_pc=0 - v27 Imm(9) -> x0 - terminator Return(v27) (exit_acc=v27) + v29 Imm(9) -> x0 + terminator Return(v29) (exit_acc=v29) block 18 start_pc=0 - v28 Imm(4602678819172646912) -> x0 - v29 Fneg(v28) -> d0 - v30 Binop { op=fne, lhs=v29, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b20, fall=b19 } (exit_acc=v30) + v30 Imm(4602678819172646912) -> x0 + v31 Fneg(v30) -> d0 + v32 Binop { op=fne, lhs=v31, rhs=v31 } -> x0 + terminator Bz { cond=v32, target=b20, fall=b19 } (exit_acc=v32) block 19 start_pc=0 - v31 Imm(10) -> x0 - terminator Return(v31) (exit_acc=v31) + v33 Imm(10) -> x0 + terminator Return(v33) (exit_acc=v33) block 20 start_pc=0 - v32 Imm(4621819117588971520) -> x0 - v33 StoreLocal { off=-1, value=v32, kind=F64 } -> - - v34 LoadLocal { off=-1, kind=F64 } -> d0 - v35 Binop { op=fne, lhs=v34, rhs=v32 } -> x0 - terminator Bz { cond=v35, target=b22, fall=b21 } (exit_acc=v35) + v34 Imm(4621819117588971520) -> x0 + v35 StoreLocal { off=-1, value=v34, kind=F64 } -> - + v36 LoadLocal { off=-1, kind=F64 } -> d0 + v37 Binop { op=fne, lhs=v36, rhs=v34 } -> x0 + terminator Bz { cond=v37, target=b22, fall=b21 } (exit_acc=v37) block 21 start_pc=0 - v36 Imm(11) -> x0 - terminator Return(v36) (exit_acc=v36) + v38 Imm(11) -> x0 + terminator Return(v38) (exit_acc=v38) block 22 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) + v39 Imm(0) -> x0 + terminator Return(v39) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hfa_param_interleave.ssa b/tests/snapshots/ssa/hfa_param_interleave.ssa index 9df4cfbe4..a04eaf215 100644 --- a/tests/snapshots/ssa/hfa_param_interleave.ssa +++ b/tests/snapshots/ssa/hfa_param_interleave.ssa @@ -84,39 +84,35 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v17 LocalAddr(-2) -> x6 v18 LocalAddr(-3) -> x2 v19 LocalAddr(-4) -> x1 - v20 Imm(4621537642612260864) -> x0 - v21 FpCast { kind=F64ToF32, value=v20 } -> d0 [f32] - v22 LocalAddr(-5) -> x8 - v23 Call { target_pc=0, args=[v16, v17, v18, v19, v21, v22], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] - v24 Imm(4633007747913220096) -> x0 - v25 FpCast { kind=F32ToF64, value=v23 } -> d0 - v26 Binop { op=fne, lhs=v25, rhs=v24 } -> x0 - terminator Bz { cond=v26, target=b2, fall=b1 } (exit_acc=v26) + v20 Imm(1092091904) -> x8 [f32] + v21 LocalAddr(-5) -> x9 + v22 Call { target_pc=0, args=[v16, v17, v18, v19, v20, v21], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] + v23 Imm(1113456640) -> x0 [f32] + v24 Binop { op=fne, lhs=v22, rhs=v23 } -> x0 + terminator Bz { cond=v24, target=b2, fall=b1 } (exit_acc=v24) block 1 start_pc=0 - v27 Imm(1) -> x0 - terminator Return(v27) (exit_acc=v27) + v25 Imm(1) -> x0 + terminator Return(v25) (exit_acc=v25) block 2 start_pc=0 - v28 LocalAddr(-6) -> x0 - v29 ImmData(44) -> x1 - v30 Mcpy { dst=v28, src=v29, size=8 } -> x0 - v31 LocalAddr(-6) -> x7 - v32 LocalAddr(-6) -> x6 - v33 LocalAddr(-6) -> x2 - v34 LocalAddr(-6) -> x1 - v35 Imm(4598175219545276416) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 LocalAddr(-5) -> x8 - v38 Call { target_pc=0, args=[v31, v32, v33, v34, v36, v37], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] - v39 Imm(4621959855077326848) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b4, fall=b3 } (exit_acc=v41) + v26 LocalAddr(-6) -> x0 + v27 ImmData(44) -> x1 + v28 Mcpy { dst=v26, src=v27, size=8 } -> x0 + v29 LocalAddr(-6) -> x7 + v30 LocalAddr(-6) -> x6 + v31 LocalAddr(-6) -> x2 + v32 LocalAddr(-6) -> x1 + v33 Imm(1048576000) -> x8 [f32] + v34 LocalAddr(-5) -> x9 + v35 Call { target_pc=0, args=[v29, v30, v31, v32, v33, v34], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] + v36 Imm(1092878336) -> x0 [f32] + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b4, fall=b3 } (exit_acc=v37) block 3 start_pc=0 - v42 Imm(2) -> x0 - terminator Return(v42) (exit_acc=v42) + v38 Imm(2) -> x0 + terminator Return(v38) (exit_acc=v38) block 4 start_pc=0 - v43 Imm(0) -> x0 - terminator Return(v43) (exit_acc=v43) + v39 Imm(0) -> x0 + terminator Return(v39) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hfa_struct_return.ssa b/tests/snapshots/ssa/hfa_struct_return.ssa index 8c8399831..94d38524a 100644 --- a/tests/snapshots/ssa/hfa_struct_return.ssa +++ b/tests/snapshots/ssa/hfa_struct_return.ssa @@ -153,7 +153,7 @@ fn ent_pc=7 n_params=1 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=8 --- ; name=main fn ent_pc=8 n_params=0 variadic=false locals=45 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4619567317775286272) -> x3 @@ -177,19 +177,19 @@ fn ent_pc=8 n_params=0 variadic=false locals=45 v15 Mcpy { dst=v14, src=v13, size=16 } -> x0 v16 LocalAddr(-4) -> x0 v17 Load { addr=v16, disp=0, kind=F64 } -> d0 - v18 Binop { op=fne, lhs=v17, rhs=v10 } -> x3 + v18 Binop { op=fne, lhs=v17, rhs=v10 } -> x1 v19 Imm(0) -> x0 - terminator Bnz { cond=v18, target=b31, fall=b3 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b37, fall=b3 } (exit_acc=v18) block 3 start_pc=0 v20 LocalAddr(-4) -> x0 v21 BinopI { op=add, lhs=v20, rhs_imm=8 } -> x1 v22 Load { addr=v20, disp=8, kind=F64 } -> d0 v23 Imm(4602678819172646912) -> x0 - v24 Binop { op=fne, lhs=v22, rhs=v23 } -> x3 + v24 Binop { op=fne, lhs=v22, rhs=v23 } -> x1 v25 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v24) block 4 start_pc=0 - v26 Phi { incoming=[b31:v18, b3:v24], kind=I64 } -> x3 + v26 Phi { incoming=[b37:v18, b3:v24], kind=I64 } -> x1 v27 LoadLocal { off=-29, kind=I64 } -> x0 terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) block 5 start_pc=0 @@ -209,33 +209,33 @@ fn ent_pc=8 n_params=0 variadic=false locals=45 v39 LocalAddr(-9) -> x0 v40 Load { addr=v39, disp=0, kind=F64 } -> d0 v41 Binop { op=fne, lhs=v40, rhs=v32 } -> x0 - v42 Imm(1) -> x3 + v42 Imm(1) -> x2 v43 Imm(0) -> x1 - terminator Bnz { cond=v41, target=b32, fall=b7 } (exit_acc=v41) + terminator Bnz { cond=v41, target=b36, fall=b7 } (exit_acc=v41) block 7 start_pc=0 v44 LocalAddr(-9) -> x0 v45 BinopI { op=add, lhs=v44, rhs_imm=8 } -> x1 v46 Load { addr=v44, disp=8, kind=F64 } -> d0 v47 Imm(4611686018427387904) -> x0 v48 Binop { op=fne, lhs=v46, rhs=v47 } -> x0 - v49 BinopI { op=ne, lhs=v48, rhs_imm=0 } -> x3 + v49 BinopI { op=ne, lhs=v48, rhs_imm=0 } -> x2 v50 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v49) block 8 start_pc=0 - v51 Phi { incoming=[b32:v42, b7:v49], kind=I64 } -> x3 + v51 Phi { incoming=[b36:v42, b7:v49], kind=I64 } -> x2 v52 LoadLocal { off=-35, kind=I64 } -> x0 v53 Imm(0) -> x0 - terminator Bnz { cond=v51, target=b33, fall=b9 } (exit_acc=v51) + terminator Bnz { cond=v51, target=b35, fall=b9 } (exit_acc=v51) block 9 start_pc=0 v54 LocalAddr(-9) -> x0 v55 BinopI { op=add, lhs=v54, rhs_imm=16 } -> x1 v56 Load { addr=v54, disp=16, kind=F64 } -> d0 v57 Imm(4613937818241073152) -> x0 - v58 Binop { op=fne, lhs=v56, rhs=v57 } -> x3 + v58 Binop { op=fne, lhs=v56, rhs=v57 } -> x2 v59 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v58) block 10 start_pc=0 - v60 Phi { incoming=[b33:v51, b9:v58], kind=I64 } -> x3 + v60 Phi { incoming=[b35:v51, b9:v58], kind=I64 } -> x2 v61 LoadLocal { off=-34, kind=I64 } -> x0 terminator Bz { cond=v60, target=b12, fall=b11 } (exit_acc=v60) block 11 start_pc=0 @@ -256,7 +256,7 @@ fn ent_pc=8 n_params=0 variadic=false locals=45 v74 LocalAddr(-16) -> x0 v75 Load { addr=v74, disp=0, kind=F64 } -> d0 v76 Binop { op=fne, lhs=v75, rhs=v66 } -> x0 - v77 Imm(1) -> x3 + v77 Imm(1) -> x2 v78 Imm(0) -> x1 terminator Bnz { cond=v76, target=b34, fall=b13 } (exit_acc=v76) block 13 start_pc=0 @@ -265,123 +265,118 @@ fn ent_pc=8 n_params=0 variadic=false locals=45 v81 Load { addr=v79, disp=8, kind=F64 } -> d0 v82 Imm(4626322717216342016) -> x0 v83 Binop { op=fne, lhs=v81, rhs=v82 } -> x0 - v84 BinopI { op=ne, lhs=v83, rhs_imm=0 } -> x3 + v84 BinopI { op=ne, lhs=v83, rhs_imm=0 } -> x2 v85 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v84) block 14 start_pc=0 - v86 Phi { incoming=[b34:v77, b13:v84], kind=I64 } -> x3 + v86 Phi { incoming=[b34:v77, b13:v84], kind=I64 } -> x2 v87 LoadLocal { off=-43, kind=I64 } -> x0 - v88 Imm(1) -> x12 + v88 Imm(1) -> x1 v89 Imm(0) -> x0 - terminator Bnz { cond=v86, target=b35, fall=b15 } (exit_acc=v86) + terminator Bnz { cond=v86, target=b33, fall=b15 } (exit_acc=v86) block 15 start_pc=0 v90 LocalAddr(-16) -> x0 v91 BinopI { op=add, lhs=v90, rhs_imm=16 } -> x1 v92 Load { addr=v90, disp=16, kind=F64 } -> d0 v93 Imm(4629137466983448576) -> x0 v94 Binop { op=fne, lhs=v92, rhs=v93 } -> x0 - v95 BinopI { op=ne, lhs=v94, rhs_imm=0 } -> x12 + v95 BinopI { op=ne, lhs=v94, rhs_imm=0 } -> x1 v96 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v95) block 16 start_pc=0 - v97 Phi { incoming=[b35:v88, b15:v95], kind=I64 } -> x12 + v97 Phi { incoming=[b33:v88, b15:v95], kind=I64 } -> x1 v98 LoadLocal { off=-42, kind=I64 } -> x0 v99 Imm(0) -> x0 - terminator Bnz { cond=v97, target=b36, fall=b17 } (exit_acc=v97) + terminator Bnz { cond=v97, target=b32, fall=b17 } (exit_acc=v97) block 17 start_pc=0 v100 LocalAddr(-16) -> x0 v101 BinopI { op=add, lhs=v100, rhs_imm=24 } -> x1 v102 Load { addr=v100, disp=24, kind=F64 } -> d0 v103 Imm(4630826316843712512) -> x0 - v104 Binop { op=fne, lhs=v102, rhs=v103 } -> x12 + v104 Binop { op=fne, lhs=v102, rhs=v103 } -> x1 v105 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v104) block 18 start_pc=0 - v106 Phi { incoming=[b36:v97, b17:v104], kind=I64 } -> x12 + v106 Phi { incoming=[b32:v97, b17:v104], kind=I64 } -> x1 v107 LoadLocal { off=-41, kind=I64 } -> x0 terminator Bz { cond=v106, target=b20, fall=b19 } (exit_acc=v106) block 19 start_pc=0 v108 Imm(4) -> x0 terminator Return(v108) (exit_acc=v108) block 20 start_pc=0 - v109 Imm(4609434218613702656) -> x3 - v110 FpCast { kind=F64ToF32, value=v109 } -> d0 [f32] - v111 Imm(4612811918334230528) -> x0 - v112 FpCast { kind=F64ToF32, value=v111 } -> d1 [f32] - v113 Call { target_pc=4, args=[v110, v112], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v114 LocalAddr(-44) -> x0 - v115 LocalAddr(-21) -> x1 - v116 Mcpy { dst=v115, src=v114, size=8 } -> x0 - v117 LocalAddr(-21) -> x0 - v118 Load { addr=v117, disp=0, kind=F32 } -> d0 [f32] - v119 FpCast { kind=F32ToF64, value=v118 } -> d0 - v120 Binop { op=fne, lhs=v119, rhs=v109 } -> x3 - v121 Imm(0) -> x0 - terminator Bnz { cond=v120, target=b37, fall=b21 } (exit_acc=v120) + v109 Imm(1069547520) -> x3 [f32] + v110 Imm(1075838976) -> x6 [f32] + v111 Call { target_pc=4, args=[v109, v110], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v112 LocalAddr(-44) -> x0 + v113 LocalAddr(-21) -> x1 + v114 Mcpy { dst=v113, src=v112, size=8 } -> x0 + v115 LocalAddr(-21) -> x0 + v116 Load { addr=v115, disp=0, kind=F32 } -> d0 [f32] + v117 Binop { op=fne, lhs=v116, rhs=v109 } -> x1 + v118 Imm(0) -> x0 + terminator Bnz { cond=v117, target=b31, fall=b21 } (exit_acc=v117) block 21 start_pc=0 - v122 LocalAddr(-21) -> x0 - v123 BinopI { op=add, lhs=v122, rhs_imm=4 } -> x1 - v124 Load { addr=v122, disp=4, kind=F32 } -> d0 [f32] - v125 Imm(4612811918334230528) -> x0 - v126 FpCast { kind=F32ToF64, value=v124 } -> d0 - v127 Binop { op=fne, lhs=v126, rhs=v125 } -> x3 - v128 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v127) + v119 LocalAddr(-21) -> x0 + v120 BinopI { op=add, lhs=v119, rhs_imm=4 } -> x1 + v121 Load { addr=v119, disp=4, kind=F32 } -> d0 [f32] + v122 Imm(1075838976) -> x0 [f32] + v123 Binop { op=fne, lhs=v121, rhs=v122 } -> x1 + v124 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v123) block 22 start_pc=0 - v129 Phi { incoming=[b37:v120, b21:v127], kind=I64 } -> x3 - v130 LoadLocal { off=-45, kind=I64 } -> x0 - terminator Bz { cond=v129, target=b24, fall=b23 } (exit_acc=v129) + v125 Phi { incoming=[b31:v117, b21:v123], kind=I64 } -> x1 + v126 LoadLocal { off=-45, kind=I64 } -> x0 + terminator Bz { cond=v125, target=b24, fall=b23 } (exit_acc=v125) block 23 start_pc=0 - v131 Imm(5) -> x0 - terminator Return(v131) (exit_acc=v131) + v127 Imm(5) -> x0 + terminator Return(v127) (exit_acc=v127) block 24 start_pc=0 - v132 LocalAddr(-24) -> x0 - v133 ImmData(8) -> x1 - v134 Mcpy { dst=v132, src=v133, size=16 } -> x0 - v135 LocalAddr(-4) -> x7 - v136 Call { target_pc=5, args=[v135], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v137 Imm(4604930618986332160) -> x0 - v138 Binop { op=fne, lhs=v136, rhs=v137 } -> x0 - terminator Bz { cond=v138, target=b26, fall=b25 } (exit_acc=v138) + v128 LocalAddr(-24) -> x0 + v129 ImmData(8) -> x1 + v130 Mcpy { dst=v128, src=v129, size=16 } -> x0 + v131 LocalAddr(-4) -> x7 + v132 Call { target_pc=5, args=[v131], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v133 Imm(4604930618986332160) -> x0 + v134 Binop { op=fne, lhs=v132, rhs=v133 } -> x0 + terminator Bz { cond=v134, target=b26, fall=b25 } (exit_acc=v134) block 25 start_pc=0 - v139 Imm(6) -> x0 - terminator Return(v139) (exit_acc=v139) + v135 Imm(6) -> x0 + terminator Return(v135) (exit_acc=v135) block 26 start_pc=0 - v140 LocalAddr(-16) -> x7 - v141 Call { target_pc=6, args=[v140], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v142 Imm(4636737291354636288) -> x0 - v143 Binop { op=fne, lhs=v141, rhs=v142 } -> x0 - terminator Bz { cond=v143, target=b28, fall=b27 } (exit_acc=v143) + v136 LocalAddr(-16) -> x7 + v137 Call { target_pc=6, args=[v136], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v138 Imm(4636737291354636288) -> x0 + v139 Binop { op=fne, lhs=v137, rhs=v138 } -> x0 + terminator Bz { cond=v139, target=b28, fall=b27 } (exit_acc=v139) block 27 start_pc=0 - v144 Imm(7) -> x0 - terminator Return(v144) (exit_acc=v144) + v140 Imm(7) -> x0 + terminator Return(v140) (exit_acc=v140) block 28 start_pc=0 - v145 LocalAddr(-24) -> x7 - v146 Call { target_pc=7, args=[v145], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v147 Imm(4621819117588971520) -> x0 - v148 FpCast { kind=F32ToF64, value=v146 } -> d0 - v149 Binop { op=fne, lhs=v148, rhs=v147 } -> x0 - terminator Bz { cond=v149, target=b30, fall=b29 } (exit_acc=v149) + v141 LocalAddr(-24) -> x7 + v142 Call { target_pc=7, args=[v141], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v143 Imm(1092616192) -> x0 [f32] + v144 Binop { op=fne, lhs=v142, rhs=v143 } -> x0 + terminator Bz { cond=v144, target=b30, fall=b29 } (exit_acc=v144) block 29 start_pc=0 - v150 Imm(8) -> x0 - terminator Return(v150) (exit_acc=v150) + v145 Imm(8) -> x0 + terminator Return(v145) (exit_acc=v145) block 30 start_pc=0 - v151 Imm(0) -> x0 - terminator Return(v151) (exit_acc=v151) + v146 Imm(0) -> x0 + terminator Return(v146) (exit_acc=v146) block 31 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b22) block 32 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b18) block 33 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b16) block 34 start_pc=0 terminator Jmp(b14) block 35 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b10) block 36 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b8) block 37 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/implicit_int_decl.ssa b/tests/snapshots/ssa/implicit_int_decl.ssa index c8b516a1c..233b1ce0e 100644 --- a/tests/snapshots/ssa/implicit_int_decl.ssa +++ b/tests/snapshots/ssa/implicit_int_decl.ssa @@ -18,27 +18,27 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(41) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 BinopI { op=ne, lhs=v6, rhs_imm=42 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(41) -> x0 + v3 Imm(0) -> x0 + v4 Imm(42) -> x0 + v5 Imm(180388626432) -> x0 + v6 Imm(42) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 ImmData(8) -> x0 v10 Load { addr=v9, disp=0, kind=I32 } -> x0 v11 BinopI { op=ne, lhs=v10, rhs_imm=5 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 3 start_pc=0 + terminator Bz { cond=v11, target=b3, fall=b2 } (exit_acc=v11) + block 2 start_pc=0 v12 Imm(2) -> x0 terminator Return(v12) (exit_acc=v12) - block 4 start_pc=0 + block 3 start_pc=0 v13 Imm(0) -> x0 terminator Return(v13) (exit_acc=v13) + block 4 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inc_dec_step_one.ssa b/tests/snapshots/ssa/inc_dec_step_one.ssa index 2a4dce388..98082257f 100644 --- a/tests/snapshots/ssa/inc_dec_step_one.ssa +++ b/tests/snapshots/ssa/inc_dec_step_one.ssa @@ -57,26 +57,26 @@ fn ent_pc=4 n_params=1 variadic=false locals=2 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v17], kind=I64 } -> x0 - v8 Extend { value=v6, kind=I32 } -> x2 - v9 LoadLocal { off=2, kind=I32 } -> x6 - v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v14 Extend { value=v7, kind=I32 } -> x6 + v15 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x6 + v17 Extend { value=v15, kind=I32 } -> x0 + v18 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 v11 Extend { value=v6, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) + terminator Jmp(b3) (exit_acc=v12) block 3 start_pc=0 - v14 Extend { value=v7, kind=I32 } -> x2 - v15 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x2 - v17 Extend { value=v15, kind=I32 } -> x0 - v18 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v17) + v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b2:v17], kind=I64 } -> x0 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 LoadLocal { off=2, kind=I32 } -> x6 + v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v19 Extend { value=v7, kind=I32 } -> x0 terminator Return(v19) (exit_acc=v19) @@ -99,79 +99,79 @@ fn ent_pc=6 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(41) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 BinopI { op=ne, lhs=v6, rhs_imm=42 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(41) -> x0 + v3 Imm(0) -> x0 + v4 Imm(42) -> x0 + v5 Imm(180388626432) -> x0 + v6 Imm(42) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 Imm(43) -> x0 - v10 Extend { value=v9, kind=I32 } -> x1 - v11 Imm(0) -> x1 - v12 BinopI { op=sub, lhs=v9, rhs_imm=1 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x0 - v15 BinopI { op=ne, lhs=v14, rhs_imm=42 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) - block 4 start_pc=0 + v10 Imm(43) -> x0 + v11 Imm(0) -> x0 + v12 Imm(42) -> x0 + v13 Imm(180388626432) -> x0 + v14 Imm(42) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) + block 2 start_pc=0 v17 Imm(9999999999) -> x0 - v18 Imm(0) -> x1 - v19 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x0 - v20 BinopI { op=ne, lhs=v19, rhs_imm=10000000000 } -> x0 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) - block 5 start_pc=0 - v21 Imm(3) -> x0 - terminator Return(v21) (exit_acc=v21) - block 6 start_pc=0 + v18 Imm(0) -> x0 + v19 Imm(10000000000) -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v20) + block 3 start_pc=0 v22 Imm(41) -> x0 - v23 Imm(0) -> x1 - v24 BinopI { op=sub, lhs=v22, rhs_imm=-1 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=42 } -> x0 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) - block 7 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) - block 8 start_pc=0 + v23 Imm(0) -> x0 + v24 Imm(42) -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v25) + block 4 start_pc=0 v27 Imm(42) -> x7 v28 Call { target_pc=4, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=42 } -> x0 - terminator Bz { cond=v29, target=b10, fall=b9 } (exit_acc=v29) - block 9 start_pc=0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) + block 5 start_pc=0 v30 Imm(5) -> x0 terminator Return(v30) (exit_acc=v30) - block 10 start_pc=0 + block 6 start_pc=0 v31 Imm(4294967295) -> x0 - v32 Imm(0) -> x1 - v33 BinopI { op=and, lhs=v31, rhs_imm=4294967295 } -> x0 - v34 BinopI { op=add, lhs=v33, rhs_imm=1 } -> x0 - v35 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x0 - v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) + v32 Imm(0) -> x0 + v33 Imm(4294967295) -> x0 + v34 Imm(4294967296) -> x0 + v35 Imm(0) -> x0 + v36 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v36) + block 7 start_pc=0 + v38 Imm(41) -> x0 + v39 Imm(0) -> x0 + v40 Imm(41) -> x0 + v41 Imm(42) -> x0 + v42 Imm(42) -> x0 + v43 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v43) + block 8 start_pc=0 + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) + block 9 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) + block 10 start_pc=0 + v16 Imm(2) -> x0 + terminator Return(v16) (exit_acc=v16) block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) block 12 start_pc=0 - v38 Imm(41) -> x0 - v39 Imm(0) -> x1 - v40 BinopI { op=and, lhs=v38, rhs_imm=4294967295 } -> x0 - v41 BinopI { op=add, lhs=v40, rhs_imm=1 } -> x0 - v42 BinopI { op=and, lhs=v41, rhs_imm=4294967295 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=42 } -> x0 - terminator Bz { cond=v43, target=b14, fall=b13 } (exit_acc=v43) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) block 13 start_pc=0 + v37 Imm(6) -> x0 + terminator Return(v37) (exit_acc=v37) + block 14 start_pc=0 v44 Imm(7) -> x0 terminator Return(v44) (exit_acc=v44) - block 14 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/include_macro_operand.ssa b/tests/snapshots/ssa/include_macro_operand.ssa index 862302d92..943a3d190 100644 --- a/tests/snapshots/ssa/include_macro_operand.ssa +++ b/tests/snapshots/ssa/include_macro_operand.ssa @@ -1,12 +1,12 @@ ; --- SSA dump (ok=true) ent_pc=5 --- ; name=main fn ent_pc=5 n_params=0 variadic=false locals=4 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(-1) -> x3 + v1 Imm(-1) -> x0 v2 Imm(0) -> x0 - v3 Imm(42) -> x12 + v3 Imm(42) -> x0 v4 Imm(0) -> x0 v5 Imm(8) -> x7 v6 CallExt { binding_idx=0, args=[v5], fp_arg_mask=0x0 } -> x7 @@ -21,21 +21,21 @@ fn ent_pc=5 n_params=0 variadic=false locals=4 v11 LoadLocal { off=-3, kind=I64 } -> x0 v12 CallExt { binding_idx=3, args=[v6], fp_arg_mask=0x0 } -> x0 v13 LoadLocal { off=-1, kind=I8 } -> x0 - v14 BinopI { op=ne, lhs=v1, rhs_imm=-1 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v14 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) - block 4 start_pc=0 v16 LoadLocal { off=-2, kind=I32 } -> x0 - v17 BinopI { op=ne, lhs=v3, rhs_imm=42 } -> x0 - terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) + v17 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v17) + block 4 start_pc=0 + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) block 5 start_pc=0 + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) + block 6 start_pc=0 v18 Imm(3) -> x0 terminator Return(v18) (exit_acc=v18) - block 6 start_pc=0 - v19 Imm(0) -> x0 - terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indexed_load_store.ssa b/tests/snapshots/ssa/indexed_load_store.ssa index f5990dd00..082b94599 100644 --- a/tests/snapshots/ssa/indexed_load_store.ssa +++ b/tests/snapshots/ssa/indexed_load_store.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=work fn ent_pc=0 n_params=4 variadic=false locals=4 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13, 14] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -15,62 +15,62 @@ fn ent_pc=0 n_params=4 variadic=false locals=4 v9 Imm(0) -> x8 v10 Imm(0) -> x0 v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v12 Phi { incoming=[b0:v9, b2:v59], kind=I64 } -> x8 - v13 Phi { incoming=[b0:v9, b2:v18], kind=I64 } -> x0 - v14 Extend { value=v13, kind=I32 } -> x9 - v15 LoadLocal { off=4, kind=I32 } -> x3 - v16 Binop { op=lt, lhs=v14, rhs=v5 } -> x9 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) - block 2 start_pc=0 - v17 Extend { value=v13, kind=I32 } -> x0 - v18 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x0 - v19 Imm(0) -> x9 - terminator Jmp(b1) (exit_acc=v18) - block 3 start_pc=0 - v20 LoadLocal { off=2, kind=I64 } -> x9 - v21 Extend { value=v13, kind=I32 } -> x9 - v22 BinopI { op=shl, lhs=v21, rhs_imm=2 } -> x9 - v23 Binop { op=add, lhs=v1, rhs=v22 } -> x3 - v24 Load { addr=v23, disp=0, kind=I32 } -> x12 - v25 LoadLocal { off=5, kind=I32 } -> x13 - v26 Binop { op=add, lhs=v24, rhs=v7 } -> x12 - v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x13 - v28 Extend { value=v26, kind=I32 } -> x13 - v29 Imm(0) -> x13 - v30 LoadLocal { off=3, kind=I64 } -> x13 - v31 Binop { op=add, lhs=v3, rhs=v22 } -> x9 - v32 Load { addr=v31, disp=0, kind=I32 } -> x9 - v33 Binop { op=sub, lhs=v32, rhs=v7 } -> x9 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x13 - v35 Extend { value=v33, kind=I32 } -> x13 - v36 Imm(0) -> x13 - v37 LoadLocal { off=-4, kind=I32 } -> x13 + v20 LoadLocal { off=2, kind=I64 } -> x3 + v21 Extend { value=v13, kind=I32 } -> x3 + v22 BinopI { op=shl, lhs=v14, rhs_imm=2 } -> x3 + v23 Binop { op=add, lhs=v1, rhs=v22 } -> x12 + v24 Load { addr=v23, disp=0, kind=I32 } -> x13 + v25 LoadLocal { off=5, kind=I32 } -> x14 + v26 Binop { op=add, lhs=v24, rhs=v7 } -> x13 + v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x14 + v28 Extend { value=v26, kind=I32 } -> x14 + v29 Imm(0) -> x14 + v30 LoadLocal { off=3, kind=I64 } -> x14 + v31 Binop { op=add, lhs=v3, rhs=v22 } -> x3 + v32 Load { addr=v31, disp=0, kind=I32 } -> x3 + v33 Binop { op=sub, lhs=v32, rhs=v7 } -> x3 + v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x14 + v35 Extend { value=v33, kind=I32 } -> x14 + v36 Imm(0) -> x14 + v37 LoadLocal { off=-4, kind=I32 } -> x14 v38 Store { addr=v23, disp=0, value=v33, kind=I32 } -> - - v39 LoadLocal { off=3, kind=I64 } -> x9 - v40 Extend { value=v13, kind=I32 } -> x9 - v41 BinopI { op=shl, lhs=v40, rhs_imm=2 } -> x3 + v39 LoadLocal { off=3, kind=I64 } -> x3 + v40 Extend { value=v13, kind=I32 } -> x3 + v41 BinopI { op=shl, lhs=v14, rhs_imm=2 } -> x3 v42 Binop { op=add, lhs=v3, rhs=v41 } -> x3 v43 LoadLocal { off=-3, kind=I32 } -> x3 - v44 StoreIndexed { base=v3, index=v40, scale=4, value=v26, kind=I32 } -> - - v45 Extend { value=v12, kind=I32 } -> x9 - v46 LoadLocal { off=2, kind=I64 } -> x9 - v47 Extend { value=v13, kind=I32 } -> x9 - v48 BinopI { op=shl, lhs=v47, rhs_imm=2 } -> x9 - v49 Binop { op=add, lhs=v1, rhs=v48 } -> x3 - v50 Load { addr=v49, disp=0, kind=I32 } -> x3 - v51 LoadLocal { off=3, kind=I64 } -> x12 - v52 Binop { op=add, lhs=v3, rhs=v48 } -> x9 - v53 Load { addr=v52, disp=0, kind=I32 } -> x9 - v54 Binop { op=mul, lhs=v50, rhs=v53 } -> x9 - v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x3 - v56 Extend { value=v54, kind=I32 } -> x3 + v44 StoreIndexed { base=v3, index=v14, scale=4, value=v26, kind=I32 } -> - + v45 Extend { value=v12, kind=I32 } -> x3 + v46 LoadLocal { off=2, kind=I64 } -> x3 + v47 Extend { value=v13, kind=I32 } -> x3 + v48 BinopI { op=shl, lhs=v14, rhs_imm=2 } -> x3 + v49 Binop { op=add, lhs=v1, rhs=v48 } -> x12 + v50 Load { addr=v49, disp=0, kind=I32 } -> x12 + v51 LoadLocal { off=3, kind=I64 } -> x13 + v52 Binop { op=add, lhs=v3, rhs=v48 } -> x3 + v53 Load { addr=v52, disp=0, kind=I32 } -> x3 + v54 Binop { op=mul, lhs=v50, rhs=v53 } -> x3 + v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x12 + v56 Extend { value=v54, kind=I32 } -> x12 v57 Binop { op=add, lhs=v12, rhs=v54 } -> x8 - v58 BinopI { op=shl, lhs=v57, rhs_imm=32 } -> x9 + v58 BinopI { op=shl, lhs=v57, rhs_imm=32 } -> x3 v59 Extend { value=v57, kind=I32 } -> x8 - v60 Imm(0) -> x9 + v60 Imm(0) -> x3 terminator Jmp(b2) (exit_acc=v59) + block 2 start_pc=0 + v17 Extend { value=v13, kind=I32 } -> x0 + v18 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x0 + v19 Imm(0) -> x9 + terminator Jmp(b3) (exit_acc=v18) + block 3 start_pc=0 + v12 Phi { incoming=[b0:v9, b2:v59], kind=I64 } -> x8 + v13 Phi { incoming=[b0:v9, b2:v18], kind=I64 } -> x0 + v14 Extend { value=v13, kind=I32 } -> x9 + v15 LoadLocal { off=4, kind=I32 } -> x3 + v16 Binop { op=lt, lhs=v14, rhs=v5 } -> x3 + terminator Bnz { cond=v16, target=b1, fall=b4 } (exit_acc=v16) block 4 start_pc=0 v61 Extend { value=v12, kind=I32 } -> x0 terminator Return(v61) (exit_acc=v61) @@ -80,60 +80,225 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=8 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-4) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(1) -> x1 + v10 Imm(4294967296) -> x1 + v11 Imm(1) -> x1 + v12 Store { addr=v8, disp=0, value=v11, kind=I32 } -> - + v13 LocalAddr(-8) -> x0 + v14 Imm(0) -> x1 + v15 Imm(0) -> x1 + v16 BinopI { op=add, lhs=v13, rhs_imm=0 } -> x0 + v17 Imm(1) -> x1 + v18 Imm(4294967296) -> x1 + v19 Imm(1) -> x1 + v20 Imm(10) -> x1 + v21 Imm(42949672960) -> x1 + v22 Imm(10) -> x1 + v23 Store { addr=v16, disp=0, value=v22, kind=I32 } -> - + v24 Imm(0) -> x0 + v25 Imm(1) -> x0 + v26 Imm(0) -> x0 + v27 Imm(1) -> x0 + v28 Imm(1) -> x0 + v29 LocalAddr(-4) -> x0 + v30 Imm(1) -> x1 + v31 Imm(4) -> x1 + v32 BinopI { op=add, lhs=v29, rhs_imm=4 } -> x1 + v33 Imm(2) -> x1 + v34 Imm(8589934592) -> x1 + v35 Imm(2) -> x1 + v36 Store { addr=v29, disp=4, value=v35, kind=I32 } -> - + v37 LocalAddr(-8) -> x0 + v38 Imm(1) -> x1 + v39 Imm(4) -> x1 + v40 BinopI { op=add, lhs=v37, rhs_imm=4 } -> x1 + v41 Imm(2) -> x1 + v42 Imm(8589934592) -> x1 + v43 Imm(2) -> x1 + v44 Imm(20) -> x1 + v45 Imm(85899345920) -> x1 + v46 Imm(20) -> x1 + v47 Store { addr=v37, disp=4, value=v46, kind=I32 } -> - + v48 Imm(1) -> x0 + v49 Imm(2) -> x0 + v50 Imm(0) -> x0 + v51 Imm(2) -> x0 + v52 Imm(1) -> x0 + v53 LocalAddr(-4) -> x0 + v54 Imm(2) -> x1 + v55 Imm(8) -> x1 + v56 BinopI { op=add, lhs=v53, rhs_imm=8 } -> x1 + v57 Imm(3) -> x1 + v58 Imm(12884901888) -> x1 + v59 Imm(3) -> x1 + v60 Store { addr=v53, disp=8, value=v59, kind=I32 } -> - + v61 LocalAddr(-8) -> x0 + v62 Imm(2) -> x1 + v63 Imm(8) -> x1 + v64 BinopI { op=add, lhs=v61, rhs_imm=8 } -> x1 + v65 Imm(3) -> x1 + v66 Imm(12884901888) -> x1 + v67 Imm(3) -> x1 + v68 Imm(30) -> x1 + v69 Imm(128849018880) -> x1 + v70 Imm(30) -> x1 + v71 Store { addr=v61, disp=8, value=v70, kind=I32 } -> - + v72 Imm(2) -> x0 + v73 Imm(3) -> x0 + v74 Imm(0) -> x0 + v75 Imm(3) -> x0 + v76 Imm(1) -> x0 + v77 LocalAddr(-4) -> x0 + v78 Imm(3) -> x1 + v79 Imm(12) -> x1 + v80 BinopI { op=add, lhs=v77, rhs_imm=12 } -> x1 + v81 Imm(4) -> x1 + v82 Imm(17179869184) -> x1 + v83 Imm(4) -> x1 + v84 Store { addr=v77, disp=12, value=v83, kind=I32 } -> - + v85 LocalAddr(-8) -> x0 + v86 Imm(3) -> x1 + v87 Imm(12) -> x1 + v88 BinopI { op=add, lhs=v85, rhs_imm=12 } -> x1 + v89 Imm(4) -> x1 + v90 Imm(17179869184) -> x1 + v91 Imm(4) -> x1 + v92 Imm(40) -> x1 + v93 Imm(171798691840) -> x1 + v94 Imm(40) -> x1 + v95 Store { addr=v85, disp=12, value=v94, kind=I32 } -> - + v96 Imm(3) -> x0 + v97 Imm(4) -> x0 + v98 Imm(0) -> x0 + v99 Imm(4) -> x0 + v100 Imm(1) -> x0 + v101 LocalAddr(-4) -> x0 + v102 Imm(4) -> x1 + v103 Imm(16) -> x1 + v104 BinopI { op=add, lhs=v101, rhs_imm=16 } -> x1 + v105 Imm(5) -> x1 + v106 Imm(21474836480) -> x1 + v107 Imm(5) -> x1 + v108 Store { addr=v101, disp=16, value=v107, kind=I32 } -> - + v109 LocalAddr(-8) -> x0 + v110 Imm(4) -> x1 + v111 Imm(16) -> x1 + v112 BinopI { op=add, lhs=v109, rhs_imm=16 } -> x1 + v113 Imm(5) -> x1 + v114 Imm(21474836480) -> x1 + v115 Imm(5) -> x1 + v116 Imm(50) -> x1 + v117 Imm(214748364800) -> x1 + v118 Imm(50) -> x1 + v119 Store { addr=v109, disp=16, value=v118, kind=I32 } -> - + v120 Imm(4) -> x0 + v121 Imm(5) -> x0 + v122 Imm(0) -> x0 + v123 Imm(5) -> x0 + v124 Imm(1) -> x0 + v125 LocalAddr(-4) -> x0 + v126 Imm(5) -> x1 + v127 Imm(20) -> x1 + v128 BinopI { op=add, lhs=v125, rhs_imm=20 } -> x1 + v129 Imm(6) -> x1 + v130 Imm(25769803776) -> x1 + v131 Imm(6) -> x1 + v132 Store { addr=v125, disp=20, value=v131, kind=I32 } -> - + v133 LocalAddr(-8) -> x0 + v134 Imm(5) -> x1 + v135 Imm(20) -> x1 + v136 BinopI { op=add, lhs=v133, rhs_imm=20 } -> x1 + v137 Imm(6) -> x1 + v138 Imm(25769803776) -> x1 + v139 Imm(6) -> x1 + v140 Imm(60) -> x1 + v141 Imm(257698037760) -> x1 + v142 Imm(60) -> x1 + v143 Store { addr=v133, disp=20, value=v142, kind=I32 } -> - + v144 Imm(5) -> x0 + v145 Imm(6) -> x0 + v146 Imm(0) -> x0 + v147 Imm(6) -> x0 + v148 Imm(1) -> x0 + v149 LocalAddr(-4) -> x0 + v150 Imm(6) -> x1 + v151 Imm(24) -> x1 + v152 BinopI { op=add, lhs=v149, rhs_imm=24 } -> x1 + v153 Imm(7) -> x1 + v154 Imm(30064771072) -> x1 + v155 Imm(7) -> x1 + v156 Store { addr=v149, disp=24, value=v155, kind=I32 } -> - + v157 LocalAddr(-8) -> x0 + v158 Imm(6) -> x1 + v159 Imm(24) -> x1 + v160 BinopI { op=add, lhs=v157, rhs_imm=24 } -> x1 + v161 Imm(7) -> x1 + v162 Imm(30064771072) -> x1 + v163 Imm(7) -> x1 + v164 Imm(70) -> x1 + v165 Imm(300647710720) -> x1 + v166 Imm(70) -> x1 + v167 Store { addr=v157, disp=24, value=v166, kind=I32 } -> - + v168 Imm(6) -> x0 + v169 Imm(7) -> x0 + v170 Imm(0) -> x0 + v171 Imm(7) -> x0 + v172 Imm(1) -> x0 + v173 LocalAddr(-4) -> x0 + v174 Imm(7) -> x1 + v175 Imm(28) -> x1 + v176 BinopI { op=add, lhs=v173, rhs_imm=28 } -> x1 + v177 Imm(8) -> x1 + v178 Imm(34359738368) -> x1 + v179 Imm(8) -> x1 + v180 Store { addr=v173, disp=28, value=v179, kind=I32 } -> - + v181 LocalAddr(-8) -> x0 + v182 Imm(7) -> x1 + v183 Imm(28) -> x1 + v184 BinopI { op=add, lhs=v181, rhs_imm=28 } -> x1 + v185 Imm(8) -> x1 + v186 Imm(34359738368) -> x1 + v187 Imm(8) -> x1 + v188 Imm(80) -> x1 + v189 Imm(343597383680) -> x1 + v190 Imm(80) -> x1 + v191 Store { addr=v181, disp=28, value=v190, kind=I32 } -> - + v192 Imm(7) -> x0 + v193 Imm(8) -> x0 + v194 Imm(0) -> x0 + v195 Imm(8) -> x0 + v196 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v196) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v197 LocalAddr(-4) -> x7 + v198 LocalAddr(-8) -> x6 + v199 Imm(8) -> x2 + v200 Imm(3) -> x1 + v201 Call { target_pc=0, args=[v197, v198, v199, v200], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v202 BinopI { op=eq, lhs=v201, rhs_imm=2940 } -> x0 + terminator Bz { cond=v202, target=b5, fall=b3 } (exit_acc=v202) block 3 start_pc=0 - v9 LocalAddr(-4) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=2 } -> x6 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 - v13 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x6 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 - v15 Extend { value=v13, kind=I32 } -> x7 - v16 StoreIndexed { base=v9, index=v10, scale=4, value=v13, kind=I32 } -> - - v17 LocalAddr(-8) -> x0 - v18 Extend { value=v3, kind=I32 } -> x2 - v19 BinopI { op=shl, lhs=v18, rhs_imm=2 } -> x6 - v20 Binop { op=add, lhs=v17, rhs=v19 } -> x6 - v21 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x6 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x7 - v23 Extend { value=v21, kind=I32 } -> x7 - v24 BinopI { op=mul, lhs=v21, rhs_imm=10 } -> x6 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x7 - v26 Extend { value=v24, kind=I32 } -> x7 - v27 StoreIndexed { base=v17, index=v18, scale=4, value=v24, kind=I32 } -> - - terminator Jmp(b2) (exit_acc=v27) + v203 Imm(0) -> x1 + v204 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v203) block 4 start_pc=0 - v28 LocalAddr(-4) -> x7 - v29 LocalAddr(-8) -> x6 - v30 Imm(8) -> x2 - v31 Imm(3) -> x1 - v32 Call { target_pc=0, args=[v28, v29, v30, v31], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v33 BinopI { op=eq, lhs=v32, rhs_imm=2940 } -> x0 - terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + v207 Phi { incoming=[b3:v203, b5:v205], kind=I64 } -> x1 + v208 LoadLocal { off=-14, kind=I64 } -> x0 + terminator Return(v207) (exit_acc=v207) block 5 start_pc=0 - v34 Imm(0) -> x1 - v35 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v34) - block 6 start_pc=0 - v36 Imm(1) -> x1 - v37 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v36) - block 7 start_pc=0 - v38 Phi { incoming=[b5:v34, b6:v36], kind=I64 } -> x1 - v39 LoadLocal { off=-14, kind=I64 } -> x0 - terminator Return(v38) (exit_acc=v38) + v205 Imm(1) -> x1 + v206 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v205) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indexed_swap_shared_addr.ssa b/tests/snapshots/ssa/indexed_swap_shared_addr.ssa index 4405ec1ab..70d3957fc 100644 --- a/tests/snapshots/ssa/indexed_swap_shared_addr.ssa +++ b/tests/snapshots/ssa/indexed_swap_shared_addr.ssa @@ -35,115 +35,164 @@ fn ent_pc=1 n_params=0 variadic=false locals=13 spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=5 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-5) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(1) -> x1 + v10 Imm(4294967296) -> x1 + v11 Imm(1) -> x1 + v12 Store { addr=v8, disp=0, value=v11, kind=I64 } -> - + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(0) -> x0 + v16 Imm(1) -> x0 + v17 Imm(1) -> x0 + v18 LocalAddr(-5) -> x0 + v19 Imm(1) -> x1 + v20 Imm(8) -> x1 + v21 BinopI { op=add, lhs=v18, rhs_imm=8 } -> x1 + v22 Imm(2) -> x1 + v23 Imm(8589934592) -> x1 + v24 Imm(2) -> x1 + v25 Store { addr=v18, disp=8, value=v24, kind=I64 } -> - + v26 Imm(1) -> x0 + v27 Imm(2) -> x0 + v28 Imm(0) -> x0 + v29 Imm(2) -> x0 + v30 Imm(1) -> x0 + v31 LocalAddr(-5) -> x0 + v32 Imm(2) -> x1 + v33 Imm(16) -> x1 + v34 BinopI { op=add, lhs=v31, rhs_imm=16 } -> x1 + v35 Imm(3) -> x1 + v36 Imm(12884901888) -> x1 + v37 Imm(3) -> x1 + v38 Store { addr=v31, disp=16, value=v37, kind=I64 } -> - + v39 Imm(2) -> x0 + v40 Imm(3) -> x0 + v41 Imm(0) -> x0 + v42 Imm(3) -> x0 + v43 Imm(1) -> x0 + v44 LocalAddr(-5) -> x0 + v45 Imm(3) -> x1 + v46 Imm(24) -> x1 + v47 BinopI { op=add, lhs=v44, rhs_imm=24 } -> x1 + v48 Imm(4) -> x1 + v49 Imm(17179869184) -> x1 + v50 Imm(4) -> x1 + v51 Store { addr=v44, disp=24, value=v50, kind=I64 } -> - + v52 Imm(3) -> x0 + v53 Imm(4) -> x0 + v54 Imm(0) -> x0 + v55 Imm(4) -> x0 + v56 Imm(1) -> x0 + v57 LocalAddr(-5) -> x0 + v58 Imm(4) -> x1 + v59 Imm(32) -> x1 + v60 BinopI { op=add, lhs=v57, rhs_imm=32 } -> x1 + v61 Imm(5) -> x1 + v62 Imm(21474836480) -> x1 + v63 Imm(5) -> x1 + v64 Store { addr=v57, disp=32, value=v63, kind=I64 } -> - + v65 Imm(4) -> x0 + v66 Imm(5) -> x0 + v67 Imm(0) -> x0 + v68 Imm(5) -> x0 + v69 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v69) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v70 LocalAddr(-5) -> x7 + v71 Imm(0) -> x3 + v72 Imm(4) -> x2 + v73 Call { target_pc=0, args=[v70, v71, v72], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v74 LocalAddr(-5) -> x0 + v75 Imm(8) -> x1 + v76 BinopI { op=add, lhs=v74, rhs_imm=8 } -> x7 + v77 Imm(2) -> x2 + v78 Call { target_pc=0, args=[v76, v71, v77], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v79 LocalAddr(-5) -> x0 + v80 Load { addr=v79, disp=0, kind=I64 } -> x0 + v81 BinopI { op=ne, lhs=v80, rhs_imm=5 } -> x0 + v82 Imm(1) -> x2 + v83 Imm(0) -> x1 + terminator Bnz { cond=v81, target=b16, fall=b3 } (exit_acc=v81) block 3 start_pc=0 - v9 LocalAddr(-5) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=3 } -> x6 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 - v13 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x6 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 - v15 Extend { value=v13, kind=I32 } -> x6 - v16 StoreIndexed { base=v9, index=v10, scale=8, value=v15, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v16) + v84 LocalAddr(-5) -> x0 + v85 Imm(8) -> x1 + v86 BinopI { op=add, lhs=v84, rhs_imm=8 } -> x1 + v87 Load { addr=v84, disp=8, kind=I64 } -> x0 + v88 BinopI { op=ne, lhs=v87, rhs_imm=4 } -> x0 + v89 BinopI { op=ne, lhs=v88, rhs_imm=0 } -> x2 + v90 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v89) block 4 start_pc=0 - v17 LocalAddr(-5) -> x7 - v18 Imm(0) -> x3 - v19 Imm(4) -> x2 - v20 Call { target_pc=0, args=[v17, v18, v19], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 - v21 LocalAddr(-5) -> x0 - v22 Imm(8) -> x1 - v23 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x7 - v24 Imm(2) -> x2 - v25 Call { target_pc=0, args=[v23, v18, v24], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 - v26 LocalAddr(-5) -> x0 - v27 Load { addr=v26, disp=0, kind=I64 } -> x0 - v28 BinopI { op=ne, lhs=v27, rhs_imm=5 } -> x0 - v29 Imm(1) -> x2 - v30 Imm(0) -> x1 - terminator Bnz { cond=v28, target=b15, fall=b5 } (exit_acc=v28) + v91 Phi { incoming=[b16:v82, b3:v89], kind=I64 } -> x2 + v92 LoadLocal { off=-13, kind=I64 } -> x0 + v93 Imm(1) -> x1 + v94 Imm(0) -> x0 + terminator Bnz { cond=v91, target=b15, fall=b5 } (exit_acc=v91) block 5 start_pc=0 - v31 LocalAddr(-5) -> x0 - v32 Imm(8) -> x1 - v33 BinopI { op=add, lhs=v31, rhs_imm=8 } -> x1 - v34 Load { addr=v31, disp=8, kind=I64 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=4 } -> x0 - v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x2 - v37 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v36) + v95 LocalAddr(-5) -> x0 + v96 Imm(16) -> x1 + v97 BinopI { op=add, lhs=v95, rhs_imm=16 } -> x1 + v98 Load { addr=v95, disp=16, kind=I64 } -> x0 + v99 BinopI { op=ne, lhs=v98, rhs_imm=3 } -> x0 + v100 BinopI { op=ne, lhs=v99, rhs_imm=0 } -> x1 + v101 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v100) block 6 start_pc=0 - v38 Phi { incoming=[b15:v29, b5:v36], kind=I64 } -> x2 - v39 LoadLocal { off=-13, kind=I64 } -> x0 - v40 Imm(1) -> x1 - v41 Imm(0) -> x0 - terminator Bnz { cond=v38, target=b16, fall=b7 } (exit_acc=v38) + v102 Phi { incoming=[b15:v93, b5:v100], kind=I64 } -> x1 + v103 LoadLocal { off=-12, kind=I64 } -> x0 + v104 Imm(1) -> x2 + v105 Imm(0) -> x0 + terminator Bnz { cond=v102, target=b14, fall=b7 } (exit_acc=v102) block 7 start_pc=0 - v42 LocalAddr(-5) -> x0 - v43 Imm(16) -> x1 - v44 BinopI { op=add, lhs=v42, rhs_imm=16 } -> x1 - v45 Load { addr=v42, disp=16, kind=I64 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=3 } -> x0 - v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x1 - v48 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v47) + v106 LocalAddr(-5) -> x0 + v107 Imm(24) -> x1 + v108 BinopI { op=add, lhs=v106, rhs_imm=24 } -> x1 + v109 Load { addr=v106, disp=24, kind=I64 } -> x0 + v110 BinopI { op=ne, lhs=v109, rhs_imm=2 } -> x0 + v111 BinopI { op=ne, lhs=v110, rhs_imm=0 } -> x2 + v112 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v111) block 8 start_pc=0 - v49 Phi { incoming=[b16:v40, b7:v47], kind=I64 } -> x1 - v50 LoadLocal { off=-12, kind=I64 } -> x0 - v51 Imm(1) -> x2 - v52 Imm(0) -> x0 - terminator Bnz { cond=v49, target=b17, fall=b9 } (exit_acc=v49) + v113 Phi { incoming=[b14:v104, b7:v111], kind=I64 } -> x2 + v114 LoadLocal { off=-11, kind=I64 } -> x0 + v115 Imm(0) -> x0 + terminator Bnz { cond=v113, target=b13, fall=b9 } (exit_acc=v113) block 9 start_pc=0 - v53 LocalAddr(-5) -> x0 - v54 Imm(24) -> x1 - v55 BinopI { op=add, lhs=v53, rhs_imm=24 } -> x1 - v56 Load { addr=v53, disp=24, kind=I64 } -> x0 - v57 BinopI { op=ne, lhs=v56, rhs_imm=2 } -> x0 - v58 BinopI { op=ne, lhs=v57, rhs_imm=0 } -> x2 - v59 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v58) + v116 LocalAddr(-5) -> x0 + v117 Imm(32) -> x1 + v118 BinopI { op=add, lhs=v116, rhs_imm=32 } -> x1 + v119 Load { addr=v116, disp=32, kind=I64 } -> x0 + v120 BinopI { op=ne, lhs=v119, rhs_imm=1 } -> x2 + v121 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v120) block 10 start_pc=0 - v60 Phi { incoming=[b17:v51, b9:v58], kind=I64 } -> x2 - v61 LoadLocal { off=-11, kind=I64 } -> x0 - v62 Imm(0) -> x0 - terminator Bnz { cond=v60, target=b18, fall=b11 } (exit_acc=v60) + v122 Phi { incoming=[b13:v113, b9:v120], kind=I64 } -> x2 + v123 LoadLocal { off=-10, kind=I64 } -> x0 + terminator Bz { cond=v122, target=b12, fall=b11 } (exit_acc=v122) block 11 start_pc=0 - v63 LocalAddr(-5) -> x0 - v64 Imm(32) -> x1 - v65 BinopI { op=add, lhs=v63, rhs_imm=32 } -> x1 - v66 Load { addr=v63, disp=32, kind=I64 } -> x0 - v67 BinopI { op=ne, lhs=v66, rhs_imm=1 } -> x2 - v68 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v67) + v124 Imm(1) -> x0 + terminator Return(v124) (exit_acc=v124) block 12 start_pc=0 - v69 Phi { incoming=[b18:v60, b11:v67], kind=I64 } -> x2 - v70 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v69, target=b14, fall=b13 } (exit_acc=v69) + v125 Imm(0) -> x0 + terminator Return(v125) (exit_acc=v125) block 13 start_pc=0 - v71 Imm(1) -> x0 - terminator Return(v71) (exit_acc=v71) + terminator Jmp(b10) block 14 start_pc=0 - v72 Imm(0) -> x0 - terminator Return(v72) (exit_acc=v72) + terminator Jmp(b8) block 15 start_pc=0 terminator Jmp(b6) block 16 start_pc=0 - terminator Jmp(b8) - block 17 start_pc=0 - terminator Jmp(b10) - block 18 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indirect_call_mixed_fp_int_args.ssa b/tests/snapshots/ssa/indirect_call_mixed_fp_int_args.ssa new file mode 100644 index 000000000..d2cb3962f --- /dev/null +++ b/tests/snapshots/ssa/indirect_call_mixed_fp_int_args.ssa @@ -0,0 +1,182 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=mixfn +fn ent_pc=0 n_params=6 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=F64) -> d0 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x6 + v6 Imm(0) -> x0 + v7 ParamRef(3, kind=F64) -> d1 + v8 Imm(0) -> x0 + v9 ParamRef(5, kind=I32) -> x2 + v10 Imm(0) -> x0 + v11 ParamRef(4, kind=F32) -> d2 [f32] + v12 Imm(0) -> x0 + v13 LoadLocal { off=2, kind=I32 } -> x0 + v14 LoadLocal { off=3, kind=F64 } -> d3 + v15 Imm(4621819117588971520) -> x0 + v16 Binop { op=fmul, lhs=v3, rhs=v15 } -> d0 + v17 FpCast { kind=FpToInt, value=v16 } -> x0 + v18 Binop { op=add, lhs=v1, rhs=v17 } -> x0 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 + v20 Extend { value=v18, kind=I32 } -> x1 + v21 LoadLocal { off=4, kind=I32 } -> x1 + v22 Binop { op=add, lhs=v18, rhs=v5 } -> x0 + v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x1 + v24 Extend { value=v22, kind=I32 } -> x1 + v25 LoadLocal { off=5, kind=F64 } -> d0 + v26 Imm(4636737291354636288) -> x1 + v27 Binop { op=fmul, lhs=v7, rhs=v26 } -> d0 + v28 FpCast { kind=FpToInt, value=v27 } -> x1 + v29 Binop { op=add, lhs=v22, rhs=v28 } -> x0 + v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x1 + v31 Extend { value=v29, kind=I32 } -> x1 + v32 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v33 Imm(1073741824) -> x1 [f32] + v34 Binop { op=fmul, lhs=v11, rhs=v33 } -> d0 [f32] + v35 FpCast { kind=F32ToF64, value=v34 } -> d0 + v36 FpCast { kind=FpToInt, value=v35 } -> x1 + v37 Binop { op=add, lhs=v29, rhs=v36 } -> x0 + v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x1 + v39 Extend { value=v37, kind=I32 } -> x1 + v40 LoadLocal { off=7, kind=I32 } -> x1 + v41 Binop { op=add, lhs=v37, rhs=v9 } -> x0 + v42 BinopI { op=shl, lhs=v41, rhs_imm=32 } -> x1 + v43 Extend { value=v41, kind=I32 } -> x0 + terminator Return(v43) (exit_acc=v43) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=10 + spill_count=1 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmCode(ent_pc=0) -> x0 + v2 Imm(0) -> x1 + v3 ImmData(8) -> x1 + v4 Load { addr=v3, disp=0, kind=I32, volatile } -> x3 + v5 Imm(0) -> x1 + v6 ImmData(16) -> x1 + v7 Load { addr=v6, disp=0, kind=F64, volatile } -> [spill 0] + v8 Imm(0) -> x1 + v9 Extend { value=v4, kind=I32 } -> x1 + v10 LoadLocal { off=-3, kind=F64 } -> d0 + v11 BinopI { op=add, lhs=v4, rhs_imm=2 } -> x1 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x2 + v13 Extend { value=v11, kind=I32 } -> x6 + v14 Imm(4598175219545276416) -> x2 + v15 Imm(1069547520) -> x1 [f32] + v16 Imm(7) -> x8 + v17 LoadLocal { off=-1, kind=I64 } -> x7 + v18 CallIndirect { target=v1, args=[v4, v7, v13, v14, v15, v16], callee_variadic=false, fixed_args=6, fp_return=false, fp_arg_mask=0x1a } -> x0 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 + v20 Extend { value=v18, kind=I32 } -> x0 + v21 Imm(0) -> x1 + v22 LoadLocal { off=-4, kind=I32 } -> x1 + v23 BinopI { op=ne, lhs=v20, rhs_imm=64 } -> x1 + terminator Bz { cond=v23, target=b2, fall=b1 } (exit_acc=v23) + block 1 start_pc=0 + v24 Imm(1) -> x0 + terminator Return(v24) (exit_acc=v24) + block 2 start_pc=0 + v25 LoadLocal { off=-4, kind=I32 } -> x1 + v26 Extend { value=v4, kind=I32 } -> x1 + v27 LoadLocal { off=-3, kind=F64 } -> d0 + v28 BinopI { op=add, lhs=v4, rhs_imm=2 } -> x2 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x6 + v30 Extend { value=v28, kind=I32 } -> x6 + v31 Imm(4598175219545276416) -> x7 + v32 Imm(1069547520) -> x8 [f32] + v33 Imm(7) -> x9 + v34 Extend { value=v26, kind=I32 } -> x1 + v35 Imm(0) -> x1 + v36 Imm(0) -> x1 + v37 Extend { value=v30, kind=I32 } -> x1 + v38 Imm(0) -> x1 + v39 Imm(0) -> x1 + v40 Imm(7) -> x1 + v41 Imm(0) -> x1 + v42 Imm(0) -> x1 + v43 Imm(4621819117588971520) -> x1 + v44 Binop { op=fmul, lhs=v7, rhs=v43 } -> d0 + v45 FpCast { kind=FpToInt, value=v44 } -> x1 + v46 Binop { op=add, lhs=v4, rhs=v45 } -> x1 + v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x6 + v48 Extend { value=v46, kind=I32 } -> x6 + v49 Binop { op=add, lhs=v46, rhs=v28 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=32 } -> x2 + v51 Extend { value=v49, kind=I32 } -> x2 + v52 Imm(4636737291354636288) -> x2 + v53 Binop { op=fmul, lhs=v31, rhs=v52 } -> d0 + v54 FpCast { kind=FpToInt, value=v53 } -> x2 + v55 Binop { op=add, lhs=v49, rhs=v54 } -> x1 + v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x2 + v57 Extend { value=v55, kind=I32 } -> x2 + v58 Imm(1073741824) -> x2 [f32] + v59 Binop { op=fmul, lhs=v32, rhs=v58 } -> d0 [f32] + v60 FpCast { kind=F32ToF64, value=v59 } -> d0 + v61 FpCast { kind=FpToInt, value=v60 } -> x2 + v62 Binop { op=add, lhs=v55, rhs=v61 } -> x1 + v63 BinopI { op=shl, lhs=v62, rhs_imm=32 } -> x2 + v64 Extend { value=v62, kind=I32 } -> x2 + v65 BinopI { op=add, lhs=v62, rhs_imm=7 } -> x1 + v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x2 + v67 Extend { value=v65, kind=I32 } -> x1 + v68 Binop { op=ne, lhs=v20, rhs=v67 } -> x0 + terminator Bz { cond=v68, target=b4, fall=b3 } (exit_acc=v68) + block 3 start_pc=0 + v69 Imm(2) -> x0 + terminator Return(v69) (exit_acc=v69) + block 4 start_pc=0 + v70 Imm(0) -> x0 + terminator Return(v70) (exit_acc=v70) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/indirect_call_narrow_scalar_args.ssa b/tests/snapshots/ssa/indirect_call_narrow_scalar_args.ssa new file mode 100644 index 000000000..bb4860eeb --- /dev/null +++ b/tests/snapshots/ssa/indirect_call_narrow_scalar_args.ssa @@ -0,0 +1,137 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=take +fn ent_pc=0 n_params=3 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I8) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I16) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x2 + v6 Imm(0) -> x0 + v7 LoadLocal { off=2, kind=I8 } -> x0 + v8 BinopI { op=mul, lhs=v1, rhs_imm=100000 } -> x0 + v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x1 + v10 Extend { value=v8, kind=I32 } -> x1 + v11 LoadLocal { off=3, kind=I16 } -> x1 + v12 BinopI { op=mul, lhs=v3, rhs_imm=10 } -> x1 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x6 + v14 Extend { value=v12, kind=I32 } -> x6 + v15 Binop { op=add, lhs=v8, rhs=v12 } -> x0 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 + v17 Extend { value=v15, kind=I32 } -> x1 + v18 LoadLocal { off=4, kind=I32 } -> x1 + v19 Binop { op=add, lhs=v15, rhs=v5 } -> x0 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x1 + v21 Extend { value=v19, kind=I32 } -> x0 + terminator Return(v21) (exit_acc=v21) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=7 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmCode(ent_pc=0) -> x0 + v2 Imm(0) -> x1 + v3 ImmData(8) -> x1 + v4 Load { addr=v3, disp=0, kind=I32, volatile } -> x7 + v5 Imm(0) -> x1 + v6 Extend { value=v4, kind=I32 } -> x1 + v7 Extend { value=v6, kind=I8 } -> x2 + v8 Imm(0) -> x6 + v9 Extend { value=v6, kind=I16 } -> x6 + v10 Imm(0) -> x8 + v11 Extend { value=v6, kind=I32 } -> x1 + v12 Imm(0) -> x1 + v13 BinopI { op=mul, lhs=v7, rhs_imm=100000 } -> x1 + v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x2 + v15 Extend { value=v13, kind=I32 } -> x2 + v16 BinopI { op=mul, lhs=v9, rhs_imm=10 } -> x2 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x6 + v18 Extend { value=v16, kind=I32 } -> x6 + v19 Binop { op=add, lhs=v13, rhs=v16 } -> x1 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x2 + v21 Extend { value=v19, kind=I32 } -> x2 + v22 Binop { op=add, lhs=v19, rhs=v4 } -> x1 + v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x2 + v24 Extend { value=v22, kind=I32 } -> x3 + v25 Imm(0) -> x1 + v26 Extend { value=v4, kind=I32 } -> x1 + v27 LoadLocal { off=-1, kind=I64 } -> x1 + v28 CallIndirect { target=v1, args=[v4, v4, v4], callee_variadic=false, fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 + v30 Extend { value=v28, kind=I32 } -> x0 + v31 Imm(0) -> x1 + v32 Extend { value=v24, kind=I32 } -> x1 + v33 LoadLocal { off=-4, kind=I32 } -> x2 + v34 Binop { op=ne, lhs=v32, rhs=v30 } -> x1 + terminator Bz { cond=v34, target=b2, fall=b1 } (exit_acc=v34) + block 1 start_pc=0 + v35 Imm(1) -> x0 + terminator Return(v35) (exit_acc=v35) + block 2 start_pc=0 + v36 LoadLocal { off=-4, kind=I32 } -> x1 + v37 Imm(6900000) -> x1 + v38 Imm(29635274342400000) -> x1 + v39 Imm(90290) -> x1 + v40 Imm(387792597155840) -> x1 + v41 Imm(6990290) -> x1 + v42 Imm(30023066939555840) -> x1 + v43 Imm(7064855) -> x1 + v44 Imm(30343321175982080) -> x1 + v45 BinopI { op=ne, lhs=v30, rhs_imm=7064855 } -> x0 + terminator Bz { cond=v45, target=b4, fall=b3 } (exit_acc=v45) + block 3 start_pc=0 + v46 Imm(2) -> x0 + terminator Return(v46) (exit_acc=v46) + block 4 start_pc=0 + v47 Imm(0) -> x0 + terminator Return(v47) (exit_acc=v47) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/indirect_call_six_args_spilled_target.ssa b/tests/snapshots/ssa/indirect_call_six_args_spilled_target.ssa index e448d58ee..b91314eeb 100644 --- a/tests/snapshots/ssa/indirect_call_six_args_spilled_target.ssa +++ b/tests/snapshots/ssa/indirect_call_six_args_spilled_target.ssa @@ -94,19 +94,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=16 v19 Imm(0) -> x1 v20 LoadLocal { off=-10, kind=I64 } -> x1 v21 BinopI { op=eq, lhs=v18, rhs_imm=3085 } -> x0 - terminator Bz { cond=v21, target=b2, fall=b1 } (exit_acc=v21) + terminator Bz { cond=v21, target=b3, fall=b1 } (exit_acc=v21) block 1 start_pc=0 v22 Imm(0) -> x1 v23 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v22) + terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 - v24 Imm(1) -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v24) - block 3 start_pc=0 - v26 Phi { incoming=[b1:v22, b2:v24], kind=I64 } -> x1 + v26 Phi { incoming=[b1:v22, b3:v24], kind=I64 } -> x1 v27 LoadLocal { off=-16, kind=I64 } -> x0 terminator Return(v26) (exit_acc=v26) + block 3 start_pc=0 + v24 Imm(1) -> x1 + v25 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v24) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indirect_call_target_scratch_exhausted.ssa b/tests/snapshots/ssa/indirect_call_target_scratch_exhausted.ssa index 33163816c..e3168ba1f 100644 --- a/tests/snapshots/ssa/indirect_call_target_scratch_exhausted.ssa +++ b/tests/snapshots/ssa/indirect_call_target_scratch_exhausted.ssa @@ -178,101 +178,353 @@ fn ent_pc=2 n_params=0 variadic=false locals=20 v2 Imm(0) -> x1 v3 ImmCode(ent_pc=1) -> x3 v4 Imm(0) -> x1 - v5 Imm(0) -> x2 - v6 Imm(0) -> x1 + v5 Imm(0) -> x1 + v6 Imm(0) -> x2 terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v7 Phi { incoming=[b0:v5, b2:v11], kind=I64 } -> x2 - v8 LoadLocal { off=-3, kind=I64 } -> x1 - v9 BinopI { op=lt, lhs=v7, rhs_imm=16 } -> x1 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v7 LoadLocal { off=-3, kind=I64 } -> x2 + v8 Imm(1) -> x2 + v9 ImmData(24) -> x2 + v10 LoadLocal { off=-3, kind=I64 } -> x6 + v11 Imm(0) -> x6 + v12 BinopI { op=add, lhs=v9, rhs_imm=0 } -> x6 + v13 Store { addr=v12, disp=0, value=v5, kind=I64 } -> - + v14 LoadLocal { off=-3, kind=I64 } -> x1 + v15 Imm(0) -> x1 + v16 BinopI { op=add, lhs=v9, rhs_imm=0 } -> x1 + v17 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x2 + v18 Imm(2) -> x2 + v19 Imm(0) -> x2 + v20 Store { addr=v16, disp=8, value=v19, kind=I64 } -> - + v21 LoadLocal { off=-3, kind=I64 } -> x1 + v22 Imm(1) -> x1 + v23 Imm(0) -> x2 + v24 LoadLocal { off=-3, kind=I64 } -> x2 + v25 Imm(1) -> x2 + v26 ImmData(24) -> x2 + v27 LoadLocal { off=-3, kind=I64 } -> x6 + v28 Imm(16) -> x6 + v29 BinopI { op=add, lhs=v26, rhs_imm=16 } -> x6 + v30 Store { addr=v26, disp=16, value=v22, kind=I64 } -> - + v31 LoadLocal { off=-3, kind=I64 } -> x1 + v32 Imm(16) -> x1 + v33 BinopI { op=add, lhs=v26, rhs_imm=16 } -> x1 + v34 BinopI { op=add, lhs=v33, rhs_imm=8 } -> x2 + v35 Imm(2) -> x2 + v36 Imm(2) -> x2 + v37 Store { addr=v33, disp=8, value=v36, kind=I64 } -> - + v38 LoadLocal { off=-3, kind=I64 } -> x1 + v39 Imm(2) -> x1 + v40 Imm(0) -> x2 + v41 LoadLocal { off=-3, kind=I64 } -> x2 + v42 Imm(1) -> x2 + v43 ImmData(24) -> x2 + v44 LoadLocal { off=-3, kind=I64 } -> x6 + v45 Imm(32) -> x6 + v46 BinopI { op=add, lhs=v43, rhs_imm=32 } -> x6 + v47 Store { addr=v43, disp=32, value=v39, kind=I64 } -> - + v48 LoadLocal { off=-3, kind=I64 } -> x1 + v49 Imm(32) -> x1 + v50 BinopI { op=add, lhs=v43, rhs_imm=32 } -> x1 + v51 BinopI { op=add, lhs=v50, rhs_imm=8 } -> x2 + v52 Imm(2) -> x2 + v53 Imm(4) -> x2 + v54 Store { addr=v50, disp=8, value=v53, kind=I64 } -> - + v55 LoadLocal { off=-3, kind=I64 } -> x1 + v56 Imm(3) -> x1 + v57 Imm(0) -> x2 + v58 LoadLocal { off=-3, kind=I64 } -> x2 + v59 Imm(1) -> x2 + v60 ImmData(24) -> x2 + v61 LoadLocal { off=-3, kind=I64 } -> x6 + v62 Imm(48) -> x6 + v63 BinopI { op=add, lhs=v60, rhs_imm=48 } -> x6 + v64 Store { addr=v60, disp=48, value=v56, kind=I64 } -> - + v65 LoadLocal { off=-3, kind=I64 } -> x1 + v66 Imm(48) -> x1 + v67 BinopI { op=add, lhs=v60, rhs_imm=48 } -> x1 + v68 BinopI { op=add, lhs=v67, rhs_imm=8 } -> x2 + v69 Imm(2) -> x2 + v70 Imm(6) -> x2 + v71 Store { addr=v67, disp=8, value=v70, kind=I64 } -> - + v72 LoadLocal { off=-3, kind=I64 } -> x1 + v73 Imm(4) -> x1 + v74 Imm(0) -> x2 + v75 LoadLocal { off=-3, kind=I64 } -> x2 + v76 Imm(1) -> x2 + v77 ImmData(24) -> x2 + v78 LoadLocal { off=-3, kind=I64 } -> x6 + v79 Imm(64) -> x6 + v80 BinopI { op=add, lhs=v77, rhs_imm=64 } -> x6 + v81 Store { addr=v77, disp=64, value=v73, kind=I64 } -> - + v82 LoadLocal { off=-3, kind=I64 } -> x1 + v83 Imm(64) -> x1 + v84 BinopI { op=add, lhs=v77, rhs_imm=64 } -> x1 + v85 BinopI { op=add, lhs=v84, rhs_imm=8 } -> x2 + v86 Imm(2) -> x2 + v87 Imm(8) -> x2 + v88 Store { addr=v84, disp=8, value=v87, kind=I64 } -> - + v89 LoadLocal { off=-3, kind=I64 } -> x1 + v90 Imm(5) -> x1 + v91 Imm(0) -> x2 + v92 LoadLocal { off=-3, kind=I64 } -> x2 + v93 Imm(1) -> x2 + v94 ImmData(24) -> x2 + v95 LoadLocal { off=-3, kind=I64 } -> x6 + v96 Imm(80) -> x6 + v97 BinopI { op=add, lhs=v94, rhs_imm=80 } -> x6 + v98 Store { addr=v94, disp=80, value=v90, kind=I64 } -> - + v99 LoadLocal { off=-3, kind=I64 } -> x1 + v100 Imm(80) -> x1 + v101 BinopI { op=add, lhs=v94, rhs_imm=80 } -> x1 + v102 BinopI { op=add, lhs=v101, rhs_imm=8 } -> x2 + v103 Imm(2) -> x2 + v104 Imm(10) -> x2 + v105 Store { addr=v101, disp=8, value=v104, kind=I64 } -> - + v106 LoadLocal { off=-3, kind=I64 } -> x1 + v107 Imm(6) -> x1 + v108 Imm(0) -> x2 + v109 LoadLocal { off=-3, kind=I64 } -> x2 + v110 Imm(1) -> x2 + v111 ImmData(24) -> x2 + v112 LoadLocal { off=-3, kind=I64 } -> x6 + v113 Imm(96) -> x6 + v114 BinopI { op=add, lhs=v111, rhs_imm=96 } -> x6 + v115 Store { addr=v111, disp=96, value=v107, kind=I64 } -> - + v116 LoadLocal { off=-3, kind=I64 } -> x1 + v117 Imm(96) -> x1 + v118 BinopI { op=add, lhs=v111, rhs_imm=96 } -> x1 + v119 BinopI { op=add, lhs=v118, rhs_imm=8 } -> x2 + v120 Imm(2) -> x2 + v121 Imm(12) -> x2 + v122 Store { addr=v118, disp=8, value=v121, kind=I64 } -> - + v123 LoadLocal { off=-3, kind=I64 } -> x1 + v124 Imm(7) -> x1 + v125 Imm(0) -> x2 + v126 LoadLocal { off=-3, kind=I64 } -> x2 + v127 Imm(1) -> x2 + v128 ImmData(24) -> x2 + v129 LoadLocal { off=-3, kind=I64 } -> x6 + v130 Imm(112) -> x6 + v131 BinopI { op=add, lhs=v128, rhs_imm=112 } -> x6 + v132 Store { addr=v128, disp=112, value=v124, kind=I64 } -> - + v133 LoadLocal { off=-3, kind=I64 } -> x1 + v134 Imm(112) -> x1 + v135 BinopI { op=add, lhs=v128, rhs_imm=112 } -> x1 + v136 BinopI { op=add, lhs=v135, rhs_imm=8 } -> x2 + v137 Imm(2) -> x2 + v138 Imm(14) -> x2 + v139 Store { addr=v135, disp=8, value=v138, kind=I64 } -> - + v140 LoadLocal { off=-3, kind=I64 } -> x1 + v141 Imm(8) -> x1 + v142 Imm(0) -> x2 + v143 LoadLocal { off=-3, kind=I64 } -> x2 + v144 Imm(1) -> x2 + v145 ImmData(24) -> x2 + v146 LoadLocal { off=-3, kind=I64 } -> x6 + v147 Imm(128) -> x6 + v148 BinopI { op=add, lhs=v145, rhs_imm=128 } -> x6 + v149 Store { addr=v145, disp=128, value=v141, kind=I64 } -> - + v150 LoadLocal { off=-3, kind=I64 } -> x1 + v151 Imm(128) -> x1 + v152 BinopI { op=add, lhs=v145, rhs_imm=128 } -> x1 + v153 BinopI { op=add, lhs=v152, rhs_imm=8 } -> x2 + v154 Imm(2) -> x2 + v155 Imm(16) -> x2 + v156 Store { addr=v152, disp=8, value=v155, kind=I64 } -> - + v157 LoadLocal { off=-3, kind=I64 } -> x1 + v158 Imm(9) -> x1 + v159 Imm(0) -> x2 + v160 LoadLocal { off=-3, kind=I64 } -> x2 + v161 Imm(1) -> x2 + v162 ImmData(24) -> x2 + v163 LoadLocal { off=-3, kind=I64 } -> x6 + v164 Imm(144) -> x6 + v165 BinopI { op=add, lhs=v162, rhs_imm=144 } -> x6 + v166 Store { addr=v162, disp=144, value=v158, kind=I64 } -> - + v167 LoadLocal { off=-3, kind=I64 } -> x1 + v168 Imm(144) -> x1 + v169 BinopI { op=add, lhs=v162, rhs_imm=144 } -> x1 + v170 BinopI { op=add, lhs=v169, rhs_imm=8 } -> x2 + v171 Imm(2) -> x2 + v172 Imm(18) -> x2 + v173 Store { addr=v169, disp=8, value=v172, kind=I64 } -> - + v174 LoadLocal { off=-3, kind=I64 } -> x1 + v175 Imm(10) -> x1 + v176 Imm(0) -> x2 + v177 LoadLocal { off=-3, kind=I64 } -> x2 + v178 Imm(1) -> x2 + v179 ImmData(24) -> x2 + v180 LoadLocal { off=-3, kind=I64 } -> x6 + v181 Imm(160) -> x6 + v182 BinopI { op=add, lhs=v179, rhs_imm=160 } -> x6 + v183 Store { addr=v179, disp=160, value=v175, kind=I64 } -> - + v184 LoadLocal { off=-3, kind=I64 } -> x1 + v185 Imm(160) -> x1 + v186 BinopI { op=add, lhs=v179, rhs_imm=160 } -> x1 + v187 BinopI { op=add, lhs=v186, rhs_imm=8 } -> x2 + v188 Imm(2) -> x2 + v189 Imm(20) -> x2 + v190 Store { addr=v186, disp=8, value=v189, kind=I64 } -> - + v191 LoadLocal { off=-3, kind=I64 } -> x1 + v192 Imm(11) -> x1 + v193 Imm(0) -> x2 + v194 LoadLocal { off=-3, kind=I64 } -> x2 + v195 Imm(1) -> x2 + v196 ImmData(24) -> x2 + v197 LoadLocal { off=-3, kind=I64 } -> x6 + v198 Imm(176) -> x6 + v199 BinopI { op=add, lhs=v196, rhs_imm=176 } -> x6 + v200 Store { addr=v196, disp=176, value=v192, kind=I64 } -> - + v201 LoadLocal { off=-3, kind=I64 } -> x1 + v202 Imm(176) -> x1 + v203 BinopI { op=add, lhs=v196, rhs_imm=176 } -> x1 + v204 BinopI { op=add, lhs=v203, rhs_imm=8 } -> x2 + v205 Imm(2) -> x2 + v206 Imm(22) -> x2 + v207 Store { addr=v203, disp=8, value=v206, kind=I64 } -> - + v208 LoadLocal { off=-3, kind=I64 } -> x1 + v209 Imm(12) -> x1 + v210 Imm(0) -> x2 + v211 LoadLocal { off=-3, kind=I64 } -> x2 + v212 Imm(1) -> x2 + v213 ImmData(24) -> x2 + v214 LoadLocal { off=-3, kind=I64 } -> x6 + v215 Imm(192) -> x6 + v216 BinopI { op=add, lhs=v213, rhs_imm=192 } -> x6 + v217 Store { addr=v213, disp=192, value=v209, kind=I64 } -> - + v218 LoadLocal { off=-3, kind=I64 } -> x1 + v219 Imm(192) -> x1 + v220 BinopI { op=add, lhs=v213, rhs_imm=192 } -> x1 + v221 BinopI { op=add, lhs=v220, rhs_imm=8 } -> x2 + v222 Imm(2) -> x2 + v223 Imm(24) -> x2 + v224 Store { addr=v220, disp=8, value=v223, kind=I64 } -> - + v225 LoadLocal { off=-3, kind=I64 } -> x1 + v226 Imm(13) -> x1 + v227 Imm(0) -> x2 + v228 LoadLocal { off=-3, kind=I64 } -> x2 + v229 Imm(1) -> x2 + v230 ImmData(24) -> x2 + v231 LoadLocal { off=-3, kind=I64 } -> x6 + v232 Imm(208) -> x6 + v233 BinopI { op=add, lhs=v230, rhs_imm=208 } -> x6 + v234 Store { addr=v230, disp=208, value=v226, kind=I64 } -> - + v235 LoadLocal { off=-3, kind=I64 } -> x1 + v236 Imm(208) -> x1 + v237 BinopI { op=add, lhs=v230, rhs_imm=208 } -> x1 + v238 BinopI { op=add, lhs=v237, rhs_imm=8 } -> x2 + v239 Imm(2) -> x2 + v240 Imm(26) -> x2 + v241 Store { addr=v237, disp=8, value=v240, kind=I64 } -> - + v242 LoadLocal { off=-3, kind=I64 } -> x1 + v243 Imm(14) -> x1 + v244 Imm(0) -> x2 + v245 LoadLocal { off=-3, kind=I64 } -> x2 + v246 Imm(1) -> x2 + v247 ImmData(24) -> x2 + v248 LoadLocal { off=-3, kind=I64 } -> x6 + v249 Imm(224) -> x6 + v250 BinopI { op=add, lhs=v247, rhs_imm=224 } -> x6 + v251 Store { addr=v247, disp=224, value=v243, kind=I64 } -> - + v252 LoadLocal { off=-3, kind=I64 } -> x1 + v253 Imm(224) -> x1 + v254 BinopI { op=add, lhs=v247, rhs_imm=224 } -> x1 + v255 BinopI { op=add, lhs=v254, rhs_imm=8 } -> x2 + v256 Imm(2) -> x2 + v257 Imm(28) -> x2 + v258 Store { addr=v254, disp=8, value=v257, kind=I64 } -> - + v259 LoadLocal { off=-3, kind=I64 } -> x1 + v260 Imm(15) -> x1 + v261 Imm(0) -> x2 + v262 LoadLocal { off=-3, kind=I64 } -> x2 + v263 Imm(1) -> x2 + v264 ImmData(24) -> x2 + v265 LoadLocal { off=-3, kind=I64 } -> x6 + v266 Imm(240) -> x6 + v267 BinopI { op=add, lhs=v264, rhs_imm=240 } -> x6 + v268 Store { addr=v264, disp=240, value=v260, kind=I64 } -> - + v269 LoadLocal { off=-3, kind=I64 } -> x1 + v270 Imm(240) -> x1 + v271 BinopI { op=add, lhs=v264, rhs_imm=240 } -> x1 + v272 BinopI { op=add, lhs=v271, rhs_imm=8 } -> x2 + v273 Imm(2) -> x2 + v274 Imm(30) -> x2 + v275 Store { addr=v271, disp=8, value=v274, kind=I64 } -> - + v276 LoadLocal { off=-3, kind=I64 } -> x1 + v277 Imm(16) -> x1 + v278 Imm(0) -> x1 + v279 LoadLocal { off=-3, kind=I64 } -> x1 + v280 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v280) block 2 start_pc=0 - v10 LoadLocal { off=-3, kind=I64 } -> x1 - v11 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x2 - v12 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v11) + v281 Imm(1) -> x7 + v282 Imm(2) -> x6 + v283 Imm(3) -> x2 + v284 Imm(4) -> x1 + v285 Imm(5) -> x8 + v286 Imm(6) -> x9 + v287 Imm(7) -> x12 + v288 Imm(8) -> x13 + v289 Imm(9) -> x14 + v290 Imm(10) -> x15 + v291 Imm(11) -> [spill 0] + v292 Imm(12) -> [spill 1] + v293 Imm(13) -> [spill 2] + v294 Imm(14) -> [spill 3] + v295 Imm(15) -> [spill 4] + v296 Imm(16) -> [spill 5] + v297 Imm(17) -> [spill 6] + v298 LoadLocal { off=-1, kind=I64 } -> [spill 7] + v299 CallIndirect { target=v1, args=[v281, v282, v283, v284, v285, v286, v287, v288, v289, v290, v291, v292, v293, v294, v295, v296, v297], callee_variadic=false, fixed_args=17, fp_return=false, fp_arg_mask=0x0 } -> x0 + v300 BinopI { op=ne, lhs=v299, rhs_imm=153 } -> x0 + terminator Bz { cond=v300, target=b4, fall=b3 } (exit_acc=v300) block 3 start_pc=0 - v13 ImmData(24) -> x1 - v14 LoadLocal { off=-3, kind=I64 } -> x6 - v15 BinopI { op=shl, lhs=v7, rhs_imm=4 } -> x6 - v16 Binop { op=add, lhs=v13, rhs=v15 } -> x6 - v17 Store { addr=v16, disp=0, value=v7, kind=I64 } -> - - v18 LoadLocal { off=-3, kind=I64 } -> x6 - v19 BinopI { op=shl, lhs=v7, rhs_imm=4 } -> x6 - v20 Binop { op=add, lhs=v13, rhs=v19 } -> x1 - v21 BinopI { op=add, lhs=v20, rhs_imm=8 } -> x6 - v22 Imm(2) -> x6 - v23 BinopI { op=shl, lhs=v7, rhs_imm=1 } -> x6 - v24 Store { addr=v20, disp=8, value=v23, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v24) + v301 Imm(1) -> x0 + terminator Return(v301) (exit_acc=v301) block 4 start_pc=0 - v25 Imm(1) -> x7 - v26 Imm(2) -> x6 - v27 Imm(3) -> x2 - v28 Imm(4) -> x1 - v29 Imm(5) -> x8 - v30 Imm(6) -> x9 - v31 Imm(7) -> x12 - v32 Imm(8) -> x13 - v33 Imm(9) -> x14 - v34 Imm(10) -> x15 - v35 Imm(11) -> [spill 0] - v36 Imm(12) -> [spill 1] - v37 Imm(13) -> [spill 2] - v38 Imm(14) -> [spill 3] - v39 Imm(15) -> [spill 4] - v40 Imm(16) -> [spill 5] - v41 Imm(17) -> [spill 6] - v42 LoadLocal { off=-1, kind=I64 } -> [spill 7] - v43 CallIndirect { target=v1, args=[v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41], callee_variadic=false, fixed_args=17, fp_return=false, fp_arg_mask=0x0 } -> x0 - v44 BinopI { op=ne, lhs=v43, rhs_imm=153 } -> x0 - terminator Bz { cond=v44, target=b6, fall=b5 } (exit_acc=v44) + v302 ImmData(24) -> x7 + v303 Imm(0) -> x0 + v304 Imm(16) -> x0 + v305 BinopI { op=add, lhs=v302, rhs_imm=16 } -> x6 + v306 Imm(32) -> x0 + v307 BinopI { op=add, lhs=v302, rhs_imm=32 } -> x2 + v308 Imm(48) -> x0 + v309 BinopI { op=add, lhs=v302, rhs_imm=48 } -> x1 + v310 Imm(64) -> x0 + v311 BinopI { op=add, lhs=v302, rhs_imm=64 } -> x8 + v312 Imm(80) -> x0 + v313 BinopI { op=add, lhs=v302, rhs_imm=80 } -> x9 + v314 Imm(96) -> x0 + v315 BinopI { op=add, lhs=v302, rhs_imm=96 } -> x0 + v316 Imm(112) -> x12 + v317 BinopI { op=add, lhs=v302, rhs_imm=112 } -> x12 + v318 Imm(128) -> x13 + v319 BinopI { op=add, lhs=v302, rhs_imm=128 } -> x13 + v320 Imm(144) -> x14 + v321 BinopI { op=add, lhs=v302, rhs_imm=144 } -> x14 + v322 Imm(160) -> x15 + v323 BinopI { op=add, lhs=v302, rhs_imm=160 } -> x15 + v324 Imm(176) -> [spill 0] + v325 BinopI { op=add, lhs=v302, rhs_imm=176 } -> [spill 0] + v326 Imm(192) -> [spill 1] + v327 BinopI { op=add, lhs=v302, rhs_imm=192 } -> [spill 1] + v328 Imm(208) -> [spill 2] + v329 BinopI { op=add, lhs=v302, rhs_imm=208 } -> [spill 2] + v330 Imm(224) -> [spill 3] + v331 BinopI { op=add, lhs=v302, rhs_imm=224 } -> [spill 3] + v332 Imm(240) -> [spill 4] + v333 BinopI { op=add, lhs=v302, rhs_imm=240 } -> [spill 4] + v334 LoadLocal { off=-2, kind=I64 } -> [spill 5] + v335 CallIndirect { target=v3, args=[v302, v305, v307, v309, v311, v313, v315, v317, v319, v321, v323, v325, v327, v329, v331, v333], callee_variadic=false, fixed_args=16, fp_return=false, fp_arg_mask=0x0 } -> x0 + v336 BinopI { op=ne, lhs=v335, rhs_imm=360 } -> x0 + terminator Bz { cond=v336, target=b6, fall=b5 } (exit_acc=v336) block 5 start_pc=0 - v45 Imm(1) -> x0 - terminator Return(v45) (exit_acc=v45) + v337 Imm(2) -> x0 + terminator Return(v337) (exit_acc=v337) block 6 start_pc=0 - v46 ImmData(24) -> x7 - v47 Imm(0) -> x0 - v48 Imm(16) -> x0 - v49 BinopI { op=add, lhs=v46, rhs_imm=16 } -> x6 - v50 Imm(32) -> x0 - v51 BinopI { op=add, lhs=v46, rhs_imm=32 } -> x2 - v52 Imm(48) -> x0 - v53 BinopI { op=add, lhs=v46, rhs_imm=48 } -> x1 - v54 Imm(64) -> x0 - v55 BinopI { op=add, lhs=v46, rhs_imm=64 } -> x8 - v56 Imm(80) -> x0 - v57 BinopI { op=add, lhs=v46, rhs_imm=80 } -> x9 - v58 Imm(96) -> x0 - v59 BinopI { op=add, lhs=v46, rhs_imm=96 } -> x0 - v60 Imm(112) -> x12 - v61 BinopI { op=add, lhs=v46, rhs_imm=112 } -> x12 - v62 Imm(128) -> x13 - v63 BinopI { op=add, lhs=v46, rhs_imm=128 } -> x13 - v64 Imm(144) -> x14 - v65 BinopI { op=add, lhs=v46, rhs_imm=144 } -> x14 - v66 Imm(160) -> x15 - v67 BinopI { op=add, lhs=v46, rhs_imm=160 } -> x15 - v68 Imm(176) -> [spill 0] - v69 BinopI { op=add, lhs=v46, rhs_imm=176 } -> [spill 0] - v70 Imm(192) -> [spill 1] - v71 BinopI { op=add, lhs=v46, rhs_imm=192 } -> [spill 1] - v72 Imm(208) -> [spill 2] - v73 BinopI { op=add, lhs=v46, rhs_imm=208 } -> [spill 2] - v74 Imm(224) -> [spill 3] - v75 BinopI { op=add, lhs=v46, rhs_imm=224 } -> [spill 3] - v76 Imm(240) -> [spill 4] - v77 BinopI { op=add, lhs=v46, rhs_imm=240 } -> [spill 4] - v78 LoadLocal { off=-2, kind=I64 } -> [spill 5] - v79 CallIndirect { target=v3, args=[v46, v49, v51, v53, v55, v57, v59, v61, v63, v65, v67, v69, v71, v73, v75, v77], callee_variadic=false, fixed_args=16, fp_return=false, fp_arg_mask=0x0 } -> x0 - v80 BinopI { op=ne, lhs=v79, rhs_imm=360 } -> x0 - terminator Bz { cond=v80, target=b8, fall=b7 } (exit_acc=v80) - block 7 start_pc=0 - v81 Imm(2) -> x0 - terminator Return(v81) (exit_acc=v81) - block 8 start_pc=0 - v82 Imm(0) -> x0 - terminator Return(v82) (exit_acc=v82) + v338 Imm(0) -> x0 + terminator Return(v338) (exit_acc=v338) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indirect_call_ten_scalar_args.ssa b/tests/snapshots/ssa/indirect_call_ten_scalar_args.ssa new file mode 100644 index 000000000..bde0c43c7 --- /dev/null +++ b/tests/snapshots/ssa/indirect_call_ten_scalar_args.ssa @@ -0,0 +1,147 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=weight10 +fn ent_pc=0 n_params=10 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I64) -> x2 + v6 Imm(0) -> x0 + v7 ParamRef(3, kind=I64) -> x1 + v8 Imm(0) -> x0 + v9 ParamRef(4, kind=I64) -> x8 + v10 Imm(0) -> x0 + v11 ParamRef(5, kind=I64) -> x9 + v12 Imm(0) -> x0 + v13 LoadLocal { off=2, kind=I64 } -> x0 + v14 LoadLocal { off=3, kind=I64 } -> x0 + v15 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x0 + v16 Binop { op=add, lhs=v1, rhs=v15 } -> x0 + v17 LoadLocal { off=4, kind=I64 } -> x6 + v18 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x2 + v19 Binop { op=add, lhs=v16, rhs=v18 } -> x0 + v20 LoadLocal { off=5, kind=I64 } -> x2 + v21 BinopI { op=shl, lhs=v7, rhs_imm=2 } -> x1 + v22 Binop { op=add, lhs=v19, rhs=v21 } -> x0 + v23 LoadLocal { off=6, kind=I64 } -> x1 + v24 BinopI { op=mul, lhs=v9, rhs_imm=5 } -> x1 + v25 Binop { op=add, lhs=v22, rhs=v24 } -> x0 + v26 LoadLocal { off=7, kind=I64 } -> x1 + v27 BinopI { op=mul, lhs=v11, rhs_imm=6 } -> x1 + v28 Binop { op=add, lhs=v25, rhs=v27 } -> x0 + v29 LoadLocal { off=8, kind=I64 } -> x1 + v30 BinopI { op=mul, lhs=v29, rhs_imm=7 } -> x1 + v31 Binop { op=add, lhs=v28, rhs=v30 } -> x0 + v32 LoadLocal { off=9, kind=I64 } -> x1 + v33 BinopI { op=shl, lhs=v32, rhs_imm=3 } -> x1 + v34 Binop { op=add, lhs=v31, rhs=v33 } -> x0 + v35 LoadLocal { off=10, kind=I64 } -> x1 + v36 BinopI { op=mul, lhs=v35, rhs_imm=9 } -> x1 + v37 Binop { op=add, lhs=v34, rhs=v36 } -> x0 + v38 LoadLocal { off=11, kind=I64 } -> x1 + v39 BinopI { op=mul, lhs=v38, rhs_imm=10 } -> x1 + v40 Binop { op=add, lhs=v37, rhs=v39 } -> x0 + terminator Return(v40) (exit_acc=v40) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=14 + spill_count=0 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmCode(ent_pc=0) -> x0 + v2 Imm(0) -> x1 + v3 ImmData(8) -> x1 + v4 Load { addr=v3, disp=0, kind=I64, volatile } -> x3 + v5 Imm(0) -> x1 + v6 LoadLocal { off=-2, kind=I64 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x6 + v8 BinopI { op=add, lhs=v4, rhs_imm=2 } -> x2 + v9 BinopI { op=add, lhs=v4, rhs_imm=3 } -> x1 + v10 BinopI { op=add, lhs=v4, rhs_imm=4 } -> x8 + v11 BinopI { op=add, lhs=v4, rhs_imm=5 } -> x9 + v12 BinopI { op=add, lhs=v4, rhs_imm=6 } -> x7 + v13 BinopI { op=add, lhs=v4, rhs_imm=7 } -> x12 + v14 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x13 + v15 BinopI { op=add, lhs=v4, rhs_imm=9 } -> x14 + v16 LoadLocal { off=-1, kind=I64 } -> x15 + v17 CallIndirect { target=v1, args=[v4, v7, v8, v9, v10, v11, v12, v13, v14, v15], callee_variadic=false, fixed_args=10, fp_return=false, fp_arg_mask=0x0 } -> x12 + v18 Imm(0) -> x0 + v19 LoadLocal { off=-3, kind=I64 } -> x0 + v20 BinopI { op=ne, lhs=v17, rhs_imm=385 } -> x0 + terminator Bz { cond=v20, target=b2, fall=b1 } (exit_acc=v20) + block 1 start_pc=0 + v21 Imm(1) -> x0 + terminator Return(v21) (exit_acc=v21) + block 2 start_pc=0 + v22 LoadLocal { off=-2, kind=I64 } -> x0 + v23 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x6 + v24 BinopI { op=add, lhs=v4, rhs_imm=2 } -> x2 + v25 BinopI { op=add, lhs=v4, rhs_imm=3 } -> x1 + v26 BinopI { op=add, lhs=v4, rhs_imm=4 } -> x8 + v27 BinopI { op=add, lhs=v4, rhs_imm=5 } -> x9 + v28 BinopI { op=add, lhs=v4, rhs_imm=6 } -> x0 + v29 BinopI { op=add, lhs=v4, rhs_imm=7 } -> x7 + v30 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x13 + v31 BinopI { op=add, lhs=v4, rhs_imm=9 } -> x14 + v32 Call { target_pc=0, args=[v4, v23, v24, v25, v26, v27, v28, v29, v30, v31], fixed_args=10, fp_return=false, fp_arg_mask=0x0 } -> x0 + v33 Imm(0) -> x1 + v34 LoadLocal { off=-3, kind=I64 } -> x1 + v35 LoadLocal { off=-4, kind=I64 } -> x1 + v36 Binop { op=ne, lhs=v17, rhs=v32 } -> x0 + terminator Bz { cond=v36, target=b4, fall=b3 } (exit_acc=v36) + block 3 start_pc=0 + v37 Imm(2) -> x0 + terminator Return(v37) (exit_acc=v37) + block 4 start_pc=0 + v38 Imm(0) -> x0 + terminator Return(v38) (exit_acc=v38) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/indirect_call_variadic_fp_control.ssa b/tests/snapshots/ssa/indirect_call_variadic_fp_control.ssa new file mode 100644 index 000000000..262161841 --- /dev/null +++ b/tests/snapshots/ssa/indirect_call_variadic_fp_control.ssa @@ -0,0 +1,148 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=vsum +fn ent_pc=0 n_params=1 variadic=true locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-3) -> x0 + v2 LocalAddr(2) -> x1 + v3 Intrinsic { kind=4, args=[v1, v2] } -> x0 + v4 Imm(0) -> x1 + v5 StoreLocal { off=-4, value=v4, kind=F64 } -> - + v6 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v4) + block 1 start_pc=0 + v14 Extend { value=v7, kind=I32 } -> x2 + v15 Imm(2) -> x2 + v16 BinopI { op=shr, lhs=v8, rhs_imm=63 } -> x2 + v17 BinopI { op=shru, lhs=v16, rhs_imm=63 } -> x2 + v18 Binop { op=add, lhs=v8, rhs=v17 } -> x6 + v19 BinopI { op=and, lhs=v18, rhs_imm=1 } -> x6 + v20 Binop { op=sub, lhs=v19, rhs=v17 } -> x2 + v21 BinopI { op=eq, lhs=v20, rhs_imm=0 } -> x2 + terminator Bz { cond=v21, target=b3, fall=b2 } (exit_acc=v21) + block 2 start_pc=0 + v25 LoadLocal { off=-4, kind=F64 } -> d0 + v26 LocalAddr(-3) -> x2 + v27 Imm(4) -> x6 + v28 Intrinsic { kind=5, args=[v26, v27] } -> x2 + v29 Load { addr=v28, disp=0, kind=I32 } -> x2 + v30 FpCast { kind=IntToFp, value=v29 } -> d1 + v31 Binop { op=fadd, lhs=v25, rhs=v30 } -> d0 + v32 StoreLocal { off=-4, value=v31, kind=F64 } -> - + v33 LoadLocal { off=-4, kind=F64 } -> d0 + terminator Jmp(b4) (exit_acc=v33) + block 3 start_pc=0 + v34 LoadLocal { off=-4, kind=F64 } -> d0 + v35 LocalAddr(-3) -> x2 + v36 Imm(65544) -> x6 + v37 Intrinsic { kind=5, args=[v35, v36] } -> x2 + v38 Load { addr=v37, disp=0, kind=F64 } -> d1 + v39 Binop { op=fadd, lhs=v34, rhs=v38 } -> d0 + v40 StoreLocal { off=-4, value=v39, kind=F64 } -> - + v41 LoadLocal { off=-4, kind=F64 } -> d0 + terminator Jmp(b4) (exit_acc=v41) + block 4 start_pc=0 + v11 Extend { value=v7, kind=I32 } -> x1 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v13 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v12) + block 5 start_pc=0 + v7 Phi { incoming=[b0:v4, b4:v12], kind=I64 } -> x1 + v8 Extend { value=v7, kind=I32 } -> x0 + v9 LoadLocal { off=2, kind=I32 } -> x2 + v10 Binop { op=lt, lhs=v8, rhs=v9 } -> x2 + terminator Bnz { cond=v10, target=b1, fall=b6 } (exit_acc=v10) + block 6 start_pc=0 + v22 LocalAddr(-3) -> x0 + v23 Intrinsic { kind=6, args=[v22] } -> x0 + v24 LoadLocal { off=-4, kind=F64 } -> d0 + terminator Return(v24) (exit_acc=v24) + block 7 start_pc=0 + terminator Jmp(b4) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=7 + spill_count=1 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmCode(ent_pc=0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(4) -> x7 + v4 Imm(1) -> x6 + v5 Imm(4612811918334230528) -> x2 + v6 Imm(3) -> x1 + v7 Imm(4616471093031469056) -> x8 + v8 LoadLocal { off=-1, kind=I64 } -> x9 + v9 CallIndirect { target=v1, args=[v3, v4, v5, v6, v7], callee_variadic=true, fixed_args=1, fp_return=true, fp_arg_mask=0x14 } -> [spill 0] + v10 Imm(0) -> x0 + v11 LoadLocal { off=-2, kind=F64 } -> d0 + v12 Imm(4622241330054037504) -> x0 + v13 Binop { op=fne, lhs=v9, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) + block 1 start_pc=0 + v14 Imm(1) -> x0 + terminator Return(v14) (exit_acc=v14) + block 2 start_pc=0 + v15 LoadLocal { off=-2, kind=F64 } -> d0 + v16 Imm(4) -> x7 + v17 Imm(1) -> x6 + v18 Imm(4612811918334230528) -> x2 + v19 Imm(3) -> x1 + v20 Imm(4616471093031469056) -> x8 + v21 Call { target_pc=0, args=[v16, v17, v18, v19, v20], fixed_args=1, fp_return=true, fp_arg_mask=0x14 } -> d0 + v22 Binop { op=fne, lhs=v9, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) + block 3 start_pc=0 + v23 Imm(2) -> x0 + terminator Return(v23) (exit_acc=v23) + block 4 start_pc=0 + v24 Imm(0) -> x0 + terminator Return(v24) (exit_acc=v24) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/indirect_struct_return.ssa b/tests/snapshots/ssa/indirect_struct_return.ssa index 7008c0e50..26746a2de 100644 --- a/tests/snapshots/ssa/indirect_struct_return.ssa +++ b/tests/snapshots/ssa/indirect_struct_return.ssa @@ -37,18 +37,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v8 Mcpy { dst=v7, src=v6, size=8 } -> x0 v9 LocalAddr(-2) -> x0 v10 Load { addr=v9, disp=0, kind=I32 } -> x0 - v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x12 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x1 v12 Imm(0) -> x0 - terminator Bnz { cond=v11, target=b11, fall=b1 } (exit_acc=v11) + terminator Bnz { cond=v11, target=b12, fall=b1 } (exit_acc=v11) block 1 start_pc=0 v13 LocalAddr(-2) -> x0 v14 BinopI { op=add, lhs=v13, rhs_imm=4 } -> x1 v15 Load { addr=v13, disp=4, kind=I32 } -> x0 - v16 BinopI { op=ne, lhs=v15, rhs_imm=14 } -> x12 + v16 BinopI { op=ne, lhs=v15, rhs_imm=14 } -> x1 v17 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v18 Phi { incoming=[b11:v11, b1:v16], kind=I64 } -> x12 + v18 Phi { incoming=[b12:v11, b1:v16], kind=I64 } -> x1 v19 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 @@ -67,18 +67,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v30 Mcpy { dst=v29, src=v28, size=8 } -> x0 v31 LocalAddr(-4) -> x0 v32 Load { addr=v31, disp=0, kind=I32 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=10 } -> x12 + v33 BinopI { op=ne, lhs=v32, rhs_imm=10 } -> x1 v34 Imm(0) -> x0 - terminator Bnz { cond=v33, target=b12, fall=b5 } (exit_acc=v33) + terminator Bnz { cond=v33, target=b11, fall=b5 } (exit_acc=v33) block 5 start_pc=0 v35 LocalAddr(-4) -> x0 v36 BinopI { op=add, lhs=v35, rhs_imm=4 } -> x1 v37 Load { addr=v35, disp=4, kind=I32 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=20 } -> x12 + v38 BinopI { op=ne, lhs=v37, rhs_imm=20 } -> x1 v39 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v38) block 6 start_pc=0 - v40 Phi { incoming=[b12:v33, b5:v38], kind=I64 } -> x12 + v40 Phi { incoming=[b11:v33, b5:v38], kind=I64 } -> x1 v41 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v40, target=b8, fall=b7 } (exit_acc=v40) block 7 start_pc=0 @@ -110,9 +110,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v61 Imm(0) -> x0 terminator Return(v61) (exit_acc=v61) block 11 start_pc=0 - terminator Jmp(b2) - block 12 start_pc=0 terminator Jmp(b6) + block 12 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/indirect_struct_return_outptr.ssa b/tests/snapshots/ssa/indirect_struct_return_outptr.ssa index d6aaa5e26..5ab049aff 100644 --- a/tests/snapshots/ssa/indirect_struct_return_outptr.ssa +++ b/tests/snapshots/ssa/indirect_struct_return_outptr.ssa @@ -10,15 +10,15 @@ fn ent_pc=0 n_params=2 variadic=false locals=5 v4 LoadLocal { off=3, kind=I32 } -> x0 v5 LocalAddr(-5) -> x1 v6 Store { addr=v5, disp=0, value=v4, kind=I64 } -> - - v7 LoadLocal { off=3, kind=I32 } -> x0 - v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 - v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x1 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 LocalAddr(-5) -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=8 } -> x2 + v7 LoadLocal { off=3, kind=I32 } -> x1 + v8 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x2 + v10 Extend { value=v8, kind=I32 } -> x1 + v11 LocalAddr(-5) -> x2 + v12 BinopI { op=add, lhs=v11, rhs_imm=8 } -> x6 v13 Store { addr=v11, disp=8, value=v10, kind=I64 } -> - - v14 LoadLocal { off=3, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=2 } -> x0 + v14 LoadLocal { off=3, kind=I32 } -> x1 + v15 BinopI { op=add, lhs=v4, rhs_imm=2 } -> x0 v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 v17 Extend { value=v15, kind=I32 } -> x0 v18 LocalAddr(-5) -> x1 @@ -87,19 +87,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=31 v14 LocalAddr(-7) -> x0 v15 Load { addr=v14, disp=0, kind=I64 } -> x0 v16 BinopI { op=ne, lhs=v15, rhs_imm=10 } -> x0 - v17 Imm(1) -> x13 + v17 Imm(1) -> x2 v18 Imm(0) -> x1 - terminator Bnz { cond=v16, target=b15, fall=b1 } (exit_acc=v16) + terminator Bnz { cond=v16, target=b17, fall=b1 } (exit_acc=v16) block 1 start_pc=0 v19 LocalAddr(-7) -> x0 v20 BinopI { op=add, lhs=v19, rhs_imm=16 } -> x1 v21 Load { addr=v19, disp=16, kind=I64 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=12 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x13 + v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x2 v24 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v23) block 2 start_pc=0 - v25 Phi { incoming=[b15:v17, b1:v23], kind=I64 } -> x13 + v25 Phi { incoming=[b17:v17, b1:v23], kind=I64 } -> x2 v26 LoadLocal { off=-18, kind=I64 } -> x0 v27 Imm(0) -> x0 terminator Bnz { cond=v25, target=b16, fall=b3 } (exit_acc=v25) @@ -107,11 +107,11 @@ fn ent_pc=2 n_params=0 variadic=false locals=31 v28 LocalAddr(-7) -> x0 v29 BinopI { op=add, lhs=v28, rhs_imm=32 } -> x1 v30 Load { addr=v28, disp=32, kind=I64 } -> x0 - v31 BinopI { op=ne, lhs=v30, rhs_imm=14 } -> x13 + v31 BinopI { op=ne, lhs=v30, rhs_imm=14 } -> x2 v32 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v31) block 4 start_pc=0 - v33 Phi { incoming=[b16:v25, b3:v31], kind=I64 } -> x13 + v33 Phi { incoming=[b16:v25, b3:v31], kind=I64 } -> x2 v34 LoadLocal { off=-17, kind=I64 } -> x0 terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) block 5 start_pc=0 @@ -126,18 +126,18 @@ fn ent_pc=2 n_params=0 variadic=false locals=31 v41 Mcpy { dst=v40, src=v39, size=16 } -> x0 v42 LocalAddr(-9) -> x0 v43 Load { addr=v42, disp=0, kind=I64 } -> x0 - v44 BinopI { op=ne, lhs=v43, rhs_imm=7 } -> x13 + v44 BinopI { op=ne, lhs=v43, rhs_imm=7 } -> x1 v45 Imm(0) -> x0 - terminator Bnz { cond=v44, target=b17, fall=b7 } (exit_acc=v44) + terminator Bnz { cond=v44, target=b15, fall=b7 } (exit_acc=v44) block 7 start_pc=0 v46 LocalAddr(-9) -> x0 v47 BinopI { op=add, lhs=v46, rhs_imm=8 } -> x1 v48 Load { addr=v46, disp=8, kind=I64 } -> x0 - v49 BinopI { op=ne, lhs=v48, rhs_imm=14 } -> x13 + v49 BinopI { op=ne, lhs=v48, rhs_imm=14 } -> x1 v50 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v49) block 8 start_pc=0 - v51 Phi { incoming=[b17:v44, b7:v49], kind=I64 } -> x13 + v51 Phi { incoming=[b15:v44, b7:v49], kind=I64 } -> x1 v52 LoadLocal { off=-21, kind=I64 } -> x0 terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) block 9 start_pc=0 @@ -179,11 +179,11 @@ fn ent_pc=2 n_params=0 variadic=false locals=31 v78 Imm(0) -> x0 terminator Return(v78) (exit_acc=v78) block 15 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b8) block 16 start_pc=0 terminator Jmp(b4) block 17 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/init_brace_intermediate_cast.ssa b/tests/snapshots/ssa/init_brace_intermediate_cast.ssa new file mode 100644 index 000000000..15a9529b4 --- /dev/null +++ b/tests/snapshots/ssa/init_brace_intermediate_cast.ssa @@ -0,0 +1,330 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=11 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-4) -> x0 + v2 ImmData(128) -> x1 + v3 Mcpy { dst=v1, src=v2, size=32 } -> x0 + v4 LocalAddr(-6) -> x0 + v5 ImmData(160) -> x1 + v6 Mcpy { dst=v4, src=v5, size=16 } -> x0 + v7 LocalAddr(-7) -> x0 + v8 ImmData(176) -> x1 + v9 Mcpy { dst=v7, src=v8, size=8 } -> x0 + v10 LocalAddr(-10) -> x0 + v11 ImmData(184) -> x1 + v12 Mcpy { dst=v10, src=v11, size=24 } -> x0 + v13 Imm(2454267027) -> x0 + v14 Imm(-7905747457093402624) -> x0 + v15 Imm(-1840700269) -> x0 + v16 Imm(0) -> x0 + v17 ImmData(8) -> x0 + v18 Imm(0) -> x1 + v19 Load { addr=v17, disp=0, kind=I64 } -> x1 + v20 BinopI { op=ne, lhs=v19, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v20, target=b2, fall=b1 } (exit_acc=v20) + block 1 start_pc=0 + v21 Imm(1) -> x0 + terminator Return(v21) (exit_acc=v21) + block 2 start_pc=0 + v22 ImmData(8) -> x1 + v23 Imm(8) -> x1 + v24 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x1 + v25 Load { addr=v17, disp=8, kind=I64 } -> x1 + v26 BinopI { op=ne, lhs=v25, rhs_imm=4294967295 } -> x1 + terminator Bz { cond=v26, target=b4, fall=b3 } (exit_acc=v26) + block 3 start_pc=0 + v27 Imm(2) -> x0 + terminator Return(v27) (exit_acc=v27) + block 4 start_pc=0 + v28 ImmData(8) -> x1 + v29 Imm(16) -> x1 + v30 BinopI { op=add, lhs=v17, rhs_imm=16 } -> x1 + v31 Load { addr=v17, disp=16, kind=I64 } -> x1 + v32 BinopI { op=ne, lhs=v31, rhs_imm=-1 } -> x1 + terminator Bz { cond=v32, target=b6, fall=b5 } (exit_acc=v32) + block 5 start_pc=0 + v33 Imm(3) -> x0 + terminator Return(v33) (exit_acc=v33) + block 6 start_pc=0 + v34 ImmData(8) -> x1 + v35 Imm(24) -> x1 + v36 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x1 + v37 Load { addr=v17, disp=24, kind=I64 } -> x0 + v38 BinopI { op=ne, lhs=v37, rhs_imm=-1 } -> x0 + terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + block 7 start_pc=0 + v39 Imm(4) -> x0 + terminator Return(v39) (exit_acc=v39) + block 8 start_pc=0 + v40 ImmData(40) -> x0 + v41 Imm(0) -> x1 + v42 Load { addr=v40, disp=0, kind=I64 } -> x0 + v43 BinopI { op=ne, lhs=v42, rhs_imm=-1 } -> x0 + terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) + block 9 start_pc=0 + v44 Imm(5) -> x0 + terminator Return(v44) (exit_acc=v44) + block 10 start_pc=0 + v45 ImmData(40) -> x0 + v46 Imm(8) -> x1 + v47 BinopI { op=add, lhs=v45, rhs_imm=8 } -> x1 + v48 Load { addr=v45, disp=8, kind=I64 } -> x0 + v49 BinopI { op=ne, lhs=v48, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v49, target=b12, fall=b11 } (exit_acc=v49) + block 11 start_pc=0 + v50 Imm(6) -> x0 + terminator Return(v50) (exit_acc=v50) + block 12 start_pc=0 + v51 ImmData(56) -> x0 + v52 Imm(0) -> x1 + v53 Load { addr=v51, disp=0, kind=I32 } -> x0 + v54 BinopI { op=ne, lhs=v53, rhs_imm=-56 } -> x0 + terminator Bz { cond=v54, target=b14, fall=b13 } (exit_acc=v54) + block 13 start_pc=0 + v55 Imm(7) -> x0 + terminator Return(v55) (exit_acc=v55) + block 14 start_pc=0 + v56 ImmData(56) -> x0 + v57 Imm(4) -> x1 + v58 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x1 + v59 Load { addr=v56, disp=4, kind=I32 } -> x0 + v60 BinopI { op=ne, lhs=v59, rhs_imm=-32768 } -> x0 + terminator Bz { cond=v60, target=b16, fall=b15 } (exit_acc=v60) + block 15 start_pc=0 + v61 Imm(8) -> x0 + terminator Return(v61) (exit_acc=v61) + block 16 start_pc=0 + v62 ImmData(64) -> x0 + v63 Load { addr=v62, disp=0, kind=I64 } -> x0 + v64 BinopI { op=ne, lhs=v63, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v64, target=b18, fall=b17 } (exit_acc=v64) + block 17 start_pc=0 + v65 Imm(9) -> x0 + terminator Return(v65) (exit_acc=v65) + block 18 start_pc=0 + v66 ImmData(64) -> x0 + v67 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x1 + v68 Load { addr=v66, disp=8, kind=I64 } -> x0 + v69 BinopI { op=ne, lhs=v68, rhs_imm=-1 } -> x0 + terminator Bz { cond=v69, target=b20, fall=b19 } (exit_acc=v69) + block 19 start_pc=0 + v70 Imm(10) -> x0 + terminator Return(v70) (exit_acc=v70) + block 20 start_pc=0 + v71 ImmData(64) -> x0 + v72 BinopI { op=add, lhs=v71, rhs_imm=16 } -> x1 + v73 Load { addr=v71, disp=16, kind=I32 } -> x0 + v74 BinopI { op=ne, lhs=v73, rhs_imm=-56 } -> x0 + terminator Bz { cond=v74, target=b22, fall=b21 } (exit_acc=v74) + block 21 start_pc=0 + v75 Imm(11) -> x0 + terminator Return(v75) (exit_acc=v75) + block 22 start_pc=0 + v76 ImmData(88) -> x0 + v77 Load { addr=v76, disp=0, kind=I64 } -> x0 + v78 BinopI { op=ne, lhs=v77, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v78, target=b24, fall=b23 } (exit_acc=v78) + block 23 start_pc=0 + v79 Imm(12) -> x0 + terminator Return(v79) (exit_acc=v79) + block 24 start_pc=0 + v80 ImmData(96) -> x0 + v81 Imm(0) -> x1 + v82 Load { addr=v80, disp=0, kind=I64 } -> x0 + v83 BinopI { op=ne, lhs=v82, rhs_imm=0 } -> x0 + terminator Bz { cond=v83, target=b26, fall=b25 } (exit_acc=v83) + block 25 start_pc=0 + v84 Imm(13) -> x0 + terminator Return(v84) (exit_acc=v84) + block 26 start_pc=0 + v85 ImmData(96) -> x0 + v86 Imm(8) -> x1 + v87 BinopI { op=add, lhs=v85, rhs_imm=8 } -> x1 + v88 Load { addr=v85, disp=8, kind=I64 } -> x0 + v89 BinopI { op=ne, lhs=v88, rhs_imm=-1 } -> x0 + terminator Bz { cond=v89, target=b28, fall=b27 } (exit_acc=v89) + block 27 start_pc=0 + v90 Imm(14) -> x0 + terminator Return(v90) (exit_acc=v90) + block 28 start_pc=0 + v91 ImmData(112) -> x0 + v92 Imm(0) -> x1 + v93 Load { addr=v91, disp=0, kind=I32 } -> x0 + v94 BinopI { op=ne, lhs=v93, rhs_imm=2 } -> x0 + terminator Bz { cond=v94, target=b30, fall=b29 } (exit_acc=v94) + block 29 start_pc=0 + v95 Imm(15) -> x0 + terminator Return(v95) (exit_acc=v95) + block 30 start_pc=0 + v96 ImmData(120) -> x0 + v97 Imm(0) -> x1 + v98 Load { addr=v96, disp=0, kind=F64 } -> d0 + v99 Imm(4613937818241073152) -> x0 + v100 Binop { op=fne, lhs=v98, rhs=v99 } -> x0 + terminator Bz { cond=v100, target=b32, fall=b31 } (exit_acc=v100) + block 31 start_pc=0 + v101 Imm(16) -> x0 + terminator Return(v101) (exit_acc=v101) + block 32 start_pc=0 + v102 LocalAddr(-4) -> x0 + v103 Imm(0) -> x1 + v104 Load { addr=v102, disp=0, kind=I64 } -> x0 + v105 BinopI { op=ne, lhs=v104, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v105, target=b34, fall=b33 } (exit_acc=v105) + block 33 start_pc=0 + v106 Imm(17) -> x0 + terminator Return(v106) (exit_acc=v106) + block 34 start_pc=0 + v107 LocalAddr(-4) -> x0 + v108 Imm(8) -> x1 + v109 BinopI { op=add, lhs=v107, rhs_imm=8 } -> x1 + v110 Load { addr=v107, disp=8, kind=I64 } -> x0 + v111 BinopI { op=ne, lhs=v110, rhs_imm=4294967295 } -> x0 + terminator Bz { cond=v111, target=b36, fall=b35 } (exit_acc=v111) + block 35 start_pc=0 + v112 Imm(18) -> x0 + terminator Return(v112) (exit_acc=v112) + block 36 start_pc=0 + v113 LocalAddr(-4) -> x0 + v114 Imm(16) -> x1 + v115 BinopI { op=add, lhs=v113, rhs_imm=16 } -> x1 + v116 Load { addr=v113, disp=16, kind=I64 } -> x0 + v117 BinopI { op=ne, lhs=v116, rhs_imm=-1 } -> x0 + terminator Bz { cond=v117, target=b38, fall=b37 } (exit_acc=v117) + block 37 start_pc=0 + v118 Imm(19) -> x0 + terminator Return(v118) (exit_acc=v118) + block 38 start_pc=0 + v119 LocalAddr(-4) -> x0 + v120 Imm(24) -> x1 + v121 BinopI { op=add, lhs=v119, rhs_imm=24 } -> x1 + v122 Load { addr=v119, disp=24, kind=I64 } -> x0 + v123 BinopI { op=ne, lhs=v122, rhs_imm=-1 } -> x0 + terminator Bz { cond=v123, target=b40, fall=b39 } (exit_acc=v123) + block 39 start_pc=0 + v124 Imm(20) -> x0 + terminator Return(v124) (exit_acc=v124) + block 40 start_pc=0 + v125 LocalAddr(-6) -> x0 + v126 Imm(0) -> x1 + v127 Load { addr=v125, disp=0, kind=I64 } -> x0 + v128 BinopI { op=ne, lhs=v127, rhs_imm=-1 } -> x0 + terminator Bz { cond=v128, target=b42, fall=b41 } (exit_acc=v128) + block 41 start_pc=0 + v129 Imm(21) -> x0 + terminator Return(v129) (exit_acc=v129) + block 42 start_pc=0 + v130 LocalAddr(-6) -> x0 + v131 Imm(8) -> x1 + v132 BinopI { op=add, lhs=v130, rhs_imm=8 } -> x1 + v133 Load { addr=v130, disp=8, kind=I64 } -> x0 + v134 BinopI { op=ne, lhs=v133, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v134, target=b44, fall=b43 } (exit_acc=v134) + block 43 start_pc=0 + v135 Imm(22) -> x0 + terminator Return(v135) (exit_acc=v135) + block 44 start_pc=0 + v136 LocalAddr(-7) -> x0 + v137 Imm(0) -> x1 + v138 Load { addr=v136, disp=0, kind=I32 } -> x0 + v139 BinopI { op=ne, lhs=v138, rhs_imm=-56 } -> x0 + terminator Bz { cond=v139, target=b46, fall=b45 } (exit_acc=v139) + block 45 start_pc=0 + v140 Imm(23) -> x0 + terminator Return(v140) (exit_acc=v140) + block 46 start_pc=0 + v141 LocalAddr(-7) -> x0 + v142 Imm(4) -> x1 + v143 BinopI { op=add, lhs=v141, rhs_imm=4 } -> x1 + v144 Load { addr=v141, disp=4, kind=I32 } -> x0 + v145 BinopI { op=ne, lhs=v144, rhs_imm=-32768 } -> x0 + terminator Bz { cond=v145, target=b48, fall=b47 } (exit_acc=v145) + block 47 start_pc=0 + v146 Imm(24) -> x0 + terminator Return(v146) (exit_acc=v146) + block 48 start_pc=0 + v147 LocalAddr(-10) -> x0 + v148 Load { addr=v147, disp=0, kind=I64 } -> x0 + v149 BinopI { op=ne, lhs=v148, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v149, target=b50, fall=b49 } (exit_acc=v149) + block 49 start_pc=0 + v150 Imm(25) -> x0 + terminator Return(v150) (exit_acc=v150) + block 50 start_pc=0 + v151 LocalAddr(-10) -> x0 + v152 BinopI { op=add, lhs=v151, rhs_imm=8 } -> x1 + v153 Load { addr=v151, disp=8, kind=I64 } -> x0 + v154 BinopI { op=ne, lhs=v153, rhs_imm=-1 } -> x0 + terminator Bz { cond=v154, target=b52, fall=b51 } (exit_acc=v154) + block 51 start_pc=0 + v155 Imm(26) -> x0 + terminator Return(v155) (exit_acc=v155) + block 52 start_pc=0 + v156 LocalAddr(-10) -> x0 + v157 BinopI { op=add, lhs=v156, rhs_imm=16 } -> x1 + v158 Load { addr=v156, disp=16, kind=I32 } -> x0 + v159 BinopI { op=ne, lhs=v158, rhs_imm=-56 } -> x0 + terminator Bz { cond=v159, target=b54, fall=b53 } (exit_acc=v159) + block 53 start_pc=0 + v160 Imm(27) -> x0 + terminator Return(v160) (exit_acc=v160) + block 54 start_pc=0 + v161 LoadLocal { off=-11, kind=I64 } -> x0 + v162 Imm(0) -> x0 + terminator Jmp(b55) (exit_acc=v162) + block 55 start_pc=0 + v164 Imm(0) -> x0 + terminator Return(v164) (exit_acc=v164) + block 56 start_pc=0 + v163 Imm(28) -> x0 + terminator Return(v163) (exit_acc=v163) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/init_float_to_int.ssa b/tests/snapshots/ssa/init_float_to_int.ssa index 3adc41c1a..df5c26d8f 100644 --- a/tests/snapshots/ssa/init_float_to_int.ssa +++ b/tests/snapshots/ssa/init_float_to_int.ssa @@ -10,7 +10,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v4 BinopI { op=ne, lhs=v3, rhs_imm=1 } -> x1 v5 Imm(1) -> x6 v6 Imm(0) -> x2 - terminator Bnz { cond=v4, target=b17, fall=b1 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b20, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v7 ImmData(8) -> x1 v8 Imm(4) -> x1 @@ -21,10 +21,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v13 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v14 Phi { incoming=[b17:v5, b1:v12], kind=I64 } -> x6 + v14 Phi { incoming=[b20:v5, b1:v12], kind=I64 } -> x6 v15 LoadLocal { off=-2, kind=I64 } -> x1 v16 Imm(0) -> x1 - terminator Bnz { cond=v14, target=b18, fall=b3 } (exit_acc=v14) + terminator Bnz { cond=v14, target=b19, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v17 ImmData(8) -> x1 v18 Imm(8) -> x1 @@ -34,7 +34,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v22 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v21) block 4 start_pc=0 - v23 Phi { incoming=[b18:v14, b3:v21], kind=I64 } -> x6 + v23 Phi { incoming=[b19:v14, b3:v21], kind=I64 } -> x6 v24 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) block 5 start_pc=0 @@ -46,7 +46,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v28 Load { addr=v26, disp=0, kind=I64 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=7 } -> x1 v30 Imm(0) -> x0 - terminator Bnz { cond=v29, target=b19, fall=b7 } (exit_acc=v29) + terminator Bnz { cond=v29, target=b18, fall=b7 } (exit_acc=v29) block 7 start_pc=0 v31 ImmData(24) -> x0 v32 Imm(8) -> x1 @@ -56,7 +56,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v36 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v35) block 8 start_pc=0 - v37 Phi { incoming=[b19:v29, b7:v35], kind=I64 } -> x1 + v37 Phi { incoming=[b18:v29, b7:v35], kind=I64 } -> x1 v38 LoadLocal { off=-3, kind=I64 } -> x0 terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) block 9 start_pc=0 @@ -80,7 +80,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v50 Imm(4607182418800017408) -> x0 v51 Binop { op=fne, lhs=v49, rhs=v50 } -> x1 v52 Imm(0) -> x0 - terminator Bnz { cond=v51, target=b20, fall=b13 } (exit_acc=v51) + terminator Bnz { cond=v51, target=b17, fall=b13 } (exit_acc=v51) block 13 start_pc=0 v53 ImmData(48) -> x0 v54 Imm(8) -> x1 @@ -91,7 +91,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v59 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v58) block 14 start_pc=0 - v60 Phi { incoming=[b20:v51, b13:v58], kind=I64 } -> x1 + v60 Phi { incoming=[b17:v51, b13:v58], kind=I64 } -> x1 v61 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v60, target=b16, fall=b15 } (exit_acc=v60) block 15 start_pc=0 @@ -101,13 +101,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v63 Imm(0) -> x0 terminator Return(v63) (exit_acc=v63) block 17 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b14) block 18 start_pc=0 - terminator Jmp(b4) - block 19 start_pc=0 terminator Jmp(b8) + block 19 start_pc=0 + terminator Jmp(b4) block 20 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/init_scalar_conversion.ssa b/tests/snapshots/ssa/init_scalar_conversion.ssa index ddf079a52..dcef48059 100644 --- a/tests/snapshots/ssa/init_scalar_conversion.ssa +++ b/tests/snapshots/ssa/init_scalar_conversion.ssa @@ -9,7 +9,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=7 v3 Imm(0) -> x2 v4 Binop { op=feq, lhs=v2, rhs=v3 } -> x0 v5 Imm(0) -> x1 - terminator Bz { cond=v4, target=b7, fall=b1 } (exit_acc=v4) + terminator Bz { cond=v4, target=b9, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v6 LocalAddr(-4) -> x0 v7 BinopI { op=add, lhs=v6, rhs_imm=8 } -> x1 @@ -20,7 +20,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=7 v12 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v11) block 2 start_pc=0 - v13 Phi { incoming=[b7:v3, b1:v11], kind=I64 } -> x2 + v13 Phi { incoming=[b9:v3, b1:v11], kind=I64 } -> x2 v14 LoadLocal { off=-7, kind=I64 } -> x0 v15 Imm(0) -> x1 v16 Imm(0) -> x0 @@ -39,7 +39,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=7 v25 LoadLocal { off=-6, kind=I64 } -> x0 v26 Imm(0) -> x2 v27 Imm(0) -> x0 - terminator Bz { cond=v24, target=b9, fall=b5 } (exit_acc=v24) + terminator Bz { cond=v24, target=b7, fall=b5 } (exit_acc=v24) block 5 start_pc=0 v28 LocalAddr(-4) -> x0 v29 BinopI { op=add, lhs=v28, rhs_imm=16 } -> x1 @@ -51,19 +51,19 @@ fn ent_pc=0 n_params=1 variadic=false locals=7 v35 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v34) block 6 start_pc=0 - v36 Phi { incoming=[b9:v26, b5:v34], kind=I64 } -> x2 + v36 Phi { incoming=[b7:v26, b5:v34], kind=I64 } -> x2 v37 LoadLocal { off=-5, kind=I64 } -> x0 terminator Return(v36) (exit_acc=v36) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) block 8 start_pc=0 terminator Jmp(b4) block 9 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=24 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(840) -> x3 @@ -85,19 +85,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v17 LocalAddr(-4) -> x0 v18 Load { addr=v17, disp=0, kind=F64 } -> d0 v19 Imm(4650599933957636096) -> x0 - v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x13 + v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x1 v21 Imm(0) -> x0 - terminator Bnz { cond=v20, target=b25, fall=b1 } (exit_acc=v20) + terminator Bnz { cond=v20, target=b29, fall=b1 } (exit_acc=v20) block 1 start_pc=0 v22 LocalAddr(-4) -> x0 v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x1 v24 Load { addr=v22, disp=8, kind=F64 } -> d0 v25 Imm(4647961106050973696) -> x0 - v26 Binop { op=fne, lhs=v24, rhs=v25 } -> x13 + v26 Binop { op=fne, lhs=v24, rhs=v25 } -> x1 v27 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v26) block 2 start_pc=0 - v28 Phi { incoming=[b25:v20, b1:v26], kind=I64 } -> x13 + v28 Phi { incoming=[b29:v20, b1:v26], kind=I64 } -> x1 v29 LoadLocal { off=-20, kind=I64 } -> x0 terminator Bz { cond=v28, target=b4, fall=b3 } (exit_acc=v28) block 3 start_pc=0 @@ -128,20 +128,20 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v52 BinopI { op=add, lhs=v51, rhs_imm=16 } -> x1 v53 Load { addr=v51, disp=16, kind=F64 } -> d0 v54 Imm(4650599933957636096) -> x0 - v55 Binop { op=fne, lhs=v53, rhs=v54 } -> x13 + v55 Binop { op=fne, lhs=v53, rhs=v54 } -> x1 v56 Imm(0) -> x0 - terminator Bnz { cond=v55, target=b26, fall=b5 } (exit_acc=v55) + terminator Bnz { cond=v55, target=b28, fall=b5 } (exit_acc=v55) block 5 start_pc=0 v57 LocalAddr(-8) -> x0 v58 BinopI { op=add, lhs=v57, rhs_imm=16 } -> x1 v59 BinopI { op=add, lhs=v57, rhs_imm=24 } -> x1 v60 Load { addr=v57, disp=24, kind=F64 } -> d0 v61 Imm(4647961106050973696) -> x0 - v62 Binop { op=fne, lhs=v60, rhs=v61 } -> x13 + v62 Binop { op=fne, lhs=v60, rhs=v61 } -> x1 v63 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v62) block 6 start_pc=0 - v64 Phi { incoming=[b26:v55, b5:v62], kind=I64 } -> x13 + v64 Phi { incoming=[b28:v55, b5:v62], kind=I64 } -> x1 v65 LoadLocal { off=-21, kind=I64 } -> x0 terminator Bz { cond=v64, target=b8, fall=b7 } (exit_acc=v64) block 7 start_pc=0 @@ -164,7 +164,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v80 Imm(0) -> x1 v81 Load { addr=v79, disp=0, kind=F64 } -> d0 v82 Imm(4650599933957636096) -> x0 - v83 Binop { op=fne, lhs=v81, rhs=v82 } -> x13 + v83 Binop { op=fne, lhs=v81, rhs=v82 } -> x1 v84 Imm(0) -> x0 terminator Bnz { cond=v83, target=b27, fall=b9 } (exit_acc=v83) block 9 start_pc=0 @@ -173,11 +173,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v87 BinopI { op=add, lhs=v85, rhs_imm=8 } -> x1 v88 Load { addr=v85, disp=8, kind=F64 } -> d0 v89 Imm(4647961106050973696) -> x0 - v90 Binop { op=fne, lhs=v88, rhs=v89 } -> x13 + v90 Binop { op=fne, lhs=v88, rhs=v89 } -> x1 v91 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v90) block 10 start_pc=0 - v92 Phi { incoming=[b27:v83, b9:v90], kind=I64 } -> x13 + v92 Phi { incoming=[b27:v83, b9:v90], kind=I64 } -> x1 v93 LoadLocal { off=-22, kind=I64 } -> x0 terminator Bz { cond=v92, target=b12, fall=b11 } (exit_acc=v92) block 11 start_pc=0 @@ -199,107 +199,105 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v107 Store { addr=v105, disp=4, value=v104, kind=I32 } -> - v108 LocalAddr(-12) -> x0 v109 Load { addr=v108, disp=0, kind=I32 } -> x0 - v110 BinopI { op=ne, lhs=v109, rhs_imm=3 } -> x13 + v110 BinopI { op=ne, lhs=v109, rhs_imm=3 } -> x1 v111 Imm(0) -> x0 - terminator Bnz { cond=v110, target=b28, fall=b13 } (exit_acc=v110) + terminator Bnz { cond=v110, target=b26, fall=b13 } (exit_acc=v110) block 13 start_pc=0 v112 LocalAddr(-12) -> x0 v113 BinopI { op=add, lhs=v112, rhs_imm=4 } -> x1 v114 Load { addr=v112, disp=4, kind=I32 } -> x0 - v115 BinopI { op=ne, lhs=v114, rhs_imm=7 } -> x13 + v115 BinopI { op=ne, lhs=v114, rhs_imm=7 } -> x1 v116 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v115) block 14 start_pc=0 - v117 Phi { incoming=[b28:v110, b13:v115], kind=I64 } -> x13 + v117 Phi { incoming=[b26:v110, b13:v115], kind=I64 } -> x1 v118 LoadLocal { off=-23, kind=I64 } -> x0 terminator Bz { cond=v117, target=b16, fall=b15 } (exit_acc=v117) block 15 start_pc=0 v119 Imm(4) -> x0 terminator Return(v119) (exit_acc=v119) block 16 start_pc=0 - v120 Imm(0) -> x0 - v121 FpCast { kind=F64ToF32, value=v120 } -> d0 [f32] - v122 Imm(0) -> x1 - v123 LocalAddr(-14) -> x1 - v124 ImmData(80) -> x2 - v125 Mcpy { dst=v123, src=v124, size=4 } -> x1 - v126 LoadLocal { off=-11, kind=F64 } -> d0 - v127 Binop { op=fadd, lhs=v126, rhs=v120 } -> d0 + v120 Imm(0) -> x0 [f32] + v121 StoreLocal { off=-13, value=v120, kind=F32 } -> - + v122 LocalAddr(-14) -> x0 + v123 ImmData(80) -> x1 + v124 Mcpy { dst=v122, src=v123, size=4 } -> x0 + v125 LoadLocal { off=-11, kind=F64 } -> d0 + v126 Imm(0) -> x0 + v127 Binop { op=fadd, lhs=v125, rhs=v126 } -> d0 v128 FpCast { kind=F64ToF32, value=v127 } -> d0 [f32] v129 LocalAddr(-14) -> x0 v130 Store { addr=v129, disp=0, value=v128, kind=F32 } -> - v131 LocalAddr(-14) -> x0 v132 Load { addr=v131, disp=0, kind=F32 } -> d0 [f32] - v133 Imm(0) -> x0 - v134 LoadLocal { off=-13, kind=F32 } -> d1 [f32] - v135 Imm(4615941920075253023) -> x0 - v136 FpCast { kind=F32ToF64, value=v132 } -> d1 - v137 Binop { op=flt, lhs=v136, rhs=v135 } -> x13 - v138 Imm(0) -> x0 - terminator Bnz { cond=v137, target=b29, fall=b17 } (exit_acc=v137) + v133 StoreLocal { off=-13, value=v132, kind=F32 } -> - + v134 LoadLocal { off=-13, kind=F32 } -> d0 [f32] + v135 Imm(1081669059) -> x0 [f32] + v136 Binop { op=flt, lhs=v134, rhs=v135 } -> x1 + v137 Imm(0) -> x0 + terminator Bnz { cond=v136, target=b25, fall=b17 } (exit_acc=v136) block 17 start_pc=0 - v139 LoadLocal { off=-13, kind=F32 } -> d1 [f32] - v140 Imm(4615986956071526728) -> x0 - v141 FpCast { kind=F32ToF64, value=v132 } -> d0 - v142 Binop { op=fgt, lhs=v141, rhs=v140 } -> x13 - v143 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v142) + v138 LoadLocal { off=-13, kind=F32 } -> d0 [f32] + v139 Imm(1081752945) -> x0 [f32] + v140 Binop { op=fgt, lhs=v138, rhs=v139 } -> x1 + v141 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v140) block 18 start_pc=0 - v144 Phi { incoming=[b29:v137, b17:v142], kind=I64 } -> x13 - v145 LoadLocal { off=-24, kind=I64 } -> x0 - terminator Bz { cond=v144, target=b20, fall=b19 } (exit_acc=v144) + v142 Phi { incoming=[b25:v136, b17:v140], kind=I64 } -> x1 + v143 LoadLocal { off=-24, kind=I64 } -> x0 + terminator Bz { cond=v142, target=b20, fall=b19 } (exit_acc=v142) block 19 start_pc=0 - v146 Imm(5) -> x0 - terminator Return(v146) (exit_acc=v146) + v144 Imm(5) -> x0 + terminator Return(v144) (exit_acc=v144) block 20 start_pc=0 - v147 LocalAddr(-8) -> x7 - v148 Call { target_pc=0, args=[v147], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v149 BinopI { op=eq, lhs=v148, rhs_imm=0 } -> x0 - terminator Bz { cond=v149, target=b22, fall=b21 } (exit_acc=v149) + v145 LocalAddr(-8) -> x7 + v146 Call { target_pc=0, args=[v145], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v147 BinopI { op=eq, lhs=v146, rhs_imm=0 } -> x0 + terminator Bz { cond=v147, target=b22, fall=b21 } (exit_acc=v147) block 21 start_pc=0 - v150 Imm(6) -> x0 - terminator Return(v150) (exit_acc=v150) + v148 Imm(6) -> x0 + terminator Return(v148) (exit_acc=v148) block 22 start_pc=0 - v151 LocalAddr(-19) -> x0 - v152 ImmData(84) -> x1 - v153 Mcpy { dst=v151, src=v152, size=32 } -> x0 - v154 Imm(0) -> x0 - v155 FpCast { kind=IntToFp, value=v154 } -> d0 + v149 LocalAddr(-19) -> x0 + v150 ImmData(84) -> x1 + v151 Mcpy { dst=v149, src=v150, size=32 } -> x0 + v152 Imm(0) -> x0 + v153 FpCast { kind=IntToFp, value=v152 } -> d0 + v154 LocalAddr(-19) -> x0 + v155 Store { addr=v154, disp=0, value=v153, kind=F64 } -> - v156 LocalAddr(-19) -> x0 - v157 Store { addr=v156, disp=0, value=v155, kind=F64 } -> - - v158 LocalAddr(-19) -> x0 - v159 BinopI { op=add, lhs=v158, rhs_imm=8 } -> x1 - v160 Store { addr=v158, disp=8, value=v155, kind=F64 } -> - - v161 LoadLocal { off=-1, kind=I32 } -> x0 - v162 FpCast { kind=IntToFp, value=v1 } -> d0 - v163 LocalAddr(-19) -> x0 - v164 BinopI { op=add, lhs=v163, rhs_imm=16 } -> x1 - v165 Store { addr=v163, disp=16, value=v162, kind=F64 } -> - - v166 LoadLocal { off=-2, kind=I32 } -> x0 - v167 FpCast { kind=IntToFp, value=v3 } -> d0 - v168 LocalAddr(-19) -> x0 - v169 BinopI { op=add, lhs=v168, rhs_imm=24 } -> x1 - v170 Store { addr=v168, disp=24, value=v167, kind=F64 } -> - - v171 LocalAddr(-19) -> x7 - v172 Call { target_pc=0, args=[v171], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v173 BinopI { op=eq, lhs=v172, rhs_imm=0 } -> x0 - terminator Bz { cond=v173, target=b24, fall=b23 } (exit_acc=v173) + v157 BinopI { op=add, lhs=v156, rhs_imm=8 } -> x1 + v158 Store { addr=v156, disp=8, value=v153, kind=F64 } -> - + v159 LoadLocal { off=-1, kind=I32 } -> x0 + v160 FpCast { kind=IntToFp, value=v1 } -> d0 + v161 LocalAddr(-19) -> x0 + v162 BinopI { op=add, lhs=v161, rhs_imm=16 } -> x1 + v163 Store { addr=v161, disp=16, value=v160, kind=F64 } -> - + v164 LoadLocal { off=-2, kind=I32 } -> x0 + v165 FpCast { kind=IntToFp, value=v3 } -> d0 + v166 LocalAddr(-19) -> x0 + v167 BinopI { op=add, lhs=v166, rhs_imm=24 } -> x1 + v168 Store { addr=v166, disp=24, value=v165, kind=F64 } -> - + v169 LocalAddr(-19) -> x7 + v170 Call { target_pc=0, args=[v169], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v171 BinopI { op=eq, lhs=v170, rhs_imm=0 } -> x0 + terminator Bz { cond=v171, target=b24, fall=b23 } (exit_acc=v171) block 23 start_pc=0 - v174 Imm(7) -> x0 - terminator Return(v174) (exit_acc=v174) + v172 Imm(7) -> x0 + terminator Return(v172) (exit_acc=v172) block 24 start_pc=0 - v175 Imm(0) -> x0 - terminator Return(v175) (exit_acc=v175) + v173 Imm(0) -> x0 + terminator Return(v173) (exit_acc=v173) block 25 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 26 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b14) block 27 start_pc=0 terminator Jmp(b10) block 28 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b6) block 29 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_arg_count_mismatch.ssa b/tests/snapshots/ssa/inline_arg_count_mismatch.ssa index 6f90e00db..a5918527e 100644 --- a/tests/snapshots/ssa/inline_arg_count_mismatch.ssa +++ b/tests/snapshots/ssa/inline_arg_count_mismatch.ssa @@ -18,39 +18,39 @@ fn ent_pc=0 n_params=2 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=4 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(3) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x3 + v2 Imm(3) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 Imm(3) -> x0 + v6 Imm(0) -> x0 + v7 Imm(5) -> x0 + v8 Imm(21474836480) -> x0 + v9 Imm(5) -> x0 v10 Imm(0) -> x0 v11 Imm(7) -> x7 v12 Call { target_pc=0, args=[v11], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v13 Imm(0) -> x1 v14 Extend { value=v12, kind=I32 } -> x1 v15 BinopI { op=and, lhs=v12, rhs_imm=255 } -> x0 - v16 Extend { value=v9, kind=I32 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=5 } -> x0 - terminator Bz { cond=v17, target=b2, fall=b1 } (exit_acc=v17) + v16 Imm(5) -> x0 + v17 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v17) block 1 start_pc=0 v18 Imm(0) -> x1 v19 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v18) + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v20 Imm(1) -> x1 - v21 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v20) - block 3 start_pc=0 - v22 Phi { incoming=[b1:v18, b2:v20], kind=I64 } -> x1 + v22 Phi { incoming=[b1:v18, b3:v20], kind=I64 } -> x1 v23 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v22) (exit_acc=v22) + block 3 start_pc=0 + v20 Imm(1) -> x1 + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_asm_hint.ssa b/tests/snapshots/ssa/inline_asm_hint.ssa index f9917383b..25f3721a5 100644 --- a/tests/snapshots/ssa/inline_asm_hint.ssa +++ b/tests/snapshots/ssa/inline_asm_hint.ssa @@ -9,27 +9,27 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v17], kind=I64 } -> x0 - v8 Extend { value=v6, kind=I32 } -> x2 - v9 LoadLocal { off=2, kind=I32 } -> x6 - v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v14 Intrinsic { kind=31, args=[] } -> x6 + v15 Extend { value=v7, kind=I32 } -> x6 + v16 Extend { value=v6, kind=I32 } -> x6 + v17 Binop { op=add, lhs=v7, rhs=v6 } -> x0 + v18 Imm(0) -> x6 + v19 Extend { value=v17, kind=I32 } -> x6 + terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 v11 Extend { value=v6, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) + terminator Jmp(b3) (exit_acc=v12) block 3 start_pc=0 - v14 Intrinsic { kind=31, args=[] } -> x2 - v15 Extend { value=v7, kind=I32 } -> x2 - v16 Extend { value=v6, kind=I32 } -> x2 - v17 Binop { op=add, lhs=v7, rhs=v6 } -> x0 - v18 Imm(0) -> x2 - v19 Extend { value=v17, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v19) + v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b2:v17], kind=I64 } -> x0 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 LoadLocal { off=2, kind=I32 } -> x6 + v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v20 Extend { value=v7, kind=I32 } -> x0 terminator Return(v20) (exit_acc=v20) diff --git a/tests/snapshots/ssa/inline_forward_ref_value.ssa b/tests/snapshots/ssa/inline_forward_ref_value.ssa index 31e72dc34..7ff263136 100644 --- a/tests/snapshots/ssa/inline_forward_ref_value.ssa +++ b/tests/snapshots/ssa/inline_forward_ref_value.ssa @@ -49,7 +49,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=3 --- ; name=compute fn ent_pc=3 n_params=1 variadic=false locals=6 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -64,35 +64,35 @@ fn ent_pc=3 n_params=1 variadic=false locals=6 v10 Extend { value=v8, kind=I32 } -> x3 v11 Imm(0) -> x0 v12 LoadLocal { off=2, kind=I64 } -> x0 - terminator Bz { cond=v1, target=b3, fall=b1 } (exit_acc=v1) + terminator Bz { cond=v1, target=b5, fall=b1 } (exit_acc=v1) block 1 start_pc=0 v13 LoadLocal { off=2, kind=I64 } -> x0 - v14 BinopI { op=add, lhs=v1, rhs_imm=100 } -> x12 - v15 Imm(0) -> x0 - v16 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x13 - v17 Imm(0) -> x0 - v18 LoadLocal { off=-3, kind=I64 } -> x0 - v19 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b4 } (exit_acc=v19) + v14 BinopI { op=add, lhs=v1, rhs_imm=100 } -> x0 + v15 Imm(0) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x1 + v17 Imm(0) -> x2 + v18 LoadLocal { off=-3, kind=I64 } -> x2 + v19 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x2 + terminator Bz { cond=v19, target=b3, fall=b2 } (exit_acc=v19) block 2 start_pc=0 + v26 Imm(-1) -> x0 + terminator Return(v26) (exit_acc=v26) + block 3 start_pc=0 + v27 LoadLocal { off=-3, kind=I64 } -> x2 + v28 Imm(0) -> x2 + v29 BinopI { op=shl, lhs=v14, rhs_imm=1 } -> x2 + v30 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v29) + block 4 start_pc=0 v20 LoadLocal { off=-1, kind=I64 } -> x0 v21 LoadLocal { off=-2, kind=I64 } -> x0 v22 Call { target_pc=1, args=[v29, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v23 Extend { value=v10, kind=I32 } -> x1 v24 Binop { op=add, lhs=v22, rhs=v23 } -> x0 terminator Return(v24) (exit_acc=v24) - block 3 start_pc=0 + block 5 start_pc=0 v25 Imm(-2) -> x0 terminator Return(v25) (exit_acc=v25) - block 4 start_pc=0 - v26 Imm(-1) -> x0 - terminator Return(v26) (exit_acc=v26) - block 5 start_pc=0 - v27 LoadLocal { off=-3, kind=I64 } -> x0 - v28 Imm(0) -> x0 - v29 BinopI { op=shl, lhs=v14, rhs_imm=1 } -> x1 - v30 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=4 --- ; name=main fn ent_pc=4 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_into_computed_goto.ssa b/tests/snapshots/ssa/inline_into_computed_goto.ssa index e17acd065..761c067a5 100644 --- a/tests/snapshots/ssa/inline_into_computed_goto.ssa +++ b/tests/snapshots/ssa/inline_into_computed_goto.ssa @@ -47,8 +47,8 @@ fn ent_pc=2 n_params=2 variadic=false locals=6 v19 StoreLocal { off=-4, value=v6, kind=I64 } -> - v20 StoreLocal { off=-5, value=v6, kind=I32 } -> - v21 LocalAddr(-3) -> x0 - v22 LoadLocal { off=2, kind=I64 } -> x1 - v23 LoadLocal { off=-5, kind=I32 } -> x2 + v22 LoadLocal { off=2, kind=I64 } -> x2 + v23 Extend { value=v6, kind=I32 } -> x1 v24 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x6 v25 StoreLocal { off=-5, value=v24, kind=I32 } -> - v26 BinopI { op=shl, lhs=v23, rhs_imm=2 } -> x6 @@ -65,24 +65,24 @@ fn ent_pc=2 n_params=2 variadic=false locals=6 v35 LoadLocal { off=-5, kind=I32 } -> x6 v36 BinopI { op=add, lhs=v35, rhs_imm=1 } -> x7 v37 StoreLocal { off=-5, value=v36, kind=I32 } -> - - v38 BinopI { op=shl, lhs=v35, rhs_imm=2 } -> x7 - v39 Binop { op=add, lhs=v34, rhs=v38 } -> x7 - v40 LoadIndexed { base=v34, index=v35, scale=4, kind=I32 } -> x2 - v41 BinopI { op=shl, lhs=v40, rhs_imm=3 } -> x6 - v42 Binop { op=add, lhs=v33, rhs=v41 } -> x6 + v38 BinopI { op=shl, lhs=v35, rhs_imm=2 } -> x8 + v39 Binop { op=add, lhs=v34, rhs=v38 } -> x8 + v40 LoadIndexed { base=v34, index=v35, scale=4, kind=I32 } -> x6 + v41 BinopI { op=shl, lhs=v40, rhs_imm=3 } -> x8 + v42 Binop { op=add, lhs=v33, rhs=v41 } -> x8 v43 LoadIndexed { base=v33, index=v40, scale=8, kind=I64 } -> x1 - v44 Imm(-4) -> x2 + v44 Imm(-4) -> x6 v45 BinopI { op=and, lhs=v43, rhs_imm=-4 } -> x1 v46 Binop { op=add, lhs=v32, rhs=v45 } -> x0 v47 StoreLocal { off=-4, value=v46, kind=I64 } -> - v48 LocalAddr(-3) -> x0 v49 LoadLocal { off=2, kind=I64 } -> x1 - v50 LoadLocal { off=-5, kind=I32 } -> x2 + v50 Extend { value=v36, kind=I32 } -> x1 v51 BinopI { op=add, lhs=v50, rhs_imm=1 } -> x6 v52 StoreLocal { off=-5, value=v51, kind=I32 } -> - v53 BinopI { op=shl, lhs=v50, rhs_imm=2 } -> x6 - v54 Binop { op=add, lhs=v49, rhs=v53 } -> x6 - v55 LoadIndexed { base=v49, index=v50, scale=4, kind=I32 } -> x1 + v54 Binop { op=add, lhs=v34, rhs=v53 } -> x6 + v55 LoadIndexed { base=v34, index=v50, scale=4, kind=I32 } -> x1 v56 BinopI { op=shl, lhs=v55, rhs_imm=3 } -> x2 v57 Binop { op=add, lhs=v48, rhs=v56 } -> x2 v58 LoadIndexed { base=v48, index=v55, scale=8, kind=I64 } -> x0 @@ -134,19 +134,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=10 v19 LocalAddr(-3) -> x6 v20 Call { target_pc=2, args=[v18, v19], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v21 BinopI { op=eq, lhs=v20, rhs_imm=900 } -> x0 - terminator Bz { cond=v21, target=b2, fall=b1 } (exit_acc=v21) + terminator Bz { cond=v21, target=b3, fall=b1 } (exit_acc=v21) block 1 start_pc=0 v22 Imm(0) -> x1 v23 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v22) + terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 - v24 Imm(1) -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v24) - block 3 start_pc=0 - v26 Phi { incoming=[b1:v22, b2:v24], kind=I64 } -> x1 + v26 Phi { incoming=[b1:v22, b3:v24], kind=I64 } -> x1 v27 LoadLocal { off=-10, kind=I64 } -> x0 terminator Return(v26) (exit_acc=v26) + block 3 start_pc=0 + v24 Imm(1) -> x1 + v25 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v24) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_keyword_uncaps.ssa b/tests/snapshots/ssa/inline_keyword_uncaps.ssa index d8f74f8c3..0850b3a43 100644 --- a/tests/snapshots/ssa/inline_keyword_uncaps.ssa +++ b/tests/snapshots/ssa/inline_keyword_uncaps.ssa @@ -63,90 +63,90 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v4 Imm(0) -> x1 - v5 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x0 - v6 Imm(0) -> x1 - v7 BinopI { op=add, lhs=v5, rhs_imm=3 } -> x0 - v8 Imm(0) -> x1 - v9 BinopI { op=add, lhs=v7, rhs_imm=4 } -> x0 - v10 Imm(0) -> x1 - v11 BinopI { op=add, lhs=v9, rhs_imm=5 } -> x0 - v12 Imm(0) -> x1 - v13 BinopI { op=add, lhs=v11, rhs_imm=6 } -> x0 - v14 Imm(0) -> x1 - v15 BinopI { op=add, lhs=v13, rhs_imm=7 } -> x0 - v16 Imm(0) -> x1 - v17 BinopI { op=add, lhs=v15, rhs_imm=8 } -> x0 - v18 Imm(0) -> x1 - v19 BinopI { op=add, lhs=v17, rhs_imm=9 } -> x0 - v20 Imm(0) -> x1 - v21 BinopI { op=add, lhs=v19, rhs_imm=10 } -> x0 - v22 Imm(0) -> x1 - v23 BinopI { op=add, lhs=v21, rhs_imm=11 } -> x0 - v24 Imm(0) -> x1 - v25 BinopI { op=add, lhs=v23, rhs_imm=12 } -> x0 - v26 Imm(0) -> x1 - v27 BinopI { op=add, lhs=v25, rhs_imm=13 } -> x0 - v28 Imm(0) -> x1 - v29 BinopI { op=add, lhs=v27, rhs_imm=14 } -> x0 - v30 Imm(0) -> x1 - v31 BinopI { op=add, lhs=v29, rhs_imm=15 } -> x0 - v32 Imm(0) -> x1 - v33 BinopI { op=add, lhs=v31, rhs_imm=16 } -> x0 - v34 Imm(0) -> x1 - v35 Imm(100) -> x1 - v36 Imm(0) -> x2 - v37 BinopI { op=add, lhs=v35, rhs_imm=1 } -> x1 - v38 Imm(0) -> x2 - v39 BinopI { op=add, lhs=v37, rhs_imm=2 } -> x1 - v40 Imm(0) -> x2 - v41 BinopI { op=add, lhs=v39, rhs_imm=3 } -> x1 - v42 Imm(0) -> x2 - v43 BinopI { op=add, lhs=v41, rhs_imm=4 } -> x1 - v44 Imm(0) -> x2 - v45 BinopI { op=add, lhs=v43, rhs_imm=5 } -> x1 - v46 Imm(0) -> x2 - v47 BinopI { op=add, lhs=v45, rhs_imm=6 } -> x1 - v48 Imm(0) -> x2 - v49 BinopI { op=add, lhs=v47, rhs_imm=7 } -> x1 - v50 Imm(0) -> x2 - v51 BinopI { op=add, lhs=v49, rhs_imm=8 } -> x1 - v52 Imm(0) -> x2 - v53 BinopI { op=add, lhs=v51, rhs_imm=9 } -> x1 - v54 Imm(0) -> x2 - v55 BinopI { op=add, lhs=v53, rhs_imm=10 } -> x1 - v56 Imm(0) -> x2 - v57 BinopI { op=add, lhs=v55, rhs_imm=11 } -> x1 - v58 Imm(0) -> x2 - v59 BinopI { op=add, lhs=v57, rhs_imm=12 } -> x1 - v60 Imm(0) -> x2 - v61 BinopI { op=add, lhs=v59, rhs_imm=13 } -> x1 - v62 Imm(0) -> x2 - v63 BinopI { op=add, lhs=v61, rhs_imm=14 } -> x1 - v64 Imm(0) -> x2 - v65 BinopI { op=add, lhs=v63, rhs_imm=15 } -> x1 - v66 Imm(0) -> x2 - v67 BinopI { op=add, lhs=v65, rhs_imm=16 } -> x1 - v68 Imm(0) -> x2 - v69 Binop { op=add, lhs=v33, rhs=v67 } -> x0 - v70 Imm(0) -> x1 - v71 LoadLocal { off=-1, kind=I64 } -> x1 - v72 BinopI { op=eq, lhs=v69, rhs_imm=372 } -> x0 - terminator Bz { cond=v72, target=b2, fall=b1 } (exit_acc=v72) + v2 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 Imm(0) -> x0 + v5 Imm(3) -> x0 + v6 Imm(0) -> x0 + v7 Imm(6) -> x0 + v8 Imm(0) -> x0 + v9 Imm(10) -> x0 + v10 Imm(0) -> x0 + v11 Imm(15) -> x0 + v12 Imm(0) -> x0 + v13 Imm(21) -> x0 + v14 Imm(0) -> x0 + v15 Imm(28) -> x0 + v16 Imm(0) -> x0 + v17 Imm(36) -> x0 + v18 Imm(0) -> x0 + v19 Imm(45) -> x0 + v20 Imm(0) -> x0 + v21 Imm(55) -> x0 + v22 Imm(0) -> x0 + v23 Imm(66) -> x0 + v24 Imm(0) -> x0 + v25 Imm(78) -> x0 + v26 Imm(0) -> x0 + v27 Imm(91) -> x0 + v28 Imm(0) -> x0 + v29 Imm(105) -> x0 + v30 Imm(0) -> x0 + v31 Imm(120) -> x0 + v32 Imm(0) -> x0 + v33 Imm(136) -> x0 + v34 Imm(0) -> x0 + v35 Imm(100) -> x0 + v36 Imm(0) -> x0 + v37 Imm(101) -> x0 + v38 Imm(0) -> x0 + v39 Imm(103) -> x0 + v40 Imm(0) -> x0 + v41 Imm(106) -> x0 + v42 Imm(0) -> x0 + v43 Imm(110) -> x0 + v44 Imm(0) -> x0 + v45 Imm(115) -> x0 + v46 Imm(0) -> x0 + v47 Imm(121) -> x0 + v48 Imm(0) -> x0 + v49 Imm(128) -> x0 + v50 Imm(0) -> x0 + v51 Imm(136) -> x0 + v52 Imm(0) -> x0 + v53 Imm(145) -> x0 + v54 Imm(0) -> x0 + v55 Imm(155) -> x0 + v56 Imm(0) -> x0 + v57 Imm(166) -> x0 + v58 Imm(0) -> x0 + v59 Imm(178) -> x0 + v60 Imm(0) -> x0 + v61 Imm(191) -> x0 + v62 Imm(0) -> x0 + v63 Imm(205) -> x0 + v64 Imm(0) -> x0 + v65 Imm(220) -> x0 + v66 Imm(0) -> x0 + v67 Imm(236) -> x0 + v68 Imm(0) -> x0 + v69 Imm(372) -> x0 + v70 Imm(0) -> x0 + v71 LoadLocal { off=-1, kind=I64 } -> x0 + v72 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v72) block 1 start_pc=0 v73 Imm(0) -> x1 v74 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v73) + terminator Jmp(b2) (exit_acc=v73) block 2 start_pc=0 - v75 Imm(1) -> x1 - v76 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v75) - block 3 start_pc=0 - v77 Phi { incoming=[b1:v73, b2:v75], kind=I64 } -> x1 + v77 Phi { incoming=[b1:v73, b3:v75], kind=I64 } -> x1 v78 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v77) (exit_acc=v77) + block 3 start_pc=0 + v75 Imm(1) -> x1 + v76 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v75) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_linkage.ssa b/tests/snapshots/ssa/inline_linkage.ssa index b5e53cc99..6f1db4c8d 100644 --- a/tests/snapshots/ssa/inline_linkage.ssa +++ b/tests/snapshots/ssa/inline_linkage.ssa @@ -44,60 +44,58 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(10) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 BinopI { op=eq, lhs=v6, rhs_imm=11 } -> x0 + v2 Imm(10) -> x0 + v3 Imm(0) -> x0 + v4 Imm(11) -> x0 + v5 Imm(47244640256) -> x0 + v6 Imm(11) -> x0 + v7 Imm(1) -> x0 v8 Imm(0) -> x2 v9 Imm(0) -> x1 - terminator Bz { cond=v7, target=b8, fall=b1 } (exit_acc=v7) + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 v10 Imm(10) -> x0 - v11 Extend { value=v10, kind=I32 } -> x1 - v12 Imm(0) -> x1 - v13 BinopI { op=add, lhs=v10, rhs_imm=2 } -> x0 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x1 - v15 Extend { value=v13, kind=I32 } -> x0 - v16 BinopI { op=eq, lhs=v15, rhs_imm=12 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=0 } -> x2 + v11 Imm(10) -> x0 + v12 Imm(0) -> x0 + v13 Imm(12) -> x0 + v14 Imm(51539607552) -> x0 + v15 Imm(12) -> x0 + v16 Imm(1) -> x0 + v17 Imm(1) -> x2 v18 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 - v19 Phi { incoming=[b8:v8, b1:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b0:v8, b1:v17], kind=I64 } -> x2 v20 LoadLocal { off=-3, kind=I64 } -> x0 v21 Imm(0) -> x0 - terminator Bz { cond=v19, target=b9, fall=b3 } (exit_acc=v19) + terminator Bz { cond=v19, target=b8, fall=b3 } (exit_acc=v19) block 3 start_pc=0 v22 Imm(10) -> x0 - v23 Extend { value=v22, kind=I32 } -> x1 - v24 Imm(0) -> x1 - v25 BinopI { op=add, lhs=v22, rhs_imm=3 } -> x0 - v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x1 - v27 Extend { value=v25, kind=I32 } -> x0 - v28 BinopI { op=eq, lhs=v27, rhs_imm=13 } -> x2 + v23 Imm(10) -> x0 + v24 Imm(0) -> x0 + v25 Imm(13) -> x0 + v26 Imm(55834574848) -> x0 + v27 Imm(13) -> x0 + v28 Imm(1) -> x2 v29 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v28) block 4 start_pc=0 - v30 Phi { incoming=[b9:v19, b3:v28], kind=I64 } -> x2 + v30 Phi { incoming=[b8:v19, b3:v28], kind=I64 } -> x2 v31 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + terminator Bz { cond=v30, target=b7, fall=b5 } (exit_acc=v30) block 5 start_pc=0 v32 Imm(0) -> x1 v33 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v32) + terminator Jmp(b6) (exit_acc=v32) block 6 start_pc=0 - v34 Imm(1) -> x1 - v35 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v34) - block 7 start_pc=0 - v36 Phi { incoming=[b5:v32, b6:v34], kind=I64 } -> x1 + v36 Phi { incoming=[b5:v32, b7:v34], kind=I64 } -> x1 v37 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v36) (exit_acc=v36) + block 7 start_pc=0 + v34 Imm(1) -> x1 + v35 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v34) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/inline_multi_block_result_forward.ssa b/tests/snapshots/ssa/inline_multi_block_result_forward.ssa index 7556898d7..889dbeb18 100644 --- a/tests/snapshots/ssa/inline_multi_block_result_forward.ssa +++ b/tests/snapshots/ssa/inline_multi_block_result_forward.ssa @@ -37,8 +37,18 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 - terminator Jmp(b4) + terminator Jmp(b1) block 1 start_pc=0 + v10 Extend { value=v1, kind=I32 } -> x0 + v11 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v10) + block 2 start_pc=0 + v12 BinopI { op=shl, lhs=v10, rhs_imm=1 } -> x0 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 + v14 Extend { value=v12, kind=I32 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 v16 Imm(0) -> x0 v17 LoadLocal { off=2, kind=I32 } -> x0 v18 Extend { value=v1, kind=I32 } -> x0 @@ -49,27 +59,17 @@ fn ent_pc=2 n_params=1 variadic=false locals=3 v23 Imm(0) -> x0 v24 LoadLocal { off=2, kind=I32 } -> x0 v25 BinopI { op=gt, lhs=v1, rhs_imm=3 } -> x0 - terminator Bz { cond=v25, target=b3, fall=b2 } (exit_acc=v25) - block 2 start_pc=0 + terminator Bz { cond=v25, target=b5, fall=b4 } (exit_acc=v25) + block 4 start_pc=0 v4 Extend { value=v14, kind=I32 } -> x0 terminator Return(v4) (exit_acc=v4) - block 3 start_pc=0 + block 5 start_pc=0 v5 Extend { value=v14, kind=I32 } -> x0 v6 Extend { value=v22, kind=I32 } -> x0 v7 Binop { op=add, lhs=v14, rhs=v20 } -> x0 v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 v9 Extend { value=v7, kind=I32 } -> x0 terminator Return(v9) (exit_acc=v9) - block 4 start_pc=0 - v10 Extend { value=v1, kind=I32 } -> x0 - v11 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v10) - block 5 start_pc=0 - v12 BinopI { op=shl, lhs=v10, rhs_imm=1 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_one_word_struct.ssa b/tests/snapshots/ssa/inline_one_word_struct.ssa index 728b97ddc..27e477961 100644 --- a/tests/snapshots/ssa/inline_one_word_struct.ssa +++ b/tests/snapshots/ssa/inline_one_word_struct.ssa @@ -20,29 +20,29 @@ fn ent_pc=1 n_params=2 variadic=false locals=3 v5 Imm(0) -> x1 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v14], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v22], kind=I64 } -> x0 - v10 Extend { value=v8, kind=I32 } -> x2 - v11 LoadLocal { off=3, kind=I32 } -> x8 - v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x2 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v16 LoadLocal { off=-1, kind=I64 } -> x8 + v17 LoadLocal { off=2, kind=I64 } -> x8 + v18 Extend { value=v8, kind=I32 } -> x8 + v19 BinopI { op=shl, lhs=v10, rhs_imm=3 } -> x8 + v20 Binop { op=add, lhs=v1, rhs=v19 } -> x8 + v21 LoadIndexed { base=v1, index=v10, scale=8, kind=I64 } -> x8 + v22 Binop { op=add, lhs=v9, rhs=v21 } -> x0 + v23 Imm(0) -> x8 + terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 v13 Extend { value=v8, kind=I32 } -> x1 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 v15 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v14) + terminator Jmp(b3) (exit_acc=v14) block 3 start_pc=0 - v16 LoadLocal { off=-1, kind=I64 } -> x2 - v17 LoadLocal { off=2, kind=I64 } -> x2 - v18 Extend { value=v8, kind=I32 } -> x2 - v19 BinopI { op=shl, lhs=v18, rhs_imm=3 } -> x8 - v20 Binop { op=add, lhs=v1, rhs=v19 } -> x8 - v21 LoadIndexed { base=v1, index=v18, scale=8, kind=I64 } -> x2 - v22 Binop { op=add, lhs=v9, rhs=v21 } -> x0 - v23 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v22) + v8 Phi { incoming=[b0:v5, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v22], kind=I64 } -> x0 + v10 Extend { value=v8, kind=I32 } -> x2 + v11 LoadLocal { off=3, kind=I32 } -> x8 + v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x8 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v24 LoadLocal { off=-1, kind=I64 } -> x1 terminator Return(v9) (exit_acc=v9) @@ -52,48 +52,101 @@ fn ent_pc=2 n_params=0 variadic=false locals=9 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=5 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-5) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(1) -> x1 + v10 Imm(4294967296) -> x1 + v11 Imm(1) -> x1 + v12 Imm(100) -> x1 + v13 Store { addr=v8, disp=0, value=v12, kind=I64 } -> - + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 LocalAddr(-5) -> x0 + v20 Imm(1) -> x1 + v21 Imm(8) -> x1 + v22 BinopI { op=add, lhs=v19, rhs_imm=8 } -> x1 + v23 Imm(2) -> x1 + v24 Imm(8589934592) -> x1 + v25 Imm(2) -> x1 + v26 Imm(200) -> x1 + v27 Store { addr=v19, disp=8, value=v26, kind=I64 } -> - + v28 Imm(1) -> x0 + v29 Imm(2) -> x0 + v30 Imm(0) -> x0 + v31 Imm(2) -> x0 + v32 Imm(1) -> x0 + v33 LocalAddr(-5) -> x0 + v34 Imm(2) -> x1 + v35 Imm(16) -> x1 + v36 BinopI { op=add, lhs=v33, rhs_imm=16 } -> x1 + v37 Imm(3) -> x1 + v38 Imm(12884901888) -> x1 + v39 Imm(3) -> x1 + v40 Imm(300) -> x1 + v41 Store { addr=v33, disp=16, value=v40, kind=I64 } -> - + v42 Imm(2) -> x0 + v43 Imm(3) -> x0 + v44 Imm(0) -> x0 + v45 Imm(3) -> x0 + v46 Imm(1) -> x0 + v47 LocalAddr(-5) -> x0 + v48 Imm(3) -> x1 + v49 Imm(24) -> x1 + v50 BinopI { op=add, lhs=v47, rhs_imm=24 } -> x1 + v51 Imm(4) -> x1 + v52 Imm(17179869184) -> x1 + v53 Imm(4) -> x1 + v54 Imm(400) -> x1 + v55 Store { addr=v47, disp=24, value=v54, kind=I64 } -> - + v56 Imm(3) -> x0 + v57 Imm(4) -> x0 + v58 Imm(0) -> x0 + v59 Imm(4) -> x0 + v60 Imm(1) -> x0 + v61 LocalAddr(-5) -> x0 + v62 Imm(4) -> x1 + v63 Imm(32) -> x1 + v64 BinopI { op=add, lhs=v61, rhs_imm=32 } -> x1 + v65 Imm(5) -> x1 + v66 Imm(21474836480) -> x1 + v67 Imm(5) -> x1 + v68 Imm(500) -> x1 + v69 Store { addr=v61, disp=32, value=v68, kind=I64 } -> - + v70 Imm(4) -> x0 + v71 Imm(5) -> x0 + v72 Imm(0) -> x0 + v73 Imm(5) -> x0 + v74 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v74) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v75 LocalAddr(-5) -> x7 + v76 Imm(5) -> x6 + v77 Call { target_pc=1, args=[v75, v76], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v78 BinopI { op=eq, lhs=v77, rhs_imm=1500 } -> x0 + terminator Bz { cond=v78, target=b5, fall=b3 } (exit_acc=v78) block 3 start_pc=0 - v9 LocalAddr(-5) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=3 } -> x6 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 - v13 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x6 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 - v15 Extend { value=v13, kind=I32 } -> x6 - v16 BinopI { op=mul, lhs=v15, rhs_imm=100 } -> x6 - v17 StoreIndexed { base=v9, index=v10, scale=8, value=v16, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v17) + v79 Imm(0) -> x1 + v80 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v79) block 4 start_pc=0 - v18 LocalAddr(-5) -> x7 - v19 Imm(5) -> x6 - v20 Call { target_pc=1, args=[v18, v19], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v21 BinopI { op=eq, lhs=v20, rhs_imm=1500 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) + v83 Phi { incoming=[b3:v79, b5:v81], kind=I64 } -> x1 + v84 LoadLocal { off=-9, kind=I64 } -> x0 + terminator Return(v83) (exit_acc=v83) block 5 start_pc=0 - v22 Imm(0) -> x1 - v23 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v22) - block 6 start_pc=0 - v24 Imm(1) -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v24) - block 7 start_pc=0 - v26 Phi { incoming=[b5:v22, b6:v24], kind=I64 } -> x1 - v27 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Return(v26) (exit_acc=v26) + v81 Imm(1) -> x1 + v82 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v81) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_one_word_struct_return.ssa b/tests/snapshots/ssa/inline_one_word_struct_return.ssa index cae2c09e3..694ae6bbe 100644 --- a/tests/snapshots/ssa/inline_one_word_struct_return.ssa +++ b/tests/snapshots/ssa/inline_one_word_struct_return.ssa @@ -32,56 +32,56 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v29], kind=I64 } -> x0 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=5 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v11 Extend { value=v4, kind=I32 } -> x6 + v12 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x6 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x7 + v14 Extend { value=v12, kind=I32 } -> x6 + v15 BinopI { op=mul, lhs=v14, rhs_imm=10 } -> x6 + v16 Imm(0) -> x7 + v17 LocalAddr(-6) -> x7 + v18 ImmData(8) -> x7 + v19 Imm(0) -> x7 + v20 LocalAddr(-6) -> x7 + v21 Imm(0) -> x7 + v22 LocalAddr(-6) -> x7 + v23 LocalAddr(-6) -> x7 + v24 LocalAddr(-3) -> x7 + v25 Imm(0) -> x7 + v26 LoadLocal { off=-1, kind=I64 } -> x7 + v27 LocalAddr(-3) -> x7 + v28 Load { addr=v27, disp=0, kind=I64 } -> x7 + v29 Binop { op=add, lhs=v5, rhs=v15 } -> x0 + v30 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v29) block 2 start_pc=0 v8 Extend { value=v4, kind=I32 } -> x1 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v9 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 v10 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 3 start_pc=0 - v11 Extend { value=v4, kind=I32 } -> x2 - v12 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x2 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x6 - v14 Extend { value=v12, kind=I32 } -> x2 - v15 BinopI { op=mul, lhs=v14, rhs_imm=10 } -> x2 - v16 Imm(0) -> x6 - v17 LocalAddr(-6) -> x6 - v18 ImmData(8) -> x6 - v19 Imm(0) -> x6 - v20 LocalAddr(-6) -> x6 - v21 Imm(0) -> x6 - v22 LocalAddr(-6) -> x6 - v23 LocalAddr(-6) -> x6 - v24 LocalAddr(-3) -> x6 - v25 Imm(0) -> x6 - v26 LoadLocal { off=-1, kind=I64 } -> x6 - v27 LocalAddr(-3) -> x6 - v28 Load { addr=v27, disp=0, kind=I64 } -> x6 - v29 Binop { op=add, lhs=v5, rhs=v15 } -> x0 - v30 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v29) + v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 + v5 Phi { incoming=[b0:v1, b2:v29], kind=I64 } -> x0 + v6 Extend { value=v4, kind=I32 } -> x2 + v7 BinopI { op=lt, lhs=v6, rhs_imm=5 } -> x6 + terminator Bnz { cond=v7, target=b1, fall=b4 } (exit_acc=v7) block 4 start_pc=0 v31 LoadLocal { off=-1, kind=I64 } -> x1 v32 BinopI { op=eq, lhs=v5, rhs_imm=150 } -> x0 - terminator Bz { cond=v32, target=b6, fall=b5 } (exit_acc=v32) + terminator Bz { cond=v32, target=b7, fall=b5 } (exit_acc=v32) block 5 start_pc=0 v33 Imm(0) -> x1 v34 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v33) + terminator Jmp(b6) (exit_acc=v33) block 6 start_pc=0 - v35 Imm(1) -> x1 - v36 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v35) - block 7 start_pc=0 - v37 Phi { incoming=[b5:v33, b6:v35], kind=I64 } -> x1 + v37 Phi { incoming=[b5:v33, b7:v35], kind=I64 } -> x1 v38 LoadLocal { off=-7, kind=I64 } -> x0 terminator Return(v37) (exit_acc=v37) + block 7 start_pc=0 + v35 Imm(1) -> x1 + v36 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_phi_caller_leaf_helper.ssa b/tests/snapshots/ssa/inline_phi_caller_leaf_helper.ssa index 8499050c5..91dd4b0dd 100644 --- a/tests/snapshots/ssa/inline_phi_caller_leaf_helper.ssa +++ b/tests/snapshots/ssa/inline_phi_caller_leaf_helper.ssa @@ -22,7 +22,7 @@ fn ent_pc=0 n_params=3 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=digest fn ent_pc=1 n_params=2 variadic=false locals=8 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -37,51 +37,51 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v10 Imm(0) -> x0 v11 Imm(0) -> x1 v12 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v11) + terminator Jmp(b3) (exit_acc=v11) block 1 start_pc=0 - v13 Phi { incoming=[b0:v11, b2:v21], kind=I64 } -> x1 - v14 Phi { incoming=[b0:v9, b2:v45], kind=I64 } -> x2 - v15 Phi { incoming=[b0:v7, b2:v47], kind=I64 } -> x8 - v16 Phi { incoming=[b0:v5, b2:v49], kind=I64 } -> x9 - v17 Extend { value=v13, kind=I32 } -> x0 - v18 LoadLocal { off=3, kind=I32 } -> x3 - v19 Binop { op=lt, lhs=v17, rhs=v3 } -> x0 - terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) - block 2 start_pc=0 - v20 Extend { value=v13, kind=I32 } -> x0 - v21 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x1 - v22 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v21) - block 3 start_pc=0 - v23 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x0 - v24 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x3 + v23 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x3 + v24 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x12 v25 BinopI { op=and, lhs=v14, rhs_imm=4294967295 } -> x2 - v26 Imm(0) -> x12 - v27 Imm(0) -> x12 - v28 Imm(0) -> x12 - v29 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x0 - v30 BinopI { op=and, lhs=v24, rhs_imm=4294967295 } -> x3 - v31 Binop { op=and, lhs=v29, rhs=v30 } -> x3 - v32 BinopI { op=xor, lhs=v29, rhs_imm=-1 } -> x0 - v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x0 + v26 Imm(0) -> x13 + v27 Imm(0) -> x13 + v28 Imm(0) -> x13 + v29 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x3 + v30 BinopI { op=and, lhs=v24, rhs_imm=4294967295 } -> x12 + v31 Binop { op=and, lhs=v29, rhs=v30 } -> x12 + v32 BinopI { op=xor, lhs=v29, rhs_imm=-1 } -> x3 + v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x3 v34 BinopI { op=and, lhs=v25, rhs_imm=4294967295 } -> x2 - v35 Binop { op=and, lhs=v33, rhs=v34 } -> x0 - v36 Binop { op=xor, lhs=v31, rhs=v35 } -> x0 - v37 LoadLocal { off=2, kind=I64 } -> x2 - v38 Extend { value=v13, kind=I32 } -> x2 - v39 BinopI { op=shl, lhs=v38, rhs_imm=2 } -> x3 + v35 Binop { op=and, lhs=v33, rhs=v34 } -> x2 + v36 Binop { op=xor, lhs=v31, rhs=v35 } -> x2 + v37 LoadLocal { off=2, kind=I64 } -> x3 + v38 Extend { value=v13, kind=I32 } -> x3 + v39 BinopI { op=shl, lhs=v17, rhs_imm=2 } -> x3 v40 Binop { op=add, lhs=v1, rhs=v39 } -> x3 - v41 LoadIndexed { base=v1, index=v38, scale=4, kind=U32 } -> x2 - v42 Binop { op=add, lhs=v36, rhs=v41 } -> x0 - v43 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x0 + v41 LoadIndexed { base=v1, index=v17, scale=4, kind=U32 } -> x3 + v42 Binop { op=add, lhs=v36, rhs=v41 } -> x2 + v43 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x3 v44 Imm(0) -> x2 v45 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x2 v46 Imm(0) -> x8 v47 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x8 v48 Imm(0) -> x9 v49 BinopI { op=and, lhs=v43, rhs_imm=4294967295 } -> x9 - v50 Imm(0) -> x0 + v50 Imm(0) -> x3 terminator Jmp(b2) (exit_acc=v49) + block 2 start_pc=0 + v20 Extend { value=v13, kind=I32 } -> x1 + v21 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x1 + v22 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v21) + block 3 start_pc=0 + v13 Phi { incoming=[b0:v11, b2:v21], kind=I64 } -> x1 + v14 Phi { incoming=[b0:v9, b2:v45], kind=I64 } -> x2 + v15 Phi { incoming=[b0:v7, b2:v47], kind=I64 } -> x8 + v16 Phi { incoming=[b0:v5, b2:v49], kind=I64 } -> x9 + v17 Extend { value=v13, kind=I32 } -> x0 + v18 LoadLocal { off=3, kind=I32 } -> x3 + v19 Binop { op=lt, lhs=v17, rhs=v3 } -> x3 + terminator Bnz { cond=v19, target=b1, fall=b4 } (exit_acc=v19) block 4 start_pc=0 v51 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x0 v52 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x1 @@ -102,19 +102,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 v5 Imm(8) -> x6 v6 Call { target_pc=1, args=[v4, v5], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v7 BinopI { op=eq, lhs=v6, rhs_imm=4285530095 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + terminator Bz { cond=v7, target=b3, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v8 Imm(0) -> x1 v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) + terminator Jmp(b2) (exit_acc=v8) block 2 start_pc=0 - v10 Imm(1) -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v10) - block 3 start_pc=0 - v12 Phi { incoming=[b1:v8, b2:v10], kind=I64 } -> x1 + v12 Phi { incoming=[b1:v8, b3:v10], kind=I64 } -> x1 v13 LoadLocal { off=-7, kind=I64 } -> x0 terminator Return(v12) (exit_acc=v12) + block 3 start_pc=0 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_phi_narrow_param_return.ssa b/tests/snapshots/ssa/inline_phi_narrow_param_return.ssa index fea4962b3..765d07b3e 100644 --- a/tests/snapshots/ssa/inline_phi_narrow_param_return.ssa +++ b/tests/snapshots/ssa/inline_phi_narrow_param_return.ssa @@ -20,29 +20,29 @@ fn ent_pc=1 n_params=1 variadic=false locals=3 v4 Imm(0) -> x0 v5 Imm(0) -> x1 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 + v15 LoadLocal { off=-1, kind=I64 } -> x6 + v16 BinopI { op=mul, lhs=v8, rhs_imm=1000003 } -> x2 + v17 Extend { value=v7, kind=I32 } -> x6 + v18 Binop { op=add, lhs=v16, rhs=v7 } -> x2 + v19 Extend { value=v18, kind=I32 } -> x2 + v20 Imm(0) -> x6 + v21 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x2 + v22 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v12 Extend { value=v7, kind=I32 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v14 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 v7 Phi { incoming=[b0:v5, b2:v13], kind=I64 } -> x1 v8 Phi { incoming=[b0:v3, b2:v21], kind=I64 } -> x2 v9 Extend { value=v7, kind=I32 } -> x0 v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v1 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 Extend { value=v7, kind=I32 } -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 - v14 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v13) - block 3 start_pc=0 - v15 LoadLocal { off=-1, kind=I64 } -> x0 - v16 BinopI { op=mul, lhs=v8, rhs_imm=1000003 } -> x0 - v17 Extend { value=v7, kind=I32 } -> x2 - v18 Binop { op=add, lhs=v16, rhs=v7 } -> x0 - v19 Extend { value=v18, kind=I32 } -> x0 - v20 Imm(0) -> x2 - v21 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x2 - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v21) + v11 Binop { op=lt, lhs=v9, rhs=v1 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v23 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v8) (exit_acc=v8) @@ -55,19 +55,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=2 v1 Imm(50) -> x7 v2 Call { target_pc=1, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v3 BinopI { op=eq, lhs=v2, rhs_imm=-1193861050 } -> x0 - terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + terminator Bz { cond=v3, target=b3, fall=b1 } (exit_acc=v3) block 1 start_pc=0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v4) + terminator Jmp(b2) (exit_acc=v4) block 2 start_pc=0 - v6 Imm(1) -> x1 - v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) - block 3 start_pc=0 - v8 Phi { incoming=[b1:v4, b2:v6], kind=I64 } -> x1 + v8 Phi { incoming=[b1:v4, b3:v6], kind=I64 } -> x1 v9 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v8) (exit_acc=v8) + block 3 start_pc=0 + v6 Imm(1) -> x1 + v7 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_struct_param_mutated.ssa b/tests/snapshots/ssa/inline_struct_param_mutated.ssa index fb5cf367f..fe9721cd9 100644 --- a/tests/snapshots/ssa/inline_struct_param_mutated.ssa +++ b/tests/snapshots/ssa/inline_struct_param_mutated.ssa @@ -30,19 +30,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v10 Load { addr=v9, disp=0, kind=I64 } -> x1 v11 Binop { op=add, lhs=v8, rhs=v10 } -> x0 v12 BinopI { op=eq, lhs=v11, rhs_imm=105005 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + terminator Bz { cond=v12, target=b3, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v13) + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Imm(1) -> x1 - v16 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v15) - block 3 start_pc=0 - v17 Phi { incoming=[b1:v13, b2:v15], kind=I64 } -> x1 + v17 Phi { incoming=[b1:v13, b3:v15], kind=I64 } -> x1 v18 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v17) (exit_acc=v17) + block 3 start_pc=0 + v15 Imm(1) -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_struct_return_escape.ssa b/tests/snapshots/ssa/inline_struct_return_escape.ssa index cc7aac0a6..8b3441881 100644 --- a/tests/snapshots/ssa/inline_struct_return_escape.ssa +++ b/tests/snapshots/ssa/inline_struct_return_escape.ssa @@ -46,19 +46,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 block 2 start_pc=0 v16 Phi { incoming=[b6:v11, b1:v14], kind=I64 } -> x1 v17 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + terminator Bz { cond=v16, target=b5, fall=b3 } (exit_acc=v16) block 3 start_pc=0 v18 Imm(0) -> x1 v19 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v18) + terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v20 Imm(1) -> x1 - v21 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v20) - block 5 start_pc=0 - v22 Phi { incoming=[b3:v18, b4:v20], kind=I64 } -> x1 + v22 Phi { incoming=[b3:v18, b5:v20], kind=I64 } -> x1 v23 LoadLocal { off=-8, kind=I64 } -> x0 terminator Return(v22) (exit_acc=v22) + block 5 start_pc=0 + v20 Imm(1) -> x1 + v21 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v20) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/inline_struct_return_reg.ssa b/tests/snapshots/ssa/inline_struct_return_reg.ssa index f3f598738..7c86704b5 100644 --- a/tests/snapshots/ssa/inline_struct_return_reg.ssa +++ b/tests/snapshots/ssa/inline_struct_return_reg.ssa @@ -31,89 +31,124 @@ fn ent_pc=2 n_params=0 variadic=false locals=18 v3 Mcpy { dst=v1, src=v2, size=32 } -> x0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 - v7 Extend { value=v6, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=4 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) - block 2 start_pc=0 - v9 Extend { value=v6, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) - block 3 start_pc=0 - v12 LocalAddr(-4) -> x0 - v13 Extend { value=v6, kind=I32 } -> x2 - v14 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x6 + v12 LocalAddr(-4) -> x2 + v13 Extend { value=v6, kind=I32 } -> x6 + v14 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x6 v15 Binop { op=add, lhs=v12, rhs=v14 } -> x6 v16 LocalAddr(-8) -> x6 v17 Extend { value=v6, kind=I32 } -> x7 - v18 BinopI { op=shl, lhs=v17, rhs_imm=3 } -> x8 - v19 Binop { op=add, lhs=v16, rhs=v18 } -> x8 - v20 LoadIndexed { base=v16, index=v17, scale=8, kind=I64 } -> x6 + v18 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x7 + v19 Binop { op=add, lhs=v16, rhs=v18 } -> x7 + v20 LoadIndexed { base=v16, index=v7, scale=8, kind=I64 } -> x6 v21 Imm(0) -> x7 v22 LocalAddr(-16) -> x7 v23 Imm(0) -> x7 v24 LocalAddr(-16) -> x7 v25 LocalAddr(-16) -> x7 - v26 StoreIndexed { base=v12, index=v13, scale=8, value=v20, kind=I64 } -> - + v26 StoreIndexed { base=v12, index=v7, scale=8, value=v20, kind=I64 } -> - terminator Jmp(b2) (exit_acc=v20) + block 2 start_pc=0 + v9 Extend { value=v6, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v10) + block 3 start_pc=0 + v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 + v7 Extend { value=v6, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=4 } -> x2 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) block 4 start_pc=0 - v27 Imm(0) -> x1 - v28 Imm(0) -> x0 - v29 Imm(0) -> x0 + v27 Imm(0) -> x0 + v28 Imm(0) -> x1 + v29 Imm(0) -> x1 terminator Jmp(b5) (exit_acc=v27) block 5 start_pc=0 - v30 Phi { incoming=[b4:v27, b6:v35], kind=I64 } -> x1 - v31 Phi { incoming=[b4:v27, b6:v43], kind=I64 } -> x0 - v32 Extend { value=v30, kind=I32 } -> x2 - v33 BinopI { op=lt, lhs=v32, rhs_imm=4 } -> x2 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) + v30 Imm(0) -> x0 + v31 Imm(1) -> x0 + v32 LoadLocal { off=-11, kind=I64 } -> x0 + v33 LocalAddr(-4) -> x0 + v34 Imm(0) -> x1 + v35 Imm(0) -> x1 + v36 BinopI { op=add, lhs=v33, rhs_imm=0 } -> x0 + v37 Load { addr=v36, disp=0, kind=I64 } -> x0 + v38 BinopI { op=add, lhs=v37, rhs_imm=0 } -> x0 + v39 Imm(0) -> x1 + v40 Imm(0) -> x1 + v41 Imm(1) -> x1 + v42 Imm(0) -> x1 + v43 Imm(1) -> x1 + v44 Imm(1) -> x1 + v45 LoadLocal { off=-11, kind=I64 } -> x1 + v46 LocalAddr(-4) -> x1 + v47 Imm(1) -> x2 + v48 Imm(8) -> x2 + v49 BinopI { op=add, lhs=v46, rhs_imm=8 } -> x2 + v50 Load { addr=v46, disp=8, kind=I64 } -> x1 + v51 Binop { op=add, lhs=v38, rhs=v50 } -> x0 + v52 Imm(0) -> x1 + v53 Imm(1) -> x1 + v54 Imm(2) -> x1 + v55 Imm(0) -> x1 + v56 Imm(2) -> x1 + v57 Imm(1) -> x1 + v58 LoadLocal { off=-11, kind=I64 } -> x1 + v59 LocalAddr(-4) -> x1 + v60 Imm(2) -> x2 + v61 Imm(16) -> x2 + v62 BinopI { op=add, lhs=v59, rhs_imm=16 } -> x2 + v63 Load { addr=v59, disp=16, kind=I64 } -> x1 + v64 Binop { op=add, lhs=v51, rhs=v63 } -> x0 + v65 Imm(0) -> x1 + v66 Imm(2) -> x1 + v67 Imm(3) -> x1 + v68 Imm(0) -> x1 + v69 Imm(3) -> x1 + v70 Imm(1) -> x1 + v71 LoadLocal { off=-11, kind=I64 } -> x1 + v72 LocalAddr(-4) -> x1 + v73 Imm(3) -> x2 + v74 Imm(24) -> x2 + v75 BinopI { op=add, lhs=v72, rhs_imm=24 } -> x2 + v76 Load { addr=v72, disp=24, kind=I64 } -> x1 + v77 Binop { op=add, lhs=v64, rhs=v76 } -> x0 + v78 Imm(0) -> x1 + v79 Imm(3) -> x1 + v80 Imm(4) -> x1 + v81 Imm(0) -> x1 + v82 Imm(4) -> x1 + v83 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v83) block 6 start_pc=0 - v34 Extend { value=v30, kind=I32 } -> x1 - v35 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x1 - v36 Imm(0) -> x2 - terminator Jmp(b5) (exit_acc=v35) + v84 Imm(85) -> x1 + v85 Imm(0) -> x1 + v86 LocalAddr(-17) -> x1 + v87 Imm(0) -> x1 + v88 LocalAddr(-17) -> x1 + v89 LocalAddr(-17) -> x1 + v90 LocalAddr(-13) -> x1 + v91 Imm(0) -> x1 + v92 LoadLocal { off=-11, kind=I64 } -> x1 + v93 LocalAddr(-13) -> x1 + v94 Load { addr=v93, disp=0, kind=I64 } -> x1 + v95 BinopI { op=add, lhs=v77, rhs_imm=85 } -> x0 + v96 Imm(0) -> x1 + v97 LoadLocal { off=-11, kind=I64 } -> x1 + v98 BinopI { op=eq, lhs=v95, rhs_imm=41045 } -> x0 + terminator Bz { cond=v98, target=b9, fall=b7 } (exit_acc=v98) block 7 start_pc=0 - v37 LoadLocal { off=-11, kind=I64 } -> x2 - v38 LocalAddr(-4) -> x2 - v39 Extend { value=v30, kind=I32 } -> x6 - v40 BinopI { op=shl, lhs=v39, rhs_imm=3 } -> x7 - v41 Binop { op=add, lhs=v38, rhs=v40 } -> x7 - v42 LoadIndexed { base=v38, index=v39, scale=8, kind=I64 } -> x2 - v43 Binop { op=add, lhs=v31, rhs=v42 } -> x0 - v44 Imm(0) -> x2 - terminator Jmp(b6) (exit_acc=v43) + v99 Imm(0) -> x1 + v100 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v99) block 8 start_pc=0 - v45 Imm(85) -> x1 - v46 Imm(0) -> x2 - v47 LocalAddr(-17) -> x2 - v48 Imm(0) -> x2 - v49 LocalAddr(-17) -> x2 - v50 LocalAddr(-17) -> x2 - v51 LocalAddr(-13) -> x2 - v52 Imm(0) -> x2 - v53 LoadLocal { off=-11, kind=I64 } -> x2 - v54 LocalAddr(-13) -> x2 - v55 Load { addr=v54, disp=0, kind=I64 } -> x2 - v56 Binop { op=add, lhs=v31, rhs=v45 } -> x0 - v57 Imm(0) -> x1 - v58 LoadLocal { off=-11, kind=I64 } -> x1 - v59 BinopI { op=eq, lhs=v56, rhs_imm=41045 } -> x0 - terminator Bz { cond=v59, target=b10, fall=b9 } (exit_acc=v59) + v103 Phi { incoming=[b7:v99, b9:v101], kind=I64 } -> x1 + v104 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Return(v103) (exit_acc=v103) block 9 start_pc=0 - v60 Imm(0) -> x1 - v61 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v60) - block 10 start_pc=0 - v62 Imm(1) -> x1 - v63 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v62) - block 11 start_pc=0 - v64 Phi { incoming=[b9:v60, b10:v62], kind=I64 } -> x1 - v65 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Return(v64) (exit_acc=v64) + v101 Imm(1) -> x1 + v102 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v101) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inline_two_word_struct_return.ssa b/tests/snapshots/ssa/inline_two_word_struct_return.ssa index 1c5717421..8eb9354fc 100644 --- a/tests/snapshots/ssa/inline_two_word_struct_return.ssa +++ b/tests/snapshots/ssa/inline_two_word_struct_return.ssa @@ -40,116 +40,252 @@ fn ent_pc=2 n_params=0 variadic=false locals=32 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x7 + v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x0 - v5 Extend { value=v4, kind=I32 } -> x1 - v6 BinopI { op=lt, lhs=v5, rhs_imm=8 } -> x1 - terminator Bz { cond=v6, target=b4, fall=b3 } (exit_acc=v6) - block 2 start_pc=0 - v7 Extend { value=v4, kind=I32 } -> x0 - v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 - v9 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v8) - block 3 start_pc=0 - v10 LocalAddr(-16) -> x1 - v11 Extend { value=v4, kind=I32 } -> x2 - v12 BinopI { op=shl, lhs=v11, rhs_imm=4 } -> x6 - v13 Binop { op=add, lhs=v10, rhs=v12 } -> x1 - v14 BinopI { op=mul, lhs=v11, rhs_imm=10 } -> x2 - v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x6 - v16 Extend { value=v14, kind=I32 } -> x6 - v17 Extend { value=v16, kind=I32 } -> x6 - v18 Imm(0) -> x6 - v19 LocalAddr(-29) -> x6 + v10 LocalAddr(-16) -> x2 + v11 Extend { value=v4, kind=I32 } -> x6 + v12 BinopI { op=shl, lhs=v5, rhs_imm=4 } -> x6 + v13 Binop { op=add, lhs=v10, rhs=v12 } -> x2 + v14 BinopI { op=mul, lhs=v5, rhs_imm=10 } -> x6 + v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x7 + v16 Extend { value=v14, kind=I32 } -> x7 + v17 Extend { value=v16, kind=I32 } -> x7 + v18 Imm(0) -> x7 + v19 LocalAddr(-29) -> x7 v20 Store { addr=v19, disp=0, value=v14, kind=I32 } -> - - v21 LocalAddr(-29) -> x2 - v22 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x6 - v23 Imm(1) -> x6 + v21 LocalAddr(-29) -> x6 + v22 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x7 + v23 Imm(1) -> x7 v24 Store { addr=v21, disp=8, value=v23, kind=I64 } -> - - v25 LocalAddr(-29) -> x2 - v26 LocalAddr(-29) -> x2 - v27 Mcpy { dst=v13, src=v26, size=16 } -> x1 + v25 LocalAddr(-29) -> x6 + v26 LocalAddr(-29) -> x6 + v27 Mcpy { dst=v13, src=v26, size=16 } -> x2 terminator Jmp(b2) (exit_acc=v27) + block 2 start_pc=0 + v7 Extend { value=v4, kind=I32 } -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v8) + block 3 start_pc=0 + v4 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x1 + v5 Extend { value=v4, kind=I32 } -> x0 + v6 BinopI { op=lt, lhs=v5, rhs_imm=8 } -> x2 + terminator Bnz { cond=v6, target=b1, fall=b4 } (exit_acc=v6) block 4 start_pc=0 - v28 Imm(0) -> x1 - v29 Imm(0) -> x0 + v28 Imm(0) -> x0 + v29 Imm(0) -> x1 terminator Jmp(b5) (exit_acc=v28) block 5 start_pc=0 - v30 Phi { incoming=[b4:v28, b6:v35], kind=I64 } -> x1 - v31 Phi { incoming=[b4:v1, b6:v50], kind=I64 } -> x7 - v32 Extend { value=v30, kind=I32 } -> x0 - v33 BinopI { op=lt, lhs=v32, rhs_imm=8 } -> x0 - terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) + v30 Imm(0) -> x0 + v31 Imm(1) -> x0 + v32 LoadLocal { off=-17, kind=I64 } -> x0 + v33 LocalAddr(-16) -> x0 + v34 Imm(0) -> x1 + v35 Imm(0) -> x1 + v36 BinopI { op=add, lhs=v33, rhs_imm=0 } -> x0 + v37 Load { addr=v36, disp=0, kind=I32 } -> x0 + v38 LocalAddr(-16) -> x1 + v39 Imm(0) -> x2 + v40 Imm(0) -> x2 + v41 BinopI { op=add, lhs=v38, rhs_imm=0 } -> x1 + v42 BinopI { op=add, lhs=v41, rhs_imm=8 } -> x2 + v43 Load { addr=v41, disp=8, kind=I64 } -> x1 + v44 Binop { op=add, lhs=v37, rhs=v43 } -> x0 + v45 BinopI { op=add, lhs=v44, rhs_imm=0 } -> x0 + v46 Imm(0) -> x1 + v47 Imm(0) -> x1 + v48 Imm(1) -> x1 + v49 Imm(0) -> x1 + v50 Imm(1) -> x1 + v51 Imm(1) -> x1 + v52 LoadLocal { off=-17, kind=I64 } -> x1 + v53 LocalAddr(-16) -> x1 + v54 Imm(1) -> x2 + v55 Imm(16) -> x2 + v56 BinopI { op=add, lhs=v53, rhs_imm=16 } -> x2 + v57 Load { addr=v53, disp=16, kind=I32 } -> x1 + v58 LocalAddr(-16) -> x2 + v59 Imm(1) -> x6 + v60 Imm(16) -> x6 + v61 BinopI { op=add, lhs=v58, rhs_imm=16 } -> x2 + v62 BinopI { op=add, lhs=v61, rhs_imm=8 } -> x6 + v63 Load { addr=v61, disp=8, kind=I64 } -> x2 + v64 Binop { op=add, lhs=v57, rhs=v63 } -> x1 + v65 Binop { op=add, lhs=v45, rhs=v64 } -> x0 + v66 Imm(0) -> x1 + v67 Imm(1) -> x1 + v68 Imm(2) -> x1 + v69 Imm(0) -> x1 + v70 Imm(2) -> x1 + v71 Imm(1) -> x1 + v72 LoadLocal { off=-17, kind=I64 } -> x1 + v73 LocalAddr(-16) -> x1 + v74 Imm(2) -> x2 + v75 Imm(32) -> x2 + v76 BinopI { op=add, lhs=v73, rhs_imm=32 } -> x2 + v77 Load { addr=v73, disp=32, kind=I32 } -> x1 + v78 LocalAddr(-16) -> x2 + v79 Imm(2) -> x6 + v80 Imm(32) -> x6 + v81 BinopI { op=add, lhs=v78, rhs_imm=32 } -> x2 + v82 BinopI { op=add, lhs=v81, rhs_imm=8 } -> x6 + v83 Load { addr=v81, disp=8, kind=I64 } -> x2 + v84 Binop { op=add, lhs=v77, rhs=v83 } -> x1 + v85 Binop { op=add, lhs=v65, rhs=v84 } -> x0 + v86 Imm(0) -> x1 + v87 Imm(2) -> x1 + v88 Imm(3) -> x1 + v89 Imm(0) -> x1 + v90 Imm(3) -> x1 + v91 Imm(1) -> x1 + v92 LoadLocal { off=-17, kind=I64 } -> x1 + v93 LocalAddr(-16) -> x1 + v94 Imm(3) -> x2 + v95 Imm(48) -> x2 + v96 BinopI { op=add, lhs=v93, rhs_imm=48 } -> x2 + v97 Load { addr=v93, disp=48, kind=I32 } -> x1 + v98 LocalAddr(-16) -> x2 + v99 Imm(3) -> x6 + v100 Imm(48) -> x6 + v101 BinopI { op=add, lhs=v98, rhs_imm=48 } -> x2 + v102 BinopI { op=add, lhs=v101, rhs_imm=8 } -> x6 + v103 Load { addr=v101, disp=8, kind=I64 } -> x2 + v104 Binop { op=add, lhs=v97, rhs=v103 } -> x1 + v105 Binop { op=add, lhs=v85, rhs=v104 } -> x0 + v106 Imm(0) -> x1 + v107 Imm(3) -> x1 + v108 Imm(4) -> x1 + v109 Imm(0) -> x1 + v110 Imm(4) -> x1 + v111 Imm(1) -> x1 + v112 LoadLocal { off=-17, kind=I64 } -> x1 + v113 LocalAddr(-16) -> x1 + v114 Imm(4) -> x2 + v115 Imm(64) -> x2 + v116 BinopI { op=add, lhs=v113, rhs_imm=64 } -> x2 + v117 Load { addr=v113, disp=64, kind=I32 } -> x1 + v118 LocalAddr(-16) -> x2 + v119 Imm(4) -> x6 + v120 Imm(64) -> x6 + v121 BinopI { op=add, lhs=v118, rhs_imm=64 } -> x2 + v122 BinopI { op=add, lhs=v121, rhs_imm=8 } -> x6 + v123 Load { addr=v121, disp=8, kind=I64 } -> x2 + v124 Binop { op=add, lhs=v117, rhs=v123 } -> x1 + v125 Binop { op=add, lhs=v105, rhs=v124 } -> x0 + v126 Imm(0) -> x1 + v127 Imm(4) -> x1 + v128 Imm(5) -> x1 + v129 Imm(0) -> x1 + v130 Imm(5) -> x1 + v131 Imm(1) -> x1 + v132 LoadLocal { off=-17, kind=I64 } -> x1 + v133 LocalAddr(-16) -> x1 + v134 Imm(5) -> x2 + v135 Imm(80) -> x2 + v136 BinopI { op=add, lhs=v133, rhs_imm=80 } -> x2 + v137 Load { addr=v133, disp=80, kind=I32 } -> x1 + v138 LocalAddr(-16) -> x2 + v139 Imm(5) -> x6 + v140 Imm(80) -> x6 + v141 BinopI { op=add, lhs=v138, rhs_imm=80 } -> x2 + v142 BinopI { op=add, lhs=v141, rhs_imm=8 } -> x6 + v143 Load { addr=v141, disp=8, kind=I64 } -> x2 + v144 Binop { op=add, lhs=v137, rhs=v143 } -> x1 + v145 Binop { op=add, lhs=v125, rhs=v144 } -> x0 + v146 Imm(0) -> x1 + v147 Imm(5) -> x1 + v148 Imm(6) -> x1 + v149 Imm(0) -> x1 + v150 Imm(6) -> x1 + v151 Imm(1) -> x1 + v152 LoadLocal { off=-17, kind=I64 } -> x1 + v153 LocalAddr(-16) -> x1 + v154 Imm(6) -> x2 + v155 Imm(96) -> x2 + v156 BinopI { op=add, lhs=v153, rhs_imm=96 } -> x2 + v157 Load { addr=v153, disp=96, kind=I32 } -> x1 + v158 LocalAddr(-16) -> x2 + v159 Imm(6) -> x6 + v160 Imm(96) -> x6 + v161 BinopI { op=add, lhs=v158, rhs_imm=96 } -> x2 + v162 BinopI { op=add, lhs=v161, rhs_imm=8 } -> x6 + v163 Load { addr=v161, disp=8, kind=I64 } -> x2 + v164 Binop { op=add, lhs=v157, rhs=v163 } -> x1 + v165 Binop { op=add, lhs=v145, rhs=v164 } -> x0 + v166 Imm(0) -> x1 + v167 Imm(6) -> x1 + v168 Imm(7) -> x1 + v169 Imm(0) -> x1 + v170 Imm(7) -> x1 + v171 Imm(1) -> x1 + v172 LoadLocal { off=-17, kind=I64 } -> x1 + v173 LocalAddr(-16) -> x1 + v174 Imm(7) -> x2 + v175 Imm(112) -> x2 + v176 BinopI { op=add, lhs=v173, rhs_imm=112 } -> x2 + v177 Load { addr=v173, disp=112, kind=I32 } -> x1 + v178 LocalAddr(-16) -> x2 + v179 Imm(7) -> x6 + v180 Imm(112) -> x6 + v181 BinopI { op=add, lhs=v178, rhs_imm=112 } -> x2 + v182 BinopI { op=add, lhs=v181, rhs_imm=8 } -> x6 + v183 Load { addr=v181, disp=8, kind=I64 } -> x2 + v184 Binop { op=add, lhs=v177, rhs=v183 } -> x1 + v185 Binop { op=add, lhs=v165, rhs=v184 } -> x0 + v186 Imm(0) -> x1 + v187 Imm(7) -> x1 + v188 Imm(8) -> x1 + v189 Imm(0) -> x1 + v190 Imm(8) -> x1 + v191 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v191) block 6 start_pc=0 - v34 Extend { value=v30, kind=I32 } -> x0 - v35 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x1 - v36 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v35) + v192 Imm(43690) -> x1 + v193 Imm(48059) -> x2 + v194 Imm(0) -> x6 + v195 Imm(0) -> x6 + v196 LocalAddr(-31) -> x6 + v197 Store { addr=v196, disp=0, value=v192, kind=I64 } -> - + v198 LocalAddr(-31) -> x1 + v199 BinopI { op=add, lhs=v198, rhs_imm=8 } -> x6 + v200 Store { addr=v198, disp=8, value=v193, kind=I64 } -> - + v201 LocalAddr(-31) -> x1 + v202 LocalAddr(-31) -> x1 + v203 LocalAddr(-23) -> x2 + v204 Mcpy { dst=v203, src=v202, size=16 } -> x1 + v205 LoadLocal { off=-17, kind=I64 } -> x1 + v206 LocalAddr(-23) -> x1 + v207 Load { addr=v206, disp=0, kind=I64 } -> x1 + v208 LocalAddr(-23) -> x2 + v209 BinopI { op=add, lhs=v208, rhs_imm=8 } -> x6 + v210 Load { addr=v208, disp=8, kind=I64 } -> x2 + v211 Binop { op=add, lhs=v207, rhs=v210 } -> x1 + v212 Binop { op=add, lhs=v185, rhs=v211 } -> x0 + v213 Imm(0) -> x1 + v214 LoadLocal { off=-17, kind=I64 } -> x1 + v215 Imm(288) -> x1 + v216 Imm(1236950581248) -> x1 + v217 Imm(43978) -> x1 + v218 Imm(188884071743488) -> x1 + v219 Imm(92037) -> x1 + v220 Imm(395295905021952) -> x1 + v221 BinopI { op=eq, lhs=v212, rhs_imm=92037 } -> x0 + terminator Bz { cond=v221, target=b9, fall=b7 } (exit_acc=v221) block 7 start_pc=0 - v37 LoadLocal { off=-17, kind=I64 } -> x0 - v38 LocalAddr(-16) -> x0 - v39 Extend { value=v30, kind=I32 } -> x2 - v40 BinopI { op=shl, lhs=v39, rhs_imm=4 } -> x2 - v41 Binop { op=add, lhs=v38, rhs=v40 } -> x0 - v42 Load { addr=v41, disp=0, kind=I32 } -> x0 - v43 LocalAddr(-16) -> x2 - v44 Extend { value=v30, kind=I32 } -> x6 - v45 BinopI { op=shl, lhs=v44, rhs_imm=4 } -> x6 - v46 Binop { op=add, lhs=v43, rhs=v45 } -> x2 - v47 BinopI { op=add, lhs=v46, rhs_imm=8 } -> x6 - v48 Load { addr=v46, disp=8, kind=I64 } -> x2 - v49 Binop { op=add, lhs=v42, rhs=v48 } -> x0 - v50 Binop { op=add, lhs=v31, rhs=v49 } -> x7 - v51 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v50) + v222 Imm(0) -> x1 + v223 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v222) block 8 start_pc=0 - v52 Imm(43690) -> x0 - v53 Imm(48059) -> x1 - v54 Imm(0) -> x2 - v55 Imm(0) -> x2 - v56 LocalAddr(-31) -> x2 - v57 Store { addr=v56, disp=0, value=v52, kind=I64 } -> - - v58 LocalAddr(-31) -> x0 - v59 BinopI { op=add, lhs=v58, rhs_imm=8 } -> x2 - v60 Store { addr=v58, disp=8, value=v53, kind=I64 } -> - - v61 LocalAddr(-31) -> x0 - v62 LocalAddr(-31) -> x0 - v63 LocalAddr(-23) -> x1 - v64 Mcpy { dst=v63, src=v62, size=16 } -> x0 - v65 LoadLocal { off=-17, kind=I64 } -> x0 - v66 LocalAddr(-23) -> x0 - v67 Load { addr=v66, disp=0, kind=I64 } -> x0 - v68 LocalAddr(-23) -> x1 - v69 BinopI { op=add, lhs=v68, rhs_imm=8 } -> x2 - v70 Load { addr=v68, disp=8, kind=I64 } -> x1 - v71 Binop { op=add, lhs=v67, rhs=v70 } -> x0 - v72 Binop { op=add, lhs=v31, rhs=v71 } -> x0 - v73 Imm(0) -> x1 - v74 LoadLocal { off=-17, kind=I64 } -> x1 - v75 Imm(288) -> x1 - v76 Imm(1236950581248) -> x1 - v77 Imm(43978) -> x1 - v78 Imm(188884071743488) -> x1 - v79 Imm(92037) -> x1 - v80 Imm(395295905021952) -> x1 - v81 BinopI { op=eq, lhs=v72, rhs_imm=92037 } -> x0 - terminator Bz { cond=v81, target=b10, fall=b9 } (exit_acc=v81) + v226 Phi { incoming=[b7:v222, b9:v224], kind=I64 } -> x1 + v227 LoadLocal { off=-32, kind=I64 } -> x0 + terminator Return(v226) (exit_acc=v226) block 9 start_pc=0 - v82 Imm(0) -> x1 - v83 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v82) - block 10 start_pc=0 - v84 Imm(1) -> x1 - v85 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v84) - block 11 start_pc=0 - v86 Phi { incoming=[b9:v82, b10:v84], kind=I64 } -> x1 - v87 LoadLocal { off=-32, kind=I64 } -> x0 - terminator Return(v86) (exit_acc=v86) + v224 Imm(1) -> x1 + v225 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v224) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/int32_sign_extend_elision.ssa b/tests/snapshots/ssa/int32_sign_extend_elision.ssa index 8a2cb715e..eb95a432b 100644 --- a/tests/snapshots/ssa/int32_sign_extend_elision.ssa +++ b/tests/snapshots/ssa/int32_sign_extend_elision.ssa @@ -109,116 +109,98 @@ fn ent_pc=5 n_params=0 variadic=false locals=8 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2147483647) -> x0 - v2 Imm(0) -> x1 - v3 Imm(-2147483648) -> x1 - v4 Imm(-9223372036854775808) -> x2 - v5 Imm(0) -> x2 - v6 LoadLocal { off=-1, kind=I32 } -> x2 - v7 Imm(1) -> x2 - v8 LoadLocal { off=-2, kind=I32 } -> x6 - v9 Imm(-1) -> x6 - v10 Extend { value=v1, kind=I32 } -> x7 - v11 Imm(0) -> x7 - v12 Extend { value=v7, kind=I32 } -> x7 - v13 Imm(0) -> x7 - v14 Extend { value=v3, kind=I32 } -> x7 - v15 Imm(0) -> x7 - v16 Extend { value=v9, kind=I32 } -> x7 - v17 Imm(0) -> x7 - v18 Binop { op=add, lhs=v1, rhs=v7 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x2 - v20 Extend { value=v18, kind=I32 } -> x2 - v21 Binop { op=add, lhs=v18, rhs=v3 } -> x0 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x2 - v23 Extend { value=v21, kind=I32 } -> x2 - v24 Binop { op=add, lhs=v21, rhs=v9 } -> x0 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x2 - v26 Extend { value=v24, kind=I32 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=-1 } -> x0 - terminator Bz { cond=v27, target=b2, fall=b1 } (exit_acc=v27) + v2 Imm(0) -> x0 + v3 Imm(-2147483648) -> x0 + v4 Imm(-9223372036854775808) -> x0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-1, kind=I32 } -> x0 + v7 Imm(1) -> x0 + v8 LoadLocal { off=-2, kind=I32 } -> x0 + v9 Imm(-1) -> x0 + v10 Imm(2147483647) -> x0 + v11 Imm(0) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(-2147483648) -> x0 + v15 Imm(0) -> x0 + v16 Imm(-1) -> x0 + v17 Imm(0) -> x0 + v18 Imm(2147483648) -> x0 + v19 Imm(-9223372036854775808) -> x0 + v20 Imm(-2147483648) -> x0 + v21 Imm(-4294967296) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + v24 Imm(-1) -> x0 + v25 Imm(-4294967296) -> x0 + v26 Imm(-1) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v27) block 1 start_pc=0 - v28 Imm(1) -> x0 - terminator Return(v28) (exit_acc=v28) - block 2 start_pc=0 v29 LoadLocal { off=-2, kind=I32 } -> x0 v30 Imm(-1) -> x0 - v31 Extend { value=v3, kind=I32 } -> x2 - v32 Imm(0) -> x2 - v33 Extend { value=v30, kind=I32 } -> x2 - v34 Imm(0) -> x2 - v35 Binop { op=add, lhs=v3, rhs=v30 } -> x0 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x2 - v37 Extend { value=v35, kind=I32 } -> x0 - v38 Imm(0) -> x2 - v39 BinopI { op=ne, lhs=v37, rhs_imm=2147483647 } -> x0 - terminator Bz { cond=v39, target=b4, fall=b3 } (exit_acc=v39) - block 3 start_pc=0 - v40 Imm(2) -> x0 - terminator Return(v40) (exit_acc=v40) - block 4 start_pc=0 + v31 Imm(-2147483648) -> x0 + v32 Imm(0) -> x0 + v33 Imm(-1) -> x0 + v34 Imm(0) -> x0 + v35 Imm(-2147483649) -> x0 + v36 Imm(9223372032559808512) -> x0 + v37 Imm(2147483647) -> x0 + v38 Imm(0) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v39) + block 2 start_pc=0 v41 Imm(2000000000) -> x0 - v42 Extend { value=v41, kind=I32 } -> x2 - v43 Imm(0) -> x2 - v44 Extend { value=v41, kind=I32 } -> x2 - v45 Imm(0) -> x2 - v46 Binop { op=add, lhs=v41, rhs=v41 } -> x0 - v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x2 - v48 Extend { value=v46, kind=I32 } -> x0 - v49 Imm(0) -> x2 - v50 BinopI { op=ne, lhs=v48, rhs_imm=-294967296 } -> x0 - terminator Bz { cond=v50, target=b6, fall=b5 } (exit_acc=v50) - block 5 start_pc=0 - v51 Imm(3) -> x0 - terminator Return(v51) (exit_acc=v51) - block 6 start_pc=0 + v42 Imm(2000000000) -> x0 + v43 Imm(0) -> x0 + v44 Imm(2000000000) -> x0 + v45 Imm(0) -> x0 + v46 Imm(4000000000) -> x0 + v47 Imm(-1266874889709551616) -> x0 + v48 Imm(-294967296) -> x0 + v49 Imm(0) -> x0 + v50 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v50) + block 3 start_pc=0 v52 Imm(-3) -> x0 - v53 Imm(4) -> x2 - v54 Extend { value=v52, kind=I32 } -> x6 - v55 Imm(0) -> x6 - v56 Extend { value=v53, kind=I32 } -> x6 - v57 Imm(0) -> x6 - v58 Binop { op=mul, lhs=v52, rhs=v53 } -> x0 - v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x2 - v60 Extend { value=v58, kind=I32 } -> x0 - v61 Imm(0) -> x2 - v62 BinopI { op=lt, lhs=v60, rhs_imm=0 } -> x0 - v63 BinopI { op=ne, lhs=v62, rhs_imm=1 } -> x0 - terminator Bz { cond=v63, target=b8, fall=b7 } (exit_acc=v63) - block 7 start_pc=0 - v64 Imm(4) -> x0 - terminator Return(v64) (exit_acc=v64) - block 8 start_pc=0 + v53 Imm(4) -> x0 + v54 Imm(-3) -> x0 + v55 Imm(0) -> x0 + v56 Imm(4) -> x0 + v57 Imm(0) -> x0 + v58 Imm(-12) -> x0 + v59 Imm(-51539607552) -> x0 + v60 Imm(-12) -> x0 + v61 Imm(0) -> x0 + v62 Imm(1) -> x0 + v63 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v63) + block 4 start_pc=0 v65 LoadLocal { off=-2, kind=I32 } -> x0 v66 Imm(2) -> x0 - v67 Extend { value=v3, kind=I32 } -> x2 - v68 Imm(0) -> x2 - v69 Extend { value=v66, kind=I32 } -> x2 - v70 Imm(0) -> x2 - v71 Binop { op=mul, lhs=v3, rhs=v66 } -> x0 - v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x1 - v73 Extend { value=v71, kind=I32 } -> x0 - v74 Imm(0) -> x1 - v75 BinopI { op=lt, lhs=v73, rhs_imm=0 } -> x0 - v76 BinopI { op=ne, lhs=v75, rhs_imm=0 } -> x0 - terminator Bz { cond=v76, target=b10, fall=b9 } (exit_acc=v76) - block 9 start_pc=0 - v77 Imm(5) -> x0 - terminator Return(v77) (exit_acc=v77) - block 10 start_pc=0 + v67 Imm(-2147483648) -> x0 + v68 Imm(0) -> x0 + v69 Imm(2) -> x0 + v70 Imm(0) -> x0 + v71 Imm(-4294967296) -> x0 + v72 Imm(0) -> x0 + v73 Imm(0) -> x0 + v74 Imm(0) -> x0 + v75 Imm(0) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v76) + block 5 start_pc=0 v78 Imm(4294967295) -> x0 - v79 Imm(2) -> x1 - v80 Imm(0) -> x2 - v81 Imm(0) -> x2 - v82 BinopI { op=and, lhs=v78, rhs_imm=4294967295 } -> x0 - v83 BinopI { op=and, lhs=v79, rhs_imm=4294967295 } -> x1 - v84 Binop { op=add, lhs=v82, rhs=v83 } -> x0 - v85 BinopI { op=and, lhs=v84, rhs_imm=4294967295 } -> x0 - v86 BinopI { op=ne, lhs=v85, rhs_imm=1 } -> x0 - terminator Bz { cond=v86, target=b12, fall=b11 } (exit_acc=v86) - block 11 start_pc=0 - v87 Imm(6) -> x0 - terminator Return(v87) (exit_acc=v87) - block 12 start_pc=0 + v79 Imm(2) -> x0 + v80 Imm(0) -> x0 + v81 Imm(0) -> x0 + v82 Imm(4294967295) -> x0 + v83 Imm(2) -> x0 + v84 Imm(4294967297) -> x0 + v85 Imm(1) -> x0 + v86 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v86) + block 6 start_pc=0 v88 LocalAddr(-5) -> x0 v89 ImmData(8) -> x1 v90 Mcpy { dst=v88, src=v89, size=20 } -> x0 @@ -226,26 +208,44 @@ fn ent_pc=5 n_params=0 variadic=false locals=8 v92 Imm(8) -> x1 v93 BinopI { op=add, lhs=v91, rhs_imm=8 } -> x0 v94 Imm(-1) -> x1 - v95 Imm(0) -> x2 - v96 Extend { value=v94, kind=I32 } -> x2 - v97 Imm(0) -> x2 - v98 Extend { value=v94, kind=I32 } -> x2 - v99 Imm(0) -> x2 - v100 Binop { op=add, lhs=v94, rhs=v94 } -> x1 - v101 BinopI { op=shl, lhs=v100, rhs_imm=32 } -> x2 - v102 Extend { value=v100, kind=I32 } -> x1 - v103 Imm(0) -> x2 - v104 BinopI { op=shl, lhs=v102, rhs_imm=2 } -> x2 - v105 Binop { op=add, lhs=v93, rhs=v104 } -> x2 - v106 LoadIndexed { base=v93, index=v102, scale=4, kind=I32 } -> x0 + v95 Imm(0) -> x1 + v96 Imm(-1) -> x1 + v97 Imm(0) -> x1 + v98 Imm(-1) -> x1 + v99 Imm(0) -> x1 + v100 Imm(-2) -> x1 + v101 Imm(-8589934592) -> x1 + v102 Imm(-2) -> x1 + v103 Imm(0) -> x1 + v104 Imm(-8) -> x1 + v105 BinopI { op=add, lhs=v93, rhs_imm=-8 } -> x0 + v106 Load { addr=v105, disp=0, kind=I32 } -> x0 v107 BinopI { op=ne, lhs=v106, rhs_imm=10 } -> x0 - terminator Bz { cond=v107, target=b14, fall=b13 } (exit_acc=v107) - block 13 start_pc=0 + terminator Bz { cond=v107, target=b8, fall=b7 } (exit_acc=v107) + block 7 start_pc=0 v108 Imm(7) -> x0 terminator Return(v108) (exit_acc=v108) - block 14 start_pc=0 + block 8 start_pc=0 v109 Imm(0) -> x0 terminator Return(v109) (exit_acc=v109) + block 9 start_pc=0 + v28 Imm(1) -> x0 + terminator Return(v28) (exit_acc=v28) + block 10 start_pc=0 + v40 Imm(2) -> x0 + terminator Return(v40) (exit_acc=v40) + block 11 start_pc=0 + v51 Imm(3) -> x0 + terminator Return(v51) (exit_acc=v51) + block 12 start_pc=0 + v64 Imm(4) -> x0 + terminator Return(v64) (exit_acc=v64) + block 13 start_pc=0 + v77 Imm(5) -> x0 + terminator Return(v77) (exit_acc=v77) + block 14 start_pc=0 + v87 Imm(6) -> x0 + terminator Return(v87) (exit_acc=v87) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/int_literal_boundary_types.ssa b/tests/snapshots/ssa/int_literal_boundary_types.ssa index 1a5c96b40..0c59a6f03 100644 --- a/tests/snapshots/ssa/int_literal_boundary_types.ssa +++ b/tests/snapshots/ssa/int_literal_boundary_types.ssa @@ -5,98 +5,98 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-2147483649) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 BinopI { op=ne, lhs=v1, rhs_imm=-2147483649 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 Imm(0) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v6) - block 3 start_pc=0 - v8 Imm(0) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v8) - block 4 start_pc=0 - v10 Phi { incoming=[b2:v6, b3:v8], kind=I64 } -> x1 + terminator Jmp(b2) (exit_acc=v6) + block 2 start_pc=0 + v10 Phi { incoming=[b1:v6, b18:v8], kind=I64 } -> x1 v11 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) - block 5 start_pc=0 + terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + block 3 start_pc=0 v12 Imm(2) -> x0 terminator Return(v12) (exit_acc=v12) - block 6 start_pc=0 + block 4 start_pc=0 v13 Imm(-1) -> x0 v14 Imm(2147483648) -> x0 - v15 Imm(4294967295) -> x1 - v16 Binop { op=ult, lhs=v15, rhs=v14 } -> x0 - terminator Bz { cond=v16, target=b8, fall=b7 } (exit_acc=v16) - block 7 start_pc=0 - v17 Imm(3) -> x0 - terminator Return(v17) (exit_acc=v17) - block 8 start_pc=0 + v15 Imm(4294967295) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v16) + block 5 start_pc=0 v18 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v18) - block 9 start_pc=0 - v19 Imm(4) -> x0 - terminator Return(v19) (exit_acc=v19) - block 10 start_pc=0 + terminator Jmp(b6) (exit_acc=v18) + block 6 start_pc=0 v20 Imm(1) -> x0 v21 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v21) - block 11 start_pc=0 - v22 Imm(5) -> x0 - terminator Return(v22) (exit_acc=v22) - block 12 start_pc=0 + terminator Jmp(b7) (exit_acc=v21) + block 7 start_pc=0 v23 Imm(-9223372036854775808) -> x0 v24 Imm(2) -> x0 v25 Imm(4611686018427387904) -> x0 v26 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v26) - block 13 start_pc=0 - v27 Imm(6) -> x0 - terminator Return(v27) (exit_acc=v27) - block 14 start_pc=0 + terminator Jmp(b8) (exit_acc=v26) + block 8 start_pc=0 v28 Imm(0) -> x0 v29 Imm(1) -> x2 v30 Imm(0) -> x1 - terminator Jmp(b15) (exit_acc=v28) - block 15 start_pc=0 + terminator Jmp(b9) (exit_acc=v28) + block 9 start_pc=0 v31 Imm(0) -> x2 v32 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v31) - block 16 start_pc=0 - v33 Phi { incoming=[b14:v29, b15:v31], kind=I64 } -> x2 + terminator Jmp(b10) (exit_acc=v31) + block 10 start_pc=0 + v33 Phi { incoming=[b8:v29, b9:v31], kind=I64 } -> x2 v34 LoadLocal { off=-4, kind=I64 } -> x0 v35 Imm(0) -> x0 - terminator Bnz { cond=v33, target=b23, fall=b17 } (exit_acc=v33) - block 17 start_pc=0 + terminator Bnz { cond=v33, target=b16, fall=b11 } (exit_acc=v33) + block 11 start_pc=0 v36 Imm(0) -> x2 v37 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v36) - block 18 start_pc=0 - v38 Phi { incoming=[b23:v33, b17:v36], kind=I64 } -> x2 + terminator Jmp(b12) (exit_acc=v36) + block 12 start_pc=0 + v38 Phi { incoming=[b16:v33, b11:v36], kind=I64 } -> x2 v39 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v38, target=b20, fall=b19 } (exit_acc=v38) - block 19 start_pc=0 + terminator Bz { cond=v38, target=b14, fall=b13 } (exit_acc=v38) + block 13 start_pc=0 v40 Imm(7) -> x0 terminator Return(v40) (exit_acc=v40) - block 20 start_pc=0 + block 14 start_pc=0 v41 Imm(-1) -> x0 v42 Imm(8) -> x0 - v43 Imm(4294967295) -> x1 - v44 Binop { op=ult, lhs=v43, rhs=v42 } -> x0 - terminator Bz { cond=v44, target=b22, fall=b21 } (exit_acc=v44) - block 21 start_pc=0 - v45 Imm(8) -> x0 - terminator Return(v45) (exit_acc=v45) - block 22 start_pc=0 + v43 Imm(4294967295) -> x0 + v44 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v44) + block 15 start_pc=0 v46 Imm(0) -> x0 terminator Return(v46) (exit_acc=v46) + block 16 start_pc=0 + terminator Jmp(b12) + block 17 start_pc=0 + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) + block 18 start_pc=0 + v8 Imm(0) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) + block 19 start_pc=0 + v17 Imm(3) -> x0 + terminator Return(v17) (exit_acc=v17) + block 20 start_pc=0 + v19 Imm(4) -> x0 + terminator Return(v19) (exit_acc=v19) + block 21 start_pc=0 + v22 Imm(5) -> x0 + terminator Return(v22) (exit_acc=v22) + block 22 start_pc=0 + v27 Imm(6) -> x0 + terminator Return(v27) (exit_acc=v27) block 23 start_pc=0 - terminator Jmp(b18) + v45 Imm(8) -> x0 + terminator Return(v45) (exit_acc=v45) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/int_to_float_assign_conversion.ssa b/tests/snapshots/ssa/int_to_float_assign_conversion.ssa index 4dda0dff3..f75fc8d5b 100644 --- a/tests/snapshots/ssa/int_to_float_assign_conversion.ssa +++ b/tests/snapshots/ssa/int_to_float_assign_conversion.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=10 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 @@ -93,66 +93,59 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 v73 Imm(4) -> x0 terminator Return(v73) (exit_acc=v73) block 8 start_pc=0 - v74 Imm(4599057925072241033) -> x0 + v74 Imm(1050220167) -> x0 [f32] v75 LoadLocal { off=-2, kind=F32 } -> d3 [f32] - v76 FpCast { kind=F32ToF64, value=v18 } -> d0 - v77 Binop { op=fmul, lhs=v74, rhs=v76 } -> d3 - v78 Imm(4603462445507809378) -> x1 - v79 LoadLocal { off=-3, kind=F32 } -> d3 [f32] - v80 FpCast { kind=F32ToF64, value=v24 } -> d1 - v81 Binop { op=fmul, lhs=v78, rhs=v80 } -> d1 - v82 Fma { a=v74, b=v76, c=v81, neg_product=false, neg_addend=false } -> d0 - v83 Imm(4592878986383488713) -> x0 - v84 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v85 FpCast { kind=F32ToF64, value=v30 } -> d1 - v86 Binop { op=fmul, lhs=v83, rhs=v85 } -> d2 - v87 Fma { a=v83, b=v85, c=v82, neg_product=false, neg_addend=false } -> d0 - v88 Imm(4638707616191610880) -> x0 - v89 Binop { op=fsub, lhs=v87, rhs=v88 } -> d0 - v90 FpCast { kind=F64ToF32, value=v89 } -> d0 [f32] - v91 Imm(0) -> x0 - v92 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v93 Imm(4631248529308778496) -> x0 - v94 Fneg(v93) -> d1 - v95 FpCast { kind=F32ToF64, value=v90 } -> d2 - v96 Binop { op=fgt, lhs=v95, rhs=v94 } -> x3 - v97 Imm(0) -> x0 - terminator Bnz { cond=v96, target=b15, fall=b9 } (exit_acc=v96) + v76 Binop { op=fmul, lhs=v74, rhs=v18 } -> d3 [f32] + v77 Imm(1058424226) -> x1 [f32] + v78 LoadLocal { off=-3, kind=F32 } -> d3 [f32] + v79 Binop { op=fmul, lhs=v77, rhs=v24 } -> d1 [f32] + v80 Fma { a=v74, b=v18, c=v79, neg_product=false, neg_addend=false } -> d0 [f32] + v81 Imm(1038710997) -> x0 [f32] + v82 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v83 Binop { op=fmul, lhs=v81, rhs=v30 } -> d1 [f32] + v84 Fma { a=v81, b=v30, c=v80, neg_product=false, neg_addend=false } -> d0 [f32] + v85 Imm(1124073472) -> x0 [f32] + v86 Binop { op=fsub, lhs=v84, rhs=v85 } -> d0 [f32] + v87 Imm(0) -> x0 + v88 LoadLocal { off=-6, kind=F32 } -> d1 [f32] + v89 Imm(1110179840) -> x0 [f32] + v90 Fneg(v89) -> d1 [f32] + v91 Binop { op=fgt, lhs=v86, rhs=v90 } -> x1 + v92 Imm(0) -> x0 + terminator Bnz { cond=v91, target=b15, fall=b9 } (exit_acc=v91) block 9 start_pc=0 - v98 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v99 Imm(4631389266797133824) -> x0 - v100 Fneg(v99) -> d1 - v101 FpCast { kind=F32ToF64, value=v90 } -> d0 - v102 Binop { op=flt, lhs=v101, rhs=v100 } -> x3 - v103 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v102) + v93 LoadLocal { off=-6, kind=F32 } -> d1 [f32] + v94 Imm(1110441984) -> x0 [f32] + v95 Fneg(v94) -> d1 [f32] + v96 Binop { op=flt, lhs=v86, rhs=v95 } -> x1 + v97 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v96) block 10 start_pc=0 - v104 Phi { incoming=[b15:v96, b9:v102], kind=I64 } -> x3 - v105 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v104, target=b12, fall=b11 } (exit_acc=v104) + v98 Phi { incoming=[b15:v91, b9:v96], kind=I64 } -> x1 + v99 LoadLocal { off=-10, kind=I64 } -> x0 + terminator Bz { cond=v98, target=b12, fall=b11 } (exit_acc=v98) block 11 start_pc=0 - v106 Imm(5) -> x0 - terminator Return(v106) (exit_acc=v106) + v100 Imm(5) -> x0 + terminator Return(v100) (exit_acc=v100) block 12 start_pc=0 - v107 Imm(7) -> x0 - v108 Imm(0) -> x1 - v109 LoadLocal { off=-7, kind=I32 } -> x1 - v110 FpCast { kind=IntToFp, value=v107 } -> d0 - v111 FpCast { kind=F64ToF32, value=v110 } -> d0 [f32] - v112 Imm(0) -> x0 - v113 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v114 Imm(4619567317775286272) -> x0 - v115 FpCast { kind=F32ToF64, value=v111 } -> d0 - v116 Binop { op=fne, lhs=v115, rhs=v114 } -> x0 - terminator Bz { cond=v116, target=b14, fall=b13 } (exit_acc=v116) + v101 Imm(7) -> x0 + v102 Imm(0) -> x1 + v103 LoadLocal { off=-7, kind=I32 } -> x1 + v104 FpCast { kind=IntToFp, value=v101 } -> d0 + v105 FpCast { kind=F64ToF32, value=v104 } -> d0 [f32] + v106 Imm(0) -> x0 + v107 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v108 Imm(1088421888) -> x0 [f32] + v109 Binop { op=fne, lhs=v105, rhs=v108 } -> x0 + terminator Bz { cond=v109, target=b14, fall=b13 } (exit_acc=v109) block 13 start_pc=0 - v117 Imm(6) -> x0 - terminator Return(v117) (exit_acc=v117) + v110 Imm(6) -> x0 + terminator Return(v110) (exit_acc=v110) block 14 start_pc=0 - v118 ImmData(36) -> x7 - v119 CallExt { binding_idx=0, args=[v118], fp_arg_mask=0x0 } -> x0 - v120 Imm(0) -> x0 - terminator Return(v120) (exit_acc=v120) + v111 ImmData(36) -> x7 + v112 CallExt { binding_idx=0, args=[v111], fp_arg_mask=0x0 } -> x0 + v113 Imm(0) -> x0 + terminator Return(v113) (exit_acc=v113) block 15 start_pc=0 terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/integer_boundary_c99.ssa b/tests/snapshots/ssa/integer_boundary_c99.ssa index 9205eabe0..daf635d3a 100644 --- a/tests/snapshots/ssa/integer_boundary_c99.ssa +++ b/tests/snapshots/ssa/integer_boundary_c99.ssa @@ -62,20 +62,666 @@ fn ent_pc=0 n_params=1 variadic=false locals=6 ; --- SSA dump (ok=true) ent_pc=6 --- ; name=main fn ent_pc=6 n_params=0 variadic=false locals=39 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - terminator Jmp(b1) (exit_acc=v0) block 1 start_pc=0 v1 Imm(1) -> x0 v2 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v2) + terminator Jmp(b2) (exit_acc=v2) block 2 start_pc=0 v11 Imm(0) -> x0 terminator Jmp(b3) (exit_acc=v11) block 3 start_pc=0 - terminator Jmp(b6) + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v13) block 4 start_pc=0 + v22 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 + v23 Imm(1) -> x0 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v24) + block 6 start_pc=0 + v33 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v33) + block 7 start_pc=0 + v34 Imm(1) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v35) + block 8 start_pc=0 + v44 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v44) + block 9 start_pc=0 + v45 Imm(1) -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v46) + block 10 start_pc=0 + v55 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v55) + block 11 start_pc=0 + v56 Imm(1) -> x0 + v57 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v57) + block 12 start_pc=0 + v66 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v66) + block 13 start_pc=0 + v67 Imm(1) -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v68) + block 14 start_pc=0 + v77 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v77) + block 15 start_pc=0 + v78 Imm(1) -> x0 + v79 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v79) + block 16 start_pc=0 + v88 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v88) + block 17 start_pc=0 + v89 Imm(255) -> x0 + v90 Imm(0) -> x1 + terminator Jmp(b18) (exit_acc=v89) + block 18 start_pc=0 + v91 LoadLocal { off=-1, kind=U8 } -> x0 + v92 Imm(0) -> x0 + v93 Imm(0) -> x0 + v94 Imm(1) -> x0 + v95 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v95) + block 19 start_pc=0 + v104 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v104) + block 20 start_pc=0 + v105 LoadLocal { off=-1, kind=U8 } -> x0 + v106 Imm(256) -> x0 + v107 Imm(0) -> x1 + terminator Jmp(b21) (exit_acc=v106) + block 21 start_pc=0 + v108 Imm(0) -> x0 + v109 Imm(1) -> x0 + v110 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v110) + block 22 start_pc=0 + v119 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v119) + block 23 start_pc=0 + v120 Imm(0) -> x0 + v121 Imm(-1) -> x0 + v122 Imm(0) -> x1 + terminator Jmp(b24) (exit_acc=v121) + block 24 start_pc=0 + v123 Imm(255) -> x0 + v124 Imm(0) -> x0 + v125 Imm(0) -> x0 + v126 Imm(1) -> x0 + v127 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v127) + block 25 start_pc=0 + v136 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v136) + block 26 start_pc=0 + v137 Imm(127) -> x0 + v138 Imm(0) -> x1 + terminator Jmp(b27) (exit_acc=v137) + block 27 start_pc=0 + v139 LoadLocal { off=-2, kind=I8 } -> x0 + v140 Imm(1) -> x0 + v141 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v141) + block 28 start_pc=0 + v150 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v150) + block 29 start_pc=0 + v151 Imm(-128) -> x0 + v152 Imm(0) -> x1 + terminator Jmp(b30) (exit_acc=v151) + block 30 start_pc=0 + v153 LoadLocal { off=-3, kind=I8 } -> x0 + v154 Imm(1) -> x0 + v155 Imm(0) -> x0 + terminator Jmp(b31) (exit_acc=v155) + block 31 start_pc=0 + v164 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v164) + block 32 start_pc=0 + v165 LoadLocal { off=-3, kind=I8 } -> x0 + v166 Imm(-129) -> x0 + v167 Imm(0) -> x1 + terminator Jmp(b33) (exit_acc=v166) + block 33 start_pc=0 + v168 Imm(127) -> x0 + v169 Imm(127) -> x0 + v170 Imm(0) -> x0 + v171 Imm(0) -> x0 + v172 Imm(1) -> x0 + v173 Imm(0) -> x0 + terminator Jmp(b34) (exit_acc=v173) + block 34 start_pc=0 + v182 Imm(0) -> x0 + terminator Jmp(b35) (exit_acc=v182) + block 35 start_pc=0 + v183 Imm(65535) -> x0 + v184 Imm(0) -> x1 + terminator Jmp(b36) (exit_acc=v183) + block 36 start_pc=0 + v185 LoadLocal { off=-4, kind=U16 } -> x0 + v186 Imm(0) -> x0 + v187 Imm(0) -> x0 + v188 Imm(1) -> x0 + v189 Imm(0) -> x0 + terminator Jmp(b37) (exit_acc=v189) + block 37 start_pc=0 + v198 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v198) + block 38 start_pc=0 + v199 LoadLocal { off=-4, kind=U16 } -> x0 + v200 Imm(65536) -> x0 + v201 Imm(0) -> x1 + terminator Jmp(b39) (exit_acc=v200) + block 39 start_pc=0 + v202 Imm(0) -> x0 + v203 Imm(1) -> x0 + v204 Imm(0) -> x0 + terminator Jmp(b40) (exit_acc=v204) + block 40 start_pc=0 + v213 Imm(0) -> x0 + terminator Jmp(b41) (exit_acc=v213) + block 41 start_pc=0 + v214 Imm(0) -> x0 + v215 Imm(0) -> x0 + v216 LoadLocal { off=-4, kind=U16 } -> x0 + v217 Imm(-1) -> x0 + v218 Imm(0) -> x1 + terminator Jmp(b42) (exit_acc=v217) + block 42 start_pc=0 + v219 Imm(65535) -> x0 + v220 Imm(0) -> x0 + v221 Imm(0) -> x0 + v222 Imm(1) -> x0 + v223 Imm(0) -> x0 + terminator Jmp(b43) (exit_acc=v223) + block 43 start_pc=0 + v232 Imm(0) -> x0 + terminator Jmp(b44) (exit_acc=v232) + block 44 start_pc=0 + v233 Imm(32767) -> x0 + v234 Imm(0) -> x1 + terminator Jmp(b45) (exit_acc=v233) + block 45 start_pc=0 + v235 LoadLocal { off=-5, kind=I16 } -> x0 + v236 Imm(1) -> x0 + v237 Imm(0) -> x0 + terminator Jmp(b46) (exit_acc=v237) + block 46 start_pc=0 + v246 Imm(0) -> x0 + terminator Jmp(b47) (exit_acc=v246) + block 47 start_pc=0 + v247 Imm(-32768) -> x0 + v248 Imm(0) -> x1 + terminator Jmp(b48) (exit_acc=v247) + block 48 start_pc=0 + v249 LoadLocal { off=-6, kind=I16 } -> x0 + v250 Imm(1) -> x0 + v251 Imm(0) -> x0 + terminator Jmp(b49) (exit_acc=v251) + block 49 start_pc=0 + v260 Imm(0) -> x0 + terminator Jmp(b50) (exit_acc=v260) + block 50 start_pc=0 + v261 LoadLocal { off=-6, kind=I16 } -> x0 + v262 Imm(32768) -> x0 + v263 Imm(0) -> x1 + terminator Jmp(b51) (exit_acc=v262) + block 51 start_pc=0 + v264 Imm(32768) -> x0 + v265 Imm(0) -> x0 + v266 Imm(0) -> x0 + v267 Imm(1) -> x0 + v268 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v268) + block 52 start_pc=0 + v277 Imm(0) -> x0 + terminator Jmp(b53) (exit_acc=v277) + block 53 start_pc=0 + v278 Imm(74565) -> x0 + v279 Imm(0) -> x0 + v280 LoadLocal { off=-8, kind=I32 } -> x0 + v281 Imm(2541437564720513024) -> x0 + v282 Imm(9029) -> x0 + v283 Imm(0) -> x1 + terminator Jmp(b54) (exit_acc=v282) + block 54 start_pc=0 + v284 LoadLocal { off=-9, kind=I16 } -> x0 + v285 Imm(1) -> x0 + v286 Imm(0) -> x0 + terminator Jmp(b55) (exit_acc=v286) + block 55 start_pc=0 + v295 Imm(0) -> x0 + terminator Jmp(b56) (exit_acc=v295) + block 56 start_pc=0 + v296 Imm(-42) -> x0 + v297 Imm(0) -> x1 + v298 LoadLocal { off=-10, kind=I16 } -> x1 + v299 Imm(0) -> x1 + terminator Jmp(b57) (exit_acc=v296) + block 57 start_pc=0 + v300 Imm(-42) -> x0 + v301 Imm(1) -> x0 + v302 Imm(0) -> x0 + terminator Jmp(b58) (exit_acc=v302) + block 58 start_pc=0 + v311 Imm(0) -> x0 + terminator Jmp(b59) (exit_acc=v311) + block 59 start_pc=0 + v312 Imm(65535) -> x0 + v313 Imm(0) -> x1 + v314 LoadLocal { off=-12, kind=U16 } -> x1 + v315 Imm(0) -> x1 + terminator Jmp(b60) (exit_acc=v312) + block 60 start_pc=0 + v316 Imm(65535) -> x0 + v317 Imm(0) -> x0 + v318 Imm(0) -> x0 + v319 Imm(1) -> x0 + v320 Imm(0) -> x0 + terminator Jmp(b61) (exit_acc=v320) + block 61 start_pc=0 + v329 Imm(0) -> x0 + terminator Jmp(b62) (exit_acc=v329) + block 62 start_pc=0 + v330 LoadLocal { off=-12, kind=U16 } -> x0 + v331 Imm(1) -> x0 + v332 Imm(0) -> x0 + terminator Jmp(b63) (exit_acc=v332) + block 63 start_pc=0 + v341 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v341) + block 64 start_pc=0 + v342 Imm(4294967295) -> x0 + v343 Imm(0) -> x1 + terminator Jmp(b65) (exit_acc=v342) + block 65 start_pc=0 + v344 LoadLocal { off=-14, kind=U32 } -> x0 + v345 Imm(1) -> x0 + v346 Imm(0) -> x0 + terminator Jmp(b66) (exit_acc=v346) + block 66 start_pc=0 + v355 Imm(0) -> x0 + terminator Jmp(b67) (exit_acc=v355) + block 67 start_pc=0 + v356 LoadLocal { off=-14, kind=U32 } -> x0 + v357 Imm(4294967296) -> x0 + v358 Imm(0) -> x1 + terminator Jmp(b68) (exit_acc=v357) + block 68 start_pc=0 + v359 Imm(0) -> x0 + v360 Imm(1) -> x0 + v361 Imm(0) -> x0 + terminator Jmp(b69) (exit_acc=v361) + block 69 start_pc=0 + v370 Imm(0) -> x0 + terminator Jmp(b70) (exit_acc=v370) + block 70 start_pc=0 + v371 Imm(0) -> x0 + v372 Imm(0) -> x0 + v373 LoadLocal { off=-14, kind=U32 } -> x0 + v374 Imm(-1) -> x0 + v375 Imm(0) -> x1 + terminator Jmp(b71) (exit_acc=v374) + block 71 start_pc=0 + v376 Imm(4294967295) -> x0 + v377 Imm(1) -> x0 + v378 Imm(0) -> x0 + terminator Jmp(b72) (exit_acc=v378) + block 72 start_pc=0 + v387 Imm(0) -> x0 + terminator Jmp(b73) (exit_acc=v387) + block 73 start_pc=0 + v388 Imm(2147483647) -> x0 + v389 Imm(0) -> x1 + terminator Jmp(b74) (exit_acc=v388) + block 74 start_pc=0 + v390 LoadLocal { off=-15, kind=I32 } -> x0 + v391 Imm(1) -> x0 + v392 Imm(0) -> x0 + terminator Jmp(b75) (exit_acc=v392) + block 75 start_pc=0 + v401 Imm(0) -> x0 + terminator Jmp(b76) (exit_acc=v401) + block 76 start_pc=0 + v402 Imm(-2147483648) -> x3 + v403 Imm(-9223372036854775808) -> x0 + v404 Imm(0) -> x0 + terminator Jmp(b77) (exit_acc=v402) + block 77 start_pc=0 + v405 LoadLocal { off=-16, kind=I32 } -> x0 + v406 Imm(1) -> x0 + v407 Imm(0) -> x0 + terminator Jmp(b78) (exit_acc=v407) + block 78 start_pc=0 + v416 Imm(0) -> x0 + terminator Jmp(b79) (exit_acc=v416) + block 79 start_pc=0 + v417 LoadLocal { off=-16, kind=I32 } -> x0 + v418 Imm(0) -> x0 + terminator Jmp(b80) (exit_acc=v402) + block 80 start_pc=0 + v419 LoadLocal { off=-17, kind=I64 } -> x0 + v420 Imm(1) -> x0 + v421 Imm(0) -> x0 + terminator Jmp(b81) (exit_acc=v421) + block 81 start_pc=0 + v430 Imm(0) -> x0 + terminator Jmp(b82) (exit_acc=v430) + block 82 start_pc=0 + v431 LoadLocal { off=-16, kind=I32 } -> x0 + v432 Imm(2147483648) -> x0 + v433 Imm(0) -> x1 + terminator Jmp(b83) (exit_acc=v432) + block 83 start_pc=0 + v434 LoadLocal { off=-18, kind=I64 } -> x0 + v435 Imm(1) -> x0 + v436 Imm(0) -> x0 + terminator Jmp(b84) (exit_acc=v436) + block 84 start_pc=0 + v444 Imm(0) -> x0 + terminator Jmp(b85) (exit_acc=v444) + block 85 start_pc=0 + v445 Imm(-1) -> x0 + v446 Imm(0) -> x1 + terminator Jmp(b86) (exit_acc=v445) + block 86 start_pc=0 + v447 LoadLocal { off=-19, kind=I64 } -> x0 + v448 Imm(1) -> x0 + v449 Imm(0) -> x0 + terminator Jmp(b87) (exit_acc=v449) + block 87 start_pc=0 + v458 Imm(0) -> x0 + terminator Jmp(b88) (exit_acc=v458) + block 88 start_pc=0 + v459 LoadLocal { off=-19, kind=I64 } -> x0 + v460 Imm(0) -> x0 + v461 Imm(0) -> x1 + terminator Jmp(b89) (exit_acc=v460) + block 89 start_pc=0 + v462 LoadLocal { off=-19, kind=I64 } -> x0 + v463 Imm(1) -> x0 + v464 Imm(0) -> x0 + terminator Jmp(b90) (exit_acc=v464) + block 90 start_pc=0 + v473 Imm(0) -> x0 + terminator Jmp(b91) (exit_acc=v473) + block 91 start_pc=0 + v474 LoadLocal { off=-19, kind=I64 } -> x0 + v475 Imm(-1) -> x0 + v476 Imm(0) -> x1 + terminator Jmp(b92) (exit_acc=v475) + block 92 start_pc=0 + v477 LoadLocal { off=-19, kind=I64 } -> x0 + v478 Imm(1) -> x0 + v479 Imm(0) -> x0 + terminator Jmp(b93) (exit_acc=v479) + block 93 start_pc=0 + v488 Imm(0) -> x0 + terminator Jmp(b94) (exit_acc=v488) + block 94 start_pc=0 + v489 Imm(9223372036854775807) -> x0 + v490 Imm(0) -> x1 + terminator Jmp(b95) (exit_acc=v489) + block 95 start_pc=0 + v491 LoadLocal { off=-20, kind=I64 } -> x0 + v492 Imm(1) -> x0 + v493 Imm(0) -> x0 + terminator Jmp(b96) (exit_acc=v493) + block 96 start_pc=0 + v502 Imm(0) -> x0 + terminator Jmp(b97) (exit_acc=v502) + block 97 start_pc=0 + v503 Imm(-1) -> x0 + v504 Imm(0) -> x1 + terminator Jmp(b98) (exit_acc=v503) + block 98 start_pc=0 + v505 LoadLocal { off=-21, kind=I64 } -> x0 + v506 Imm(-1) -> x0 + v507 Imm(1) -> x0 + v508 Imm(0) -> x0 + terminator Jmp(b99) (exit_acc=v508) + block 99 start_pc=0 + v517 Imm(0) -> x0 + terminator Jmp(b100) (exit_acc=v517) + block 100 start_pc=0 + v518 Imm(-9223372036854775808) -> x0 + v519 Imm(0) -> x1 + terminator Jmp(b101) (exit_acc=v518) + block 101 start_pc=0 + v520 LoadLocal { off=-22, kind=I64 } -> x0 + v521 Imm(4611686018427387904) -> x0 + v522 Imm(1) -> x0 + v523 Imm(0) -> x0 + terminator Jmp(b102) (exit_acc=v523) + block 102 start_pc=0 + v532 Imm(0) -> x0 + terminator Jmp(b103) (exit_acc=v532) + block 103 start_pc=0 + v533 Imm(-1) -> x0 + v534 Imm(0) -> x1 + terminator Jmp(b104) (exit_acc=v533) + block 104 start_pc=0 + v535 LoadLocal { off=-23, kind=I64 } -> x0 + v536 Imm(4294967295) -> x0 + v537 Imm(1) -> x0 + v538 Imm(0) -> x0 + terminator Jmp(b105) (exit_acc=v538) + block 105 start_pc=0 + v547 Imm(0) -> x0 + terminator Jmp(b106) (exit_acc=v547) + block 106 start_pc=0 + v548 Imm(-300) -> x0 + v549 Imm(0) -> x0 + v550 LoadLocal { off=-24, kind=I32 } -> x0 + v551 Imm(-3170534137668829184) -> x0 + v552 Imm(-44) -> x0 + v553 Imm(0) -> x1 + terminator Jmp(b107) (exit_acc=v552) + block 107 start_pc=0 + v554 LoadLocal { off=-25, kind=I8 } -> x0 + v555 Imm(212) -> x0 + v556 Imm(-3170534137668829184) -> x0 + v557 Imm(-44) -> x0 + v558 Imm(1) -> x0 + v559 Imm(0) -> x0 + terminator Jmp(b108) (exit_acc=v559) + block 108 start_pc=0 + v568 Imm(0) -> x0 + terminator Jmp(b109) (exit_acc=v568) + block 109 start_pc=0 + v569 LoadLocal { off=-25, kind=I8 } -> x0 + v570 Imm(1) -> x0 + v571 Imm(0) -> x0 + terminator Jmp(b110) (exit_acc=v571) + block 110 start_pc=0 + v580 Imm(0) -> x0 + terminator Jmp(b111) (exit_acc=v580) + block 111 start_pc=0 + v581 LoadLocal { off=-24, kind=I32 } -> x0 + v582 Imm(212) -> x0 + v583 Imm(0) -> x1 + terminator Jmp(b112) (exit_acc=v582) + block 112 start_pc=0 + v584 Imm(212) -> x0 + v585 Imm(0) -> x0 + v586 Imm(0) -> x0 + v587 Imm(1) -> x0 + v588 Imm(0) -> x0 + terminator Jmp(b113) (exit_acc=v588) + block 113 start_pc=0 + v597 Imm(0) -> x0 + terminator Jmp(b114) (exit_acc=v597) + block 114 start_pc=0 + v598 Imm(212) -> x0 + v599 Imm(1) -> x0 + v600 Imm(0) -> x0 + terminator Jmp(b115) (exit_acc=v600) + block 115 start_pc=0 + v609 Imm(0) -> x0 + terminator Jmp(b116) (exit_acc=v609) + block 116 start_pc=0 + v610 Imm(74565) -> x0 + v611 Imm(0) -> x0 + v612 LoadLocal { off=-24, kind=I32 } -> x0 + v613 Imm(2541437564720513024) -> x0 + v614 Imm(9029) -> x0 + v615 Imm(0) -> x1 + terminator Jmp(b117) (exit_acc=v614) + block 117 start_pc=0 + v616 LoadLocal { off=-27, kind=I16 } -> x0 + v617 Imm(1) -> x0 + v618 Imm(0) -> x0 + terminator Jmp(b118) (exit_acc=v618) + block 118 start_pc=0 + v627 Imm(0) -> x0 + terminator Jmp(b119) (exit_acc=v627) + block 119 start_pc=0 + v628 LoadLocal { off=-27, kind=I16 } -> x0 + v629 Imm(1) -> x0 + v630 Imm(0) -> x0 + terminator Jmp(b120) (exit_acc=v630) + block 120 start_pc=0 + v639 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v639) + block 121 start_pc=0 + v640 Imm(131071) -> x0 + v641 Imm(0) -> x0 + v642 LoadLocal { off=-24, kind=I32 } -> x0 + v643 Imm(-281474976710656) -> x0 + v644 Imm(-1) -> x0 + v645 Imm(0) -> x1 + terminator Jmp(b122) (exit_acc=v644) + block 122 start_pc=0 + v646 LoadLocal { off=-27, kind=I16 } -> x0 + v647 Imm(1) -> x0 + v648 Imm(0) -> x0 + terminator Jmp(b123) (exit_acc=v648) + block 123 start_pc=0 + v657 Imm(0) -> x0 + terminator Jmp(b124) (exit_acc=v657) + block 124 start_pc=0 + v658 LoadLocal { off=-27, kind=I16 } -> x0 + v659 Imm(1) -> x0 + v660 Imm(0) -> x0 + terminator Jmp(b125) (exit_acc=v660) + block 125 start_pc=0 + v669 Imm(0) -> x0 + terminator Jmp(b126) (exit_acc=v669) + block 126 start_pc=0 + v670 Imm(4294967295) -> x0 + v671 Imm(0) -> x0 + v672 Imm(1) -> x0 + v673 Imm(0) -> x1 + terminator Jmp(b127) (exit_acc=v672) + block 127 start_pc=0 + v674 LoadLocal { off=-28, kind=U32 } -> x0 + v675 LoadLocal { off=-29, kind=U32 } -> x0 + v676 Imm(1) -> x0 + v677 Imm(0) -> x0 + terminator Jmp(b128) (exit_acc=v677) + block 128 start_pc=0 + v686 Imm(0) -> x0 + terminator Jmp(b129) (exit_acc=v686) + block 129 start_pc=0 + v687 LoadLocal { off=-28, kind=U32 } -> x0 + v688 Imm(-4294967296) -> x0 + v689 Imm(-1) -> x0 + v690 Imm(0) -> x0 + v691 LoadLocal { off=-29, kind=U32 } -> x0 + v692 Imm(4294967296) -> x0 + v693 Imm(1) -> x0 + v694 Imm(0) -> x1 + terminator Jmp(b130) (exit_acc=v693) + block 130 start_pc=0 + v695 LoadLocal { off=-30, kind=I32 } -> x0 + v696 LoadLocal { off=-31, kind=I32 } -> x0 + v697 Imm(1) -> x0 + v698 Imm(0) -> x0 + terminator Jmp(b131) (exit_acc=v698) + block 131 start_pc=0 + v707 Imm(0) -> x0 + terminator Jmp(b132) (exit_acc=v707) + block 132 start_pc=0 + v708 Imm(1) -> x0 + v709 Imm(0) -> x1 + terminator Jmp(b133) (exit_acc=v708) + block 133 start_pc=0 + v710 LoadLocal { off=-32, kind=I32 } -> x0 + v711 Imm(1073741824) -> x0 + v712 Imm(4611686018427387904) -> x0 + v713 Imm(1073741824) -> x0 + v714 Imm(1) -> x0 + v715 Imm(0) -> x0 + terminator Jmp(b134) (exit_acc=v715) + block 134 start_pc=0 + v724 Imm(0) -> x0 + terminator Jmp(b135) (exit_acc=v724) + block 135 start_pc=0 + v725 Imm(1) -> x0 + v726 Imm(0) -> x1 + terminator Jmp(b136) (exit_acc=v725) + block 136 start_pc=0 + v727 LoadLocal { off=-33, kind=U32 } -> x0 + v728 Imm(2147483648) -> x0 + v729 Imm(2147483648) -> x0 + v730 Imm(1) -> x0 + v731 Imm(0) -> x0 + terminator Jmp(b137) (exit_acc=v731) + block 137 start_pc=0 + v740 Imm(0) -> x0 + terminator Jmp(b138) (exit_acc=v740) + block 138 start_pc=0 + v741 Imm(-1) -> x0 + v742 Imm(0) -> x1 + terminator Jmp(b139) (exit_acc=v741) + block 139 start_pc=0 + v743 LoadLocal { off=-34, kind=I32 } -> x0 + v744 Imm(1) -> x0 + v745 Imm(0) -> x0 + terminator Jmp(b140) (exit_acc=v745) + block 140 start_pc=0 + v754 Imm(0) -> x0 + terminator Jmp(b141) (exit_acc=v754) + block 141 start_pc=0 + v755 Imm(4294967295) -> x0 + v756 Imm(0) -> x1 + terminator Jmp(b142) (exit_acc=v755) + block 142 start_pc=0 + v757 LoadLocal { off=-35, kind=U32 } -> x0 + v758 Imm(1) -> x0 + v759 Imm(0) -> x0 + terminator Jmp(b143) (exit_acc=v759) + block 143 start_pc=0 + v768 Imm(0) -> x0 + terminator Jmp(b144) (exit_acc=v768) + block 144 start_pc=0 + v769 ImmData(1480) -> x0 + v770 Load { addr=v769, disp=0, kind=I32 } -> x0 + v771 BinopI { op=eq, lhs=v770, rhs_imm=0 } -> x0 + terminator Bz { cond=v771, target=b146, fall=b145 } (exit_acc=v771) + block 145 start_pc=0 + v772 ImmData(1468) -> x7 + v773 CallExt { binding_idx=0, args=[v772], fp_arg_mask=0x0 } -> x0 + v774 Imm(0) -> x0 + terminator Return(v774) (exit_acc=v774) + block 146 start_pc=0 + v775 ImmData(1480) -> x0 + v776 Load { addr=v775, disp=0, kind=I32 } -> x0 + terminator Return(v776) (exit_acc=v776) + block 147 start_pc=0 + terminator Jmp(b3) + block 148 start_pc=0 v3 ImmData(1480) -> x0 v4 Imm(100) -> x3 v5 Store { addr=v3, disp=0, value=v4, kind=I32 } -> - @@ -84,19 +730,12 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v8 ImmData(64) -> x6 v9 Imm(54) -> x2 v10 CallExt { binding_idx=1, args=[v7, v8, v9, v4], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b5) (exit_acc=v10) - block 5 start_pc=0 + terminator Jmp(b2) (exit_acc=v10) + block 149 start_pc=0 terminator Jmp(b2) - block 6 start_pc=0 - v12 Imm(1) -> x0 - v13 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v13) - block 7 start_pc=0 - v22 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v22) - block 8 start_pc=0 - terminator Jmp(b11) - block 9 start_pc=0 + block 150 start_pc=0 + terminator Jmp(b5) + block 151 start_pc=0 v14 ImmData(1480) -> x0 v15 Imm(101) -> x3 v16 Store { addr=v14, disp=0, value=v15, kind=I32 } -> - @@ -105,19 +744,12 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v19 ImmData(91) -> x6 v20 Imm(55) -> x2 v21 CallExt { binding_idx=1, args=[v18, v19, v20, v15], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b10) (exit_acc=v21) - block 10 start_pc=0 + terminator Jmp(b4) (exit_acc=v21) + block 152 start_pc=0 + terminator Jmp(b4) + block 153 start_pc=0 terminator Jmp(b7) - block 11 start_pc=0 - v23 Imm(1) -> x0 - v24 Imm(0) -> x0 - terminator Jmp(b15) (exit_acc=v24) - block 12 start_pc=0 - v33 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v33) - block 13 start_pc=0 - terminator Jmp(b16) - block 14 start_pc=0 + block 154 start_pc=0 v25 ImmData(1480) -> x0 v26 Imm(102) -> x3 v27 Store { addr=v25, disp=0, value=v26, kind=I32 } -> - @@ -126,19 +758,12 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v30 ImmData(118) -> x6 v31 Imm(56) -> x2 v32 CallExt { binding_idx=1, args=[v29, v30, v31, v26], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b15) (exit_acc=v32) - block 15 start_pc=0 - terminator Jmp(b12) - block 16 start_pc=0 - v34 Imm(1) -> x0 - v35 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v35) - block 17 start_pc=0 - v44 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v44) - block 18 start_pc=0 - terminator Jmp(b21) - block 19 start_pc=0 + terminator Jmp(b6) (exit_acc=v32) + block 155 start_pc=0 + terminator Jmp(b6) + block 156 start_pc=0 + terminator Jmp(b9) + block 157 start_pc=0 v36 ImmData(1480) -> x0 v37 Imm(103) -> x3 v38 Store { addr=v36, disp=0, value=v37, kind=I32 } -> - @@ -147,40 +772,26 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v41 ImmData(145) -> x6 v42 Imm(57) -> x2 v43 CallExt { binding_idx=1, args=[v40, v41, v42, v37], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b20) (exit_acc=v43) - block 20 start_pc=0 - terminator Jmp(b17) - block 21 start_pc=0 - v45 Imm(1) -> x0 - v46 Imm(0) -> x0 - terminator Jmp(b25) (exit_acc=v46) - block 22 start_pc=0 - v55 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v55) - block 23 start_pc=0 - terminator Jmp(b26) - block 24 start_pc=0 + terminator Jmp(b8) (exit_acc=v43) + block 158 start_pc=0 + terminator Jmp(b8) + block 159 start_pc=0 + terminator Jmp(b11) + block 160 start_pc=0 v47 ImmData(1480) -> x0 v48 Imm(104) -> x3 v49 Store { addr=v47, disp=0, value=v48, kind=I32 } -> - - v50 Imm(2) -> x7 - v51 Call { target_pc=0, args=[v50], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v52 ImmData(172) -> x6 - v53 Imm(58) -> x2 - v54 CallExt { binding_idx=1, args=[v51, v52, v53, v48], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b25) (exit_acc=v54) - block 25 start_pc=0 - terminator Jmp(b22) - block 26 start_pc=0 - v56 Imm(1) -> x0 - v57 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v57) - block 27 start_pc=0 - v66 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v66) - block 28 start_pc=0 - terminator Jmp(b31) - block 29 start_pc=0 + v50 Imm(2) -> x7 + v51 Call { target_pc=0, args=[v50], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v52 ImmData(172) -> x6 + v53 Imm(58) -> x2 + v54 CallExt { binding_idx=1, args=[v51, v52, v53, v48], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b10) (exit_acc=v54) + block 161 start_pc=0 + terminator Jmp(b10) + block 162 start_pc=0 + terminator Jmp(b13) + block 163 start_pc=0 v58 ImmData(1480) -> x0 v59 Imm(105) -> x3 v60 Store { addr=v58, disp=0, value=v59, kind=I32 } -> - @@ -189,19 +800,12 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v63 ImmData(199) -> x6 v64 Imm(59) -> x2 v65 CallExt { binding_idx=1, args=[v62, v63, v64, v59], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b30) (exit_acc=v65) - block 30 start_pc=0 - terminator Jmp(b27) - block 31 start_pc=0 - v67 Imm(1) -> x0 - v68 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v68) - block 32 start_pc=0 - v77 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v77) - block 33 start_pc=0 - terminator Jmp(b36) - block 34 start_pc=0 + terminator Jmp(b12) (exit_acc=v65) + block 164 start_pc=0 + terminator Jmp(b12) + block 165 start_pc=0 + terminator Jmp(b15) + block 166 start_pc=0 v69 ImmData(1480) -> x0 v70 Imm(106) -> x3 v71 Store { addr=v69, disp=0, value=v70, kind=I32 } -> - @@ -210,21 +814,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v74 ImmData(226) -> x6 v75 Imm(60) -> x2 v76 CallExt { binding_idx=1, args=[v73, v74, v75, v70], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b35) (exit_acc=v76) - block 35 start_pc=0 - terminator Jmp(b32) - block 36 start_pc=0 - v78 Imm(1) -> x0 - v79 Imm(0) -> x0 - terminator Jmp(b40) (exit_acc=v79) - block 37 start_pc=0 - v88 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v88) - block 38 start_pc=0 - v89 Imm(255) -> x3 - v90 Imm(0) -> x0 - terminator Jmp(b41) (exit_acc=v89) - block 39 start_pc=0 + terminator Jmp(b14) (exit_acc=v76) + block 167 start_pc=0 + terminator Jmp(b14) + block 168 start_pc=0 v80 ImmData(1480) -> x0 v81 Imm(107) -> x3 v82 Store { addr=v80, disp=0, value=v81, kind=I32 } -> - @@ -233,76 +826,34 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v85 ImmData(253) -> x6 v86 Imm(61) -> x2 v87 CallExt { binding_idx=1, args=[v84, v85, v86, v81], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b40) (exit_acc=v87) - block 40 start_pc=0 - terminator Jmp(b37) - block 41 start_pc=0 - v91 LoadLocal { off=-1, kind=U8 } -> x0 - v92 BinopI { op=xor, lhs=v89, rhs_imm=255 } -> x0 - v93 BinopI { op=and, lhs=v92, rhs_imm=4294967295 } -> x0 - v94 BinopI { op=eq, lhs=v93, rhs_imm=0 } -> x0 - v95 BinopI { op=eq, lhs=v94, rhs_imm=0 } -> x0 - terminator Bz { cond=v95, target=b45, fall=b44 } (exit_acc=v95) - block 42 start_pc=0 - v104 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v104) - block 43 start_pc=0 - v105 LoadLocal { off=-1, kind=U8 } -> x0 - v106 BinopI { op=add, lhs=v89, rhs_imm=1 } -> x3 - v107 Imm(0) -> x0 - terminator Jmp(b46) (exit_acc=v106) - block 44 start_pc=0 + terminator Jmp(b16) (exit_acc=v87) + block 169 start_pc=0 + terminator Jmp(b16) + block 170 start_pc=0 v96 ImmData(1480) -> x0 - v97 Imm(110) -> x12 + v97 Imm(110) -> x3 v98 Store { addr=v96, disp=0, value=v97, kind=I32 } -> - v99 Imm(2) -> x7 v100 Call { target_pc=0, args=[v99], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v101 ImmData(280) -> x6 v102 Imm(66) -> x2 v103 CallExt { binding_idx=1, args=[v100, v101, v102, v97], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b45) (exit_acc=v103) - block 45 start_pc=0 - terminator Jmp(b42) - block 46 start_pc=0 - v108 BinopI { op=and, lhs=v106, rhs_imm=255 } -> x0 - v109 BinopI { op=eq, lhs=v108, rhs_imm=0 } -> x0 - v110 BinopI { op=eq, lhs=v109, rhs_imm=0 } -> x0 - terminator Bz { cond=v110, target=b50, fall=b49 } (exit_acc=v110) - block 47 start_pc=0 - v119 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v119) - block 48 start_pc=0 - v120 BinopI { op=and, lhs=v106, rhs_imm=255 } -> x0 - v121 BinopI { op=add, lhs=v120, rhs_imm=-1 } -> x0 - v122 Imm(0) -> x1 - terminator Jmp(b51) (exit_acc=v121) - block 49 start_pc=0 + terminator Jmp(b19) (exit_acc=v103) + block 171 start_pc=0 + terminator Jmp(b19) + block 172 start_pc=0 v111 ImmData(1480) -> x0 - v112 Imm(111) -> x12 + v112 Imm(111) -> x3 v113 Store { addr=v111, disp=0, value=v112, kind=I32 } -> - v114 Imm(2) -> x7 v115 Call { target_pc=0, args=[v114], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v116 ImmData(307) -> x6 v117 Imm(68) -> x2 v118 CallExt { binding_idx=1, args=[v115, v116, v117, v112], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b50) (exit_acc=v118) - block 50 start_pc=0 - terminator Jmp(b47) - block 51 start_pc=0 - v123 BinopI { op=and, lhs=v121, rhs_imm=255 } -> x0 - v124 BinopI { op=xor, lhs=v123, rhs_imm=255 } -> x0 - v125 BinopI { op=and, lhs=v124, rhs_imm=4294967295 } -> x0 - v126 BinopI { op=eq, lhs=v125, rhs_imm=0 } -> x0 - v127 BinopI { op=eq, lhs=v126, rhs_imm=0 } -> x0 - terminator Bz { cond=v127, target=b55, fall=b54 } (exit_acc=v127) - block 52 start_pc=0 - v136 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v136) - block 53 start_pc=0 - v137 Imm(127) -> x0 - v138 Imm(0) -> x1 - terminator Jmp(b56) (exit_acc=v137) - block 54 start_pc=0 + terminator Jmp(b22) (exit_acc=v118) + block 173 start_pc=0 + terminator Jmp(b22) + block 174 start_pc=0 v128 ImmData(1480) -> x0 v129 Imm(112) -> x3 v130 Store { addr=v128, disp=0, value=v129, kind=I32 } -> - @@ -311,22 +862,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v133 ImmData(334) -> x6 v134 Imm(70) -> x2 v135 CallExt { binding_idx=1, args=[v132, v133, v134, v129], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b55) (exit_acc=v135) - block 55 start_pc=0 - terminator Jmp(b52) - block 56 start_pc=0 - v139 LoadLocal { off=-2, kind=I8 } -> x1 - v140 BinopI { op=eq, lhs=v137, rhs_imm=127 } -> x0 - v141 BinopI { op=eq, lhs=v140, rhs_imm=0 } -> x0 - terminator Bz { cond=v141, target=b60, fall=b59 } (exit_acc=v141) - block 57 start_pc=0 - v150 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v150) - block 58 start_pc=0 - v151 Imm(-128) -> x3 - v152 Imm(0) -> x0 - terminator Jmp(b61) (exit_acc=v151) - block 59 start_pc=0 + terminator Jmp(b25) (exit_acc=v135) + block 175 start_pc=0 + terminator Jmp(b25) + block 176 start_pc=0 v142 ImmData(1480) -> x0 v143 Imm(113) -> x3 v144 Store { addr=v142, disp=0, value=v143, kind=I32 } -> - @@ -335,50 +874,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v147 ImmData(361) -> x6 v148 Imm(73) -> x2 v149 CallExt { binding_idx=1, args=[v146, v147, v148, v143], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b60) (exit_acc=v149) - block 60 start_pc=0 - terminator Jmp(b57) - block 61 start_pc=0 - v153 LoadLocal { off=-3, kind=I8 } -> x0 - v154 BinopI { op=eq, lhs=v151, rhs_imm=-128 } -> x0 - v155 BinopI { op=eq, lhs=v154, rhs_imm=0 } -> x0 - terminator Bz { cond=v155, target=b65, fall=b64 } (exit_acc=v155) - block 62 start_pc=0 - v164 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v164) - block 63 start_pc=0 - v165 LoadLocal { off=-3, kind=I8 } -> x0 - v166 BinopI { op=add, lhs=v151, rhs_imm=-1 } -> x0 - v167 Imm(0) -> x1 - terminator Jmp(b66) (exit_acc=v166) - block 64 start_pc=0 + terminator Jmp(b28) (exit_acc=v149) + block 177 start_pc=0 + terminator Jmp(b28) + block 178 start_pc=0 v156 ImmData(1480) -> x0 - v157 Imm(114) -> x12 + v157 Imm(114) -> x3 v158 Store { addr=v156, disp=0, value=v157, kind=I32 } -> - v159 Imm(2) -> x7 v160 Call { target_pc=0, args=[v159], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v161 ImmData(388) -> x6 v162 Imm(75) -> x2 v163 CallExt { binding_idx=1, args=[v160, v161, v162, v157], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b65) (exit_acc=v163) - block 65 start_pc=0 - terminator Jmp(b62) - block 66 start_pc=0 - v168 Extend { value=v166, kind=I8 } -> x0 - v169 BinopI { op=and, lhs=v168, rhs_imm=255 } -> x0 - v170 BinopI { op=xor, lhs=v169, rhs_imm=127 } -> x0 - v171 BinopI { op=and, lhs=v170, rhs_imm=4294967295 } -> x0 - v172 BinopI { op=eq, lhs=v171, rhs_imm=0 } -> x0 - v173 BinopI { op=eq, lhs=v172, rhs_imm=0 } -> x0 - terminator Bz { cond=v173, target=b70, fall=b69 } (exit_acc=v173) - block 67 start_pc=0 - v182 Imm(0) -> x0 - terminator Jmp(b68) (exit_acc=v182) - block 68 start_pc=0 - v183 Imm(65535) -> x3 - v184 Imm(0) -> x0 - terminator Jmp(b71) (exit_acc=v183) - block 69 start_pc=0 + terminator Jmp(b31) (exit_acc=v163) + block 179 start_pc=0 + terminator Jmp(b31) + block 180 start_pc=0 v174 ImmData(1480) -> x0 v175 Imm(115) -> x3 v176 Store { addr=v174, disp=0, value=v175, kind=I32 } -> - @@ -387,52 +898,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v179 ImmData(415) -> x6 v180 Imm(77) -> x2 v181 CallExt { binding_idx=1, args=[v178, v179, v180, v175], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b70) (exit_acc=v181) - block 70 start_pc=0 - terminator Jmp(b67) - block 71 start_pc=0 - v185 LoadLocal { off=-4, kind=U16 } -> x0 - v186 BinopI { op=xor, lhs=v183, rhs_imm=65535 } -> x0 - v187 BinopI { op=and, lhs=v186, rhs_imm=4294967295 } -> x0 - v188 BinopI { op=eq, lhs=v187, rhs_imm=0 } -> x0 - v189 BinopI { op=eq, lhs=v188, rhs_imm=0 } -> x0 - terminator Bz { cond=v189, target=b75, fall=b74 } (exit_acc=v189) - block 72 start_pc=0 - v198 Imm(0) -> x0 - terminator Jmp(b73) (exit_acc=v198) - block 73 start_pc=0 - v199 LoadLocal { off=-4, kind=U16 } -> x0 - v200 BinopI { op=add, lhs=v183, rhs_imm=1 } -> x0 - v201 Imm(0) -> x1 - terminator Jmp(b76) (exit_acc=v200) - block 74 start_pc=0 + terminator Jmp(b34) (exit_acc=v181) + block 181 start_pc=0 + terminator Jmp(b34) + block 182 start_pc=0 v190 ImmData(1480) -> x0 - v191 Imm(120) -> x12 + v191 Imm(120) -> x3 v192 Store { addr=v190, disp=0, value=v191, kind=I32 } -> - v193 Imm(2) -> x7 v194 Call { target_pc=0, args=[v193], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v195 ImmData(442) -> x6 v196 Imm(83) -> x2 v197 CallExt { binding_idx=1, args=[v194, v195, v196, v191], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b75) (exit_acc=v197) - block 75 start_pc=0 - terminator Jmp(b72) - block 76 start_pc=0 - v202 BinopI { op=and, lhs=v200, rhs_imm=65535 } -> x0 - v203 BinopI { op=eq, lhs=v202, rhs_imm=0 } -> x0 - v204 BinopI { op=eq, lhs=v203, rhs_imm=0 } -> x0 - terminator Bz { cond=v204, target=b80, fall=b79 } (exit_acc=v204) - block 77 start_pc=0 - v213 Imm(0) -> x0 - terminator Jmp(b78) (exit_acc=v213) - block 78 start_pc=0 - v214 Imm(0) -> x0 - v215 Imm(0) -> x1 - v216 LoadLocal { off=-4, kind=U16 } -> x1 - v217 BinopI { op=add, lhs=v214, rhs_imm=-1 } -> x0 - v218 Imm(0) -> x1 - terminator Jmp(b81) (exit_acc=v217) - block 79 start_pc=0 + terminator Jmp(b37) (exit_acc=v197) + block 183 start_pc=0 + terminator Jmp(b37) + block 184 start_pc=0 v205 ImmData(1480) -> x0 v206 Imm(121) -> x3 v207 Store { addr=v205, disp=0, value=v206, kind=I32 } -> - @@ -441,24 +922,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v210 ImmData(469) -> x6 v211 Imm(85) -> x2 v212 CallExt { binding_idx=1, args=[v209, v210, v211, v206], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b80) (exit_acc=v212) - block 80 start_pc=0 - terminator Jmp(b77) - block 81 start_pc=0 - v219 BinopI { op=and, lhs=v217, rhs_imm=65535 } -> x0 - v220 BinopI { op=xor, lhs=v219, rhs_imm=65535 } -> x0 - v221 BinopI { op=and, lhs=v220, rhs_imm=4294967295 } -> x0 - v222 BinopI { op=eq, lhs=v221, rhs_imm=0 } -> x0 - v223 BinopI { op=eq, lhs=v222, rhs_imm=0 } -> x0 - terminator Bz { cond=v223, target=b85, fall=b84 } (exit_acc=v223) - block 82 start_pc=0 - v232 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v232) - block 83 start_pc=0 - v233 Imm(32767) -> x0 - v234 Imm(0) -> x1 - terminator Jmp(b86) (exit_acc=v233) - block 84 start_pc=0 + terminator Jmp(b40) (exit_acc=v212) + block 185 start_pc=0 + terminator Jmp(b40) + block 186 start_pc=0 v224 ImmData(1480) -> x0 v225 Imm(122) -> x3 v226 Store { addr=v224, disp=0, value=v225, kind=I32 } -> - @@ -467,22 +934,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v229 ImmData(496) -> x6 v230 Imm(88) -> x2 v231 CallExt { binding_idx=1, args=[v228, v229, v230, v225], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b85) (exit_acc=v231) - block 85 start_pc=0 - terminator Jmp(b82) - block 86 start_pc=0 - v235 LoadLocal { off=-5, kind=I16 } -> x1 - v236 BinopI { op=eq, lhs=v233, rhs_imm=32767 } -> x0 - v237 BinopI { op=eq, lhs=v236, rhs_imm=0 } -> x0 - terminator Bz { cond=v237, target=b90, fall=b89 } (exit_acc=v237) - block 87 start_pc=0 - v246 Imm(0) -> x0 - terminator Jmp(b88) (exit_acc=v246) - block 88 start_pc=0 - v247 Imm(-32768) -> x3 - v248 Imm(0) -> x0 - terminator Jmp(b91) (exit_acc=v247) - block 89 start_pc=0 + terminator Jmp(b43) (exit_acc=v231) + block 187 start_pc=0 + terminator Jmp(b43) + block 188 start_pc=0 v238 ImmData(1480) -> x0 v239 Imm(123) -> x3 v240 Store { addr=v238, disp=0, value=v239, kind=I32 } -> - @@ -491,53 +946,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v243 ImmData(523) -> x6 v244 Imm(91) -> x2 v245 CallExt { binding_idx=1, args=[v242, v243, v244, v239], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b90) (exit_acc=v245) - block 90 start_pc=0 - terminator Jmp(b87) - block 91 start_pc=0 - v249 LoadLocal { off=-6, kind=I16 } -> x0 - v250 BinopI { op=eq, lhs=v247, rhs_imm=-32768 } -> x0 - v251 BinopI { op=eq, lhs=v250, rhs_imm=0 } -> x0 - terminator Bz { cond=v251, target=b95, fall=b94 } (exit_acc=v251) - block 92 start_pc=0 - v260 Imm(0) -> x0 - terminator Jmp(b93) (exit_acc=v260) - block 93 start_pc=0 - v261 LoadLocal { off=-6, kind=I16 } -> x0 - v262 BinopI { op=and, lhs=v247, rhs_imm=65535 } -> x0 - v263 Imm(0) -> x1 - terminator Jmp(b96) (exit_acc=v262) - block 94 start_pc=0 + terminator Jmp(b46) (exit_acc=v245) + block 189 start_pc=0 + terminator Jmp(b46) + block 190 start_pc=0 v252 ImmData(1480) -> x0 - v253 Imm(124) -> x12 + v253 Imm(124) -> x3 v254 Store { addr=v252, disp=0, value=v253, kind=I32 } -> - v255 Imm(2) -> x7 v256 Call { target_pc=0, args=[v255], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v257 ImmData(550) -> x6 v258 Imm(93) -> x2 v259 CallExt { binding_idx=1, args=[v256, v257, v258, v253], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b95) (exit_acc=v259) - block 95 start_pc=0 - terminator Jmp(b92) - block 96 start_pc=0 - v264 BinopI { op=and, lhs=v262, rhs_imm=65535 } -> x0 - v265 BinopI { op=xor, lhs=v264, rhs_imm=32768 } -> x0 - v266 BinopI { op=and, lhs=v265, rhs_imm=4294967295 } -> x0 - v267 BinopI { op=eq, lhs=v266, rhs_imm=0 } -> x0 - v268 BinopI { op=eq, lhs=v267, rhs_imm=0 } -> x0 - terminator Bz { cond=v268, target=b100, fall=b99 } (exit_acc=v268) - block 97 start_pc=0 - v277 Imm(0) -> x0 - terminator Jmp(b98) (exit_acc=v277) - block 98 start_pc=0 - v278 Imm(74565) -> x0 - v279 Imm(0) -> x1 - v280 LoadLocal { off=-8, kind=I32 } -> x1 - v281 BinopI { op=shl, lhs=v278, rhs_imm=48 } -> x1 - v282 Extend { value=v278, kind=I16 } -> x0 - v283 Imm(0) -> x1 - terminator Jmp(b101) (exit_acc=v282) - block 99 start_pc=0 + terminator Jmp(b49) (exit_acc=v259) + block 191 start_pc=0 + terminator Jmp(b49) + block 192 start_pc=0 v269 ImmData(1480) -> x0 v270 Imm(125) -> x3 v271 Store { addr=v269, disp=0, value=v270, kind=I32 } -> - @@ -546,24 +970,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v274 ImmData(577) -> x6 v275 Imm(95) -> x2 v276 CallExt { binding_idx=1, args=[v273, v274, v275, v270], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b100) (exit_acc=v276) - block 100 start_pc=0 - terminator Jmp(b97) - block 101 start_pc=0 - v284 LoadLocal { off=-9, kind=I16 } -> x1 - v285 BinopI { op=eq, lhs=v282, rhs_imm=9029 } -> x0 - v286 BinopI { op=eq, lhs=v285, rhs_imm=0 } -> x0 - terminator Bz { cond=v286, target=b105, fall=b104 } (exit_acc=v286) - block 102 start_pc=0 - v295 Imm(0) -> x0 - terminator Jmp(b103) (exit_acc=v295) - block 103 start_pc=0 - v296 Imm(-42) -> x0 - v297 Imm(0) -> x1 - v298 LoadLocal { off=-10, kind=I16 } -> x1 - v299 Imm(0) -> x1 - terminator Jmp(b106) (exit_acc=v296) - block 104 start_pc=0 + terminator Jmp(b52) (exit_acc=v276) + block 193 start_pc=0 + terminator Jmp(b52) + block 194 start_pc=0 v287 ImmData(1480) -> x0 v288 Imm(126) -> x3 v289 Store { addr=v287, disp=0, value=v288, kind=I32 } -> - @@ -572,24 +982,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v292 ImmData(604) -> x6 v293 Imm(100) -> x2 v294 CallExt { binding_idx=1, args=[v291, v292, v293, v288], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b105) (exit_acc=v294) - block 105 start_pc=0 - terminator Jmp(b102) - block 106 start_pc=0 - v300 Extend { value=v296, kind=I32 } -> x0 - v301 BinopI { op=eq, lhs=v300, rhs_imm=-42 } -> x0 - v302 BinopI { op=eq, lhs=v301, rhs_imm=0 } -> x0 - terminator Bz { cond=v302, target=b110, fall=b109 } (exit_acc=v302) - block 107 start_pc=0 - v311 Imm(0) -> x0 - terminator Jmp(b108) (exit_acc=v311) - block 108 start_pc=0 - v312 Imm(65535) -> x3 - v313 Imm(0) -> x0 - v314 LoadLocal { off=-12, kind=U16 } -> x0 - v315 Imm(0) -> x0 - terminator Jmp(b111) (exit_acc=v312) - block 109 start_pc=0 + terminator Jmp(b55) (exit_acc=v294) + block 195 start_pc=0 + terminator Jmp(b55) + block 196 start_pc=0 v303 ImmData(1480) -> x0 v304 Imm(127) -> x3 v305 Store { addr=v303, disp=0, value=v304, kind=I32 } -> - @@ -598,46 +994,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v308 ImmData(631) -> x6 v309 Imm(105) -> x2 v310 CallExt { binding_idx=1, args=[v307, v308, v309, v304], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b110) (exit_acc=v310) - block 110 start_pc=0 - terminator Jmp(b107) - block 111 start_pc=0 - v316 BinopI { op=and, lhs=v312, rhs_imm=4294967295 } -> x0 - v317 BinopI { op=xor, lhs=v316, rhs_imm=65535 } -> x0 - v318 BinopI { op=and, lhs=v317, rhs_imm=4294967295 } -> x0 - v319 BinopI { op=eq, lhs=v318, rhs_imm=0 } -> x0 - v320 BinopI { op=eq, lhs=v319, rhs_imm=0 } -> x0 - terminator Bz { cond=v320, target=b115, fall=b114 } (exit_acc=v320) - block 112 start_pc=0 - v329 Imm(0) -> x0 - terminator Jmp(b113) (exit_acc=v329) - block 113 start_pc=0 - terminator Jmp(b116) - block 114 start_pc=0 + terminator Jmp(b58) (exit_acc=v310) + block 197 start_pc=0 + terminator Jmp(b58) + block 198 start_pc=0 + terminator Jmp(b62) + block 199 start_pc=0 v321 ImmData(1480) -> x0 - v322 Imm(128) -> x12 + v322 Imm(128) -> x3 v323 Store { addr=v321, disp=0, value=v322, kind=I32 } -> - v324 Imm(2) -> x7 v325 Call { target_pc=0, args=[v324], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v326 ImmData(658) -> x6 v327 Imm(110) -> x2 v328 CallExt { binding_idx=1, args=[v325, v326, v327, v322], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b115) (exit_acc=v328) - block 115 start_pc=0 - terminator Jmp(b112) - block 116 start_pc=0 - v330 LoadLocal { off=-12, kind=U16 } -> x0 - v331 BinopI { op=eq, lhs=v312, rhs_imm=65535 } -> x0 - v332 BinopI { op=eq, lhs=v331, rhs_imm=0 } -> x0 - terminator Bz { cond=v332, target=b120, fall=b119 } (exit_acc=v332) - block 117 start_pc=0 - v341 Imm(0) -> x0 - terminator Jmp(b118) (exit_acc=v341) - block 118 start_pc=0 - v342 Imm(4294967295) -> x3 - v343 Imm(0) -> x0 - terminator Jmp(b121) (exit_acc=v342) - block 119 start_pc=0 + terminator Jmp(b61) (exit_acc=v328) + block 200 start_pc=0 + terminator Jmp(b61) + block 201 start_pc=0 v333 ImmData(1480) -> x0 v334 Imm(129) -> x3 v335 Store { addr=v333, disp=0, value=v334, kind=I32 } -> - @@ -646,50 +1020,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v338 ImmData(685) -> x6 v339 Imm(112) -> x2 v340 CallExt { binding_idx=1, args=[v337, v338, v339, v334], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b120) (exit_acc=v340) - block 120 start_pc=0 - terminator Jmp(b117) - block 121 start_pc=0 - v344 LoadLocal { off=-14, kind=U32 } -> x0 - v345 BinopI { op=eq, lhs=v342, rhs_imm=4294967295 } -> x0 - v346 BinopI { op=eq, lhs=v345, rhs_imm=0 } -> x0 - terminator Bz { cond=v346, target=b125, fall=b124 } (exit_acc=v346) - block 122 start_pc=0 - v355 Imm(0) -> x0 - terminator Jmp(b123) (exit_acc=v355) - block 123 start_pc=0 - v356 LoadLocal { off=-14, kind=U32 } -> x0 - v357 BinopI { op=add, lhs=v342, rhs_imm=1 } -> x0 - v358 Imm(0) -> x1 - terminator Jmp(b126) (exit_acc=v357) - block 124 start_pc=0 + terminator Jmp(b63) (exit_acc=v340) + block 202 start_pc=0 + terminator Jmp(b63) + block 203 start_pc=0 v347 ImmData(1480) -> x0 - v348 Imm(130) -> x12 + v348 Imm(130) -> x3 v349 Store { addr=v347, disp=0, value=v348, kind=I32 } -> - v350 Imm(2) -> x7 v351 Call { target_pc=0, args=[v350], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v352 ImmData(712) -> x6 v353 Imm(118) -> x2 v354 CallExt { binding_idx=1, args=[v351, v352, v353, v348], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b125) (exit_acc=v354) - block 125 start_pc=0 - terminator Jmp(b122) - block 126 start_pc=0 - v359 BinopI { op=and, lhs=v357, rhs_imm=4294967295 } -> x0 - v360 BinopI { op=eq, lhs=v359, rhs_imm=0 } -> x0 - v361 BinopI { op=eq, lhs=v360, rhs_imm=0 } -> x0 - terminator Bz { cond=v361, target=b130, fall=b129 } (exit_acc=v361) - block 127 start_pc=0 - v370 Imm(0) -> x0 - terminator Jmp(b128) (exit_acc=v370) - block 128 start_pc=0 - v371 Imm(0) -> x0 - v372 Imm(0) -> x1 - v373 LoadLocal { off=-14, kind=U32 } -> x1 - v374 BinopI { op=add, lhs=v371, rhs_imm=-1 } -> x0 - v375 Imm(0) -> x1 - terminator Jmp(b131) (exit_acc=v374) - block 129 start_pc=0 + terminator Jmp(b66) (exit_acc=v354) + block 204 start_pc=0 + terminator Jmp(b66) + block 205 start_pc=0 v362 ImmData(1480) -> x0 v363 Imm(131) -> x3 v364 Store { addr=v362, disp=0, value=v363, kind=I32 } -> - @@ -698,22 +1044,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v367 ImmData(739) -> x6 v368 Imm(120) -> x2 v369 CallExt { binding_idx=1, args=[v366, v367, v368, v363], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b130) (exit_acc=v369) - block 130 start_pc=0 - terminator Jmp(b127) - block 131 start_pc=0 - v376 BinopI { op=and, lhs=v374, rhs_imm=4294967295 } -> x0 - v377 BinopI { op=eq, lhs=v376, rhs_imm=4294967295 } -> x0 - v378 BinopI { op=eq, lhs=v377, rhs_imm=0 } -> x0 - terminator Bz { cond=v378, target=b135, fall=b134 } (exit_acc=v378) - block 132 start_pc=0 - v387 Imm(0) -> x0 - terminator Jmp(b133) (exit_acc=v387) - block 133 start_pc=0 - v388 Imm(2147483647) -> x0 - v389 Imm(0) -> x1 - terminator Jmp(b136) (exit_acc=v388) - block 134 start_pc=0 + terminator Jmp(b69) (exit_acc=v369) + block 206 start_pc=0 + terminator Jmp(b69) + block 207 start_pc=0 v379 ImmData(1480) -> x0 v380 Imm(132) -> x3 v381 Store { addr=v379, disp=0, value=v380, kind=I32 } -> - @@ -722,47 +1056,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v384 ImmData(766) -> x6 v385 Imm(123) -> x2 v386 CallExt { binding_idx=1, args=[v383, v384, v385, v380], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b135) (exit_acc=v386) - block 135 start_pc=0 - terminator Jmp(b132) - block 136 start_pc=0 - v390 LoadLocal { off=-15, kind=I32 } -> x1 - v391 BinopI { op=eq, lhs=v388, rhs_imm=2147483647 } -> x0 - v392 BinopI { op=eq, lhs=v391, rhs_imm=0 } -> x0 - terminator Bz { cond=v392, target=b140, fall=b139 } (exit_acc=v392) - block 137 start_pc=0 - v401 Imm(0) -> x0 - terminator Jmp(b138) (exit_acc=v401) - block 138 start_pc=0 - v402 Imm(-2147483648) -> x3 - v403 Imm(-9223372036854775808) -> x0 - v404 Imm(0) -> x0 - terminator Jmp(b141) (exit_acc=v402) - block 139 start_pc=0 - v393 ImmData(1480) -> x0 - v394 Imm(133) -> x3 - v395 Store { addr=v393, disp=0, value=v394, kind=I32 } -> - - v396 Imm(2) -> x7 - v397 Call { target_pc=0, args=[v396], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v398 ImmData(793) -> x6 - v399 Imm(126) -> x2 - v400 CallExt { binding_idx=1, args=[v397, v398, v399, v394], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b140) (exit_acc=v400) - block 140 start_pc=0 - terminator Jmp(b137) - block 141 start_pc=0 - v405 LoadLocal { off=-16, kind=I32 } -> x0 - v406 BinopI { op=eq, lhs=v402, rhs_imm=-2147483648 } -> x0 - v407 BinopI { op=eq, lhs=v406, rhs_imm=0 } -> x0 - terminator Bz { cond=v407, target=b145, fall=b144 } (exit_acc=v407) - block 142 start_pc=0 - v416 Imm(0) -> x0 - terminator Jmp(b143) (exit_acc=v416) - block 143 start_pc=0 - v417 LoadLocal { off=-16, kind=I32 } -> x0 - v418 Imm(0) -> x0 - terminator Jmp(b146) (exit_acc=v402) - block 144 start_pc=0 + terminator Jmp(b72) (exit_acc=v386) + block 208 start_pc=0 + terminator Jmp(b72) + block 209 start_pc=0 + v393 ImmData(1480) -> x0 + v394 Imm(133) -> x3 + v395 Store { addr=v393, disp=0, value=v394, kind=I32 } -> - + v396 Imm(2) -> x7 + v397 Call { target_pc=0, args=[v396], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v398 ImmData(793) -> x6 + v399 Imm(126) -> x2 + v400 CallExt { binding_idx=1, args=[v397, v398, v399, v394], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b75) (exit_acc=v400) + block 210 start_pc=0 + terminator Jmp(b75) + block 211 start_pc=0 v408 ImmData(1480) -> x0 v409 Imm(134) -> x12 v410 Store { addr=v408, disp=0, value=v409, kind=I32 } -> - @@ -771,47 +1080,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v413 ImmData(820) -> x6 v414 Imm(128) -> x2 v415 CallExt { binding_idx=1, args=[v412, v413, v414, v409], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b145) (exit_acc=v415) - block 145 start_pc=0 - terminator Jmp(b142) - block 146 start_pc=0 - v419 LoadLocal { off=-17, kind=I64 } -> x0 - v420 BinopI { op=eq, lhs=v402, rhs_imm=-2147483648 } -> x0 - v421 BinopI { op=eq, lhs=v420, rhs_imm=0 } -> x0 - terminator Bz { cond=v421, target=b150, fall=b149 } (exit_acc=v421) - block 147 start_pc=0 - v430 Imm(0) -> x0 - terminator Jmp(b148) (exit_acc=v430) - block 148 start_pc=0 - v431 LoadLocal { off=-16, kind=I32 } -> x0 - v432 BinopI { op=and, lhs=v402, rhs_imm=4294967295 } -> x0 - v433 Imm(0) -> x1 - terminator Jmp(b151) (exit_acc=v432) - block 149 start_pc=0 + terminator Jmp(b78) (exit_acc=v415) + block 212 start_pc=0 + terminator Jmp(b78) + block 213 start_pc=0 v422 ImmData(1480) -> x0 - v423 Imm(135) -> x12 + v423 Imm(135) -> x3 v424 Store { addr=v422, disp=0, value=v423, kind=I32 } -> - v425 Imm(2) -> x7 v426 Call { target_pc=0, args=[v425], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v427 ImmData(847) -> x6 v428 Imm(134) -> x2 v429 CallExt { binding_idx=1, args=[v426, v427, v428, v423], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b150) (exit_acc=v429) - block 150 start_pc=0 - terminator Jmp(b147) - block 151 start_pc=0 - v434 LoadLocal { off=-18, kind=I64 } -> x1 - v435 BinopI { op=eq, lhs=v432, rhs_imm=2147483648 } -> x0 - v436 BinopI { op=eq, lhs=v435, rhs_imm=0 } -> x0 - terminator Bz { cond=v436, target=b155, fall=b154 } (exit_acc=v436) - block 152 start_pc=0 - v444 Imm(0) -> x0 - terminator Jmp(b153) (exit_acc=v444) - block 153 start_pc=0 - v445 Imm(-1) -> x3 - v446 Imm(0) -> x0 - terminator Jmp(b156) (exit_acc=v445) - block 154 start_pc=0 + terminator Jmp(b81) (exit_acc=v429) + block 214 start_pc=0 + terminator Jmp(b81) + block 215 start_pc=0 v437 ImmData(1480) -> x0 v438 Imm(136) -> x3 v439 Store { addr=v437, disp=0, value=v438, kind=I32 } -> - @@ -819,72 +1103,34 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v441 Call { target_pc=0, args=[v440], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v442 ImmData(874) -> x6 v443 CallExt { binding_idx=1, args=[v441, v442, v438, v438], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b155) (exit_acc=v443) - block 155 start_pc=0 - terminator Jmp(b152) - block 156 start_pc=0 - v447 LoadLocal { off=-19, kind=I64 } -> x0 - v448 BinopI { op=eq, lhs=v445, rhs_imm=-1 } -> x0 - v449 BinopI { op=eq, lhs=v448, rhs_imm=0 } -> x0 - terminator Bz { cond=v449, target=b160, fall=b159 } (exit_acc=v449) - block 157 start_pc=0 - v458 Imm(0) -> x0 - terminator Jmp(b158) (exit_acc=v458) - block 158 start_pc=0 - v459 LoadLocal { off=-19, kind=I64 } -> x0 - v460 BinopI { op=add, lhs=v445, rhs_imm=1 } -> x3 - v461 Imm(0) -> x0 - terminator Jmp(b161) (exit_acc=v460) - block 159 start_pc=0 + terminator Jmp(b84) (exit_acc=v443) + block 216 start_pc=0 + terminator Jmp(b84) + block 217 start_pc=0 v450 ImmData(1480) -> x0 - v451 Imm(140) -> x12 + v451 Imm(140) -> x3 v452 Store { addr=v450, disp=0, value=v451, kind=I32 } -> - v453 Imm(2) -> x7 v454 Call { target_pc=0, args=[v453], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v455 ImmData(901) -> x6 v456 Imm(142) -> x2 v457 CallExt { binding_idx=1, args=[v454, v455, v456, v451], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b160) (exit_acc=v457) - block 160 start_pc=0 - terminator Jmp(b157) - block 161 start_pc=0 - v462 LoadLocal { off=-19, kind=I64 } -> x0 - v463 BinopI { op=eq, lhs=v460, rhs_imm=0 } -> x0 - v464 BinopI { op=eq, lhs=v463, rhs_imm=0 } -> x0 - terminator Bz { cond=v464, target=b165, fall=b164 } (exit_acc=v464) - block 162 start_pc=0 - v473 Imm(0) -> x0 - terminator Jmp(b163) (exit_acc=v473) - block 163 start_pc=0 - v474 LoadLocal { off=-19, kind=I64 } -> x0 - v475 BinopI { op=add, lhs=v460, rhs_imm=-1 } -> x0 - v476 Imm(0) -> x1 - terminator Jmp(b166) (exit_acc=v475) - block 164 start_pc=0 + terminator Jmp(b87) (exit_acc=v457) + block 218 start_pc=0 + terminator Jmp(b87) + block 219 start_pc=0 v465 ImmData(1480) -> x0 - v466 Imm(141) -> x12 + v466 Imm(141) -> x3 v467 Store { addr=v465, disp=0, value=v466, kind=I32 } -> - v468 Imm(2) -> x7 v469 Call { target_pc=0, args=[v468], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v470 ImmData(928) -> x6 v471 Imm(144) -> x2 v472 CallExt { binding_idx=1, args=[v469, v470, v471, v466], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b165) (exit_acc=v472) - block 165 start_pc=0 - terminator Jmp(b162) - block 166 start_pc=0 - v477 LoadLocal { off=-19, kind=I64 } -> x1 - v478 BinopI { op=eq, lhs=v475, rhs_imm=-1 } -> x0 - v479 BinopI { op=eq, lhs=v478, rhs_imm=0 } -> x0 - terminator Bz { cond=v479, target=b170, fall=b169 } (exit_acc=v479) - block 167 start_pc=0 - v488 Imm(0) -> x0 - terminator Jmp(b168) (exit_acc=v488) - block 168 start_pc=0 - v489 Imm(9223372036854775807) -> x0 - v490 Imm(0) -> x1 - terminator Jmp(b171) (exit_acc=v489) - block 169 start_pc=0 + terminator Jmp(b90) (exit_acc=v472) + block 220 start_pc=0 + terminator Jmp(b90) + block 221 start_pc=0 v480 ImmData(1480) -> x0 v481 Imm(142) -> x3 v482 Store { addr=v480, disp=0, value=v481, kind=I32 } -> - @@ -893,22 +1139,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v485 ImmData(955) -> x6 v486 Imm(146) -> x2 v487 CallExt { binding_idx=1, args=[v484, v485, v486, v481], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b170) (exit_acc=v487) - block 170 start_pc=0 - terminator Jmp(b167) - block 171 start_pc=0 - v491 LoadLocal { off=-20, kind=I64 } -> x1 - v492 BinopI { op=eq, lhs=v489, rhs_imm=9223372036854775807 } -> x0 - v493 BinopI { op=eq, lhs=v492, rhs_imm=0 } -> x0 - terminator Bz { cond=v493, target=b175, fall=b174 } (exit_acc=v493) - block 172 start_pc=0 - v502 Imm(0) -> x0 - terminator Jmp(b173) (exit_acc=v502) - block 173 start_pc=0 - v503 Imm(-1) -> x0 - v504 Imm(0) -> x1 - terminator Jmp(b176) (exit_acc=v503) - block 174 start_pc=0 + terminator Jmp(b93) (exit_acc=v487) + block 222 start_pc=0 + terminator Jmp(b93) + block 223 start_pc=0 v494 ImmData(1480) -> x0 v495 Imm(143) -> x3 v496 Store { addr=v494, disp=0, value=v495, kind=I32 } -> - @@ -917,23 +1151,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v499 ImmData(982) -> x6 v500 Imm(149) -> x2 v501 CallExt { binding_idx=1, args=[v498, v499, v500, v495], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b175) (exit_acc=v501) - block 175 start_pc=0 - terminator Jmp(b172) - block 176 start_pc=0 - v505 LoadLocal { off=-21, kind=I64 } -> x1 - v506 BinopI { op=shr, lhs=v503, rhs_imm=1 } -> x0 - v507 BinopI { op=eq, lhs=v506, rhs_imm=-1 } -> x0 - v508 BinopI { op=eq, lhs=v507, rhs_imm=0 } -> x0 - terminator Bz { cond=v508, target=b180, fall=b179 } (exit_acc=v508) - block 177 start_pc=0 - v517 Imm(0) -> x0 - terminator Jmp(b178) (exit_acc=v517) - block 178 start_pc=0 - v518 Imm(-9223372036854775808) -> x0 - v519 Imm(0) -> x1 - terminator Jmp(b181) (exit_acc=v518) - block 179 start_pc=0 + terminator Jmp(b96) (exit_acc=v501) + block 224 start_pc=0 + terminator Jmp(b96) + block 225 start_pc=0 v509 ImmData(1480) -> x0 v510 Imm(144) -> x3 v511 Store { addr=v509, disp=0, value=v510, kind=I32 } -> - @@ -942,23 +1163,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v514 ImmData(1009) -> x6 v515 Imm(154) -> x2 v516 CallExt { binding_idx=1, args=[v513, v514, v515, v510], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b180) (exit_acc=v516) - block 180 start_pc=0 - terminator Jmp(b177) - block 181 start_pc=0 - v520 LoadLocal { off=-22, kind=I64 } -> x1 - v521 BinopI { op=shru, lhs=v518, rhs_imm=1 } -> x0 - v522 BinopI { op=eq, lhs=v521, rhs_imm=4611686018427387904 } -> x0 - v523 BinopI { op=eq, lhs=v522, rhs_imm=0 } -> x0 - terminator Bz { cond=v523, target=b185, fall=b184 } (exit_acc=v523) - block 182 start_pc=0 - v532 Imm(0) -> x0 - terminator Jmp(b183) (exit_acc=v532) - block 183 start_pc=0 - v533 Imm(-1) -> x0 - v534 Imm(0) -> x1 - terminator Jmp(b186) (exit_acc=v533) - block 184 start_pc=0 + terminator Jmp(b99) (exit_acc=v516) + block 226 start_pc=0 + terminator Jmp(b99) + block 227 start_pc=0 v524 ImmData(1480) -> x0 v525 Imm(145) -> x3 v526 Store { addr=v524, disp=0, value=v525, kind=I32 } -> - @@ -967,27 +1175,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v529 ImmData(1036) -> x6 v530 Imm(157) -> x2 v531 CallExt { binding_idx=1, args=[v528, v529, v530, v525], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b185) (exit_acc=v531) - block 185 start_pc=0 - terminator Jmp(b182) - block 186 start_pc=0 - v535 LoadLocal { off=-23, kind=I64 } -> x1 - v536 BinopI { op=shru, lhs=v533, rhs_imm=32 } -> x0 - v537 BinopI { op=eq, lhs=v536, rhs_imm=4294967295 } -> x0 - v538 BinopI { op=eq, lhs=v537, rhs_imm=0 } -> x0 - terminator Bz { cond=v538, target=b190, fall=b189 } (exit_acc=v538) - block 187 start_pc=0 - v547 Imm(0) -> x0 - terminator Jmp(b188) (exit_acc=v547) - block 188 start_pc=0 - v548 Imm(-300) -> x3 - v549 Imm(0) -> x0 - v550 LoadLocal { off=-24, kind=I32 } -> x0 - v551 BinopI { op=shl, lhs=v548, rhs_imm=56 } -> x0 - v552 Extend { value=v548, kind=I8 } -> x12 - v553 Imm(0) -> x0 - terminator Jmp(b191) (exit_acc=v552) - block 189 start_pc=0 + terminator Jmp(b102) (exit_acc=v531) + block 228 start_pc=0 + terminator Jmp(b102) + block 229 start_pc=0 v539 ImmData(1480) -> x0 v540 Imm(146) -> x3 v541 Store { addr=v539, disp=0, value=v540, kind=I32 } -> - @@ -996,100 +1187,50 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v544 ImmData(1063) -> x6 v545 Imm(160) -> x2 v546 CallExt { binding_idx=1, args=[v543, v544, v545, v540], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b190) (exit_acc=v546) - block 190 start_pc=0 - terminator Jmp(b187) - block 191 start_pc=0 - v554 LoadLocal { off=-25, kind=I8 } -> x0 - v555 Imm(212) -> x0 - v556 Imm(-3170534137668829184) -> x0 - v557 Imm(-44) -> x0 - v558 BinopI { op=eq, lhs=v552, rhs_imm=-44 } -> x0 - v559 BinopI { op=eq, lhs=v558, rhs_imm=0 } -> x0 - terminator Bz { cond=v559, target=b195, fall=b194 } (exit_acc=v559) - block 192 start_pc=0 - v568 Imm(0) -> x0 - terminator Jmp(b193) (exit_acc=v568) - block 193 start_pc=0 - terminator Jmp(b196) - block 194 start_pc=0 + terminator Jmp(b105) (exit_acc=v546) + block 230 start_pc=0 + terminator Jmp(b105) + block 231 start_pc=0 + terminator Jmp(b109) + block 232 start_pc=0 v560 ImmData(1480) -> x0 - v561 Imm(150) -> x13 + v561 Imm(150) -> x3 v562 Store { addr=v560, disp=0, value=v561, kind=I32 } -> - v563 Imm(2) -> x7 v564 Call { target_pc=0, args=[v563], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v565 ImmData(1090) -> x6 v566 Imm(169) -> x2 v567 CallExt { binding_idx=1, args=[v564, v565, v566, v561], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b195) (exit_acc=v567) - block 195 start_pc=0 - terminator Jmp(b192) - block 196 start_pc=0 - v569 LoadLocal { off=-25, kind=I8 } -> x0 - v570 BinopI { op=eq, lhs=v552, rhs_imm=-44 } -> x0 - v571 BinopI { op=eq, lhs=v570, rhs_imm=0 } -> x0 - terminator Bz { cond=v571, target=b200, fall=b199 } (exit_acc=v571) - block 197 start_pc=0 - v580 Imm(0) -> x0 - terminator Jmp(b198) (exit_acc=v580) - block 198 start_pc=0 - v581 LoadLocal { off=-24, kind=I32 } -> x0 - v582 BinopI { op=and, lhs=v548, rhs_imm=255 } -> x3 - v583 Imm(0) -> x0 - terminator Jmp(b201) (exit_acc=v582) - block 199 start_pc=0 + terminator Jmp(b108) (exit_acc=v567) + block 233 start_pc=0 + terminator Jmp(b108) + block 234 start_pc=0 v572 ImmData(1480) -> x0 - v573 Imm(151) -> x12 + v573 Imm(151) -> x3 v574 Store { addr=v572, disp=0, value=v573, kind=I32 } -> - v575 Imm(2) -> x7 v576 Call { target_pc=0, args=[v575], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v577 ImmData(1117) -> x6 v578 Imm(170) -> x2 v579 CallExt { binding_idx=1, args=[v576, v577, v578, v573], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b200) (exit_acc=v579) - block 200 start_pc=0 - terminator Jmp(b197) - block 201 start_pc=0 - v584 BinopI { op=and, lhs=v582, rhs_imm=255 } -> x0 - v585 BinopI { op=xor, lhs=v584, rhs_imm=212 } -> x0 - v586 BinopI { op=and, lhs=v585, rhs_imm=4294967295 } -> x0 - v587 BinopI { op=eq, lhs=v586, rhs_imm=0 } -> x0 - v588 BinopI { op=eq, lhs=v587, rhs_imm=0 } -> x0 - terminator Bz { cond=v588, target=b205, fall=b204 } (exit_acc=v588) - block 202 start_pc=0 - v597 Imm(0) -> x0 - terminator Jmp(b203) (exit_acc=v597) - block 203 start_pc=0 - terminator Jmp(b206) - block 204 start_pc=0 + terminator Jmp(b110) (exit_acc=v579) + block 235 start_pc=0 + terminator Jmp(b110) + block 236 start_pc=0 + terminator Jmp(b114) + block 237 start_pc=0 v589 ImmData(1480) -> x0 - v590 Imm(152) -> x12 + v590 Imm(152) -> x3 v591 Store { addr=v589, disp=0, value=v590, kind=I32 } -> - v592 Imm(2) -> x7 v593 Call { target_pc=0, args=[v592], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v594 ImmData(1144) -> x6 v595 Imm(175) -> x2 v596 CallExt { binding_idx=1, args=[v593, v594, v595, v590], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b205) (exit_acc=v596) - block 205 start_pc=0 - terminator Jmp(b202) - block 206 start_pc=0 - v598 BinopI { op=and, lhs=v582, rhs_imm=255 } -> x0 - v599 BinopI { op=eq, lhs=v598, rhs_imm=212 } -> x0 - v600 BinopI { op=eq, lhs=v599, rhs_imm=0 } -> x0 - terminator Bz { cond=v600, target=b210, fall=b209 } (exit_acc=v600) - block 207 start_pc=0 - v609 Imm(0) -> x0 - terminator Jmp(b208) (exit_acc=v609) - block 208 start_pc=0 - v610 Imm(74565) -> x0 - v611 Imm(0) -> x1 - v612 LoadLocal { off=-24, kind=I32 } -> x1 - v613 BinopI { op=shl, lhs=v610, rhs_imm=48 } -> x1 - v614 Extend { value=v610, kind=I16 } -> x3 - v615 Imm(0) -> x0 - terminator Jmp(b211) (exit_acc=v614) - block 209 start_pc=0 + terminator Jmp(b113) (exit_acc=v596) + block 238 start_pc=0 + terminator Jmp(b113) + block 239 start_pc=0 v601 ImmData(1480) -> x0 v602 Imm(153) -> x3 v603 Store { addr=v601, disp=0, value=v602, kind=I32 } -> - @@ -1098,48 +1239,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v606 ImmData(1171) -> x6 v607 Imm(176) -> x2 v608 CallExt { binding_idx=1, args=[v605, v606, v607, v602], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b210) (exit_acc=v608) - block 210 start_pc=0 - terminator Jmp(b207) - block 211 start_pc=0 - v616 LoadLocal { off=-27, kind=I16 } -> x0 - v617 BinopI { op=eq, lhs=v614, rhs_imm=9029 } -> x0 - v618 BinopI { op=eq, lhs=v617, rhs_imm=0 } -> x0 - terminator Bz { cond=v618, target=b215, fall=b214 } (exit_acc=v618) - block 212 start_pc=0 - v627 Imm(0) -> x0 - terminator Jmp(b213) (exit_acc=v627) - block 213 start_pc=0 - terminator Jmp(b216) - block 214 start_pc=0 + terminator Jmp(b115) (exit_acc=v608) + block 240 start_pc=0 + terminator Jmp(b115) + block 241 start_pc=0 + terminator Jmp(b119) + block 242 start_pc=0 v619 ImmData(1480) -> x0 - v620 Imm(154) -> x12 + v620 Imm(154) -> x3 v621 Store { addr=v619, disp=0, value=v620, kind=I32 } -> - v622 Imm(2) -> x7 v623 Call { target_pc=0, args=[v622], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v624 ImmData(1198) -> x6 v625 Imm(181) -> x2 v626 CallExt { binding_idx=1, args=[v623, v624, v625, v620], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b215) (exit_acc=v626) - block 215 start_pc=0 - terminator Jmp(b212) - block 216 start_pc=0 - v628 LoadLocal { off=-27, kind=I16 } -> x0 - v629 BinopI { op=eq, lhs=v614, rhs_imm=9029 } -> x0 - v630 BinopI { op=eq, lhs=v629, rhs_imm=0 } -> x0 - terminator Bz { cond=v630, target=b220, fall=b219 } (exit_acc=v630) - block 217 start_pc=0 - v639 Imm(0) -> x0 - terminator Jmp(b218) (exit_acc=v639) - block 218 start_pc=0 - v640 Imm(131071) -> x0 - v641 Imm(0) -> x1 - v642 LoadLocal { off=-24, kind=I32 } -> x1 - v643 BinopI { op=shl, lhs=v640, rhs_imm=48 } -> x1 - v644 Extend { value=v640, kind=I16 } -> x3 - v645 Imm(0) -> x0 - terminator Jmp(b221) (exit_acc=v644) - block 219 start_pc=0 + terminator Jmp(b118) (exit_acc=v626) + block 243 start_pc=0 + terminator Jmp(b118) + block 244 start_pc=0 v631 ImmData(1480) -> x0 v632 Imm(155) -> x3 v633 Store { addr=v631, disp=0, value=v632, kind=I32 } -> - @@ -1148,46 +1265,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v636 ImmData(1225) -> x6 v637 Imm(182) -> x2 v638 CallExt { binding_idx=1, args=[v635, v636, v637, v632], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b220) (exit_acc=v638) - block 220 start_pc=0 - terminator Jmp(b217) - block 221 start_pc=0 - v646 LoadLocal { off=-27, kind=I16 } -> x0 - v647 BinopI { op=eq, lhs=v644, rhs_imm=-1 } -> x0 - v648 BinopI { op=eq, lhs=v647, rhs_imm=0 } -> x0 - terminator Bz { cond=v648, target=b225, fall=b224 } (exit_acc=v648) - block 222 start_pc=0 - v657 Imm(0) -> x0 - terminator Jmp(b223) (exit_acc=v657) - block 223 start_pc=0 - terminator Jmp(b226) - block 224 start_pc=0 + terminator Jmp(b120) (exit_acc=v638) + block 245 start_pc=0 + terminator Jmp(b120) + block 246 start_pc=0 + terminator Jmp(b124) + block 247 start_pc=0 v649 ImmData(1480) -> x0 - v650 Imm(156) -> x12 + v650 Imm(156) -> x3 v651 Store { addr=v649, disp=0, value=v650, kind=I32 } -> - v652 Imm(2) -> x7 v653 Call { target_pc=0, args=[v652], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v654 ImmData(1252) -> x6 v655 Imm(186) -> x2 v656 CallExt { binding_idx=1, args=[v653, v654, v655, v650], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b225) (exit_acc=v656) - block 225 start_pc=0 - terminator Jmp(b222) - block 226 start_pc=0 - v658 LoadLocal { off=-27, kind=I16 } -> x0 - v659 BinopI { op=eq, lhs=v644, rhs_imm=-1 } -> x0 - v660 BinopI { op=eq, lhs=v659, rhs_imm=0 } -> x0 - terminator Bz { cond=v660, target=b230, fall=b229 } (exit_acc=v660) - block 227 start_pc=0 - v669 Imm(0) -> x0 - terminator Jmp(b228) (exit_acc=v669) - block 228 start_pc=0 - v670 Imm(4294967295) -> x3 - v671 Imm(0) -> x0 - v672 Imm(1) -> x12 - v673 Imm(0) -> x0 - terminator Jmp(b231) (exit_acc=v672) - block 229 start_pc=0 + terminator Jmp(b123) (exit_acc=v656) + block 248 start_pc=0 + terminator Jmp(b123) + block 249 start_pc=0 v661 ImmData(1480) -> x0 v662 Imm(157) -> x3 v663 Store { addr=v661, disp=0, value=v662, kind=I32 } -> - @@ -1196,54 +1291,22 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v666 ImmData(1279) -> x6 v667 Imm(187) -> x2 v668 CallExt { binding_idx=1, args=[v665, v666, v667, v662], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b230) (exit_acc=v668) - block 230 start_pc=0 - terminator Jmp(b227) - block 231 start_pc=0 - v674 LoadLocal { off=-28, kind=U32 } -> x0 - v675 LoadLocal { off=-29, kind=U32 } -> x0 - v676 Binop { op=ugt, lhs=v670, rhs=v672 } -> x0 - v677 BinopI { op=eq, lhs=v676, rhs_imm=0 } -> x0 - terminator Bz { cond=v677, target=b235, fall=b234 } (exit_acc=v677) - block 232 start_pc=0 - v686 Imm(0) -> x0 - terminator Jmp(b233) (exit_acc=v686) - block 233 start_pc=0 - v687 LoadLocal { off=-28, kind=U32 } -> x0 - v688 BinopI { op=shl, lhs=v670, rhs_imm=32 } -> x0 - v689 Extend { value=v670, kind=I32 } -> x0 - v690 Imm(0) -> x1 - v691 LoadLocal { off=-29, kind=U32 } -> x1 - v692 BinopI { op=shl, lhs=v672, rhs_imm=32 } -> x1 - v693 Extend { value=v672, kind=I32 } -> x1 - v694 Imm(0) -> x2 - terminator Jmp(b236) (exit_acc=v693) - block 234 start_pc=0 + terminator Jmp(b125) (exit_acc=v668) + block 250 start_pc=0 + terminator Jmp(b125) + block 251 start_pc=0 v678 ImmData(1480) -> x0 - v679 Imm(160) -> x13 + v679 Imm(160) -> x3 v680 Store { addr=v678, disp=0, value=v679, kind=I32 } -> - v681 Imm(2) -> x7 v682 Call { target_pc=0, args=[v681], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v683 ImmData(1306) -> x6 v684 Imm(194) -> x2 v685 CallExt { binding_idx=1, args=[v682, v683, v684, v679], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b235) (exit_acc=v685) - block 235 start_pc=0 - terminator Jmp(b232) - block 236 start_pc=0 - v695 LoadLocal { off=-30, kind=I32 } -> x2 - v696 LoadLocal { off=-31, kind=I32 } -> x2 - v697 Binop { op=lt, lhs=v689, rhs=v693 } -> x0 - v698 BinopI { op=eq, lhs=v697, rhs_imm=0 } -> x0 - terminator Bz { cond=v698, target=b240, fall=b239 } (exit_acc=v698) - block 237 start_pc=0 - v707 Imm(0) -> x0 - terminator Jmp(b238) (exit_acc=v707) - block 238 start_pc=0 - v708 Imm(1) -> x0 - v709 Imm(0) -> x1 - terminator Jmp(b241) (exit_acc=v708) - block 239 start_pc=0 + terminator Jmp(b128) (exit_acc=v685) + block 252 start_pc=0 + terminator Jmp(b128) + block 253 start_pc=0 v699 ImmData(1480) -> x0 v700 Imm(161) -> x3 v701 Store { addr=v699, disp=0, value=v700, kind=I32 } -> - @@ -1252,25 +1315,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v704 ImmData(1333) -> x6 v705 Imm(197) -> x2 v706 CallExt { binding_idx=1, args=[v703, v704, v705, v700], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b240) (exit_acc=v706) - block 240 start_pc=0 - terminator Jmp(b237) - block 241 start_pc=0 - v710 LoadLocal { off=-32, kind=I32 } -> x1 - v711 BinopI { op=shl, lhs=v708, rhs_imm=30 } -> x0 - v712 BinopI { op=shl, lhs=v711, rhs_imm=32 } -> x1 - v713 Extend { value=v711, kind=I32 } -> x0 - v714 BinopI { op=eq, lhs=v713, rhs_imm=1073741824 } -> x0 - v715 BinopI { op=eq, lhs=v714, rhs_imm=0 } -> x0 - terminator Bz { cond=v715, target=b245, fall=b244 } (exit_acc=v715) - block 242 start_pc=0 - v724 Imm(0) -> x0 - terminator Jmp(b243) (exit_acc=v724) - block 243 start_pc=0 - v725 Imm(1) -> x0 - v726 Imm(0) -> x1 - terminator Jmp(b246) (exit_acc=v725) - block 244 start_pc=0 + terminator Jmp(b131) (exit_acc=v706) + block 254 start_pc=0 + terminator Jmp(b131) + block 255 start_pc=0 v716 ImmData(1480) -> x0 v717 Imm(170) -> x3 v718 Store { addr=v716, disp=0, value=v717, kind=I32 } -> - @@ -1279,24 +1327,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v721 ImmData(1360) -> x6 v722 Imm(205) -> x2 v723 CallExt { binding_idx=1, args=[v720, v721, v722, v717], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b245) (exit_acc=v723) - block 245 start_pc=0 - terminator Jmp(b242) - block 246 start_pc=0 - v727 LoadLocal { off=-33, kind=U32 } -> x1 - v728 BinopI { op=shl, lhs=v725, rhs_imm=31 } -> x0 - v729 BinopI { op=and, lhs=v728, rhs_imm=4294967295 } -> x0 - v730 BinopI { op=eq, lhs=v729, rhs_imm=2147483648 } -> x0 - v731 BinopI { op=eq, lhs=v730, rhs_imm=0 } -> x0 - terminator Bz { cond=v731, target=b250, fall=b249 } (exit_acc=v731) - block 247 start_pc=0 - v740 Imm(0) -> x0 - terminator Jmp(b248) (exit_acc=v740) - block 248 start_pc=0 - v741 Imm(-1) -> x0 - v742 Imm(0) -> x1 - terminator Jmp(b251) (exit_acc=v741) - block 249 start_pc=0 + terminator Jmp(b134) (exit_acc=v723) + block 256 start_pc=0 + terminator Jmp(b134) + block 257 start_pc=0 v732 ImmData(1480) -> x0 v733 Imm(171) -> x3 v734 Store { addr=v732, disp=0, value=v733, kind=I32 } -> - @@ -1305,22 +1339,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v737 ImmData(1387) -> x6 v738 Imm(207) -> x2 v739 CallExt { binding_idx=1, args=[v736, v737, v738, v733], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b250) (exit_acc=v739) - block 250 start_pc=0 - terminator Jmp(b247) - block 251 start_pc=0 - v743 LoadLocal { off=-34, kind=I32 } -> x1 - v744 BinopI { op=eq, lhs=v741, rhs_imm=-1 } -> x0 - v745 BinopI { op=eq, lhs=v744, rhs_imm=0 } -> x0 - terminator Bz { cond=v745, target=b255, fall=b254 } (exit_acc=v745) - block 252 start_pc=0 - v754 Imm(0) -> x0 - terminator Jmp(b253) (exit_acc=v754) - block 253 start_pc=0 - v755 Imm(4294967295) -> x0 - v756 Imm(0) -> x1 - terminator Jmp(b256) (exit_acc=v755) - block 254 start_pc=0 + terminator Jmp(b137) (exit_acc=v739) + block 258 start_pc=0 + terminator Jmp(b137) + block 259 start_pc=0 v746 ImmData(1480) -> x0 v747 Imm(172) -> x3 v748 Store { addr=v746, disp=0, value=v747, kind=I32 } -> - @@ -1329,23 +1351,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v751 ImmData(1414) -> x6 v752 Imm(211) -> x2 v753 CallExt { binding_idx=1, args=[v750, v751, v752, v747], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b255) (exit_acc=v753) - block 255 start_pc=0 - terminator Jmp(b252) - block 256 start_pc=0 - v757 LoadLocal { off=-35, kind=U32 } -> x1 - v758 BinopI { op=eq, lhs=v755, rhs_imm=4294967295 } -> x0 - v759 BinopI { op=eq, lhs=v758, rhs_imm=0 } -> x0 - terminator Bz { cond=v759, target=b260, fall=b259 } (exit_acc=v759) - block 257 start_pc=0 - v768 Imm(0) -> x0 - terminator Jmp(b258) (exit_acc=v768) - block 258 start_pc=0 - v769 ImmData(1480) -> x0 - v770 Load { addr=v769, disp=0, kind=I32 } -> x0 - v771 BinopI { op=eq, lhs=v770, rhs_imm=0 } -> x0 - terminator Bz { cond=v771, target=b262, fall=b261 } (exit_acc=v771) - block 259 start_pc=0 + terminator Jmp(b140) (exit_acc=v753) + block 260 start_pc=0 + terminator Jmp(b140) + block 261 start_pc=0 v760 ImmData(1480) -> x0 v761 Imm(173) -> x3 v762 Store { addr=v760, disp=0, value=v761, kind=I32 } -> - @@ -1354,18 +1363,9 @@ fn ent_pc=6 n_params=0 variadic=false locals=39 v765 ImmData(1441) -> x6 v766 Imm(213) -> x2 v767 CallExt { binding_idx=1, args=[v764, v765, v766, v761], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b260) (exit_acc=v767) - block 260 start_pc=0 - terminator Jmp(b257) - block 261 start_pc=0 - v772 ImmData(1468) -> x7 - v773 CallExt { binding_idx=0, args=[v772], fp_arg_mask=0x0 } -> x0 - v774 Imm(0) -> x0 - terminator Return(v774) (exit_acc=v774) + terminator Jmp(b143) (exit_acc=v767) block 262 start_pc=0 - v775 ImmData(1480) -> x0 - v776 Load { addr=v775, disp=0, kind=I32 } -> x0 - terminator Return(v776) (exit_acc=v776) + terminator Jmp(b143) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/integer_literal_suffix.ssa b/tests/snapshots/ssa/integer_literal_suffix.ssa index ee484c093..e200e3465 100644 --- a/tests/snapshots/ssa/integer_literal_suffix.ssa +++ b/tests/snapshots/ssa/integer_literal_suffix.ssa @@ -6,80 +6,78 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v0 AllocaInit(0) -> - v1 Imm(68719476736) -> x0 v2 Imm(68719476735) -> x0 - v3 Imm(0) -> x1 - v4 LoadLocal { off=-1, kind=I64 } -> x1 - v5 BinopI { op=ne, lhs=v2, rhs_imm=68719476735 } -> x0 - terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v6 Imm(11) -> x0 - terminator Return(v6) (exit_acc=v6) - block 2 start_pc=0 v7 Imm(36) -> x0 - v8 Imm(0) -> x1 - v9 Imm(1) -> x1 - v10 LoadLocal { off=-2, kind=I32 } -> x2 - v11 Binop { op=shl, lhs=v9, rhs=v7 } -> x0 - v12 BinopI { op=sub, lhs=v11, rhs_imm=1 } -> x0 - v13 Imm(0) -> x1 - v14 LoadLocal { off=-3, kind=I64 } -> x1 - v15 BinopI { op=ne, lhs=v12, rhs_imm=68719476735 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + v10 LoadLocal { off=-2, kind=I32 } -> x0 + v11 Imm(68719476736) -> x0 + v12 Imm(68719476735) -> x0 + v13 Imm(0) -> x0 + v14 LoadLocal { off=-3, kind=I64 } -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) + block 2 start_pc=0 + v17 Imm(4886718345) -> x0 + v18 Imm(0) -> x0 + v19 LoadLocal { off=-4, kind=I64 } -> x0 + v20 Imm(4886718346) -> x0 + v21 Imm(0) -> x0 + v22 LoadLocal { off=-5, kind=I64 } -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v23) block 3 start_pc=0 - v16 Imm(12) -> x0 - terminator Return(v16) (exit_acc=v16) + v25 Imm(-1) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-6, kind=I64 } -> x0 + v28 Imm(1) -> x1 + v29 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v28) block 4 start_pc=0 - v17 Imm(4886718345) -> x0 - v18 Imm(0) -> x1 - v19 LoadLocal { off=-4, kind=I64 } -> x1 - v20 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x0 - v21 Imm(0) -> x1 - v22 LoadLocal { off=-5, kind=I64 } -> x1 - v23 BinopI { op=ne, lhs=v20, rhs_imm=4886718346 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) + v30 LoadLocal { off=-6, kind=I64 } -> x0 + v31 Imm(0) -> x1 + v32 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v31) block 5 start_pc=0 - v24 Imm(13) -> x0 - terminator Return(v24) (exit_acc=v24) + v33 Phi { incoming=[b3:v28, b4:v31], kind=I64 } -> x1 + v34 LoadLocal { off=-8, kind=I64 } -> x0 + terminator Bz { cond=v33, target=b7, fall=b6 } (exit_acc=v33) block 6 start_pc=0 - v25 Imm(-1) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-6, kind=I64 } -> x1 - v28 BinopI { op=eq, lhs=v25, rhs_imm=-1 } -> x2 - v29 Imm(0) -> x1 - terminator Bz { cond=v28, target=b15, fall=b7 } (exit_acc=v28) + v35 Imm(14) -> x0 + terminator Return(v35) (exit_acc=v35) block 7 start_pc=0 - v30 LoadLocal { off=-6, kind=I64 } -> x1 - v31 BinopI { op=eq, lhs=v25, rhs_imm=4294967295 } -> x2 - v32 Imm(0) -> x1 - terminator Jmp(b8) (exit_acc=v31) + v36 LoadLocal { off=-6, kind=I64 } -> x0 + v37 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v33 Phi { incoming=[b15:v28, b7:v31], kind=I64 } -> x2 - v34 LoadLocal { off=-8, kind=I64 } -> x1 - terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) + v39 Imm(-1) -> x0 + v40 Imm(0) -> x0 + v41 LoadLocal { off=-7, kind=I64 } -> x0 + v42 Imm(0) -> x0 + v43 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v43) block 9 start_pc=0 - v35 Imm(14) -> x0 - terminator Return(v35) (exit_acc=v35) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) block 10 start_pc=0 - v36 LoadLocal { off=-6, kind=I64 } -> x1 - v37 BinopI { op=ne, lhs=v25, rhs_imm=-1 } -> x0 - terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) + v6 Imm(11) -> x0 + terminator Return(v6) (exit_acc=v6) block 11 start_pc=0 - v38 Imm(15) -> x0 - terminator Return(v38) (exit_acc=v38) + v16 Imm(12) -> x0 + terminator Return(v16) (exit_acc=v16) block 12 start_pc=0 - v39 Imm(-1) -> x0 - v40 Imm(0) -> x1 - v41 LoadLocal { off=-7, kind=I64 } -> x1 - v42 BinopI { op=add, lhs=v39, rhs_imm=1 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b14, fall=b13 } (exit_acc=v43) + v24 Imm(13) -> x0 + terminator Return(v24) (exit_acc=v24) block 13 start_pc=0 + v38 Imm(15) -> x0 + terminator Return(v38) (exit_acc=v38) + block 14 start_pc=0 v44 Imm(16) -> x0 terminator Return(v44) (exit_acc=v44) - block 14 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) - block 15 start_pc=0 - terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/integer_negate_shift_overflow.ssa b/tests/snapshots/ssa/integer_negate_shift_overflow.ssa index c27a971cd..83f63db2f 100644 --- a/tests/snapshots/ssa/integer_negate_shift_overflow.ssa +++ b/tests/snapshots/ssa/integer_negate_shift_overflow.ssa @@ -7,87 +7,87 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v1 Imm(2147483648) -> x0 v2 Imm(-9223372036854775808) -> x0 v3 Imm(-2147483648) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I32 } -> x1 - v6 BinopI { op=ne, lhs=v3, rhs_imm=-2147483648 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 Imm(2147483648) -> x0 v9 Imm(-9223372036854775808) -> x0 v10 Imm(-2147483648) -> x0 v11 Imm(-1) -> x0 v12 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v12) + terminator Jmp(b2) (exit_acc=v12) + block 2 start_pc=0 + v14 Imm(-2147483648) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-2, kind=I32 } -> x0 + v17 Imm(2147483648) -> x0 + v18 Imm(-9223372036854775808) -> x0 + v19 Imm(-2147483648) -> x0 + v20 Imm(0) -> x0 + v21 LoadLocal { off=-3, kind=I32 } -> x0 + v22 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v22) block 3 start_pc=0 - v13 Imm(2) -> x0 - terminator Return(v13) (exit_acc=v13) + v24 Imm(2147483647) -> x0 + v25 Imm(0) -> x0 + v26 LoadLocal { off=-4, kind=I32 } -> x0 + v27 Imm(-2147483647) -> x0 + v28 Imm(-9223372032559808512) -> x0 + v29 Imm(-2147483647) -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v30) block 4 start_pc=0 - v14 Imm(-2147483648) -> x0 - v15 Imm(0) -> x1 - v16 LoadLocal { off=-2, kind=I32 } -> x1 - v17 BinopI { op=mul, lhs=v14, rhs_imm=-1 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x0 - v20 Imm(0) -> x1 - v21 LoadLocal { off=-3, kind=I32 } -> x1 - v22 BinopI { op=ne, lhs=v19, rhs_imm=-2147483648 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v32 Imm(32768) -> x0 + v33 Imm(0) -> x0 + v34 LoadLocal { off=-5, kind=U16 } -> x0 + v35 Imm(2147483648) -> x0 + v36 Imm(-9223372036854775808) -> x0 + v37 Imm(-2147483648) -> x0 + v38 Imm(-32768) -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v39) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v41 Imm(0) -> x0 + v42 Imm(0) -> x0 + v43 LoadLocal { off=-6, kind=U32 } -> x0 + v44 Imm(0) -> x0 + v45 Imm(0) -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v46) block 6 start_pc=0 - v24 Imm(2147483647) -> x0 - v25 Imm(0) -> x1 - v26 LoadLocal { off=-4, kind=I32 } -> x1 - v27 BinopI { op=mul, lhs=v24, rhs_imm=-1 } -> x0 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 - v29 Extend { value=v27, kind=I32 } -> x0 - v30 BinopI { op=ne, lhs=v29, rhs_imm=-2147483647 } -> x0 - terminator Bz { cond=v30, target=b8, fall=b7 } (exit_acc=v30) + v48 Imm(1) -> x0 + v49 Imm(0) -> x0 + v50 LoadLocal { off=-7, kind=U32 } -> x0 + v51 Imm(-1) -> x0 + v52 Imm(4294967295) -> x0 + v53 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v53) block 7 start_pc=0 - v31 Imm(4) -> x0 - terminator Return(v31) (exit_acc=v31) + v55 Imm(0) -> x0 + terminator Return(v55) (exit_acc=v55) block 8 start_pc=0 - v32 Imm(32768) -> x0 - v33 Imm(0) -> x1 - v34 LoadLocal { off=-5, kind=U16 } -> x1 - v35 BinopI { op=shl, lhs=v32, rhs_imm=16 } -> x0 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x1 - v37 Extend { value=v35, kind=I32 } -> x0 - v38 BinopI { op=shr, lhs=v37, rhs_imm=16 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=-32768 } -> x0 - terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 9 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v13 Imm(2) -> x0 + terminator Return(v13) (exit_acc=v13) block 10 start_pc=0 - v41 Imm(0) -> x0 - v42 Imm(0) -> x1 - v43 LoadLocal { off=-6, kind=U32 } -> x1 - v44 BinopI { op=mul, lhs=v41, rhs_imm=-1 } -> x0 - v45 BinopI { op=and, lhs=v44, rhs_imm=4294967295 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=0 } -> x0 - terminator Bz { cond=v46, target=b12, fall=b11 } (exit_acc=v46) + v23 Imm(3) -> x0 + terminator Return(v23) (exit_acc=v23) block 11 start_pc=0 - v47 Imm(6) -> x0 - terminator Return(v47) (exit_acc=v47) + v31 Imm(4) -> x0 + terminator Return(v31) (exit_acc=v31) block 12 start_pc=0 - v48 Imm(1) -> x0 - v49 Imm(0) -> x1 - v50 LoadLocal { off=-7, kind=U32 } -> x1 - v51 BinopI { op=mul, lhs=v48, rhs_imm=-1 } -> x0 - v52 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x0 - v53 BinopI { op=ne, lhs=v52, rhs_imm=4294967295 } -> x0 - terminator Bz { cond=v53, target=b14, fall=b13 } (exit_acc=v53) + v40 Imm(5) -> x0 + terminator Return(v40) (exit_acc=v40) block 13 start_pc=0 + v47 Imm(6) -> x0 + terminator Return(v47) (exit_acc=v47) + block 14 start_pc=0 v54 Imm(7) -> x0 terminator Return(v54) (exit_acc=v54) - block 14 start_pc=0 - v55 Imm(0) -> x0 - terminator Return(v55) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/integer_ops_exhaustive.ssa b/tests/snapshots/ssa/integer_ops_exhaustive.ssa index 4576e2ccf..b5dd279c4 100644 --- a/tests/snapshots/ssa/integer_ops_exhaustive.ssa +++ b/tests/snapshots/ssa/integer_ops_exhaustive.ssa @@ -1,1082 +1,1082 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=32 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4294967294) -> x3 + v1 Imm(4294967294) -> x0 v2 Imm(0) -> x0 - v3 Imm(1) -> x12 - v4 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 v5 LoadLocal { off=-1, kind=U32 } -> x0 v6 LoadLocal { off=-2, kind=U32 } -> x0 - v7 Binop { op=ugt, lhs=v1, rhs=v3 } -> x0 - v8 BinopI { op=eq, lhs=v7, rhs_imm=0 } -> x0 - terminator Bz { cond=v8, target=b5, fall=b4 } (exit_acc=v8) + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) block 2 start_pc=0 v13 Imm(0) -> x0 terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - terminator Jmp(b6) + v14 LoadLocal { off=-2, kind=U32 } -> x0 + v15 LoadLocal { off=-1, kind=U32 } -> x0 + v16 Imm(1) -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 + v22 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 + v23 LoadLocal { off=-1, kind=U32 } -> x0 + v24 LoadLocal { off=-2, kind=U32 } -> x0 + v25 Imm(1) -> x0 + v26 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v26) + block 6 start_pc=0 + v31 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v31) + block 7 start_pc=0 + v32 LoadLocal { off=-2, kind=U32 } -> x0 + v33 LoadLocal { off=-1, kind=U32 } -> x0 + v34 Imm(1) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v35) + block 8 start_pc=0 + v40 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v40) + block 9 start_pc=0 + v41 LoadLocal { off=-1, kind=U32 } -> x0 + v42 LoadLocal { off=-2, kind=U32 } -> x0 + v43 Imm(1) -> x0 + v44 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v44) + block 10 start_pc=0 + v49 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v49) + block 11 start_pc=0 + v50 LoadLocal { off=-1, kind=U32 } -> x0 + v51 LoadLocal { off=-2, kind=U32 } -> x0 + v52 Imm(0) -> x0 + v53 Imm(1) -> x0 + v54 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v54) + block 12 start_pc=0 + v59 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v59) + block 13 start_pc=0 + v60 Imm(-2) -> x0 + v61 Imm(0) -> x0 + v62 Imm(1) -> x0 + v63 Imm(0) -> x1 + terminator Jmp(b14) (exit_acc=v62) + block 14 start_pc=0 + v64 LoadLocal { off=-3, kind=I32 } -> x0 + v65 LoadLocal { off=-4, kind=I32 } -> x0 + v66 Imm(1) -> x0 + v67 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v67) + block 15 start_pc=0 + v72 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v72) + block 16 start_pc=0 + v73 LoadLocal { off=-4, kind=I32 } -> x0 + v74 LoadLocal { off=-3, kind=I32 } -> x0 + v75 Imm(1) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v76) + block 17 start_pc=0 + v81 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v81) + block 18 start_pc=0 + v82 LoadLocal { off=-3, kind=I32 } -> x0 + v83 LoadLocal { off=-4, kind=I32 } -> x0 + v84 Imm(1) -> x0 + v85 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v85) + block 19 start_pc=0 + v90 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v90) + block 20 start_pc=0 + v91 LoadLocal { off=-4, kind=I32 } -> x0 + v92 LoadLocal { off=-3, kind=I32 } -> x0 + v93 Imm(1) -> x0 + v94 Imm(0) -> x0 + terminator Jmp(b21) (exit_acc=v94) + block 21 start_pc=0 + v99 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v99) + block 22 start_pc=0 + v100 Imm(-2) -> x0 + v101 Imm(0) -> x0 + v102 Imm(1) -> x0 + v103 Imm(0) -> x1 + terminator Jmp(b23) (exit_acc=v102) + block 23 start_pc=0 + v104 LoadLocal { off=-5, kind=I64 } -> x0 + v105 LoadLocal { off=-6, kind=I64 } -> x0 + v106 Imm(1) -> x0 + v107 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v107) + block 24 start_pc=0 + v112 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v112) + block 25 start_pc=0 + v113 LoadLocal { off=-5, kind=I64 } -> x0 + v114 LoadLocal { off=-6, kind=I64 } -> x0 + v115 Imm(1) -> x0 + v116 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v116) + block 26 start_pc=0 + v121 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v121) + block 27 start_pc=0 + v122 LoadLocal { off=-6, kind=I64 } -> x0 + v123 LoadLocal { off=-5, kind=I64 } -> x0 + v124 Imm(1) -> x0 + v125 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v125) + block 28 start_pc=0 + v130 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v130) + block 29 start_pc=0 + v131 Imm(-2) -> x0 + v132 Imm(0) -> x0 + v133 Imm(1) -> x0 + v134 Imm(0) -> x1 + terminator Jmp(b30) (exit_acc=v133) + block 30 start_pc=0 + v135 LoadLocal { off=-8, kind=I64 } -> x0 + v136 LoadLocal { off=-7, kind=I64 } -> x0 + v137 Imm(1) -> x0 + v138 Imm(0) -> x0 + terminator Jmp(b31) (exit_acc=v138) + block 31 start_pc=0 + v143 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v143) + block 32 start_pc=0 + v144 LoadLocal { off=-7, kind=I64 } -> x0 + v145 Imm(1) -> x0 + v146 Imm(0) -> x0 + terminator Jmp(b33) (exit_acc=v146) + block 33 start_pc=0 + v151 Imm(0) -> x0 + terminator Jmp(b34) (exit_acc=v151) + block 34 start_pc=0 + v152 Imm(254) -> x0 + v153 Imm(0) -> x0 + v154 Imm(1) -> x0 + v155 Imm(0) -> x1 + terminator Jmp(b35) (exit_acc=v154) + block 35 start_pc=0 + v156 LoadLocal { off=-9, kind=U8 } -> x0 + v157 LoadLocal { off=-10, kind=U8 } -> x0 + v158 Imm(1) -> x0 + v159 Imm(0) -> x0 + terminator Jmp(b36) (exit_acc=v159) + block 36 start_pc=0 + v164 Imm(0) -> x0 + terminator Jmp(b37) (exit_acc=v164) + block 37 start_pc=0 + v165 LoadLocal { off=-10, kind=U8 } -> x0 + v166 LoadLocal { off=-9, kind=U8 } -> x0 + v167 Imm(1) -> x0 + v168 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v168) + block 38 start_pc=0 + v173 Imm(0) -> x0 + terminator Jmp(b39) (exit_acc=v173) + block 39 start_pc=0 + v174 Imm(-2) -> x0 + v175 Imm(0) -> x0 + v176 Imm(1) -> x0 + v177 Imm(0) -> x1 + terminator Jmp(b40) (exit_acc=v176) + block 40 start_pc=0 + v178 LoadLocal { off=-11, kind=I8 } -> x0 + v179 LoadLocal { off=-12, kind=I8 } -> x0 + v180 Imm(1) -> x0 + v181 Imm(0) -> x0 + terminator Jmp(b41) (exit_acc=v181) + block 41 start_pc=0 + v186 Imm(0) -> x0 + terminator Jmp(b42) (exit_acc=v186) + block 42 start_pc=0 + v187 LoadLocal { off=-12, kind=I8 } -> x0 + v188 LoadLocal { off=-11, kind=I8 } -> x0 + v189 Imm(1) -> x0 + v190 Imm(0) -> x0 + terminator Jmp(b43) (exit_acc=v190) + block 43 start_pc=0 + v195 Imm(0) -> x0 + terminator Jmp(b44) (exit_acc=v195) + block 44 start_pc=0 + v196 Imm(100) -> x0 + v197 Imm(0) -> x0 + v198 LoadLocal { off=-13, kind=U32 } -> x0 + v199 Imm(105) -> x0 + v200 Imm(0) -> x0 + v201 Imm(105) -> x0 + terminator Jmp(b45) (exit_acc=v201) + block 45 start_pc=0 + v202 Imm(105) -> x0 + v203 Imm(0) -> x0 + v204 Imm(0) -> x0 + v205 Imm(1) -> x0 + v206 Imm(0) -> x0 + terminator Jmp(b46) (exit_acc=v206) + block 46 start_pc=0 + v211 Imm(0) -> x0 + terminator Jmp(b47) (exit_acc=v211) + block 47 start_pc=0 + v212 Imm(105) -> x0 + v213 Imm(95) -> x0 + v214 Imm(0) -> x0 + v215 Imm(95) -> x0 + terminator Jmp(b48) (exit_acc=v215) + block 48 start_pc=0 + v216 Imm(95) -> x0 + v217 Imm(0) -> x0 + v218 Imm(0) -> x0 + v219 Imm(1) -> x0 + v220 Imm(0) -> x0 + terminator Jmp(b49) (exit_acc=v220) + block 49 start_pc=0 + v225 Imm(0) -> x0 + terminator Jmp(b50) (exit_acc=v225) + block 50 start_pc=0 + v226 Imm(95) -> x0 + v227 Imm(190) -> x0 + v228 Imm(0) -> x0 + v229 Imm(190) -> x0 + terminator Jmp(b51) (exit_acc=v229) + block 51 start_pc=0 + v230 Imm(190) -> x0 + v231 Imm(0) -> x0 + v232 Imm(0) -> x0 + v233 Imm(1) -> x0 + v234 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v234) + block 52 start_pc=0 + v239 Imm(0) -> x0 + terminator Jmp(b53) (exit_acc=v239) + block 53 start_pc=0 + v240 Imm(190) -> x0 + v241 Imm(5) -> x0 + v242 Imm(38) -> x0 + v243 Imm(0) -> x0 + v244 Imm(38) -> x0 + terminator Jmp(b54) (exit_acc=v244) + block 54 start_pc=0 + v245 Imm(38) -> x0 + v246 Imm(0) -> x0 + v247 Imm(0) -> x0 + v248 Imm(1) -> x0 + v249 Imm(0) -> x0 + terminator Jmp(b55) (exit_acc=v249) + block 55 start_pc=0 + v254 Imm(0) -> x0 + terminator Jmp(b56) (exit_acc=v254) + block 56 start_pc=0 + v255 Imm(38) -> x0 + v256 Imm(7) -> x0 + v257 Imm(3) -> x0 + v258 Imm(0) -> x0 + v259 Imm(3) -> x0 + terminator Jmp(b57) (exit_acc=v259) + block 57 start_pc=0 + v260 Imm(3) -> x0 + v261 Imm(0) -> x0 + v262 Imm(0) -> x0 + v263 Imm(1) -> x0 + v264 Imm(0) -> x0 + terminator Jmp(b58) (exit_acc=v264) + block 58 start_pc=0 + v269 Imm(0) -> x0 + terminator Jmp(b59) (exit_acc=v269) + block 59 start_pc=0 + v270 Imm(1) -> x0 + v271 Imm(0) -> x0 + v272 LoadLocal { off=-14, kind=U32 } -> x0 + v273 Imm(-1) -> x0 + v274 Imm(4294967295) -> x0 + v275 Imm(0) -> x1 + terminator Jmp(b60) (exit_acc=v274) + block 60 start_pc=0 + v276 Imm(4294967295) -> x0 + v277 Imm(1) -> x0 + v278 Imm(0) -> x0 + terminator Jmp(b61) (exit_acc=v278) + block 61 start_pc=0 + v283 Imm(0) -> x0 + terminator Jmp(b62) (exit_acc=v283) + block 62 start_pc=0 + v284 Imm(1000) -> x0 + v285 Imm(0) -> x0 + v286 LoadLocal { off=-15, kind=I64 } -> x0 + v287 Imm(1415) -> x0 + v288 Imm(0) -> x1 + terminator Jmp(b63) (exit_acc=v287) + block 63 start_pc=0 + v289 LoadLocal { off=-15, kind=I64 } -> x0 + v290 Imm(1) -> x0 + v291 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v291) + block 64 start_pc=0 + v296 Imm(0) -> x0 + terminator Jmp(b65) (exit_acc=v296) + block 65 start_pc=0 + v297 LoadLocal { off=-15, kind=I64 } -> x0 + v298 Imm(4245) -> x0 + v299 Imm(0) -> x1 + terminator Jmp(b66) (exit_acc=v298) + block 66 start_pc=0 + v300 LoadLocal { off=-15, kind=I64 } -> x0 + v301 Imm(1) -> x0 + v302 Imm(0) -> x0 + terminator Jmp(b67) (exit_acc=v302) + block 67 start_pc=0 + v307 Imm(0) -> x0 + terminator Jmp(b68) (exit_acc=v307) + block 68 start_pc=0 + v308 LoadLocal { off=-15, kind=I64 } -> x0 + v309 Imm(5) -> x0 + v310 Imm(849) -> x0 + v311 Imm(0) -> x1 + terminator Jmp(b69) (exit_acc=v310) + block 69 start_pc=0 + v312 LoadLocal { off=-15, kind=I64 } -> x0 + v313 Imm(1) -> x0 + v314 Imm(0) -> x0 + terminator Jmp(b70) (exit_acc=v314) + block 70 start_pc=0 + v319 Imm(0) -> x0 + terminator Jmp(b71) (exit_acc=v319) + block 71 start_pc=0 + v320 Imm(4278255360) -> x0 + v321 Imm(0) -> x0 + v322 LoadLocal { off=-16, kind=U32 } -> x0 + v323 Imm(251662080) -> x0 + v324 Imm(0) -> x0 + v325 Imm(4279238400) -> x0 + v326 Imm(0) -> x0 + v327 Imm(16711935) -> x0 + v328 Imm(0) -> x0 + v329 Imm(-4278255361) -> x0 + v330 Imm(16711935) -> x0 + v331 Imm(0) -> x1 + terminator Jmp(b72) (exit_acc=v330) + block 72 start_pc=0 + v332 Imm(251662080) -> x0 + v333 Imm(0) -> x0 + v334 Imm(0) -> x0 + v335 Imm(1) -> x0 + v336 Imm(0) -> x0 + terminator Jmp(b73) (exit_acc=v336) + block 73 start_pc=0 + v341 Imm(0) -> x0 + terminator Jmp(b74) (exit_acc=v341) + block 74 start_pc=0 + v342 Imm(4279238400) -> x0 + v343 Imm(1) -> x0 + v344 Imm(0) -> x0 + terminator Jmp(b75) (exit_acc=v344) + block 75 start_pc=0 + v349 Imm(0) -> x0 + terminator Jmp(b76) (exit_acc=v349) + block 76 start_pc=0 + v350 Imm(16711935) -> x0 + v351 Imm(0) -> x0 + v352 Imm(0) -> x0 + v353 Imm(1) -> x0 + v354 Imm(0) -> x0 + terminator Jmp(b77) (exit_acc=v354) + block 77 start_pc=0 + v359 Imm(0) -> x0 + terminator Jmp(b78) (exit_acc=v359) + block 78 start_pc=0 + v360 Imm(16711935) -> x0 + v361 Imm(0) -> x0 + v362 Imm(0) -> x0 + v363 Imm(1) -> x0 + v364 Imm(0) -> x0 + terminator Jmp(b79) (exit_acc=v364) + block 79 start_pc=0 + v369 Imm(0) -> x0 + terminator Jmp(b80) (exit_acc=v369) + block 80 start_pc=0 + v370 Imm(305419896) -> x0 + v371 Imm(0) -> x0 + v372 LoadLocal { off=-21, kind=U32 } -> x0 + v373 Imm(4886718336) -> x0 + v374 Imm(591751040) -> x0 + v375 Imm(0) -> x1 + terminator Jmp(b81) (exit_acc=v374) + block 81 start_pc=0 + v376 Imm(591751040) -> x0 + v377 Imm(0) -> x0 + v378 Imm(0) -> x0 + v379 Imm(1) -> x0 + v380 Imm(0) -> x0 + terminator Jmp(b82) (exit_acc=v380) + block 82 start_pc=0 + v385 Imm(0) -> x0 + terminator Jmp(b83) (exit_acc=v385) + block 83 start_pc=0 + v386 Imm(1) -> x0 + v387 Imm(0) -> x0 + v388 LoadLocal { off=-23, kind=U32 } -> x0 + v389 Imm(2147483648) -> x0 + v390 Imm(2147483648) -> x0 + v391 Imm(0) -> x1 + terminator Jmp(b84) (exit_acc=v390) + block 84 start_pc=0 + v392 Imm(2147483648) -> x0 + v393 Imm(1) -> x0 + v394 Imm(0) -> x0 + terminator Jmp(b85) (exit_acc=v394) + block 85 start_pc=0 + v399 Imm(0) -> x0 + terminator Jmp(b86) (exit_acc=v399) + block 86 start_pc=0 + v400 Imm(1) -> x0 + v401 Imm(0) -> x1 + terminator Jmp(b87) (exit_acc=v400) + block 87 start_pc=0 + v402 LoadLocal { off=-25, kind=I64 } -> x0 + v403 Imm(-9223372036854775808) -> x0 + v404 Imm(1) -> x0 + v405 Imm(0) -> x0 + terminator Jmp(b88) (exit_acc=v405) + block 88 start_pc=0 + v410 Imm(0) -> x0 + terminator Jmp(b89) (exit_acc=v410) + block 89 start_pc=0 + v411 Imm(-1) -> x0 + v412 Imm(0) -> x0 + v413 Imm(1) -> x0 + v414 Imm(0) -> x1 + terminator Jmp(b90) (exit_acc=v413) + block 90 start_pc=0 + v415 LoadLocal { off=-26, kind=I32 } -> x0 + v416 Imm(4294967295) -> x0 + v417 LoadLocal { off=-27, kind=U32 } -> x0 + v418 Imm(1) -> x0 + v419 Imm(0) -> x0 + terminator Jmp(b91) (exit_acc=v419) + block 91 start_pc=0 + v424 Imm(0) -> x0 + terminator Jmp(b92) (exit_acc=v424) + block 92 start_pc=0 + v425 LoadLocal { off=-26, kind=I32 } -> x0 + v426 LoadLocal { off=-27, kind=U32 } -> x0 + v427 Imm(4294967296) -> x0 + v428 Imm(1) -> x0 + v429 Imm(1) -> x0 + v430 Imm(0) -> x0 + terminator Jmp(b93) (exit_acc=v430) + block 93 start_pc=0 + v435 Imm(0) -> x0 + terminator Jmp(b94) (exit_acc=v435) + block 94 start_pc=0 + v436 Imm(4294967294) -> x0 + v437 Imm(0) -> x0 + v438 LoadLocal { off=-28, kind=U32 } -> x0 + v439 Imm(4294967295) -> x0 + v440 Imm(0) -> x0 + v441 Imm(4294967295) -> x0 + terminator Jmp(b95) (exit_acc=v441) + block 95 start_pc=0 + v442 Imm(4294967295) -> x0 + v443 Imm(1) -> x0 + v444 Imm(0) -> x0 + terminator Jmp(b96) (exit_acc=v444) + block 96 start_pc=0 + v449 Imm(0) -> x0 + terminator Jmp(b97) (exit_acc=v449) + block 97 start_pc=0 + v450 Imm(4294967295) -> x0 + v451 Imm(4294967296) -> x0 + v452 Imm(0) -> x0 + v453 Imm(0) -> x0 + terminator Jmp(b98) (exit_acc=v453) + block 98 start_pc=0 + v454 Imm(0) -> x0 + v455 Imm(1) -> x0 + v456 Imm(0) -> x0 + terminator Jmp(b99) (exit_acc=v456) + block 99 start_pc=0 + v461 Imm(0) -> x0 + terminator Jmp(b100) (exit_acc=v461) + block 100 start_pc=0 + v462 Imm(254) -> x0 + v463 Imm(0) -> x0 + v464 LoadLocal { off=-29, kind=U8 } -> x0 + v465 Imm(255) -> x0 + v466 Imm(0) -> x0 + v467 Imm(255) -> x0 + terminator Jmp(b101) (exit_acc=v467) + block 101 start_pc=0 + v468 Imm(255) -> x0 + v469 Imm(0) -> x0 + v470 Imm(0) -> x0 + v471 Imm(1) -> x0 + v472 Imm(0) -> x0 + terminator Jmp(b102) (exit_acc=v472) + block 102 start_pc=0 + v477 Imm(0) -> x0 + terminator Jmp(b103) (exit_acc=v477) + block 103 start_pc=0 + v478 Imm(255) -> x0 + v479 Imm(256) -> x0 + v480 Imm(0) -> x0 + v481 Imm(0) -> x0 + terminator Jmp(b104) (exit_acc=v481) + block 104 start_pc=0 + v482 Imm(0) -> x0 + v483 Imm(1) -> x0 + v484 Imm(0) -> x0 + terminator Jmp(b105) (exit_acc=v484) + block 105 start_pc=0 + v489 Imm(0) -> x0 + terminator Jmp(b106) (exit_acc=v489) + block 106 start_pc=0 + v490 Imm(-2) -> x0 + v491 Imm(0) -> x0 + v492 LoadLocal { off=-30, kind=I64 } -> x0 + v493 Imm(-1) -> x0 + v494 Imm(0) -> x1 + terminator Jmp(b107) (exit_acc=v493) + block 107 start_pc=0 + v495 LoadLocal { off=-30, kind=I64 } -> x0 + v496 Imm(1) -> x0 + v497 Imm(0) -> x0 + terminator Jmp(b108) (exit_acc=v497) + block 108 start_pc=0 + v502 Imm(0) -> x0 + terminator Jmp(b109) (exit_acc=v502) + block 109 start_pc=0 + v503 LoadLocal { off=-30, kind=I64 } -> x0 + v504 Imm(0) -> x0 + v505 Imm(0) -> x1 + terminator Jmp(b110) (exit_acc=v504) + block 110 start_pc=0 + v506 LoadLocal { off=-30, kind=I64 } -> x0 + v507 Imm(1) -> x0 + v508 Imm(0) -> x0 + terminator Jmp(b111) (exit_acc=v508) + block 111 start_pc=0 + v513 Imm(0) -> x0 + terminator Jmp(b112) (exit_acc=v513) + block 112 start_pc=0 + v514 Imm(1) -> x0 + v515 Imm(0) -> x0 + terminator Jmp(b113) (exit_acc=v515) + block 113 start_pc=0 + v520 Imm(0) -> x0 + terminator Jmp(b114) (exit_acc=v520) + block 114 start_pc=0 + v521 Imm(1) -> x0 + v522 Imm(0) -> x0 + terminator Jmp(b115) (exit_acc=v522) + block 115 start_pc=0 + v527 Imm(0) -> x0 + terminator Jmp(b116) (exit_acc=v527) + block 116 start_pc=0 + v528 Imm(1) -> x0 + v529 Imm(0) -> x0 + terminator Jmp(b117) (exit_acc=v529) + block 117 start_pc=0 + v534 Imm(0) -> x0 + terminator Jmp(b118) (exit_acc=v534) + block 118 start_pc=0 + v535 Imm(1) -> x0 + v536 Imm(0) -> x0 + terminator Jmp(b119) (exit_acc=v536) + block 119 start_pc=0 + v541 Imm(0) -> x0 + terminator Jmp(b120) (exit_acc=v541) + block 120 start_pc=0 + v542 Imm(1) -> x0 + v543 Imm(0) -> x0 + terminator Jmp(b121) (exit_acc=v543) + block 121 start_pc=0 + v548 Imm(0) -> x0 + terminator Jmp(b122) (exit_acc=v548) + block 122 start_pc=0 + v549 Imm(1) -> x0 + v550 Imm(0) -> x0 + terminator Jmp(b123) (exit_acc=v550) + block 123 start_pc=0 + v555 Imm(0) -> x0 + terminator Jmp(b124) (exit_acc=v555) + block 124 start_pc=0 + v556 Imm(1) -> x0 + v557 Imm(0) -> x0 + terminator Jmp(b125) (exit_acc=v557) + block 125 start_pc=0 + v562 Imm(0) -> x0 + terminator Jmp(b126) (exit_acc=v562) + block 126 start_pc=0 + v563 Imm(1) -> x0 + v564 Imm(0) -> x0 + terminator Jmp(b127) (exit_acc=v564) + block 127 start_pc=0 + v569 Imm(0) -> x0 + terminator Jmp(b128) (exit_acc=v569) + block 128 start_pc=0 + v570 Imm(0) -> x0 + terminator Return(v570) (exit_acc=v570) + block 129 start_pc=0 + terminator Jmp(b3) + block 130 start_pc=0 v9 ImmData(36) -> x7 v10 ImmData(46) -> x6 v11 CallExt { binding_idx=0, args=[v9, v10], fp_arg_mask=0x0 } -> x0 v12 Imm(1) -> x0 terminator Return(v12) (exit_acc=v12) - block 5 start_pc=0 + block 131 start_pc=0 terminator Jmp(b2) - block 6 start_pc=0 - v14 LoadLocal { off=-2, kind=U32 } -> x0 - v15 LoadLocal { off=-1, kind=U32 } -> x0 - v16 Binop { op=ult, lhs=v3, rhs=v1 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x0 - terminator Bz { cond=v17, target=b10, fall=b9 } (exit_acc=v17) - block 7 start_pc=0 - v22 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v22) - block 8 start_pc=0 - terminator Jmp(b11) - block 9 start_pc=0 + block 132 start_pc=0 + terminator Jmp(b5) + block 133 start_pc=0 v18 ImmData(65) -> x7 v19 ImmData(75) -> x6 v20 CallExt { binding_idx=0, args=[v18, v19], fp_arg_mask=0x0 } -> x0 v21 Imm(1) -> x0 terminator Return(v21) (exit_acc=v21) - block 10 start_pc=0 + block 134 start_pc=0 + terminator Jmp(b4) + block 135 start_pc=0 terminator Jmp(b7) - block 11 start_pc=0 - v23 LoadLocal { off=-1, kind=U32 } -> x0 - v24 LoadLocal { off=-2, kind=U32 } -> x0 - v25 Binop { op=uge, lhs=v1, rhs=v3 } -> x0 - v26 BinopI { op=eq, lhs=v25, rhs_imm=0 } -> x0 - terminator Bz { cond=v26, target=b15, fall=b14 } (exit_acc=v26) - block 12 start_pc=0 - v31 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v31) - block 13 start_pc=0 - terminator Jmp(b16) - block 14 start_pc=0 + block 136 start_pc=0 v27 ImmData(94) -> x7 v28 ImmData(104) -> x6 v29 CallExt { binding_idx=0, args=[v27, v28], fp_arg_mask=0x0 } -> x0 v30 Imm(1) -> x0 terminator Return(v30) (exit_acc=v30) - block 15 start_pc=0 - terminator Jmp(b12) - block 16 start_pc=0 - v32 LoadLocal { off=-2, kind=U32 } -> x0 - v33 LoadLocal { off=-1, kind=U32 } -> x0 - v34 Binop { op=ule, lhs=v3, rhs=v1 } -> x0 - v35 BinopI { op=eq, lhs=v34, rhs_imm=0 } -> x0 - terminator Bz { cond=v35, target=b20, fall=b19 } (exit_acc=v35) - block 17 start_pc=0 - v40 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v40) - block 18 start_pc=0 - terminator Jmp(b21) - block 19 start_pc=0 + block 137 start_pc=0 + terminator Jmp(b6) + block 138 start_pc=0 + terminator Jmp(b9) + block 139 start_pc=0 v36 ImmData(124) -> x7 v37 ImmData(134) -> x6 v38 CallExt { binding_idx=0, args=[v36, v37], fp_arg_mask=0x0 } -> x0 v39 Imm(1) -> x0 terminator Return(v39) (exit_acc=v39) - block 20 start_pc=0 - terminator Jmp(b17) - block 21 start_pc=0 - v41 LoadLocal { off=-1, kind=U32 } -> x0 - v42 LoadLocal { off=-2, kind=U32 } -> x0 - v43 Binop { op=ne, lhs=v1, rhs=v3 } -> x0 - v44 BinopI { op=eq, lhs=v43, rhs_imm=0 } -> x0 - terminator Bz { cond=v44, target=b25, fall=b24 } (exit_acc=v44) - block 22 start_pc=0 - v49 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v49) - block 23 start_pc=0 - terminator Jmp(b26) - block 24 start_pc=0 + block 140 start_pc=0 + terminator Jmp(b8) + block 141 start_pc=0 + terminator Jmp(b11) + block 142 start_pc=0 v45 ImmData(154) -> x7 v46 ImmData(164) -> x6 v47 CallExt { binding_idx=0, args=[v45, v46], fp_arg_mask=0x0 } -> x0 v48 Imm(1) -> x0 - terminator Return(v48) (exit_acc=v48) - block 25 start_pc=0 - terminator Jmp(b22) - block 26 start_pc=0 - v50 LoadLocal { off=-1, kind=U32 } -> x0 - v51 LoadLocal { off=-2, kind=U32 } -> x0 - v52 Binop { op=eq, lhs=v1, rhs=v3 } -> x0 - v53 BinopI { op=eq, lhs=v52, rhs_imm=0 } -> x0 - v54 BinopI { op=eq, lhs=v53, rhs_imm=0 } -> x0 - terminator Bz { cond=v54, target=b30, fall=b29 } (exit_acc=v54) - block 27 start_pc=0 - v59 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v59) - block 28 start_pc=0 - v60 Imm(-2) -> x3 - v61 Imm(0) -> x0 - v62 Imm(1) -> x12 - v63 Imm(0) -> x0 - terminator Jmp(b31) (exit_acc=v62) - block 29 start_pc=0 + terminator Return(v48) (exit_acc=v48) + block 143 start_pc=0 + terminator Jmp(b10) + block 144 start_pc=0 v55 ImmData(184) -> x7 v56 ImmData(194) -> x6 v57 CallExt { binding_idx=0, args=[v55, v56], fp_arg_mask=0x0 } -> x0 v58 Imm(1) -> x0 terminator Return(v58) (exit_acc=v58) - block 30 start_pc=0 - terminator Jmp(b27) - block 31 start_pc=0 - v64 LoadLocal { off=-3, kind=I32 } -> x0 - v65 LoadLocal { off=-4, kind=I32 } -> x0 - v66 Binop { op=lt, lhs=v60, rhs=v62 } -> x0 - v67 BinopI { op=eq, lhs=v66, rhs_imm=0 } -> x0 - terminator Bz { cond=v67, target=b35, fall=b34 } (exit_acc=v67) - block 32 start_pc=0 - v72 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v72) - block 33 start_pc=0 - terminator Jmp(b36) - block 34 start_pc=0 + block 145 start_pc=0 + terminator Jmp(b12) + block 146 start_pc=0 + terminator Jmp(b16) + block 147 start_pc=0 v68 ImmData(214) -> x7 v69 ImmData(224) -> x6 v70 CallExt { binding_idx=0, args=[v68, v69], fp_arg_mask=0x0 } -> x0 v71 Imm(1) -> x0 terminator Return(v71) (exit_acc=v71) - block 35 start_pc=0 - terminator Jmp(b32) - block 36 start_pc=0 - v73 LoadLocal { off=-4, kind=I32 } -> x0 - v74 LoadLocal { off=-3, kind=I32 } -> x0 - v75 Binop { op=gt, lhs=v62, rhs=v60 } -> x0 - v76 BinopI { op=eq, lhs=v75, rhs_imm=0 } -> x0 - terminator Bz { cond=v76, target=b40, fall=b39 } (exit_acc=v76) - block 37 start_pc=0 - v81 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v81) - block 38 start_pc=0 - terminator Jmp(b41) - block 39 start_pc=0 + block 148 start_pc=0 + terminator Jmp(b15) + block 149 start_pc=0 + terminator Jmp(b18) + block 150 start_pc=0 v77 ImmData(235) -> x7 v78 ImmData(245) -> x6 v79 CallExt { binding_idx=0, args=[v77, v78], fp_arg_mask=0x0 } -> x0 v80 Imm(1) -> x0 terminator Return(v80) (exit_acc=v80) - block 40 start_pc=0 - terminator Jmp(b37) - block 41 start_pc=0 - v82 LoadLocal { off=-3, kind=I32 } -> x0 - v83 LoadLocal { off=-4, kind=I32 } -> x0 - v84 Binop { op=le, lhs=v60, rhs=v62 } -> x0 - v85 BinopI { op=eq, lhs=v84, rhs_imm=0 } -> x0 - terminator Bz { cond=v85, target=b45, fall=b44 } (exit_acc=v85) - block 42 start_pc=0 - v90 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v90) - block 43 start_pc=0 - terminator Jmp(b46) - block 44 start_pc=0 + block 151 start_pc=0 + terminator Jmp(b17) + block 152 start_pc=0 + terminator Jmp(b20) + block 153 start_pc=0 v86 ImmData(256) -> x7 v87 ImmData(266) -> x6 v88 CallExt { binding_idx=0, args=[v86, v87], fp_arg_mask=0x0 } -> x0 v89 Imm(1) -> x0 terminator Return(v89) (exit_acc=v89) - block 45 start_pc=0 - terminator Jmp(b42) - block 46 start_pc=0 - v91 LoadLocal { off=-4, kind=I32 } -> x0 - v92 LoadLocal { off=-3, kind=I32 } -> x0 - v93 Binop { op=ge, lhs=v62, rhs=v60 } -> x0 - v94 BinopI { op=eq, lhs=v93, rhs_imm=0 } -> x0 - terminator Bz { cond=v94, target=b50, fall=b49 } (exit_acc=v94) - block 47 start_pc=0 - v99 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v99) - block 48 start_pc=0 - v100 Imm(-2) -> x3 - v101 Imm(0) -> x0 - v102 Imm(1) -> x12 - v103 Imm(0) -> x0 - terminator Jmp(b51) (exit_acc=v102) - block 49 start_pc=0 + block 154 start_pc=0 + terminator Jmp(b19) + block 155 start_pc=0 v95 ImmData(278) -> x7 v96 ImmData(288) -> x6 v97 CallExt { binding_idx=0, args=[v95, v96], fp_arg_mask=0x0 } -> x0 v98 Imm(1) -> x0 terminator Return(v98) (exit_acc=v98) - block 50 start_pc=0 - terminator Jmp(b47) - block 51 start_pc=0 - v104 LoadLocal { off=-5, kind=I64 } -> x0 - v105 LoadLocal { off=-6, kind=I64 } -> x0 - v106 Binop { op=ugt, lhs=v100, rhs=v102 } -> x0 - v107 BinopI { op=eq, lhs=v106, rhs_imm=0 } -> x0 - terminator Bz { cond=v107, target=b55, fall=b54 } (exit_acc=v107) - block 52 start_pc=0 - v112 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v112) - block 53 start_pc=0 - terminator Jmp(b56) - block 54 start_pc=0 + block 156 start_pc=0 + terminator Jmp(b21) + block 157 start_pc=0 + terminator Jmp(b25) + block 158 start_pc=0 v108 ImmData(300) -> x7 v109 ImmData(310) -> x6 v110 CallExt { binding_idx=0, args=[v108, v109], fp_arg_mask=0x0 } -> x0 v111 Imm(1) -> x0 terminator Return(v111) (exit_acc=v111) - block 55 start_pc=0 - terminator Jmp(b52) - block 56 start_pc=0 - v113 LoadLocal { off=-5, kind=I64 } -> x0 - v114 LoadLocal { off=-6, kind=I64 } -> x0 - v115 Binop { op=uge, lhs=v100, rhs=v102 } -> x0 - v116 BinopI { op=eq, lhs=v115, rhs_imm=0 } -> x0 - terminator Bz { cond=v116, target=b60, fall=b59 } (exit_acc=v116) - block 57 start_pc=0 - v121 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v121) - block 58 start_pc=0 - terminator Jmp(b61) - block 59 start_pc=0 + block 159 start_pc=0 + terminator Jmp(b24) + block 160 start_pc=0 + terminator Jmp(b27) + block 161 start_pc=0 v117 ImmData(323) -> x7 v118 ImmData(333) -> x6 v119 CallExt { binding_idx=0, args=[v117, v118], fp_arg_mask=0x0 } -> x0 v120 Imm(1) -> x0 terminator Return(v120) (exit_acc=v120) - block 60 start_pc=0 - terminator Jmp(b57) - block 61 start_pc=0 - v122 LoadLocal { off=-6, kind=I64 } -> x0 - v123 LoadLocal { off=-5, kind=I64 } -> x0 - v124 Binop { op=ult, lhs=v102, rhs=v100 } -> x0 - v125 BinopI { op=eq, lhs=v124, rhs_imm=0 } -> x0 - terminator Bz { cond=v125, target=b65, fall=b64 } (exit_acc=v125) - block 62 start_pc=0 - v130 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v130) - block 63 start_pc=0 - v131 Imm(-2) -> x3 - v132 Imm(0) -> x0 - v133 Imm(1) -> x0 - v134 Imm(0) -> x1 - terminator Jmp(b66) (exit_acc=v133) - block 64 start_pc=0 + block 162 start_pc=0 + terminator Jmp(b26) + block 163 start_pc=0 v126 ImmData(347) -> x7 v127 ImmData(357) -> x6 v128 CallExt { binding_idx=0, args=[v126, v127], fp_arg_mask=0x0 } -> x0 v129 Imm(1) -> x0 terminator Return(v129) (exit_acc=v129) - block 65 start_pc=0 - terminator Jmp(b62) - block 66 start_pc=0 - v135 LoadLocal { off=-8, kind=I64 } -> x1 - v136 LoadLocal { off=-7, kind=I64 } -> x1 - v137 Binop { op=gt, lhs=v133, rhs=v131 } -> x0 - v138 BinopI { op=eq, lhs=v137, rhs_imm=0 } -> x0 - terminator Bz { cond=v138, target=b70, fall=b69 } (exit_acc=v138) - block 67 start_pc=0 - v143 Imm(0) -> x0 - terminator Jmp(b68) (exit_acc=v143) - block 68 start_pc=0 - terminator Jmp(b71) - block 69 start_pc=0 + block 164 start_pc=0 + terminator Jmp(b28) + block 165 start_pc=0 + terminator Jmp(b32) + block 166 start_pc=0 v139 ImmData(370) -> x7 v140 ImmData(380) -> x6 v141 CallExt { binding_idx=0, args=[v139, v140], fp_arg_mask=0x0 } -> x0 v142 Imm(1) -> x0 terminator Return(v142) (exit_acc=v142) - block 70 start_pc=0 - terminator Jmp(b67) - block 71 start_pc=0 - v144 LoadLocal { off=-7, kind=I64 } -> x0 - v145 BinopI { op=lt, lhs=v131, rhs_imm=0 } -> x0 - v146 BinopI { op=eq, lhs=v145, rhs_imm=0 } -> x0 - terminator Bz { cond=v146, target=b75, fall=b74 } (exit_acc=v146) - block 72 start_pc=0 - v151 Imm(0) -> x0 - terminator Jmp(b73) (exit_acc=v151) - block 73 start_pc=0 - v152 Imm(254) -> x3 - v153 Imm(0) -> x0 - v154 Imm(1) -> x12 - v155 Imm(0) -> x0 - terminator Jmp(b76) (exit_acc=v154) - block 74 start_pc=0 + block 167 start_pc=0 + terminator Jmp(b31) + block 168 start_pc=0 v147 ImmData(391) -> x7 v148 ImmData(401) -> x6 v149 CallExt { binding_idx=0, args=[v147, v148], fp_arg_mask=0x0 } -> x0 v150 Imm(1) -> x0 terminator Return(v150) (exit_acc=v150) - block 75 start_pc=0 - terminator Jmp(b72) - block 76 start_pc=0 - v156 LoadLocal { off=-9, kind=U8 } -> x0 - v157 LoadLocal { off=-10, kind=U8 } -> x0 - v158 Binop { op=gt, lhs=v152, rhs=v154 } -> x0 - v159 BinopI { op=eq, lhs=v158, rhs_imm=0 } -> x0 - terminator Bz { cond=v159, target=b80, fall=b79 } (exit_acc=v159) - block 77 start_pc=0 - v164 Imm(0) -> x0 - terminator Jmp(b78) (exit_acc=v164) - block 78 start_pc=0 - terminator Jmp(b81) - block 79 start_pc=0 + block 169 start_pc=0 + terminator Jmp(b33) + block 170 start_pc=0 + terminator Jmp(b37) + block 171 start_pc=0 v160 ImmData(412) -> x7 v161 ImmData(422) -> x6 v162 CallExt { binding_idx=0, args=[v160, v161], fp_arg_mask=0x0 } -> x0 v163 Imm(1) -> x0 terminator Return(v163) (exit_acc=v163) - block 80 start_pc=0 - terminator Jmp(b77) - block 81 start_pc=0 - v165 LoadLocal { off=-10, kind=U8 } -> x0 - v166 LoadLocal { off=-9, kind=U8 } -> x0 - v167 Binop { op=lt, lhs=v154, rhs=v152 } -> x0 - v168 BinopI { op=eq, lhs=v167, rhs_imm=0 } -> x0 - terminator Bz { cond=v168, target=b85, fall=b84 } (exit_acc=v168) - block 82 start_pc=0 - v173 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v173) - block 83 start_pc=0 - v174 Imm(-2) -> x3 - v175 Imm(0) -> x0 - v176 Imm(1) -> x12 - v177 Imm(0) -> x0 - terminator Jmp(b86) (exit_acc=v176) - block 84 start_pc=0 + block 172 start_pc=0 + terminator Jmp(b36) + block 173 start_pc=0 v169 ImmData(434) -> x7 v170 ImmData(444) -> x6 v171 CallExt { binding_idx=0, args=[v169, v170], fp_arg_mask=0x0 } -> x0 v172 Imm(1) -> x0 terminator Return(v172) (exit_acc=v172) - block 85 start_pc=0 - terminator Jmp(b82) - block 86 start_pc=0 - v178 LoadLocal { off=-11, kind=I8 } -> x0 - v179 LoadLocal { off=-12, kind=I8 } -> x0 - v180 Binop { op=lt, lhs=v174, rhs=v176 } -> x0 - v181 BinopI { op=eq, lhs=v180, rhs_imm=0 } -> x0 - terminator Bz { cond=v181, target=b90, fall=b89 } (exit_acc=v181) - block 87 start_pc=0 - v186 Imm(0) -> x0 - terminator Jmp(b88) (exit_acc=v186) - block 88 start_pc=0 - terminator Jmp(b91) - block 89 start_pc=0 + block 174 start_pc=0 + terminator Jmp(b38) + block 175 start_pc=0 + terminator Jmp(b42) + block 176 start_pc=0 v182 ImmData(456) -> x7 v183 ImmData(466) -> x6 v184 CallExt { binding_idx=0, args=[v182, v183], fp_arg_mask=0x0 } -> x0 v185 Imm(1) -> x0 terminator Return(v185) (exit_acc=v185) - block 90 start_pc=0 - terminator Jmp(b87) - block 91 start_pc=0 - v187 LoadLocal { off=-12, kind=I8 } -> x0 - v188 LoadLocal { off=-11, kind=I8 } -> x0 - v189 Binop { op=gt, lhs=v176, rhs=v174 } -> x0 - v190 BinopI { op=eq, lhs=v189, rhs_imm=0 } -> x0 - terminator Bz { cond=v190, target=b95, fall=b94 } (exit_acc=v190) - block 92 start_pc=0 - v195 Imm(0) -> x0 - terminator Jmp(b93) (exit_acc=v195) - block 93 start_pc=0 - v196 Imm(100) -> x0 - v197 Imm(0) -> x1 - v198 LoadLocal { off=-13, kind=U32 } -> x1 - v199 BinopI { op=add, lhs=v196, rhs_imm=5 } -> x3 - v200 Imm(0) -> x0 - v201 BinopI { op=and, lhs=v199, rhs_imm=4294967295 } -> x0 - terminator Jmp(b96) (exit_acc=v201) - block 94 start_pc=0 + block 177 start_pc=0 + terminator Jmp(b41) + block 178 start_pc=0 v191 ImmData(476) -> x7 v192 ImmData(486) -> x6 v193 CallExt { binding_idx=0, args=[v191, v192], fp_arg_mask=0x0 } -> x0 v194 Imm(1) -> x0 terminator Return(v194) (exit_acc=v194) - block 95 start_pc=0 - terminator Jmp(b92) - block 96 start_pc=0 - v202 BinopI { op=and, lhs=v199, rhs_imm=4294967295 } -> x0 - v203 BinopI { op=xor, lhs=v202, rhs_imm=105 } -> x0 - v204 BinopI { op=and, lhs=v203, rhs_imm=4294967295 } -> x0 - v205 BinopI { op=eq, lhs=v204, rhs_imm=0 } -> x0 - v206 BinopI { op=eq, lhs=v205, rhs_imm=0 } -> x0 - terminator Bz { cond=v206, target=b100, fall=b99 } (exit_acc=v206) - block 97 start_pc=0 - v211 Imm(0) -> x0 - terminator Jmp(b98) (exit_acc=v211) - block 98 start_pc=0 - v212 BinopI { op=and, lhs=v199, rhs_imm=4294967295 } -> x0 - v213 BinopI { op=sub, lhs=v212, rhs_imm=10 } -> x3 - v214 Imm(0) -> x0 - v215 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> x0 - terminator Jmp(b101) (exit_acc=v215) - block 99 start_pc=0 + block 179 start_pc=0 + terminator Jmp(b43) + block 180 start_pc=0 v207 ImmData(496) -> x7 v208 ImmData(506) -> x6 v209 CallExt { binding_idx=0, args=[v207, v208], fp_arg_mask=0x0 } -> x0 v210 Imm(1) -> x0 terminator Return(v210) (exit_acc=v210) - block 100 start_pc=0 - terminator Jmp(b97) - block 101 start_pc=0 - v216 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> x0 - v217 BinopI { op=xor, lhs=v216, rhs_imm=95 } -> x0 - v218 BinopI { op=and, lhs=v217, rhs_imm=4294967295 } -> x0 - v219 BinopI { op=eq, lhs=v218, rhs_imm=0 } -> x0 - v220 BinopI { op=eq, lhs=v219, rhs_imm=0 } -> x0 - terminator Bz { cond=v220, target=b105, fall=b104 } (exit_acc=v220) - block 102 start_pc=0 - v225 Imm(0) -> x0 - terminator Jmp(b103) (exit_acc=v225) - block 103 start_pc=0 - v226 BinopI { op=and, lhs=v213, rhs_imm=4294967295 } -> x0 - v227 BinopI { op=shl, lhs=v226, rhs_imm=1 } -> x3 - v228 Imm(0) -> x0 - v229 BinopI { op=and, lhs=v227, rhs_imm=4294967295 } -> x0 - terminator Jmp(b106) (exit_acc=v229) - block 104 start_pc=0 + block 181 start_pc=0 + terminator Jmp(b46) + block 182 start_pc=0 v221 ImmData(515) -> x7 v222 ImmData(525) -> x6 v223 CallExt { binding_idx=0, args=[v221, v222], fp_arg_mask=0x0 } -> x0 v224 Imm(1) -> x0 terminator Return(v224) (exit_acc=v224) - block 105 start_pc=0 - terminator Jmp(b102) - block 106 start_pc=0 - v230 BinopI { op=and, lhs=v227, rhs_imm=4294967295 } -> x0 - v231 BinopI { op=xor, lhs=v230, rhs_imm=190 } -> x0 - v232 BinopI { op=and, lhs=v231, rhs_imm=4294967295 } -> x0 - v233 BinopI { op=eq, lhs=v232, rhs_imm=0 } -> x0 - v234 BinopI { op=eq, lhs=v233, rhs_imm=0 } -> x0 - terminator Bz { cond=v234, target=b110, fall=b109 } (exit_acc=v234) - block 107 start_pc=0 - v239 Imm(0) -> x0 - terminator Jmp(b108) (exit_acc=v239) - block 108 start_pc=0 - v240 BinopI { op=and, lhs=v227, rhs_imm=4294967295 } -> x0 - v241 Imm(5) -> x1 - v242 Binop { op=divu, lhs=v240, rhs=v241 } -> x3 - v243 Imm(0) -> x0 - v244 BinopI { op=and, lhs=v242, rhs_imm=4294967295 } -> x0 - terminator Jmp(b111) (exit_acc=v244) - block 109 start_pc=0 + block 183 start_pc=0 + terminator Jmp(b49) + block 184 start_pc=0 v235 ImmData(535) -> x7 v236 ImmData(545) -> x6 v237 CallExt { binding_idx=0, args=[v235, v236], fp_arg_mask=0x0 } -> x0 v238 Imm(1) -> x0 terminator Return(v238) (exit_acc=v238) - block 110 start_pc=0 - terminator Jmp(b107) - block 111 start_pc=0 - v245 BinopI { op=and, lhs=v242, rhs_imm=4294967295 } -> x0 - v246 BinopI { op=xor, lhs=v245, rhs_imm=38 } -> x0 - v247 BinopI { op=and, lhs=v246, rhs_imm=4294967295 } -> x0 - v248 BinopI { op=eq, lhs=v247, rhs_imm=0 } -> x0 - v249 BinopI { op=eq, lhs=v248, rhs_imm=0 } -> x0 - terminator Bz { cond=v249, target=b115, fall=b114 } (exit_acc=v249) - block 112 start_pc=0 - v254 Imm(0) -> x0 - terminator Jmp(b113) (exit_acc=v254) - block 113 start_pc=0 - v255 BinopI { op=and, lhs=v242, rhs_imm=4294967295 } -> x0 - v256 Imm(7) -> x1 - v257 Binop { op=modu, lhs=v255, rhs=v256 } -> x0 - v258 Imm(0) -> x1 - v259 BinopI { op=and, lhs=v257, rhs_imm=4294967295 } -> x1 - terminator Jmp(b116) (exit_acc=v259) - block 114 start_pc=0 + block 185 start_pc=0 + terminator Jmp(b52) + block 186 start_pc=0 v250 ImmData(554) -> x7 v251 ImmData(564) -> x6 v252 CallExt { binding_idx=0, args=[v250, v251], fp_arg_mask=0x0 } -> x0 v253 Imm(1) -> x0 terminator Return(v253) (exit_acc=v253) - block 115 start_pc=0 - terminator Jmp(b112) - block 116 start_pc=0 - v260 BinopI { op=and, lhs=v257, rhs_imm=4294967295 } -> x0 - v261 BinopI { op=xor, lhs=v260, rhs_imm=3 } -> x0 - v262 BinopI { op=and, lhs=v261, rhs_imm=4294967295 } -> x0 - v263 BinopI { op=eq, lhs=v262, rhs_imm=0 } -> x0 - v264 BinopI { op=eq, lhs=v263, rhs_imm=0 } -> x0 - terminator Bz { cond=v264, target=b120, fall=b119 } (exit_acc=v264) - block 117 start_pc=0 - v269 Imm(0) -> x0 - terminator Jmp(b118) (exit_acc=v269) - block 118 start_pc=0 - v270 Imm(1) -> x0 - v271 Imm(0) -> x1 - v272 LoadLocal { off=-14, kind=U32 } -> x1 - v273 BinopI { op=sub, lhs=v270, rhs_imm=2 } -> x0 - v274 BinopI { op=and, lhs=v273, rhs_imm=4294967295 } -> x0 - v275 Imm(0) -> x1 - terminator Jmp(b121) (exit_acc=v274) - block 119 start_pc=0 + block 187 start_pc=0 + terminator Jmp(b55) + block 188 start_pc=0 v265 ImmData(573) -> x7 v266 ImmData(583) -> x6 v267 CallExt { binding_idx=0, args=[v265, v266], fp_arg_mask=0x0 } -> x0 v268 Imm(1) -> x0 terminator Return(v268) (exit_acc=v268) - block 120 start_pc=0 - terminator Jmp(b117) - block 121 start_pc=0 - v276 BinopI { op=and, lhs=v274, rhs_imm=4294967295 } -> x0 - v277 BinopI { op=eq, lhs=v276, rhs_imm=4294967295 } -> x0 - v278 BinopI { op=eq, lhs=v277, rhs_imm=0 } -> x0 - terminator Bz { cond=v278, target=b125, fall=b124 } (exit_acc=v278) - block 122 start_pc=0 - v283 Imm(0) -> x0 - terminator Jmp(b123) (exit_acc=v283) - block 123 start_pc=0 - v284 Imm(1000) -> x0 - v285 Imm(0) -> x1 - v286 LoadLocal { off=-15, kind=I64 } -> x1 - v287 BinopI { op=add, lhs=v284, rhs_imm=415 } -> x3 - v288 Imm(0) -> x0 - terminator Jmp(b126) (exit_acc=v287) - block 124 start_pc=0 + block 189 start_pc=0 + terminator Jmp(b58) + block 190 start_pc=0 v279 ImmData(592) -> x7 v280 ImmData(602) -> x6 v281 CallExt { binding_idx=0, args=[v279, v280], fp_arg_mask=0x0 } -> x0 v282 Imm(1) -> x0 terminator Return(v282) (exit_acc=v282) - block 125 start_pc=0 - terminator Jmp(b122) - block 126 start_pc=0 - v289 LoadLocal { off=-15, kind=I64 } -> x0 - v290 BinopI { op=eq, lhs=v287, rhs_imm=1415 } -> x0 - v291 BinopI { op=eq, lhs=v290, rhs_imm=0 } -> x0 - terminator Bz { cond=v291, target=b130, fall=b129 } (exit_acc=v291) - block 127 start_pc=0 - v296 Imm(0) -> x0 - terminator Jmp(b128) (exit_acc=v296) - block 128 start_pc=0 - v297 LoadLocal { off=-15, kind=I64 } -> x0 - v298 BinopI { op=mul, lhs=v287, rhs_imm=3 } -> x3 - v299 Imm(0) -> x0 - terminator Jmp(b131) (exit_acc=v298) - block 129 start_pc=0 - v292 ImmData(616) -> x7 - v293 ImmData(626) -> x6 - v294 CallExt { binding_idx=0, args=[v292, v293], fp_arg_mask=0x0 } -> x0 - v295 Imm(1) -> x0 - terminator Return(v295) (exit_acc=v295) - block 130 start_pc=0 - terminator Jmp(b127) - block 131 start_pc=0 - v300 LoadLocal { off=-15, kind=I64 } -> x0 - v301 BinopI { op=eq, lhs=v298, rhs_imm=4245 } -> x0 - v302 BinopI { op=eq, lhs=v301, rhs_imm=0 } -> x0 - terminator Bz { cond=v302, target=b135, fall=b134 } (exit_acc=v302) - block 132 start_pc=0 - v307 Imm(0) -> x0 - terminator Jmp(b133) (exit_acc=v307) - block 133 start_pc=0 - v308 LoadLocal { off=-15, kind=I64 } -> x0 - v309 Imm(5) -> x0 - v310 Binop { op=divu, lhs=v298, rhs=v309 } -> x0 - v311 Imm(0) -> x1 - terminator Jmp(b136) (exit_acc=v310) - block 134 start_pc=0 + block 191 start_pc=0 + terminator Jmp(b61) + block 192 start_pc=0 + v292 ImmData(616) -> x7 + v293 ImmData(626) -> x6 + v294 CallExt { binding_idx=0, args=[v292, v293], fp_arg_mask=0x0 } -> x0 + v295 Imm(1) -> x0 + terminator Return(v295) (exit_acc=v295) + block 193 start_pc=0 + terminator Jmp(b64) + block 194 start_pc=0 v303 ImmData(637) -> x7 v304 ImmData(647) -> x6 v305 CallExt { binding_idx=0, args=[v303, v304], fp_arg_mask=0x0 } -> x0 v306 Imm(1) -> x0 terminator Return(v306) (exit_acc=v306) - block 135 start_pc=0 - terminator Jmp(b132) - block 136 start_pc=0 - v312 LoadLocal { off=-15, kind=I64 } -> x1 - v313 BinopI { op=eq, lhs=v310, rhs_imm=849 } -> x0 - v314 BinopI { op=eq, lhs=v313, rhs_imm=0 } -> x0 - terminator Bz { cond=v314, target=b140, fall=b139 } (exit_acc=v314) - block 137 start_pc=0 - v319 Imm(0) -> x0 - terminator Jmp(b138) (exit_acc=v319) - block 138 start_pc=0 - v320 Imm(4278255360) -> x0 - v321 Imm(0) -> x1 - v322 LoadLocal { off=-16, kind=U32 } -> x1 - v323 BinopI { op=and, lhs=v320, rhs_imm=252645135 } -> x1 - v324 Imm(0) -> x2 - v325 BinopI { op=or, lhs=v320, rhs_imm=1044480 } -> x3 - v326 Imm(0) -> x2 - v327 BinopI { op=xor, lhs=v320, rhs_imm=4294967295 } -> x12 - v328 Imm(0) -> x2 - v329 BinopI { op=xor, lhs=v320, rhs_imm=-1 } -> x0 - v330 BinopI { op=and, lhs=v329, rhs_imm=4294967295 } -> x13 - v331 Imm(0) -> x0 - terminator Jmp(b141) (exit_acc=v330) - block 139 start_pc=0 + block 195 start_pc=0 + terminator Jmp(b67) + block 196 start_pc=0 v315 ImmData(656) -> x7 v316 ImmData(666) -> x6 v317 CallExt { binding_idx=0, args=[v315, v316], fp_arg_mask=0x0 } -> x0 v318 Imm(1) -> x0 terminator Return(v318) (exit_acc=v318) - block 140 start_pc=0 - terminator Jmp(b137) - block 141 start_pc=0 - v332 BinopI { op=and, lhs=v323, rhs_imm=4294967295 } -> x0 - v333 BinopI { op=xor, lhs=v332, rhs_imm=251662080 } -> x0 - v334 BinopI { op=and, lhs=v333, rhs_imm=4294967295 } -> x0 - v335 BinopI { op=eq, lhs=v334, rhs_imm=0 } -> x0 - v336 BinopI { op=eq, lhs=v335, rhs_imm=0 } -> x0 - terminator Bz { cond=v336, target=b145, fall=b144 } (exit_acc=v336) - block 142 start_pc=0 - v341 Imm(0) -> x0 - terminator Jmp(b143) (exit_acc=v341) - block 143 start_pc=0 - terminator Jmp(b146) - block 144 start_pc=0 + block 197 start_pc=0 + terminator Jmp(b70) + block 198 start_pc=0 + terminator Jmp(b74) + block 199 start_pc=0 v337 ImmData(675) -> x7 v338 ImmData(685) -> x6 v339 CallExt { binding_idx=0, args=[v337, v338], fp_arg_mask=0x0 } -> x0 v340 Imm(1) -> x0 terminator Return(v340) (exit_acc=v340) - block 145 start_pc=0 - terminator Jmp(b142) - block 146 start_pc=0 - v342 BinopI { op=and, lhs=v325, rhs_imm=4294967295 } -> x0 - v343 BinopI { op=eq, lhs=v342, rhs_imm=4279238400 } -> x0 - v344 BinopI { op=eq, lhs=v343, rhs_imm=0 } -> x0 - terminator Bz { cond=v344, target=b150, fall=b149 } (exit_acc=v344) - block 147 start_pc=0 - v349 Imm(0) -> x0 - terminator Jmp(b148) (exit_acc=v349) - block 148 start_pc=0 - terminator Jmp(b151) - block 149 start_pc=0 + block 200 start_pc=0 + terminator Jmp(b73) + block 201 start_pc=0 + terminator Jmp(b76) + block 202 start_pc=0 v345 ImmData(691) -> x7 v346 ImmData(701) -> x6 v347 CallExt { binding_idx=0, args=[v345, v346], fp_arg_mask=0x0 } -> x0 v348 Imm(1) -> x0 terminator Return(v348) (exit_acc=v348) - block 150 start_pc=0 - terminator Jmp(b147) - block 151 start_pc=0 - v350 BinopI { op=and, lhs=v327, rhs_imm=4294967295 } -> x0 - v351 BinopI { op=xor, lhs=v350, rhs_imm=16711935 } -> x0 - v352 BinopI { op=and, lhs=v351, rhs_imm=4294967295 } -> x0 - v353 BinopI { op=eq, lhs=v352, rhs_imm=0 } -> x0 - v354 BinopI { op=eq, lhs=v353, rhs_imm=0 } -> x0 - terminator Bz { cond=v354, target=b155, fall=b154 } (exit_acc=v354) - block 152 start_pc=0 - v359 Imm(0) -> x0 - terminator Jmp(b153) (exit_acc=v359) - block 153 start_pc=0 - terminator Jmp(b156) - block 154 start_pc=0 + block 203 start_pc=0 + terminator Jmp(b75) + block 204 start_pc=0 + terminator Jmp(b78) + block 205 start_pc=0 v355 ImmData(707) -> x7 v356 ImmData(717) -> x6 v357 CallExt { binding_idx=0, args=[v355, v356], fp_arg_mask=0x0 } -> x0 v358 Imm(1) -> x0 terminator Return(v358) (exit_acc=v358) - block 155 start_pc=0 - terminator Jmp(b152) - block 156 start_pc=0 - v360 BinopI { op=and, lhs=v330, rhs_imm=4294967295 } -> x0 - v361 BinopI { op=xor, lhs=v360, rhs_imm=16711935 } -> x0 - v362 BinopI { op=and, lhs=v361, rhs_imm=4294967295 } -> x0 - v363 BinopI { op=eq, lhs=v362, rhs_imm=0 } -> x0 - v364 BinopI { op=eq, lhs=v363, rhs_imm=0 } -> x0 - terminator Bz { cond=v364, target=b160, fall=b159 } (exit_acc=v364) - block 157 start_pc=0 - v369 Imm(0) -> x0 - terminator Jmp(b158) (exit_acc=v369) - block 158 start_pc=0 - v370 Imm(305419896) -> x0 - v371 Imm(0) -> x1 - v372 LoadLocal { off=-21, kind=U32 } -> x1 - v373 BinopI { op=shl, lhs=v370, rhs_imm=4 } -> x0 - v374 BinopI { op=and, lhs=v373, rhs_imm=4294967295 } -> x0 - v375 Imm(0) -> x1 - terminator Jmp(b161) (exit_acc=v374) - block 159 start_pc=0 + block 206 start_pc=0 + terminator Jmp(b77) + block 207 start_pc=0 v365 ImmData(723) -> x7 v366 ImmData(733) -> x6 v367 CallExt { binding_idx=0, args=[v365, v366], fp_arg_mask=0x0 } -> x0 v368 Imm(1) -> x0 terminator Return(v368) (exit_acc=v368) - block 160 start_pc=0 - terminator Jmp(b157) - block 161 start_pc=0 - v376 BinopI { op=and, lhs=v374, rhs_imm=4294967295 } -> x0 - v377 BinopI { op=xor, lhs=v376, rhs_imm=591751040 } -> x0 - v378 BinopI { op=and, lhs=v377, rhs_imm=4294967295 } -> x0 - v379 BinopI { op=eq, lhs=v378, rhs_imm=0 } -> x0 - v380 BinopI { op=eq, lhs=v379, rhs_imm=0 } -> x0 - terminator Bz { cond=v380, target=b165, fall=b164 } (exit_acc=v380) - block 162 start_pc=0 - v385 Imm(0) -> x0 - terminator Jmp(b163) (exit_acc=v385) - block 163 start_pc=0 - v386 Imm(1) -> x0 - v387 Imm(0) -> x1 - v388 LoadLocal { off=-23, kind=U32 } -> x1 - v389 BinopI { op=shl, lhs=v386, rhs_imm=31 } -> x0 - v390 BinopI { op=and, lhs=v389, rhs_imm=4294967295 } -> x0 - v391 Imm(0) -> x1 - terminator Jmp(b166) (exit_acc=v390) - block 164 start_pc=0 + block 208 start_pc=0 + terminator Jmp(b79) + block 209 start_pc=0 v381 ImmData(739) -> x7 v382 ImmData(749) -> x6 v383 CallExt { binding_idx=0, args=[v381, v382], fp_arg_mask=0x0 } -> x0 v384 Imm(1) -> x0 terminator Return(v384) (exit_acc=v384) - block 165 start_pc=0 - terminator Jmp(b162) - block 166 start_pc=0 - v392 BinopI { op=and, lhs=v390, rhs_imm=4294967295 } -> x0 - v393 BinopI { op=eq, lhs=v392, rhs_imm=2147483648 } -> x0 - v394 BinopI { op=eq, lhs=v393, rhs_imm=0 } -> x0 - terminator Bz { cond=v394, target=b170, fall=b169 } (exit_acc=v394) - block 167 start_pc=0 - v399 Imm(0) -> x0 - terminator Jmp(b168) (exit_acc=v399) - block 168 start_pc=0 - v400 Imm(1) -> x0 - v401 Imm(0) -> x1 - terminator Jmp(b171) (exit_acc=v400) - block 169 start_pc=0 + block 210 start_pc=0 + terminator Jmp(b82) + block 211 start_pc=0 v395 ImmData(758) -> x7 v396 ImmData(768) -> x6 v397 CallExt { binding_idx=0, args=[v395, v396], fp_arg_mask=0x0 } -> x0 v398 Imm(1) -> x0 terminator Return(v398) (exit_acc=v398) - block 170 start_pc=0 - terminator Jmp(b167) - block 171 start_pc=0 - v402 LoadLocal { off=-25, kind=I64 } -> x1 - v403 BinopI { op=shl, lhs=v400, rhs_imm=63 } -> x0 - v404 BinopI { op=eq, lhs=v403, rhs_imm=-9223372036854775808 } -> x0 - v405 BinopI { op=eq, lhs=v404, rhs_imm=0 } -> x0 - terminator Bz { cond=v405, target=b175, fall=b174 } (exit_acc=v405) - block 172 start_pc=0 - v410 Imm(0) -> x0 - terminator Jmp(b173) (exit_acc=v410) - block 173 start_pc=0 - v411 Imm(-1) -> x3 - v412 Imm(0) -> x0 - v413 Imm(1) -> x12 - v414 Imm(0) -> x0 - terminator Jmp(b176) (exit_acc=v413) - block 174 start_pc=0 + block 212 start_pc=0 + terminator Jmp(b85) + block 213 start_pc=0 v406 ImmData(778) -> x7 v407 ImmData(788) -> x6 v408 CallExt { binding_idx=0, args=[v406, v407], fp_arg_mask=0x0 } -> x0 v409 Imm(1) -> x0 terminator Return(v409) (exit_acc=v409) - block 175 start_pc=0 - terminator Jmp(b172) - block 176 start_pc=0 - v415 LoadLocal { off=-26, kind=I32 } -> x0 - v416 BinopI { op=and, lhs=v411, rhs_imm=4294967295 } -> x0 - v417 LoadLocal { off=-27, kind=U32 } -> x1 - v418 Binop { op=ugt, lhs=v416, rhs=v413 } -> x0 - v419 BinopI { op=eq, lhs=v418, rhs_imm=0 } -> x0 - terminator Bz { cond=v419, target=b180, fall=b179 } (exit_acc=v419) - block 177 start_pc=0 - v424 Imm(0) -> x0 - terminator Jmp(b178) (exit_acc=v424) - block 178 start_pc=0 - terminator Jmp(b181) - block 179 start_pc=0 + block 214 start_pc=0 + terminator Jmp(b88) + block 215 start_pc=0 + terminator Jmp(b92) + block 216 start_pc=0 v420 ImmData(798) -> x7 v421 ImmData(808) -> x6 v422 CallExt { binding_idx=0, args=[v420, v421], fp_arg_mask=0x0 } -> x0 v423 Imm(1) -> x0 terminator Return(v423) (exit_acc=v423) - block 180 start_pc=0 - terminator Jmp(b177) - block 181 start_pc=0 - v425 LoadLocal { off=-26, kind=I32 } -> x0 - v426 LoadLocal { off=-27, kind=U32 } -> x0 - v427 BinopI { op=shl, lhs=v413, rhs_imm=32 } -> x0 - v428 Extend { value=v413, kind=I32 } -> x0 - v429 Binop { op=lt, lhs=v411, rhs=v428 } -> x0 - v430 BinopI { op=eq, lhs=v429, rhs_imm=0 } -> x0 - terminator Bz { cond=v430, target=b185, fall=b184 } (exit_acc=v430) - block 182 start_pc=0 - v435 Imm(0) -> x0 - terminator Jmp(b183) (exit_acc=v435) - block 183 start_pc=0 - v436 Imm(4294967294) -> x0 - v437 Imm(0) -> x1 - v438 LoadLocal { off=-28, kind=U32 } -> x1 - v439 BinopI { op=add, lhs=v436, rhs_imm=1 } -> x3 - v440 Imm(0) -> x0 - v441 BinopI { op=and, lhs=v439, rhs_imm=4294967295 } -> x0 - terminator Jmp(b186) (exit_acc=v441) - block 184 start_pc=0 + block 217 start_pc=0 + terminator Jmp(b91) + block 218 start_pc=0 v431 ImmData(820) -> x7 v432 ImmData(830) -> x6 v433 CallExt { binding_idx=0, args=[v431, v432], fp_arg_mask=0x0 } -> x0 v434 Imm(1) -> x0 terminator Return(v434) (exit_acc=v434) - block 185 start_pc=0 - terminator Jmp(b182) - block 186 start_pc=0 - v442 BinopI { op=and, lhs=v439, rhs_imm=4294967295 } -> x0 - v443 BinopI { op=eq, lhs=v442, rhs_imm=4294967295 } -> x0 - v444 BinopI { op=eq, lhs=v443, rhs_imm=0 } -> x0 - terminator Bz { cond=v444, target=b190, fall=b189 } (exit_acc=v444) - block 187 start_pc=0 - v449 Imm(0) -> x0 - terminator Jmp(b188) (exit_acc=v449) - block 188 start_pc=0 - v450 BinopI { op=and, lhs=v439, rhs_imm=4294967295 } -> x0 - v451 BinopI { op=add, lhs=v450, rhs_imm=1 } -> x0 - v452 Imm(0) -> x1 - v453 BinopI { op=and, lhs=v451, rhs_imm=4294967295 } -> x1 - terminator Jmp(b191) (exit_acc=v453) - block 189 start_pc=0 + block 219 start_pc=0 + terminator Jmp(b93) + block 220 start_pc=0 v445 ImmData(841) -> x7 v446 ImmData(851) -> x6 v447 CallExt { binding_idx=0, args=[v445, v446], fp_arg_mask=0x0 } -> x0 v448 Imm(1) -> x0 terminator Return(v448) (exit_acc=v448) - block 190 start_pc=0 - terminator Jmp(b187) - block 191 start_pc=0 - v454 BinopI { op=and, lhs=v451, rhs_imm=4294967295 } -> x0 - v455 BinopI { op=eq, lhs=v454, rhs_imm=0 } -> x0 - v456 BinopI { op=eq, lhs=v455, rhs_imm=0 } -> x0 - terminator Bz { cond=v456, target=b195, fall=b194 } (exit_acc=v456) - block 192 start_pc=0 - v461 Imm(0) -> x0 - terminator Jmp(b193) (exit_acc=v461) - block 193 start_pc=0 - v462 Imm(254) -> x0 - v463 Imm(0) -> x1 - v464 LoadLocal { off=-29, kind=U8 } -> x1 - v465 BinopI { op=add, lhs=v462, rhs_imm=1 } -> x3 - v466 Imm(0) -> x0 - v467 BinopI { op=and, lhs=v465, rhs_imm=255 } -> x0 - terminator Jmp(b196) (exit_acc=v467) - block 194 start_pc=0 + block 221 start_pc=0 + terminator Jmp(b96) + block 222 start_pc=0 v457 ImmData(866) -> x7 v458 ImmData(876) -> x6 v459 CallExt { binding_idx=0, args=[v457, v458], fp_arg_mask=0x0 } -> x0 v460 Imm(1) -> x0 terminator Return(v460) (exit_acc=v460) - block 195 start_pc=0 - terminator Jmp(b192) - block 196 start_pc=0 - v468 BinopI { op=and, lhs=v465, rhs_imm=255 } -> x0 - v469 BinopI { op=xor, lhs=v468, rhs_imm=255 } -> x0 - v470 BinopI { op=and, lhs=v469, rhs_imm=4294967295 } -> x0 - v471 BinopI { op=eq, lhs=v470, rhs_imm=0 } -> x0 - v472 BinopI { op=eq, lhs=v471, rhs_imm=0 } -> x0 - terminator Bz { cond=v472, target=b200, fall=b199 } (exit_acc=v472) - block 197 start_pc=0 - v477 Imm(0) -> x0 - terminator Jmp(b198) (exit_acc=v477) - block 198 start_pc=0 - v478 BinopI { op=and, lhs=v465, rhs_imm=255 } -> x0 - v479 BinopI { op=add, lhs=v478, rhs_imm=1 } -> x0 - v480 Imm(0) -> x1 - v481 BinopI { op=and, lhs=v479, rhs_imm=255 } -> x1 - terminator Jmp(b201) (exit_acc=v481) - block 199 start_pc=0 + block 223 start_pc=0 + terminator Jmp(b99) + block 224 start_pc=0 v473 ImmData(894) -> x7 v474 ImmData(904) -> x6 v475 CallExt { binding_idx=0, args=[v473, v474], fp_arg_mask=0x0 } -> x0 v476 Imm(1) -> x0 terminator Return(v476) (exit_acc=v476) - block 200 start_pc=0 - terminator Jmp(b197) - block 201 start_pc=0 - v482 BinopI { op=and, lhs=v479, rhs_imm=255 } -> x0 - v483 BinopI { op=eq, lhs=v482, rhs_imm=0 } -> x0 - v484 BinopI { op=eq, lhs=v483, rhs_imm=0 } -> x0 - terminator Bz { cond=v484, target=b205, fall=b204 } (exit_acc=v484) - block 202 start_pc=0 - v489 Imm(0) -> x0 - terminator Jmp(b203) (exit_acc=v489) - block 203 start_pc=0 - v490 Imm(-2) -> x0 - v491 Imm(0) -> x1 - v492 LoadLocal { off=-30, kind=I64 } -> x1 - v493 BinopI { op=add, lhs=v490, rhs_imm=1 } -> x3 - v494 Imm(0) -> x0 - terminator Jmp(b206) (exit_acc=v493) - block 204 start_pc=0 + block 225 start_pc=0 + terminator Jmp(b102) + block 226 start_pc=0 v485 ImmData(923) -> x7 v486 ImmData(933) -> x6 v487 CallExt { binding_idx=0, args=[v485, v486], fp_arg_mask=0x0 } -> x0 v488 Imm(1) -> x0 terminator Return(v488) (exit_acc=v488) - block 205 start_pc=0 - terminator Jmp(b202) - block 206 start_pc=0 - v495 LoadLocal { off=-30, kind=I64 } -> x0 - v496 BinopI { op=eq, lhs=v493, rhs_imm=-1 } -> x0 - v497 BinopI { op=eq, lhs=v496, rhs_imm=0 } -> x0 - terminator Bz { cond=v497, target=b210, fall=b209 } (exit_acc=v497) - block 207 start_pc=0 - v502 Imm(0) -> x0 - terminator Jmp(b208) (exit_acc=v502) - block 208 start_pc=0 - v503 LoadLocal { off=-30, kind=I64 } -> x0 - v504 BinopI { op=add, lhs=v493, rhs_imm=1 } -> x0 - v505 Imm(0) -> x1 - terminator Jmp(b211) (exit_acc=v504) - block 209 start_pc=0 + block 227 start_pc=0 + terminator Jmp(b105) + block 228 start_pc=0 v498 ImmData(950) -> x7 v499 ImmData(960) -> x6 v500 CallExt { binding_idx=0, args=[v498, v499], fp_arg_mask=0x0 } -> x0 v501 Imm(1) -> x0 terminator Return(v501) (exit_acc=v501) - block 210 start_pc=0 - terminator Jmp(b207) - block 211 start_pc=0 - v506 LoadLocal { off=-30, kind=I64 } -> x1 - v507 BinopI { op=eq, lhs=v504, rhs_imm=0 } -> x0 - v508 BinopI { op=eq, lhs=v507, rhs_imm=0 } -> x0 - terminator Bz { cond=v508, target=b215, fall=b214 } (exit_acc=v508) - block 212 start_pc=0 - v513 Imm(0) -> x0 - terminator Jmp(b213) (exit_acc=v513) - block 213 start_pc=0 - terminator Jmp(b216) - block 214 start_pc=0 + block 229 start_pc=0 + terminator Jmp(b108) + block 230 start_pc=0 + terminator Jmp(b112) + block 231 start_pc=0 v509 ImmData(975) -> x7 v510 ImmData(985) -> x6 v511 CallExt { binding_idx=0, args=[v509, v510], fp_arg_mask=0x0 } -> x0 v512 Imm(1) -> x0 terminator Return(v512) (exit_acc=v512) - block 215 start_pc=0 - terminator Jmp(b212) - block 216 start_pc=0 - v514 Imm(1) -> x0 - v515 Imm(0) -> x0 - terminator Jmp(b220) (exit_acc=v515) - block 217 start_pc=0 - v520 Imm(0) -> x0 - terminator Jmp(b218) (exit_acc=v520) - block 218 start_pc=0 - terminator Jmp(b221) - block 219 start_pc=0 + block 232 start_pc=0 + terminator Jmp(b111) + block 233 start_pc=0 + terminator Jmp(b114) + block 234 start_pc=0 v516 ImmData(1003) -> x7 v517 ImmData(1013) -> x6 v518 CallExt { binding_idx=0, args=[v516, v517], fp_arg_mask=0x0 } -> x0 v519 Imm(1) -> x0 terminator Return(v519) (exit_acc=v519) - block 220 start_pc=0 - terminator Jmp(b217) - block 221 start_pc=0 - v521 Imm(1) -> x0 - v522 Imm(0) -> x0 - terminator Jmp(b225) (exit_acc=v522) - block 222 start_pc=0 - v527 Imm(0) -> x0 - terminator Jmp(b223) (exit_acc=v527) - block 223 start_pc=0 - terminator Jmp(b226) - block 224 start_pc=0 + block 235 start_pc=0 + terminator Jmp(b113) + block 236 start_pc=0 + terminator Jmp(b116) + block 237 start_pc=0 v523 ImmData(1024) -> x7 v524 ImmData(1034) -> x6 v525 CallExt { binding_idx=0, args=[v523, v524], fp_arg_mask=0x0 } -> x0 v526 Imm(1) -> x0 terminator Return(v526) (exit_acc=v526) - block 225 start_pc=0 - terminator Jmp(b222) - block 226 start_pc=0 - v528 Imm(1) -> x0 - v529 Imm(0) -> x0 - terminator Jmp(b230) (exit_acc=v529) - block 227 start_pc=0 - v534 Imm(0) -> x0 - terminator Jmp(b228) (exit_acc=v534) - block 228 start_pc=0 - terminator Jmp(b231) - block 229 start_pc=0 + block 238 start_pc=0 + terminator Jmp(b115) + block 239 start_pc=0 + terminator Jmp(b118) + block 240 start_pc=0 v530 ImmData(1048) -> x7 v531 ImmData(1058) -> x6 v532 CallExt { binding_idx=0, args=[v530, v531], fp_arg_mask=0x0 } -> x0 v533 Imm(1) -> x0 terminator Return(v533) (exit_acc=v533) - block 230 start_pc=0 - terminator Jmp(b227) - block 231 start_pc=0 - v535 Imm(1) -> x0 - v536 Imm(0) -> x0 - terminator Jmp(b235) (exit_acc=v536) - block 232 start_pc=0 - v541 Imm(0) -> x0 - terminator Jmp(b233) (exit_acc=v541) - block 233 start_pc=0 - terminator Jmp(b236) - block 234 start_pc=0 + block 241 start_pc=0 + terminator Jmp(b117) + block 242 start_pc=0 + terminator Jmp(b120) + block 243 start_pc=0 v537 ImmData(1070) -> x7 v538 ImmData(1080) -> x6 v539 CallExt { binding_idx=0, args=[v537, v538], fp_arg_mask=0x0 } -> x0 v540 Imm(1) -> x0 terminator Return(v540) (exit_acc=v540) - block 235 start_pc=0 - terminator Jmp(b232) - block 236 start_pc=0 - v542 Imm(1) -> x0 - v543 Imm(0) -> x0 - terminator Jmp(b240) (exit_acc=v543) - block 237 start_pc=0 - v548 Imm(0) -> x0 - terminator Jmp(b238) (exit_acc=v548) - block 238 start_pc=0 - terminator Jmp(b241) - block 239 start_pc=0 + block 244 start_pc=0 + terminator Jmp(b119) + block 245 start_pc=0 + terminator Jmp(b122) + block 246 start_pc=0 v544 ImmData(1092) -> x7 v545 ImmData(1102) -> x6 v546 CallExt { binding_idx=0, args=[v544, v545], fp_arg_mask=0x0 } -> x0 v547 Imm(1) -> x0 terminator Return(v547) (exit_acc=v547) - block 240 start_pc=0 - terminator Jmp(b237) - block 241 start_pc=0 - v549 Imm(1) -> x0 - v550 Imm(0) -> x0 - terminator Jmp(b245) (exit_acc=v550) - block 242 start_pc=0 - v555 Imm(0) -> x0 - terminator Jmp(b243) (exit_acc=v555) - block 243 start_pc=0 - terminator Jmp(b246) - block 244 start_pc=0 + block 247 start_pc=0 + terminator Jmp(b121) + block 248 start_pc=0 + terminator Jmp(b124) + block 249 start_pc=0 v551 ImmData(1114) -> x7 v552 ImmData(1124) -> x6 v553 CallExt { binding_idx=0, args=[v551, v552], fp_arg_mask=0x0 } -> x0 v554 Imm(1) -> x0 terminator Return(v554) (exit_acc=v554) - block 245 start_pc=0 - terminator Jmp(b242) - block 246 start_pc=0 - v556 Imm(1) -> x0 - v557 Imm(0) -> x0 - terminator Jmp(b250) (exit_acc=v557) - block 247 start_pc=0 - v562 Imm(0) -> x0 - terminator Jmp(b248) (exit_acc=v562) - block 248 start_pc=0 - terminator Jmp(b251) - block 249 start_pc=0 + block 250 start_pc=0 + terminator Jmp(b123) + block 251 start_pc=0 + terminator Jmp(b126) + block 252 start_pc=0 v558 ImmData(1144) -> x7 v559 ImmData(1154) -> x6 v560 CallExt { binding_idx=0, args=[v558, v559], fp_arg_mask=0x0 } -> x0 v561 Imm(1) -> x0 terminator Return(v561) (exit_acc=v561) - block 250 start_pc=0 - terminator Jmp(b247) - block 251 start_pc=0 - v563 Imm(1) -> x0 - v564 Imm(0) -> x0 - terminator Jmp(b255) (exit_acc=v564) - block 252 start_pc=0 - v569 Imm(0) -> x0 - terminator Jmp(b253) (exit_acc=v569) block 253 start_pc=0 - v570 Imm(0) -> x0 - terminator Return(v570) (exit_acc=v570) + terminator Jmp(b125) block 254 start_pc=0 v565 ImmData(1166) -> x7 v566 ImmData(1176) -> x6 @@ -1084,7 +1084,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=32 v568 Imm(1) -> x0 terminator Return(v568) (exit_acc=v568) block 255 start_pc=0 - terminator Jmp(b252) + terminator Jmp(b127) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/integer_suffixes.ssa b/tests/snapshots/ssa/integer_suffixes.ssa index cb069b3ba..7ba11c1c6 100644 --- a/tests/snapshots/ssa/integer_suffixes.ssa +++ b/tests/snapshots/ssa/integer_suffixes.ssa @@ -1,160 +1,160 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=15 - spill_count=3 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 Imm(4294967296) -> x1 - v4 Imm(2) -> x2 - v5 Imm(0) -> x6 - v6 Imm(8589934592) -> x6 - v7 Imm(3) -> x6 - v8 Imm(0) -> x7 - v9 Imm(12884901888) -> x7 - v10 Imm(4) -> x7 - v11 Imm(0) -> x8 - v12 Imm(17179869184) -> x8 - v13 Imm(5) -> x8 - v14 Imm(0) -> x9 - v15 Imm(21474836480) -> x9 - v16 Imm(6) -> x9 - v17 Imm(0) -> x3 - v18 Imm(25769803776) -> x3 - v19 Imm(7) -> x3 - v20 Imm(0) -> x12 - v21 Imm(30064771072) -> x12 - v22 Imm(8) -> x12 - v23 Imm(0) -> x13 - v24 Imm(34359738368) -> x13 - v25 Imm(9) -> x13 - v26 Imm(0) -> x14 - v27 Imm(38654705664) -> x14 - v28 Imm(10) -> x14 - v29 Imm(0) -> x15 - v30 Imm(42949672960) -> x15 - v31 Imm(255) -> x15 - v32 Imm(0) -> [spill 0] - v33 Imm(1095216660480) -> [spill 0] - v34 Imm(51966) -> [spill 0] - v35 Imm(0) -> [spill 1] - v36 Imm(223192270503936) -> [spill 1] - v37 Imm(1000000000000) -> [spill 1] - v38 Imm(0) -> [spill 2] - v39 Imm(0) -> [spill 2] - v40 LoadLocal { off=-1, kind=I32 } -> [spill 2] - v41 BinopI { op=ne, lhs=v1, rhs_imm=1 } -> x0 - terminator Bz { cond=v41, target=b2, fall=b1 } (exit_acc=v41) + v2 Imm(0) -> x0 + v3 Imm(4294967296) -> x0 + v4 Imm(2) -> x0 + v5 Imm(0) -> x0 + v6 Imm(8589934592) -> x0 + v7 Imm(3) -> x0 + v8 Imm(0) -> x0 + v9 Imm(12884901888) -> x0 + v10 Imm(4) -> x0 + v11 Imm(0) -> x0 + v12 Imm(17179869184) -> x0 + v13 Imm(5) -> x0 + v14 Imm(0) -> x0 + v15 Imm(21474836480) -> x0 + v16 Imm(6) -> x0 + v17 Imm(0) -> x0 + v18 Imm(25769803776) -> x0 + v19 Imm(7) -> x0 + v20 Imm(0) -> x0 + v21 Imm(30064771072) -> x0 + v22 Imm(8) -> x0 + v23 Imm(0) -> x0 + v24 Imm(34359738368) -> x0 + v25 Imm(9) -> x0 + v26 Imm(0) -> x0 + v27 Imm(38654705664) -> x0 + v28 Imm(10) -> x0 + v29 Imm(0) -> x0 + v30 Imm(42949672960) -> x0 + v31 Imm(255) -> x0 + v32 Imm(0) -> x0 + v33 Imm(1095216660480) -> x0 + v34 Imm(51966) -> x0 + v35 Imm(0) -> x0 + v36 Imm(223192270503936) -> x0 + v37 Imm(1000000000000) -> x0 + v38 Imm(0) -> x0 + v39 Imm(0) -> x0 + v40 LoadLocal { off=-1, kind=I32 } -> x0 + v41 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v41) block 1 start_pc=0 - v42 Imm(1) -> x0 - terminator Return(v42) (exit_acc=v42) - block 2 start_pc=0 v43 LoadLocal { off=-2, kind=I32 } -> x0 - v44 BinopI { op=ne, lhs=v4, rhs_imm=2 } -> x0 - terminator Bz { cond=v44, target=b4, fall=b3 } (exit_acc=v44) + v44 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v44) + block 2 start_pc=0 + v46 LoadLocal { off=-3, kind=I32 } -> x0 + v47 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v47) block 3 start_pc=0 - v45 Imm(2) -> x0 - terminator Return(v45) (exit_acc=v45) + v49 LoadLocal { off=-4, kind=I32 } -> x0 + v50 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v50) block 4 start_pc=0 - v46 LoadLocal { off=-3, kind=I32 } -> x0 - v47 BinopI { op=ne, lhs=v7, rhs_imm=3 } -> x0 - terminator Bz { cond=v47, target=b6, fall=b5 } (exit_acc=v47) + v52 LoadLocal { off=-5, kind=I32 } -> x0 + v53 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v53) block 5 start_pc=0 - v48 Imm(3) -> x0 - terminator Return(v48) (exit_acc=v48) + v55 LoadLocal { off=-6, kind=I32 } -> x0 + v56 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v56) block 6 start_pc=0 - v49 LoadLocal { off=-4, kind=I32 } -> x0 - v50 BinopI { op=ne, lhs=v10, rhs_imm=4 } -> x0 - terminator Bz { cond=v50, target=b8, fall=b7 } (exit_acc=v50) + v58 LoadLocal { off=-7, kind=I32 } -> x0 + v59 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v59) block 7 start_pc=0 - v51 Imm(4) -> x0 - terminator Return(v51) (exit_acc=v51) + v61 LoadLocal { off=-8, kind=I32 } -> x0 + v62 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v62) block 8 start_pc=0 - v52 LoadLocal { off=-5, kind=I32 } -> x0 - v53 BinopI { op=ne, lhs=v13, rhs_imm=5 } -> x0 - terminator Bz { cond=v53, target=b10, fall=b9 } (exit_acc=v53) + v64 LoadLocal { off=-9, kind=I32 } -> x0 + v65 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v65) block 9 start_pc=0 - v54 Imm(5) -> x0 - terminator Return(v54) (exit_acc=v54) + v67 LoadLocal { off=-10, kind=I32 } -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v68) block 10 start_pc=0 - v55 LoadLocal { off=-6, kind=I32 } -> x0 - v56 BinopI { op=ne, lhs=v16, rhs_imm=6 } -> x0 - terminator Bz { cond=v56, target=b12, fall=b11 } (exit_acc=v56) + v70 LoadLocal { off=-11, kind=I32 } -> x0 + v71 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v71) block 11 start_pc=0 - v57 Imm(6) -> x0 - terminator Return(v57) (exit_acc=v57) + v73 LoadLocal { off=-12, kind=I32 } -> x0 + v74 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v74) block 12 start_pc=0 - v58 LoadLocal { off=-7, kind=I32 } -> x0 - v59 BinopI { op=ne, lhs=v19, rhs_imm=7 } -> x0 - terminator Bz { cond=v59, target=b14, fall=b13 } (exit_acc=v59) + v76 LoadLocal { off=-13, kind=I64 } -> x0 + v77 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v77) block 13 start_pc=0 - v60 Imm(7) -> x0 - terminator Return(v60) (exit_acc=v60) + v79 LoadLocal { off=-14, kind=I64 } -> x0 + v80 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v80) block 14 start_pc=0 - v61 LoadLocal { off=-8, kind=I32 } -> x0 - v62 BinopI { op=ne, lhs=v22, rhs_imm=8 } -> x0 - terminator Bz { cond=v62, target=b16, fall=b15 } (exit_acc=v62) + v82 Imm(3) -> x0 + v83 Imm(6) -> x0 + v84 Imm(10) -> x0 + v85 Imm(0) -> x0 + v86 Imm(42949672960) -> x0 + v87 LoadLocal { off=-15, kind=I32 } -> x0 + v88 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v88) block 15 start_pc=0 - v63 Imm(8) -> x0 - terminator Return(v63) (exit_acc=v63) + v90 Imm(0) -> x0 + terminator Return(v90) (exit_acc=v90) block 16 start_pc=0 - v64 LoadLocal { off=-9, kind=I32 } -> x0 - v65 BinopI { op=ne, lhs=v25, rhs_imm=9 } -> x0 - terminator Bz { cond=v65, target=b18, fall=b17 } (exit_acc=v65) + v42 Imm(1) -> x0 + terminator Return(v42) (exit_acc=v42) block 17 start_pc=0 - v66 Imm(9) -> x0 - terminator Return(v66) (exit_acc=v66) + v45 Imm(2) -> x0 + terminator Return(v45) (exit_acc=v45) block 18 start_pc=0 - v67 LoadLocal { off=-10, kind=I32 } -> x0 - v68 BinopI { op=ne, lhs=v28, rhs_imm=10 } -> x0 - terminator Bz { cond=v68, target=b20, fall=b19 } (exit_acc=v68) + v48 Imm(3) -> x0 + terminator Return(v48) (exit_acc=v48) block 19 start_pc=0 - v69 Imm(10) -> x0 - terminator Return(v69) (exit_acc=v69) + v51 Imm(4) -> x0 + terminator Return(v51) (exit_acc=v51) block 20 start_pc=0 - v70 LoadLocal { off=-11, kind=I32 } -> x0 - v71 BinopI { op=ne, lhs=v31, rhs_imm=255 } -> x0 - terminator Bz { cond=v71, target=b22, fall=b21 } (exit_acc=v71) + v54 Imm(5) -> x0 + terminator Return(v54) (exit_acc=v54) block 21 start_pc=0 - v72 Imm(11) -> x0 - terminator Return(v72) (exit_acc=v72) + v57 Imm(6) -> x0 + terminator Return(v57) (exit_acc=v57) block 22 start_pc=0 - v73 LoadLocal { off=-12, kind=I32 } -> x0 - v74 BinopI { op=ne, lhs=v34, rhs_imm=51966 } -> x0 - terminator Bz { cond=v74, target=b24, fall=b23 } (exit_acc=v74) + v60 Imm(7) -> x0 + terminator Return(v60) (exit_acc=v60) block 23 start_pc=0 - v75 Imm(12) -> x0 - terminator Return(v75) (exit_acc=v75) + v63 Imm(8) -> x0 + terminator Return(v63) (exit_acc=v63) block 24 start_pc=0 - v76 LoadLocal { off=-13, kind=I64 } -> x0 - v77 BinopI { op=ne, lhs=v37, rhs_imm=1000000000000 } -> x0 - terminator Bz { cond=v77, target=b26, fall=b25 } (exit_acc=v77) + v66 Imm(9) -> x0 + terminator Return(v66) (exit_acc=v66) block 25 start_pc=0 - v78 Imm(13) -> x0 - terminator Return(v78) (exit_acc=v78) + v69 Imm(10) -> x0 + terminator Return(v69) (exit_acc=v69) block 26 start_pc=0 - v79 LoadLocal { off=-14, kind=I64 } -> x0 - v80 BinopI { op=ne, lhs=v3, rhs_imm=4294967296 } -> x0 - terminator Bz { cond=v80, target=b28, fall=b27 } (exit_acc=v80) + v72 Imm(11) -> x0 + terminator Return(v72) (exit_acc=v72) block 27 start_pc=0 - v81 Imm(14) -> x0 - terminator Return(v81) (exit_acc=v81) + v75 Imm(12) -> x0 + terminator Return(v75) (exit_acc=v75) block 28 start_pc=0 - v82 Imm(3) -> x0 - v83 Imm(6) -> x0 - v84 Imm(10) -> x0 - v85 Imm(0) -> x1 - v86 Imm(42949672960) -> x1 - v87 LoadLocal { off=-15, kind=I32 } -> x1 - v88 BinopI { op=ne, lhs=v84, rhs_imm=10 } -> x0 - terminator Bz { cond=v88, target=b30, fall=b29 } (exit_acc=v88) + v78 Imm(13) -> x0 + terminator Return(v78) (exit_acc=v78) block 29 start_pc=0 + v81 Imm(14) -> x0 + terminator Return(v81) (exit_acc=v81) + block 30 start_pc=0 v89 Imm(15) -> x0 terminator Return(v89) (exit_acc=v89) - block 30 start_pc=0 - v90 Imm(0) -> x0 - terminator Return(v90) (exit_acc=v90) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/inttypes_header.ssa b/tests/snapshots/ssa/inttypes_header.ssa index b902f0350..5db41bf63 100644 --- a/tests/snapshots/ssa/inttypes_header.ssa +++ b/tests/snapshots/ssa/inttypes_header.ssa @@ -39,77 +39,41 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v23 LocalAddr(-8) -> x0 v24 Imm(0) -> x0 v25 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v25) + terminator Jmp(b1) (exit_acc=v25) block 1 start_pc=0 - v26 Imm(11) -> x0 - terminator Return(v26) (exit_acc=v26) - block 2 start_pc=0 v27 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v27) - block 3 start_pc=0 - v28 Imm(12) -> x0 - terminator Return(v28) (exit_acc=v28) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v27) + block 2 start_pc=0 v29 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v29) - block 5 start_pc=0 - v30 Imm(13) -> x0 - terminator Return(v30) (exit_acc=v30) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v29) + block 3 start_pc=0 v31 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v31) - block 7 start_pc=0 - v32 Imm(14) -> x0 - terminator Return(v32) (exit_acc=v32) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v31) + block 4 start_pc=0 v33 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v33) - block 9 start_pc=0 - v34 Imm(15) -> x0 - terminator Return(v34) (exit_acc=v34) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v33) + block 5 start_pc=0 v35 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v35) - block 11 start_pc=0 - v36 Imm(16) -> x0 - terminator Return(v36) (exit_acc=v36) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v35) + block 6 start_pc=0 v37 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v37) - block 13 start_pc=0 - v38 Imm(17) -> x0 - terminator Return(v38) (exit_acc=v38) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v37) + block 7 start_pc=0 v39 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v39) - block 15 start_pc=0 - v40 Imm(18) -> x0 - terminator Return(v40) (exit_acc=v40) - block 16 start_pc=0 + terminator Jmp(b8) (exit_acc=v39) + block 8 start_pc=0 v41 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v41) - block 17 start_pc=0 - v42 Imm(19) -> x0 - terminator Return(v42) (exit_acc=v42) - block 18 start_pc=0 + terminator Jmp(b9) (exit_acc=v41) + block 9 start_pc=0 v43 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v43) - block 19 start_pc=0 - v44 Imm(20) -> x0 - terminator Return(v44) (exit_acc=v44) - block 20 start_pc=0 + terminator Jmp(b10) (exit_acc=v43) + block 10 start_pc=0 v45 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v45) - block 21 start_pc=0 - v46 Imm(21) -> x0 - terminator Return(v46) (exit_acc=v46) - block 22 start_pc=0 + terminator Jmp(b11) (exit_acc=v45) + block 11 start_pc=0 v47 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v47) - block 23 start_pc=0 - v48 Imm(22) -> x0 - terminator Return(v48) (exit_acc=v48) - block 24 start_pc=0 + terminator Jmp(b12) (exit_acc=v47) + block 12 start_pc=0 v49 ImmData(8) -> x0 v50 Imm(0) -> x1 v51 LoadLocal { off=-13, kind=I64 } -> x1 @@ -118,8 +82,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v54 BinopI { op=ne, lhs=v53, rhs_imm=108 } -> x1 v55 Imm(1) -> x6 v56 Imm(0) -> x2 - terminator Bnz { cond=v54, target=b83, fall=b25 } (exit_acc=v54) - block 25 start_pc=0 + terminator Bnz { cond=v54, target=b91, fall=b13 } (exit_acc=v54) + block 13 start_pc=0 v57 LoadLocal { off=-13, kind=I64 } -> x1 v58 Imm(1) -> x1 v59 BinopI { op=add, lhs=v49, rhs_imm=1 } -> x1 @@ -127,14 +91,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v61 BinopI { op=ne, lhs=v60, rhs_imm=108 } -> x1 v62 BinopI { op=ne, lhs=v61, rhs_imm=0 } -> x6 v63 Imm(0) -> x1 - terminator Jmp(b26) (exit_acc=v62) - block 26 start_pc=0 - v64 Phi { incoming=[b83:v55, b25:v62], kind=I64 } -> x6 + terminator Jmp(b14) (exit_acc=v62) + block 14 start_pc=0 + v64 Phi { incoming=[b91:v55, b13:v62], kind=I64 } -> x6 v65 LoadLocal { off=-23, kind=I64 } -> x1 v66 Imm(1) -> x2 v67 Imm(0) -> x1 - terminator Bnz { cond=v64, target=b84, fall=b27 } (exit_acc=v64) - block 27 start_pc=0 + terminator Bnz { cond=v64, target=b90, fall=b15 } (exit_acc=v64) + block 15 start_pc=0 v68 LoadLocal { off=-13, kind=I64 } -> x1 v69 Imm(2) -> x1 v70 BinopI { op=add, lhs=v49, rhs_imm=2 } -> x1 @@ -142,28 +106,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v72 BinopI { op=ne, lhs=v71, rhs_imm=100 } -> x1 v73 BinopI { op=ne, lhs=v72, rhs_imm=0 } -> x2 v74 Imm(0) -> x1 - terminator Jmp(b28) (exit_acc=v73) - block 28 start_pc=0 - v75 Phi { incoming=[b84:v66, b27:v73], kind=I64 } -> x2 + terminator Jmp(b16) (exit_acc=v73) + block 16 start_pc=0 + v75 Phi { incoming=[b90:v66, b15:v73], kind=I64 } -> x2 v76 LoadLocal { off=-22, kind=I64 } -> x1 v77 Imm(0) -> x1 - terminator Bnz { cond=v75, target=b85, fall=b29 } (exit_acc=v75) - block 29 start_pc=0 + terminator Bnz { cond=v75, target=b89, fall=b17 } (exit_acc=v75) + block 17 start_pc=0 v78 LoadLocal { off=-13, kind=I64 } -> x1 v79 Imm(3) -> x1 v80 BinopI { op=add, lhs=v49, rhs_imm=3 } -> x1 v81 Load { addr=v49, disp=3, kind=I8 } -> x0 v82 BinopI { op=ne, lhs=v81, rhs_imm=0 } -> x2 v83 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v82) - block 30 start_pc=0 - v84 Phi { incoming=[b85:v75, b29:v82], kind=I64 } -> x2 + terminator Jmp(b18) (exit_acc=v82) + block 18 start_pc=0 + v84 Phi { incoming=[b89:v75, b17:v82], kind=I64 } -> x2 v85 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v84, target=b32, fall=b31 } (exit_acc=v84) - block 31 start_pc=0 + terminator Bz { cond=v84, target=b20, fall=b19 } (exit_acc=v84) + block 19 start_pc=0 v86 Imm(30) -> x0 terminator Return(v86) (exit_acc=v86) - block 32 start_pc=0 + block 20 start_pc=0 v87 ImmData(12) -> x0 v88 Imm(0) -> x1 v89 LoadLocal { off=-14, kind=I64 } -> x1 @@ -172,8 +136,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v92 BinopI { op=ne, lhs=v91, rhs_imm=108 } -> x1 v93 Imm(1) -> x6 v94 Imm(0) -> x2 - terminator Bnz { cond=v92, target=b86, fall=b33 } (exit_acc=v92) - block 33 start_pc=0 + terminator Bnz { cond=v92, target=b88, fall=b21 } (exit_acc=v92) + block 21 start_pc=0 v95 LoadLocal { off=-14, kind=I64 } -> x1 v96 Imm(1) -> x1 v97 BinopI { op=add, lhs=v87, rhs_imm=1 } -> x1 @@ -181,14 +145,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v99 BinopI { op=ne, lhs=v98, rhs_imm=108 } -> x1 v100 BinopI { op=ne, lhs=v99, rhs_imm=0 } -> x6 v101 Imm(0) -> x1 - terminator Jmp(b34) (exit_acc=v100) - block 34 start_pc=0 - v102 Phi { incoming=[b86:v93, b33:v100], kind=I64 } -> x6 + terminator Jmp(b22) (exit_acc=v100) + block 22 start_pc=0 + v102 Phi { incoming=[b88:v93, b21:v100], kind=I64 } -> x6 v103 LoadLocal { off=-26, kind=I64 } -> x1 v104 Imm(1) -> x2 v105 Imm(0) -> x1 - terminator Bnz { cond=v102, target=b87, fall=b35 } (exit_acc=v102) - block 35 start_pc=0 + terminator Bnz { cond=v102, target=b87, fall=b23 } (exit_acc=v102) + block 23 start_pc=0 v106 LoadLocal { off=-14, kind=I64 } -> x1 v107 Imm(2) -> x1 v108 BinopI { op=add, lhs=v87, rhs_imm=2 } -> x1 @@ -196,28 +160,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v110 BinopI { op=ne, lhs=v109, rhs_imm=117 } -> x1 v111 BinopI { op=ne, lhs=v110, rhs_imm=0 } -> x2 v112 Imm(0) -> x1 - terminator Jmp(b36) (exit_acc=v111) - block 36 start_pc=0 - v113 Phi { incoming=[b87:v104, b35:v111], kind=I64 } -> x2 + terminator Jmp(b24) (exit_acc=v111) + block 24 start_pc=0 + v113 Phi { incoming=[b87:v104, b23:v111], kind=I64 } -> x2 v114 LoadLocal { off=-25, kind=I64 } -> x1 v115 Imm(0) -> x1 - terminator Bnz { cond=v113, target=b88, fall=b37 } (exit_acc=v113) - block 37 start_pc=0 + terminator Bnz { cond=v113, target=b86, fall=b25 } (exit_acc=v113) + block 25 start_pc=0 v116 LoadLocal { off=-14, kind=I64 } -> x1 v117 Imm(3) -> x1 v118 BinopI { op=add, lhs=v87, rhs_imm=3 } -> x1 v119 Load { addr=v87, disp=3, kind=I8 } -> x0 v120 BinopI { op=ne, lhs=v119, rhs_imm=0 } -> x2 v121 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v120) - block 38 start_pc=0 - v122 Phi { incoming=[b88:v113, b37:v120], kind=I64 } -> x2 + terminator Jmp(b26) (exit_acc=v120) + block 26 start_pc=0 + v122 Phi { incoming=[b86:v113, b25:v120], kind=I64 } -> x2 v123 LoadLocal { off=-24, kind=I64 } -> x0 - terminator Bz { cond=v122, target=b40, fall=b39 } (exit_acc=v122) - block 39 start_pc=0 + terminator Bz { cond=v122, target=b28, fall=b27 } (exit_acc=v122) + block 27 start_pc=0 v124 Imm(31) -> x0 terminator Return(v124) (exit_acc=v124) - block 40 start_pc=0 + block 28 start_pc=0 v125 ImmData(16) -> x0 v126 Imm(0) -> x1 v127 LoadLocal { off=-15, kind=I64 } -> x1 @@ -226,8 +190,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v130 BinopI { op=ne, lhs=v129, rhs_imm=108 } -> x1 v131 Imm(1) -> x6 v132 Imm(0) -> x2 - terminator Bnz { cond=v130, target=b89, fall=b41 } (exit_acc=v130) - block 41 start_pc=0 + terminator Bnz { cond=v130, target=b85, fall=b29 } (exit_acc=v130) + block 29 start_pc=0 v133 LoadLocal { off=-15, kind=I64 } -> x1 v134 Imm(1) -> x1 v135 BinopI { op=add, lhs=v125, rhs_imm=1 } -> x1 @@ -235,14 +199,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v137 BinopI { op=ne, lhs=v136, rhs_imm=108 } -> x1 v138 BinopI { op=ne, lhs=v137, rhs_imm=0 } -> x6 v139 Imm(0) -> x1 - terminator Jmp(b42) (exit_acc=v138) - block 42 start_pc=0 - v140 Phi { incoming=[b89:v131, b41:v138], kind=I64 } -> x6 + terminator Jmp(b30) (exit_acc=v138) + block 30 start_pc=0 + v140 Phi { incoming=[b85:v131, b29:v138], kind=I64 } -> x6 v141 LoadLocal { off=-29, kind=I64 } -> x1 v142 Imm(1) -> x2 v143 Imm(0) -> x1 - terminator Bnz { cond=v140, target=b90, fall=b43 } (exit_acc=v140) - block 43 start_pc=0 + terminator Bnz { cond=v140, target=b84, fall=b31 } (exit_acc=v140) + block 31 start_pc=0 v144 LoadLocal { off=-15, kind=I64 } -> x1 v145 Imm(2) -> x1 v146 BinopI { op=add, lhs=v125, rhs_imm=2 } -> x1 @@ -250,28 +214,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v148 BinopI { op=ne, lhs=v147, rhs_imm=120 } -> x1 v149 BinopI { op=ne, lhs=v148, rhs_imm=0 } -> x2 v150 Imm(0) -> x1 - terminator Jmp(b44) (exit_acc=v149) - block 44 start_pc=0 - v151 Phi { incoming=[b90:v142, b43:v149], kind=I64 } -> x2 + terminator Jmp(b32) (exit_acc=v149) + block 32 start_pc=0 + v151 Phi { incoming=[b84:v142, b31:v149], kind=I64 } -> x2 v152 LoadLocal { off=-28, kind=I64 } -> x1 v153 Imm(0) -> x1 - terminator Bnz { cond=v151, target=b91, fall=b45 } (exit_acc=v151) - block 45 start_pc=0 + terminator Bnz { cond=v151, target=b83, fall=b33 } (exit_acc=v151) + block 33 start_pc=0 v154 LoadLocal { off=-15, kind=I64 } -> x1 v155 Imm(3) -> x1 v156 BinopI { op=add, lhs=v125, rhs_imm=3 } -> x1 v157 Load { addr=v125, disp=3, kind=I8 } -> x0 v158 BinopI { op=ne, lhs=v157, rhs_imm=0 } -> x2 v159 Imm(0) -> x0 - terminator Jmp(b46) (exit_acc=v158) - block 46 start_pc=0 - v160 Phi { incoming=[b91:v151, b45:v158], kind=I64 } -> x2 + terminator Jmp(b34) (exit_acc=v158) + block 34 start_pc=0 + v160 Phi { incoming=[b83:v151, b33:v158], kind=I64 } -> x2 v161 LoadLocal { off=-27, kind=I64 } -> x0 - terminator Bz { cond=v160, target=b48, fall=b47 } (exit_acc=v160) - block 47 start_pc=0 + terminator Bz { cond=v160, target=b36, fall=b35 } (exit_acc=v160) + block 35 start_pc=0 v162 Imm(32) -> x0 terminator Return(v162) (exit_acc=v162) - block 48 start_pc=0 + block 36 start_pc=0 v163 ImmData(20) -> x0 v164 Imm(0) -> x1 v165 LoadLocal { off=-16, kind=I64 } -> x1 @@ -279,23 +243,23 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v167 Load { addr=v163, disp=0, kind=I8 } -> x1 v168 BinopI { op=ne, lhs=v167, rhs_imm=100 } -> x2 v169 Imm(0) -> x1 - terminator Bnz { cond=v168, target=b92, fall=b49 } (exit_acc=v168) - block 49 start_pc=0 + terminator Bnz { cond=v168, target=b82, fall=b37 } (exit_acc=v168) + block 37 start_pc=0 v170 LoadLocal { off=-16, kind=I64 } -> x1 v171 Imm(1) -> x1 v172 BinopI { op=add, lhs=v163, rhs_imm=1 } -> x1 v173 Load { addr=v163, disp=1, kind=I8 } -> x0 v174 BinopI { op=ne, lhs=v173, rhs_imm=0 } -> x2 v175 Imm(0) -> x0 - terminator Jmp(b50) (exit_acc=v174) - block 50 start_pc=0 - v176 Phi { incoming=[b92:v168, b49:v174], kind=I64 } -> x2 + terminator Jmp(b38) (exit_acc=v174) + block 38 start_pc=0 + v176 Phi { incoming=[b82:v168, b37:v174], kind=I64 } -> x2 v177 LoadLocal { off=-30, kind=I64 } -> x0 - terminator Bz { cond=v176, target=b52, fall=b51 } (exit_acc=v176) - block 51 start_pc=0 + terminator Bz { cond=v176, target=b40, fall=b39 } (exit_acc=v176) + block 39 start_pc=0 v178 Imm(33) -> x0 terminator Return(v178) (exit_acc=v178) - block 52 start_pc=0 + block 40 start_pc=0 v179 ImmData(22) -> x0 v180 Imm(0) -> x1 v181 LoadLocal { off=-17, kind=I64 } -> x1 @@ -304,8 +268,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v184 BinopI { op=ne, lhs=v183, rhs_imm=104 } -> x1 v185 Imm(1) -> x6 v186 Imm(0) -> x2 - terminator Bnz { cond=v184, target=b93, fall=b53 } (exit_acc=v184) - block 53 start_pc=0 + terminator Bnz { cond=v184, target=b81, fall=b41 } (exit_acc=v184) + block 41 start_pc=0 v187 LoadLocal { off=-17, kind=I64 } -> x1 v188 Imm(1) -> x1 v189 BinopI { op=add, lhs=v179, rhs_imm=1 } -> x1 @@ -313,14 +277,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v191 BinopI { op=ne, lhs=v190, rhs_imm=104 } -> x1 v192 BinopI { op=ne, lhs=v191, rhs_imm=0 } -> x6 v193 Imm(0) -> x1 - terminator Jmp(b54) (exit_acc=v192) - block 54 start_pc=0 - v194 Phi { incoming=[b93:v185, b53:v192], kind=I64 } -> x6 + terminator Jmp(b42) (exit_acc=v192) + block 42 start_pc=0 + v194 Phi { incoming=[b81:v185, b41:v192], kind=I64 } -> x6 v195 LoadLocal { off=-33, kind=I64 } -> x1 v196 Imm(1) -> x2 v197 Imm(0) -> x1 - terminator Bnz { cond=v194, target=b94, fall=b55 } (exit_acc=v194) - block 55 start_pc=0 + terminator Bnz { cond=v194, target=b80, fall=b43 } (exit_acc=v194) + block 43 start_pc=0 v198 LoadLocal { off=-17, kind=I64 } -> x1 v199 Imm(2) -> x1 v200 BinopI { op=add, lhs=v179, rhs_imm=2 } -> x1 @@ -328,28 +292,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v202 BinopI { op=ne, lhs=v201, rhs_imm=100 } -> x1 v203 BinopI { op=ne, lhs=v202, rhs_imm=0 } -> x2 v204 Imm(0) -> x1 - terminator Jmp(b56) (exit_acc=v203) - block 56 start_pc=0 - v205 Phi { incoming=[b94:v196, b55:v203], kind=I64 } -> x2 + terminator Jmp(b44) (exit_acc=v203) + block 44 start_pc=0 + v205 Phi { incoming=[b80:v196, b43:v203], kind=I64 } -> x2 v206 LoadLocal { off=-32, kind=I64 } -> x1 v207 Imm(0) -> x1 - terminator Bnz { cond=v205, target=b95, fall=b57 } (exit_acc=v205) - block 57 start_pc=0 + terminator Bnz { cond=v205, target=b79, fall=b45 } (exit_acc=v205) + block 45 start_pc=0 v208 LoadLocal { off=-17, kind=I64 } -> x1 v209 Imm(3) -> x1 v210 BinopI { op=add, lhs=v179, rhs_imm=3 } -> x1 v211 Load { addr=v179, disp=3, kind=I8 } -> x0 v212 BinopI { op=ne, lhs=v211, rhs_imm=0 } -> x2 v213 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v212) - block 58 start_pc=0 - v214 Phi { incoming=[b95:v205, b57:v212], kind=I64 } -> x2 + terminator Jmp(b46) (exit_acc=v212) + block 46 start_pc=0 + v214 Phi { incoming=[b79:v205, b45:v212], kind=I64 } -> x2 v215 LoadLocal { off=-31, kind=I64 } -> x0 - terminator Bz { cond=v214, target=b60, fall=b59 } (exit_acc=v214) - block 59 start_pc=0 + terminator Bz { cond=v214, target=b48, fall=b47 } (exit_acc=v214) + block 47 start_pc=0 v216 Imm(34) -> x0 terminator Return(v216) (exit_acc=v216) - block 60 start_pc=0 + block 48 start_pc=0 v217 ImmData(26) -> x0 v218 Imm(0) -> x1 v219 LoadLocal { off=-18, kind=I64 } -> x1 @@ -358,8 +322,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v222 BinopI { op=ne, lhs=v221, rhs_imm=104 } -> x1 v223 Imm(1) -> x6 v224 Imm(0) -> x2 - terminator Bnz { cond=v222, target=b96, fall=b61 } (exit_acc=v222) - block 61 start_pc=0 + terminator Bnz { cond=v222, target=b78, fall=b49 } (exit_acc=v222) + block 49 start_pc=0 v225 LoadLocal { off=-18, kind=I64 } -> x1 v226 Imm(1) -> x1 v227 BinopI { op=add, lhs=v217, rhs_imm=1 } -> x1 @@ -367,28 +331,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v229 BinopI { op=ne, lhs=v228, rhs_imm=100 } -> x1 v230 BinopI { op=ne, lhs=v229, rhs_imm=0 } -> x6 v231 Imm(0) -> x1 - terminator Jmp(b62) (exit_acc=v230) - block 62 start_pc=0 - v232 Phi { incoming=[b96:v223, b61:v230], kind=I64 } -> x6 + terminator Jmp(b50) (exit_acc=v230) + block 50 start_pc=0 + v232 Phi { incoming=[b78:v223, b49:v230], kind=I64 } -> x6 v233 LoadLocal { off=-35, kind=I64 } -> x1 v234 Imm(0) -> x1 - terminator Bnz { cond=v232, target=b97, fall=b63 } (exit_acc=v232) - block 63 start_pc=0 + terminator Bnz { cond=v232, target=b77, fall=b51 } (exit_acc=v232) + block 51 start_pc=0 v235 LoadLocal { off=-18, kind=I64 } -> x1 v236 Imm(2) -> x1 v237 BinopI { op=add, lhs=v217, rhs_imm=2 } -> x1 v238 Load { addr=v217, disp=2, kind=I8 } -> x0 v239 BinopI { op=ne, lhs=v238, rhs_imm=0 } -> x6 v240 Imm(0) -> x0 - terminator Jmp(b64) (exit_acc=v239) - block 64 start_pc=0 - v241 Phi { incoming=[b97:v232, b63:v239], kind=I64 } -> x6 + terminator Jmp(b52) (exit_acc=v239) + block 52 start_pc=0 + v241 Phi { incoming=[b77:v232, b51:v239], kind=I64 } -> x6 v242 LoadLocal { off=-34, kind=I64 } -> x0 - terminator Bz { cond=v241, target=b66, fall=b65 } (exit_acc=v241) - block 65 start_pc=0 + terminator Bz { cond=v241, target=b54, fall=b53 } (exit_acc=v241) + block 53 start_pc=0 v243 Imm(35) -> x0 terminator Return(v243) (exit_acc=v243) - block 66 start_pc=0 + block 54 start_pc=0 v244 ImmData(29) -> x0 v245 Imm(0) -> x1 v246 LoadLocal { off=-19, kind=I64 } -> x1 @@ -397,8 +361,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v249 BinopI { op=ne, lhs=v248, rhs_imm=108 } -> x1 v250 Imm(1) -> x6 v251 Imm(0) -> x2 - terminator Bnz { cond=v249, target=b98, fall=b67 } (exit_acc=v249) - block 67 start_pc=0 + terminator Bnz { cond=v249, target=b76, fall=b55 } (exit_acc=v249) + block 55 start_pc=0 v252 LoadLocal { off=-19, kind=I64 } -> x1 v253 Imm(1) -> x1 v254 BinopI { op=add, lhs=v244, rhs_imm=1 } -> x1 @@ -406,14 +370,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v256 BinopI { op=ne, lhs=v255, rhs_imm=108 } -> x1 v257 BinopI { op=ne, lhs=v256, rhs_imm=0 } -> x6 v258 Imm(0) -> x1 - terminator Jmp(b68) (exit_acc=v257) - block 68 start_pc=0 - v259 Phi { incoming=[b98:v250, b67:v257], kind=I64 } -> x6 + terminator Jmp(b56) (exit_acc=v257) + block 56 start_pc=0 + v259 Phi { incoming=[b76:v250, b55:v257], kind=I64 } -> x6 v260 LoadLocal { off=-38, kind=I64 } -> x1 v261 Imm(1) -> x2 v262 Imm(0) -> x1 - terminator Bnz { cond=v259, target=b99, fall=b69 } (exit_acc=v259) - block 69 start_pc=0 + terminator Bnz { cond=v259, target=b75, fall=b57 } (exit_acc=v259) + block 57 start_pc=0 v263 LoadLocal { off=-19, kind=I64 } -> x1 v264 Imm(2) -> x1 v265 BinopI { op=add, lhs=v244, rhs_imm=2 } -> x1 @@ -421,28 +385,28 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v267 BinopI { op=ne, lhs=v266, rhs_imm=100 } -> x1 v268 BinopI { op=ne, lhs=v267, rhs_imm=0 } -> x2 v269 Imm(0) -> x1 - terminator Jmp(b70) (exit_acc=v268) - block 70 start_pc=0 - v270 Phi { incoming=[b99:v261, b69:v268], kind=I64 } -> x2 + terminator Jmp(b58) (exit_acc=v268) + block 58 start_pc=0 + v270 Phi { incoming=[b75:v261, b57:v268], kind=I64 } -> x2 v271 LoadLocal { off=-37, kind=I64 } -> x1 v272 Imm(0) -> x1 - terminator Bnz { cond=v270, target=b100, fall=b71 } (exit_acc=v270) - block 71 start_pc=0 + terminator Bnz { cond=v270, target=b74, fall=b59 } (exit_acc=v270) + block 59 start_pc=0 v273 LoadLocal { off=-19, kind=I64 } -> x1 v274 Imm(3) -> x1 v275 BinopI { op=add, lhs=v244, rhs_imm=3 } -> x1 v276 Load { addr=v244, disp=3, kind=I8 } -> x0 v277 BinopI { op=ne, lhs=v276, rhs_imm=0 } -> x2 v278 Imm(0) -> x0 - terminator Jmp(b72) (exit_acc=v277) - block 72 start_pc=0 - v279 Phi { incoming=[b100:v270, b71:v277], kind=I64 } -> x2 + terminator Jmp(b60) (exit_acc=v277) + block 60 start_pc=0 + v279 Phi { incoming=[b74:v270, b59:v277], kind=I64 } -> x2 v280 LoadLocal { off=-36, kind=I64 } -> x0 - terminator Bz { cond=v279, target=b74, fall=b73 } (exit_acc=v279) - block 73 start_pc=0 + terminator Bz { cond=v279, target=b62, fall=b61 } (exit_acc=v279) + block 61 start_pc=0 v281 Imm(36) -> x0 terminator Return(v281) (exit_acc=v281) - block 74 start_pc=0 + block 62 start_pc=0 v282 ImmData(33) -> x0 v283 Imm(0) -> x1 v284 LoadLocal { off=-20, kind=I64 } -> x1 @@ -451,8 +415,8 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v287 BinopI { op=ne, lhs=v286, rhs_imm=108 } -> x1 v288 Imm(1) -> x6 v289 Imm(0) -> x2 - terminator Bnz { cond=v287, target=b101, fall=b75 } (exit_acc=v287) - block 75 start_pc=0 + terminator Bnz { cond=v287, target=b73, fall=b63 } (exit_acc=v287) + block 63 start_pc=0 v290 LoadLocal { off=-20, kind=I64 } -> x1 v291 Imm(1) -> x1 v292 BinopI { op=add, lhs=v282, rhs_imm=1 } -> x1 @@ -460,14 +424,14 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v294 BinopI { op=ne, lhs=v293, rhs_imm=108 } -> x1 v295 BinopI { op=ne, lhs=v294, rhs_imm=0 } -> x6 v296 Imm(0) -> x1 - terminator Jmp(b76) (exit_acc=v295) - block 76 start_pc=0 - v297 Phi { incoming=[b101:v288, b75:v295], kind=I64 } -> x6 + terminator Jmp(b64) (exit_acc=v295) + block 64 start_pc=0 + v297 Phi { incoming=[b73:v288, b63:v295], kind=I64 } -> x6 v298 LoadLocal { off=-41, kind=I64 } -> x1 v299 Imm(1) -> x2 v300 Imm(0) -> x1 - terminator Bnz { cond=v297, target=b102, fall=b77 } (exit_acc=v297) - block 77 start_pc=0 + terminator Bnz { cond=v297, target=b72, fall=b65 } (exit_acc=v297) + block 65 start_pc=0 v301 LoadLocal { off=-20, kind=I64 } -> x1 v302 Imm(2) -> x1 v303 BinopI { op=add, lhs=v282, rhs_imm=2 } -> x1 @@ -475,72 +439,108 @@ fn ent_pc=9 n_params=0 variadic=false locals=41 v305 BinopI { op=ne, lhs=v304, rhs_imm=100 } -> x1 v306 BinopI { op=ne, lhs=v305, rhs_imm=0 } -> x2 v307 Imm(0) -> x1 - terminator Jmp(b78) (exit_acc=v306) - block 78 start_pc=0 - v308 Phi { incoming=[b102:v299, b77:v306], kind=I64 } -> x2 + terminator Jmp(b66) (exit_acc=v306) + block 66 start_pc=0 + v308 Phi { incoming=[b72:v299, b65:v306], kind=I64 } -> x2 v309 LoadLocal { off=-40, kind=I64 } -> x1 v310 Imm(0) -> x1 - terminator Bnz { cond=v308, target=b103, fall=b79 } (exit_acc=v308) - block 79 start_pc=0 + terminator Bnz { cond=v308, target=b71, fall=b67 } (exit_acc=v308) + block 67 start_pc=0 v311 LoadLocal { off=-20, kind=I64 } -> x1 v312 Imm(3) -> x1 v313 BinopI { op=add, lhs=v282, rhs_imm=3 } -> x1 v314 Load { addr=v282, disp=3, kind=I8 } -> x0 v315 BinopI { op=ne, lhs=v314, rhs_imm=0 } -> x2 v316 Imm(0) -> x0 - terminator Jmp(b80) (exit_acc=v315) - block 80 start_pc=0 - v317 Phi { incoming=[b103:v308, b79:v315], kind=I64 } -> x2 + terminator Jmp(b68) (exit_acc=v315) + block 68 start_pc=0 + v317 Phi { incoming=[b71:v308, b67:v315], kind=I64 } -> x2 v318 LoadLocal { off=-39, kind=I64 } -> x0 - terminator Bz { cond=v317, target=b82, fall=b81 } (exit_acc=v317) - block 81 start_pc=0 + terminator Bz { cond=v317, target=b70, fall=b69 } (exit_acc=v317) + block 69 start_pc=0 v319 Imm(37) -> x0 terminator Return(v319) (exit_acc=v319) - block 82 start_pc=0 + block 70 start_pc=0 v320 Imm(0) -> x0 terminator Return(v320) (exit_acc=v320) + block 71 start_pc=0 + terminator Jmp(b68) + block 72 start_pc=0 + terminator Jmp(b66) + block 73 start_pc=0 + terminator Jmp(b64) + block 74 start_pc=0 + terminator Jmp(b60) + block 75 start_pc=0 + terminator Jmp(b58) + block 76 start_pc=0 + terminator Jmp(b56) + block 77 start_pc=0 + terminator Jmp(b52) + block 78 start_pc=0 + terminator Jmp(b50) + block 79 start_pc=0 + terminator Jmp(b46) + block 80 start_pc=0 + terminator Jmp(b44) + block 81 start_pc=0 + terminator Jmp(b42) + block 82 start_pc=0 + terminator Jmp(b38) block 83 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b34) block 84 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b32) block 85 start_pc=0 terminator Jmp(b30) block 86 start_pc=0 - terminator Jmp(b34) + terminator Jmp(b26) block 87 start_pc=0 - terminator Jmp(b36) + terminator Jmp(b24) block 88 start_pc=0 - terminator Jmp(b38) + terminator Jmp(b22) block 89 start_pc=0 - terminator Jmp(b42) + terminator Jmp(b18) block 90 start_pc=0 - terminator Jmp(b44) + terminator Jmp(b16) block 91 start_pc=0 - terminator Jmp(b46) + terminator Jmp(b14) block 92 start_pc=0 - terminator Jmp(b50) + v26 Imm(11) -> x0 + terminator Return(v26) (exit_acc=v26) block 93 start_pc=0 - terminator Jmp(b54) + v28 Imm(12) -> x0 + terminator Return(v28) (exit_acc=v28) block 94 start_pc=0 - terminator Jmp(b56) + v30 Imm(13) -> x0 + terminator Return(v30) (exit_acc=v30) block 95 start_pc=0 - terminator Jmp(b58) + v32 Imm(14) -> x0 + terminator Return(v32) (exit_acc=v32) block 96 start_pc=0 - terminator Jmp(b62) + v34 Imm(15) -> x0 + terminator Return(v34) (exit_acc=v34) block 97 start_pc=0 - terminator Jmp(b64) + v36 Imm(16) -> x0 + terminator Return(v36) (exit_acc=v36) block 98 start_pc=0 - terminator Jmp(b68) + v38 Imm(17) -> x0 + terminator Return(v38) (exit_acc=v38) block 99 start_pc=0 - terminator Jmp(b70) + v40 Imm(18) -> x0 + terminator Return(v40) (exit_acc=v40) block 100 start_pc=0 - terminator Jmp(b72) + v42 Imm(19) -> x0 + terminator Return(v42) (exit_acc=v42) block 101 start_pc=0 - terminator Jmp(b76) + v44 Imm(20) -> x0 + terminator Return(v44) (exit_acc=v44) block 102 start_pc=0 - terminator Jmp(b78) + v46 Imm(21) -> x0 + terminator Return(v46) (exit_acc=v46) block 103 start_pc=0 - terminator Jmp(b80) + v48 Imm(22) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ir_translation_while.ssa b/tests/snapshots/ssa/ir_translation_while.ssa index 831676768..379e4e7da 100644 --- a/tests/snapshots/ssa/ir_translation_while.ssa +++ b/tests/snapshots/ssa/ir_translation_while.ssa @@ -7,13 +7,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 terminator Jmp(b1) (exit_acc=v0) block 1 start_pc=0 v1 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v1) + terminator Jmp(b2) (exit_acc=v1) block 2 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 3 start_pc=0 v3 Imm(0) -> x0 terminator Return(v3) (exit_acc=v3) + block 3 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/kr_old_style_def.ssa b/tests/snapshots/ssa/kr_old_style_def.ssa index 80db654c9..60deb2f39 100644 --- a/tests/snapshots/ssa/kr_old_style_def.ssa +++ b/tests/snapshots/ssa/kr_old_style_def.ssa @@ -35,48 +35,48 @@ fn ent_pc=2 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x6 - v5 Extend { value=v2, kind=I8 } -> x1 - v6 Imm(0) -> x6 - v7 Imm(0) -> x6 - v8 Binop { op=sub, lhs=v3, rhs=v1 } -> x0 - v9 Binop { op=add, lhs=v8, rhs=v5 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=0 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(10) -> x0 - v13 Imm(5) -> x1 - v14 Imm(3) -> x2 - v15 Extend { value=v12, kind=I32 } -> x0 - v16 Imm(0) -> x6 - v17 Extend { value=v13, kind=I8 } -> x1 - v18 Imm(0) -> x6 - v19 Imm(0) -> x6 - v20 Binop { op=sub, lhs=v15, rhs=v14 } -> x0 - v21 Binop { op=add, lhs=v20, rhs=v17 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=12 } -> x0 - terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) - block 3 start_pc=0 - v23 Imm(2) -> x0 - terminator Return(v23) (exit_acc=v23) - block 4 start_pc=0 + v13 Imm(5) -> x0 + v14 Imm(3) -> x0 + v15 Imm(10) -> x0 + v16 Imm(0) -> x0 + v17 Imm(5) -> x0 + v18 Imm(0) -> x0 + v19 Imm(0) -> x0 + v20 Imm(7) -> x0 + v21 Imm(12) -> x0 + v22 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v22) + block 2 start_pc=0 v24 ImmData(8) -> x0 v25 Imm(0) -> x1 v26 Imm(0) -> x1 v27 Load { addr=v24, disp=0, kind=I8 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=90 } -> x0 - terminator Bz { cond=v28, target=b6, fall=b5 } (exit_acc=v28) - block 5 start_pc=0 + terminator Bz { cond=v28, target=b4, fall=b3 } (exit_acc=v28) + block 3 start_pc=0 v29 Imm(3) -> x0 terminator Return(v29) (exit_acc=v29) - block 6 start_pc=0 + block 4 start_pc=0 v30 Imm(0) -> x0 terminator Return(v30) (exit_acc=v30) + block 5 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 6 start_pc=0 + v23 Imm(2) -> x0 + terminator Return(v23) (exit_acc=v23) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/label_addr_array_init.ssa b/tests/snapshots/ssa/label_addr_array_init.ssa index 547f2b214..4859d7667 100644 --- a/tests/snapshots/ssa/label_addr_array_init.ssa +++ b/tests/snapshots/ssa/label_addr_array_init.ssa @@ -20,7 +20,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v14 Imm(0) -> x0 v15 StoreLocal { off=-4, value=v14, kind=I32 } -> - v16 LocalAddr(-3) -> x0 - v17 LoadLocal { off=2, kind=I32 } -> x1 + v17 Extend { value=v1, kind=I32 } -> x1 v18 BinopI { op=shl, lhs=v17, rhs_imm=3 } -> x2 v19 Binop { op=add, lhs=v16, rhs=v18 } -> x2 v20 LoadIndexed { base=v16, index=v17, scale=8, kind=I64 } -> x0 @@ -42,86 +42,128 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 terminator Return(v27) (exit_acc=v27) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=run_static -fn ent_pc=1 n_params=1 variadic=false locals=1 +fn ent_pc=1 n_params=1 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - v3 ImmData(8) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x2 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x2 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 - v9 BlockAddr(block=2) -> x2 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x2 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x2 - v13 BlockAddr(block=3) -> x2 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 StoreLocal { off=-1, value=v4, kind=I32 } -> - - v16 LoadLocal { off=2, kind=I32 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=3 } -> x2 - v18 Binop { op=add, lhs=v3, rhs=v17 } -> x2 - v19 LoadIndexed { base=v3, index=v16, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v19) (exit_acc=v19) + v4 Imm(24) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v6 Load { addr=v3, disp=24, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v20 Imm(1) -> x0 - v21 StoreLocal { off=-1, value=v20, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v21) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-2, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v22 Imm(2) -> x0 - v23 StoreLocal { off=-1, value=v22, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v23) + v9 ImmData(8) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 Imm(1) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I8 } -> - + v25 Imm(72057594037927936) -> x2 + v26 StoreLocal { off=-2, value=v23, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v26) block 3 start_pc=0 - v24 Imm(3) -> x0 - v25 StoreLocal { off=-1, value=v24, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v25) + v27 LoadLocal { off=-2, kind=I64 } -> x1 + v28 Imm(0) -> x1 + v29 StoreLocal { off=-1, value=v28, kind=I32 } -> - + v30 ImmData(8) -> x1 + v31 LoadLocal { off=2, kind=I32 } -> x1 + v32 BinopI { op=shl, lhs=v31, rhs_imm=3 } -> x2 + v33 Binop { op=add, lhs=v3, rhs=v32 } -> x2 + v34 LoadIndexed { base=v3, index=v31, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v34) (exit_acc=v34) block 4 start_pc=0 - v26 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v26) (exit_acc=v26) + v35 Imm(1) -> x0 + v36 StoreLocal { off=-1, value=v35, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v36) + block 5 start_pc=0 + v37 Imm(2) -> x0 + v38 StoreLocal { off=-1, value=v37, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v38) + block 6 start_pc=0 + v39 Imm(3) -> x0 + v40 StoreLocal { off=-1, value=v39, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v40) + block 7 start_pc=0 + v41 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=run_static_const -fn ent_pc=2 n_params=1 variadic=false locals=1 +fn ent_pc=2 n_params=1 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - - v3 ImmData(32) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x2 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x2 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 - v9 BlockAddr(block=2) -> x2 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x2 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x2 - v13 BlockAddr(block=3) -> x2 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 StoreLocal { off=-1, value=v4, kind=I32 } -> - - v16 LoadLocal { off=2, kind=I32 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=3 } -> x2 - v18 Binop { op=add, lhs=v3, rhs=v17 } -> x2 - v19 LoadIndexed { base=v3, index=v16, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v19) (exit_acc=v19) + v3 ImmData(40) -> x0 + v4 Imm(24) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v6 Load { addr=v3, disp=24, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v20 Imm(100) -> x0 - v21 StoreLocal { off=-1, value=v20, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v21) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-2, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v22 Imm(200) -> x0 - v23 StoreLocal { off=-1, value=v22, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v23) + v9 ImmData(40) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 Imm(1) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I8 } -> - + v25 Imm(72057594037927936) -> x2 + v26 StoreLocal { off=-2, value=v23, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v26) block 3 start_pc=0 - v24 Imm(300) -> x0 - v25 StoreLocal { off=-1, value=v24, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v25) + v27 LoadLocal { off=-2, kind=I64 } -> x1 + v28 Imm(0) -> x1 + v29 StoreLocal { off=-1, value=v28, kind=I32 } -> - + v30 ImmData(40) -> x1 + v31 LoadLocal { off=2, kind=I32 } -> x1 + v32 BinopI { op=shl, lhs=v31, rhs_imm=3 } -> x2 + v33 Binop { op=add, lhs=v3, rhs=v32 } -> x2 + v34 LoadIndexed { base=v3, index=v31, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v34) (exit_acc=v34) block 4 start_pc=0 - v26 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v26) (exit_acc=v26) + v35 Imm(100) -> x0 + v36 StoreLocal { off=-1, value=v35, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v36) + block 5 start_pc=0 + v37 Imm(200) -> x0 + v38 StoreLocal { off=-1, value=v37, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v38) + block 6 start_pc=0 + v39 Imm(300) -> x0 + v40 StoreLocal { off=-1, value=v39, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v40) + block 7 start_pc=0 + v41 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/large_int_literal_auto_promotes.ssa b/tests/snapshots/ssa/large_int_literal_auto_promotes.ssa index 96f60ea6c..925a2d5f4 100644 --- a/tests/snapshots/ssa/large_int_literal_auto_promotes.ssa +++ b/tests/snapshots/ssa/large_int_literal_auto_promotes.ssa @@ -5,53 +5,53 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(9223372036854775807) -> x0 - v2 Imm(0) -> x1 - v3 Imm(-9223372036854775808) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I64 } -> x2 - v6 BinopI { op=ne, lhs=v1, rhs_imm=9223372036854775807 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(-9223372036854775808) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I64 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 LoadLocal { off=-2, kind=I64 } -> x0 v9 Imm(-9223372036854775808) -> x0 - v10 BinopI { op=ne, lhs=v3, rhs_imm=-9223372036854775808 } -> x0 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v10 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v10) + block 2 start_pc=0 + v12 Imm(9223372036854775806) -> x0 + v13 Imm(0) -> x0 + v14 LoadLocal { off=-3, kind=I64 } -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) block 3 start_pc=0 - v11 Imm(2) -> x0 - terminator Return(v11) (exit_acc=v11) + v17 Imm(-9223372036854775808) -> x0 + v18 Imm(0) -> x0 + v19 LoadLocal { off=-4, kind=I64 } -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v20) block 4 start_pc=0 - v12 Imm(9223372036854775806) -> x0 - v13 Imm(0) -> x1 - v14 LoadLocal { off=-3, kind=I64 } -> x1 - v15 BinopI { op=ne, lhs=v12, rhs_imm=9223372036854775806 } -> x0 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) + v22 Imm(5000000001) -> x0 + v23 Imm(0) -> x0 + v24 LoadLocal { off=-5, kind=I64 } -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v25) block 5 start_pc=0 - v16 Imm(3) -> x0 - terminator Return(v16) (exit_acc=v16) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 6 start_pc=0 - v17 Imm(-9223372036854775808) -> x0 - v18 Imm(0) -> x1 - v19 LoadLocal { off=-4, kind=I64 } -> x1 - v20 BinopI { op=ne, lhs=v17, rhs_imm=-9223372036854775808 } -> x0 - terminator Bz { cond=v20, target=b8, fall=b7 } (exit_acc=v20) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 7 start_pc=0 - v21 Imm(4) -> x0 - terminator Return(v21) (exit_acc=v21) + v11 Imm(2) -> x0 + terminator Return(v11) (exit_acc=v11) block 8 start_pc=0 - v22 Imm(5000000001) -> x0 - v23 Imm(0) -> x1 - v24 LoadLocal { off=-5, kind=I64 } -> x1 - v25 BinopI { op=ne, lhs=v22, rhs_imm=5000000001 } -> x0 - terminator Bz { cond=v25, target=b10, fall=b9 } (exit_acc=v25) + v16 Imm(3) -> x0 + terminator Return(v16) (exit_acc=v16) block 9 start_pc=0 + v21 Imm(4) -> x0 + terminator Return(v21) (exit_acc=v21) + block 10 start_pc=0 v26 Imm(5) -> x0 terminator Return(v26) (exit_acc=v26) - block 10 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/large_stack_frame.ssa b/tests/snapshots/ssa/large_stack_frame.ssa index d95b1c905..181892795 100644 --- a/tests/snapshots/ssa/large_stack_frame.ssa +++ b/tests/snapshots/ssa/large_stack_frame.ssa @@ -624,20 +624,20 @@ fn ent_pc=6 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(40) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x1 - v9 Imm(0) -> x1 - v10 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x0 - v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x1 - v12 Extend { value=v10, kind=I32 } -> x0 - v13 Imm(0) -> x1 - v14 Imm(0) -> x1 - v15 Extend { value=v12, kind=I32 } -> x0 + v2 Imm(40) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(40) -> x0 + v6 Imm(41) -> x0 + v7 Imm(176093659136) -> x0 + v8 Imm(41) -> x0 + v9 Imm(0) -> x0 + v10 Imm(42) -> x0 + v11 Imm(180388626432) -> x0 + v12 Imm(42) -> x0 + v13 Imm(0) -> x0 + v14 Imm(0) -> x0 + v15 Imm(42) -> x0 terminator Return(v15) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/large_struct_copy.ssa b/tests/snapshots/ssa/large_struct_copy.ssa index 6d5d85cb4..bb44021ff 100644 --- a/tests/snapshots/ssa/large_struct_copy.ssa +++ b/tests/snapshots/ssa/large_struct_copy.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=142 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-66) -> x0 @@ -49,49 +49,49 @@ fn ent_pc=1 n_params=0 variadic=false locals=142 v43 Store { addr=v40, disp=520, value=v42, kind=I32 } -> - v44 Imm(0) -> x1 v45 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v44) + terminator Jmp(b3) (exit_acc=v44) block 1 start_pc=0 - v46 Phi { incoming=[b0:v44, b2:v50], kind=I64 } -> x1 - v47 Extend { value=v46, kind=I32 } -> x0 - v48 BinopI { op=lt, lhs=v47, rhs_imm=40 } -> x0 - terminator Bz { cond=v48, target=b4, fall=b3 } (exit_acc=v48) - block 2 start_pc=0 - v49 Extend { value=v46, kind=I32 } -> x0 - v50 BinopI { op=add, lhs=v49, rhs_imm=1 } -> x1 - v51 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v50) - block 3 start_pc=0 - v52 LocalAddr(-66) -> x0 - v53 BinopI { op=add, lhs=v52, rhs_imm=16 } -> x0 - v54 Extend { value=v46, kind=I32 } -> x2 - v55 BinopI { op=shl, lhs=v54, rhs_imm=2 } -> x6 + v52 LocalAddr(-66) -> x2 + v53 BinopI { op=add, lhs=v52, rhs_imm=16 } -> x2 + v54 Extend { value=v46, kind=I32 } -> x6 + v55 BinopI { op=shl, lhs=v47, rhs_imm=2 } -> x6 v56 Binop { op=add, lhs=v53, rhs=v55 } -> x6 v57 Imm(1000) -> x6 - v58 BinopI { op=add, lhs=v54, rhs_imm=1000 } -> x6 + v58 BinopI { op=add, lhs=v47, rhs_imm=1000 } -> x6 v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x7 v60 Extend { value=v58, kind=I32 } -> x7 - v61 StoreIndexed { base=v53, index=v54, scale=4, value=v58, kind=I32 } -> - - v62 LocalAddr(-66) -> x0 - v63 BinopI { op=add, lhs=v62, rhs_imm=180 } -> x0 - v64 Extend { value=v46, kind=I32 } -> x2 - v65 BinopI { op=shl, lhs=v64, rhs_imm=2 } -> x6 + v61 StoreIndexed { base=v53, index=v47, scale=4, value=v58, kind=I32 } -> - + v62 LocalAddr(-66) -> x2 + v63 BinopI { op=add, lhs=v62, rhs_imm=180 } -> x2 + v64 Extend { value=v46, kind=I32 } -> x6 + v65 BinopI { op=shl, lhs=v47, rhs_imm=2 } -> x6 v66 Binop { op=add, lhs=v63, rhs=v65 } -> x6 v67 Imm(2000) -> x6 - v68 BinopI { op=add, lhs=v64, rhs_imm=2000 } -> x6 + v68 BinopI { op=add, lhs=v47, rhs_imm=2000 } -> x6 v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x7 v70 Extend { value=v68, kind=I32 } -> x7 - v71 StoreIndexed { base=v63, index=v64, scale=4, value=v68, kind=I32 } -> - - v72 LocalAddr(-66) -> x0 - v73 BinopI { op=add, lhs=v72, rhs_imm=344 } -> x0 - v74 Extend { value=v46, kind=I32 } -> x2 - v75 BinopI { op=shl, lhs=v74, rhs_imm=2 } -> x6 + v71 StoreIndexed { base=v63, index=v47, scale=4, value=v68, kind=I32 } -> - + v72 LocalAddr(-66) -> x2 + v73 BinopI { op=add, lhs=v72, rhs_imm=344 } -> x2 + v74 Extend { value=v46, kind=I32 } -> x6 + v75 BinopI { op=shl, lhs=v47, rhs_imm=2 } -> x6 v76 Binop { op=add, lhs=v73, rhs=v75 } -> x6 v77 Imm(3000) -> x6 - v78 BinopI { op=add, lhs=v74, rhs_imm=3000 } -> x6 + v78 BinopI { op=add, lhs=v47, rhs_imm=3000 } -> x6 v79 BinopI { op=shl, lhs=v78, rhs_imm=32 } -> x7 v80 Extend { value=v78, kind=I32 } -> x7 - v81 StoreIndexed { base=v73, index=v74, scale=4, value=v78, kind=I32 } -> - + v81 StoreIndexed { base=v73, index=v47, scale=4, value=v78, kind=I32 } -> - terminator Jmp(b2) (exit_acc=v81) + block 2 start_pc=0 + v49 Extend { value=v46, kind=I32 } -> x1 + v50 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x1 + v51 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v50) + block 3 start_pc=0 + v46 Phi { incoming=[b0:v44, b2:v50], kind=I64 } -> x1 + v47 Extend { value=v46, kind=I32 } -> x0 + v48 BinopI { op=lt, lhs=v47, rhs_imm=40 } -> x2 + terminator Bnz { cond=v48, target=b1, fall=b4 } (exit_acc=v48) block 4 start_pc=0 v82 LocalAddr(-132) -> x7 v83 Imm(126) -> x6 @@ -103,33 +103,33 @@ fn ent_pc=1 n_params=0 variadic=false locals=142 v89 LocalAddr(-132) -> x0 v90 Load { addr=v89, disp=0, kind=I32 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=100 } -> x0 - v92 Imm(1) -> x3 + v92 Imm(1) -> x2 v93 Imm(0) -> x1 - terminator Bnz { cond=v91, target=b37, fall=b5 } (exit_acc=v91) + terminator Bnz { cond=v91, target=b41, fall=b5 } (exit_acc=v91) block 5 start_pc=0 v94 LocalAddr(-132) -> x0 v95 BinopI { op=add, lhs=v94, rhs_imm=4 } -> x1 v96 Load { addr=v94, disp=4, kind=I32 } -> x0 v97 BinopI { op=ne, lhs=v96, rhs_imm=200 } -> x0 - v98 BinopI { op=ne, lhs=v97, rhs_imm=0 } -> x3 + v98 BinopI { op=ne, lhs=v97, rhs_imm=0 } -> x2 v99 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v98) block 6 start_pc=0 - v100 Phi { incoming=[b37:v92, b5:v98], kind=I64 } -> x3 + v100 Phi { incoming=[b41:v92, b5:v98], kind=I64 } -> x2 v101 LoadLocal { off=-139, kind=I64 } -> x0 - v102 Imm(1) -> x12 + v102 Imm(1) -> x1 v103 Imm(0) -> x0 - terminator Bnz { cond=v100, target=b38, fall=b7 } (exit_acc=v100) + terminator Bnz { cond=v100, target=b40, fall=b7 } (exit_acc=v100) block 7 start_pc=0 v104 LocalAddr(-132) -> x0 v105 BinopI { op=add, lhs=v104, rhs_imm=8 } -> x1 v106 Load { addr=v104, disp=8, kind=I32 } -> x0 v107 BinopI { op=ne, lhs=v106, rhs_imm=300 } -> x0 - v108 BinopI { op=ne, lhs=v107, rhs_imm=0 } -> x12 + v108 BinopI { op=ne, lhs=v107, rhs_imm=0 } -> x1 v109 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v108) block 8 start_pc=0 - v110 Phi { incoming=[b38:v102, b7:v108], kind=I64 } -> x12 + v110 Phi { incoming=[b40:v102, b7:v108], kind=I64 } -> x1 v111 LoadLocal { off=-138, kind=I64 } -> x0 v112 Imm(0) -> x0 terminator Bnz { cond=v110, target=b39, fall=b9 } (exit_acc=v110) @@ -137,11 +137,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=142 v113 LocalAddr(-132) -> x0 v114 BinopI { op=add, lhs=v113, rhs_imm=12 } -> x1 v115 Load { addr=v113, disp=12, kind=I32 } -> x0 - v116 BinopI { op=ne, lhs=v115, rhs_imm=400 } -> x12 + v116 BinopI { op=ne, lhs=v115, rhs_imm=400 } -> x1 v117 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v116) block 10 start_pc=0 - v118 Phi { incoming=[b39:v110, b9:v116], kind=I64 } -> x12 + v118 Phi { incoming=[b39:v110, b9:v116], kind=I64 } -> x1 v119 LoadLocal { off=-137, kind=I64 } -> x0 terminator Bz { cond=v118, target=b12, fall=b11 } (exit_acc=v118) block 11 start_pc=0 @@ -152,45 +152,45 @@ fn ent_pc=1 n_params=0 variadic=false locals=142 v122 BinopI { op=add, lhs=v121, rhs_imm=508 } -> x1 v123 Load { addr=v121, disp=508, kind=I32 } -> x0 v124 BinopI { op=ne, lhs=v123, rhs_imm=500 } -> x0 - v125 Imm(1) -> x3 + v125 Imm(1) -> x2 v126 Imm(0) -> x1 - terminator Bnz { cond=v124, target=b40, fall=b13 } (exit_acc=v124) + terminator Bnz { cond=v124, target=b38, fall=b13 } (exit_acc=v124) block 13 start_pc=0 v127 LocalAddr(-132) -> x0 v128 BinopI { op=add, lhs=v127, rhs_imm=512 } -> x1 v129 Load { addr=v127, disp=512, kind=I32 } -> x0 v130 BinopI { op=ne, lhs=v129, rhs_imm=600 } -> x0 - v131 BinopI { op=ne, lhs=v130, rhs_imm=0 } -> x3 + v131 BinopI { op=ne, lhs=v130, rhs_imm=0 } -> x2 v132 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v131) block 14 start_pc=0 - v133 Phi { incoming=[b40:v125, b13:v131], kind=I64 } -> x3 + v133 Phi { incoming=[b38:v125, b13:v131], kind=I64 } -> x2 v134 LoadLocal { off=-142, kind=I64 } -> x0 - v135 Imm(1) -> x12 + v135 Imm(1) -> x1 v136 Imm(0) -> x0 - terminator Bnz { cond=v133, target=b41, fall=b15 } (exit_acc=v133) + terminator Bnz { cond=v133, target=b37, fall=b15 } (exit_acc=v133) block 15 start_pc=0 v137 LocalAddr(-132) -> x0 v138 BinopI { op=add, lhs=v137, rhs_imm=516 } -> x1 v139 Load { addr=v137, disp=516, kind=I32 } -> x0 v140 BinopI { op=ne, lhs=v139, rhs_imm=700 } -> x0 - v141 BinopI { op=ne, lhs=v140, rhs_imm=0 } -> x12 + v141 BinopI { op=ne, lhs=v140, rhs_imm=0 } -> x1 v142 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v141) block 16 start_pc=0 - v143 Phi { incoming=[b41:v135, b15:v141], kind=I64 } -> x12 + v143 Phi { incoming=[b37:v135, b15:v141], kind=I64 } -> x1 v144 LoadLocal { off=-141, kind=I64 } -> x0 v145 Imm(0) -> x0 - terminator Bnz { cond=v143, target=b42, fall=b17 } (exit_acc=v143) + terminator Bnz { cond=v143, target=b36, fall=b17 } (exit_acc=v143) block 17 start_pc=0 v146 LocalAddr(-132) -> x0 v147 BinopI { op=add, lhs=v146, rhs_imm=520 } -> x1 v148 Load { addr=v146, disp=520, kind=I32 } -> x0 - v149 BinopI { op=ne, lhs=v148, rhs_imm=800 } -> x12 + v149 BinopI { op=ne, lhs=v148, rhs_imm=800 } -> x1 v150 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v149) block 18 start_pc=0 - v151 Phi { incoming=[b42:v143, b17:v149], kind=I64 } -> x12 + v151 Phi { incoming=[b36:v143, b17:v149], kind=I64 } -> x1 v152 LoadLocal { off=-140, kind=I64 } -> x0 terminator Bz { cond=v151, target=b20, fall=b19 } (exit_acc=v151) block 19 start_pc=0 @@ -224,98 +224,98 @@ fn ent_pc=1 n_params=0 variadic=false locals=142 v168 Imm(5) -> x0 terminator Return(v168) (exit_acc=v168) block 26 start_pc=0 - v169 Imm(0) -> x3 + v169 Imm(0) -> x1 v170 Imm(0) -> x0 - terminator Jmp(b27) (exit_acc=v169) + terminator Jmp(b31) (exit_acc=v169) block 27 start_pc=0 - v171 Phi { incoming=[b26:v169, b28:v175], kind=I64 } -> x3 - v172 Extend { value=v171, kind=I32 } -> x0 - v173 BinopI { op=lt, lhs=v172, rhs_imm=40 } -> x0 - terminator Bz { cond=v173, target=b30, fall=b29 } (exit_acc=v173) + v177 LocalAddr(-132) -> x2 + v178 BinopI { op=add, lhs=v177, rhs_imm=16 } -> x2 + v179 Extend { value=v171, kind=I32 } -> x6 + v180 BinopI { op=shl, lhs=v172, rhs_imm=2 } -> x6 + v181 Binop { op=add, lhs=v178, rhs=v180 } -> x6 + v182 LoadIndexed { base=v178, index=v172, scale=4, kind=I32 } -> x2 + v183 Imm(1000) -> x6 + v184 BinopI { op=add, lhs=v172, rhs_imm=1000 } -> x6 + v185 BinopI { op=shl, lhs=v184, rhs_imm=32 } -> x7 + v186 Extend { value=v184, kind=I32 } -> x6 + v187 Binop { op=ne, lhs=v182, rhs=v186 } -> x2 + terminator Bnz { cond=v187, target=b35, fall=b28 } (exit_acc=v187) block 28 start_pc=0 - v174 Extend { value=v171, kind=I32 } -> x0 - v175 BinopI { op=add, lhs=v174, rhs_imm=1 } -> x3 - v176 Imm(0) -> x0 - terminator Jmp(b27) (exit_acc=v175) + v196 LocalAddr(-132) -> x2 + v197 BinopI { op=add, lhs=v196, rhs_imm=180 } -> x2 + v198 Extend { value=v171, kind=I32 } -> x6 + v199 BinopI { op=shl, lhs=v172, rhs_imm=2 } -> x6 + v200 Binop { op=add, lhs=v197, rhs=v199 } -> x6 + v201 LoadIndexed { base=v197, index=v172, scale=4, kind=I32 } -> x2 + v202 Imm(2000) -> x6 + v203 BinopI { op=add, lhs=v172, rhs_imm=2000 } -> x6 + v204 BinopI { op=shl, lhs=v203, rhs_imm=32 } -> x7 + v205 Extend { value=v203, kind=I32 } -> x6 + v206 Binop { op=ne, lhs=v201, rhs=v205 } -> x2 + terminator Bnz { cond=v206, target=b34, fall=b29 } (exit_acc=v206) block 29 start_pc=0 - v177 LocalAddr(-132) -> x0 - v178 BinopI { op=add, lhs=v177, rhs_imm=16 } -> x0 - v179 Extend { value=v171, kind=I32 } -> x1 - v180 BinopI { op=shl, lhs=v179, rhs_imm=2 } -> x2 - v181 Binop { op=add, lhs=v178, rhs=v180 } -> x2 - v182 LoadIndexed { base=v178, index=v179, scale=4, kind=I32 } -> x0 - v183 Imm(1000) -> x2 - v184 BinopI { op=add, lhs=v179, rhs_imm=1000 } -> x1 - v185 BinopI { op=shl, lhs=v184, rhs_imm=32 } -> x2 - v186 Extend { value=v184, kind=I32 } -> x1 - v187 Binop { op=ne, lhs=v182, rhs=v186 } -> x0 - terminator Bz { cond=v187, target=b32, fall=b31 } (exit_acc=v187) + v212 LocalAddr(-132) -> x2 + v213 BinopI { op=add, lhs=v212, rhs_imm=344 } -> x2 + v214 Extend { value=v171, kind=I32 } -> x6 + v215 BinopI { op=shl, lhs=v172, rhs_imm=2 } -> x6 + v216 Binop { op=add, lhs=v213, rhs=v215 } -> x6 + v217 LoadIndexed { base=v213, index=v172, scale=4, kind=I32 } -> x2 + v218 Imm(3000) -> x6 + v219 BinopI { op=add, lhs=v172, rhs_imm=3000 } -> x6 + v220 BinopI { op=shl, lhs=v219, rhs_imm=32 } -> x7 + v221 Extend { value=v219, kind=I32 } -> x6 + v222 Binop { op=ne, lhs=v217, rhs=v221 } -> x2 + terminator Bnz { cond=v222, target=b33, fall=b30 } (exit_acc=v222) block 30 start_pc=0 + v174 Extend { value=v171, kind=I32 } -> x1 + v175 BinopI { op=add, lhs=v172, rhs_imm=1 } -> x1 + v176 Imm(0) -> x0 + terminator Jmp(b31) (exit_acc=v175) + block 31 start_pc=0 + v171 Phi { incoming=[b26:v169, b30:v175], kind=I64 } -> x1 + v172 Extend { value=v171, kind=I32 } -> x0 + v173 BinopI { op=lt, lhs=v172, rhs_imm=40 } -> x2 + terminator Bnz { cond=v173, target=b27, fall=b32 } (exit_acc=v173) + block 32 start_pc=0 v188 ImmData(36) -> x7 v189 CallExt { binding_idx=0, args=[v188], fp_arg_mask=0x0 } -> x0 v190 Imm(0) -> x0 terminator Return(v190) (exit_acc=v190) - block 31 start_pc=0 - v191 Imm(10) -> x0 - v192 Extend { value=v171, kind=I32 } -> x0 - v193 BinopI { op=add, lhs=v171, rhs_imm=10 } -> x0 - v194 BinopI { op=shl, lhs=v193, rhs_imm=32 } -> x1 - v195 Extend { value=v193, kind=I32 } -> x0 - terminator Return(v195) (exit_acc=v195) - block 32 start_pc=0 - v196 LocalAddr(-132) -> x0 - v197 BinopI { op=add, lhs=v196, rhs_imm=180 } -> x0 - v198 Extend { value=v171, kind=I32 } -> x1 - v199 BinopI { op=shl, lhs=v198, rhs_imm=2 } -> x2 - v200 Binop { op=add, lhs=v197, rhs=v199 } -> x2 - v201 LoadIndexed { base=v197, index=v198, scale=4, kind=I32 } -> x0 - v202 Imm(2000) -> x2 - v203 BinopI { op=add, lhs=v198, rhs_imm=2000 } -> x1 - v204 BinopI { op=shl, lhs=v203, rhs_imm=32 } -> x2 - v205 Extend { value=v203, kind=I32 } -> x1 - v206 Binop { op=ne, lhs=v201, rhs=v205 } -> x0 - terminator Bz { cond=v206, target=b34, fall=b33 } (exit_acc=v206) block 33 start_pc=0 + v223 Imm(110) -> x0 + v224 Extend { value=v171, kind=I32 } -> x0 + v225 BinopI { op=add, lhs=v171, rhs_imm=110 } -> x0 + v226 BinopI { op=shl, lhs=v225, rhs_imm=32 } -> x1 + v227 Extend { value=v225, kind=I32 } -> x0 + terminator Return(v227) (exit_acc=v227) + block 34 start_pc=0 v207 Imm(60) -> x0 v208 Extend { value=v171, kind=I32 } -> x0 v209 BinopI { op=add, lhs=v171, rhs_imm=60 } -> x0 v210 BinopI { op=shl, lhs=v209, rhs_imm=32 } -> x1 v211 Extend { value=v209, kind=I32 } -> x0 terminator Return(v211) (exit_acc=v211) - block 34 start_pc=0 - v212 LocalAddr(-132) -> x0 - v213 BinopI { op=add, lhs=v212, rhs_imm=344 } -> x0 - v214 Extend { value=v171, kind=I32 } -> x1 - v215 BinopI { op=shl, lhs=v214, rhs_imm=2 } -> x2 - v216 Binop { op=add, lhs=v213, rhs=v215 } -> x2 - v217 LoadIndexed { base=v213, index=v214, scale=4, kind=I32 } -> x0 - v218 Imm(3000) -> x2 - v219 BinopI { op=add, lhs=v214, rhs_imm=3000 } -> x1 - v220 BinopI { op=shl, lhs=v219, rhs_imm=32 } -> x2 - v221 Extend { value=v219, kind=I32 } -> x1 - v222 Binop { op=ne, lhs=v217, rhs=v221 } -> x0 - terminator Bz { cond=v222, target=b36, fall=b35 } (exit_acc=v222) block 35 start_pc=0 - v223 Imm(110) -> x0 - v224 Extend { value=v171, kind=I32 } -> x0 - v225 BinopI { op=add, lhs=v171, rhs_imm=110 } -> x0 - v226 BinopI { op=shl, lhs=v225, rhs_imm=32 } -> x1 - v227 Extend { value=v225, kind=I32 } -> x0 - terminator Return(v227) (exit_acc=v227) + v191 Imm(10) -> x0 + v192 Extend { value=v171, kind=I32 } -> x0 + v193 BinopI { op=add, lhs=v171, rhs_imm=10 } -> x0 + v194 BinopI { op=shl, lhs=v193, rhs_imm=32 } -> x1 + v195 Extend { value=v193, kind=I32 } -> x0 + terminator Return(v195) (exit_acc=v195) block 36 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b18) block 37 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 38 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b14) block 39 start_pc=0 terminator Jmp(b10) block 40 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b8) block 41 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 42 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b30) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/layout_bottom_test_loop.ssa b/tests/snapshots/ssa/layout_bottom_test_loop.ssa new file mode 100644 index 000000000..17999da73 --- /dev/null +++ b/tests/snapshots/ssa/layout_bottom_test_loop.ssa @@ -0,0 +1,164 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(1) -> x0 + v22 Imm(2) -> x0 + v23 Imm(0) -> x0 + v24 Imm(2) -> x0 + v25 Imm(1) -> x0 + v26 Imm(1) -> x0 + v27 Imm(2) -> x0 + v28 Imm(3) -> x0 + v29 Imm(0) -> x0 + v30 Imm(3) -> x0 + v31 Imm(2) -> x0 + v32 Imm(3) -> x0 + v33 Imm(0) -> x0 + v34 Imm(3) -> x0 + v35 Imm(1) -> x0 + v36 Imm(3) -> x0 + v37 Imm(3) -> x0 + v38 Imm(6) -> x0 + v39 Imm(0) -> x0 + v40 Imm(6) -> x0 + v41 Imm(3) -> x0 + v42 Imm(4) -> x0 + v43 Imm(0) -> x0 + v44 Imm(4) -> x0 + v45 Imm(1) -> x0 + v46 Imm(6) -> x0 + v47 Imm(4) -> x0 + v48 Imm(10) -> x0 + v49 Imm(0) -> x0 + v50 Imm(10) -> x0 + v51 Imm(4) -> x0 + v52 Imm(5) -> x0 + v53 Imm(0) -> x0 + v54 Imm(5) -> x0 + v55 Imm(1) -> x0 + v56 Imm(10) -> x0 + v57 Imm(5) -> x0 + v58 Imm(15) -> x0 + v59 Imm(0) -> x0 + v60 Imm(15) -> x0 + v61 Imm(5) -> x0 + v62 Imm(6) -> x0 + v63 Imm(0) -> x0 + v64 Imm(6) -> x0 + v65 Imm(1) -> x0 + v66 Imm(15) -> x0 + v67 Imm(6) -> x0 + v68 Imm(21) -> x0 + v69 Imm(0) -> x0 + v70 Imm(21) -> x0 + v71 Imm(6) -> x0 + v72 Imm(7) -> x0 + v73 Imm(0) -> x0 + v74 Imm(7) -> x0 + v75 Imm(1) -> x0 + v76 Imm(21) -> x0 + v77 Imm(7) -> x0 + v78 Imm(28) -> x0 + v79 Imm(0) -> x0 + v80 Imm(28) -> x0 + v81 Imm(7) -> x0 + v82 Imm(8) -> x0 + v83 Imm(0) -> x0 + v84 Imm(8) -> x0 + v85 Imm(1) -> x0 + v86 Imm(28) -> x0 + v87 Imm(8) -> x0 + v88 Imm(36) -> x0 + v89 Imm(0) -> x0 + v90 Imm(36) -> x0 + v91 Imm(8) -> x0 + v92 Imm(9) -> x0 + v93 Imm(0) -> x0 + v94 Imm(9) -> x0 + v95 Imm(1) -> x0 + v96 Imm(36) -> x0 + v97 Imm(9) -> x0 + v98 Imm(45) -> x0 + v99 Imm(0) -> x0 + v100 Imm(45) -> x0 + v101 Imm(9) -> x0 + v102 Imm(10) -> x0 + v103 Imm(0) -> x0 + v104 Imm(10) -> x0 + v105 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v105) + block 2 start_pc=0 + v106 Imm(45) -> x0 + terminator Return(v106) (exit_acc=v106) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/layout_goto_block_addr.ssa b/tests/snapshots/ssa/layout_goto_block_addr.ssa new file mode 100644 index 000000000..fdae73f4f --- /dev/null +++ b/tests/snapshots/ssa/layout_goto_block_addr.ssa @@ -0,0 +1,171 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=dispatch +fn ent_pc=0 n_params=1 variadic=false locals=4 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 LocalAddr(-2) -> x0 + v4 Imm(0) -> x1 + v5 BlockAddr(block=1) -> x2 + v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - + v7 LocalAddr(-2) -> x0 + v8 Imm(8) -> x2 + v9 BinopI { op=add, lhs=v7, rhs_imm=8 } -> x2 + v10 BlockAddr(block=2) -> x2 + v11 Store { addr=v7, disp=8, value=v10, kind=I64 } -> - + v12 StoreLocal { off=-3, value=v4, kind=I32 } -> - + v13 StoreLocal { off=-4, value=v4, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v13) + block 1 start_pc=0 + v24 LoadLocal { off=-3, kind=I32 } -> x0 + v25 BinopI { op=add, lhs=v24, rhs_imm=2 } -> x0 + v26 StoreLocal { off=-3, value=v25, kind=I32 } -> - + v27 Extend { value=v25, kind=I32 } -> x0 + v28 LoadLocal { off=-4, kind=I32 } -> x0 + v29 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x0 + v30 StoreLocal { off=-4, value=v29, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v30) + block 2 start_pc=0 + v31 LoadLocal { off=-3, kind=I32 } -> x0 + v32 BinopI { op=add, lhs=v31, rhs_imm=1 } -> x0 + v33 StoreLocal { off=-3, value=v32, kind=I32 } -> - + v34 Extend { value=v32, kind=I32 } -> x0 + v35 LoadLocal { off=-4, kind=I32 } -> x0 + v36 BinopI { op=add, lhs=v35, rhs_imm=1 } -> x0 + v37 StoreLocal { off=-4, value=v36, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v37) + block 3 start_pc=0 + v14 LoadLocal { off=-4, kind=I32 } -> x0 + v15 LoadLocal { off=2, kind=I32 } -> x1 + v16 Binop { op=ge, lhs=v14, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b5, fall=b4 } (exit_acc=v16) + block 4 start_pc=0 + v17 LoadLocal { off=-3, kind=I32 } -> x0 + terminator Return(v17) (exit_acc=v17) + block 5 start_pc=0 + v18 LocalAddr(-2) -> x0 + v19 LoadLocal { off=-4, kind=I32 } -> x1 + v20 BinopI { op=and, lhs=v19, rhs_imm=1 } -> x1 + v21 BinopI { op=shl, lhs=v20, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v18, rhs=v21 } -> x2 + v23 LoadIndexed { base=v18, index=v20, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v23) (exit_acc=v23) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x7 + v6 Call { target_pc=0, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=0 } -> x3 + v8 Imm(0) -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Imm(0) -> x0 + v11 Imm(1) -> x0 + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(1) -> x0 + v15 Extend { value=v7, kind=I32 } -> x0 + v16 Imm(1) -> x7 + v17 Call { target_pc=0, args=[v16], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v18 Binop { op=add, lhs=v7, rhs=v17 } -> x3 + v19 Imm(0) -> x0 + v20 Extend { value=v18, kind=I32 } -> x0 + v21 Imm(1) -> x0 + v22 Imm(2) -> x0 + v23 Imm(0) -> x0 + v24 Imm(2) -> x0 + v25 Imm(1) -> x0 + v26 Extend { value=v18, kind=I32 } -> x0 + v27 Imm(2) -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v29 Binop { op=add, lhs=v18, rhs=v28 } -> x3 + v30 Imm(0) -> x0 + v31 Extend { value=v29, kind=I32 } -> x0 + v32 Imm(2) -> x0 + v33 Imm(3) -> x0 + v34 Imm(0) -> x0 + v35 Imm(3) -> x0 + v36 Imm(1) -> x0 + v37 Extend { value=v29, kind=I32 } -> x0 + v38 Imm(3) -> x7 + v39 Call { target_pc=0, args=[v38], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v40 Binop { op=add, lhs=v29, rhs=v39 } -> x3 + v41 Imm(0) -> x0 + v42 Extend { value=v40, kind=I32 } -> x0 + v43 Imm(3) -> x0 + v44 Imm(4) -> x0 + v45 Imm(0) -> x0 + v46 Imm(4) -> x0 + v47 Imm(1) -> x0 + v48 Extend { value=v40, kind=I32 } -> x0 + v49 Imm(4) -> x7 + v50 Call { target_pc=0, args=[v49], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v51 Binop { op=add, lhs=v40, rhs=v50 } -> x0 + v52 Imm(0) -> x1 + v53 Extend { value=v51, kind=I32 } -> x1 + v54 Imm(4) -> x1 + v55 Imm(5) -> x1 + v56 Imm(0) -> x1 + v57 Imm(5) -> x1 + v58 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v58) + block 2 start_pc=0 + v59 Extend { value=v51, kind=I32 } -> x0 + terminator Return(v59) (exit_acc=v59) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/layout_nested_loops.ssa b/tests/snapshots/ssa/layout_nested_loops.ssa new file mode 100644 index 000000000..79220f142 --- /dev/null +++ b/tests/snapshots/ssa/layout_nested_loops.ssa @@ -0,0 +1,120 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x1 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v1) + block 1 start_pc=0 + v11 Imm(0) -> x7 + v12 Imm(0) -> x6 + terminator Jmp(b8) (exit_acc=v11) + block 2 start_pc=0 + v23 Extend { value=v4, kind=I32 } -> x8 + v24 Extend { value=v14, kind=I32 } -> x8 + v25 Binop { op=add, lhs=v4, rhs=v14 } -> x8 + v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x9 + v27 Extend { value=v25, kind=I32 } -> x8 + v28 Imm(3) -> x9 + v29 Binop { op=mod, lhs=v27, rhs=v28 } -> x8 + v30 BinopI { op=eq, lhs=v29, rhs_imm=0 } -> x8 + terminator Bz { cond=v30, target=b4, fall=b3 } (exit_acc=v30) + block 3 start_pc=0 + terminator Jmp(b7) + block 4 start_pc=0 + v36 Extend { value=v14, kind=I32 } -> x8 + v37 BinopI { op=eq, lhs=v16, rhs_imm=4 } -> x8 + terminator Bz { cond=v37, target=b6, fall=b5 } (exit_acc=v37) + block 5 start_pc=0 + terminator Jmp(b7) + block 6 start_pc=0 + v38 Extend { value=v15, kind=I32 } -> x8 + v39 Extend { value=v14, kind=I32 } -> x8 + v40 Binop { op=add, lhs=v15, rhs=v14 } -> x0 + v41 Imm(0) -> x8 + v42 Extend { value=v40, kind=I32 } -> x8 + terminator Jmp(b7) (exit_acc=v42) + block 7 start_pc=0 + v19 Phi { incoming=[b3:v15, b5:v15, b6:v40], kind=I64 } -> x0 + v20 Extend { value=v14, kind=I32 } -> x7 + v21 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x7 + v22 Imm(0) -> x6 + terminator Jmp(b8) (exit_acc=v21) + block 8 start_pc=0 + v14 Phi { incoming=[b1:v11, b7:v21], kind=I64 } -> x7 + v15 Phi { incoming=[b1:v5, b7:v19], kind=I64 } -> x0 + v16 Extend { value=v14, kind=I32 } -> x6 + v17 Extend { value=v4, kind=I32 } -> x8 + v18 Binop { op=lt, lhs=v16, rhs=v6 } -> x8 + terminator Bnz { cond=v18, target=b2, fall=b9 } (exit_acc=v18) + block 9 start_pc=0 + v31 Extend { value=v15, kind=I32 } -> x6 + v32 Extend { value=v4, kind=I32 } -> x6 + v33 Binop { op=add, lhs=v15, rhs=v4 } -> x0 + v34 Imm(0) -> x6 + v35 Extend { value=v33, kind=I32 } -> x6 + terminator Jmp(b10) (exit_acc=v35) + block 10 start_pc=0 + v8 Extend { value=v4, kind=I32 } -> x1 + v9 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 + v10 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v9) + block 11 start_pc=0 + v4 Phi { incoming=[b0:v1, b10:v9], kind=I64 } -> x1 + v5 Phi { incoming=[b0:v1, b10:v33], kind=I64 } -> x0 + v6 Extend { value=v4, kind=I32 } -> x2 + v7 BinopI { op=lt, lhs=v6, rhs_imm=6 } -> x6 + terminator Bnz { cond=v7, target=b1, fall=b12 } (exit_acc=v7) + block 12 start_pc=0 + v13 Extend { value=v5, kind=I32 } -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/leading_dot_float_literal.ssa b/tests/snapshots/ssa/leading_dot_float_literal.ssa index 9f2d9791c..73aeb2b70 100644 --- a/tests/snapshots/ssa/leading_dot_float_literal.ssa +++ b/tests/snapshots/ssa/leading_dot_float_literal.ssa @@ -4,79 +4,78 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4602678819172646912) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x1 - v4 Imm(4598175219545276416) -> x1 - v5 StoreLocal { off=-2, value=v4, kind=F64 } -> - - v6 Imm(4627730092099895296) -> x1 - v7 StoreLocal { off=-3, value=v6, kind=F64 } -> - - v8 Imm(0) -> x1 - v9 Imm(1) -> x2 - v10 Imm(0) -> x1 - v11 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v12 FpCast { kind=F32ToF64, value=v2 } -> d1 + v1 Imm(1056964608) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(4598175219545276416) -> x1 + v4 StoreLocal { off=-2, value=v3, kind=F64 } -> - + v5 Imm(4627730092099895296) -> x1 + v6 StoreLocal { off=-3, value=v5, kind=F64 } -> - + v7 Imm(4602678819172646912) -> x1 + v8 FpCast { kind=F64ToF32, value=v7 } -> d0 [f32] + v9 Imm(0) -> x1 + v10 Imm(1) -> x2 + v11 Imm(0) -> x1 + v12 LoadLocal { off=-1, kind=F32 } -> d1 [f32] v13 Binop { op=fne, lhs=v12, rhs=v1 } -> x0 - terminator Bz { cond=v13, target=b12, fall=b1 } (exit_acc=v13) + terminator Bz { cond=v13, target=b15, fall=b1 } (exit_acc=v13) block 1 start_pc=0 v14 Imm(0) -> x2 v15 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v14) block 2 start_pc=0 - v16 Phi { incoming=[b12:v9, b1:v14], kind=I64 } -> x2 + v16 Phi { incoming=[b15:v10, b1:v14], kind=I64 } -> x2 v17 LoadLocal { off=-2, kind=F64 } -> d1 v18 Imm(4598175219545276416) -> x0 v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 - terminator Bz { cond=v19, target=b13, fall=b3 } (exit_acc=v19) + terminator Bz { cond=v19, target=b14, fall=b3 } (exit_acc=v19) block 3 start_pc=0 v20 Imm(0) -> x2 v21 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v20) block 4 start_pc=0 - v22 Phi { incoming=[b13:v16, b3:v20], kind=I64 } -> x2 + v22 Phi { incoming=[b14:v16, b3:v20], kind=I64 } -> x2 v23 LoadLocal { off=-3, kind=F64 } -> d1 v24 Imm(4627730092099895296) -> x0 v25 Binop { op=fne, lhs=v23, rhs=v24 } -> x0 - terminator Bz { cond=v25, target=b14, fall=b5 } (exit_acc=v25) + terminator Bz { cond=v25, target=b13, fall=b5 } (exit_acc=v25) block 5 start_pc=0 v26 Imm(0) -> x2 v27 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v28 Phi { incoming=[b14:v22, b5:v26], kind=I64 } -> x2 + v28 Phi { incoming=[b13:v22, b5:v26], kind=I64 } -> x2 v29 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v30 Imm(4602678819172646912) -> x0 - v31 FpCast { kind=F32ToF64, value=v2 } -> d0 - v32 Binop { op=fne, lhs=v31, rhs=v30 } -> x0 - terminator Bz { cond=v32, target=b15, fall=b7 } (exit_acc=v32) + v30 Imm(1056964608) -> x0 [f32] + v31 Binop { op=fne, lhs=v8, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b12, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v33 Imm(0) -> x2 - v34 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v33) + v32 Imm(0) -> x2 + v33 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v32) block 8 start_pc=0 - v35 Phi { incoming=[b15:v28, b7:v33], kind=I64 } -> x2 - v36 Extend { value=v35, kind=I32 } -> x0 - terminator Bz { cond=v36, target=b10, fall=b9 } (exit_acc=v36) + v34 Phi { incoming=[b12:v28, b7:v32], kind=I64 } -> x2 + v35 Extend { value=v34, kind=I32 } -> x0 + terminator Bz { cond=v35, target=b11, fall=b9 } (exit_acc=v35) block 9 start_pc=0 - v37 Imm(7) -> x1 - v38 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v37) + v36 Imm(7) -> x1 + v37 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v36) block 10 start_pc=0 - v39 Imm(0) -> x1 - v40 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v39) + v40 Phi { incoming=[b9:v36, b11:v38], kind=I64 } -> x1 + v41 LoadLocal { off=-6, kind=I64 } -> x0 + terminator Return(v40) (exit_acc=v40) block 11 start_pc=0 - v41 Phi { incoming=[b9:v37, b10:v39], kind=I64 } -> x1 - v42 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Return(v41) (exit_acc=v41) + v38 Imm(0) -> x1 + v39 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v38) block 12 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b8) block 13 start_pc=0 - terminator Jmp(b4) - block 14 start_pc=0 terminator Jmp(b6) + block 14 start_pc=0 + terminator Jmp(b4) block 15 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_div.ssa b/tests/snapshots/ssa/libc_div.ssa index 7f1f248a8..b445be3d3 100644 --- a/tests/snapshots/ssa/libc_div.ssa +++ b/tests/snapshots/ssa/libc_div.ssa @@ -74,17 +74,17 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(17) -> x0 - v2 Imm(5) -> x1 - v3 Extend { value=v1, kind=I32 } -> x0 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x1 - v6 Imm(0) -> x2 - v7 LocalAddr(-15) -> x2 - v8 Binop { op=div, lhs=v3, rhs=v5 } -> x6 + v2 Imm(5) -> x0 + v3 Imm(17) -> x0 + v4 Imm(0) -> x0 + v5 Imm(5) -> x0 + v6 Imm(0) -> x0 + v7 LocalAddr(-15) -> x0 + v8 Imm(3) -> x1 v9 Store { addr=v7, disp=0, value=v8, kind=I32 } -> - - v10 LocalAddr(-15) -> x2 - v11 BinopI { op=add, lhs=v10, rhs_imm=4 } -> x6 - v12 Binop { op=mod, lhs=v3, rhs=v5 } -> x0 + v10 LocalAddr(-15) -> x0 + v11 BinopI { op=add, lhs=v10, rhs_imm=4 } -> x1 + v12 Imm(2) -> x1 v13 Store { addr=v10, disp=4, value=v12, kind=I32 } -> - v14 LocalAddr(-15) -> x0 v15 LocalAddr(-15) -> x0 @@ -94,7 +94,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v19 Load { addr=v18, disp=0, kind=I32 } -> x0 v20 BinopI { op=ne, lhs=v19, rhs_imm=3 } -> x1 v21 Imm(0) -> x0 - terminator Bnz { cond=v20, target=b19, fall=b1 } (exit_acc=v20) + terminator Bnz { cond=v20, target=b22, fall=b1 } (exit_acc=v20) block 1 start_pc=0 v22 LocalAddr(-1) -> x0 v23 BinopI { op=add, lhs=v22, rhs_imm=4 } -> x1 @@ -103,7 +103,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v26 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v25) block 2 start_pc=0 - v27 Phi { incoming=[b19:v20, b1:v25], kind=I64 } -> x1 + v27 Phi { incoming=[b22:v20, b1:v25], kind=I64 } -> x1 v28 LoadLocal { off=-16, kind=I64 } -> x0 terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) block 3 start_pc=0 @@ -111,17 +111,17 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 terminator Return(v29) (exit_acc=v29) block 4 start_pc=0 v30 Imm(-17) -> x0 - v31 Imm(5) -> x1 - v32 Extend { value=v30, kind=I32 } -> x0 - v33 Imm(0) -> x2 - v34 Extend { value=v31, kind=I32 } -> x1 - v35 Imm(0) -> x2 - v36 LocalAddr(-17) -> x2 - v37 Binop { op=div, lhs=v32, rhs=v34 } -> x6 + v31 Imm(5) -> x0 + v32 Imm(-17) -> x0 + v33 Imm(0) -> x0 + v34 Imm(5) -> x0 + v35 Imm(0) -> x0 + v36 LocalAddr(-17) -> x0 + v37 Imm(-3) -> x1 v38 Store { addr=v36, disp=0, value=v37, kind=I32 } -> - - v39 LocalAddr(-17) -> x2 - v40 BinopI { op=add, lhs=v39, rhs_imm=4 } -> x6 - v41 Binop { op=mod, lhs=v32, rhs=v34 } -> x0 + v39 LocalAddr(-17) -> x0 + v40 BinopI { op=add, lhs=v39, rhs_imm=4 } -> x1 + v41 Imm(-2) -> x1 v42 Store { addr=v39, disp=4, value=v41, kind=I32 } -> - v43 LocalAddr(-17) -> x0 v44 LocalAddr(-17) -> x0 @@ -131,7 +131,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v48 Load { addr=v47, disp=0, kind=I32 } -> x0 v49 BinopI { op=ne, lhs=v48, rhs_imm=-3 } -> x1 v50 Imm(0) -> x0 - terminator Bnz { cond=v49, target=b20, fall=b5 } (exit_acc=v49) + terminator Bnz { cond=v49, target=b21, fall=b5 } (exit_acc=v49) block 5 start_pc=0 v51 LocalAddr(-3) -> x0 v52 BinopI { op=add, lhs=v51, rhs_imm=4 } -> x1 @@ -140,7 +140,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v55 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v54) block 6 start_pc=0 - v56 Phi { incoming=[b20:v49, b5:v54], kind=I64 } -> x1 + v56 Phi { incoming=[b21:v49, b5:v54], kind=I64 } -> x1 v57 LoadLocal { off=-18, kind=I64 } -> x0 terminator Bz { cond=v56, target=b8, fall=b7 } (exit_acc=v56) block 7 start_pc=0 @@ -165,15 +165,15 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 terminator Return(v71) (exit_acc=v71) block 10 start_pc=0 v72 Imm(100) -> x0 - v73 Imm(7) -> x1 - v74 Imm(0) -> x2 - v75 Imm(0) -> x2 - v76 LocalAddr(-20) -> x2 - v77 Binop { op=div, lhs=v72, rhs=v73 } -> x6 + v73 Imm(7) -> x0 + v74 Imm(0) -> x0 + v75 Imm(0) -> x0 + v76 LocalAddr(-20) -> x0 + v77 Imm(14) -> x1 v78 Store { addr=v76, disp=0, value=v77, kind=I64 } -> - - v79 LocalAddr(-20) -> x2 - v80 BinopI { op=add, lhs=v79, rhs_imm=8 } -> x6 - v81 Binop { op=mod, lhs=v72, rhs=v73 } -> x0 + v79 LocalAddr(-20) -> x0 + v80 BinopI { op=add, lhs=v79, rhs_imm=8 } -> x1 + v81 Imm(2) -> x1 v82 Store { addr=v79, disp=8, value=v81, kind=I64 } -> - v83 LocalAddr(-20) -> x0 v84 LocalAddr(-20) -> x0 @@ -183,7 +183,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v88 Load { addr=v87, disp=0, kind=I64 } -> x0 v89 BinopI { op=ne, lhs=v88, rhs_imm=14 } -> x1 v90 Imm(0) -> x0 - terminator Bnz { cond=v89, target=b21, fall=b11 } (exit_acc=v89) + terminator Bnz { cond=v89, target=b20, fall=b11 } (exit_acc=v89) block 11 start_pc=0 v91 LocalAddr(-6) -> x0 v92 BinopI { op=add, lhs=v91, rhs_imm=8 } -> x1 @@ -192,7 +192,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v95 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v94) block 12 start_pc=0 - v96 Phi { incoming=[b21:v89, b11:v94], kind=I64 } -> x1 + v96 Phi { incoming=[b20:v89, b11:v94], kind=I64 } -> x1 v97 LoadLocal { off=-21, kind=I64 } -> x0 terminator Bz { cond=v96, target=b14, fall=b13 } (exit_acc=v96) block 13 start_pc=0 @@ -200,15 +200,15 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 terminator Return(v98) (exit_acc=v98) block 14 start_pc=0 v99 Imm(1000) -> x0 - v100 Imm(3) -> x1 - v101 Imm(0) -> x2 - v102 Imm(0) -> x2 - v103 LocalAddr(-23) -> x2 - v104 Binop { op=div, lhs=v99, rhs=v100 } -> x6 + v100 Imm(3) -> x0 + v101 Imm(0) -> x0 + v102 Imm(0) -> x0 + v103 LocalAddr(-23) -> x0 + v104 Imm(333) -> x1 v105 Store { addr=v103, disp=0, value=v104, kind=I64 } -> - - v106 LocalAddr(-23) -> x2 - v107 BinopI { op=add, lhs=v106, rhs_imm=8 } -> x6 - v108 Binop { op=mod, lhs=v99, rhs=v100 } -> x0 + v106 LocalAddr(-23) -> x0 + v107 BinopI { op=add, lhs=v106, rhs_imm=8 } -> x1 + v108 Imm(1) -> x1 v109 Store { addr=v106, disp=8, value=v108, kind=I64 } -> - v110 LocalAddr(-23) -> x0 v111 LocalAddr(-23) -> x0 @@ -218,7 +218,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v115 Load { addr=v114, disp=0, kind=I64 } -> x0 v116 BinopI { op=ne, lhs=v115, rhs_imm=333 } -> x1 v117 Imm(0) -> x0 - terminator Bnz { cond=v116, target=b22, fall=b15 } (exit_acc=v116) + terminator Bnz { cond=v116, target=b19, fall=b15 } (exit_acc=v116) block 15 start_pc=0 v118 LocalAddr(-10) -> x0 v119 BinopI { op=add, lhs=v118, rhs_imm=8 } -> x1 @@ -227,7 +227,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v122 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v121) block 16 start_pc=0 - v123 Phi { incoming=[b22:v116, b15:v121], kind=I64 } -> x1 + v123 Phi { incoming=[b19:v116, b15:v121], kind=I64 } -> x1 v124 LoadLocal { off=-24, kind=I64 } -> x0 terminator Bz { cond=v123, target=b18, fall=b17 } (exit_acc=v123) block 17 start_pc=0 @@ -237,13 +237,13 @@ fn ent_pc=5 n_params=0 variadic=false locals=24 v126 Imm(0) -> x0 terminator Return(v126) (exit_acc=v126) block 19 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b16) block 20 start_pc=0 - terminator Jmp(b6) - block 21 start_pc=0 terminator Jmp(b12) + block 21 start_pc=0 + terminator Jmp(b6) block 22 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_fp_classify.ssa b/tests/snapshots/ssa/libc_fp_classify.ssa index 72af75b50..1d4b2d095 100644 --- a/tests/snapshots/ssa/libc_fp_classify.ssa +++ b/tests/snapshots/ssa/libc_fp_classify.ssa @@ -20,46 +20,46 @@ fn ent_pc=0 n_params=1 variadic=false locals=5 v14 Imm(0) -> x2 v15 LoadLocal { off=-2, kind=I64 } -> x2 v16 BinopI { op=eq, lhs=v9, rhs_imm=0 } -> x2 - terminator Bz { cond=v16, target=b2, fall=b1 } (exit_acc=v16) + terminator Bz { cond=v16, target=b5, fall=b1 } (exit_acc=v16) block 1 start_pc=0 v17 LoadLocal { off=-3, kind=I64 } -> x0 v18 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) + terminator Bz { cond=v18, target=b4, fall=b2 } (exit_acc=v18) block 2 start_pc=0 - v19 LoadLocal { off=-2, kind=I64 } -> x2 - v20 BinopI { op=eq, lhs=v9, rhs_imm=2047 } -> x0 - terminator Bz { cond=v20, target=b7, fall=b6 } (exit_acc=v20) - block 3 start_pc=0 v21 Imm(2) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v21) + terminator Jmp(b3) (exit_acc=v21) + block 3 start_pc=0 + v25 Phi { incoming=[b2:v21, b4:v23], kind=I64 } -> x1 + v26 LoadLocal { off=-4, kind=I64 } -> x0 + terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 v23 Imm(3) -> x1 v24 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v23) + terminator Jmp(b3) (exit_acc=v23) block 5 start_pc=0 - v25 Phi { incoming=[b3:v21, b4:v23], kind=I64 } -> x1 - v26 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Return(v25) (exit_acc=v25) + v19 LoadLocal { off=-2, kind=I64 } -> x2 + v20 BinopI { op=eq, lhs=v9, rhs_imm=2047 } -> x0 + terminator Bz { cond=v20, target=b10, fall=b6 } (exit_acc=v20) block 6 start_pc=0 v27 LoadLocal { off=-3, kind=I64 } -> x0 v28 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v28, target=b9, fall=b8 } (exit_acc=v28) + terminator Bz { cond=v28, target=b9, fall=b7 } (exit_acc=v28) block 7 start_pc=0 - v29 Imm(4) -> x0 - terminator Return(v29) (exit_acc=v29) - block 8 start_pc=0 v30 Imm(1) -> x1 v31 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v30) + terminator Jmp(b8) (exit_acc=v30) + block 8 start_pc=0 + v34 Phi { incoming=[b7:v30, b9:v32], kind=I64 } -> x1 + v35 LoadLocal { off=-5, kind=I64 } -> x0 + terminator Return(v34) (exit_acc=v34) block 9 start_pc=0 v32 Imm(0) -> x1 v33 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v32) + terminator Jmp(b8) (exit_acc=v32) block 10 start_pc=0 - v34 Phi { incoming=[b8:v30, b9:v32], kind=I64 } -> x1 - v35 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Return(v34) (exit_acc=v34) + v29 Imm(4) -> x0 + terminator Return(v29) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=4 --- ; name=signbit fn ent_pc=4 n_params=1 variadic=false locals=1 @@ -149,90 +149,87 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v13 Imm(2) -> x0 terminator Return(v13) (exit_acc=v13) block 4 start_pc=0 - v14 Imm(4611686018427387904) -> x3 - v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] - v16 Imm(4617315517961601024) -> x0 - v17 Fneg(v16) -> d1 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Call { target_pc=6, args=[v15, v18], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v20 Fneg(v14) -> d1 - v21 FpCast { kind=F32ToF64, value=v19 } -> d0 - v22 Binop { op=fne, lhs=v21, rhs=v20 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v14 Imm(1073741824) -> x3 [f32] + v15 Imm(1084227584) -> x0 [f32] + v16 Fneg(v15) -> d0 [f32] + v17 Call { target_pc=6, args=[v14, v16], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v18 Fneg(v14) -> d1 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 6 start_pc=0 - v24 Imm(4607182418800017408) -> x0 - v25 Fneg(v24) -> d0 - v26 Call { target_pc=4, args=[v25], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v27 BinopI { op=eq, lhs=v26, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v21 Imm(4607182418800017408) -> x0 + v22 Fneg(v21) -> d0 + v23 Call { target_pc=4, args=[v22], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x0 + terminator Bz { cond=v24, target=b8, fall=b7 } (exit_acc=v24) block 7 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) + v25 Imm(4) -> x0 + terminator Return(v25) (exit_acc=v25) block 8 start_pc=0 - v29 Imm(4607182418800017408) -> x7 - v30 Call { target_pc=4, args=[v29], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v26 Imm(4607182418800017408) -> x7 + v27 Call { target_pc=4, args=[v26], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v28 Imm(5) -> x0 + terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v32 Imm(0) -> x0 - v33 Fneg(v32) -> d0 - v34 Call { target_pc=4, args=[v33], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v35 BinopI { op=eq, lhs=v34, rhs_imm=0 } -> x0 - terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) + v29 Imm(0) -> x0 + v30 Fneg(v29) -> d0 + v31 Call { target_pc=4, args=[v30], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v32 BinopI { op=eq, lhs=v31, rhs_imm=0 } -> x0 + terminator Bz { cond=v32, target=b12, fall=b11 } (exit_acc=v32) block 11 start_pc=0 - v36 Imm(6) -> x0 - terminator Return(v36) (exit_acc=v36) + v33 Imm(6) -> x0 + terminator Return(v33) (exit_acc=v33) block 12 start_pc=0 - v37 Imm(0) -> x7 - v38 Call { target_pc=0, args=[v37], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=2 } -> x0 - terminator Bz { cond=v39, target=b14, fall=b13 } (exit_acc=v39) + v34 Imm(0) -> x7 + v35 Call { target_pc=0, args=[v34], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v36 BinopI { op=ne, lhs=v35, rhs_imm=2 } -> x0 + terminator Bz { cond=v36, target=b14, fall=b13 } (exit_acc=v36) block 13 start_pc=0 - v40 Imm(7) -> x0 - terminator Return(v40) (exit_acc=v40) + v37 Imm(7) -> x0 + terminator Return(v37) (exit_acc=v37) block 14 start_pc=0 - v41 Imm(4607182418800017408) -> x7 - v42 Call { target_pc=0, args=[v41], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=4 } -> x0 - terminator Bz { cond=v43, target=b16, fall=b15 } (exit_acc=v43) + v38 Imm(4607182418800017408) -> x7 + v39 Call { target_pc=0, args=[v38], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v40 BinopI { op=ne, lhs=v39, rhs_imm=4 } -> x0 + terminator Bz { cond=v40, target=b16, fall=b15 } (exit_acc=v40) block 15 start_pc=0 - v44 Imm(8) -> x0 - terminator Return(v44) (exit_acc=v44) + v41 Imm(8) -> x0 + terminator Return(v41) (exit_acc=v41) block 16 start_pc=0 - v45 Imm(9214871658872686752) -> x0 - v46 Imm(4621819117588971520) -> x1 - v47 Binop { op=fmul, lhs=v45, rhs=v46 } -> d0 - v48 Call { target_pc=0, args=[v47], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v49 BinopI { op=ne, lhs=v48, rhs_imm=1 } -> x0 - terminator Bz { cond=v49, target=b18, fall=b17 } (exit_acc=v49) + v42 Imm(9214871658872686752) -> x0 + v43 Imm(4621819117588971520) -> x1 + v44 Binop { op=fmul, lhs=v42, rhs=v43 } -> d0 + v45 Call { target_pc=0, args=[v44], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v46 BinopI { op=ne, lhs=v45, rhs_imm=1 } -> x0 + terminator Bz { cond=v46, target=b18, fall=b17 } (exit_acc=v46) block 17 start_pc=0 - v50 Imm(9) -> x0 - terminator Return(v50) (exit_acc=v50) + v47 Imm(9) -> x0 + terminator Return(v47) (exit_acc=v47) block 18 start_pc=0 - v51 Imm(0) -> x0 - v52 Binop { op=fdiv, lhs=v51, rhs=v51 } -> d0 - v53 Call { target_pc=0, args=[v52], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x0 - terminator Bz { cond=v54, target=b20, fall=b19 } (exit_acc=v54) + v48 Imm(0) -> x0 + v49 Binop { op=fdiv, lhs=v48, rhs=v48 } -> d0 + v50 Call { target_pc=0, args=[v49], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v51 BinopI { op=ne, lhs=v50, rhs_imm=0 } -> x0 + terminator Bz { cond=v51, target=b20, fall=b19 } (exit_acc=v51) block 19 start_pc=0 - v55 Imm(10) -> x0 - terminator Return(v55) (exit_acc=v55) + v52 Imm(10) -> x0 + terminator Return(v52) (exit_acc=v52) block 20 start_pc=0 - v56 Imm(20240225330731) -> x7 - v57 Call { target_pc=0, args=[v56], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v58 BinopI { op=ne, lhs=v57, rhs_imm=3 } -> x0 - terminator Bz { cond=v58, target=b22, fall=b21 } (exit_acc=v58) + v53 Imm(20240225330731) -> x7 + v54 Call { target_pc=0, args=[v53], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v55 BinopI { op=ne, lhs=v54, rhs_imm=3 } -> x0 + terminator Bz { cond=v55, target=b22, fall=b21 } (exit_acc=v55) block 21 start_pc=0 - v59 Imm(11) -> x0 - terminator Return(v59) (exit_acc=v59) + v56 Imm(11) -> x0 + terminator Return(v56) (exit_acc=v56) block 22 start_pc=0 - v60 Imm(0) -> x0 - terminator Return(v60) (exit_acc=v60) + v57 Imm(0) -> x0 + terminator Return(v57) (exit_acc=v57) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_fp_return_value.ssa b/tests/snapshots/ssa/libc_fp_return_value.ssa index 51ff01001..aa8948b69 100644 --- a/tests/snapshots/ssa/libc_fp_return_value.ssa +++ b/tests/snapshots/ssa/libc_fp_return_value.ssa @@ -12,52 +12,52 @@ fn ent_pc=14 n_params=0 variadic=false locals=15 v6 LoadLocal { off=-2, kind=F64 } -> d1 v7 Imm(4611686018427387904) -> x0 v8 Binop { op=fne, lhs=v4, rhs=v7 } -> x0 - terminator Bz { cond=v8, target=b26, fall=b1 } (exit_acc=v8) + terminator Bz { cond=v8, target=b36, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v9 Imm(0) -> x3 v10 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v11 Phi { incoming=[b26:v1, b1:v9], kind=I64 } -> x3 + v11 Phi { incoming=[b36:v1, b1:v9], kind=I64 } -> x3 v12 Imm(4613262278296967578) -> x0 v13 Intrinsic { kind=15, args=[v12] } -> d0 v14 Imm(0) -> x0 v15 LoadLocal { off=-3, kind=F64 } -> d1 v16 Imm(4611686018427387904) -> x0 v17 Binop { op=fne, lhs=v13, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b27, fall=b3 } (exit_acc=v17) + terminator Bz { cond=v17, target=b35, fall=b3 } (exit_acc=v17) block 3 start_pc=0 v18 Imm(0) -> x3 v19 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v20 Phi { incoming=[b27:v11, b3:v18], kind=I64 } -> x3 + v20 Phi { incoming=[b35:v11, b3:v18], kind=I64 } -> x3 v21 Imm(4612361558371493478) -> x0 v22 Intrinsic { kind=17, args=[v21] } -> d0 v23 Imm(0) -> x0 v24 LoadLocal { off=-4, kind=F64 } -> d1 v25 Imm(4613937818241073152) -> x0 v26 Binop { op=fne, lhs=v22, rhs=v25 } -> x0 - terminator Bz { cond=v26, target=b28, fall=b5 } (exit_acc=v26) + terminator Bz { cond=v26, target=b34, fall=b5 } (exit_acc=v26) block 5 start_pc=0 v27 Imm(0) -> x3 v28 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v27) block 6 start_pc=0 - v29 Phi { incoming=[b28:v20, b5:v27], kind=I64 } -> x3 + v29 Phi { incoming=[b34:v20, b5:v27], kind=I64 } -> x3 v30 Imm(4615063718147915776) -> x0 v31 Fneg(v30) -> d0 v32 Intrinsic { kind=13, args=[v31] } -> d0 v33 Imm(0) -> x1 v34 LoadLocal { off=-5, kind=F64 } -> d1 v35 Binop { op=fne, lhs=v32, rhs=v30 } -> x0 - terminator Bz { cond=v35, target=b29, fall=b7 } (exit_acc=v35) + terminator Bz { cond=v35, target=b33, fall=b7 } (exit_acc=v35) block 7 start_pc=0 v36 Imm(0) -> x3 v37 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v36) block 8 start_pc=0 - v38 Phi { incoming=[b29:v29, b7:v36], kind=I64 } -> x3 + v38 Phi { incoming=[b33:v29, b7:v36], kind=I64 } -> x3 v39 Imm(4619567317775286272) -> x7 v40 Imm(4616189618054758400) -> x6 v41 CallExt { binding_idx=62, args=[v39, v40], fp_arg_mask=0x3, fp_return=true } -> d0 @@ -65,141 +65,129 @@ fn ent_pc=14 n_params=0 variadic=false locals=15 v43 LoadLocal { off=-6, kind=F64 } -> d1 v44 Imm(4613937818241073152) -> x0 v45 Binop { op=fne, lhs=v41, rhs=v44 } -> x0 - terminator Bz { cond=v45, target=b30, fall=b9 } (exit_acc=v45) + terminator Bz { cond=v45, target=b32, fall=b9 } (exit_acc=v45) block 9 start_pc=0 v46 Imm(0) -> x3 v47 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v46) block 10 start_pc=0 - v48 Phi { incoming=[b30:v38, b9:v46], kind=I64 } -> x3 - v49 Imm(4616189618054758400) -> x0 - v50 FpCast { kind=F64ToF32, value=v49 } -> d0 [f32] - v51 Intrinsic { kind=12, args=[v50] } -> d0 [f32] - v52 Imm(0) -> x0 - v53 LoadLocal { off=-7, kind=F32 } -> d1 [f32] - v54 Imm(4611686018427387904) -> x0 - v55 FpCast { kind=F32ToF64, value=v51 } -> d0 - v56 Binop { op=fne, lhs=v55, rhs=v54 } -> x0 - terminator Bz { cond=v56, target=b31, fall=b11 } (exit_acc=v56) + v48 Phi { incoming=[b32:v38, b9:v46], kind=I64 } -> x3 + v49 Imm(1082130432) -> x0 [f32] + v50 Intrinsic { kind=12, args=[v49] } -> d0 [f32] + v51 Imm(0) -> x0 + v52 LoadLocal { off=-7, kind=F32 } -> d1 [f32] + v53 Imm(1073741824) -> x0 [f32] + v54 Binop { op=fne, lhs=v50, rhs=v53 } -> x0 + terminator Bz { cond=v54, target=b31, fall=b11 } (exit_acc=v54) block 11 start_pc=0 - v57 Imm(0) -> x3 - v58 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v57) + v55 Imm(0) -> x3 + v56 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v55) block 12 start_pc=0 - v59 Phi { incoming=[b31:v48, b11:v57], kind=I64 } -> x3 - v60 Imm(4615063718147915776) -> x0 - v61 Fneg(v60) -> d0 - v62 FpCast { kind=F64ToF32, value=v61 } -> d0 [f32] - v63 Intrinsic { kind=14, args=[v62] } -> d0 [f32] - v64 Imm(0) -> x1 - v65 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v66 FpCast { kind=F32ToF64, value=v63 } -> d0 - v67 Binop { op=fne, lhs=v66, rhs=v60 } -> x0 - terminator Bz { cond=v67, target=b32, fall=b13 } (exit_acc=v67) + v57 Phi { incoming=[b31:v48, b11:v55], kind=I64 } -> x3 + v58 Imm(1080033280) -> x0 [f32] + v59 Fneg(v58) -> d0 [f32] + v60 Intrinsic { kind=14, args=[v59] } -> d0 [f32] + v61 Imm(0) -> x1 + v62 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v63 Binop { op=fne, lhs=v60, rhs=v58 } -> x0 + terminator Bz { cond=v63, target=b30, fall=b13 } (exit_acc=v63) block 13 start_pc=0 - v68 Imm(0) -> x3 - v69 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v68) + v64 Imm(0) -> x3 + v65 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v64) block 14 start_pc=0 - v70 Phi { incoming=[b32:v59, b13:v68], kind=I64 } -> x3 - v71 Imm(4625196817309499392) -> x0 - v72 FpCast { kind=F64ToF32, value=v71 } -> d0 [f32] - v73 Intrinsic { kind=12, args=[v72] } -> d0 [f32] - v74 FpCast { kind=F32ToF64, value=v73 } -> d0 - v75 Imm(0) -> x0 - v76 LoadLocal { off=-9, kind=F64 } -> d1 - v77 Imm(4616189618054758400) -> x0 - v78 Binop { op=fne, lhs=v74, rhs=v77 } -> x0 - terminator Bz { cond=v78, target=b33, fall=b15 } (exit_acc=v78) + v66 Phi { incoming=[b30:v57, b13:v64], kind=I64 } -> x3 + v67 Imm(1098907648) -> x0 [f32] + v68 Intrinsic { kind=12, args=[v67] } -> d0 [f32] + v69 FpCast { kind=F32ToF64, value=v68 } -> d0 + v70 Imm(0) -> x0 + v71 LoadLocal { off=-9, kind=F64 } -> d1 + v72 Imm(4616189618054758400) -> x0 + v73 Binop { op=fne, lhs=v69, rhs=v72 } -> x0 + terminator Bz { cond=v73, target=b29, fall=b15 } (exit_acc=v73) block 15 start_pc=0 - v79 Imm(0) -> x3 - v80 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v79) + v74 Imm(0) -> x3 + v75 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v74) block 16 start_pc=0 - v81 Phi { incoming=[b33:v70, b15:v79], kind=I64 } -> x3 - v82 Imm(4613262278296967578) -> x0 - v83 FpCast { kind=F64ToF32, value=v82 } -> d0 [f32] - v84 Intrinsic { kind=16, args=[v83] } -> d0 [f32] - v85 Imm(0) -> x0 - v86 LoadLocal { off=-10, kind=F32 } -> d1 [f32] - v87 Imm(4611686018427387904) -> x0 - v88 FpCast { kind=F32ToF64, value=v84 } -> d0 - v89 Binop { op=fne, lhs=v88, rhs=v87 } -> x0 - terminator Bz { cond=v89, target=b34, fall=b17 } (exit_acc=v89) + v76 Phi { incoming=[b29:v66, b15:v74], kind=I64 } -> x3 + v77 Imm(1076677837) -> x0 [f32] + v78 Intrinsic { kind=16, args=[v77] } -> d0 [f32] + v79 Imm(0) -> x0 + v80 LoadLocal { off=-10, kind=F32 } -> d1 [f32] + v81 Imm(1073741824) -> x0 [f32] + v82 Binop { op=fne, lhs=v78, rhs=v81 } -> x0 + terminator Bz { cond=v82, target=b28, fall=b17 } (exit_acc=v82) block 17 start_pc=0 - v90 Imm(0) -> x3 - v91 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v90) + v83 Imm(0) -> x3 + v84 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v83) block 18 start_pc=0 - v92 Phi { incoming=[b34:v81, b17:v90], kind=I64 } -> x3 - v93 Imm(4612361558371493478) -> x0 - v94 FpCast { kind=F64ToF32, value=v93 } -> d0 [f32] - v95 Intrinsic { kind=18, args=[v94] } -> d0 [f32] - v96 Imm(0) -> x0 - v97 LoadLocal { off=-11, kind=F32 } -> d1 [f32] - v98 Imm(4613937818241073152) -> x0 - v99 FpCast { kind=F32ToF64, value=v95 } -> d0 - v100 Binop { op=fne, lhs=v99, rhs=v98 } -> x0 - terminator Bz { cond=v100, target=b35, fall=b19 } (exit_acc=v100) + v85 Phi { incoming=[b28:v76, b17:v83], kind=I64 } -> x3 + v86 Imm(1075000115) -> x0 [f32] + v87 Intrinsic { kind=18, args=[v86] } -> d0 [f32] + v88 Imm(0) -> x0 + v89 LoadLocal { off=-11, kind=F32 } -> d1 [f32] + v90 Imm(1077936128) -> x0 [f32] + v91 Binop { op=fne, lhs=v87, rhs=v90 } -> x0 + terminator Bz { cond=v91, target=b27, fall=b19 } (exit_acc=v91) block 19 start_pc=0 - v101 Imm(0) -> x3 - v102 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v101) + v92 Imm(0) -> x3 + v93 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v92) block 20 start_pc=0 - v103 Phi { incoming=[b35:v92, b19:v101], kind=I64 } -> x3 - v104 Imm(4619567317775286272) -> x0 - v105 FpCast { kind=F64ToF32, value=v104 } -> d0 [f32] - v106 Imm(4616189618054758400) -> x0 - v107 FpCast { kind=F64ToF32, value=v106 } -> d1 [f32] - v108 CallExt { binding_idx=113, args=[v105, v107], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v109 Imm(0) -> x0 - v110 LoadLocal { off=-12, kind=F32 } -> d1 [f32] - v111 Imm(4613937818241073152) -> x0 - v112 FpCast { kind=F32ToF64, value=v108 } -> d0 - v113 Binop { op=fne, lhs=v112, rhs=v111 } -> x0 - terminator Bz { cond=v113, target=b36, fall=b21 } (exit_acc=v113) + v94 Phi { incoming=[b27:v85, b19:v92], kind=I64 } -> x3 + v95 Imm(1088421888) -> x7 [f32] + v96 Imm(1082130432) -> x6 [f32] + v97 CallExt { binding_idx=113, args=[v95, v96], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v98 Imm(0) -> x0 + v99 LoadLocal { off=-12, kind=F32 } -> d1 [f32] + v100 Imm(1077936128) -> x0 [f32] + v101 Binop { op=fne, lhs=v97, rhs=v100 } -> x0 + terminator Bz { cond=v101, target=b26, fall=b21 } (exit_acc=v101) block 21 start_pc=0 - v114 Imm(0) -> x3 - v115 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v114) + v102 Imm(0) -> x3 + v103 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v102) block 22 start_pc=0 - v116 Phi { incoming=[b36:v103, b21:v114], kind=I64 } -> x3 - v117 Extend { value=v116, kind=I32 } -> x0 - terminator Bz { cond=v117, target=b24, fall=b23 } (exit_acc=v117) + v104 Phi { incoming=[b26:v94, b21:v102], kind=I64 } -> x3 + v105 Extend { value=v104, kind=I32 } -> x0 + terminator Bz { cond=v105, target=b25, fall=b23 } (exit_acc=v105) block 23 start_pc=0 - v118 Imm(11) -> x1 - v119 Imm(0) -> x0 - terminator Jmp(b25) (exit_acc=v118) + v106 Imm(11) -> x1 + v107 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v106) block 24 start_pc=0 - v120 Imm(0) -> x1 - v121 Imm(0) -> x0 - terminator Jmp(b25) (exit_acc=v120) + v110 Phi { incoming=[b23:v106, b25:v108], kind=I64 } -> x1 + v111 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Return(v110) (exit_acc=v110) block 25 start_pc=0 - v122 Phi { incoming=[b23:v118, b24:v120], kind=I64 } -> x1 - v123 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Return(v122) (exit_acc=v122) + v108 Imm(0) -> x1 + v109 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v108) block 26 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b22) block 27 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b20) block 28 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b18) block 29 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b16) block 30 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b14) block 31 start_pc=0 terminator Jmp(b12) block 32 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b10) block 33 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b8) block 34 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b6) block 35 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b4) block 36 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_int_arith.ssa b/tests/snapshots/ssa/libc_int_arith.ssa index a01bbdea3..d3fd56cd2 100644 --- a/tests/snapshots/ssa/libc_int_arith.ssa +++ b/tests/snapshots/ssa/libc_int_arith.ssa @@ -8,20 +8,20 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v5 LoadLocal { off=2, kind=I64 } -> x0 v6 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x7 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 LoadLocal { off=2, kind=I64 } -> x0 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v1) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v1], kind=I64 } -> x7 + v10 Phi { incoming=[b1:v6, b3:v1], kind=I64 } -> x7 v11 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v10) (exit_acc=v10) + block 3 start_pc=0 + v8 LoadLocal { off=2, kind=I64 } -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=llabs fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -32,20 +32,20 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v5 LoadLocal { off=2, kind=I64 } -> x0 v6 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x7 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 LoadLocal { off=2, kind=I64 } -> x0 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v1) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v1], kind=I64 } -> x7 + v10 Phi { incoming=[b1:v6, b3:v1], kind=I64 } -> x7 v11 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v10) (exit_acc=v10) + block 3 start_pc=0 + v8 LoadLocal { off=2, kind=I64 } -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=imaxabs fn ent_pc=5 n_params=1 variadic=false locals=1 @@ -56,20 +56,20 @@ fn ent_pc=5 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v5 LoadLocal { off=2, kind=I64 } -> x0 v6 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x7 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 LoadLocal { off=2, kind=I64 } -> x0 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v1) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v1], kind=I64 } -> x7 + v10 Phi { incoming=[b1:v6, b3:v1], kind=I64 } -> x7 v11 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v10) (exit_acc=v10) + block 3 start_pc=0 + v8 LoadLocal { off=2, kind=I64 } -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=6 --- ; name=imaxdiv fn ent_pc=6 n_params=2 variadic=false locals=2 @@ -130,7 +130,7 @@ fn ent_pc=8 n_params=3 variadic=false locals=3 ; --- SSA dump (ok=true) ent_pc=9 --- ; name=main fn ent_pc=9 n_params=0 variadic=false locals=10 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-7) -> x7 @@ -166,15 +166,15 @@ fn ent_pc=9 n_params=0 variadic=false locals=10 terminator Return(v16) (exit_acc=v16) block 8 start_pc=0 v17 Imm(-17) -> x0 - v18 Imm(5) -> x1 - v19 Imm(0) -> x2 - v20 Imm(0) -> x2 - v21 LocalAddr(-9) -> x2 - v22 Binop { op=div, lhs=v17, rhs=v18 } -> x6 + v18 Imm(5) -> x0 + v19 Imm(0) -> x0 + v20 Imm(0) -> x0 + v21 LocalAddr(-9) -> x0 + v22 Imm(-3) -> x1 v23 Store { addr=v21, disp=0, value=v22, kind=I64 } -> - - v24 LocalAddr(-9) -> x2 - v25 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x6 - v26 Binop { op=mod, lhs=v17, rhs=v18 } -> x0 + v24 LocalAddr(-9) -> x0 + v25 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x1 + v26 Imm(-2) -> x1 v27 Store { addr=v24, disp=8, value=v26, kind=I64 } -> - v28 LocalAddr(-9) -> x0 v29 LocalAddr(-9) -> x0 @@ -182,18 +182,18 @@ fn ent_pc=9 n_params=0 variadic=false locals=10 v31 Mcpy { dst=v30, src=v29, size=16 } -> x0 v32 LocalAddr(-2) -> x0 v33 Load { addr=v32, disp=0, kind=I64 } -> x0 - v34 BinopI { op=ne, lhs=v33, rhs_imm=-3 } -> x3 + v34 BinopI { op=ne, lhs=v33, rhs_imm=-3 } -> x1 v35 Imm(0) -> x0 terminator Bnz { cond=v34, target=b19, fall=b9 } (exit_acc=v34) block 9 start_pc=0 v36 LocalAddr(-2) -> x0 v37 BinopI { op=add, lhs=v36, rhs_imm=8 } -> x1 v38 Load { addr=v36, disp=8, kind=I64 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=-2 } -> x3 + v39 BinopI { op=ne, lhs=v38, rhs_imm=-2 } -> x1 v40 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v39) block 10 start_pc=0 - v41 Phi { incoming=[b19:v34, b9:v39], kind=I64 } -> x3 + v41 Phi { incoming=[b19:v34, b9:v39], kind=I64 } -> x1 v42 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) block 11 start_pc=0 diff --git a/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa b/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa index e7c0d86cd..b6f98a528 100644 --- a/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa +++ b/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa @@ -13,7 +13,7 @@ fn ent_pc=7 n_params=2 variadic=false locals=3 v7 Binop { op=fgt, lhs=v1, rhs=v3 } -> x0 v8 Imm(1) -> x2 v9 Imm(0) -> x1 - terminator Bnz { cond=v7, target=b8, fall=b1 } (exit_acc=v7) + terminator Bnz { cond=v7, target=b9, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v10 LoadLocal { off=2, kind=F64 } -> d2 v11 Binop { op=fne, lhs=v1, rhs=v1 } -> x0 @@ -21,36 +21,36 @@ fn ent_pc=7 n_params=2 variadic=false locals=3 v13 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v14 Phi { incoming=[b8:v8, b1:v12], kind=I64 } -> x2 + v14 Phi { incoming=[b9:v8, b1:v12], kind=I64 } -> x2 v15 LoadLocal { off=-2, kind=I64 } -> x0 v16 Imm(0) -> x0 - terminator Bnz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + terminator Bnz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v17 LoadLocal { off=3, kind=F64 } -> d2 v18 Binop { op=fne, lhs=v3, rhs=v3 } -> x2 v19 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v20 Phi { incoming=[b9:v14, b3:v18], kind=I64 } -> x2 + v20 Phi { incoming=[b8:v14, b3:v18], kind=I64 } -> x2 v21 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) + terminator Bz { cond=v20, target=b7, fall=b5 } (exit_acc=v20) block 5 start_pc=0 v22 LoadLocal { off=2, kind=F64 } -> d2 v23 LoadLocal { off=3, kind=F64 } -> d2 v24 Binop { op=fsub, lhs=v1, rhs=v3 } -> d0 v25 StoreLocal { off=-3, value=v24, kind=F64 } -> - - terminator Jmp(b7) (exit_acc=v25) + terminator Jmp(b6) (exit_acc=v25) block 6 start_pc=0 - v26 Imm(0) -> x0 - v27 StoreLocal { off=-3, value=v26, kind=F64 } -> - - terminator Jmp(b7) (exit_acc=v27) - block 7 start_pc=0 v28 LoadLocal { off=-3, kind=F64 } -> d0 terminator Return(v28) (exit_acc=v28) + block 7 start_pc=0 + v26 Imm(0) -> x0 + v27 StoreLocal { off=-3, value=v26, kind=F64 } -> - + terminator Jmp(b6) (exit_acc=v27) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) + block 9 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=8 --- ; name=fdimf fn ent_pc=8 n_params=2 variadic=false locals=4 @@ -179,33 +179,28 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v35 Imm(6) -> x0 terminator Return(v35) (exit_acc=v35) block 12 start_pc=0 - v36 Imm(4607182418800017408) -> x0 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 Imm(2) -> x7 - v39 Call { target_pc=11, args=[v37, v38], fixed_args=2, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v40 Imm(4616189618054758400) -> x0 - v41 FpCast { kind=F32ToF64, value=v39 } -> d0 - v42 Binop { op=fne, lhs=v41, rhs=v40 } -> x0 - terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) + v36 Imm(1065353216) -> x7 [f32] + v37 Imm(2) -> x6 + v38 Call { target_pc=11, args=[v36, v37], fixed_args=2, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v39 Imm(1082130432) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b14, fall=b13 } (exit_acc=v40) block 13 start_pc=0 - v43 Imm(7) -> x0 - terminator Return(v43) (exit_acc=v43) + v41 Imm(7) -> x0 + terminator Return(v41) (exit_acc=v41) block 14 start_pc=0 - v44 Imm(4617315517961601024) -> x0 - v45 FpCast { kind=F64ToF32, value=v44 } -> d0 [f32] - v46 Imm(4613937818241073152) -> x0 - v47 FpCast { kind=F64ToF32, value=v46 } -> d1 [f32] - v48 Call { target_pc=8, args=[v45, v47], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v49 Imm(4611686018427387904) -> x0 - v50 FpCast { kind=F32ToF64, value=v48 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b16, fall=b15 } (exit_acc=v51) + v42 Imm(1084227584) -> x7 [f32] + v43 Imm(1077936128) -> x6 [f32] + v44 Call { target_pc=8, args=[v42, v43], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v45 Imm(1073741824) -> x0 [f32] + v46 Binop { op=fne, lhs=v44, rhs=v45 } -> x0 + terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) block 15 start_pc=0 - v52 Imm(8) -> x0 - terminator Return(v52) (exit_acc=v52) + v47 Imm(8) -> x0 + terminator Return(v47) (exit_acc=v47) block 16 start_pc=0 - v53 Imm(0) -> x0 - terminator Return(v53) (exit_acc=v53) + v48 Imm(0) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_hyperbolic.ssa b/tests/snapshots/ssa/libc_math_hyperbolic.ssa index 89903de75..d938c762f 100644 --- a/tests/snapshots/ssa/libc_math_hyperbolic.ssa +++ b/tests/snapshots/ssa/libc_math_hyperbolic.ssa @@ -94,22 +94,22 @@ fn ent_pc=14 n_params=0 variadic=false locals=3 v34 Imm(6) -> x0 terminator Return(v34) (exit_acc=v34) block 12 start_pc=0 - v35 Imm(0) -> x3 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 CallExt { binding_idx=68, args=[v36], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v38 FpCast { kind=F32ToF64, value=v37 } -> d0 - v39 Call { target_pc=13, args=[v38, v35], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v35 Imm(0) -> x7 [f32] + v36 CallExt { binding_idx=68, args=[v35], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v37 FpCast { kind=F32ToF64, value=v36 } -> d0 + v38 Imm(0) -> x7 + v39 Call { target_pc=13, args=[v37, v38], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v40 BinopI { op=eq, lhs=v39, rhs_imm=0 } -> x0 terminator Bz { cond=v40, target=b14, fall=b13 } (exit_acc=v40) block 13 start_pc=0 v41 Imm(7) -> x0 terminator Return(v41) (exit_acc=v41) block 14 start_pc=0 - v42 Imm(0) -> x3 - v43 FpCast { kind=F64ToF32, value=v42 } -> d0 [f32] - v44 CallExt { binding_idx=70, args=[v43], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v45 FpCast { kind=F32ToF64, value=v44 } -> d0 - v46 Call { target_pc=13, args=[v45, v42], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v42 Imm(0) -> x7 [f32] + v43 CallExt { binding_idx=70, args=[v42], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v44 FpCast { kind=F32ToF64, value=v43 } -> d0 + v45 Imm(0) -> x7 + v46 Call { target_pc=13, args=[v44, v45], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v47 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x0 terminator Bz { cond=v47, target=b16, fall=b15 } (exit_acc=v47) block 15 start_pc=0 diff --git a/tests/snapshots/ssa/libc_math_libm.ssa b/tests/snapshots/ssa/libc_math_libm.ssa index b190a3db6..332773a90 100644 --- a/tests/snapshots/ssa/libc_math_libm.ssa +++ b/tests/snapshots/ssa/libc_math_libm.ssa @@ -102,35 +102,33 @@ fn ent_pc=14 n_params=0 variadic=false locals=3 v38 Imm(7) -> x0 terminator Return(v38) (exit_acc=v38) block 14 start_pc=0 - v39 Imm(4628293042053316608) -> x0 - v40 FpCast { kind=F64ToF32, value=v39 } -> d0 [f32] - v41 CallExt { binding_idx=79, args=[v40], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v42 FpCast { kind=F32ToF64, value=v41 } -> d0 - v43 Imm(4613937818241073152) -> x7 - v44 Call { target_pc=13, args=[v42, v43], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v39 Imm(1104674816) -> x7 [f32] + v40 CallExt { binding_idx=79, args=[v39], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v41 FpCast { kind=F32ToF64, value=v40 } -> d0 + v42 Imm(1077936128) -> x0 [f32] + v43 FpCast { kind=F32ToF64, value=v42 } -> d1 + v44 Call { target_pc=13, args=[v41, v43], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v45 BinopI { op=eq, lhs=v44, rhs_imm=0 } -> x0 terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) block 15 start_pc=0 v46 Imm(8) -> x0 terminator Return(v46) (exit_acc=v46) block 16 start_pc=0 - v47 Imm(4617315517961601024) -> x0 - v48 FpCast { kind=F64ToF32, value=v47 } -> d0 [f32] - v49 Imm(4613937818241073152) -> x0 - v50 FpCast { kind=F64ToF32, value=v49 } -> d1 [f32] - v51 CallExt { binding_idx=82, args=[v48, v50], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v52 FpCast { kind=F32ToF64, value=v51 } -> d0 - v53 Imm(4607182418800017408) -> x0 - v54 Fneg(v53) -> d1 - v55 Call { target_pc=13, args=[v52, v54], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v56 BinopI { op=eq, lhs=v55, rhs_imm=0 } -> x0 - terminator Bz { cond=v56, target=b18, fall=b17 } (exit_acc=v56) + v47 Imm(1084227584) -> x7 [f32] + v48 Imm(1077936128) -> x6 [f32] + v49 CallExt { binding_idx=82, args=[v47, v48], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v50 FpCast { kind=F32ToF64, value=v49 } -> d0 + v51 Imm(4607182418800017408) -> x0 + v52 Fneg(v51) -> d1 + v53 Call { target_pc=13, args=[v50, v52], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v54 BinopI { op=eq, lhs=v53, rhs_imm=0 } -> x0 + terminator Bz { cond=v54, target=b18, fall=b17 } (exit_acc=v54) block 17 start_pc=0 - v57 Imm(9) -> x0 - terminator Return(v57) (exit_acc=v57) + v55 Imm(9) -> x0 + terminator Return(v55) (exit_acc=v55) block 18 start_pc=0 - v58 Imm(0) -> x0 - terminator Return(v58) (exit_acc=v58) + v56 Imm(0) -> x0 + terminator Return(v56) (exit_acc=v56) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_minmax.ssa b/tests/snapshots/ssa/libc_math_minmax.ssa index e6781124e..b7ab32dbf 100644 --- a/tests/snapshots/ssa/libc_math_minmax.ssa +++ b/tests/snapshots/ssa/libc_math_minmax.ssa @@ -52,45 +52,36 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v28 Imm(5) -> x0 terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v29 Imm(4613937818241073152) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 Imm(4616189618054758400) -> x0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 CallExt { binding_idx=74, args=[v30, v32], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v34 Imm(4617315517961601024) -> x0 - v35 FpCast { kind=F32ToF64, value=v33 } -> d0 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) + v29 Imm(1077936128) -> x7 [f32] + v30 Imm(1082130432) -> x6 [f32] + v31 CallExt { binding_idx=74, args=[v29, v30], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v32 Imm(1084227584) -> x0 [f32] + v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x0 + terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) + v34 Imm(6) -> x0 + terminator Return(v34) (exit_acc=v34) block 12 start_pc=0 - v38 Imm(4611686018427387904) -> x3 - v39 FpCast { kind=F64ToF32, value=v38 } -> d0 [f32] - v40 Imm(4613937818241073152) -> x0 - v41 FpCast { kind=F64ToF32, value=v40 } -> d1 [f32] - v42 CallExt { binding_idx=75, args=[v39, v41], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v43 FpCast { kind=F32ToF64, value=v42 } -> d0 - v44 Binop { op=fne, lhs=v43, rhs=v38 } -> x0 - terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) + v35 Imm(1073741824) -> x3 [f32] + v36 Imm(1077936128) -> x6 [f32] + v37 CallExt { binding_idx=75, args=[v35, v36], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v38 Binop { op=fne, lhs=v37, rhs=v35 } -> x0 + terminator Bz { cond=v38, target=b14, fall=b13 } (exit_acc=v38) block 13 start_pc=0 - v45 Imm(7) -> x0 - terminator Return(v45) (exit_acc=v45) + v39 Imm(7) -> x0 + terminator Return(v39) (exit_acc=v39) block 14 start_pc=0 - v46 Imm(4611686018427387904) -> x0 - v47 FpCast { kind=F64ToF32, value=v46 } -> d0 [f32] - v48 Imm(4613937818241073152) -> x3 - v49 FpCast { kind=F64ToF32, value=v48 } -> d1 [f32] - v50 CallExt { binding_idx=76, args=[v47, v49], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v51 FpCast { kind=F32ToF64, value=v50 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v48 } -> x0 - terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) + v40 Imm(1073741824) -> x7 [f32] + v41 Imm(1077936128) -> x3 [f32] + v42 CallExt { binding_idx=76, args=[v40, v41], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x0 + terminator Bz { cond=v43, target=b16, fall=b15 } (exit_acc=v43) block 15 start_pc=0 - v53 Imm(8) -> x0 - terminator Return(v53) (exit_acc=v53) + v44 Imm(8) -> x0 + terminator Return(v44) (exit_acc=v44) block 16 start_pc=0 - v54 Imm(0) -> x0 - terminator Return(v54) (exit_acc=v54) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_nextafter.ssa b/tests/snapshots/ssa/libc_math_nextafter.ssa index 8c8cc1a5e..ff7aefdb3 100644 --- a/tests/snapshots/ssa/libc_math_nextafter.ssa +++ b/tests/snapshots/ssa/libc_math_nextafter.ssa @@ -54,29 +54,25 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v26 Imm(6) -> x0 terminator Return(v26) (exit_acc=v26) block 12 start_pc=0 - v27 Imm(4607182418800017408) -> x3 - v28 FpCast { kind=F64ToF32, value=v27 } -> d0 [f32] - v29 Imm(4611686018427387904) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d1 [f32] - v31 CallExt { binding_idx=59, args=[v28, v30], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v32 FpCast { kind=F32ToF64, value=v31 } -> d0 - v33 Binop { op=fle, lhs=v32, rhs=v27 } -> x0 - terminator Bz { cond=v33, target=b14, fall=b13 } (exit_acc=v33) + v27 Imm(1065353216) -> x3 [f32] + v28 Imm(1073741824) -> x6 [f32] + v29 CallExt { binding_idx=59, args=[v27, v28], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v30 Binop { op=fle, lhs=v29, rhs=v27 } -> x0 + terminator Bz { cond=v30, target=b14, fall=b13 } (exit_acc=v30) block 13 start_pc=0 - v34 Imm(7) -> x0 - terminator Return(v34) (exit_acc=v34) + v31 Imm(7) -> x0 + terminator Return(v31) (exit_acc=v31) block 14 start_pc=0 - v35 Imm(4625196817309499392) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 CallExt { binding_idx=60, args=[v36], fp_arg_mask=0x1 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=4 } -> x0 - terminator Bz { cond=v38, target=b16, fall=b15 } (exit_acc=v38) + v32 Imm(1098907648) -> x7 [f32] + v33 CallExt { binding_idx=60, args=[v32], fp_arg_mask=0x1 } -> x0 + v34 BinopI { op=ne, lhs=v33, rhs_imm=4 } -> x0 + terminator Bz { cond=v34, target=b16, fall=b15 } (exit_acc=v34) block 15 start_pc=0 - v39 Imm(8) -> x0 - terminator Return(v39) (exit_acc=v39) + v35 Imm(8) -> x0 + terminator Return(v35) (exit_acc=v35) block 16 start_pc=0 - v40 Imm(0) -> x0 - terminator Return(v40) (exit_acc=v40) + v36 Imm(0) -> x0 + terminator Return(v36) (exit_acc=v36) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_round.ssa b/tests/snapshots/ssa/libc_math_round.ssa index dbe78076b..bc9c3080f 100644 --- a/tests/snapshots/ssa/libc_math_round.ssa +++ b/tests/snapshots/ssa/libc_math_round.ssa @@ -67,30 +67,26 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v35 Imm(7) -> x0 terminator Return(v35) (exit_acc=v35) block 14 start_pc=0 - v36 Imm(4612811918334230528) -> x0 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 CallExt { binding_idx=77, args=[v37], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v39 Imm(4611686018427387904) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b16, fall=b15 } (exit_acc=v41) + v36 Imm(1075838976) -> x7 [f32] + v37 CallExt { binding_idx=77, args=[v36], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v38 Imm(1073741824) -> x0 [f32] + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 + terminator Bz { cond=v39, target=b16, fall=b15 } (exit_acc=v39) block 15 start_pc=0 - v42 Imm(8) -> x0 - terminator Return(v42) (exit_acc=v42) + v40 Imm(8) -> x0 + terminator Return(v40) (exit_acc=v40) block 16 start_pc=0 - v43 Imm(4615063718147915776) -> x0 - v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] - v45 CallExt { binding_idx=78, args=[v44], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v46 Imm(4616189618054758400) -> x0 - v47 FpCast { kind=F32ToF64, value=v45 } -> d0 - v48 Binop { op=fne, lhs=v47, rhs=v46 } -> x0 - terminator Bz { cond=v48, target=b18, fall=b17 } (exit_acc=v48) + v41 Imm(1080033280) -> x7 [f32] + v42 CallExt { binding_idx=78, args=[v41], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v43 Imm(1082130432) -> x0 [f32] + v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b18, fall=b17 } (exit_acc=v44) block 17 start_pc=0 - v49 Imm(9) -> x0 - terminator Return(v49) (exit_acc=v49) + v45 Imm(9) -> x0 + terminator Return(v45) (exit_acc=v45) block 18 start_pc=0 - v50 Imm(0) -> x0 - terminator Return(v50) (exit_acc=v50) + v46 Imm(0) -> x0 + terminator Return(v46) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_special.ssa b/tests/snapshots/ssa/libc_math_special.ssa index 1a040e754..f68d66bce 100644 --- a/tests/snapshots/ssa/libc_math_special.ssa +++ b/tests/snapshots/ssa/libc_math_special.ssa @@ -85,31 +85,30 @@ fn ent_pc=14 n_params=0 variadic=false locals=2 v29 Imm(5) -> x0 terminator Return(v29) (exit_acc=v29) block 10 start_pc=0 - v30 Imm(4617315517961601024) -> x0 - v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] - v32 CallExt { binding_idx=71, args=[v31], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v33 FpCast { kind=F32ToF64, value=v32 } -> d0 - v34 Imm(4627448617123184640) -> x7 - v35 Call { target_pc=13, args=[v33, v34], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v36 BinopI { op=eq, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) + v30 Imm(1084227584) -> x7 [f32] + v31 CallExt { binding_idx=71, args=[v30], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v32 FpCast { kind=F32ToF64, value=v31 } -> d0 + v33 Imm(4627448617123184640) -> x7 + v34 Call { target_pc=13, args=[v32, v33], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v35 BinopI { op=eq, lhs=v34, rhs_imm=0 } -> x0 + terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) + v36 Imm(6) -> x0 + terminator Return(v36) (exit_acc=v36) block 12 start_pc=0 - v38 Imm(0) -> x3 - v39 FpCast { kind=F64ToF32, value=v38 } -> d0 [f32] - v40 CallExt { binding_idx=72, args=[v39], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v41 FpCast { kind=F32ToF64, value=v40 } -> d0 - v42 Call { target_pc=13, args=[v41, v38], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v43 BinopI { op=eq, lhs=v42, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b14, fall=b13 } (exit_acc=v43) + v37 Imm(0) -> x7 [f32] + v38 CallExt { binding_idx=72, args=[v37], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v39 FpCast { kind=F32ToF64, value=v38 } -> d0 + v40 Imm(0) -> x7 + v41 Call { target_pc=13, args=[v39, v40], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v42 BinopI { op=eq, lhs=v41, rhs_imm=0 } -> x0 + terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) block 13 start_pc=0 - v44 Imm(7) -> x0 - terminator Return(v44) (exit_acc=v44) + v43 Imm(7) -> x0 + terminator Return(v43) (exit_acc=v43) block 14 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/line_directive.ssa b/tests/snapshots/ssa/line_directive.ssa index 5b611e320..5c33364e6 100644 --- a/tests/snapshots/ssa/line_directive.ssa +++ b/tests/snapshots/ssa/line_directive.ssa @@ -5,25 +5,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Return(v7) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 5 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 6 start_pc=0 v6 Imm(3) -> x0 terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/linked_list.ssa b/tests/snapshots/ssa/linked_list.ssa index b6b11ffa6..33e7304d3 100644 --- a/tests/snapshots/ssa/linked_list.ssa +++ b/tests/snapshots/ssa/linked_list.ssa @@ -4,66 +4,142 @@ fn ent_pc=5 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[3, 12, 13] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x12 + v1 Imm(0) -> x13 v2 Imm(0) -> x0 v3 Imm(0) -> x0 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x3 - v6 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x13 - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=5 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v5 Imm(0) -> x0 + v6 Imm(1) -> x0 + v7 Imm(16) -> x7 + v8 Imm(68719476736) -> x0 + v9 CallExt { binding_idx=0, args=[v7], fp_arg_mask=0x0 } -> x3 + v10 Imm(0) -> x0 + v11 LoadLocal { off=-3, kind=I64 } -> x0 + v12 Imm(0) -> x0 + v13 Imm(0) -> x0 + v14 Store { addr=v9, disp=0, value=v13, kind=I64 } -> - + v15 LoadLocal { off=-3, kind=I64 } -> x0 + v16 Imm(8) -> x0 + v17 BinopI { op=add, lhs=v9, rhs_imm=8 } -> x0 + v18 LoadLocal { off=-1, kind=I64 } -> x0 + v19 Store { addr=v9, disp=8, value=v1, kind=I64 } -> - + v20 LoadLocal { off=-3, kind=I64 } -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(1) -> x0 + v24 Imm(0) -> x0 + v25 Imm(1) -> x0 + v26 Imm(1) -> x0 + v27 Imm(16) -> x7 + v28 Imm(68719476736) -> x0 + v29 CallExt { binding_idx=0, args=[v27], fp_arg_mask=0x0 } -> x12 + v30 Imm(0) -> x0 + v31 LoadLocal { off=-3, kind=I64 } -> x0 + v32 Imm(0) -> x0 + v33 Imm(1) -> x0 + v34 Store { addr=v29, disp=0, value=v33, kind=I64 } -> - + v35 LoadLocal { off=-3, kind=I64 } -> x0 + v36 Imm(8) -> x0 + v37 BinopI { op=add, lhs=v29, rhs_imm=8 } -> x0 + v38 LoadLocal { off=-1, kind=I64 } -> x0 + v39 Store { addr=v29, disp=8, value=v9, kind=I64 } -> - + v40 LoadLocal { off=-3, kind=I64 } -> x0 + v41 Imm(0) -> x0 + v42 Imm(1) -> x0 + v43 Imm(2) -> x0 + v44 Imm(0) -> x0 + v45 Imm(2) -> x0 + v46 Imm(1) -> x0 + v47 Imm(16) -> x7 + v48 Imm(68719476736) -> x0 + v49 CallExt { binding_idx=0, args=[v47], fp_arg_mask=0x0 } -> x3 + v50 Imm(0) -> x0 + v51 LoadLocal { off=-3, kind=I64 } -> x0 + v52 Imm(0) -> x0 + v53 Imm(2) -> x0 + v54 Store { addr=v49, disp=0, value=v53, kind=I64 } -> - + v55 LoadLocal { off=-3, kind=I64 } -> x0 + v56 Imm(8) -> x0 + v57 BinopI { op=add, lhs=v49, rhs_imm=8 } -> x0 + v58 LoadLocal { off=-1, kind=I64 } -> x0 + v59 Store { addr=v49, disp=8, value=v29, kind=I64 } -> - + v60 LoadLocal { off=-3, kind=I64 } -> x0 + v61 Imm(0) -> x0 + v62 Imm(2) -> x0 + v63 Imm(3) -> x0 + v64 Imm(0) -> x0 + v65 Imm(3) -> x0 + v66 Imm(1) -> x0 + v67 Imm(16) -> x7 + v68 Imm(68719476736) -> x0 + v69 CallExt { binding_idx=0, args=[v67], fp_arg_mask=0x0 } -> x12 + v70 Imm(0) -> x0 + v71 LoadLocal { off=-3, kind=I64 } -> x0 + v72 Imm(0) -> x0 + v73 Imm(3) -> x0 + v74 Store { addr=v69, disp=0, value=v73, kind=I64 } -> - + v75 LoadLocal { off=-3, kind=I64 } -> x0 + v76 Imm(8) -> x0 + v77 BinopI { op=add, lhs=v69, rhs_imm=8 } -> x0 + v78 LoadLocal { off=-1, kind=I64 } -> x0 + v79 Store { addr=v69, disp=8, value=v49, kind=I64 } -> - + v80 LoadLocal { off=-3, kind=I64 } -> x0 + v81 Imm(0) -> x0 + v82 Imm(3) -> x0 + v83 Imm(4) -> x0 + v84 Imm(0) -> x0 + v85 Imm(4) -> x0 + v86 Imm(1) -> x0 + v87 Imm(16) -> x7 + v88 Imm(68719476736) -> x0 + v89 CallExt { binding_idx=0, args=[v87], fp_arg_mask=0x0 } -> x1 + v90 Imm(0) -> x0 + v91 LoadLocal { off=-3, kind=I64 } -> x0 + v92 Imm(0) -> x0 + v93 Imm(4) -> x0 + v94 Store { addr=v89, disp=0, value=v93, kind=I64 } -> - + v95 LoadLocal { off=-3, kind=I64 } -> x0 + v96 Imm(8) -> x0 + v97 BinopI { op=add, lhs=v89, rhs_imm=8 } -> x0 + v98 LoadLocal { off=-1, kind=I64 } -> x0 + v99 Store { addr=v89, disp=8, value=v69, kind=I64 } -> - + v100 LoadLocal { off=-3, kind=I64 } -> x0 + v101 Imm(0) -> x0 + v102 Imm(4) -> x0 + v103 Imm(5) -> x0 + v104 Imm(0) -> x0 + v105 Imm(5) -> x0 + v106 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v106) block 2 start_pc=0 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x3 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + v107 LoadLocal { off=-1, kind=I64 } -> x0 + v108 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v89) block 3 start_pc=0 - v12 Imm(16) -> x7 - v13 Imm(68719476736) -> x0 - v14 CallExt { binding_idx=0, args=[v12], fp_arg_mask=0x0 } -> x1 - v15 Imm(0) -> x0 - v16 LoadLocal { off=-3, kind=I64 } -> x0 - v17 Imm(0) -> x0 - v18 Extend { value=v5, kind=I32 } -> x0 - v19 Store { addr=v14, disp=0, value=v18, kind=I64 } -> - - v20 LoadLocal { off=-3, kind=I64 } -> x0 - v21 Imm(8) -> x0 - v22 BinopI { op=add, lhs=v14, rhs_imm=8 } -> x0 - v23 LoadLocal { off=-1, kind=I64 } -> x0 - v24 Store { addr=v14, disp=8, value=v6, kind=I64 } -> - - v25 LoadLocal { off=-3, kind=I64 } -> x0 - v26 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v14) + v113 Extend { value=v109, kind=I32 } -> x0 + v114 LoadLocal { off=-2, kind=I64 } -> x0 + v115 Imm(0) -> x0 + v116 Load { addr=v110, disp=0, kind=I64 } -> x0 + v117 Binop { op=add, lhs=v109, rhs=v116 } -> x13 + v118 Imm(0) -> x0 + v119 BinopI { op=shl, lhs=v117, rhs_imm=32 } -> x0 + v120 Extend { value=v117, kind=I32 } -> x0 + v121 Imm(8) -> x0 + v122 BinopI { op=add, lhs=v110, rhs_imm=8 } -> x0 + v123 Load { addr=v110, disp=8, kind=I64 } -> x1 + v124 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v123) block 4 start_pc=0 - v27 LoadLocal { off=-1, kind=I64 } -> x0 - v28 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v6) + v109 Phi { incoming=[b2:v1, b3:v117], kind=I64 } -> x13 + v110 Phi { incoming=[b2:v89, b3:v123], kind=I64 } -> x1 + v111 LoadLocal { off=-2, kind=I64 } -> x0 + v112 BinopI { op=ne, lhs=v110, rhs_imm=0 } -> x0 + terminator Bnz { cond=v112, target=b3, fall=b5 } (exit_acc=v112) block 5 start_pc=0 - v29 Phi { incoming=[b4:v1, b6:v37], kind=I64 } -> x12 - v30 Phi { incoming=[b4:v6, b6:v43], kind=I64 } -> x13 - v31 LoadLocal { off=-2, kind=I64 } -> x0 - v32 BinopI { op=ne, lhs=v30, rhs_imm=0 } -> x0 - terminator Bz { cond=v32, target=b7, fall=b6 } (exit_acc=v32) - block 6 start_pc=0 - v33 Extend { value=v29, kind=I32 } -> x0 - v34 LoadLocal { off=-2, kind=I64 } -> x0 - v35 Imm(0) -> x0 - v36 Load { addr=v30, disp=0, kind=I64 } -> x0 - v37 Binop { op=add, lhs=v29, rhs=v36 } -> x12 - v38 Imm(0) -> x0 - v39 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x0 - v40 Extend { value=v37, kind=I32 } -> x0 - v41 Imm(8) -> x0 - v42 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x0 - v43 Load { addr=v30, disp=8, kind=I64 } -> x13 - v44 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v43) - block 7 start_pc=0 - v45 Extend { value=v29, kind=I32 } -> x0 - terminator Return(v45) (exit_acc=v45) + v125 Extend { value=v109, kind=I32 } -> x0 + terminator Return(v125) (exit_acc=v125) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_aggregate_runtime_init.ssa b/tests/snapshots/ssa/local_aggregate_runtime_init.ssa index 13d94b7a0..8a3054b5c 100644 --- a/tests/snapshots/ssa/local_aggregate_runtime_init.ssa +++ b/tests/snapshots/ssa/local_aggregate_runtime_init.ssa @@ -64,7 +64,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v54 BinopI { op=ne, lhs=v53, rhs_imm=104 } -> x1 v55 Imm(1) -> x6 v56 Imm(0) -> x2 - terminator Bnz { cond=v54, target=b27, fall=b3 } (exit_acc=v54) + terminator Bnz { cond=v54, target=b33, fall=b3 } (exit_acc=v54) block 3 start_pc=0 v57 LocalAddr(-3) -> x1 v58 BinopI { op=add, lhs=v57, rhs_imm=4 } -> x2 @@ -76,11 +76,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v64 Imm(0) -> x1 terminator Jmp(b4) (exit_acc=v63) block 4 start_pc=0 - v65 Phi { incoming=[b27:v55, b3:v63], kind=I64 } -> x6 + v65 Phi { incoming=[b33:v55, b3:v63], kind=I64 } -> x6 v66 LoadLocal { off=-9, kind=I64 } -> x1 v67 Imm(1) -> x2 v68 Imm(0) -> x1 - terminator Bnz { cond=v65, target=b28, fall=b5 } (exit_acc=v65) + terminator Bnz { cond=v65, target=b32, fall=b5 } (exit_acc=v65) block 5 start_pc=0 v69 LocalAddr(-3) -> x1 v70 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x2 @@ -92,10 +92,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v76 Imm(0) -> x1 terminator Jmp(b6) (exit_acc=v75) block 6 start_pc=0 - v77 Phi { incoming=[b28:v67, b5:v75], kind=I64 } -> x2 + v77 Phi { incoming=[b32:v67, b5:v75], kind=I64 } -> x2 v78 LoadLocal { off=-8, kind=I64 } -> x1 v79 Imm(0) -> x1 - terminator Bnz { cond=v77, target=b29, fall=b7 } (exit_acc=v77) + terminator Bnz { cond=v77, target=b31, fall=b7 } (exit_acc=v77) block 7 start_pc=0 v80 LocalAddr(-3) -> x1 v81 BinopI { op=add, lhs=v80, rhs_imm=4 } -> x2 @@ -106,7 +106,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v86 Imm(0) -> x1 terminator Jmp(b8) (exit_acc=v85) block 8 start_pc=0 - v87 Phi { incoming=[b29:v77, b7:v85], kind=I64 } -> x2 + v87 Phi { incoming=[b31:v77, b7:v85], kind=I64 } -> x2 v88 LoadLocal { off=-7, kind=I64 } -> x1 terminator Bz { cond=v87, target=b10, fall=b9 } (exit_acc=v87) block 9 start_pc=0 @@ -170,7 +170,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v132 BinopI { op=ne, lhs=v131, rhs_imm=3 } -> x0 v133 Imm(1) -> x2 v134 Imm(0) -> x1 - terminator Bnz { cond=v132, target=b31, fall=b17 } (exit_acc=v132) + terminator Bnz { cond=v132, target=b29, fall=b17 } (exit_acc=v132) block 17 start_pc=0 v135 LocalAddr(-5) -> x0 v136 Imm(4) -> x1 @@ -181,10 +181,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v141 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v140) block 18 start_pc=0 - v142 Phi { incoming=[b31:v133, b17:v140], kind=I64 } -> x2 + v142 Phi { incoming=[b29:v133, b17:v140], kind=I64 } -> x2 v143 LoadLocal { off=-12, kind=I64 } -> x0 v144 Imm(0) -> x0 - terminator Bnz { cond=v142, target=b32, fall=b19 } (exit_acc=v142) + terminator Bnz { cond=v142, target=b28, fall=b19 } (exit_acc=v142) block 19 start_pc=0 v145 LocalAddr(-5) -> x0 v146 Imm(8) -> x1 @@ -194,7 +194,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v150 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v149) block 20 start_pc=0 - v151 Phi { incoming=[b32:v142, b19:v149], kind=I64 } -> x2 + v151 Phi { incoming=[b28:v142, b19:v149], kind=I64 } -> x2 v152 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v151, target=b22, fall=b21 } (exit_acc=v151) block 21 start_pc=0 @@ -209,7 +209,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v159 Load { addr=v155, disp=0, kind=I8 } -> x1 v160 BinopI { op=ne, lhs=v159, rhs_imm=111 } -> x2 v161 Imm(0) -> x1 - terminator Bnz { cond=v160, target=b33, fall=b23 } (exit_acc=v160) + terminator Bnz { cond=v160, target=b27, fall=b23 } (exit_acc=v160) block 23 start_pc=0 v162 LoadLocal { off=-6, kind=I64 } -> x1 v163 Imm(1) -> x1 @@ -219,7 +219,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v167 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v166) block 24 start_pc=0 - v168 Phi { incoming=[b33:v160, b23:v166], kind=I64 } -> x2 + v168 Phi { incoming=[b27:v160, b23:v166], kind=I64 } -> x2 v169 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v168, target=b26, fall=b25 } (exit_acc=v168) block 25 start_pc=0 @@ -229,19 +229,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v171 Imm(0) -> x0 terminator Return(v171) (exit_acc=v171) block 27 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b24) block 28 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b20) block 29 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b18) block 30 start_pc=0 terminator Jmp(b12) block 31 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b8) block 32 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b6) block 33 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_array_partial_init_zero.ssa b/tests/snapshots/ssa/local_array_partial_init_zero.ssa index a6e53dca7..19040d804 100644 --- a/tests/snapshots/ssa/local_array_partial_init_zero.ssa +++ b/tests/snapshots/ssa/local_array_partial_init_zero.ssa @@ -8,25 +8,25 @@ fn ent_pc=0 n_params=1 variadic=false locals=22 v2 Imm(0) -> x0 v3 Imm(0) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v3, b2:v9], kind=I64 } -> x1 - v6 Extend { value=v5, kind=I32 } -> x0 - v7 BinopI { op=lt, lhs=v6, rhs_imm=40 } -> x0 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) - block 2 start_pc=0 - v8 Extend { value=v5, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 - v11 LocalAddr(-20) -> x0 - v12 Extend { value=v5, kind=I32 } -> x2 - v13 BinopI { op=shl, lhs=v12, rhs_imm=2 } -> x6 + v11 LocalAddr(-20) -> x2 + v12 Extend { value=v5, kind=I32 } -> x6 + v13 BinopI { op=shl, lhs=v6, rhs_imm=2 } -> x6 v14 Binop { op=add, lhs=v11, rhs=v13 } -> x6 v15 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x6 - v16 StoreIndexed { base=v11, index=v12, scale=4, value=v15, kind=I32 } -> - + v16 StoreIndexed { base=v11, index=v6, scale=4, value=v15, kind=I32 } -> - terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v8 Extend { value=v5, kind=I32 } -> x1 + v9 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v9) + block 3 start_pc=0 + v5 Phi { incoming=[b0:v3, b2:v9], kind=I64 } -> x1 + v6 Extend { value=v5, kind=I32 } -> x0 + v7 BinopI { op=lt, lhs=v6, rhs_imm=40 } -> x2 + terminator Bnz { cond=v7, target=b1, fall=b4 } (exit_acc=v7) block 4 start_pc=0 v17 LocalAddr(-20) -> x0 v18 Imm(0) -> x1 @@ -53,29 +53,29 @@ fn ent_pc=1 n_params=0 variadic=false locals=15 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v12], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 BinopI { op=lt, lhs=v9, rhs_imm=25 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) - block 2 start_pc=0 - v11 Extend { value=v7, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 - v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) - block 3 start_pc=0 v14 BinopI { op=and, lhs=v8, rhs_imm=4294967295 } -> x0 - v15 LocalAddr(-13) -> x2 - v16 Extend { value=v7, kind=I32 } -> x6 - v17 BinopI { op=shl, lhs=v16, rhs_imm=2 } -> x7 + v15 LocalAddr(-13) -> x6 + v16 Extend { value=v7, kind=I32 } -> x7 + v17 BinopI { op=shl, lhs=v9, rhs_imm=2 } -> x7 v18 Binop { op=add, lhs=v15, rhs=v17 } -> x7 - v19 LoadIndexed { base=v15, index=v16, scale=4, kind=U32 } -> x2 + v19 LoadIndexed { base=v15, index=v9, scale=4, kind=U32 } -> x6 v20 Binop { op=add, lhs=v14, rhs=v19 } -> x0 - v21 Imm(0) -> x2 - v22 BinopI { op=and, lhs=v20, rhs_imm=4294967295 } -> x2 + v21 Imm(0) -> x6 + v22 BinopI { op=and, lhs=v20, rhs_imm=4294967295 } -> x6 terminator Jmp(b2) (exit_acc=v22) + block 2 start_pc=0 + v11 Extend { value=v7, kind=I32 } -> x1 + v12 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v13 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 + v7 Phi { incoming=[b0:v4, b2:v12], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 BinopI { op=lt, lhs=v9, rhs_imm=25 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v23 BinopI { op=and, lhs=v8, rhs_imm=4294967295 } -> x0 terminator Return(v23) (exit_acc=v23) diff --git a/tests/snapshots/ssa/local_array_runtime_init.ssa b/tests/snapshots/ssa/local_array_runtime_init.ssa index 0a0070f5d..7286093d6 100644 --- a/tests/snapshots/ssa/local_array_runtime_init.ssa +++ b/tests/snapshots/ssa/local_array_runtime_init.ssa @@ -164,34 +164,69 @@ fn ent_pc=4 n_params=1 variadic=false locals=3 v29 LocalAddr(-1) -> x1 v30 BinopI { op=add, lhs=v29, rhs_imm=3 } -> x2 v31 Store { addr=v29, disp=3, value=v28, kind=I8 } -> - - v32 Imm(0) -> x1 - v33 Imm(0) -> x0 - v34 Imm(0) -> x0 + v32 Imm(0) -> x0 + v33 Imm(0) -> x1 + v34 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v32) block 1 start_pc=0 - v35 Phi { incoming=[b0:v32, b2:v40], kind=I64 } -> x1 - v36 Phi { incoming=[b0:v32, b2:v47], kind=I64 } -> x0 - v37 Extend { value=v35, kind=I32 } -> x2 - v38 BinopI { op=lt, lhs=v37, rhs_imm=4 } -> x2 - terminator Bz { cond=v38, target=b4, fall=b3 } (exit_acc=v38) + v35 Imm(0) -> x0 + v36 Imm(1) -> x0 + v37 Imm(0) -> x0 + v38 LocalAddr(-1) -> x0 + v39 Imm(0) -> x1 + v40 BinopI { op=add, lhs=v38, rhs_imm=0 } -> x0 + v41 Load { addr=v40, disp=0, kind=I8 } -> x0 + v42 BinopI { op=add, lhs=v41, rhs_imm=0 } -> x0 + v43 Imm(0) -> x1 + v44 Extend { value=v42, kind=I32 } -> x1 + v45 Imm(0) -> x1 + v46 Imm(1) -> x1 + v47 Imm(0) -> x1 + v48 Imm(1) -> x1 + v49 Imm(1) -> x1 + v50 Extend { value=v42, kind=I32 } -> x1 + v51 LocalAddr(-1) -> x1 + v52 Imm(1) -> x2 + v53 BinopI { op=add, lhs=v51, rhs_imm=1 } -> x2 + v54 Load { addr=v51, disp=1, kind=I8 } -> x1 + v55 Binop { op=add, lhs=v42, rhs=v54 } -> x0 + v56 Imm(0) -> x1 + v57 Extend { value=v55, kind=I32 } -> x1 + v58 Imm(1) -> x1 + v59 Imm(2) -> x1 + v60 Imm(0) -> x1 + v61 Imm(2) -> x1 + v62 Imm(1) -> x1 + v63 Extend { value=v55, kind=I32 } -> x1 + v64 LocalAddr(-1) -> x1 + v65 Imm(2) -> x2 + v66 BinopI { op=add, lhs=v64, rhs_imm=2 } -> x2 + v67 Load { addr=v64, disp=2, kind=I8 } -> x1 + v68 Binop { op=add, lhs=v55, rhs=v67 } -> x0 + v69 Imm(0) -> x1 + v70 Extend { value=v68, kind=I32 } -> x1 + v71 Imm(2) -> x1 + v72 Imm(3) -> x1 + v73 Imm(0) -> x1 + v74 Imm(3) -> x1 + v75 Imm(1) -> x1 + v76 Extend { value=v68, kind=I32 } -> x1 + v77 LocalAddr(-1) -> x1 + v78 Imm(3) -> x2 + v79 BinopI { op=add, lhs=v77, rhs_imm=3 } -> x2 + v80 Load { addr=v77, disp=3, kind=I8 } -> x1 + v81 Binop { op=add, lhs=v68, rhs=v80 } -> x0 + v82 Imm(0) -> x1 + v83 Extend { value=v81, kind=I32 } -> x1 + v84 Imm(3) -> x1 + v85 Imm(4) -> x1 + v86 Imm(0) -> x1 + v87 Imm(4) -> x1 + v88 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v88) block 2 start_pc=0 - v39 Extend { value=v35, kind=I32 } -> x1 - v40 BinopI { op=add, lhs=v39, rhs_imm=1 } -> x1 - v41 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v40) - block 3 start_pc=0 - v42 Extend { value=v36, kind=I32 } -> x2 - v43 LocalAddr(-1) -> x2 - v44 Extend { value=v35, kind=I32 } -> x6 - v45 Binop { op=add, lhs=v43, rhs=v44 } -> x2 - v46 Load { addr=v45, disp=0, kind=I8 } -> x2 - v47 Binop { op=add, lhs=v36, rhs=v46 } -> x0 - v48 Imm(0) -> x2 - v49 Extend { value=v47, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v49) - block 4 start_pc=0 - v50 Extend { value=v36, kind=I32 } -> x0 - terminator Return(v50) (exit_acc=v50) + v89 Extend { value=v81, kind=I32 } -> x0 + terminator Return(v89) (exit_acc=v89) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=main fn ent_pc=5 n_params=0 variadic=false locals=5 @@ -280,7 +315,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v60 BinopI { op=ne, lhs=v59, rhs_imm=104 } -> x0 v61 Imm(1) -> x2 v62 Imm(0) -> x1 - terminator Bnz { cond=v60, target=b17, fall=b11 } (exit_acc=v60) + terminator Bnz { cond=v60, target=b18, fall=b11 } (exit_acc=v60) block 11 start_pc=0 v63 LocalAddr(-3) -> x0 v64 Imm(4) -> x1 @@ -291,10 +326,10 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v69 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v68) block 12 start_pc=0 - v70 Phi { incoming=[b17:v61, b11:v68], kind=I64 } -> x2 + v70 Phi { incoming=[b18:v61, b11:v68], kind=I64 } -> x2 v71 LoadLocal { off=-5, kind=I64 } -> x0 v72 Imm(0) -> x0 - terminator Bnz { cond=v70, target=b18, fall=b13 } (exit_acc=v70) + terminator Bnz { cond=v70, target=b17, fall=b13 } (exit_acc=v70) block 13 start_pc=0 v73 LocalAddr(-3) -> x0 v74 Imm(5) -> x1 @@ -304,7 +339,7 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v78 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v77) block 14 start_pc=0 - v79 Phi { incoming=[b18:v70, b13:v77], kind=I64 } -> x2 + v79 Phi { incoming=[b17:v70, b13:v77], kind=I64 } -> x2 v80 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v79, target=b16, fall=b15 } (exit_acc=v79) block 15 start_pc=0 @@ -314,9 +349,9 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v82 Imm(0) -> x0 terminator Return(v82) (exit_acc=v82) block 17 start_pc=0 - terminator Jmp(b12) - block 18 start_pc=0 terminator Jmp(b14) + block 18 start_pc=0 + terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_array_runtime_nested_init.ssa b/tests/snapshots/ssa/local_array_runtime_nested_init.ssa index 9f08dd3f3..1c94e82d7 100644 --- a/tests/snapshots/ssa/local_array_runtime_nested_init.ssa +++ b/tests/snapshots/ssa/local_array_runtime_nested_init.ssa @@ -37,7 +37,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v31 BinopI { op=ne, lhs=v30, rhs_imm=5 } -> x0 v32 Imm(1) -> x2 v33 Imm(0) -> x1 - terminator Bnz { cond=v31, target=b27, fall=b1 } (exit_acc=v31) + terminator Bnz { cond=v31, target=b35, fall=b1 } (exit_acc=v31) block 1 start_pc=0 v34 LocalAddr(-8) -> x0 v35 Imm(0) -> x1 @@ -50,11 +50,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v42 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v41) block 2 start_pc=0 - v43 Phi { incoming=[b27:v32, b1:v41], kind=I64 } -> x2 + v43 Phi { incoming=[b35:v32, b1:v41], kind=I64 } -> x2 v44 LoadLocal { off=-25, kind=I64 } -> x0 v45 Imm(1) -> x1 v46 Imm(0) -> x0 - terminator Bnz { cond=v43, target=b28, fall=b3 } (exit_acc=v43) + terminator Bnz { cond=v43, target=b34, fall=b3 } (exit_acc=v43) block 3 start_pc=0 v47 LocalAddr(-8) -> x0 v48 Imm(16) -> x1 @@ -67,10 +67,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v55 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v54) block 4 start_pc=0 - v56 Phi { incoming=[b28:v45, b3:v54], kind=I64 } -> x1 + v56 Phi { incoming=[b34:v45, b3:v54], kind=I64 } -> x1 v57 LoadLocal { off=-24, kind=I64 } -> x0 v58 Imm(0) -> x0 - terminator Bnz { cond=v56, target=b29, fall=b5 } (exit_acc=v56) + terminator Bnz { cond=v56, target=b33, fall=b5 } (exit_acc=v56) block 5 start_pc=0 v59 LocalAddr(-8) -> x0 v60 Imm(16) -> x1 @@ -83,7 +83,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v67 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v66) block 6 start_pc=0 - v68 Phi { incoming=[b29:v56, b5:v66], kind=I64 } -> x1 + v68 Phi { incoming=[b33:v56, b5:v66], kind=I64 } -> x1 v69 LoadLocal { off=-23, kind=I64 } -> x0 terminator Bz { cond=v68, target=b8, fall=b7 } (exit_acc=v68) block 7 start_pc=0 @@ -116,7 +116,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v94 Load { addr=v93, disp=0, kind=I32 } -> x0 v95 BinopI { op=ne, lhs=v94, rhs_imm=7 } -> x1 v96 Imm(0) -> x0 - terminator Bnz { cond=v95, target=b30, fall=b9 } (exit_acc=v95) + terminator Bnz { cond=v95, target=b32, fall=b9 } (exit_acc=v95) block 9 start_pc=0 v97 LocalAddr(-12) -> x0 v98 Imm(16) -> x1 @@ -129,7 +129,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v105 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v104) block 10 start_pc=0 - v106 Phi { incoming=[b30:v95, b9:v104], kind=I64 } -> x1 + v106 Phi { incoming=[b32:v95, b9:v104], kind=I64 } -> x1 v107 LoadLocal { off=-26, kind=I64 } -> x0 terminator Bz { cond=v106, target=b12, fall=b11 } (exit_acc=v106) block 11 start_pc=0 @@ -173,7 +173,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v139 LoadLocal { off=-29, kind=I64 } -> x0 v140 Imm(1) -> x1 v141 Imm(0) -> x0 - terminator Bnz { cond=v138, target=b32, fall=b15 } (exit_acc=v138) + terminator Bnz { cond=v138, target=b30, fall=b15 } (exit_acc=v138) block 15 start_pc=0 v142 LocalAddr(-18) -> x0 v143 Imm(24) -> x1 @@ -187,10 +187,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v151 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v150) block 16 start_pc=0 - v152 Phi { incoming=[b32:v140, b15:v150], kind=I64 } -> x1 + v152 Phi { incoming=[b30:v140, b15:v150], kind=I64 } -> x1 v153 LoadLocal { off=-28, kind=I64 } -> x0 v154 Imm(0) -> x0 - terminator Bnz { cond=v152, target=b33, fall=b17 } (exit_acc=v152) + terminator Bnz { cond=v152, target=b29, fall=b17 } (exit_acc=v152) block 17 start_pc=0 v155 LocalAddr(-18) -> x0 v156 Imm(24) -> x1 @@ -202,7 +202,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v162 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v161) block 18 start_pc=0 - v163 Phi { incoming=[b33:v152, b17:v161], kind=I64 } -> x1 + v163 Phi { incoming=[b29:v152, b17:v161], kind=I64 } -> x1 v164 LoadLocal { off=-27, kind=I64 } -> x0 terminator Bz { cond=v163, target=b20, fall=b19 } (exit_acc=v163) block 19 start_pc=0 @@ -232,7 +232,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v186 Binop { op=ne, lhs=v184, rhs=v185 } -> x0 v187 Imm(1) -> x2 v188 Imm(0) -> x1 - terminator Bnz { cond=v186, target=b34, fall=b21 } (exit_acc=v186) + terminator Bnz { cond=v186, target=b28, fall=b21 } (exit_acc=v186) block 21 start_pc=0 v189 LocalAddr(-22) -> x0 v190 Imm(16) -> x1 @@ -247,10 +247,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v199 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v198) block 22 start_pc=0 - v200 Phi { incoming=[b34:v187, b21:v198], kind=I64 } -> x2 + v200 Phi { incoming=[b28:v187, b21:v198], kind=I64 } -> x2 v201 LoadLocal { off=-31, kind=I64 } -> x0 v202 Imm(0) -> x0 - terminator Bnz { cond=v200, target=b35, fall=b23 } (exit_acc=v200) + terminator Bnz { cond=v200, target=b27, fall=b23 } (exit_acc=v200) block 23 start_pc=0 v203 LocalAddr(-22) -> x0 v204 Imm(0) -> x1 @@ -261,7 +261,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v209 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v208) block 24 start_pc=0 - v210 Phi { incoming=[b35:v200, b23:v208], kind=I64 } -> x2 + v210 Phi { incoming=[b27:v200, b23:v208], kind=I64 } -> x2 v211 LoadLocal { off=-30, kind=I64 } -> x0 terminator Bz { cond=v210, target=b26, fall=b25 } (exit_acc=v210) block 25 start_pc=0 @@ -271,23 +271,23 @@ fn ent_pc=0 n_params=0 variadic=false locals=31 v213 Imm(0) -> x0 terminator Return(v213) (exit_acc=v213) block 27 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b24) block 28 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b22) block 29 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b18) block 30 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b16) block 31 start_pc=0 terminator Jmp(b14) block 32 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b10) block 33 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b6) block 34 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b4) block 35 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_init_and_block_scope.ssa b/tests/snapshots/ssa/local_init_and_block_scope.ssa index 0ce1f54f8..ae748be7c 100644 --- a/tests/snapshots/ssa/local_init_and_block_scope.ssa +++ b/tests/snapshots/ssa/local_init_and_block_scope.ssa @@ -27,158 +27,143 @@ fn ent_pc=1 n_params=0 variadic=false locals=13 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 Imm(65) -> x1 - v4 Imm(0) -> x2 - v5 ImmData(8) -> x2 - v6 Imm(0) -> x6 - v7 Imm(1) -> x6 + v2 Imm(0) -> x0 + v3 Imm(65) -> x0 + v4 Imm(0) -> x0 + v5 ImmData(8) -> x0 + v6 Imm(0) -> x1 + v7 Imm(1) -> x1 v8 StoreLocal { off=-4, value=v7, kind=I32 } -> - - v9 Imm(3) -> x6 - v10 Imm(0) -> x7 - v11 Imm(2) -> x7 - v12 Imm(0) -> x8 - v13 LoadLocal { off=-1, kind=I32 } -> x8 - v14 BinopI { op=ne, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v14, target=b2, fall=b1 } (exit_acc=v14) + v9 Imm(3) -> x1 + v10 Imm(0) -> x1 + v11 Imm(2) -> x1 + v12 Imm(0) -> x1 + v13 LoadLocal { off=-1, kind=I32 } -> x1 + v14 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v14) block 1 start_pc=0 - v15 Imm(1) -> x0 - terminator Return(v15) (exit_acc=v15) + v16 LoadLocal { off=-2, kind=I8 } -> x1 + v17 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 - v16 LoadLocal { off=-2, kind=I8 } -> x0 - v17 BinopI { op=ne, lhs=v3, rhs_imm=65 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) + v19 LoadLocal { off=-3, kind=I64 } -> x1 + v20 Imm(0) -> x1 + v21 Load { addr=v5, disp=0, kind=I8 } -> x1 + v22 BinopI { op=ne, lhs=v21, rhs_imm=104 } -> x1 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 - v18 Imm(2) -> x0 - terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 - v19 LoadLocal { off=-3, kind=I64 } -> x0 - v20 Imm(0) -> x0 - v21 Load { addr=v5, disp=0, kind=I8 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=104 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) - block 5 start_pc=0 v23 Imm(3) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 - v24 LoadLocal { off=-3, kind=I64 } -> x0 - v25 Imm(1) -> x0 - v26 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x0 + block 4 start_pc=0 + v24 LoadLocal { off=-3, kind=I64 } -> x1 + v25 Imm(1) -> x1 + v26 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x1 v27 Load { addr=v5, disp=1, kind=I8 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=105 } -> x0 - terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) - block 7 start_pc=0 + terminator Bz { cond=v28, target=b6, fall=b5 } (exit_acc=v28) + block 5 start_pc=0 v29 Imm(4) -> x0 terminator Return(v29) (exit_acc=v29) - block 8 start_pc=0 + block 6 start_pc=0 v30 LoadLocal { off=-4, kind=I32 } -> x0 v31 LoadLocal { off=-5, kind=I32 } -> x1 - v32 Binop { op=add, lhs=v30, rhs=v11 } -> x0 + v32 BinopI { op=add, lhs=v30, rhs_imm=2 } -> x0 v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 v34 Extend { value=v32, kind=I32 } -> x1 v35 LoadLocal { off=-6, kind=I32 } -> x1 - v36 Binop { op=add, lhs=v32, rhs=v9 } -> x0 + v36 BinopI { op=add, lhs=v32, rhs_imm=3 } -> x0 v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 v38 Extend { value=v36, kind=I32 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=6 } -> x0 - terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) - block 9 start_pc=0 + terminator Bz { cond=v39, target=b8, fall=b7 } (exit_acc=v39) + block 7 start_pc=0 v40 Imm(5) -> x0 terminator Return(v40) (exit_acc=v40) - block 10 start_pc=0 + block 8 start_pc=0 v41 LoadLocal { off=-4, kind=I32 } -> x0 v42 LoadLocal { off=-5, kind=I32 } -> x1 v43 LoadLocal { off=-6, kind=I32 } -> x1 v44 Extend { value=v41, kind=I32 } -> x1 v45 Imm(0) -> x1 - v46 Extend { value=v11, kind=I32 } -> x1 + v46 Imm(2) -> x1 v47 Imm(0) -> x1 - v48 Extend { value=v9, kind=I32 } -> x1 + v48 Imm(3) -> x1 v49 Imm(0) -> x1 - v50 Binop { op=add, lhs=v41, rhs=v11 } -> x0 + v50 BinopI { op=add, lhs=v41, rhs_imm=2 } -> x0 v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x1 v52 Extend { value=v50, kind=I32 } -> x1 - v53 Binop { op=add, lhs=v50, rhs=v9 } -> x0 + v53 BinopI { op=add, lhs=v50, rhs_imm=3 } -> x0 v54 BinopI { op=shl, lhs=v53, rhs_imm=32 } -> x1 v55 Extend { value=v53, kind=I32 } -> x1 v56 Imm(0) -> x2 v57 Extend { value=v55, kind=I32 } -> x2 - v58 BinopI { op=ne, lhs=v57, rhs_imm=6 } -> x2 - terminator Bz { cond=v58, target=b12, fall=b11 } (exit_acc=v58) - block 11 start_pc=0 + v58 BinopI { op=ne, lhs=v57, rhs_imm=6 } -> x6 + terminator Bz { cond=v58, target=b10, fall=b9 } (exit_acc=v58) + block 9 start_pc=0 v59 Imm(6) -> x0 terminator Return(v59) (exit_acc=v59) - block 12 start_pc=0 - v60 Extend { value=v55, kind=I32 } -> x2 + block 10 start_pc=0 + v60 Extend { value=v55, kind=I32 } -> x6 v61 BinopI { op=shl, lhs=v53, rhs_imm=1 } -> x0 - v62 BinopI { op=shl, lhs=v61, rhs_imm=32 } -> x2 + v62 BinopI { op=shl, lhs=v61, rhs_imm=32 } -> x6 v63 Extend { value=v61, kind=I32 } -> x0 - v64 Imm(0) -> x2 - v65 LoadLocal { off=-7, kind=I32 } -> x2 + v64 Imm(0) -> x6 + v65 LoadLocal { off=-7, kind=I32 } -> x6 v66 BinopI { op=ne, lhs=v63, rhs_imm=12 } -> x0 - terminator Bz { cond=v66, target=b14, fall=b13 } (exit_acc=v66) - block 13 start_pc=0 + terminator Bz { cond=v66, target=b12, fall=b11 } (exit_acc=v66) + block 11 start_pc=0 v67 Imm(7) -> x0 terminator Return(v67) (exit_acc=v67) - block 14 start_pc=0 + block 12 start_pc=0 v68 Imm(10) -> x0 - v69 Imm(20) -> x2 - v70 Imm(30) -> x6 - v71 Extend { value=v68, kind=I32 } -> x7 - v72 Imm(0) -> x7 - v73 Extend { value=v69, kind=I32 } -> x7 - v74 Imm(0) -> x7 - v75 Extend { value=v70, kind=I32 } -> x7 - v76 Imm(0) -> x7 - v77 Binop { op=add, lhs=v68, rhs=v69 } -> x0 - v78 BinopI { op=shl, lhs=v77, rhs_imm=32 } -> x2 - v79 Extend { value=v77, kind=I32 } -> x2 - v80 Binop { op=add, lhs=v77, rhs=v70 } -> x0 - v81 BinopI { op=shl, lhs=v80, rhs_imm=32 } -> x2 - v82 Extend { value=v80, kind=I32 } -> x0 - v83 Imm(0) -> x2 - v84 Extend { value=v82, kind=I32 } -> x0 - v85 BinopI { op=ne, lhs=v84, rhs_imm=60 } -> x0 - terminator Bz { cond=v85, target=b16, fall=b15 } (exit_acc=v85) - block 15 start_pc=0 - v86 Imm(8) -> x0 - terminator Return(v86) (exit_acc=v86) - block 16 start_pc=0 + v69 Imm(20) -> x0 + v70 Imm(30) -> x0 + v71 Imm(10) -> x0 + v72 Imm(0) -> x0 + v73 Imm(20) -> x0 + v74 Imm(0) -> x0 + v75 Imm(30) -> x0 + v76 Imm(0) -> x0 + v77 Imm(30) -> x0 + v78 Imm(128849018880) -> x0 + v79 Imm(30) -> x0 + v80 Imm(60) -> x0 + v81 Imm(257698037760) -> x0 + v82 Imm(60) -> x0 + v83 Imm(0) -> x0 + v84 Imm(60) -> x0 + v85 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v85) + block 13 start_pc=0 v87 Imm(99) -> x0 - v88 Imm(0) -> x2 - v89 LoadLocal { off=-9, kind=I32 } -> x2 - v90 BinopI { op=ne, lhs=v87, rhs_imm=99 } -> x0 - terminator Bz { cond=v90, target=b18, fall=b17 } (exit_acc=v90) - block 17 start_pc=0 - v91 Imm(9) -> x0 - terminator Return(v91) (exit_acc=v91) - block 18 start_pc=0 + v88 Imm(0) -> x0 + v89 LoadLocal { off=-9, kind=I32 } -> x0 + v90 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v90) + block 14 start_pc=0 v92 Imm(7) -> x0 - v93 Imm(0) -> x2 - v94 LoadLocal { off=-10, kind=I32 } -> x2 - v95 BinopI { op=ne, lhs=v92, rhs_imm=7 } -> x0 - terminator Bz { cond=v95, target=b20, fall=b19 } (exit_acc=v95) - block 19 start_pc=0 - v96 Imm(10) -> x0 - terminator Return(v96) (exit_acc=v96) - block 20 start_pc=0 + v93 Imm(0) -> x0 + v94 LoadLocal { off=-10, kind=I32 } -> x0 + v95 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v95) + block 15 start_pc=0 v97 Extend { value=v55, kind=I32 } -> x0 - v98 BinopI { op=ne, lhs=v97, rhs_imm=6 } -> x0 - terminator Bz { cond=v98, target=b22, fall=b21 } (exit_acc=v98) - block 21 start_pc=0 + v98 BinopI { op=ne, lhs=v57, rhs_imm=6 } -> x0 + terminator Bz { cond=v98, target=b17, fall=b16 } (exit_acc=v98) + block 16 start_pc=0 v99 Imm(11) -> x0 terminator Return(v99) (exit_acc=v99) - block 22 start_pc=0 + block 17 start_pc=0 v100 LocalAddr(-4) -> x0 v101 Imm(0) -> x1 v102 LoadLocal { off=-11, kind=I64 } -> x1 v103 Load { addr=v100, disp=0, kind=I32 } -> x0 v104 BinopI { op=ne, lhs=v103, rhs_imm=1 } -> x0 - terminator Bz { cond=v104, target=b24, fall=b23 } (exit_acc=v104) - block 23 start_pc=0 + terminator Bz { cond=v104, target=b19, fall=b18 } (exit_acc=v104) + block 18 start_pc=0 v105 Imm(12) -> x0 terminator Return(v105) (exit_acc=v105) - block 24 start_pc=0 + block 19 start_pc=0 v106 LocalAddr(-12) -> x0 v107 Imm(0) -> x1 v108 Store { addr=v106, disp=0, value=v107, kind=I32 } -> - @@ -191,22 +176,37 @@ fn ent_pc=1 n_params=0 variadic=false locals=13 v115 LocalAddr(-13) -> x0 v116 Load { addr=v115, disp=0, kind=I32 } -> x0 v117 BinopI { op=ne, lhs=v116, rhs_imm=0 } -> x0 - terminator Bz { cond=v117, target=b26, fall=b25 } (exit_acc=v117) - block 25 start_pc=0 + terminator Bz { cond=v117, target=b21, fall=b20 } (exit_acc=v117) + block 20 start_pc=0 v118 Imm(13) -> x0 terminator Return(v118) (exit_acc=v118) - block 26 start_pc=0 + block 21 start_pc=0 v119 LocalAddr(-13) -> x0 v120 BinopI { op=add, lhs=v119, rhs_imm=4 } -> x1 v121 Load { addr=v119, disp=4, kind=I32 } -> x0 v122 BinopI { op=ne, lhs=v121, rhs_imm=0 } -> x0 - terminator Bz { cond=v122, target=b28, fall=b27 } (exit_acc=v122) - block 27 start_pc=0 + terminator Bz { cond=v122, target=b23, fall=b22 } (exit_acc=v122) + block 22 start_pc=0 v123 Imm(14) -> x0 terminator Return(v123) (exit_acc=v123) - block 28 start_pc=0 + block 23 start_pc=0 v124 Imm(0) -> x0 terminator Return(v124) (exit_acc=v124) + block 24 start_pc=0 + v15 Imm(1) -> x0 + terminator Return(v15) (exit_acc=v15) + block 25 start_pc=0 + v18 Imm(2) -> x0 + terminator Return(v18) (exit_acc=v18) + block 26 start_pc=0 + v86 Imm(8) -> x0 + terminator Return(v86) (exit_acc=v86) + block 27 start_pc=0 + v91 Imm(9) -> x0 + terminator Return(v91) (exit_acc=v91) + block 28 start_pc=0 + v96 Imm(10) -> x0 + terminator Return(v96) (exit_acc=v96) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_init_int_to_float.ssa b/tests/snapshots/ssa/local_init_int_to_float.ssa index 547074d33..37405bafc 100644 --- a/tests/snapshots/ssa/local_init_int_to_float.ssa +++ b/tests/snapshots/ssa/local_init_int_to_float.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=18 - spill_count=1 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 @@ -11,167 +11,160 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v5 Imm(0) -> x1 v6 Load { addr=v4, disp=0, kind=U8 } -> x0 v7 FpCast { kind=IntToFp, value=v6 } -> d0 - v8 FpCast { kind=F64ToF32, value=v7 } -> [spill 0] [f32] + v8 FpCast { kind=F64ToF32, value=v7 } -> d0 [f32] v9 Imm(0) -> x0 - v10 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v11 Imm(4631093718071587635) -> x0 - v12 FpCast { kind=F32ToF64, value=v8 } -> d0 - v13 Binop { op=flt, lhs=v12, rhs=v11 } -> x3 - v14 Imm(0) -> x0 - terminator Bnz { cond=v13, target=b21, fall=b1 } (exit_acc=v13) + v10 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v11 Imm(1109891482) -> x0 [f32] + v12 Binop { op=flt, lhs=v8, rhs=v11 } -> x1 + v13 Imm(0) -> x0 + terminator Bnz { cond=v12, target=b24, fall=b1 } (exit_acc=v12) block 1 start_pc=0 - v15 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v16 Imm(4631121865569258701) -> x0 - v17 FpCast { kind=F32ToF64, value=v8 } -> d0 - v18 Binop { op=fgt, lhs=v17, rhs=v16 } -> x3 - v19 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v18) + v14 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v15 Imm(1109943910) -> x0 [f32] + v16 Binop { op=fgt, lhs=v8, rhs=v15 } -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v20 Phi { incoming=[b21:v13, b1:v18], kind=I64 } -> x3 - v21 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v18 Phi { incoming=[b24:v12, b1:v16], kind=I64 } -> x1 + v19 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v22 ImmData(56) -> x7 - v23 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v8 } -> d0 - v25 CallExt { binding_idx=0, args=[v22, v24], fp_arg_mask=0x2 } -> x0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v20 ImmData(56) -> x7 + v21 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v22 FpCast { kind=F32ToF64, value=v8 } -> d0 + v23 CallExt { binding_idx=0, args=[v20, v22], fp_arg_mask=0x2 } -> x0 + v24 Imm(1) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v27 Imm(12345) -> x0 - v28 Imm(0) -> x1 - v29 LoadLocal { off=-3, kind=I32 } -> x1 - v30 FpCast { kind=IntToFp, value=v27 } -> d0 - v31 FpCast { kind=F64ToF32, value=v30 } -> [spill 0] [f32] - v32 Imm(0) -> x0 - v33 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v34 Imm(4668012074973003776) -> x0 - v35 FpCast { kind=F32ToF64, value=v31 } -> d0 - v36 Binop { op=flt, lhs=v35, rhs=v34 } -> x3 - v37 Imm(0) -> x0 - terminator Bnz { cond=v36, target=b22, fall=b5 } (exit_acc=v36) + v25 Imm(12345) -> x0 + v26 Imm(0) -> x1 + v27 LoadLocal { off=-3, kind=I32 } -> x1 + v28 FpCast { kind=IntToFp, value=v25 } -> d0 + v29 FpCast { kind=F64ToF32, value=v28 } -> d0 [f32] + v30 Imm(0) -> x0 + v31 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v32 Imm(1178657280) -> x0 [f32] + v33 Binop { op=flt, lhs=v29, rhs=v32 } -> x1 + v34 Imm(0) -> x0 + terminator Bnz { cond=v33, target=b23, fall=b5 } (exit_acc=v33) block 5 start_pc=0 - v38 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v39 Imm(4668012624728817664) -> x0 - v40 FpCast { kind=F32ToF64, value=v31 } -> d0 - v41 Binop { op=fgt, lhs=v40, rhs=v39 } -> x3 - v42 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v41) + v35 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v36 Imm(1178658304) -> x0 [f32] + v37 Binop { op=fgt, lhs=v29, rhs=v36 } -> x1 + v38 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v37) block 6 start_pc=0 - v43 Phi { incoming=[b22:v36, b5:v41], kind=I64 } -> x3 - v44 LoadLocal { off=-16, kind=I64 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v39 Phi { incoming=[b23:v33, b5:v37], kind=I64 } -> x1 + v40 LoadLocal { off=-16, kind=I64 } -> x0 + terminator Bz { cond=v39, target=b8, fall=b7 } (exit_acc=v39) block 7 start_pc=0 - v45 ImmData(78) -> x7 - v46 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v47 FpCast { kind=F32ToF64, value=v31 } -> d0 - v48 CallExt { binding_idx=0, args=[v45, v47], fp_arg_mask=0x2 } -> x0 - v49 Imm(2) -> x0 - terminator Return(v49) (exit_acc=v49) + v41 ImmData(78) -> x7 + v42 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v43 FpCast { kind=F32ToF64, value=v29 } -> d0 + v44 CallExt { binding_idx=0, args=[v41, v43], fp_arg_mask=0x2 } -> x0 + v45 Imm(2) -> x0 + terminator Return(v45) (exit_acc=v45) block 8 start_pc=0 - v50 Imm(-7) -> x0 - v51 Imm(0) -> x1 - v52 LoadLocal { off=-5, kind=I32 } -> x1 - v53 FpCast { kind=IntToFp, value=v50 } -> [spill 0] - v54 Imm(0) -> x0 - v55 LoadLocal { off=-6, kind=F64 } -> d0 - v56 Imm(4620130267728707584) -> x0 - v57 Fneg(v56) -> d0 - v58 Binop { op=flt, lhs=v53, rhs=v57 } -> x3 - v59 Imm(0) -> x0 - terminator Bnz { cond=v58, target=b23, fall=b9 } (exit_acc=v58) + v46 Imm(-7) -> x0 + v47 Imm(0) -> x1 + v48 LoadLocal { off=-5, kind=I32 } -> x1 + v49 FpCast { kind=IntToFp, value=v46 } -> d0 + v50 Imm(0) -> x0 + v51 LoadLocal { off=-6, kind=F64 } -> d1 + v52 Imm(4620130267728707584) -> x0 + v53 Fneg(v52) -> d1 + v54 Binop { op=flt, lhs=v49, rhs=v53 } -> x1 + v55 Imm(0) -> x0 + terminator Bnz { cond=v54, target=b22, fall=b9 } (exit_acc=v54) block 9 start_pc=0 - v60 LoadLocal { off=-6, kind=F64 } -> d0 - v61 Imm(4619004367821864960) -> x0 - v62 Fneg(v61) -> d0 - v63 Binop { op=fgt, lhs=v53, rhs=v62 } -> x3 - v64 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v63) + v56 LoadLocal { off=-6, kind=F64 } -> d1 + v57 Imm(4619004367821864960) -> x0 + v58 Fneg(v57) -> d1 + v59 Binop { op=fgt, lhs=v49, rhs=v58 } -> x1 + v60 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v59) block 10 start_pc=0 - v65 Phi { incoming=[b23:v58, b9:v63], kind=I64 } -> x3 - v66 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v65, target=b12, fall=b11 } (exit_acc=v65) + v61 Phi { incoming=[b22:v54, b9:v59], kind=I64 } -> x1 + v62 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v61, target=b12, fall=b11 } (exit_acc=v61) block 11 start_pc=0 - v67 ImmData(102) -> x7 - v68 LoadLocal { off=-6, kind=F64 } -> d0 - v69 CallExt { binding_idx=0, args=[v67, v53], fp_arg_mask=0x2 } -> x0 - v70 Imm(3) -> x0 - terminator Return(v70) (exit_acc=v70) + v63 ImmData(102) -> x7 + v64 LoadLocal { off=-6, kind=F64 } -> d1 + v65 CallExt { binding_idx=0, args=[v63, v49], fp_arg_mask=0x2 } -> x0 + v66 Imm(3) -> x0 + terminator Return(v66) (exit_acc=v66) block 12 start_pc=0 - v71 Imm(4294967295) -> x0 - v72 Imm(0) -> x1 - v73 LoadLocal { off=-7, kind=U32 } -> x1 - v74 FpCast { kind=IntToFp, value=v71 } -> d0 - v75 FpCast { kind=F64ToF32, value=v74 } -> [spill 0] [f32] + v67 Imm(4294967295) -> x0 + v68 Imm(0) -> x1 + v69 LoadLocal { off=-7, kind=U32 } -> x1 + v70 FpCast { kind=IntToFp, value=v67 } -> d0 + v71 FpCast { kind=F64ToF32, value=v70 } -> d0 [f32] + v72 Imm(0) -> x0 + v73 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v74 Imm(1333769268) -> x0 [f32] + v75 Binop { op=flt, lhs=v71, rhs=v74 } -> x1 v76 Imm(0) -> x0 - v77 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v78 Imm(4751287189701132288) -> x0 - v79 FpCast { kind=F32ToF64, value=v75 } -> d0 - v80 Binop { op=flt, lhs=v79, rhs=v78 } -> x3 - v81 Imm(0) -> x0 - terminator Bnz { cond=v80, target=b24, fall=b13 } (exit_acc=v80) + terminator Bnz { cond=v75, target=b21, fall=b13 } (exit_acc=v75) block 13 start_pc=0 - v82 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v83 Imm(4751302884048502784) -> x0 - v84 FpCast { kind=F32ToF64, value=v75 } -> d0 - v85 Binop { op=fgt, lhs=v84, rhs=v83 } -> x3 - v86 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v85) + v77 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v78 Imm(1333798502) -> x0 [f32] + v79 Binop { op=fgt, lhs=v71, rhs=v78 } -> x1 + v80 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v79) block 14 start_pc=0 - v87 Phi { incoming=[b24:v80, b13:v85], kind=I64 } -> x3 - v88 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v87, target=b16, fall=b15 } (exit_acc=v87) + v81 Phi { incoming=[b21:v75, b13:v79], kind=I64 } -> x1 + v82 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v81, target=b16, fall=b15 } (exit_acc=v81) block 15 start_pc=0 - v89 ImmData(127) -> x7 - v90 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v91 FpCast { kind=F32ToF64, value=v75 } -> d0 - v92 CallExt { binding_idx=0, args=[v89, v91], fp_arg_mask=0x2 } -> x0 - v93 Imm(4) -> x0 - terminator Return(v93) (exit_acc=v93) + v83 ImmData(127) -> x7 + v84 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v85 FpCast { kind=F32ToF64, value=v71 } -> d0 + v86 CallExt { binding_idx=0, args=[v83, v85], fp_arg_mask=0x2 } -> x0 + v87 Imm(4) -> x0 + terminator Return(v87) (exit_acc=v87) block 16 start_pc=0 - v94 Imm(4615514078110652826) -> x0 - v95 FpCast { kind=F64ToF32, value=v94 } -> d0 [f32] - v96 Imm(0) -> x0 - v97 LoadLocal { off=-9, kind=F32 } -> d1 [f32] - v98 FpCast { kind=F32ToF64, value=v95 } -> d0 - v99 FpCast { kind=FpToInt, value=v98 } -> x0 - v100 Imm(0) -> x1 - v101 Extend { value=v99, kind=I32 } -> x1 - v102 BinopI { op=ne, lhs=v101, rhs_imm=3 } -> x1 - terminator Bz { cond=v102, target=b18, fall=b17 } (exit_acc=v102) + v88 Imm(1080872141) -> x0 [f32] + v89 StoreLocal { off=-9, value=v88, kind=F32 } -> - + v90 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v91 FpCast { kind=F32ToF64, value=v90 } -> d0 + v92 FpCast { kind=FpToInt, value=v91 } -> x0 + v93 Imm(0) -> x1 + v94 Extend { value=v92, kind=I32 } -> x1 + v95 BinopI { op=ne, lhs=v94, rhs_imm=3 } -> x1 + terminator Bz { cond=v95, target=b18, fall=b17 } (exit_acc=v95) block 17 start_pc=0 - v103 ImmData(151) -> x7 - v104 Extend { value=v99, kind=I32 } -> x6 - v105 CallExt { binding_idx=0, args=[v103, v104], fp_arg_mask=0x0 } -> x0 - v106 Imm(5) -> x0 - terminator Return(v106) (exit_acc=v106) + v96 ImmData(151) -> x7 + v97 Extend { value=v92, kind=I32 } -> x6 + v98 CallExt { binding_idx=0, args=[v96, v97], fp_arg_mask=0x0 } -> x0 + v99 Imm(5) -> x0 + terminator Return(v99) (exit_acc=v99) block 18 start_pc=0 - v107 Imm(4613712638259704627) -> x0 - v108 Fneg(v107) -> d0 - v109 Imm(0) -> x0 - v110 LoadLocal { off=-11, kind=F64 } -> d1 - v111 FpCast { kind=FpToInt, value=v108 } -> x0 - v112 Imm(0) -> x1 - v113 Extend { value=v111, kind=I32 } -> x1 - v114 BinopI { op=ne, lhs=v113, rhs_imm=-2 } -> x1 - terminator Bz { cond=v114, target=b20, fall=b19 } (exit_acc=v114) + v100 Imm(4613712638259704627) -> x0 + v101 Fneg(v100) -> d0 + v102 Imm(0) -> x0 + v103 LoadLocal { off=-11, kind=F64 } -> d1 + v104 FpCast { kind=FpToInt, value=v101 } -> x0 + v105 Imm(0) -> x1 + v106 Extend { value=v104, kind=I32 } -> x1 + v107 BinopI { op=ne, lhs=v106, rhs_imm=-2 } -> x1 + terminator Bz { cond=v107, target=b20, fall=b19 } (exit_acc=v107) block 19 start_pc=0 - v115 ImmData(174) -> x7 - v116 Extend { value=v111, kind=I32 } -> x6 - v117 CallExt { binding_idx=0, args=[v115, v116], fp_arg_mask=0x0 } -> x0 - v118 Imm(6) -> x0 - terminator Return(v118) (exit_acc=v118) + v108 ImmData(174) -> x7 + v109 Extend { value=v104, kind=I32 } -> x6 + v110 CallExt { binding_idx=0, args=[v108, v109], fp_arg_mask=0x0 } -> x0 + v111 Imm(6) -> x0 + terminator Return(v111) (exit_acc=v111) block 20 start_pc=0 - v119 Imm(0) -> x0 - terminator Return(v119) (exit_acc=v119) + v112 Imm(0) -> x0 + terminator Return(v112) (exit_acc=v112) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b14) block 22 start_pc=0 - terminator Jmp(b6) - block 23 start_pc=0 terminator Jmp(b10) + block 23 start_pc=0 + terminator Jmp(b6) block 24 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_multidim_aggregate_array_init.ssa b/tests/snapshots/ssa/local_multidim_aggregate_array_init.ssa index afd2ec926..7904dbabf 100644 --- a/tests/snapshots/ssa/local_multidim_aggregate_array_init.ssa +++ b/tests/snapshots/ssa/local_multidim_aggregate_array_init.ssa @@ -13,7 +13,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v7 BinopI { op=ne, lhs=v6, rhs_imm=1 } -> x0 v8 Imm(1) -> x2 v9 Imm(0) -> x1 - terminator Bnz { cond=v7, target=b15, fall=b1 } (exit_acc=v7) + terminator Bnz { cond=v7, target=b18, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v10 LocalAddr(-4) -> x0 v11 Imm(16) -> x1 @@ -27,10 +27,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v19 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v20 Phi { incoming=[b15:v8, b1:v18], kind=I64 } -> x2 + v20 Phi { incoming=[b18:v8, b1:v18], kind=I64 } -> x2 v21 LoadLocal { off=-18, kind=I64 } -> x0 v22 Imm(0) -> x0 - terminator Bnz { cond=v20, target=b16, fall=b3 } (exit_acc=v20) + terminator Bnz { cond=v20, target=b17, fall=b3 } (exit_acc=v20) block 3 start_pc=0 v23 LocalAddr(-4) -> x0 v24 Imm(16) -> x1 @@ -41,7 +41,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v29 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v28) block 4 start_pc=0 - v30 Phi { incoming=[b16:v20, b3:v28], kind=I64 } -> x2 + v30 Phi { incoming=[b17:v20, b3:v28], kind=I64 } -> x2 v31 LoadLocal { off=-17, kind=I64 } -> x0 terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) block 5 start_pc=0 @@ -56,7 +56,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v38 Load { addr=v36, disp=0, kind=I32 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=1 } -> x1 v40 Imm(0) -> x0 - terminator Bnz { cond=v39, target=b17, fall=b7 } (exit_acc=v39) + terminator Bnz { cond=v39, target=b16, fall=b7 } (exit_acc=v39) block 7 start_pc=0 v41 LocalAddr(-8) -> x0 v42 Imm(16) -> x1 @@ -68,7 +68,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v48 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v47) block 8 start_pc=0 - v49 Phi { incoming=[b17:v39, b7:v47], kind=I64 } -> x1 + v49 Phi { incoming=[b16:v39, b7:v47], kind=I64 } -> x1 v50 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) block 9 start_pc=0 @@ -89,7 +89,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v63 Load { addr=v55, disp=60, kind=I32 } -> x0 v64 BinopI { op=ne, lhs=v63, rhs_imm=16 } -> x1 v65 Imm(0) -> x0 - terminator Bnz { cond=v64, target=b18, fall=b11 } (exit_acc=v64) + terminator Bnz { cond=v64, target=b15, fall=b11 } (exit_acc=v64) block 11 start_pc=0 v66 LocalAddr(-16) -> x0 v67 Imm(0) -> x1 @@ -100,7 +100,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v72 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v71) block 12 start_pc=0 - v73 Phi { incoming=[b18:v64, b11:v71], kind=I64 } -> x1 + v73 Phi { incoming=[b15:v64, b11:v71], kind=I64 } -> x1 v74 LoadLocal { off=-20, kind=I64 } -> x0 terminator Bz { cond=v73, target=b14, fall=b13 } (exit_acc=v73) block 13 start_pc=0 @@ -110,13 +110,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=20 v76 Imm(0) -> x0 terminator Return(v76) (exit_acc=v76) block 15 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b12) block 16 start_pc=0 - terminator Jmp(b4) - block 17 start_pc=0 terminator Jmp(b8) + block 17 start_pc=0 + terminator Jmp(b4) block 18 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_struct_array_brace_init.ssa b/tests/snapshots/ssa/local_struct_array_brace_init.ssa index 22d2ee57d..907f59c3b 100644 --- a/tests/snapshots/ssa/local_struct_array_brace_init.ssa +++ b/tests/snapshots/ssa/local_struct_array_brace_init.ssa @@ -11,30 +11,30 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 v5 Imm(0) -> x1 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v14], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v23], kind=I64 } -> x0 - v10 Extend { value=v8, kind=I32 } -> x2 - v11 LoadLocal { off=3, kind=I32 } -> x8 - v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x2 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v16 LoadLocal { off=-1, kind=I64 } -> x8 + v17 LoadLocal { off=2, kind=I64 } -> x8 + v18 Extend { value=v8, kind=I32 } -> x8 + v19 BinopI { op=shl, lhs=v10, rhs_imm=4 } -> x8 + v20 Binop { op=add, lhs=v1, rhs=v19 } -> x8 + v21 BinopI { op=add, lhs=v20, rhs_imm=8 } -> x9 + v22 Load { addr=v20, disp=8, kind=I64 } -> x8 + v23 Binop { op=add, lhs=v9, rhs=v22 } -> x0 + v24 Imm(0) -> x8 + terminator Jmp(b2) (exit_acc=v23) block 2 start_pc=0 v13 Extend { value=v8, kind=I32 } -> x1 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 v15 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v14) + terminator Jmp(b3) (exit_acc=v14) block 3 start_pc=0 - v16 LoadLocal { off=-1, kind=I64 } -> x2 - v17 LoadLocal { off=2, kind=I64 } -> x2 - v18 Extend { value=v8, kind=I32 } -> x2 - v19 BinopI { op=shl, lhs=v18, rhs_imm=4 } -> x2 - v20 Binop { op=add, lhs=v1, rhs=v19 } -> x2 - v21 BinopI { op=add, lhs=v20, rhs_imm=8 } -> x8 - v22 Load { addr=v20, disp=8, kind=I64 } -> x2 - v23 Binop { op=add, lhs=v9, rhs=v22 } -> x0 - v24 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v23) + v8 Phi { incoming=[b0:v5, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v23], kind=I64 } -> x0 + v10 Extend { value=v8, kind=I32 } -> x2 + v11 LoadLocal { off=3, kind=I32 } -> x8 + v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x8 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v25 LoadLocal { off=-1, kind=I64 } -> x1 terminator Return(v9) (exit_acc=v9) diff --git a/tests/snapshots/ssa/logical_not_float.ssa b/tests/snapshots/ssa/logical_not_float.ssa index 69c0c0289..6f4b9129d 100644 --- a/tests/snapshots/ssa/logical_not_float.ssa +++ b/tests/snapshots/ssa/logical_not_float.ssa @@ -70,51 +70,49 @@ fn ent_pc=2 n_params=0 variadic=false locals=2 v25 Imm(4) -> x0 terminator Return(v25) (exit_acc=v25) block 8 start_pc=0 - v26 Imm(0) -> x0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Imm(0) -> x0 - v29 Imm(0) -> x0 - v30 FpCast { kind=F32ToF64, value=v27 } -> d0 - v31 Binop { op=feq, lhs=v30, rhs=v29 } -> x0 - v32 BinopI { op=ne, lhs=v31, rhs_imm=1 } -> x0 - terminator Bz { cond=v32, target=b10, fall=b9 } (exit_acc=v32) + v26 Imm(0) -> x0 [f32] + v27 Imm(0) -> x1 + v28 Imm(0) -> x1 + v29 FpCast { kind=F32ToF64, value=v26 } -> d0 + v30 Binop { op=feq, lhs=v29, rhs=v28 } -> x0 + v31 BinopI { op=ne, lhs=v30, rhs_imm=1 } -> x0 + terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) block 9 start_pc=0 - v33 Imm(5) -> x0 - terminator Return(v33) (exit_acc=v33) + v32 Imm(5) -> x0 + terminator Return(v32) (exit_acc=v32) block 10 start_pc=0 - v34 Imm(4615063718147915776) -> x0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 Imm(0) -> x0 - v37 Imm(0) -> x0 - v38 FpCast { kind=F32ToF64, value=v35 } -> d0 - v39 Binop { op=feq, lhs=v38, rhs=v37 } -> x0 - v40 BinopI { op=ne, lhs=v39, rhs_imm=0 } -> x0 - terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) + v33 Imm(1080033280) -> x0 [f32] + v34 Imm(0) -> x1 + v35 Imm(0) -> x1 + v36 FpCast { kind=F32ToF64, value=v33 } -> d0 + v37 Binop { op=feq, lhs=v36, rhs=v35 } -> x0 + v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x0 + terminator Bz { cond=v38, target=b12, fall=b11 } (exit_acc=v38) block 11 start_pc=0 - v41 Imm(6) -> x0 - terminator Return(v41) (exit_acc=v41) + v39 Imm(6) -> x0 + terminator Return(v39) (exit_acc=v39) block 12 start_pc=0 - v42 Imm(4611686018427387904) -> x0 - v43 StoreLocal { off=-1, value=v42, kind=F64 } -> - - v44 LoadLocal { off=-1, kind=F64 } -> d0 - v45 Imm(0) -> x0 - v46 Binop { op=feq, lhs=v44, rhs=v45 } -> x0 - terminator Bz { cond=v46, target=b14, fall=b13 } (exit_acc=v46) + v40 Imm(4611686018427387904) -> x0 + v41 StoreLocal { off=-1, value=v40, kind=F64 } -> - + v42 LoadLocal { off=-1, kind=F64 } -> d0 + v43 Imm(0) -> x0 + v44 Binop { op=feq, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) block 13 start_pc=0 - v47 Imm(7) -> x0 - terminator Return(v47) (exit_acc=v47) + v45 Imm(7) -> x0 + terminator Return(v45) (exit_acc=v45) block 14 start_pc=0 - v48 Imm(0) -> x0 - v49 StoreLocal { off=-2, value=v48, kind=F64 } -> - - v50 LoadLocal { off=-2, kind=F64 } -> d0 - v51 Binop { op=feq, lhs=v50, rhs=v48 } -> x0 - terminator Bz { cond=v51, target=b16, fall=b15 } (exit_acc=v51) + v46 Imm(0) -> x0 + v47 StoreLocal { off=-2, value=v46, kind=F64 } -> - + v48 LoadLocal { off=-2, kind=F64 } -> d0 + v49 Binop { op=feq, lhs=v48, rhs=v46 } -> x0 + terminator Bz { cond=v49, target=b16, fall=b15 } (exit_acc=v49) block 15 start_pc=0 - v52 Imm(0) -> x0 - terminator Return(v52) (exit_acc=v52) + v50 Imm(0) -> x0 + terminator Return(v50) (exit_acc=v50) block 16 start_pc=0 - v53 Imm(8) -> x0 - terminator Return(v53) (exit_acc=v53) + v51 Imm(8) -> x0 + terminator Return(v51) (exit_acc=v51) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/logical_op_normalize.ssa b/tests/snapshots/ssa/logical_op_normalize.ssa index 7d93b9e8d..93bde185b 100644 --- a/tests/snapshots/ssa/logical_op_normalize.ssa +++ b/tests/snapshots/ssa/logical_op_normalize.ssa @@ -187,13 +187,13 @@ fn ent_pc=4 n_params=0 variadic=false locals=8 v50 LoadLocal { off=-1, kind=I64 } -> x0 v51 Imm(1) -> x1 v52 Imm(0) -> x0 - terminator Bnz { cond=v2, target=b27, fall=b15 } (exit_acc=v2) + terminator Bnz { cond=v2, target=b29, fall=b15 } (exit_acc=v2) block 15 start_pc=0 v53 Imm(0) -> x1 v54 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v53) block 16 start_pc=0 - v55 Phi { incoming=[b27:v51, b15:v53], kind=I64 } -> x1 + v55 Phi { incoming=[b29:v51, b15:v53], kind=I64 } -> x1 v56 LoadLocal { off=-6, kind=I64 } -> x0 v57 Imm(1) -> x2 v58 Imm(0) -> x0 @@ -225,14 +225,14 @@ fn ent_pc=4 n_params=0 variadic=false locals=8 v72 LoadLocal { off=-8, kind=I64 } -> x0 v73 Imm(0) -> x1 v74 Imm(0) -> x0 - terminator Bz { cond=v71, target=b29, fall=b23 } (exit_acc=v71) + terminator Bz { cond=v71, target=b27, fall=b23 } (exit_acc=v71) block 23 start_pc=0 v75 Imm(3) -> x0 v76 Imm(1) -> x1 v77 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v76) block 24 start_pc=0 - v78 Phi { incoming=[b29:v73, b23:v76], kind=I64 } -> x1 + v78 Phi { incoming=[b27:v73, b23:v76], kind=I64 } -> x1 v79 LoadLocal { off=-7, kind=I64 } -> x0 v80 BinopI { op=ne, lhs=v78, rhs_imm=1 } -> x0 terminator Bz { cond=v80, target=b26, fall=b25 } (exit_acc=v80) @@ -243,11 +243,11 @@ fn ent_pc=4 n_params=0 variadic=false locals=8 v82 Imm(0) -> x0 terminator Return(v82) (exit_acc=v82) block 27 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b24) block 28 start_pc=0 terminator Jmp(b18) block 29 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/long_long_distinct.ssa b/tests/snapshots/ssa/long_long_distinct.ssa index b35699b16..45cccf6ec 100644 --- a/tests/snapshots/ssa/long_long_distinct.ssa +++ b/tests/snapshots/ssa/long_long_distinct.ssa @@ -5,68 +5,44 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) - block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) - block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v9) + block 5 start_pc=0 v11 Imm(81985529216486895) -> x0 - v12 Imm(0) -> x1 - v13 LoadLocal { off=-1, kind=I64 } -> x1 - v14 BinopI { op=ne, lhs=v11, rhs_imm=81985529216486895 } -> x0 - terminator Bz { cond=v14, target=b12, fall=b11 } (exit_acc=v14) - block 11 start_pc=0 - v15 Imm(6) -> x0 - terminator Return(v15) (exit_acc=v15) - block 12 start_pc=0 + v12 Imm(0) -> x0 + v13 LoadLocal { off=-1, kind=I64 } -> x0 + v14 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v14) + block 6 start_pc=0 v16 Imm(-1) -> x0 - v17 Imm(0) -> x1 - v18 LoadLocal { off=-2, kind=I64 } -> x1 - v19 BinopI { op=ne, lhs=v16, rhs_imm=-1 } -> x0 - terminator Bz { cond=v19, target=b14, fall=b13 } (exit_acc=v19) - block 13 start_pc=0 - v20 Imm(7) -> x0 - terminator Return(v20) (exit_acc=v20) - block 14 start_pc=0 + v17 Imm(0) -> x0 + v18 LoadLocal { off=-2, kind=I64 } -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v19) + block 7 start_pc=0 v21 Imm(100) -> x0 - v22 Imm(0) -> x1 - v23 Imm(200) -> x1 - v24 Imm(0) -> x2 - v25 LoadLocal { off=-3, kind=I64 } -> x2 - v26 LoadLocal { off=-4, kind=I64 } -> x2 - v27 Binop { op=add, lhs=v21, rhs=v23 } -> x0 - v28 Imm(0) -> x1 - v29 LoadLocal { off=-5, kind=I64 } -> x1 - v30 BinopI { op=ne, lhs=v27, rhs_imm=300 } -> x0 - terminator Bz { cond=v30, target=b16, fall=b15 } (exit_acc=v30) - block 15 start_pc=0 - v31 Imm(8) -> x0 - terminator Return(v31) (exit_acc=v31) - block 16 start_pc=0 + v22 Imm(0) -> x0 + v23 Imm(200) -> x0 + v24 Imm(0) -> x0 + v25 LoadLocal { off=-3, kind=I64 } -> x0 + v26 LoadLocal { off=-4, kind=I64 } -> x0 + v27 Imm(300) -> x0 + v28 Imm(0) -> x0 + v29 LoadLocal { off=-5, kind=I64 } -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v30) + block 8 start_pc=0 v32 LocalAddr(-8) -> x0 v33 Imm(0) -> x1 v34 Imm(10) -> x1 @@ -87,21 +63,21 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v49 BinopI { op=add, lhs=v46, rhs_imm=8 } -> x1 v50 Load { addr=v46, disp=8, kind=I64 } -> x1 v51 BinopI { op=ne, lhs=v50, rhs_imm=20 } -> x1 - terminator Bz { cond=v51, target=b18, fall=b17 } (exit_acc=v51) - block 17 start_pc=0 + terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) + block 9 start_pc=0 v52 Imm(9) -> x0 terminator Return(v52) (exit_acc=v52) - block 18 start_pc=0 + block 10 start_pc=0 v53 LoadLocal { off=-9, kind=I64 } -> x1 v54 Imm(16) -> x1 v55 BinopI { op=add, lhs=v46, rhs_imm=16 } -> x1 v56 Load { addr=v46, disp=16, kind=I64 } -> x0 v57 BinopI { op=ne, lhs=v56, rhs_imm=30 } -> x0 - terminator Bz { cond=v57, target=b20, fall=b19 } (exit_acc=v57) - block 19 start_pc=0 + terminator Bz { cond=v57, target=b12, fall=b11 } (exit_acc=v57) + block 11 start_pc=0 v58 Imm(10) -> x0 terminator Return(v58) (exit_acc=v58) - block 20 start_pc=0 + block 12 start_pc=0 v59 LocalAddr(-12) -> x0 v60 Imm(0) -> x1 v61 Imm(100) -> x1 @@ -122,25 +98,49 @@ fn ent_pc=1 n_params=0 variadic=false locals=14 v76 BinopI { op=add, lhs=v73, rhs_imm=8 } -> x1 v77 Load { addr=v73, disp=8, kind=I64 } -> x1 v78 BinopI { op=ne, lhs=v77, rhs_imm=200 } -> x1 - terminator Bz { cond=v78, target=b22, fall=b21 } (exit_acc=v78) - block 21 start_pc=0 + terminator Bz { cond=v78, target=b14, fall=b13 } (exit_acc=v78) + block 13 start_pc=0 v79 Imm(11) -> x0 terminator Return(v79) (exit_acc=v79) - block 22 start_pc=0 + block 14 start_pc=0 v80 LoadLocal { off=-13, kind=I64 } -> x1 v81 Imm(16) -> x1 v82 BinopI { op=add, lhs=v73, rhs_imm=16 } -> x1 v83 Load { addr=v73, disp=16, kind=I64 } -> x0 v84 BinopI { op=ne, lhs=v83, rhs_imm=300 } -> x0 - terminator Bz { cond=v84, target=b24, fall=b23 } (exit_acc=v84) - block 23 start_pc=0 + terminator Bz { cond=v84, target=b16, fall=b15 } (exit_acc=v84) + block 15 start_pc=0 v85 Imm(12) -> x0 terminator Return(v85) (exit_acc=v85) - block 24 start_pc=0 + block 16 start_pc=0 v86 ImmData(36) -> x7 v87 CallExt { binding_idx=0, args=[v86], fp_arg_mask=0x0 } -> x0 v88 Imm(0) -> x0 terminator Return(v88) (exit_acc=v88) + block 17 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 18 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 19 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 20 start_pc=0 + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) + block 21 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 22 start_pc=0 + v15 Imm(6) -> x0 + terminator Return(v15) (exit_acc=v15) + block 23 start_pc=0 + v20 Imm(7) -> x0 + terminator Return(v20) (exit_acc=v20) + block 24 start_pc=0 + v31 Imm(8) -> x0 + terminator Return(v31) (exit_acc=v31) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/lp64_predefine.ssa b/tests/snapshots/ssa/lp64_predefine.ssa index 18039c6a2..f83f6ead1 100644 --- a/tests/snapshots/ssa/lp64_predefine.ssa +++ b/tests/snapshots/ssa/lp64_predefine.ssa @@ -5,25 +5,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(1) -> x0 - terminator Jmp(b3) (exit_acc=v3) - block 3 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) + block 3 start_pc=0 + v8 Phi { incoming=[b2:v4, b5:v6], kind=I64 } -> x1 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Return(v8) (exit_acc=v8) block 4 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 5 start_pc=0 v6 Imm(3) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v6) - block 5 start_pc=0 - v8 Phi { incoming=[b3:v4, b4:v6], kind=I64 } -> x1 - v9 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Return(v8) (exit_acc=v8) + terminator Jmp(b3) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/macro_argument_rescan.ssa b/tests/snapshots/ssa/macro_argument_rescan.ssa index 1d1699675..3ae00f1e8 100644 --- a/tests/snapshots/ssa/macro_argument_rescan.ssa +++ b/tests/snapshots/ssa/macro_argument_rescan.ssa @@ -7,29 +7,29 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 v1 Imm(7) -> x0 v2 Imm(30064771072) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(4) -> x0 v6 Imm(17179869184) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(2) -> x0 - terminator Return(v8) (exit_acc=v8) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 v9 Imm(123) -> x0 v10 Imm(528280977408) -> x0 v11 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v11) + terminator Jmp(b3) (exit_acc=v11) + block 3 start_pc=0 + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) + block 4 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 5 start_pc=0 + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) + block 6 start_pc=0 v12 Imm(3) -> x0 terminator Return(v12) (exit_acc=v12) - block 6 start_pc=0 - v13 Imm(0) -> x0 - terminator Return(v13) (exit_acc=v13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/macro_multiline_comment_body.ssa b/tests/snapshots/ssa/macro_multiline_comment_body.ssa index 1e5957666..94fc06e64 100644 --- a/tests/snapshots/ssa/macro_multiline_comment_body.ssa +++ b/tests/snapshots/ssa/macro_multiline_comment_body.ssa @@ -8,53 +8,53 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 v2 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x1 + v3 Phi { incoming=[b0:v1, b4:v8], kind=I64 } -> x1 v4 Imm(1) -> x0 - terminator Jmp(b4) (exit_acc=v4) + terminator Jmp(b2) (exit_acc=v4) block 2 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 3 start_pc=0 - terminator Jmp(b6) - block 4 start_pc=0 v6 Imm(7) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v6) + terminator Jmp(b3) (exit_acc=v6) + block 3 start_pc=0 + v8 Phi { incoming=[b1:v3, b2:v6], kind=I64 } -> x1 + terminator Jmp(b4) + block 4 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v5) block 5 start_pc=0 - v8 Phi { incoming=[b1:v3, b4:v6], kind=I64 } -> x1 - terminator Jmp(b2) + terminator Jmp(b6) block 6 start_pc=0 - v9 Phi { incoming=[b3:v8, b7:v16], kind=I64 } -> x1 + v9 Phi { incoming=[b5:v8, b8:v16], kind=I64 } -> x1 v10 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v10) + terminator Jmp(b7) (exit_acc=v10) block 7 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v11) + v16 Phi { incoming=[b6:v9, b14:v14], kind=I64 } -> x1 + terminator Jmp(b8) block 8 start_pc=0 + v11 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v11) + block 9 start_pc=0 v12 Extend { value=v16, kind=I32 } -> x0 v13 BinopI { op=ne, lhs=v12, rhs_imm=7 } -> x0 - terminator Bz { cond=v13, target=b12, fall=b11 } (exit_acc=v13) - block 9 start_pc=0 - v14 Imm(99) -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v14) + terminator Bz { cond=v13, target=b11, fall=b10 } (exit_acc=v13) block 10 start_pc=0 - v16 Phi { incoming=[b6:v9, b9:v14], kind=I64 } -> x1 - terminator Jmp(b7) - block 11 start_pc=0 v17 Imm(1) -> x0 terminator Return(v17) (exit_acc=v17) - block 12 start_pc=0 + block 11 start_pc=0 v18 ImmData(40) -> x0 v19 Load { addr=v18, disp=0, kind=I32 } -> x0 v20 BinopI { op=ne, lhs=v19, rhs_imm=1234 } -> x0 - terminator Bz { cond=v20, target=b14, fall=b13 } (exit_acc=v20) - block 13 start_pc=0 + terminator Bz { cond=v20, target=b13, fall=b12 } (exit_acc=v20) + block 12 start_pc=0 v21 Imm(2) -> x0 terminator Return(v21) (exit_acc=v21) - block 14 start_pc=0 + block 13 start_pc=0 v22 Imm(0) -> x0 terminator Return(v22) (exit_acc=v22) + block 14 start_pc=0 + v14 Imm(99) -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/macro_operators.ssa b/tests/snapshots/ssa/macro_operators.ssa index 86077d40c..84b1f0e48 100644 --- a/tests/snapshots/ssa/macro_operators.ssa +++ b/tests/snapshots/ssa/macro_operators.ssa @@ -88,37 +88,31 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 terminator Return(v37) (exit_acc=v37) block 12 start_pc=0 v38 Imm(42) -> x0 - v39 Imm(0) -> x1 - v40 LoadLocal { off=-2, kind=I32 } -> x1 - v41 BinopI { op=ne, lhs=v38, rhs_imm=42 } -> x0 - terminator Bz { cond=v41, target=b14, fall=b13 } (exit_acc=v41) + v39 Imm(0) -> x0 + v40 LoadLocal { off=-2, kind=I32 } -> x0 + v41 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v41) block 13 start_pc=0 - v42 Imm(7) -> x0 - terminator Return(v42) (exit_acc=v42) - block 14 start_pc=0 v43 Imm(1) -> x0 - v44 Imm(2) -> x1 - v45 Imm(3) -> x2 - v46 Extend { value=v43, kind=I32 } -> x6 - v47 Imm(0) -> x6 - v48 Extend { value=v44, kind=I32 } -> x6 - v49 Imm(0) -> x6 - v50 Extend { value=v45, kind=I32 } -> x6 - v51 Imm(0) -> x6 - v52 Binop { op=add, lhs=v43, rhs=v44 } -> x0 - v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> x1 - v54 Extend { value=v52, kind=I32 } -> x1 - v55 Binop { op=add, lhs=v52, rhs=v45 } -> x0 - v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 - v57 Extend { value=v55, kind=I32 } -> x0 - v58 Imm(0) -> x1 - v59 Extend { value=v57, kind=I32 } -> x0 - v60 BinopI { op=ne, lhs=v59, rhs_imm=6 } -> x0 - terminator Bz { cond=v60, target=b16, fall=b15 } (exit_acc=v60) - block 15 start_pc=0 - v61 Imm(8) -> x0 - terminator Return(v61) (exit_acc=v61) - block 16 start_pc=0 + v44 Imm(2) -> x0 + v45 Imm(3) -> x0 + v46 Imm(1) -> x0 + v47 Imm(0) -> x0 + v48 Imm(2) -> x0 + v49 Imm(0) -> x0 + v50 Imm(3) -> x0 + v51 Imm(0) -> x0 + v52 Imm(3) -> x0 + v53 Imm(12884901888) -> x0 + v54 Imm(3) -> x0 + v55 Imm(6) -> x0 + v56 Imm(25769803776) -> x0 + v57 Imm(6) -> x0 + v58 Imm(0) -> x0 + v59 Imm(6) -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v60) + block 14 start_pc=0 v62 ImmData(42) -> x7 v63 Imm(7) -> x6 v64 Imm(8) -> x2 @@ -126,6 +120,12 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 v66 CallExt { binding_idx=0, args=[v62, v63, v64, v65], fp_arg_mask=0x0 } -> x0 v67 Imm(0) -> x0 terminator Return(v67) (exit_acc=v67) + block 15 start_pc=0 + v42 Imm(7) -> x0 + terminator Return(v42) (exit_acc=v42) + block 16 start_pc=0 + v61 Imm(8) -> x0 + terminator Return(v61) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/macro_paste_rescan.ssa b/tests/snapshots/ssa/macro_paste_rescan.ssa index e505aeca2..725262d4f 100644 --- a/tests/snapshots/ssa/macro_paste_rescan.ssa +++ b/tests/snapshots/ssa/macro_paste_rescan.ssa @@ -6,44 +6,44 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 v0 AllocaInit(0) -> - v1 Imm(3) -> x0 v2 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v2) + terminator Jmp(b1) (exit_acc=v2) block 1 start_pc=0 - v3 Imm(11) -> x0 - terminator Return(v3) (exit_acc=v3) - block 2 start_pc=0 v4 Imm(3) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v5) - block 3 start_pc=0 - v6 Imm(12) -> x0 - terminator Return(v6) (exit_acc=v6) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v5) + block 2 start_pc=0 v7 Imm(50) -> x0 v8 Imm(214748364800) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v9) - block 5 start_pc=0 - v10 Imm(13) -> x0 - terminator Return(v10) (exit_acc=v10) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v9) + block 3 start_pc=0 v11 Imm(17) -> x0 v12 Imm(73014444032) -> x0 v13 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v13) - block 7 start_pc=0 - v14 Imm(14) -> x0 - terminator Return(v14) (exit_acc=v14) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v13) + block 4 start_pc=0 v15 Imm(3) -> x0 v16 Imm(12884901888) -> x0 v17 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v17) + terminator Jmp(b5) (exit_acc=v17) + block 5 start_pc=0 + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) + block 6 start_pc=0 + v3 Imm(11) -> x0 + terminator Return(v3) (exit_acc=v3) + block 7 start_pc=0 + v6 Imm(12) -> x0 + terminator Return(v6) (exit_acc=v6) + block 8 start_pc=0 + v10 Imm(13) -> x0 + terminator Return(v10) (exit_acc=v10) block 9 start_pc=0 + v14 Imm(14) -> x0 + terminator Return(v14) (exit_acc=v14) + block 10 start_pc=0 v18 Imm(15) -> x0 terminator Return(v18) (exit_acc=v18) - block 10 start_pc=0 - v19 Imm(0) -> x0 - terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/macro_paste_stringize_unexpanded.ssa b/tests/snapshots/ssa/macro_paste_stringize_unexpanded.ssa index 76f62691f..d40a219ba 100644 --- a/tests/snapshots/ssa/macro_paste_stringize_unexpanded.ssa +++ b/tests/snapshots/ssa/macro_paste_stringize_unexpanded.ssa @@ -44,7 +44,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v30 LoadLocal { off=-6, kind=I64 } -> x1 v31 Imm(1) -> x2 v32 Imm(0) -> x1 - terminator Bnz { cond=v29, target=b16, fall=b5 } (exit_acc=v29) + terminator Bnz { cond=v29, target=b14, fall=b5 } (exit_acc=v29) block 5 start_pc=0 v33 LoadLocal { off=-1, kind=I64 } -> x1 v34 Imm(2) -> x1 @@ -55,10 +55,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v39 Imm(0) -> x1 terminator Jmp(b6) (exit_acc=v38) block 6 start_pc=0 - v40 Phi { incoming=[b16:v31, b5:v38], kind=I64 } -> x2 + v40 Phi { incoming=[b14:v31, b5:v38], kind=I64 } -> x2 v41 LoadLocal { off=-5, kind=I64 } -> x1 v42 Imm(0) -> x1 - terminator Bnz { cond=v40, target=b17, fall=b7 } (exit_acc=v40) + terminator Bnz { cond=v40, target=b13, fall=b7 } (exit_acc=v40) block 7 start_pc=0 v43 LoadLocal { off=-1, kind=I64 } -> x1 v44 Imm(3) -> x1 @@ -68,7 +68,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v48 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v47) block 8 start_pc=0 - v49 Phi { incoming=[b17:v40, b7:v47], kind=I64 } -> x2 + v49 Phi { incoming=[b13:v40, b7:v47], kind=I64 } -> x2 v50 LoadLocal { off=-4, kind=I64 } -> x0 terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) block 9 start_pc=0 @@ -76,31 +76,31 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 terminator Return(v51) (exit_acc=v51) block 10 start_pc=0 v52 Imm(7) -> x0 - v53 Imm(0) -> x1 - v54 LoadLocal { off=-2, kind=I32 } -> x1 - v55 BinopI { op=ne, lhs=v52, rhs_imm=7 } -> x0 - terminator Bz { cond=v55, target=b12, fall=b11 } (exit_acc=v55) + v53 Imm(0) -> x0 + v54 LoadLocal { off=-2, kind=I32 } -> x0 + v55 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v55) block 11 start_pc=0 - v56 Imm(3) -> x0 - terminator Return(v56) (exit_acc=v56) - block 12 start_pc=0 v57 Imm(9) -> x0 - v58 Imm(0) -> x1 - v59 LoadLocal { off=-3, kind=I32 } -> x1 - v60 BinopI { op=ne, lhs=v57, rhs_imm=9 } -> x0 - terminator Bz { cond=v60, target=b14, fall=b13 } (exit_acc=v60) - block 13 start_pc=0 - v61 Imm(4) -> x0 - terminator Return(v61) (exit_acc=v61) - block 14 start_pc=0 + v58 Imm(0) -> x0 + v59 LoadLocal { off=-3, kind=I32 } -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v60) + block 12 start_pc=0 v62 Imm(0) -> x0 terminator Return(v62) (exit_acc=v62) + block 13 start_pc=0 + terminator Jmp(b8) + block 14 start_pc=0 + terminator Jmp(b6) block 15 start_pc=0 terminator Jmp(b4) block 16 start_pc=0 - terminator Jmp(b6) + v56 Imm(3) -> x0 + terminator Return(v56) (exit_acc=v56) block 17 start_pc=0 - terminator Jmp(b8) + v61 Imm(4) -> x0 + terminator Return(v61) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/math_classify.ssa b/tests/snapshots/ssa/math_classify.ssa index b139a45c1..9607ded70 100644 --- a/tests/snapshots/ssa/math_classify.ssa +++ b/tests/snapshots/ssa/math_classify.ssa @@ -20,46 +20,46 @@ fn ent_pc=0 n_params=1 variadic=false locals=5 v14 Imm(0) -> x2 v15 LoadLocal { off=-2, kind=I64 } -> x2 v16 BinopI { op=eq, lhs=v9, rhs_imm=0 } -> x2 - terminator Bz { cond=v16, target=b2, fall=b1 } (exit_acc=v16) + terminator Bz { cond=v16, target=b5, fall=b1 } (exit_acc=v16) block 1 start_pc=0 v17 LoadLocal { off=-3, kind=I64 } -> x0 v18 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) + terminator Bz { cond=v18, target=b4, fall=b2 } (exit_acc=v18) block 2 start_pc=0 - v19 LoadLocal { off=-2, kind=I64 } -> x2 - v20 BinopI { op=eq, lhs=v9, rhs_imm=2047 } -> x0 - terminator Bz { cond=v20, target=b7, fall=b6 } (exit_acc=v20) - block 3 start_pc=0 v21 Imm(2) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v21) + terminator Jmp(b3) (exit_acc=v21) + block 3 start_pc=0 + v25 Phi { incoming=[b2:v21, b4:v23], kind=I64 } -> x1 + v26 LoadLocal { off=-4, kind=I64 } -> x0 + terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 v23 Imm(3) -> x1 v24 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v23) + terminator Jmp(b3) (exit_acc=v23) block 5 start_pc=0 - v25 Phi { incoming=[b3:v21, b4:v23], kind=I64 } -> x1 - v26 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Return(v25) (exit_acc=v25) + v19 LoadLocal { off=-2, kind=I64 } -> x2 + v20 BinopI { op=eq, lhs=v9, rhs_imm=2047 } -> x0 + terminator Bz { cond=v20, target=b10, fall=b6 } (exit_acc=v20) block 6 start_pc=0 v27 LoadLocal { off=-3, kind=I64 } -> x0 v28 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v28, target=b9, fall=b8 } (exit_acc=v28) + terminator Bz { cond=v28, target=b9, fall=b7 } (exit_acc=v28) block 7 start_pc=0 - v29 Imm(4) -> x0 - terminator Return(v29) (exit_acc=v29) - block 8 start_pc=0 v30 Imm(1) -> x1 v31 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v30) + terminator Jmp(b8) (exit_acc=v30) + block 8 start_pc=0 + v34 Phi { incoming=[b7:v30, b9:v32], kind=I64 } -> x1 + v35 LoadLocal { off=-5, kind=I64 } -> x0 + terminator Return(v34) (exit_acc=v34) block 9 start_pc=0 v32 Imm(0) -> x1 v33 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v32) + terminator Jmp(b8) (exit_acc=v32) block 10 start_pc=0 - v34 Phi { incoming=[b8:v30, b9:v32], kind=I64 } -> x1 - v35 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Return(v34) (exit_acc=v34) + v29 Imm(4) -> x0 + terminator Return(v29) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=isnan fn ent_pc=1 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mcpy_temp_aliases_src.ssa b/tests/snapshots/ssa/mcpy_temp_aliases_src.ssa index b7717aff9..70622ddf9 100644 --- a/tests/snapshots/ssa/mcpy_temp_aliases_src.ssa +++ b/tests/snapshots/ssa/mcpy_temp_aliases_src.ssa @@ -1,114 +1,114 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=15 - spill_count=0 gpr_used=[3, 12, 13, 14] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 Imm(2) -> x1 - v4 Imm(0) -> x2 - v5 Imm(3) -> x2 - v6 Imm(0) -> x6 - v7 Imm(4) -> x6 - v8 Imm(0) -> x7 - v9 Imm(5) -> x7 - v10 Imm(0) -> x8 - v11 Imm(6) -> x8 - v12 Imm(0) -> x9 - v13 Imm(7) -> x9 - v14 Imm(0) -> x3 - v15 Imm(8) -> x3 - v16 Imm(0) -> x12 - v17 Imm(9) -> x12 - v18 Imm(0) -> x13 - v19 Imm(10) -> x13 - v20 Imm(0) -> x14 - v21 LoadLocal { off=-5, kind=I32 } -> x14 - v22 LoadLocal { off=-6, kind=I32 } -> x14 - v23 Binop { op=add, lhs=v1, rhs=v3 } -> x0 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x1 - v25 Extend { value=v23, kind=I32 } -> x1 - v26 LoadLocal { off=-7, kind=I32 } -> x1 - v27 Binop { op=add, lhs=v23, rhs=v5 } -> x0 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 - v29 Extend { value=v27, kind=I32 } -> x1 - v30 LoadLocal { off=-8, kind=I32 } -> x1 - v31 Binop { op=add, lhs=v27, rhs=v7 } -> x0 - v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x1 - v33 Extend { value=v31, kind=I32 } -> x1 - v34 LoadLocal { off=-9, kind=I32 } -> x1 - v35 Binop { op=add, lhs=v31, rhs=v9 } -> x0 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x1 - v37 Extend { value=v35, kind=I32 } -> x1 - v38 LoadLocal { off=-10, kind=I32 } -> x1 - v39 Binop { op=add, lhs=v35, rhs=v11 } -> x0 - v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x1 - v41 Extend { value=v39, kind=I32 } -> x1 - v42 LoadLocal { off=-11, kind=I32 } -> x1 - v43 Binop { op=add, lhs=v39, rhs=v13 } -> x0 - v44 BinopI { op=shl, lhs=v43, rhs_imm=32 } -> x1 - v45 Extend { value=v43, kind=I32 } -> x1 - v46 LoadLocal { off=-12, kind=I32 } -> x1 - v47 Binop { op=add, lhs=v43, rhs=v15 } -> x0 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x1 - v49 Extend { value=v47, kind=I32 } -> x1 - v50 LoadLocal { off=-13, kind=I32 } -> x1 - v51 Binop { op=add, lhs=v47, rhs=v17 } -> x0 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x1 - v53 Extend { value=v51, kind=I32 } -> x1 - v54 LoadLocal { off=-14, kind=I32 } -> x1 - v55 Binop { op=add, lhs=v51, rhs=v19 } -> x0 - v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 - v57 Extend { value=v55, kind=I32 } -> x0 - v58 Imm(0) -> x1 - v59 LocalAddr(-4) -> x1 - v60 ImmData(8) -> x2 - v61 Mcpy { dst=v59, src=v60, size=32 } -> x1 - v62 LoadLocal { off=-15, kind=I32 } -> x1 - v63 BinopI { op=ne, lhs=v57, rhs_imm=55 } -> x0 - terminator Bz { cond=v63, target=b2, fall=b1 } (exit_acc=v63) + v2 Imm(0) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 Imm(3) -> x0 + v6 Imm(0) -> x0 + v7 Imm(4) -> x0 + v8 Imm(0) -> x0 + v9 Imm(5) -> x0 + v10 Imm(0) -> x0 + v11 Imm(6) -> x0 + v12 Imm(0) -> x0 + v13 Imm(7) -> x0 + v14 Imm(0) -> x0 + v15 Imm(8) -> x0 + v16 Imm(0) -> x0 + v17 Imm(9) -> x0 + v18 Imm(0) -> x0 + v19 Imm(10) -> x0 + v20 Imm(0) -> x0 + v21 LoadLocal { off=-5, kind=I32 } -> x0 + v22 LoadLocal { off=-6, kind=I32 } -> x0 + v23 Imm(3) -> x0 + v24 Imm(12884901888) -> x0 + v25 Imm(3) -> x0 + v26 LoadLocal { off=-7, kind=I32 } -> x0 + v27 Imm(6) -> x0 + v28 Imm(25769803776) -> x0 + v29 Imm(6) -> x0 + v30 LoadLocal { off=-8, kind=I32 } -> x0 + v31 Imm(10) -> x0 + v32 Imm(42949672960) -> x0 + v33 Imm(10) -> x0 + v34 LoadLocal { off=-9, kind=I32 } -> x0 + v35 Imm(15) -> x0 + v36 Imm(64424509440) -> x0 + v37 Imm(15) -> x0 + v38 LoadLocal { off=-10, kind=I32 } -> x0 + v39 Imm(21) -> x0 + v40 Imm(90194313216) -> x0 + v41 Imm(21) -> x0 + v42 LoadLocal { off=-11, kind=I32 } -> x0 + v43 Imm(28) -> x0 + v44 Imm(120259084288) -> x0 + v45 Imm(28) -> x0 + v46 LoadLocal { off=-12, kind=I32 } -> x0 + v47 Imm(36) -> x0 + v48 Imm(154618822656) -> x0 + v49 Imm(36) -> x0 + v50 LoadLocal { off=-13, kind=I32 } -> x0 + v51 Imm(45) -> x0 + v52 Imm(193273528320) -> x0 + v53 Imm(45) -> x0 + v54 LoadLocal { off=-14, kind=I32 } -> x0 + v55 Imm(55) -> x0 + v56 Imm(236223201280) -> x0 + v57 Imm(55) -> x0 + v58 Imm(0) -> x0 + v59 LocalAddr(-4) -> x0 + v60 ImmData(8) -> x1 + v61 Mcpy { dst=v59, src=v60, size=32 } -> x0 + v62 LoadLocal { off=-15, kind=I32 } -> x0 + v63 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v63) block 1 start_pc=0 - v64 Imm(1) -> x0 - terminator Return(v64) (exit_acc=v64) - block 2 start_pc=0 v65 LocalAddr(-4) -> x0 v66 Load { addr=v65, disp=0, kind=I64 } -> x0 v67 BinopI { op=ne, lhs=v66, rhs_imm=4369 } -> x0 - terminator Bz { cond=v67, target=b4, fall=b3 } (exit_acc=v67) - block 3 start_pc=0 + terminator Bz { cond=v67, target=b3, fall=b2 } (exit_acc=v67) + block 2 start_pc=0 v68 Imm(2) -> x0 terminator Return(v68) (exit_acc=v68) - block 4 start_pc=0 + block 3 start_pc=0 v69 LocalAddr(-4) -> x0 v70 BinopI { op=add, lhs=v69, rhs_imm=8 } -> x1 v71 Load { addr=v69, disp=8, kind=I64 } -> x0 v72 BinopI { op=ne, lhs=v71, rhs_imm=8738 } -> x0 - terminator Bz { cond=v72, target=b6, fall=b5 } (exit_acc=v72) - block 5 start_pc=0 + terminator Bz { cond=v72, target=b5, fall=b4 } (exit_acc=v72) + block 4 start_pc=0 v73 Imm(3) -> x0 terminator Return(v73) (exit_acc=v73) - block 6 start_pc=0 + block 5 start_pc=0 v74 LocalAddr(-4) -> x0 v75 BinopI { op=add, lhs=v74, rhs_imm=16 } -> x1 v76 Load { addr=v74, disp=16, kind=I64 } -> x0 v77 BinopI { op=ne, lhs=v76, rhs_imm=13107 } -> x0 - terminator Bz { cond=v77, target=b8, fall=b7 } (exit_acc=v77) - block 7 start_pc=0 + terminator Bz { cond=v77, target=b7, fall=b6 } (exit_acc=v77) + block 6 start_pc=0 v78 Imm(4) -> x0 terminator Return(v78) (exit_acc=v78) - block 8 start_pc=0 + block 7 start_pc=0 v79 LocalAddr(-4) -> x0 v80 BinopI { op=add, lhs=v79, rhs_imm=24 } -> x1 v81 Load { addr=v79, disp=24, kind=I64 } -> x0 v82 BinopI { op=ne, lhs=v81, rhs_imm=17476 } -> x0 - terminator Bz { cond=v82, target=b10, fall=b9 } (exit_acc=v82) - block 9 start_pc=0 + terminator Bz { cond=v82, target=b9, fall=b8 } (exit_acc=v82) + block 8 start_pc=0 v83 Imm(5) -> x0 terminator Return(v83) (exit_acc=v83) - block 10 start_pc=0 + block 9 start_pc=0 v84 Imm(0) -> x0 terminator Return(v84) (exit_acc=v84) + block 10 start_pc=0 + v64 Imm(1) -> x0 + terminator Return(v64) (exit_acc=v64) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_addr_taken_neighbor.ssa b/tests/snapshots/ssa/mem2reg_addr_taken_neighbor.ssa index fbe515f73..1079540d7 100644 --- a/tests/snapshots/ssa/mem2reg_addr_taken_neighbor.ssa +++ b/tests/snapshots/ssa/mem2reg_addr_taken_neighbor.ssa @@ -6,39 +6,66 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 - v3 Imm(0) -> x6 + v3 Imm(0) -> x0 v4 StoreLocal { off=-1, value=v3, kind=I32 } -> - - v5 LoadLocal { off=2, kind=I32 } -> x0 - v6 BinopI { op=shl, lhs=v1, rhs_imm=1 } -> x0 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x1 - v9 Imm(0) -> x1 - v10 LocalAddr(-1) -> x1 - v11 Imm(0) -> x2 - v12 Imm(0) -> x2 + v5 LoadLocal { off=2, kind=I32 } -> x1 + v6 BinopI { op=shl, lhs=v1, rhs_imm=1 } -> x1 + v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x2 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 Imm(0) -> x2 + v10 LocalAddr(-1) -> x2 + v11 Imm(0) -> x6 + v12 Imm(0) -> x6 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v13 Phi { incoming=[b0:v3, b2:v26], kind=I64 } -> x6 - v14 Extend { value=v13, kind=I32 } -> x2 - v15 BinopI { op=lt, lhs=v14, rhs_imm=3 } -> x2 - terminator Bz { cond=v15, target=b3, fall=b2 } (exit_acc=v15) + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 LoadLocal { off=-3, kind=I64 } -> x0 + v16 Load { addr=v10, disp=0, kind=I32 } -> x0 + v17 LoadLocal { off=-2, kind=I32 } -> x6 + v18 Binop { op=add, lhs=v16, rhs=v6 } -> x0 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x6 + v20 Extend { value=v18, kind=I32 } -> x6 + v21 Store { addr=v10, disp=0, value=v18, kind=I32 } -> - + v22 Imm(0) -> x6 + v23 Imm(1) -> x6 + v24 Imm(4294967296) -> x6 + v25 Imm(1) -> x6 + v26 Imm(0) -> x6 + v27 Imm(1) -> x6 + v28 Imm(1) -> x6 + v29 LoadLocal { off=-3, kind=I64 } -> x6 + v30 Extend { value=v18, kind=I32 } -> x0 + v31 LoadLocal { off=-2, kind=I32 } -> x6 + v32 Binop { op=add, lhs=v30, rhs=v6 } -> x0 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x6 + v34 Extend { value=v32, kind=I32 } -> x6 + v35 Store { addr=v10, disp=0, value=v32, kind=I32 } -> - + v36 Imm(1) -> x6 + v37 Imm(2) -> x6 + v38 Imm(8589934592) -> x6 + v39 Imm(2) -> x6 + v40 Imm(0) -> x6 + v41 Imm(2) -> x6 + v42 Imm(1) -> x6 + v43 LoadLocal { off=-3, kind=I64 } -> x6 + v44 Extend { value=v32, kind=I32 } -> x0 + v45 LoadLocal { off=-2, kind=I32 } -> x6 + v46 Binop { op=add, lhs=v44, rhs=v6 } -> x0 + v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x1 + v48 Extend { value=v46, kind=I32 } -> x1 + v49 Store { addr=v10, disp=0, value=v46, kind=I32 } -> - + v50 Imm(2) -> x0 + v51 Imm(3) -> x0 + v52 Imm(12884901888) -> x0 + v53 Imm(3) -> x0 + v54 Imm(0) -> x0 + v55 Imm(3) -> x0 + v56 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v56) block 2 start_pc=0 - v16 LoadLocal { off=-3, kind=I64 } -> x2 - v17 Load { addr=v10, disp=0, kind=I32 } -> x2 - v18 LoadLocal { off=-2, kind=I32 } -> x7 - v19 Binop { op=add, lhs=v17, rhs=v6 } -> x2 - v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x7 - v21 Extend { value=v19, kind=I32 } -> x7 - v22 Store { addr=v10, disp=0, value=v19, kind=I32 } -> - - v23 Extend { value=v13, kind=I32 } -> x2 - v24 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x2 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x6 - v26 Extend { value=v24, kind=I32 } -> x6 - v27 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v26) - block 3 start_pc=0 - v28 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v28) (exit_acc=v28) + v57 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v57) (exit_acc=v57) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_cross_block.ssa b/tests/snapshots/ssa/mem2reg_cross_block.ssa index 180876107..ca60a5135 100644 --- a/tests/snapshots/ssa/mem2reg_cross_block.ssa +++ b/tests/snapshots/ssa/mem2reg_cross_block.ssa @@ -5,33 +5,57 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(14) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 v4 Imm(0) -> x1 v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v19], kind=I64 } -> x2 - v7 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x6 - v9 BinopI { op=lt, lhs=v8, rhs_imm=3 } -> x6 - terminator Bz { cond=v9, target=b3, fall=b2 } (exit_acc=v9) + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I32 } -> x0 + v10 Imm(14) -> x0 + v11 Imm(60129542144) -> x0 + v12 Imm(14) -> x0 + v13 Imm(0) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(4294967296) -> x0 + v17 Imm(1) -> x0 + v18 Imm(0) -> x0 + v19 Imm(1) -> x0 + v20 Imm(1) -> x0 + v21 Imm(14) -> x0 + v22 LoadLocal { off=-1, kind=I32 } -> x0 + v23 Imm(28) -> x0 + v24 Imm(120259084288) -> x0 + v25 Imm(28) -> x0 + v26 Imm(0) -> x0 + v27 Imm(1) -> x0 + v28 Imm(2) -> x0 + v29 Imm(8589934592) -> x0 + v30 Imm(2) -> x0 + v31 Imm(0) -> x0 + v32 Imm(2) -> x0 + v33 Imm(1) -> x0 + v34 Imm(28) -> x0 + v35 LoadLocal { off=-1, kind=I32 } -> x0 + v36 Imm(42) -> x0 + v37 Imm(180388626432) -> x0 + v38 Imm(42) -> x0 + v39 Imm(0) -> x0 + v40 Imm(2) -> x0 + v41 Imm(3) -> x0 + v42 Imm(12884901888) -> x0 + v43 Imm(3) -> x0 + v44 Imm(0) -> x0 + v45 Imm(3) -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v46) block 2 start_pc=0 - v10 Extend { value=v7, kind=I32 } -> x6 - v11 LoadLocal { off=-1, kind=I32 } -> x6 - v12 Binop { op=add, lhs=v7, rhs=v1 } -> x1 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x6 - v14 Extend { value=v12, kind=I32 } -> x6 - v15 Imm(0) -> x6 - v16 Extend { value=v6, kind=I32 } -> x6 - v17 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x2 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x6 - v19 Extend { value=v17, kind=I32 } -> x2 - v20 Imm(0) -> x6 - terminator Jmp(b1) (exit_acc=v19) - block 3 start_pc=0 - v21 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v21) (exit_acc=v21) + v47 Imm(42) -> x0 + terminator Return(v47) (exit_acc=v47) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_i64_local.ssa b/tests/snapshots/ssa/mem2reg_i64_local.ssa index 86007816d..332e28347 100644 --- a/tests/snapshots/ssa/mem2reg_i64_local.ssa +++ b/tests/snapshots/ssa/mem2reg_i64_local.ssa @@ -9,28 +9,53 @@ fn ent_pc=0 n_params=1 variadic=false locals=3 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 BinopI { op=mul, lhs=v1, rhs_imm=3 } -> x0 v5 Imm(0) -> x1 - v6 Imm(0) -> x2 - v7 Imm(0) -> x1 - v8 Imm(0) -> x1 + v6 Imm(0) -> x1 + v7 Imm(0) -> x2 + v8 Imm(0) -> x2 terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v9 Phi { incoming=[b0:v6, b2:v18], kind=I64 } -> x2 - v10 Phi { incoming=[b0:v6, b2:v15], kind=I64 } -> x1 - v11 LoadLocal { off=-3, kind=I64 } -> x6 - v12 BinopI { op=lt, lhs=v9, rhs_imm=4 } -> x6 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) + v9 LoadLocal { off=-3, kind=I64 } -> x1 + v10 Imm(1) -> x1 + v11 LoadLocal { off=-2, kind=I64 } -> x1 + v12 LoadLocal { off=-1, kind=I64 } -> x1 + v13 BinopI { op=add, lhs=v4, rhs_imm=0 } -> x1 + v14 Imm(0) -> x2 + v15 LoadLocal { off=-3, kind=I64 } -> x2 + v16 Imm(1) -> x2 + v17 Imm(0) -> x2 + v18 LoadLocal { off=-3, kind=I64 } -> x2 + v19 Imm(1) -> x2 + v20 LoadLocal { off=-2, kind=I64 } -> x2 + v21 LoadLocal { off=-1, kind=I64 } -> x2 + v22 Binop { op=add, lhs=v13, rhs=v4 } -> x1 + v23 Imm(0) -> x2 + v24 LoadLocal { off=-3, kind=I64 } -> x2 + v25 Imm(2) -> x2 + v26 Imm(0) -> x2 + v27 LoadLocal { off=-3, kind=I64 } -> x2 + v28 Imm(1) -> x2 + v29 LoadLocal { off=-2, kind=I64 } -> x2 + v30 LoadLocal { off=-1, kind=I64 } -> x2 + v31 Binop { op=add, lhs=v22, rhs=v4 } -> x1 + v32 Imm(0) -> x2 + v33 LoadLocal { off=-3, kind=I64 } -> x2 + v34 Imm(3) -> x2 + v35 Imm(0) -> x2 + v36 LoadLocal { off=-3, kind=I64 } -> x2 + v37 Imm(1) -> x2 + v38 LoadLocal { off=-2, kind=I64 } -> x2 + v39 LoadLocal { off=-1, kind=I64 } -> x2 + v40 Binop { op=add, lhs=v31, rhs=v4 } -> x0 + v41 Imm(0) -> x1 + v42 LoadLocal { off=-3, kind=I64 } -> x1 + v43 Imm(4) -> x1 + v44 Imm(0) -> x1 + v45 LoadLocal { off=-3, kind=I64 } -> x1 + v46 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v46) block 2 start_pc=0 - v13 LoadLocal { off=-2, kind=I64 } -> x6 - v14 LoadLocal { off=-1, kind=I64 } -> x6 - v15 Binop { op=add, lhs=v10, rhs=v4 } -> x1 - v16 Imm(0) -> x6 - v17 LoadLocal { off=-3, kind=I64 } -> x6 - v18 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x2 - v19 Imm(0) -> x6 - terminator Jmp(b1) (exit_acc=v18) - block 3 start_pc=0 - v20 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Return(v10) (exit_acc=v10) + v47 LoadLocal { off=-2, kind=I64 } -> x1 + terminator Return(v40) (exit_acc=v40) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_narrow_store_trunc.ssa b/tests/snapshots/ssa/mem2reg_narrow_store_trunc.ssa index cbcb257c7..259c69011 100644 --- a/tests/snapshots/ssa/mem2reg_narrow_store_trunc.ssa +++ b/tests/snapshots/ssa/mem2reg_narrow_store_trunc.ssa @@ -10,19 +10,19 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v4 Imm(0) -> x0 v5 Extend { value=v1, kind=I8 } -> x0 v6 BinopI { op=eq, lhs=v5, rhs_imm=44 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b3, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v7 Imm(0) -> x1 v8 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v7) + terminator Jmp(b2) (exit_acc=v7) block 2 start_pc=0 - v9 Imm(1) -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v9) - block 3 start_pc=0 - v11 Phi { incoming=[b1:v7, b2:v9], kind=I64 } -> x1 + v11 Phi { incoming=[b1:v7, b3:v9], kind=I64 } -> x1 v12 LoadLocal { off=-2, kind=I64 } -> x0 terminator Return(v11) (exit_acc=v11) + block 3 start_pc=0 + v9 Imm(1) -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_param_promoted.ssa b/tests/snapshots/ssa/mem2reg_param_promoted.ssa index b40ee14c4..14a6aba2e 100644 --- a/tests/snapshots/ssa/mem2reg_param_promoted.ssa +++ b/tests/snapshots/ssa/mem2reg_param_promoted.ssa @@ -14,15 +14,15 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 terminator Return(v1) (exit_acc=v1) block 2 start_pc=0 v6 LoadLocal { off=2, kind=I32 } -> x0 - v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x7 - v10 Call { target_pc=0, args=[v9], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x12 v11 LoadLocal { off=2, kind=I32 } -> x0 - v12 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x7 - v15 Call { target_pc=0, args=[v14], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v12 BinopI { op=sub, lhs=v1, rhs_imm=2 } -> x7 + v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x0 + v14 Extend { value=v12, kind=I32 } -> x0 + v15 Call { target_pc=0, args=[v12], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v16 Binop { op=add, lhs=v10, rhs=v15 } -> x0 terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=1 --- diff --git a/tests/snapshots/ssa/mem2reg_unsigned_narrow.ssa b/tests/snapshots/ssa/mem2reg_unsigned_narrow.ssa index a35b74431..431485b68 100644 --- a/tests/snapshots/ssa/mem2reg_unsigned_narrow.ssa +++ b/tests/snapshots/ssa/mem2reg_unsigned_narrow.ssa @@ -5,109 +5,136 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(300) -> x0 - v2 Imm(0) -> x1 - v3 Imm(74565) -> x1 - v4 Imm(0) -> x2 - v5 Imm(0) -> x6 - v6 Imm(0) -> x2 - v7 Imm(0) -> x2 - v8 Imm(0) -> x2 + v2 Imm(0) -> x0 + v3 Imm(74565) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v9 Phi { incoming=[b0:v5, b2:v22], kind=I64 } -> x6 - v10 Phi { incoming=[b0:v5, b2:v16], kind=I64 } -> x2 - v11 Phi { incoming=[b0:v5, b2:v29], kind=I64 } -> x7 - v12 Extend { value=v11, kind=I32 } -> x8 - v13 BinopI { op=lt, lhs=v12, rhs_imm=3 } -> x8 - terminator Bz { cond=v13, target=b3, fall=b2 } (exit_acc=v13) + v9 Imm(0) -> x0 + v10 Imm(1) -> x0 + v11 Imm(0) -> x0 + v12 Imm(44) -> x0 + v13 Imm(44) -> x0 + v14 Imm(188978561024) -> x0 + v15 Imm(44) -> x0 + v16 Imm(0) -> x0 + v17 Imm(0) -> x0 + v18 Imm(9029) -> x0 + v19 Imm(9029) -> x0 + v20 Imm(38779259715584) -> x0 + v21 Imm(9029) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + v24 Imm(1) -> x0 + v25 Imm(4294967296) -> x0 + v26 Imm(1) -> x0 + v27 Imm(0) -> x0 + v28 Imm(1) -> x0 + v29 Imm(1) -> x0 + v30 Imm(44) -> x0 + v31 Imm(44) -> x0 + v32 Imm(88) -> x0 + v33 Imm(377957122048) -> x0 + v34 Imm(88) -> x0 + v35 Imm(0) -> x0 + v36 Imm(9029) -> x0 + v37 Imm(9029) -> x0 + v38 Imm(18058) -> x0 + v39 Imm(77558519431168) -> x0 + v40 Imm(18058) -> x0 + v41 Imm(0) -> x0 + v42 Imm(1) -> x0 + v43 Imm(2) -> x0 + v44 Imm(8589934592) -> x0 + v45 Imm(2) -> x0 + v46 Imm(0) -> x0 + v47 Imm(2) -> x0 + v48 Imm(1) -> x0 + v49 Imm(88) -> x0 + v50 Imm(44) -> x0 + v51 Imm(132) -> x0 + v52 Imm(566935683072) -> x0 + v53 Imm(132) -> x0 + v54 Imm(0) -> x0 + v55 Imm(18058) -> x0 + v56 Imm(9029) -> x0 + v57 Imm(27087) -> x0 + v58 Imm(116337779146752) -> x0 + v59 Imm(27087) -> x0 + v60 Imm(0) -> x0 + v61 Imm(2) -> x0 + v62 Imm(3) -> x0 + v63 Imm(12884901888) -> x0 + v64 Imm(3) -> x0 + v65 Imm(0) -> x0 + v66 Imm(3) -> x0 + v67 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v67) block 2 start_pc=0 - v14 Extend { value=v10, kind=I32 } -> x8 - v15 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x8 - v16 Binop { op=add, lhs=v10, rhs=v15 } -> x2 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x8 - v18 Extend { value=v16, kind=I32 } -> x8 - v19 Imm(0) -> x8 - v20 Extend { value=v9, kind=I32 } -> x8 - v21 BinopI { op=and, lhs=v3, rhs_imm=65535 } -> x8 - v22 Binop { op=add, lhs=v9, rhs=v21 } -> x6 - v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x8 - v24 Extend { value=v22, kind=I32 } -> x8 - v25 Imm(0) -> x8 - v26 Extend { value=v11, kind=I32 } -> x8 - v27 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x7 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x8 - v29 Extend { value=v27, kind=I32 } -> x7 - v30 Imm(0) -> x8 - terminator Jmp(b1) (exit_acc=v29) + v68 Imm(0) -> x1 + v69 Imm(0) -> x0 + v70 Imm(44) -> x0 + v71 Imm(0) -> x0 + v72 Imm(0) -> x0 + v73 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v73) block 3 start_pc=0 - v31 Imm(0) -> x8 - v32 Imm(0) -> x7 - v33 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 - v34 BinopI { op=xor, lhs=v33, rhs_imm=44 } -> x0 - v35 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x0 - v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b4 } (exit_acc=v36) + v79 Phi { incoming=[b2:v68, b7:v77], kind=I64 } -> x1 + v80 Imm(9029) -> x0 + v81 Imm(0) -> x0 + v82 Imm(0) -> x0 + v83 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v83) block 4 start_pc=0 - v37 LoadLocal { off=-6, kind=I32 } -> x0 - v38 BinopI { op=add, lhs=v31, rhs_imm=1 } -> x0 - v39 BinopI { op=shl, lhs=v38, rhs_imm=32 } -> x7 - v40 Extend { value=v38, kind=I32 } -> x8 - v41 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v40) + v89 Phi { incoming=[b3:v79, b8:v87], kind=I64 } -> x1 + v90 Imm(132) -> x0 + v91 Imm(132) -> x0 + v92 Imm(566935683072) -> x0 + v93 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v93) block 5 start_pc=0 - v42 Phi { incoming=[b12:v31, b4:v40], kind=I64 } -> x8 - v43 BinopI { op=and, lhs=v3, rhs_imm=65535 } -> x0 - v44 BinopI { op=xor, lhs=v43, rhs_imm=9029 } -> x0 - v45 BinopI { op=and, lhs=v44, rhs_imm=4294967295 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=0 } -> x0 - terminator Bz { cond=v46, target=b13, fall=b6 } (exit_acc=v46) + v99 Phi { incoming=[b4:v89, b9:v97], kind=I64 } -> x1 + v100 Imm(27087) -> x0 + v101 Imm(27087) -> x0 + v102 Imm(116337779146752) -> x0 + v103 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v103) block 6 start_pc=0 - v47 Extend { value=v42, kind=I32 } -> x0 - v48 BinopI { op=add, lhs=v42, rhs_imm=2 } -> x0 - v49 BinopI { op=shl, lhs=v48, rhs_imm=32 } -> x1 - v50 Extend { value=v48, kind=I32 } -> x8 - v51 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v50) + v109 Phi { incoming=[b5:v99, b10:v107], kind=I64 } -> x1 + v110 Extend { value=v109, kind=I32 } -> x0 + terminator Return(v110) (exit_acc=v110) block 7 start_pc=0 - v52 Phi { incoming=[b13:v42, b6:v50], kind=I64 } -> x8 - v53 Extend { value=v10, kind=I32 } -> x0 - v54 Imm(132) -> x1 - v55 Imm(566935683072) -> x1 - v56 BinopI { op=ne, lhs=v53, rhs_imm=132 } -> x0 - terminator Bz { cond=v56, target=b14, fall=b8 } (exit_acc=v56) + v74 LoadLocal { off=-6, kind=I32 } -> x0 + v75 Imm(1) -> x0 + v76 Imm(4294967296) -> x0 + v77 Imm(1) -> x1 + v78 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v77) block 8 start_pc=0 - v57 Extend { value=v52, kind=I32 } -> x0 - v58 BinopI { op=add, lhs=v52, rhs_imm=4 } -> x0 - v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x1 - v60 Extend { value=v58, kind=I32 } -> x8 - v61 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v60) + v84 Extend { value=v79, kind=I32 } -> x0 + v85 BinopI { op=add, lhs=v79, rhs_imm=2 } -> x0 + v86 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x1 + v87 Extend { value=v85, kind=I32 } -> x1 + v88 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v87) block 9 start_pc=0 - v62 Phi { incoming=[b14:v52, b8:v60], kind=I64 } -> x8 - v63 Extend { value=v9, kind=I32 } -> x0 - v64 Imm(27087) -> x1 - v65 Imm(116337779146752) -> x1 - v66 BinopI { op=ne, lhs=v63, rhs_imm=27087 } -> x0 - terminator Bz { cond=v66, target=b15, fall=b10 } (exit_acc=v66) + v94 Extend { value=v89, kind=I32 } -> x0 + v95 BinopI { op=add, lhs=v89, rhs_imm=4 } -> x0 + v96 BinopI { op=shl, lhs=v95, rhs_imm=32 } -> x1 + v97 Extend { value=v95, kind=I32 } -> x1 + v98 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v97) block 10 start_pc=0 - v67 Extend { value=v62, kind=I32 } -> x0 - v68 BinopI { op=add, lhs=v62, rhs_imm=8 } -> x0 - v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x1 - v70 Extend { value=v68, kind=I32 } -> x8 - v71 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v70) - block 11 start_pc=0 - v72 Phi { incoming=[b15:v62, b10:v70], kind=I64 } -> x8 - v73 Extend { value=v72, kind=I32 } -> x0 - terminator Return(v73) (exit_acc=v73) - block 12 start_pc=0 - terminator Jmp(b5) - block 13 start_pc=0 - terminator Jmp(b7) - block 14 start_pc=0 - terminator Jmp(b9) - block 15 start_pc=0 - terminator Jmp(b11) + v104 Extend { value=v99, kind=I32 } -> x0 + v105 BinopI { op=add, lhs=v99, rhs_imm=8 } -> x0 + v106 BinopI { op=shl, lhs=v105, rhs_imm=32 } -> x1 + v107 Extend { value=v105, kind=I32 } -> x1 + v108 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v107) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mem2reg_value_across_call.ssa b/tests/snapshots/ssa/mem2reg_value_across_call.ssa index 15037f538..7fe801bc9 100644 --- a/tests/snapshots/ssa/mem2reg_value_across_call.ssa +++ b/tests/snapshots/ssa/mem2reg_value_across_call.ssa @@ -34,34 +34,34 @@ fn ent_pc=2 n_params=1 variadic=false locals=4 v5 Imm(0) -> x13 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b2) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v27], kind=I64 } -> x13 - v9 Phi { incoming=[b0:v5, b2:v24], kind=I64 } -> x14 - v10 LoadLocal { off=-3, kind=I64 } -> x0 - v11 LoadLocal { off=2, kind=I64 } -> x0 - v12 Binop { op=lt, lhs=v8, rhs=v1 } -> x0 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) - block 2 start_pc=0 - v13 LoadLocal { off=-2, kind=I64 } -> x0 - v14 LoadLocal { off=-3, kind=I64 } -> x0 - v15 Imm(0) -> x0 - v16 BinopI { op=shl, lhs=v8, rhs_imm=1 } -> x0 - v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x0 + v13 LoadLocal { off=-2, kind=I64 } -> x1 + v14 LoadLocal { off=-3, kind=I64 } -> x1 + v15 Imm(0) -> x1 + v16 BinopI { op=shl, lhs=v8, rhs_imm=1 } -> x1 + v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x1 v18 Binop { op=add, lhs=v9, rhs=v17 } -> x14 v19 Imm(0) -> x0 v20 LoadLocal { off=-2, kind=I64 } -> x0 v21 LoadLocal { off=-3, kind=I64 } -> x0 v22 LoadLocal { off=-1, kind=I64 } -> x0 v23 CallIndirect { target=v3, args=[v8], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v24 Binop { op=add, lhs=v18, rhs=v23 } -> x14 - v25 Imm(0) -> x0 - v26 LoadLocal { off=-3, kind=I64 } -> x0 + v24 Binop { op=add, lhs=v18, rhs=v23 } -> x0 + v25 Imm(0) -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 v27 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x13 - v28 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v27) + v28 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v27) + block 2 start_pc=0 + v8 Phi { incoming=[b0:v5, b1:v27], kind=I64 } -> x13 + v9 Phi { incoming=[b0:v5, b1:v24], kind=I64 } -> x0 + v10 LoadLocal { off=-3, kind=I64 } -> x1 + v11 LoadLocal { off=2, kind=I64 } -> x1 + v12 Binop { op=lt, lhs=v8, rhs=v1 } -> x1 + terminator Bnz { cond=v12, target=b1, fall=b3 } (exit_acc=v12) block 3 start_pc=0 - v29 LoadLocal { off=-2, kind=I64 } -> x0 + v29 LoadLocal { off=-2, kind=I64 } -> x1 terminator Return(v9) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main diff --git a/tests/snapshots/ssa/mixed_signed_unsigned_div.ssa b/tests/snapshots/ssa/mixed_signed_unsigned_div.ssa index 4f95c5a25..32ffc1ff7 100644 --- a/tests/snapshots/ssa/mixed_signed_unsigned_div.ssa +++ b/tests/snapshots/ssa/mixed_signed_unsigned_div.ssa @@ -5,39 +5,39 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-1) -> x0 - v2 Imm(0) -> x1 - v3 Imm(2) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I32 } -> x2 - v6 LoadLocal { off=-2, kind=U32 } -> x2 - v7 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x2 - v8 Binop { op=divu, lhs=v7, rhs=v3 } -> x1 - v9 Imm(0) -> x2 - v10 BinopI { op=and, lhs=v8, rhs_imm=4294967295 } -> x1 - v11 BinopI { op=ne, lhs=v10, rhs_imm=2147483647 } -> x1 - terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) + v2 Imm(0) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I32 } -> x0 + v6 LoadLocal { off=-2, kind=U32 } -> x0 + v7 Imm(4294967295) -> x0 + v8 Imm(2147483647) -> x0 + v9 Imm(0) -> x0 + v10 Imm(2147483647) -> x0 + v11 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v11) block 1 start_pc=0 - v12 Imm(1) -> x0 - terminator Return(v12) (exit_acc=v12) + v13 Imm(7) -> x0 + v14 Imm(0) -> x0 + v15 LoadLocal { off=-1, kind=I32 } -> x0 + v16 LoadLocal { off=-5, kind=U32 } -> x0 + v17 Imm(4294967295) -> x0 + v18 Imm(3) -> x0 + v19 Imm(0) -> x0 + v20 Imm(3) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) block 2 start_pc=0 - v13 Imm(7) -> x1 - v14 Imm(0) -> x2 - v15 LoadLocal { off=-1, kind=I32 } -> x2 - v16 LoadLocal { off=-5, kind=U32 } -> x2 - v17 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 - v18 Binop { op=modu, lhs=v17, rhs=v13 } -> x0 - v19 Imm(0) -> x1 - v20 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 - v21 BinopI { op=xor, lhs=v20, rhs_imm=3 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v25 Imm(0) -> x0 + terminator Return(v25) (exit_acc=v25) block 3 start_pc=0 + v12 Imm(1) -> x0 + terminator Return(v12) (exit_acc=v12) + block 4 start_pc=0 v24 Imm(2) -> x0 terminator Return(v24) (exit_acc=v24) - block 4 start_pc=0 - v25 Imm(0) -> x0 - terminator Return(v25) (exit_acc=v25) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mixed_sse_int_aggregate_args.ssa b/tests/snapshots/ssa/mixed_sse_int_aggregate_args.ssa index 14b3bc870..c923ef9c3 100644 --- a/tests/snapshots/ssa/mixed_sse_int_aggregate_args.ssa +++ b/tests/snapshots/ssa/mixed_sse_int_aggregate_args.ssa @@ -13,7 +13,7 @@ fn ent_pc=0 n_params=5 variadic=false locals=9 v7 Imm(4612811918334230528) -> x0 v8 Binop { op=fne, lhs=v6, rhs=v7 } -> x1 v9 Imm(0) -> x0 - terminator Bnz { cond=v8, target=b17, fall=b1 } (exit_acc=v8) + terminator Bnz { cond=v8, target=b19, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v10 LocalAddr(-2) -> x0 v11 BinopI { op=add, lhs=v10, rhs_imm=8 } -> x1 @@ -22,7 +22,7 @@ fn ent_pc=0 n_params=5 variadic=false locals=9 v14 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Phi { incoming=[b17:v8, b1:v13], kind=I64 } -> x1 + v15 Phi { incoming=[b19:v8, b1:v13], kind=I64 } -> x1 v16 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) block 3 start_pc=0 @@ -70,7 +70,7 @@ fn ent_pc=0 n_params=5 variadic=false locals=9 v40 Imm(4615063718147915776) -> x0 v41 Binop { op=fne, lhs=v39, rhs=v40 } -> x1 v42 Imm(0) -> x0 - terminator Bnz { cond=v41, target=b19, fall=b13 } (exit_acc=v41) + terminator Bnz { cond=v41, target=b17, fall=b13 } (exit_acc=v41) block 13 start_pc=0 v43 LocalAddr(-6) -> x0 v44 BinopI { op=add, lhs=v43, rhs_imm=8 } -> x1 @@ -80,7 +80,7 @@ fn ent_pc=0 n_params=5 variadic=false locals=9 v48 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v47) block 14 start_pc=0 - v49 Phi { incoming=[b19:v41, b13:v47], kind=I64 } -> x1 + v49 Phi { incoming=[b17:v41, b13:v47], kind=I64 } -> x1 v50 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v49, target=b16, fall=b15 } (exit_acc=v49) block 15 start_pc=0 @@ -90,11 +90,11 @@ fn ent_pc=0 n_params=5 variadic=false locals=9 v52 Imm(0) -> x0 terminator Return(v52) (exit_acc=v52) block 17 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b14) block 18 start_pc=0 terminator Jmp(b8) block 19 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=docall fn ent_pc=1 n_params=5 variadic=false locals=5 diff --git a/tests/snapshots/ssa/mmap_anonymous.ssa b/tests/snapshots/ssa/mmap_anonymous.ssa index 1ac84c7c3..224c250fe 100644 --- a/tests/snapshots/ssa/mmap_anonymous.ssa +++ b/tests/snapshots/ssa/mmap_anonymous.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=8 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(16384) -> x3 @@ -11,84 +11,127 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v5 Imm(3) -> x2 v6 Imm(34) -> x1 v7 Imm(-1) -> x8 - v8 CallExt { binding_idx=54, args=[v3, v1, v5, v6, v7, v3], fp_arg_mask=0x0 } -> x12 - v9 Imm(0) -> x0 - v10 LoadLocal { off=-2, kind=I64 } -> x0 - v11 BinopI { op=eq, lhs=v8, rhs_imm=-1 } -> x0 + v8 CallExt { binding_idx=54, args=[v3, v1, v5, v6, v7, v3], fp_arg_mask=0x0 } -> x0 + v9 Imm(0) -> x1 + v10 LoadLocal { off=-2, kind=I64 } -> x1 + v11 BinopI { op=eq, lhs=v8, rhs_imm=-1 } -> x1 terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) block 1 start_pc=0 v12 Imm(1) -> x0 terminator Return(v12) (exit_acc=v12) block 2 start_pc=0 v13 Imm(0) -> x1 - v14 Imm(0) -> x0 + v14 Imm(0) -> x2 terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 Phi { incoming=[b2:v13, b4:v20], kind=I64 } -> x1 - v16 LoadLocal { off=-3, kind=I64 } -> x0 - v17 LoadLocal { off=-1, kind=I64 } -> x0 - v18 Binop { op=ult, lhs=v15, rhs=v1 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v15 LoadLocal { off=-3, kind=I64 } -> x1 + v16 LoadLocal { off=-1, kind=I64 } -> x1 + v17 Imm(1) -> x1 + v18 LoadLocal { off=-2, kind=I64 } -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x1 + v20 BinopI { op=add, lhs=v8, rhs_imm=0 } -> x1 + v21 Imm(4096) -> x2 + v22 Imm(0) -> x2 + v23 Imm(1) -> x2 + v24 Imm(72057594037927936) -> x2 + v25 Imm(1) -> x2 + v26 Store { addr=v20, disp=0, value=v25, kind=I8 } -> - + v27 LoadLocal { off=-3, kind=I64 } -> x1 + v28 Imm(4096) -> x1 + v29 Imm(0) -> x1 + v30 LoadLocal { off=-3, kind=I64 } -> x1 + v31 LoadLocal { off=-1, kind=I64 } -> x1 + v32 Imm(1) -> x1 + v33 LoadLocal { off=-2, kind=I64 } -> x1 + v34 LoadLocal { off=-3, kind=I64 } -> x1 + v35 BinopI { op=add, lhs=v8, rhs_imm=4096 } -> x1 + v36 Imm(4096) -> x2 + v37 Imm(1) -> x2 + v38 Imm(2) -> x2 + v39 Imm(144115188075855872) -> x2 + v40 Imm(2) -> x2 + v41 Store { addr=v35, disp=0, value=v40, kind=I8 } -> - + v42 LoadLocal { off=-3, kind=I64 } -> x1 + v43 Imm(8192) -> x1 + v44 Imm(0) -> x1 + v45 LoadLocal { off=-3, kind=I64 } -> x1 + v46 LoadLocal { off=-1, kind=I64 } -> x1 + v47 Imm(1) -> x1 + v48 LoadLocal { off=-2, kind=I64 } -> x1 + v49 LoadLocal { off=-3, kind=I64 } -> x1 + v50 BinopI { op=add, lhs=v8, rhs_imm=8192 } -> x1 + v51 Imm(4096) -> x2 + v52 Imm(2) -> x2 + v53 Imm(3) -> x2 + v54 Imm(216172782113783808) -> x2 + v55 Imm(3) -> x2 + v56 Store { addr=v50, disp=0, value=v55, kind=I8 } -> - + v57 LoadLocal { off=-3, kind=I64 } -> x1 + v58 Imm(12288) -> x1 + v59 Imm(0) -> x1 + v60 LoadLocal { off=-3, kind=I64 } -> x1 + v61 LoadLocal { off=-1, kind=I64 } -> x1 + v62 Imm(1) -> x1 + v63 LoadLocal { off=-2, kind=I64 } -> x1 + v64 LoadLocal { off=-3, kind=I64 } -> x1 + v65 BinopI { op=add, lhs=v8, rhs_imm=12288 } -> x1 + v66 Imm(4096) -> x2 + v67 Imm(3) -> x2 + v68 Imm(4) -> x2 + v69 Imm(288230376151711744) -> x2 + v70 Imm(4) -> x2 + v71 Store { addr=v65, disp=0, value=v70, kind=I8 } -> - + v72 LoadLocal { off=-3, kind=I64 } -> x1 + v73 Imm(16384) -> x1 + v74 Imm(0) -> x1 + v75 LoadLocal { off=-3, kind=I64 } -> x1 + v76 LoadLocal { off=-1, kind=I64 } -> x1 + v77 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v77) block 4 start_pc=0 - v19 LoadLocal { off=-3, kind=I64 } -> x0 - v20 BinopI { op=add, lhs=v15, rhs_imm=4096 } -> x1 - v21 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v20) + v78 Imm(0) -> x2 + v79 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v78) block 5 start_pc=0 - v22 LoadLocal { off=-2, kind=I64 } -> x0 - v23 LoadLocal { off=-3, kind=I64 } -> x0 - v24 Binop { op=add, lhs=v8, rhs=v15 } -> x0 - v25 Imm(4096) -> x2 - v26 BinopI { op=shru, lhs=v15, rhs_imm=12 } -> x2 - v27 BinopI { op=add, lhs=v26, rhs_imm=1 } -> x2 - v28 BinopI { op=shl, lhs=v27, rhs_imm=56 } -> x6 - v29 Extend { value=v27, kind=I8 } -> x6 - v30 Store { addr=v24, disp=0, value=v27, kind=I8 } -> - - terminator Jmp(b4) (exit_acc=v30) + v87 LoadLocal { off=-2, kind=I64 } -> x1 + v88 LoadLocal { off=-4, kind=I64 } -> x1 + v89 Binop { op=add, lhs=v8, rhs=v80 } -> x1 + v90 Load { addr=v89, disp=0, kind=I8 } -> x1 + v91 Imm(4096) -> x6 + v92 BinopI { op=shru, lhs=v80, rhs_imm=12 } -> x6 + v93 BinopI { op=add, lhs=v92, rhs_imm=1 } -> x6 + v94 BinopI { op=shl, lhs=v93, rhs_imm=56 } -> x7 + v95 Extend { value=v93, kind=I8 } -> x6 + v96 Binop { op=ne, lhs=v90, rhs=v95 } -> x1 + terminator Bnz { cond=v96, target=b11, fall=b6 } (exit_acc=v96) block 6 start_pc=0 - v31 Imm(0) -> x13 - v32 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v31) + v84 LoadLocal { off=-4, kind=I64 } -> x1 + v85 BinopI { op=add, lhs=v80, rhs_imm=4096 } -> x2 + v86 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v85) block 7 start_pc=0 - v33 Phi { incoming=[b6:v31, b8:v38], kind=I64 } -> x13 - v34 LoadLocal { off=-4, kind=I64 } -> x0 - v35 LoadLocal { off=-1, kind=I64 } -> x0 - v36 Binop { op=ult, lhs=v33, rhs=v1 } -> x0 - terminator Bz { cond=v36, target=b10, fall=b9 } (exit_acc=v36) + v80 Phi { incoming=[b4:v78, b6:v85], kind=I64 } -> x2 + v81 LoadLocal { off=-4, kind=I64 } -> x1 + v82 LoadLocal { off=-1, kind=I64 } -> x1 + v83 Binop { op=ult, lhs=v80, rhs=v1 } -> x1 + terminator Bnz { cond=v83, target=b5, fall=b8 } (exit_acc=v83) block 8 start_pc=0 - v37 LoadLocal { off=-4, kind=I64 } -> x0 - v38 BinopI { op=add, lhs=v33, rhs_imm=4096 } -> x13 - v39 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v38) + v97 LoadLocal { off=-2, kind=I64 } -> x1 + v98 LoadLocal { off=-1, kind=I64 } -> x1 + v99 CallExt { binding_idx=55, args=[v8, v1], fp_arg_mask=0x0 } -> x0 + v100 BinopI { op=ne, lhs=v99, rhs_imm=0 } -> x0 + terminator Bz { cond=v100, target=b10, fall=b9 } (exit_acc=v100) block 9 start_pc=0 - v40 LoadLocal { off=-2, kind=I64 } -> x0 - v41 LoadLocal { off=-4, kind=I64 } -> x0 - v42 Binop { op=add, lhs=v8, rhs=v33 } -> x0 - v43 Load { addr=v42, disp=0, kind=I8 } -> x0 - v44 Imm(4096) -> x1 - v45 BinopI { op=shru, lhs=v33, rhs_imm=12 } -> x1 - v46 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x1 - v47 BinopI { op=shl, lhs=v46, rhs_imm=56 } -> x2 - v48 Extend { value=v46, kind=I8 } -> x1 - v49 Binop { op=ne, lhs=v43, rhs=v48 } -> x0 - terminator Bz { cond=v49, target=b12, fall=b11 } (exit_acc=v49) + v102 Imm(3) -> x0 + terminator Return(v102) (exit_acc=v102) block 10 start_pc=0 - v50 LoadLocal { off=-2, kind=I64 } -> x0 - v51 LoadLocal { off=-1, kind=I64 } -> x0 - v52 CallExt { binding_idx=55, args=[v8, v1], fp_arg_mask=0x0 } -> x0 - v53 BinopI { op=ne, lhs=v52, rhs_imm=0 } -> x0 - terminator Bz { cond=v53, target=b14, fall=b13 } (exit_acc=v53) + v103 Imm(0) -> x0 + terminator Return(v103) (exit_acc=v103) block 11 start_pc=0 - v54 Imm(2) -> x0 - terminator Return(v54) (exit_acc=v54) + v101 Imm(2) -> x0 + terminator Return(v101) (exit_acc=v101) block 12 start_pc=0 - terminator Jmp(b8) - block 13 start_pc=0 - v55 Imm(3) -> x0 - terminator Return(v55) (exit_acc=v55) - block 14 start_pc=0 - v56 Imm(0) -> x0 - terminator Return(v56) (exit_acc=v56) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/msvc_callconv.ssa b/tests/snapshots/ssa/msvc_callconv.ssa index 9738ccfd0..484ecd486 100644 --- a/tests/snapshots/ssa/msvc_callconv.ssa +++ b/tests/snapshots/ssa/msvc_callconv.ssa @@ -79,26 +79,26 @@ fn ent_pc=4 n_params=0 variadic=false locals=7 v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x1 v10 Extend { value=v8, kind=I32 } -> x1 v11 Imm(1) -> x1 - v12 Extend { value=v11, kind=I32 } -> x2 - v13 Imm(0) -> x2 - v14 Extend { value=v11, kind=I32 } -> x2 - v15 Imm(0) -> x2 - v16 Binop { op=add, lhs=v11, rhs=v11 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x2 - v18 Extend { value=v16, kind=I32 } -> x2 - v19 Binop { op=add, lhs=v8, rhs=v16 } -> x0 + v12 Imm(1) -> x1 + v13 Imm(0) -> x1 + v14 Imm(1) -> x1 + v15 Imm(0) -> x1 + v16 Imm(2) -> x1 + v17 Imm(8589934592) -> x1 + v18 Imm(2) -> x1 + v19 BinopI { op=add, lhs=v8, rhs_imm=2 } -> x0 v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x1 v21 Extend { value=v19, kind=I32 } -> x1 v22 Imm(3) -> x1 - v23 Imm(4) -> x2 - v24 Extend { value=v22, kind=I32 } -> x6 - v25 Imm(0) -> x6 - v26 Extend { value=v23, kind=I32 } -> x6 - v27 Imm(0) -> x6 - v28 Binop { op=add, lhs=v22, rhs=v23 } -> x1 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x2 - v30 Extend { value=v28, kind=I32 } -> x2 - v31 Binop { op=add, lhs=v19, rhs=v28 } -> x0 + v23 Imm(4) -> x1 + v24 Imm(3) -> x1 + v25 Imm(0) -> x1 + v26 Imm(4) -> x1 + v27 Imm(0) -> x1 + v28 Imm(7) -> x1 + v29 Imm(30064771072) -> x1 + v30 Imm(7) -> x1 + v31 BinopI { op=add, lhs=v19, rhs_imm=7 } -> x0 v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x1 v33 Extend { value=v31, kind=I32 } -> x12 v34 Imm(0) -> x0 @@ -119,19 +119,19 @@ fn ent_pc=4 n_params=0 variadic=false locals=7 block 2 start_pc=0 v46 Phi { incoming=[b6:v40, b1:v44], kind=I64 } -> x1 v47 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v46, target=b4, fall=b3 } (exit_acc=v46) + terminator Bz { cond=v46, target=b5, fall=b3 } (exit_acc=v46) block 3 start_pc=0 v48 Imm(0) -> x1 v49 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v48) + terminator Jmp(b4) (exit_acc=v48) block 4 start_pc=0 - v50 Imm(1) -> x1 - v51 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v50) - block 5 start_pc=0 - v52 Phi { incoming=[b3:v48, b4:v50], kind=I64 } -> x1 + v52 Phi { incoming=[b3:v48, b5:v50], kind=I64 } -> x1 v53 LoadLocal { off=-7, kind=I64 } -> x0 terminator Return(v52) (exit_acc=v52) + block 5 start_pc=0 + v50 Imm(1) -> x1 + v51 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v50) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/msvc_decl_decorators.ssa b/tests/snapshots/ssa/msvc_decl_decorators.ssa index 3a3c61957..66eee995c 100644 --- a/tests/snapshots/ssa/msvc_decl_decorators.ssa +++ b/tests/snapshots/ssa/msvc_decl_decorators.ssa @@ -28,11 +28,11 @@ fn ent_pc=7 n_params=0 variadic=false locals=0 terminator Jmp(b1) (exit_acc=v0) block 1 start_pc=0 v1 Imm(1) -> x0 - terminator Jmp(b3) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 2 start_pc=0 terminator Jmp(b1) block 3 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b1) block 4 start_pc=0 v2 Imm(0) -> x0 terminator Return(v2) (exit_acc=v2) @@ -50,29 +50,29 @@ fn ent_pc=8 n_params=0 variadic=false locals=1 v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x2 v7 Extend { value=v5, kind=I32 } -> x2 v8 Imm(3) -> x2 - v9 Binop { op=add, lhs=v5, rhs=v8 } -> x1 + v9 BinopI { op=add, lhs=v5, rhs_imm=3 } -> x1 v10 BinopI { op=shl, lhs=v9, rhs_imm=32 } -> x2 v11 Extend { value=v9, kind=I32 } -> x2 v12 Store { addr=v1, disp=0, value=v9, kind=I32 } -> - v13 Extend { value=v9, kind=I32 } -> x0 v14 BinopI { op=ne, lhs=v13, rhs_imm=11 } -> x0 - terminator Bz { cond=v14, target=b3, fall=b1 } (exit_acc=v14) + terminator Bz { cond=v14, target=b2, fall=b1 } (exit_acc=v14) block 1 start_pc=0 - terminator Jmp(b4) + v16 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v16) block 2 start_pc=0 - terminator Jmp(b3) (exit_acc=v17) - block 3 start_pc=0 v15 Imm(0) -> x0 terminator Return(v15) (exit_acc=v15) + block 3 start_pc=0 + terminator Jmp(b1) block 4 start_pc=0 - terminator Jmp(b5) + terminator Jmp(b2) (exit_acc=v17) block 5 start_pc=0 - v16 Imm(1) -> x0 - terminator Jmp(b7) (exit_acc=v16) + terminator Jmp(b1) block 6 start_pc=0 - terminator Jmp(b5) + terminator Jmp(b1) block 7 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b1) block 8 start_pc=0 v17 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v17) diff --git a/tests/snapshots/ssa/msvc_pragma_operator.ssa b/tests/snapshots/ssa/msvc_pragma_operator.ssa index 5b611e320..5c33364e6 100644 --- a/tests/snapshots/ssa/msvc_pragma_operator.ssa +++ b/tests/snapshots/ssa/msvc_pragma_operator.ssa @@ -5,25 +5,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Return(v7) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 5 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 6 start_pc=0 v6 Imm(3) -> x0 terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/mul_pow2_to_shift.ssa b/tests/snapshots/ssa/mul_pow2_to_shift.ssa index 70d292f4b..1081bacd3 100644 --- a/tests/snapshots/ssa/mul_pow2_to_shift.ssa +++ b/tests/snapshots/ssa/mul_pow2_to_shift.ssa @@ -1,94 +1,94 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=17 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x1 - v4 Imm(0) -> x1 - v5 Imm(0) -> x1 - v6 LoadLocal { off=-1, kind=I32 } -> x1 - v7 BinopI { op=shl, lhs=v1, rhs_imm=1 } -> x1 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x2 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 Imm(0) -> x2 - v11 BinopI { op=shl, lhs=v1, rhs_imm=2 } -> x2 - v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x6 - v13 Extend { value=v11, kind=I32 } -> x6 - v14 Imm(0) -> x6 - v15 BinopI { op=shl, lhs=v1, rhs_imm=3 } -> x6 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x7 - v17 Extend { value=v15, kind=I32 } -> x7 - v18 Imm(0) -> x7 - v19 BinopI { op=shl, lhs=v1, rhs_imm=4 } -> x7 - v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x8 - v21 Extend { value=v19, kind=I32 } -> x8 - v22 Imm(0) -> x8 - v23 BinopI { op=shl, lhs=v1, rhs_imm=10 } -> x8 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x9 - v25 Extend { value=v23, kind=I32 } -> x9 - v26 Imm(0) -> x9 - v27 LoadLocal { off=-2, kind=U32 } -> x9 - v28 BinopI { op=shl, lhs=v1, rhs_imm=1 } -> x9 - v29 BinopI { op=and, lhs=v28, rhs_imm=4294967295 } -> x9 - v30 Imm(0) -> x3 - v31 BinopI { op=shl, lhs=v1, rhs_imm=8 } -> x3 - v32 BinopI { op=and, lhs=v31, rhs_imm=4294967295 } -> x3 - v33 Imm(0) -> x12 - v34 LoadLocal { off=-3, kind=I64 } -> x12 - v35 BinopI { op=shl, lhs=v1, rhs_imm=5 } -> x12 - v36 Imm(0) -> x13 - v37 LoadLocal { off=-4, kind=I64 } -> x13 - v38 BinopI { op=shl, lhs=v1, rhs_imm=16 } -> x0 - v39 Imm(0) -> x13 - v40 LoadLocal { off=-5, kind=I32 } -> x13 - v41 LoadLocal { off=-6, kind=I32 } -> x13 - v42 Binop { op=add, lhs=v7, rhs=v11 } -> x1 - v43 BinopI { op=shl, lhs=v42, rhs_imm=32 } -> x2 - v44 Extend { value=v42, kind=I32 } -> x2 - v45 LoadLocal { off=-7, kind=I32 } -> x2 - v46 Binop { op=add, lhs=v42, rhs=v15 } -> x1 - v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x2 - v48 Extend { value=v46, kind=I32 } -> x2 - v49 LoadLocal { off=-8, kind=I32 } -> x2 - v50 Binop { op=add, lhs=v46, rhs=v19 } -> x1 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x2 - v52 Extend { value=v50, kind=I32 } -> x2 - v53 LoadLocal { off=-9, kind=I32 } -> x2 - v54 Binop { op=add, lhs=v50, rhs=v23 } -> x1 - v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x2 - v56 Extend { value=v54, kind=I32 } -> x1 - v57 BinopI { op=and, lhs=v29, rhs_imm=4294967295 } -> x2 - v58 Binop { op=add, lhs=v56, rhs=v57 } -> x1 - v59 BinopI { op=and, lhs=v58, rhs_imm=4294967295 } -> x1 - v60 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x2 - v61 Binop { op=add, lhs=v59, rhs=v60 } -> x1 - v62 BinopI { op=and, lhs=v61, rhs_imm=4294967295 } -> x1 - v63 LoadLocal { off=-12, kind=I64 } -> x2 - v64 Binop { op=add, lhs=v62, rhs=v35 } -> x1 - v65 LoadLocal { off=-13, kind=I64 } -> x2 - v66 Binop { op=add, lhs=v64, rhs=v38 } -> x3 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-1, kind=I32 } -> x0 + v7 Imm(14) -> x0 + v8 Imm(60129542144) -> x0 + v9 Imm(14) -> x0 + v10 Imm(0) -> x0 + v11 Imm(28) -> x0 + v12 Imm(120259084288) -> x0 + v13 Imm(28) -> x0 + v14 Imm(0) -> x0 + v15 Imm(56) -> x0 + v16 Imm(240518168576) -> x0 + v17 Imm(56) -> x0 + v18 Imm(0) -> x0 + v19 Imm(112) -> x0 + v20 Imm(481036337152) -> x0 + v21 Imm(112) -> x0 + v22 Imm(0) -> x0 + v23 Imm(7168) -> x0 + v24 Imm(30786325577728) -> x0 + v25 Imm(7168) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-2, kind=U32 } -> x0 + v28 Imm(14) -> x0 + v29 Imm(14) -> x0 + v30 Imm(0) -> x0 + v31 Imm(1792) -> x0 + v32 Imm(1792) -> x0 + v33 Imm(0) -> x0 + v34 LoadLocal { off=-3, kind=I64 } -> x0 + v35 Imm(224) -> x0 + v36 Imm(0) -> x0 + v37 LoadLocal { off=-4, kind=I64 } -> x0 + v38 Imm(458752) -> x0 + v39 Imm(0) -> x0 + v40 LoadLocal { off=-5, kind=I32 } -> x0 + v41 LoadLocal { off=-6, kind=I32 } -> x0 + v42 Imm(42) -> x0 + v43 Imm(180388626432) -> x0 + v44 Imm(42) -> x0 + v45 LoadLocal { off=-7, kind=I32 } -> x0 + v46 Imm(98) -> x0 + v47 Imm(420906795008) -> x0 + v48 Imm(98) -> x0 + v49 LoadLocal { off=-8, kind=I32 } -> x0 + v50 Imm(210) -> x0 + v51 Imm(901943132160) -> x0 + v52 Imm(210) -> x0 + v53 LoadLocal { off=-9, kind=I32 } -> x0 + v54 Imm(7378) -> x0 + v55 Imm(31688268709888) -> x0 + v56 Imm(7378) -> x0 + v57 Imm(14) -> x0 + v58 Imm(7392) -> x0 + v59 Imm(7392) -> x0 + v60 Imm(1792) -> x0 + v61 Imm(9184) -> x0 + v62 Imm(9184) -> x0 + v63 LoadLocal { off=-12, kind=I64 } -> x0 + v64 Imm(9408) -> x0 + v65 LoadLocal { off=-13, kind=I64 } -> x0 + v66 Imm(468160) -> x6 v67 Imm(0) -> x0 v68 ImmData(36) -> x7 v69 LoadLocal { off=-14, kind=I64 } -> x0 v70 CallExt { binding_idx=0, args=[v68, v66], fp_arg_mask=0x0 } -> x0 v71 LoadLocal { off=-14, kind=I64 } -> x0 - v72 BinopI { op=eq, lhs=v66, rhs_imm=468160 } -> x0 - terminator Bz { cond=v72, target=b2, fall=b1 } (exit_acc=v72) + v72 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v72) block 1 start_pc=0 v73 Imm(0) -> x1 v74 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v73) + terminator Jmp(b2) (exit_acc=v73) block 2 start_pc=0 - v75 Imm(1) -> x1 - v76 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v75) - block 3 start_pc=0 - v77 Phi { incoming=[b1:v73, b2:v75], kind=I64 } -> x1 + v77 Phi { incoming=[b1:v73, b3:v75], kind=I64 } -> x1 v78 LoadLocal { off=-17, kind=I64 } -> x0 terminator Return(v77) (exit_acc=v77) + block 3 start_pc=0 + v75 Imm(1) -> x1 + v76 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v75) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/multi_declarator_prototypes.ssa b/tests/snapshots/ssa/multi_declarator_prototypes.ssa index 91b150ff3..c63204bdd 100644 --- a/tests/snapshots/ssa/multi_declarator_prototypes.ssa +++ b/tests/snapshots/ssa/multi_declarator_prototypes.ssa @@ -31,36 +31,36 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 v2 Imm(10) -> x1 v3 Store { addr=v1, disp=0, value=v2, kind=I32 } -> - v4 Imm(3) -> x1 - v5 Extend { value=v4, kind=I32 } -> x1 - v6 Imm(0) -> x2 - v7 BinopI { op=ne, lhs=v5, rhs_imm=3 } -> x1 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Imm(3) -> x1 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 Imm(3) -> x1 - v10 Extend { value=v9, kind=I32 } -> x2 - v11 Imm(0) -> x2 - v12 BinopI { op=shl, lhs=v9, rhs_imm=1 } -> x1 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x2 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 BinopI { op=ne, lhs=v14, rhs_imm=6 } -> x1 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) - block 4 start_pc=0 + v10 Imm(3) -> x1 + v11 Imm(0) -> x1 + v12 Imm(6) -> x1 + v13 Imm(25769803776) -> x1 + v14 Imm(6) -> x1 + v15 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v15) + block 2 start_pc=0 v17 ImmData(24) -> x1 v18 Load { addr=v1, disp=0, kind=I32 } -> x0 v19 BinopI { op=ne, lhs=v18, rhs_imm=10 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) - block 5 start_pc=0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) + block 3 start_pc=0 v20 Imm(3) -> x0 terminator Return(v20) (exit_acc=v20) - block 6 start_pc=0 + block 4 start_pc=0 v21 Imm(0) -> x0 terminator Return(v21) (exit_acc=v21) + block 5 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) + block 6 start_pc=0 + v16 Imm(2) -> x0 + terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/multichar_constant.ssa b/tests/snapshots/ssa/multichar_constant.ssa index 928f02918..74c1a70de 100644 --- a/tests/snapshots/ssa/multichar_constant.ssa +++ b/tests/snapshots/ssa/multichar_constant.ssa @@ -8,67 +8,67 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v2 Imm(16640) -> x0 v3 Imm(71468255805440) -> x0 v4 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v4) + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v6) - block 3 start_pc=0 - v7 Imm(2) -> x0 - terminator Return(v7) (exit_acc=v7) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v6) + block 2 start_pc=0 v8 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v8) - block 5 start_pc=0 - v9 Imm(3) -> x0 - terminator Return(v9) (exit_acc=v9) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v8) + block 3 start_pc=0 v10 Imm(0) -> x0 v11 Imm(1) -> x2 v12 Imm(0) -> x1 - terminator Jmp(b7) (exit_acc=v10) - block 7 start_pc=0 + terminator Jmp(b4) (exit_acc=v10) + block 4 start_pc=0 v13 Imm(0) -> x2 v14 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v13) - block 8 start_pc=0 - v15 Phi { incoming=[b6:v11, b7:v13], kind=I64 } -> x2 + terminator Jmp(b5) (exit_acc=v13) + block 5 start_pc=0 + v15 Phi { incoming=[b3:v11, b4:v13], kind=I64 } -> x2 v16 LoadLocal { off=-2, kind=I64 } -> x0 v17 Imm(0) -> x0 - terminator Bnz { cond=v15, target=b17, fall=b9 } (exit_acc=v15) - block 9 start_pc=0 + terminator Bnz { cond=v15, target=b12, fall=b6 } (exit_acc=v15) + block 6 start_pc=0 v18 Imm(0) -> x2 v19 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v18) - block 10 start_pc=0 - v20 Phi { incoming=[b17:v15, b9:v18], kind=I64 } -> x2 + terminator Jmp(b7) (exit_acc=v18) + block 7 start_pc=0 + v20 Phi { incoming=[b12:v15, b6:v18], kind=I64 } -> x2 v21 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v20, target=b12, fall=b11 } (exit_acc=v20) - block 11 start_pc=0 + terminator Bz { cond=v20, target=b9, fall=b8 } (exit_acc=v20) + block 8 start_pc=0 v22 Imm(4) -> x0 terminator Return(v22) (exit_acc=v22) - block 12 start_pc=0 + block 9 start_pc=0 v23 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v23) - block 13 start_pc=0 - v24 Imm(5) -> x0 - terminator Return(v24) (exit_acc=v24) - block 14 start_pc=0 + terminator Jmp(b10) (exit_acc=v23) + block 10 start_pc=0 v25 Imm(16706) -> x0 v26 Imm(16640) -> x0 v27 Imm(71468255805440) -> x0 v28 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v28) - block 15 start_pc=0 - v29 Imm(6) -> x0 - terminator Return(v29) (exit_acc=v29) - block 16 start_pc=0 + terminator Jmp(b11) (exit_acc=v28) + block 11 start_pc=0 v30 Imm(0) -> x0 terminator Return(v30) (exit_acc=v30) + block 12 start_pc=0 + terminator Jmp(b7) + block 13 start_pc=0 + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) + block 14 start_pc=0 + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) + block 15 start_pc=0 + v9 Imm(3) -> x0 + terminator Return(v9) (exit_acc=v9) + block 16 start_pc=0 + v24 Imm(5) -> x0 + terminator Return(v24) (exit_acc=v24) block 17 start_pc=0 - terminator Jmp(b10) + v29 Imm(6) -> x0 + terminator Return(v29) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/multidim_array_init.ssa b/tests/snapshots/ssa/multidim_array_init.ssa index dd238562b..9abfc51b7 100644 --- a/tests/snapshots/ssa/multidim_array_init.ssa +++ b/tests/snapshots/ssa/multidim_array_init.ssa @@ -11,22 +11,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v5 Imm(128849018880) -> x0 v6 Imm(515396075520) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v7) + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 ImmData(8) -> x0 v10 Imm(0) -> x1 v11 Imm(16) -> x1 v12 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x1 v13 Load { addr=v9, disp=16, kind=I32 } -> x0 v14 BinopI { op=ne, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 3 start_pc=0 + terminator Bz { cond=v14, target=b3, fall=b2 } (exit_acc=v14) + block 2 start_pc=0 v15 Imm(2) -> x0 terminator Return(v15) (exit_acc=v15) - block 4 start_pc=0 + block 3 start_pc=0 v16 ImmData(8) -> x0 v17 Imm(0) -> x1 v18 Imm(20) -> x1 @@ -35,8 +32,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v21 BinopI { op=ne, lhs=v20, rhs_imm=1 } -> x0 v22 Imm(1) -> x2 v23 Imm(0) -> x1 - terminator Bnz { cond=v21, target=b37, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bnz { cond=v21, target=b42, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v24 ImmData(8) -> x0 v25 Imm(0) -> x1 v26 Imm(20) -> x1 @@ -47,13 +44,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v31 BinopI { op=ne, lhs=v30, rhs_imm=6 } -> x0 v32 BinopI { op=ne, lhs=v31, rhs_imm=0 } -> x2 v33 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v32) - block 6 start_pc=0 - v34 Phi { incoming=[b37:v22, b5:v32], kind=I64 } -> x2 + terminator Jmp(b5) (exit_acc=v32) + block 5 start_pc=0 + v34 Phi { incoming=[b42:v22, b4:v32], kind=I64 } -> x2 v35 LoadLocal { off=-2, kind=I64 } -> x0 v36 Imm(0) -> x0 - terminator Bnz { cond=v34, target=b38, fall=b7 } (exit_acc=v34) - block 7 start_pc=0 + terminator Bnz { cond=v34, target=b41, fall=b6 } (exit_acc=v34) + block 6 start_pc=0 v37 ImmData(8) -> x0 v38 Imm(0) -> x1 v39 Imm(20) -> x1 @@ -63,26 +60,26 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v43 Load { addr=v37, disp=36, kind=I32 } -> x0 v44 BinopI { op=ne, lhs=v43, rhs_imm=7 } -> x2 v45 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v44) - block 8 start_pc=0 - v46 Phi { incoming=[b38:v34, b7:v44], kind=I64 } -> x2 + terminator Jmp(b7) (exit_acc=v44) + block 7 start_pc=0 + v46 Phi { incoming=[b41:v34, b6:v44], kind=I64 } -> x2 v47 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v46, target=b10, fall=b9 } (exit_acc=v46) - block 9 start_pc=0 + terminator Bz { cond=v46, target=b9, fall=b8 } (exit_acc=v46) + block 8 start_pc=0 v48 Imm(3) -> x0 terminator Return(v48) (exit_acc=v48) - block 10 start_pc=0 + block 9 start_pc=0 v49 ImmData(8) -> x0 v50 Imm(0) -> x1 v51 Imm(40) -> x1 v52 BinopI { op=add, lhs=v49, rhs_imm=40 } -> x1 v53 Load { addr=v49, disp=40, kind=I32 } -> x0 v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x0 - terminator Bz { cond=v54, target=b12, fall=b11 } (exit_acc=v54) - block 11 start_pc=0 + terminator Bz { cond=v54, target=b11, fall=b10 } (exit_acc=v54) + block 10 start_pc=0 v55 Imm(4) -> x0 terminator Return(v55) (exit_acc=v55) - block 12 start_pc=0 + block 11 start_pc=0 v56 ImmData(8) -> x0 v57 Imm(60) -> x1 v58 BinopI { op=add, lhs=v56, rhs_imm=60 } -> x1 @@ -90,8 +87,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v60 Load { addr=v56, disp=60, kind=I32 } -> x0 v61 BinopI { op=ne, lhs=v60, rhs_imm=1 } -> x1 v62 Imm(0) -> x0 - terminator Bnz { cond=v61, target=b39, fall=b13 } (exit_acc=v61) - block 13 start_pc=0 + terminator Bnz { cond=v61, target=b40, fall=b12 } (exit_acc=v61) + block 12 start_pc=0 v63 ImmData(8) -> x0 v64 Imm(60) -> x1 v65 BinopI { op=add, lhs=v63, rhs_imm=60 } -> x1 @@ -101,15 +98,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v69 Load { addr=v63, disp=64, kind=I32 } -> x0 v70 BinopI { op=ne, lhs=v69, rhs_imm=2 } -> x1 v71 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v70) - block 14 start_pc=0 - v72 Phi { incoming=[b39:v61, b13:v70], kind=I64 } -> x1 + terminator Jmp(b13) (exit_acc=v70) + block 13 start_pc=0 + v72 Phi { incoming=[b40:v61, b12:v70], kind=I64 } -> x1 v73 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v72, target=b16, fall=b15 } (exit_acc=v72) - block 15 start_pc=0 + terminator Bz { cond=v72, target=b15, fall=b14 } (exit_acc=v72) + block 14 start_pc=0 v74 Imm(5) -> x0 terminator Return(v74) (exit_acc=v74) - block 16 start_pc=0 + block 15 start_pc=0 v75 ImmData(8) -> x0 v76 Imm(60) -> x1 v77 BinopI { op=add, lhs=v75, rhs_imm=60 } -> x1 @@ -120,8 +117,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v82 Load { addr=v75, disp=96, kind=I32 } -> x0 v83 BinopI { op=ne, lhs=v82, rhs_imm=7 } -> x1 v84 Imm(0) -> x0 - terminator Bnz { cond=v83, target=b40, fall=b17 } (exit_acc=v83) - block 17 start_pc=0 + terminator Bnz { cond=v83, target=b39, fall=b16 } (exit_acc=v83) + block 16 start_pc=0 v85 ImmData(8) -> x0 v86 Imm(60) -> x1 v87 BinopI { op=add, lhs=v85, rhs_imm=60 } -> x1 @@ -131,15 +128,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v91 Load { addr=v85, disp=80, kind=I32 } -> x0 v92 BinopI { op=ne, lhs=v91, rhs_imm=0 } -> x1 v93 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v92) - block 18 start_pc=0 - v94 Phi { incoming=[b40:v83, b17:v92], kind=I64 } -> x1 + terminator Jmp(b17) (exit_acc=v92) + block 17 start_pc=0 + v94 Phi { incoming=[b39:v83, b16:v92], kind=I64 } -> x1 v95 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v94, target=b20, fall=b19 } (exit_acc=v94) - block 19 start_pc=0 + terminator Bz { cond=v94, target=b19, fall=b18 } (exit_acc=v94) + block 18 start_pc=0 v96 Imm(6) -> x0 terminator Return(v96) (exit_acc=v96) - block 20 start_pc=0 + block 19 start_pc=0 v97 ImmData(128) -> x0 v98 Imm(0) -> x1 v99 Imm(20) -> x1 @@ -152,11 +149,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v106 BinopI { op=add, lhs=v104, rhs_imm=36 } -> x2 v107 Load { addr=v104, disp=36, kind=I32 } -> x1 v108 Binop { op=ne, lhs=v103, rhs=v107 } -> x0 - terminator Bz { cond=v108, target=b22, fall=b21 } (exit_acc=v108) - block 21 start_pc=0 + terminator Bz { cond=v108, target=b21, fall=b20 } (exit_acc=v108) + block 20 start_pc=0 v109 Imm(7) -> x0 terminator Return(v109) (exit_acc=v109) - block 22 start_pc=0 + block 21 start_pc=0 v110 ImmData(128) -> x0 v111 Imm(60) -> x1 v112 BinopI { op=add, lhs=v110, rhs_imm=60 } -> x1 @@ -171,19 +168,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v121 BinopI { op=add, lhs=v118, rhs_imm=96 } -> x2 v122 Load { addr=v118, disp=96, kind=I32 } -> x1 v123 Binop { op=ne, lhs=v117, rhs=v122 } -> x0 - terminator Bz { cond=v123, target=b24, fall=b23 } (exit_acc=v123) - block 23 start_pc=0 + terminator Bz { cond=v123, target=b23, fall=b22 } (exit_acc=v123) + block 22 start_pc=0 v124 Imm(8) -> x0 terminator Return(v124) (exit_acc=v124) - block 24 start_pc=0 + block 23 start_pc=0 v125 ImmData(248) -> x0 v126 Imm(0) -> x1 v127 Load { addr=v125, disp=0, kind=I32 } -> x0 v128 BinopI { op=ne, lhs=v127, rhs_imm=1 } -> x0 v129 Imm(1) -> x2 v130 Imm(0) -> x1 - terminator Bnz { cond=v128, target=b41, fall=b25 } (exit_acc=v128) - block 25 start_pc=0 + terminator Bnz { cond=v128, target=b38, fall=b24 } (exit_acc=v128) + block 24 start_pc=0 v131 ImmData(248) -> x0 v132 Imm(0) -> x1 v133 Imm(4) -> x1 @@ -192,13 +189,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v136 BinopI { op=ne, lhs=v135, rhs_imm=2 } -> x0 v137 BinopI { op=ne, lhs=v136, rhs_imm=0 } -> x2 v138 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v137) - block 26 start_pc=0 - v139 Phi { incoming=[b41:v129, b25:v137], kind=I64 } -> x2 + terminator Jmp(b25) (exit_acc=v137) + block 25 start_pc=0 + v139 Phi { incoming=[b38:v129, b24:v137], kind=I64 } -> x2 v140 LoadLocal { off=-6, kind=I64 } -> x0 v141 Imm(0) -> x0 - terminator Bnz { cond=v139, target=b42, fall=b27 } (exit_acc=v139) - block 27 start_pc=0 + terminator Bnz { cond=v139, target=b37, fall=b26 } (exit_acc=v139) + block 26 start_pc=0 v142 ImmData(248) -> x0 v143 Imm(0) -> x1 v144 Imm(12) -> x1 @@ -206,15 +203,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v146 Load { addr=v142, disp=12, kind=I32 } -> x0 v147 BinopI { op=ne, lhs=v146, rhs_imm=0 } -> x2 v148 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v147) - block 28 start_pc=0 - v149 Phi { incoming=[b42:v139, b27:v147], kind=I64 } -> x2 + terminator Jmp(b27) (exit_acc=v147) + block 27 start_pc=0 + v149 Phi { incoming=[b37:v139, b26:v147], kind=I64 } -> x2 v150 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v149, target=b30, fall=b29 } (exit_acc=v149) - block 29 start_pc=0 + terminator Bz { cond=v149, target=b29, fall=b28 } (exit_acc=v149) + block 28 start_pc=0 v151 Imm(9) -> x0 terminator Return(v151) (exit_acc=v151) - block 30 start_pc=0 + block 29 start_pc=0 v152 ImmData(248) -> x0 v153 Imm(16) -> x1 v154 BinopI { op=add, lhs=v152, rhs_imm=16 } -> x1 @@ -223,8 +220,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v157 Load { addr=v152, disp=24, kind=I32 } -> x0 v158 BinopI { op=ne, lhs=v157, rhs_imm=9 } -> x1 v159 Imm(0) -> x0 - terminator Bnz { cond=v158, target=b43, fall=b31 } (exit_acc=v158) - block 31 start_pc=0 + terminator Bnz { cond=v158, target=b36, fall=b30 } (exit_acc=v158) + block 30 start_pc=0 v160 ImmData(248) -> x0 v161 Imm(16) -> x1 v162 BinopI { op=add, lhs=v160, rhs_imm=16 } -> x1 @@ -232,42 +229,45 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v164 Load { addr=v160, disp=16, kind=I32 } -> x0 v165 BinopI { op=ne, lhs=v164, rhs_imm=0 } -> x1 v166 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v165) - block 32 start_pc=0 - v167 Phi { incoming=[b43:v158, b31:v165], kind=I64 } -> x1 + terminator Jmp(b31) (exit_acc=v165) + block 31 start_pc=0 + v167 Phi { incoming=[b36:v158, b30:v165], kind=I64 } -> x1 v168 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v167, target=b34, fall=b33 } (exit_acc=v167) - block 33 start_pc=0 + terminator Bz { cond=v167, target=b33, fall=b32 } (exit_acc=v167) + block 32 start_pc=0 v169 Imm(10) -> x0 terminator Return(v169) (exit_acc=v169) - block 34 start_pc=0 + block 33 start_pc=0 v170 ImmData(248) -> x0 v171 Imm(32) -> x1 v172 BinopI { op=add, lhs=v170, rhs_imm=32 } -> x1 v173 Imm(0) -> x1 v174 Load { addr=v170, disp=32, kind=I32 } -> x0 v175 BinopI { op=ne, lhs=v174, rhs_imm=0 } -> x0 - terminator Bz { cond=v175, target=b36, fall=b35 } (exit_acc=v175) - block 35 start_pc=0 + terminator Bz { cond=v175, target=b35, fall=b34 } (exit_acc=v175) + block 34 start_pc=0 v176 Imm(11) -> x0 terminator Return(v176) (exit_acc=v176) - block 36 start_pc=0 + block 35 start_pc=0 v177 Imm(0) -> x0 terminator Return(v177) (exit_acc=v177) + block 36 start_pc=0 + terminator Jmp(b31) block 37 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b27) block 38 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b25) block 39 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b17) block 40 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b13) block 41 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b7) block 42 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b5) block 43 start_pc=0 - terminator Jmp(b32) + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/narrow_param_entry_extend.ssa b/tests/snapshots/ssa/narrow_param_entry_extend.ssa new file mode 100644 index 000000000..7c55968b5 --- /dev/null +++ b/tests/snapshots/ssa/narrow_param_entry_extend.ssa @@ -0,0 +1,179 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=scale +fn ent_pc=0 n_params=3 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I8) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I16) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x2 + v6 Imm(0) -> x0 + v7 Imm(0) -> x1 + v8 StoreLocal { off=-1, value=v7, kind=I32, volatile } -> - + v9 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 1 start_pc=0 + v16 LoadLocal { off=-1, kind=I32, volatile } -> x8 + v17 Extend { value=v10, kind=I32 } -> x9 + v18 Binop { op=add, lhs=v16, rhs=v10 } -> x8 + v19 StoreLocal { off=-1, value=v18, kind=I32, volatile } -> - + v20 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x9 + v21 Extend { value=v18, kind=I32 } -> x8 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v13 Extend { value=v10, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v10 Phi { incoming=[b0:v7, b2:v14], kind=I64 } -> x1 + v11 Extend { value=v10, kind=I32 } -> x0 + v12 BinopI { op=lt, lhs=v11, rhs_imm=3 } -> x8 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) + block 4 start_pc=0 + v22 LoadLocal { off=-1, kind=I32, volatile } -> x0 + v23 BinopI { op=and, lhs=v22, rhs_imm=255 } -> x0 + v24 LoadLocal { off=2, kind=I8 } -> x0 + v25 BinopI { op=mul, lhs=v1, rhs_imm=100000 } -> x0 + v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x1 + v27 Extend { value=v25, kind=I32 } -> x1 + v28 LoadLocal { off=3, kind=I16 } -> x1 + v29 BinopI { op=mul, lhs=v3, rhs_imm=10 } -> x1 + v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x6 + v31 Extend { value=v29, kind=I32 } -> x6 + v32 Binop { op=add, lhs=v25, rhs=v29 } -> x0 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 + v34 Extend { value=v32, kind=I32 } -> x1 + v35 LoadLocal { off=4, kind=I32 } -> x1 + v36 Binop { op=add, lhs=v32, rhs=v5 } -> x0 + v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 + v38 Extend { value=v36, kind=I32 } -> x0 + terminator Return(v38) (exit_acc=v38) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=uscale +fn ent_pc=1 n_params=2 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 Imm(0) -> x1 + v6 StoreLocal { off=-1, value=v5, kind=I32, volatile } -> - + v7 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) + block 1 start_pc=0 + v14 LoadLocal { off=-1, kind=I32, volatile } -> x2 + v15 Extend { value=v8, kind=I32 } -> x8 + v16 Binop { op=add, lhs=v14, rhs=v8 } -> x2 + v17 StoreLocal { off=-1, value=v16, kind=I32, volatile } -> - + v18 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x8 + v19 Extend { value=v16, kind=I32 } -> x2 + terminator Jmp(b2) (exit_acc=v19) + block 2 start_pc=0 + v11 Extend { value=v8, kind=I32 } -> x1 + v12 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v13 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v5, b2:v12], kind=I64 } -> x1 + v9 Extend { value=v8, kind=I32 } -> x0 + v10 BinopI { op=lt, lhs=v9, rhs_imm=3 } -> x2 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) + block 4 start_pc=0 + v20 LoadLocal { off=-1, kind=I32, volatile } -> x0 + v21 BinopI { op=and, lhs=v20, rhs_imm=255 } -> x0 + v22 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 + v23 BinopI { op=mul, lhs=v22, rhs_imm=100000 } -> x0 + v24 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x0 + v25 BinopI { op=and, lhs=v3, rhs_imm=65535 } -> x1 + v26 Binop { op=add, lhs=v24, rhs=v25 } -> x0 + v27 BinopI { op=and, lhs=v26, rhs_imm=4294967295 } -> x0 + terminator Return(v27) (exit_acc=v27) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=4 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmData(8) -> x0 + v2 Load { addr=v1, disp=0, kind=I32, volatile } -> x3 + v3 Imm(0) -> x0 + v4 Extend { value=v2, kind=I32 } -> x0 + v5 Call { target_pc=0, args=[v2, v2, v2], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v6 Imm(6900000) -> x1 + v7 Imm(29635274342400000) -> x1 + v8 Imm(90290) -> x1 + v9 Imm(387792597155840) -> x1 + v10 Imm(6990290) -> x1 + v11 Imm(30023066939555840) -> x1 + v12 Imm(7064855) -> x1 + v13 Imm(30343321175982080) -> x1 + v14 BinopI { op=ne, lhs=v5, rhs_imm=7064855 } -> x0 + terminator Bz { cond=v14, target=b2, fall=b1 } (exit_acc=v14) + block 1 start_pc=0 + v15 Imm(1) -> x0 + terminator Return(v15) (exit_acc=v15) + block 2 start_pc=0 + v16 Extend { value=v2, kind=I32 } -> x0 + v17 Call { target_pc=1, args=[v2, v2], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v18 Imm(6900000) -> x1 + v19 Imm(6909029) -> x1 + v20 BinopI { op=ne, lhs=v17, rhs_imm=6909029 } -> x0 + terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + block 3 start_pc=0 + v21 Imm(2) -> x0 + terminator Return(v21) (exit_acc=v21) + block 4 start_pc=0 + v22 Imm(0) -> x0 + terminator Return(v22) (exit_acc=v22) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/natural_width_local.ssa b/tests/snapshots/ssa/natural_width_local.ssa index 31b489396..ba7eace19 100644 --- a/tests/snapshots/ssa/natural_width_local.ssa +++ b/tests/snapshots/ssa/natural_width_local.ssa @@ -5,96 +5,125 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(300) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x1 - v4 Imm(200) -> x1 - v5 Imm(0) -> x2 - v6 Imm(0) -> x6 - v7 Imm(0) -> x2 - v8 Imm(0) -> x2 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(200) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x1 + v8 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v9 Phi { incoming=[b0:v6, b2:v15], kind=I64 } -> x6 - v10 Phi { incoming=[b0:v6, b2:v22], kind=I64 } -> x2 - v11 Extend { value=v10, kind=I32 } -> x7 - v12 BinopI { op=lt, lhs=v11, rhs_imm=4 } -> x7 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) + v9 Imm(0) -> x0 + v10 Imm(1) -> x0 + v11 Imm(0) -> x0 + v12 Imm(44) -> x0 + v13 Imm(44) -> x0 + v14 Imm(188978561024) -> x0 + v15 Imm(44) -> x0 + v16 Imm(0) -> x0 + v17 Imm(0) -> x0 + v18 Imm(1) -> x0 + v19 Imm(4294967296) -> x0 + v20 Imm(1) -> x0 + v21 Imm(0) -> x0 + v22 Imm(1) -> x0 + v23 Imm(1) -> x0 + v24 Imm(44) -> x0 + v25 Imm(44) -> x0 + v26 Imm(88) -> x0 + v27 Imm(377957122048) -> x0 + v28 Imm(88) -> x0 + v29 Imm(0) -> x0 + v30 Imm(1) -> x0 + v31 Imm(2) -> x0 + v32 Imm(8589934592) -> x0 + v33 Imm(2) -> x0 + v34 Imm(0) -> x0 + v35 Imm(2) -> x0 + v36 Imm(1) -> x0 + v37 Imm(88) -> x0 + v38 Imm(44) -> x0 + v39 Imm(132) -> x0 + v40 Imm(566935683072) -> x0 + v41 Imm(132) -> x0 + v42 Imm(0) -> x0 + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(12884901888) -> x0 + v46 Imm(3) -> x0 + v47 Imm(0) -> x0 + v48 Imm(3) -> x0 + v49 Imm(1) -> x0 + v50 Imm(132) -> x0 + v51 Imm(44) -> x0 + v52 Imm(176) -> x0 + v53 Imm(755914244096) -> x0 + v54 Imm(176) -> x0 + v55 Imm(0) -> x0 + v56 Imm(3) -> x0 + v57 Imm(4) -> x0 + v58 Imm(17179869184) -> x0 + v59 Imm(4) -> x0 + v60 Imm(0) -> x0 + v61 Imm(4) -> x0 + v62 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v62) block 2 start_pc=0 - v13 Extend { value=v9, kind=I32 } -> x7 - v14 Extend { value=v1, kind=I8 } -> x7 - v15 Binop { op=add, lhs=v9, rhs=v14 } -> x6 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x7 - v17 Extend { value=v15, kind=I32 } -> x7 - v18 Imm(0) -> x7 - v19 Extend { value=v10, kind=I32 } -> x7 - v20 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 - v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x7 - v22 Extend { value=v20, kind=I32 } -> x2 - v23 Imm(0) -> x7 - terminator Jmp(b1) (exit_acc=v22) + v63 Imm(0) -> x1 + v64 Imm(0) -> x0 + v65 Imm(44) -> x0 + v66 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v66) block 3 start_pc=0 - v24 Imm(0) -> x7 - v25 Imm(0) -> x2 - v26 Extend { value=v1, kind=I8 } -> x2 - v27 BinopI { op=ne, lhs=v26, rhs_imm=44 } -> x2 - terminator Bz { cond=v27, target=b12, fall=b4 } (exit_acc=v27) + v72 Phi { incoming=[b2:v63, b7:v70], kind=I64 } -> x1 + v73 Imm(44) -> x0 + v74 Imm(0) -> x0 + v75 Imm(0) -> x0 + v76 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v76) block 4 start_pc=0 - v28 LoadLocal { off=-6, kind=I32 } -> x2 - v29 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x2 - v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x7 - v31 Extend { value=v29, kind=I32 } -> x7 - v32 Imm(0) -> x2 - terminator Jmp(b5) (exit_acc=v31) + v82 Phi { incoming=[b3:v72, b8:v80], kind=I64 } -> x1 + v83 Imm(-56) -> x0 + v84 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v84) block 5 start_pc=0 - v33 Phi { incoming=[b12:v24, b4:v31], kind=I64 } -> x7 - v34 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 - v35 BinopI { op=xor, lhs=v34, rhs_imm=44 } -> x0 - v36 BinopI { op=and, lhs=v35, rhs_imm=4294967295 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=0 } -> x0 - terminator Bz { cond=v37, target=b13, fall=b6 } (exit_acc=v37) + v90 Phi { incoming=[b4:v82, b9:v88], kind=I64 } -> x1 + v91 Imm(176) -> x0 + v92 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v92) block 6 start_pc=0 - v38 Extend { value=v33, kind=I32 } -> x0 - v39 BinopI { op=add, lhs=v33, rhs_imm=2 } -> x0 - v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x2 - v41 Extend { value=v39, kind=I32 } -> x7 - v42 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v41) + v98 Phi { incoming=[b5:v90, b10:v96], kind=I64 } -> x1 + v99 Extend { value=v98, kind=I32 } -> x0 + terminator Return(v99) (exit_acc=v99) block 7 start_pc=0 - v43 Phi { incoming=[b13:v33, b6:v41], kind=I64 } -> x7 - v44 Extend { value=v4, kind=I8 } -> x0 - v45 BinopI { op=ne, lhs=v44, rhs_imm=-56 } -> x0 - terminator Bz { cond=v45, target=b14, fall=b8 } (exit_acc=v45) + v67 LoadLocal { off=-6, kind=I32 } -> x0 + v68 Imm(1) -> x0 + v69 Imm(4294967296) -> x0 + v70 Imm(1) -> x1 + v71 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v70) block 8 start_pc=0 - v46 Extend { value=v43, kind=I32 } -> x0 - v47 BinopI { op=add, lhs=v43, rhs_imm=4 } -> x0 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x1 - v49 Extend { value=v47, kind=I32 } -> x7 - v50 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v49) + v77 Extend { value=v72, kind=I32 } -> x0 + v78 BinopI { op=add, lhs=v72, rhs_imm=2 } -> x0 + v79 BinopI { op=shl, lhs=v78, rhs_imm=32 } -> x1 + v80 Extend { value=v78, kind=I32 } -> x1 + v81 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v80) block 9 start_pc=0 - v51 Phi { incoming=[b14:v43, b8:v49], kind=I64 } -> x7 - v52 Extend { value=v9, kind=I32 } -> x0 - v53 BinopI { op=ne, lhs=v52, rhs_imm=176 } -> x0 - terminator Bz { cond=v53, target=b15, fall=b10 } (exit_acc=v53) + v85 Extend { value=v82, kind=I32 } -> x0 + v86 BinopI { op=add, lhs=v82, rhs_imm=4 } -> x0 + v87 BinopI { op=shl, lhs=v86, rhs_imm=32 } -> x1 + v88 Extend { value=v86, kind=I32 } -> x1 + v89 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v88) block 10 start_pc=0 - v54 Extend { value=v51, kind=I32 } -> x0 - v55 BinopI { op=add, lhs=v51, rhs_imm=8 } -> x0 - v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 - v57 Extend { value=v55, kind=I32 } -> x7 - v58 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v57) - block 11 start_pc=0 - v59 Phi { incoming=[b15:v51, b10:v57], kind=I64 } -> x7 - v60 Extend { value=v59, kind=I32 } -> x0 - terminator Return(v60) (exit_acc=v60) - block 12 start_pc=0 - terminator Jmp(b5) - block 13 start_pc=0 - terminator Jmp(b7) - block 14 start_pc=0 - terminator Jmp(b9) - block 15 start_pc=0 - terminator Jmp(b11) + v93 Extend { value=v90, kind=I32 } -> x0 + v94 BinopI { op=add, lhs=v90, rhs_imm=8 } -> x0 + v95 BinopI { op=shl, lhs=v94, rhs_imm=32 } -> x1 + v96 Extend { value=v94, kind=I32 } -> x1 + v97 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v96) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ndebug_optimize_predefine.ssa b/tests/snapshots/ssa/ndebug_optimize_predefine.ssa new file mode 100644 index 000000000..b2afb98cf --- /dev/null +++ b/tests/snapshots/ssa/ndebug_optimize_predefine.ssa @@ -0,0 +1,55 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1) -> x0 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa b/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa new file mode 100644 index 000000000..a198b25d4 --- /dev/null +++ b/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa @@ -0,0 +1,55 @@ +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/nested_aggregate_brace_elision.ssa b/tests/snapshots/ssa/nested_aggregate_brace_elision.ssa index 9d99ec1e6..d99cce07a 100644 --- a/tests/snapshots/ssa/nested_aggregate_brace_elision.ssa +++ b/tests/snapshots/ssa/nested_aggregate_brace_elision.ssa @@ -12,7 +12,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v6 BinopI { op=ne, lhs=v5, rhs_imm=1 } -> x0 v7 Imm(1) -> x2 v8 Imm(0) -> x1 - terminator Bnz { cond=v6, target=b25, fall=b1 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b32, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v9 LocalAddr(-2) -> x0 v10 BinopI { op=add, lhs=v9, rhs_imm=4 } -> x1 @@ -22,11 +22,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v14 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Phi { incoming=[b25:v7, b1:v13], kind=I64 } -> x2 + v15 Phi { incoming=[b32:v7, b1:v13], kind=I64 } -> x2 v16 LoadLocal { off=-14, kind=I64 } -> x0 v17 Imm(1) -> x1 v18 Imm(0) -> x0 - terminator Bnz { cond=v15, target=b26, fall=b3 } (exit_acc=v15) + terminator Bnz { cond=v15, target=b31, fall=b3 } (exit_acc=v15) block 3 start_pc=0 v19 LocalAddr(-2) -> x0 v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x1 @@ -37,10 +37,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v25 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v24) block 4 start_pc=0 - v26 Phi { incoming=[b26:v17, b3:v24], kind=I64 } -> x1 + v26 Phi { incoming=[b31:v17, b3:v24], kind=I64 } -> x1 v27 LoadLocal { off=-13, kind=I64 } -> x0 v28 Imm(0) -> x0 - terminator Bnz { cond=v26, target=b27, fall=b5 } (exit_acc=v26) + terminator Bnz { cond=v26, target=b30, fall=b5 } (exit_acc=v26) block 5 start_pc=0 v29 LocalAddr(-2) -> x0 v30 BinopI { op=add, lhs=v29, rhs_imm=12 } -> x1 @@ -49,7 +49,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v33 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v32) block 6 start_pc=0 - v34 Phi { incoming=[b27:v26, b5:v32], kind=I64 } -> x1 + v34 Phi { incoming=[b30:v26, b5:v32], kind=I64 } -> x1 v35 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v34, target=b8, fall=b7 } (exit_acc=v34) block 7 start_pc=0 @@ -64,7 +64,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v42 BinopI { op=ne, lhs=v41, rhs_imm=1 } -> x0 v43 Imm(1) -> x2 v44 Imm(0) -> x1 - terminator Bnz { cond=v42, target=b28, fall=b9 } (exit_acc=v42) + terminator Bnz { cond=v42, target=b29, fall=b9 } (exit_acc=v42) block 9 start_pc=0 v45 LocalAddr(-4) -> x0 v46 BinopI { op=add, lhs=v45, rhs_imm=4 } -> x1 @@ -74,10 +74,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v50 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v49) block 10 start_pc=0 - v51 Phi { incoming=[b28:v43, b9:v49], kind=I64 } -> x2 + v51 Phi { incoming=[b29:v43, b9:v49], kind=I64 } -> x2 v52 LoadLocal { off=-16, kind=I64 } -> x0 v53 Imm(0) -> x0 - terminator Bnz { cond=v51, target=b29, fall=b11 } (exit_acc=v51) + terminator Bnz { cond=v51, target=b28, fall=b11 } (exit_acc=v51) block 11 start_pc=0 v54 LocalAddr(-4) -> x0 v55 BinopI { op=add, lhs=v54, rhs_imm=4 } -> x1 @@ -87,7 +87,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v59 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v58) block 12 start_pc=0 - v60 Phi { incoming=[b29:v51, b11:v58], kind=I64 } -> x2 + v60 Phi { incoming=[b28:v51, b11:v58], kind=I64 } -> x2 v61 LoadLocal { off=-15, kind=I64 } -> x0 terminator Bz { cond=v60, target=b14, fall=b13 } (exit_acc=v60) block 13 start_pc=0 @@ -102,7 +102,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v68 BinopI { op=ne, lhs=v67, rhs_imm=1 } -> x0 v69 Imm(1) -> x2 v70 Imm(0) -> x1 - terminator Bnz { cond=v68, target=b30, fall=b15 } (exit_acc=v68) + terminator Bnz { cond=v68, target=b27, fall=b15 } (exit_acc=v68) block 15 start_pc=0 v71 LocalAddr(-7) -> x0 v72 BinopI { op=add, lhs=v71, rhs_imm=8 } -> x1 @@ -112,10 +112,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v76 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v75) block 16 start_pc=0 - v77 Phi { incoming=[b30:v69, b15:v75], kind=I64 } -> x2 + v77 Phi { incoming=[b27:v69, b15:v75], kind=I64 } -> x2 v78 LoadLocal { off=-18, kind=I64 } -> x0 v79 Imm(0) -> x0 - terminator Bnz { cond=v77, target=b31, fall=b17 } (exit_acc=v77) + terminator Bnz { cond=v77, target=b26, fall=b17 } (exit_acc=v77) block 17 start_pc=0 v80 LocalAddr(-7) -> x0 v81 BinopI { op=add, lhs=v80, rhs_imm=16 } -> x1 @@ -124,7 +124,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v84 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v83) block 18 start_pc=0 - v85 Phi { incoming=[b31:v77, b17:v83], kind=I64 } -> x2 + v85 Phi { incoming=[b26:v77, b17:v83], kind=I64 } -> x2 v86 LoadLocal { off=-17, kind=I64 } -> x0 terminator Bz { cond=v85, target=b20, fall=b19 } (exit_acc=v85) block 19 start_pc=0 @@ -142,7 +142,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v96 Load { addr=v91, disp=24, kind=I32 } -> x0 v97 BinopI { op=ne, lhs=v96, rhs_imm=7 } -> x1 v98 Imm(0) -> x0 - terminator Bnz { cond=v97, target=b32, fall=b21 } (exit_acc=v97) + terminator Bnz { cond=v97, target=b25, fall=b21 } (exit_acc=v97) block 21 start_pc=0 v99 LocalAddr(-11) -> x0 v100 Imm(16) -> x1 @@ -153,7 +153,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v105 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v104) block 22 start_pc=0 - v106 Phi { incoming=[b32:v97, b21:v104], kind=I64 } -> x1 + v106 Phi { incoming=[b25:v97, b21:v104], kind=I64 } -> x1 v107 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v106, target=b24, fall=b23 } (exit_acc=v106) block 23 start_pc=0 @@ -163,21 +163,21 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v109 Imm(0) -> x0 terminator Return(v109) (exit_acc=v109) block 25 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b22) block 26 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b18) block 27 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 28 start_pc=0 - terminator Jmp(b10) - block 29 start_pc=0 terminator Jmp(b12) + block 29 start_pc=0 + terminator Jmp(b10) block 30 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 31 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b4) block 32 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/nested_compound_literal.ssa b/tests/snapshots/ssa/nested_compound_literal.ssa index c03309bb9..76b9b3fef 100644 --- a/tests/snapshots/ssa/nested_compound_literal.ssa +++ b/tests/snapshots/ssa/nested_compound_literal.ssa @@ -26,7 +26,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v9 BinopI { op=ne, lhs=v8, rhs_imm=3 } -> x0 v10 Imm(1) -> x2 v11 Imm(0) -> x1 - terminator Bnz { cond=v9, target=b31, fall=b1 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b39, fall=b1 } (exit_acc=v9) block 1 start_pc=0 v12 LocalAddr(-2) -> x0 v13 BinopI { op=add, lhs=v12, rhs_imm=4 } -> x1 @@ -36,10 +36,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v17 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v18 Phi { incoming=[b31:v10, b1:v16], kind=I64 } -> x2 + v18 Phi { incoming=[b39:v10, b1:v16], kind=I64 } -> x2 v19 LoadLocal { off=-16, kind=I64 } -> x0 v20 Imm(0) -> x0 - terminator Bnz { cond=v18, target=b32, fall=b3 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b38, fall=b3 } (exit_acc=v18) block 3 start_pc=0 v21 LocalAddr(-2) -> x0 v22 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x1 @@ -48,7 +48,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v25 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v24) block 4 start_pc=0 - v26 Phi { incoming=[b32:v18, b3:v24], kind=I64 } -> x2 + v26 Phi { incoming=[b38:v18, b3:v24], kind=I64 } -> x2 v27 LoadLocal { off=-15, kind=I64 } -> x0 terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) block 5 start_pc=0 @@ -63,7 +63,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v34 BinopI { op=ne, lhs=v33, rhs_imm=6 } -> x0 v35 Imm(1) -> x2 v36 Imm(0) -> x1 - terminator Bnz { cond=v34, target=b33, fall=b7 } (exit_acc=v34) + terminator Bnz { cond=v34, target=b37, fall=b7 } (exit_acc=v34) block 7 start_pc=0 v37 LocalAddr(-6) -> x0 v38 BinopI { op=add, lhs=v37, rhs_imm=4 } -> x1 @@ -73,10 +73,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v42 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v41) block 8 start_pc=0 - v43 Phi { incoming=[b33:v35, b7:v41], kind=I64 } -> x2 + v43 Phi { incoming=[b37:v35, b7:v41], kind=I64 } -> x2 v44 LoadLocal { off=-18, kind=I64 } -> x0 v45 Imm(0) -> x0 - terminator Bnz { cond=v43, target=b34, fall=b9 } (exit_acc=v43) + terminator Bnz { cond=v43, target=b36, fall=b9 } (exit_acc=v43) block 9 start_pc=0 v46 LocalAddr(-6) -> x0 v47 BinopI { op=add, lhs=v46, rhs_imm=8 } -> x1 @@ -85,7 +85,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v50 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v49) block 10 start_pc=0 - v51 Phi { incoming=[b34:v43, b9:v49], kind=I64 } -> x2 + v51 Phi { incoming=[b36:v43, b9:v49], kind=I64 } -> x2 v52 LoadLocal { off=-17, kind=I64 } -> x0 terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) block 11 start_pc=0 @@ -110,7 +110,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v65 Phi { incoming=[b35:v57, b13:v63], kind=I64 } -> x2 v66 LoadLocal { off=-20, kind=I64 } -> x0 v67 Imm(0) -> x0 - terminator Bnz { cond=v65, target=b36, fall=b15 } (exit_acc=v65) + terminator Bnz { cond=v65, target=b34, fall=b15 } (exit_acc=v65) block 15 start_pc=0 v68 ImmData(8) -> x0 v69 BinopI { op=add, lhs=v68, rhs_imm=8 } -> x1 @@ -119,7 +119,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v72 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v71) block 16 start_pc=0 - v73 Phi { incoming=[b36:v65, b15:v71], kind=I64 } -> x2 + v73 Phi { incoming=[b34:v65, b15:v71], kind=I64 } -> x2 v74 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v73, target=b18, fall=b17 } (exit_acc=v73) block 17 start_pc=0 @@ -137,7 +137,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v84 Load { addr=v82, disp=8, kind=I64 } -> x0 v85 BinopI { op=ne, lhs=v84, rhs_imm=7 } -> x1 v86 Imm(0) -> x0 - terminator Bnz { cond=v85, target=b37, fall=b19 } (exit_acc=v85) + terminator Bnz { cond=v85, target=b33, fall=b19 } (exit_acc=v85) block 19 start_pc=0 v87 LocalAddr(-8) -> x0 v88 Load { addr=v87, disp=0, kind=I32 } -> x0 @@ -145,7 +145,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v90 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v89) block 20 start_pc=0 - v91 Phi { incoming=[b37:v85, b19:v89], kind=I64 } -> x1 + v91 Phi { incoming=[b33:v85, b19:v89], kind=I64 } -> x1 v92 LoadLocal { off=-21, kind=I64 } -> x0 terminator Bz { cond=v91, target=b22, fall=b21 } (exit_acc=v91) block 21 start_pc=0 @@ -157,7 +157,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v96 Load { addr=v94, disp=8, kind=I64 } -> x0 v97 BinopI { op=ne, lhs=v96, rhs_imm=3 } -> x1 v98 Imm(0) -> x0 - terminator Bnz { cond=v97, target=b38, fall=b23 } (exit_acc=v97) + terminator Bnz { cond=v97, target=b32, fall=b23 } (exit_acc=v97) block 23 start_pc=0 v99 ImmData(24) -> x0 v100 Load { addr=v99, disp=0, kind=I32 } -> x0 @@ -165,7 +165,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v102 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v101) block 24 start_pc=0 - v103 Phi { incoming=[b38:v97, b23:v101], kind=I64 } -> x1 + v103 Phi { incoming=[b32:v97, b23:v101], kind=I64 } -> x1 v104 LoadLocal { off=-22, kind=I64 } -> x0 terminator Bz { cond=v103, target=b26, fall=b25 } (exit_acc=v103) block 25 start_pc=0 @@ -184,7 +184,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v115 Load { addr=v113, disp=8, kind=I64 } -> x0 v116 BinopI { op=ne, lhs=v115, rhs_imm=2 } -> x1 v117 Imm(0) -> x0 - terminator Bnz { cond=v116, target=b39, fall=b27 } (exit_acc=v116) + terminator Bnz { cond=v116, target=b31, fall=b27 } (exit_acc=v116) block 27 start_pc=0 v118 LocalAddr(-12) -> x0 v119 Load { addr=v118, disp=0, kind=I32 } -> x0 @@ -192,7 +192,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v121 Imm(0) -> x0 terminator Jmp(b28) (exit_acc=v120) block 28 start_pc=0 - v122 Phi { incoming=[b39:v116, b27:v120], kind=I64 } -> x1 + v122 Phi { incoming=[b31:v116, b27:v120], kind=I64 } -> x1 v123 LoadLocal { off=-25, kind=I64 } -> x0 terminator Bz { cond=v122, target=b30, fall=b29 } (exit_acc=v122) block 29 start_pc=0 @@ -202,23 +202,23 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v125 Imm(0) -> x0 terminator Return(v125) (exit_acc=v125) block 31 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b28) block 32 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b24) block 33 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b20) block 34 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b16) block 35 start_pc=0 terminator Jmp(b14) block 36 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b10) block 37 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b8) block 38 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b4) block 39 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/nested_designator_string_member.ssa b/tests/snapshots/ssa/nested_designator_string_member.ssa index b9ea18718..74eba0387 100644 --- a/tests/snapshots/ssa/nested_designator_string_member.ssa +++ b/tests/snapshots/ssa/nested_designator_string_member.ssa @@ -10,13 +10,25 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b6, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -24,31 +36,19 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 LoadLocal { off=3, kind=I64 } -> x1 v19 Load { addr=v6, disp=0, kind=I8 } -> x1 v20 Binop { op=eq, lhs=v17, rhs=v19 } -> x0 terminator Return(v20) (exit_acc=v20) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b6:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=2 variadic=false locals=8 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x3 @@ -72,20 +72,20 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v15 Imm(3) -> x0 v16 BinopI { op=add, lhs=v7, rhs_imm=7 } -> x0 v17 Load { addr=v7, disp=7, kind=I8 } -> x0 - v18 BinopI { op=ne, lhs=v17, rhs_imm=0 } -> x13 + v18 BinopI { op=ne, lhs=v17, rhs_imm=0 } -> x1 v19 Imm(0) -> x0 - terminator Bnz { cond=v18, target=b21, fall=b3 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b24, fall=b3 } (exit_acc=v18) block 3 start_pc=0 v20 ImmData(8) -> x0 v21 BinopI { op=add, lhs=v7, rhs_imm=4 } -> x0 v22 Imm(7) -> x0 v23 BinopI { op=add, lhs=v7, rhs_imm=11 } -> x0 v24 Load { addr=v7, disp=11, kind=I8 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x13 + v25 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x1 v26 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v25) block 4 start_pc=0 - v27 Phi { incoming=[b21:v18, b3:v25], kind=I64 } -> x13 + v27 Phi { incoming=[b24:v18, b3:v25], kind=I64 } -> x1 v28 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) block 5 start_pc=0 @@ -95,17 +95,17 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v30 ImmData(8) -> x0 v31 BinopI { op=add, lhs=v7, rhs_imm=12 } -> x0 v32 Load { addr=v7, disp=12, kind=I32 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=7 } -> x13 + v33 BinopI { op=ne, lhs=v32, rhs_imm=7 } -> x1 v34 Imm(0) -> x0 - terminator Bnz { cond=v33, target=b22, fall=b7 } (exit_acc=v33) + terminator Bnz { cond=v33, target=b23, fall=b7 } (exit_acc=v33) block 7 start_pc=0 v35 ImmData(8) -> x0 v36 Load { addr=v7, disp=0, kind=I32 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=5 } -> x13 + v37 BinopI { op=ne, lhs=v36, rhs_imm=5 } -> x1 v38 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Phi { incoming=[b22:v33, b7:v37], kind=I64 } -> x13 + v39 Phi { incoming=[b23:v33, b7:v37], kind=I64 } -> x1 v40 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) block 9 start_pc=0 @@ -174,7 +174,7 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v97 Load { addr=v93, disp=8, kind=I8 } -> x0 v98 BinopI { op=ne, lhs=v97, rhs_imm=0 } -> x1 v99 Imm(0) -> x0 - terminator Bnz { cond=v98, target=b23, fall=b13 } (exit_acc=v98) + terminator Bnz { cond=v98, target=b22, fall=b13 } (exit_acc=v98) block 13 start_pc=0 v100 LocalAddr(-2) -> x0 v101 BinopI { op=add, lhs=v100, rhs_imm=4 } -> x1 @@ -185,7 +185,7 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v106 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v105) block 14 start_pc=0 - v107 Phi { incoming=[b23:v98, b13:v105], kind=I64 } -> x1 + v107 Phi { incoming=[b22:v98, b13:v105], kind=I64 } -> x1 v108 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v107, target=b16, fall=b15 } (exit_acc=v107) block 15 start_pc=0 @@ -201,7 +201,7 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v116 Extend { value=v114, kind=I32 } -> x1 v117 Binop { op=ne, lhs=v112, rhs=v116 } -> x1 v118 Imm(0) -> x0 - terminator Bnz { cond=v117, target=b24, fall=b17 } (exit_acc=v117) + terminator Bnz { cond=v117, target=b21, fall=b17 } (exit_acc=v117) block 17 start_pc=0 v119 LocalAddr(-2) -> x0 v120 Load { addr=v119, disp=0, kind=I32 } -> x0 @@ -213,7 +213,7 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v126 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v125) block 18 start_pc=0 - v127 Phi { incoming=[b24:v117, b17:v125], kind=I64 } -> x1 + v127 Phi { incoming=[b21:v117, b17:v125], kind=I64 } -> x1 v128 LoadLocal { off=-8, kind=I64 } -> x0 terminator Bz { cond=v127, target=b20, fall=b19 } (exit_acc=v127) block 19 start_pc=0 @@ -223,13 +223,13 @@ fn ent_pc=1 n_params=2 variadic=false locals=8 v130 Imm(0) -> x0 terminator Return(v130) (exit_acc=v130) block 21 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b8) - block 23 start_pc=0 terminator Jmp(b14) + block 23 start_pc=0 + terminator Jmp(b8) block 24 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/nested_function_calls.ssa b/tests/snapshots/ssa/nested_function_calls.ssa index 0364645e8..2cf7e3752 100644 --- a/tests/snapshots/ssa/nested_function_calls.ssa +++ b/tests/snapshots/ssa/nested_function_calls.ssa @@ -21,30 +21,30 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(10) -> x0 - v2 Imm(20) -> x1 - v3 Extend { value=v1, kind=I32 } -> x2 - v4 Imm(0) -> x2 - v5 Extend { value=v2, kind=I32 } -> x2 - v6 Imm(0) -> x2 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x1 - v10 Imm(30) -> x2 - v11 Imm(40) -> x6 - v12 Extend { value=v10, kind=I32 } -> x7 - v13 Imm(0) -> x7 - v14 Extend { value=v11, kind=I32 } -> x7 - v15 Imm(0) -> x7 - v16 Binop { op=add, lhs=v10, rhs=v11 } -> x2 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x6 - v18 Extend { value=v16, kind=I32 } -> x6 - v19 Extend { value=v9, kind=I32 } -> x1 - v20 Imm(0) -> x1 - v21 Extend { value=v18, kind=I32 } -> x1 - v22 Imm(0) -> x1 - v23 Binop { op=add, lhs=v7, rhs=v16 } -> x0 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x1 - v25 Extend { value=v23, kind=I32 } -> x0 + v2 Imm(20) -> x0 + v3 Imm(10) -> x0 + v4 Imm(0) -> x0 + v5 Imm(20) -> x0 + v6 Imm(0) -> x0 + v7 Imm(30) -> x0 + v8 Imm(128849018880) -> x0 + v9 Imm(30) -> x0 + v10 Imm(30) -> x0 + v11 Imm(40) -> x0 + v12 Imm(30) -> x0 + v13 Imm(0) -> x0 + v14 Imm(40) -> x0 + v15 Imm(0) -> x0 + v16 Imm(70) -> x0 + v17 Imm(300647710720) -> x0 + v18 Imm(70) -> x0 + v19 Imm(30) -> x0 + v20 Imm(0) -> x0 + v21 Imm(70) -> x0 + v22 Imm(0) -> x0 + v23 Imm(100) -> x0 + v24 Imm(429496729600) -> x0 + v25 Imm(100) -> x0 terminator Return(v25) (exit_acc=v25) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/nested_runtime_init.ssa b/tests/snapshots/ssa/nested_runtime_init.ssa index 86e48a198..a6d349825 100644 --- a/tests/snapshots/ssa/nested_runtime_init.ssa +++ b/tests/snapshots/ssa/nested_runtime_init.ssa @@ -6,242 +6,242 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b24) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=20 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) - block 3 start_pc=0 - v9 LocalAddr(-3) -> x0 - v10 ImmData(8) -> x2 - v11 Mcpy { dst=v9, src=v10, size=16 } -> x0 - v12 Extend { value=v3, kind=I32 } -> x0 - v13 LocalAddr(-3) -> x0 + v9 LocalAddr(-3) -> x2 + v10 ImmData(8) -> x6 + v11 Mcpy { dst=v9, src=v10, size=16 } -> x2 + v12 Extend { value=v3, kind=I32 } -> x2 + v13 LocalAddr(-3) -> x2 v14 Store { addr=v13, disp=0, value=v3, kind=I32 } -> - - v15 Extend { value=v3, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x2 - v18 Extend { value=v16, kind=I32 } -> x0 - v19 LocalAddr(-3) -> x2 - v20 BinopI { op=add, lhs=v19, rhs_imm=8 } -> x6 + v15 Extend { value=v3, kind=I32 } -> x2 + v16 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x2 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x6 + v18 Extend { value=v16, kind=I32 } -> x2 + v19 LocalAddr(-3) -> x6 + v20 BinopI { op=add, lhs=v19, rhs_imm=8 } -> x7 v21 Store { addr=v19, disp=8, value=v18, kind=I64 } -> - - v22 LocalAddr(-3) -> x0 - v23 Load { addr=v22, disp=0, kind=I32 } -> x0 - v24 Extend { value=v3, kind=I32 } -> x2 - v25 Binop { op=ne, lhs=v23, rhs=v24 } -> x2 - v26 Imm(0) -> x0 - terminator Bnz { cond=v25, target=b25, fall=b5 } (exit_acc=v25) + v22 LocalAddr(-3) -> x2 + v23 Load { addr=v22, disp=0, kind=I32 } -> x2 + v24 Extend { value=v3, kind=I32 } -> x6 + v25 Binop { op=ne, lhs=v23, rhs=v4 } -> x6 + v26 Imm(0) -> x2 + terminator Bnz { cond=v25, target=b22, fall=b2 } (exit_acc=v25) + block 2 start_pc=0 + v28 LocalAddr(-3) -> x2 + v29 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x6 + v30 Load { addr=v28, disp=8, kind=I64 } -> x2 + v31 Extend { value=v3, kind=I32 } -> x6 + v32 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x6 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x7 + v34 Extend { value=v32, kind=I32 } -> x6 + v35 Binop { op=ne, lhs=v30, rhs=v34 } -> x6 + v36 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v35) + block 3 start_pc=0 + v37 Phi { incoming=[b22:v25, b2:v35], kind=I64 } -> x6 + v38 LoadLocal { off=-10, kind=I64 } -> x2 + terminator Bnz { cond=v37, target=b29, fall=b4 } (exit_acc=v37) block 4 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v40 LocalAddr(-5) -> x2 + v41 ImmData(24) -> x6 + v42 Mcpy { dst=v40, src=v41, size=16 } -> x2 + v43 Extend { value=v3, kind=I32 } -> x2 + v44 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x2 + v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x6 + v46 Extend { value=v44, kind=I32 } -> x6 + v47 LocalAddr(-5) -> x6 + v48 Store { addr=v47, disp=0, value=v44, kind=I32 } -> - + v49 Extend { value=v3, kind=I32 } -> x2 + v50 BinopI { op=add, lhs=v3, rhs_imm=3 } -> x2 + v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x6 + v52 Extend { value=v50, kind=I32 } -> x2 + v53 LocalAddr(-5) -> x6 + v54 BinopI { op=add, lhs=v53, rhs_imm=8 } -> x7 + v55 Store { addr=v53, disp=8, value=v52, kind=I64 } -> - + v56 LocalAddr(-5) -> x2 + v57 Load { addr=v56, disp=0, kind=I32 } -> x2 + v58 Extend { value=v3, kind=I32 } -> x6 + v59 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x6 + v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x7 + v61 Extend { value=v59, kind=I32 } -> x6 + v62 Binop { op=ne, lhs=v57, rhs=v61 } -> x6 + v63 Imm(0) -> x2 + terminator Bnz { cond=v62, target=b21, fall=b5 } (exit_acc=v62) block 5 start_pc=0 - v28 LocalAddr(-3) -> x0 - v29 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x2 - v30 Load { addr=v28, disp=8, kind=I64 } -> x0 - v31 Extend { value=v3, kind=I32 } -> x2 - v32 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x2 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x6 - v34 Extend { value=v32, kind=I32 } -> x2 - v35 Binop { op=ne, lhs=v30, rhs=v34 } -> x2 - v36 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v35) + v64 LocalAddr(-5) -> x2 + v65 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x6 + v66 Load { addr=v64, disp=8, kind=I64 } -> x2 + v67 Extend { value=v3, kind=I32 } -> x6 + v68 BinopI { op=add, lhs=v3, rhs_imm=3 } -> x6 + v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x7 + v70 Extend { value=v68, kind=I32 } -> x6 + v71 Binop { op=ne, lhs=v66, rhs=v70 } -> x6 + v72 Imm(0) -> x2 + terminator Jmp(b6) (exit_acc=v71) block 6 start_pc=0 - v37 Phi { incoming=[b25:v25, b5:v35], kind=I64 } -> x2 - v38 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) + v73 Phi { incoming=[b21:v62, b5:v71], kind=I64 } -> x6 + v74 LoadLocal { off=-11, kind=I64 } -> x2 + terminator Bnz { cond=v73, target=b28, fall=b7 } (exit_acc=v73) block 7 start_pc=0 - v39 Imm(1) -> x0 - terminator Return(v39) (exit_acc=v39) + v76 LocalAddr(-7) -> x2 + v77 ImmData(40) -> x6 + v78 Mcpy { dst=v76, src=v77, size=16 } -> x2 + v79 Extend { value=v3, kind=I32 } -> x2 + v80 LocalAddr(-7) -> x2 + v81 Store { addr=v80, disp=0, value=v3, kind=I32 } -> - + v82 Extend { value=v3, kind=I32 } -> x2 + v83 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x2 + v84 BinopI { op=shl, lhs=v83, rhs_imm=32 } -> x6 + v85 Extend { value=v83, kind=I32 } -> x6 + v86 LocalAddr(-7) -> x6 + v87 BinopI { op=add, lhs=v86, rhs_imm=4 } -> x7 + v88 Store { addr=v86, disp=4, value=v83, kind=I32 } -> - + v89 Extend { value=v3, kind=I32 } -> x2 + v90 BinopI { op=add, lhs=v3, rhs_imm=5 } -> x2 + v91 BinopI { op=shl, lhs=v90, rhs_imm=32 } -> x6 + v92 Extend { value=v90, kind=I32 } -> x2 + v93 LocalAddr(-7) -> x6 + v94 BinopI { op=add, lhs=v93, rhs_imm=8 } -> x7 + v95 Store { addr=v93, disp=8, value=v92, kind=I64 } -> - + v96 LocalAddr(-7) -> x2 + v97 Load { addr=v96, disp=0, kind=I32 } -> x2 + v98 Extend { value=v3, kind=I32 } -> x6 + v99 Binop { op=ne, lhs=v97, rhs=v4 } -> x2 + v100 Imm(1) -> x7 + v101 Imm(0) -> x6 + terminator Bnz { cond=v99, target=b20, fall=b8 } (exit_acc=v99) block 8 start_pc=0 - v40 LocalAddr(-5) -> x0 - v41 ImmData(24) -> x2 - v42 Mcpy { dst=v40, src=v41, size=16 } -> x0 - v43 Extend { value=v3, kind=I32 } -> x0 - v44 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x0 - v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x2 - v46 Extend { value=v44, kind=I32 } -> x2 - v47 LocalAddr(-5) -> x2 - v48 Store { addr=v47, disp=0, value=v44, kind=I32 } -> - - v49 Extend { value=v3, kind=I32 } -> x0 - v50 BinopI { op=add, lhs=v3, rhs_imm=3 } -> x0 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x2 - v52 Extend { value=v50, kind=I32 } -> x0 - v53 LocalAddr(-5) -> x2 - v54 BinopI { op=add, lhs=v53, rhs_imm=8 } -> x6 - v55 Store { addr=v53, disp=8, value=v52, kind=I64 } -> - - v56 LocalAddr(-5) -> x0 - v57 Load { addr=v56, disp=0, kind=I32 } -> x0 - v58 Extend { value=v3, kind=I32 } -> x2 - v59 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x2 - v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x6 - v61 Extend { value=v59, kind=I32 } -> x2 - v62 Binop { op=ne, lhs=v57, rhs=v61 } -> x2 - v63 Imm(0) -> x0 - terminator Bnz { cond=v62, target=b26, fall=b9 } (exit_acc=v62) + v102 LocalAddr(-7) -> x2 + v103 BinopI { op=add, lhs=v102, rhs_imm=4 } -> x6 + v104 Load { addr=v102, disp=4, kind=I32 } -> x2 + v105 Extend { value=v3, kind=I32 } -> x6 + v106 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x6 + v107 BinopI { op=shl, lhs=v106, rhs_imm=32 } -> x7 + v108 Extend { value=v106, kind=I32 } -> x6 + v109 Binop { op=ne, lhs=v104, rhs=v108 } -> x2 + v110 BinopI { op=ne, lhs=v109, rhs_imm=0 } -> x7 + v111 Imm(0) -> x2 + terminator Jmp(b9) (exit_acc=v110) block 9 start_pc=0 - v64 LocalAddr(-5) -> x0 - v65 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x2 - v66 Load { addr=v64, disp=8, kind=I64 } -> x0 - v67 Extend { value=v3, kind=I32 } -> x2 - v68 BinopI { op=add, lhs=v3, rhs_imm=3 } -> x2 - v69 BinopI { op=shl, lhs=v68, rhs_imm=32 } -> x6 - v70 Extend { value=v68, kind=I32 } -> x2 - v71 Binop { op=ne, lhs=v66, rhs=v70 } -> x2 - v72 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v71) + v112 Phi { incoming=[b20:v100, b8:v110], kind=I64 } -> x7 + v113 LoadLocal { off=-13, kind=I64 } -> x2 + v114 Imm(0) -> x2 + terminator Bnz { cond=v112, target=b19, fall=b10 } (exit_acc=v112) block 10 start_pc=0 - v73 Phi { incoming=[b26:v62, b9:v71], kind=I64 } -> x2 - v74 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v73, target=b12, fall=b11 } (exit_acc=v73) + v115 LocalAddr(-7) -> x2 + v116 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x6 + v117 Load { addr=v115, disp=8, kind=I64 } -> x2 + v118 Extend { value=v3, kind=I32 } -> x6 + v119 BinopI { op=add, lhs=v3, rhs_imm=5 } -> x6 + v120 BinopI { op=shl, lhs=v119, rhs_imm=32 } -> x7 + v121 Extend { value=v119, kind=I32 } -> x6 + v122 Binop { op=ne, lhs=v117, rhs=v121 } -> x7 + v123 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v122) block 11 start_pc=0 - v75 Imm(2) -> x0 - terminator Return(v75) (exit_acc=v75) + v124 Phi { incoming=[b19:v112, b10:v122], kind=I64 } -> x7 + v125 LoadLocal { off=-12, kind=I64 } -> x2 + terminator Bnz { cond=v124, target=b27, fall=b12 } (exit_acc=v124) block 12 start_pc=0 - v76 LocalAddr(-7) -> x0 - v77 ImmData(40) -> x2 - v78 Mcpy { dst=v76, src=v77, size=16 } -> x0 - v79 Extend { value=v3, kind=I32 } -> x0 - v80 LocalAddr(-7) -> x0 - v81 Store { addr=v80, disp=0, value=v3, kind=I32 } -> - - v82 Extend { value=v3, kind=I32 } -> x0 - v83 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x0 - v84 BinopI { op=shl, lhs=v83, rhs_imm=32 } -> x2 - v85 Extend { value=v83, kind=I32 } -> x2 - v86 LocalAddr(-7) -> x2 - v87 BinopI { op=add, lhs=v86, rhs_imm=4 } -> x6 - v88 Store { addr=v86, disp=4, value=v83, kind=I32 } -> - - v89 Extend { value=v3, kind=I32 } -> x0 - v90 BinopI { op=add, lhs=v3, rhs_imm=5 } -> x0 - v91 BinopI { op=shl, lhs=v90, rhs_imm=32 } -> x2 - v92 Extend { value=v90, kind=I32 } -> x0 - v93 LocalAddr(-7) -> x2 - v94 BinopI { op=add, lhs=v93, rhs_imm=8 } -> x6 - v95 Store { addr=v93, disp=8, value=v92, kind=I64 } -> - - v96 LocalAddr(-7) -> x0 - v97 Load { addr=v96, disp=0, kind=I32 } -> x0 - v98 Extend { value=v3, kind=I32 } -> x2 - v99 Binop { op=ne, lhs=v97, rhs=v98 } -> x0 - v100 Imm(1) -> x6 - v101 Imm(0) -> x2 - terminator Bnz { cond=v99, target=b27, fall=b13 } (exit_acc=v99) + v127 LocalAddr(-9) -> x2 + v128 ImmData(56) -> x6 + v129 Mcpy { dst=v127, src=v128, size=12 } -> x2 + v130 Extend { value=v3, kind=I32 } -> x2 + v131 LocalAddr(-9) -> x2 + v132 Store { addr=v131, disp=0, value=v3, kind=I32 } -> - + v133 Extend { value=v3, kind=I32 } -> x2 + v134 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x2 + v135 BinopI { op=shl, lhs=v134, rhs_imm=32 } -> x6 + v136 Extend { value=v134, kind=I32 } -> x6 + v137 LocalAddr(-9) -> x6 + v138 BinopI { op=add, lhs=v137, rhs_imm=4 } -> x7 + v139 Store { addr=v137, disp=4, value=v134, kind=I32 } -> - + v140 Extend { value=v3, kind=I32 } -> x2 + v141 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x2 + v142 BinopI { op=shl, lhs=v141, rhs_imm=32 } -> x6 + v143 Extend { value=v141, kind=I32 } -> x6 + v144 LocalAddr(-9) -> x6 + v145 BinopI { op=add, lhs=v144, rhs_imm=8 } -> x7 + v146 Store { addr=v144, disp=8, value=v141, kind=I32 } -> - + v147 LocalAddr(-9) -> x2 + v148 Load { addr=v147, disp=0, kind=I32 } -> x2 + v149 Extend { value=v3, kind=I32 } -> x6 + v150 Binop { op=ne, lhs=v148, rhs=v4 } -> x2 + v151 Imm(1) -> x7 + v152 Imm(0) -> x6 + terminator Bnz { cond=v150, target=b18, fall=b13 } (exit_acc=v150) block 13 start_pc=0 - v102 LocalAddr(-7) -> x0 - v103 BinopI { op=add, lhs=v102, rhs_imm=4 } -> x2 - v104 Load { addr=v102, disp=4, kind=I32 } -> x0 - v105 Extend { value=v3, kind=I32 } -> x2 - v106 BinopI { op=shl, lhs=v3, rhs_imm=1 } -> x2 - v107 BinopI { op=shl, lhs=v106, rhs_imm=32 } -> x6 - v108 Extend { value=v106, kind=I32 } -> x2 - v109 Binop { op=ne, lhs=v104, rhs=v108 } -> x0 - v110 BinopI { op=ne, lhs=v109, rhs_imm=0 } -> x6 - v111 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v110) + v153 LocalAddr(-9) -> x2 + v154 BinopI { op=add, lhs=v153, rhs_imm=4 } -> x6 + v155 Load { addr=v153, disp=4, kind=I32 } -> x2 + v156 Extend { value=v3, kind=I32 } -> x6 + v157 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x6 + v158 BinopI { op=shl, lhs=v157, rhs_imm=32 } -> x7 + v159 Extend { value=v157, kind=I32 } -> x6 + v160 Binop { op=ne, lhs=v155, rhs=v159 } -> x2 + v161 BinopI { op=ne, lhs=v160, rhs_imm=0 } -> x7 + v162 Imm(0) -> x2 + terminator Jmp(b14) (exit_acc=v161) block 14 start_pc=0 - v112 Phi { incoming=[b27:v100, b13:v110], kind=I64 } -> x6 - v113 LoadLocal { off=-13, kind=I64 } -> x0 - v114 Imm(0) -> x0 - terminator Bnz { cond=v112, target=b28, fall=b15 } (exit_acc=v112) + v163 Phi { incoming=[b18:v151, b13:v161], kind=I64 } -> x7 + v164 LoadLocal { off=-15, kind=I64 } -> x2 + v165 Imm(0) -> x2 + terminator Bnz { cond=v163, target=b17, fall=b15 } (exit_acc=v163) block 15 start_pc=0 - v115 LocalAddr(-7) -> x0 - v116 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x2 - v117 Load { addr=v115, disp=8, kind=I64 } -> x0 - v118 Extend { value=v3, kind=I32 } -> x2 - v119 BinopI { op=add, lhs=v3, rhs_imm=5 } -> x2 - v120 BinopI { op=shl, lhs=v119, rhs_imm=32 } -> x6 - v121 Extend { value=v119, kind=I32 } -> x2 - v122 Binop { op=ne, lhs=v117, rhs=v121 } -> x6 - v123 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v122) + v166 LocalAddr(-9) -> x2 + v167 BinopI { op=add, lhs=v166, rhs_imm=8 } -> x6 + v168 Load { addr=v166, disp=8, kind=I32 } -> x2 + v169 Extend { value=v3, kind=I32 } -> x6 + v170 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x6 + v171 BinopI { op=shl, lhs=v170, rhs_imm=32 } -> x7 + v172 Extend { value=v170, kind=I32 } -> x6 + v173 Binop { op=ne, lhs=v168, rhs=v172 } -> x7 + v174 Imm(0) -> x2 + terminator Jmp(b16) (exit_acc=v173) block 16 start_pc=0 - v124 Phi { incoming=[b28:v112, b15:v122], kind=I64 } -> x6 - v125 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Bz { cond=v124, target=b18, fall=b17 } (exit_acc=v124) + v175 Phi { incoming=[b17:v163, b15:v173], kind=I64 } -> x7 + v176 LoadLocal { off=-14, kind=I64 } -> x2 + terminator Bz { cond=v175, target=b23, fall=b26 } (exit_acc=v175) block 17 start_pc=0 - v126 Imm(3) -> x0 - terminator Return(v126) (exit_acc=v126) + terminator Jmp(b16) block 18 start_pc=0 - v127 LocalAddr(-9) -> x0 - v128 ImmData(56) -> x2 - v129 Mcpy { dst=v127, src=v128, size=12 } -> x0 - v130 Extend { value=v3, kind=I32 } -> x0 - v131 LocalAddr(-9) -> x0 - v132 Store { addr=v131, disp=0, value=v3, kind=I32 } -> - - v133 Extend { value=v3, kind=I32 } -> x0 - v134 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v135 BinopI { op=shl, lhs=v134, rhs_imm=32 } -> x2 - v136 Extend { value=v134, kind=I32 } -> x2 - v137 LocalAddr(-9) -> x2 - v138 BinopI { op=add, lhs=v137, rhs_imm=4 } -> x6 - v139 Store { addr=v137, disp=4, value=v134, kind=I32 } -> - - v140 Extend { value=v3, kind=I32 } -> x0 - v141 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x0 - v142 BinopI { op=shl, lhs=v141, rhs_imm=32 } -> x2 - v143 Extend { value=v141, kind=I32 } -> x2 - v144 LocalAddr(-9) -> x2 - v145 BinopI { op=add, lhs=v144, rhs_imm=8 } -> x6 - v146 Store { addr=v144, disp=8, value=v141, kind=I32 } -> - - v147 LocalAddr(-9) -> x0 - v148 Load { addr=v147, disp=0, kind=I32 } -> x0 - v149 Extend { value=v3, kind=I32 } -> x2 - v150 Binop { op=ne, lhs=v148, rhs=v149 } -> x0 - v151 Imm(1) -> x6 - v152 Imm(0) -> x2 - terminator Bnz { cond=v150, target=b29, fall=b19 } (exit_acc=v150) + terminator Jmp(b14) block 19 start_pc=0 - v153 LocalAddr(-9) -> x0 - v154 BinopI { op=add, lhs=v153, rhs_imm=4 } -> x2 - v155 Load { addr=v153, disp=4, kind=I32 } -> x0 - v156 Extend { value=v3, kind=I32 } -> x2 - v157 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x2 - v158 BinopI { op=shl, lhs=v157, rhs_imm=32 } -> x6 - v159 Extend { value=v157, kind=I32 } -> x2 - v160 Binop { op=ne, lhs=v155, rhs=v159 } -> x0 - v161 BinopI { op=ne, lhs=v160, rhs_imm=0 } -> x6 - v162 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v161) + terminator Jmp(b11) block 20 start_pc=0 - v163 Phi { incoming=[b29:v151, b19:v161], kind=I64 } -> x6 - v164 LoadLocal { off=-15, kind=I64 } -> x0 - v165 Imm(0) -> x0 - terminator Bnz { cond=v163, target=b30, fall=b21 } (exit_acc=v163) + terminator Jmp(b9) block 21 start_pc=0 - v166 LocalAddr(-9) -> x0 - v167 BinopI { op=add, lhs=v166, rhs_imm=8 } -> x2 - v168 Load { addr=v166, disp=8, kind=I32 } -> x0 - v169 Extend { value=v3, kind=I32 } -> x2 - v170 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x2 - v171 BinopI { op=shl, lhs=v170, rhs_imm=32 } -> x6 - v172 Extend { value=v170, kind=I32 } -> x2 - v173 Binop { op=ne, lhs=v168, rhs=v172 } -> x6 - v174 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v173) + terminator Jmp(b6) block 22 start_pc=0 - v175 Phi { incoming=[b30:v163, b21:v173], kind=I64 } -> x6 - v176 LoadLocal { off=-14, kind=I64 } -> x0 - terminator Bz { cond=v175, target=b24, fall=b23 } (exit_acc=v175) + terminator Jmp(b3) block 23 start_pc=0 - v177 Imm(4) -> x0 - terminator Return(v177) (exit_acc=v177) + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v7) block 24 start_pc=0 - terminator Jmp(b2) + v3 Phi { incoming=[b0:v1, b23:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=20 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b25 } (exit_acc=v5) block 25 start_pc=0 - terminator Jmp(b6) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 26 start_pc=0 - terminator Jmp(b10) + v177 Imm(4) -> x0 + terminator Return(v177) (exit_acc=v177) block 27 start_pc=0 - terminator Jmp(b14) + v126 Imm(3) -> x0 + terminator Return(v126) (exit_acc=v126) block 28 start_pc=0 - terminator Jmp(b16) + v75 Imm(2) -> x0 + terminator Return(v75) (exit_acc=v75) block 29 start_pc=0 - terminator Jmp(b20) + v39 Imm(1) -> x0 + terminator Return(v39) (exit_acc=v39) block 30 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b23) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/nonconst_local_struct_init.ssa b/tests/snapshots/ssa/nonconst_local_struct_init.ssa index 2441dd84e..420dadbb2 100644 --- a/tests/snapshots/ssa/nonconst_local_struct_init.ssa +++ b/tests/snapshots/ssa/nonconst_local_struct_init.ssa @@ -11,38 +11,38 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=30 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(42) -> x3 - v2 Imm(0) -> x0 - v3 Imm(99) -> x12 - v4 Imm(0) -> x0 - v5 LocalAddr(-3) -> x0 - v6 ImmData(52) -> x1 - v7 Mcpy { dst=v5, src=v6, size=8 } -> x0 - v8 LoadLocal { off=-1, kind=I32 } -> x0 - v9 LocalAddr(-3) -> x0 + v1 Imm(42) -> x0 + v2 Imm(0) -> x1 + v3 Imm(99) -> x1 + v4 Imm(0) -> x2 + v5 LocalAddr(-3) -> x2 + v6 ImmData(52) -> x6 + v7 Mcpy { dst=v5, src=v6, size=8 } -> x2 + v8 LoadLocal { off=-1, kind=I32 } -> x2 + v9 LocalAddr(-3) -> x2 v10 Store { addr=v9, disp=0, value=v1, kind=I32 } -> - - v11 LoadLocal { off=-2, kind=I32 } -> x0 - v12 LocalAddr(-3) -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=4 } -> x1 + v11 LoadLocal { off=-2, kind=I32 } -> x2 + v12 LocalAddr(-3) -> x2 + v13 BinopI { op=add, lhs=v12, rhs_imm=4 } -> x6 v14 Store { addr=v12, disp=4, value=v3, kind=I32 } -> - - v15 LocalAddr(-3) -> x0 - v16 Load { addr=v15, disp=0, kind=I32 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=42 } -> x13 - v18 Imm(0) -> x0 - terminator Bnz { cond=v17, target=b37, fall=b1 } (exit_acc=v17) + v15 LocalAddr(-3) -> x2 + v16 Load { addr=v15, disp=0, kind=I32 } -> x2 + v17 BinopI { op=ne, lhs=v16, rhs_imm=42 } -> x6 + v18 Imm(0) -> x2 + terminator Bnz { cond=v17, target=b47, fall=b1 } (exit_acc=v17) block 1 start_pc=0 - v19 LocalAddr(-3) -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x1 - v21 Load { addr=v19, disp=4, kind=I32 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=99 } -> x13 - v23 Imm(0) -> x0 + v19 LocalAddr(-3) -> x2 + v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x6 + v21 Load { addr=v19, disp=4, kind=I32 } -> x2 + v22 BinopI { op=ne, lhs=v21, rhs_imm=99 } -> x6 + v23 Imm(0) -> x2 terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 - v24 Phi { incoming=[b37:v17, b1:v22], kind=I64 } -> x13 - v25 LoadLocal { off=-20, kind=I64 } -> x0 + v24 Phi { incoming=[b47:v17, b1:v22], kind=I64 } -> x6 + v25 LoadLocal { off=-20, kind=I64 } -> x2 terminator Bz { cond=v24, target=b4, fall=b3 } (exit_acc=v24) block 3 start_pc=0 v26 ImmData(60) -> x7 @@ -55,31 +55,31 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v33 Imm(1) -> x0 terminator Return(v33) (exit_acc=v33) block 4 start_pc=0 - v34 LocalAddr(-4) -> x0 - v35 ImmData(76) -> x1 - v36 Mcpy { dst=v34, src=v35, size=8 } -> x0 - v37 Imm(7) -> x0 - v38 LocalAddr(-4) -> x1 + v34 LocalAddr(-4) -> x2 + v35 ImmData(76) -> x6 + v36 Mcpy { dst=v34, src=v35, size=8 } -> x2 + v37 Imm(7) -> x2 + v38 LocalAddr(-4) -> x6 v39 Store { addr=v38, disp=0, value=v37, kind=I32 } -> - - v40 LoadLocal { off=-2, kind=I32 } -> x0 - v41 LocalAddr(-4) -> x0 - v42 BinopI { op=add, lhs=v41, rhs_imm=4 } -> x1 + v40 LoadLocal { off=-2, kind=I32 } -> x2 + v41 LocalAddr(-4) -> x2 + v42 BinopI { op=add, lhs=v41, rhs_imm=4 } -> x6 v43 Store { addr=v41, disp=4, value=v3, kind=I32 } -> - - v44 LocalAddr(-4) -> x0 - v45 Load { addr=v44, disp=0, kind=I32 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=7 } -> x13 - v47 Imm(0) -> x0 - terminator Bnz { cond=v46, target=b38, fall=b5 } (exit_acc=v46) + v44 LocalAddr(-4) -> x2 + v45 Load { addr=v44, disp=0, kind=I32 } -> x2 + v46 BinopI { op=ne, lhs=v45, rhs_imm=7 } -> x6 + v47 Imm(0) -> x2 + terminator Bnz { cond=v46, target=b46, fall=b5 } (exit_acc=v46) block 5 start_pc=0 - v48 LocalAddr(-4) -> x0 - v49 BinopI { op=add, lhs=v48, rhs_imm=4 } -> x1 - v50 Load { addr=v48, disp=4, kind=I32 } -> x0 - v51 BinopI { op=ne, lhs=v50, rhs_imm=99 } -> x13 - v52 Imm(0) -> x0 + v48 LocalAddr(-4) -> x2 + v49 BinopI { op=add, lhs=v48, rhs_imm=4 } -> x6 + v50 Load { addr=v48, disp=4, kind=I32 } -> x2 + v51 BinopI { op=ne, lhs=v50, rhs_imm=99 } -> x6 + v52 Imm(0) -> x2 terminator Jmp(b6) (exit_acc=v51) block 6 start_pc=0 - v53 Phi { incoming=[b38:v46, b5:v51], kind=I64 } -> x13 - v54 LoadLocal { off=-21, kind=I64 } -> x0 + v53 Phi { incoming=[b46:v46, b5:v51], kind=I64 } -> x6 + v54 LoadLocal { off=-21, kind=I64 } -> x2 terminator Bz { cond=v53, target=b8, fall=b7 } (exit_acc=v53) block 7 start_pc=0 v55 ImmData(84) -> x7 @@ -92,35 +92,35 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v62 Imm(2) -> x0 terminator Return(v62) (exit_acc=v62) block 8 start_pc=0 - v63 LocalAddr(-5) -> x0 - v64 ImmData(100) -> x1 - v65 Mcpy { dst=v63, src=v64, size=8 } -> x0 - v66 Imm(11) -> x0 - v67 Extend { value=v66, kind=I32 } -> x1 - v68 Imm(0) -> x1 - v69 LocalAddr(-5) -> x1 - v70 Store { addr=v69, disp=0, value=v66, kind=I32 } -> - - v71 Imm(22) -> x0 - v72 Extend { value=v71, kind=I32 } -> x1 - v73 Imm(0) -> x1 - v74 LocalAddr(-5) -> x1 - v75 BinopI { op=add, lhs=v74, rhs_imm=4 } -> x2 - v76 Store { addr=v74, disp=4, value=v71, kind=I32 } -> - - v77 LocalAddr(-5) -> x0 - v78 Load { addr=v77, disp=0, kind=I32 } -> x0 - v79 BinopI { op=ne, lhs=v78, rhs_imm=11 } -> x13 - v80 Imm(0) -> x0 - terminator Bnz { cond=v79, target=b39, fall=b9 } (exit_acc=v79) + v63 LocalAddr(-5) -> x2 + v64 ImmData(100) -> x6 + v65 Mcpy { dst=v63, src=v64, size=8 } -> x2 + v66 Imm(11) -> x2 + v67 Imm(11) -> x2 + v68 Imm(0) -> x6 + v69 LocalAddr(-5) -> x6 + v70 Store { addr=v69, disp=0, value=v67, kind=I32 } -> - + v71 Imm(22) -> x2 + v72 Imm(22) -> x2 + v73 Imm(0) -> x6 + v74 LocalAddr(-5) -> x6 + v75 BinopI { op=add, lhs=v74, rhs_imm=4 } -> x7 + v76 Store { addr=v74, disp=4, value=v72, kind=I32 } -> - + v77 LocalAddr(-5) -> x2 + v78 Load { addr=v77, disp=0, kind=I32 } -> x2 + v79 BinopI { op=ne, lhs=v78, rhs_imm=11 } -> x6 + v80 Imm(0) -> x2 + terminator Bnz { cond=v79, target=b45, fall=b9 } (exit_acc=v79) block 9 start_pc=0 - v81 LocalAddr(-5) -> x0 - v82 BinopI { op=add, lhs=v81, rhs_imm=4 } -> x1 - v83 Load { addr=v81, disp=4, kind=I32 } -> x0 - v84 BinopI { op=ne, lhs=v83, rhs_imm=22 } -> x13 - v85 Imm(0) -> x0 + v81 LocalAddr(-5) -> x2 + v82 BinopI { op=add, lhs=v81, rhs_imm=4 } -> x6 + v83 Load { addr=v81, disp=4, kind=I32 } -> x2 + v84 BinopI { op=ne, lhs=v83, rhs_imm=22 } -> x6 + v85 Imm(0) -> x2 terminator Jmp(b10) (exit_acc=v84) block 10 start_pc=0 - v86 Phi { incoming=[b39:v79, b9:v84], kind=I64 } -> x13 - v87 LoadLocal { off=-22, kind=I64 } -> x0 + v86 Phi { incoming=[b45:v79, b9:v84], kind=I64 } -> x6 + v87 LoadLocal { off=-22, kind=I64 } -> x2 terminator Bz { cond=v86, target=b12, fall=b11 } (exit_acc=v86) block 11 start_pc=0 v88 ImmData(108) -> x7 @@ -133,45 +133,45 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v95 Imm(3) -> x0 terminator Return(v95) (exit_acc=v95) block 12 start_pc=0 - v96 LocalAddr(-7) -> x0 - v97 ImmData(124) -> x1 - v98 Mcpy { dst=v96, src=v97, size=12 } -> x0 - v99 LoadLocal { off=-1, kind=I32 } -> x0 - v100 LocalAddr(-7) -> x0 + v96 LocalAddr(-7) -> x2 + v97 ImmData(124) -> x6 + v98 Mcpy { dst=v96, src=v97, size=12 } -> x2 + v99 LoadLocal { off=-1, kind=I32 } -> x2 + v100 LocalAddr(-7) -> x2 v101 Store { addr=v100, disp=0, value=v1, kind=I32 } -> - - v102 LoadLocal { off=-2, kind=I32 } -> x0 - v103 LocalAddr(-7) -> x0 - v104 BinopI { op=add, lhs=v103, rhs_imm=8 } -> x1 + v102 LoadLocal { off=-2, kind=I32 } -> x2 + v103 LocalAddr(-7) -> x2 + v104 BinopI { op=add, lhs=v103, rhs_imm=8 } -> x6 v105 Store { addr=v103, disp=8, value=v3, kind=I32 } -> - - v106 LocalAddr(-7) -> x0 - v107 Load { addr=v106, disp=0, kind=I32 } -> x0 - v108 BinopI { op=ne, lhs=v107, rhs_imm=42 } -> x0 - v109 Imm(1) -> x13 - v110 Imm(0) -> x1 - terminator Bnz { cond=v108, target=b40, fall=b13 } (exit_acc=v108) + v106 LocalAddr(-7) -> x2 + v107 Load { addr=v106, disp=0, kind=I32 } -> x2 + v108 BinopI { op=ne, lhs=v107, rhs_imm=42 } -> x2 + v109 Imm(1) -> x7 + v110 Imm(0) -> x6 + terminator Bnz { cond=v108, target=b44, fall=b13 } (exit_acc=v108) block 13 start_pc=0 - v111 LocalAddr(-7) -> x0 - v112 BinopI { op=add, lhs=v111, rhs_imm=4 } -> x1 - v113 Load { addr=v111, disp=4, kind=I32 } -> x0 - v114 BinopI { op=ne, lhs=v113, rhs_imm=0 } -> x0 - v115 BinopI { op=ne, lhs=v114, rhs_imm=0 } -> x13 - v116 Imm(0) -> x0 + v111 LocalAddr(-7) -> x2 + v112 BinopI { op=add, lhs=v111, rhs_imm=4 } -> x6 + v113 Load { addr=v111, disp=4, kind=I32 } -> x2 + v114 BinopI { op=ne, lhs=v113, rhs_imm=0 } -> x2 + v115 BinopI { op=ne, lhs=v114, rhs_imm=0 } -> x7 + v116 Imm(0) -> x2 terminator Jmp(b14) (exit_acc=v115) block 14 start_pc=0 - v117 Phi { incoming=[b40:v109, b13:v115], kind=I64 } -> x13 - v118 LoadLocal { off=-24, kind=I64 } -> x0 - v119 Imm(0) -> x0 - terminator Bnz { cond=v117, target=b41, fall=b15 } (exit_acc=v117) + v117 Phi { incoming=[b44:v109, b13:v115], kind=I64 } -> x7 + v118 LoadLocal { off=-24, kind=I64 } -> x2 + v119 Imm(0) -> x2 + terminator Bnz { cond=v117, target=b43, fall=b15 } (exit_acc=v117) block 15 start_pc=0 - v120 LocalAddr(-7) -> x0 - v121 BinopI { op=add, lhs=v120, rhs_imm=8 } -> x1 - v122 Load { addr=v120, disp=8, kind=I32 } -> x0 - v123 BinopI { op=ne, lhs=v122, rhs_imm=99 } -> x13 - v124 Imm(0) -> x0 + v120 LocalAddr(-7) -> x2 + v121 BinopI { op=add, lhs=v120, rhs_imm=8 } -> x6 + v122 Load { addr=v120, disp=8, kind=I32 } -> x2 + v123 BinopI { op=ne, lhs=v122, rhs_imm=99 } -> x7 + v124 Imm(0) -> x2 terminator Jmp(b16) (exit_acc=v123) block 16 start_pc=0 - v125 Phi { incoming=[b41:v117, b15:v123], kind=I64 } -> x13 - v126 LoadLocal { off=-23, kind=I64 } -> x0 + v125 Phi { incoming=[b43:v117, b15:v123], kind=I64 } -> x7 + v126 LoadLocal { off=-23, kind=I64 } -> x2 terminator Bz { cond=v125, target=b18, fall=b17 } (exit_acc=v125) block 17 start_pc=0 v127 ImmData(136) -> x7 @@ -187,45 +187,45 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v137 Imm(4) -> x0 terminator Return(v137) (exit_acc=v137) block 18 start_pc=0 - v138 LocalAddr(-9) -> x0 - v139 ImmData(155) -> x1 - v140 Mcpy { dst=v138, src=v139, size=12 } -> x0 - v141 LoadLocal { off=-2, kind=I32 } -> x0 - v142 LocalAddr(-9) -> x0 - v143 BinopI { op=add, lhs=v142, rhs_imm=8 } -> x1 + v138 LocalAddr(-9) -> x2 + v139 ImmData(155) -> x6 + v140 Mcpy { dst=v138, src=v139, size=12 } -> x2 + v141 LoadLocal { off=-2, kind=I32 } -> x2 + v142 LocalAddr(-9) -> x2 + v143 BinopI { op=add, lhs=v142, rhs_imm=8 } -> x6 v144 Store { addr=v142, disp=8, value=v3, kind=I32 } -> - - v145 LoadLocal { off=-1, kind=I32 } -> x0 - v146 LocalAddr(-9) -> x0 + v145 LoadLocal { off=-1, kind=I32 } -> x2 + v146 LocalAddr(-9) -> x2 v147 Store { addr=v146, disp=0, value=v1, kind=I32 } -> - - v148 LocalAddr(-9) -> x0 - v149 Load { addr=v148, disp=0, kind=I32 } -> x0 - v150 BinopI { op=ne, lhs=v149, rhs_imm=42 } -> x0 - v151 Imm(1) -> x13 - v152 Imm(0) -> x1 + v148 LocalAddr(-9) -> x2 + v149 Load { addr=v148, disp=0, kind=I32 } -> x2 + v150 BinopI { op=ne, lhs=v149, rhs_imm=42 } -> x2 + v151 Imm(1) -> x7 + v152 Imm(0) -> x6 terminator Bnz { cond=v150, target=b42, fall=b19 } (exit_acc=v150) block 19 start_pc=0 - v153 LocalAddr(-9) -> x0 - v154 BinopI { op=add, lhs=v153, rhs_imm=4 } -> x1 - v155 Load { addr=v153, disp=4, kind=I32 } -> x0 - v156 BinopI { op=ne, lhs=v155, rhs_imm=0 } -> x0 - v157 BinopI { op=ne, lhs=v156, rhs_imm=0 } -> x13 - v158 Imm(0) -> x0 + v153 LocalAddr(-9) -> x2 + v154 BinopI { op=add, lhs=v153, rhs_imm=4 } -> x6 + v155 Load { addr=v153, disp=4, kind=I32 } -> x2 + v156 BinopI { op=ne, lhs=v155, rhs_imm=0 } -> x2 + v157 BinopI { op=ne, lhs=v156, rhs_imm=0 } -> x7 + v158 Imm(0) -> x2 terminator Jmp(b20) (exit_acc=v157) block 20 start_pc=0 - v159 Phi { incoming=[b42:v151, b19:v157], kind=I64 } -> x13 - v160 LoadLocal { off=-26, kind=I64 } -> x0 - v161 Imm(0) -> x0 - terminator Bnz { cond=v159, target=b43, fall=b21 } (exit_acc=v159) + v159 Phi { incoming=[b42:v151, b19:v157], kind=I64 } -> x7 + v160 LoadLocal { off=-26, kind=I64 } -> x2 + v161 Imm(0) -> x2 + terminator Bnz { cond=v159, target=b41, fall=b21 } (exit_acc=v159) block 21 start_pc=0 - v162 LocalAddr(-9) -> x0 - v163 BinopI { op=add, lhs=v162, rhs_imm=8 } -> x1 - v164 Load { addr=v162, disp=8, kind=I32 } -> x0 - v165 BinopI { op=ne, lhs=v164, rhs_imm=99 } -> x13 - v166 Imm(0) -> x0 + v162 LocalAddr(-9) -> x2 + v163 BinopI { op=add, lhs=v162, rhs_imm=8 } -> x6 + v164 Load { addr=v162, disp=8, kind=I32 } -> x2 + v165 BinopI { op=ne, lhs=v164, rhs_imm=99 } -> x7 + v166 Imm(0) -> x2 terminator Jmp(b22) (exit_acc=v165) block 22 start_pc=0 - v167 Phi { incoming=[b43:v159, b21:v165], kind=I64 } -> x13 - v168 LoadLocal { off=-25, kind=I64 } -> x0 + v167 Phi { incoming=[b41:v159, b21:v165], kind=I64 } -> x7 + v168 LoadLocal { off=-25, kind=I64 } -> x2 terminator Bz { cond=v167, target=b24, fall=b23 } (exit_acc=v167) block 23 start_pc=0 v169 ImmData(167) -> x7 @@ -241,44 +241,44 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v179 Imm(5) -> x0 terminator Return(v179) (exit_acc=v179) block 24 start_pc=0 - v180 LocalAddr(-11) -> x0 - v181 ImmData(186) -> x1 - v182 Mcpy { dst=v180, src=v181, size=12 } -> x0 - v183 LoadLocal { off=-1, kind=I32 } -> x0 - v184 LocalAddr(-11) -> x0 + v180 LocalAddr(-11) -> x2 + v181 ImmData(186) -> x6 + v182 Mcpy { dst=v180, src=v181, size=12 } -> x2 + v183 LoadLocal { off=-1, kind=I32 } -> x2 + v184 LocalAddr(-11) -> x2 v185 Store { addr=v184, disp=0, value=v1, kind=I32 } -> - v186 LoadLocal { off=-2, kind=I32 } -> x0 v187 LocalAddr(-11) -> x0 - v188 BinopI { op=add, lhs=v187, rhs_imm=8 } -> x1 + v188 BinopI { op=add, lhs=v187, rhs_imm=8 } -> x2 v189 Store { addr=v187, disp=8, value=v3, kind=I32 } -> - v190 LocalAddr(-11) -> x0 v191 Load { addr=v190, disp=0, kind=I32 } -> x0 v192 BinopI { op=ne, lhs=v191, rhs_imm=42 } -> x0 - v193 Imm(1) -> x3 - v194 Imm(0) -> x1 - terminator Bnz { cond=v192, target=b44, fall=b25 } (exit_acc=v192) + v193 Imm(1) -> x6 + v194 Imm(0) -> x2 + terminator Bnz { cond=v192, target=b40, fall=b25 } (exit_acc=v192) block 25 start_pc=0 v195 LocalAddr(-11) -> x0 - v196 BinopI { op=add, lhs=v195, rhs_imm=4 } -> x1 + v196 BinopI { op=add, lhs=v195, rhs_imm=4 } -> x2 v197 Load { addr=v195, disp=4, kind=I32 } -> x0 v198 BinopI { op=ne, lhs=v197, rhs_imm=0 } -> x0 - v199 BinopI { op=ne, lhs=v198, rhs_imm=0 } -> x3 + v199 BinopI { op=ne, lhs=v198, rhs_imm=0 } -> x6 v200 Imm(0) -> x0 terminator Jmp(b26) (exit_acc=v199) block 26 start_pc=0 - v201 Phi { incoming=[b44:v193, b25:v199], kind=I64 } -> x3 + v201 Phi { incoming=[b40:v193, b25:v199], kind=I64 } -> x6 v202 LoadLocal { off=-28, kind=I64 } -> x0 v203 Imm(0) -> x0 - terminator Bnz { cond=v201, target=b45, fall=b27 } (exit_acc=v201) + terminator Bnz { cond=v201, target=b39, fall=b27 } (exit_acc=v201) block 27 start_pc=0 v204 LocalAddr(-11) -> x0 - v205 BinopI { op=add, lhs=v204, rhs_imm=8 } -> x1 + v205 BinopI { op=add, lhs=v204, rhs_imm=8 } -> x2 v206 Load { addr=v204, disp=8, kind=I32 } -> x0 - v207 BinopI { op=ne, lhs=v206, rhs_imm=99 } -> x3 + v207 BinopI { op=ne, lhs=v206, rhs_imm=99 } -> x6 v208 Imm(0) -> x0 terminator Jmp(b28) (exit_acc=v207) block 28 start_pc=0 - v209 Phi { incoming=[b45:v201, b27:v207], kind=I64 } -> x3 + v209 Phi { incoming=[b39:v201, b27:v207], kind=I64 } -> x6 v210 LoadLocal { off=-27, kind=I64 } -> x0 terminator Bz { cond=v209, target=b30, fall=b29 } (exit_acc=v209) block 29 start_pc=0 @@ -296,45 +296,45 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 terminator Return(v221) (exit_acc=v221) block 30 start_pc=0 v222 LocalAddr(-13) -> x0 - v223 ImmData(217) -> x1 + v223 ImmData(217) -> x2 v224 Mcpy { dst=v222, src=v223, size=12 } -> x0 v225 LocalAddr(-13) -> x0 v226 BinopI { op=and, lhs=v225, rhs_imm=255 } -> x0 v227 LocalAddr(-15) -> x0 - v228 ImmData(229) -> x1 + v228 ImmData(229) -> x2 v229 Mcpy { dst=v227, src=v228, size=12 } -> x0 v230 LoadLocal { off=-2, kind=I32 } -> x0 v231 LocalAddr(-15) -> x0 - v232 BinopI { op=add, lhs=v231, rhs_imm=4 } -> x1 + v232 BinopI { op=add, lhs=v231, rhs_imm=4 } -> x2 v233 Store { addr=v231, disp=4, value=v3, kind=I32 } -> - v234 LocalAddr(-15) -> x0 v235 Load { addr=v234, disp=0, kind=I32 } -> x0 v236 BinopI { op=ne, lhs=v235, rhs_imm=0 } -> x0 - v237 Imm(1) -> x3 + v237 Imm(1) -> x2 v238 Imm(0) -> x1 - terminator Bnz { cond=v236, target=b46, fall=b31 } (exit_acc=v236) + terminator Bnz { cond=v236, target=b38, fall=b31 } (exit_acc=v236) block 31 start_pc=0 v239 LocalAddr(-15) -> x0 v240 BinopI { op=add, lhs=v239, rhs_imm=4 } -> x1 v241 Load { addr=v239, disp=4, kind=I32 } -> x0 v242 BinopI { op=ne, lhs=v241, rhs_imm=99 } -> x0 - v243 BinopI { op=ne, lhs=v242, rhs_imm=0 } -> x3 + v243 BinopI { op=ne, lhs=v242, rhs_imm=0 } -> x2 v244 Imm(0) -> x0 terminator Jmp(b32) (exit_acc=v243) block 32 start_pc=0 - v245 Phi { incoming=[b46:v237, b31:v243], kind=I64 } -> x3 + v245 Phi { incoming=[b38:v237, b31:v243], kind=I64 } -> x2 v246 LoadLocal { off=-30, kind=I64 } -> x0 v247 Imm(0) -> x0 - terminator Bnz { cond=v245, target=b47, fall=b33 } (exit_acc=v245) + terminator Bnz { cond=v245, target=b37, fall=b33 } (exit_acc=v245) block 33 start_pc=0 v248 LocalAddr(-15) -> x0 v249 BinopI { op=add, lhs=v248, rhs_imm=8 } -> x1 v250 Load { addr=v248, disp=8, kind=I32 } -> x0 - v251 BinopI { op=ne, lhs=v250, rhs_imm=0 } -> x3 + v251 BinopI { op=ne, lhs=v250, rhs_imm=0 } -> x2 v252 Imm(0) -> x0 terminator Jmp(b34) (exit_acc=v251) block 34 start_pc=0 - v253 Phi { incoming=[b47:v245, b33:v251], kind=I64 } -> x3 + v253 Phi { incoming=[b37:v245, b33:v251], kind=I64 } -> x2 v254 LoadLocal { off=-29, kind=I64 } -> x0 terminator Bz { cond=v253, target=b36, fall=b35 } (exit_acc=v253) block 35 start_pc=0 @@ -354,27 +354,27 @@ fn ent_pc=2 n_params=0 variadic=false locals=30 v266 Imm(0) -> x0 terminator Return(v266) (exit_acc=v266) block 37 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b34) block 38 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b32) block 39 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b28) block 40 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b26) block 41 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b22) block 42 start_pc=0 terminator Jmp(b20) block 43 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b16) block 44 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b14) block 45 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b10) block 46 start_pc=0 - terminator Jmp(b32) + terminator Jmp(b6) block 47 start_pc=0 - terminator Jmp(b34) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa index cd0d1043c..9aa088703 100644 --- a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa +++ b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa @@ -1,71 +1,14 @@ -; --- SSA dump (ok=true) ent_pc=1 --- -; name=__c5_assert_fail -fn ent_pc=1 n_params=3 variadic=false locals=4 - spill_count=0 gpr_used=[3] fp_used=[] - block 0 start_pc=0 - v0 AllocaInit(0) -> - - v1 ParamRef(0, kind=I64) -> x7 - v2 Imm(0) -> x0 - v3 ParamRef(1, kind=I64) -> x6 - v4 Imm(0) -> x0 - v5 ParamRef(2, kind=I32) -> x2 - v6 Imm(0) -> x0 - v7 ImmData(36) -> x0 - v8 LoadLocal { off=2, kind=I64 } -> x1 - v9 LoadLocal { off=3, kind=I64 } -> x1 - v10 LoadLocal { off=4, kind=I32 } -> x1 - v11 CallExt { binding_idx=0, args=[v7, v1, v3, v5], fp_arg_mask=0x0 } -> x0 - v12 Imm(0) -> x3 - v13 CallExt { binding_idx=37, args=[v12], fp_arg_mask=0x0 } -> x0 - v14 Intrinsic { kind=10, args=[] } -> x0 - terminator Return(v12) (exit_acc=v12) +object_macro_to_fn_macro_rescan.c:18: warning: unused variable `x` ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main -fn ent_pc=2 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3] fp_used=[] +fn ent_pc=2 n_params=0 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(7) -> x3 + v1 Imm(7) -> x0 v2 Imm(0) -> x0 - v3 LoadLocal { off=-1, kind=I32 } -> x0 - v4 BinopI { op=eq, lhs=v1, rhs_imm=7 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) - block 1 start_pc=0 - v5 Imm(0) -> x1 - v6 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 2 start_pc=0 - v7 ImmData(76) -> x7 - v8 ImmData(83) -> x6 - v9 Imm(19) -> x2 - v10 Call { target_pc=1, args=[v7, v8, v9], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v10) - block 3 start_pc=0 - v12 Phi { incoming=[b1:v5, b2:v10], kind=I64 } -> x1 - v13 LoadLocal { off=-5, kind=I64 } -> x0 - v14 LoadLocal { off=-1, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 - v17 Extend { value=v15, kind=I32 } -> x0 - v18 BinopI { op=eq, lhs=v17, rhs_imm=8 } -> x0 - terminator Bz { cond=v18, target=b5, fall=b4 } (exit_acc=v18) - block 4 start_pc=0 - v19 Imm(0) -> x1 - v20 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v19) - block 5 start_pc=0 - v21 ImmData(162) -> x7 - v22 ImmData(173) -> x6 - v23 Imm(20) -> x2 - v24 Call { target_pc=1, args=[v21, v22, v23], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v24) - block 6 start_pc=0 - v26 Phi { incoming=[b4:v19, b5:v24], kind=I64 } -> x1 - v27 LoadLocal { off=-6, kind=I64 } -> x0 - v28 Imm(0) -> x0 - terminator Return(v28) (exit_acc=v28) + v3 Imm(0) -> x0 + terminator Return(v3) (exit_acc=v3) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/octal_literal.ssa b/tests/snapshots/ssa/octal_literal.ssa index 28168895f..a69ead8dc 100644 --- a/tests/snapshots/ssa/octal_literal.ssa +++ b/tests/snapshots/ssa/octal_literal.ssa @@ -5,58 +5,58 @@ fn ent_pc=5 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(484) -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v12) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v14 Imm(384) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v15) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v17 Imm(-421) -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v18) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v20 Imm(42) -> x0 + terminator Return(v20) (exit_acc=v20) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 10 start_pc=0 - v11 Imm(484) -> x0 - v12 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v12) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 11 start_pc=0 - v13 Imm(6) -> x0 - terminator Return(v13) (exit_acc=v13) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 12 start_pc=0 - v14 Imm(384) -> x0 - v15 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v15) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 13 start_pc=0 - v16 Imm(7) -> x0 - terminator Return(v16) (exit_acc=v16) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 14 start_pc=0 - v17 Imm(-421) -> x0 - v18 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v18) + v13 Imm(6) -> x0 + terminator Return(v13) (exit_acc=v13) block 15 start_pc=0 + v16 Imm(7) -> x0 + terminator Return(v16) (exit_acc=v16) + block 16 start_pc=0 v19 Imm(8) -> x0 terminator Return(v19) (exit_acc=v19) - block 16 start_pc=0 - v20 Imm(42) -> x0 - terminator Return(v20) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/optimizer_fp_arg_mask_remap.ssa b/tests/snapshots/ssa/optimizer_fp_arg_mask_remap.ssa index c602118fd..886c8bb0e 100644 --- a/tests/snapshots/ssa/optimizer_fp_arg_mask_remap.ssa +++ b/tests/snapshots/ssa/optimizer_fp_arg_mask_remap.ssa @@ -22,7 +22,7 @@ fn ent_pc=14 n_params=0 variadic=false locals=9 v16 Imm(4602300516803947790) -> x0 v17 Binop { op=flt, lhs=v4, rhs=v16 } -> x1 v18 Imm(0) -> x0 - terminator Bnz { cond=v17, target=b15, fall=b1 } (exit_acc=v17) + terminator Bnz { cond=v17, target=b17, fall=b1 } (exit_acc=v17) block 1 start_pc=0 v19 LoadLocal { off=-2, kind=F64 } -> d1 v20 Imm(4602318531202457272) -> x0 @@ -30,7 +30,7 @@ fn ent_pc=14 n_params=0 variadic=false locals=9 v22 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 - v23 Phi { incoming=[b15:v17, b1:v21], kind=I64 } -> x1 + v23 Phi { incoming=[b17:v17, b1:v21], kind=I64 } -> x1 v24 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 @@ -68,7 +68,7 @@ fn ent_pc=14 n_params=0 variadic=false locals=9 v42 Imm(4607173411600762667) -> x0 v43 Binop { op=flt, lhs=v13, rhs=v42 } -> x1 v44 Imm(0) -> x0 - terminator Bnz { cond=v43, target=b17, fall=b11 } (exit_acc=v43) + terminator Bnz { cond=v43, target=b15, fall=b11 } (exit_acc=v43) block 11 start_pc=0 v45 LoadLocal { off=-5, kind=F64 } -> d1 v46 Imm(4607186922399644778) -> x0 @@ -76,7 +76,7 @@ fn ent_pc=14 n_params=0 variadic=false locals=9 v48 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v47) block 12 start_pc=0 - v49 Phi { incoming=[b17:v43, b11:v47], kind=I64 } -> x1 + v49 Phi { incoming=[b15:v43, b11:v47], kind=I64 } -> x1 v50 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v49, target=b14, fall=b13 } (exit_acc=v49) block 13 start_pc=0 @@ -86,11 +86,11 @@ fn ent_pc=14 n_params=0 variadic=false locals=9 v52 Imm(19) -> x0 terminator Return(v52) (exit_acc=v52) block 15 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b12) block 16 start_pc=0 terminator Jmp(b6) block 17 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/out_pointer_return_float_args.ssa b/tests/snapshots/ssa/out_pointer_return_float_args.ssa index 4ddff7ed4..bc4876be0 100644 --- a/tests/snapshots/ssa/out_pointer_return_float_args.ssa +++ b/tests/snapshots/ssa/out_pointer_return_float_args.ssa @@ -92,245 +92,227 @@ fn ent_pc=2 n_params=4 variadic=false locals=3 ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=43 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x3 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4611686018427387904) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d1 [f32] - v5 Imm(4613937818241073152) -> x0 - v6 FpCast { kind=F64ToF32, value=v5 } -> d2 [f32] - v7 Imm(4616189618054758400) -> x0 - v8 FpCast { kind=F64ToF32, value=v7 } -> d3 [f32] - v9 Call { target_pc=0, args=[v2, v4, v6, v8], fixed_args=4, fp_return=false, fp_arg_mask=0xf } -> x0 - v10 LocalAddr(-21) -> x0 - v11 LocalAddr(-2) -> x1 - v12 Mcpy { dst=v11, src=v10, size=16 } -> x0 - v13 LocalAddr(-2) -> x0 - v14 Load { addr=v13, disp=0, kind=F32 } -> d0 [f32] - v15 FpCast { kind=F32ToF64, value=v14 } -> d0 - v16 Binop { op=fne, lhs=v15, rhs=v1 } -> x0 - v17 Imm(1) -> x3 - v18 Imm(0) -> x1 - terminator Bnz { cond=v16, target=b25, fall=b1 } (exit_acc=v16) + v1 Imm(1065353216) -> x3 [f32] + v2 Imm(1073741824) -> x6 [f32] + v3 Imm(1077936128) -> x2 [f32] + v4 Imm(1082130432) -> x1 [f32] + v5 Call { target_pc=0, args=[v1, v2, v3, v4], fixed_args=4, fp_return=false, fp_arg_mask=0xf } -> x0 + v6 LocalAddr(-21) -> x0 + v7 LocalAddr(-2) -> x1 + v8 Mcpy { dst=v7, src=v6, size=16 } -> x0 + v9 LocalAddr(-2) -> x0 + v10 Load { addr=v9, disp=0, kind=F32 } -> d0 [f32] + v11 Binop { op=fne, lhs=v10, rhs=v1 } -> x0 + v12 Imm(1) -> x2 + v13 Imm(0) -> x1 + terminator Bnz { cond=v11, target=b33, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v19 LocalAddr(-2) -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x1 - v21 Load { addr=v19, disp=4, kind=F32 } -> d0 [f32] - v22 Imm(4611686018427387904) -> x0 - v23 FpCast { kind=F32ToF64, value=v21 } -> d0 - v24 Binop { op=fne, lhs=v23, rhs=v22 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x3 - v26 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v25) + v14 LocalAddr(-2) -> x0 + v15 BinopI { op=add, lhs=v14, rhs_imm=4 } -> x1 + v16 Load { addr=v14, disp=4, kind=F32 } -> d0 [f32] + v17 Imm(1073741824) -> x0 [f32] + v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 + v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x2 + v20 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v27 Phi { incoming=[b25:v17, b1:v25], kind=I64 } -> x3 - v28 LoadLocal { off=-24, kind=I64 } -> x0 - v29 Imm(1) -> x12 - v30 Imm(0) -> x0 - terminator Bnz { cond=v27, target=b26, fall=b3 } (exit_acc=v27) + v21 Phi { incoming=[b33:v12, b1:v19], kind=I64 } -> x2 + v22 LoadLocal { off=-24, kind=I64 } -> x0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Bnz { cond=v21, target=b32, fall=b3 } (exit_acc=v21) block 3 start_pc=0 - v31 LocalAddr(-2) -> x0 - v32 BinopI { op=add, lhs=v31, rhs_imm=8 } -> x1 - v33 Load { addr=v31, disp=8, kind=F32 } -> d0 [f32] - v34 Imm(4613937818241073152) -> x0 - v35 FpCast { kind=F32ToF64, value=v33 } -> d0 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=0 } -> x12 - v38 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v37) + v25 LocalAddr(-2) -> x0 + v26 BinopI { op=add, lhs=v25, rhs_imm=8 } -> x1 + v27 Load { addr=v25, disp=8, kind=F32 } -> d0 [f32] + v28 Imm(1077936128) -> x0 [f32] + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + v30 BinopI { op=ne, lhs=v29, rhs_imm=0 } -> x1 + v31 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v30) block 4 start_pc=0 - v39 Phi { incoming=[b26:v29, b3:v37], kind=I64 } -> x12 - v40 LoadLocal { off=-23, kind=I64 } -> x0 - v41 Imm(0) -> x0 - terminator Bnz { cond=v39, target=b27, fall=b5 } (exit_acc=v39) + v32 Phi { incoming=[b32:v23, b3:v30], kind=I64 } -> x1 + v33 LoadLocal { off=-23, kind=I64 } -> x0 + v34 Imm(0) -> x0 + terminator Bnz { cond=v32, target=b31, fall=b5 } (exit_acc=v32) block 5 start_pc=0 - v42 LocalAddr(-2) -> x0 - v43 BinopI { op=add, lhs=v42, rhs_imm=12 } -> x1 - v44 Load { addr=v42, disp=12, kind=F32 } -> d0 [f32] - v45 Imm(4616189618054758400) -> x0 - v46 FpCast { kind=F32ToF64, value=v44 } -> d0 - v47 Binop { op=fne, lhs=v46, rhs=v45 } -> x12 - v48 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v47) + v35 LocalAddr(-2) -> x0 + v36 BinopI { op=add, lhs=v35, rhs_imm=12 } -> x1 + v37 Load { addr=v35, disp=12, kind=F32 } -> d0 [f32] + v38 Imm(1082130432) -> x0 [f32] + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x1 + v40 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v39) block 6 start_pc=0 - v49 Phi { incoming=[b27:v39, b5:v47], kind=I64 } -> x12 - v50 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v49, target=b8, fall=b7 } (exit_acc=v49) + v41 Phi { incoming=[b31:v32, b5:v39], kind=I64 } -> x1 + v42 LoadLocal { off=-22, kind=I64 } -> x0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) block 7 start_pc=0 - v51 Imm(1) -> x0 - terminator Return(v51) (exit_acc=v51) + v43 Imm(1) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v52 LocalAddr(-27) -> x7 - v53 Imm(0) -> x0 - v54 LoadLocal { off=-28, kind=I64 } -> x0 - v55 Imm(4609434218613702656) -> x3 - v56 FpCast { kind=F64ToF32, value=v55 } -> d0 [f32] - v57 FpCast { kind=F32ToF64, value=v56 } -> d0 - v58 StoreLocal { off=-29, value=v57, kind=I64 } -> - - v59 LoadLocal { off=-29, kind=I64 } -> x6 - v60 Imm(4612811918334230528) -> x0 - v61 FpCast { kind=F64ToF32, value=v60 } -> d0 [f32] - v62 FpCast { kind=F32ToF64, value=v61 } -> d0 - v63 StoreLocal { off=-30, value=v62, kind=I64 } -> - - v64 LoadLocal { off=-30, kind=I64 } -> x2 - v65 Imm(4615063718147915776) -> x0 - v66 FpCast { kind=F64ToF32, value=v65 } -> d0 [f32] - v67 FpCast { kind=F32ToF64, value=v66 } -> d0 - v68 StoreLocal { off=-31, value=v67, kind=I64 } -> - - v69 LoadLocal { off=-31, kind=I64 } -> x1 - v70 Imm(4616752568008179712) -> x0 - v71 FpCast { kind=F64ToF32, value=v70 } -> d0 [f32] - v72 FpCast { kind=F32ToF64, value=v71 } -> d0 - v73 StoreLocal { off=-32, value=v72, kind=I64 } -> - - v74 LoadLocal { off=-32, kind=I64 } -> x8 - v75 Imm(4617878467915022336) -> x0 - v76 FpCast { kind=F64ToF32, value=v75 } -> d0 [f32] - v77 FpCast { kind=F32ToF64, value=v76 } -> d0 - v78 StoreLocal { off=-33, value=v77, kind=I64 } -> - - v79 LoadLocal { off=-33, kind=I64 } -> x9 - v80 Call { target_pc=1, args=[v52, v59, v64, v69, v74, v79], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 - v81 LocalAddr(-27) -> x0 - v82 LocalAddr(-7) -> x1 - v83 Mcpy { dst=v82, src=v81, size=20 } -> x0 - v84 LocalAddr(-7) -> x0 - v85 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] - v86 FpCast { kind=F32ToF64, value=v85 } -> d0 - v87 Binop { op=fne, lhs=v86, rhs=v55 } -> x0 - v88 Imm(1) -> x3 - v89 Imm(0) -> x1 - terminator Bnz { cond=v87, target=b28, fall=b9 } (exit_acc=v87) + v44 LocalAddr(-27) -> x7 + v45 Imm(0) -> x0 + v46 LoadLocal { off=-28, kind=I64 } -> x0 + v47 Imm(1069547520) -> x3 [f32] + v48 FpCast { kind=F32ToF64, value=v47 } -> d0 + v49 StoreLocal { off=-29, value=v48, kind=I64 } -> - + v50 LoadLocal { off=-29, kind=I64 } -> x0 + v51 Imm(1075838976) -> x0 [f32] + v52 FpCast { kind=F32ToF64, value=v51 } -> d1 + v53 StoreLocal { off=-30, value=v52, kind=I64 } -> - + v54 LoadLocal { off=-30, kind=I64 } -> x0 + v55 Imm(1080033280) -> x0 [f32] + v56 FpCast { kind=F32ToF64, value=v55 } -> d2 + v57 StoreLocal { off=-31, value=v56, kind=I64 } -> - + v58 LoadLocal { off=-31, kind=I64 } -> x0 + v59 Imm(1083179008) -> x0 [f32] + v60 FpCast { kind=F32ToF64, value=v59 } -> d3 + v61 StoreLocal { off=-32, value=v60, kind=I64 } -> - + v62 LoadLocal { off=-32, kind=I64 } -> x0 + v63 Imm(1085276160) -> x0 [f32] + v64 FpCast { kind=F32ToF64, value=v63 } -> d4 + v65 StoreLocal { off=-33, value=v64, kind=I64 } -> - + v66 LoadLocal { off=-33, kind=I64 } -> x0 + v67 Call { target_pc=1, args=[v44, v48, v52, v56, v60, v64], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 + v68 LocalAddr(-27) -> x0 + v69 LocalAddr(-7) -> x1 + v70 Mcpy { dst=v69, src=v68, size=20 } -> x0 + v71 LocalAddr(-7) -> x0 + v72 Load { addr=v71, disp=0, kind=F32 } -> d0 [f32] + v73 Binop { op=fne, lhs=v72, rhs=v47 } -> x0 + v74 Imm(1) -> x2 + v75 Imm(0) -> x1 + terminator Bnz { cond=v73, target=b30, fall=b9 } (exit_acc=v73) block 9 start_pc=0 - v90 LocalAddr(-7) -> x0 - v91 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x1 - v92 Load { addr=v90, disp=4, kind=F32 } -> d0 [f32] - v93 Imm(4612811918334230528) -> x0 - v94 FpCast { kind=F32ToF64, value=v92 } -> d0 - v95 Binop { op=fne, lhs=v94, rhs=v93 } -> x0 - v96 BinopI { op=ne, lhs=v95, rhs_imm=0 } -> x3 - v97 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v96) + v76 LocalAddr(-7) -> x0 + v77 BinopI { op=add, lhs=v76, rhs_imm=4 } -> x1 + v78 Load { addr=v76, disp=4, kind=F32 } -> d0 [f32] + v79 Imm(1075838976) -> x0 [f32] + v80 Binop { op=fne, lhs=v78, rhs=v79 } -> x0 + v81 BinopI { op=ne, lhs=v80, rhs_imm=0 } -> x2 + v82 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v81) block 10 start_pc=0 - v98 Phi { incoming=[b28:v88, b9:v96], kind=I64 } -> x3 - v99 LoadLocal { off=-37, kind=I64 } -> x0 - v100 Imm(1) -> x12 - v101 Imm(0) -> x0 - terminator Bnz { cond=v98, target=b29, fall=b11 } (exit_acc=v98) + v83 Phi { incoming=[b30:v74, b9:v81], kind=I64 } -> x2 + v84 LoadLocal { off=-37, kind=I64 } -> x0 + v85 Imm(1) -> x1 + v86 Imm(0) -> x0 + terminator Bnz { cond=v83, target=b29, fall=b11 } (exit_acc=v83) block 11 start_pc=0 - v102 LocalAddr(-7) -> x0 - v103 BinopI { op=add, lhs=v102, rhs_imm=8 } -> x1 - v104 Load { addr=v102, disp=8, kind=F32 } -> d0 [f32] - v105 Imm(4615063718147915776) -> x0 - v106 FpCast { kind=F32ToF64, value=v104 } -> d0 - v107 Binop { op=fne, lhs=v106, rhs=v105 } -> x0 - v108 BinopI { op=ne, lhs=v107, rhs_imm=0 } -> x12 - v109 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v108) + v87 LocalAddr(-7) -> x0 + v88 BinopI { op=add, lhs=v87, rhs_imm=8 } -> x1 + v89 Load { addr=v87, disp=8, kind=F32 } -> d0 [f32] + v90 Imm(1080033280) -> x0 [f32] + v91 Binop { op=fne, lhs=v89, rhs=v90 } -> x0 + v92 BinopI { op=ne, lhs=v91, rhs_imm=0 } -> x1 + v93 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v92) block 12 start_pc=0 - v110 Phi { incoming=[b29:v100, b11:v108], kind=I64 } -> x12 - v111 LoadLocal { off=-36, kind=I64 } -> x0 - v112 Imm(1) -> x3 - v113 Imm(0) -> x0 - terminator Bnz { cond=v110, target=b30, fall=b13 } (exit_acc=v110) + v94 Phi { incoming=[b29:v85, b11:v92], kind=I64 } -> x1 + v95 LoadLocal { off=-36, kind=I64 } -> x0 + v96 Imm(1) -> x2 + v97 Imm(0) -> x0 + terminator Bnz { cond=v94, target=b28, fall=b13 } (exit_acc=v94) block 13 start_pc=0 - v114 LocalAddr(-7) -> x0 - v115 BinopI { op=add, lhs=v114, rhs_imm=12 } -> x1 - v116 Load { addr=v114, disp=12, kind=F32 } -> d0 [f32] - v117 Imm(4616752568008179712) -> x0 - v118 FpCast { kind=F32ToF64, value=v116 } -> d0 - v119 Binop { op=fne, lhs=v118, rhs=v117 } -> x0 - v120 BinopI { op=ne, lhs=v119, rhs_imm=0 } -> x3 - v121 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v120) + v98 LocalAddr(-7) -> x0 + v99 BinopI { op=add, lhs=v98, rhs_imm=12 } -> x1 + v100 Load { addr=v98, disp=12, kind=F32 } -> d0 [f32] + v101 Imm(1083179008) -> x0 [f32] + v102 Binop { op=fne, lhs=v100, rhs=v101 } -> x0 + v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x2 + v104 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v103) block 14 start_pc=0 - v122 Phi { incoming=[b30:v112, b13:v120], kind=I64 } -> x3 - v123 LoadLocal { off=-35, kind=I64 } -> x0 - v124 Imm(0) -> x0 - terminator Bnz { cond=v122, target=b31, fall=b15 } (exit_acc=v122) + v105 Phi { incoming=[b28:v96, b13:v103], kind=I64 } -> x2 + v106 LoadLocal { off=-35, kind=I64 } -> x0 + v107 Imm(0) -> x0 + terminator Bnz { cond=v105, target=b27, fall=b15 } (exit_acc=v105) block 15 start_pc=0 - v125 LocalAddr(-7) -> x0 - v126 BinopI { op=add, lhs=v125, rhs_imm=16 } -> x1 - v127 Load { addr=v125, disp=16, kind=F32 } -> d0 [f32] - v128 Imm(4617878467915022336) -> x0 - v129 FpCast { kind=F32ToF64, value=v127 } -> d0 - v130 Binop { op=fne, lhs=v129, rhs=v128 } -> x3 - v131 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v130) + v108 LocalAddr(-7) -> x0 + v109 BinopI { op=add, lhs=v108, rhs_imm=16 } -> x1 + v110 Load { addr=v108, disp=16, kind=F32 } -> d0 [f32] + v111 Imm(1085276160) -> x0 [f32] + v112 Binop { op=fne, lhs=v110, rhs=v111 } -> x2 + v113 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v112) block 16 start_pc=0 - v132 Phi { incoming=[b31:v122, b15:v130], kind=I64 } -> x3 - v133 LoadLocal { off=-34, kind=I64 } -> x0 - terminator Bz { cond=v132, target=b18, fall=b17 } (exit_acc=v132) + v114 Phi { incoming=[b27:v105, b15:v112], kind=I64 } -> x2 + v115 LoadLocal { off=-34, kind=I64 } -> x0 + terminator Bz { cond=v114, target=b18, fall=b17 } (exit_acc=v114) block 17 start_pc=0 - v134 Imm(2) -> x0 - terminator Return(v134) (exit_acc=v134) + v116 Imm(2) -> x0 + terminator Return(v116) (exit_acc=v116) block 18 start_pc=0 - v135 LocalAddr(-40) -> x7 - v136 Imm(0) -> x0 - v137 LoadLocal { off=-41, kind=I64 } -> x0 - v138 Imm(4621819117588971520) -> x3 - v139 Imm(4626322717216342016) -> x2 - v140 Imm(4629137466983448576) -> x1 - v141 Call { target_pc=2, args=[v135, v138, v139, v140], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v142 LocalAddr(-40) -> x0 - v143 LocalAddr(-13) -> x1 - v144 Mcpy { dst=v143, src=v142, size=24 } -> x0 - v145 LocalAddr(-13) -> x0 - v146 Load { addr=v145, disp=0, kind=F64 } -> d0 - v147 Binop { op=fne, lhs=v146, rhs=v138 } -> x0 - v148 Imm(1) -> x2 - v149 Imm(0) -> x1 - terminator Bnz { cond=v147, target=b32, fall=b19 } (exit_acc=v147) + v117 LocalAddr(-40) -> x7 + v118 Imm(0) -> x0 + v119 LoadLocal { off=-41, kind=I64 } -> x0 + v120 Imm(4621819117588971520) -> x3 + v121 Imm(4626322717216342016) -> x2 + v122 Imm(4629137466983448576) -> x1 + v123 Call { target_pc=2, args=[v117, v120, v121, v122], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v124 LocalAddr(-40) -> x0 + v125 LocalAddr(-13) -> x1 + v126 Mcpy { dst=v125, src=v124, size=24 } -> x0 + v127 LocalAddr(-13) -> x0 + v128 Load { addr=v127, disp=0, kind=F64 } -> d0 + v129 Binop { op=fne, lhs=v128, rhs=v120 } -> x0 + v130 Imm(1) -> x2 + v131 Imm(0) -> x1 + terminator Bnz { cond=v129, target=b26, fall=b19 } (exit_acc=v129) block 19 start_pc=0 - v150 LocalAddr(-13) -> x0 - v151 BinopI { op=add, lhs=v150, rhs_imm=8 } -> x1 - v152 Load { addr=v150, disp=8, kind=F64 } -> d0 - v153 Imm(4626322717216342016) -> x0 - v154 Binop { op=fne, lhs=v152, rhs=v153 } -> x0 - v155 BinopI { op=ne, lhs=v154, rhs_imm=0 } -> x2 - v156 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v155) + v132 LocalAddr(-13) -> x0 + v133 BinopI { op=add, lhs=v132, rhs_imm=8 } -> x1 + v134 Load { addr=v132, disp=8, kind=F64 } -> d0 + v135 Imm(4626322717216342016) -> x0 + v136 Binop { op=fne, lhs=v134, rhs=v135 } -> x0 + v137 BinopI { op=ne, lhs=v136, rhs_imm=0 } -> x2 + v138 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v137) block 20 start_pc=0 - v157 Phi { incoming=[b32:v148, b19:v155], kind=I64 } -> x2 - v158 LoadLocal { off=-43, kind=I64 } -> x0 - v159 Imm(0) -> x0 - terminator Bnz { cond=v157, target=b33, fall=b21 } (exit_acc=v157) + v139 Phi { incoming=[b26:v130, b19:v137], kind=I64 } -> x2 + v140 LoadLocal { off=-43, kind=I64 } -> x0 + v141 Imm(0) -> x0 + terminator Bnz { cond=v139, target=b25, fall=b21 } (exit_acc=v139) block 21 start_pc=0 - v160 LocalAddr(-13) -> x0 - v161 BinopI { op=add, lhs=v160, rhs_imm=16 } -> x1 - v162 Load { addr=v160, disp=16, kind=F64 } -> d0 - v163 Imm(4629137466983448576) -> x0 - v164 Binop { op=fne, lhs=v162, rhs=v163 } -> x2 - v165 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v164) + v142 LocalAddr(-13) -> x0 + v143 BinopI { op=add, lhs=v142, rhs_imm=16 } -> x1 + v144 Load { addr=v142, disp=16, kind=F64 } -> d0 + v145 Imm(4629137466983448576) -> x0 + v146 Binop { op=fne, lhs=v144, rhs=v145 } -> x2 + v147 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v146) block 22 start_pc=0 - v166 Phi { incoming=[b33:v157, b21:v164], kind=I64 } -> x2 - v167 LoadLocal { off=-42, kind=I64 } -> x0 - terminator Bz { cond=v166, target=b24, fall=b23 } (exit_acc=v166) + v148 Phi { incoming=[b25:v139, b21:v146], kind=I64 } -> x2 + v149 LoadLocal { off=-42, kind=I64 } -> x0 + terminator Bz { cond=v148, target=b24, fall=b23 } (exit_acc=v148) block 23 start_pc=0 - v168 Imm(3) -> x0 - terminator Return(v168) (exit_acc=v168) + v150 Imm(3) -> x0 + terminator Return(v150) (exit_acc=v150) block 24 start_pc=0 - v169 Imm(0) -> x0 - terminator Return(v169) (exit_acc=v169) + v151 Imm(0) -> x0 + terminator Return(v151) (exit_acc=v151) block 25 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b22) block 26 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b20) block 27 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 28 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b14) block 29 start_pc=0 terminator Jmp(b12) block 30 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b10) block 31 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 32 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b4) block 33 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/packed_bitfield_repack.ssa b/tests/snapshots/ssa/packed_bitfield_repack.ssa index b85f525bd..4311995f7 100644 --- a/tests/snapshots/ssa/packed_bitfield_repack.ssa +++ b/tests/snapshots/ssa/packed_bitfield_repack.ssa @@ -53,16 +53,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 terminator Return(v24) (exit_acc=v24) block 12 start_pc=0 v25 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v25) + terminator Jmp(b13) (exit_acc=v25) block 13 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) - block 14 start_pc=0 v27 LocalAddr(-1) -> x0 v28 Imm(85) -> x1 - v29 Load { addr=v27, disp=0, kind=U8 } -> x2 - v30 BinopI { op=and, lhs=v29, rhs_imm=-256 } -> x2 - v31 Binop { op=or, lhs=v30, rhs=v28 } -> x1 + v29 Load { addr=v27, disp=0, kind=U8 } -> x1 + v30 BinopI { op=and, lhs=v29, rhs_imm=-256 } -> x1 + v31 BinopI { op=or, lhs=v30, rhs_imm=85 } -> x1 v32 Store { addr=v27, disp=0, value=v31, kind=I8 } -> - v33 Imm(6124895493223874560) -> x0 v34 LocalAddr(-1) -> x0 @@ -76,27 +73,27 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v42 Extend { value=v40, kind=I8 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=85 } -> x1 v44 Imm(0) -> x0 - terminator Bnz { cond=v43, target=b39, fall=b15 } (exit_acc=v43) - block 15 start_pc=0 + terminator Bnz { cond=v43, target=b44, fall=b14 } (exit_acc=v43) + block 14 start_pc=0 v45 LocalAddr(-1) -> x0 v46 BinopI { op=add, lhs=v45, rhs_imm=1 } -> x1 v47 Load { addr=v45, disp=1, kind=I8 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=7 } -> x1 v49 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v48) - block 16 start_pc=0 - v50 Phi { incoming=[b39:v43, b15:v48], kind=I64 } -> x1 + terminator Jmp(b15) (exit_acc=v48) + block 15 start_pc=0 + v50 Phi { incoming=[b44:v43, b14:v48], kind=I64 } -> x1 v51 LoadLocal { off=-8, kind=I64 } -> x0 - terminator Bz { cond=v50, target=b18, fall=b17 } (exit_acc=v50) - block 17 start_pc=0 + terminator Bz { cond=v50, target=b17, fall=b16 } (exit_acc=v50) + block 16 start_pc=0 v52 Imm(5) -> x0 terminator Return(v52) (exit_acc=v52) - block 18 start_pc=0 + block 17 start_pc=0 v53 LocalAddr(-2) -> x0 v54 Imm(65000) -> x1 - v55 Load { addr=v53, disp=0, kind=U32 } -> x2 - v56 BinopI { op=and, lhs=v55, rhs_imm=-131072 } -> x2 - v57 Binop { op=or, lhs=v56, rhs=v54 } -> x1 + v55 Load { addr=v53, disp=0, kind=U32 } -> x1 + v56 BinopI { op=and, lhs=v55, rhs_imm=-131072 } -> x1 + v57 BinopI { op=or, lhs=v56, rhs_imm=65000 } -> x1 v58 Store { addr=v53, disp=0, value=v57, kind=I32 } -> - v59 Imm(9147936743096320000) -> x0 v60 LocalAddr(-2) -> x0 @@ -105,7 +102,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v63 Load { addr=v60, disp=2, kind=U16 } -> x1 v64 BinopI { op=and, lhs=v63, rhs_imm=-2047 } -> x1 v65 Imm(1000) -> x2 - v66 Binop { op=or, lhs=v64, rhs=v65 } -> x1 + v66 BinopI { op=or, lhs=v64, rhs_imm=1000 } -> x1 v67 Store { addr=v60, disp=2, value=v66, kind=I16 } -> - v68 Imm(9007199254740992000) -> x0 v69 LocalAddr(-2) -> x0 @@ -121,8 +118,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v79 BinopI { op=ne, lhs=v78, rhs_imm=65000 } -> x0 v80 Imm(1) -> x2 v81 Imm(0) -> x1 - terminator Bnz { cond=v79, target=b40, fall=b19 } (exit_acc=v79) - block 19 start_pc=0 + terminator Bnz { cond=v79, target=b43, fall=b18 } (exit_acc=v79) + block 18 start_pc=0 v82 LocalAddr(-2) -> x0 v83 BinopI { op=add, lhs=v82, rhs_imm=2 } -> x1 v84 Load { addr=v82, disp=2, kind=U16 } -> x0 @@ -133,32 +130,32 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v89 BinopI { op=ne, lhs=v88, rhs_imm=500 } -> x0 v90 BinopI { op=ne, lhs=v89, rhs_imm=0 } -> x2 v91 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v90) - block 20 start_pc=0 - v92 Phi { incoming=[b40:v80, b19:v90], kind=I64 } -> x2 + terminator Jmp(b19) (exit_acc=v90) + block 19 start_pc=0 + v92 Phi { incoming=[b43:v80, b18:v90], kind=I64 } -> x2 v93 LoadLocal { off=-10, kind=I64 } -> x0 v94 Imm(0) -> x0 - terminator Bnz { cond=v92, target=b41, fall=b21 } (exit_acc=v92) - block 21 start_pc=0 + terminator Bnz { cond=v92, target=b42, fall=b20 } (exit_acc=v92) + block 20 start_pc=0 v95 LocalAddr(-2) -> x0 v96 BinopI { op=add, lhs=v95, rhs_imm=4 } -> x1 v97 Load { addr=v95, disp=4, kind=I8 } -> x0 v98 BinopI { op=ne, lhs=v97, rhs_imm=9 } -> x2 v99 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v98) - block 22 start_pc=0 - v100 Phi { incoming=[b41:v92, b21:v98], kind=I64 } -> x2 + terminator Jmp(b21) (exit_acc=v98) + block 21 start_pc=0 + v100 Phi { incoming=[b42:v92, b20:v98], kind=I64 } -> x2 v101 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v100, target=b24, fall=b23 } (exit_acc=v100) - block 23 start_pc=0 + terminator Bz { cond=v100, target=b23, fall=b22 } (exit_acc=v100) + block 22 start_pc=0 v102 Imm(6) -> x0 terminator Return(v102) (exit_acc=v102) - block 24 start_pc=0 + block 23 start_pc=0 v103 LocalAddr(-3) -> x0 v104 Imm(3) -> x1 - v105 Load { addr=v103, disp=0, kind=U8 } -> x2 - v106 BinopI { op=and, lhs=v105, rhs_imm=-8 } -> x2 - v107 Binop { op=or, lhs=v106, rhs=v104 } -> x1 + v105 Load { addr=v103, disp=0, kind=U8 } -> x1 + v106 BinopI { op=and, lhs=v105, rhs_imm=-8 } -> x1 + v107 BinopI { op=or, lhs=v106, rhs_imm=3 } -> x1 v108 Store { addr=v103, disp=0, value=v107, kind=I8 } -> - v109 Imm(6917529027641081856) -> x0 v110 LocalAddr(-3) -> x0 @@ -166,7 +163,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v112 Load { addr=v110, disp=0, kind=U16 } -> x1 v113 BinopI { op=and, lhs=v112, rhs_imm=-1017 } -> x1 v114 Imm(480) -> x2 - v115 Binop { op=or, lhs=v113, rhs=v114 } -> x1 + v115 BinopI { op=or, lhs=v113, rhs_imm=480 } -> x1 v116 Store { addr=v110, disp=0, value=v115, kind=I16 } -> - v117 Imm(8646911284551352320) -> x0 v118 LocalAddr(-3) -> x0 @@ -182,8 +179,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v128 BinopI { op=ne, lhs=v127, rhs_imm=3 } -> x0 v129 Imm(1) -> x2 v130 Imm(0) -> x1 - terminator Bnz { cond=v128, target=b42, fall=b25 } (exit_acc=v128) - block 25 start_pc=0 + terminator Bnz { cond=v128, target=b41, fall=b24 } (exit_acc=v128) + block 24 start_pc=0 v131 LocalAddr(-3) -> x0 v132 Load { addr=v131, disp=0, kind=U16 } -> x0 v133 BinopI { op=shr, lhs=v132, rhs_imm=3 } -> x0 @@ -193,27 +190,27 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v137 BinopI { op=ne, lhs=v136, rhs_imm=60 } -> x0 v138 BinopI { op=ne, lhs=v137, rhs_imm=0 } -> x2 v139 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v138) - block 26 start_pc=0 - v140 Phi { incoming=[b42:v129, b25:v138], kind=I64 } -> x2 + terminator Jmp(b25) (exit_acc=v138) + block 25 start_pc=0 + v140 Phi { incoming=[b41:v129, b24:v138], kind=I64 } -> x2 v141 LoadLocal { off=-12, kind=I64 } -> x0 v142 Imm(0) -> x0 - terminator Bnz { cond=v140, target=b43, fall=b27 } (exit_acc=v140) - block 27 start_pc=0 + terminator Bnz { cond=v140, target=b40, fall=b26 } (exit_acc=v140) + block 26 start_pc=0 v143 LocalAddr(-3) -> x0 v144 BinopI { op=add, lhs=v143, rhs_imm=2 } -> x1 v145 Load { addr=v143, disp=2, kind=I8 } -> x0 v146 BinopI { op=ne, lhs=v145, rhs_imm=4 } -> x2 v147 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v146) - block 28 start_pc=0 - v148 Phi { incoming=[b43:v140, b27:v146], kind=I64 } -> x2 + terminator Jmp(b27) (exit_acc=v146) + block 27 start_pc=0 + v148 Phi { incoming=[b40:v140, b26:v146], kind=I64 } -> x2 v149 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v148, target=b30, fall=b29 } (exit_acc=v148) - block 29 start_pc=0 + terminator Bz { cond=v148, target=b29, fall=b28 } (exit_acc=v148) + block 28 start_pc=0 v150 Imm(7) -> x0 terminator Return(v150) (exit_acc=v150) - block 30 start_pc=0 + block 29 start_pc=0 v151 LocalAddr(-4) -> x0 v152 Imm(11) -> x1 v153 Store { addr=v151, disp=0, value=v152, kind=I8 } -> - @@ -221,17 +218,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v155 LocalAddr(-4) -> x0 v156 BinopI { op=add, lhs=v155, rhs_imm=1 } -> x0 v157 Imm(30000) -> x1 - v158 Load { addr=v156, disp=0, kind=U16 } -> x2 - v159 BinopI { op=and, lhs=v158, rhs_imm=-65536 } -> x2 - v160 Binop { op=or, lhs=v159, rhs=v157 } -> x1 + v158 Load { addr=v156, disp=0, kind=U16 } -> x1 + v159 BinopI { op=and, lhs=v158, rhs_imm=-65536 } -> x1 + v160 BinopI { op=or, lhs=v159, rhs_imm=30000 } -> x1 v161 Store { addr=v156, disp=0, value=v160, kind=I16 } -> - v162 Imm(8444249301319680000) -> x0 v163 LocalAddr(-4) -> x0 v164 Load { addr=v163, disp=0, kind=I8 } -> x0 v165 BinopI { op=ne, lhs=v164, rhs_imm=11 } -> x1 v166 Imm(0) -> x0 - terminator Bnz { cond=v165, target=b44, fall=b31 } (exit_acc=v165) - block 31 start_pc=0 + terminator Bnz { cond=v165, target=b39, fall=b30 } (exit_acc=v165) + block 30 start_pc=0 v167 LocalAddr(-4) -> x0 v168 BinopI { op=add, lhs=v167, rhs_imm=1 } -> x0 v169 Load { addr=v168, disp=0, kind=U16 } -> x0 @@ -239,53 +236,56 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v171 Extend { value=v169, kind=I16 } -> x0 v172 BinopI { op=ne, lhs=v171, rhs_imm=30000 } -> x1 v173 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v172) - block 32 start_pc=0 - v174 Phi { incoming=[b44:v165, b31:v172], kind=I64 } -> x1 + terminator Jmp(b31) (exit_acc=v172) + block 31 start_pc=0 + v174 Phi { incoming=[b39:v165, b30:v172], kind=I64 } -> x1 v175 LoadLocal { off=-13, kind=I64 } -> x0 - terminator Bz { cond=v174, target=b34, fall=b33 } (exit_acc=v174) - block 33 start_pc=0 + terminator Bz { cond=v174, target=b33, fall=b32 } (exit_acc=v174) + block 32 start_pc=0 v176 Imm(8) -> x0 terminator Return(v176) (exit_acc=v176) - block 34 start_pc=0 + block 33 start_pc=0 v177 ImmData(8) -> x0 v178 Load { addr=v177, disp=0, kind=U8 } -> x0 v179 BinopI { op=shl, lhs=v178, rhs_imm=56 } -> x1 v180 Extend { value=v178, kind=I8 } -> x0 v181 BinopI { op=ne, lhs=v180, rhs_imm=85 } -> x1 v182 Imm(0) -> x0 - terminator Bnz { cond=v181, target=b45, fall=b35 } (exit_acc=v181) - block 35 start_pc=0 + terminator Bnz { cond=v181, target=b38, fall=b34 } (exit_acc=v181) + block 34 start_pc=0 v183 ImmData(8) -> x0 v184 BinopI { op=add, lhs=v183, rhs_imm=1 } -> x1 v185 Load { addr=v183, disp=1, kind=I8 } -> x0 v186 BinopI { op=ne, lhs=v185, rhs_imm=7 } -> x1 v187 Imm(0) -> x0 - terminator Jmp(b36) (exit_acc=v186) - block 36 start_pc=0 - v188 Phi { incoming=[b45:v181, b35:v186], kind=I64 } -> x1 + terminator Jmp(b35) (exit_acc=v186) + block 35 start_pc=0 + v188 Phi { incoming=[b38:v181, b34:v186], kind=I64 } -> x1 v189 LoadLocal { off=-14, kind=I64 } -> x0 - terminator Bz { cond=v188, target=b38, fall=b37 } (exit_acc=v188) - block 37 start_pc=0 + terminator Bz { cond=v188, target=b37, fall=b36 } (exit_acc=v188) + block 36 start_pc=0 v190 Imm(9) -> x0 terminator Return(v190) (exit_acc=v190) - block 38 start_pc=0 + block 37 start_pc=0 v191 Imm(0) -> x0 terminator Return(v191) (exit_acc=v191) + block 38 start_pc=0 + terminator Jmp(b35) block 39 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b31) block 40 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b27) block 41 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b25) block 42 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b21) block 43 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b19) block 44 start_pc=0 - terminator Jmp(b32) + terminator Jmp(b15) block 45 start_pc=0 - terminator Jmp(b36) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/param_fp_before_int_pressure.ssa b/tests/snapshots/ssa/param_fp_before_int_pressure.ssa index c3680483f..1058d1910 100644 --- a/tests/snapshots/ssa/param_fp_before_int_pressure.ssa +++ b/tests/snapshots/ssa/param_fp_before_int_pressure.ssa @@ -72,70 +72,69 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 v2 StoreLocal { off=-1, value=v1, kind=I32 } -> - - v3 Imm(0) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 Imm(1) -> x0 - v6 Imm(2) -> x1 - v7 Imm(3) -> x2 - v8 LocalAddr(-1) -> x6 - v9 Imm(4) -> x7 - v10 Imm(5) -> x8 - v11 Extend { value=v5, kind=I32 } -> x9 - v12 Imm(0) -> x9 - v13 Extend { value=v6, kind=I32 } -> x9 - v14 Imm(0) -> x9 - v15 Extend { value=v7, kind=I32 } -> x9 - v16 Imm(0) -> x9 - v17 Imm(0) -> x9 - v18 Extend { value=v9, kind=I32 } -> x9 - v19 Imm(0) -> x9 - v20 Extend { value=v10, kind=I32 } -> x9 - v21 Imm(0) -> x9 - v22 Imm(0) -> x9 - v23 Imm(0) -> x9 - v24 FpCast { kind=F32ToF64, value=v4 } -> d1 - v25 FpCast { kind=FpToInt, value=v24 } -> x9 - v26 FpCast { kind=F32ToF64, value=v4 } -> d0 - v27 FpCast { kind=FpToInt, value=v26 } -> x9 - v28 BinopI { op=mul, lhs=v5, rhs_imm=100000 } -> x0 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x9 - v30 Extend { value=v28, kind=I32 } -> x9 - v31 BinopI { op=mul, lhs=v6, rhs_imm=10000 } -> x1 - v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x9 - v33 Extend { value=v31, kind=I32 } -> x9 - v34 Binop { op=add, lhs=v28, rhs=v31 } -> x0 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x1 - v36 Extend { value=v34, kind=I32 } -> x1 - v37 BinopI { op=mul, lhs=v7, rhs_imm=1000 } -> x1 - v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x2 - v39 Extend { value=v37, kind=I32 } -> x2 - v40 Binop { op=add, lhs=v34, rhs=v37 } -> x0 - v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x1 - v42 Extend { value=v40, kind=I32 } -> x1 - v43 Load { addr=v8, disp=0, kind=I32 } -> x1 - v44 BinopI { op=mul, lhs=v43, rhs_imm=100 } -> x1 - v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x2 - v46 Extend { value=v44, kind=I32 } -> x2 - v47 Binop { op=add, lhs=v40, rhs=v44 } -> x0 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x1 - v49 Extend { value=v47, kind=I32 } -> x1 - v50 BinopI { op=mul, lhs=v9, rhs_imm=10 } -> x1 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x2 - v52 Extend { value=v50, kind=I32 } -> x2 - v53 Binop { op=add, lhs=v47, rhs=v50 } -> x0 - v54 BinopI { op=shl, lhs=v53, rhs_imm=32 } -> x1 - v55 Extend { value=v53, kind=I32 } -> x1 - v56 Binop { op=add, lhs=v53, rhs=v10 } -> x0 - v57 BinopI { op=shl, lhs=v56, rhs_imm=32 } -> x1 - v58 Extend { value=v56, kind=I32 } -> x0 - v59 BinopI { op=ne, lhs=v58, rhs_imm=123745 } -> x0 - terminator Bz { cond=v59, target=b2, fall=b1 } (exit_acc=v59) + v3 Imm(0) -> x0 [f32] + v4 Imm(1) -> x1 + v5 Imm(2) -> x1 + v6 Imm(3) -> x1 + v7 LocalAddr(-1) -> x1 + v8 Imm(4) -> x2 + v9 Imm(5) -> x2 + v10 Imm(1) -> x2 + v11 Imm(0) -> x2 + v12 Imm(2) -> x2 + v13 Imm(0) -> x2 + v14 Imm(3) -> x2 + v15 Imm(0) -> x2 + v16 Imm(0) -> x2 + v17 Imm(4) -> x2 + v18 Imm(0) -> x2 + v19 Imm(5) -> x2 + v20 Imm(0) -> x2 + v21 Imm(0) -> x2 + v22 Imm(0) -> x2 + v23 FpCast { kind=F32ToF64, value=v3 } -> d0 + v24 FpCast { kind=FpToInt, value=v23 } -> x2 + v25 FpCast { kind=F32ToF64, value=v3 } -> d0 + v26 FpCast { kind=FpToInt, value=v25 } -> x0 + v27 Imm(100000) -> x0 + v28 Imm(429496729600000) -> x0 + v29 Imm(100000) -> x0 + v30 Imm(20000) -> x0 + v31 Imm(85899345920000) -> x0 + v32 Imm(20000) -> x0 + v33 Imm(120000) -> x0 + v34 Imm(515396075520000) -> x0 + v35 Imm(120000) -> x0 + v36 Imm(3000) -> x0 + v37 Imm(12884901888000) -> x0 + v38 Imm(3000) -> x0 + v39 Imm(123000) -> x0 + v40 Imm(528280977408000) -> x0 + v41 Imm(123000) -> x0 + v42 Load { addr=v7, disp=0, kind=I32 } -> x0 + v43 BinopI { op=mul, lhs=v42, rhs_imm=100 } -> x0 + v44 BinopI { op=shl, lhs=v43, rhs_imm=32 } -> x1 + v45 Extend { value=v43, kind=I32 } -> x1 + v46 BinopI { op=add, lhs=v43, rhs_imm=123000 } -> x0 + v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x1 + v48 Extend { value=v46, kind=I32 } -> x1 + v49 Imm(40) -> x1 + v50 Imm(171798691840) -> x1 + v51 Imm(40) -> x1 + v52 BinopI { op=add, lhs=v46, rhs_imm=40 } -> x0 + v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> x1 + v54 Extend { value=v52, kind=I32 } -> x1 + v55 BinopI { op=add, lhs=v52, rhs_imm=5 } -> x0 + v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 + v57 Extend { value=v55, kind=I32 } -> x0 + v58 BinopI { op=ne, lhs=v57, rhs_imm=123745 } -> x0 + terminator Bz { cond=v58, target=b2, fall=b1 } (exit_acc=v58) block 1 start_pc=0 - v60 Imm(1) -> x0 - terminator Return(v60) (exit_acc=v60) + v59 Imm(1) -> x0 + terminator Return(v59) (exit_acc=v59) block 2 start_pc=0 - v61 Imm(0) -> x0 - terminator Return(v61) (exit_acc=v61) + v60 Imm(0) -> x0 + terminator Return(v60) (exit_acc=v60) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/param_incoming_reg_clobber.ssa b/tests/snapshots/ssa/param_incoming_reg_clobber.ssa index 1e7ab1a69..31bae3863 100644 --- a/tests/snapshots/ssa/param_incoming_reg_clobber.ssa +++ b/tests/snapshots/ssa/param_incoming_reg_clobber.ssa @@ -10,16 +10,8 @@ fn ent_pc=0 n_params=3 variadic=false locals=0 v4 Imm(0) -> x0 v5 ParamRef(2, kind=I64) -> x2 v6 StoreLocal { off=4, value=v5, kind=I64 } -> - - terminator Jmp(b1) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b0:v1, b2:v14], kind=I64 } -> x7 - v8 Phi { incoming=[b0:v3, b2:v17], kind=I64 } -> x6 - v9 LoadLocal { off=4, kind=U32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=-1 } -> x1 - v11 StoreLocal { off=4, value=v10, kind=I32 } -> - - v12 BinopI { op=ne, lhs=v9, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b3, fall=b2 } (exit_acc=v12) - block 2 start_pc=0 v13 LoadLocal { off=2, kind=I64 } -> x0 v14 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 v15 Imm(0) -> x1 @@ -28,17 +20,25 @@ fn ent_pc=0 n_params=3 variadic=false locals=0 v18 Imm(0) -> x2 v19 Load { addr=v8, disp=0, kind=I8 } -> x2 v20 Store { addr=v7, disp=0, value=v19, kind=I8 } -> - - terminator Jmp(b1) (exit_acc=v20) + terminator Jmp(b2) (exit_acc=v20) + block 2 start_pc=0 + v7 Phi { incoming=[b0:v1, b1:v14], kind=I64 } -> x7 + v8 Phi { incoming=[b0:v3, b1:v17], kind=I64 } -> x6 + v9 LoadLocal { off=4, kind=U32 } -> x0 + v10 BinopI { op=add, lhs=v9, rhs_imm=-1 } -> x1 + v11 StoreLocal { off=4, value=v10, kind=I32 } -> - + v12 BinopI { op=ne, lhs=v9, rhs_imm=0 } -> x0 + terminator Bnz { cond=v12, target=b1, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v21 Imm(0) -> x0 terminator Return(v21) (exit_acc=v21) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=swap_or_copy fn ent_pc=1 n_params=4 variadic=false locals=3 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 ParamRef(0, kind=I64) -> x3 + v1 ParamRef(0, kind=I64) -> x7 v2 Imm(0) -> x0 v3 ParamRef(1, kind=I64) -> x6 v4 Imm(0) -> x0 @@ -65,16 +65,8 @@ fn ent_pc=1 n_params=4 variadic=false locals=3 v19 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 v20 Binop { op=add, lhs=v1, rhs=v19 } -> x1 v21 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v20) + terminator Jmp(b5) (exit_acc=v20) block 4 start_pc=0 - v22 Phi { incoming=[b3:v20, b5:v29], kind=I64 } -> x1 - v23 Phi { incoming=[b3:v3, b5:v32], kind=I64 } -> x6 - v24 LoadLocal { off=4, kind=U32 } -> x0 - v25 BinopI { op=add, lhs=v24, rhs_imm=-1 } -> x2 - v26 StoreLocal { off=4, value=v25, kind=I32 } -> - - v27 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) - block 5 start_pc=0 v28 LoadLocal { off=2, kind=I64 } -> x0 v29 BinopI { op=add, lhs=v22, rhs_imm=-1 } -> x0 v30 Imm(0) -> x2 @@ -83,7 +75,15 @@ fn ent_pc=1 n_params=4 variadic=false locals=3 v33 Imm(0) -> x7 v34 Load { addr=v23, disp=0, kind=I8 } -> x6 v35 Store { addr=v22, disp=0, value=v34, kind=I8 } -> - - terminator Jmp(b4) (exit_acc=v35) + terminator Jmp(b5) (exit_acc=v35) + block 5 start_pc=0 + v22 Phi { incoming=[b3:v20, b4:v29], kind=I64 } -> x1 + v23 Phi { incoming=[b3:v3, b4:v32], kind=I64 } -> x6 + v24 LoadLocal { off=4, kind=U32 } -> x0 + v25 BinopI { op=add, lhs=v24, rhs_imm=-1 } -> x2 + v26 StoreLocal { off=4, value=v25, kind=I32 } -> - + v27 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x0 + terminator Bz { cond=v27, target=b2, fall=b4 } (exit_acc=v27) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -92,113 +92,208 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=8 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-1) -> x0 + v6 Imm(0) -> x1 + v7 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v8 Imm(1) -> x1 + v9 Imm(4294967296) -> x1 + v10 Imm(1) -> x1 + v11 Imm(72057594037927936) -> x1 + v12 Imm(1) -> x1 + v13 Store { addr=v7, disp=0, value=v12, kind=I8 } -> - + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 Imm(1) -> x0 + v19 LocalAddr(-1) -> x0 + v20 Imm(1) -> x1 + v21 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x1 + v22 Imm(2) -> x1 + v23 Imm(8589934592) -> x1 + v24 Imm(2) -> x1 + v25 Imm(144115188075855872) -> x1 + v26 Imm(2) -> x1 + v27 Store { addr=v19, disp=1, value=v26, kind=I8 } -> - + v28 Imm(1) -> x0 + v29 Imm(2) -> x0 + v30 Imm(0) -> x0 + v31 Imm(2) -> x0 + v32 Imm(1) -> x0 + v33 LocalAddr(-1) -> x0 + v34 Imm(2) -> x1 + v35 BinopI { op=add, lhs=v33, rhs_imm=2 } -> x1 + v36 Imm(3) -> x1 + v37 Imm(12884901888) -> x1 + v38 Imm(3) -> x1 + v39 Imm(216172782113783808) -> x1 + v40 Imm(3) -> x1 + v41 Store { addr=v33, disp=2, value=v40, kind=I8 } -> - + v42 Imm(2) -> x0 + v43 Imm(3) -> x0 + v44 Imm(0) -> x0 + v45 Imm(3) -> x0 + v46 Imm(1) -> x0 + v47 LocalAddr(-1) -> x0 + v48 Imm(3) -> x1 + v49 BinopI { op=add, lhs=v47, rhs_imm=3 } -> x1 + v50 Imm(4) -> x1 + v51 Imm(17179869184) -> x1 + v52 Imm(4) -> x1 + v53 Imm(288230376151711744) -> x1 + v54 Imm(4) -> x1 + v55 Store { addr=v47, disp=3, value=v54, kind=I8 } -> - + v56 Imm(3) -> x0 + v57 Imm(4) -> x0 + v58 Imm(0) -> x0 + v59 Imm(4) -> x0 + v60 Imm(1) -> x0 + v61 LocalAddr(-1) -> x0 + v62 Imm(4) -> x1 + v63 BinopI { op=add, lhs=v61, rhs_imm=4 } -> x1 + v64 Imm(5) -> x1 + v65 Imm(21474836480) -> x1 + v66 Imm(5) -> x1 + v67 Imm(360287970189639680) -> x1 + v68 Imm(5) -> x1 + v69 Store { addr=v61, disp=4, value=v68, kind=I8 } -> - + v70 Imm(4) -> x0 + v71 Imm(5) -> x0 + v72 Imm(0) -> x0 + v73 Imm(5) -> x0 + v74 Imm(1) -> x0 + v75 LocalAddr(-1) -> x0 + v76 Imm(5) -> x1 + v77 BinopI { op=add, lhs=v75, rhs_imm=5 } -> x1 + v78 Imm(6) -> x1 + v79 Imm(25769803776) -> x1 + v80 Imm(6) -> x1 + v81 Imm(432345564227567616) -> x1 + v82 Imm(6) -> x1 + v83 Store { addr=v75, disp=5, value=v82, kind=I8 } -> - + v84 Imm(5) -> x0 + v85 Imm(6) -> x0 + v86 Imm(0) -> x0 + v87 Imm(6) -> x0 + v88 Imm(1) -> x0 + v89 LocalAddr(-1) -> x0 + v90 Imm(6) -> x1 + v91 BinopI { op=add, lhs=v89, rhs_imm=6 } -> x1 + v92 Imm(7) -> x1 + v93 Imm(30064771072) -> x1 + v94 Imm(7) -> x1 + v95 Imm(504403158265495552) -> x1 + v96 Imm(7) -> x1 + v97 Store { addr=v89, disp=6, value=v96, kind=I8 } -> - + v98 Imm(6) -> x0 + v99 Imm(7) -> x0 + v100 Imm(0) -> x0 + v101 Imm(7) -> x0 + v102 Imm(1) -> x0 + v103 LocalAddr(-1) -> x0 + v104 Imm(7) -> x1 + v105 BinopI { op=add, lhs=v103, rhs_imm=7 } -> x1 + v106 Imm(8) -> x1 + v107 Imm(34359738368) -> x1 + v108 Imm(8) -> x1 + v109 Imm(576460752303423488) -> x1 + v110 Imm(8) -> x1 + v111 Store { addr=v103, disp=7, value=v110, kind=I8 } -> - + v112 Imm(7) -> x0 + v113 Imm(8) -> x0 + v114 Imm(0) -> x0 + v115 Imm(8) -> x0 + v116 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v116) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v117 LocalAddr(-2) -> x7 + v118 LocalAddr(-1) -> x6 + v119 Imm(8) -> x2 + v120 Imm(1) -> x1 + v121 Call { target_pc=1, args=[v117, v118, v119, v120], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v122 Imm(0) -> x1 + v123 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v122) block 3 start_pc=0 - v9 LocalAddr(-1) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 Binop { op=add, lhs=v9, rhs=v10 } -> x0 - v12 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x6 - v14 Extend { value=v12, kind=I32 } -> x6 - v15 BinopI { op=shl, lhs=v12, rhs_imm=56 } -> x2 - v16 Extend { value=v14, kind=I8 } -> x2 - v17 Store { addr=v11, disp=0, value=v14, kind=I8 } -> - - terminator Jmp(b2) (exit_acc=v17) + v130 LocalAddr(-2) -> x2 + v131 Extend { value=v124, kind=I32 } -> x6 + v132 Binop { op=add, lhs=v130, rhs=v125 } -> x2 + v133 Load { addr=v132, disp=0, kind=I8 } -> x2 + v134 Imm(8) -> x6 + v135 Binop { op=sub, lhs=v134, rhs=v125 } -> x6 + v136 BinopI { op=shl, lhs=v135, rhs_imm=32 } -> x7 + v137 Extend { value=v135, kind=I32 } -> x7 + v138 BinopI { op=shl, lhs=v135, rhs_imm=56 } -> x6 + v139 Extend { value=v137, kind=I8 } -> x6 + v140 Binop { op=ne, lhs=v133, rhs=v139 } -> x2 + terminator Bnz { cond=v140, target=b12, fall=b4 } (exit_acc=v140) block 4 start_pc=0 - v18 LocalAddr(-2) -> x7 - v19 LocalAddr(-1) -> x6 - v20 Imm(8) -> x2 - v21 Imm(1) -> x1 - v22 Call { target_pc=1, args=[v18, v19, v20, v21], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v23 Imm(0) -> x3 - v24 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v23) + v127 Extend { value=v124, kind=I32 } -> x1 + v128 BinopI { op=add, lhs=v125, rhs_imm=1 } -> x1 + v129 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v128) block 5 start_pc=0 - v25 Phi { incoming=[b4:v23, b6:v29], kind=I64 } -> x3 - v26 Extend { value=v25, kind=I32 } -> x0 - v27 BinopI { op=lt, lhs=v26, rhs_imm=8 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v124 Phi { incoming=[b2:v122, b4:v128], kind=I64 } -> x1 + v125 Extend { value=v124, kind=I32 } -> x0 + v126 BinopI { op=lt, lhs=v125, rhs_imm=8 } -> x2 + terminator Bnz { cond=v126, target=b3, fall=b6 } (exit_acc=v126) block 6 start_pc=0 - v28 Extend { value=v25, kind=I32 } -> x0 - v29 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x3 - v30 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v29) + v141 LocalAddr(-2) -> x7 + v142 LocalAddr(-1) -> x6 + v143 Imm(8) -> x2 + v144 Imm(0) -> x3 + v145 Call { target_pc=1, args=[v141, v142, v143, v144], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v146 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v144) block 7 start_pc=0 - v31 LocalAddr(-2) -> x0 - v32 Extend { value=v25, kind=I32 } -> x1 - v33 Binop { op=add, lhs=v31, rhs=v32 } -> x0 - v34 Load { addr=v33, disp=0, kind=I8 } -> x0 - v35 Imm(8) -> x2 - v36 Binop { op=sub, lhs=v35, rhs=v32 } -> x1 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x2 - v38 Extend { value=v36, kind=I32 } -> x2 - v39 BinopI { op=shl, lhs=v36, rhs_imm=56 } -> x1 - v40 Extend { value=v38, kind=I8 } -> x1 - v41 Binop { op=ne, lhs=v34, rhs=v40 } -> x0 - terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) + v158 LocalAddr(-2) -> x1 + v159 Extend { value=v152, kind=I32 } -> x2 + v160 Binop { op=add, lhs=v158, rhs=v153 } -> x1 + v161 Load { addr=v160, disp=0, kind=I8 } -> x1 + v162 BinopI { op=add, lhs=v153, rhs_imm=1 } -> x2 + v163 BinopI { op=shl, lhs=v162, rhs_imm=32 } -> x6 + v164 Extend { value=v162, kind=I32 } -> x6 + v165 BinopI { op=shl, lhs=v162, rhs_imm=56 } -> x2 + v166 Extend { value=v164, kind=I8 } -> x2 + v167 Binop { op=ne, lhs=v161, rhs=v166 } -> x1 + terminator Bnz { cond=v167, target=b11, fall=b8 } (exit_acc=v167) block 8 start_pc=0 - v42 LocalAddr(-2) -> x7 - v43 LocalAddr(-1) -> x6 - v44 Imm(8) -> x2 - v45 Imm(0) -> x3 - v46 Call { target_pc=1, args=[v42, v43, v44, v45], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v47 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v45) + v155 Extend { value=v152, kind=I32 } -> x1 + v156 BinopI { op=add, lhs=v153, rhs_imm=1 } -> x3 + v157 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v156) block 9 start_pc=0 - v48 Imm(10) -> x0 - v49 Extend { value=v25, kind=I32 } -> x0 - v50 BinopI { op=add, lhs=v25, rhs_imm=10 } -> x0 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x1 - v52 Extend { value=v50, kind=I32 } -> x0 - terminator Return(v52) (exit_acc=v52) + v152 Phi { incoming=[b6:v144, b8:v156], kind=I64 } -> x3 + v153 Extend { value=v152, kind=I32 } -> x0 + v154 BinopI { op=lt, lhs=v153, rhs_imm=8 } -> x1 + terminator Bnz { cond=v154, target=b7, fall=b10 } (exit_acc=v154) block 10 start_pc=0 - terminator Jmp(b6) + v168 Imm(0) -> x0 + terminator Return(v168) (exit_acc=v168) block 11 start_pc=0 - v53 Phi { incoming=[b8:v45, b12:v57], kind=I64 } -> x3 - v54 Extend { value=v53, kind=I32 } -> x0 - v55 BinopI { op=lt, lhs=v54, rhs_imm=8 } -> x0 - terminator Bz { cond=v55, target=b14, fall=b13 } (exit_acc=v55) + v169 Imm(20) -> x0 + v170 Extend { value=v152, kind=I32 } -> x0 + v171 BinopI { op=add, lhs=v152, rhs_imm=20 } -> x0 + v172 BinopI { op=shl, lhs=v171, rhs_imm=32 } -> x1 + v173 Extend { value=v171, kind=I32 } -> x0 + terminator Return(v173) (exit_acc=v173) block 12 start_pc=0 - v56 Extend { value=v53, kind=I32 } -> x0 - v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x3 - v58 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v57) + v147 Imm(10) -> x0 + v148 Extend { value=v124, kind=I32 } -> x0 + v149 BinopI { op=add, lhs=v124, rhs_imm=10 } -> x0 + v150 BinopI { op=shl, lhs=v149, rhs_imm=32 } -> x1 + v151 Extend { value=v149, kind=I32 } -> x0 + terminator Return(v151) (exit_acc=v151) block 13 start_pc=0 - v59 LocalAddr(-2) -> x0 - v60 Extend { value=v53, kind=I32 } -> x1 - v61 Binop { op=add, lhs=v59, rhs=v60 } -> x0 - v62 Load { addr=v61, disp=0, kind=I8 } -> x0 - v63 BinopI { op=add, lhs=v60, rhs_imm=1 } -> x1 - v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x2 - v65 Extend { value=v63, kind=I32 } -> x2 - v66 BinopI { op=shl, lhs=v63, rhs_imm=56 } -> x1 - v67 Extend { value=v65, kind=I8 } -> x1 - v68 Binop { op=ne, lhs=v62, rhs=v67 } -> x0 - terminator Bz { cond=v68, target=b16, fall=b15 } (exit_acc=v68) + terminator Jmp(b4) block 14 start_pc=0 - v69 Imm(0) -> x0 - terminator Return(v69) (exit_acc=v69) - block 15 start_pc=0 - v70 Imm(20) -> x0 - v71 Extend { value=v53, kind=I32 } -> x0 - v72 BinopI { op=add, lhs=v53, rhs_imm=20 } -> x0 - v73 BinopI { op=shl, lhs=v72, rhs_imm=32 } -> x1 - v74 Extend { value=v72, kind=I32 } -> x0 - terminator Return(v74) (exit_acc=v74) - block 16 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/param_reg_swap.ssa b/tests/snapshots/ssa/param_reg_swap.ssa index 52a53397b..10a06b4e2 100644 --- a/tests/snapshots/ssa/param_reg_swap.ssa +++ b/tests/snapshots/ssa/param_reg_swap.ssa @@ -39,7 +39,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=core fn ent_pc=1 n_params=4 variadic=false locals=10 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13, 14] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -52,197 +52,197 @@ fn ent_pc=1 n_params=4 variadic=false locals=10 v8 Imm(0) -> x0 v9 Imm(0) -> x8 v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v11 Phi { incoming=[b0:v9, b2:v15], kind=I64 } -> x8 - v12 Extend { value=v11, kind=I32 } -> x0 - v13 BinopI { op=lt, lhs=v12, rhs_imm=4 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) - block 2 start_pc=0 - v14 Extend { value=v11, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x8 - v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) - block 3 start_pc=0 - v17 LocalAddr(-8) -> x0 - v18 Imm(5) -> x9 - v19 Extend { value=v11, kind=I32 } -> x9 - v20 BinopI { op=mul, lhs=v11, rhs_imm=5 } -> x9 - v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x3 - v22 Extend { value=v20, kind=I32 } -> x9 - v23 BinopI { op=shl, lhs=v22, rhs_imm=2 } -> x3 - v24 Binop { op=add, lhs=v17, rhs=v23 } -> x3 - v25 LoadLocal { off=5, kind=I64 } -> x3 - v26 Imm(4) -> x3 - v27 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x12 - v29 Extend { value=v27, kind=I32 } -> x3 - v30 Binop { op=add, lhs=v7, rhs=v29 } -> x3 - v31 Imm(0) -> x12 - v32 Imm(3) -> x12 - v33 BinopI { op=add, lhs=v30, rhs_imm=3 } -> x12 - v34 Load { addr=v30, disp=3, kind=U8 } -> x12 - v35 Imm(0) -> x13 - v36 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x12 - v37 BinopI { op=shl, lhs=v36, rhs_imm=8 } -> x12 - v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x12 - v39 Imm(2) -> x13 - v40 BinopI { op=add, lhs=v30, rhs_imm=2 } -> x13 - v41 Load { addr=v30, disp=2, kind=U8 } -> x13 - v42 Binop { op=or, lhs=v38, rhs=v41 } -> x12 - v43 Imm(0) -> x13 - v44 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x13 - v45 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x12 - v46 BinopI { op=shl, lhs=v45, rhs_imm=8 } -> x12 - v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x12 - v48 Imm(1) -> x13 - v49 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x13 - v50 Load { addr=v30, disp=1, kind=U8 } -> x13 - v51 Binop { op=or, lhs=v47, rhs=v50 } -> x12 - v52 Imm(0) -> x13 - v53 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x13 - v54 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x12 - v55 BinopI { op=shl, lhs=v54, rhs_imm=8 } -> x12 - v56 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x12 - v57 Imm(0) -> x13 - v58 Load { addr=v30, disp=0, kind=U8 } -> x3 - v59 Binop { op=or, lhs=v56, rhs=v58 } -> x3 + v17 LocalAddr(-8) -> x9 + v18 Imm(5) -> x3 + v19 Extend { value=v11, kind=I32 } -> x3 + v20 BinopI { op=mul, lhs=v11, rhs_imm=5 } -> x3 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x12 + v22 Extend { value=v20, kind=I32 } -> x3 + v23 BinopI { op=shl, lhs=v22, rhs_imm=2 } -> x12 + v24 Binop { op=add, lhs=v17, rhs=v23 } -> x12 + v25 LoadLocal { off=5, kind=I64 } -> x12 + v26 Imm(4) -> x12 + v27 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x13 + v29 Extend { value=v27, kind=I32 } -> x12 + v30 Binop { op=add, lhs=v7, rhs=v29 } -> x12 + v31 Imm(0) -> x13 + v32 Imm(3) -> x13 + v33 BinopI { op=add, lhs=v30, rhs_imm=3 } -> x13 + v34 Load { addr=v30, disp=3, kind=U8 } -> x13 + v35 Imm(0) -> x14 + v36 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x13 + v37 BinopI { op=shl, lhs=v36, rhs_imm=8 } -> x13 + v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x13 + v39 Imm(2) -> x14 + v40 BinopI { op=add, lhs=v30, rhs_imm=2 } -> x14 + v41 Load { addr=v30, disp=2, kind=U8 } -> x14 + v42 Binop { op=or, lhs=v38, rhs=v41 } -> x13 + v43 Imm(0) -> x14 + v44 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x14 + v45 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x13 + v46 BinopI { op=shl, lhs=v45, rhs_imm=8 } -> x13 + v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x13 + v48 Imm(1) -> x14 + v49 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x14 + v50 Load { addr=v30, disp=1, kind=U8 } -> x14 + v51 Binop { op=or, lhs=v47, rhs=v50 } -> x13 + v52 Imm(0) -> x14 + v53 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x14 + v54 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x13 + v55 BinopI { op=shl, lhs=v54, rhs_imm=8 } -> x13 + v56 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x13 + v57 Imm(0) -> x14 + v58 Load { addr=v30, disp=0, kind=U8 } -> x12 + v59 Binop { op=or, lhs=v56, rhs=v58 } -> x12 v60 StoreIndexed { base=v17, index=v22, scale=4, value=v59, kind=I32 } -> - - v61 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x0 - v62 LocalAddr(-8) -> x0 - v63 Imm(1) -> x9 - v64 Extend { value=v11, kind=I32 } -> x9 - v65 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x9 - v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x3 - v67 Extend { value=v65, kind=I32 } -> x9 - v68 BinopI { op=shl, lhs=v67, rhs_imm=2 } -> x3 - v69 Binop { op=add, lhs=v62, rhs=v68 } -> x3 - v70 LoadLocal { off=4, kind=I64 } -> x3 - v71 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x12 - v73 Extend { value=v71, kind=I32 } -> x3 - v74 Binop { op=add, lhs=v5, rhs=v73 } -> x3 - v75 Imm(0) -> x12 - v76 Imm(3) -> x12 - v77 BinopI { op=add, lhs=v74, rhs_imm=3 } -> x12 - v78 Load { addr=v74, disp=3, kind=U8 } -> x12 - v79 Imm(0) -> x13 - v80 BinopI { op=and, lhs=v78, rhs_imm=4294967295 } -> x12 - v81 BinopI { op=shl, lhs=v80, rhs_imm=8 } -> x12 - v82 BinopI { op=and, lhs=v81, rhs_imm=4294967295 } -> x12 - v83 Imm(2) -> x13 - v84 BinopI { op=add, lhs=v74, rhs_imm=2 } -> x13 - v85 Load { addr=v74, disp=2, kind=U8 } -> x13 - v86 Binop { op=or, lhs=v82, rhs=v85 } -> x12 - v87 Imm(0) -> x13 - v88 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x13 - v89 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x12 - v90 BinopI { op=shl, lhs=v89, rhs_imm=8 } -> x12 - v91 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x12 - v92 Imm(1) -> x13 - v93 BinopI { op=add, lhs=v74, rhs_imm=1 } -> x13 - v94 Load { addr=v74, disp=1, kind=U8 } -> x13 - v95 Binop { op=or, lhs=v91, rhs=v94 } -> x12 - v96 Imm(0) -> x13 - v97 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x13 - v98 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x12 - v99 BinopI { op=shl, lhs=v98, rhs_imm=8 } -> x12 - v100 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x12 - v101 Imm(0) -> x13 - v102 Load { addr=v74, disp=0, kind=U8 } -> x3 - v103 Binop { op=or, lhs=v100, rhs=v102 } -> x3 + v61 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x9 + v62 LocalAddr(-8) -> x9 + v63 Imm(1) -> x3 + v64 Extend { value=v11, kind=I32 } -> x3 + v65 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x3 + v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x12 + v67 Extend { value=v65, kind=I32 } -> x3 + v68 BinopI { op=shl, lhs=v67, rhs_imm=2 } -> x12 + v69 Binop { op=add, lhs=v62, rhs=v68 } -> x12 + v70 LoadLocal { off=4, kind=I64 } -> x12 + v71 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x13 + v73 Extend { value=v71, kind=I32 } -> x12 + v74 Binop { op=add, lhs=v5, rhs=v73 } -> x12 + v75 Imm(0) -> x13 + v76 Imm(3) -> x13 + v77 BinopI { op=add, lhs=v74, rhs_imm=3 } -> x13 + v78 Load { addr=v74, disp=3, kind=U8 } -> x13 + v79 Imm(0) -> x14 + v80 BinopI { op=and, lhs=v78, rhs_imm=4294967295 } -> x13 + v81 BinopI { op=shl, lhs=v80, rhs_imm=8 } -> x13 + v82 BinopI { op=and, lhs=v81, rhs_imm=4294967295 } -> x13 + v83 Imm(2) -> x14 + v84 BinopI { op=add, lhs=v74, rhs_imm=2 } -> x14 + v85 Load { addr=v74, disp=2, kind=U8 } -> x14 + v86 Binop { op=or, lhs=v82, rhs=v85 } -> x13 + v87 Imm(0) -> x14 + v88 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x14 + v89 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x13 + v90 BinopI { op=shl, lhs=v89, rhs_imm=8 } -> x13 + v91 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x13 + v92 Imm(1) -> x14 + v93 BinopI { op=add, lhs=v74, rhs_imm=1 } -> x14 + v94 Load { addr=v74, disp=1, kind=U8 } -> x14 + v95 Binop { op=or, lhs=v91, rhs=v94 } -> x13 + v96 Imm(0) -> x14 + v97 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x14 + v98 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x13 + v99 BinopI { op=shl, lhs=v98, rhs_imm=8 } -> x13 + v100 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x13 + v101 Imm(0) -> x14 + v102 Load { addr=v74, disp=0, kind=U8 } -> x12 + v103 Binop { op=or, lhs=v100, rhs=v102 } -> x12 v104 StoreIndexed { base=v62, index=v67, scale=4, value=v103, kind=I32 } -> - - v105 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x0 - v106 LocalAddr(-8) -> x0 - v107 Imm(6) -> x9 - v108 Extend { value=v11, kind=I32 } -> x9 - v109 BinopI { op=add, lhs=v11, rhs_imm=6 } -> x9 - v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x3 - v111 Extend { value=v109, kind=I32 } -> x9 - v112 BinopI { op=shl, lhs=v111, rhs_imm=2 } -> x3 - v113 Binop { op=add, lhs=v106, rhs=v112 } -> x3 - v114 LoadLocal { off=3, kind=I64 } -> x3 - v115 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> x12 - v117 Extend { value=v115, kind=I32 } -> x3 - v118 Binop { op=add, lhs=v3, rhs=v117 } -> x3 - v119 Imm(0) -> x12 - v120 Imm(3) -> x12 - v121 BinopI { op=add, lhs=v118, rhs_imm=3 } -> x12 - v122 Load { addr=v118, disp=3, kind=U8 } -> x12 - v123 Imm(0) -> x13 - v124 BinopI { op=and, lhs=v122, rhs_imm=4294967295 } -> x12 - v125 BinopI { op=shl, lhs=v124, rhs_imm=8 } -> x12 - v126 BinopI { op=and, lhs=v125, rhs_imm=4294967295 } -> x12 - v127 Imm(2) -> x13 - v128 BinopI { op=add, lhs=v118, rhs_imm=2 } -> x13 - v129 Load { addr=v118, disp=2, kind=U8 } -> x13 - v130 Binop { op=or, lhs=v126, rhs=v129 } -> x12 - v131 Imm(0) -> x13 - v132 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x13 - v133 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x12 - v134 BinopI { op=shl, lhs=v133, rhs_imm=8 } -> x12 - v135 BinopI { op=and, lhs=v134, rhs_imm=4294967295 } -> x12 - v136 Imm(1) -> x13 - v137 BinopI { op=add, lhs=v118, rhs_imm=1 } -> x13 - v138 Load { addr=v118, disp=1, kind=U8 } -> x13 - v139 Binop { op=or, lhs=v135, rhs=v138 } -> x12 - v140 Imm(0) -> x13 - v141 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x13 - v142 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x12 - v143 BinopI { op=shl, lhs=v142, rhs_imm=8 } -> x12 - v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x12 - v145 Imm(0) -> x13 - v146 Load { addr=v118, disp=0, kind=U8 } -> x3 - v147 Binop { op=or, lhs=v144, rhs=v146 } -> x3 + v105 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x9 + v106 LocalAddr(-8) -> x9 + v107 Imm(6) -> x3 + v108 Extend { value=v11, kind=I32 } -> x3 + v109 BinopI { op=add, lhs=v11, rhs_imm=6 } -> x3 + v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x12 + v111 Extend { value=v109, kind=I32 } -> x3 + v112 BinopI { op=shl, lhs=v111, rhs_imm=2 } -> x12 + v113 Binop { op=add, lhs=v106, rhs=v112 } -> x12 + v114 LoadLocal { off=3, kind=I64 } -> x12 + v115 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> x13 + v117 Extend { value=v115, kind=I32 } -> x12 + v118 Binop { op=add, lhs=v3, rhs=v117 } -> x12 + v119 Imm(0) -> x13 + v120 Imm(3) -> x13 + v121 BinopI { op=add, lhs=v118, rhs_imm=3 } -> x13 + v122 Load { addr=v118, disp=3, kind=U8 } -> x13 + v123 Imm(0) -> x14 + v124 BinopI { op=and, lhs=v122, rhs_imm=4294967295 } -> x13 + v125 BinopI { op=shl, lhs=v124, rhs_imm=8 } -> x13 + v126 BinopI { op=and, lhs=v125, rhs_imm=4294967295 } -> x13 + v127 Imm(2) -> x14 + v128 BinopI { op=add, lhs=v118, rhs_imm=2 } -> x14 + v129 Load { addr=v118, disp=2, kind=U8 } -> x14 + v130 Binop { op=or, lhs=v126, rhs=v129 } -> x13 + v131 Imm(0) -> x14 + v132 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x14 + v133 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x13 + v134 BinopI { op=shl, lhs=v133, rhs_imm=8 } -> x13 + v135 BinopI { op=and, lhs=v134, rhs_imm=4294967295 } -> x13 + v136 Imm(1) -> x14 + v137 BinopI { op=add, lhs=v118, rhs_imm=1 } -> x14 + v138 Load { addr=v118, disp=1, kind=U8 } -> x14 + v139 Binop { op=or, lhs=v135, rhs=v138 } -> x13 + v140 Imm(0) -> x14 + v141 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x14 + v142 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x13 + v143 BinopI { op=shl, lhs=v142, rhs_imm=8 } -> x13 + v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x13 + v145 Imm(0) -> x14 + v146 Load { addr=v118, disp=0, kind=U8 } -> x12 + v147 Binop { op=or, lhs=v144, rhs=v146 } -> x12 v148 StoreIndexed { base=v106, index=v111, scale=4, value=v147, kind=I32 } -> - - v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x0 - v150 LocalAddr(-8) -> x0 - v151 Imm(11) -> x9 - v152 Extend { value=v11, kind=I32 } -> x9 - v153 BinopI { op=add, lhs=v11, rhs_imm=11 } -> x9 - v154 BinopI { op=shl, lhs=v153, rhs_imm=32 } -> x3 - v155 Extend { value=v153, kind=I32 } -> x9 - v156 BinopI { op=shl, lhs=v155, rhs_imm=2 } -> x3 - v157 Binop { op=add, lhs=v150, rhs=v156 } -> x3 - v158 LoadLocal { off=4, kind=I64 } -> x3 - v159 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x3 - v160 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 - v161 BinopI { op=shl, lhs=v160, rhs_imm=32 } -> x13 - v162 Extend { value=v160, kind=I32 } -> x12 - v163 Binop { op=add, lhs=v159, rhs=v162 } -> x3 - v164 Imm(0) -> x12 - v165 Imm(3) -> x12 - v166 BinopI { op=add, lhs=v163, rhs_imm=3 } -> x12 - v167 Load { addr=v163, disp=3, kind=U8 } -> x12 - v168 Imm(0) -> x13 - v169 BinopI { op=and, lhs=v167, rhs_imm=4294967295 } -> x12 - v170 BinopI { op=shl, lhs=v169, rhs_imm=8 } -> x12 - v171 BinopI { op=and, lhs=v170, rhs_imm=4294967295 } -> x12 - v172 Imm(2) -> x13 - v173 BinopI { op=add, lhs=v163, rhs_imm=2 } -> x13 - v174 Load { addr=v163, disp=2, kind=U8 } -> x13 - v175 Binop { op=or, lhs=v171, rhs=v174 } -> x12 - v176 Imm(0) -> x13 - v177 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x13 - v178 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x12 - v179 BinopI { op=shl, lhs=v178, rhs_imm=8 } -> x12 - v180 BinopI { op=and, lhs=v179, rhs_imm=4294967295 } -> x12 - v181 Imm(1) -> x13 - v182 BinopI { op=add, lhs=v163, rhs_imm=1 } -> x13 - v183 Load { addr=v163, disp=1, kind=U8 } -> x13 - v184 Binop { op=or, lhs=v180, rhs=v183 } -> x12 - v185 Imm(0) -> x13 - v186 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x13 - v187 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x12 - v188 BinopI { op=shl, lhs=v187, rhs_imm=8 } -> x12 - v189 BinopI { op=and, lhs=v188, rhs_imm=4294967295 } -> x12 - v190 Imm(0) -> x13 - v191 Load { addr=v163, disp=0, kind=U8 } -> x3 - v192 Binop { op=or, lhs=v189, rhs=v191 } -> x3 + v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x9 + v150 LocalAddr(-8) -> x9 + v151 Imm(11) -> x3 + v152 Extend { value=v11, kind=I32 } -> x3 + v153 BinopI { op=add, lhs=v11, rhs_imm=11 } -> x3 + v154 BinopI { op=shl, lhs=v153, rhs_imm=32 } -> x12 + v155 Extend { value=v153, kind=I32 } -> x3 + v156 BinopI { op=shl, lhs=v155, rhs_imm=2 } -> x12 + v157 Binop { op=add, lhs=v150, rhs=v156 } -> x12 + v158 LoadLocal { off=4, kind=I64 } -> x12 + v159 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x12 + v160 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x13 + v161 BinopI { op=shl, lhs=v160, rhs_imm=32 } -> x14 + v162 Extend { value=v160, kind=I32 } -> x13 + v163 Binop { op=add, lhs=v159, rhs=v162 } -> x12 + v164 Imm(0) -> x13 + v165 Imm(3) -> x13 + v166 BinopI { op=add, lhs=v163, rhs_imm=3 } -> x13 + v167 Load { addr=v163, disp=3, kind=U8 } -> x13 + v168 Imm(0) -> x14 + v169 BinopI { op=and, lhs=v167, rhs_imm=4294967295 } -> x13 + v170 BinopI { op=shl, lhs=v169, rhs_imm=8 } -> x13 + v171 BinopI { op=and, lhs=v170, rhs_imm=4294967295 } -> x13 + v172 Imm(2) -> x14 + v173 BinopI { op=add, lhs=v163, rhs_imm=2 } -> x14 + v174 Load { addr=v163, disp=2, kind=U8 } -> x14 + v175 Binop { op=or, lhs=v171, rhs=v174 } -> x13 + v176 Imm(0) -> x14 + v177 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x14 + v178 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x13 + v179 BinopI { op=shl, lhs=v178, rhs_imm=8 } -> x13 + v180 BinopI { op=and, lhs=v179, rhs_imm=4294967295 } -> x13 + v181 Imm(1) -> x14 + v182 BinopI { op=add, lhs=v163, rhs_imm=1 } -> x14 + v183 Load { addr=v163, disp=1, kind=U8 } -> x14 + v184 Binop { op=or, lhs=v180, rhs=v183 } -> x13 + v185 Imm(0) -> x14 + v186 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x14 + v187 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x13 + v188 BinopI { op=shl, lhs=v187, rhs_imm=8 } -> x13 + v189 BinopI { op=and, lhs=v188, rhs_imm=4294967295 } -> x13 + v190 Imm(0) -> x14 + v191 Load { addr=v163, disp=0, kind=U8 } -> x12 + v192 Binop { op=or, lhs=v189, rhs=v191 } -> x12 v193 StoreIndexed { base=v150, index=v155, scale=4, value=v192, kind=I32 } -> - - v194 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x0 + v194 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x9 terminator Jmp(b2) (exit_acc=v194) + block 2 start_pc=0 + v14 Extend { value=v11, kind=I32 } -> x8 + v15 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x8 + v16 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) + block 3 start_pc=0 + v11 Phi { incoming=[b0:v9, b2:v15], kind=I64 } -> x8 + v12 Extend { value=v11, kind=I32 } -> x0 + v13 BinopI { op=lt, lhs=v12, rhs_imm=4 } -> x9 + terminator Bnz { cond=v13, target=b1, fall=b4 } (exit_acc=v13) block 4 start_pc=0 v195 LoadLocal { off=2, kind=I64 } -> x0 v196 Imm(0) -> x0 @@ -272,57 +272,204 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=16 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-3) -> x0 + v6 Imm(0) -> x1 + v7 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v8 Imm(0) -> x1 + v9 Store { addr=v7, disp=0, value=v8, kind=I8 } -> - + v10 Imm(0) -> x0 + v11 Imm(1) -> x0 + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(1) -> x0 + v15 LocalAddr(-3) -> x0 + v16 Imm(1) -> x1 + v17 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x1 + v18 Imm(1) -> x1 + v19 Store { addr=v15, disp=1, value=v18, kind=I8 } -> - + v20 Imm(1) -> x0 + v21 Imm(2) -> x0 + v22 Imm(0) -> x0 + v23 Imm(2) -> x0 + v24 Imm(1) -> x0 + v25 LocalAddr(-3) -> x0 + v26 Imm(2) -> x1 + v27 BinopI { op=add, lhs=v25, rhs_imm=2 } -> x1 + v28 Imm(2) -> x1 + v29 Store { addr=v25, disp=2, value=v28, kind=I8 } -> - + v30 Imm(2) -> x0 + v31 Imm(3) -> x0 + v32 Imm(0) -> x0 + v33 Imm(3) -> x0 + v34 Imm(1) -> x0 + v35 LocalAddr(-3) -> x0 + v36 Imm(3) -> x1 + v37 BinopI { op=add, lhs=v35, rhs_imm=3 } -> x1 + v38 Imm(3) -> x1 + v39 Store { addr=v35, disp=3, value=v38, kind=I8 } -> - + v40 Imm(3) -> x0 + v41 Imm(4) -> x0 + v42 Imm(0) -> x0 + v43 Imm(4) -> x0 + v44 Imm(1) -> x0 + v45 LocalAddr(-3) -> x0 + v46 Imm(4) -> x1 + v47 BinopI { op=add, lhs=v45, rhs_imm=4 } -> x1 + v48 Imm(4) -> x1 + v49 Store { addr=v45, disp=4, value=v48, kind=I8 } -> - + v50 Imm(4) -> x0 + v51 Imm(5) -> x0 + v52 Imm(0) -> x0 + v53 Imm(5) -> x0 + v54 Imm(1) -> x0 + v55 LocalAddr(-3) -> x0 + v56 Imm(5) -> x1 + v57 BinopI { op=add, lhs=v55, rhs_imm=5 } -> x1 + v58 Imm(5) -> x1 + v59 Store { addr=v55, disp=5, value=v58, kind=I8 } -> - + v60 Imm(5) -> x0 + v61 Imm(6) -> x0 + v62 Imm(0) -> x0 + v63 Imm(6) -> x0 + v64 Imm(1) -> x0 + v65 LocalAddr(-3) -> x0 + v66 Imm(6) -> x1 + v67 BinopI { op=add, lhs=v65, rhs_imm=6 } -> x1 + v68 Imm(6) -> x1 + v69 Store { addr=v65, disp=6, value=v68, kind=I8 } -> - + v70 Imm(6) -> x0 + v71 Imm(7) -> x0 + v72 Imm(0) -> x0 + v73 Imm(7) -> x0 + v74 Imm(1) -> x0 + v75 LocalAddr(-3) -> x0 + v76 Imm(7) -> x1 + v77 BinopI { op=add, lhs=v75, rhs_imm=7 } -> x1 + v78 Imm(7) -> x1 + v79 Store { addr=v75, disp=7, value=v78, kind=I8 } -> - + v80 Imm(7) -> x0 + v81 Imm(8) -> x0 + v82 Imm(0) -> x0 + v83 Imm(8) -> x0 + v84 Imm(1) -> x0 + v85 LocalAddr(-3) -> x0 + v86 Imm(8) -> x1 + v87 BinopI { op=add, lhs=v85, rhs_imm=8 } -> x1 + v88 Imm(8) -> x1 + v89 Store { addr=v85, disp=8, value=v88, kind=I8 } -> - + v90 Imm(8) -> x0 + v91 Imm(9) -> x0 + v92 Imm(0) -> x0 + v93 Imm(9) -> x0 + v94 Imm(1) -> x0 + v95 LocalAddr(-3) -> x0 + v96 Imm(9) -> x1 + v97 BinopI { op=add, lhs=v95, rhs_imm=9 } -> x1 + v98 Imm(9) -> x1 + v99 Store { addr=v95, disp=9, value=v98, kind=I8 } -> - + v100 Imm(9) -> x0 + v101 Imm(10) -> x0 + v102 Imm(0) -> x0 + v103 Imm(10) -> x0 + v104 Imm(1) -> x0 + v105 LocalAddr(-3) -> x0 + v106 Imm(10) -> x1 + v107 BinopI { op=add, lhs=v105, rhs_imm=10 } -> x1 + v108 Imm(10) -> x1 + v109 Store { addr=v105, disp=10, value=v108, kind=I8 } -> - + v110 Imm(10) -> x0 + v111 Imm(11) -> x0 + v112 Imm(0) -> x0 + v113 Imm(11) -> x0 + v114 Imm(1) -> x0 + v115 LocalAddr(-3) -> x0 + v116 Imm(11) -> x1 + v117 BinopI { op=add, lhs=v115, rhs_imm=11 } -> x1 + v118 Imm(11) -> x1 + v119 Store { addr=v115, disp=11, value=v118, kind=I8 } -> - + v120 Imm(11) -> x0 + v121 Imm(12) -> x0 + v122 Imm(0) -> x0 + v123 Imm(12) -> x0 + v124 Imm(1) -> x0 + v125 LocalAddr(-3) -> x0 + v126 Imm(12) -> x1 + v127 BinopI { op=add, lhs=v125, rhs_imm=12 } -> x1 + v128 Imm(12) -> x1 + v129 Store { addr=v125, disp=12, value=v128, kind=I8 } -> - + v130 Imm(12) -> x0 + v131 Imm(13) -> x0 + v132 Imm(0) -> x0 + v133 Imm(13) -> x0 + v134 Imm(1) -> x0 + v135 LocalAddr(-3) -> x0 + v136 Imm(13) -> x1 + v137 BinopI { op=add, lhs=v135, rhs_imm=13 } -> x1 + v138 Imm(13) -> x1 + v139 Store { addr=v135, disp=13, value=v138, kind=I8 } -> - + v140 Imm(13) -> x0 + v141 Imm(14) -> x0 + v142 Imm(0) -> x0 + v143 Imm(14) -> x0 + v144 Imm(1) -> x0 + v145 LocalAddr(-3) -> x0 + v146 Imm(14) -> x1 + v147 BinopI { op=add, lhs=v145, rhs_imm=14 } -> x1 + v148 Imm(14) -> x1 + v149 Store { addr=v145, disp=14, value=v148, kind=I8 } -> - + v150 Imm(14) -> x0 + v151 Imm(15) -> x0 + v152 Imm(0) -> x0 + v153 Imm(15) -> x0 + v154 Imm(1) -> x0 + v155 LocalAddr(-3) -> x0 + v156 Imm(15) -> x1 + v157 BinopI { op=add, lhs=v155, rhs_imm=15 } -> x1 + v158 Imm(15) -> x1 + v159 Store { addr=v155, disp=15, value=v158, kind=I8 } -> - + v160 Imm(15) -> x0 + v161 Imm(16) -> x0 + v162 Imm(0) -> x0 + v163 Imm(16) -> x0 + v164 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v164) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v165 Imm(0) -> x1 + v166 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v165) block 3 start_pc=0 - v9 LocalAddr(-3) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 Binop { op=add, lhs=v9, rhs=v10 } -> x0 - v12 BinopI { op=and, lhs=v10, rhs_imm=255 } -> x2 - v13 Store { addr=v11, disp=0, value=v12, kind=I8 } -> - - terminator Jmp(b2) (exit_acc=v13) + v173 LocalAddr(-7) -> x2 + v174 Extend { value=v167, kind=I32 } -> x6 + v175 Binop { op=add, lhs=v173, rhs=v168 } -> x2 + v176 BinopI { op=and, lhs=v168, rhs_imm=255 } -> x6 + v177 Store { addr=v175, disp=0, value=v176, kind=I8 } -> - + terminator Jmp(b4) (exit_acc=v177) block 4 start_pc=0 - v14 Imm(0) -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v14) + v170 Extend { value=v167, kind=I32 } -> x1 + v171 BinopI { op=add, lhs=v168, rhs_imm=1 } -> x1 + v172 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v171) block 5 start_pc=0 - v16 Phi { incoming=[b4:v14, b6:v20], kind=I64 } -> x1 - v17 Extend { value=v16, kind=I32 } -> x0 - v18 BinopI { op=lt, lhs=v17, rhs_imm=32 } -> x0 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) + v167 Phi { incoming=[b2:v165, b4:v171], kind=I64 } -> x1 + v168 Extend { value=v167, kind=I32 } -> x0 + v169 BinopI { op=lt, lhs=v168, rhs_imm=32 } -> x2 + terminator Bnz { cond=v169, target=b3, fall=b6 } (exit_acc=v169) block 6 start_pc=0 - v19 Extend { value=v16, kind=I32 } -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x1 - v21 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v20) - block 7 start_pc=0 - v22 LocalAddr(-7) -> x0 - v23 Extend { value=v16, kind=I32 } -> x2 - v24 Binop { op=add, lhs=v22, rhs=v23 } -> x0 - v25 BinopI { op=and, lhs=v23, rhs_imm=255 } -> x2 - v26 Store { addr=v24, disp=0, value=v25, kind=I8 } -> - - terminator Jmp(b6) (exit_acc=v26) - block 8 start_pc=0 - v27 LocalAddr(-1) -> x7 - v28 LocalAddr(-3) -> x6 - v29 LocalAddr(-7) -> x2 - v30 ImmData(8) -> x1 - v31 Call { target_pc=1, args=[v27, v28, v29, v30], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v32 LocalAddr(-1) -> x0 - v33 Imm(0) -> x1 - v34 Load { addr=v32, disp=0, kind=U8 } -> x0 - terminator Return(v34) (exit_acc=v34) + v178 LocalAddr(-1) -> x7 + v179 LocalAddr(-3) -> x6 + v180 LocalAddr(-7) -> x2 + v181 ImmData(8) -> x1 + v182 Call { target_pc=1, args=[v178, v179, v180, v181], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v183 LocalAddr(-1) -> x0 + v184 Imm(0) -> x1 + v185 Load { addr=v183, disp=0, kind=U8 } -> x0 + terminator Return(v185) (exit_acc=v185) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/paren_string_char_array_init.ssa b/tests/snapshots/ssa/paren_string_char_array_init.ssa index 275f34bf7..46ee9b161 100644 --- a/tests/snapshots/ssa/paren_string_char_array_init.ssa +++ b/tests/snapshots/ssa/paren_string_char_array_init.ssa @@ -13,7 +13,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v7 BinopI { op=ne, lhs=v6, rhs_imm=0 } -> x1 v8 Imm(1) -> x6 v9 Imm(0) -> x2 - terminator Bnz { cond=v7, target=b29, fall=b1 } (exit_acc=v7) + terminator Bnz { cond=v7, target=b33, fall=b1 } (exit_acc=v7) block 1 start_pc=0 v10 ImmData(8) -> x1 v11 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -27,10 +27,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v19 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v20 Phi { incoming=[b29:v8, b1:v18], kind=I64 } -> x6 + v20 Phi { incoming=[b33:v8, b1:v18], kind=I64 } -> x6 v21 LoadLocal { off=-3, kind=I64 } -> x1 v22 Imm(0) -> x1 - terminator Bnz { cond=v20, target=b30, fall=b3 } (exit_acc=v20) + terminator Bnz { cond=v20, target=b32, fall=b3 } (exit_acc=v20) block 3 start_pc=0 v23 ImmData(8) -> x1 v24 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 @@ -43,7 +43,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v31 Imm(0) -> x1 terminator Jmp(b4) (exit_acc=v30) block 4 start_pc=0 - v32 Phi { incoming=[b30:v20, b3:v30], kind=I64 } -> x6 + v32 Phi { incoming=[b32:v20, b3:v30], kind=I64 } -> x6 v33 LoadLocal { off=-2, kind=I64 } -> x1 terminator Bz { cond=v32, target=b6, fall=b5 } (exit_acc=v32) block 5 start_pc=0 @@ -63,31 +63,31 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 block 8 start_pc=0 v42 Imm(0) -> x2 v43 Imm(0) -> x1 - terminator Jmp(b9) (exit_acc=v42) + terminator Jmp(b11) (exit_acc=v42) block 9 start_pc=0 - v44 Phi { incoming=[b8:v42, b10:v50], kind=I64 } -> x2 - v45 ImmData(101) -> x1 - v46 Extend { value=v44, kind=I32 } -> x6 - v47 Binop { op=add, lhs=v45, rhs=v46 } -> x1 - v48 Load { addr=v47, disp=0, kind=I8 } -> x1 - terminator Bz { cond=v48, target=b12, fall=b11 } (exit_acc=v48) - block 10 start_pc=0 - v49 Extend { value=v44, kind=I32 } -> x1 - v50 BinopI { op=add, lhs=v49, rhs_imm=1 } -> x2 - v51 Imm(0) -> x1 - terminator Jmp(b9) (exit_acc=v50) - block 11 start_pc=0 v52 ImmData(8) -> x1 v53 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 - v54 Extend { value=v44, kind=I32 } -> x6 - v55 Binop { op=add, lhs=v53, rhs=v54 } -> x1 + v54 Extend { value=v44, kind=I32 } -> x7 + v55 Binop { op=add, lhs=v53, rhs=v46 } -> x1 v56 Load { addr=v55, disp=0, kind=U8 } -> x1 v57 ImmData(110) -> x7 - v58 Binop { op=add, lhs=v57, rhs=v54 } -> x6 - v59 Load { addr=v58, disp=0, kind=I8 } -> x6 - v60 BinopI { op=and, lhs=v59, rhs_imm=255 } -> x6 + v58 Binop { op=add, lhs=v57, rhs=v46 } -> x7 + v59 Load { addr=v58, disp=0, kind=I8 } -> x7 + v60 BinopI { op=and, lhs=v59, rhs_imm=255 } -> x7 v61 Binop { op=ne, lhs=v56, rhs=v60 } -> x1 - terminator Bz { cond=v61, target=b14, fall=b13 } (exit_acc=v61) + terminator Bnz { cond=v61, target=b31, fall=b10 } (exit_acc=v61) + block 10 start_pc=0 + v49 Extend { value=v44, kind=I32 } -> x1 + v50 BinopI { op=add, lhs=v46, rhs_imm=1 } -> x2 + v51 Imm(0) -> x1 + terminator Jmp(b11) (exit_acc=v50) + block 11 start_pc=0 + v44 Phi { incoming=[b8:v42, b10:v50], kind=I64 } -> x2 + v45 ImmData(101) -> x1 + v46 Extend { value=v44, kind=I32 } -> x6 + v47 Binop { op=add, lhs=v45, rhs=v46 } -> x1 + v48 Load { addr=v47, disp=0, kind=I8 } -> x1 + terminator Bnz { cond=v48, target=b9, fall=b12 } (exit_acc=v48) block 12 start_pc=0 v62 ImmData(49) -> x0 v63 Imm(0) -> x1 @@ -95,13 +95,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v65 BinopI { op=ne, lhs=v64, rhs_imm=104 } -> x0 v66 Imm(1) -> x2 v67 Imm(0) -> x1 - terminator Bnz { cond=v65, target=b31, fall=b15 } (exit_acc=v65) + terminator Bnz { cond=v65, target=b30, fall=b13 } (exit_acc=v65) block 13 start_pc=0 - v68 Imm(3) -> x0 - terminator Return(v68) (exit_acc=v68) - block 14 start_pc=0 - terminator Jmp(b10) - block 15 start_pc=0 v69 ImmData(49) -> x0 v70 Imm(4) -> x1 v71 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x1 @@ -109,86 +104,91 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v73 BinopI { op=ne, lhs=v72, rhs_imm=111 } -> x0 v74 BinopI { op=ne, lhs=v73, rhs_imm=0 } -> x2 v75 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v74) - block 16 start_pc=0 - v76 Phi { incoming=[b31:v66, b15:v74], kind=I64 } -> x2 + terminator Jmp(b14) (exit_acc=v74) + block 14 start_pc=0 + v76 Phi { incoming=[b30:v66, b13:v74], kind=I64 } -> x2 v77 LoadLocal { off=-5, kind=I64 } -> x0 v78 Imm(0) -> x0 - terminator Bnz { cond=v76, target=b32, fall=b17 } (exit_acc=v76) - block 17 start_pc=0 + terminator Bnz { cond=v76, target=b29, fall=b15 } (exit_acc=v76) + block 15 start_pc=0 v79 ImmData(49) -> x0 v80 Imm(5) -> x1 v81 BinopI { op=add, lhs=v79, rhs_imm=5 } -> x1 v82 Load { addr=v79, disp=5, kind=I8 } -> x0 v83 BinopI { op=ne, lhs=v82, rhs_imm=0 } -> x2 v84 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v83) - block 18 start_pc=0 - v85 Phi { incoming=[b32:v76, b17:v83], kind=I64 } -> x2 + terminator Jmp(b16) (exit_acc=v83) + block 16 start_pc=0 + v85 Phi { incoming=[b29:v76, b15:v83], kind=I64 } -> x2 v86 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v85, target=b20, fall=b19 } (exit_acc=v85) - block 19 start_pc=0 + terminator Bz { cond=v85, target=b18, fall=b17 } (exit_acc=v85) + block 17 start_pc=0 v87 Imm(4) -> x0 terminator Return(v87) (exit_acc=v87) - block 20 start_pc=0 + block 18 start_pc=0 v88 ImmData(68) -> x0 v89 Imm(0) -> x1 v90 Load { addr=v88, disp=0, kind=I8 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=119 } -> x1 v92 Imm(0) -> x0 - terminator Bnz { cond=v91, target=b33, fall=b21 } (exit_acc=v91) - block 21 start_pc=0 + terminator Bnz { cond=v91, target=b28, fall=b19 } (exit_acc=v91) + block 19 start_pc=0 v93 ImmData(68) -> x0 v94 Imm(4) -> x1 v95 BinopI { op=add, lhs=v93, rhs_imm=4 } -> x1 v96 Load { addr=v93, disp=4, kind=I8 } -> x0 v97 BinopI { op=ne, lhs=v96, rhs_imm=100 } -> x1 v98 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v97) - block 22 start_pc=0 - v99 Phi { incoming=[b33:v91, b21:v97], kind=I64 } -> x1 + terminator Jmp(b20) (exit_acc=v97) + block 20 start_pc=0 + v99 Phi { incoming=[b28:v91, b19:v97], kind=I64 } -> x1 v100 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v99, target=b24, fall=b23 } (exit_acc=v99) - block 23 start_pc=0 + terminator Bz { cond=v99, target=b22, fall=b21 } (exit_acc=v99) + block 21 start_pc=0 v101 Imm(5) -> x0 terminator Return(v101) (exit_acc=v101) - block 24 start_pc=0 + block 22 start_pc=0 v102 ImmData(87) -> x0 v103 Imm(0) -> x1 v104 Load { addr=v102, disp=0, kind=I8 } -> x0 v105 BinopI { op=ne, lhs=v104, rhs_imm=112 } -> x1 v106 Imm(0) -> x0 - terminator Bnz { cond=v105, target=b34, fall=b25 } (exit_acc=v105) - block 25 start_pc=0 + terminator Bnz { cond=v105, target=b27, fall=b23 } (exit_acc=v105) + block 23 start_pc=0 v107 ImmData(87) -> x0 v108 Imm(4) -> x1 v109 BinopI { op=add, lhs=v107, rhs_imm=4 } -> x1 v110 Load { addr=v107, disp=4, kind=I8 } -> x0 v111 BinopI { op=ne, lhs=v110, rhs_imm=110 } -> x1 v112 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v111) - block 26 start_pc=0 - v113 Phi { incoming=[b34:v105, b25:v111], kind=I64 } -> x1 + terminator Jmp(b24) (exit_acc=v111) + block 24 start_pc=0 + v113 Phi { incoming=[b27:v105, b23:v111], kind=I64 } -> x1 v114 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v113, target=b28, fall=b27 } (exit_acc=v113) - block 27 start_pc=0 + terminator Bz { cond=v113, target=b26, fall=b25 } (exit_acc=v113) + block 25 start_pc=0 v115 Imm(6) -> x0 terminator Return(v115) (exit_acc=v115) - block 28 start_pc=0 + block 26 start_pc=0 v116 Imm(0) -> x0 terminator Return(v116) (exit_acc=v116) + block 27 start_pc=0 + terminator Jmp(b24) + block 28 start_pc=0 + terminator Jmp(b20) block 29 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b16) block 30 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b14) block 31 start_pc=0 - terminator Jmp(b16) + v68 Imm(3) -> x0 + terminator Return(v68) (exit_acc=v68) block 32 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b4) block 33 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b2) block 34 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/parenthesized_function_declarator.ssa b/tests/snapshots/ssa/parenthesized_function_declarator.ssa index 9cd78fb39..e096518a8 100644 --- a/tests/snapshots/ssa/parenthesized_function_declarator.ssa +++ b/tests/snapshots/ssa/parenthesized_function_declarator.ssa @@ -29,48 +29,48 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=4 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(10) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x3 + v2 Imm(10) -> x0 + v3 Imm(0) -> x0 + v4 Imm(11) -> x0 + v5 Imm(47244640256) -> x0 + v6 Imm(11) -> x0 v7 Imm(0) -> x0 v8 Imm(5) -> x7 v9 Call { target_pc=1, args=[v8], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v10 Imm(0) -> x1 - v11 Extend { value=v6, kind=I32 } -> x1 - v12 BinopI { op=ne, lhs=v11, rhs_imm=11 } -> x1 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v11 Imm(11) -> x1 + v12 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v12) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) - block 2 start_pc=0 v14 LoadLocal { off=-2, kind=I64 } -> x1 v15 BinopI { op=eq, lhs=v9, rhs_imm=0 } -> x2 v16 Imm(0) -> x1 - terminator Bnz { cond=v15, target=b7, fall=b3 } (exit_acc=v15) - block 3 start_pc=0 + terminator Bnz { cond=v15, target=b6, fall=b2 } (exit_acc=v15) + block 2 start_pc=0 v17 LoadLocal { off=-2, kind=I64 } -> x1 v18 Load { addr=v9, disp=0, kind=I32 } -> x0 v19 BinopI { op=ne, lhs=v18, rhs_imm=10 } -> x2 v20 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v19) - block 4 start_pc=0 - v21 Phi { incoming=[b7:v15, b3:v19], kind=I64 } -> x2 + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v21 Phi { incoming=[b6:v15, b2:v19], kind=I64 } -> x2 v22 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bz { cond=v21, target=b5, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 + block 5 start_pc=0 v24 Imm(0) -> x0 terminator Return(v24) (exit_acc=v24) + block 6 start_pc=0 + terminator Jmp(b3) block 7 start_pc=0 - terminator Jmp(b4) + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/phi_class_for_loop_sum.ssa b/tests/snapshots/ssa/phi_class_for_loop_sum.ssa index 073f2feae..f9cead3f1 100644 --- a/tests/snapshots/ssa/phi_class_for_loop_sum.ssa +++ b/tests/snapshots/ssa/phi_class_for_loop_sum.ssa @@ -9,27 +9,27 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v18], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x2 - v9 LoadLocal { off=2, kind=I32 } -> x6 - v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v14 Extend { value=v6, kind=I32 } -> x6 + v15 Extend { value=v7, kind=I32 } -> x6 + v16 Binop { op=add, lhs=v6, rhs=v7 } -> x1 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x6 + v18 Extend { value=v16, kind=I32 } -> x1 + v19 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 v11 Extend { value=v7, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x0 v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) + terminator Jmp(b3) (exit_acc=v12) block 3 start_pc=0 - v14 Extend { value=v6, kind=I32 } -> x2 - v15 Extend { value=v7, kind=I32 } -> x2 - v16 Binop { op=add, lhs=v6, rhs=v7 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x2 - v18 Extend { value=v16, kind=I32 } -> x1 - v19 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v18) + v6 Phi { incoming=[b0:v3, b2:v18], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x2 + v9 LoadLocal { off=2, kind=I32 } -> x6 + v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v20 Extend { value=v6, kind=I32 } -> x0 terminator Return(v20) (exit_acc=v20) diff --git a/tests/snapshots/ssa/phi_class_nested_loops.ssa b/tests/snapshots/ssa/phi_class_nested_loops.ssa index a163cc50c..164987de4 100644 --- a/tests/snapshots/ssa/phi_class_nested_loops.ssa +++ b/tests/snapshots/ssa/phi_class_nested_loops.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=test fn ent_pc=0 n_params=1 variadic=false locals=4 - spill_count=0 gpr_used=[] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 @@ -9,54 +9,54 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b7) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v35], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x2 - v9 LoadLocal { off=2, kind=I32 } -> x6 - v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) + v14 Imm(0) -> x8 + v15 Imm(0) -> x6 + v16 Imm(0) -> x6 + terminator Jmp(b4) (exit_acc=v14) block 2 start_pc=0 - v11 Extend { value=v7, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 - v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) + v26 Extend { value=v18, kind=I32 } -> x3 + v27 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x8 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x3 + v29 Extend { value=v27, kind=I32 } -> x8 + v30 Imm(0) -> x3 + terminator Jmp(b3) (exit_acc=v29) block 3 start_pc=0 - v14 Imm(0) -> x6 - v15 Imm(0) -> x2 - v16 Imm(0) -> x2 - terminator Jmp(b5) (exit_acc=v14) + v23 Extend { value=v19, kind=I32 } -> x6 + v24 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x6 + v25 Imm(0) -> x9 + terminator Jmp(b4) (exit_acc=v24) block 4 start_pc=0 - v17 Extend { value=v6, kind=I32 } -> x0 - terminator Return(v17) (exit_acc=v17) + v18 Phi { incoming=[b1:v14, b3:v29], kind=I64 } -> x8 + v19 Phi { incoming=[b1:v14, b3:v24], kind=I64 } -> x6 + v20 Extend { value=v19, kind=I32 } -> x9 + v21 LoadLocal { off=2, kind=I32 } -> x3 + v22 Binop { op=lt, lhs=v20, rhs=v1 } -> x3 + terminator Bnz { cond=v22, target=b2, fall=b5 } (exit_acc=v22) block 5 start_pc=0 - v18 Phi { incoming=[b3:v14, b6:v29], kind=I64 } -> x6 - v19 Phi { incoming=[b3:v14, b6:v24], kind=I64 } -> x2 - v20 Extend { value=v19, kind=I32 } -> x8 - v21 LoadLocal { off=2, kind=I32 } -> x9 - v22 Binop { op=lt, lhs=v20, rhs=v1 } -> x8 - terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) + v31 Extend { value=v6, kind=I32 } -> x6 + v32 Extend { value=v18, kind=I32 } -> x6 + v33 Binop { op=add, lhs=v6, rhs=v18 } -> x1 + v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x6 + v35 Extend { value=v33, kind=I32 } -> x1 + v36 Imm(0) -> x6 + terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v23 Extend { value=v19, kind=I32 } -> x2 - v24 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x2 - v25 Imm(0) -> x8 - terminator Jmp(b5) (exit_acc=v24) + v11 Extend { value=v7, kind=I32 } -> x0 + v12 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x0 + v13 Imm(0) -> x2 + terminator Jmp(b7) (exit_acc=v12) block 7 start_pc=0 - v26 Extend { value=v18, kind=I32 } -> x8 - v27 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x6 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x8 - v29 Extend { value=v27, kind=I32 } -> x6 - v30 Imm(0) -> x8 - terminator Jmp(b6) (exit_acc=v29) + v6 Phi { incoming=[b0:v3, b6:v35], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b6:v12], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x2 + v9 LoadLocal { off=2, kind=I32 } -> x6 + v10 Binop { op=lt, lhs=v8, rhs=v1 } -> x6 + terminator Bnz { cond=v10, target=b1, fall=b8 } (exit_acc=v10) block 8 start_pc=0 - v31 Extend { value=v6, kind=I32 } -> x2 - v32 Extend { value=v18, kind=I32 } -> x2 - v33 Binop { op=add, lhs=v6, rhs=v18 } -> x1 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x2 - v35 Extend { value=v33, kind=I32 } -> x1 - v36 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v35) + v17 Extend { value=v6, kind=I32 } -> x0 + terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/plain_char_signedness.ssa b/tests/snapshots/ssa/plain_char_signedness.ssa index 07021447a..3d3c62dad 100644 --- a/tests/snapshots/ssa/plain_char_signedness.ssa +++ b/tests/snapshots/ssa/plain_char_signedness.ssa @@ -5,14 +5,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-29) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I8 } -> x1 - v4 BinopI { op=ne, lhs=v1, rhs_imm=-29 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I8 } -> x0 + v4 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x0 - terminator Return(v5) (exit_acc=v5) - block 2 start_pc=0 v6 LocalAddr(-2) -> x0 v7 Imm(0) -> x1 v8 Imm(-29) -> x1 @@ -21,11 +18,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v11 LocalAddr(-2) -> x0 v12 Load { addr=v11, disp=0, kind=I8 } -> x0 v13 BinopI { op=ne, lhs=v12, rhs_imm=-29 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) - block 3 start_pc=0 + terminator Bz { cond=v13, target=b3, fall=b2 } (exit_acc=v13) + block 2 start_pc=0 v14 Imm(2) -> x0 terminator Return(v14) (exit_acc=v14) - block 4 start_pc=0 + block 3 start_pc=0 v15 LocalAddr(-3) -> x0 v16 Imm(-29) -> x1 v17 Store { addr=v15, disp=0, value=v16, kind=I8 } -> - @@ -33,11 +30,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v19 LocalAddr(-3) -> x0 v20 Load { addr=v19, disp=0, kind=I8 } -> x0 v21 BinopI { op=ne, lhs=v20, rhs_imm=-29 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bz { cond=v21, target=b5, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v22 Imm(3) -> x0 terminator Return(v22) (exit_acc=v22) - block 6 start_pc=0 + block 5 start_pc=0 v23 Imm(227) -> x0 v24 StoreLocal { off=-4, value=v23, kind=I8 } -> - v25 LocalAddr(-4) -> x0 @@ -45,31 +42,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v27 LoadLocal { off=-5, kind=I64 } -> x1 v28 Load { addr=v25, disp=0, kind=I8 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=-29 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) - block 7 start_pc=0 + terminator Bz { cond=v29, target=b7, fall=b6 } (exit_acc=v29) + block 6 start_pc=0 v30 Imm(4) -> x0 terminator Return(v30) (exit_acc=v30) - block 8 start_pc=0 + block 7 start_pc=0 v31 Imm(-29) -> x0 - v32 Imm(0) -> x1 - v33 LoadLocal { off=-6, kind=I8 } -> x1 - v34 BinopI { op=ne, lhs=v31, rhs_imm=-29 } -> x0 - terminator Bz { cond=v34, target=b10, fall=b9 } (exit_acc=v34) + v32 Imm(0) -> x0 + v33 LoadLocal { off=-6, kind=I8 } -> x0 + v34 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v34) + block 8 start_pc=0 + v36 Imm(227) -> x0 + v37 Imm(0) -> x0 + v38 LoadLocal { off=-7, kind=U8 } -> x0 + v39 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v39) block 9 start_pc=0 - v35 Imm(5) -> x0 - terminator Return(v35) (exit_acc=v35) + v41 Imm(0) -> x0 + terminator Return(v41) (exit_acc=v41) block 10 start_pc=0 - v36 Imm(227) -> x0 - v37 Imm(0) -> x1 - v38 LoadLocal { off=-7, kind=U8 } -> x1 - v39 BinopI { op=ne, lhs=v36, rhs_imm=227 } -> x0 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) block 11 start_pc=0 + v35 Imm(5) -> x0 + terminator Return(v35) (exit_acc=v35) + block 12 start_pc=0 v40 Imm(6) -> x0 terminator Return(v40) (exit_acc=v40) - block 12 start_pc=0 - v41 Imm(0) -> x0 - terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/pointer_arithmetic_scaling.ssa b/tests/snapshots/ssa/pointer_arithmetic_scaling.ssa index 64410ac2f..ef60ed7a1 100644 --- a/tests/snapshots/ssa/pointer_arithmetic_scaling.ssa +++ b/tests/snapshots/ssa/pointer_arithmetic_scaling.ssa @@ -6,10 +6,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(100) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 Imm(4) -> x1 - v5 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(4) -> x0 + v5 Imm(104) -> x0 terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/pointer_to_array_arithmetic.ssa b/tests/snapshots/ssa/pointer_to_array_arithmetic.ssa index 206d4aea3..a220ff707 100644 --- a/tests/snapshots/ssa/pointer_to_array_arithmetic.ssa +++ b/tests/snapshots/ssa/pointer_to_array_arithmetic.ssa @@ -46,7 +46,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v28 Load { addr=v20, disp=0, kind=I32 } -> x6 v29 BinopI { op=ne, lhs=v28, rhs_imm=4 } -> x7 v30 Imm(0) -> x6 - terminator Bnz { cond=v29, target=b19, fall=b7 } (exit_acc=v29) + terminator Bnz { cond=v29, target=b20, fall=b7 } (exit_acc=v29) block 7 start_pc=0 v31 LoadLocal { off=-2, kind=I64 } -> x6 v32 Imm(4) -> x6 @@ -56,7 +56,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v36 Imm(0) -> x2 terminator Jmp(b8) (exit_acc=v35) block 8 start_pc=0 - v37 Phi { incoming=[b19:v29, b7:v35], kind=I64 } -> x7 + v37 Phi { incoming=[b20:v29, b7:v35], kind=I64 } -> x7 v38 LoadLocal { off=-7, kind=I64 } -> x2 terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) block 9 start_pc=0 @@ -93,14 +93,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v63 Extend { value=v57, kind=I32 } -> x6 v64 BinopI { op=ne, lhs=v57, rhs_imm=1 } -> x6 v65 Imm(0) -> x2 - terminator Bnz { cond=v64, target=b20, fall=b13 } (exit_acc=v64) + terminator Bnz { cond=v64, target=b19, fall=b13 } (exit_acc=v64) block 13 start_pc=0 v66 Extend { value=v61, kind=I32 } -> x2 v67 BinopI { op=ne, lhs=v61, rhs_imm=3 } -> x6 v68 Imm(0) -> x1 terminator Jmp(b14) (exit_acc=v67) block 14 start_pc=0 - v69 Phi { incoming=[b20:v64, b13:v67], kind=I64 } -> x6 + v69 Phi { incoming=[b19:v64, b13:v67], kind=I64 } -> x6 v70 LoadLocal { off=-8, kind=I64 } -> x1 terminator Bz { cond=v69, target=b16, fall=b15 } (exit_acc=v69) block 15 start_pc=0 @@ -125,9 +125,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=8 v83 Imm(0) -> x0 terminator Return(v83) (exit_acc=v83) block 19 start_pc=0 - terminator Jmp(b8) - block 20 start_pc=0 terminator Jmp(b14) + block 20 start_pc=0 + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/pointer_to_array_cast.ssa b/tests/snapshots/ssa/pointer_to_array_cast.ssa index b5609dca7..de6c5acfe 100644 --- a/tests/snapshots/ssa/pointer_to_array_cast.ssa +++ b/tests/snapshots/ssa/pointer_to_array_cast.ssa @@ -6,29 +6,29 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=24 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) - block 3 start_pc=0 - v9 LocalAddr(-6) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=1 } -> x6 + v9 LocalAddr(-6) -> x2 + v10 Extend { value=v3, kind=I32 } -> x6 + v11 BinopI { op=shl, lhs=v4, rhs_imm=1 } -> x6 v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 - v13 BinopI { op=mul, lhs=v10, rhs_imm=3 } -> x6 + v13 BinopI { op=mul, lhs=v4, rhs_imm=3 } -> x6 v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 v15 Extend { value=v13, kind=I32 } -> x7 v16 BinopI { op=shl, lhs=v13, rhs_imm=48 } -> x6 v17 Extend { value=v15, kind=I16 } -> x6 - v18 StoreIndexed { base=v9, index=v10, scale=2, value=v15, kind=I16 } -> - + v18 StoreIndexed { base=v9, index=v4, scale=2, value=v15, kind=I16 } -> - terminator Jmp(b2) (exit_acc=v18) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=24 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) block 4 start_pc=0 v19 LocalAddr(-6) -> x0 v20 Imm(0) -> x1 diff --git a/tests/snapshots/ssa/pointer_to_array_struct_field.ssa b/tests/snapshots/ssa/pointer_to_array_struct_field.ssa index 0a954ac91..38edf0756 100644 --- a/tests/snapshots/ssa/pointer_to_array_struct_field.ssa +++ b/tests/snapshots/ssa/pointer_to_array_struct_field.ssa @@ -19,141 +19,292 @@ fn ent_pc=6 n_params=0 variadic=false locals=4 block 2 start_pc=0 v10 Imm(0) -> x1 v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v10) + terminator Jmp(b6) (exit_acc=v10) block 3 start_pc=0 - v12 Phi { incoming=[b2:v10, b4:v16], kind=I64 } -> x1 - v13 Extend { value=v12, kind=I32 } -> x0 - v14 BinopI { op=lt, lhs=v13, rhs_imm=4 } -> x0 - terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) + v18 Imm(0) -> x2 + v19 Imm(0) -> x6 + terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v15 Extend { value=v12, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x1 - v17 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v16) + v22 Imm(0) -> x2 + v23 Imm(1) -> x2 + v24 LocalAddr(-1) -> x2 + v25 Load { addr=v24, disp=0, kind=I64 } -> x2 + v26 Extend { value=v12, kind=I32 } -> x6 + v27 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v28 Binop { op=add, lhs=v25, rhs=v27 } -> x2 + v29 Imm(0) -> x6 + v30 Imm(0) -> x6 + v31 BinopI { op=add, lhs=v28, rhs_imm=0 } -> x2 + v32 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x7 + v34 Extend { value=v32, kind=I32 } -> x7 + v35 BinopI { op=add, lhs=v32, rhs_imm=0 } -> x6 + v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x7 + v37 Extend { value=v35, kind=I32 } -> x7 + v38 BinopI { op=shl, lhs=v35, rhs_imm=48 } -> x6 + v39 Extend { value=v37, kind=I16 } -> x6 + v40 Store { addr=v31, disp=0, value=v37, kind=I16 } -> - + v41 Imm(0) -> x2 + v42 Imm(1) -> x2 + v43 Imm(0) -> x2 + v44 Imm(1) -> x2 + v45 Imm(1) -> x2 + v46 LocalAddr(-1) -> x2 + v47 Load { addr=v46, disp=0, kind=I64 } -> x2 + v48 Extend { value=v12, kind=I32 } -> x6 + v49 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v50 Binop { op=add, lhs=v47, rhs=v49 } -> x2 + v51 Imm(1) -> x6 + v52 Imm(2) -> x6 + v53 BinopI { op=add, lhs=v50, rhs_imm=2 } -> x6 + v54 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x7 + v56 Extend { value=v54, kind=I32 } -> x7 + v57 BinopI { op=add, lhs=v54, rhs_imm=1 } -> x6 + v58 BinopI { op=shl, lhs=v57, rhs_imm=32 } -> x7 + v59 Extend { value=v57, kind=I32 } -> x7 + v60 BinopI { op=shl, lhs=v57, rhs_imm=48 } -> x6 + v61 Extend { value=v59, kind=I16 } -> x6 + v62 Store { addr=v50, disp=2, value=v59, kind=I16 } -> - + v63 Imm(1) -> x2 + v64 Imm(2) -> x2 + v65 Imm(0) -> x2 + v66 Imm(2) -> x2 + v67 Imm(1) -> x2 + v68 LocalAddr(-1) -> x2 + v69 Load { addr=v68, disp=0, kind=I64 } -> x2 + v70 Extend { value=v12, kind=I32 } -> x6 + v71 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v72 Binop { op=add, lhs=v69, rhs=v71 } -> x2 + v73 Imm(2) -> x6 + v74 Imm(4) -> x6 + v75 BinopI { op=add, lhs=v72, rhs_imm=4 } -> x6 + v76 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v77 BinopI { op=shl, lhs=v76, rhs_imm=32 } -> x7 + v78 Extend { value=v76, kind=I32 } -> x7 + v79 BinopI { op=add, lhs=v76, rhs_imm=2 } -> x6 + v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x7 + v81 Extend { value=v79, kind=I32 } -> x7 + v82 BinopI { op=shl, lhs=v79, rhs_imm=48 } -> x6 + v83 Extend { value=v81, kind=I16 } -> x6 + v84 Store { addr=v72, disp=4, value=v81, kind=I16 } -> - + v85 Imm(2) -> x2 + v86 Imm(3) -> x2 + v87 Imm(0) -> x2 + v88 Imm(3) -> x2 + v89 Imm(1) -> x2 + v90 LocalAddr(-1) -> x2 + v91 Load { addr=v90, disp=0, kind=I64 } -> x2 + v92 Extend { value=v12, kind=I32 } -> x6 + v93 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v94 Binop { op=add, lhs=v91, rhs=v93 } -> x2 + v95 Imm(3) -> x6 + v96 Imm(6) -> x6 + v97 BinopI { op=add, lhs=v94, rhs_imm=6 } -> x6 + v98 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v99 BinopI { op=shl, lhs=v98, rhs_imm=32 } -> x7 + v100 Extend { value=v98, kind=I32 } -> x7 + v101 BinopI { op=add, lhs=v98, rhs_imm=3 } -> x6 + v102 BinopI { op=shl, lhs=v101, rhs_imm=32 } -> x7 + v103 Extend { value=v101, kind=I32 } -> x7 + v104 BinopI { op=shl, lhs=v101, rhs_imm=48 } -> x6 + v105 Extend { value=v103, kind=I16 } -> x6 + v106 Store { addr=v94, disp=6, value=v103, kind=I16 } -> - + v107 Imm(3) -> x2 + v108 Imm(4) -> x2 + v109 Imm(0) -> x2 + v110 Imm(4) -> x2 + v111 Imm(1) -> x2 + v112 LocalAddr(-1) -> x2 + v113 Load { addr=v112, disp=0, kind=I64 } -> x2 + v114 Extend { value=v12, kind=I32 } -> x6 + v115 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v116 Binop { op=add, lhs=v113, rhs=v115 } -> x2 + v117 Imm(4) -> x6 + v118 Imm(8) -> x6 + v119 BinopI { op=add, lhs=v116, rhs_imm=8 } -> x6 + v120 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v121 BinopI { op=shl, lhs=v120, rhs_imm=32 } -> x7 + v122 Extend { value=v120, kind=I32 } -> x7 + v123 BinopI { op=add, lhs=v120, rhs_imm=4 } -> x6 + v124 BinopI { op=shl, lhs=v123, rhs_imm=32 } -> x7 + v125 Extend { value=v123, kind=I32 } -> x7 + v126 BinopI { op=shl, lhs=v123, rhs_imm=48 } -> x6 + v127 Extend { value=v125, kind=I16 } -> x6 + v128 Store { addr=v116, disp=8, value=v125, kind=I16 } -> - + v129 Imm(4) -> x2 + v130 Imm(5) -> x2 + v131 Imm(0) -> x2 + v132 Imm(5) -> x2 + v133 Imm(1) -> x2 + v134 LocalAddr(-1) -> x2 + v135 Load { addr=v134, disp=0, kind=I64 } -> x2 + v136 Extend { value=v12, kind=I32 } -> x6 + v137 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v138 Binop { op=add, lhs=v135, rhs=v137 } -> x2 + v139 Imm(5) -> x6 + v140 Imm(10) -> x6 + v141 BinopI { op=add, lhs=v138, rhs_imm=10 } -> x6 + v142 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v143 BinopI { op=shl, lhs=v142, rhs_imm=32 } -> x7 + v144 Extend { value=v142, kind=I32 } -> x7 + v145 BinopI { op=add, lhs=v142, rhs_imm=5 } -> x6 + v146 BinopI { op=shl, lhs=v145, rhs_imm=32 } -> x7 + v147 Extend { value=v145, kind=I32 } -> x7 + v148 BinopI { op=shl, lhs=v145, rhs_imm=48 } -> x6 + v149 Extend { value=v147, kind=I16 } -> x6 + v150 Store { addr=v138, disp=10, value=v147, kind=I16 } -> - + v151 Imm(5) -> x2 + v152 Imm(6) -> x2 + v153 Imm(0) -> x2 + v154 Imm(6) -> x2 + v155 Imm(1) -> x2 + v156 LocalAddr(-1) -> x2 + v157 Load { addr=v156, disp=0, kind=I64 } -> x2 + v158 Extend { value=v12, kind=I32 } -> x6 + v159 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v160 Binop { op=add, lhs=v157, rhs=v159 } -> x2 + v161 Imm(6) -> x6 + v162 Imm(12) -> x6 + v163 BinopI { op=add, lhs=v160, rhs_imm=12 } -> x6 + v164 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v165 BinopI { op=shl, lhs=v164, rhs_imm=32 } -> x7 + v166 Extend { value=v164, kind=I32 } -> x7 + v167 BinopI { op=add, lhs=v164, rhs_imm=6 } -> x6 + v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x7 + v169 Extend { value=v167, kind=I32 } -> x7 + v170 BinopI { op=shl, lhs=v167, rhs_imm=48 } -> x6 + v171 Extend { value=v169, kind=I16 } -> x6 + v172 Store { addr=v160, disp=12, value=v169, kind=I16 } -> - + v173 Imm(6) -> x2 + v174 Imm(7) -> x2 + v175 Imm(0) -> x2 + v176 Imm(7) -> x2 + v177 Imm(1) -> x2 + v178 LocalAddr(-1) -> x2 + v179 Load { addr=v178, disp=0, kind=I64 } -> x2 + v180 Extend { value=v12, kind=I32 } -> x6 + v181 BinopI { op=shl, lhs=v13, rhs_imm=4 } -> x6 + v182 Binop { op=add, lhs=v179, rhs=v181 } -> x2 + v183 Imm(7) -> x6 + v184 Imm(14) -> x6 + v185 BinopI { op=add, lhs=v182, rhs_imm=14 } -> x6 + v186 BinopI { op=mul, lhs=v13, rhs_imm=100 } -> x6 + v187 BinopI { op=shl, lhs=v186, rhs_imm=32 } -> x7 + v188 Extend { value=v186, kind=I32 } -> x7 + v189 BinopI { op=add, lhs=v186, rhs_imm=7 } -> x6 + v190 BinopI { op=shl, lhs=v189, rhs_imm=32 } -> x7 + v191 Extend { value=v189, kind=I32 } -> x7 + v192 BinopI { op=shl, lhs=v189, rhs_imm=48 } -> x6 + v193 Extend { value=v191, kind=I16 } -> x6 + v194 Store { addr=v182, disp=14, value=v191, kind=I16 } -> - + v195 Imm(7) -> x2 + v196 Imm(8) -> x2 + v197 Imm(0) -> x2 + v198 Imm(8) -> x2 + v199 Imm(0) -> x2 + terminator Jmp(b5) (exit_acc=v199) block 5 start_pc=0 - v18 Imm(0) -> x2 - v19 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v18) + v15 Extend { value=v12, kind=I32 } -> x1 + v16 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v16) block 6 start_pc=0 + v12 Phi { incoming=[b2:v10, b5:v16], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=lt, lhs=v13, rhs_imm=4 } -> x2 + terminator Bnz { cond=v14, target=b3, fall=b7 } (exit_acc=v14) + block 7 start_pc=0 v20 Imm(0) -> x1 v21 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v20) - block 7 start_pc=0 - v22 Phi { incoming=[b5:v18, b8:v26], kind=I64 } -> x2 - v23 Extend { value=v22, kind=I32 } -> x0 - v24 BinopI { op=lt, lhs=v23, rhs_imm=8 } -> x0 - terminator Bz { cond=v24, target=b10, fall=b9 } (exit_acc=v24) + terminator Jmp(b13) (exit_acc=v20) block 8 start_pc=0 - v25 Extend { value=v22, kind=I32 } -> x0 - v26 BinopI { op=add, lhs=v25, rhs_imm=1 } -> x2 - v27 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v26) + v206 Imm(0) -> x6 + v207 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v206) block 9 start_pc=0 - v28 LocalAddr(-1) -> x0 - v29 Load { addr=v28, disp=0, kind=I64 } -> x0 - v30 Extend { value=v12, kind=I32 } -> x6 - v31 BinopI { op=shl, lhs=v30, rhs_imm=4 } -> x7 - v32 Binop { op=add, lhs=v29, rhs=v31 } -> x0 - v33 Extend { value=v22, kind=I32 } -> x7 - v34 BinopI { op=shl, lhs=v33, rhs_imm=1 } -> x8 - v35 Binop { op=add, lhs=v32, rhs=v34 } -> x8 - v36 BinopI { op=mul, lhs=v30, rhs_imm=100 } -> x6 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x8 - v38 Extend { value=v36, kind=I32 } -> x8 - v39 Binop { op=add, lhs=v36, rhs=v33 } -> x6 - v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x8 - v41 Extend { value=v39, kind=I32 } -> x8 - v42 BinopI { op=shl, lhs=v39, rhs_imm=48 } -> x6 - v43 Extend { value=v41, kind=I16 } -> x6 - v44 StoreIndexed { base=v32, index=v33, scale=2, value=v41, kind=I16 } -> - - terminator Jmp(b8) (exit_acc=v44) + v224 LocalAddr(-1) -> x7 + v225 Load { addr=v224, disp=0, kind=I64 } -> x7 + v226 Extend { value=v200, kind=I32 } -> x8 + v227 BinopI { op=shl, lhs=v201, rhs_imm=4 } -> x8 + v228 Binop { op=add, lhs=v225, rhs=v227 } -> x7 + v229 Extend { value=v218, kind=I32 } -> x8 + v230 BinopI { op=shl, lhs=v219, rhs_imm=1 } -> x8 + v231 Binop { op=add, lhs=v228, rhs=v230 } -> x8 + v232 LoadIndexed { base=v228, index=v219, scale=2, kind=I16 } -> x7 + v233 BinopI { op=mul, lhs=v201, rhs_imm=100 } -> x8 + v234 BinopI { op=shl, lhs=v233, rhs_imm=32 } -> x9 + v235 Extend { value=v233, kind=I32 } -> x9 + v236 Binop { op=add, lhs=v233, rhs=v219 } -> x8 + v237 BinopI { op=shl, lhs=v236, rhs_imm=32 } -> x9 + v238 Extend { value=v236, kind=I32 } -> x9 + v239 BinopI { op=shl, lhs=v236, rhs_imm=48 } -> x8 + v240 Extend { value=v238, kind=I16 } -> x8 + v241 Binop { op=ne, lhs=v232, rhs=v240 } -> x7 + terminator Bnz { cond=v241, target=b17, fall=b10 } (exit_acc=v241) block 10 start_pc=0 - terminator Jmp(b4) + v221 Extend { value=v218, kind=I32 } -> x6 + v222 BinopI { op=add, lhs=v219, rhs_imm=1 } -> x6 + v223 Imm(0) -> x2 + terminator Jmp(b11) (exit_acc=v222) block 11 start_pc=0 - v45 Phi { incoming=[b6:v20, b12:v49], kind=I64 } -> x1 - v46 Extend { value=v45, kind=I32 } -> x0 - v47 BinopI { op=lt, lhs=v46, rhs_imm=4 } -> x0 - terminator Bz { cond=v47, target=b14, fall=b13 } (exit_acc=v47) + v218 Phi { incoming=[b8:v206, b10:v222], kind=I64 } -> x6 + v219 Extend { value=v218, kind=I32 } -> x2 + v220 BinopI { op=lt, lhs=v219, rhs_imm=8 } -> x7 + terminator Bnz { cond=v220, target=b9, fall=b12 } (exit_acc=v220) block 12 start_pc=0 - v48 Extend { value=v45, kind=I32 } -> x0 - v49 BinopI { op=add, lhs=v48, rhs_imm=1 } -> x1 - v50 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v49) + v203 Extend { value=v200, kind=I32 } -> x1 + v204 BinopI { op=add, lhs=v201, rhs_imm=1 } -> x1 + v205 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v204) block 13 start_pc=0 - v51 Imm(0) -> x2 - v52 Imm(0) -> x0 - terminator Jmp(b15) (exit_acc=v51) + v200 Phi { incoming=[b7:v20, b12:v204], kind=I64 } -> x1 + v201 Extend { value=v200, kind=I32 } -> x0 + v202 BinopI { op=lt, lhs=v201, rhs_imm=4 } -> x2 + terminator Bnz { cond=v202, target=b8, fall=b14 } (exit_acc=v202) block 14 start_pc=0 - v53 LocalAddr(-1) -> x0 - v54 Load { addr=v53, disp=0, kind=I64 } -> x0 - v55 Imm(0) -> x1 - v56 Imm(-1) -> x1 - v57 Store { addr=v54, disp=0, value=v56, kind=I16 } -> - - v58 Imm(-281474976710656) -> x0 - v59 LocalAddr(-1) -> x0 - v60 Load { addr=v59, disp=0, kind=I64 } -> x0 - v61 Load { addr=v60, disp=0, kind=I16 } -> x0 - v62 BinopI { op=ne, lhs=v61, rhs_imm=-1 } -> x0 - terminator Bz { cond=v62, target=b22, fall=b21 } (exit_acc=v62) + v208 LocalAddr(-1) -> x0 + v209 Load { addr=v208, disp=0, kind=I64 } -> x0 + v210 Imm(0) -> x1 + v211 Imm(-1) -> x1 + v212 Store { addr=v209, disp=0, value=v211, kind=I16 } -> - + v213 Imm(-281474976710656) -> x0 + v214 LocalAddr(-1) -> x0 + v215 Load { addr=v214, disp=0, kind=I64 } -> x0 + v216 Load { addr=v215, disp=0, kind=I16 } -> x0 + v217 BinopI { op=ne, lhs=v216, rhs_imm=-1 } -> x0 + terminator Bz { cond=v217, target=b16, fall=b15 } (exit_acc=v217) block 15 start_pc=0 - v63 Phi { incoming=[b13:v51, b16:v67], kind=I64 } -> x2 - v64 Extend { value=v63, kind=I32 } -> x0 - v65 BinopI { op=lt, lhs=v64, rhs_imm=8 } -> x0 - terminator Bz { cond=v65, target=b18, fall=b17 } (exit_acc=v65) + v254 Imm(99) -> x0 + terminator Return(v254) (exit_acc=v254) block 16 start_pc=0 - v66 Extend { value=v63, kind=I32 } -> x0 - v67 BinopI { op=add, lhs=v66, rhs_imm=1 } -> x2 - v68 Imm(0) -> x0 - terminator Jmp(b15) (exit_acc=v67) + v255 LocalAddr(-1) -> x0 + v256 Load { addr=v255, disp=0, kind=I64 } -> x7 + v257 CallExt { binding_idx=57, args=[v256], fp_arg_mask=0x0 } -> x0 + v258 ImmData(36) -> x7 + v259 CallExt { binding_idx=0, args=[v258], fp_arg_mask=0x0 } -> x0 + v260 Imm(0) -> x0 + terminator Return(v260) (exit_acc=v260) block 17 start_pc=0 - v69 LocalAddr(-1) -> x0 - v70 Load { addr=v69, disp=0, kind=I64 } -> x0 - v71 Extend { value=v45, kind=I32 } -> x6 - v72 BinopI { op=shl, lhs=v71, rhs_imm=4 } -> x7 - v73 Binop { op=add, lhs=v70, rhs=v72 } -> x0 - v74 Extend { value=v63, kind=I32 } -> x7 - v75 BinopI { op=shl, lhs=v74, rhs_imm=1 } -> x8 - v76 Binop { op=add, lhs=v73, rhs=v75 } -> x8 - v77 LoadIndexed { base=v73, index=v74, scale=2, kind=I16 } -> x0 - v78 BinopI { op=mul, lhs=v71, rhs_imm=100 } -> x6 - v79 BinopI { op=shl, lhs=v78, rhs_imm=32 } -> x8 - v80 Extend { value=v78, kind=I32 } -> x8 - v81 Binop { op=add, lhs=v78, rhs=v74 } -> x6 - v82 BinopI { op=shl, lhs=v81, rhs_imm=32 } -> x7 - v83 Extend { value=v81, kind=I32 } -> x7 - v84 BinopI { op=shl, lhs=v81, rhs_imm=48 } -> x6 - v85 Extend { value=v83, kind=I16 } -> x6 - v86 Binop { op=ne, lhs=v77, rhs=v85 } -> x0 - terminator Bz { cond=v86, target=b20, fall=b19 } (exit_acc=v86) + v242 Imm(10) -> x0 + v243 Extend { value=v200, kind=I32 } -> x0 + v244 BinopI { op=shl, lhs=v200, rhs_imm=3 } -> x0 + v245 BinopI { op=shl, lhs=v244, rhs_imm=32 } -> x1 + v246 Extend { value=v244, kind=I32 } -> x1 + v247 BinopI { op=add, lhs=v244, rhs_imm=10 } -> x0 + v248 BinopI { op=shl, lhs=v247, rhs_imm=32 } -> x1 + v249 Extend { value=v247, kind=I32 } -> x1 + v250 Extend { value=v218, kind=I32 } -> x1 + v251 Binop { op=add, lhs=v247, rhs=v218 } -> x0 + v252 BinopI { op=shl, lhs=v251, rhs_imm=32 } -> x1 + v253 Extend { value=v251, kind=I32 } -> x0 + terminator Return(v253) (exit_acc=v253) block 18 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b5) block 19 start_pc=0 - v87 Imm(10) -> x0 - v88 Extend { value=v45, kind=I32 } -> x0 - v89 BinopI { op=shl, lhs=v45, rhs_imm=3 } -> x0 - v90 BinopI { op=shl, lhs=v89, rhs_imm=32 } -> x1 - v91 Extend { value=v89, kind=I32 } -> x1 - v92 BinopI { op=add, lhs=v89, rhs_imm=10 } -> x0 - v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x1 - v94 Extend { value=v92, kind=I32 } -> x1 - v95 Extend { value=v63, kind=I32 } -> x1 - v96 Binop { op=add, lhs=v92, rhs=v63 } -> x0 - v97 BinopI { op=shl, lhs=v96, rhs_imm=32 } -> x1 - v98 Extend { value=v96, kind=I32 } -> x0 - terminator Return(v98) (exit_acc=v98) + terminator Jmp(b12) block 20 start_pc=0 - terminator Jmp(b16) - block 21 start_pc=0 - v99 Imm(99) -> x0 - terminator Return(v99) (exit_acc=v99) - block 22 start_pc=0 - v100 LocalAddr(-1) -> x0 - v101 Load { addr=v100, disp=0, kind=I64 } -> x7 - v102 CallExt { binding_idx=57, args=[v101], fp_arg_mask=0x0 } -> x0 - v103 ImmData(36) -> x7 - v104 CallExt { binding_idx=0, args=[v103], fp_arg_mask=0x0 } -> x0 - v105 Imm(0) -> x0 - terminator Return(v105) (exit_acc=v105) + terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/posix_module_headers.ssa b/tests/snapshots/ssa/posix_module_headers.ssa index e8a798b35..a9293265a 100644 --- a/tests/snapshots/ssa/posix_module_headers.ssa +++ b/tests/snapshots/ssa/posix_module_headers.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=123 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(65) -> x7 @@ -16,17 +16,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=123 block 2 start_pc=0 v7 Extend { value=v2, kind=I32 } -> x7 v8 CallExt { binding_idx=25, args=[v7], fp_arg_mask=0x0 } -> x0 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x12 + v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 v10 Imm(0) -> x0 - terminator Bnz { cond=v9, target=b47, fall=b3 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b50, fall=b3 } (exit_acc=v9) block 3 start_pc=0 v11 Extend { value=v2, kind=I32 } -> x7 v12 CallExt { binding_idx=35, args=[v11], fp_arg_mask=0x0 } -> x0 - v13 BinopI { op=eq, lhs=v12, rhs_imm=0 } -> x12 + v13 BinopI { op=eq, lhs=v12, rhs_imm=0 } -> x1 v14 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v13) block 4 start_pc=0 - v15 Phi { incoming=[b47:v9, b3:v13], kind=I64 } -> x12 + v15 Phi { incoming=[b50:v9, b3:v13], kind=I64 } -> x1 v16 LoadLocal { off=-115, kind=I64 } -> x0 terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) block 5 start_pc=0 @@ -96,34 +96,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=123 v54 Imm(2) -> x0 v55 Imm(8589934592) -> x0 v56 Imm(3) -> x0 - v57 Imm(12884901888) -> x1 - v58 Imm(0) -> x1 - v59 Imm(1) -> x3 - v60 Imm(4294967296) -> x1 - v61 Imm(0) -> x1 - v62 Imm(0) -> x1 - v63 LoadLocal { off=-18, kind=I32 } -> x1 - v64 BinopI { op=lt, lhs=v56, rhs_imm=0 } -> x1 - v65 Imm(0) -> x2 - terminator Bnz { cond=v64, target=b48, fall=b19 } (exit_acc=v64) + v57 Imm(12884901888) -> x0 + v58 Imm(0) -> x0 + v59 Imm(1) -> x2 + v60 Imm(4294967296) -> x0 + v61 Imm(0) -> x0 + v62 Imm(0) -> x0 + v63 LoadLocal { off=-18, kind=I32 } -> x0 + v64 Imm(0) -> x0 + v65 Imm(0) -> x1 + terminator Jmp(b19) (exit_acc=v64) block 19 start_pc=0 - v66 LoadLocal { off=-19, kind=I32 } -> x1 - v67 BinopI { op=lt, lhs=v56, rhs_imm=0 } -> x0 - v68 BinopI { op=ne, lhs=v67, rhs_imm=0 } -> x12 + v66 LoadLocal { off=-19, kind=I32 } -> x0 + v67 Imm(0) -> x0 + v68 Imm(0) -> x2 v69 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v68) block 20 start_pc=0 - v70 Phi { incoming=[b48:v59, b19:v68], kind=I64 } -> x12 + v70 Phi { incoming=[b18:v59, b19:v68], kind=I64 } -> x2 v71 LoadLocal { off=-117, kind=I64 } -> x0 v72 Imm(0) -> x0 terminator Bnz { cond=v70, target=b49, fall=b21 } (exit_acc=v70) block 21 start_pc=0 v73 LoadLocal { off=-20, kind=I32 } -> x0 - v74 BinopI { op=ne, lhs=v59, rhs_imm=1 } -> x12 + v74 Imm(0) -> x2 v75 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v74) block 22 start_pc=0 - v76 Phi { incoming=[b49:v70, b21:v74], kind=I64 } -> x12 + v76 Phi { incoming=[b49:v70, b21:v74], kind=I64 } -> x2 v77 LoadLocal { off=-116, kind=I64 } -> x0 terminator Bz { cond=v76, target=b24, fall=b23 } (exit_acc=v76) block 23 start_pc=0 @@ -147,68 +147,59 @@ fn ent_pc=0 n_params=0 variadic=false locals=123 v89 Store { addr=v88, disp=0, value=v86, kind=I64 } -> - v90 Imm(32) -> x0 v91 Imm(137438953472) -> x0 - terminator Jmp(b28) (exit_acc=v86) + terminator Jmp(b27) (exit_acc=v86) block 27 start_pc=0 - v92 Imm(11) -> x0 - terminator Return(v92) (exit_acc=v92) - block 28 start_pc=0 v93 Imm(156) -> x0 v94 Imm(670014898176) -> x0 v95 Imm(668) -> x0 - v96 Imm(2869038153728) -> x1 - v97 Imm(0) -> x1 - v98 Imm(1) -> x1 - v99 Imm(4294967296) -> x1 - v100 Imm(3) -> x1 - v101 Imm(12884901888) -> x2 - v102 Imm(0) -> x2 - v103 Imm(12) -> x2 - v104 Imm(51539607552) -> x6 - v105 Imm(0) -> x6 - v106 LoadLocal { off=-27, kind=I32 } -> x6 - v107 BinopI { op=eq, lhs=v95, rhs_imm=0 } -> x0 - v108 Imm(0) -> x7 - v109 Imm(0) -> x6 - terminator Bz { cond=v107, target=b50, fall=b29 } (exit_acc=v107) - block 29 start_pc=0 - v110 LoadLocal { off=-28, kind=I32 } -> x0 - v111 BinopI { op=eq, lhs=v100, rhs_imm=0 } -> x0 - v112 BinopI { op=ne, lhs=v111, rhs_imm=0 } -> x7 - v113 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v112) - block 30 start_pc=0 - v114 Phi { incoming=[b50:v108, b29:v112], kind=I64 } -> x7 + v96 Imm(2869038153728) -> x0 + v97 Imm(0) -> x0 + v98 Imm(1) -> x0 + v99 Imm(4294967296) -> x0 + v100 Imm(3) -> x0 + v101 Imm(12884901888) -> x0 + v102 Imm(0) -> x0 + v103 Imm(12) -> x0 + v104 Imm(51539607552) -> x0 + v105 Imm(0) -> x0 + v106 LoadLocal { off=-27, kind=I32 } -> x0 + v107 Imm(0) -> x0 + v108 Imm(0) -> x2 + v109 Imm(0) -> x1 + terminator Jmp(b28) (exit_acc=v107) + block 28 start_pc=0 + v114 Phi { incoming=[b27:v108, b52:v112], kind=I64 } -> x2 v115 LoadLocal { off=-119, kind=I64 } -> x0 v116 Imm(0) -> x0 - terminator Bz { cond=v114, target=b51, fall=b31 } (exit_acc=v114) - block 31 start_pc=0 + terminator Bz { cond=v114, target=b48, fall=b29 } (exit_acc=v114) + block 29 start_pc=0 v117 LoadLocal { off=-29, kind=I32 } -> x0 - v118 BinopI { op=eq, lhs=v103, rhs_imm=0 } -> x7 + v118 Imm(0) -> x2 v119 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v118) - block 32 start_pc=0 - v120 Phi { incoming=[b51:v114, b31:v118], kind=I64 } -> x7 + terminator Jmp(b30) (exit_acc=v118) + block 30 start_pc=0 + v120 Phi { incoming=[b48:v114, b29:v118], kind=I64 } -> x2 v121 LoadLocal { off=-118, kind=I64 } -> x0 - terminator Bz { cond=v120, target=b34, fall=b33 } (exit_acc=v120) - block 33 start_pc=0 + terminator Bz { cond=v120, target=b32, fall=b31 } (exit_acc=v120) + block 31 start_pc=0 v122 Imm(12) -> x0 terminator Return(v122) (exit_acc=v122) - block 34 start_pc=0 + block 32 start_pc=0 v123 Imm(0) -> x1 v124 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v123) - block 35 start_pc=0 + terminator Jmp(b33) (exit_acc=v123) + block 33 start_pc=0 v125 Imm(0) -> x1 v126 Imm(0) -> x0 - terminator Jmp(b36) (exit_acc=v125) - block 36 start_pc=0 - v127 Phi { incoming=[b34:v123, b35:v125], kind=I64 } -> x1 + terminator Jmp(b34) (exit_acc=v125) + block 34 start_pc=0 + v127 Phi { incoming=[b32:v123, b33:v125], kind=I64 } -> x1 v128 LoadLocal { off=-120, kind=I64 } -> x0 - terminator Bz { cond=v127, target=b38, fall=b37 } (exit_acc=v127) - block 37 start_pc=0 + terminator Bz { cond=v127, target=b36, fall=b35 } (exit_acc=v127) + block 35 start_pc=0 v129 Imm(13) -> x0 terminator Return(v129) (exit_acc=v129) - block 38 start_pc=0 + block 36 start_pc=0 v130 LocalAddr(-30) -> x0 v131 Imm(0) -> x1 v132 Store { addr=v130, disp=0, value=v131, kind=I32 } -> - @@ -216,62 +207,67 @@ fn ent_pc=0 n_params=0 variadic=false locals=123 v134 BinopI { op=eq, lhs=v133, rhs_imm=0 } -> x0 v135 Imm(1) -> x2 v136 Imm(0) -> x1 - terminator Bnz { cond=v134, target=b52, fall=b39 } (exit_acc=v134) - block 39 start_pc=0 + terminator Bnz { cond=v134, target=b47, fall=b37 } (exit_acc=v134) + block 37 start_pc=0 v137 LocalAddr(-110) -> x0 v138 BinopI { op=eq, lhs=v137, rhs_imm=0 } -> x0 v139 BinopI { op=ne, lhs=v138, rhs_imm=0 } -> x2 v140 Imm(0) -> x0 - terminator Jmp(b40) (exit_acc=v139) - block 40 start_pc=0 - v141 Phi { incoming=[b52:v135, b39:v139], kind=I64 } -> x2 + terminator Jmp(b38) (exit_acc=v139) + block 38 start_pc=0 + v141 Phi { incoming=[b47:v135, b37:v139], kind=I64 } -> x2 v142 LoadLocal { off=-123, kind=I64 } -> x0 v143 Imm(1) -> x1 v144 Imm(0) -> x0 - terminator Bnz { cond=v141, target=b53, fall=b41 } (exit_acc=v141) - block 41 start_pc=0 + terminator Bnz { cond=v141, target=b46, fall=b39 } (exit_acc=v141) + block 39 start_pc=0 v145 LocalAddr(-114) -> x0 v146 BinopI { op=eq, lhs=v145, rhs_imm=0 } -> x0 v147 BinopI { op=ne, lhs=v146, rhs_imm=0 } -> x1 v148 Imm(0) -> x0 - terminator Jmp(b42) (exit_acc=v147) - block 42 start_pc=0 - v149 Phi { incoming=[b53:v143, b41:v147], kind=I64 } -> x1 + terminator Jmp(b40) (exit_acc=v147) + block 40 start_pc=0 + v149 Phi { incoming=[b46:v143, b39:v147], kind=I64 } -> x1 v150 LoadLocal { off=-122, kind=I64 } -> x0 v151 Imm(0) -> x0 - terminator Bnz { cond=v149, target=b54, fall=b43 } (exit_acc=v149) - block 43 start_pc=0 + terminator Bnz { cond=v149, target=b45, fall=b41 } (exit_acc=v149) + block 41 start_pc=0 v152 LocalAddr(-30) -> x0 v153 Load { addr=v152, disp=0, kind=I32 } -> x0 v154 BinopI { op=ne, lhs=v153, rhs_imm=0 } -> x1 v155 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v154) - block 44 start_pc=0 - v156 Phi { incoming=[b54:v149, b43:v154], kind=I64 } -> x1 + terminator Jmp(b42) (exit_acc=v154) + block 42 start_pc=0 + v156 Phi { incoming=[b45:v149, b41:v154], kind=I64 } -> x1 v157 LoadLocal { off=-121, kind=I64 } -> x0 - terminator Bz { cond=v156, target=b46, fall=b45 } (exit_acc=v156) - block 45 start_pc=0 + terminator Bz { cond=v156, target=b44, fall=b43 } (exit_acc=v156) + block 43 start_pc=0 v158 Imm(14) -> x0 terminator Return(v158) (exit_acc=v158) - block 46 start_pc=0 + block 44 start_pc=0 v159 Imm(0) -> x0 terminator Return(v159) (exit_acc=v159) + block 45 start_pc=0 + terminator Jmp(b42) + block 46 start_pc=0 + terminator Jmp(b40) block 47 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b38) block 48 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b30) block 49 start_pc=0 terminator Jmp(b22) block 50 start_pc=0 - terminator Jmp(b30) + terminator Jmp(b4) block 51 start_pc=0 - terminator Jmp(b32) + v92 Imm(11) -> x0 + terminator Return(v92) (exit_acc=v92) block 52 start_pc=0 - terminator Jmp(b40) - block 53 start_pc=0 - terminator Jmp(b42) - block 54 start_pc=0 - terminator Jmp(b44) + v110 LoadLocal { off=-28, kind=I32 } -> x0 + v111 Imm(0) -> x0 + v112 Imm(0) -> x2 + v113 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v112) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/posix_unix_headers.ssa b/tests/snapshots/ssa/posix_unix_headers.ssa index 85306b915..30a4850ea 100644 --- a/tests/snapshots/ssa/posix_unix_headers.ssa +++ b/tests/snapshots/ssa/posix_unix_headers.ssa @@ -5,32 +5,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=72 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 - terminator Jmp(b3) - block 3 start_pc=0 v3 LocalAddr(-16) -> x0 v4 Imm(0) -> x1 v5 Imm(0) -> x2 v6 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v5) - block 4 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v7) - block 5 start_pc=0 - terminator Jmp(b9) - block 6 start_pc=0 - v8 Phi { incoming=[b3:v5, b7:v19], kind=I64 } -> x2 - v9 Extend { value=v8, kind=I32 } -> x1 - v10 BinopI { op=lt, lhs=v9, rhs_imm=128 } -> x1 - terminator Bz { cond=v10, target=b8, fall=b7 } (exit_acc=v10) - block 7 start_pc=0 - v11 LoadLocal { off=-17, kind=I64 } -> x1 - v12 Extend { value=v8, kind=I32 } -> x1 - v13 Binop { op=add, lhs=v3, rhs=v12 } -> x1 + terminator Jmp(b3) (exit_acc=v5) + block 2 start_pc=0 + v11 LoadLocal { off=-17, kind=I64 } -> x6 + v12 Extend { value=v8, kind=I32 } -> x6 + v13 Binop { op=add, lhs=v3, rhs=v9 } -> x1 v14 Imm(0) -> x6 v15 Store { addr=v13, disp=0, value=v14, kind=I8 } -> - v16 Extend { value=v8, kind=I32 } -> x1 @@ -38,117 +23,119 @@ fn ent_pc=0 n_params=0 variadic=false locals=72 v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x2 v19 Extend { value=v17, kind=I32 } -> x2 v20 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v19) - block 8 start_pc=0 - terminator Jmp(b4) - block 9 start_pc=0 + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v8 Phi { incoming=[b1:v5, b2:v19], kind=I64 } -> x2 + v9 Extend { value=v8, kind=I32 } -> x1 + v10 BinopI { op=lt, lhs=v9, rhs_imm=128 } -> x6 + terminator Bnz { cond=v10, target=b2, fall=b4 } (exit_acc=v10) + block 4 start_pc=0 + v7 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v7) + block 5 start_pc=0 v21 LocalAddr(-16) -> x0 v22 Imm(0) -> x1 v23 LoadLocal { off=-19, kind=I64 } -> x1 v24 Imm(3) -> x1 - v25 Imm(8) -> x2 - v26 Imm(0) -> x2 - v27 Binop { op=add, lhs=v24, rhs=v26 } -> x1 - v28 BinopI { op=shr, lhs=v27, rhs_imm=3 } -> x1 - v29 Binop { op=add, lhs=v21, rhs=v28 } -> x0 + v25 Imm(8) -> x1 + v26 Imm(0) -> x1 + v27 Imm(3) -> x1 + v28 Imm(0) -> x1 + v29 BinopI { op=add, lhs=v21, rhs_imm=0 } -> x0 v30 Load { addr=v29, disp=0, kind=U8 } -> x1 v31 Imm(1) -> x2 v32 Imm(34359738368) -> x2 v33 BinopI { op=or, lhs=v30, rhs_imm=8 } -> x1 v34 Store { addr=v29, disp=0, value=v33, kind=I8 } -> - v35 BinopI { op=and, lhs=v33, rhs_imm=255 } -> x0 - terminator Jmp(b10) (exit_acc=v35) - block 10 start_pc=0 + terminator Jmp(b6) (exit_acc=v35) + block 6 start_pc=0 v36 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v36) - block 11 start_pc=0 - terminator Jmp(b12) - block 12 start_pc=0 + terminator Jmp(b7) (exit_acc=v36) + block 7 start_pc=0 v37 LocalAddr(-16) -> x0 v38 Imm(0) -> x1 v39 LoadLocal { off=-20, kind=I64 } -> x1 v40 Imm(40) -> x1 - v41 Imm(8) -> x2 - v42 Imm(0) -> x2 - v43 Binop { op=add, lhs=v40, rhs=v42 } -> x1 - v44 BinopI { op=shr, lhs=v43, rhs_imm=3 } -> x1 - v45 Binop { op=add, lhs=v37, rhs=v44 } -> x0 - v46 Load { addr=v45, disp=0, kind=U8 } -> x1 + v41 Imm(8) -> x1 + v42 Imm(0) -> x1 + v43 Imm(40) -> x1 + v44 Imm(5) -> x1 + v45 BinopI { op=add, lhs=v37, rhs_imm=5 } -> x1 + v46 Load { addr=v37, disp=5, kind=U8 } -> x1 v47 Imm(1) -> x2 v48 Imm(4294967296) -> x2 v49 BinopI { op=or, lhs=v46, rhs_imm=1 } -> x1 - v50 Store { addr=v45, disp=0, value=v49, kind=I8 } -> - + v50 Store { addr=v37, disp=5, value=v49, kind=I8 } -> - v51 BinopI { op=and, lhs=v49, rhs_imm=255 } -> x0 - terminator Jmp(b13) (exit_acc=v51) - block 13 start_pc=0 + terminator Jmp(b8) (exit_acc=v51) + block 8 start_pc=0 v52 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v52) - block 14 start_pc=0 + terminator Jmp(b9) (exit_acc=v52) + block 9 start_pc=0 v53 LocalAddr(-16) -> x0 v54 Imm(3) -> x1 - v55 Imm(8) -> x2 - v56 Imm(0) -> x2 - v57 Binop { op=add, lhs=v54, rhs=v56 } -> x1 - v58 BinopI { op=shr, lhs=v57, rhs_imm=3 } -> x1 - v59 Binop { op=add, lhs=v53, rhs=v58 } -> x0 + v55 Imm(8) -> x1 + v56 Imm(0) -> x1 + v57 Imm(3) -> x1 + v58 Imm(0) -> x1 + v59 BinopI { op=add, lhs=v53, rhs_imm=0 } -> x0 v60 Load { addr=v59, disp=0, kind=U8 } -> x0 v61 Imm(1) -> x1 v62 Imm(34359738368) -> x1 v63 BinopI { op=and, lhs=v60, rhs_imm=8 } -> x0 v64 BinopI { op=eq, lhs=v63, rhs_imm=0 } -> x1 v65 Imm(0) -> x0 - terminator Bnz { cond=v64, target=b36, fall=b15 } (exit_acc=v64) - block 15 start_pc=0 + terminator Bnz { cond=v64, target=b28, fall=b10 } (exit_acc=v64) + block 10 start_pc=0 v66 LocalAddr(-16) -> x0 v67 Imm(40) -> x1 - v68 Imm(8) -> x2 - v69 Imm(0) -> x2 - v70 Binop { op=add, lhs=v67, rhs=v69 } -> x1 - v71 BinopI { op=shr, lhs=v70, rhs_imm=3 } -> x1 - v72 Binop { op=add, lhs=v66, rhs=v71 } -> x0 - v73 Load { addr=v72, disp=0, kind=U8 } -> x0 + v68 Imm(8) -> x1 + v69 Imm(0) -> x1 + v70 Imm(40) -> x1 + v71 Imm(5) -> x1 + v72 BinopI { op=add, lhs=v66, rhs_imm=5 } -> x1 + v73 Load { addr=v66, disp=5, kind=U8 } -> x0 v74 Imm(1) -> x1 v75 Imm(4294967296) -> x1 v76 BinopI { op=and, lhs=v73, rhs_imm=1 } -> x0 v77 BinopI { op=eq, lhs=v76, rhs_imm=0 } -> x1 v78 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v77) - block 16 start_pc=0 - v79 Phi { incoming=[b36:v64, b15:v77], kind=I64 } -> x1 + terminator Jmp(b11) (exit_acc=v77) + block 11 start_pc=0 + v79 Phi { incoming=[b28:v64, b10:v77], kind=I64 } -> x1 v80 LoadLocal { off=-71, kind=I64 } -> x0 - terminator Bz { cond=v79, target=b18, fall=b17 } (exit_acc=v79) - block 17 start_pc=0 + terminator Bz { cond=v79, target=b13, fall=b12 } (exit_acc=v79) + block 12 start_pc=0 v81 Imm(2) -> x0 terminator Return(v81) (exit_acc=v81) - block 18 start_pc=0 + block 13 start_pc=0 v82 LocalAddr(-16) -> x0 v83 Imm(4) -> x1 - v84 Imm(8) -> x2 - v85 Imm(0) -> x2 - v86 Binop { op=add, lhs=v83, rhs=v85 } -> x1 - v87 BinopI { op=shr, lhs=v86, rhs_imm=3 } -> x1 - v88 Binop { op=add, lhs=v82, rhs=v87 } -> x0 + v84 Imm(8) -> x1 + v85 Imm(0) -> x1 + v86 Imm(4) -> x1 + v87 Imm(0) -> x1 + v88 BinopI { op=add, lhs=v82, rhs_imm=0 } -> x0 v89 Load { addr=v88, disp=0, kind=U8 } -> x0 v90 Imm(1) -> x1 v91 Imm(16) -> x1 v92 Imm(68719476736) -> x1 v93 BinopI { op=and, lhs=v89, rhs_imm=16 } -> x0 - terminator Bz { cond=v93, target=b20, fall=b19 } (exit_acc=v93) - block 19 start_pc=0 + terminator Bz { cond=v93, target=b15, fall=b14 } (exit_acc=v93) + block 14 start_pc=0 v94 Imm(3) -> x0 terminator Return(v94) (exit_acc=v94) - block 20 start_pc=0 - terminator Jmp(b21) - block 21 start_pc=0 + block 15 start_pc=0 v95 LocalAddr(-16) -> x0 v96 Imm(0) -> x1 v97 LoadLocal { off=-21, kind=I64 } -> x1 v98 Imm(3) -> x1 - v99 Imm(8) -> x2 - v100 Imm(0) -> x2 - v101 Binop { op=add, lhs=v98, rhs=v100 } -> x1 - v102 BinopI { op=shr, lhs=v101, rhs_imm=3 } -> x1 - v103 Binop { op=add, lhs=v95, rhs=v102 } -> x0 + v99 Imm(8) -> x1 + v100 Imm(0) -> x1 + v101 Imm(3) -> x1 + v102 Imm(0) -> x1 + v103 BinopI { op=add, lhs=v95, rhs_imm=0 } -> x0 v104 Load { addr=v103, disp=0, kind=U8 } -> x1 v105 Imm(1) -> x2 v106 Imm(34359738368) -> x2 @@ -156,47 +143,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=72 v108 BinopI { op=and, lhs=v104, rhs_imm=-9 } -> x2 v109 Store { addr=v103, disp=0, value=v108, kind=I8 } -> - v110 BinopI { op=and, lhs=v104, rhs_imm=247 } -> x0 - terminator Jmp(b22) (exit_acc=v110) - block 22 start_pc=0 + terminator Jmp(b16) (exit_acc=v110) + block 16 start_pc=0 v111 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v111) - block 23 start_pc=0 + terminator Jmp(b17) (exit_acc=v111) + block 17 start_pc=0 v112 LocalAddr(-16) -> x0 v113 Imm(3) -> x1 - v114 Imm(8) -> x2 - v115 Imm(0) -> x2 - v116 Binop { op=add, lhs=v113, rhs=v115 } -> x1 - v117 BinopI { op=shr, lhs=v116, rhs_imm=3 } -> x1 - v118 Binop { op=add, lhs=v112, rhs=v117 } -> x0 + v114 Imm(8) -> x1 + v115 Imm(0) -> x1 + v116 Imm(3) -> x1 + v117 Imm(0) -> x1 + v118 BinopI { op=add, lhs=v112, rhs_imm=0 } -> x0 v119 Load { addr=v118, disp=0, kind=U8 } -> x0 v120 Imm(1) -> x1 v121 Imm(34359738368) -> x1 v122 BinopI { op=and, lhs=v119, rhs_imm=8 } -> x0 - terminator Bz { cond=v122, target=b25, fall=b24 } (exit_acc=v122) - block 24 start_pc=0 + terminator Bz { cond=v122, target=b19, fall=b18 } (exit_acc=v122) + block 18 start_pc=0 v123 Imm(4) -> x0 terminator Return(v123) (exit_acc=v123) - block 25 start_pc=0 + block 19 start_pc=0 v124 Imm(0) -> x0 - terminator Jmp(b27) (exit_acc=v124) - block 26 start_pc=0 - v125 Imm(5) -> x0 - terminator Return(v125) (exit_acc=v125) - block 27 start_pc=0 + terminator Jmp(b20) (exit_acc=v124) + block 20 start_pc=0 v126 Imm(0) -> x0 v127 Imm(16) -> x1 - terminator Jmp(b29) (exit_acc=v126) - block 28 start_pc=0 - v128 Imm(6) -> x0 - terminator Return(v128) (exit_acc=v128) - block 29 start_pc=0 + terminator Jmp(b21) (exit_acc=v126) + block 21 start_pc=0 v129 Imm(0) -> x0 v130 Imm(24) -> x1 - terminator Jmp(b31) (exit_acc=v129) - block 30 start_pc=0 - v131 Imm(7) -> x0 - terminator Return(v131) (exit_acc=v131) - block 31 start_pc=0 + terminator Jmp(b22) (exit_acc=v129) + block 22 start_pc=0 v132 LocalAddr(-70) -> x0 v133 Imm(0) -> x1 v134 Imm(120) -> x1 @@ -211,29 +189,51 @@ fn ent_pc=0 n_params=0 variadic=false locals=72 v143 Load { addr=v142, disp=0, kind=I8 } -> x0 v144 BinopI { op=ne, lhs=v143, rhs_imm=120 } -> x1 v145 Imm(0) -> x0 - terminator Bnz { cond=v144, target=b37, fall=b32 } (exit_acc=v144) - block 32 start_pc=0 + terminator Bnz { cond=v144, target=b27, fall=b23 } (exit_acc=v144) + block 23 start_pc=0 v146 LocalAddr(-70) -> x0 v147 BinopI { op=add, lhs=v146, rhs_imm=65 } -> x1 v148 Imm(0) -> x1 v149 Load { addr=v146, disp=65, kind=I8 } -> x0 v150 BinopI { op=ne, lhs=v149, rhs_imm=121 } -> x1 v151 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v150) - block 33 start_pc=0 - v152 Phi { incoming=[b37:v144, b32:v150], kind=I64 } -> x1 + terminator Jmp(b24) (exit_acc=v150) + block 24 start_pc=0 + v152 Phi { incoming=[b27:v144, b23:v150], kind=I64 } -> x1 v153 LoadLocal { off=-72, kind=I64 } -> x0 - terminator Bz { cond=v152, target=b35, fall=b34 } (exit_acc=v152) - block 34 start_pc=0 + terminator Bz { cond=v152, target=b26, fall=b25 } (exit_acc=v152) + block 25 start_pc=0 v154 Imm(8) -> x0 terminator Return(v154) (exit_acc=v154) - block 35 start_pc=0 + block 26 start_pc=0 v155 Imm(0) -> x0 terminator Return(v155) (exit_acc=v155) + block 27 start_pc=0 + terminator Jmp(b24) + block 28 start_pc=0 + terminator Jmp(b11) + block 29 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 30 start_pc=0 + terminator Jmp(b1) + block 31 start_pc=0 + terminator Jmp(b5) + block 32 start_pc=0 + terminator Jmp(b4) + block 33 start_pc=0 + terminator Jmp(b7) + block 34 start_pc=0 + terminator Jmp(b15) + block 35 start_pc=0 + v125 Imm(5) -> x0 + terminator Return(v125) (exit_acc=v125) block 36 start_pc=0 - terminator Jmp(b16) + v128 Imm(6) -> x0 + terminator Return(v128) (exit_acc=v128) block 37 start_pc=0 - terminator Jmp(b33) + v131 Imm(7) -> x0 + terminator Return(v131) (exit_acc=v131) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/posix_utime_errno_headers.ssa b/tests/snapshots/ssa/posix_utime_errno_headers.ssa index b44508b4b..e28d66755 100644 --- a/tests/snapshots/ssa/posix_utime_errno_headers.ssa +++ b/tests/snapshots/ssa/posix_utime_errno_headers.ssa @@ -24,19 +24,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 terminator Return(v15) (exit_acc=v15) block 2 start_pc=0 v16 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v16) + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) - block 4 start_pc=0 v18 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v18) + terminator Jmp(b4) (exit_acc=v18) + block 4 start_pc=0 + v20 Imm(0) -> x0 + terminator Return(v20) (exit_acc=v20) block 5 start_pc=0 + v17 Imm(2) -> x0 + terminator Return(v17) (exit_acc=v17) + block 6 start_pc=0 v19 Imm(3) -> x0 terminator Return(v19) (exit_acc=v19) - block 6 start_pc=0 - v20 Imm(0) -> x0 - terminator Return(v20) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/pragma_operator.ssa b/tests/snapshots/ssa/pragma_operator.ssa index c22b9515c..cd68c8d72 100644 --- a/tests/snapshots/ssa/pragma_operator.ssa +++ b/tests/snapshots/ssa/pragma_operator.ssa @@ -5,17 +5,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 ImmData(8) -> x0 v6 Imm(0) -> x1 v7 LoadLocal { off=-1, kind=I64 } -> x1 @@ -23,27 +17,33 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v9 Load { addr=v5, disp=0, kind=I8 } -> x1 v10 BinopI { op=ne, lhs=v9, rhs_imm=95 } -> x2 v11 Imm(0) -> x1 - terminator Bnz { cond=v10, target=b9, fall=b5 } (exit_acc=v10) - block 5 start_pc=0 + terminator Bnz { cond=v10, target=b7, fall=b3 } (exit_acc=v10) + block 3 start_pc=0 v12 LoadLocal { off=-1, kind=I64 } -> x1 v13 Imm(1) -> x1 v14 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x1 v15 Load { addr=v5, disp=1, kind=I8 } -> x0 v16 BinopI { op=ne, lhs=v15, rhs_imm=80 } -> x2 v17 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v16) - block 6 start_pc=0 - v18 Phi { incoming=[b9:v10, b5:v16], kind=I64 } -> x2 + terminator Jmp(b4) (exit_acc=v16) + block 4 start_pc=0 + v18 Phi { incoming=[b7:v10, b3:v16], kind=I64 } -> x2 v19 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) - block 7 start_pc=0 + terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + block 5 start_pc=0 v20 Imm(3) -> x0 terminator Return(v20) (exit_acc=v20) - block 8 start_pc=0 + block 6 start_pc=0 v21 Imm(0) -> x0 terminator Return(v21) (exit_acc=v21) + block 7 start_pc=0 + terminator Jmp(b4) + block 8 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 9 start_pc=0 - terminator Jmp(b6) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/predefined_constants.ssa b/tests/snapshots/ssa/predefined_constants.ssa index 43dd4c1ef..7bc6600b8 100644 --- a/tests/snapshots/ssa/predefined_constants.ssa +++ b/tests/snapshots/ssa/predefined_constants.ssa @@ -5,85 +5,85 @@ fn ent_pc=5 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v17 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v17) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v19 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v19) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v21 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v21) block 11 start_pc=0 - v12 Imm(6) -> x0 - terminator Return(v12) (exit_acc=v12) + v23 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v23) block 12 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v13) + v25 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v25) block 13 start_pc=0 - v14 Imm(7) -> x0 - terminator Return(v14) (exit_acc=v14) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 14 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v15) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 15 start_pc=0 - v16 Imm(8) -> x0 - terminator Return(v16) (exit_acc=v16) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 16 start_pc=0 - v17 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v17) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 17 start_pc=0 - v18 Imm(9) -> x0 - terminator Return(v18) (exit_acc=v18) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 18 start_pc=0 - v19 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v19) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 19 start_pc=0 - v20 Imm(10) -> x0 - terminator Return(v20) (exit_acc=v20) + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) block 20 start_pc=0 - v21 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v21) + v14 Imm(7) -> x0 + terminator Return(v14) (exit_acc=v14) block 21 start_pc=0 - v22 Imm(11) -> x0 - terminator Return(v22) (exit_acc=v22) + v16 Imm(8) -> x0 + terminator Return(v16) (exit_acc=v16) block 22 start_pc=0 - v23 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v23) + v18 Imm(9) -> x0 + terminator Return(v18) (exit_acc=v18) block 23 start_pc=0 - v24 Imm(12) -> x0 - terminator Return(v24) (exit_acc=v24) + v20 Imm(10) -> x0 + terminator Return(v20) (exit_acc=v20) block 24 start_pc=0 - v25 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v25) + v22 Imm(11) -> x0 + terminator Return(v22) (exit_acc=v22) block 25 start_pc=0 + v24 Imm(12) -> x0 + terminator Return(v24) (exit_acc=v24) + block 26 start_pc=0 v26 Imm(13) -> x0 terminator Return(v26) (exit_acc=v26) - block 26 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/predefined_macros.ssa b/tests/snapshots/ssa/predefined_macros.ssa index c6ab0d1a0..189f15c7e 100644 --- a/tests/snapshots/ssa/predefined_macros.ssa +++ b/tests/snapshots/ssa/predefined_macros.ssa @@ -5,26 +5,20 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(15) -> x0 - v2 Imm(0) -> x1 - v3 Imm(16) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-2, kind=I32 } -> x2 - v6 LoadLocal { off=-1, kind=I32 } -> x2 - v7 Binop { op=sub, lhs=v3, rhs=v1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=1 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(0) -> x0 + v3 Imm(16) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-2, kind=I32 } -> x0 + v6 LoadLocal { off=-1, kind=I32 } -> x0 + v7 Imm(1) -> x0 + v8 Imm(4294967296) -> x0 + v9 Imm(1) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v12) - block 3 start_pc=0 - v13 Imm(2) -> x0 - terminator Return(v13) (exit_acc=v13) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v12) + block 2 start_pc=0 v14 ImmData(8) -> x0 v15 Imm(0) -> x1 v16 LoadLocal { off=-3, kind=I64 } -> x1 @@ -32,31 +26,31 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v18 BinopI { op=add, lhs=v14, rhs_imm=3 } -> x1 v19 Load { addr=v14, disp=3, kind=I8 } -> x1 v20 BinopI { op=ne, lhs=v19, rhs_imm=32 } -> x1 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) - block 5 start_pc=0 + terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + block 3 start_pc=0 v21 Imm(3) -> x0 terminator Return(v21) (exit_acc=v21) - block 6 start_pc=0 + block 4 start_pc=0 v22 LoadLocal { off=-3, kind=I64 } -> x1 v23 Imm(6) -> x1 v24 BinopI { op=add, lhs=v14, rhs_imm=6 } -> x1 v25 Load { addr=v14, disp=6, kind=I8 } -> x1 v26 BinopI { op=ne, lhs=v25, rhs_imm=32 } -> x1 - terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) - block 7 start_pc=0 + terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) + block 5 start_pc=0 v27 Imm(4) -> x0 terminator Return(v27) (exit_acc=v27) - block 8 start_pc=0 + block 6 start_pc=0 v28 LoadLocal { off=-3, kind=I64 } -> x1 v29 Imm(11) -> x1 v30 BinopI { op=add, lhs=v14, rhs_imm=11 } -> x1 v31 Load { addr=v14, disp=11, kind=I8 } -> x0 v32 BinopI { op=ne, lhs=v31, rhs_imm=0 } -> x0 - terminator Bz { cond=v32, target=b10, fall=b9 } (exit_acc=v32) - block 9 start_pc=0 + terminator Bz { cond=v32, target=b8, fall=b7 } (exit_acc=v32) + block 7 start_pc=0 v33 Imm(5) -> x0 terminator Return(v33) (exit_acc=v33) - block 10 start_pc=0 + block 8 start_pc=0 v34 ImmData(20) -> x0 v35 Imm(0) -> x1 v36 LoadLocal { off=-4, kind=I64 } -> x1 @@ -64,44 +58,50 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v38 BinopI { op=add, lhs=v34, rhs_imm=2 } -> x1 v39 Load { addr=v34, disp=2, kind=I8 } -> x1 v40 BinopI { op=ne, lhs=v39, rhs_imm=58 } -> x1 - terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) - block 11 start_pc=0 + terminator Bz { cond=v40, target=b10, fall=b9 } (exit_acc=v40) + block 9 start_pc=0 v41 Imm(6) -> x0 terminator Return(v41) (exit_acc=v41) - block 12 start_pc=0 + block 10 start_pc=0 v42 LoadLocal { off=-4, kind=I64 } -> x1 v43 Imm(5) -> x1 v44 BinopI { op=add, lhs=v34, rhs_imm=5 } -> x1 v45 Load { addr=v34, disp=5, kind=I8 } -> x1 v46 BinopI { op=ne, lhs=v45, rhs_imm=58 } -> x1 - terminator Bz { cond=v46, target=b14, fall=b13 } (exit_acc=v46) - block 13 start_pc=0 + terminator Bz { cond=v46, target=b12, fall=b11 } (exit_acc=v46) + block 11 start_pc=0 v47 Imm(7) -> x0 terminator Return(v47) (exit_acc=v47) - block 14 start_pc=0 + block 12 start_pc=0 v48 LoadLocal { off=-4, kind=I64 } -> x1 v49 Imm(8) -> x1 v50 BinopI { op=add, lhs=v34, rhs_imm=8 } -> x1 v51 Load { addr=v34, disp=8, kind=I8 } -> x0 v52 BinopI { op=ne, lhs=v51, rhs_imm=0 } -> x0 - terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) - block 15 start_pc=0 + terminator Bz { cond=v52, target=b14, fall=b13 } (exit_acc=v52) + block 13 start_pc=0 v53 Imm(8) -> x0 terminator Return(v53) (exit_acc=v53) - block 16 start_pc=0 + block 14 start_pc=0 v54 ImmData(29) -> x0 v55 Imm(0) -> x1 v56 LoadLocal { off=-5, kind=I64 } -> x1 v57 Imm(0) -> x1 v58 Load { addr=v54, disp=0, kind=I8 } -> x0 v59 BinopI { op=eq, lhs=v58, rhs_imm=0 } -> x0 - terminator Bz { cond=v59, target=b18, fall=b17 } (exit_acc=v59) - block 17 start_pc=0 + terminator Bz { cond=v59, target=b16, fall=b15 } (exit_acc=v59) + block 15 start_pc=0 v60 Imm(9) -> x0 terminator Return(v60) (exit_acc=v60) - block 18 start_pc=0 + block 16 start_pc=0 v61 Imm(0) -> x0 terminator Return(v61) (exit_acc=v61) + block 17 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 18 start_pc=0 + v13 Imm(2) -> x0 + terminator Return(v13) (exit_acc=v13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/preinc_narrow_lvalue_wraps.ssa b/tests/snapshots/ssa/preinc_narrow_lvalue_wraps.ssa index 7e9234a43..f08c5ddb6 100644 --- a/tests/snapshots/ssa/preinc_narrow_lvalue_wraps.ssa +++ b/tests/snapshots/ssa/preinc_narrow_lvalue_wraps.ssa @@ -5,49 +5,47 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(255) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=U8 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=255 } -> x1 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 - terminator Bz { cond=v9, target=b8, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U8 } -> x0 + v6 Imm(256) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x2 - v11 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b8:v3, b1:v10], kind=I64 } -> x2 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x1 - terminator Bz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + v12 Phi { incoming=[b0:v3, b1:v10], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Bz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v16 BinopI { op=and, lhs=v6, rhs_imm=255 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 + v16 Imm(0) -> x0 + v17 Imm(1) -> x1 v18 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b9:v14, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b8:v14, b3:v17], kind=I64 } -> x1 v20 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Imm(1) -> x1 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v23) - block 7 start_pc=0 - v25 Phi { incoming=[b5:v21, b6:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b5:v21, b7:v23], kind=I64 } -> x1 v26 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) + block 7 start_pc=0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=preinc_u16_wrap @@ -56,49 +54,47 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(65535) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=U16 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=65535 } -> x1 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 - terminator Bz { cond=v9, target=b8, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U16 } -> x0 + v6 Imm(65536) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x2 - v11 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b8:v3, b1:v10], kind=I64 } -> x2 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x1 - terminator Bz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + v12 Phi { incoming=[b0:v3, b1:v10], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Bz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v16 BinopI { op=and, lhs=v6, rhs_imm=65535 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 + v16 Imm(0) -> x0 + v17 Imm(1) -> x1 v18 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b9:v14, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b8:v14, b3:v17], kind=I64 } -> x1 v20 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Imm(1) -> x1 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v23) - block 7 start_pc=0 - v25 Phi { incoming=[b5:v21, b6:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b5:v21, b7:v23], kind=I64 } -> x1 v26 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) + block 7 start_pc=0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=preinc_u32_wrap @@ -107,49 +103,47 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294967295) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=U32 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x1 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 - terminator Bz { cond=v9, target=b8, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U32 } -> x0 + v6 Imm(4294967296) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x2 - v11 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b8:v3, b1:v10], kind=I64 } -> x2 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x1 - terminator Bz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + v12 Phi { incoming=[b0:v3, b1:v10], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Bz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v16 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 + v16 Imm(0) -> x0 + v17 Imm(1) -> x1 v18 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b9:v14, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b8:v14, b3:v17], kind=I64 } -> x1 v20 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Imm(1) -> x1 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v23) - block 7 start_pc=0 - v25 Phi { incoming=[b5:v21, b6:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b5:v21, b7:v23], kind=I64 } -> x1 v26 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) + block 7 start_pc=0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=4 --- ; name=compound_u8_wrap @@ -158,49 +152,47 @@ fn ent_pc=4 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(240) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=U8 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=255 } -> x1 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 - terminator Bz { cond=v9, target=b8, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U8 } -> x0 + v6 Imm(256) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x2 - v11 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b8:v3, b1:v10], kind=I64 } -> x2 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x1 - terminator Bz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + v12 Phi { incoming=[b0:v3, b1:v10], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Bz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v16 BinopI { op=and, lhs=v6, rhs_imm=255 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 + v16 Imm(0) -> x0 + v17 Imm(1) -> x1 v18 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b9:v14, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b8:v14, b3:v17], kind=I64 } -> x1 v20 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Imm(1) -> x1 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v23) - block 7 start_pc=0 - v25 Phi { incoming=[b5:v21, b6:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b5:v21, b7:v23], kind=I64 } -> x1 v26 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) + block 7 start_pc=0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=compound_u16_wrap @@ -209,49 +201,47 @@ fn ent_pc=5 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(65520) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=U16 } -> x1 - v6 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x0 - v7 Imm(0) -> x1 - v8 BinopI { op=and, lhs=v6, rhs_imm=65535 } -> x1 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x1 - terminator Bz { cond=v9, target=b8, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U16 } -> x0 + v6 Imm(65536) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x2 - v11 Imm(0) -> x1 + v10 Imm(1) -> x1 + v11 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b8:v3, b1:v10], kind=I64 } -> x2 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x2 - v15 Imm(0) -> x1 - terminator Bz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) + v12 Phi { incoming=[b0:v3, b1:v10], kind=I64 } -> x1 + v13 Extend { value=v12, kind=I32 } -> x0 + v14 BinopI { op=eq, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Bz { cond=v14, target=b8, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v16 BinopI { op=and, lhs=v6, rhs_imm=65535 } -> x0 - v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x2 + v16 Imm(0) -> x0 + v17 Imm(1) -> x1 v18 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v19 Phi { incoming=[b9:v14, b3:v17], kind=I64 } -> x2 + v19 Phi { incoming=[b8:v14, b3:v17], kind=I64 } -> x1 v20 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v21) + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v23 Imm(1) -> x1 - v24 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v23) - block 7 start_pc=0 - v25 Phi { incoming=[b5:v21, b6:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b5:v21, b7:v23], kind=I64 } -> x1 v26 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) + block 7 start_pc=0 + v23 Imm(1) -> x1 + v24 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=6 --- ; name=preinc_u8_through_pointer @@ -271,53 +261,53 @@ fn ent_pc=6 n_params=0 variadic=false locals=5 v10 Store { addr=v3, disp=0, value=v9, kind=I8 } -> - v11 Load { addr=v3, disp=0, kind=U8 } -> x0 v12 BinopI { op=eq, lhs=v11, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b8, fall=b1 } (exit_acc=v12) + terminator Bz { cond=v12, target=b9, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 Imm(1) -> x2 v14 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Phi { incoming=[b8:v5, b1:v13], kind=I64 } -> x2 + v15 Phi { incoming=[b9:v5, b1:v13], kind=I64 } -> x2 v16 Extend { value=v15, kind=I32 } -> x0 v17 BinopI { op=eq, lhs=v16, rhs_imm=1 } -> x1 v18 Imm(0) -> x0 - terminator Bz { cond=v17, target=b9, fall=b3 } (exit_acc=v17) + terminator Bz { cond=v17, target=b8, fall=b3 } (exit_acc=v17) block 3 start_pc=0 v19 LoadLocal { off=-1, kind=U8 } -> x0 v20 BinopI { op=eq, lhs=v19, rhs_imm=0 } -> x1 v21 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v20) block 4 start_pc=0 - v22 Phi { incoming=[b9:v17, b3:v20], kind=I64 } -> x1 + v22 Phi { incoming=[b8:v17, b3:v20], kind=I64 } -> x1 v23 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + terminator Bz { cond=v22, target=b7, fall=b5 } (exit_acc=v22) block 5 start_pc=0 v24 Imm(0) -> x1 v25 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v24) + terminator Jmp(b6) (exit_acc=v24) block 6 start_pc=0 - v26 Imm(1) -> x1 - v27 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v26) - block 7 start_pc=0 - v28 Phi { incoming=[b5:v24, b6:v26], kind=I64 } -> x1 + v28 Phi { incoming=[b5:v24, b7:v26], kind=I64 } -> x1 v29 LoadLocal { off=-5, kind=I64 } -> x0 terminator Return(v28) (exit_acc=v28) + block 7 start_pc=0 + v26 Imm(1) -> x1 + v27 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v26) block 8 start_pc=0 - terminator Jmp(b2) - block 9 start_pc=0 terminator Jmp(b4) + block 9 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=7 --- ; name=main fn ent_pc=7 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x3 + v1 Imm(0) -> x0 v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=I32 } -> x0 v4 Call { target_pc=1, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 - v5 Binop { op=or, lhs=v1, rhs=v4 } -> x3 + v5 BinopI { op=or, lhs=v4, rhs_imm=0 } -> x3 v6 Imm(0) -> x0 v7 Extend { value=v5, kind=I32 } -> x0 v8 Call { target_pc=2, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 diff --git a/tests/snapshots/ssa/pthread_cond_timedwait.ssa b/tests/snapshots/ssa/pthread_cond_timedwait.ssa index daa6d94e9..790425e3e 100644 --- a/tests/snapshots/ssa/pthread_cond_timedwait.ssa +++ b/tests/snapshots/ssa/pthread_cond_timedwait.ssa @@ -52,19 +52,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=25 v34 CallExt { binding_idx=33, args=[v33], fp_arg_mask=0x0 } -> x0 v35 Extend { value=v27, kind=I32 } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b8, fall=b7 } (exit_acc=v36) + terminator Bz { cond=v36, target=b9, fall=b7 } (exit_acc=v36) block 7 start_pc=0 v37 Imm(0) -> x1 v38 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v37) + terminator Jmp(b8) (exit_acc=v37) block 8 start_pc=0 - v39 Imm(4) -> x1 - v40 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v39) - block 9 start_pc=0 - v41 Phi { incoming=[b7:v37, b8:v39], kind=I64 } -> x1 + v41 Phi { incoming=[b7:v37, b9:v39], kind=I64 } -> x1 v42 LoadLocal { off=-25, kind=I64 } -> x0 terminator Return(v41) (exit_acc=v41) + block 9 start_pc=0 + v39 Imm(4) -> x1 + v40 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/pthread_key_once_width.ssa b/tests/snapshots/ssa/pthread_key_once_width.ssa index bbe72cdc1..9dbab975a 100644 --- a/tests/snapshots/ssa/pthread_key_once_width.ssa +++ b/tests/snapshots/ssa/pthread_key_once_width.ssa @@ -20,58 +20,58 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 terminator Return(v7) (exit_acc=v7) block 4 start_pc=0 v8 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v8) + terminator Jmp(b5) (exit_acc=v8) block 5 start_pc=0 - v9 Imm(2) -> x0 - terminator Return(v9) (exit_acc=v9) - block 6 start_pc=0 v10 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v10) - block 7 start_pc=0 - v11 Imm(3) -> x0 - terminator Return(v11) (exit_acc=v11) - block 8 start_pc=0 + terminator Jmp(b6) (exit_acc=v10) + block 6 start_pc=0 v12 Imm(0) -> x0 v13 Imm(1) -> x2 v14 Imm(0) -> x1 - terminator Jmp(b9) (exit_acc=v12) - block 9 start_pc=0 + terminator Jmp(b7) (exit_acc=v12) + block 7 start_pc=0 v15 Imm(0) -> x2 v16 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v15) - block 10 start_pc=0 - v17 Phi { incoming=[b8:v13, b9:v15], kind=I64 } -> x2 + terminator Jmp(b8) (exit_acc=v15) + block 8 start_pc=0 + v17 Phi { incoming=[b6:v13, b7:v15], kind=I64 } -> x2 v18 LoadLocal { off=-4, kind=I64 } -> x0 v19 Imm(1) -> x1 v20 Imm(0) -> x0 - terminator Bnz { cond=v17, target=b17, fall=b11 } (exit_acc=v17) - block 11 start_pc=0 + terminator Bnz { cond=v17, target=b16, fall=b9 } (exit_acc=v17) + block 9 start_pc=0 v21 Imm(0) -> x1 v22 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v21) - block 12 start_pc=0 - v23 Phi { incoming=[b17:v19, b11:v21], kind=I64 } -> x1 + terminator Jmp(b10) (exit_acc=v21) + block 10 start_pc=0 + v23 Phi { incoming=[b16:v19, b9:v21], kind=I64 } -> x1 v24 LoadLocal { off=-3, kind=I64 } -> x0 v25 Imm(0) -> x0 - terminator Bnz { cond=v23, target=b18, fall=b13 } (exit_acc=v23) - block 13 start_pc=0 + terminator Bnz { cond=v23, target=b15, fall=b11 } (exit_acc=v23) + block 11 start_pc=0 v26 Imm(0) -> x1 v27 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v26) - block 14 start_pc=0 - v28 Phi { incoming=[b18:v23, b13:v26], kind=I64 } -> x1 + terminator Jmp(b12) (exit_acc=v26) + block 12 start_pc=0 + v28 Phi { incoming=[b15:v23, b11:v26], kind=I64 } -> x1 v29 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v28, target=b16, fall=b15 } (exit_acc=v28) - block 15 start_pc=0 + terminator Bz { cond=v28, target=b14, fall=b13 } (exit_acc=v28) + block 13 start_pc=0 v30 Imm(4) -> x0 terminator Return(v30) (exit_acc=v30) - block 16 start_pc=0 + block 14 start_pc=0 v31 Imm(0) -> x0 terminator Return(v31) (exit_acc=v31) - block 17 start_pc=0 + block 15 start_pc=0 terminator Jmp(b12) + block 16 start_pc=0 + terminator Jmp(b10) + block 17 start_pc=0 + v9 Imm(2) -> x0 + terminator Return(v9) (exit_acc=v9) block 18 start_pc=0 - terminator Jmp(b14) + v11 Imm(3) -> x0 + terminator Return(v11) (exit_acc=v11) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/qsort_scan_extend_dedup.ssa b/tests/snapshots/ssa/qsort_scan_extend_dedup.ssa new file mode 100644 index 000000000..56903f12e --- /dev/null +++ b/tests/snapshots/ssa/qsort_scan_extend_dedup.ssa @@ -0,0 +1,257 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=qs +fn ent_pc=0 n_params=3 variadic=false locals=7 + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x3 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x12 + v6 Imm(0) -> x0 + v7 LoadLocal { off=3, kind=I32 } -> x0 + v8 LoadLocal { off=4, kind=I32 } -> x0 + v9 Binop { op=ge, lhs=v3, rhs=v5 } -> x0 + terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + block 1 start_pc=0 + v10 Imm(0) -> x0 + terminator Return(v10) (exit_acc=v10) + block 2 start_pc=0 + v11 LoadLocal { off=2, kind=I64 } -> x0 + v12 LoadLocal { off=3, kind=I32 } -> x0 + v13 LoadLocal { off=4, kind=I32 } -> x0 + v14 Binop { op=add, lhs=v3, rhs=v5 } -> x0 + v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 + v16 Extend { value=v14, kind=I32 } -> x0 + v17 Imm(2) -> x1 + v18 BinopI { op=shr, lhs=v16, rhs_imm=63 } -> x1 + v19 BinopI { op=shru, lhs=v18, rhs_imm=63 } -> x1 + v20 Binop { op=add, lhs=v16, rhs=v19 } -> x0 + v21 BinopI { op=shr, lhs=v20, rhs_imm=1 } -> x0 + v22 BinopI { op=shl, lhs=v21, rhs_imm=2 } -> x1 + v23 Binop { op=add, lhs=v1, rhs=v22 } -> x1 + v24 LoadIndexed { base=v1, index=v21, scale=4, kind=I32 } -> x0 + v25 Imm(0) -> x1 + v26 Imm(0) -> x1 + v27 Imm(0) -> x1 + terminator Jmp(b13) (exit_acc=v5) + block 3 start_pc=0 + terminator Jmp(b5) + block 4 start_pc=0 + v50 Extend { value=v42, kind=I32 } -> x7 + v51 BinopI { op=add, lhs=v44, rhs_imm=1 } -> x13 + v52 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v51) + block 5 start_pc=0 + v42 Phi { incoming=[b3:v29, b4:v51], kind=I64 } -> x13 + v43 LoadLocal { off=2, kind=I64 } -> x1 + v44 Extend { value=v42, kind=I32 } -> x1 + v45 BinopI { op=shl, lhs=v44, rhs_imm=2 } -> x7 + v46 Binop { op=add, lhs=v1, rhs=v45 } -> x7 + v47 LoadIndexed { base=v1, index=v44, scale=4, kind=I32 } -> x7 + v48 Extend { value=v24, kind=I32 } -> x8 + v49 Binop { op=lt, lhs=v47, rhs=v24 } -> x7 + terminator Bnz { cond=v49, target=b4, fall=b6 } (exit_acc=v49) + block 6 start_pc=0 + terminator Jmp(b8) + block 7 start_pc=0 + v61 Extend { value=v53, kind=I32 } -> x2 + v62 BinopI { op=add, lhs=v55, rhs_imm=-1 } -> x2 + v63 Imm(0) -> x7 + terminator Jmp(b8) (exit_acc=v62) + block 8 start_pc=0 + v53 Phi { incoming=[b6:v28, b7:v62], kind=I64 } -> x2 + v54 LoadLocal { off=2, kind=I64 } -> x7 + v55 Extend { value=v53, kind=I32 } -> x7 + v56 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x8 + v57 Binop { op=add, lhs=v1, rhs=v56 } -> x8 + v58 LoadIndexed { base=v1, index=v55, scale=4, kind=I32 } -> x8 + v59 Extend { value=v24, kind=I32 } -> x9 + v60 Binop { op=gt, lhs=v58, rhs=v24 } -> x8 + terminator Bnz { cond=v60, target=b7, fall=b9 } (exit_acc=v60) + block 9 start_pc=0 + v64 Extend { value=v42, kind=I32 } -> x8 + v65 Extend { value=v53, kind=I32 } -> x8 + v66 Binop { op=le, lhs=v44, rhs=v55 } -> x8 + terminator Bz { cond=v66, target=b11, fall=b10 } (exit_acc=v66) + block 10 start_pc=0 + v67 LoadLocal { off=2, kind=I64 } -> x8 + v68 Extend { value=v42, kind=I32 } -> x8 + v69 BinopI { op=shl, lhs=v44, rhs_imm=2 } -> x8 + v70 Binop { op=add, lhs=v1, rhs=v69 } -> x8 + v71 LoadIndexed { base=v1, index=v44, scale=4, kind=I32 } -> x8 + v72 Imm(0) -> x9 + v73 Extend { value=v53, kind=I32 } -> x9 + v74 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x9 + v75 Binop { op=add, lhs=v1, rhs=v74 } -> x9 + v76 LoadIndexed { base=v1, index=v55, scale=4, kind=I32 } -> x9 + v77 StoreIndexed { base=v1, index=v44, scale=4, value=v76, kind=I32 } -> - + v78 LoadLocal { off=2, kind=I64 } -> x1 + v79 Extend { value=v53, kind=I32 } -> x1 + v80 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x1 + v81 Binop { op=add, lhs=v1, rhs=v80 } -> x1 + v82 Extend { value=v71, kind=I32 } -> x1 + v83 StoreIndexed { base=v1, index=v55, scale=4, value=v71, kind=I32 } -> - + v84 Extend { value=v42, kind=I32 } -> x1 + v85 BinopI { op=add, lhs=v42, rhs_imm=1 } -> x13 + v86 Imm(0) -> x1 + v87 Extend { value=v53, kind=I32 } -> x1 + v88 BinopI { op=add, lhs=v55, rhs_imm=-1 } -> x2 + v89 Imm(0) -> x1 + terminator Jmp(b12) (exit_acc=v88) + block 11 start_pc=0 + terminator Jmp(b12) + block 12 start_pc=0 + v90 Phi { incoming=[b11:v53, b10:v88], kind=I64 } -> x2 + v91 Phi { incoming=[b11:v42, b10:v85], kind=I64 } -> x13 + terminator Jmp(b13) + block 13 start_pc=0 + v28 Phi { incoming=[b2:v5, b12:v90], kind=I64 } -> x2 + v29 Phi { incoming=[b2:v3, b12:v91], kind=I64 } -> x13 + v30 Extend { value=v29, kind=I32 } -> x1 + v31 Extend { value=v28, kind=I32 } -> x7 + v32 Binop { op=le, lhs=v30, rhs=v31 } -> x1 + terminator Bnz { cond=v32, target=b3, fall=b14 } (exit_acc=v32) + block 14 start_pc=0 + v33 LoadLocal { off=2, kind=I64 } -> x0 + v34 LoadLocal { off=3, kind=I32 } -> x0 + v35 Extend { value=v28, kind=I32 } -> x0 + v36 Call { target_pc=0, args=[v1, v3, v28], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v37 LoadLocal { off=2, kind=I64 } -> x0 + v38 Extend { value=v29, kind=I32 } -> x0 + v39 LoadLocal { off=4, kind=I32 } -> x0 + v40 Call { target_pc=0, args=[v1, v29, v5], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v41 Imm(0) -> x0 + terminator Return(v41) (exit_acc=v41) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=37 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(12345) -> x2 + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v3) + block 1 start_pc=0 + v12 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x2 + v13 BinopI { op=mul, lhs=v12, rhs_imm=1103515245 } -> x2 + v14 BinopI { op=and, lhs=v13, rhs_imm=4294967295 } -> x2 + v15 BinopI { op=add, lhs=v14, rhs_imm=12345 } -> x2 + v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x2 + v17 Imm(0) -> x6 + v18 LocalAddr(-32) -> x6 + v19 Extend { value=v5, kind=I32 } -> x7 + v20 BinopI { op=shl, lhs=v7, rhs_imm=2 } -> x7 + v21 Binop { op=add, lhs=v18, rhs=v20 } -> x7 + v22 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x7 + v23 BinopI { op=shru, lhs=v22, rhs_imm=16 } -> x7 + v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x8 + v25 Extend { value=v23, kind=I32 } -> x8 + v26 BinopI { op=sub, lhs=v23, rhs_imm=16384 } -> x7 + v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x8 + v28 Extend { value=v26, kind=I32 } -> x8 + v29 StoreIndexed { base=v18, index=v7, scale=4, value=v26, kind=I32 } -> - + terminator Jmp(b2) (exit_acc=v29) + block 2 start_pc=0 + v9 Extend { value=v5, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v10) + block 3 start_pc=0 + v5 Phi { incoming=[b0:v3, b2:v10], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x2 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=64 } -> x6 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) + block 4 start_pc=0 + v30 LocalAddr(-32) -> x7 + v31 Imm(0) -> x6 + v32 Imm(63) -> x2 + v33 Call { target_pc=0, args=[v30, v31, v32], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v34 Imm(1) -> x1 + v35 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v34) + block 5 start_pc=0 + v42 LocalAddr(-32) -> x2 + v43 Extend { value=v36, kind=I32 } -> x6 + v44 BinopI { op=shl, lhs=v37, rhs_imm=2 } -> x6 + v45 Binop { op=add, lhs=v42, rhs=v44 } -> x6 + v46 LoadIndexed { base=v42, index=v37, scale=4, kind=I32 } -> x2 + v47 LocalAddr(-32) -> x6 + v48 Extend { value=v36, kind=I32 } -> x7 + v49 BinopI { op=sub, lhs=v36, rhs_imm=1 } -> x7 + v50 BinopI { op=shl, lhs=v49, rhs_imm=32 } -> x8 + v51 Extend { value=v49, kind=I32 } -> x7 + v52 BinopI { op=shl, lhs=v51, rhs_imm=2 } -> x8 + v53 Binop { op=add, lhs=v47, rhs=v52 } -> x8 + v54 LoadIndexed { base=v47, index=v51, scale=4, kind=I32 } -> x6 + v55 Binop { op=lt, lhs=v46, rhs=v54 } -> x2 + terminator Bnz { cond=v55, target=b9, fall=b6 } (exit_acc=v55) + block 6 start_pc=0 + v39 Extend { value=v36, kind=I32 } -> x1 + v40 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x1 + v41 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v40) + block 7 start_pc=0 + v36 Phi { incoming=[b4:v34, b6:v40], kind=I64 } -> x1 + v37 Extend { value=v36, kind=I32 } -> x0 + v38 BinopI { op=lt, lhs=v37, rhs_imm=64 } -> x2 + terminator Bnz { cond=v38, target=b5, fall=b8 } (exit_acc=v38) + block 8 start_pc=0 + v56 Imm(0) -> x0 + terminator Return(v56) (exit_acc=v56) + block 9 start_pc=0 + v57 Imm(1) -> x0 + terminator Return(v57) (exit_acc=v57) + block 10 start_pc=0 + terminator Jmp(b6) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/queens.ssa b/tests/snapshots/ssa/queens.ssa index c71d5fe0a..99aaa55e6 100644 --- a/tests/snapshots/ssa/queens.ssa +++ b/tests/snapshots/ssa/queens.ssa @@ -12,72 +12,72 @@ fn ent_pc=0 n_params=3 variadic=false locals=3 v6 Imm(0) -> x0 v7 Imm(0) -> x1 v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + terminator Jmp(b7) (exit_acc=v7) block 1 start_pc=0 - v9 Phi { incoming=[b0:v7, b2:v16], kind=I64 } -> x1 - v10 Extend { value=v9, kind=I32 } -> x0 - v11 LoadLocal { off=3, kind=I32 } -> x8 - v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) - block 2 start_pc=0 - v13 Extend { value=v9, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 - v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 - v16 Extend { value=v14, kind=I32 } -> x1 - v17 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v16) - block 3 start_pc=0 - v18 LoadLocal { off=3, kind=I32 } -> x0 - v19 Extend { value=v9, kind=I32 } -> x0 - v20 Binop { op=sub, lhs=v3, rhs=v19 } -> x8 + v18 LoadLocal { off=3, kind=I32 } -> x8 + v19 Extend { value=v9, kind=I32 } -> x8 + v20 Binop { op=sub, lhs=v3, rhs=v10 } -> x8 v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x9 v22 Extend { value=v20, kind=I32 } -> x8 v23 Imm(0) -> x9 v24 LoadLocal { off=4, kind=I32 } -> x9 v25 LoadLocal { off=2, kind=I64 } -> x9 - v26 BinopI { op=shl, lhs=v19, rhs_imm=2 } -> x9 + v26 BinopI { op=shl, lhs=v10, rhs_imm=2 } -> x9 v27 Binop { op=add, lhs=v1, rhs=v26 } -> x9 - v28 LoadIndexed { base=v1, index=v19, scale=4, kind=I32 } -> x0 - v29 Binop { op=sub, lhs=v5, rhs=v28 } -> x0 - v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x9 - v31 Extend { value=v29, kind=I32 } -> x9 - v32 Imm(0) -> x0 - v33 LoadLocal { off=-3, kind=I32 } -> x0 - v34 BinopI { op=lt, lhs=v31, rhs_imm=0 } -> x0 - terminator Bz { cond=v34, target=b11, fall=b5 } (exit_acc=v34) + v28 LoadIndexed { base=v1, index=v10, scale=4, kind=I32 } -> x9 + v29 Binop { op=sub, lhs=v5, rhs=v28 } -> x9 + v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x3 + v31 Extend { value=v29, kind=I32 } -> x3 + v32 Imm(0) -> x9 + v33 LoadLocal { off=-3, kind=I32 } -> x9 + v34 BinopI { op=lt, lhs=v31, rhs_imm=0 } -> x9 + terminator Bz { cond=v34, target=b5, fall=b2 } (exit_acc=v34) + block 2 start_pc=0 + v36 LoadLocal { off=-3, kind=I32 } -> x9 + v37 BinopI { op=mul, lhs=v31, rhs_imm=-1 } -> x9 + v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x3 + v39 Extend { value=v37, kind=I32 } -> x3 + v40 Imm(0) -> x9 + terminator Jmp(b3) (exit_acc=v39) + block 3 start_pc=0 + v41 Phi { incoming=[b5:v31, b2:v39], kind=I64 } -> x3 + v42 LoadLocal { off=2, kind=I64 } -> x9 + v43 Extend { value=v9, kind=I32 } -> x9 + v44 BinopI { op=shl, lhs=v10, rhs_imm=2 } -> x9 + v45 Binop { op=add, lhs=v1, rhs=v44 } -> x9 + v46 LoadIndexed { base=v1, index=v10, scale=4, kind=I32 } -> x0 + v47 LoadLocal { off=4, kind=I32 } -> x9 + v48 Binop { op=eq, lhs=v46, rhs=v5 } -> x0 + terminator Bnz { cond=v48, target=b10, fall=b4 } (exit_acc=v48) block 4 start_pc=0 - v35 Imm(0) -> x0 - terminator Return(v35) (exit_acc=v35) + v50 LoadLocal { off=-2, kind=I32 } -> x0 + v51 Extend { value=v41, kind=I32 } -> x0 + v52 Binop { op=eq, lhs=v22, rhs=v51 } -> x0 + terminator Bz { cond=v52, target=b6, fall=b9 } (exit_acc=v52) block 5 start_pc=0 - v36 LoadLocal { off=-3, kind=I32 } -> x0 - v37 BinopI { op=mul, lhs=v31, rhs_imm=-1 } -> x0 - v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x9 - v39 Extend { value=v37, kind=I32 } -> x9 - v40 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v39) + terminator Jmp(b3) block 6 start_pc=0 - v41 Phi { incoming=[b11:v31, b5:v39], kind=I64 } -> x9 - v42 LoadLocal { off=2, kind=I64 } -> x0 - v43 Extend { value=v9, kind=I32 } -> x0 - v44 BinopI { op=shl, lhs=v43, rhs_imm=2 } -> x3 - v45 Binop { op=add, lhs=v1, rhs=v44 } -> x3 - v46 LoadIndexed { base=v1, index=v43, scale=4, kind=I32 } -> x0 - v47 LoadLocal { off=4, kind=I32 } -> x3 - v48 Binop { op=eq, lhs=v46, rhs=v5 } -> x0 - terminator Bz { cond=v48, target=b8, fall=b7 } (exit_acc=v48) + v13 Extend { value=v9, kind=I32 } -> x0 + v14 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 + v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 + v16 Extend { value=v14, kind=I32 } -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v16) block 7 start_pc=0 - v49 Imm(1) -> x0 - terminator Return(v49) (exit_acc=v49) + v9 Phi { incoming=[b0:v7, b6:v16], kind=I64 } -> x1 + v10 Extend { value=v9, kind=I32 } -> x0 + v11 LoadLocal { off=3, kind=I32 } -> x8 + v12 Binop { op=lt, lhs=v10, rhs=v3 } -> x8 + terminator Bnz { cond=v12, target=b1, fall=b8 } (exit_acc=v12) block 8 start_pc=0 - v50 LoadLocal { off=-2, kind=I32 } -> x0 - v51 Extend { value=v41, kind=I32 } -> x0 - v52 Binop { op=eq, lhs=v22, rhs=v51 } -> x0 - terminator Bz { cond=v52, target=b10, fall=b9 } (exit_acc=v52) + v35 Imm(0) -> x0 + terminator Return(v35) (exit_acc=v35) block 9 start_pc=0 v53 Imm(1) -> x0 terminator Return(v53) (exit_acc=v53) block 10 start_pc=0 - terminator Jmp(b2) + v49 Imm(1) -> x0 + terminator Return(v49) (exit_acc=v49) block 11 start_pc=0 terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -100,33 +100,16 @@ fn ent_pc=1 n_params=2 variadic=false locals=5 v8 Imm(0) -> x13 v9 Imm(0) -> x0 v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) + terminator Jmp(b7) (exit_acc=v8) block 3 start_pc=0 - v11 Phi { incoming=[b2:v8, b4:v19], kind=I64 } -> x13 - v12 Phi { incoming=[b2:v8, b4:v15], kind=I64 } -> x14 - v13 Extend { value=v11, kind=I32 } -> x0 - v14 BinopI { op=lt, lhs=v13, rhs_imm=8 } -> x0 - terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) - block 4 start_pc=0 - v15 Phi { incoming=[b7:v12, b8:v41], kind=I64 } -> x14 - v16 Extend { value=v11, kind=I32 } -> x0 - v17 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x13 - v20 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v19) - block 5 start_pc=0 v21 LoadLocal { off=2, kind=I64 } -> x0 v22 LoadLocal { off=3, kind=I32 } -> x0 - v23 Extend { value=v11, kind=I32 } -> x2 - v24 Call { target_pc=0, args=[v1, v3, v23], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Bz { cond=v24, target=b8, fall=b7 } (exit_acc=v24) - block 6 start_pc=0 - v25 Extend { value=v12, kind=I32 } -> x0 - terminator Return(v25) (exit_acc=v25) - block 7 start_pc=0 - terminator Jmp(b4) - block 8 start_pc=0 + v23 Extend { value=v11, kind=I32 } -> x0 + v24 Call { target_pc=0, args=[v1, v3, v11], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Bz { cond=v24, target=b5, fall=b4 } (exit_acc=v24) + block 4 start_pc=0 + terminator Jmp(b6) + block 5 start_pc=0 v26 LoadLocal { off=2, kind=I64 } -> x0 v27 LoadLocal { off=3, kind=I32 } -> x0 v28 BinopI { op=shl, lhs=v3, rhs_imm=2 } -> x0 @@ -136,15 +119,32 @@ fn ent_pc=1 n_params=2 variadic=false locals=5 v32 Extend { value=v12, kind=I32 } -> x0 v33 LoadLocal { off=2, kind=I64 } -> x0 v34 LoadLocal { off=3, kind=I32 } -> x0 - v35 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x1 - v37 Extend { value=v35, kind=I32 } -> x6 - v38 Call { target_pc=1, args=[v1, v37], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v35 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x6 + v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x0 + v37 Extend { value=v35, kind=I32 } -> x0 + v38 Call { target_pc=1, args=[v1, v35], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v39 Binop { op=add, lhs=v12, rhs=v38 } -> x0 v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x1 v41 Extend { value=v39, kind=I32 } -> x14 v42 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v41) + terminator Jmp(b6) (exit_acc=v41) + block 6 start_pc=0 + v15 Phi { incoming=[b4:v12, b5:v41], kind=I64 } -> x14 + v16 Extend { value=v11, kind=I32 } -> x0 + v17 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x0 + v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 + v19 Extend { value=v17, kind=I32 } -> x13 + v20 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v19) + block 7 start_pc=0 + v11 Phi { incoming=[b2:v8, b6:v19], kind=I64 } -> x13 + v12 Phi { incoming=[b2:v8, b6:v15], kind=I64 } -> x14 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 BinopI { op=lt, lhs=v13, rhs_imm=8 } -> x0 + terminator Bnz { cond=v14, target=b3, fall=b8 } (exit_acc=v14) + block 8 start_pc=0 + v25 Extend { value=v12, kind=I32 } -> x0 + terminator Return(v25) (exit_acc=v25) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=7 diff --git a/tests/snapshots/ssa/quicksort.ssa b/tests/snapshots/ssa/quicksort.ssa index eada53a15..9d36a8ed5 100644 --- a/tests/snapshots/ssa/quicksort.ssa +++ b/tests/snapshots/ssa/quicksort.ssa @@ -43,20 +43,8 @@ fn ent_pc=6 n_params=3 variadic=false locals=5 v16 Extend { value=v14, kind=I32 } -> x0 v17 Imm(0) -> x0 v18 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b6) (exit_acc=v3) block 1 start_pc=0 - v19 Phi { incoming=[b0:v3, b2:v25], kind=I64 } -> x14 - v20 Phi { incoming=[b0:v14, b2:v60], kind=I64 } -> x15 - v21 Extend { value=v19, kind=I32 } -> x0 - v22 LoadLocal { off=4, kind=I32 } -> x1 - v23 Binop { op=lt, lhs=v21, rhs=v5 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) - block 2 start_pc=0 - v24 Extend { value=v19, kind=I32 } -> x0 - v25 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x14 - v26 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v25) - block 3 start_pc=0 v27 LoadLocal { off=2, kind=I64 } -> x0 v28 Extend { value=v19, kind=I32 } -> x0 v29 BinopI { op=shl, lhs=v28, rhs_imm=2 } -> x1 @@ -64,8 +52,38 @@ fn ent_pc=6 n_params=3 variadic=false locals=5 v31 LoadIndexed { base=v1, index=v28, scale=4, kind=I32 } -> x0 v32 Extend { value=v11, kind=I32 } -> x1 v33 Binop { op=le, lhs=v31, rhs=v11 } -> x0 - terminator Bz { cond=v33, target=b7, fall=b5 } (exit_acc=v33) + terminator Bz { cond=v33, target=b4, fall=b2 } (exit_acc=v33) + block 2 start_pc=0 + v49 Extend { value=v20, kind=I32 } -> x0 + v50 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x15 + v51 Imm(0) -> x0 + v52 LoadLocal { off=2, kind=I64 } -> x0 + v53 Extend { value=v50, kind=I32 } -> x0 + v54 BinopI { op=shl, lhs=v53, rhs_imm=2 } -> x0 + v55 Binop { op=add, lhs=v1, rhs=v54 } -> x7 + v56 Extend { value=v19, kind=I32 } -> x0 + v57 BinopI { op=shl, lhs=v56, rhs_imm=2 } -> x0 + v58 Binop { op=add, lhs=v1, rhs=v57 } -> x6 + v59 Call { target_pc=5, args=[v55, v58], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Jmp(b3) (exit_acc=v59) + block 3 start_pc=0 + v60 Phi { incoming=[b4:v20, b2:v50], kind=I64 } -> x15 + terminator Jmp(b5) block 4 start_pc=0 + terminator Jmp(b3) + block 5 start_pc=0 + v24 Extend { value=v19, kind=I32 } -> x0 + v25 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x14 + v26 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v25) + block 6 start_pc=0 + v19 Phi { incoming=[b0:v3, b5:v25], kind=I64 } -> x14 + v20 Phi { incoming=[b0:v14, b5:v60], kind=I64 } -> x15 + v21 Extend { value=v19, kind=I32 } -> x0 + v22 LoadLocal { off=4, kind=I32 } -> x1 + v23 Binop { op=lt, lhs=v21, rhs=v5 } -> x0 + terminator Bnz { cond=v23, target=b1, fall=b7 } (exit_acc=v23) + block 7 start_pc=0 v34 LoadLocal { off=2, kind=I64 } -> x0 v35 Extend { value=v20, kind=I32 } -> x0 v36 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x0 @@ -82,24 +100,6 @@ fn ent_pc=6 n_params=3 variadic=false locals=5 v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x1 v48 Extend { value=v46, kind=I32 } -> x0 terminator Return(v48) (exit_acc=v48) - block 5 start_pc=0 - v49 Extend { value=v20, kind=I32 } -> x0 - v50 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x15 - v51 Imm(0) -> x0 - v52 LoadLocal { off=2, kind=I64 } -> x0 - v53 Extend { value=v50, kind=I32 } -> x0 - v54 BinopI { op=shl, lhs=v53, rhs_imm=2 } -> x0 - v55 Binop { op=add, lhs=v1, rhs=v54 } -> x7 - v56 Extend { value=v19, kind=I32 } -> x0 - v57 BinopI { op=shl, lhs=v56, rhs_imm=2 } -> x0 - v58 Binop { op=add, lhs=v1, rhs=v57 } -> x6 - v59 Call { target_pc=5, args=[v55, v58], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Jmp(b6) (exit_acc=v59) - block 6 start_pc=0 - v60 Phi { incoming=[b7:v20, b5:v50], kind=I64 } -> x15 - terminator Jmp(b2) - block 7 start_pc=0 - terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=7 --- ; name=quicksort fn ent_pc=7 n_params=3 variadic=false locals=4 @@ -125,17 +125,17 @@ fn ent_pc=7 n_params=3 variadic=false locals=4 v15 LoadLocal { off=2, kind=I64 } -> x0 v16 LoadLocal { off=3, kind=I32 } -> x0 v17 Extend { value=v13, kind=I32 } -> x0 - v18 BinopI { op=sub, lhs=v13, rhs_imm=1 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x2 - v21 Call { target_pc=7, args=[v1, v3, v20], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v18 BinopI { op=sub, lhs=v13, rhs_imm=1 } -> x2 + v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x0 + v20 Extend { value=v18, kind=I32 } -> x0 + v21 Call { target_pc=7, args=[v1, v3, v18], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 v22 LoadLocal { off=2, kind=I64 } -> x0 v23 Extend { value=v13, kind=I32 } -> x0 - v24 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x0 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x1 - v26 Extend { value=v24, kind=I32 } -> x6 + v24 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x6 + v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x0 + v26 Extend { value=v24, kind=I32 } -> x0 v27 LoadLocal { off=4, kind=I32 } -> x0 - v28 Call { target_pc=7, args=[v1, v26, v5], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v28 Call { target_pc=7, args=[v1, v24, v5], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 terminator Jmp(b2) (exit_acc=v28) block 2 start_pc=0 v29 Imm(0) -> x0 diff --git a/tests/snapshots/ssa/recursion_factorial.ssa b/tests/snapshots/ssa/recursion_factorial.ssa index c32f1bc82..b1386a7f0 100644 --- a/tests/snapshots/ssa/recursion_factorial.ssa +++ b/tests/snapshots/ssa/recursion_factorial.ssa @@ -14,10 +14,10 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 terminator Return(v5) (exit_acc=v5) block 2 start_pc=0 v6 LoadLocal { off=2, kind=I32 } -> x0 - v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x7 - v10 Call { target_pc=0, args=[v9], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v7], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v11 Binop { op=mul, lhs=v1, rhs=v10 } -> x0 v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 v13 Extend { value=v11, kind=I32 } -> x0 diff --git a/tests/snapshots/ssa/reg_alloc_callee_bank_call_block_before_loop.ssa b/tests/snapshots/ssa/reg_alloc_callee_bank_call_block_before_loop.ssa new file mode 100644 index 000000000..1cf1d6597 --- /dev/null +++ b/tests/snapshots/ssa/reg_alloc_callee_bank_call_block_before_loop.ssa @@ -0,0 +1,254 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=qs +fn ent_pc=0 n_params=3 variadic=false locals=7 + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x3 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x12 + v6 Imm(0) -> x0 + v7 LoadLocal { off=3, kind=I32 } -> x0 + v8 LoadLocal { off=4, kind=I32 } -> x0 + v9 Binop { op=ge, lhs=v3, rhs=v5 } -> x0 + terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + block 1 start_pc=0 + v10 Imm(0) -> x0 + terminator Return(v10) (exit_acc=v10) + block 2 start_pc=0 + v11 LoadLocal { off=2, kind=I64 } -> x0 + v12 LoadLocal { off=3, kind=I32 } -> x0 + v13 LoadLocal { off=4, kind=I32 } -> x0 + v14 Binop { op=add, lhs=v3, rhs=v5 } -> x0 + v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 + v16 Extend { value=v14, kind=I32 } -> x0 + v17 Imm(2) -> x1 + v18 BinopI { op=shr, lhs=v16, rhs_imm=63 } -> x1 + v19 BinopI { op=shru, lhs=v18, rhs_imm=63 } -> x1 + v20 Binop { op=add, lhs=v16, rhs=v19 } -> x0 + v21 BinopI { op=shr, lhs=v20, rhs_imm=1 } -> x0 + v22 BinopI { op=shl, lhs=v21, rhs_imm=2 } -> x1 + v23 Binop { op=add, lhs=v1, rhs=v22 } -> x1 + v24 LoadIndexed { base=v1, index=v21, scale=4, kind=I32 } -> x0 + v25 Imm(0) -> x1 + v26 Imm(0) -> x1 + v27 Imm(0) -> x1 + terminator Jmp(b13) (exit_acc=v5) + block 3 start_pc=0 + terminator Jmp(b5) + block 4 start_pc=0 + v50 Extend { value=v42, kind=I32 } -> x7 + v51 BinopI { op=add, lhs=v44, rhs_imm=1 } -> x13 + v52 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v51) + block 5 start_pc=0 + v42 Phi { incoming=[b3:v29, b4:v51], kind=I64 } -> x13 + v43 LoadLocal { off=2, kind=I64 } -> x1 + v44 Extend { value=v42, kind=I32 } -> x1 + v45 BinopI { op=shl, lhs=v44, rhs_imm=2 } -> x7 + v46 Binop { op=add, lhs=v1, rhs=v45 } -> x7 + v47 LoadIndexed { base=v1, index=v44, scale=4, kind=I32 } -> x7 + v48 Extend { value=v24, kind=I32 } -> x8 + v49 Binop { op=lt, lhs=v47, rhs=v24 } -> x7 + terminator Bnz { cond=v49, target=b4, fall=b6 } (exit_acc=v49) + block 6 start_pc=0 + terminator Jmp(b8) + block 7 start_pc=0 + v61 Extend { value=v53, kind=I32 } -> x2 + v62 BinopI { op=add, lhs=v55, rhs_imm=-1 } -> x2 + v63 Imm(0) -> x7 + terminator Jmp(b8) (exit_acc=v62) + block 8 start_pc=0 + v53 Phi { incoming=[b6:v28, b7:v62], kind=I64 } -> x2 + v54 LoadLocal { off=2, kind=I64 } -> x7 + v55 Extend { value=v53, kind=I32 } -> x7 + v56 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x8 + v57 Binop { op=add, lhs=v1, rhs=v56 } -> x8 + v58 LoadIndexed { base=v1, index=v55, scale=4, kind=I32 } -> x8 + v59 Extend { value=v24, kind=I32 } -> x9 + v60 Binop { op=gt, lhs=v58, rhs=v24 } -> x8 + terminator Bnz { cond=v60, target=b7, fall=b9 } (exit_acc=v60) + block 9 start_pc=0 + v64 Extend { value=v42, kind=I32 } -> x8 + v65 Extend { value=v53, kind=I32 } -> x8 + v66 Binop { op=le, lhs=v44, rhs=v55 } -> x8 + terminator Bz { cond=v66, target=b11, fall=b10 } (exit_acc=v66) + block 10 start_pc=0 + v67 LoadLocal { off=2, kind=I64 } -> x8 + v68 Extend { value=v42, kind=I32 } -> x8 + v69 BinopI { op=shl, lhs=v44, rhs_imm=2 } -> x8 + v70 Binop { op=add, lhs=v1, rhs=v69 } -> x8 + v71 LoadIndexed { base=v1, index=v44, scale=4, kind=I32 } -> x8 + v72 Imm(0) -> x9 + v73 Extend { value=v53, kind=I32 } -> x9 + v74 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x9 + v75 Binop { op=add, lhs=v1, rhs=v74 } -> x9 + v76 LoadIndexed { base=v1, index=v55, scale=4, kind=I32 } -> x9 + v77 StoreIndexed { base=v1, index=v44, scale=4, value=v76, kind=I32 } -> - + v78 LoadLocal { off=2, kind=I64 } -> x1 + v79 Extend { value=v53, kind=I32 } -> x1 + v80 BinopI { op=shl, lhs=v55, rhs_imm=2 } -> x1 + v81 Binop { op=add, lhs=v1, rhs=v80 } -> x1 + v82 Extend { value=v71, kind=I32 } -> x1 + v83 StoreIndexed { base=v1, index=v55, scale=4, value=v71, kind=I32 } -> - + v84 Extend { value=v42, kind=I32 } -> x1 + v85 BinopI { op=add, lhs=v42, rhs_imm=1 } -> x13 + v86 Imm(0) -> x1 + v87 Extend { value=v53, kind=I32 } -> x1 + v88 BinopI { op=add, lhs=v55, rhs_imm=-1 } -> x2 + v89 Imm(0) -> x1 + terminator Jmp(b12) (exit_acc=v88) + block 11 start_pc=0 + terminator Jmp(b12) + block 12 start_pc=0 + v90 Phi { incoming=[b11:v53, b10:v88], kind=I64 } -> x2 + v91 Phi { incoming=[b11:v42, b10:v85], kind=I64 } -> x13 + terminator Jmp(b13) + block 13 start_pc=0 + v28 Phi { incoming=[b2:v5, b12:v90], kind=I64 } -> x2 + v29 Phi { incoming=[b2:v3, b12:v91], kind=I64 } -> x13 + v30 Extend { value=v29, kind=I32 } -> x1 + v31 Extend { value=v28, kind=I32 } -> x7 + v32 Binop { op=le, lhs=v30, rhs=v31 } -> x1 + terminator Bnz { cond=v32, target=b3, fall=b14 } (exit_acc=v32) + block 14 start_pc=0 + v33 LoadLocal { off=2, kind=I64 } -> x0 + v34 LoadLocal { off=3, kind=I32 } -> x0 + v35 Extend { value=v28, kind=I32 } -> x0 + v36 Call { target_pc=0, args=[v1, v3, v28], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v37 LoadLocal { off=2, kind=I64 } -> x0 + v38 Extend { value=v29, kind=I32 } -> x0 + v39 LoadLocal { off=4, kind=I32 } -> x0 + v40 Call { target_pc=0, args=[v1, v29, v5], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v41 Imm(0) -> x0 + terminator Return(v41) (exit_acc=v41) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=37 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(12345) -> x2 + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v3) + block 1 start_pc=0 + v12 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x2 + v13 BinopI { op=mul, lhs=v12, rhs_imm=1103515245 } -> x2 + v14 BinopI { op=and, lhs=v13, rhs_imm=4294967295 } -> x2 + v15 BinopI { op=add, lhs=v14, rhs_imm=12345 } -> x2 + v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x2 + v17 Imm(0) -> x6 + v18 LocalAddr(-32) -> x6 + v19 Extend { value=v5, kind=I32 } -> x7 + v20 BinopI { op=shl, lhs=v7, rhs_imm=2 } -> x7 + v21 Binop { op=add, lhs=v18, rhs=v20 } -> x7 + v22 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x7 + v23 BinopI { op=and, lhs=v22, rhs_imm=2147483647 } -> x7 + v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x8 + v25 Extend { value=v23, kind=I32 } -> x8 + v26 StoreIndexed { base=v18, index=v7, scale=4, value=v23, kind=I32 } -> - + terminator Jmp(b2) (exit_acc=v26) + block 2 start_pc=0 + v9 Extend { value=v5, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v10) + block 3 start_pc=0 + v5 Phi { incoming=[b0:v3, b2:v10], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x2 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=64 } -> x6 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) + block 4 start_pc=0 + v27 LocalAddr(-32) -> x7 + v28 Imm(0) -> x6 + v29 Imm(63) -> x2 + v30 Call { target_pc=0, args=[v27, v28, v29], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v31 Imm(1) -> x1 + v32 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v31) + block 5 start_pc=0 + v39 LocalAddr(-32) -> x2 + v40 Extend { value=v33, kind=I32 } -> x6 + v41 BinopI { op=shl, lhs=v34, rhs_imm=2 } -> x6 + v42 Binop { op=add, lhs=v39, rhs=v41 } -> x6 + v43 LoadIndexed { base=v39, index=v34, scale=4, kind=I32 } -> x2 + v44 LocalAddr(-32) -> x6 + v45 Extend { value=v33, kind=I32 } -> x7 + v46 BinopI { op=sub, lhs=v33, rhs_imm=1 } -> x7 + v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x8 + v48 Extend { value=v46, kind=I32 } -> x7 + v49 BinopI { op=shl, lhs=v48, rhs_imm=2 } -> x8 + v50 Binop { op=add, lhs=v44, rhs=v49 } -> x8 + v51 LoadIndexed { base=v44, index=v48, scale=4, kind=I32 } -> x6 + v52 Binop { op=lt, lhs=v43, rhs=v51 } -> x2 + terminator Bnz { cond=v52, target=b9, fall=b6 } (exit_acc=v52) + block 6 start_pc=0 + v36 Extend { value=v33, kind=I32 } -> x1 + v37 BinopI { op=add, lhs=v34, rhs_imm=1 } -> x1 + v38 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v37) + block 7 start_pc=0 + v33 Phi { incoming=[b4:v31, b6:v37], kind=I64 } -> x1 + v34 Extend { value=v33, kind=I32 } -> x0 + v35 BinopI { op=lt, lhs=v34, rhs_imm=64 } -> x2 + terminator Bnz { cond=v35, target=b5, fall=b8 } (exit_acc=v35) + block 8 start_pc=0 + v53 Imm(0) -> x0 + terminator Return(v53) (exit_acc=v53) + block 9 start_pc=0 + v54 Imm(1) -> x0 + terminator Return(v54) (exit_acc=v54) + block 10 start_pc=0 + terminator Jmp(b6) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/return_int_widens_to_double.ssa b/tests/snapshots/ssa/return_int_widens_to_double.ssa index 3f3a333db..d4d763529 100644 --- a/tests/snapshots/ssa/return_int_widens_to_double.ssa +++ b/tests/snapshots/ssa/return_int_widens_to_double.ssa @@ -19,7 +19,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=7 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(505) -> x0 @@ -35,17 +35,17 @@ fn ent_pc=3 n_params=0 variadic=false locals=7 block 2 start_pc=0 v8 LoadLocal { off=-1, kind=F64 } -> d0 v9 Imm(4647574077957996544) -> x0 - v10 Binop { op=flt, lhs=v8, rhs=v9 } -> x3 + v10 Binop { op=flt, lhs=v8, rhs=v9 } -> x1 v11 Imm(0) -> x0 terminator Bnz { cond=v10, target=b13, fall=b3 } (exit_acc=v10) block 3 start_pc=0 v12 LoadLocal { off=-1, kind=F64 } -> d0 v13 Imm(4647609262330085376) -> x0 - v14 Binop { op=fgt, lhs=v12, rhs=v13 } -> x3 + v14 Binop { op=fgt, lhs=v12, rhs=v13 } -> x1 v15 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v14) block 4 start_pc=0 - v16 Phi { incoming=[b13:v10, b3:v14], kind=I64 } -> x3 + v16 Phi { incoming=[b13:v10, b3:v14], kind=I64 } -> x1 v17 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) block 5 start_pc=0 diff --git a/tests/snapshots/ssa/return_void_expression.ssa b/tests/snapshots/ssa/return_void_expression.ssa index c3cd0ac9e..9ff8942f6 100644 --- a/tests/snapshots/ssa/return_void_expression.ssa +++ b/tests/snapshots/ssa/return_void_expression.ssa @@ -30,19 +30,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 v3 ImmData(24) -> x0 v4 Load { addr=v3, disp=0, kind=I32 } -> x0 v5 BinopI { op=eq, lhs=v4, rhs_imm=2 } -> x0 - terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) + terminator Bz { cond=v5, target=b3, fall=b1 } (exit_acc=v5) block 1 start_pc=0 v6 Imm(0) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 Imm(1) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v8], kind=I64 } -> x1 + v10 Phi { incoming=[b1:v6, b3:v8], kind=I64 } -> x1 v11 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v10) (exit_acc=v10) + block 3 start_pc=0 + v8 Imm(1) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/rotate_inline_const_count.ssa b/tests/snapshots/ssa/rotate_inline_const_count.ssa new file mode 100644 index 000000000..cea63d6d5 --- /dev/null +++ b/tests/snapshots/ssa/rotate_inline_const_count.ssa @@ -0,0 +1,167 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=R +fn ent_pc=0 n_params=2 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=2, kind=I64 } -> x0 + v6 LoadLocal { off=3, kind=I32 } -> x0 + v7 Binop { op=shru, lhs=v1, rhs=v3 } -> x0 + v8 Imm(64) -> x0 + v9 Binop { op=sub, lhs=v8, rhs=v3 } -> x0 + v10 BinopI { op=shl, lhs=v9, rhs_imm=32 } -> x1 + v11 Extend { value=v9, kind=I32 } -> x0 + v12 Binop { op=shl, lhs=v1, rhs=v11 } -> x0 + v13 Binop { op=ror, lhs=v1, rhs=v3 } -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=mix +fn ent_pc=1 n_params=1 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I64 } -> x0 + v4 Imm(28) -> x0 + v5 Imm(0) -> x0 + v6 Imm(28) -> x0 + v7 Imm(0) -> x0 + v8 BinopI { op=shru, lhs=v1, rhs_imm=28 } -> x0 + v9 Imm(64) -> x0 + v10 Imm(36) -> x0 + v11 Imm(154618822656) -> x0 + v12 Imm(36) -> x0 + v13 BinopI { op=shl, lhs=v1, rhs_imm=36 } -> x0 + v14 BinopI { op=ror, lhs=v1, rhs_imm=28 } -> x0 + v15 LoadLocal { off=2, kind=I64 } -> x1 + v16 Imm(34) -> x1 + v17 Imm(0) -> x1 + v18 Imm(34) -> x1 + v19 Imm(0) -> x1 + v20 BinopI { op=shru, lhs=v1, rhs_imm=34 } -> x1 + v21 Imm(64) -> x1 + v22 Imm(30) -> x1 + v23 Imm(128849018880) -> x1 + v24 Imm(30) -> x1 + v25 BinopI { op=shl, lhs=v1, rhs_imm=30 } -> x1 + v26 BinopI { op=ror, lhs=v1, rhs_imm=34 } -> x1 + v27 Binop { op=xor, lhs=v14, rhs=v26 } -> x0 + v28 LoadLocal { off=2, kind=I64 } -> x1 + v29 Imm(39) -> x1 + v30 Imm(0) -> x1 + v31 Imm(39) -> x1 + v32 Imm(0) -> x1 + v33 BinopI { op=shru, lhs=v1, rhs_imm=39 } -> x1 + v34 Imm(64) -> x1 + v35 Imm(25) -> x1 + v36 Imm(107374182400) -> x1 + v37 Imm(25) -> x1 + v38 BinopI { op=shl, lhs=v1, rhs_imm=25 } -> x1 + v39 BinopI { op=ror, lhs=v1, rhs_imm=39 } -> x1 + v40 Binop { op=xor, lhs=v27, rhs=v39 } -> x0 + terminator Return(v40) (exit_acc=v40) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(81985529216486895) -> x0 + v2 StoreLocal { off=-1, value=v1, kind=I64, volatile } -> - + v3 LoadLocal { off=-1, kind=I64, volatile } -> x0 + v4 Imm(0) -> x1 + v5 Imm(28) -> x1 + v6 Imm(0) -> x1 + v7 Imm(28) -> x1 + v8 Imm(0) -> x1 + v9 BinopI { op=shru, lhs=v3, rhs_imm=28 } -> x1 + v10 Imm(64) -> x1 + v11 Imm(36) -> x1 + v12 Imm(154618822656) -> x1 + v13 Imm(36) -> x1 + v14 BinopI { op=shl, lhs=v3, rhs_imm=36 } -> x1 + v15 BinopI { op=ror, lhs=v3, rhs_imm=28 } -> x1 + v16 Imm(34) -> x2 + v17 Imm(0) -> x2 + v18 Imm(34) -> x2 + v19 Imm(0) -> x2 + v20 BinopI { op=shru, lhs=v3, rhs_imm=34 } -> x2 + v21 Imm(64) -> x2 + v22 Imm(30) -> x2 + v23 Imm(128849018880) -> x2 + v24 Imm(30) -> x2 + v25 BinopI { op=shl, lhs=v3, rhs_imm=30 } -> x2 + v26 BinopI { op=ror, lhs=v3, rhs_imm=34 } -> x2 + v27 Binop { op=xor, lhs=v15, rhs=v26 } -> x1 + v28 Imm(39) -> x2 + v29 Imm(0) -> x2 + v30 Imm(39) -> x2 + v31 Imm(0) -> x2 + v32 BinopI { op=shru, lhs=v3, rhs_imm=39 } -> x2 + v33 Imm(64) -> x2 + v34 Imm(25) -> x2 + v35 Imm(107374182400) -> x2 + v36 Imm(25) -> x2 + v37 BinopI { op=shl, lhs=v3, rhs_imm=25 } -> x2 + v38 BinopI { op=ror, lhs=v3, rhs_imm=39 } -> x0 + v39 Binop { op=xor, lhs=v27, rhs=v38 } -> x0 + v40 BinopI { op=ne, lhs=v39, rhs_imm=-5204619585009040981 } -> x0 + terminator Bz { cond=v40, target=b2, fall=b1 } (exit_acc=v40) + block 1 start_pc=0 + v41 Imm(1) -> x0 + terminator Return(v41) (exit_acc=v41) + block 2 start_pc=0 + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/rotate_variable_count.ssa b/tests/snapshots/ssa/rotate_variable_count.ssa index 65a320067..f4f11bb36 100644 --- a/tests/snapshots/ssa/rotate_variable_count.ssa +++ b/tests/snapshots/ssa/rotate_variable_count.ssa @@ -31,48 +31,48 @@ fn ent_pc=1 n_params=2 variadic=false locals=3 v5 Imm(0) -> x1 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b6) (exit_acc=v5) block 1 start_pc=0 - v8 Phi { incoming=[b0:v5, b2:v13], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v34], kind=I64 } -> x0 - v10 Extend { value=v8, kind=I32 } -> x2 - v11 BinopI { op=lt, lhs=v10, rhs_imm=64 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 LoadLocal { off=2, kind=I64 } -> x8 + v16 Imm(1) -> x8 + v17 Extend { value=v8, kind=I32 } -> x9 + v18 Binop { op=shl, lhs=v16, rhs=v10 } -> x8 + v19 Binop { op=and, lhs=v1, rhs=v18 } -> x8 + terminator Bz { cond=v19, target=b4, fall=b2 } (exit_acc=v19) block 2 start_pc=0 - v12 Extend { value=v8, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 - v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + v21 Extend { value=v8, kind=I32 } -> x8 + v22 LoadLocal { off=3, kind=I32 } -> x8 + v23 Binop { op=sub, lhs=v8, rhs=v3 } -> x8 + v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x9 + v25 Extend { value=v23, kind=I32 } -> x9 + v26 BinopI { op=and, lhs=v23, rhs_imm=63 } -> x8 + v27 Imm(0) -> x9 + v28 LoadLocal { off=-1, kind=I64 } -> x9 + v29 Imm(1) -> x9 + v30 Extend { value=v26, kind=I32 } -> x8 + v31 Binop { op=shl, lhs=v29, rhs=v30 } -> x8 + v32 Binop { op=or, lhs=v9, rhs=v31 } -> x0 + v33 Imm(0) -> x8 + terminator Jmp(b3) (exit_acc=v32) block 3 start_pc=0 - v15 LoadLocal { off=2, kind=I64 } -> x2 - v16 Imm(1) -> x2 - v17 Extend { value=v8, kind=I32 } -> x8 - v18 Binop { op=shl, lhs=v16, rhs=v17 } -> x2 - v19 Binop { op=and, lhs=v1, rhs=v18 } -> x2 - terminator Bz { cond=v19, target=b7, fall=b5 } (exit_acc=v19) + v34 Phi { incoming=[b4:v9, b2:v32], kind=I64 } -> x0 + terminator Jmp(b5) block 4 start_pc=0 - v20 LoadLocal { off=-1, kind=I64 } -> x1 - terminator Return(v9) (exit_acc=v9) + terminator Jmp(b3) block 5 start_pc=0 - v21 Extend { value=v8, kind=I32 } -> x2 - v22 LoadLocal { off=3, kind=I32 } -> x2 - v23 Binop { op=sub, lhs=v8, rhs=v3 } -> x2 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x8 - v25 Extend { value=v23, kind=I32 } -> x8 - v26 BinopI { op=and, lhs=v23, rhs_imm=63 } -> x2 - v27 Imm(0) -> x8 - v28 LoadLocal { off=-1, kind=I64 } -> x8 - v29 Imm(1) -> x8 - v30 Extend { value=v26, kind=I32 } -> x2 - v31 Binop { op=shl, lhs=v29, rhs=v30 } -> x2 - v32 Binop { op=or, lhs=v9, rhs=v31 } -> x0 - v33 Imm(0) -> x2 - terminator Jmp(b6) (exit_acc=v32) + v12 Extend { value=v8, kind=I32 } -> x1 + v13 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 + v14 Imm(0) -> x2 + terminator Jmp(b6) (exit_acc=v13) block 6 start_pc=0 - v34 Phi { incoming=[b7:v9, b5:v32], kind=I64 } -> x0 - terminator Jmp(b2) + v8 Phi { incoming=[b0:v5, b5:v13], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b5:v34], kind=I64 } -> x0 + v10 Extend { value=v8, kind=I32 } -> x2 + v11 BinopI { op=lt, lhs=v10, rhs_imm=64 } -> x8 + terminator Bnz { cond=v11, target=b1, fall=b7 } (exit_acc=v11) block 7 start_pc=0 - terminator Jmp(b6) + v20 LoadLocal { off=-1, kind=I64 } -> x1 + terminator Return(v9) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=11 @@ -84,49 +84,12 @@ fn ent_pc=2 n_params=0 variadic=false locals=11 v3 Mcpy { dst=v1, src=v2, size=48 } -> x0 v4 Imm(0) -> x3 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b6) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v4, b2:v16], kind=I64 } -> x3 - v7 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 - v8 Imm(48) -> x1 - v9 Imm(8) -> x2 - v10 Imm(0) -> x2 - v11 Binop { op=add, lhs=v8, rhs=v10 } -> x1 - v12 BinopI { op=shr, lhs=v11, rhs_imm=3 } -> x1 - v13 BinopI { op=and, lhs=v12, rhs_imm=4294967295 } -> x1 - v14 Binop { op=ult, lhs=v7, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 2 start_pc=0 - v15 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x3 - v17 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v16) - block 3 start_pc=0 v18 Imm(1) -> x0 v19 StoreLocal { off=-8, value=v18, kind=I32, volatile } -> - - terminator Jmp(b5) (exit_acc=v19) - block 4 start_pc=0 - v20 Imm(81985529216486895) -> x7 - v21 StoreLocal { off=-9, value=v20, kind=I64, volatile } -> - - v22 LoadLocal { off=-9, kind=I64, volatile } -> x0 - v23 BinopI { op=shru, lhs=v22, rhs_imm=7 } -> x0 - v24 LoadLocal { off=-9, kind=I64, volatile } -> x1 - v25 BinopI { op=shl, lhs=v24, rhs_imm=57 } -> x1 - v26 Binop { op=or, lhs=v23, rhs=v25 } -> x3 - v27 Imm(7) -> x6 - v28 Call { target_pc=1, args=[v20, v27], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v29 Binop { op=ne, lhs=v26, rhs=v28 } -> x0 - terminator Bz { cond=v29, target=b12, fall=b11 } (exit_acc=v29) - block 5 start_pc=0 - v30 LoadLocal { off=-8, kind=I32, volatile } -> x0 - v31 BinopI { op=lt, lhs=v30, rhs_imm=64 } -> x0 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) - block 6 start_pc=0 - v32 LoadLocal { off=-8, kind=I32, volatile } -> x0 - v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x0 - v34 StoreLocal { off=-8, value=v33, kind=I32, volatile } -> - - terminator Jmp(b5) (exit_acc=v34) - block 7 start_pc=0 + terminator Jmp(b4) (exit_acc=v19) + block 2 start_pc=0 v35 LocalAddr(-6) -> x0 v36 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x1 v37 BinopI { op=shl, lhs=v36, rhs_imm=3 } -> x2 @@ -151,20 +114,57 @@ fn ent_pc=2 n_params=0 variadic=false locals=11 v56 LoadLocal { off=-8, kind=I32, volatile } -> x6 v57 Call { target_pc=1, args=[v55, v56], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v58 Binop { op=ne, lhs=v50, rhs=v57 } -> x0 - terminator Bz { cond=v58, target=b10, fall=b9 } (exit_acc=v58) + terminator Bnz { cond=v58, target=b10, fall=b3 } (exit_acc=v58) + block 3 start_pc=0 + v32 LoadLocal { off=-8, kind=I32, volatile } -> x0 + v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x0 + v34 StoreLocal { off=-8, value=v33, kind=I32, volatile } -> - + terminator Jmp(b4) (exit_acc=v34) + block 4 start_pc=0 + v30 LoadLocal { off=-8, kind=I32, volatile } -> x0 + v31 BinopI { op=lt, lhs=v30, rhs_imm=64 } -> x0 + terminator Bnz { cond=v31, target=b2, fall=b5 } (exit_acc=v31) + block 5 start_pc=0 + v15 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 + v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x3 + v17 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v16) + block 6 start_pc=0 + v6 Phi { incoming=[b0:v4, b5:v16], kind=I64 } -> x3 + v7 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 + v8 Imm(48) -> x1 + v9 Imm(8) -> x1 + v10 Imm(0) -> x1 + v11 Imm(48) -> x1 + v12 Imm(6) -> x1 + v13 Imm(6) -> x1 + v14 BinopI { op=ult, lhs=v7, rhs_imm=6 } -> x0 + terminator Bnz { cond=v14, target=b1, fall=b7 } (exit_acc=v14) + block 7 start_pc=0 + v20 Imm(81985529216486895) -> x7 + v21 StoreLocal { off=-9, value=v20, kind=I64, volatile } -> - + v22 LoadLocal { off=-9, kind=I64, volatile } -> x0 + v23 BinopI { op=shru, lhs=v22, rhs_imm=7 } -> x0 + v24 LoadLocal { off=-9, kind=I64, volatile } -> x1 + v25 BinopI { op=shl, lhs=v24, rhs_imm=57 } -> x1 + v26 Binop { op=or, lhs=v23, rhs=v25 } -> x3 + v27 Imm(7) -> x6 + v28 Call { target_pc=1, args=[v20, v27], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v29 Binop { op=ne, lhs=v26, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b9, fall=b8 } (exit_acc=v29) block 8 start_pc=0 - terminator Jmp(b2) + v60 Imm(2) -> x0 + terminator Return(v60) (exit_acc=v60) block 9 start_pc=0 + v61 Imm(0) -> x0 + terminator Return(v61) (exit_acc=v61) + block 10 start_pc=0 v59 Imm(1) -> x0 terminator Return(v59) (exit_acc=v59) - block 10 start_pc=0 - terminator Jmp(b6) block 11 start_pc=0 - v60 Imm(2) -> x0 - terminator Return(v60) (exit_acc=v60) + terminator Jmp(b5) block 12 start_pc=0 - v61 Imm(0) -> x0 - terminator Return(v61) (exit_acc=v61) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/scalar_brace_initializer.ssa b/tests/snapshots/ssa/scalar_brace_initializer.ssa index fe837986d..91f7efb0f 100644 --- a/tests/snapshots/ssa/scalar_brace_initializer.ssa +++ b/tests/snapshots/ssa/scalar_brace_initializer.ssa @@ -5,108 +5,108 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(5) -> x0 - v2 Imm(0) -> x1 - v3 ImmData(16) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I32 } -> x2 - v6 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x2 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x6 - v8 Extend { value=v6, kind=I32 } -> x2 - v9 Imm(0) -> x6 - v10 Imm(7) -> x6 - v11 Imm(0) -> x7 - v12 LoadLocal { off=-3, kind=I32 } -> x7 - v13 Binop { op=add, lhs=v1, rhs=v8 } -> x7 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x8 - v15 Extend { value=v13, kind=I32 } -> x7 - v16 Imm(0) -> x8 - v17 LoadLocal { off=-5, kind=I32 } -> x8 - v18 BinopI { op=ne, lhs=v15, rhs_imm=11 } -> x7 - terminator Bz { cond=v18, target=b2, fall=b1 } (exit_acc=v18) + v2 Imm(0) -> x0 + v3 ImmData(16) -> x0 + v4 Imm(0) -> x1 + v5 LoadLocal { off=-1, kind=I32 } -> x1 + v6 Imm(6) -> x1 + v7 Imm(25769803776) -> x1 + v8 Imm(6) -> x1 + v9 Imm(0) -> x1 + v10 Imm(7) -> x1 + v11 Imm(0) -> x1 + v12 LoadLocal { off=-3, kind=I32 } -> x1 + v13 Imm(11) -> x1 + v14 Imm(47244640256) -> x1 + v15 Imm(11) -> x1 + v16 Imm(0) -> x1 + v17 LoadLocal { off=-5, kind=I32 } -> x1 + v18 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v18) block 1 start_pc=0 - v19 Imm(5) -> x0 - terminator Return(v19) (exit_acc=v19) + v20 ImmData(8) -> x1 + v21 Load { addr=v20, disp=0, kind=I32 } -> x1 + v22 BinopI { op=ne, lhs=v21, rhs_imm=41 } -> x1 + terminator Bz { cond=v22, target=b3, fall=b2 } (exit_acc=v22) block 2 start_pc=0 - v20 ImmData(8) -> x7 - v21 Load { addr=v20, disp=0, kind=I32 } -> x7 - v22 BinopI { op=ne, lhs=v21, rhs_imm=41 } -> x7 - terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) - block 3 start_pc=0 v23 Imm(1) -> x0 terminator Return(v23) (exit_acc=v23) + block 3 start_pc=0 + v24 LoadLocal { off=-1, kind=I32 } -> x1 + v25 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v25) block 4 start_pc=0 - v24 LoadLocal { off=-1, kind=I32 } -> x7 - v25 BinopI { op=ne, lhs=v1, rhs_imm=5 } -> x0 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) + v27 LoadLocal { off=-2, kind=I64 } -> x1 + v28 Imm(0) -> x1 + v29 Load { addr=v3, disp=0, kind=I8 } -> x1 + v30 BinopI { op=ne, lhs=v29, rhs_imm=120 } -> x1 + v31 Imm(1) -> x6 + v32 Imm(0) -> x2 + terminator Bnz { cond=v30, target=b16, fall=b5 } (exit_acc=v30) block 5 start_pc=0 - v26 Imm(2) -> x0 - terminator Return(v26) (exit_acc=v26) + v33 LoadLocal { off=-2, kind=I64 } -> x1 + v34 Imm(1) -> x1 + v35 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x1 + v36 Load { addr=v3, disp=1, kind=I8 } -> x1 + v37 BinopI { op=ne, lhs=v36, rhs_imm=121 } -> x1 + v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x6 + v39 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v38) block 6 start_pc=0 - v27 LoadLocal { off=-2, kind=I64 } -> x0 - v28 Imm(0) -> x0 - v29 Load { addr=v3, disp=0, kind=I8 } -> x0 - v30 BinopI { op=ne, lhs=v29, rhs_imm=120 } -> x0 - v31 Imm(1) -> x8 - v32 Imm(0) -> x7 - terminator Bnz { cond=v30, target=b19, fall=b7 } (exit_acc=v30) + v40 Phi { incoming=[b16:v31, b5:v38], kind=I64 } -> x6 + v41 LoadLocal { off=-7, kind=I64 } -> x1 + v42 Imm(0) -> x1 + terminator Bnz { cond=v40, target=b15, fall=b7 } (exit_acc=v40) block 7 start_pc=0 - v33 LoadLocal { off=-2, kind=I64 } -> x0 - v34 Imm(1) -> x0 - v35 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x0 - v36 Load { addr=v3, disp=1, kind=I8 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=121 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x8 - v39 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v38) - block 8 start_pc=0 - v40 Phi { incoming=[b19:v31, b7:v38], kind=I64 } -> x8 - v41 LoadLocal { off=-7, kind=I64 } -> x0 - v42 Imm(0) -> x0 - terminator Bnz { cond=v40, target=b20, fall=b9 } (exit_acc=v40) - block 9 start_pc=0 - v43 LoadLocal { off=-2, kind=I64 } -> x0 - v44 Imm(2) -> x0 - v45 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x0 + v43 LoadLocal { off=-2, kind=I64 } -> x1 + v44 Imm(2) -> x1 + v45 BinopI { op=add, lhs=v3, rhs_imm=2 } -> x1 v46 Load { addr=v3, disp=2, kind=I8 } -> x0 - v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x8 + v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x6 v48 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v47) - block 10 start_pc=0 - v49 Phi { incoming=[b20:v40, b9:v47], kind=I64 } -> x8 + terminator Jmp(b8) (exit_acc=v47) + block 8 start_pc=0 + v49 Phi { incoming=[b15:v40, b7:v47], kind=I64 } -> x6 v50 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Bz { cond=v49, target=b12, fall=b11 } (exit_acc=v49) - block 11 start_pc=0 + terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) + block 9 start_pc=0 v51 Imm(3) -> x0 terminator Return(v51) (exit_acc=v51) - block 12 start_pc=0 + block 10 start_pc=0 v52 LoadLocal { off=-3, kind=I32 } -> x0 - v53 BinopI { op=ne, lhs=v8, rhs_imm=6 } -> x0 - terminator Bz { cond=v53, target=b14, fall=b13 } (exit_acc=v53) - block 13 start_pc=0 - v54 Imm(4) -> x0 - terminator Return(v54) (exit_acc=v54) - block 14 start_pc=0 + v53 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v53) + block 11 start_pc=0 v55 LoadLocal { off=-4, kind=I32 } -> x0 - v56 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x0 - terminator Bz { cond=v56, target=b16, fall=b15 } (exit_acc=v56) - block 15 start_pc=0 - v57 Imm(6) -> x0 - terminator Return(v57) (exit_acc=v57) - block 16 start_pc=0 + v56 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v56) + block 12 start_pc=0 v58 ImmData(24) -> x0 v59 Load { addr=v58, disp=0, kind=I64 } -> x0 v60 BinopI { op=ne, lhs=v59, rhs_imm=100 } -> x0 - terminator Bz { cond=v60, target=b18, fall=b17 } (exit_acc=v60) - block 17 start_pc=0 + terminator Bz { cond=v60, target=b14, fall=b13 } (exit_acc=v60) + block 13 start_pc=0 v61 Imm(7) -> x0 terminator Return(v61) (exit_acc=v61) - block 18 start_pc=0 + block 14 start_pc=0 v62 Imm(0) -> x0 terminator Return(v62) (exit_acc=v62) - block 19 start_pc=0 + block 15 start_pc=0 terminator Jmp(b8) + block 16 start_pc=0 + terminator Jmp(b6) + block 17 start_pc=0 + v19 Imm(5) -> x0 + terminator Return(v19) (exit_acc=v19) + block 18 start_pc=0 + v26 Imm(2) -> x0 + terminator Return(v26) (exit_acc=v26) + block 19 start_pc=0 + v54 Imm(4) -> x0 + terminator Return(v54) (exit_acc=v54) block 20 start_pc=0 - terminator Jmp(b10) + v57 Imm(6) -> x0 + terminator Return(v57) (exit_acc=v57) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/setjmp_longjmp.ssa b/tests/snapshots/ssa/setjmp_longjmp.ssa index c50f93c1f..6ccc6b8c3 100644 --- a/tests/snapshots/ssa/setjmp_longjmp.ssa +++ b/tests/snapshots/ssa/setjmp_longjmp.ssa @@ -20,24 +20,21 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=69 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(11) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 v4 StoreLocal { off=-66, value=v3, kind=I32, volatile } -> - v5 LocalAddr(-65) -> x7 - v6 CallExt { binding_idx=0, args=[v5], fp_arg_mask=0x0 } -> x3 - v7 Imm(0) -> x0 - v8 Extend { value=v6, kind=I32 } -> x0 - v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) - block 3 start_pc=0 + v6 CallExt { binding_idx=0, args=[v5], fp_arg_mask=0x0 } -> x0 + v7 Imm(0) -> x1 + v8 Extend { value=v6, kind=I32 } -> x1 + v9 BinopI { op=eq, lhs=v8, rhs_imm=0 } -> x2 + terminator Bz { cond=v9, target=b3, fall=b2 } (exit_acc=v9) + block 2 start_pc=0 v10 LoadLocal { off=-66, kind=I32, volatile } -> x0 v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x0 v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 @@ -48,32 +45,35 @@ fn ent_pc=1 n_params=0 variadic=false locals=69 v17 Call { target_pc=0, args=[v15, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v18 Imm(12) -> x0 terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 + block 3 start_pc=0 v19 Extend { value=v6, kind=I32 } -> x0 - v20 BinopI { op=ne, lhs=v19, rhs_imm=7 } -> x0 - terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) - block 5 start_pc=0 + v20 BinopI { op=ne, lhs=v8, rhs_imm=7 } -> x0 + terminator Bz { cond=v20, target=b5, fall=b4 } (exit_acc=v20) + block 4 start_pc=0 v21 Imm(13) -> x0 terminator Return(v21) (exit_acc=v21) - block 6 start_pc=0 + block 5 start_pc=0 v22 LoadLocal { off=-66, kind=I32, volatile } -> x0 v23 BinopI { op=ne, lhs=v22, rhs_imm=1 } -> x0 - terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) - block 7 start_pc=0 + terminator Bz { cond=v23, target=b7, fall=b6 } (exit_acc=v23) + block 6 start_pc=0 v24 Imm(14) -> x0 terminator Return(v24) (exit_acc=v24) - block 8 start_pc=0 + block 7 start_pc=0 v25 LocalAddr(-65) -> x0 v26 BinopI { op=add, lhs=v25, rhs_imm=512 } -> x1 v27 Load { addr=v25, disp=512, kind=I32 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=7 } -> x0 - terminator Bz { cond=v28, target=b10, fall=b9 } (exit_acc=v28) - block 9 start_pc=0 + terminator Bz { cond=v28, target=b9, fall=b8 } (exit_acc=v28) + block 8 start_pc=0 v29 Imm(15) -> x0 terminator Return(v29) (exit_acc=v29) - block 10 start_pc=0 + block 9 start_pc=0 v30 Imm(0) -> x0 terminator Return(v30) (exit_acc=v30) + block 10 start_pc=0 + v2 Imm(11) -> x0 + terminator Return(v2) (exit_acc=v2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/setjmp_longjmp_roundtrip.ssa b/tests/snapshots/ssa/setjmp_longjmp_roundtrip.ssa index 4fdd962e0..11b90fd5a 100644 --- a/tests/snapshots/ssa/setjmp_longjmp_roundtrip.ssa +++ b/tests/snapshots/ssa/setjmp_longjmp_roundtrip.ssa @@ -1,12 +1,12 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=deep fn ent_pc=0 n_params=2 variadic=false locals=2 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 - v3 ParamRef(1, kind=I32) -> x3 + v3 ParamRef(1, kind=I32) -> x6 v4 Imm(0) -> x0 v5 ImmData(536) -> x0 v6 Load { addr=v5, disp=0, kind=I32, volatile } -> x1 @@ -19,11 +19,11 @@ fn ent_pc=0 n_params=2 variadic=false locals=2 terminator Bz { cond=v12, target=b3, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 LoadLocal { off=2, kind=I32 } -> x0 - v14 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x0 - v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x1 - v16 Extend { value=v14, kind=I32 } -> x7 + v14 BinopI { op=sub, lhs=v1, rhs_imm=1 } -> x7 + v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x0 + v16 Extend { value=v14, kind=I32 } -> x0 v17 LoadLocal { off=3, kind=I32 } -> x0 - v18 Call { target_pc=0, args=[v16, v3], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v18 Call { target_pc=0, args=[v14, v3], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 v22 Imm(0) -> x0 @@ -84,13 +84,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v31 ImmData(24) -> x0 v32 CallExt { binding_idx=0, args=[v4], fp_arg_mask=0x0 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=0 } -> x0 - terminator Bz { cond=v33, target=b9, fall=b7 } (exit_acc=v33) + terminator Bz { cond=v33, target=b14, fall=b7 } (exit_acc=v33) block 7 start_pc=0 v34 ImmData(544) -> x0 v35 Load { addr=v34, disp=0, kind=I32, volatile } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=1 } -> x0 - terminator Bz { cond=v36, target=b11, fall=b10 } (exit_acc=v36) + terminator Bz { cond=v36, target=b9, fall=b8 } (exit_acc=v36) block 8 start_pc=0 + v37 Imm(22) -> x0 + terminator Return(v37) (exit_acc=v37) + block 9 start_pc=0 v45 ImmData(552) -> x0 v46 Imm(3) -> x0 v47 Store { addr=v1, disp=0, value=v46, kind=I32, volatile } -> - @@ -100,30 +103,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v51 ImmData(24) -> x0 v52 CallExt { binding_idx=0, args=[v4], fp_arg_mask=0x0 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=0 } -> x0 - terminator Bz { cond=v53, target=b14, fall=b12 } (exit_acc=v53) - block 9 start_pc=0 - v38 ImmData(544) -> x0 - v39 Imm(1) -> x1 - v40 Store { addr=v38, disp=0, value=v39, kind=I32, volatile } -> - - v41 ImmData(24) -> x0 - v42 Imm(0) -> x6 - v43 CallExt { binding_idx=1, args=[v4, v42], fp_arg_mask=0x0 } -> x0 - v44 Imm(23) -> x0 - terminator Return(v44) (exit_acc=v44) + terminator Bz { cond=v53, target=b13, fall=b10 } (exit_acc=v53) block 10 start_pc=0 - v37 Imm(22) -> x0 - terminator Return(v37) (exit_acc=v37) - block 11 start_pc=0 - terminator Jmp(b8) - block 12 start_pc=0 v54 ImmData(544) -> x0 v55 Load { addr=v54, disp=0, kind=I32, volatile } -> x0 v56 BinopI { op=ne, lhs=v55, rhs_imm=7 } -> x0 - terminator Bz { cond=v56, target=b16, fall=b15 } (exit_acc=v56) - block 13 start_pc=0 + terminator Bz { cond=v56, target=b12, fall=b11 } (exit_acc=v56) + block 11 start_pc=0 + v57 Imm(32) -> x0 + terminator Return(v57) (exit_acc=v57) + block 12 start_pc=0 v64 Imm(0) -> x0 terminator Return(v64) (exit_acc=v64) - block 14 start_pc=0 + block 13 start_pc=0 v58 ImmData(544) -> x0 v59 Imm(7) -> x6 v60 Store { addr=v58, disp=0, value=v59, kind=I32, volatile } -> - @@ -131,11 +123,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v62 CallExt { binding_idx=1, args=[v4, v59], fp_arg_mask=0x0 } -> x0 v63 Imm(31) -> x0 terminator Return(v63) (exit_acc=v63) + block 14 start_pc=0 + v38 ImmData(544) -> x0 + v39 Imm(1) -> x1 + v40 Store { addr=v38, disp=0, value=v39, kind=I32, volatile } -> - + v41 ImmData(24) -> x0 + v42 Imm(0) -> x6 + v43 CallExt { binding_idx=1, args=[v4, v42], fp_arg_mask=0x0 } -> x0 + v44 Imm(23) -> x0 + terminator Return(v44) (exit_acc=v44) block 15 start_pc=0 - v57 Imm(32) -> x0 - terminator Return(v57) (exit_acc=v57) + terminator Jmp(b9) block 16 start_pc=0 - terminator Jmp(b13) + terminator Jmp(b12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/setjmp_spill_slots_unshared.ssa b/tests/snapshots/ssa/setjmp_spill_slots_unshared.ssa new file mode 100644 index 000000000..b0278de93 --- /dev/null +++ b/tests/snapshots/ssa/setjmp_spill_slots_unshared.ssa @@ -0,0 +1,659 @@ +; --- SSA dump (ok=true) ent_pc=6 --- +; name=main +fn ent_pc=6 n_params=0 variadic=false locals=32 + spill_count=98 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x1 + v2 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v1) + block 1 start_pc=0 + v9 ImmData(584) -> x2 + v10 Extend { value=v3, kind=I32 } -> x6 + v11 BinopI { op=shl, lhs=v4, rhs_imm=2 } -> x6 + v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 + v13 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x6 + v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 + v15 Extend { value=v13, kind=I32 } -> x7 + v16 StoreIndexed { base=v9, index=v4, scale=4, value=v13, kind=I32 } -> - + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=64 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) + block 4 start_pc=0 + v17 ImmData(584) -> x0 + v18 Imm(0) -> x1 + v19 Load { addr=v17, disp=0, kind=I32 } -> x1 + v20 BinopI { op=mul, lhs=v19, rhs_imm=3 } -> x1 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x2 + v22 Extend { value=v20, kind=I32 } -> x2 + v23 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x1 + v24 Extend { value=v22, kind=I32 } -> x3 + v25 Imm(0) -> x1 + v26 Imm(4) -> x1 + v27 BinopI { op=add, lhs=v17, rhs_imm=4 } -> x1 + v28 Load { addr=v17, disp=4, kind=I32 } -> x1 + v29 BinopI { op=mul, lhs=v28, rhs_imm=3 } -> x1 + v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x2 + v31 Extend { value=v29, kind=I32 } -> x2 + v32 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x1 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x2 + v34 Extend { value=v32, kind=I32 } -> x12 + v35 Imm(0) -> x1 + v36 Imm(8) -> x1 + v37 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x1 + v38 Load { addr=v17, disp=8, kind=I32 } -> x1 + v39 BinopI { op=mul, lhs=v38, rhs_imm=3 } -> x1 + v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x2 + v41 Extend { value=v39, kind=I32 } -> x2 + v42 BinopI { op=add, lhs=v39, rhs_imm=2 } -> x1 + v43 BinopI { op=shl, lhs=v42, rhs_imm=32 } -> x2 + v44 Extend { value=v42, kind=I32 } -> x13 + v45 Imm(0) -> x1 + v46 Imm(12) -> x1 + v47 BinopI { op=add, lhs=v17, rhs_imm=12 } -> x1 + v48 Load { addr=v17, disp=12, kind=I32 } -> x1 + v49 BinopI { op=mul, lhs=v48, rhs_imm=3 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=32 } -> x2 + v51 Extend { value=v49, kind=I32 } -> x2 + v52 BinopI { op=add, lhs=v49, rhs_imm=3 } -> x1 + v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> x2 + v54 Extend { value=v52, kind=I32 } -> x14 + v55 Imm(0) -> x1 + v56 Imm(16) -> x1 + v57 BinopI { op=add, lhs=v17, rhs_imm=16 } -> x1 + v58 Load { addr=v17, disp=16, kind=I32 } -> x1 + v59 BinopI { op=mul, lhs=v58, rhs_imm=3 } -> x1 + v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x2 + v61 Extend { value=v59, kind=I32 } -> x2 + v62 BinopI { op=add, lhs=v59, rhs_imm=4 } -> x1 + v63 BinopI { op=shl, lhs=v62, rhs_imm=32 } -> x2 + v64 Extend { value=v62, kind=I32 } -> x15 + v65 Imm(0) -> x1 + v66 Imm(20) -> x1 + v67 BinopI { op=add, lhs=v17, rhs_imm=20 } -> x1 + v68 Load { addr=v17, disp=20, kind=I32 } -> x1 + v69 BinopI { op=mul, lhs=v68, rhs_imm=3 } -> x1 + v70 BinopI { op=shl, lhs=v69, rhs_imm=32 } -> x2 + v71 Extend { value=v69, kind=I32 } -> x2 + v72 BinopI { op=add, lhs=v69, rhs_imm=5 } -> x1 + v73 BinopI { op=shl, lhs=v72, rhs_imm=32 } -> x2 + v74 Extend { value=v72, kind=I32 } -> [spill 0] + v75 Imm(0) -> x1 + v76 Imm(24) -> x1 + v77 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x1 + v78 Load { addr=v17, disp=24, kind=I32 } -> x1 + v79 BinopI { op=mul, lhs=v78, rhs_imm=3 } -> x1 + v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x2 + v81 Extend { value=v79, kind=I32 } -> x2 + v82 BinopI { op=add, lhs=v79, rhs_imm=6 } -> x1 + v83 BinopI { op=shl, lhs=v82, rhs_imm=32 } -> x2 + v84 Extend { value=v82, kind=I32 } -> [spill 1] + v85 Imm(0) -> x1 + v86 Imm(28) -> x1 + v87 BinopI { op=add, lhs=v17, rhs_imm=28 } -> x1 + v88 Load { addr=v17, disp=28, kind=I32 } -> x0 + v89 BinopI { op=mul, lhs=v88, rhs_imm=3 } -> x0 + v90 BinopI { op=shl, lhs=v89, rhs_imm=32 } -> x1 + v91 Extend { value=v89, kind=I32 } -> x1 + v92 BinopI { op=add, lhs=v89, rhs_imm=7 } -> x0 + v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x1 + v94 Extend { value=v92, kind=I32 } -> [spill 2] + v95 Imm(0) -> x0 + v96 ImmData(72) -> x7 + v97 CallExt { binding_idx=0, args=[v96], fp_arg_mask=0x0 } -> x0 + v98 BinopI { op=ne, lhs=v97, rhs_imm=0 } -> x0 + terminator Bz { cond=v98, target=b32, fall=b5 } (exit_acc=v98) + block 5 start_pc=0 + v99 Imm(0) -> x2 + v100 Imm(0) -> x0 + v101 LoadLocal { off=-2, kind=I32 } -> x0 + v102 ImmData(584) -> x0 + v103 Load { addr=v102, disp=0, kind=I32 } -> x0 + v104 BinopI { op=mul, lhs=v103, rhs_imm=3 } -> x0 + v105 BinopI { op=shl, lhs=v104, rhs_imm=32 } -> x1 + v106 Extend { value=v104, kind=I32 } -> x1 + v107 BinopI { op=shl, lhs=v104, rhs_imm=32 } -> x0 + v108 Extend { value=v106, kind=I32 } -> x0 + v109 Binop { op=ne, lhs=v24, rhs=v108 } -> x0 + terminator Bz { cond=v109, target=b31, fall=b6 } (exit_acc=v109) + block 6 start_pc=0 + v394 LoadLocal { off=-10, kind=I32 } -> x0 + v395 Imm(1) -> x0 + v396 Imm(4294967296) -> x0 + v397 Imm(1) -> x2 + v398 Imm(0) -> x0 + v399 Imm(1) -> x0 + terminator Jmp(b7) (exit_acc=v399) + block 7 start_pc=0 + v400 Phi { incoming=[b31:v99, b6:v397], kind=I64 } -> x2 + v401 LoadLocal { off=-3, kind=I32 } -> x0 + v402 ImmData(584) -> x0 + v403 Imm(4) -> x1 + v404 BinopI { op=add, lhs=v402, rhs_imm=4 } -> x1 + v405 Load { addr=v402, disp=4, kind=I32 } -> x0 + v406 BinopI { op=mul, lhs=v405, rhs_imm=3 } -> x0 + v407 BinopI { op=shl, lhs=v406, rhs_imm=32 } -> x1 + v408 Extend { value=v406, kind=I32 } -> x1 + v409 BinopI { op=add, lhs=v406, rhs_imm=1 } -> x0 + v410 BinopI { op=shl, lhs=v409, rhs_imm=32 } -> x1 + v411 Extend { value=v409, kind=I32 } -> x0 + v412 Binop { op=ne, lhs=v34, rhs=v411 } -> x0 + terminator Bz { cond=v412, target=b30, fall=b8 } (exit_acc=v412) + block 8 start_pc=0 + v413 Extend { value=v400, kind=I32 } -> x0 + v414 Imm(2) -> x0 + v415 Imm(8589934592) -> x0 + v416 BinopI { op=or, lhs=v400, rhs_imm=2 } -> x2 + v417 Imm(0) -> x0 + v418 Extend { value=v416, kind=I32 } -> x0 + terminator Jmp(b9) (exit_acc=v418) + block 9 start_pc=0 + v419 Phi { incoming=[b30:v400, b8:v416], kind=I64 } -> x2 + v420 LoadLocal { off=-4, kind=I32 } -> x0 + v421 ImmData(584) -> x0 + v422 Imm(8) -> x1 + v423 BinopI { op=add, lhs=v421, rhs_imm=8 } -> x1 + v424 Load { addr=v421, disp=8, kind=I32 } -> x0 + v425 BinopI { op=mul, lhs=v424, rhs_imm=3 } -> x0 + v426 BinopI { op=shl, lhs=v425, rhs_imm=32 } -> x1 + v427 Extend { value=v425, kind=I32 } -> x1 + v428 BinopI { op=add, lhs=v425, rhs_imm=2 } -> x0 + v429 BinopI { op=shl, lhs=v428, rhs_imm=32 } -> x1 + v430 Extend { value=v428, kind=I32 } -> x0 + v431 Binop { op=ne, lhs=v44, rhs=v430 } -> x0 + terminator Bz { cond=v431, target=b29, fall=b10 } (exit_acc=v431) + block 10 start_pc=0 + v432 Extend { value=v419, kind=I32 } -> x0 + v433 Imm(4) -> x0 + v434 Imm(17179869184) -> x0 + v435 BinopI { op=or, lhs=v419, rhs_imm=4 } -> x2 + v436 Imm(0) -> x0 + v437 Extend { value=v435, kind=I32 } -> x0 + terminator Jmp(b11) (exit_acc=v437) + block 11 start_pc=0 + v438 Phi { incoming=[b29:v419, b10:v435], kind=I64 } -> x2 + v439 LoadLocal { off=-5, kind=I32 } -> x0 + v440 ImmData(584) -> x0 + v441 Imm(12) -> x1 + v442 BinopI { op=add, lhs=v440, rhs_imm=12 } -> x1 + v443 Load { addr=v440, disp=12, kind=I32 } -> x0 + v444 BinopI { op=mul, lhs=v443, rhs_imm=3 } -> x0 + v445 BinopI { op=shl, lhs=v444, rhs_imm=32 } -> x1 + v446 Extend { value=v444, kind=I32 } -> x1 + v447 BinopI { op=add, lhs=v444, rhs_imm=3 } -> x0 + v448 BinopI { op=shl, lhs=v447, rhs_imm=32 } -> x1 + v449 Extend { value=v447, kind=I32 } -> x0 + v450 Binop { op=ne, lhs=v54, rhs=v449 } -> x0 + terminator Bz { cond=v450, target=b28, fall=b12 } (exit_acc=v450) + block 12 start_pc=0 + v451 Extend { value=v438, kind=I32 } -> x0 + v452 Imm(8) -> x0 + v453 Imm(34359738368) -> x0 + v454 BinopI { op=or, lhs=v438, rhs_imm=8 } -> x2 + v455 Imm(0) -> x0 + v456 Extend { value=v454, kind=I32 } -> x0 + terminator Jmp(b13) (exit_acc=v456) + block 13 start_pc=0 + v457 Phi { incoming=[b28:v438, b12:v454], kind=I64 } -> x2 + v458 LoadLocal { off=-6, kind=I32 } -> x0 + v459 ImmData(584) -> x0 + v460 Imm(16) -> x1 + v461 BinopI { op=add, lhs=v459, rhs_imm=16 } -> x1 + v462 Load { addr=v459, disp=16, kind=I32 } -> x0 + v463 BinopI { op=mul, lhs=v462, rhs_imm=3 } -> x0 + v464 BinopI { op=shl, lhs=v463, rhs_imm=32 } -> x1 + v465 Extend { value=v463, kind=I32 } -> x1 + v466 BinopI { op=add, lhs=v463, rhs_imm=4 } -> x0 + v467 BinopI { op=shl, lhs=v466, rhs_imm=32 } -> x1 + v468 Extend { value=v466, kind=I32 } -> x0 + v469 Binop { op=ne, lhs=v64, rhs=v468 } -> x0 + terminator Bz { cond=v469, target=b27, fall=b14 } (exit_acc=v469) + block 14 start_pc=0 + v470 Extend { value=v457, kind=I32 } -> x0 + v471 Imm(16) -> x0 + v472 Imm(68719476736) -> x0 + v473 BinopI { op=or, lhs=v457, rhs_imm=16 } -> x2 + v474 Imm(0) -> x0 + v475 Extend { value=v473, kind=I32 } -> x0 + terminator Jmp(b15) (exit_acc=v475) + block 15 start_pc=0 + v476 Phi { incoming=[b27:v457, b14:v473], kind=I64 } -> x2 + v477 LoadLocal { off=-7, kind=I32 } -> x0 + v478 ImmData(584) -> x0 + v479 Imm(20) -> x1 + v480 BinopI { op=add, lhs=v478, rhs_imm=20 } -> x1 + v481 Load { addr=v478, disp=20, kind=I32 } -> x0 + v482 BinopI { op=mul, lhs=v481, rhs_imm=3 } -> x0 + v483 BinopI { op=shl, lhs=v482, rhs_imm=32 } -> x1 + v484 Extend { value=v482, kind=I32 } -> x1 + v485 BinopI { op=add, lhs=v482, rhs_imm=5 } -> x0 + v486 BinopI { op=shl, lhs=v485, rhs_imm=32 } -> x1 + v487 Extend { value=v485, kind=I32 } -> x0 + v488 Binop { op=ne, lhs=v74, rhs=v487 } -> x0 + terminator Bz { cond=v488, target=b26, fall=b16 } (exit_acc=v488) + block 16 start_pc=0 + v489 Extend { value=v476, kind=I32 } -> x0 + v490 Imm(32) -> x0 + v491 Imm(137438953472) -> x0 + v492 BinopI { op=or, lhs=v476, rhs_imm=32 } -> x2 + v493 Imm(0) -> x0 + v494 Extend { value=v492, kind=I32 } -> x0 + terminator Jmp(b17) (exit_acc=v494) + block 17 start_pc=0 + v495 Phi { incoming=[b26:v476, b16:v492], kind=I64 } -> x2 + v496 LoadLocal { off=-8, kind=I32 } -> x0 + v497 ImmData(584) -> x0 + v498 Imm(24) -> x1 + v499 BinopI { op=add, lhs=v497, rhs_imm=24 } -> x1 + v500 Load { addr=v497, disp=24, kind=I32 } -> x0 + v501 BinopI { op=mul, lhs=v500, rhs_imm=3 } -> x0 + v502 BinopI { op=shl, lhs=v501, rhs_imm=32 } -> x1 + v503 Extend { value=v501, kind=I32 } -> x1 + v504 BinopI { op=add, lhs=v501, rhs_imm=6 } -> x0 + v505 BinopI { op=shl, lhs=v504, rhs_imm=32 } -> x1 + v506 Extend { value=v504, kind=I32 } -> x0 + v507 Binop { op=ne, lhs=v84, rhs=v506 } -> x0 + terminator Bz { cond=v507, target=b25, fall=b18 } (exit_acc=v507) + block 18 start_pc=0 + v508 Extend { value=v495, kind=I32 } -> x0 + v509 Imm(64) -> x0 + v510 Imm(274877906944) -> x0 + v511 BinopI { op=or, lhs=v495, rhs_imm=64 } -> x2 + v512 Imm(0) -> x0 + v513 Extend { value=v511, kind=I32 } -> x0 + terminator Jmp(b19) (exit_acc=v513) + block 19 start_pc=0 + v514 Phi { incoming=[b25:v495, b18:v511], kind=I64 } -> x2 + v515 LoadLocal { off=-9, kind=I32 } -> x0 + v516 ImmData(584) -> x0 + v517 Imm(28) -> x1 + v518 BinopI { op=add, lhs=v516, rhs_imm=28 } -> x1 + v519 Load { addr=v516, disp=28, kind=I32 } -> x0 + v520 BinopI { op=mul, lhs=v519, rhs_imm=3 } -> x0 + v521 BinopI { op=shl, lhs=v520, rhs_imm=32 } -> x1 + v522 Extend { value=v520, kind=I32 } -> x1 + v523 BinopI { op=add, lhs=v520, rhs_imm=7 } -> x0 + v524 BinopI { op=shl, lhs=v523, rhs_imm=32 } -> x1 + v525 Extend { value=v523, kind=I32 } -> x0 + v526 Binop { op=ne, lhs=v94, rhs=v525 } -> x0 + terminator Bz { cond=v526, target=b24, fall=b20 } (exit_acc=v526) + block 20 start_pc=0 + v527 Extend { value=v514, kind=I32 } -> x0 + v528 Imm(128) -> x0 + v529 Imm(549755813888) -> x0 + v530 BinopI { op=or, lhs=v514, rhs_imm=128 } -> x2 + v531 Imm(0) -> x0 + v532 Extend { value=v530, kind=I32 } -> x0 + terminator Jmp(b21) (exit_acc=v532) + block 21 start_pc=0 + v533 Phi { incoming=[b24:v514, b20:v530], kind=I64 } -> x2 + v534 Extend { value=v533, kind=I32 } -> x0 + terminator Bz { cond=v534, target=b23, fall=b22 } (exit_acc=v534) + block 22 start_pc=0 + v535 ImmData(32) -> x7 + v536 Extend { value=v533, kind=I32 } -> x6 + v537 CallExt { binding_idx=2, args=[v535, v536], fp_arg_mask=0x0 } -> x0 + v538 Imm(1) -> x0 + terminator Return(v538) (exit_acc=v538) + block 23 start_pc=0 + v539 ImmData(51) -> x7 + v540 CallExt { binding_idx=2, args=[v539], fp_arg_mask=0x0 } -> x0 + v541 Imm(0) -> x0 + terminator Return(v541) (exit_acc=v541) + block 24 start_pc=0 + terminator Jmp(b21) + block 25 start_pc=0 + terminator Jmp(b19) + block 26 start_pc=0 + terminator Jmp(b17) + block 27 start_pc=0 + terminator Jmp(b15) + block 28 start_pc=0 + terminator Jmp(b13) + block 29 start_pc=0 + terminator Jmp(b11) + block 30 start_pc=0 + terminator Jmp(b9) + block 31 start_pc=0 + terminator Jmp(b7) + block 32 start_pc=0 + v110 ImmData(584) -> x0 + v111 Imm(64) -> x1 + v112 BinopI { op=add, lhs=v110, rhs_imm=64 } -> x1 + v113 Load { addr=v110, disp=64, kind=I32 } -> x1 + v114 BinopI { op=mul, lhs=v113, rhs_imm=5 } -> x1 + v115 BinopI { op=shl, lhs=v114, rhs_imm=32 } -> x2 + v116 Extend { value=v114, kind=I32 } -> x2 + v117 BinopI { op=add, lhs=v114, rhs_imm=1 } -> x1 + v118 BinopI { op=shl, lhs=v117, rhs_imm=32 } -> x2 + v119 Extend { value=v117, kind=I32 } -> x2 + v120 Imm(0) -> x2 + v121 Imm(68) -> x2 + v122 BinopI { op=add, lhs=v110, rhs_imm=68 } -> x2 + v123 Load { addr=v110, disp=68, kind=I32 } -> x2 + v124 BinopI { op=mul, lhs=v123, rhs_imm=5 } -> x2 + v125 BinopI { op=shl, lhs=v124, rhs_imm=32 } -> x6 + v126 Extend { value=v124, kind=I32 } -> x6 + v127 BinopI { op=add, lhs=v124, rhs_imm=2 } -> x2 + v128 BinopI { op=shl, lhs=v127, rhs_imm=32 } -> x6 + v129 Extend { value=v127, kind=I32 } -> x6 + v130 Imm(0) -> x6 + v131 Imm(72) -> x6 + v132 BinopI { op=add, lhs=v110, rhs_imm=72 } -> x6 + v133 Load { addr=v110, disp=72, kind=I32 } -> x6 + v134 BinopI { op=mul, lhs=v133, rhs_imm=5 } -> x6 + v135 BinopI { op=shl, lhs=v134, rhs_imm=32 } -> x7 + v136 Extend { value=v134, kind=I32 } -> x7 + v137 BinopI { op=add, lhs=v134, rhs_imm=3 } -> x6 + v138 BinopI { op=shl, lhs=v137, rhs_imm=32 } -> x7 + v139 Extend { value=v137, kind=I32 } -> x7 + v140 Imm(0) -> x7 + v141 Imm(76) -> x7 + v142 BinopI { op=add, lhs=v110, rhs_imm=76 } -> x7 + v143 Load { addr=v110, disp=76, kind=I32 } -> x7 + v144 BinopI { op=mul, lhs=v143, rhs_imm=5 } -> x7 + v145 BinopI { op=shl, lhs=v144, rhs_imm=32 } -> x8 + v146 Extend { value=v144, kind=I32 } -> x8 + v147 BinopI { op=add, lhs=v144, rhs_imm=4 } -> x7 + v148 BinopI { op=shl, lhs=v147, rhs_imm=32 } -> x8 + v149 Extend { value=v147, kind=I32 } -> x8 + v150 Imm(0) -> x8 + v151 Imm(80) -> x8 + v152 BinopI { op=add, lhs=v110, rhs_imm=80 } -> x8 + v153 Load { addr=v110, disp=80, kind=I32 } -> x8 + v154 BinopI { op=mul, lhs=v153, rhs_imm=5 } -> x8 + v155 BinopI { op=shl, lhs=v154, rhs_imm=32 } -> x9 + v156 Extend { value=v154, kind=I32 } -> x9 + v157 BinopI { op=add, lhs=v154, rhs_imm=5 } -> x8 + v158 BinopI { op=shl, lhs=v157, rhs_imm=32 } -> x9 + v159 Extend { value=v157, kind=I32 } -> x9 + v160 Imm(0) -> x9 + v161 Imm(84) -> x9 + v162 BinopI { op=add, lhs=v110, rhs_imm=84 } -> x9 + v163 Load { addr=v110, disp=84, kind=I32 } -> x9 + v164 BinopI { op=mul, lhs=v163, rhs_imm=5 } -> x9 + v165 BinopI { op=shl, lhs=v164, rhs_imm=32 } -> x3 + v166 Extend { value=v164, kind=I32 } -> x3 + v167 BinopI { op=add, lhs=v164, rhs_imm=6 } -> x9 + v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x3 + v169 Extend { value=v167, kind=I32 } -> x3 + v170 Imm(0) -> x3 + v171 Imm(88) -> x3 + v172 BinopI { op=add, lhs=v110, rhs_imm=88 } -> x3 + v173 Load { addr=v110, disp=88, kind=I32 } -> x3 + v174 BinopI { op=mul, lhs=v173, rhs_imm=5 } -> x3 + v175 BinopI { op=shl, lhs=v174, rhs_imm=32 } -> x12 + v176 Extend { value=v174, kind=I32 } -> x12 + v177 BinopI { op=add, lhs=v174, rhs_imm=7 } -> x3 + v178 BinopI { op=shl, lhs=v177, rhs_imm=32 } -> x12 + v179 Extend { value=v177, kind=I32 } -> x12 + v180 Imm(0) -> x12 + v181 Imm(92) -> x12 + v182 BinopI { op=add, lhs=v110, rhs_imm=92 } -> x12 + v183 Load { addr=v110, disp=92, kind=I32 } -> x12 + v184 BinopI { op=mul, lhs=v183, rhs_imm=5 } -> x12 + v185 BinopI { op=shl, lhs=v184, rhs_imm=32 } -> x13 + v186 Extend { value=v184, kind=I32 } -> x13 + v187 BinopI { op=add, lhs=v184, rhs_imm=8 } -> x12 + v188 BinopI { op=shl, lhs=v187, rhs_imm=32 } -> x13 + v189 Extend { value=v187, kind=I32 } -> x13 + v190 Imm(0) -> x13 + v191 Imm(96) -> x13 + v192 BinopI { op=add, lhs=v110, rhs_imm=96 } -> x13 + v193 Load { addr=v110, disp=96, kind=I32 } -> x13 + v194 BinopI { op=mul, lhs=v193, rhs_imm=5 } -> x13 + v195 BinopI { op=shl, lhs=v194, rhs_imm=32 } -> x14 + v196 Extend { value=v194, kind=I32 } -> x14 + v197 BinopI { op=add, lhs=v194, rhs_imm=9 } -> x13 + v198 BinopI { op=shl, lhs=v197, rhs_imm=32 } -> x14 + v199 Extend { value=v197, kind=I32 } -> x14 + v200 Imm(0) -> x14 + v201 Imm(100) -> x14 + v202 BinopI { op=add, lhs=v110, rhs_imm=100 } -> x14 + v203 Load { addr=v110, disp=100, kind=I32 } -> x14 + v204 BinopI { op=mul, lhs=v203, rhs_imm=5 } -> x14 + v205 BinopI { op=shl, lhs=v204, rhs_imm=32 } -> x15 + v206 Extend { value=v204, kind=I32 } -> x15 + v207 BinopI { op=add, lhs=v204, rhs_imm=10 } -> x14 + v208 BinopI { op=shl, lhs=v207, rhs_imm=32 } -> x15 + v209 Extend { value=v207, kind=I32 } -> x15 + v210 Imm(0) -> x15 + v211 Imm(104) -> x15 + v212 BinopI { op=add, lhs=v110, rhs_imm=104 } -> x15 + v213 Load { addr=v110, disp=104, kind=I32 } -> x15 + v214 BinopI { op=mul, lhs=v213, rhs_imm=5 } -> x15 + v215 BinopI { op=shl, lhs=v214, rhs_imm=32 } -> [spill 3] + v216 Extend { value=v214, kind=I32 } -> [spill 4] + v217 BinopI { op=add, lhs=v214, rhs_imm=11 } -> x15 + v218 BinopI { op=shl, lhs=v217, rhs_imm=32 } -> [spill 5] + v219 Extend { value=v217, kind=I32 } -> [spill 6] + v220 Imm(0) -> [spill 7] + v221 Imm(108) -> [spill 8] + v222 BinopI { op=add, lhs=v110, rhs_imm=108 } -> [spill 9] + v223 Load { addr=v110, disp=108, kind=I32 } -> [spill 10] + v224 BinopI { op=mul, lhs=v223, rhs_imm=5 } -> [spill 11] + v225 BinopI { op=shl, lhs=v224, rhs_imm=32 } -> [spill 12] + v226 Extend { value=v224, kind=I32 } -> [spill 13] + v227 BinopI { op=add, lhs=v224, rhs_imm=12 } -> [spill 14] + v228 BinopI { op=shl, lhs=v227, rhs_imm=32 } -> [spill 15] + v229 Extend { value=v227, kind=I32 } -> [spill 16] + v230 Imm(0) -> [spill 17] + v231 Imm(112) -> [spill 18] + v232 BinopI { op=add, lhs=v110, rhs_imm=112 } -> [spill 19] + v233 Load { addr=v110, disp=112, kind=I32 } -> [spill 20] + v234 BinopI { op=mul, lhs=v233, rhs_imm=5 } -> [spill 21] + v235 BinopI { op=shl, lhs=v234, rhs_imm=32 } -> [spill 22] + v236 Extend { value=v234, kind=I32 } -> [spill 23] + v237 BinopI { op=add, lhs=v234, rhs_imm=13 } -> [spill 24] + v238 BinopI { op=shl, lhs=v237, rhs_imm=32 } -> [spill 25] + v239 Extend { value=v237, kind=I32 } -> [spill 26] + v240 Imm(0) -> [spill 27] + v241 Imm(116) -> [spill 28] + v242 BinopI { op=add, lhs=v110, rhs_imm=116 } -> [spill 29] + v243 Load { addr=v110, disp=116, kind=I32 } -> [spill 30] + v244 BinopI { op=mul, lhs=v243, rhs_imm=5 } -> [spill 31] + v245 BinopI { op=shl, lhs=v244, rhs_imm=32 } -> [spill 32] + v246 Extend { value=v244, kind=I32 } -> [spill 33] + v247 BinopI { op=add, lhs=v244, rhs_imm=14 } -> [spill 34] + v248 BinopI { op=shl, lhs=v247, rhs_imm=32 } -> [spill 35] + v249 Extend { value=v247, kind=I32 } -> [spill 36] + v250 Imm(0) -> [spill 37] + v251 Imm(120) -> [spill 38] + v252 BinopI { op=add, lhs=v110, rhs_imm=120 } -> [spill 39] + v253 Load { addr=v110, disp=120, kind=I32 } -> [spill 40] + v254 BinopI { op=mul, lhs=v253, rhs_imm=5 } -> [spill 41] + v255 BinopI { op=shl, lhs=v254, rhs_imm=32 } -> [spill 42] + v256 Extend { value=v254, kind=I32 } -> [spill 43] + v257 BinopI { op=add, lhs=v254, rhs_imm=15 } -> [spill 44] + v258 BinopI { op=shl, lhs=v257, rhs_imm=32 } -> [spill 45] + v259 Extend { value=v257, kind=I32 } -> [spill 46] + v260 Imm(0) -> [spill 47] + v261 Imm(124) -> [spill 48] + v262 BinopI { op=add, lhs=v110, rhs_imm=124 } -> [spill 49] + v263 Load { addr=v110, disp=124, kind=I32 } -> [spill 50] + v264 BinopI { op=mul, lhs=v263, rhs_imm=5 } -> [spill 51] + v265 BinopI { op=shl, lhs=v264, rhs_imm=32 } -> [spill 52] + v266 Extend { value=v264, kind=I32 } -> [spill 53] + v267 BinopI { op=add, lhs=v264, rhs_imm=16 } -> [spill 54] + v268 BinopI { op=shl, lhs=v267, rhs_imm=32 } -> [spill 55] + v269 Extend { value=v267, kind=I32 } -> [spill 56] + v270 Imm(0) -> [spill 57] + v271 Imm(128) -> [spill 58] + v272 BinopI { op=add, lhs=v110, rhs_imm=128 } -> [spill 59] + v273 Load { addr=v110, disp=128, kind=I32 } -> [spill 60] + v274 BinopI { op=mul, lhs=v273, rhs_imm=5 } -> [spill 61] + v275 BinopI { op=shl, lhs=v274, rhs_imm=32 } -> [spill 62] + v276 Extend { value=v274, kind=I32 } -> [spill 63] + v277 BinopI { op=add, lhs=v274, rhs_imm=17 } -> [spill 64] + v278 BinopI { op=shl, lhs=v277, rhs_imm=32 } -> [spill 65] + v279 Extend { value=v277, kind=I32 } -> [spill 66] + v280 Imm(0) -> [spill 67] + v281 Imm(132) -> [spill 68] + v282 BinopI { op=add, lhs=v110, rhs_imm=132 } -> [spill 69] + v283 Load { addr=v110, disp=132, kind=I32 } -> [spill 70] + v284 BinopI { op=mul, lhs=v283, rhs_imm=5 } -> [spill 71] + v285 BinopI { op=shl, lhs=v284, rhs_imm=32 } -> [spill 72] + v286 Extend { value=v284, kind=I32 } -> [spill 73] + v287 BinopI { op=add, lhs=v284, rhs_imm=18 } -> [spill 74] + v288 BinopI { op=shl, lhs=v287, rhs_imm=32 } -> [spill 75] + v289 Extend { value=v287, kind=I32 } -> [spill 76] + v290 Imm(0) -> [spill 77] + v291 Imm(136) -> [spill 78] + v292 BinopI { op=add, lhs=v110, rhs_imm=136 } -> [spill 79] + v293 Load { addr=v110, disp=136, kind=I32 } -> [spill 80] + v294 BinopI { op=mul, lhs=v293, rhs_imm=5 } -> [spill 81] + v295 BinopI { op=shl, lhs=v294, rhs_imm=32 } -> [spill 82] + v296 Extend { value=v294, kind=I32 } -> [spill 83] + v297 BinopI { op=add, lhs=v294, rhs_imm=19 } -> [spill 84] + v298 BinopI { op=shl, lhs=v297, rhs_imm=32 } -> [spill 85] + v299 Extend { value=v297, kind=I32 } -> [spill 86] + v300 Imm(0) -> [spill 87] + v301 Imm(140) -> [spill 88] + v302 BinopI { op=add, lhs=v110, rhs_imm=140 } -> [spill 89] + v303 Load { addr=v110, disp=140, kind=I32 } -> x0 + v304 BinopI { op=mul, lhs=v303, rhs_imm=5 } -> x0 + v305 BinopI { op=shl, lhs=v304, rhs_imm=32 } -> [spill 90] + v306 Extend { value=v304, kind=I32 } -> [spill 91] + v307 BinopI { op=add, lhs=v304, rhs_imm=20 } -> x0 + v308 BinopI { op=shl, lhs=v307, rhs_imm=32 } -> [spill 92] + v309 Extend { value=v307, kind=I32 } -> [spill 93] + v310 Imm(0) -> [spill 94] + v311 ImmData(840) -> [spill 95] + v312 LoadLocal { off=-11, kind=I32 } -> [spill 96] + v313 LoadLocal { off=-12, kind=I32 } -> [spill 97] + v314 Binop { op=add, lhs=v117, rhs=v127 } -> x1 + v315 BinopI { op=shl, lhs=v314, rhs_imm=32 } -> x2 + v316 Extend { value=v314, kind=I32 } -> x2 + v317 LoadLocal { off=-13, kind=I32 } -> x2 + v318 Binop { op=add, lhs=v314, rhs=v137 } -> x1 + v319 BinopI { op=shl, lhs=v318, rhs_imm=32 } -> x2 + v320 Extend { value=v318, kind=I32 } -> x2 + v321 LoadLocal { off=-14, kind=I32 } -> x2 + v322 Binop { op=add, lhs=v318, rhs=v147 } -> x1 + v323 BinopI { op=shl, lhs=v322, rhs_imm=32 } -> x2 + v324 Extend { value=v322, kind=I32 } -> x2 + v325 LoadLocal { off=-15, kind=I32 } -> x2 + v326 Binop { op=add, lhs=v322, rhs=v157 } -> x1 + v327 BinopI { op=shl, lhs=v326, rhs_imm=32 } -> x2 + v328 Extend { value=v326, kind=I32 } -> x2 + v329 LoadLocal { off=-16, kind=I32 } -> x2 + v330 Binop { op=add, lhs=v326, rhs=v167 } -> x1 + v331 BinopI { op=shl, lhs=v330, rhs_imm=32 } -> x2 + v332 Extend { value=v330, kind=I32 } -> x2 + v333 LoadLocal { off=-17, kind=I32 } -> x2 + v334 Binop { op=add, lhs=v330, rhs=v177 } -> x1 + v335 BinopI { op=shl, lhs=v334, rhs_imm=32 } -> x2 + v336 Extend { value=v334, kind=I32 } -> x2 + v337 LoadLocal { off=-18, kind=I32 } -> x2 + v338 Binop { op=add, lhs=v334, rhs=v187 } -> x1 + v339 BinopI { op=shl, lhs=v338, rhs_imm=32 } -> x2 + v340 Extend { value=v338, kind=I32 } -> x2 + v341 LoadLocal { off=-19, kind=I32 } -> x2 + v342 Binop { op=add, lhs=v338, rhs=v197 } -> x1 + v343 BinopI { op=shl, lhs=v342, rhs_imm=32 } -> x2 + v344 Extend { value=v342, kind=I32 } -> x2 + v345 LoadLocal { off=-20, kind=I32 } -> x2 + v346 Binop { op=add, lhs=v342, rhs=v207 } -> x1 + v347 BinopI { op=shl, lhs=v346, rhs_imm=32 } -> x2 + v348 Extend { value=v346, kind=I32 } -> x2 + v349 LoadLocal { off=-21, kind=I32 } -> x2 + v350 Binop { op=add, lhs=v346, rhs=v217 } -> x1 + v351 BinopI { op=shl, lhs=v350, rhs_imm=32 } -> x2 + v352 Extend { value=v350, kind=I32 } -> x2 + v353 LoadLocal { off=-22, kind=I32 } -> x2 + v354 Binop { op=add, lhs=v350, rhs=v227 } -> x1 + v355 BinopI { op=shl, lhs=v354, rhs_imm=32 } -> x2 + v356 Extend { value=v354, kind=I32 } -> x2 + v357 LoadLocal { off=-23, kind=I32 } -> x2 + v358 Binop { op=add, lhs=v354, rhs=v237 } -> x1 + v359 BinopI { op=shl, lhs=v358, rhs_imm=32 } -> x2 + v360 Extend { value=v358, kind=I32 } -> x2 + v361 LoadLocal { off=-24, kind=I32 } -> x2 + v362 Binop { op=add, lhs=v358, rhs=v247 } -> x1 + v363 BinopI { op=shl, lhs=v362, rhs_imm=32 } -> x2 + v364 Extend { value=v362, kind=I32 } -> x2 + v365 LoadLocal { off=-25, kind=I32 } -> x2 + v366 Binop { op=add, lhs=v362, rhs=v257 } -> x1 + v367 BinopI { op=shl, lhs=v366, rhs_imm=32 } -> x2 + v368 Extend { value=v366, kind=I32 } -> x2 + v369 LoadLocal { off=-26, kind=I32 } -> x2 + v370 Binop { op=add, lhs=v366, rhs=v267 } -> x1 + v371 BinopI { op=shl, lhs=v370, rhs_imm=32 } -> x2 + v372 Extend { value=v370, kind=I32 } -> x2 + v373 LoadLocal { off=-27, kind=I32 } -> x2 + v374 Binop { op=add, lhs=v370, rhs=v277 } -> x1 + v375 BinopI { op=shl, lhs=v374, rhs_imm=32 } -> x2 + v376 Extend { value=v374, kind=I32 } -> x2 + v377 LoadLocal { off=-28, kind=I32 } -> x2 + v378 Binop { op=add, lhs=v374, rhs=v287 } -> x1 + v379 BinopI { op=shl, lhs=v378, rhs_imm=32 } -> x2 + v380 Extend { value=v378, kind=I32 } -> x2 + v381 LoadLocal { off=-29, kind=I32 } -> x2 + v382 Binop { op=add, lhs=v378, rhs=v297 } -> x1 + v383 BinopI { op=shl, lhs=v382, rhs_imm=32 } -> x2 + v384 Extend { value=v382, kind=I32 } -> x2 + v385 LoadLocal { off=-30, kind=I32 } -> x2 + v386 Binop { op=add, lhs=v382, rhs=v307 } -> x0 + v387 BinopI { op=shl, lhs=v386, rhs_imm=32 } -> x1 + v388 Extend { value=v386, kind=I32 } -> x1 + v389 Store { addr=v311, disp=0, value=v386, kind=I32 } -> - + v390 ImmData(72) -> x7 + v391 Imm(1) -> x6 + v392 CallExt { binding_idx=1, args=[v390, v391], fp_arg_mask=0x0 } -> x0 + v393 Imm(2) -> x0 + terminator Return(v393) (exit_acc=v393) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/setjmp_value_live_across.ssa b/tests/snapshots/ssa/setjmp_value_live_across.ssa index 9b18b1ed5..687c3278a 100644 --- a/tests/snapshots/ssa/setjmp_value_live_across.ssa +++ b/tests/snapshots/ssa/setjmp_value_live_across.ssa @@ -48,19 +48,19 @@ fn ent_pc=7 n_params=0 variadic=false locals=3 v2 Imm(7) -> x6 v3 Call { target_pc=6, args=[v1, v2], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v4 BinopI { op=eq, lhs=v3, rhs_imm=42 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + terminator Bz { cond=v4, target=b3, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v5 Imm(0) -> x1 v6 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) + terminator Jmp(b2) (exit_acc=v5) block 2 start_pc=0 - v7 Imm(1) -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v7) - block 3 start_pc=0 - v9 Phi { incoming=[b1:v5, b2:v7], kind=I64 } -> x1 + v9 Phi { incoming=[b1:v5, b3:v7], kind=I64 } -> x1 v10 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v9) (exit_acc=v9) + block 3 start_pc=0 + v7 Imm(1) -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/shift_result_promoted_type.ssa b/tests/snapshots/ssa/shift_result_promoted_type.ssa index 1b42b4b32..1a584a155 100644 --- a/tests/snapshots/ssa/shift_result_promoted_type.ssa +++ b/tests/snapshots/ssa/shift_result_promoted_type.ssa @@ -5,61 +5,61 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-8589934592) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 BinopI { op=shr, lhs=v1, rhs_imm=1 } -> x0 - v5 Imm(0) -> x1 - v6 LoadLocal { off=-2, kind=I64 } -> x1 - v7 BinopI { op=ne, lhs=v4, rhs_imm=-4294967296 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(-4294967296) -> x0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-2, kind=I64 } -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 v9 Imm(-9223372036854775808) -> x0 - v10 Imm(0) -> x1 - v11 LoadLocal { off=-3, kind=I64 } -> x1 - v12 BinopI { op=shru, lhs=v9, rhs_imm=63 } -> x0 - v13 BinopI { op=ne, lhs=v12, rhs_imm=1 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v10 Imm(0) -> x0 + v11 LoadLocal { off=-3, kind=I64 } -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) + block 2 start_pc=0 + v15 Imm(2147483648) -> x0 + v16 Imm(0) -> x0 + v17 LoadLocal { off=-4, kind=U32 } -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(0) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v21) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v23 Imm(-16) -> x0 + v24 Imm(0) -> x0 + v25 LoadLocal { off=-5, kind=I32 } -> x0 + v26 Imm(-4) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v27) block 4 start_pc=0 - v15 Imm(2147483648) -> x0 - v16 Imm(0) -> x1 - v17 LoadLocal { off=-4, kind=U32 } -> x1 - v18 BinopI { op=shru, lhs=v15, rhs_imm=31 } -> x0 - v19 BinopI { op=xor, lhs=v18, rhs_imm=1 } -> x0 - v20 BinopI { op=and, lhs=v19, rhs_imm=4294967295 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=0 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) + v29 Imm(128) -> x0 + v30 Imm(0) -> x0 + v31 LoadLocal { off=-6, kind=U8 } -> x0 + v32 Imm(16) -> x0 + v33 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v33) block 5 start_pc=0 - v22 Imm(3) -> x0 - terminator Return(v22) (exit_acc=v22) + v35 Imm(0) -> x0 + terminator Return(v35) (exit_acc=v35) block 6 start_pc=0 - v23 Imm(-16) -> x0 - v24 Imm(0) -> x1 - v25 LoadLocal { off=-5, kind=I32 } -> x1 - v26 BinopI { op=shr, lhs=v23, rhs_imm=2 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=-4 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) block 7 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 8 start_pc=0 - v29 Imm(128) -> x0 - v30 Imm(0) -> x1 - v31 LoadLocal { off=-6, kind=U8 } -> x1 - v32 BinopI { op=shru, lhs=v29, rhs_imm=3 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=16 } -> x0 - terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) + v22 Imm(3) -> x0 + terminator Return(v22) (exit_acc=v22) block 9 start_pc=0 + v28 Imm(4) -> x0 + terminator Return(v28) (exit_acc=v28) + block 10 start_pc=0 v34 Imm(5) -> x0 terminator Return(v34) (exit_acc=v34) - block 10 start_pc=0 - v35 Imm(0) -> x0 - terminator Return(v35) (exit_acc=v35) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/shift_result_type_signedness.ssa b/tests/snapshots/ssa/shift_result_type_signedness.ssa index 8014718d4..ecd93bd86 100644 --- a/tests/snapshots/ssa/shift_result_type_signedness.ssa +++ b/tests/snapshots/ssa/shift_result_type_signedness.ssa @@ -23,88 +23,88 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(251) -> x0 - v2 Imm(24) -> x1 - v3 Imm(0) -> x2 - v4 Extend { value=v2, kind=I32 } -> x1 - v5 Imm(0) -> x2 - v6 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 - v7 Binop { op=shl, lhs=v6, rhs=v4 } -> x0 - v8 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x0 - v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x2 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 Binop { op=shr, lhs=v10, rhs=v4 } -> x0 - v12 BinopI { op=ne, lhs=v11, rhs_imm=-5 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v2 Imm(24) -> x0 + v3 Imm(0) -> x0 + v4 Imm(24) -> x0 + v5 Imm(0) -> x0 + v6 Imm(251) -> x0 + v7 Imm(4211081216) -> x0 + v8 Imm(4211081216) -> x0 + v9 Imm(-360287970189639680) -> x0 + v10 Imm(-83886080) -> x0 + v11 Imm(-5) -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v12) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) - block 2 start_pc=0 v14 Imm(255) -> x0 - v15 Imm(24) -> x1 - v16 Imm(0) -> x2 - v17 Extend { value=v15, kind=I32 } -> x1 - v18 Imm(0) -> x2 - v19 BinopI { op=and, lhs=v14, rhs_imm=4294967295 } -> x0 - v20 Binop { op=shl, lhs=v19, rhs=v17 } -> x0 - v21 BinopI { op=and, lhs=v20, rhs_imm=4294967295 } -> x0 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x2 - v23 Extend { value=v21, kind=I32 } -> x0 - v24 Binop { op=shr, lhs=v23, rhs=v17 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=-1 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v15 Imm(24) -> x0 + v16 Imm(0) -> x0 + v17 Imm(24) -> x0 + v18 Imm(0) -> x0 + v19 Imm(255) -> x0 + v20 Imm(4278190080) -> x0 + v21 Imm(4278190080) -> x0 + v22 Imm(-72057594037927936) -> x0 + v23 Imm(-16777216) -> x0 + v24 Imm(-1) -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v25) + block 2 start_pc=0 + v27 Imm(128) -> x0 + v28 Imm(24) -> x0 + v29 Imm(0) -> x0 + v30 Imm(24) -> x0 + v31 Imm(0) -> x0 + v32 Imm(128) -> x0 + v33 Imm(2147483648) -> x0 + v34 Imm(2147483648) -> x0 + v35 Imm(-9223372036854775808) -> x0 + v36 Imm(-2147483648) -> x0 + v37 Imm(-128) -> x0 + v38 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v38) block 3 start_pc=0 - v26 Imm(2) -> x0 - terminator Return(v26) (exit_acc=v26) + v40 Imm(127) -> x0 + v41 Imm(24) -> x0 + v42 Imm(0) -> x0 + v43 Imm(24) -> x0 + v44 Imm(0) -> x0 + v45 Imm(127) -> x0 + v46 Imm(2130706432) -> x0 + v47 Imm(2130706432) -> x0 + v48 Imm(9151314442816847872) -> x0 + v49 Imm(2130706432) -> x0 + v50 Imm(127) -> x0 + v51 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v51) block 4 start_pc=0 - v27 Imm(128) -> x0 - v28 Imm(24) -> x1 - v29 Imm(0) -> x2 - v30 Extend { value=v28, kind=I32 } -> x1 - v31 Imm(0) -> x2 - v32 BinopI { op=and, lhs=v27, rhs_imm=4294967295 } -> x0 - v33 Binop { op=shl, lhs=v32, rhs=v30 } -> x0 - v34 BinopI { op=and, lhs=v33, rhs_imm=4294967295 } -> x0 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x2 - v36 Extend { value=v34, kind=I32 } -> x0 - v37 Binop { op=shr, lhs=v36, rhs=v30 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=-128 } -> x0 - terminator Bz { cond=v38, target=b6, fall=b5 } (exit_acc=v38) + v53 Imm(32768) -> x0 + v54 Imm(0) -> x0 + v55 LoadLocal { off=-1, kind=U16 } -> x0 + v56 Imm(2147483648) -> x0 + v57 Imm(-9223372036854775808) -> x0 + v58 Imm(-2147483648) -> x0 + v59 Imm(-32768) -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v60) block 5 start_pc=0 - v39 Imm(3) -> x0 - terminator Return(v39) (exit_acc=v39) + v62 Imm(0) -> x0 + terminator Return(v62) (exit_acc=v62) block 6 start_pc=0 - v40 Imm(127) -> x0 - v41 Imm(24) -> x1 - v42 Imm(0) -> x2 - v43 Extend { value=v41, kind=I32 } -> x1 - v44 Imm(0) -> x2 - v45 BinopI { op=and, lhs=v40, rhs_imm=4294967295 } -> x0 - v46 Binop { op=shl, lhs=v45, rhs=v43 } -> x0 - v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x0 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x2 - v49 Extend { value=v47, kind=I32 } -> x0 - v50 Binop { op=shr, lhs=v49, rhs=v43 } -> x0 - v51 BinopI { op=ne, lhs=v50, rhs_imm=127 } -> x0 - terminator Bz { cond=v51, target=b8, fall=b7 } (exit_acc=v51) + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) block 7 start_pc=0 - v52 Imm(4) -> x0 - terminator Return(v52) (exit_acc=v52) + v26 Imm(2) -> x0 + terminator Return(v26) (exit_acc=v26) block 8 start_pc=0 - v53 Imm(32768) -> x0 - v54 Imm(0) -> x1 - v55 LoadLocal { off=-1, kind=U16 } -> x1 - v56 BinopI { op=shl, lhs=v53, rhs_imm=16 } -> x0 - v57 BinopI { op=shl, lhs=v56, rhs_imm=32 } -> x1 - v58 Extend { value=v56, kind=I32 } -> x0 - v59 BinopI { op=shr, lhs=v58, rhs_imm=16 } -> x0 - v60 BinopI { op=eq, lhs=v59, rhs_imm=0 } -> x0 - terminator Bz { cond=v60, target=b10, fall=b9 } (exit_acc=v60) + v39 Imm(3) -> x0 + terminator Return(v39) (exit_acc=v39) block 9 start_pc=0 + v52 Imm(4) -> x0 + terminator Return(v52) (exit_acc=v52) + block 10 start_pc=0 v61 Imm(5) -> x0 terminator Return(v61) (exit_acc=v61) - block 10 start_pc=0 - v62 Imm(0) -> x0 - terminator Return(v62) (exit_acc=v62) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/short_types.ssa b/tests/snapshots/ssa/short_types.ssa index 9f8b52f17..839236175 100644 --- a/tests/snapshots/ssa/short_types.ssa +++ b/tests/snapshots/ssa/short_types.ssa @@ -39,247 +39,199 @@ fn ent_pc=3 n_params=0 variadic=false locals=28 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1234) -> x0 - v2 Imm(0) -> x1 - v3 Imm(-42) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I16 } -> x2 - v6 BinopI { op=ne, lhs=v1, rhs_imm=1234 } -> x2 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(-42) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I16 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v8 LoadLocal { off=-2, kind=I16 } -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v8 LoadLocal { off=-2, kind=I16 } -> x2 - v9 BinopI { op=ne, lhs=v3, rhs_imm=-42 } -> x2 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v11 LoadLocal { off=-1, kind=I16 } -> x0 + v12 LoadLocal { off=-2, kind=I16 } -> x0 + v13 Imm(1192) -> x0 + v14 Imm(5119601016832) -> x0 + v15 Imm(1192) -> x0 + v16 Imm(0) -> x0 + v17 Imm(1192) -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v18) block 3 start_pc=0 - v10 Imm(2) -> x0 - terminator Return(v10) (exit_acc=v10) + v20 LoadLocal { off=-1, kind=I16 } -> x0 + v21 LoadLocal { off=-2, kind=I16 } -> x0 + v22 Imm(1276) -> x0 + v23 Imm(5480378269696) -> x0 + v24 Imm(1276) -> x0 + v25 Imm(0) -> x0 + v26 Imm(1276) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v27) block 4 start_pc=0 - v11 LoadLocal { off=-1, kind=I16 } -> x2 - v12 LoadLocal { off=-2, kind=I16 } -> x2 - v13 Binop { op=add, lhs=v1, rhs=v3 } -> x2 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x6 - v15 Extend { value=v13, kind=I32 } -> x2 - v16 Imm(0) -> x6 - v17 Extend { value=v15, kind=I16 } -> x2 - v18 BinopI { op=ne, lhs=v17, rhs_imm=1192 } -> x2 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v29 LoadLocal { off=-2, kind=I16 } -> x0 + v30 Imm(-126) -> x0 + v31 Imm(-541165879296) -> x0 + v32 Imm(-126) -> x0 + v33 Imm(0) -> x0 + v34 Imm(-126) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v35) block 5 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v37 LoadLocal { off=-1, kind=I16 } -> x0 + v38 Imm(7) -> x0 + v39 Imm(176) -> x0 + v40 Imm(0) -> x0 + v41 Imm(176) -> x0 + v42 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v42) block 6 start_pc=0 - v20 LoadLocal { off=-1, kind=I16 } -> x2 - v21 LoadLocal { off=-2, kind=I16 } -> x2 - v22 Binop { op=sub, lhs=v1, rhs=v3 } -> x2 - v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x6 - v24 Extend { value=v22, kind=I32 } -> x2 - v25 Imm(0) -> x6 - v26 Extend { value=v24, kind=I16 } -> x2 - v27 BinopI { op=ne, lhs=v26, rhs_imm=1276 } -> x2 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v44 LoadLocal { off=-1, kind=I16 } -> x0 + v45 Imm(7) -> x0 + v46 Imm(2) -> x0 + v47 Imm(0) -> x0 + v48 Imm(2) -> x0 + v49 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v49) block 7 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) - block 8 start_pc=0 - v29 LoadLocal { off=-2, kind=I16 } -> x2 - v30 BinopI { op=mul, lhs=v3, rhs_imm=3 } -> x1 - v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x2 - v32 Extend { value=v30, kind=I32 } -> x1 - v33 Imm(0) -> x2 - v34 Extend { value=v32, kind=I16 } -> x1 - v35 BinopI { op=ne, lhs=v34, rhs_imm=-126 } -> x1 - terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) - block 9 start_pc=0 - v36 Imm(5) -> x0 - terminator Return(v36) (exit_acc=v36) - block 10 start_pc=0 - v37 LoadLocal { off=-1, kind=I16 } -> x1 - v38 Imm(7) -> x1 - v39 Binop { op=div, lhs=v1, rhs=v38 } -> x1 - v40 Imm(0) -> x2 - v41 Extend { value=v39, kind=I16 } -> x1 - v42 BinopI { op=ne, lhs=v41, rhs_imm=176 } -> x1 - terminator Bz { cond=v42, target=b12, fall=b11 } (exit_acc=v42) - block 11 start_pc=0 - v43 Imm(6) -> x0 - terminator Return(v43) (exit_acc=v43) - block 12 start_pc=0 - v44 LoadLocal { off=-1, kind=I16 } -> x1 - v45 Imm(7) -> x1 - v46 Binop { op=mod, lhs=v1, rhs=v45 } -> x0 - v47 Imm(0) -> x1 - v48 Extend { value=v46, kind=I16 } -> x0 - v49 BinopI { op=ne, lhs=v48, rhs_imm=2 } -> x0 - terminator Bz { cond=v49, target=b14, fall=b13 } (exit_acc=v49) - block 13 start_pc=0 - v50 Imm(7) -> x0 - terminator Return(v50) (exit_acc=v50) - block 14 start_pc=0 - v51 Imm(1) -> x3 + v51 Imm(1) -> x0 v52 Imm(0) -> x0 v53 LoadLocal { off=-8, kind=I16 } -> x0 - v54 BinopI { op=shl, lhs=v51, rhs_imm=14 } -> x0 - v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x1 - v56 Extend { value=v54, kind=I32 } -> x0 - v57 Imm(0) -> x1 - v58 Extend { value=v56, kind=I16 } -> x0 - v59 BinopI { op=ne, lhs=v58, rhs_imm=16384 } -> x0 - terminator Bz { cond=v59, target=b16, fall=b15 } (exit_acc=v59) - block 15 start_pc=0 - v60 Imm(8) -> x0 - terminator Return(v60) (exit_acc=v60) - block 16 start_pc=0 + v54 Imm(16384) -> x0 + v55 Imm(70368744177664) -> x0 + v56 Imm(16384) -> x0 + v57 Imm(0) -> x0 + v58 Imm(16384) -> x0 + v59 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v59) + block 8 start_pc=0 v61 LoadLocal { off=-8, kind=I16 } -> x0 - v62 BinopI { op=shl, lhs=v51, rhs_imm=16 } -> x0 - v63 BinopI { op=shl, lhs=v62, rhs_imm=32 } -> x1 - v64 Extend { value=v62, kind=I32 } -> x7 + v62 Imm(65536) -> x0 + v63 Imm(281474976710656) -> x0 + v64 Imm(65536) -> x7 v65 Call { target_pc=1, args=[v64], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v66 Imm(0) -> x1 v67 Extend { value=v65, kind=I16 } -> x0 v68 BinopI { op=ne, lhs=v67, rhs_imm=0 } -> x0 - terminator Bz { cond=v68, target=b18, fall=b17 } (exit_acc=v68) - block 17 start_pc=0 + terminator Bz { cond=v68, target=b10, fall=b9 } (exit_acc=v68) + block 9 start_pc=0 v69 Imm(9) -> x0 terminator Return(v69) (exit_acc=v69) - block 18 start_pc=0 + block 10 start_pc=0 v70 LoadLocal { off=-8, kind=I16 } -> x0 - v71 BinopI { op=shl, lhs=v51, rhs_imm=15 } -> x0 - v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x1 - v73 Extend { value=v71, kind=I32 } -> x7 + v71 Imm(32768) -> x0 + v72 Imm(140737488355328) -> x0 + v73 Imm(32768) -> x7 v74 Call { target_pc=1, args=[v73], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v75 Imm(0) -> x1 v76 Extend { value=v74, kind=I16 } -> x0 v77 BinopI { op=ne, lhs=v76, rhs_imm=-32768 } -> x0 - terminator Bz { cond=v77, target=b20, fall=b19 } (exit_acc=v77) - block 19 start_pc=0 + terminator Bz { cond=v77, target=b12, fall=b11 } (exit_acc=v77) + block 11 start_pc=0 v78 Imm(10) -> x0 terminator Return(v78) (exit_acc=v78) - block 20 start_pc=0 + block 12 start_pc=0 v79 Imm(-8) -> x0 - v80 Imm(0) -> x1 - v81 LoadLocal { off=-12, kind=I16 } -> x1 - v82 BinopI { op=shr, lhs=v79, rhs_imm=1 } -> x0 - v83 Imm(0) -> x1 - v84 Extend { value=v82, kind=I16 } -> x0 - v85 BinopI { op=ne, lhs=v84, rhs_imm=-4 } -> x0 - terminator Bz { cond=v85, target=b22, fall=b21 } (exit_acc=v85) - block 21 start_pc=0 - v86 Imm(11) -> x0 - terminator Return(v86) (exit_acc=v86) - block 22 start_pc=0 + v80 Imm(0) -> x0 + v81 LoadLocal { off=-12, kind=I16 } -> x0 + v82 Imm(-4) -> x0 + v83 Imm(0) -> x0 + v84 Imm(-4) -> x0 + v85 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v85) + block 13 start_pc=0 v87 Imm(65534) -> x0 - v88 Imm(0) -> x1 - v89 Imm(1) -> x1 - v90 Imm(0) -> x2 - v91 LoadLocal { off=-14, kind=U16 } -> x2 - v92 LoadLocal { off=-15, kind=U16 } -> x2 - v93 Binop { op=add, lhs=v87, rhs=v89 } -> x2 - v94 BinopI { op=shl, lhs=v93, rhs_imm=32 } -> x6 - v95 Extend { value=v93, kind=I32 } -> x2 - v96 Imm(0) -> x6 - v97 LoadLocal { off=-16, kind=I32 } -> x6 - v98 Extend { value=v95, kind=I32 } -> x2 - v99 Imm(0) -> x6 - v100 BinopI { op=and, lhs=v98, rhs_imm=65535 } -> x2 - v101 Imm(0) -> x6 - v102 BinopI { op=and, lhs=v100, rhs_imm=65535 } -> x2 - v103 BinopI { op=xor, lhs=v102, rhs_imm=65535 } -> x2 - v104 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x2 - v105 BinopI { op=ne, lhs=v104, rhs_imm=0 } -> x2 - terminator Bz { cond=v105, target=b24, fall=b23 } (exit_acc=v105) - block 23 start_pc=0 - v106 Imm(12) -> x0 - terminator Return(v106) (exit_acc=v106) - block 24 start_pc=0 - v107 LoadLocal { off=-14, kind=U16 } -> x2 - v108 LoadLocal { off=-15, kind=U16 } -> x2 - v109 Binop { op=add, lhs=v87, rhs=v89 } -> x0 - v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x2 - v111 Extend { value=v109, kind=I32 } -> x2 - v112 BinopI { op=add, lhs=v109, rhs_imm=1 } -> x0 - v113 BinopI { op=shl, lhs=v112, rhs_imm=32 } -> x2 - v114 Extend { value=v112, kind=I32 } -> x0 - v115 Extend { value=v114, kind=I32 } -> x0 - v116 Imm(0) -> x2 - v117 BinopI { op=and, lhs=v115, rhs_imm=65535 } -> x0 - v118 Imm(0) -> x2 - v119 BinopI { op=and, lhs=v117, rhs_imm=65535 } -> x0 - v120 BinopI { op=ne, lhs=v119, rhs_imm=0 } -> x0 - terminator Bz { cond=v120, target=b26, fall=b25 } (exit_acc=v120) - block 25 start_pc=0 - v121 Imm(13) -> x0 - terminator Return(v121) (exit_acc=v121) - block 26 start_pc=0 + v88 Imm(0) -> x0 + v89 Imm(1) -> x0 + v90 Imm(0) -> x0 + v91 LoadLocal { off=-14, kind=U16 } -> x0 + v92 LoadLocal { off=-15, kind=U16 } -> x0 + v93 Imm(65535) -> x0 + v94 Imm(281470681743360) -> x0 + v95 Imm(65535) -> x0 + v96 Imm(0) -> x0 + v97 LoadLocal { off=-16, kind=I32 } -> x0 + v98 Imm(65535) -> x0 + v99 Imm(0) -> x0 + v100 Imm(65535) -> x0 + v101 Imm(0) -> x0 + v102 Imm(65535) -> x0 + v103 Imm(0) -> x0 + v104 Imm(0) -> x0 + v105 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v105) + block 14 start_pc=0 + v107 LoadLocal { off=-14, kind=U16 } -> x0 + v108 LoadLocal { off=-15, kind=U16 } -> x0 + v109 Imm(65535) -> x0 + v110 Imm(281470681743360) -> x0 + v111 Imm(65535) -> x0 + v112 Imm(65536) -> x0 + v113 Imm(281474976710656) -> x0 + v114 Imm(65536) -> x0 + v115 Imm(65536) -> x0 + v116 Imm(0) -> x0 + v117 Imm(0) -> x0 + v118 Imm(0) -> x0 + v119 Imm(0) -> x0 + v120 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v120) + block 15 start_pc=0 v122 Imm(-1) -> x0 - v123 Imm(0) -> x2 - v124 Imm(1) -> x2 - v125 Imm(0) -> x6 - v126 LoadLocal { off=-20, kind=U16 } -> x6 - v127 LoadLocal { off=-19, kind=I16 } -> x6 - v128 Binop { op=add, lhs=v124, rhs=v122 } -> x6 - v129 BinopI { op=shl, lhs=v128, rhs_imm=32 } -> x7 - v130 Extend { value=v128, kind=I32 } -> x6 - v131 Imm(0) -> x7 - v132 LoadLocal { off=-21, kind=I32 } -> x7 - v133 BinopI { op=ne, lhs=v130, rhs_imm=0 } -> x6 - terminator Bz { cond=v133, target=b28, fall=b27 } (exit_acc=v133) - block 27 start_pc=0 - v134 Imm(14) -> x0 - terminator Return(v134) (exit_acc=v134) - block 28 start_pc=0 - v135 LoadLocal { off=-19, kind=I16 } -> x6 - v136 Extend { value=v122, kind=I32 } -> x6 - v137 Imm(0) -> x6 - v138 BinopI { op=and, lhs=v122, rhs_imm=65535 } -> x0 - v139 Imm(0) -> x6 - v140 Extend { value=v138, kind=I32 } -> x6 - v141 BinopI { op=ne, lhs=v140, rhs_imm=65535 } -> x6 - terminator Bz { cond=v141, target=b30, fall=b29 } (exit_acc=v141) - block 29 start_pc=0 - v142 Imm(15) -> x0 - terminator Return(v142) (exit_acc=v142) - block 30 start_pc=0 - v143 Extend { value=v138, kind=I32 } -> x0 - v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x0 - v145 LoadLocal { off=-20, kind=U16 } -> x6 - v146 Binop { op=ule, lhs=v144, rhs=v124 } -> x0 - terminator Bz { cond=v146, target=b32, fall=b31 } (exit_acc=v146) - block 31 start_pc=0 - v147 Imm(16) -> x0 - terminator Return(v147) (exit_acc=v147) - block 32 start_pc=0 + v123 Imm(0) -> x0 + v124 Imm(1) -> x0 + v125 Imm(0) -> x0 + v126 LoadLocal { off=-20, kind=U16 } -> x0 + v127 LoadLocal { off=-19, kind=I16 } -> x0 + v128 Imm(0) -> x0 + v129 Imm(0) -> x0 + v130 Imm(0) -> x0 + v131 Imm(0) -> x0 + v132 LoadLocal { off=-21, kind=I32 } -> x0 + v133 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v133) + block 16 start_pc=0 + v135 LoadLocal { off=-19, kind=I16 } -> x0 + v136 Imm(-1) -> x0 + v137 Imm(0) -> x0 + v138 Imm(65535) -> x0 + v139 Imm(0) -> x0 + v140 Imm(65535) -> x0 + v141 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v141) + block 17 start_pc=0 + v143 Imm(65535) -> x0 + v144 Imm(65535) -> x0 + v145 LoadLocal { off=-20, kind=U16 } -> x0 + v146 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v146) + block 18 start_pc=0 v148 LoadLocal { off=-15, kind=U16 } -> x0 - v149 BinopI { op=shl, lhs=v89, rhs_imm=15 } -> x0 - v150 BinopI { op=shl, lhs=v149, rhs_imm=32 } -> x1 - v151 Extend { value=v149, kind=I32 } -> x0 - v152 Extend { value=v151, kind=I32 } -> x0 - v153 Imm(0) -> x1 - v154 BinopI { op=and, lhs=v152, rhs_imm=65535 } -> x0 - v155 Imm(0) -> x1 - v156 BinopI { op=and, lhs=v154, rhs_imm=65535 } -> x0 - v157 BinopI { op=xor, lhs=v156, rhs_imm=32768 } -> x0 - v158 BinopI { op=and, lhs=v157, rhs_imm=4294967295 } -> x0 - v159 BinopI { op=ne, lhs=v158, rhs_imm=0 } -> x0 - terminator Bz { cond=v159, target=b34, fall=b33 } (exit_acc=v159) - block 33 start_pc=0 - v160 Imm(17) -> x0 - terminator Return(v160) (exit_acc=v160) - block 34 start_pc=0 + v149 Imm(32768) -> x0 + v150 Imm(140737488355328) -> x0 + v151 Imm(32768) -> x0 + v152 Imm(32768) -> x0 + v153 Imm(0) -> x0 + v154 Imm(32768) -> x0 + v155 Imm(0) -> x0 + v156 Imm(32768) -> x0 + v157 Imm(0) -> x0 + v158 Imm(0) -> x0 + v159 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v159) + block 19 start_pc=0 v161 Imm(32768) -> x0 - v162 Imm(0) -> x1 - v163 LoadLocal { off=-24, kind=U16 } -> x1 - v164 Imm(0) -> x1 - v165 Extend { value=v161, kind=I32 } -> x0 - v166 BinopI { op=shr, lhs=v165, rhs_imm=1 } -> x0 - v167 Imm(0) -> x1 - v168 Extend { value=v166, kind=I32 } -> x0 - v169 BinopI { op=ne, lhs=v168, rhs_imm=16384 } -> x0 - terminator Bz { cond=v169, target=b36, fall=b35 } (exit_acc=v169) - block 35 start_pc=0 - v170 Imm(18) -> x0 - terminator Return(v170) (exit_acc=v170) - block 36 start_pc=0 + v162 Imm(0) -> x0 + v163 LoadLocal { off=-24, kind=U16 } -> x0 + v164 Imm(0) -> x0 + v165 Imm(32768) -> x0 + v166 Imm(16384) -> x0 + v167 Imm(0) -> x0 + v168 Imm(16384) -> x0 + v169 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v169) + block 20 start_pc=0 v171 LocalAddr(-27) -> x0 v172 Imm(0) -> x1 v173 Imm(100) -> x1 @@ -311,10 +263,10 @@ fn ent_pc=3 n_params=0 variadic=false locals=28 v199 LocalAddr(-27) -> x1 v200 BinopI { op=add, lhs=v199, rhs_imm=4 } -> x2 v201 Load { addr=v199, disp=4, kind=I16 } -> x1 - v202 Binop { op=add, lhs=v196, rhs=v201 } -> x0 - v203 BinopI { op=shl, lhs=v202, rhs_imm=32 } -> x1 - v204 Extend { value=v202, kind=I32 } -> x7 - v205 Call { target_pc=1, args=[v204], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v202 Binop { op=add, lhs=v196, rhs=v201 } -> x7 + v203 BinopI { op=shl, lhs=v202, rhs_imm=32 } -> x0 + v204 Extend { value=v202, kind=I32 } -> x0 + v205 Call { target_pc=1, args=[v202], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v206 Store { addr=v188, disp=6, value=v205, kind=I16 } -> - v207 BinopI { op=shl, lhs=v205, rhs_imm=48 } -> x1 v208 Extend { value=v205, kind=I16 } -> x0 @@ -322,11 +274,11 @@ fn ent_pc=3 n_params=0 variadic=false locals=28 v210 BinopI { op=add, lhs=v209, rhs_imm=6 } -> x1 v211 Load { addr=v209, disp=6, kind=I16 } -> x0 v212 BinopI { op=ne, lhs=v211, rhs_imm=0 } -> x0 - terminator Bz { cond=v212, target=b38, fall=b37 } (exit_acc=v212) - block 37 start_pc=0 + terminator Bz { cond=v212, target=b22, fall=b21 } (exit_acc=v212) + block 21 start_pc=0 v213 Imm(19) -> x0 terminator Return(v213) (exit_acc=v213) - block 38 start_pc=0 + block 22 start_pc=0 v214 LocalAddr(-28) -> x0 v215 Imm(7) -> x1 v216 Store { addr=v214, disp=0, value=v215, kind=I16 } -> - @@ -349,24 +301,72 @@ fn ent_pc=3 n_params=0 variadic=false locals=28 v233 BinopI { op=shl, lhs=v232, rhs_imm=32 } -> x1 v234 Extend { value=v232, kind=I32 } -> x0 v235 BinopI { op=ne, lhs=v234, rhs_imm=0 } -> x0 - terminator Bz { cond=v235, target=b40, fall=b39 } (exit_acc=v235) - block 39 start_pc=0 + terminator Bz { cond=v235, target=b24, fall=b23 } (exit_acc=v235) + block 23 start_pc=0 v236 Imm(20) -> x0 terminator Return(v236) (exit_acc=v236) - block 40 start_pc=0 + block 24 start_pc=0 v237 LocalAddr(-28) -> x0 v238 BinopI { op=add, lhs=v237, rhs_imm=4 } -> x1 v239 Load { addr=v237, disp=4, kind=U16 } -> x0 v240 BinopI { op=xor, lhs=v239, rhs_imm=49374 } -> x0 v241 BinopI { op=and, lhs=v240, rhs_imm=4294967295 } -> x0 v242 BinopI { op=ne, lhs=v241, rhs_imm=0 } -> x0 - terminator Bz { cond=v242, target=b42, fall=b41 } (exit_acc=v242) - block 41 start_pc=0 + terminator Bz { cond=v242, target=b26, fall=b25 } (exit_acc=v242) + block 25 start_pc=0 v243 Imm(21) -> x0 terminator Return(v243) (exit_acc=v243) - block 42 start_pc=0 + block 26 start_pc=0 v244 Imm(42) -> x0 terminator Return(v244) (exit_acc=v244) + block 27 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 28 start_pc=0 + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) + block 29 start_pc=0 + v19 Imm(3) -> x0 + terminator Return(v19) (exit_acc=v19) + block 30 start_pc=0 + v28 Imm(4) -> x0 + terminator Return(v28) (exit_acc=v28) + block 31 start_pc=0 + v36 Imm(5) -> x0 + terminator Return(v36) (exit_acc=v36) + block 32 start_pc=0 + v43 Imm(6) -> x0 + terminator Return(v43) (exit_acc=v43) + block 33 start_pc=0 + v50 Imm(7) -> x0 + terminator Return(v50) (exit_acc=v50) + block 34 start_pc=0 + v60 Imm(8) -> x0 + terminator Return(v60) (exit_acc=v60) + block 35 start_pc=0 + v86 Imm(11) -> x0 + terminator Return(v86) (exit_acc=v86) + block 36 start_pc=0 + v106 Imm(12) -> x0 + terminator Return(v106) (exit_acc=v106) + block 37 start_pc=0 + v121 Imm(13) -> x0 + terminator Return(v121) (exit_acc=v121) + block 38 start_pc=0 + v134 Imm(14) -> x0 + terminator Return(v134) (exit_acc=v134) + block 39 start_pc=0 + v142 Imm(15) -> x0 + terminator Return(v142) (exit_acc=v142) + block 40 start_pc=0 + v147 Imm(16) -> x0 + terminator Return(v147) (exit_acc=v147) + block 41 start_pc=0 + v160 Imm(17) -> x0 + terminator Return(v160) (exit_acc=v160) + block 42 start_pc=0 + v170 Imm(18) -> x0 + terminator Return(v170) (exit_acc=v170) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sieve_of_eratosthenes.ssa b/tests/snapshots/ssa/sieve_of_eratosthenes.ssa index 50e8bb52a..ad6bfadd8 100644 --- a/tests/snapshots/ssa/sieve_of_eratosthenes.ssa +++ b/tests/snapshots/ssa/sieve_of_eratosthenes.ssa @@ -6,106 +6,106 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v0 AllocaInit(0) -> - v1 Imm(2) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b7) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 Binop { op=mul, lhs=v4, rhs=v4 } -> x0 - v6 BinopI { op=lt, lhs=v5, rhs_imm=100000 } -> x0 - terminator Bz { cond=v6, target=b4, fall=b3 } (exit_acc=v6) + v10 ImmData(24) -> x2 + v11 Extend { value=v3, kind=I32 } -> x6 + v12 Binop { op=add, lhs=v10, rhs=v4 } -> x2 + v13 Load { addr=v12, disp=0, kind=I8 } -> x2 + v14 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x2 + terminator Bz { cond=v14, target=b6, fall=b2 } (exit_acc=v14) block 2 start_pc=0 - v7 Extend { value=v3, kind=I32 } -> x0 - v8 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v8) + v19 Extend { value=v3, kind=I32 } -> x2 + v20 Binop { op=mul, lhs=v3, rhs=v3 } -> x2 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x6 + v22 Extend { value=v20, kind=I32 } -> x6 + v23 Imm(0) -> x2 + terminator Jmp(b5) (exit_acc=v22) block 3 start_pc=0 - v10 ImmData(24) -> x0 - v11 Extend { value=v3, kind=I32 } -> x2 - v12 Binop { op=add, lhs=v10, rhs=v11 } -> x0 - v13 Load { addr=v12, disp=0, kind=I8 } -> x0 - v14 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) + v32 ImmData(24) -> x7 + v33 Extend { value=v24, kind=I32 } -> x8 + v34 Binop { op=add, lhs=v32, rhs=v25 } -> x2 + v35 Imm(1) -> x7 + v36 Store { addr=v34, disp=0, value=v35, kind=I8 } -> - + v37 Imm(72057594037927936) -> x2 + terminator Jmp(b4) (exit_acc=v37) block 4 start_pc=0 - v15 Imm(0) -> x2 - v16 Imm(0) -> x0 - v17 Imm(2) -> x1 - v18 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v17) + v27 Extend { value=v24, kind=I32 } -> x2 + v28 Extend { value=v3, kind=I32 } -> x2 + v29 Binop { op=add, lhs=v24, rhs=v3 } -> x6 + v30 Imm(0) -> x2 + v31 Extend { value=v29, kind=I32 } -> x2 + terminator Jmp(b5) (exit_acc=v31) block 5 start_pc=0 - v19 Extend { value=v3, kind=I32 } -> x0 - v20 Binop { op=mul, lhs=v3, rhs=v3 } -> x0 - v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x2 - v22 Extend { value=v20, kind=I32 } -> x2 - v23 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v22) + v24 Phi { incoming=[b2:v22, b4:v29], kind=I64 } -> x6 + v25 Extend { value=v24, kind=I32 } -> x2 + v26 BinopI { op=lt, lhs=v25, rhs_imm=100000 } -> x7 + terminator Bnz { cond=v26, target=b3, fall=b6 } (exit_acc=v26) block 6 start_pc=0 - terminator Jmp(b2) + v7 Extend { value=v3, kind=I32 } -> x1 + v8 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v8) block 7 start_pc=0 - v24 Phi { incoming=[b5:v22, b8:v29], kind=I64 } -> x2 - v25 Extend { value=v24, kind=I32 } -> x0 - v26 BinopI { op=lt, lhs=v25, rhs_imm=100000 } -> x0 - terminator Bz { cond=v26, target=b10, fall=b9 } (exit_acc=v26) + v3 Phi { incoming=[b0:v1, b6:v8], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 Binop { op=mul, lhs=v4, rhs=v4 } -> x2 + v6 BinopI { op=lt, lhs=v5, rhs_imm=100000 } -> x2 + terminator Bnz { cond=v6, target=b1, fall=b8 } (exit_acc=v6) block 8 start_pc=0 - v27 Extend { value=v24, kind=I32 } -> x0 - v28 Extend { value=v3, kind=I32 } -> x0 - v29 Binop { op=add, lhs=v24, rhs=v3 } -> x2 - v30 Imm(0) -> x0 - v31 Extend { value=v29, kind=I32 } -> x0 - terminator Jmp(b7) (exit_acc=v31) + v15 Imm(0) -> x2 + v16 Imm(0) -> x0 + v17 Imm(2) -> x1 + v18 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v17) block 9 start_pc=0 - v32 ImmData(24) -> x0 - v33 Extend { value=v24, kind=I32 } -> x6 - v34 Binop { op=add, lhs=v32, rhs=v33 } -> x0 - v35 Imm(1) -> x6 - v36 Store { addr=v34, disp=0, value=v35, kind=I8 } -> - - v37 Imm(72057594037927936) -> x0 - terminator Jmp(b8) (exit_acc=v37) + v45 ImmData(24) -> x6 + v46 Extend { value=v38, kind=I32 } -> x7 + v47 Binop { op=add, lhs=v45, rhs=v40 } -> x6 + v48 Load { addr=v47, disp=0, kind=I8 } -> x6 + v49 BinopI { op=eq, lhs=v48, rhs_imm=0 } -> x6 + terminator Bz { cond=v49, target=b12, fall=b10 } (exit_acc=v49) block 10 start_pc=0 - terminator Jmp(b6) + v52 Extend { value=v39, kind=I32 } -> x2 + v53 BinopI { op=add, lhs=v52, rhs_imm=1 } -> x2 + v54 Imm(0) -> x6 + terminator Jmp(b11) (exit_acc=v53) block 11 start_pc=0 - v38 Phi { incoming=[b4:v17, b12:v43], kind=I64 } -> x1 - v39 Phi { incoming=[b4:v15, b12:v55], kind=I64 } -> x2 - v40 Extend { value=v38, kind=I32 } -> x0 - v41 BinopI { op=lt, lhs=v40, rhs_imm=100000 } -> x0 - terminator Bz { cond=v41, target=b14, fall=b13 } (exit_acc=v41) + v55 Phi { incoming=[b12:v39, b10:v53], kind=I64 } -> x2 + terminator Jmp(b13) block 12 start_pc=0 - v42 Extend { value=v38, kind=I32 } -> x0 - v43 BinopI { op=add, lhs=v42, rhs_imm=1 } -> x1 - v44 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v43) + terminator Jmp(b11) block 13 start_pc=0 - v45 ImmData(24) -> x0 - v46 Extend { value=v38, kind=I32 } -> x6 - v47 Binop { op=add, lhs=v45, rhs=v46 } -> x0 - v48 Load { addr=v47, disp=0, kind=I8 } -> x0 - v49 BinopI { op=eq, lhs=v48, rhs_imm=0 } -> x0 - terminator Bz { cond=v49, target=b20, fall=b15 } (exit_acc=v49) + v42 Extend { value=v38, kind=I32 } -> x1 + v43 BinopI { op=add, lhs=v40, rhs_imm=1 } -> x1 + v44 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v43) block 14 start_pc=0 + v38 Phi { incoming=[b8:v17, b13:v43], kind=I64 } -> x1 + v39 Phi { incoming=[b8:v15, b13:v55], kind=I64 } -> x2 + v40 Extend { value=v38, kind=I32 } -> x0 + v41 BinopI { op=lt, lhs=v40, rhs_imm=100000 } -> x6 + terminator Bnz { cond=v41, target=b9, fall=b15 } (exit_acc=v41) + block 15 start_pc=0 v50 Extend { value=v39, kind=I32 } -> x0 v51 BinopI { op=eq, lhs=v50, rhs_imm=9592 } -> x0 - terminator Bz { cond=v51, target=b18, fall=b17 } (exit_acc=v51) - block 15 start_pc=0 - v52 Extend { value=v39, kind=I32 } -> x0 - v53 BinopI { op=add, lhs=v52, rhs_imm=1 } -> x2 - v54 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v53) + terminator Bz { cond=v51, target=b18, fall=b16 } (exit_acc=v51) block 16 start_pc=0 - v55 Phi { incoming=[b20:v39, b15:v53], kind=I64 } -> x2 - terminator Jmp(b12) - block 17 start_pc=0 v56 Imm(0) -> x1 v57 Imm(0) -> x0 - terminator Jmp(b19) (exit_acc=v56) + terminator Jmp(b17) (exit_acc=v56) + block 17 start_pc=0 + v60 Phi { incoming=[b16:v56, b18:v58], kind=I64 } -> x1 + v61 LoadLocal { off=-5, kind=I64 } -> x0 + terminator Return(v60) (exit_acc=v60) block 18 start_pc=0 v58 Imm(1) -> x1 v59 Imm(0) -> x0 - terminator Jmp(b19) (exit_acc=v58) + terminator Jmp(b17) (exit_acc=v58) block 19 start_pc=0 - v60 Phi { incoming=[b17:v56, b18:v58], kind=I64 } -> x1 - v61 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Return(v60) (exit_acc=v60) + terminator Jmp(b6) block 20 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/signal_nsig.ssa b/tests/snapshots/ssa/signal_nsig.ssa index ca2c84478..3a8675c16 100644 --- a/tests/snapshots/ssa/signal_nsig.ssa +++ b/tests/snapshots/ssa/signal_nsig.ssa @@ -5,17 +5,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=34 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(2) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(3) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 LocalAddr(-34) -> x0 v6 BinopI { op=add, lhs=v5, rhs_imm=264 } -> x0 v7 LocalAddr(-34) -> x1 @@ -23,13 +17,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=34 v9 Imm(260) -> x1 v10 Imm(1116691496960) -> x1 v11 BinopI { op=lt, lhs=v8, rhs_imm=260 } -> x0 - terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) - block 5 start_pc=0 + terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + block 3 start_pc=0 v12 Imm(5) -> x0 terminator Return(v12) (exit_acc=v12) - block 6 start_pc=0 + block 4 start_pc=0 v13 Imm(0) -> x0 terminator Return(v13) (exit_acc=v13) + block 5 start_pc=0 + v2 Imm(2) -> x0 + terminator Return(v2) (exit_acc=v2) + block 6 start_pc=0 + v4 Imm(3) -> x0 + terminator Return(v4) (exit_acc=v4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/signal_sig_t.ssa b/tests/snapshots/ssa/signal_sig_t.ssa index 5f10e297f..2ae719055 100644 --- a/tests/snapshots/ssa/signal_sig_t.ssa +++ b/tests/snapshots/ssa/signal_sig_t.ssa @@ -19,9 +19,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v1 ImmCode(ent_pc=0) -> x0 v2 Imm(0) -> x1 v3 Imm(0) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I64 } -> x2 - v6 ImmCode(ent_pc=0) -> x2 + v4 Imm(0) -> x1 + v5 LoadLocal { off=-1, kind=I64 } -> x1 + v6 ImmCode(ent_pc=0) -> x1 v7 Binop { op=ne, lhs=v1, rhs=v6 } -> x0 terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) block 1 start_pc=0 @@ -30,14 +30,14 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 block 2 start_pc=0 v9 LoadLocal { off=-2, kind=I64 } -> x0 v10 Imm(0) -> x0 - v11 BinopI { op=ne, lhs=v3, rhs_imm=0 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v11 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v11) block 3 start_pc=0 - v12 Imm(2) -> x0 - terminator Return(v12) (exit_acc=v12) - block 4 start_pc=0 v13 Imm(0) -> x0 terminator Return(v13) (exit_acc=v13) + block 4 start_pc=0 + v12 Imm(2) -> x0 + terminator Return(v12) (exit_acc=v12) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/signed_cast_extends.ssa b/tests/snapshots/ssa/signed_cast_extends.ssa index d52f1e28f..a277777f8 100644 --- a/tests/snapshots/ssa/signed_cast_extends.ssa +++ b/tests/snapshots/ssa/signed_cast_extends.ssa @@ -5,146 +5,113 @@ fn ent_pc=1 n_params=0 variadic=false locals=26 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(255) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U8 } -> x1 - v4 BinopI { op=shl, lhs=v1, rhs_imm=56 } -> x1 - v5 Extend { value=v1, kind=I8 } -> x0 - v6 Imm(0) -> x1 - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=ne, lhs=v7, rhs_imm=-1 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U8 } -> x0 + v4 Imm(-72057594037927936) -> x0 + v5 Imm(-1) -> x0 + v6 Imm(0) -> x0 + v7 Imm(-1) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 - v9 Imm(1) -> x0 - terminator Return(v9) (exit_acc=v9) - block 2 start_pc=0 v10 Imm(128) -> x0 - v11 Imm(0) -> x1 - v12 LoadLocal { off=-3, kind=U8 } -> x1 - v13 BinopI { op=shl, lhs=v10, rhs_imm=56 } -> x1 - v14 Extend { value=v10, kind=I8 } -> x0 - v15 Imm(0) -> x1 - v16 Extend { value=v14, kind=I32 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=-128 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) - block 3 start_pc=0 - v18 Imm(2) -> x0 - terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 + v11 Imm(0) -> x0 + v12 LoadLocal { off=-3, kind=U8 } -> x0 + v13 Imm(-9223372036854775808) -> x0 + v14 Imm(-128) -> x0 + v15 Imm(0) -> x0 + v16 Imm(-128) -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v17) + block 2 start_pc=0 v19 Imm(127) -> x0 - v20 Imm(0) -> x1 - v21 LoadLocal { off=-5, kind=U8 } -> x1 - v22 BinopI { op=shl, lhs=v19, rhs_imm=56 } -> x1 - v23 Extend { value=v19, kind=I8 } -> x0 - v24 Imm(0) -> x1 - v25 Extend { value=v23, kind=I32 } -> x0 - v26 BinopI { op=ne, lhs=v25, rhs_imm=127 } -> x0 - terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) - block 5 start_pc=0 - v27 Imm(3) -> x0 - terminator Return(v27) (exit_acc=v27) - block 6 start_pc=0 + v20 Imm(0) -> x0 + v21 LoadLocal { off=-5, kind=U8 } -> x0 + v22 Imm(9151314442816847872) -> x0 + v23 Imm(127) -> x0 + v24 Imm(0) -> x0 + v25 Imm(127) -> x0 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v26) + block 3 start_pc=0 v28 Imm(255) -> x0 - v29 Imm(0) -> x1 - v30 LoadLocal { off=-7, kind=U32 } -> x1 - v31 BinopI { op=shl, lhs=v28, rhs_imm=56 } -> x1 - v32 Extend { value=v28, kind=I8 } -> x0 - v33 Imm(0) -> x1 - v34 Extend { value=v32, kind=I32 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=-1 } -> x0 - terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) - block 7 start_pc=0 - v36 Imm(4) -> x0 - terminator Return(v36) (exit_acc=v36) - block 8 start_pc=0 + v29 Imm(0) -> x0 + v30 LoadLocal { off=-7, kind=U32 } -> x0 + v31 Imm(-72057594037927936) -> x0 + v32 Imm(-1) -> x0 + v33 Imm(0) -> x0 + v34 Imm(-1) -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v35) + block 4 start_pc=0 v37 Imm(305419896) -> x0 - v38 Imm(0) -> x1 - v39 LoadLocal { off=-9, kind=U32 } -> x1 - v40 BinopI { op=shl, lhs=v37, rhs_imm=56 } -> x1 - v41 Extend { value=v37, kind=I8 } -> x0 - v42 Imm(0) -> x1 - v43 Extend { value=v41, kind=I32 } -> x0 - v44 BinopI { op=ne, lhs=v43, rhs_imm=120 } -> x0 - terminator Bz { cond=v44, target=b10, fall=b9 } (exit_acc=v44) - block 9 start_pc=0 - v45 Imm(5) -> x0 - terminator Return(v45) (exit_acc=v45) - block 10 start_pc=0 + v38 Imm(0) -> x0 + v39 LoadLocal { off=-9, kind=U32 } -> x0 + v40 Imm(8646911284551352320) -> x0 + v41 Imm(120) -> x0 + v42 Imm(0) -> x0 + v43 Imm(120) -> x0 + v44 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v44) + block 5 start_pc=0 v46 Imm(305441791) -> x0 - v47 Imm(0) -> x1 - v48 LoadLocal { off=-11, kind=U32 } -> x1 - v49 BinopI { op=shl, lhs=v46, rhs_imm=56 } -> x1 - v50 Extend { value=v46, kind=I8 } -> x0 - v51 Imm(0) -> x1 - v52 Extend { value=v50, kind=I32 } -> x0 - v53 BinopI { op=ne, lhs=v52, rhs_imm=-1 } -> x0 - terminator Bz { cond=v53, target=b12, fall=b11 } (exit_acc=v53) - block 11 start_pc=0 - v54 Imm(6) -> x0 - terminator Return(v54) (exit_acc=v54) - block 12 start_pc=0 + v47 Imm(0) -> x0 + v48 LoadLocal { off=-11, kind=U32 } -> x0 + v49 Imm(-72057594037927936) -> x0 + v50 Imm(-1) -> x0 + v51 Imm(0) -> x0 + v52 Imm(-1) -> x0 + v53 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v53) + block 6 start_pc=0 v55 Imm(65535) -> x0 - v56 Imm(0) -> x1 - v57 LoadLocal { off=-13, kind=U16 } -> x1 - v58 BinopI { op=shl, lhs=v55, rhs_imm=48 } -> x1 - v59 Extend { value=v55, kind=I16 } -> x0 - v60 Imm(0) -> x1 - v61 Extend { value=v59, kind=I32 } -> x0 - v62 BinopI { op=ne, lhs=v61, rhs_imm=-1 } -> x0 - terminator Bz { cond=v62, target=b14, fall=b13 } (exit_acc=v62) - block 13 start_pc=0 - v63 Imm(7) -> x0 - terminator Return(v63) (exit_acc=v63) - block 14 start_pc=0 + v56 Imm(0) -> x0 + v57 LoadLocal { off=-13, kind=U16 } -> x0 + v58 Imm(-281474976710656) -> x0 + v59 Imm(-1) -> x0 + v60 Imm(0) -> x0 + v61 Imm(-1) -> x0 + v62 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v62) + block 7 start_pc=0 v64 Imm(32768) -> x0 - v65 Imm(0) -> x1 - v66 LoadLocal { off=-15, kind=U16 } -> x1 - v67 BinopI { op=shl, lhs=v64, rhs_imm=48 } -> x1 - v68 Extend { value=v64, kind=I16 } -> x0 - v69 Imm(0) -> x1 - v70 Extend { value=v68, kind=I32 } -> x0 - v71 BinopI { op=ne, lhs=v70, rhs_imm=-32768 } -> x0 - terminator Bz { cond=v71, target=b16, fall=b15 } (exit_acc=v71) - block 15 start_pc=0 - v72 Imm(8) -> x0 - terminator Return(v72) (exit_acc=v72) - block 16 start_pc=0 + v65 Imm(0) -> x0 + v66 LoadLocal { off=-15, kind=U16 } -> x0 + v67 Imm(-9223372036854775808) -> x0 + v68 Imm(-32768) -> x0 + v69 Imm(0) -> x0 + v70 Imm(-32768) -> x0 + v71 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v71) + block 8 start_pc=0 v73 Imm(305419896) -> x0 - v74 Imm(0) -> x1 - v75 LoadLocal { off=-17, kind=U32 } -> x1 - v76 BinopI { op=shl, lhs=v73, rhs_imm=48 } -> x1 - v77 Extend { value=v73, kind=I16 } -> x0 - v78 Imm(0) -> x1 - v79 Extend { value=v77, kind=I32 } -> x0 - v80 BinopI { op=ne, lhs=v79, rhs_imm=22136 } -> x0 - terminator Bz { cond=v80, target=b18, fall=b17 } (exit_acc=v80) - block 17 start_pc=0 - v81 Imm(9) -> x0 - terminator Return(v81) (exit_acc=v81) - block 18 start_pc=0 + v74 Imm(0) -> x0 + v75 LoadLocal { off=-17, kind=U32 } -> x0 + v76 Imm(6230730084467081216) -> x0 + v77 Imm(22136) -> x0 + v78 Imm(0) -> x0 + v79 Imm(22136) -> x0 + v80 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v80) + block 9 start_pc=0 v82 Imm(305463295) -> x0 - v83 Imm(0) -> x1 - v84 LoadLocal { off=-19, kind=U32 } -> x1 - v85 BinopI { op=shl, lhs=v82, rhs_imm=48 } -> x1 - v86 Extend { value=v82, kind=I16 } -> x0 - v87 Imm(0) -> x1 - v88 Extend { value=v86, kind=I32 } -> x0 - v89 BinopI { op=ne, lhs=v88, rhs_imm=-1 } -> x0 - terminator Bz { cond=v89, target=b20, fall=b19 } (exit_acc=v89) - block 19 start_pc=0 - v90 Imm(10) -> x0 - terminator Return(v90) (exit_acc=v90) - block 20 start_pc=0 + v83 Imm(0) -> x0 + v84 LoadLocal { off=-19, kind=U32 } -> x0 + v85 Imm(-281474976710656) -> x0 + v86 Imm(-1) -> x0 + v87 Imm(0) -> x0 + v88 Imm(-1) -> x0 + v89 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v89) + block 10 start_pc=0 v91 Imm(-42) -> x0 - v92 Imm(0) -> x1 - v93 LoadLocal { off=-21, kind=I8 } -> x1 - v94 Imm(0) -> x1 - v95 Extend { value=v91, kind=I32 } -> x0 - v96 BinopI { op=ne, lhs=v95, rhs_imm=-42 } -> x0 - terminator Bz { cond=v96, target=b22, fall=b21 } (exit_acc=v96) - block 21 start_pc=0 - v97 Imm(11) -> x0 - terminator Return(v97) (exit_acc=v97) - block 22 start_pc=0 + v92 Imm(0) -> x0 + v93 LoadLocal { off=-21, kind=I8 } -> x0 + v94 Imm(0) -> x0 + v95 Imm(-42) -> x0 + v96 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v96) + block 11 start_pc=0 v98 LocalAddr(-23) -> x0 v99 Imm(0) -> x1 v100 Imm(255) -> x1 @@ -166,11 +133,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=26 v116 Imm(0) -> x1 v117 Extend { value=v115, kind=I32 } -> x0 v118 BinopI { op=ne, lhs=v117, rhs_imm=-1 } -> x0 - terminator Bz { cond=v118, target=b24, fall=b23 } (exit_acc=v118) - block 23 start_pc=0 + terminator Bz { cond=v118, target=b13, fall=b12 } (exit_acc=v118) + block 12 start_pc=0 v119 Imm(12) -> x0 terminator Return(v119) (exit_acc=v119) - block 24 start_pc=0 + block 13 start_pc=0 v120 Imm(256) -> x0 v121 LocalAddr(-23) -> x0 v122 Imm(0) -> x1 @@ -189,15 +156,48 @@ fn ent_pc=1 n_params=0 variadic=false locals=26 v135 Extend { value=v133, kind=I32 } -> x0 v136 Imm(-190) -> x1 v137 BinopI { op=ne, lhs=v135, rhs_imm=-190 } -> x0 - terminator Bz { cond=v137, target=b26, fall=b25 } (exit_acc=v137) - block 25 start_pc=0 + terminator Bz { cond=v137, target=b15, fall=b14 } (exit_acc=v137) + block 14 start_pc=0 v138 Imm(13) -> x0 terminator Return(v138) (exit_acc=v138) - block 26 start_pc=0 + block 15 start_pc=0 v139 ImmData(36) -> x7 v140 CallExt { binding_idx=0, args=[v139], fp_arg_mask=0x0 } -> x0 v141 Imm(0) -> x0 terminator Return(v141) (exit_acc=v141) + block 16 start_pc=0 + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) + block 17 start_pc=0 + v18 Imm(2) -> x0 + terminator Return(v18) (exit_acc=v18) + block 18 start_pc=0 + v27 Imm(3) -> x0 + terminator Return(v27) (exit_acc=v27) + block 19 start_pc=0 + v36 Imm(4) -> x0 + terminator Return(v36) (exit_acc=v36) + block 20 start_pc=0 + v45 Imm(5) -> x0 + terminator Return(v45) (exit_acc=v45) + block 21 start_pc=0 + v54 Imm(6) -> x0 + terminator Return(v54) (exit_acc=v54) + block 22 start_pc=0 + v63 Imm(7) -> x0 + terminator Return(v63) (exit_acc=v63) + block 23 start_pc=0 + v72 Imm(8) -> x0 + terminator Return(v72) (exit_acc=v72) + block 24 start_pc=0 + v81 Imm(9) -> x0 + terminator Return(v81) (exit_acc=v81) + block 25 start_pc=0 + v90 Imm(10) -> x0 + terminator Return(v90) (exit_acc=v90) + block 26 start_pc=0 + v97 Imm(11) -> x0 + terminator Return(v97) (exit_acc=v97) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/size_t_is_unsigned.ssa b/tests/snapshots/ssa/size_t_is_unsigned.ssa index a3956b6fb..e10c3a8d9 100644 --- a/tests/snapshots/ssa/size_t_is_unsigned.ssa +++ b/tests/snapshots/ssa/size_t_is_unsigned.ssa @@ -6,66 +6,66 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 v2 Imm(-1) -> x0 - v3 Imm(0) -> x1 - v4 LoadLocal { off=-1, kind=I64 } -> x1 - v5 Imm(9) -> x1 - v6 Binop { op=divu, lhs=v2, rhs=v5 } -> x1 - v7 BinopI { op=eq, lhs=v6, rhs_imm=0 } -> x1 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v3 Imm(0) -> x0 + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 Imm(9) -> x0 + v6 Imm(2049638230412172401) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(9) -> x0 + v11 Imm(2049638230412172401) -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v9 LoadLocal { off=-1, kind=I64 } -> x1 - v10 Imm(9) -> x1 - v11 Binop { op=divu, lhs=v2, rhs=v10 } -> x1 - v12 BinopI { op=ne, lhs=v11, rhs_imm=2049638230412172401 } -> x1 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v14 LoadLocal { off=-1, kind=I64 } -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) block 3 start_pc=0 - v13 Imm(2) -> x0 - terminator Return(v13) (exit_acc=v13) + v17 Imm(2147483648) -> x0 + v18 Imm(0) -> x1 + v19 LoadLocal { off=-1, kind=I64 } -> x1 + v20 Imm(5) -> x1 + v21 Imm(21474836480) -> x1 + v22 Imm(3689348814741910323) -> x1 + v23 Imm(0) -> x1 + v24 LoadLocal { off=-2, kind=U32 } -> x1 + v25 LoadLocal { off=-3, kind=I64 } -> x1 + v26 Imm(1) -> x1 + terminator Jmp(b4) (exit_acc=v26) block 4 start_pc=0 - v14 LoadLocal { off=-1, kind=I64 } -> x1 - v15 BinopI { op=ult, lhs=v2, rhs_imm=1000 } -> x1 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) + v27 LoadLocal { off=-2, kind=U32 } -> x1 + v28 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v17) block 5 start_pc=0 - v16 Imm(3) -> x0 - terminator Return(v16) (exit_acc=v16) - block 6 start_pc=0 - v17 Imm(2147483648) -> x1 - v18 Imm(0) -> x2 - v19 LoadLocal { off=-1, kind=I64 } -> x2 - v20 Imm(5) -> x2 - v21 Imm(21474836480) -> x6 - v22 Binop { op=divu, lhs=v2, rhs=v20 } -> x0 - v23 Imm(0) -> x2 - v24 LoadLocal { off=-2, kind=U32 } -> x2 - v25 LoadLocal { off=-3, kind=I64 } -> x2 - v26 Binop { op=ult, lhs=v17, rhs=v22 } -> x2 - terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) - block 7 start_pc=0 - v27 LoadLocal { off=-2, kind=U32 } -> x0 - v28 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v17) - block 8 start_pc=0 - v29 LoadLocal { off=-3, kind=I64 } -> x2 - v30 BinopI { op=and, lhs=v22, rhs_imm=4294967295 } -> x2 - v31 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v30) - block 9 start_pc=0 - v32 Phi { incoming=[b7:v17, b8:v30], kind=I64 } -> x2 - v33 LoadLocal { off=-5, kind=I64 } -> x0 - v34 Imm(0) -> x0 - v35 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x0 + v32 Phi { incoming=[b4:v17, b11:v30], kind=I64 } -> x2 + v33 LoadLocal { off=-5, kind=I64 } -> x1 + v34 Imm(0) -> x1 + v35 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x1 v36 LoadLocal { off=-2, kind=U32 } -> x2 v37 Binop { op=ne, lhs=v35, rhs=v17 } -> x0 - terminator Bz { cond=v37, target=b11, fall=b10 } (exit_acc=v37) - block 10 start_pc=0 + terminator Bz { cond=v37, target=b7, fall=b6 } (exit_acc=v37) + block 6 start_pc=0 v38 Imm(4) -> x0 terminator Return(v38) (exit_acc=v38) - block 11 start_pc=0 + block 7 start_pc=0 v39 Imm(0) -> x0 terminator Return(v39) (exit_acc=v39) + block 8 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) + block 9 start_pc=0 + v13 Imm(2) -> x0 + terminator Return(v13) (exit_acc=v13) + block 10 start_pc=0 + v16 Imm(3) -> x0 + terminator Return(v16) (exit_acc=v16) + block 11 start_pc=0 + v29 LoadLocal { off=-3, kind=I64 } -> x1 + v30 Imm(858993459) -> x2 + v31 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v30) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_abstract_fn_ptr.ssa b/tests/snapshots/ssa/sizeof_abstract_fn_ptr.ssa index cbb1be560..ac99ec0f1 100644 --- a/tests/snapshots/ssa/sizeof_abstract_fn_ptr.ssa +++ b/tests/snapshots/ssa/sizeof_abstract_fn_ptr.ssa @@ -6,69 +6,69 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v17 Imm(20) -> x0 + v18 Imm(85899345920) -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v19) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v21 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v21) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v23 Imm(0) -> x0 + terminator Return(v23) (exit_acc=v23) block 11 start_pc=0 - v12 Imm(6) -> x0 - terminator Return(v12) (exit_acc=v12) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 12 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v13) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 13 start_pc=0 - v14 Imm(7) -> x0 - terminator Return(v14) (exit_acc=v14) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 14 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v15) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 15 start_pc=0 - v16 Imm(8) -> x0 - terminator Return(v16) (exit_acc=v16) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 16 start_pc=0 - v17 Imm(20) -> x0 - v18 Imm(85899345920) -> x0 - v19 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v19) + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) block 17 start_pc=0 - v20 Imm(9) -> x0 - terminator Return(v20) (exit_acc=v20) + v14 Imm(7) -> x0 + terminator Return(v14) (exit_acc=v14) block 18 start_pc=0 - v21 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v21) + v16 Imm(8) -> x0 + terminator Return(v16) (exit_acc=v16) block 19 start_pc=0 + v20 Imm(9) -> x0 + terminator Return(v20) (exit_acc=v20) + block 20 start_pc=0 v22 Imm(10) -> x0 terminator Return(v22) (exit_acc=v22) - block 20 start_pc=0 - v23 Imm(0) -> x0 - terminator Return(v23) (exit_acc=v23) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_array_type_and_binding.ssa b/tests/snapshots/ssa/sizeof_array_type_and_binding.ssa index a46451e93..d505d54ad 100644 --- a/tests/snapshots/ssa/sizeof_array_type_and_binding.ssa +++ b/tests/snapshots/ssa/sizeof_array_type_and_binding.ssa @@ -7,41 +7,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 v1 Imm(8) -> x0 v2 Imm(34359738368) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(24) -> x0 v6 Imm(103079215104) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(2) -> x0 - terminator Return(v8) (exit_acc=v8) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 v9 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v9) - block 5 start_pc=0 - v10 Imm(3) -> x0 - terminator Return(v10) (exit_acc=v10) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v9) + block 3 start_pc=0 v11 Imm(512) -> x0 v12 Imm(2199023255552) -> x0 v13 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v13) + terminator Jmp(b4) (exit_acc=v13) + block 4 start_pc=0 + v15 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v15) + block 5 start_pc=0 + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) + block 6 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 7 start_pc=0 - v14 Imm(4) -> x0 - terminator Return(v14) (exit_acc=v14) + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) block 8 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v15) + v10 Imm(3) -> x0 + terminator Return(v10) (exit_acc=v10) block 9 start_pc=0 + v14 Imm(4) -> x0 + terminator Return(v14) (exit_acc=v14) + block 10 start_pc=0 v16 Imm(5) -> x0 terminator Return(v16) (exit_acc=v16) - block 10 start_pc=0 - v17 Imm(0) -> x0 - terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_basic.ssa b/tests/snapshots/ssa/sizeof_basic.ssa index f68afa29a..56384d7fe 100644 --- a/tests/snapshots/ssa/sizeof_basic.ssa +++ b/tests/snapshots/ssa/sizeof_basic.ssa @@ -5,49 +5,49 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v15 Imm(0) -> x0 + terminator Return(v15) (exit_acc=v15) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 11 start_pc=0 - v12 Imm(6) -> x0 - terminator Return(v12) (exit_acc=v12) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 12 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v13) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 13 start_pc=0 + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) + block 14 start_pc=0 v14 Imm(7) -> x0 terminator Return(v14) (exit_acc=v14) - block 14 start_pc=0 - v15 Imm(0) -> x0 - terminator Return(v15) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_deref_array_clears_decay.ssa b/tests/snapshots/ssa/sizeof_deref_array_clears_decay.ssa index b337490d9..943e5d9c9 100644 --- a/tests/snapshots/ssa/sizeof_deref_array_clears_decay.ssa +++ b/tests/snapshots/ssa/sizeof_deref_array_clears_decay.ssa @@ -7,31 +7,31 @@ fn ent_pc=1 n_params=0 variadic=false locals=0 v1 Imm(184) -> x0 v2 Imm(790273982464) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(8) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) + block 2 start_pc=0 + v8 Imm(184) -> x0 + v9 Imm(8) -> x0 + v10 Imm(0) -> x0 + v11 Imm(184) -> x0 + v12 Imm(23) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v7 Imm(2) -> x0 - terminator Return(v7) (exit_acc=v7) + v15 Imm(0) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v8 Imm(184) -> x0 - v9 Imm(8) -> x1 - v10 Imm(0) -> x1 - v11 Binop { op=add, lhs=v8, rhs=v10 } -> x0 - v12 BinopI { op=shr, lhs=v11, rhs_imm=3 } -> x0 - v13 BinopI { op=ne, lhs=v12, rhs_imm=23 } -> x0 - terminator Bz { cond=v13, target=b6, fall=b5 } (exit_acc=v13) + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 5 start_pc=0 + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) + block 6 start_pc=0 v14 Imm(3) -> x0 terminator Return(v14) (exit_acc=v14) - block 6 start_pc=0 - v15 Imm(0) -> x0 - terminator Return(v15) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_expr.ssa b/tests/snapshots/ssa/sizeof_expr.ssa index 309f968a6..9498cfd9b 100644 --- a/tests/snapshots/ssa/sizeof_expr.ssa +++ b/tests/snapshots/ssa/sizeof_expr.ssa @@ -8,61 +8,61 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v17 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v17) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 11 start_pc=0 - v12 Imm(6) -> x0 - terminator Return(v12) (exit_acc=v12) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 12 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v13) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 13 start_pc=0 - v14 Imm(7) -> x0 - terminator Return(v14) (exit_acc=v14) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 14 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v15) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 15 start_pc=0 - v16 Imm(8) -> x0 - terminator Return(v16) (exit_acc=v16) + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) block 16 start_pc=0 - v17 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v17) + v14 Imm(7) -> x0 + terminator Return(v14) (exit_acc=v14) block 17 start_pc=0 + v16 Imm(8) -> x0 + terminator Return(v16) (exit_acc=v16) + block 18 start_pc=0 v18 Imm(9) -> x0 terminator Return(v18) (exit_acc=v18) - block 18 start_pc=0 - v19 Imm(0) -> x0 - terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_function_call_truncation.ssa b/tests/snapshots/ssa/sizeof_function_call_truncation.ssa index 52e18e886..2ad5f2337 100644 --- a/tests/snapshots/ssa/sizeof_function_call_truncation.ssa +++ b/tests/snapshots/ssa/sizeof_function_call_truncation.ssa @@ -33,82 +33,82 @@ fn ent_pc=4 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4660) -> x0 - v2 Extend { value=v1, kind=I32 } -> x0 - v3 Imm(0) -> x1 - v4 Imm(4) -> x1 - v5 BinopI { op=and, lhs=v2, rhs_imm=255 } -> x1 - v6 Imm(0) -> x2 - v7 BinopI { op=shr, lhs=v2, rhs_imm=8 } -> x0 - v8 BinopI { op=and, lhs=v7, rhs_imm=255 } -> x0 - v9 Imm(0) -> x2 - v10 Extend { value=v5, kind=I32 } -> x2 - v11 Extend { value=v8, kind=I32 } -> x2 - v12 Binop { op=add, lhs=v5, rhs=v8 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 Imm(0) -> x1 - v16 BinopI { op=shl, lhs=v12, rhs_imm=1 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 - v18 Extend { value=v16, kind=I32 } -> x0 - v19 Imm(0) -> x1 - v20 BinopI { op=ne, lhs=v18, rhs_imm=140 } -> x0 - terminator Bz { cond=v20, target=b2, fall=b1 } (exit_acc=v20) + v2 Imm(4660) -> x0 + v3 Imm(0) -> x0 + v4 Imm(4) -> x0 + v5 Imm(52) -> x0 + v6 Imm(0) -> x0 + v7 Imm(18) -> x0 + v8 Imm(18) -> x0 + v9 Imm(0) -> x0 + v10 Imm(52) -> x0 + v11 Imm(18) -> x0 + v12 Imm(70) -> x0 + v13 Imm(300647710720) -> x0 + v14 Imm(70) -> x0 + v15 Imm(0) -> x0 + v16 Imm(140) -> x0 + v17 Imm(601295421440) -> x0 + v18 Imm(140) -> x0 + v19 Imm(0) -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v20) block 1 start_pc=0 - v21 Imm(1) -> x0 - terminator Return(v21) (exit_acc=v21) - block 2 start_pc=0 v22 Imm(0) -> x0 - v23 Extend { value=v22, kind=I32 } -> x0 - v24 Imm(0) -> x1 - v25 Imm(4) -> x1 - v26 BinopI { op=and, lhs=v23, rhs_imm=255 } -> x1 - v27 Imm(0) -> x2 - v28 BinopI { op=shr, lhs=v23, rhs_imm=8 } -> x0 - v29 BinopI { op=and, lhs=v28, rhs_imm=255 } -> x0 - v30 Imm(0) -> x2 - v31 Extend { value=v26, kind=I32 } -> x2 - v32 Extend { value=v29, kind=I32 } -> x2 - v33 Binop { op=add, lhs=v26, rhs=v29 } -> x0 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x1 - v35 Extend { value=v33, kind=I32 } -> x1 - v36 Imm(0) -> x1 - v37 BinopI { op=shl, lhs=v33, rhs_imm=1 } -> x0 - v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x1 - v39 Extend { value=v37, kind=I32 } -> x0 - v40 Imm(0) -> x1 - v41 BinopI { op=ne, lhs=v39, rhs_imm=0 } -> x0 - terminator Bz { cond=v41, target=b4, fall=b3 } (exit_acc=v41) + v23 Imm(0) -> x0 + v24 Imm(0) -> x0 + v25 Imm(4) -> x0 + v26 Imm(0) -> x0 + v27 Imm(0) -> x0 + v28 Imm(0) -> x0 + v29 Imm(0) -> x0 + v30 Imm(0) -> x0 + v31 Imm(0) -> x0 + v32 Imm(0) -> x0 + v33 Imm(0) -> x0 + v34 Imm(0) -> x0 + v35 Imm(0) -> x0 + v36 Imm(0) -> x0 + v37 Imm(0) -> x0 + v38 Imm(0) -> x0 + v39 Imm(0) -> x0 + v40 Imm(0) -> x0 + v41 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v41) + block 2 start_pc=0 + v43 Imm(65280) -> x0 + v44 Imm(65280) -> x0 + v45 Imm(0) -> x0 + v46 Imm(4) -> x0 + v47 Imm(0) -> x0 + v48 Imm(0) -> x0 + v49 Imm(255) -> x0 + v50 Imm(255) -> x0 + v51 Imm(0) -> x0 + v52 Imm(0) -> x0 + v53 Imm(255) -> x0 + v54 Imm(255) -> x0 + v55 Imm(1095216660480) -> x0 + v56 Imm(255) -> x0 + v57 Imm(0) -> x0 + v58 Imm(510) -> x0 + v59 Imm(2190433320960) -> x0 + v60 Imm(510) -> x0 + v61 Imm(0) -> x0 + v62 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v62) block 3 start_pc=0 - v42 Imm(2) -> x0 - terminator Return(v42) (exit_acc=v42) + v64 Imm(0) -> x0 + terminator Return(v64) (exit_acc=v64) block 4 start_pc=0 - v43 Imm(65280) -> x0 - v44 Extend { value=v43, kind=I32 } -> x0 - v45 Imm(0) -> x1 - v46 Imm(4) -> x1 - v47 BinopI { op=and, lhs=v44, rhs_imm=255 } -> x1 - v48 Imm(0) -> x2 - v49 BinopI { op=shr, lhs=v44, rhs_imm=8 } -> x0 - v50 BinopI { op=and, lhs=v49, rhs_imm=255 } -> x0 - v51 Imm(0) -> x2 - v52 Extend { value=v47, kind=I32 } -> x2 - v53 Extend { value=v50, kind=I32 } -> x2 - v54 Binop { op=add, lhs=v47, rhs=v50 } -> x0 - v55 BinopI { op=shl, lhs=v54, rhs_imm=32 } -> x1 - v56 Extend { value=v54, kind=I32 } -> x1 - v57 Imm(0) -> x1 - v58 BinopI { op=shl, lhs=v54, rhs_imm=1 } -> x0 - v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x1 - v60 Extend { value=v58, kind=I32 } -> x0 - v61 Imm(0) -> x1 - v62 BinopI { op=ne, lhs=v60, rhs_imm=510 } -> x0 - terminator Bz { cond=v62, target=b6, fall=b5 } (exit_acc=v62) + v21 Imm(1) -> x0 + terminator Return(v21) (exit_acc=v21) block 5 start_pc=0 + v42 Imm(2) -> x0 + terminator Return(v42) (exit_acc=v42) + block 6 start_pc=0 v63 Imm(3) -> x0 terminator Return(v63) (exit_acc=v63) - block 6 start_pc=0 - v64 Imm(0) -> x0 - terminator Return(v64) (exit_acc=v64) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_member_via_null_cast.ssa b/tests/snapshots/ssa/sizeof_member_via_null_cast.ssa index a910b4363..222d5d3df 100644 --- a/tests/snapshots/ssa/sizeof_member_via_null_cast.ssa +++ b/tests/snapshots/ssa/sizeof_member_via_null_cast.ssa @@ -5,50 +5,50 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(11) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(12) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(13) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + v12 Imm(4) -> x1 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v14 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v14) block 7 start_pc=0 - v8 Imm(14) -> x0 - terminator Return(v8) (exit_acc=v8) + v16 Imm(0) -> x0 + terminator Return(v16) (exit_acc=v16) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v2 Imm(11) -> x0 + terminator Return(v2) (exit_acc=v2) block 9 start_pc=0 - v10 Imm(15) -> x0 - terminator Return(v10) (exit_acc=v10) + v4 Imm(12) -> x0 + terminator Return(v4) (exit_acc=v4) block 10 start_pc=0 - v11 Imm(0) -> x0 - v12 Imm(4) -> x1 - terminator Jmp(b12) (exit_acc=v11) + v6 Imm(13) -> x0 + terminator Return(v6) (exit_acc=v6) block 11 start_pc=0 - v13 Imm(16) -> x0 - terminator Return(v13) (exit_acc=v13) + v8 Imm(14) -> x0 + terminator Return(v8) (exit_acc=v8) block 12 start_pc=0 - v14 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v14) + v10 Imm(15) -> x0 + terminator Return(v10) (exit_acc=v10) block 13 start_pc=0 + v13 Imm(16) -> x0 + terminator Return(v13) (exit_acc=v13) + block 14 start_pc=0 v15 Imm(17) -> x0 terminator Return(v15) (exit_acc=v15) - block 14 start_pc=0 - v16 Imm(0) -> x0 - terminator Return(v16) (exit_acc=v16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_pointer_to_array_subscript.ssa b/tests/snapshots/ssa/sizeof_pointer_to_array_subscript.ssa index 25b31b1b8..bf79ef8c2 100644 --- a/tests/snapshots/ssa/sizeof_pointer_to_array_subscript.ssa +++ b/tests/snapshots/ssa/sizeof_pointer_to_array_subscript.ssa @@ -2,7 +2,7 @@ sizeof_pointer_to_array_subscript.c:83: warning: unused function `check_local` ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=17 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-14) -> x0 @@ -170,563 +170,865 @@ fn ent_pc=1 n_params=0 variadic=false locals=17 v129 Imm(19) -> x0 terminator Return(v129) (exit_acc=v129) block 18 start_pc=0 - v130 Imm(0) -> x1 - v131 Imm(0) -> x0 + v130 Imm(0) -> x0 + v131 Imm(0) -> x1 terminator Jmp(b19) (exit_acc=v130) block 19 start_pc=0 - v132 Phi { incoming=[b18:v130, b20:v136], kind=I64 } -> x1 - v133 Extend { value=v132, kind=I32 } -> x0 - v134 BinopI { op=lt, lhs=v133, rhs_imm=8 } -> x0 - terminator Bz { cond=v134, target=b22, fall=b21 } (exit_acc=v134) + v132 Imm(0) -> x0 + v133 Imm(1) -> x0 + v134 LocalAddr(-14) -> x0 + v135 BinopI { op=add, lhs=v134, rhs_imm=8 } -> x1 + v136 Load { addr=v134, disp=8, kind=I64 } -> x0 + v137 Imm(0) -> x1 + v138 Imm(0) -> x1 + v139 Imm(0) -> x1 + v140 BinopI { op=add, lhs=v136, rhs_imm=0 } -> x0 + v141 Imm(1000) -> x1 + v142 Imm(1000) -> x1 + v143 Imm(4294967296000) -> x1 + v144 Imm(1000) -> x1 + v145 Imm(281474976710656000) -> x1 + v146 Imm(1000) -> x1 + v147 Store { addr=v140, disp=0, value=v146, kind=I16 } -> - + v148 Imm(0) -> x0 + v149 Imm(1) -> x0 + v150 Imm(0) -> x0 + v151 Imm(1) -> x0 + v152 Imm(1) -> x0 + v153 LocalAddr(-14) -> x0 + v154 BinopI { op=add, lhs=v153, rhs_imm=8 } -> x1 + v155 Load { addr=v153, disp=8, kind=I64 } -> x0 + v156 Imm(0) -> x1 + v157 Imm(1) -> x1 + v158 Imm(2) -> x1 + v159 BinopI { op=add, lhs=v155, rhs_imm=2 } -> x1 + v160 Imm(1000) -> x1 + v161 Imm(1001) -> x1 + v162 Imm(4299262263296) -> x1 + v163 Imm(1001) -> x1 + v164 Imm(281756451687366656) -> x1 + v165 Imm(1001) -> x1 + v166 Store { addr=v155, disp=2, value=v165, kind=I16 } -> - + v167 Imm(1) -> x0 + v168 Imm(2) -> x0 + v169 Imm(0) -> x0 + v170 Imm(2) -> x0 + v171 Imm(1) -> x0 + v172 LocalAddr(-14) -> x0 + v173 BinopI { op=add, lhs=v172, rhs_imm=8 } -> x1 + v174 Load { addr=v172, disp=8, kind=I64 } -> x0 + v175 Imm(0) -> x1 + v176 Imm(2) -> x1 + v177 Imm(4) -> x1 + v178 BinopI { op=add, lhs=v174, rhs_imm=4 } -> x1 + v179 Imm(1000) -> x1 + v180 Imm(1002) -> x1 + v181 Imm(4303557230592) -> x1 + v182 Imm(1002) -> x1 + v183 Imm(282037926664077312) -> x1 + v184 Imm(1002) -> x1 + v185 Store { addr=v174, disp=4, value=v184, kind=I16 } -> - + v186 Imm(2) -> x0 + v187 Imm(3) -> x0 + v188 Imm(0) -> x0 + v189 Imm(3) -> x0 + v190 Imm(1) -> x0 + v191 LocalAddr(-14) -> x0 + v192 BinopI { op=add, lhs=v191, rhs_imm=8 } -> x1 + v193 Load { addr=v191, disp=8, kind=I64 } -> x0 + v194 Imm(0) -> x1 + v195 Imm(3) -> x1 + v196 Imm(6) -> x1 + v197 BinopI { op=add, lhs=v193, rhs_imm=6 } -> x1 + v198 Imm(1000) -> x1 + v199 Imm(1003) -> x1 + v200 Imm(4307852197888) -> x1 + v201 Imm(1003) -> x1 + v202 Imm(282319401640787968) -> x1 + v203 Imm(1003) -> x1 + v204 Store { addr=v193, disp=6, value=v203, kind=I16 } -> - + v205 Imm(3) -> x0 + v206 Imm(4) -> x0 + v207 Imm(0) -> x0 + v208 Imm(4) -> x0 + v209 Imm(1) -> x0 + v210 LocalAddr(-14) -> x0 + v211 BinopI { op=add, lhs=v210, rhs_imm=8 } -> x1 + v212 Load { addr=v210, disp=8, kind=I64 } -> x0 + v213 Imm(0) -> x1 + v214 Imm(4) -> x1 + v215 Imm(8) -> x1 + v216 BinopI { op=add, lhs=v212, rhs_imm=8 } -> x1 + v217 Imm(1000) -> x1 + v218 Imm(1004) -> x1 + v219 Imm(4312147165184) -> x1 + v220 Imm(1004) -> x1 + v221 Imm(282600876617498624) -> x1 + v222 Imm(1004) -> x1 + v223 Store { addr=v212, disp=8, value=v222, kind=I16 } -> - + v224 Imm(4) -> x0 + v225 Imm(5) -> x0 + v226 Imm(0) -> x0 + v227 Imm(5) -> x0 + v228 Imm(1) -> x0 + v229 LocalAddr(-14) -> x0 + v230 BinopI { op=add, lhs=v229, rhs_imm=8 } -> x1 + v231 Load { addr=v229, disp=8, kind=I64 } -> x0 + v232 Imm(0) -> x1 + v233 Imm(5) -> x1 + v234 Imm(10) -> x1 + v235 BinopI { op=add, lhs=v231, rhs_imm=10 } -> x1 + v236 Imm(1000) -> x1 + v237 Imm(1005) -> x1 + v238 Imm(4316442132480) -> x1 + v239 Imm(1005) -> x1 + v240 Imm(282882351594209280) -> x1 + v241 Imm(1005) -> x1 + v242 Store { addr=v231, disp=10, value=v241, kind=I16 } -> - + v243 Imm(5) -> x0 + v244 Imm(6) -> x0 + v245 Imm(0) -> x0 + v246 Imm(6) -> x0 + v247 Imm(1) -> x0 + v248 LocalAddr(-14) -> x0 + v249 BinopI { op=add, lhs=v248, rhs_imm=8 } -> x1 + v250 Load { addr=v248, disp=8, kind=I64 } -> x0 + v251 Imm(0) -> x1 + v252 Imm(6) -> x1 + v253 Imm(12) -> x1 + v254 BinopI { op=add, lhs=v250, rhs_imm=12 } -> x1 + v255 Imm(1000) -> x1 + v256 Imm(1006) -> x1 + v257 Imm(4320737099776) -> x1 + v258 Imm(1006) -> x1 + v259 Imm(283163826570919936) -> x1 + v260 Imm(1006) -> x1 + v261 Store { addr=v250, disp=12, value=v260, kind=I16 } -> - + v262 Imm(6) -> x0 + v263 Imm(7) -> x0 + v264 Imm(0) -> x0 + v265 Imm(7) -> x0 + v266 Imm(1) -> x0 + v267 LocalAddr(-14) -> x0 + v268 BinopI { op=add, lhs=v267, rhs_imm=8 } -> x1 + v269 Load { addr=v267, disp=8, kind=I64 } -> x0 + v270 Imm(0) -> x1 + v271 Imm(7) -> x1 + v272 Imm(14) -> x1 + v273 BinopI { op=add, lhs=v269, rhs_imm=14 } -> x1 + v274 Imm(1000) -> x1 + v275 Imm(1007) -> x1 + v276 Imm(4325032067072) -> x1 + v277 Imm(1007) -> x1 + v278 Imm(283445301547630592) -> x1 + v279 Imm(1007) -> x1 + v280 Store { addr=v269, disp=14, value=v279, kind=I16 } -> - + v281 Imm(7) -> x0 + v282 Imm(8) -> x0 + v283 Imm(0) -> x0 + v284 Imm(8) -> x0 + v285 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v285) block 20 start_pc=0 - v135 Extend { value=v132, kind=I32 } -> x0 - v136 BinopI { op=add, lhs=v135, rhs_imm=1 } -> x1 - v137 Imm(0) -> x0 - terminator Jmp(b19) (exit_acc=v136) + v286 Imm(0) -> x1 + v287 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v286) block 21 start_pc=0 - v138 LocalAddr(-14) -> x0 - v139 BinopI { op=add, lhs=v138, rhs_imm=8 } -> x2 - v140 Load { addr=v138, disp=8, kind=I64 } -> x0 - v141 Imm(0) -> x2 - v142 Extend { value=v132, kind=I32 } -> x2 - v143 BinopI { op=shl, lhs=v142, rhs_imm=1 } -> x6 - v144 Binop { op=add, lhs=v140, rhs=v143 } -> x6 - v145 Imm(1000) -> x6 - v146 BinopI { op=add, lhs=v142, rhs_imm=1000 } -> x6 - v147 BinopI { op=shl, lhs=v146, rhs_imm=32 } -> x7 - v148 Extend { value=v146, kind=I32 } -> x7 - v149 BinopI { op=shl, lhs=v146, rhs_imm=48 } -> x6 - v150 Extend { value=v148, kind=I16 } -> x6 - v151 StoreIndexed { base=v140, index=v142, scale=2, value=v148, kind=I16 } -> - - terminator Jmp(b20) (exit_acc=v151) + v294 LocalAddr(-14) -> x2 + v295 BinopI { op=add, lhs=v294, rhs_imm=8 } -> x6 + v296 Load { addr=v294, disp=8, kind=I64 } -> x2 + v297 Imm(0) -> x6 + v298 Extend { value=v288, kind=I32 } -> x6 + v299 BinopI { op=shl, lhs=v289, rhs_imm=1 } -> x6 + v300 Binop { op=add, lhs=v296, rhs=v299 } -> x6 + v301 LoadIndexed { base=v296, index=v289, scale=2, kind=I16 } -> x2 + v302 Imm(1000) -> x6 + v303 BinopI { op=add, lhs=v289, rhs_imm=1000 } -> x6 + v304 BinopI { op=shl, lhs=v303, rhs_imm=32 } -> x7 + v305 Extend { value=v303, kind=I32 } -> x7 + v306 BinopI { op=shl, lhs=v303, rhs_imm=48 } -> x6 + v307 Extend { value=v305, kind=I16 } -> x6 + v308 Binop { op=ne, lhs=v301, rhs=v307 } -> x2 + terminator Bnz { cond=v308, target=b81, fall=b22 } (exit_acc=v308) block 22 start_pc=0 - v152 Imm(0) -> x1 - v153 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v152) + v291 Extend { value=v288, kind=I32 } -> x1 + v292 BinopI { op=add, lhs=v289, rhs_imm=1 } -> x1 + v293 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v292) block 23 start_pc=0 - v154 Phi { incoming=[b22:v152, b24:v158], kind=I64 } -> x1 - v155 Extend { value=v154, kind=I32 } -> x0 - v156 BinopI { op=lt, lhs=v155, rhs_imm=8 } -> x0 - terminator Bz { cond=v156, target=b26, fall=b25 } (exit_acc=v156) + v288 Phi { incoming=[b20:v286, b22:v292], kind=I64 } -> x1 + v289 Extend { value=v288, kind=I32 } -> x0 + v290 BinopI { op=lt, lhs=v289, rhs_imm=8 } -> x2 + terminator Bnz { cond=v290, target=b21, fall=b24 } (exit_acc=v290) block 24 start_pc=0 - v157 Extend { value=v154, kind=I32 } -> x0 - v158 BinopI { op=add, lhs=v157, rhs_imm=1 } -> x1 - v159 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v158) + v309 Imm(0) -> x1 + v310 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v309) block 25 start_pc=0 - v160 LocalAddr(-14) -> x0 - v161 BinopI { op=add, lhs=v160, rhs_imm=8 } -> x2 - v162 Load { addr=v160, disp=8, kind=I64 } -> x0 - v163 Imm(0) -> x2 - v164 Extend { value=v154, kind=I32 } -> x2 - v165 BinopI { op=shl, lhs=v164, rhs_imm=1 } -> x6 - v166 Binop { op=add, lhs=v162, rhs=v165 } -> x6 - v167 LoadIndexed { base=v162, index=v164, scale=2, kind=I16 } -> x0 - v168 Imm(1000) -> x6 - v169 BinopI { op=add, lhs=v164, rhs_imm=1000 } -> x2 - v170 BinopI { op=shl, lhs=v169, rhs_imm=32 } -> x6 - v171 Extend { value=v169, kind=I32 } -> x6 - v172 BinopI { op=shl, lhs=v169, rhs_imm=48 } -> x2 - v173 Extend { value=v171, kind=I16 } -> x2 - v174 Binop { op=ne, lhs=v167, rhs=v173 } -> x0 - terminator Bz { cond=v174, target=b28, fall=b27 } (exit_acc=v174) + v322 LocalAddr(-14) -> x2 + v323 BinopI { op=add, lhs=v322, rhs_imm=8 } -> x6 + v324 Load { addr=v322, disp=8, kind=I64 } -> x2 + v325 Extend { value=v316, kind=I32 } -> x6 + v326 BinopI { op=shl, lhs=v317, rhs_imm=1 } -> x6 + v327 Binop { op=add, lhs=v324, rhs=v326 } -> x6 + v328 LoadIndexed { base=v324, index=v317, scale=2, kind=I16 } -> x2 + v329 Imm(1000) -> x6 + v330 BinopI { op=add, lhs=v317, rhs_imm=1000 } -> x6 + v331 BinopI { op=shl, lhs=v330, rhs_imm=32 } -> x7 + v332 Extend { value=v330, kind=I32 } -> x7 + v333 BinopI { op=shl, lhs=v330, rhs_imm=48 } -> x6 + v334 Extend { value=v332, kind=I16 } -> x6 + v335 Binop { op=ne, lhs=v328, rhs=v334 } -> x2 + terminator Bnz { cond=v335, target=b80, fall=b26 } (exit_acc=v335) block 26 start_pc=0 - v175 Imm(0) -> x1 - v176 Imm(0) -> x0 - terminator Jmp(b29) (exit_acc=v175) + v319 Extend { value=v316, kind=I32 } -> x1 + v320 BinopI { op=add, lhs=v317, rhs_imm=1 } -> x1 + v321 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v320) block 27 start_pc=0 - v177 Imm(20) -> x0 - v178 Extend { value=v154, kind=I32 } -> x0 - v179 BinopI { op=add, lhs=v154, rhs_imm=20 } -> x0 - v180 BinopI { op=shl, lhs=v179, rhs_imm=32 } -> x1 - v181 Extend { value=v179, kind=I32 } -> x0 - terminator Return(v181) (exit_acc=v181) + v316 Phi { incoming=[b24:v309, b26:v320], kind=I64 } -> x1 + v317 Extend { value=v316, kind=I32 } -> x0 + v318 BinopI { op=lt, lhs=v317, rhs_imm=8 } -> x2 + terminator Bnz { cond=v318, target=b25, fall=b28 } (exit_acc=v318) block 28 start_pc=0 - terminator Jmp(b24) + v336 Imm(0) -> x1 + v337 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v336) block 29 start_pc=0 - v182 Phi { incoming=[b26:v175, b30:v186], kind=I64 } -> x1 - v183 Extend { value=v182, kind=I32 } -> x0 - v184 BinopI { op=lt, lhs=v183, rhs_imm=8 } -> x0 - terminator Bz { cond=v184, target=b32, fall=b31 } (exit_acc=v184) + v349 Imm(0) -> x2 + v350 Imm(0) -> x6 + terminator Jmp(b30) (exit_acc=v349) block 30 start_pc=0 - v185 Extend { value=v182, kind=I32 } -> x0 - v186 BinopI { op=add, lhs=v185, rhs_imm=1 } -> x1 - v187 Imm(0) -> x0 - terminator Jmp(b29) (exit_acc=v186) + v353 Imm(0) -> x2 + v354 Imm(1) -> x2 + v355 LocalAddr(-14) -> x2 + v356 BinopI { op=add, lhs=v355, rhs_imm=32 } -> x6 + v357 Load { addr=v355, disp=32, kind=I64 } -> x2 + v358 Imm(0) -> x6 + v359 Extend { value=v343, kind=I32 } -> x6 + v360 BinopI { op=mul, lhs=v344, rhs_imm=20 } -> x6 + v361 Binop { op=add, lhs=v357, rhs=v360 } -> x2 + v362 Imm(0) -> x6 + v363 Imm(0) -> x6 + v364 BinopI { op=add, lhs=v361, rhs_imm=0 } -> x2 + v365 BinopI { op=mul, lhs=v344, rhs_imm=100 } -> x6 + v366 BinopI { op=shl, lhs=v365, rhs_imm=32 } -> x7 + v367 Extend { value=v365, kind=I32 } -> x7 + v368 BinopI { op=add, lhs=v365, rhs_imm=0 } -> x6 + v369 BinopI { op=shl, lhs=v368, rhs_imm=32 } -> x7 + v370 Extend { value=v368, kind=I32 } -> x7 + v371 Store { addr=v364, disp=0, value=v368, kind=I32 } -> - + v372 Imm(0) -> x2 + v373 Imm(1) -> x2 + v374 Imm(0) -> x2 + v375 Imm(1) -> x2 + v376 Imm(1) -> x2 + v377 LocalAddr(-14) -> x2 + v378 BinopI { op=add, lhs=v377, rhs_imm=32 } -> x6 + v379 Load { addr=v377, disp=32, kind=I64 } -> x2 + v380 Imm(0) -> x6 + v381 Extend { value=v343, kind=I32 } -> x6 + v382 BinopI { op=mul, lhs=v344, rhs_imm=20 } -> x6 + v383 Binop { op=add, lhs=v379, rhs=v382 } -> x2 + v384 Imm(1) -> x6 + v385 Imm(4) -> x6 + v386 BinopI { op=add, lhs=v383, rhs_imm=4 } -> x6 + v387 BinopI { op=mul, lhs=v344, rhs_imm=100 } -> x6 + v388 BinopI { op=shl, lhs=v387, rhs_imm=32 } -> x7 + v389 Extend { value=v387, kind=I32 } -> x7 + v390 BinopI { op=add, lhs=v387, rhs_imm=1 } -> x6 + v391 BinopI { op=shl, lhs=v390, rhs_imm=32 } -> x7 + v392 Extend { value=v390, kind=I32 } -> x7 + v393 Store { addr=v383, disp=4, value=v390, kind=I32 } -> - + v394 Imm(1) -> x2 + v395 Imm(2) -> x2 + v396 Imm(0) -> x2 + v397 Imm(2) -> x2 + v398 Imm(1) -> x2 + v399 LocalAddr(-14) -> x2 + v400 BinopI { op=add, lhs=v399, rhs_imm=32 } -> x6 + v401 Load { addr=v399, disp=32, kind=I64 } -> x2 + v402 Imm(0) -> x6 + v403 Extend { value=v343, kind=I32 } -> x6 + v404 BinopI { op=mul, lhs=v344, rhs_imm=20 } -> x6 + v405 Binop { op=add, lhs=v401, rhs=v404 } -> x2 + v406 Imm(2) -> x6 + v407 Imm(8) -> x6 + v408 BinopI { op=add, lhs=v405, rhs_imm=8 } -> x6 + v409 BinopI { op=mul, lhs=v344, rhs_imm=100 } -> x6 + v410 BinopI { op=shl, lhs=v409, rhs_imm=32 } -> x7 + v411 Extend { value=v409, kind=I32 } -> x7 + v412 BinopI { op=add, lhs=v409, rhs_imm=2 } -> x6 + v413 BinopI { op=shl, lhs=v412, rhs_imm=32 } -> x7 + v414 Extend { value=v412, kind=I32 } -> x7 + v415 Store { addr=v405, disp=8, value=v412, kind=I32 } -> - + v416 Imm(2) -> x2 + v417 Imm(3) -> x2 + v418 Imm(0) -> x2 + v419 Imm(3) -> x2 + v420 Imm(1) -> x2 + v421 LocalAddr(-14) -> x2 + v422 BinopI { op=add, lhs=v421, rhs_imm=32 } -> x6 + v423 Load { addr=v421, disp=32, kind=I64 } -> x2 + v424 Imm(0) -> x6 + v425 Extend { value=v343, kind=I32 } -> x6 + v426 BinopI { op=mul, lhs=v344, rhs_imm=20 } -> x6 + v427 Binop { op=add, lhs=v423, rhs=v426 } -> x2 + v428 Imm(3) -> x6 + v429 Imm(12) -> x6 + v430 BinopI { op=add, lhs=v427, rhs_imm=12 } -> x6 + v431 BinopI { op=mul, lhs=v344, rhs_imm=100 } -> x6 + v432 BinopI { op=shl, lhs=v431, rhs_imm=32 } -> x7 + v433 Extend { value=v431, kind=I32 } -> x7 + v434 BinopI { op=add, lhs=v431, rhs_imm=3 } -> x6 + v435 BinopI { op=shl, lhs=v434, rhs_imm=32 } -> x7 + v436 Extend { value=v434, kind=I32 } -> x7 + v437 Store { addr=v427, disp=12, value=v434, kind=I32 } -> - + v438 Imm(3) -> x2 + v439 Imm(4) -> x2 + v440 Imm(0) -> x2 + v441 Imm(4) -> x2 + v442 Imm(1) -> x2 + v443 LocalAddr(-14) -> x2 + v444 BinopI { op=add, lhs=v443, rhs_imm=32 } -> x6 + v445 Load { addr=v443, disp=32, kind=I64 } -> x2 + v446 Imm(0) -> x6 + v447 Extend { value=v343, kind=I32 } -> x6 + v448 BinopI { op=mul, lhs=v344, rhs_imm=20 } -> x6 + v449 Binop { op=add, lhs=v445, rhs=v448 } -> x2 + v450 Imm(4) -> x6 + v451 Imm(16) -> x6 + v452 BinopI { op=add, lhs=v449, rhs_imm=16 } -> x6 + v453 BinopI { op=mul, lhs=v344, rhs_imm=100 } -> x6 + v454 BinopI { op=shl, lhs=v453, rhs_imm=32 } -> x7 + v455 Extend { value=v453, kind=I32 } -> x7 + v456 BinopI { op=add, lhs=v453, rhs_imm=4 } -> x6 + v457 BinopI { op=shl, lhs=v456, rhs_imm=32 } -> x7 + v458 Extend { value=v456, kind=I32 } -> x7 + v459 Store { addr=v449, disp=16, value=v456, kind=I32 } -> - + v460 Imm(4) -> x2 + v461 Imm(5) -> x2 + v462 Imm(0) -> x2 + v463 Imm(5) -> x2 + v464 Imm(0) -> x2 + terminator Jmp(b31) (exit_acc=v464) block 31 start_pc=0 - v188 LocalAddr(-14) -> x0 - v189 BinopI { op=add, lhs=v188, rhs_imm=8 } -> x2 - v190 Load { addr=v188, disp=8, kind=I64 } -> x0 - v191 Extend { value=v182, kind=I32 } -> x2 - v192 BinopI { op=shl, lhs=v191, rhs_imm=1 } -> x6 - v193 Binop { op=add, lhs=v190, rhs=v192 } -> x6 - v194 LoadIndexed { base=v190, index=v191, scale=2, kind=I16 } -> x0 - v195 Imm(1000) -> x6 - v196 BinopI { op=add, lhs=v191, rhs_imm=1000 } -> x2 - v197 BinopI { op=shl, lhs=v196, rhs_imm=32 } -> x6 - v198 Extend { value=v196, kind=I32 } -> x6 - v199 BinopI { op=shl, lhs=v196, rhs_imm=48 } -> x2 - v200 Extend { value=v198, kind=I16 } -> x2 - v201 Binop { op=ne, lhs=v194, rhs=v200 } -> x0 - terminator Bz { cond=v201, target=b34, fall=b33 } (exit_acc=v201) + v346 Extend { value=v343, kind=I32 } -> x1 + v347 BinopI { op=add, lhs=v344, rhs_imm=1 } -> x1 + v348 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v347) block 32 start_pc=0 - v202 Imm(0) -> x1 - v203 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v202) + v343 Phi { incoming=[b28:v336, b31:v347], kind=I64 } -> x1 + v344 Extend { value=v343, kind=I32 } -> x0 + v345 BinopI { op=lt, lhs=v344, rhs_imm=3 } -> x2 + terminator Bnz { cond=v345, target=b29, fall=b33 } (exit_acc=v345) block 33 start_pc=0 - v204 Imm(28) -> x0 - v205 Extend { value=v182, kind=I32 } -> x0 - v206 BinopI { op=add, lhs=v182, rhs_imm=28 } -> x0 - v207 BinopI { op=shl, lhs=v206, rhs_imm=32 } -> x1 - v208 Extend { value=v206, kind=I32 } -> x0 - terminator Return(v208) (exit_acc=v208) + v351 Imm(0) -> x1 + v352 Imm(0) -> x0 + terminator Jmp(b39) (exit_acc=v351) block 34 start_pc=0 - terminator Jmp(b30) + v471 Imm(0) -> x6 + v472 Imm(0) -> x2 + terminator Jmp(b37) (exit_acc=v471) block 35 start_pc=0 - v209 Phi { incoming=[b32:v202, b36:v213], kind=I64 } -> x1 - v210 Extend { value=v209, kind=I32 } -> x0 - v211 BinopI { op=lt, lhs=v210, rhs_imm=3 } -> x0 - terminator Bz { cond=v211, target=b38, fall=b37 } (exit_acc=v211) + v481 LocalAddr(-14) -> x7 + v482 BinopI { op=add, lhs=v481, rhs_imm=32 } -> x8 + v483 Load { addr=v481, disp=32, kind=I64 } -> x7 + v484 Imm(0) -> x8 + v485 Extend { value=v465, kind=I32 } -> x8 + v486 BinopI { op=mul, lhs=v466, rhs_imm=20 } -> x8 + v487 Binop { op=add, lhs=v483, rhs=v486 } -> x7 + v488 Extend { value=v475, kind=I32 } -> x8 + v489 BinopI { op=shl, lhs=v476, rhs_imm=2 } -> x8 + v490 Binop { op=add, lhs=v487, rhs=v489 } -> x8 + v491 LoadIndexed { base=v487, index=v476, scale=4, kind=I32 } -> x7 + v492 BinopI { op=mul, lhs=v466, rhs_imm=100 } -> x8 + v493 BinopI { op=shl, lhs=v492, rhs_imm=32 } -> x9 + v494 Extend { value=v492, kind=I32 } -> x9 + v495 Binop { op=add, lhs=v492, rhs=v476 } -> x8 + v496 BinopI { op=shl, lhs=v495, rhs_imm=32 } -> x9 + v497 Extend { value=v495, kind=I32 } -> x8 + v498 Binop { op=ne, lhs=v491, rhs=v497 } -> x7 + terminator Bnz { cond=v498, target=b79, fall=b36 } (exit_acc=v498) block 36 start_pc=0 - v212 Extend { value=v209, kind=I32 } -> x0 - v213 BinopI { op=add, lhs=v212, rhs_imm=1 } -> x1 - v214 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v213) + v478 Extend { value=v475, kind=I32 } -> x6 + v479 BinopI { op=add, lhs=v476, rhs_imm=1 } -> x6 + v480 Imm(0) -> x2 + terminator Jmp(b37) (exit_acc=v479) block 37 start_pc=0 - v215 Imm(0) -> x2 - v216 Imm(0) -> x0 - terminator Jmp(b39) (exit_acc=v215) + v475 Phi { incoming=[b34:v471, b36:v479], kind=I64 } -> x6 + v476 Extend { value=v475, kind=I32 } -> x2 + v477 BinopI { op=lt, lhs=v476, rhs_imm=5 } -> x7 + terminator Bnz { cond=v477, target=b35, fall=b38 } (exit_acc=v477) block 38 start_pc=0 - v217 Imm(0) -> x1 - v218 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v217) + v468 Extend { value=v465, kind=I32 } -> x1 + v469 BinopI { op=add, lhs=v466, rhs_imm=1 } -> x1 + v470 Imm(0) -> x0 + terminator Jmp(b39) (exit_acc=v469) block 39 start_pc=0 - v219 Phi { incoming=[b37:v215, b40:v223], kind=I64 } -> x2 - v220 Extend { value=v219, kind=I32 } -> x0 - v221 BinopI { op=lt, lhs=v220, rhs_imm=5 } -> x0 - terminator Bz { cond=v221, target=b42, fall=b41 } (exit_acc=v221) + v465 Phi { incoming=[b33:v351, b38:v469], kind=I64 } -> x1 + v466 Extend { value=v465, kind=I32 } -> x0 + v467 BinopI { op=lt, lhs=v466, rhs_imm=3 } -> x2 + terminator Bnz { cond=v467, target=b34, fall=b40 } (exit_acc=v467) block 40 start_pc=0 - v222 Extend { value=v219, kind=I32 } -> x0 - v223 BinopI { op=add, lhs=v222, rhs_imm=1 } -> x2 - v224 Imm(0) -> x0 - terminator Jmp(b39) (exit_acc=v223) + v473 Imm(0) -> x1 + v474 Imm(0) -> x0 + terminator Jmp(b46) (exit_acc=v473) block 41 start_pc=0 - v225 LocalAddr(-14) -> x0 - v226 BinopI { op=add, lhs=v225, rhs_imm=32 } -> x6 - v227 Load { addr=v225, disp=32, kind=I64 } -> x0 - v228 Imm(0) -> x6 - v229 Extend { value=v209, kind=I32 } -> x6 - v230 BinopI { op=mul, lhs=v229, rhs_imm=20 } -> x7 - v231 Binop { op=add, lhs=v227, rhs=v230 } -> x0 - v232 Extend { value=v219, kind=I32 } -> x7 - v233 BinopI { op=shl, lhs=v232, rhs_imm=2 } -> x8 - v234 Binop { op=add, lhs=v231, rhs=v233 } -> x8 - v235 BinopI { op=mul, lhs=v229, rhs_imm=100 } -> x6 - v236 BinopI { op=shl, lhs=v235, rhs_imm=32 } -> x8 - v237 Extend { value=v235, kind=I32 } -> x8 - v238 Binop { op=add, lhs=v235, rhs=v232 } -> x6 - v239 BinopI { op=shl, lhs=v238, rhs_imm=32 } -> x8 - v240 Extend { value=v238, kind=I32 } -> x8 - v241 StoreIndexed { base=v231, index=v232, scale=4, value=v238, kind=I32 } -> - - terminator Jmp(b40) (exit_acc=v241) + v517 Imm(0) -> x6 + v518 Imm(0) -> x2 + terminator Jmp(b44) (exit_acc=v517) block 42 start_pc=0 - terminator Jmp(b36) + v527 LocalAddr(-14) -> x7 + v528 BinopI { op=add, lhs=v527, rhs_imm=32 } -> x8 + v529 Load { addr=v527, disp=32, kind=I64 } -> x7 + v530 Extend { value=v511, kind=I32 } -> x8 + v531 BinopI { op=mul, lhs=v512, rhs_imm=20 } -> x8 + v532 Binop { op=add, lhs=v529, rhs=v531 } -> x7 + v533 Extend { value=v521, kind=I32 } -> x8 + v534 BinopI { op=shl, lhs=v522, rhs_imm=2 } -> x8 + v535 Binop { op=add, lhs=v532, rhs=v534 } -> x8 + v536 LoadIndexed { base=v532, index=v522, scale=4, kind=I32 } -> x7 + v537 BinopI { op=mul, lhs=v512, rhs_imm=100 } -> x8 + v538 BinopI { op=shl, lhs=v537, rhs_imm=32 } -> x9 + v539 Extend { value=v537, kind=I32 } -> x9 + v540 Binop { op=add, lhs=v537, rhs=v522 } -> x8 + v541 BinopI { op=shl, lhs=v540, rhs_imm=32 } -> x9 + v542 Extend { value=v540, kind=I32 } -> x8 + v543 Binop { op=ne, lhs=v536, rhs=v542 } -> x7 + terminator Bnz { cond=v543, target=b78, fall=b43 } (exit_acc=v543) block 43 start_pc=0 - v242 Phi { incoming=[b38:v217, b44:v246], kind=I64 } -> x1 - v243 Extend { value=v242, kind=I32 } -> x0 - v244 BinopI { op=lt, lhs=v243, rhs_imm=3 } -> x0 - terminator Bz { cond=v244, target=b46, fall=b45 } (exit_acc=v244) + v524 Extend { value=v521, kind=I32 } -> x6 + v525 BinopI { op=add, lhs=v522, rhs_imm=1 } -> x6 + v526 Imm(0) -> x2 + terminator Jmp(b44) (exit_acc=v525) block 44 start_pc=0 - v245 Extend { value=v242, kind=I32 } -> x0 - v246 BinopI { op=add, lhs=v245, rhs_imm=1 } -> x1 - v247 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v246) + v521 Phi { incoming=[b41:v517, b43:v525], kind=I64 } -> x6 + v522 Extend { value=v521, kind=I32 } -> x2 + v523 BinopI { op=lt, lhs=v522, rhs_imm=5 } -> x7 + terminator Bnz { cond=v523, target=b42, fall=b45 } (exit_acc=v523) block 45 start_pc=0 - v248 Imm(0) -> x2 - v249 Imm(0) -> x0 - terminator Jmp(b47) (exit_acc=v248) + v514 Extend { value=v511, kind=I32 } -> x1 + v515 BinopI { op=add, lhs=v512, rhs_imm=1 } -> x1 + v516 Imm(0) -> x0 + terminator Jmp(b46) (exit_acc=v515) block 46 start_pc=0 - v250 Imm(0) -> x1 - v251 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v250) + v511 Phi { incoming=[b40:v473, b45:v515], kind=I64 } -> x1 + v512 Extend { value=v511, kind=I32 } -> x0 + v513 BinopI { op=lt, lhs=v512, rhs_imm=3 } -> x2 + terminator Bnz { cond=v513, target=b41, fall=b47 } (exit_acc=v513) block 47 start_pc=0 - v252 Phi { incoming=[b45:v248, b48:v256], kind=I64 } -> x2 - v253 Extend { value=v252, kind=I32 } -> x0 - v254 BinopI { op=lt, lhs=v253, rhs_imm=5 } -> x0 - terminator Bz { cond=v254, target=b50, fall=b49 } (exit_acc=v254) + v519 Imm(0) -> x1 + v520 Imm(0) -> x0 + terminator Jmp(b54) (exit_acc=v519) block 48 start_pc=0 - v255 Extend { value=v252, kind=I32 } -> x0 - v256 BinopI { op=add, lhs=v255, rhs_imm=1 } -> x2 - v257 Imm(0) -> x0 - terminator Jmp(b47) (exit_acc=v256) + v562 Imm(0) -> x6 + v563 Imm(0) -> x2 + terminator Jmp(b52) (exit_acc=v562) block 49 start_pc=0 - v258 LocalAddr(-14) -> x0 - v259 BinopI { op=add, lhs=v258, rhs_imm=32 } -> x6 - v260 Load { addr=v258, disp=32, kind=I64 } -> x0 - v261 Imm(0) -> x6 - v262 Extend { value=v242, kind=I32 } -> x6 - v263 BinopI { op=mul, lhs=v262, rhs_imm=20 } -> x7 - v264 Binop { op=add, lhs=v260, rhs=v263 } -> x0 - v265 Extend { value=v252, kind=I32 } -> x7 - v266 BinopI { op=shl, lhs=v265, rhs_imm=2 } -> x8 - v267 Binop { op=add, lhs=v264, rhs=v266 } -> x8 - v268 LoadIndexed { base=v264, index=v265, scale=4, kind=I32 } -> x0 - v269 BinopI { op=mul, lhs=v262, rhs_imm=100 } -> x6 - v270 BinopI { op=shl, lhs=v269, rhs_imm=32 } -> x8 - v271 Extend { value=v269, kind=I32 } -> x8 - v272 Binop { op=add, lhs=v269, rhs=v265 } -> x6 - v273 BinopI { op=shl, lhs=v272, rhs_imm=32 } -> x7 - v274 Extend { value=v272, kind=I32 } -> x6 - v275 Binop { op=ne, lhs=v268, rhs=v274 } -> x0 - terminator Bz { cond=v275, target=b52, fall=b51 } (exit_acc=v275) + v572 Imm(0) -> x7 + v573 Imm(0) -> x8 + terminator Jmp(b50) (exit_acc=v572) block 50 start_pc=0 - terminator Jmp(b44) + v574 Imm(0) -> x7 + v575 Imm(1) -> x7 + v576 LocalAddr(-14) -> x7 + v577 BinopI { op=add, lhs=v576, rhs_imm=40 } -> x8 + v578 Load { addr=v576, disp=40, kind=I64 } -> x7 + v579 Imm(0) -> x8 + v580 Extend { value=v556, kind=I32 } -> x8 + v581 BinopI { op=mul, lhs=v557, rhs_imm=12 } -> x8 + v582 Binop { op=add, lhs=v578, rhs=v581 } -> x7 + v583 Extend { value=v566, kind=I32 } -> x9 + v584 BinopI { op=shl, lhs=v567, rhs_imm=2 } -> x9 + v585 Binop { op=add, lhs=v582, rhs=v584 } -> x7 + v586 Imm(0) -> x3 + v587 BinopI { op=add, lhs=v585, rhs_imm=0 } -> x7 + v588 BinopI { op=shl, lhs=v581, rhs_imm=32 } -> x3 + v589 Extend { value=v581, kind=I32 } -> x3 + v590 BinopI { op=shl, lhs=v584, rhs_imm=32 } -> x3 + v591 Extend { value=v584, kind=I32 } -> x3 + v592 Binop { op=add, lhs=v581, rhs=v584 } -> x8 + v593 BinopI { op=shl, lhs=v592, rhs_imm=32 } -> x9 + v594 Extend { value=v592, kind=I32 } -> x9 + v595 BinopI { op=add, lhs=v592, rhs_imm=0 } -> x8 + v596 BinopI { op=shl, lhs=v595, rhs_imm=32 } -> x9 + v597 Extend { value=v595, kind=I32 } -> x9 + v598 BinopI { op=shl, lhs=v595, rhs_imm=56 } -> x8 + v599 Extend { value=v597, kind=I8 } -> x8 + v600 Store { addr=v587, disp=0, value=v597, kind=I8 } -> - + v601 Imm(0) -> x7 + v602 Imm(1) -> x7 + v603 Imm(0) -> x7 + v604 Imm(1) -> x7 + v605 Imm(1) -> x7 + v606 LocalAddr(-14) -> x7 + v607 BinopI { op=add, lhs=v606, rhs_imm=40 } -> x8 + v608 Load { addr=v606, disp=40, kind=I64 } -> x7 + v609 Imm(0) -> x8 + v610 Extend { value=v556, kind=I32 } -> x8 + v611 BinopI { op=mul, lhs=v557, rhs_imm=12 } -> x8 + v612 Binop { op=add, lhs=v608, rhs=v611 } -> x7 + v613 Extend { value=v566, kind=I32 } -> x9 + v614 BinopI { op=shl, lhs=v567, rhs_imm=2 } -> x9 + v615 Binop { op=add, lhs=v612, rhs=v614 } -> x7 + v616 Imm(1) -> x3 + v617 BinopI { op=add, lhs=v615, rhs_imm=1 } -> x3 + v618 BinopI { op=shl, lhs=v611, rhs_imm=32 } -> x3 + v619 Extend { value=v611, kind=I32 } -> x3 + v620 BinopI { op=shl, lhs=v614, rhs_imm=32 } -> x3 + v621 Extend { value=v614, kind=I32 } -> x3 + v622 Binop { op=add, lhs=v611, rhs=v614 } -> x8 + v623 BinopI { op=shl, lhs=v622, rhs_imm=32 } -> x9 + v624 Extend { value=v622, kind=I32 } -> x9 + v625 BinopI { op=add, lhs=v622, rhs_imm=1 } -> x8 + v626 BinopI { op=shl, lhs=v625, rhs_imm=32 } -> x9 + v627 Extend { value=v625, kind=I32 } -> x9 + v628 BinopI { op=shl, lhs=v625, rhs_imm=56 } -> x8 + v629 Extend { value=v627, kind=I8 } -> x8 + v630 Store { addr=v615, disp=1, value=v627, kind=I8 } -> - + v631 Imm(1) -> x7 + v632 Imm(2) -> x7 + v633 Imm(0) -> x7 + v634 Imm(2) -> x7 + v635 Imm(1) -> x7 + v636 LocalAddr(-14) -> x7 + v637 BinopI { op=add, lhs=v636, rhs_imm=40 } -> x8 + v638 Load { addr=v636, disp=40, kind=I64 } -> x7 + v639 Imm(0) -> x8 + v640 Extend { value=v556, kind=I32 } -> x8 + v641 BinopI { op=mul, lhs=v557, rhs_imm=12 } -> x8 + v642 Binop { op=add, lhs=v638, rhs=v641 } -> x7 + v643 Extend { value=v566, kind=I32 } -> x9 + v644 BinopI { op=shl, lhs=v567, rhs_imm=2 } -> x9 + v645 Binop { op=add, lhs=v642, rhs=v644 } -> x7 + v646 Imm(2) -> x3 + v647 BinopI { op=add, lhs=v645, rhs_imm=2 } -> x3 + v648 BinopI { op=shl, lhs=v641, rhs_imm=32 } -> x3 + v649 Extend { value=v641, kind=I32 } -> x3 + v650 BinopI { op=shl, lhs=v644, rhs_imm=32 } -> x3 + v651 Extend { value=v644, kind=I32 } -> x3 + v652 Binop { op=add, lhs=v641, rhs=v644 } -> x8 + v653 BinopI { op=shl, lhs=v652, rhs_imm=32 } -> x9 + v654 Extend { value=v652, kind=I32 } -> x9 + v655 BinopI { op=add, lhs=v652, rhs_imm=2 } -> x8 + v656 BinopI { op=shl, lhs=v655, rhs_imm=32 } -> x9 + v657 Extend { value=v655, kind=I32 } -> x9 + v658 BinopI { op=shl, lhs=v655, rhs_imm=56 } -> x8 + v659 Extend { value=v657, kind=I8 } -> x8 + v660 Store { addr=v645, disp=2, value=v657, kind=I8 } -> - + v661 Imm(2) -> x7 + v662 Imm(3) -> x7 + v663 Imm(0) -> x7 + v664 Imm(3) -> x7 + v665 Imm(1) -> x7 + v666 LocalAddr(-14) -> x7 + v667 BinopI { op=add, lhs=v666, rhs_imm=40 } -> x8 + v668 Load { addr=v666, disp=40, kind=I64 } -> x7 + v669 Imm(0) -> x8 + v670 Extend { value=v556, kind=I32 } -> x8 + v671 BinopI { op=mul, lhs=v557, rhs_imm=12 } -> x8 + v672 Binop { op=add, lhs=v668, rhs=v671 } -> x7 + v673 Extend { value=v566, kind=I32 } -> x9 + v674 BinopI { op=shl, lhs=v567, rhs_imm=2 } -> x9 + v675 Binop { op=add, lhs=v672, rhs=v674 } -> x7 + v676 Imm(3) -> x3 + v677 BinopI { op=add, lhs=v675, rhs_imm=3 } -> x3 + v678 BinopI { op=shl, lhs=v671, rhs_imm=32 } -> x3 + v679 Extend { value=v671, kind=I32 } -> x3 + v680 BinopI { op=shl, lhs=v674, rhs_imm=32 } -> x3 + v681 Extend { value=v674, kind=I32 } -> x3 + v682 Binop { op=add, lhs=v671, rhs=v674 } -> x8 + v683 BinopI { op=shl, lhs=v682, rhs_imm=32 } -> x9 + v684 Extend { value=v682, kind=I32 } -> x9 + v685 BinopI { op=add, lhs=v682, rhs_imm=3 } -> x8 + v686 BinopI { op=shl, lhs=v685, rhs_imm=32 } -> x9 + v687 Extend { value=v685, kind=I32 } -> x9 + v688 BinopI { op=shl, lhs=v685, rhs_imm=56 } -> x8 + v689 Extend { value=v687, kind=I8 } -> x8 + v690 Store { addr=v675, disp=3, value=v687, kind=I8 } -> - + v691 Imm(3) -> x7 + v692 Imm(4) -> x7 + v693 Imm(0) -> x7 + v694 Imm(4) -> x7 + v695 Imm(0) -> x7 + terminator Jmp(b51) (exit_acc=v695) block 51 start_pc=0 - v276 Imm(40) -> x0 - v277 Extend { value=v242, kind=I32 } -> x0 - v278 BinopI { op=mul, lhs=v242, rhs_imm=5 } -> x0 - v279 BinopI { op=shl, lhs=v278, rhs_imm=32 } -> x1 - v280 Extend { value=v278, kind=I32 } -> x1 - v281 BinopI { op=add, lhs=v278, rhs_imm=40 } -> x0 - v282 BinopI { op=shl, lhs=v281, rhs_imm=32 } -> x1 - v283 Extend { value=v281, kind=I32 } -> x1 - v284 Extend { value=v252, kind=I32 } -> x1 - v285 Binop { op=add, lhs=v281, rhs=v252 } -> x0 - v286 BinopI { op=shl, lhs=v285, rhs_imm=32 } -> x1 - v287 Extend { value=v285, kind=I32 } -> x0 - terminator Return(v287) (exit_acc=v287) + v569 Extend { value=v566, kind=I32 } -> x6 + v570 BinopI { op=add, lhs=v567, rhs_imm=1 } -> x6 + v571 Imm(0) -> x2 + terminator Jmp(b52) (exit_acc=v570) block 52 start_pc=0 - terminator Jmp(b48) + v566 Phi { incoming=[b48:v562, b51:v570], kind=I64 } -> x6 + v567 Extend { value=v566, kind=I32 } -> x2 + v568 BinopI { op=lt, lhs=v567, rhs_imm=3 } -> x7 + terminator Bnz { cond=v568, target=b49, fall=b53 } (exit_acc=v568) block 53 start_pc=0 - v288 Phi { incoming=[b46:v250, b54:v292], kind=I64 } -> x1 - v289 Extend { value=v288, kind=I32 } -> x0 - v290 BinopI { op=lt, lhs=v289, rhs_imm=3 } -> x0 - terminator Bz { cond=v290, target=b56, fall=b55 } (exit_acc=v290) + v559 Extend { value=v556, kind=I32 } -> x1 + v560 BinopI { op=add, lhs=v557, rhs_imm=1 } -> x1 + v561 Imm(0) -> x0 + terminator Jmp(b54) (exit_acc=v560) block 54 start_pc=0 - v291 Extend { value=v288, kind=I32 } -> x0 - v292 BinopI { op=add, lhs=v291, rhs_imm=1 } -> x1 - v293 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v292) + v556 Phi { incoming=[b47:v519, b53:v560], kind=I64 } -> x1 + v557 Extend { value=v556, kind=I32 } -> x0 + v558 BinopI { op=lt, lhs=v557, rhs_imm=2 } -> x2 + terminator Bnz { cond=v558, target=b48, fall=b55 } (exit_acc=v558) block 55 start_pc=0 - v294 Imm(0) -> x2 - v295 Imm(0) -> x0 - terminator Jmp(b57) (exit_acc=v294) + v564 Imm(0) -> x1 + v565 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v564) block 56 start_pc=0 - v296 Imm(0) -> x1 - v297 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v296) + v702 Imm(0) -> x6 + v703 Imm(0) -> x2 + terminator Jmp(b62) (exit_acc=v702) block 57 start_pc=0 - v298 Phi { incoming=[b55:v294, b58:v302], kind=I64 } -> x2 - v299 Extend { value=v298, kind=I32 } -> x0 - v300 BinopI { op=lt, lhs=v299, rhs_imm=5 } -> x0 - terminator Bz { cond=v300, target=b60, fall=b59 } (exit_acc=v300) + v712 Imm(0) -> x8 + v713 Imm(0) -> x7 + terminator Jmp(b60) (exit_acc=v712) block 58 start_pc=0 - v301 Extend { value=v298, kind=I32 } -> x0 - v302 BinopI { op=add, lhs=v301, rhs_imm=1 } -> x2 - v303 Imm(0) -> x0 - terminator Jmp(b57) (exit_acc=v302) + v720 LocalAddr(-14) -> x9 + v721 BinopI { op=add, lhs=v720, rhs_imm=40 } -> x3 + v722 Load { addr=v720, disp=40, kind=I64 } -> x9 + v723 Imm(0) -> x3 + v724 Extend { value=v696, kind=I32 } -> x3 + v725 BinopI { op=mul, lhs=v697, rhs_imm=12 } -> x3 + v726 Binop { op=add, lhs=v722, rhs=v725 } -> x9 + v727 Extend { value=v706, kind=I32 } -> x12 + v728 BinopI { op=shl, lhs=v707, rhs_imm=2 } -> x12 + v729 Binop { op=add, lhs=v726, rhs=v728 } -> x9 + v730 Extend { value=v714, kind=I32 } -> x13 + v731 Binop { op=add, lhs=v729, rhs=v715 } -> x9 + v732 Load { addr=v731, disp=0, kind=I8 } -> x9 + v733 BinopI { op=shl, lhs=v725, rhs_imm=32 } -> x13 + v734 Extend { value=v725, kind=I32 } -> x13 + v735 BinopI { op=shl, lhs=v728, rhs_imm=32 } -> x13 + v736 Extend { value=v728, kind=I32 } -> x13 + v737 Binop { op=add, lhs=v725, rhs=v728 } -> x3 + v738 BinopI { op=shl, lhs=v737, rhs_imm=32 } -> x12 + v739 Extend { value=v737, kind=I32 } -> x12 + v740 Binop { op=add, lhs=v737, rhs=v715 } -> x3 + v741 BinopI { op=shl, lhs=v740, rhs_imm=32 } -> x12 + v742 Extend { value=v740, kind=I32 } -> x12 + v743 BinopI { op=shl, lhs=v740, rhs_imm=56 } -> x3 + v744 Extend { value=v742, kind=I8 } -> x3 + v745 Binop { op=ne, lhs=v732, rhs=v744 } -> x9 + terminator Bnz { cond=v745, target=b77, fall=b59 } (exit_acc=v745) block 59 start_pc=0 - v304 LocalAddr(-14) -> x0 - v305 BinopI { op=add, lhs=v304, rhs_imm=32 } -> x6 - v306 Load { addr=v304, disp=32, kind=I64 } -> x0 - v307 Extend { value=v288, kind=I32 } -> x6 - v308 BinopI { op=mul, lhs=v307, rhs_imm=20 } -> x7 - v309 Binop { op=add, lhs=v306, rhs=v308 } -> x0 - v310 Extend { value=v298, kind=I32 } -> x7 - v311 BinopI { op=shl, lhs=v310, rhs_imm=2 } -> x8 - v312 Binop { op=add, lhs=v309, rhs=v311 } -> x8 - v313 LoadIndexed { base=v309, index=v310, scale=4, kind=I32 } -> x0 - v314 BinopI { op=mul, lhs=v307, rhs_imm=100 } -> x6 - v315 BinopI { op=shl, lhs=v314, rhs_imm=32 } -> x8 - v316 Extend { value=v314, kind=I32 } -> x8 - v317 Binop { op=add, lhs=v314, rhs=v310 } -> x6 - v318 BinopI { op=shl, lhs=v317, rhs_imm=32 } -> x7 - v319 Extend { value=v317, kind=I32 } -> x6 - v320 Binop { op=ne, lhs=v313, rhs=v319 } -> x0 - terminator Bz { cond=v320, target=b62, fall=b61 } (exit_acc=v320) + v717 Extend { value=v714, kind=I32 } -> x8 + v718 BinopI { op=add, lhs=v715, rhs_imm=1 } -> x8 + v719 Imm(0) -> x7 + terminator Jmp(b60) (exit_acc=v718) block 60 start_pc=0 - terminator Jmp(b54) + v714 Phi { incoming=[b57:v712, b59:v718], kind=I64 } -> x8 + v715 Extend { value=v714, kind=I32 } -> x7 + v716 BinopI { op=lt, lhs=v715, rhs_imm=4 } -> x9 + terminator Bnz { cond=v716, target=b58, fall=b61 } (exit_acc=v716) block 61 start_pc=0 - v321 Imm(60) -> x0 - v322 Extend { value=v288, kind=I32 } -> x0 - v323 BinopI { op=mul, lhs=v288, rhs_imm=5 } -> x0 - v324 BinopI { op=shl, lhs=v323, rhs_imm=32 } -> x1 - v325 Extend { value=v323, kind=I32 } -> x1 - v326 BinopI { op=add, lhs=v323, rhs_imm=60 } -> x0 - v327 BinopI { op=shl, lhs=v326, rhs_imm=32 } -> x1 - v328 Extend { value=v326, kind=I32 } -> x1 - v329 Extend { value=v298, kind=I32 } -> x1 - v330 Binop { op=add, lhs=v326, rhs=v298 } -> x0 - v331 BinopI { op=shl, lhs=v330, rhs_imm=32 } -> x1 - v332 Extend { value=v330, kind=I32 } -> x0 - terminator Return(v332) (exit_acc=v332) + v709 Extend { value=v706, kind=I32 } -> x6 + v710 BinopI { op=add, lhs=v707, rhs_imm=1 } -> x6 + v711 Imm(0) -> x2 + terminator Jmp(b62) (exit_acc=v710) block 62 start_pc=0 - terminator Jmp(b58) + v706 Phi { incoming=[b56:v702, b61:v710], kind=I64 } -> x6 + v707 Extend { value=v706, kind=I32 } -> x2 + v708 BinopI { op=lt, lhs=v707, rhs_imm=3 } -> x7 + terminator Bnz { cond=v708, target=b57, fall=b63 } (exit_acc=v708) block 63 start_pc=0 - v333 Phi { incoming=[b56:v296, b64:v337], kind=I64 } -> x1 - v334 Extend { value=v333, kind=I32 } -> x0 - v335 BinopI { op=lt, lhs=v334, rhs_imm=2 } -> x0 - terminator Bz { cond=v335, target=b66, fall=b65 } (exit_acc=v335) + v699 Extend { value=v696, kind=I32 } -> x1 + v700 BinopI { op=add, lhs=v697, rhs_imm=1 } -> x1 + v701 Imm(0) -> x0 + terminator Jmp(b64) (exit_acc=v700) block 64 start_pc=0 - v336 Extend { value=v333, kind=I32 } -> x0 - v337 BinopI { op=add, lhs=v336, rhs_imm=1 } -> x1 - v338 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v337) + v696 Phi { incoming=[b55:v564, b63:v700], kind=I64 } -> x1 + v697 Extend { value=v696, kind=I32 } -> x0 + v698 BinopI { op=lt, lhs=v697, rhs_imm=2 } -> x2 + terminator Bnz { cond=v698, target=b56, fall=b65 } (exit_acc=v698) block 65 start_pc=0 - v339 Imm(0) -> x2 - v340 Imm(0) -> x0 - terminator Jmp(b67) (exit_acc=v339) + v704 Imm(0) -> x1 + v705 Imm(0) -> x0 + terminator Jmp(b74) (exit_acc=v704) block 66 start_pc=0 - v341 Imm(0) -> x1 - v342 Imm(0) -> x0 - terminator Jmp(b75) (exit_acc=v341) + v771 Imm(0) -> x6 + v772 Imm(0) -> x2 + terminator Jmp(b72) (exit_acc=v771) block 67 start_pc=0 - v343 Phi { incoming=[b65:v339, b68:v347], kind=I64 } -> x2 - v344 Extend { value=v343, kind=I32 } -> x0 - v345 BinopI { op=lt, lhs=v344, rhs_imm=3 } -> x0 - terminator Bz { cond=v345, target=b70, fall=b69 } (exit_acc=v345) + v780 Imm(0) -> x8 + v781 Imm(0) -> x7 + terminator Jmp(b70) (exit_acc=v780) block 68 start_pc=0 - v346 Extend { value=v343, kind=I32 } -> x0 - v347 BinopI { op=add, lhs=v346, rhs_imm=1 } -> x2 - v348 Imm(0) -> x0 - terminator Jmp(b67) (exit_acc=v347) + v788 LocalAddr(-14) -> x9 + v789 BinopI { op=add, lhs=v788, rhs_imm=40 } -> x3 + v790 Load { addr=v788, disp=40, kind=I64 } -> x9 + v791 Extend { value=v765, kind=I32 } -> x3 + v792 BinopI { op=mul, lhs=v766, rhs_imm=12 } -> x3 + v793 Binop { op=add, lhs=v790, rhs=v792 } -> x9 + v794 Extend { value=v774, kind=I32 } -> x12 + v795 BinopI { op=shl, lhs=v775, rhs_imm=2 } -> x12 + v796 Binop { op=add, lhs=v793, rhs=v795 } -> x9 + v797 Extend { value=v782, kind=I32 } -> x13 + v798 Binop { op=add, lhs=v796, rhs=v783 } -> x9 + v799 Load { addr=v798, disp=0, kind=I8 } -> x9 + v800 BinopI { op=shl, lhs=v792, rhs_imm=32 } -> x13 + v801 Extend { value=v792, kind=I32 } -> x13 + v802 BinopI { op=shl, lhs=v795, rhs_imm=32 } -> x13 + v803 Extend { value=v795, kind=I32 } -> x13 + v804 Binop { op=add, lhs=v792, rhs=v795 } -> x3 + v805 BinopI { op=shl, lhs=v804, rhs_imm=32 } -> x12 + v806 Extend { value=v804, kind=I32 } -> x12 + v807 Binop { op=add, lhs=v804, rhs=v783 } -> x3 + v808 BinopI { op=shl, lhs=v807, rhs_imm=32 } -> x12 + v809 Extend { value=v807, kind=I32 } -> x12 + v810 BinopI { op=shl, lhs=v807, rhs_imm=56 } -> x3 + v811 Extend { value=v809, kind=I8 } -> x3 + v812 Binop { op=ne, lhs=v799, rhs=v811 } -> x9 + terminator Bnz { cond=v812, target=b76, fall=b69 } (exit_acc=v812) block 69 start_pc=0 - v349 Imm(0) -> x6 - v350 Imm(0) -> x0 - terminator Jmp(b71) (exit_acc=v349) + v785 Extend { value=v782, kind=I32 } -> x8 + v786 BinopI { op=add, lhs=v783, rhs_imm=1 } -> x8 + v787 Imm(0) -> x7 + terminator Jmp(b70) (exit_acc=v786) block 70 start_pc=0 - terminator Jmp(b64) + v782 Phi { incoming=[b67:v780, b69:v786], kind=I64 } -> x8 + v783 Extend { value=v782, kind=I32 } -> x7 + v784 BinopI { op=lt, lhs=v783, rhs_imm=4 } -> x9 + terminator Bnz { cond=v784, target=b68, fall=b71 } (exit_acc=v784) block 71 start_pc=0 - v351 Phi { incoming=[b69:v349, b72:v355], kind=I64 } -> x6 - v352 Extend { value=v351, kind=I32 } -> x0 - v353 BinopI { op=lt, lhs=v352, rhs_imm=4 } -> x0 - terminator Bz { cond=v353, target=b74, fall=b73 } (exit_acc=v353) + v777 Extend { value=v774, kind=I32 } -> x6 + v778 BinopI { op=add, lhs=v775, rhs_imm=1 } -> x6 + v779 Imm(0) -> x2 + terminator Jmp(b72) (exit_acc=v778) block 72 start_pc=0 - v354 Extend { value=v351, kind=I32 } -> x0 - v355 BinopI { op=add, lhs=v354, rhs_imm=1 } -> x6 - v356 Imm(0) -> x0 - terminator Jmp(b71) (exit_acc=v355) + v774 Phi { incoming=[b66:v771, b71:v778], kind=I64 } -> x6 + v775 Extend { value=v774, kind=I32 } -> x2 + v776 BinopI { op=lt, lhs=v775, rhs_imm=3 } -> x7 + terminator Bnz { cond=v776, target=b67, fall=b73 } (exit_acc=v776) block 73 start_pc=0 - v357 LocalAddr(-14) -> x0 - v358 BinopI { op=add, lhs=v357, rhs_imm=40 } -> x7 - v359 Load { addr=v357, disp=40, kind=I64 } -> x0 - v360 Imm(0) -> x7 - v361 Extend { value=v333, kind=I32 } -> x7 - v362 BinopI { op=mul, lhs=v361, rhs_imm=12 } -> x7 - v363 Binop { op=add, lhs=v359, rhs=v362 } -> x0 - v364 Extend { value=v343, kind=I32 } -> x8 - v365 BinopI { op=shl, lhs=v364, rhs_imm=2 } -> x8 - v366 Binop { op=add, lhs=v363, rhs=v365 } -> x0 - v367 Extend { value=v351, kind=I32 } -> x9 - v368 Binop { op=add, lhs=v366, rhs=v367 } -> x0 - v369 BinopI { op=shl, lhs=v362, rhs_imm=32 } -> x3 - v370 Extend { value=v362, kind=I32 } -> x3 - v371 BinopI { op=shl, lhs=v365, rhs_imm=32 } -> x3 - v372 Extend { value=v365, kind=I32 } -> x3 - v373 Binop { op=add, lhs=v362, rhs=v365 } -> x7 - v374 BinopI { op=shl, lhs=v373, rhs_imm=32 } -> x8 - v375 Extend { value=v373, kind=I32 } -> x8 - v376 Binop { op=add, lhs=v373, rhs=v367 } -> x7 - v377 BinopI { op=shl, lhs=v376, rhs_imm=32 } -> x8 - v378 Extend { value=v376, kind=I32 } -> x8 - v379 BinopI { op=shl, lhs=v376, rhs_imm=56 } -> x7 - v380 Extend { value=v378, kind=I8 } -> x7 - v381 Store { addr=v368, disp=0, value=v378, kind=I8 } -> - - terminator Jmp(b72) (exit_acc=v381) + v768 Extend { value=v765, kind=I32 } -> x1 + v769 BinopI { op=add, lhs=v766, rhs_imm=1 } -> x1 + v770 Imm(0) -> x0 + terminator Jmp(b74) (exit_acc=v769) block 74 start_pc=0 - terminator Jmp(b68) + v765 Phi { incoming=[b65:v704, b73:v769], kind=I64 } -> x1 + v766 Extend { value=v765, kind=I32 } -> x0 + v767 BinopI { op=lt, lhs=v766, rhs_imm=2 } -> x2 + terminator Bnz { cond=v767, target=b66, fall=b75 } (exit_acc=v767) block 75 start_pc=0 - v382 Phi { incoming=[b66:v341, b76:v386], kind=I64 } -> x1 - v383 Extend { value=v382, kind=I32 } -> x0 - v384 BinopI { op=lt, lhs=v383, rhs_imm=2 } -> x0 - terminator Bz { cond=v384, target=b78, fall=b77 } (exit_acc=v384) + v773 Imm(0) -> x0 + terminator Return(v773) (exit_acc=v773) block 76 start_pc=0 - v385 Extend { value=v382, kind=I32 } -> x0 - v386 BinopI { op=add, lhs=v385, rhs_imm=1 } -> x1 - v387 Imm(0) -> x0 - terminator Jmp(b75) (exit_acc=v386) + v813 Imm(110) -> x0 + v814 Extend { value=v765, kind=I32 } -> x0 + v815 BinopI { op=mul, lhs=v765, rhs_imm=12 } -> x0 + v816 BinopI { op=shl, lhs=v815, rhs_imm=32 } -> x1 + v817 Extend { value=v815, kind=I32 } -> x1 + v818 BinopI { op=add, lhs=v815, rhs_imm=110 } -> x0 + v819 BinopI { op=shl, lhs=v818, rhs_imm=32 } -> x1 + v820 Extend { value=v818, kind=I32 } -> x1 + v821 Extend { value=v774, kind=I32 } -> x1 + v822 BinopI { op=shl, lhs=v774, rhs_imm=2 } -> x1 + v823 BinopI { op=shl, lhs=v822, rhs_imm=32 } -> x2 + v824 Extend { value=v822, kind=I32 } -> x2 + v825 Binop { op=add, lhs=v818, rhs=v822 } -> x0 + v826 BinopI { op=shl, lhs=v825, rhs_imm=32 } -> x1 + v827 Extend { value=v825, kind=I32 } -> x1 + v828 Extend { value=v782, kind=I32 } -> x1 + v829 Binop { op=add, lhs=v825, rhs=v782 } -> x0 + v830 BinopI { op=shl, lhs=v829, rhs_imm=32 } -> x1 + v831 Extend { value=v829, kind=I32 } -> x0 + terminator Return(v831) (exit_acc=v831) block 77 start_pc=0 - v388 Imm(0) -> x2 - v389 Imm(0) -> x0 - terminator Jmp(b79) (exit_acc=v388) + v746 Imm(80) -> x0 + v747 Extend { value=v696, kind=I32 } -> x0 + v748 BinopI { op=mul, lhs=v696, rhs_imm=12 } -> x0 + v749 BinopI { op=shl, lhs=v748, rhs_imm=32 } -> x1 + v750 Extend { value=v748, kind=I32 } -> x1 + v751 BinopI { op=add, lhs=v748, rhs_imm=80 } -> x0 + v752 BinopI { op=shl, lhs=v751, rhs_imm=32 } -> x1 + v753 Extend { value=v751, kind=I32 } -> x1 + v754 Extend { value=v706, kind=I32 } -> x1 + v755 BinopI { op=shl, lhs=v706, rhs_imm=2 } -> x1 + v756 BinopI { op=shl, lhs=v755, rhs_imm=32 } -> x2 + v757 Extend { value=v755, kind=I32 } -> x2 + v758 Binop { op=add, lhs=v751, rhs=v755 } -> x0 + v759 BinopI { op=shl, lhs=v758, rhs_imm=32 } -> x1 + v760 Extend { value=v758, kind=I32 } -> x1 + v761 Extend { value=v714, kind=I32 } -> x1 + v762 Binop { op=add, lhs=v758, rhs=v714 } -> x0 + v763 BinopI { op=shl, lhs=v762, rhs_imm=32 } -> x1 + v764 Extend { value=v762, kind=I32 } -> x0 + terminator Return(v764) (exit_acc=v764) block 78 start_pc=0 - v390 Imm(0) -> x1 - v391 Imm(0) -> x0 - terminator Jmp(b89) (exit_acc=v390) + v544 Imm(60) -> x0 + v545 Extend { value=v511, kind=I32 } -> x0 + v546 BinopI { op=mul, lhs=v511, rhs_imm=5 } -> x0 + v547 BinopI { op=shl, lhs=v546, rhs_imm=32 } -> x1 + v548 Extend { value=v546, kind=I32 } -> x1 + v549 BinopI { op=add, lhs=v546, rhs_imm=60 } -> x0 + v550 BinopI { op=shl, lhs=v549, rhs_imm=32 } -> x1 + v551 Extend { value=v549, kind=I32 } -> x1 + v552 Extend { value=v521, kind=I32 } -> x1 + v553 Binop { op=add, lhs=v549, rhs=v521 } -> x0 + v554 BinopI { op=shl, lhs=v553, rhs_imm=32 } -> x1 + v555 Extend { value=v553, kind=I32 } -> x0 + terminator Return(v555) (exit_acc=v555) block 79 start_pc=0 - v392 Phi { incoming=[b77:v388, b80:v396], kind=I64 } -> x2 - v393 Extend { value=v392, kind=I32 } -> x0 - v394 BinopI { op=lt, lhs=v393, rhs_imm=3 } -> x0 - terminator Bz { cond=v394, target=b82, fall=b81 } (exit_acc=v394) + v499 Imm(40) -> x0 + v500 Extend { value=v465, kind=I32 } -> x0 + v501 BinopI { op=mul, lhs=v465, rhs_imm=5 } -> x0 + v502 BinopI { op=shl, lhs=v501, rhs_imm=32 } -> x1 + v503 Extend { value=v501, kind=I32 } -> x1 + v504 BinopI { op=add, lhs=v501, rhs_imm=40 } -> x0 + v505 BinopI { op=shl, lhs=v504, rhs_imm=32 } -> x1 + v506 Extend { value=v504, kind=I32 } -> x1 + v507 Extend { value=v475, kind=I32 } -> x1 + v508 Binop { op=add, lhs=v504, rhs=v475 } -> x0 + v509 BinopI { op=shl, lhs=v508, rhs_imm=32 } -> x1 + v510 Extend { value=v508, kind=I32 } -> x0 + terminator Return(v510) (exit_acc=v510) block 80 start_pc=0 - v395 Extend { value=v392, kind=I32 } -> x0 - v396 BinopI { op=add, lhs=v395, rhs_imm=1 } -> x2 - v397 Imm(0) -> x0 - terminator Jmp(b79) (exit_acc=v396) + v338 Imm(28) -> x0 + v339 Extend { value=v316, kind=I32 } -> x0 + v340 BinopI { op=add, lhs=v316, rhs_imm=28 } -> x0 + v341 BinopI { op=shl, lhs=v340, rhs_imm=32 } -> x1 + v342 Extend { value=v340, kind=I32 } -> x0 + terminator Return(v342) (exit_acc=v342) block 81 start_pc=0 - v398 Imm(0) -> x6 - v399 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v398) + v311 Imm(20) -> x0 + v312 Extend { value=v288, kind=I32 } -> x0 + v313 BinopI { op=add, lhs=v288, rhs_imm=20 } -> x0 + v314 BinopI { op=shl, lhs=v313, rhs_imm=32 } -> x1 + v315 Extend { value=v313, kind=I32 } -> x0 + terminator Return(v315) (exit_acc=v315) block 82 start_pc=0 - terminator Jmp(b76) + terminator Jmp(b22) block 83 start_pc=0 - v400 Phi { incoming=[b81:v398, b84:v404], kind=I64 } -> x6 - v401 Extend { value=v400, kind=I32 } -> x0 - v402 BinopI { op=lt, lhs=v401, rhs_imm=4 } -> x0 - terminator Bz { cond=v402, target=b86, fall=b85 } (exit_acc=v402) + terminator Jmp(b26) block 84 start_pc=0 - v403 Extend { value=v400, kind=I32 } -> x0 - v404 BinopI { op=add, lhs=v403, rhs_imm=1 } -> x6 - v405 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v404) + terminator Jmp(b31) block 85 start_pc=0 - v406 LocalAddr(-14) -> x0 - v407 BinopI { op=add, lhs=v406, rhs_imm=40 } -> x7 - v408 Load { addr=v406, disp=40, kind=I64 } -> x0 - v409 Imm(0) -> x7 - v410 Extend { value=v382, kind=I32 } -> x7 - v411 BinopI { op=mul, lhs=v410, rhs_imm=12 } -> x7 - v412 Binop { op=add, lhs=v408, rhs=v411 } -> x0 - v413 Extend { value=v392, kind=I32 } -> x8 - v414 BinopI { op=shl, lhs=v413, rhs_imm=2 } -> x8 - v415 Binop { op=add, lhs=v412, rhs=v414 } -> x0 - v416 Extend { value=v400, kind=I32 } -> x9 - v417 Binop { op=add, lhs=v415, rhs=v416 } -> x0 - v418 Load { addr=v417, disp=0, kind=I8 } -> x0 - v419 BinopI { op=shl, lhs=v411, rhs_imm=32 } -> x3 - v420 Extend { value=v411, kind=I32 } -> x3 - v421 BinopI { op=shl, lhs=v414, rhs_imm=32 } -> x3 - v422 Extend { value=v414, kind=I32 } -> x3 - v423 Binop { op=add, lhs=v411, rhs=v414 } -> x7 - v424 BinopI { op=shl, lhs=v423, rhs_imm=32 } -> x8 - v425 Extend { value=v423, kind=I32 } -> x8 - v426 Binop { op=add, lhs=v423, rhs=v416 } -> x7 - v427 BinopI { op=shl, lhs=v426, rhs_imm=32 } -> x8 - v428 Extend { value=v426, kind=I32 } -> x8 - v429 BinopI { op=shl, lhs=v426, rhs_imm=56 } -> x7 - v430 Extend { value=v428, kind=I8 } -> x7 - v431 Binop { op=ne, lhs=v418, rhs=v430 } -> x0 - terminator Bz { cond=v431, target=b88, fall=b87 } (exit_acc=v431) + terminator Jmp(b38) block 86 start_pc=0 - terminator Jmp(b80) + terminator Jmp(b36) block 87 start_pc=0 - v432 Imm(80) -> x0 - v433 Extend { value=v382, kind=I32 } -> x0 - v434 BinopI { op=mul, lhs=v382, rhs_imm=12 } -> x0 - v435 BinopI { op=shl, lhs=v434, rhs_imm=32 } -> x1 - v436 Extend { value=v434, kind=I32 } -> x1 - v437 BinopI { op=add, lhs=v434, rhs_imm=80 } -> x0 - v438 BinopI { op=shl, lhs=v437, rhs_imm=32 } -> x1 - v439 Extend { value=v437, kind=I32 } -> x1 - v440 Extend { value=v392, kind=I32 } -> x1 - v441 BinopI { op=shl, lhs=v392, rhs_imm=2 } -> x1 - v442 BinopI { op=shl, lhs=v441, rhs_imm=32 } -> x2 - v443 Extend { value=v441, kind=I32 } -> x2 - v444 Binop { op=add, lhs=v437, rhs=v441 } -> x0 - v445 BinopI { op=shl, lhs=v444, rhs_imm=32 } -> x1 - v446 Extend { value=v444, kind=I32 } -> x1 - v447 Extend { value=v400, kind=I32 } -> x1 - v448 Binop { op=add, lhs=v444, rhs=v400 } -> x0 - v449 BinopI { op=shl, lhs=v448, rhs_imm=32 } -> x1 - v450 Extend { value=v448, kind=I32 } -> x0 - terminator Return(v450) (exit_acc=v450) + terminator Jmp(b45) block 88 start_pc=0 - terminator Jmp(b84) + terminator Jmp(b43) block 89 start_pc=0 - v451 Phi { incoming=[b78:v390, b90:v455], kind=I64 } -> x1 - v452 Extend { value=v451, kind=I32 } -> x0 - v453 BinopI { op=lt, lhs=v452, rhs_imm=2 } -> x0 - terminator Bz { cond=v453, target=b92, fall=b91 } (exit_acc=v453) + terminator Jmp(b53) block 90 start_pc=0 - v454 Extend { value=v451, kind=I32 } -> x0 - v455 BinopI { op=add, lhs=v454, rhs_imm=1 } -> x1 - v456 Imm(0) -> x0 - terminator Jmp(b89) (exit_acc=v455) + terminator Jmp(b51) block 91 start_pc=0 - v457 Imm(0) -> x2 - v458 Imm(0) -> x0 - terminator Jmp(b93) (exit_acc=v457) + terminator Jmp(b63) block 92 start_pc=0 - v459 Imm(0) -> x0 - terminator Return(v459) (exit_acc=v459) + terminator Jmp(b61) block 93 start_pc=0 - v460 Phi { incoming=[b91:v457, b94:v464], kind=I64 } -> x2 - v461 Extend { value=v460, kind=I32 } -> x0 - v462 BinopI { op=lt, lhs=v461, rhs_imm=3 } -> x0 - terminator Bz { cond=v462, target=b96, fall=b95 } (exit_acc=v462) + terminator Jmp(b59) block 94 start_pc=0 - v463 Extend { value=v460, kind=I32 } -> x0 - v464 BinopI { op=add, lhs=v463, rhs_imm=1 } -> x2 - v465 Imm(0) -> x0 - terminator Jmp(b93) (exit_acc=v464) + terminator Jmp(b73) block 95 start_pc=0 - v466 Imm(0) -> x6 - v467 Imm(0) -> x0 - terminator Jmp(b97) (exit_acc=v466) + terminator Jmp(b71) block 96 start_pc=0 - terminator Jmp(b90) - block 97 start_pc=0 - v468 Phi { incoming=[b95:v466, b98:v472], kind=I64 } -> x6 - v469 Extend { value=v468, kind=I32 } -> x0 - v470 BinopI { op=lt, lhs=v469, rhs_imm=4 } -> x0 - terminator Bz { cond=v470, target=b100, fall=b99 } (exit_acc=v470) - block 98 start_pc=0 - v471 Extend { value=v468, kind=I32 } -> x0 - v472 BinopI { op=add, lhs=v471, rhs_imm=1 } -> x6 - v473 Imm(0) -> x0 - terminator Jmp(b97) (exit_acc=v472) - block 99 start_pc=0 - v474 LocalAddr(-14) -> x0 - v475 BinopI { op=add, lhs=v474, rhs_imm=40 } -> x7 - v476 Load { addr=v474, disp=40, kind=I64 } -> x0 - v477 Extend { value=v451, kind=I32 } -> x7 - v478 BinopI { op=mul, lhs=v477, rhs_imm=12 } -> x7 - v479 Binop { op=add, lhs=v476, rhs=v478 } -> x0 - v480 Extend { value=v460, kind=I32 } -> x8 - v481 BinopI { op=shl, lhs=v480, rhs_imm=2 } -> x8 - v482 Binop { op=add, lhs=v479, rhs=v481 } -> x0 - v483 Extend { value=v468, kind=I32 } -> x9 - v484 Binop { op=add, lhs=v482, rhs=v483 } -> x0 - v485 Load { addr=v484, disp=0, kind=I8 } -> x0 - v486 BinopI { op=shl, lhs=v478, rhs_imm=32 } -> x3 - v487 Extend { value=v478, kind=I32 } -> x3 - v488 BinopI { op=shl, lhs=v481, rhs_imm=32 } -> x3 - v489 Extend { value=v481, kind=I32 } -> x3 - v490 Binop { op=add, lhs=v478, rhs=v481 } -> x7 - v491 BinopI { op=shl, lhs=v490, rhs_imm=32 } -> x8 - v492 Extend { value=v490, kind=I32 } -> x8 - v493 Binop { op=add, lhs=v490, rhs=v483 } -> x7 - v494 BinopI { op=shl, lhs=v493, rhs_imm=32 } -> x8 - v495 Extend { value=v493, kind=I32 } -> x8 - v496 BinopI { op=shl, lhs=v493, rhs_imm=56 } -> x7 - v497 Extend { value=v495, kind=I8 } -> x7 - v498 Binop { op=ne, lhs=v485, rhs=v497 } -> x0 - terminator Bz { cond=v498, target=b102, fall=b101 } (exit_acc=v498) - block 100 start_pc=0 - terminator Jmp(b94) - block 101 start_pc=0 - v499 Imm(110) -> x0 - v500 Extend { value=v451, kind=I32 } -> x0 - v501 BinopI { op=mul, lhs=v451, rhs_imm=12 } -> x0 - v502 BinopI { op=shl, lhs=v501, rhs_imm=32 } -> x1 - v503 Extend { value=v501, kind=I32 } -> x1 - v504 BinopI { op=add, lhs=v501, rhs_imm=110 } -> x0 - v505 BinopI { op=shl, lhs=v504, rhs_imm=32 } -> x1 - v506 Extend { value=v504, kind=I32 } -> x1 - v507 Extend { value=v460, kind=I32 } -> x1 - v508 BinopI { op=shl, lhs=v460, rhs_imm=2 } -> x1 - v509 BinopI { op=shl, lhs=v508, rhs_imm=32 } -> x2 - v510 Extend { value=v508, kind=I32 } -> x2 - v511 Binop { op=add, lhs=v504, rhs=v508 } -> x0 - v512 BinopI { op=shl, lhs=v511, rhs_imm=32 } -> x1 - v513 Extend { value=v511, kind=I32 } -> x1 - v514 Extend { value=v468, kind=I32 } -> x1 - v515 Binop { op=add, lhs=v511, rhs=v468 } -> x0 - v516 BinopI { op=shl, lhs=v515, rhs_imm=32 } -> x1 - v517 Extend { value=v515, kind=I32 } -> x0 - terminator Return(v517) (exit_acc=v517) - block 102 start_pc=0 - terminator Jmp(b98) + terminator Jmp(b69) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_string_literal.ssa b/tests/snapshots/ssa/sizeof_string_literal.ssa index f228a914a..3700b4b8f 100644 --- a/tests/snapshots/ssa/sizeof_string_literal.ssa +++ b/tests/snapshots/ssa/sizeof_string_literal.ssa @@ -5,51 +5,51 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(11) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(12) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(13) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(5) -> x0 + v14 Imm(21474836480) -> x0 + v15 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v15) block 7 start_pc=0 - v8 Imm(14) -> x0 - terminator Return(v8) (exit_acc=v8) + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v2 Imm(11) -> x0 + terminator Return(v2) (exit_acc=v2) block 9 start_pc=0 - v10 Imm(15) -> x0 - terminator Return(v10) (exit_acc=v10) + v4 Imm(12) -> x0 + terminator Return(v4) (exit_acc=v4) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v6 Imm(13) -> x0 + terminator Return(v6) (exit_acc=v6) block 11 start_pc=0 - v12 Imm(16) -> x0 - terminator Return(v12) (exit_acc=v12) + v8 Imm(14) -> x0 + terminator Return(v8) (exit_acc=v8) block 12 start_pc=0 - v13 Imm(5) -> x0 - v14 Imm(21474836480) -> x0 - v15 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v15) + v10 Imm(15) -> x0 + terminator Return(v10) (exit_acc=v10) block 13 start_pc=0 + v12 Imm(16) -> x0 + terminator Return(v12) (exit_acc=v12) + block 14 start_pc=0 v16 Imm(17) -> x0 terminator Return(v16) (exit_acc=v16) - block 14 start_pc=0 - v17 Imm(0) -> x0 - terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sizeof_typedef_array.ssa b/tests/snapshots/ssa/sizeof_typedef_array.ssa index 8ffba7bab..b5ca67291 100644 --- a/tests/snapshots/ssa/sizeof_typedef_array.ssa +++ b/tests/snapshots/ssa/sizeof_typedef_array.ssa @@ -9,45 +9,45 @@ fn ent_pc=0 n_params=0 variadic=false locals=69 v1 Imm(512) -> x0 v2 Imm(2199023255552) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(40) -> x0 v6 Imm(171798691840) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 + v9 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v9) block 3 start_pc=0 - v8 Imm(2) -> x0 - terminator Return(v8) (exit_acc=v8) + v11 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v11) block 4 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v9) + v13 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v13) block 5 start_pc=0 - v10 Imm(3) -> x0 - terminator Return(v10) (exit_acc=v10) + v15 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v15) block 6 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v11) + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) block 7 start_pc=0 - v12 Imm(4) -> x0 - terminator Return(v12) (exit_acc=v12) + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 8 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v13) + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) block 9 start_pc=0 - v14 Imm(5) -> x0 - terminator Return(v14) (exit_acc=v14) + v10 Imm(3) -> x0 + terminator Return(v10) (exit_acc=v10) block 10 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v15) + v12 Imm(4) -> x0 + terminator Return(v12) (exit_acc=v12) block 11 start_pc=0 + v14 Imm(5) -> x0 + terminator Return(v14) (exit_acc=v14) + block 12 start_pc=0 v16 Imm(6) -> x0 terminator Return(v16) (exit_acc=v16) - block 12 start_pc=0 - v17 Imm(0) -> x0 - terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/slot_coalesce_alloca.ssa b/tests/snapshots/ssa/slot_coalesce_alloca.ssa index 580e272cf..bf2de6730 100644 --- a/tests/snapshots/ssa/slot_coalesce_alloca.ssa +++ b/tests/snapshots/ssa/slot_coalesce_alloca.ssa @@ -7,57 +7,57 @@ fn ent_pc=0 n_params=1 variadic=false locals=27 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 - v3 Imm(0) -> x8 + v3 Imm(0) -> x9 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v10], kind=I64 } -> x0 - v7 Extend { value=v6, kind=I32 } -> x1 - v8 BinopI { op=lt, lhs=v7, rhs_imm=24 } -> x1 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v12 LocalAddr(-24) -> x2 + v13 Extend { value=v6, kind=I32 } -> x6 + v14 BinopI { op=shl, lhs=v7, rhs_imm=3 } -> x6 + v15 Binop { op=add, lhs=v12, rhs=v14 } -> x2 + v16 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x6 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x8 + v18 Extend { value=v16, kind=I32 } -> x6 + v19 LoadLocal { off=2, kind=I32 } -> x8 + v20 Binop { op=mul, lhs=v18, rhs=v1 } -> x6 + v21 Store { addr=v15, disp=0, value=v20, kind=I64, volatile } -> - + terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 v9 Extend { value=v6, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x0 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x0 v11 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v10) + terminator Jmp(b3) (exit_acc=v10) block 3 start_pc=0 - v12 LocalAddr(-24) -> x1 - v13 Extend { value=v6, kind=I32 } -> x2 - v14 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x6 - v15 Binop { op=add, lhs=v12, rhs=v14 } -> x1 - v16 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x2 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x6 - v18 Extend { value=v16, kind=I32 } -> x2 - v19 LoadLocal { off=2, kind=I32 } -> x6 - v20 Binop { op=mul, lhs=v18, rhs=v1 } -> x2 - v21 Store { addr=v15, disp=0, value=v20, kind=I64, volatile } -> - - terminator Jmp(b2) (exit_acc=v21) + v6 Phi { incoming=[b0:v3, b2:v10], kind=I64 } -> x0 + v7 Extend { value=v6, kind=I32 } -> x1 + v8 BinopI { op=lt, lhs=v7, rhs_imm=24 } -> x2 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) block 4 start_pc=0 v22 Imm(0) -> x1 v23 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v22) + terminator Jmp(b7) (exit_acc=v22) block 5 start_pc=0 - v24 Phi { incoming=[b4:v22, b6:v29], kind=I64 } -> x1 - v25 Phi { incoming=[b4:v3, b6:v37], kind=I64 } -> x8 - v26 Extend { value=v24, kind=I32 } -> x0 - v27 BinopI { op=lt, lhs=v26, rhs_imm=24 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v31 LoadLocal { off=-25, kind=I64 } -> x2 + v32 LocalAddr(-24) -> x2 + v33 Extend { value=v24, kind=I32 } -> x6 + v34 BinopI { op=shl, lhs=v26, rhs_imm=3 } -> x6 + v35 Binop { op=add, lhs=v32, rhs=v34 } -> x2 + v36 Load { addr=v35, disp=0, kind=I64, volatile } -> x2 + v37 Binop { op=add, lhs=v25, rhs=v36 } -> x9 + v38 Imm(0) -> x2 + terminator Jmp(b6) (exit_acc=v37) block 6 start_pc=0 - v28 Extend { value=v24, kind=I32 } -> x0 - v29 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x1 + v28 Extend { value=v24, kind=I32 } -> x1 + v29 BinopI { op=add, lhs=v26, rhs_imm=1 } -> x1 v30 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v29) + terminator Jmp(b7) (exit_acc=v29) block 7 start_pc=0 - v31 LoadLocal { off=-25, kind=I64 } -> x0 - v32 LocalAddr(-24) -> x0 - v33 Extend { value=v24, kind=I32 } -> x2 - v34 BinopI { op=shl, lhs=v33, rhs_imm=3 } -> x2 - v35 Binop { op=add, lhs=v32, rhs=v34 } -> x0 - v36 Load { addr=v35, disp=0, kind=I64, volatile } -> x0 - v37 Binop { op=add, lhs=v25, rhs=v36 } -> x8 - v38 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v37) + v24 Phi { incoming=[b4:v22, b6:v29], kind=I64 } -> x1 + v25 Phi { incoming=[b4:v3, b6:v37], kind=I64 } -> x9 + v26 Extend { value=v24, kind=I32 } -> x0 + v27 BinopI { op=lt, lhs=v26, rhs_imm=24 } -> x2 + terminator Bnz { cond=v27, target=b5, fall=b8 } (exit_acc=v27) block 8 start_pc=0 v39 LoadLocal { off=-25, kind=I64 } -> x0 terminator Return(v25) (exit_acc=v25) @@ -117,17 +117,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=1042 v48 StoreLocal { off=-14, value=v47, kind=I64 } -> - v49 Imm(0) -> x0 v50 StoreLocal { off=-15, value=v49, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v50) + terminator Jmp(b3) (exit_acc=v50) block 1 start_pc=0 - v51 LoadLocal { off=-15, kind=I32 } -> x0 - v52 BinopI { op=lt, lhs=v51, rhs_imm=8 } -> x0 - terminator Bz { cond=v52, target=b4, fall=b3 } (exit_acc=v52) - block 2 start_pc=0 - v53 LoadLocal { off=-15, kind=I32 } -> x0 - v54 BinopI { op=add, lhs=v53, rhs_imm=1 } -> x0 - v55 StoreLocal { off=-15, value=v54, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v55) - block 3 start_pc=0 v56 LoadLocal { off=-14, kind=I64 } -> x0 v57 LoadLocal { off=-15, kind=I32 } -> x1 v58 BinopI { op=shl, lhs=v57, rhs_imm=3 } -> x2 @@ -136,11 +127,20 @@ fn ent_pc=1 n_params=0 variadic=false locals=1042 v61 Binop { op=add, lhs=v60, rhs=v57 } -> x2 v62 StoreIndexed { base=v56, index=v57, scale=8, value=v61, kind=I64 } -> - terminator Jmp(b2) (exit_acc=v62) + block 2 start_pc=0 + v53 LoadLocal { off=-15, kind=I32 } -> x0 + v54 BinopI { op=add, lhs=v53, rhs_imm=1 } -> x0 + v55 StoreLocal { off=-15, value=v54, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v55) + block 3 start_pc=0 + v51 LoadLocal { off=-15, kind=I32 } -> x0 + v52 BinopI { op=lt, lhs=v51, rhs_imm=8 } -> x0 + terminator Bnz { cond=v52, target=b1, fall=b4 } (exit_acc=v52) block 4 start_pc=0 - v63 LoadLocal { off=-13, kind=I64 } -> x0 - v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x1 - v65 Extend { value=v63, kind=I32 } -> x7 - v66 Call { target_pc=0, args=[v65], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v63 LoadLocal { off=-13, kind=I64 } -> x7 + v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x0 + v65 Extend { value=v63, kind=I32 } -> x0 + v66 Call { target_pc=0, args=[v63], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v67 StoreLocal { off=-16, value=v66, kind=I64 } -> - v68 LoadLocal { off=-16, kind=I64 } -> x0 v69 BinopI { op=eq, lhs=v68, rhs_imm=0 } -> x0 @@ -151,17 +151,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=1042 block 6 start_pc=0 v71 Imm(0) -> x0 v72 StoreLocal { off=-17, value=v71, kind=I32 } -> - - terminator Jmp(b7) (exit_acc=v72) + terminator Jmp(b9) (exit_acc=v72) block 7 start_pc=0 - v73 LoadLocal { off=-17, kind=I32 } -> x0 - v74 BinopI { op=lt, lhs=v73, rhs_imm=8 } -> x0 - terminator Bz { cond=v74, target=b10, fall=b9 } (exit_acc=v74) - block 8 start_pc=0 - v75 LoadLocal { off=-17, kind=I32 } -> x0 - v76 BinopI { op=add, lhs=v75, rhs_imm=1 } -> x0 - v77 StoreLocal { off=-17, value=v76, kind=I32 } -> - - terminator Jmp(b7) (exit_acc=v77) - block 9 start_pc=0 v78 LoadLocal { off=-14, kind=I64 } -> x0 v79 LoadLocal { off=-17, kind=I32 } -> x1 v80 BinopI { op=shl, lhs=v79, rhs_imm=3 } -> x2 @@ -170,7 +161,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=1042 v83 LoadLocal { off=-13, kind=I64 } -> x2 v84 Binop { op=add, lhs=v83, rhs=v79 } -> x1 v85 Binop { op=ne, lhs=v82, rhs=v84 } -> x0 - terminator Bz { cond=v85, target=b12, fall=b11 } (exit_acc=v85) + terminator Bnz { cond=v85, target=b11, fall=b8 } (exit_acc=v85) + block 8 start_pc=0 + v75 LoadLocal { off=-17, kind=I32 } -> x0 + v76 BinopI { op=add, lhs=v75, rhs_imm=1 } -> x0 + v77 StoreLocal { off=-17, value=v76, kind=I32 } -> - + terminator Jmp(b9) (exit_acc=v77) + block 9 start_pc=0 + v73 LoadLocal { off=-17, kind=I32 } -> x0 + v74 BinopI { op=lt, lhs=v73, rhs_imm=8 } -> x0 + terminator Bnz { cond=v74, target=b7, fall=b10 } (exit_acc=v74) block 10 start_pc=0 v87 Imm(0) -> x0 terminator Return(v87) (exit_acc=v87) diff --git a/tests/snapshots/ssa/slot_coalesce_declared.ssa b/tests/snapshots/ssa/slot_coalesce_declared.ssa index 0c5d2a11c..dfde3786f 100644 --- a/tests/snapshots/ssa/slot_coalesce_declared.ssa +++ b/tests/snapshots/ssa/slot_coalesce_declared.ssa @@ -8,19 +8,19 @@ fn ent_pc=0 n_params=2 variadic=false locals=4 v2 LoadLocal { off=3, kind=I64 } -> x1 v3 Store { addr=v1, disp=0, value=v2, kind=I64 } -> - v4 LocalAddr(-4) -> x0 - v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x1 - v6 LoadLocal { off=3, kind=I64 } -> x1 - v7 BinopI { op=xor, lhs=v6, rhs_imm=21845 } -> x1 + v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x2 + v6 LoadLocal { off=3, kind=I64 } -> x2 + v7 BinopI { op=xor, lhs=v2, rhs_imm=21845 } -> x2 v8 Store { addr=v4, disp=8, value=v7, kind=I64 } -> - v9 LocalAddr(-4) -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x1 - v11 LoadLocal { off=3, kind=I64 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=9 } -> x1 + v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x2 + v11 LoadLocal { off=3, kind=I64 } -> x2 + v12 BinopI { op=add, lhs=v2, rhs_imm=9 } -> x2 v13 Store { addr=v9, disp=16, value=v12, kind=I64 } -> - v14 LocalAddr(-4) -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=24 } -> x1 - v16 LoadLocal { off=3, kind=I64 } -> x1 - v17 BinopI { op=mul, lhs=v16, rhs_imm=3 } -> x1 + v15 BinopI { op=add, lhs=v14, rhs_imm=24 } -> x2 + v16 LoadLocal { off=3, kind=I64 } -> x2 + v17 BinopI { op=mul, lhs=v2, rhs_imm=3 } -> x1 v18 Store { addr=v14, disp=24, value=v17, kind=I64 } -> - v19 LoadLocal { off=2, kind=I64 } -> x0 v20 LocalAddr(-4) -> x1 @@ -58,20 +58,8 @@ fn ent_pc=2 n_params=1 variadic=false locals=2 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v19], kind=I64 } -> x0 - v8 LoadLocal { off=-2, kind=I64 } -> x2 - v9 LoadLocal { off=2, kind=I64 } -> x2 - v10 Binop { op=lt, lhs=v6, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) - block 2 start_pc=0 - v11 LoadLocal { off=-2, kind=I64 } -> x2 - v12 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) - block 3 start_pc=0 v14 LoadLocal { off=-1, kind=I64 } -> x2 v15 Imm(3) -> x2 v16 LoadLocal { off=-2, kind=I64 } -> x2 @@ -80,6 +68,18 @@ fn ent_pc=2 n_params=1 variadic=false locals=2 v19 Binop { op=add, lhs=v7, rhs=v18 } -> x0 v20 Imm(0) -> x2 terminator Jmp(b2) (exit_acc=v19) + block 2 start_pc=0 + v11 LoadLocal { off=-2, kind=I64 } -> x2 + v12 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 + v13 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 + v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b2:v19], kind=I64 } -> x0 + v8 LoadLocal { off=-2, kind=I64 } -> x2 + v9 LoadLocal { off=2, kind=I64 } -> x2 + v10 Binop { op=lt, lhs=v6, rhs=v1 } -> x2 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v21 LoadLocal { off=-1, kind=I64 } -> x1 terminator Return(v7) (exit_acc=v7) @@ -94,30 +94,18 @@ fn ent_pc=3 n_params=1 variadic=false locals=11 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b3) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v49], kind=I64 } -> x0 - v8 LoadLocal { off=-2, kind=I64 } -> x2 - v9 LoadLocal { off=2, kind=I64 } -> x2 - v10 Binop { op=lt, lhs=v6, rhs=v1 } -> x2 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) - block 2 start_pc=0 - v11 LoadLocal { off=-2, kind=I64 } -> x2 - v12 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v13 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v12) - block 3 start_pc=0 v14 Imm(3) -> x2 v15 LoadLocal { off=-2, kind=I64 } -> x2 v16 BinopI { op=mul, lhs=v6, rhs_imm=3 } -> x2 v17 Imm(0) -> x6 v18 Imm(7) -> x6 - v19 Imm(0) -> x8 - v20 LoadLocal { off=-1, kind=I64 } -> x8 - v21 LoadLocal { off=-3, kind=I64 } -> x8 - v22 LoadLocal { off=-4, kind=I64 } -> x8 - v23 Binop { op=add, lhs=v16, rhs=v18 } -> x6 + v19 Imm(0) -> x6 + v20 LoadLocal { off=-1, kind=I64 } -> x6 + v21 LoadLocal { off=-3, kind=I64 } -> x6 + v22 LoadLocal { off=-4, kind=I64 } -> x6 + v23 BinopI { op=add, lhs=v16, rhs_imm=7 } -> x6 v24 Binop { op=add, lhs=v7, rhs=v23 } -> x0 v25 Imm(0) -> x6 v26 Imm(0) -> x6 @@ -146,6 +134,18 @@ fn ent_pc=3 n_params=1 variadic=false locals=11 v49 Binop { op=add, lhs=v38, rhs=v45 } -> x0 v50 Imm(0) -> x2 terminator Jmp(b2) (exit_acc=v49) + block 2 start_pc=0 + v11 LoadLocal { off=-2, kind=I64 } -> x2 + v12 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 + v13 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 + v6 Phi { incoming=[b0:v3, b2:v12], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b2:v49], kind=I64 } -> x0 + v8 LoadLocal { off=-2, kind=I64 } -> x2 + v9 LoadLocal { off=2, kind=I64 } -> x2 + v10 Binop { op=lt, lhs=v6, rhs=v1 } -> x2 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v51 LoadLocal { off=-1, kind=I64 } -> x1 terminator Return(v7) (exit_acc=v7) @@ -354,229 +354,391 @@ fn ent_pc=7 n_params=0 variadic=false locals=60 v5 Imm(0) -> x1 v6 Imm(305441741) -> x1 v7 StoreLocal { off=-2, value=v6, kind=I64 } -> - - v8 Imm(0) -> x2 - v9 LocalAddr(-2) -> x2 - v10 Imm(0) -> x6 - v11 LoadLocal { off=-4, kind=I64 } -> x6 - v12 Load { addr=v9, disp=0, kind=I64 } -> x6 - v13 BinopI { op=xor, lhs=v12, rhs_imm=65261 } -> x6 + v8 Imm(0) -> x1 + v9 LocalAddr(-2) -> x1 + v10 Imm(0) -> x2 + v11 LoadLocal { off=-4, kind=I64 } -> x2 + v12 Load { addr=v9, disp=0, kind=I64 } -> x2 + v13 BinopI { op=xor, lhs=v12, rhs_imm=65261 } -> x2 v14 Store { addr=v9, disp=0, value=v13, kind=I64 } -> - - v15 LoadLocal { off=-3, kind=I64 } -> x2 - v16 BinopI { op=xor, lhs=v6, rhs_imm=65261 } -> x1 - v17 Imm(0) -> x2 + v15 LoadLocal { off=-3, kind=I64 } -> x1 + v16 Imm(305419552) -> x1 + v17 Imm(0) -> x1 v18 Extend { value=v4, kind=I32 } -> x0 - v19 Imm(0) -> x3 - v20 Imm(0) -> x2 - terminator Bz { cond=v18, target=b23, fall=b1 } (exit_acc=v18) + v19 Imm(0) -> x2 + v20 Imm(0) -> x1 + terminator Bz { cond=v18, target=b24, fall=b1 } (exit_acc=v18) block 1 start_pc=0 v21 LoadLocal { off=-2, kind=I64 } -> x0 - v22 LoadLocal { off=-3, kind=I64 } -> x2 - v23 Binop { op=eq, lhs=v21, rhs=v16 } -> x0 - v24 BinopI { op=ne, lhs=v23, rhs_imm=0 } -> x3 + v22 LoadLocal { off=-3, kind=I64 } -> x1 + v23 BinopI { op=eq, lhs=v21, rhs_imm=305419552 } -> x0 + v24 BinopI { op=ne, lhs=v23, rhs_imm=0 } -> x2 v25 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v24) block 2 start_pc=0 - v26 Phi { incoming=[b23:v19, b1:v24], kind=I64 } -> x3 + v26 Phi { incoming=[b24:v19, b1:v24], kind=I64 } -> x2 v27 LoadLocal { off=-41, kind=I64 } -> x0 v28 Imm(0) -> x0 - v29 Imm(0) -> x9 - v30 Imm(0) -> x0 - v31 Imm(0) -> x0 - v32 Imm(0) -> x0 + v29 Imm(0) -> x0 + v30 Imm(0) -> x1 + v31 Imm(0) -> x1 + v32 Imm(0) -> x1 terminator Jmp(b3) (exit_acc=v29) block 3 start_pc=0 - v33 Phi { incoming=[b2:v29, b4:v38], kind=I64 } -> x0 - v34 Phi { incoming=[b2:v29, b4:v54], kind=I64 } -> x1 - v35 Extend { value=v33, kind=I32 } -> x2 - v36 BinopI { op=lt, lhs=v35, rhs_imm=6 } -> x2 - terminator Bz { cond=v36, target=b6, fall=b5 } (exit_acc=v36) + v33 Imm(0) -> x0 + v34 Imm(1) -> x0 + v35 Imm(0) -> x0 + v36 Imm(0) -> x0 + v37 Imm(0) -> x0 + v38 Imm(0) -> x0 + v39 Imm(1000) -> x0 + v40 Imm(1000) -> x0 + v41 Imm(4294967296000) -> x0 + v42 Imm(1000) -> x0 + v43 Imm(0) -> x1 + v44 LoadLocal { off=-12, kind=I64 } -> x1 + v45 Imm(0) -> x1 + v46 Imm(1000) -> x1 + v47 Imm(4294967296000) -> x1 + v48 Imm(1000) -> x1 + v49 Imm(1000) -> x1 + v50 Imm(0) -> x1 + v51 Imm(0) -> x1 + v52 Imm(1) -> x1 + v53 Imm(0) -> x1 + v54 Imm(1) -> x1 + v55 Imm(1) -> x1 + v56 Imm(0) -> x1 + v57 Imm(1) -> x1 + v58 Imm(8) -> x1 + v59 Imm(0) -> x1 + v60 Imm(1000) -> x1 + v61 Imm(1001) -> x1 + v62 Imm(4299262263296) -> x1 + v63 Imm(1001) -> x1 + v64 Imm(0) -> x6 + v65 LoadLocal { off=-12, kind=I64 } -> x6 + v66 Imm(1) -> x6 + v67 Imm(1001) -> x6 + v68 Imm(4299262263296) -> x6 + v69 Imm(1001) -> x6 + v70 Imm(2001) -> x6 + v71 Imm(0) -> x6 + v72 Imm(1) -> x6 + v73 Imm(2) -> x6 + v74 Imm(0) -> x6 + v75 Imm(2) -> x6 + v76 Imm(1) -> x6 + v77 Imm(0) -> x6 + v78 Imm(2) -> x6 + v79 Imm(16) -> x6 + v80 Imm(0) -> x6 + v81 Imm(1000) -> x6 + v82 Imm(1002) -> x6 + v83 Imm(4303557230592) -> x6 + v84 Imm(1002) -> x6 + v85 Imm(0) -> x7 + v86 LoadLocal { off=-12, kind=I64 } -> x7 + v87 Imm(2) -> x7 + v88 Imm(1002) -> x7 + v89 Imm(4303557230592) -> x7 + v90 Imm(1002) -> x7 + v91 Imm(3003) -> x7 + v92 Imm(0) -> x7 + v93 Imm(2) -> x7 + v94 Imm(3) -> x7 + v95 Imm(0) -> x7 + v96 Imm(3) -> x7 + v97 Imm(1) -> x7 + v98 Imm(0) -> x7 + v99 Imm(3) -> x7 + v100 Imm(24) -> x7 + v101 Imm(0) -> x7 + v102 Imm(1000) -> x7 + v103 Imm(1003) -> x7 + v104 Imm(4307852197888) -> x7 + v105 Imm(1003) -> x7 + v106 Imm(0) -> x8 + v107 LoadLocal { off=-12, kind=I64 } -> x8 + v108 Imm(3) -> x8 + v109 Imm(1003) -> x8 + v110 Imm(4307852197888) -> x8 + v111 Imm(1003) -> x8 + v112 Imm(4006) -> x8 + v113 Imm(0) -> x8 + v114 Imm(3) -> x8 + v115 Imm(4) -> x8 + v116 Imm(0) -> x8 + v117 Imm(4) -> x8 + v118 Imm(1) -> x8 + v119 Imm(0) -> x8 + v120 Imm(4) -> x8 + v121 Imm(32) -> x8 + v122 Imm(0) -> x8 + v123 Imm(1000) -> x8 + v124 Imm(1004) -> x8 + v125 Imm(4312147165184) -> x8 + v126 Imm(1004) -> x8 + v127 Imm(0) -> x9 + v128 LoadLocal { off=-12, kind=I64 } -> x9 + v129 Imm(4) -> x9 + v130 Imm(1004) -> x9 + v131 Imm(4312147165184) -> x9 + v132 Imm(1004) -> x9 + v133 Imm(5010) -> x9 + v134 Imm(0) -> x9 + v135 Imm(4) -> x9 + v136 Imm(5) -> x9 + v137 Imm(0) -> x9 + v138 Imm(5) -> x9 + v139 Imm(1) -> x9 + v140 Imm(0) -> x9 + v141 Imm(5) -> x9 + v142 Imm(40) -> x9 + v143 Imm(0) -> x9 + v144 Imm(1000) -> x9 + v145 Imm(1005) -> x9 + v146 Imm(4316442132480) -> x9 + v147 Imm(1005) -> x9 + v148 Imm(0) -> x3 + v149 LoadLocal { off=-12, kind=I64 } -> x3 + v150 Imm(5) -> x3 + v151 Imm(1005) -> x3 + v152 Imm(4316442132480) -> x3 + v153 Imm(1005) -> x3 + v154 Imm(6015) -> x3 + v155 Imm(0) -> x3 + v156 Imm(5) -> x3 + v157 Imm(6) -> x3 + v158 Imm(0) -> x3 + v159 Imm(6) -> x3 + v160 Imm(0) -> x3 + terminator Jmp(b4) (exit_acc=v160) block 4 start_pc=0 - v37 Extend { value=v33, kind=I32 } -> x0 - v38 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x0 - v39 Imm(0) -> x2 - terminator Jmp(b3) (exit_acc=v38) + v161 Imm(0) -> x3 + v162 Imm(0) -> x12 + terminator Jmp(b5) (exit_acc=v161) block 5 start_pc=0 - v40 LocalAddr(-10) -> x2 - v41 Extend { value=v33, kind=I32 } -> x6 - v42 BinopI { op=shl, lhs=v41, rhs_imm=3 } -> x7 - v43 Binop { op=add, lhs=v40, rhs=v42 } -> x7 - v44 Imm(1000) -> x7 - v45 BinopI { op=add, lhs=v41, rhs_imm=1000 } -> x7 - v46 BinopI { op=shl, lhs=v45, rhs_imm=32 } -> x8 - v47 Extend { value=v45, kind=I32 } -> x7 - v48 StoreIndexed { base=v40, index=v41, scale=8, value=v47, kind=I64 } -> - - v49 LoadLocal { off=-12, kind=I64 } -> x2 - v50 Extend { value=v33, kind=I32 } -> x2 - v51 BinopI { op=add, lhs=v33, rhs_imm=1000 } -> x2 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x6 - v53 Extend { value=v51, kind=I32 } -> x2 - v54 Binop { op=add, lhs=v34, rhs=v53 } -> x1 - v55 Imm(0) -> x2 - terminator Jmp(b4) (exit_acc=v54) + v163 Imm(0) -> x3 + v164 Imm(1) -> x3 + v165 LoadLocal { off=-11, kind=I64 } -> x3 + v166 Imm(0) -> x3 + v167 Imm(0) -> x3 + v168 Imm(0) -> x3 + v169 Imm(0) -> x3 + v170 LoadLocal { off=-10, kind=I64 } -> x3 + v171 BinopI { op=add, lhs=v42, rhs_imm=0 } -> x0 + v172 Imm(0) -> x3 + v173 Imm(0) -> x3 + v174 Imm(1) -> x3 + v175 Imm(0) -> x3 + v176 Imm(1) -> x3 + v177 Imm(1) -> x3 + v178 LoadLocal { off=-11, kind=I64 } -> x3 + v179 Imm(0) -> x3 + v180 Imm(1) -> x3 + v181 Imm(8) -> x3 + v182 Imm(0) -> x3 + v183 LoadLocal { off=-9, kind=I64 } -> x3 + v184 Binop { op=add, lhs=v171, rhs=v63 } -> x0 + v185 Imm(0) -> x1 + v186 Imm(1) -> x1 + v187 Imm(2) -> x1 + v188 Imm(0) -> x1 + v189 Imm(2) -> x1 + v190 Imm(1) -> x1 + v191 LoadLocal { off=-11, kind=I64 } -> x1 + v192 Imm(0) -> x1 + v193 Imm(2) -> x1 + v194 Imm(16) -> x1 + v195 Imm(0) -> x1 + v196 LoadLocal { off=-8, kind=I64 } -> x1 + v197 Binop { op=add, lhs=v184, rhs=v84 } -> x0 + v198 Imm(0) -> x1 + v199 Imm(2) -> x1 + v200 Imm(3) -> x1 + v201 Imm(0) -> x1 + v202 Imm(3) -> x1 + v203 Imm(1) -> x1 + v204 LoadLocal { off=-11, kind=I64 } -> x1 + v205 Imm(0) -> x1 + v206 Imm(3) -> x1 + v207 Imm(24) -> x1 + v208 Imm(0) -> x1 + v209 LoadLocal { off=-7, kind=I64 } -> x1 + v210 Binop { op=add, lhs=v197, rhs=v105 } -> x0 + v211 Imm(0) -> x1 + v212 Imm(3) -> x1 + v213 Imm(4) -> x1 + v214 Imm(0) -> x1 + v215 Imm(4) -> x1 + v216 Imm(1) -> x1 + v217 LoadLocal { off=-11, kind=I64 } -> x1 + v218 Imm(0) -> x1 + v219 Imm(4) -> x1 + v220 Imm(32) -> x1 + v221 Imm(0) -> x1 + v222 LoadLocal { off=-6, kind=I64 } -> x1 + v223 Binop { op=add, lhs=v210, rhs=v126 } -> x0 + v224 Imm(0) -> x1 + v225 Imm(4) -> x1 + v226 Imm(5) -> x1 + v227 Imm(0) -> x1 + v228 Imm(5) -> x1 + v229 Imm(1) -> x1 + v230 LoadLocal { off=-11, kind=I64 } -> x1 + v231 Imm(0) -> x1 + v232 Imm(5) -> x1 + v233 Imm(40) -> x1 + v234 Imm(0) -> x1 + v235 LoadLocal { off=-5, kind=I64 } -> x1 + v236 Binop { op=add, lhs=v223, rhs=v147 } -> x0 + v237 Imm(0) -> x1 + v238 Imm(5) -> x1 + v239 Imm(6) -> x1 + v240 Imm(0) -> x1 + v241 Imm(6) -> x1 + v242 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v242) block 6 start_pc=0 - v56 Imm(0) -> x2 - v57 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v56) + v243 Extend { value=v26, kind=I32 } -> x1 + v244 Imm(0) -> x3 + v245 Imm(0) -> x2 + terminator Bz { cond=v243, target=b23, fall=b7 } (exit_acc=v243) block 7 start_pc=0 - v58 Phi { incoming=[b6:v56, b8:v63], kind=I64 } -> x2 - v59 Phi { incoming=[b6:v29, b8:v71], kind=I64 } -> x9 - v60 Extend { value=v58, kind=I32 } -> x0 - v61 BinopI { op=lt, lhs=v60, rhs_imm=6 } -> x0 - terminator Bz { cond=v61, target=b10, fall=b9 } (exit_acc=v61) + v246 LoadLocal { off=-11, kind=I64 } -> x1 + v247 LoadLocal { off=-12, kind=I64 } -> x1 + v248 BinopI { op=eq, lhs=v236, rhs_imm=6015 } -> x0 + v249 BinopI { op=ne, lhs=v248, rhs_imm=0 } -> x3 + v250 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v249) block 8 start_pc=0 - v62 Extend { value=v58, kind=I32 } -> x0 - v63 BinopI { op=add, lhs=v62, rhs_imm=1 } -> x2 - v64 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v63) + v251 Phi { incoming=[b23:v244, b7:v249], kind=I64 } -> x3 + v252 LoadLocal { off=-42, kind=I64 } -> x0 + v253 Imm(0) -> x0 + v254 LocalAddr(-46) -> x7 + v255 Imm(0) -> x0 + v256 LoadLocal { off=-47, kind=I64 } -> x0 + v257 Imm(123) -> x6 + v258 Call { target_pc=0, args=[v254, v257], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v259 LocalAddr(-46) -> x0 + v260 LocalAddr(-18) -> x1 + v261 Mcpy { dst=v260, src=v259, size=32 } -> x0 + v262 Imm(21806) -> x0 + v263 Imm(21929) -> x0 + v264 Imm(94184337833984) -> x0 + v265 Imm(132) -> x0 + v266 Imm(566935683072) -> x0 + v267 Imm(22061) -> x0 + v268 Imm(94751273517056) -> x0 + v269 Imm(369) -> x0 + v270 Imm(1584842932224) -> x0 + v271 Imm(22430) -> x0 + v272 Imm(96336116449280) -> x0 + v273 Imm(0) -> x0 + v274 Extend { value=v251, kind=I32 } -> x0 + v275 Imm(0) -> x2 + v276 Imm(0) -> x1 + terminator Bz { cond=v274, target=b22, fall=b9 } (exit_acc=v274) block 9 start_pc=0 - v65 LoadLocal { off=-11, kind=I64 } -> x0 - v66 LocalAddr(-10) -> x0 - v67 Extend { value=v58, kind=I32 } -> x6 - v68 BinopI { op=shl, lhs=v67, rhs_imm=3 } -> x7 - v69 Binop { op=add, lhs=v66, rhs=v68 } -> x7 - v70 LoadIndexed { base=v66, index=v67, scale=8, kind=I64 } -> x0 - v71 Binop { op=add, lhs=v59, rhs=v70 } -> x9 - v72 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v71) + v277 LocalAddr(-18) -> x7 + v278 Call { target_pc=1, args=[v277], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v279 LoadLocal { off=-23, kind=I64 } -> x1 + v280 BinopI { op=eq, lhs=v278, rhs_imm=22430 } -> x0 + v281 BinopI { op=ne, lhs=v280, rhs_imm=0 } -> x2 + v282 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v281) block 10 start_pc=0 - v73 Extend { value=v26, kind=I32 } -> x0 - v74 Imm(0) -> x3 - v75 Imm(0) -> x2 - terminator Bz { cond=v73, target=b24, fall=b11 } (exit_acc=v73) + v283 Phi { incoming=[b22:v275, b9:v281], kind=I64 } -> x2 + v284 LoadLocal { off=-50, kind=I64 } -> x0 + v285 Imm(0) -> x1 + v286 Imm(0) -> x0 + terminator Bz { cond=v283, target=b21, fall=b11 } (exit_acc=v283) block 11 start_pc=0 - v76 LoadLocal { off=-11, kind=I64 } -> x0 - v77 LoadLocal { off=-12, kind=I64 } -> x0 - v78 Binop { op=eq, lhs=v59, rhs=v34 } -> x0 - v79 BinopI { op=ne, lhs=v78, rhs_imm=0 } -> x3 - v80 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v79) + v287 LocalAddr(-18) -> x0 + v288 Load { addr=v287, disp=0, kind=I64 } -> x0 + v289 BinopI { op=eq, lhs=v288, rhs_imm=123 } -> x0 + v290 BinopI { op=ne, lhs=v289, rhs_imm=0 } -> x1 + v291 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v290) block 12 start_pc=0 - v81 Phi { incoming=[b24:v74, b11:v79], kind=I64 } -> x3 - v82 LoadLocal { off=-42, kind=I64 } -> x0 - v83 Imm(0) -> x0 - v84 LocalAddr(-46) -> x7 - v85 Imm(0) -> x0 - v86 LoadLocal { off=-47, kind=I64 } -> x0 - v87 Imm(123) -> x6 - v88 Call { target_pc=0, args=[v84, v87], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v89 LocalAddr(-46) -> x0 - v90 LocalAddr(-18) -> x1 - v91 Mcpy { dst=v90, src=v89, size=32 } -> x0 - v92 Imm(21806) -> x0 - v93 Imm(21929) -> x0 - v94 Imm(94184337833984) -> x0 - v95 Imm(132) -> x0 - v96 Imm(566935683072) -> x0 - v97 Imm(22061) -> x0 - v98 Imm(94751273517056) -> x0 - v99 Imm(369) -> x0 - v100 Imm(1584842932224) -> x0 - v101 Imm(22430) -> x12 - v102 Imm(96336116449280) -> x0 - v103 Imm(0) -> x0 - v104 Extend { value=v81, kind=I32 } -> x0 - v105 Imm(0) -> x3 - v106 Imm(0) -> x1 - terminator Bz { cond=v104, target=b25, fall=b13 } (exit_acc=v104) + v292 Phi { incoming=[b21:v285, b11:v290], kind=I64 } -> x1 + v293 LoadLocal { off=-49, kind=I64 } -> x0 + v294 Imm(0) -> x3 + v295 Imm(0) -> x0 + terminator Bz { cond=v292, target=b20, fall=b13 } (exit_acc=v292) block 13 start_pc=0 - v107 LocalAddr(-18) -> x7 - v108 Call { target_pc=1, args=[v107], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v109 LoadLocal { off=-23, kind=I64 } -> x1 - v110 Binop { op=eq, lhs=v108, rhs=v101 } -> x0 - v111 BinopI { op=ne, lhs=v110, rhs_imm=0 } -> x3 - v112 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v111) + v296 LocalAddr(-18) -> x0 + v297 BinopI { op=add, lhs=v296, rhs_imm=24 } -> x1 + v298 Load { addr=v296, disp=24, kind=I64 } -> x0 + v299 BinopI { op=eq, lhs=v298, rhs_imm=369 } -> x0 + v300 BinopI { op=ne, lhs=v299, rhs_imm=0 } -> x3 + v301 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v300) block 14 start_pc=0 - v113 Phi { incoming=[b25:v105, b13:v111], kind=I64 } -> x3 - v114 LoadLocal { off=-50, kind=I64 } -> x0 - v115 Imm(0) -> x12 - v116 Imm(0) -> x0 - terminator Bz { cond=v113, target=b26, fall=b15 } (exit_acc=v113) + v302 Phi { incoming=[b20:v294, b13:v300], kind=I64 } -> x3 + v303 LoadLocal { off=-48, kind=I64 } -> x0 + v304 Imm(0) -> x0 + v305 LocalAddr(-58) -> x7 + v306 Imm(0) -> x0 + v307 LoadLocal { off=-59, kind=I64 } -> x0 + v308 Imm(10) -> x6 + v309 Call { target_pc=5, args=[v305, v308], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v310 LocalAddr(-58) -> x0 + v311 LocalAddr(-31) -> x1 + v312 Mcpy { dst=v311, src=v310, size=64 } -> x0 + v313 Extend { value=v302, kind=I32 } -> x0 + v314 Imm(0) -> x2 + v315 Imm(0) -> x1 + terminator Bz { cond=v313, target=b19, fall=b15 } (exit_acc=v313) block 15 start_pc=0 - v117 LocalAddr(-18) -> x0 - v118 Load { addr=v117, disp=0, kind=I64 } -> x0 - v119 BinopI { op=eq, lhs=v118, rhs_imm=123 } -> x0 - v120 BinopI { op=ne, lhs=v119, rhs_imm=0 } -> x12 - v121 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v120) + v316 LocalAddr(-31) -> x7 + v317 Call { target_pc=4, args=[v316], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v318 Imm(21) -> x1 + v319 Imm(90194313216) -> x1 + v320 Imm(33) -> x1 + v321 Imm(141733920768) -> x1 + v322 Imm(46) -> x1 + v323 Imm(197568495616) -> x1 + v324 Imm(60) -> x1 + v325 Imm(257698037760) -> x1 + v326 Imm(75) -> x1 + v327 Imm(322122547200) -> x1 + v328 Imm(91) -> x1 + v329 Imm(390842023936) -> x1 + v330 Imm(101) -> x1 + v331 Imm(433791696896) -> x1 + v332 BinopI { op=eq, lhs=v317, rhs_imm=101 } -> x0 + v333 BinopI { op=ne, lhs=v332, rhs_imm=0 } -> x2 + v334 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v333) block 16 start_pc=0 - v122 Phi { incoming=[b26:v115, b15:v120], kind=I64 } -> x12 - v123 LoadLocal { off=-49, kind=I64 } -> x0 - v124 Imm(0) -> x3 - v125 Imm(0) -> x0 - terminator Bz { cond=v122, target=b27, fall=b17 } (exit_acc=v122) + v335 Phi { incoming=[b19:v314, b15:v333], kind=I64 } -> x2 + v336 LoadLocal { off=-60, kind=I64 } -> x0 + v337 Imm(0) -> x0 + v338 Extend { value=v335, kind=I32 } -> x0 + v339 BinopI { op=eq, lhs=v338, rhs_imm=0 } -> x0 + terminator Bz { cond=v339, target=b18, fall=b17 } (exit_acc=v339) block 17 start_pc=0 - v126 LocalAddr(-18) -> x0 - v127 BinopI { op=add, lhs=v126, rhs_imm=24 } -> x1 - v128 Load { addr=v126, disp=24, kind=I64 } -> x0 - v129 BinopI { op=eq, lhs=v128, rhs_imm=369 } -> x0 - v130 BinopI { op=ne, lhs=v129, rhs_imm=0 } -> x3 - v131 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v130) + v340 ImmData(100) -> x7 + v341 CallExt { binding_idx=0, args=[v340], fp_arg_mask=0x0 } -> x0 + v342 Imm(1) -> x0 + terminator Return(v342) (exit_acc=v342) block 18 start_pc=0 - v132 Phi { incoming=[b27:v124, b17:v130], kind=I64 } -> x3 - v133 LoadLocal { off=-48, kind=I64 } -> x0 - v134 Imm(0) -> x0 - v135 LocalAddr(-58) -> x7 - v136 Imm(0) -> x0 - v137 LoadLocal { off=-59, kind=I64 } -> x0 - v138 Imm(10) -> x6 - v139 Call { target_pc=5, args=[v135, v138], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v140 LocalAddr(-58) -> x0 - v141 LocalAddr(-31) -> x1 - v142 Mcpy { dst=v141, src=v140, size=64 } -> x0 - v143 Extend { value=v132, kind=I32 } -> x0 - v144 Imm(0) -> x3 - v145 Imm(0) -> x1 - terminator Bz { cond=v143, target=b28, fall=b19 } (exit_acc=v143) + v343 Imm(0) -> x0 + terminator Return(v343) (exit_acc=v343) block 19 start_pc=0 - v146 LocalAddr(-31) -> x7 - v147 Call { target_pc=4, args=[v146], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v148 Imm(21) -> x1 - v149 Imm(90194313216) -> x1 - v150 Imm(33) -> x1 - v151 Imm(141733920768) -> x1 - v152 Imm(46) -> x1 - v153 Imm(197568495616) -> x1 - v154 Imm(60) -> x1 - v155 Imm(257698037760) -> x1 - v156 Imm(75) -> x1 - v157 Imm(322122547200) -> x1 - v158 Imm(91) -> x1 - v159 Imm(390842023936) -> x1 - v160 Imm(101) -> x1 - v161 Imm(433791696896) -> x1 - v162 BinopI { op=eq, lhs=v147, rhs_imm=101 } -> x0 - v163 BinopI { op=ne, lhs=v162, rhs_imm=0 } -> x3 - v164 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v163) + terminator Jmp(b16) block 20 start_pc=0 - v165 Phi { incoming=[b28:v144, b19:v163], kind=I64 } -> x3 - v166 LoadLocal { off=-60, kind=I64 } -> x0 - v167 Imm(0) -> x0 - v168 Extend { value=v165, kind=I32 } -> x0 - v169 BinopI { op=eq, lhs=v168, rhs_imm=0 } -> x0 - terminator Bz { cond=v169, target=b22, fall=b21 } (exit_acc=v169) + terminator Jmp(b14) block 21 start_pc=0 - v170 ImmData(100) -> x7 - v171 CallExt { binding_idx=0, args=[v170], fp_arg_mask=0x0 } -> x0 - v172 Imm(1) -> x0 - terminator Return(v172) (exit_acc=v172) + terminator Jmp(b12) block 22 start_pc=0 - v173 Imm(0) -> x0 - terminator Return(v173) (exit_acc=v173) + terminator Jmp(b10) block 23 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b8) block 24 start_pc=0 - terminator Jmp(b12) - block 25 start_pc=0 - terminator Jmp(b14) - block 26 start_pc=0 - terminator Jmp(b16) - block 27 start_pc=0 - terminator Jmp(b18) - block 28 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/slot_coalesce_disjoint_temps.ssa b/tests/snapshots/ssa/slot_coalesce_disjoint_temps.ssa index f495af4b0..fe1736313 100644 --- a/tests/snapshots/ssa/slot_coalesce_disjoint_temps.ssa +++ b/tests/snapshots/ssa/slot_coalesce_disjoint_temps.ssa @@ -1,245 +1,245 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=17 - spill_count=0 gpr_used=[] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b33) (exit_acc=v1) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v1, b2:v151], kind=I64 } -> x0 - v7 Phi { incoming=[b0:v1, b2:v86], kind=I64 } -> x2 - v8 Extend { value=v5, kind=I32 } -> x6 - v9 BinopI { op=lt, lhs=v8, rhs_imm=64 } -> x6 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v13 Extend { value=v5, kind=I32 } -> x7 + v14 BinopI { op=and, lhs=v8, rhs_imm=1 } -> x7 + terminator Bz { cond=v14, target=b31, fall=b2 } (exit_acc=v14) block 2 start_pc=0 - v10 Extend { value=v5, kind=I32 } -> x1 - v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 - v12 Imm(0) -> x6 - terminator Jmp(b1) (exit_acc=v11) + v18 Extend { value=v5, kind=I32 } -> x7 + v19 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x7 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x8 + v21 Extend { value=v19, kind=I32 } -> x8 + v22 Imm(0) -> x7 + terminator Jmp(b3) (exit_acc=v21) block 3 start_pc=0 - v13 Extend { value=v5, kind=I32 } -> x6 - v14 BinopI { op=and, lhs=v13, rhs_imm=1 } -> x6 - terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) + v28 Phi { incoming=[b2:v21, b31:v26], kind=I64 } -> x8 + v29 LoadLocal { off=-10, kind=I64 } -> x7 + v30 Imm(0) -> x7 + v31 Extend { value=v28, kind=I32 } -> x7 + v32 BinopI { op=gt, lhs=v31, rhs_imm=10 } -> x3 + v33 Imm(0) -> x9 + terminator Bz { cond=v32, target=b30, fall=b4 } (exit_acc=v32) block 4 start_pc=0 - v15 Extend { value=v7, kind=I32 } -> x1 - v16 Extend { value=v6, kind=I32 } -> x0 - v17 Binop { op=eq, lhs=v15, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b32, fall=b31 } (exit_acc=v17) + v34 Extend { value=v28, kind=I32 } -> x9 + v35 BinopI { op=lt, lhs=v31, rhs_imm=100 } -> x3 + v36 Imm(0) -> x7 + terminator Jmp(b5) (exit_acc=v35) block 5 start_pc=0 - v18 Extend { value=v5, kind=I32 } -> x6 - v19 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x6 - v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x7 - v21 Extend { value=v19, kind=I32 } -> x7 - v22 Imm(0) -> x6 - terminator Jmp(b7) (exit_acc=v21) + v37 Phi { incoming=[b30:v32, b4:v35], kind=I64 } -> x3 + v38 LoadLocal { off=-11, kind=I64 } -> x7 + terminator Bz { cond=v37, target=b29, fall=b6 } (exit_acc=v37) block 6 start_pc=0 - v23 Extend { value=v5, kind=I32 } -> x6 - v24 BinopI { op=add, lhs=v5, rhs_imm=7 } -> x6 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x7 - v26 Extend { value=v24, kind=I32 } -> x7 - v27 Imm(0) -> x6 - terminator Jmp(b7) (exit_acc=v26) + v39 Extend { value=v28, kind=I32 } -> x7 + v40 BinopI { op=sub, lhs=v28, rhs_imm=1 } -> x7 + v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x9 + v42 Extend { value=v40, kind=I32 } -> x9 + v43 Imm(0) -> x7 + terminator Jmp(b7) (exit_acc=v42) block 7 start_pc=0 - v28 Phi { incoming=[b5:v21, b6:v26], kind=I64 } -> x7 - v29 LoadLocal { off=-10, kind=I64 } -> x6 - v30 Imm(0) -> x6 - v31 Extend { value=v28, kind=I32 } -> x6 - v32 BinopI { op=gt, lhs=v31, rhs_imm=10 } -> x8 - v33 Imm(0) -> x6 - terminator Bz { cond=v32, target=b34, fall=b8 } (exit_acc=v32) + v49 Phi { incoming=[b6:v42, b29:v47], kind=I64 } -> x9 + v50 LoadLocal { off=-12, kind=I64 } -> x7 + v51 Imm(0) -> x7 + v52 Extend { value=v49, kind=I32 } -> x12 + v53 Imm(2) -> x7 + v54 BinopI { op=shr, lhs=v52, rhs_imm=63 } -> x7 + v55 BinopI { op=shru, lhs=v54, rhs_imm=63 } -> x7 + v56 Binop { op=add, lhs=v52, rhs=v55 } -> x3 + v57 BinopI { op=and, lhs=v56, rhs_imm=1 } -> x3 + v58 Binop { op=sub, lhs=v57, rhs=v55 } -> x7 + v59 BinopI { op=eq, lhs=v58, rhs_imm=0 } -> x3 + v60 Imm(0) -> x7 + terminator Bnz { cond=v59, target=b28, fall=b8 } (exit_acc=v59) block 8 start_pc=0 - v34 Extend { value=v28, kind=I32 } -> x6 - v35 BinopI { op=lt, lhs=v34, rhs_imm=100 } -> x8 - v36 Imm(0) -> x6 - terminator Jmp(b9) (exit_acc=v35) + v61 Extend { value=v49, kind=I32 } -> x7 + v62 BinopI { op=gt, lhs=v52, rhs_imm=50 } -> x3 + v63 Imm(0) -> x7 + terminator Jmp(b9) (exit_acc=v62) block 9 start_pc=0 - v37 Phi { incoming=[b34:v32, b8:v35], kind=I64 } -> x8 - v38 LoadLocal { off=-11, kind=I64 } -> x6 - terminator Bz { cond=v37, target=b11, fall=b10 } (exit_acc=v37) + v64 Phi { incoming=[b28:v59, b8:v62], kind=I64 } -> x3 + v65 LoadLocal { off=-13, kind=I64 } -> x7 + terminator Bz { cond=v64, target=b27, fall=b10 } (exit_acc=v64) block 10 start_pc=0 - v39 Extend { value=v28, kind=I32 } -> x6 - v40 BinopI { op=sub, lhs=v28, rhs_imm=1 } -> x6 - v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x8 - v42 Extend { value=v40, kind=I32 } -> x8 - v43 Imm(0) -> x6 - terminator Jmp(b12) (exit_acc=v42) + v66 Extend { value=v49, kind=I32 } -> x7 + v67 BinopI { op=shl, lhs=v49, rhs_imm=1 } -> x7 + v68 BinopI { op=shl, lhs=v67, rhs_imm=32 } -> x3 + v69 Extend { value=v67, kind=I32 } -> x12 + v70 Imm(0) -> x7 + terminator Jmp(b11) (exit_acc=v69) block 11 start_pc=0 - v44 Extend { value=v28, kind=I32 } -> x6 - v45 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x6 - v46 BinopI { op=shl, lhs=v45, rhs_imm=32 } -> x8 - v47 Extend { value=v45, kind=I32 } -> x8 - v48 Imm(0) -> x6 - terminator Jmp(b12) (exit_acc=v47) + v73 Phi { incoming=[b10:v69, b27:v52], kind=I64 } -> x12 + v74 LoadLocal { off=-14, kind=I64 } -> x7 + v75 Imm(0) -> x7 + v76 Extend { value=v7, kind=I32 } -> x7 + v77 Extend { value=v73, kind=I32 } -> x7 + v78 Extend { value=v28, kind=I32 } -> x7 + v79 Binop { op=add, lhs=v73, rhs=v28 } -> x7 + v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x8 + v81 Extend { value=v79, kind=I32 } -> x8 + v82 Extend { value=v49, kind=I32 } -> x8 + v83 Binop { op=add, lhs=v79, rhs=v49 } -> x7 + v84 BinopI { op=shl, lhs=v83, rhs_imm=32 } -> x8 + v85 Extend { value=v83, kind=I32 } -> x8 + v86 Binop { op=add, lhs=v7, rhs=v83 } -> x2 + v87 Imm(0) -> x7 + v88 Extend { value=v86, kind=I32 } -> x7 + v89 Extend { value=v5, kind=I32 } -> x7 + v90 BinopI { op=and, lhs=v8, rhs_imm=1 } -> x7 + terminator Bz { cond=v90, target=b26, fall=b12 } (exit_acc=v90) block 12 start_pc=0 - v49 Phi { incoming=[b10:v42, b11:v47], kind=I64 } -> x8 - v50 LoadLocal { off=-12, kind=I64 } -> x6 - v51 Imm(0) -> x6 - v52 Extend { value=v49, kind=I32 } -> x6 - v53 Imm(2) -> x9 - v54 BinopI { op=shr, lhs=v52, rhs_imm=63 } -> x9 - v55 BinopI { op=shru, lhs=v54, rhs_imm=63 } -> x9 - v56 Binop { op=add, lhs=v52, rhs=v55 } -> x6 - v57 BinopI { op=and, lhs=v56, rhs_imm=1 } -> x6 - v58 Binop { op=sub, lhs=v57, rhs=v55 } -> x6 - v59 BinopI { op=eq, lhs=v58, rhs_imm=0 } -> x9 - v60 Imm(0) -> x6 - terminator Bnz { cond=v59, target=b35, fall=b13 } (exit_acc=v59) + v91 Extend { value=v5, kind=I32 } -> x7 + v92 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x7 + v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x8 + v94 Extend { value=v92, kind=I32 } -> x8 + v95 Imm(0) -> x7 + terminator Jmp(b13) (exit_acc=v94) block 13 start_pc=0 - v61 Extend { value=v49, kind=I32 } -> x6 - v62 BinopI { op=gt, lhs=v61, rhs_imm=50 } -> x9 - v63 Imm(0) -> x6 - terminator Jmp(b14) (exit_acc=v62) + v96 Phi { incoming=[b12:v94, b26:v103], kind=I64 } -> x8 + v97 Extend { value=v96, kind=I32 } -> x7 + v98 BinopI { op=gt, lhs=v97, rhs_imm=10 } -> x3 + v99 Imm(0) -> x9 + terminator Bz { cond=v98, target=b25, fall=b14 } (exit_acc=v98) block 14 start_pc=0 - v64 Phi { incoming=[b35:v59, b13:v62], kind=I64 } -> x9 - v65 LoadLocal { off=-13, kind=I64 } -> x6 - terminator Bz { cond=v64, target=b16, fall=b15 } (exit_acc=v64) + v105 Extend { value=v96, kind=I32 } -> x9 + v106 BinopI { op=lt, lhs=v97, rhs_imm=100 } -> x3 + v107 Imm(0) -> x7 + terminator Jmp(b15) (exit_acc=v106) block 15 start_pc=0 - v66 Extend { value=v49, kind=I32 } -> x6 - v67 BinopI { op=shl, lhs=v49, rhs_imm=1 } -> x6 - v68 BinopI { op=shl, lhs=v67, rhs_imm=32 } -> x9 - v69 Extend { value=v67, kind=I32 } -> x9 - v70 Imm(0) -> x6 - terminator Jmp(b17) (exit_acc=v69) + v108 Phi { incoming=[b25:v98, b14:v106], kind=I64 } -> x3 + v109 LoadLocal { off=-15, kind=I64 } -> x7 + terminator Bz { cond=v108, target=b24, fall=b16 } (exit_acc=v108) block 16 start_pc=0 - v71 Extend { value=v49, kind=I32 } -> x9 - v72 Imm(0) -> x6 - terminator Jmp(b17) (exit_acc=v71) + v110 Extend { value=v96, kind=I32 } -> x7 + v111 BinopI { op=sub, lhs=v96, rhs_imm=1 } -> x7 + v112 BinopI { op=shl, lhs=v111, rhs_imm=32 } -> x9 + v113 Extend { value=v111, kind=I32 } -> x9 + v114 Imm(0) -> x7 + terminator Jmp(b17) (exit_acc=v113) block 17 start_pc=0 - v73 Phi { incoming=[b15:v69, b16:v71], kind=I64 } -> x9 - v74 LoadLocal { off=-14, kind=I64 } -> x6 - v75 Imm(0) -> x6 - v76 Extend { value=v7, kind=I32 } -> x6 - v77 Extend { value=v73, kind=I32 } -> x6 - v78 Extend { value=v28, kind=I32 } -> x6 - v79 Binop { op=add, lhs=v73, rhs=v28 } -> x6 - v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x7 - v81 Extend { value=v79, kind=I32 } -> x7 - v82 Extend { value=v49, kind=I32 } -> x7 - v83 Binop { op=add, lhs=v79, rhs=v49 } -> x6 - v84 BinopI { op=shl, lhs=v83, rhs_imm=32 } -> x7 - v85 Extend { value=v83, kind=I32 } -> x7 - v86 Binop { op=add, lhs=v7, rhs=v83 } -> x2 - v87 Imm(0) -> x6 - v88 Extend { value=v86, kind=I32 } -> x6 - v89 Extend { value=v5, kind=I32 } -> x6 - v90 BinopI { op=and, lhs=v89, rhs_imm=1 } -> x6 - terminator Bz { cond=v90, target=b20, fall=b18 } (exit_acc=v90) + v115 Phi { incoming=[b16:v113, b24:v128], kind=I64 } -> x9 + v116 Extend { value=v115, kind=I32 } -> x12 + v117 Imm(2) -> x7 + v118 BinopI { op=shr, lhs=v116, rhs_imm=63 } -> x7 + v119 BinopI { op=shru, lhs=v118, rhs_imm=63 } -> x7 + v120 Binop { op=add, lhs=v116, rhs=v119 } -> x3 + v121 BinopI { op=and, lhs=v120, rhs_imm=1 } -> x3 + v122 Binop { op=sub, lhs=v121, rhs=v119 } -> x7 + v123 BinopI { op=eq, lhs=v122, rhs_imm=0 } -> x3 + v124 Imm(0) -> x7 + terminator Bnz { cond=v123, target=b23, fall=b18 } (exit_acc=v123) block 18 start_pc=0 - v91 Extend { value=v5, kind=I32 } -> x6 - v92 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x6 - v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x7 - v94 Extend { value=v92, kind=I32 } -> x7 - v95 Imm(0) -> x6 - terminator Jmp(b19) (exit_acc=v94) + v130 Extend { value=v115, kind=I32 } -> x7 + v131 BinopI { op=gt, lhs=v116, rhs_imm=50 } -> x3 + v132 Imm(0) -> x7 + terminator Jmp(b19) (exit_acc=v131) block 19 start_pc=0 - v96 Phi { incoming=[b18:v94, b20:v103], kind=I64 } -> x7 - v97 Extend { value=v96, kind=I32 } -> x6 - v98 BinopI { op=gt, lhs=v97, rhs_imm=10 } -> x8 - v99 Imm(0) -> x6 - terminator Bz { cond=v98, target=b36, fall=b21 } (exit_acc=v98) + v133 Phi { incoming=[b23:v123, b18:v131], kind=I64 } -> x3 + v134 LoadLocal { off=-16, kind=I64 } -> x7 + terminator Bz { cond=v133, target=b22, fall=b20 } (exit_acc=v133) block 20 start_pc=0 - v100 Extend { value=v5, kind=I32 } -> x6 - v101 BinopI { op=add, lhs=v5, rhs_imm=7 } -> x6 - v102 BinopI { op=shl, lhs=v101, rhs_imm=32 } -> x7 - v103 Extend { value=v101, kind=I32 } -> x7 - v104 Imm(0) -> x6 - terminator Jmp(b19) (exit_acc=v103) + v135 Extend { value=v115, kind=I32 } -> x7 + v136 BinopI { op=shl, lhs=v115, rhs_imm=1 } -> x7 + v137 BinopI { op=shl, lhs=v136, rhs_imm=32 } -> x3 + v138 Extend { value=v136, kind=I32 } -> x12 + v139 Imm(0) -> x7 + terminator Jmp(b21) (exit_acc=v138) block 21 start_pc=0 - v105 Extend { value=v96, kind=I32 } -> x6 - v106 BinopI { op=lt, lhs=v105, rhs_imm=100 } -> x8 - v107 Imm(0) -> x6 - terminator Jmp(b22) (exit_acc=v106) + v140 Phi { incoming=[b20:v138, b22:v116], kind=I64 } -> x12 + v141 Extend { value=v6, kind=I32 } -> x7 + v142 Extend { value=v140, kind=I32 } -> x7 + v143 Extend { value=v96, kind=I32 } -> x7 + v144 Binop { op=add, lhs=v140, rhs=v96 } -> x7 + v145 BinopI { op=shl, lhs=v144, rhs_imm=32 } -> x8 + v146 Extend { value=v144, kind=I32 } -> x8 + v147 Extend { value=v115, kind=I32 } -> x8 + v148 Binop { op=add, lhs=v144, rhs=v115 } -> x7 + v149 BinopI { op=shl, lhs=v148, rhs_imm=32 } -> x8 + v150 Extend { value=v148, kind=I32 } -> x8 + v151 Binop { op=add, lhs=v6, rhs=v148 } -> x0 + v152 Imm(0) -> x7 + v153 Extend { value=v151, kind=I32 } -> x7 + terminator Jmp(b32) (exit_acc=v153) block 22 start_pc=0 - v108 Phi { incoming=[b36:v98, b21:v106], kind=I64 } -> x8 - v109 LoadLocal { off=-15, kind=I64 } -> x6 - terminator Bz { cond=v108, target=b25, fall=b23 } (exit_acc=v108) + v154 Extend { value=v115, kind=I32 } -> x7 + v155 Imm(0) -> x7 + terminator Jmp(b21) (exit_acc=v116) block 23 start_pc=0 - v110 Extend { value=v96, kind=I32 } -> x6 - v111 BinopI { op=sub, lhs=v96, rhs_imm=1 } -> x6 - v112 BinopI { op=shl, lhs=v111, rhs_imm=32 } -> x8 - v113 Extend { value=v111, kind=I32 } -> x8 - v114 Imm(0) -> x6 - terminator Jmp(b24) (exit_acc=v113) + terminator Jmp(b19) block 24 start_pc=0 - v115 Phi { incoming=[b23:v113, b25:v128], kind=I64 } -> x8 - v116 Extend { value=v115, kind=I32 } -> x6 - v117 Imm(2) -> x9 - v118 BinopI { op=shr, lhs=v116, rhs_imm=63 } -> x9 - v119 BinopI { op=shru, lhs=v118, rhs_imm=63 } -> x9 - v120 Binop { op=add, lhs=v116, rhs=v119 } -> x6 - v121 BinopI { op=and, lhs=v120, rhs_imm=1 } -> x6 - v122 Binop { op=sub, lhs=v121, rhs=v119 } -> x6 - v123 BinopI { op=eq, lhs=v122, rhs_imm=0 } -> x9 - v124 Imm(0) -> x6 - terminator Bnz { cond=v123, target=b37, fall=b26 } (exit_acc=v123) + v125 Extend { value=v96, kind=I32 } -> x7 + v126 BinopI { op=add, lhs=v96, rhs_imm=1 } -> x7 + v127 BinopI { op=shl, lhs=v126, rhs_imm=32 } -> x9 + v128 Extend { value=v126, kind=I32 } -> x9 + v129 Imm(0) -> x7 + terminator Jmp(b17) (exit_acc=v128) block 25 start_pc=0 - v125 Extend { value=v96, kind=I32 } -> x6 - v126 BinopI { op=add, lhs=v96, rhs_imm=1 } -> x6 - v127 BinopI { op=shl, lhs=v126, rhs_imm=32 } -> x8 - v128 Extend { value=v126, kind=I32 } -> x8 - v129 Imm(0) -> x6 - terminator Jmp(b24) (exit_acc=v128) + terminator Jmp(b15) block 26 start_pc=0 - v130 Extend { value=v115, kind=I32 } -> x6 - v131 BinopI { op=gt, lhs=v130, rhs_imm=50 } -> x9 - v132 Imm(0) -> x6 - terminator Jmp(b27) (exit_acc=v131) + v100 Extend { value=v5, kind=I32 } -> x7 + v101 BinopI { op=add, lhs=v5, rhs_imm=7 } -> x7 + v102 BinopI { op=shl, lhs=v101, rhs_imm=32 } -> x8 + v103 Extend { value=v101, kind=I32 } -> x8 + v104 Imm(0) -> x7 + terminator Jmp(b13) (exit_acc=v103) block 27 start_pc=0 - v133 Phi { incoming=[b37:v123, b26:v131], kind=I64 } -> x9 - v134 LoadLocal { off=-16, kind=I64 } -> x6 - terminator Bz { cond=v133, target=b30, fall=b28 } (exit_acc=v133) + v71 Extend { value=v49, kind=I32 } -> x7 + v72 Imm(0) -> x7 + terminator Jmp(b11) (exit_acc=v52) block 28 start_pc=0 - v135 Extend { value=v115, kind=I32 } -> x6 - v136 BinopI { op=shl, lhs=v115, rhs_imm=1 } -> x6 - v137 BinopI { op=shl, lhs=v136, rhs_imm=32 } -> x9 - v138 Extend { value=v136, kind=I32 } -> x9 - v139 Imm(0) -> x6 - terminator Jmp(b29) (exit_acc=v138) + terminator Jmp(b9) block 29 start_pc=0 - v140 Phi { incoming=[b28:v138, b30:v154], kind=I64 } -> x9 - v141 Extend { value=v6, kind=I32 } -> x6 - v142 Extend { value=v140, kind=I32 } -> x6 - v143 Extend { value=v96, kind=I32 } -> x6 - v144 Binop { op=add, lhs=v140, rhs=v96 } -> x6 - v145 BinopI { op=shl, lhs=v144, rhs_imm=32 } -> x7 - v146 Extend { value=v144, kind=I32 } -> x7 - v147 Extend { value=v115, kind=I32 } -> x7 - v148 Binop { op=add, lhs=v144, rhs=v115 } -> x6 - v149 BinopI { op=shl, lhs=v148, rhs_imm=32 } -> x7 - v150 Extend { value=v148, kind=I32 } -> x7 - v151 Binop { op=add, lhs=v6, rhs=v148 } -> x0 - v152 Imm(0) -> x6 - v153 Extend { value=v151, kind=I32 } -> x6 - terminator Jmp(b2) (exit_acc=v153) + v44 Extend { value=v28, kind=I32 } -> x7 + v45 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x7 + v46 BinopI { op=shl, lhs=v45, rhs_imm=32 } -> x9 + v47 Extend { value=v45, kind=I32 } -> x9 + v48 Imm(0) -> x7 + terminator Jmp(b7) (exit_acc=v47) block 30 start_pc=0 - v154 Extend { value=v115, kind=I32 } -> x9 - v155 Imm(0) -> x6 - terminator Jmp(b29) (exit_acc=v154) + terminator Jmp(b5) block 31 start_pc=0 - v156 Imm(0) -> x1 - v157 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v156) + v23 Extend { value=v5, kind=I32 } -> x7 + v24 BinopI { op=add, lhs=v5, rhs_imm=7 } -> x7 + v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x8 + v26 Extend { value=v24, kind=I32 } -> x8 + v27 Imm(0) -> x7 + terminator Jmp(b3) (exit_acc=v26) block 32 start_pc=0 - v158 Imm(1) -> x1 - v159 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v158) + v10 Extend { value=v5, kind=I32 } -> x1 + v11 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v12 Imm(0) -> x6 + terminator Jmp(b33) (exit_acc=v11) block 33 start_pc=0 - v160 Phi { incoming=[b31:v156, b32:v158], kind=I64 } -> x1 - v161 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Return(v160) (exit_acc=v160) + v5 Phi { incoming=[b0:v1, b32:v11], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b32:v151], kind=I64 } -> x0 + v7 Phi { incoming=[b0:v1, b32:v86], kind=I64 } -> x2 + v8 Extend { value=v5, kind=I32 } -> x6 + v9 BinopI { op=lt, lhs=v8, rhs_imm=64 } -> x7 + terminator Bnz { cond=v9, target=b1, fall=b34 } (exit_acc=v9) block 34 start_pc=0 - terminator Jmp(b9) + v15 Extend { value=v7, kind=I32 } -> x1 + v16 Extend { value=v6, kind=I32 } -> x0 + v17 Binop { op=eq, lhs=v15, rhs=v16 } -> x0 + terminator Bz { cond=v17, target=b37, fall=b35 } (exit_acc=v17) block 35 start_pc=0 - terminator Jmp(b14) + v156 Imm(0) -> x1 + v157 Imm(0) -> x0 + terminator Jmp(b36) (exit_acc=v156) block 36 start_pc=0 - terminator Jmp(b22) + v160 Phi { incoming=[b35:v156, b37:v158], kind=I64 } -> x1 + v161 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Return(v160) (exit_acc=v160) block 37 start_pc=0 - terminator Jmp(b27) + v158 Imm(1) -> x1 + v159 Imm(0) -> x0 + terminator Jmp(b36) (exit_acc=v158) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/socket_headers_abi.ssa b/tests/snapshots/ssa/socket_headers_abi.ssa index 2bf65ce5d..3fe7e3143 100644 --- a/tests/snapshots/ssa/socket_headers_abi.ssa +++ b/tests/snapshots/ssa/socket_headers_abi.ssa @@ -5,100 +5,67 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) - block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) - block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v9) + block 5 start_pc=0 v11 Imm(0) -> x0 v12 Imm(2) -> x1 - terminator Jmp(b12) (exit_acc=v11) - block 11 start_pc=0 - v13 Imm(6) -> x0 - terminator Return(v13) (exit_acc=v13) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v11) + block 6 start_pc=0 v14 Imm(0) -> x0 v15 Imm(4) -> x1 - terminator Jmp(b14) (exit_acc=v14) - block 13 start_pc=0 - v16 Imm(7) -> x0 - terminator Return(v16) (exit_acc=v16) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v14) + block 7 start_pc=0 v17 Imm(0) -> x0 v18 Imm(8) -> x1 - terminator Jmp(b16) (exit_acc=v17) - block 15 start_pc=0 - v19 Imm(8) -> x0 - terminator Return(v19) (exit_acc=v19) - block 16 start_pc=0 + terminator Jmp(b8) (exit_acc=v17) + block 8 start_pc=0 v20 Imm(0) -> x0 v21 Imm(24) -> x1 - terminator Jmp(b18) (exit_acc=v20) - block 17 start_pc=0 - v22 Imm(9) -> x0 - terminator Return(v22) (exit_acc=v22) - block 18 start_pc=0 + terminator Jmp(b9) (exit_acc=v20) + block 9 start_pc=0 v23 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v23) - block 19 start_pc=0 - v24 Imm(10) -> x0 - terminator Return(v24) (exit_acc=v24) - block 20 start_pc=0 + terminator Jmp(b10) (exit_acc=v23) + block 10 start_pc=0 v25 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v25) - block 21 start_pc=0 - v26 Imm(11) -> x0 - terminator Return(v26) (exit_acc=v26) - block 22 start_pc=0 + terminator Jmp(b11) (exit_acc=v25) + block 11 start_pc=0 v27 Imm(0) -> x0 v28 Imm(1) -> x2 v29 Imm(0) -> x1 - terminator Jmp(b23) (exit_acc=v27) - block 23 start_pc=0 + terminator Jmp(b12) (exit_acc=v27) + block 12 start_pc=0 v30 Imm(0) -> x2 v31 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v30) - block 24 start_pc=0 - v32 Phi { incoming=[b22:v28, b23:v30], kind=I64 } -> x2 + terminator Jmp(b13) (exit_acc=v30) + block 13 start_pc=0 + v32 Phi { incoming=[b11:v28, b12:v30], kind=I64 } -> x2 v33 LoadLocal { off=-10, kind=I64 } -> x0 v34 Imm(0) -> x0 - terminator Bnz { cond=v32, target=b35, fall=b25 } (exit_acc=v32) - block 25 start_pc=0 + terminator Bnz { cond=v32, target=b25, fall=b14 } (exit_acc=v32) + block 14 start_pc=0 v35 Imm(0) -> x2 v36 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v35) - block 26 start_pc=0 - v37 Phi { incoming=[b35:v32, b25:v35], kind=I64 } -> x2 + terminator Jmp(b15) (exit_acc=v35) + block 15 start_pc=0 + v37 Phi { incoming=[b25:v32, b14:v35], kind=I64 } -> x2 v38 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v37, target=b28, fall=b27 } (exit_acc=v37) - block 27 start_pc=0 + terminator Bz { cond=v37, target=b17, fall=b16 } (exit_acc=v37) + block 16 start_pc=0 v39 Imm(12) -> x0 terminator Return(v39) (exit_acc=v39) - block 28 start_pc=0 + block 17 start_pc=0 v40 LocalAddr(-2) -> x0 v41 Imm(2) -> x1 v42 Store { addr=v40, disp=0, value=v41, kind=I16 } -> - @@ -112,11 +79,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 v50 BinopI { op=xor, lhs=v49, rhs_imm=4660 } -> x0 v51 BinopI { op=and, lhs=v50, rhs_imm=4294967295 } -> x0 v52 BinopI { op=ne, lhs=v51, rhs_imm=0 } -> x0 - terminator Bz { cond=v52, target=b30, fall=b29 } (exit_acc=v52) - block 29 start_pc=0 + terminator Bz { cond=v52, target=b19, fall=b18 } (exit_acc=v52) + block 18 start_pc=0 v53 Imm(13) -> x0 terminator Return(v53) (exit_acc=v53) - block 30 start_pc=0 + block 19 start_pc=0 v54 LocalAddr(-8) -> x0 v55 BinopI { op=add, lhs=v54, rhs_imm=4 } -> x1 v56 Imm(0) -> x1 @@ -130,28 +97,61 @@ fn ent_pc=0 n_params=0 variadic=false locals=11 v64 Load { addr=v62, disp=4, kind=I32 } -> x0 v65 BinopI { op=ne, lhs=v64, rhs_imm=0 } -> x1 v66 Imm(0) -> x0 - terminator Bnz { cond=v65, target=b36, fall=b31 } (exit_acc=v65) - block 31 start_pc=0 + terminator Bnz { cond=v65, target=b24, fall=b20 } (exit_acc=v65) + block 20 start_pc=0 v67 LocalAddr(-8) -> x0 v68 BinopI { op=add, lhs=v67, rhs_imm=8 } -> x1 v69 Load { addr=v67, disp=8, kind=I32 } -> x0 v70 BinopI { op=ne, lhs=v69, rhs_imm=1 } -> x1 v71 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v70) - block 32 start_pc=0 - v72 Phi { incoming=[b36:v65, b31:v70], kind=I64 } -> x1 + terminator Jmp(b21) (exit_acc=v70) + block 21 start_pc=0 + v72 Phi { incoming=[b24:v65, b20:v70], kind=I64 } -> x1 v73 LoadLocal { off=-11, kind=I64 } -> x0 - terminator Bz { cond=v72, target=b34, fall=b33 } (exit_acc=v72) - block 33 start_pc=0 + terminator Bz { cond=v72, target=b23, fall=b22 } (exit_acc=v72) + block 22 start_pc=0 v74 Imm(14) -> x0 terminator Return(v74) (exit_acc=v74) - block 34 start_pc=0 + block 23 start_pc=0 v75 Imm(0) -> x0 terminator Return(v75) (exit_acc=v75) + block 24 start_pc=0 + terminator Jmp(b21) + block 25 start_pc=0 + terminator Jmp(b15) + block 26 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 27 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 28 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 29 start_pc=0 + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) + block 30 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 31 start_pc=0 + v13 Imm(6) -> x0 + terminator Return(v13) (exit_acc=v13) + block 32 start_pc=0 + v16 Imm(7) -> x0 + terminator Return(v16) (exit_acc=v16) + block 33 start_pc=0 + v19 Imm(8) -> x0 + terminator Return(v19) (exit_acc=v19) + block 34 start_pc=0 + v22 Imm(9) -> x0 + terminator Return(v22) (exit_acc=v22) block 35 start_pc=0 - terminator Jmp(b26) + v24 Imm(10) -> x0 + terminator Return(v24) (exit_acc=v24) block 36 start_pc=0 - terminator Jmp(b32) + v26 Imm(11) -> x0 + terminator Return(v26) (exit_acc=v26) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sroa_const_index_local_array.ssa b/tests/snapshots/ssa/sroa_const_index_local_array.ssa new file mode 100644 index 000000000..f0df280e7 --- /dev/null +++ b/tests/snapshots/ssa/sroa_const_index_local_array.ssa @@ -0,0 +1,620 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=rounds +fn ent_pc=0 n_params=2 variadic=false locals=13 + spill_count=0 gpr_used=[3, 12, 13, 14] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x13 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v5) + block 1 start_pc=0 + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(0) -> x0 + v13 LoadLocal { off=2, kind=I64 } -> x0 + v14 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 + v15 Load { addr=v14, disp=0, kind=I64 } -> x1 + v16 Imm(0) -> x0 + v17 Imm(0) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(1) -> x0 + v22 Imm(0) -> x0 + v23 Imm(1) -> x0 + v24 Imm(8) -> x0 + v25 Imm(0) -> x0 + v26 LoadLocal { off=2, kind=I64 } -> x0 + v27 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x0 + v28 Load { addr=v1, disp=8, kind=I64 } -> x2 + v29 Imm(0) -> x0 + v30 Imm(1) -> x0 + v31 Imm(2) -> x0 + v32 Imm(0) -> x0 + v33 Imm(2) -> x0 + v34 Imm(1) -> x0 + v35 Imm(0) -> x0 + v36 Imm(2) -> x0 + v37 Imm(16) -> x0 + v38 Imm(0) -> x0 + v39 LoadLocal { off=2, kind=I64 } -> x0 + v40 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x0 + v41 Load { addr=v1, disp=16, kind=I64 } -> x6 + v42 Imm(0) -> x0 + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(0) -> x0 + v46 Imm(3) -> x0 + v47 Imm(1) -> x0 + v48 Imm(0) -> x0 + v49 Imm(3) -> x0 + v50 Imm(24) -> x0 + v51 Imm(0) -> x0 + v52 LoadLocal { off=2, kind=I64 } -> x0 + v53 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x0 + v54 Load { addr=v1, disp=24, kind=I64 } -> x8 + v55 Imm(0) -> x0 + v56 Imm(3) -> x0 + v57 Imm(4) -> x0 + v58 Imm(0) -> x0 + v59 Imm(4) -> x0 + v60 Imm(1) -> x0 + v61 Imm(0) -> x0 + v62 Imm(4) -> x0 + v63 Imm(32) -> x0 + v64 Imm(0) -> x0 + v65 LoadLocal { off=2, kind=I64 } -> x0 + v66 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x0 + v67 Load { addr=v1, disp=32, kind=I64 } -> x9 + v68 Imm(0) -> x0 + v69 Imm(4) -> x0 + v70 Imm(5) -> x0 + v71 Imm(0) -> x0 + v72 Imm(5) -> x0 + v73 Imm(1) -> x0 + v74 Imm(0) -> x0 + v75 Imm(5) -> x0 + v76 Imm(40) -> x0 + v77 Imm(0) -> x0 + v78 LoadLocal { off=2, kind=I64 } -> x0 + v79 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x0 + v80 Load { addr=v1, disp=40, kind=I64 } -> x3 + v81 Imm(0) -> x0 + v82 Imm(5) -> x0 + v83 Imm(6) -> x0 + v84 Imm(0) -> x0 + v85 Imm(6) -> x0 + v86 Imm(1) -> x0 + v87 Imm(0) -> x0 + v88 Imm(6) -> x0 + v89 Imm(48) -> x0 + v90 Imm(0) -> x0 + v91 LoadLocal { off=2, kind=I64 } -> x0 + v92 BinopI { op=add, lhs=v1, rhs_imm=48 } -> x0 + v93 Load { addr=v1, disp=48, kind=I64 } -> x12 + v94 Imm(0) -> x0 + v95 Imm(6) -> x0 + v96 Imm(7) -> x0 + v97 Imm(0) -> x0 + v98 Imm(7) -> x0 + v99 Imm(1) -> x0 + v100 Imm(0) -> x0 + v101 Imm(7) -> x0 + v102 Imm(56) -> x0 + v103 Imm(0) -> x0 + v104 LoadLocal { off=2, kind=I64 } -> x0 + v105 BinopI { op=add, lhs=v1, rhs_imm=56 } -> x0 + v106 Load { addr=v1, disp=56, kind=I64 } -> x7 + v107 Imm(0) -> x0 + v108 Imm(7) -> x0 + v109 Imm(8) -> x0 + v110 Imm(0) -> x0 + v111 Imm(8) -> x0 + v112 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v112) + block 2 start_pc=0 + terminator Jmp(b6) + block 3 start_pc=0 + v126 Imm(0) -> x0 + v127 Imm(56) -> x0 + v128 Imm(0) -> x0 + v129 LoadLocal { off=-1, kind=I64 } -> x0 + v130 Imm(0) -> x0 + v131 Imm(7) -> x0 + v132 Imm(0) -> x14 + terminator Jmp(b4) (exit_acc=v131) + block 4 start_pc=0 + v136 Imm(7) -> x0 + v137 Imm(1) -> x0 + v138 Imm(0) -> x0 + v139 Imm(7) -> x0 + v140 Imm(56) -> x0 + v141 Imm(0) -> x0 + v142 Imm(0) -> x0 + v143 Imm(7) -> x0 + v144 Imm(6) -> x0 + v145 Imm(25769803776) -> x0 + v146 Imm(6) -> x0 + v147 Imm(48) -> x0 + v148 Imm(0) -> x0 + v149 LoadLocal { off=-2, kind=I64 } -> x0 + v150 Imm(0) -> x0 + v151 Imm(7) -> x0 + v152 Imm(56) -> x0 + v153 Imm(0) -> x0 + v154 LoadLocal { off=-1, kind=I64 } -> x0 + v155 BinopI { op=shl, lhs=v120, rhs_imm=1 } -> x0 + v156 Binop { op=add, lhs=v119, rhs=v155 } -> x0 + v157 Imm(0) -> x14 + v158 Imm(7) -> x14 + v159 Imm(6) -> x14 + v160 Imm(0) -> x14 + v161 Imm(6) -> x14 + v162 Imm(1) -> x14 + v163 Imm(0) -> x14 + v164 Imm(6) -> x14 + v165 Imm(48) -> x14 + v166 Imm(0) -> x14 + v167 Imm(0) -> x14 + v168 Imm(6) -> x14 + v169 Imm(5) -> x14 + v170 Imm(21474836480) -> x14 + v171 Imm(5) -> x14 + v172 Imm(40) -> x14 + v173 Imm(0) -> x14 + v174 LoadLocal { off=-3, kind=I64 } -> x14 + v175 Imm(0) -> x14 + v176 Imm(6) -> x14 + v177 Imm(48) -> x14 + v178 Imm(0) -> x14 + v179 LoadLocal { off=-2, kind=I64 } -> x14 + v180 BinopI { op=shl, lhs=v119, rhs_imm=1 } -> x12 + v181 Binop { op=add, lhs=v118, rhs=v180 } -> x12 + v182 Imm(0) -> x14 + v183 Imm(6) -> x14 + v184 Imm(5) -> x14 + v185 Imm(0) -> x14 + v186 Imm(5) -> x14 + v187 Imm(1) -> x14 + v188 Imm(0) -> x14 + v189 Imm(5) -> x14 + v190 Imm(40) -> x14 + v191 Imm(0) -> x14 + v192 Imm(0) -> x14 + v193 Imm(5) -> x14 + v194 Imm(4) -> x14 + v195 Imm(17179869184) -> x14 + v196 Imm(4) -> x14 + v197 Imm(32) -> x14 + v198 Imm(0) -> x14 + v199 LoadLocal { off=-4, kind=I64 } -> x14 + v200 Imm(0) -> x14 + v201 Imm(5) -> x14 + v202 Imm(40) -> x14 + v203 Imm(0) -> x14 + v204 LoadLocal { off=-3, kind=I64 } -> x14 + v205 BinopI { op=shl, lhs=v118, rhs_imm=1 } -> x3 + v206 Binop { op=add, lhs=v117, rhs=v205 } -> x3 + v207 Imm(0) -> x14 + v208 Imm(5) -> x14 + v209 Imm(4) -> x14 + v210 Imm(0) -> x14 + v211 Imm(4) -> x14 + v212 Imm(1) -> x14 + v213 Imm(0) -> x14 + v214 Imm(4) -> x14 + v215 Imm(32) -> x14 + v216 Imm(0) -> x14 + v217 Imm(0) -> x14 + v218 Imm(4) -> x14 + v219 Imm(3) -> x14 + v220 Imm(12884901888) -> x14 + v221 Imm(3) -> x14 + v222 Imm(24) -> x14 + v223 Imm(0) -> x14 + v224 LoadLocal { off=-5, kind=I64 } -> x14 + v225 Imm(0) -> x14 + v226 Imm(4) -> x14 + v227 Imm(32) -> x14 + v228 Imm(0) -> x14 + v229 LoadLocal { off=-4, kind=I64 } -> x14 + v230 BinopI { op=shl, lhs=v117, rhs_imm=1 } -> x9 + v231 Binop { op=add, lhs=v116, rhs=v230 } -> x9 + v232 Imm(0) -> x14 + v233 Imm(4) -> x14 + v234 Imm(3) -> x14 + v235 Imm(0) -> x14 + v236 Imm(3) -> x14 + v237 Imm(1) -> x14 + v238 Imm(0) -> x14 + v239 Imm(3) -> x14 + v240 Imm(24) -> x14 + v241 Imm(0) -> x14 + v242 Imm(0) -> x14 + v243 Imm(3) -> x14 + v244 Imm(2) -> x14 + v245 Imm(8589934592) -> x14 + v246 Imm(2) -> x14 + v247 Imm(16) -> x14 + v248 Imm(0) -> x14 + v249 LoadLocal { off=-6, kind=I64 } -> x14 + v250 Imm(0) -> x14 + v251 Imm(3) -> x14 + v252 Imm(24) -> x14 + v253 Imm(0) -> x14 + v254 LoadLocal { off=-5, kind=I64 } -> x14 + v255 BinopI { op=shl, lhs=v116, rhs_imm=1 } -> x8 + v256 Binop { op=add, lhs=v115, rhs=v255 } -> x8 + v257 Imm(0) -> x14 + v258 Imm(3) -> x14 + v259 Imm(2) -> x14 + v260 Imm(0) -> x14 + v261 Imm(2) -> x14 + v262 Imm(1) -> x14 + v263 Imm(0) -> x14 + v264 Imm(2) -> x14 + v265 Imm(16) -> x14 + v266 Imm(0) -> x14 + v267 Imm(0) -> x14 + v268 Imm(2) -> x14 + v269 Imm(1) -> x14 + v270 Imm(4294967296) -> x14 + v271 Imm(1) -> x14 + v272 Imm(8) -> x14 + v273 Imm(0) -> x14 + v274 LoadLocal { off=-7, kind=I64 } -> x14 + v275 Imm(0) -> x14 + v276 Imm(2) -> x14 + v277 Imm(16) -> x14 + v278 Imm(0) -> x14 + v279 LoadLocal { off=-6, kind=I64 } -> x14 + v280 BinopI { op=shl, lhs=v115, rhs_imm=1 } -> x6 + v281 Binop { op=add, lhs=v114, rhs=v280 } -> x6 + v282 Imm(0) -> x14 + v283 Imm(2) -> x14 + v284 Imm(1) -> x14 + v285 Imm(0) -> x14 + v286 Imm(1) -> x14 + v287 Imm(1) -> x14 + v288 Imm(0) -> x14 + v289 Imm(1) -> x14 + v290 Imm(8) -> x14 + v291 Imm(0) -> x14 + v292 Imm(0) -> x14 + v293 Imm(1) -> x14 + v294 Imm(0) -> x14 + v295 Imm(0) -> x14 + v296 Imm(0) -> x14 + v297 Imm(0) -> x14 + v298 Imm(0) -> x14 + v299 LoadLocal { off=-8, kind=I64 } -> x14 + v300 Imm(0) -> x14 + v301 Imm(1) -> x14 + v302 Imm(8) -> x14 + v303 Imm(0) -> x14 + v304 LoadLocal { off=-7, kind=I64 } -> x14 + v305 BinopI { op=shl, lhs=v114, rhs_imm=1 } -> x2 + v306 Binop { op=add, lhs=v113, rhs=v305 } -> x2 + v307 Imm(0) -> x14 + v308 Imm(1) -> x14 + v309 Imm(0) -> x14 + v310 Imm(0) -> x14 + v311 Imm(0) -> x14 + v312 Imm(0) -> x14 + terminator Jmp(b5) (exit_acc=v312) + block 5 start_pc=0 + v313 Imm(0) -> x14 + v314 Imm(0) -> x14 + v315 LoadLocal { off=-10, kind=I64 } -> x14 + v316 Imm(0) -> x14 + v317 LoadLocal { off=-8, kind=I64 } -> x14 + v318 BinopI { op=shl, lhs=v113, rhs_imm=1 } -> x1 + v319 Binop { op=xor, lhs=v120, rhs=v318 } -> x1 + v320 Imm(0) -> x7 + terminator Jmp(b6) (exit_acc=v319) + block 6 start_pc=0 + v113 Phi { incoming=[b2:v15, b5:v319], kind=I64 } -> x1 + v114 Phi { incoming=[b2:v28, b5:v306], kind=I64 } -> x2 + v115 Phi { incoming=[b2:v41, b5:v281], kind=I64 } -> x6 + v116 Phi { incoming=[b2:v54, b5:v256], kind=I64 } -> x8 + v117 Phi { incoming=[b2:v67, b5:v231], kind=I64 } -> x9 + v118 Phi { incoming=[b2:v80, b5:v206], kind=I64 } -> x3 + v119 Phi { incoming=[b2:v93, b5:v181], kind=I64 } -> x12 + v120 Phi { incoming=[b2:v106, b5:v156], kind=I64 } -> x7 + v121 Phi { incoming=[b2:v3, b5:v123], kind=I64 } -> x13 + v122 Extend { value=v121, kind=I32 } -> x0 + v123 BinopI { op=add, lhs=v122, rhs_imm=-1 } -> x13 + v124 Imm(0) -> x14 + v125 BinopI { op=gt, lhs=v122, rhs_imm=0 } -> x0 + terminator Bnz { cond=v125, target=b3, fall=b7 } (exit_acc=v125) + block 7 start_pc=0 + v133 Imm(0) -> x0 + v134 Imm(0) -> x13 + v135 Imm(0) -> x13 + terminator Jmp(b8) (exit_acc=v133) + block 8 start_pc=0 + v321 Imm(0) -> x0 + v322 Imm(1) -> x0 + v323 LoadLocal { off=-12, kind=I64 } -> x0 + v324 Imm(0) -> x0 + v325 Imm(0) -> x0 + v326 Imm(0) -> x0 + v327 Imm(0) -> x0 + v328 LoadLocal { off=-8, kind=I64 } -> x0 + v329 BinopI { op=add, lhs=v113, rhs_imm=0 } -> x0 + v330 Imm(0) -> x1 + v331 Imm(0) -> x1 + v332 Imm(1) -> x1 + v333 Imm(0) -> x1 + v334 Imm(1) -> x1 + v335 Imm(1) -> x1 + v336 LoadLocal { off=-12, kind=I64 } -> x1 + v337 Imm(0) -> x1 + v338 Imm(1) -> x1 + v339 Imm(8) -> x1 + v340 Imm(0) -> x1 + v341 LoadLocal { off=-7, kind=I64 } -> x1 + v342 Binop { op=add, lhs=v329, rhs=v114 } -> x0 + v343 Imm(0) -> x1 + v344 Imm(1) -> x1 + v345 Imm(2) -> x1 + v346 Imm(0) -> x1 + v347 Imm(2) -> x1 + v348 Imm(1) -> x1 + v349 LoadLocal { off=-12, kind=I64 } -> x1 + v350 Imm(0) -> x1 + v351 Imm(2) -> x1 + v352 Imm(16) -> x1 + v353 Imm(0) -> x1 + v354 LoadLocal { off=-6, kind=I64 } -> x1 + v355 Binop { op=add, lhs=v342, rhs=v115 } -> x0 + v356 Imm(0) -> x1 + v357 Imm(2) -> x1 + v358 Imm(3) -> x1 + v359 Imm(0) -> x1 + v360 Imm(3) -> x1 + v361 Imm(1) -> x1 + v362 LoadLocal { off=-12, kind=I64 } -> x1 + v363 Imm(0) -> x1 + v364 Imm(3) -> x1 + v365 Imm(24) -> x1 + v366 Imm(0) -> x1 + v367 LoadLocal { off=-5, kind=I64 } -> x1 + v368 Binop { op=add, lhs=v355, rhs=v116 } -> x0 + v369 Imm(0) -> x1 + v370 Imm(3) -> x1 + v371 Imm(4) -> x1 + v372 Imm(0) -> x1 + v373 Imm(4) -> x1 + v374 Imm(1) -> x1 + v375 LoadLocal { off=-12, kind=I64 } -> x1 + v376 Imm(0) -> x1 + v377 Imm(4) -> x1 + v378 Imm(32) -> x1 + v379 Imm(0) -> x1 + v380 LoadLocal { off=-4, kind=I64 } -> x1 + v381 Binop { op=add, lhs=v368, rhs=v117 } -> x0 + v382 Imm(0) -> x1 + v383 Imm(4) -> x1 + v384 Imm(5) -> x1 + v385 Imm(0) -> x1 + v386 Imm(5) -> x1 + v387 Imm(1) -> x1 + v388 LoadLocal { off=-12, kind=I64 } -> x1 + v389 Imm(0) -> x1 + v390 Imm(5) -> x1 + v391 Imm(40) -> x1 + v392 Imm(0) -> x1 + v393 LoadLocal { off=-3, kind=I64 } -> x1 + v394 Binop { op=add, lhs=v381, rhs=v118 } -> x0 + v395 Imm(0) -> x1 + v396 Imm(5) -> x1 + v397 Imm(6) -> x1 + v398 Imm(0) -> x1 + v399 Imm(6) -> x1 + v400 Imm(1) -> x1 + v401 LoadLocal { off=-12, kind=I64 } -> x1 + v402 Imm(0) -> x1 + v403 Imm(6) -> x1 + v404 Imm(48) -> x1 + v405 Imm(0) -> x1 + v406 LoadLocal { off=-2, kind=I64 } -> x1 + v407 Binop { op=add, lhs=v394, rhs=v119 } -> x0 + v408 Imm(0) -> x1 + v409 Imm(6) -> x1 + v410 Imm(7) -> x1 + v411 Imm(0) -> x1 + v412 Imm(7) -> x1 + v413 Imm(1) -> x1 + v414 LoadLocal { off=-12, kind=I64 } -> x1 + v415 Imm(0) -> x1 + v416 Imm(7) -> x1 + v417 Imm(56) -> x1 + v418 Imm(0) -> x1 + v419 LoadLocal { off=-1, kind=I64 } -> x1 + v420 Binop { op=add, lhs=v407, rhs=v120 } -> x0 + v421 Imm(0) -> x1 + v422 Imm(7) -> x1 + v423 Imm(8) -> x1 + v424 Imm(0) -> x1 + v425 Imm(8) -> x1 + v426 Imm(0) -> x1 + terminator Jmp(b9) (exit_acc=v426) + block 9 start_pc=0 + v427 LoadLocal { off=-12, kind=I64 } -> x1 + terminator Return(v420) (exit_acc=v420) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=11 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-8) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(0) -> x1 + v10 Imm(7) -> x1 + v11 Store { addr=v8, disp=0, value=v10, kind=I64 } -> - + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(0) -> x0 + v15 Imm(1) -> x0 + v16 Imm(1) -> x0 + v17 LocalAddr(-8) -> x0 + v18 Imm(1) -> x1 + v19 Imm(8) -> x1 + v20 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x1 + v21 Imm(4369) -> x1 + v22 Imm(4376) -> x1 + v23 Store { addr=v17, disp=8, value=v22, kind=I64 } -> - + v24 Imm(1) -> x0 + v25 Imm(2) -> x0 + v26 Imm(0) -> x0 + v27 Imm(2) -> x0 + v28 Imm(1) -> x0 + v29 LocalAddr(-8) -> x0 + v30 Imm(2) -> x1 + v31 Imm(16) -> x1 + v32 BinopI { op=add, lhs=v29, rhs_imm=16 } -> x1 + v33 Imm(8738) -> x1 + v34 Imm(8745) -> x1 + v35 Store { addr=v29, disp=16, value=v34, kind=I64 } -> - + v36 Imm(2) -> x0 + v37 Imm(3) -> x0 + v38 Imm(0) -> x0 + v39 Imm(3) -> x0 + v40 Imm(1) -> x0 + v41 LocalAddr(-8) -> x0 + v42 Imm(3) -> x1 + v43 Imm(24) -> x1 + v44 BinopI { op=add, lhs=v41, rhs_imm=24 } -> x1 + v45 Imm(13107) -> x1 + v46 Imm(13114) -> x1 + v47 Store { addr=v41, disp=24, value=v46, kind=I64 } -> - + v48 Imm(3) -> x0 + v49 Imm(4) -> x0 + v50 Imm(0) -> x0 + v51 Imm(4) -> x0 + v52 Imm(1) -> x0 + v53 LocalAddr(-8) -> x0 + v54 Imm(4) -> x1 + v55 Imm(32) -> x1 + v56 BinopI { op=add, lhs=v53, rhs_imm=32 } -> x1 + v57 Imm(17476) -> x1 + v58 Imm(17483) -> x1 + v59 Store { addr=v53, disp=32, value=v58, kind=I64 } -> - + v60 Imm(4) -> x0 + v61 Imm(5) -> x0 + v62 Imm(0) -> x0 + v63 Imm(5) -> x0 + v64 Imm(1) -> x0 + v65 LocalAddr(-8) -> x0 + v66 Imm(5) -> x1 + v67 Imm(40) -> x1 + v68 BinopI { op=add, lhs=v65, rhs_imm=40 } -> x1 + v69 Imm(21845) -> x1 + v70 Imm(21852) -> x1 + v71 Store { addr=v65, disp=40, value=v70, kind=I64 } -> - + v72 Imm(5) -> x0 + v73 Imm(6) -> x0 + v74 Imm(0) -> x0 + v75 Imm(6) -> x0 + v76 Imm(1) -> x0 + v77 LocalAddr(-8) -> x0 + v78 Imm(6) -> x1 + v79 Imm(48) -> x1 + v80 BinopI { op=add, lhs=v77, rhs_imm=48 } -> x1 + v81 Imm(26214) -> x1 + v82 Imm(26221) -> x1 + v83 Store { addr=v77, disp=48, value=v82, kind=I64 } -> - + v84 Imm(6) -> x0 + v85 Imm(7) -> x0 + v86 Imm(0) -> x0 + v87 Imm(7) -> x0 + v88 Imm(1) -> x0 + v89 LocalAddr(-8) -> x0 + v90 Imm(7) -> x1 + v91 Imm(56) -> x1 + v92 BinopI { op=add, lhs=v89, rhs_imm=56 } -> x1 + v93 Imm(30583) -> x1 + v94 Imm(30590) -> x1 + v95 Store { addr=v89, disp=56, value=v94, kind=I64 } -> - + v96 Imm(7) -> x0 + v97 Imm(8) -> x0 + v98 Imm(0) -> x0 + v99 Imm(8) -> x0 + v100 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v100) + block 2 start_pc=0 + v101 LocalAddr(-8) -> x7 + v102 Imm(5) -> x6 + v103 Call { target_pc=0, args=[v101, v102], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v104 BinopI { op=ne, lhs=v103, rhs_imm=21938052 } -> x0 + terminator Bz { cond=v104, target=b4, fall=b3 } (exit_acc=v104) + block 3 start_pc=0 + v105 Imm(1) -> x0 + terminator Return(v105) (exit_acc=v105) + block 4 start_pc=0 + v106 Imm(0) -> x0 + terminator Return(v106) (exit_acc=v106) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/sroa_runtime_index_stays_memory.ssa b/tests/snapshots/ssa/sroa_runtime_index_stays_memory.ssa new file mode 100644 index 000000000..84796ab54 --- /dev/null +++ b/tests/snapshots/ssa/sroa_runtime_index_stays_memory.ssa @@ -0,0 +1,307 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=pick +fn ent_pc=0 n_params=2 variadic=false locals=9 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v5) + block 1 start_pc=0 + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 LocalAddr(-8) -> x0 + v10 Imm(0) -> x1 + v11 Imm(0) -> x1 + v12 BinopI { op=add, lhs=v9, rhs_imm=0 } -> x0 + v13 LoadLocal { off=2, kind=I64 } -> x1 + v14 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x1 + v15 Load { addr=v14, disp=0, kind=I64 } -> x1 + v16 BinopI { op=mul, lhs=v15, rhs_imm=3 } -> x1 + v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x1 + v18 Store { addr=v12, disp=0, value=v17, kind=I64 } -> - + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(0) -> x0 + v22 Imm(1) -> x0 + v23 Imm(1) -> x0 + v24 LocalAddr(-8) -> x0 + v25 Imm(1) -> x1 + v26 Imm(8) -> x1 + v27 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x1 + v28 LoadLocal { off=2, kind=I64 } -> x1 + v29 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 + v30 Load { addr=v1, disp=8, kind=I64 } -> x1 + v31 BinopI { op=mul, lhs=v30, rhs_imm=3 } -> x1 + v32 BinopI { op=add, lhs=v31, rhs_imm=1 } -> x1 + v33 Store { addr=v24, disp=8, value=v32, kind=I64 } -> - + v34 Imm(1) -> x0 + v35 Imm(2) -> x0 + v36 Imm(0) -> x0 + v37 Imm(2) -> x0 + v38 Imm(1) -> x0 + v39 LocalAddr(-8) -> x0 + v40 Imm(2) -> x1 + v41 Imm(16) -> x1 + v42 BinopI { op=add, lhs=v39, rhs_imm=16 } -> x1 + v43 LoadLocal { off=2, kind=I64 } -> x1 + v44 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x1 + v45 Load { addr=v1, disp=16, kind=I64 } -> x1 + v46 BinopI { op=mul, lhs=v45, rhs_imm=3 } -> x1 + v47 BinopI { op=add, lhs=v46, rhs_imm=1 } -> x1 + v48 Store { addr=v39, disp=16, value=v47, kind=I64 } -> - + v49 Imm(2) -> x0 + v50 Imm(3) -> x0 + v51 Imm(0) -> x0 + v52 Imm(3) -> x0 + v53 Imm(1) -> x0 + v54 LocalAddr(-8) -> x0 + v55 Imm(3) -> x1 + v56 Imm(24) -> x1 + v57 BinopI { op=add, lhs=v54, rhs_imm=24 } -> x1 + v58 LoadLocal { off=2, kind=I64 } -> x1 + v59 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x1 + v60 Load { addr=v1, disp=24, kind=I64 } -> x1 + v61 BinopI { op=mul, lhs=v60, rhs_imm=3 } -> x1 + v62 BinopI { op=add, lhs=v61, rhs_imm=1 } -> x1 + v63 Store { addr=v54, disp=24, value=v62, kind=I64 } -> - + v64 Imm(3) -> x0 + v65 Imm(4) -> x0 + v66 Imm(0) -> x0 + v67 Imm(4) -> x0 + v68 Imm(1) -> x0 + v69 LocalAddr(-8) -> x0 + v70 Imm(4) -> x1 + v71 Imm(32) -> x1 + v72 BinopI { op=add, lhs=v69, rhs_imm=32 } -> x1 + v73 LoadLocal { off=2, kind=I64 } -> x1 + v74 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x1 + v75 Load { addr=v1, disp=32, kind=I64 } -> x1 + v76 BinopI { op=mul, lhs=v75, rhs_imm=3 } -> x1 + v77 BinopI { op=add, lhs=v76, rhs_imm=1 } -> x1 + v78 Store { addr=v69, disp=32, value=v77, kind=I64 } -> - + v79 Imm(4) -> x0 + v80 Imm(5) -> x0 + v81 Imm(0) -> x0 + v82 Imm(5) -> x0 + v83 Imm(1) -> x0 + v84 LocalAddr(-8) -> x0 + v85 Imm(5) -> x1 + v86 Imm(40) -> x1 + v87 BinopI { op=add, lhs=v84, rhs_imm=40 } -> x1 + v88 LoadLocal { off=2, kind=I64 } -> x1 + v89 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v90 Load { addr=v1, disp=40, kind=I64 } -> x1 + v91 BinopI { op=mul, lhs=v90, rhs_imm=3 } -> x1 + v92 BinopI { op=add, lhs=v91, rhs_imm=1 } -> x1 + v93 Store { addr=v84, disp=40, value=v92, kind=I64 } -> - + v94 Imm(5) -> x0 + v95 Imm(6) -> x0 + v96 Imm(0) -> x0 + v97 Imm(6) -> x0 + v98 Imm(1) -> x0 + v99 LocalAddr(-8) -> x0 + v100 Imm(6) -> x1 + v101 Imm(48) -> x1 + v102 BinopI { op=add, lhs=v99, rhs_imm=48 } -> x1 + v103 LoadLocal { off=2, kind=I64 } -> x1 + v104 BinopI { op=add, lhs=v1, rhs_imm=48 } -> x1 + v105 Load { addr=v1, disp=48, kind=I64 } -> x1 + v106 BinopI { op=mul, lhs=v105, rhs_imm=3 } -> x1 + v107 BinopI { op=add, lhs=v106, rhs_imm=1 } -> x1 + v108 Store { addr=v99, disp=48, value=v107, kind=I64 } -> - + v109 Imm(6) -> x0 + v110 Imm(7) -> x0 + v111 Imm(0) -> x0 + v112 Imm(7) -> x0 + v113 Imm(1) -> x0 + v114 LocalAddr(-8) -> x0 + v115 Imm(7) -> x1 + v116 Imm(56) -> x1 + v117 BinopI { op=add, lhs=v114, rhs_imm=56 } -> x1 + v118 LoadLocal { off=2, kind=I64 } -> x1 + v119 BinopI { op=add, lhs=v1, rhs_imm=56 } -> x1 + v120 Load { addr=v1, disp=56, kind=I64 } -> x1 + v121 BinopI { op=mul, lhs=v120, rhs_imm=3 } -> x1 + v122 BinopI { op=add, lhs=v121, rhs_imm=1 } -> x1 + v123 Store { addr=v114, disp=56, value=v122, kind=I64 } -> - + v124 Imm(7) -> x0 + v125 Imm(8) -> x0 + v126 Imm(0) -> x0 + v127 Imm(8) -> x0 + v128 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v128) + block 2 start_pc=0 + v129 LocalAddr(-8) -> x0 + v130 LoadLocal { off=3, kind=I32 } -> x1 + v131 BinopI { op=and, lhs=v3, rhs_imm=7 } -> x1 + v132 BinopI { op=shl, lhs=v131, rhs_imm=3 } -> x2 + v133 Binop { op=add, lhs=v129, rhs=v132 } -> x2 + v134 LoadIndexed { base=v129, index=v131, scale=8, kind=I64 } -> x0 + v135 LocalAddr(-8) -> x1 + v136 LoadLocal { off=3, kind=I32 } -> x2 + v137 BinopI { op=add, lhs=v3, rhs_imm=5 } -> x2 + v138 BinopI { op=shl, lhs=v137, rhs_imm=32 } -> x6 + v139 Extend { value=v137, kind=I32 } -> x2 + v140 BinopI { op=and, lhs=v139, rhs_imm=7 } -> x2 + v141 BinopI { op=shl, lhs=v140, rhs_imm=3 } -> x6 + v142 Binop { op=add, lhs=v135, rhs=v141 } -> x6 + v143 LoadIndexed { base=v135, index=v140, scale=8, kind=I64 } -> x1 + v144 Binop { op=add, lhs=v134, rhs=v143 } -> x0 + terminator Return(v144) (exit_acc=v144) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=11 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-8) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x2 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Store { addr=v8, disp=0, value=v6, kind=I64 } -> - + v10 Imm(0) -> x0 + v11 Imm(1) -> x0 + v12 Imm(0) -> x0 + v13 Imm(1) -> x0 + v14 Imm(1) -> x0 + v15 LocalAddr(-8) -> x0 + v16 Imm(1) -> x1 + v17 Imm(8) -> x2 + v18 BinopI { op=add, lhs=v15, rhs_imm=8 } -> x2 + v19 Store { addr=v15, disp=8, value=v16, kind=I64 } -> - + v20 Imm(1) -> x0 + v21 Imm(2) -> x0 + v22 Imm(0) -> x0 + v23 Imm(2) -> x0 + v24 Imm(1) -> x0 + v25 LocalAddr(-8) -> x0 + v26 Imm(2) -> x1 + v27 Imm(16) -> x2 + v28 BinopI { op=add, lhs=v25, rhs_imm=16 } -> x2 + v29 Store { addr=v25, disp=16, value=v26, kind=I64 } -> - + v30 Imm(2) -> x0 + v31 Imm(3) -> x0 + v32 Imm(0) -> x0 + v33 Imm(3) -> x0 + v34 Imm(1) -> x0 + v35 LocalAddr(-8) -> x0 + v36 Imm(3) -> x1 + v37 Imm(24) -> x2 + v38 BinopI { op=add, lhs=v35, rhs_imm=24 } -> x2 + v39 Store { addr=v35, disp=24, value=v36, kind=I64 } -> - + v40 Imm(3) -> x0 + v41 Imm(4) -> x0 + v42 Imm(0) -> x0 + v43 Imm(4) -> x0 + v44 Imm(1) -> x0 + v45 LocalAddr(-8) -> x0 + v46 Imm(4) -> x1 + v47 Imm(32) -> x2 + v48 BinopI { op=add, lhs=v45, rhs_imm=32 } -> x2 + v49 Store { addr=v45, disp=32, value=v46, kind=I64 } -> - + v50 Imm(4) -> x0 + v51 Imm(5) -> x0 + v52 Imm(0) -> x0 + v53 Imm(5) -> x0 + v54 Imm(1) -> x0 + v55 LocalAddr(-8) -> x0 + v56 Imm(5) -> x1 + v57 Imm(40) -> x2 + v58 BinopI { op=add, lhs=v55, rhs_imm=40 } -> x2 + v59 Store { addr=v55, disp=40, value=v56, kind=I64 } -> - + v60 Imm(5) -> x0 + v61 Imm(6) -> x0 + v62 Imm(0) -> x0 + v63 Imm(6) -> x0 + v64 Imm(1) -> x0 + v65 LocalAddr(-8) -> x0 + v66 Imm(6) -> x1 + v67 Imm(48) -> x2 + v68 BinopI { op=add, lhs=v65, rhs_imm=48 } -> x2 + v69 Store { addr=v65, disp=48, value=v66, kind=I64 } -> - + v70 Imm(6) -> x0 + v71 Imm(7) -> x0 + v72 Imm(0) -> x0 + v73 Imm(7) -> x0 + v74 Imm(1) -> x0 + v75 LocalAddr(-8) -> x0 + v76 Imm(7) -> x1 + v77 Imm(56) -> x2 + v78 BinopI { op=add, lhs=v75, rhs_imm=56 } -> x2 + v79 Store { addr=v75, disp=56, value=v76, kind=I64 } -> - + v80 Imm(7) -> x0 + v81 Imm(8) -> x0 + v82 Imm(0) -> x0 + v83 Imm(8) -> x0 + v84 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v84) + block 2 start_pc=0 + v85 LocalAddr(-8) -> x7 + v86 Imm(10) -> x6 + v87 Call { target_pc=0, args=[v85, v86], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v88 BinopI { op=ne, lhs=v87, rhs_imm=29 } -> x0 + terminator Bz { cond=v88, target=b4, fall=b3 } (exit_acc=v88) + block 3 start_pc=0 + v89 Imm(1) -> x0 + terminator Return(v89) (exit_acc=v89) + block 4 start_pc=0 + v90 Imm(0) -> x0 + terminator Return(v90) (exit_acc=v90) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/ssa_bail_fixup_rollback.ssa b/tests/snapshots/ssa/ssa_bail_fixup_rollback.ssa index 49e0a6608..8e8931d0d 100644 --- a/tests/snapshots/ssa/ssa_bail_fixup_rollback.ssa +++ b/tests/snapshots/ssa/ssa_bail_fixup_rollback.ssa @@ -39,7 +39,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=core fn ent_pc=1 n_params=4 variadic=false locals=10 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13, 14] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -52,197 +52,197 @@ fn ent_pc=1 n_params=4 variadic=false locals=10 v8 Imm(0) -> x0 v9 Imm(0) -> x8 v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v11 Phi { incoming=[b0:v9, b2:v15], kind=I64 } -> x8 - v12 Extend { value=v11, kind=I32 } -> x0 - v13 BinopI { op=lt, lhs=v12, rhs_imm=4 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) - block 2 start_pc=0 - v14 Extend { value=v11, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x8 - v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) - block 3 start_pc=0 - v17 LocalAddr(-8) -> x0 - v18 Imm(5) -> x9 - v19 Extend { value=v11, kind=I32 } -> x9 - v20 BinopI { op=mul, lhs=v11, rhs_imm=5 } -> x9 - v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x3 - v22 Extend { value=v20, kind=I32 } -> x9 - v23 BinopI { op=shl, lhs=v22, rhs_imm=2 } -> x3 - v24 Binop { op=add, lhs=v17, rhs=v23 } -> x3 - v25 LoadLocal { off=5, kind=I64 } -> x3 - v26 Imm(4) -> x3 - v27 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x12 - v29 Extend { value=v27, kind=I32 } -> x3 - v30 Binop { op=add, lhs=v7, rhs=v29 } -> x3 - v31 Imm(0) -> x12 - v32 Imm(3) -> x12 - v33 BinopI { op=add, lhs=v30, rhs_imm=3 } -> x12 - v34 Load { addr=v30, disp=3, kind=U8 } -> x12 - v35 Imm(0) -> x13 - v36 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x12 - v37 BinopI { op=shl, lhs=v36, rhs_imm=8 } -> x12 - v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x12 - v39 Imm(2) -> x13 - v40 BinopI { op=add, lhs=v30, rhs_imm=2 } -> x13 - v41 Load { addr=v30, disp=2, kind=U8 } -> x13 - v42 Binop { op=or, lhs=v38, rhs=v41 } -> x12 - v43 Imm(0) -> x13 - v44 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x13 - v45 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x12 - v46 BinopI { op=shl, lhs=v45, rhs_imm=8 } -> x12 - v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x12 - v48 Imm(1) -> x13 - v49 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x13 - v50 Load { addr=v30, disp=1, kind=U8 } -> x13 - v51 Binop { op=or, lhs=v47, rhs=v50 } -> x12 - v52 Imm(0) -> x13 - v53 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x13 - v54 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x12 - v55 BinopI { op=shl, lhs=v54, rhs_imm=8 } -> x12 - v56 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x12 - v57 Imm(0) -> x13 - v58 Load { addr=v30, disp=0, kind=U8 } -> x3 - v59 Binop { op=or, lhs=v56, rhs=v58 } -> x3 + v17 LocalAddr(-8) -> x9 + v18 Imm(5) -> x3 + v19 Extend { value=v11, kind=I32 } -> x3 + v20 BinopI { op=mul, lhs=v11, rhs_imm=5 } -> x3 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x12 + v22 Extend { value=v20, kind=I32 } -> x3 + v23 BinopI { op=shl, lhs=v22, rhs_imm=2 } -> x12 + v24 Binop { op=add, lhs=v17, rhs=v23 } -> x12 + v25 LoadLocal { off=5, kind=I64 } -> x12 + v26 Imm(4) -> x12 + v27 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x13 + v29 Extend { value=v27, kind=I32 } -> x12 + v30 Binop { op=add, lhs=v7, rhs=v29 } -> x12 + v31 Imm(0) -> x13 + v32 Imm(3) -> x13 + v33 BinopI { op=add, lhs=v30, rhs_imm=3 } -> x13 + v34 Load { addr=v30, disp=3, kind=U8 } -> x13 + v35 Imm(0) -> x14 + v36 BinopI { op=and, lhs=v34, rhs_imm=4294967295 } -> x13 + v37 BinopI { op=shl, lhs=v36, rhs_imm=8 } -> x13 + v38 BinopI { op=and, lhs=v37, rhs_imm=4294967295 } -> x13 + v39 Imm(2) -> x14 + v40 BinopI { op=add, lhs=v30, rhs_imm=2 } -> x14 + v41 Load { addr=v30, disp=2, kind=U8 } -> x14 + v42 Binop { op=or, lhs=v38, rhs=v41 } -> x13 + v43 Imm(0) -> x14 + v44 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x14 + v45 BinopI { op=and, lhs=v42, rhs_imm=4294967295 } -> x13 + v46 BinopI { op=shl, lhs=v45, rhs_imm=8 } -> x13 + v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x13 + v48 Imm(1) -> x14 + v49 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x14 + v50 Load { addr=v30, disp=1, kind=U8 } -> x14 + v51 Binop { op=or, lhs=v47, rhs=v50 } -> x13 + v52 Imm(0) -> x14 + v53 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x14 + v54 BinopI { op=and, lhs=v51, rhs_imm=4294967295 } -> x13 + v55 BinopI { op=shl, lhs=v54, rhs_imm=8 } -> x13 + v56 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x13 + v57 Imm(0) -> x14 + v58 Load { addr=v30, disp=0, kind=U8 } -> x12 + v59 Binop { op=or, lhs=v56, rhs=v58 } -> x12 v60 StoreIndexed { base=v17, index=v22, scale=4, value=v59, kind=I32 } -> - - v61 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x0 - v62 LocalAddr(-8) -> x0 - v63 Imm(1) -> x9 - v64 Extend { value=v11, kind=I32 } -> x9 - v65 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x9 - v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x3 - v67 Extend { value=v65, kind=I32 } -> x9 - v68 BinopI { op=shl, lhs=v67, rhs_imm=2 } -> x3 - v69 Binop { op=add, lhs=v62, rhs=v68 } -> x3 - v70 LoadLocal { off=4, kind=I64 } -> x3 - v71 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x12 - v73 Extend { value=v71, kind=I32 } -> x3 - v74 Binop { op=add, lhs=v5, rhs=v73 } -> x3 - v75 Imm(0) -> x12 - v76 Imm(3) -> x12 - v77 BinopI { op=add, lhs=v74, rhs_imm=3 } -> x12 - v78 Load { addr=v74, disp=3, kind=U8 } -> x12 - v79 Imm(0) -> x13 - v80 BinopI { op=and, lhs=v78, rhs_imm=4294967295 } -> x12 - v81 BinopI { op=shl, lhs=v80, rhs_imm=8 } -> x12 - v82 BinopI { op=and, lhs=v81, rhs_imm=4294967295 } -> x12 - v83 Imm(2) -> x13 - v84 BinopI { op=add, lhs=v74, rhs_imm=2 } -> x13 - v85 Load { addr=v74, disp=2, kind=U8 } -> x13 - v86 Binop { op=or, lhs=v82, rhs=v85 } -> x12 - v87 Imm(0) -> x13 - v88 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x13 - v89 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x12 - v90 BinopI { op=shl, lhs=v89, rhs_imm=8 } -> x12 - v91 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x12 - v92 Imm(1) -> x13 - v93 BinopI { op=add, lhs=v74, rhs_imm=1 } -> x13 - v94 Load { addr=v74, disp=1, kind=U8 } -> x13 - v95 Binop { op=or, lhs=v91, rhs=v94 } -> x12 - v96 Imm(0) -> x13 - v97 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x13 - v98 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x12 - v99 BinopI { op=shl, lhs=v98, rhs_imm=8 } -> x12 - v100 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x12 - v101 Imm(0) -> x13 - v102 Load { addr=v74, disp=0, kind=U8 } -> x3 - v103 Binop { op=or, lhs=v100, rhs=v102 } -> x3 + v61 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x9 + v62 LocalAddr(-8) -> x9 + v63 Imm(1) -> x3 + v64 Extend { value=v11, kind=I32 } -> x3 + v65 BinopI { op=add, lhs=v11, rhs_imm=1 } -> x3 + v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x12 + v67 Extend { value=v65, kind=I32 } -> x3 + v68 BinopI { op=shl, lhs=v67, rhs_imm=2 } -> x12 + v69 Binop { op=add, lhs=v62, rhs=v68 } -> x12 + v70 LoadLocal { off=4, kind=I64 } -> x12 + v71 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x13 + v73 Extend { value=v71, kind=I32 } -> x12 + v74 Binop { op=add, lhs=v5, rhs=v73 } -> x12 + v75 Imm(0) -> x13 + v76 Imm(3) -> x13 + v77 BinopI { op=add, lhs=v74, rhs_imm=3 } -> x13 + v78 Load { addr=v74, disp=3, kind=U8 } -> x13 + v79 Imm(0) -> x14 + v80 BinopI { op=and, lhs=v78, rhs_imm=4294967295 } -> x13 + v81 BinopI { op=shl, lhs=v80, rhs_imm=8 } -> x13 + v82 BinopI { op=and, lhs=v81, rhs_imm=4294967295 } -> x13 + v83 Imm(2) -> x14 + v84 BinopI { op=add, lhs=v74, rhs_imm=2 } -> x14 + v85 Load { addr=v74, disp=2, kind=U8 } -> x14 + v86 Binop { op=or, lhs=v82, rhs=v85 } -> x13 + v87 Imm(0) -> x14 + v88 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x14 + v89 BinopI { op=and, lhs=v86, rhs_imm=4294967295 } -> x13 + v90 BinopI { op=shl, lhs=v89, rhs_imm=8 } -> x13 + v91 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x13 + v92 Imm(1) -> x14 + v93 BinopI { op=add, lhs=v74, rhs_imm=1 } -> x14 + v94 Load { addr=v74, disp=1, kind=U8 } -> x14 + v95 Binop { op=or, lhs=v91, rhs=v94 } -> x13 + v96 Imm(0) -> x14 + v97 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x14 + v98 BinopI { op=and, lhs=v95, rhs_imm=4294967295 } -> x13 + v99 BinopI { op=shl, lhs=v98, rhs_imm=8 } -> x13 + v100 BinopI { op=and, lhs=v99, rhs_imm=4294967295 } -> x13 + v101 Imm(0) -> x14 + v102 Load { addr=v74, disp=0, kind=U8 } -> x12 + v103 Binop { op=or, lhs=v100, rhs=v102 } -> x12 v104 StoreIndexed { base=v62, index=v67, scale=4, value=v103, kind=I32 } -> - - v105 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x0 - v106 LocalAddr(-8) -> x0 - v107 Imm(6) -> x9 - v108 Extend { value=v11, kind=I32 } -> x9 - v109 BinopI { op=add, lhs=v11, rhs_imm=6 } -> x9 - v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x3 - v111 Extend { value=v109, kind=I32 } -> x9 - v112 BinopI { op=shl, lhs=v111, rhs_imm=2 } -> x3 - v113 Binop { op=add, lhs=v106, rhs=v112 } -> x3 - v114 LoadLocal { off=3, kind=I64 } -> x3 - v115 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x3 - v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> x12 - v117 Extend { value=v115, kind=I32 } -> x3 - v118 Binop { op=add, lhs=v3, rhs=v117 } -> x3 - v119 Imm(0) -> x12 - v120 Imm(3) -> x12 - v121 BinopI { op=add, lhs=v118, rhs_imm=3 } -> x12 - v122 Load { addr=v118, disp=3, kind=U8 } -> x12 - v123 Imm(0) -> x13 - v124 BinopI { op=and, lhs=v122, rhs_imm=4294967295 } -> x12 - v125 BinopI { op=shl, lhs=v124, rhs_imm=8 } -> x12 - v126 BinopI { op=and, lhs=v125, rhs_imm=4294967295 } -> x12 - v127 Imm(2) -> x13 - v128 BinopI { op=add, lhs=v118, rhs_imm=2 } -> x13 - v129 Load { addr=v118, disp=2, kind=U8 } -> x13 - v130 Binop { op=or, lhs=v126, rhs=v129 } -> x12 - v131 Imm(0) -> x13 - v132 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x13 - v133 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x12 - v134 BinopI { op=shl, lhs=v133, rhs_imm=8 } -> x12 - v135 BinopI { op=and, lhs=v134, rhs_imm=4294967295 } -> x12 - v136 Imm(1) -> x13 - v137 BinopI { op=add, lhs=v118, rhs_imm=1 } -> x13 - v138 Load { addr=v118, disp=1, kind=U8 } -> x13 - v139 Binop { op=or, lhs=v135, rhs=v138 } -> x12 - v140 Imm(0) -> x13 - v141 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x13 - v142 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x12 - v143 BinopI { op=shl, lhs=v142, rhs_imm=8 } -> x12 - v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x12 - v145 Imm(0) -> x13 - v146 Load { addr=v118, disp=0, kind=U8 } -> x3 - v147 Binop { op=or, lhs=v144, rhs=v146 } -> x3 + v105 BinopI { op=and, lhs=v103, rhs_imm=4294967295 } -> x9 + v106 LocalAddr(-8) -> x9 + v107 Imm(6) -> x3 + v108 Extend { value=v11, kind=I32 } -> x3 + v109 BinopI { op=add, lhs=v11, rhs_imm=6 } -> x3 + v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x12 + v111 Extend { value=v109, kind=I32 } -> x3 + v112 BinopI { op=shl, lhs=v111, rhs_imm=2 } -> x12 + v113 Binop { op=add, lhs=v106, rhs=v112 } -> x12 + v114 LoadLocal { off=3, kind=I64 } -> x12 + v115 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 + v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> x13 + v117 Extend { value=v115, kind=I32 } -> x12 + v118 Binop { op=add, lhs=v3, rhs=v117 } -> x12 + v119 Imm(0) -> x13 + v120 Imm(3) -> x13 + v121 BinopI { op=add, lhs=v118, rhs_imm=3 } -> x13 + v122 Load { addr=v118, disp=3, kind=U8 } -> x13 + v123 Imm(0) -> x14 + v124 BinopI { op=and, lhs=v122, rhs_imm=4294967295 } -> x13 + v125 BinopI { op=shl, lhs=v124, rhs_imm=8 } -> x13 + v126 BinopI { op=and, lhs=v125, rhs_imm=4294967295 } -> x13 + v127 Imm(2) -> x14 + v128 BinopI { op=add, lhs=v118, rhs_imm=2 } -> x14 + v129 Load { addr=v118, disp=2, kind=U8 } -> x14 + v130 Binop { op=or, lhs=v126, rhs=v129 } -> x13 + v131 Imm(0) -> x14 + v132 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x14 + v133 BinopI { op=and, lhs=v130, rhs_imm=4294967295 } -> x13 + v134 BinopI { op=shl, lhs=v133, rhs_imm=8 } -> x13 + v135 BinopI { op=and, lhs=v134, rhs_imm=4294967295 } -> x13 + v136 Imm(1) -> x14 + v137 BinopI { op=add, lhs=v118, rhs_imm=1 } -> x14 + v138 Load { addr=v118, disp=1, kind=U8 } -> x14 + v139 Binop { op=or, lhs=v135, rhs=v138 } -> x13 + v140 Imm(0) -> x14 + v141 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x14 + v142 BinopI { op=and, lhs=v139, rhs_imm=4294967295 } -> x13 + v143 BinopI { op=shl, lhs=v142, rhs_imm=8 } -> x13 + v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x13 + v145 Imm(0) -> x14 + v146 Load { addr=v118, disp=0, kind=U8 } -> x12 + v147 Binop { op=or, lhs=v144, rhs=v146 } -> x12 v148 StoreIndexed { base=v106, index=v111, scale=4, value=v147, kind=I32 } -> - - v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x0 - v150 LocalAddr(-8) -> x0 - v151 Imm(11) -> x9 - v152 Extend { value=v11, kind=I32 } -> x9 - v153 BinopI { op=add, lhs=v11, rhs_imm=11 } -> x9 - v154 BinopI { op=shl, lhs=v153, rhs_imm=32 } -> x3 - v155 Extend { value=v153, kind=I32 } -> x9 - v156 BinopI { op=shl, lhs=v155, rhs_imm=2 } -> x3 - v157 Binop { op=add, lhs=v150, rhs=v156 } -> x3 - v158 LoadLocal { off=4, kind=I64 } -> x3 - v159 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x3 - v160 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x12 - v161 BinopI { op=shl, lhs=v160, rhs_imm=32 } -> x13 - v162 Extend { value=v160, kind=I32 } -> x12 - v163 Binop { op=add, lhs=v159, rhs=v162 } -> x3 - v164 Imm(0) -> x12 - v165 Imm(3) -> x12 - v166 BinopI { op=add, lhs=v163, rhs_imm=3 } -> x12 - v167 Load { addr=v163, disp=3, kind=U8 } -> x12 - v168 Imm(0) -> x13 - v169 BinopI { op=and, lhs=v167, rhs_imm=4294967295 } -> x12 - v170 BinopI { op=shl, lhs=v169, rhs_imm=8 } -> x12 - v171 BinopI { op=and, lhs=v170, rhs_imm=4294967295 } -> x12 - v172 Imm(2) -> x13 - v173 BinopI { op=add, lhs=v163, rhs_imm=2 } -> x13 - v174 Load { addr=v163, disp=2, kind=U8 } -> x13 - v175 Binop { op=or, lhs=v171, rhs=v174 } -> x12 - v176 Imm(0) -> x13 - v177 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x13 - v178 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x12 - v179 BinopI { op=shl, lhs=v178, rhs_imm=8 } -> x12 - v180 BinopI { op=and, lhs=v179, rhs_imm=4294967295 } -> x12 - v181 Imm(1) -> x13 - v182 BinopI { op=add, lhs=v163, rhs_imm=1 } -> x13 - v183 Load { addr=v163, disp=1, kind=U8 } -> x13 - v184 Binop { op=or, lhs=v180, rhs=v183 } -> x12 - v185 Imm(0) -> x13 - v186 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x13 - v187 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x12 - v188 BinopI { op=shl, lhs=v187, rhs_imm=8 } -> x12 - v189 BinopI { op=and, lhs=v188, rhs_imm=4294967295 } -> x12 - v190 Imm(0) -> x13 - v191 Load { addr=v163, disp=0, kind=U8 } -> x3 - v192 Binop { op=or, lhs=v189, rhs=v191 } -> x3 + v149 BinopI { op=and, lhs=v147, rhs_imm=4294967295 } -> x9 + v150 LocalAddr(-8) -> x9 + v151 Imm(11) -> x3 + v152 Extend { value=v11, kind=I32 } -> x3 + v153 BinopI { op=add, lhs=v11, rhs_imm=11 } -> x3 + v154 BinopI { op=shl, lhs=v153, rhs_imm=32 } -> x12 + v155 Extend { value=v153, kind=I32 } -> x3 + v156 BinopI { op=shl, lhs=v155, rhs_imm=2 } -> x12 + v157 Binop { op=add, lhs=v150, rhs=v156 } -> x12 + v158 LoadLocal { off=4, kind=I64 } -> x12 + v159 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x12 + v160 BinopI { op=shl, lhs=v11, rhs_imm=2 } -> x13 + v161 BinopI { op=shl, lhs=v160, rhs_imm=32 } -> x14 + v162 Extend { value=v160, kind=I32 } -> x13 + v163 Binop { op=add, lhs=v159, rhs=v162 } -> x12 + v164 Imm(0) -> x13 + v165 Imm(3) -> x13 + v166 BinopI { op=add, lhs=v163, rhs_imm=3 } -> x13 + v167 Load { addr=v163, disp=3, kind=U8 } -> x13 + v168 Imm(0) -> x14 + v169 BinopI { op=and, lhs=v167, rhs_imm=4294967295 } -> x13 + v170 BinopI { op=shl, lhs=v169, rhs_imm=8 } -> x13 + v171 BinopI { op=and, lhs=v170, rhs_imm=4294967295 } -> x13 + v172 Imm(2) -> x14 + v173 BinopI { op=add, lhs=v163, rhs_imm=2 } -> x14 + v174 Load { addr=v163, disp=2, kind=U8 } -> x14 + v175 Binop { op=or, lhs=v171, rhs=v174 } -> x13 + v176 Imm(0) -> x14 + v177 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x14 + v178 BinopI { op=and, lhs=v175, rhs_imm=4294967295 } -> x13 + v179 BinopI { op=shl, lhs=v178, rhs_imm=8 } -> x13 + v180 BinopI { op=and, lhs=v179, rhs_imm=4294967295 } -> x13 + v181 Imm(1) -> x14 + v182 BinopI { op=add, lhs=v163, rhs_imm=1 } -> x14 + v183 Load { addr=v163, disp=1, kind=U8 } -> x14 + v184 Binop { op=or, lhs=v180, rhs=v183 } -> x13 + v185 Imm(0) -> x14 + v186 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x14 + v187 BinopI { op=and, lhs=v184, rhs_imm=4294967295 } -> x13 + v188 BinopI { op=shl, lhs=v187, rhs_imm=8 } -> x13 + v189 BinopI { op=and, lhs=v188, rhs_imm=4294967295 } -> x13 + v190 Imm(0) -> x14 + v191 Load { addr=v163, disp=0, kind=U8 } -> x12 + v192 Binop { op=or, lhs=v189, rhs=v191 } -> x12 v193 StoreIndexed { base=v150, index=v155, scale=4, value=v192, kind=I32 } -> - - v194 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x0 + v194 BinopI { op=and, lhs=v192, rhs_imm=4294967295 } -> x9 terminator Jmp(b2) (exit_acc=v194) + block 2 start_pc=0 + v14 Extend { value=v11, kind=I32 } -> x8 + v15 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x8 + v16 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) + block 3 start_pc=0 + v11 Phi { incoming=[b0:v9, b2:v15], kind=I64 } -> x8 + v12 Extend { value=v11, kind=I32 } -> x0 + v13 BinopI { op=lt, lhs=v12, rhs_imm=4 } -> x9 + terminator Bnz { cond=v13, target=b1, fall=b4 } (exit_acc=v13) block 4 start_pc=0 v195 LoadLocal { off=2, kind=I64 } -> x0 v196 Imm(0) -> x0 @@ -289,127 +289,355 @@ fn ent_pc=2 n_params=5 variadic=false locals=16 v13 Imm(0) -> x0 terminator Return(v13) (exit_acc=v13) block 2 start_pc=0 - v14 Imm(0) -> x2 - v15 Imm(0) -> x0 + v14 Imm(0) -> x0 + v15 Imm(0) -> x2 terminator Jmp(b3) (exit_acc=v14) block 3 start_pc=0 - v16 Phi { incoming=[b2:v14, b4:v20], kind=I64 } -> x2 - v17 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x0 - v18 BinopI { op=ult, lhs=v17, rhs_imm=16 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v16 Imm(0) -> x0 + v17 Imm(1) -> x0 + v18 LocalAddr(-2) -> x0 + v19 Imm(0) -> x2 + v20 BinopI { op=add, lhs=v18, rhs_imm=0 } -> x0 + v21 Imm(0) -> x2 + v22 Store { addr=v20, disp=0, value=v21, kind=I8 } -> - + v23 Imm(0) -> x0 + v24 Imm(1) -> x0 + v25 Imm(0) -> x0 + v26 Imm(1) -> x0 + v27 Imm(1) -> x0 + v28 LocalAddr(-2) -> x0 + v29 Imm(1) -> x2 + v30 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x2 + v31 Imm(0) -> x2 + v32 Store { addr=v28, disp=1, value=v31, kind=I8 } -> - + v33 Imm(1) -> x0 + v34 Imm(2) -> x0 + v35 Imm(0) -> x0 + v36 Imm(2) -> x0 + v37 Imm(1) -> x0 + v38 LocalAddr(-2) -> x0 + v39 Imm(2) -> x2 + v40 BinopI { op=add, lhs=v38, rhs_imm=2 } -> x2 + v41 Imm(0) -> x2 + v42 Store { addr=v38, disp=2, value=v41, kind=I8 } -> - + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(0) -> x0 + v46 Imm(3) -> x0 + v47 Imm(1) -> x0 + v48 LocalAddr(-2) -> x0 + v49 Imm(3) -> x2 + v50 BinopI { op=add, lhs=v48, rhs_imm=3 } -> x2 + v51 Imm(0) -> x2 + v52 Store { addr=v48, disp=3, value=v51, kind=I8 } -> - + v53 Imm(3) -> x0 + v54 Imm(4) -> x0 + v55 Imm(0) -> x0 + v56 Imm(4) -> x0 + v57 Imm(1) -> x0 + v58 LocalAddr(-2) -> x0 + v59 Imm(4) -> x2 + v60 BinopI { op=add, lhs=v58, rhs_imm=4 } -> x2 + v61 Imm(0) -> x2 + v62 Store { addr=v58, disp=4, value=v61, kind=I8 } -> - + v63 Imm(4) -> x0 + v64 Imm(5) -> x0 + v65 Imm(0) -> x0 + v66 Imm(5) -> x0 + v67 Imm(1) -> x0 + v68 LocalAddr(-2) -> x0 + v69 Imm(5) -> x2 + v70 BinopI { op=add, lhs=v68, rhs_imm=5 } -> x2 + v71 Imm(0) -> x2 + v72 Store { addr=v68, disp=5, value=v71, kind=I8 } -> - + v73 Imm(5) -> x0 + v74 Imm(6) -> x0 + v75 Imm(0) -> x0 + v76 Imm(6) -> x0 + v77 Imm(1) -> x0 + v78 LocalAddr(-2) -> x0 + v79 Imm(6) -> x2 + v80 BinopI { op=add, lhs=v78, rhs_imm=6 } -> x2 + v81 Imm(0) -> x2 + v82 Store { addr=v78, disp=6, value=v81, kind=I8 } -> - + v83 Imm(6) -> x0 + v84 Imm(7) -> x0 + v85 Imm(0) -> x0 + v86 Imm(7) -> x0 + v87 Imm(1) -> x0 + v88 LocalAddr(-2) -> x0 + v89 Imm(7) -> x2 + v90 BinopI { op=add, lhs=v88, rhs_imm=7 } -> x2 + v91 Imm(0) -> x2 + v92 Store { addr=v88, disp=7, value=v91, kind=I8 } -> - + v93 Imm(7) -> x0 + v94 Imm(8) -> x0 + v95 Imm(0) -> x0 + v96 Imm(8) -> x0 + v97 Imm(1) -> x0 + v98 LocalAddr(-2) -> x0 + v99 Imm(8) -> x2 + v100 BinopI { op=add, lhs=v98, rhs_imm=8 } -> x2 + v101 Imm(0) -> x2 + v102 Store { addr=v98, disp=8, value=v101, kind=I8 } -> - + v103 Imm(8) -> x0 + v104 Imm(9) -> x0 + v105 Imm(0) -> x0 + v106 Imm(9) -> x0 + v107 Imm(1) -> x0 + v108 LocalAddr(-2) -> x0 + v109 Imm(9) -> x2 + v110 BinopI { op=add, lhs=v108, rhs_imm=9 } -> x2 + v111 Imm(0) -> x2 + v112 Store { addr=v108, disp=9, value=v111, kind=I8 } -> - + v113 Imm(9) -> x0 + v114 Imm(10) -> x0 + v115 Imm(0) -> x0 + v116 Imm(10) -> x0 + v117 Imm(1) -> x0 + v118 LocalAddr(-2) -> x0 + v119 Imm(10) -> x2 + v120 BinopI { op=add, lhs=v118, rhs_imm=10 } -> x2 + v121 Imm(0) -> x2 + v122 Store { addr=v118, disp=10, value=v121, kind=I8 } -> - + v123 Imm(10) -> x0 + v124 Imm(11) -> x0 + v125 Imm(0) -> x0 + v126 Imm(11) -> x0 + v127 Imm(1) -> x0 + v128 LocalAddr(-2) -> x0 + v129 Imm(11) -> x2 + v130 BinopI { op=add, lhs=v128, rhs_imm=11 } -> x2 + v131 Imm(0) -> x2 + v132 Store { addr=v128, disp=11, value=v131, kind=I8 } -> - + v133 Imm(11) -> x0 + v134 Imm(12) -> x0 + v135 Imm(0) -> x0 + v136 Imm(12) -> x0 + v137 Imm(1) -> x0 + v138 LocalAddr(-2) -> x0 + v139 Imm(12) -> x2 + v140 BinopI { op=add, lhs=v138, rhs_imm=12 } -> x2 + v141 Imm(0) -> x2 + v142 Store { addr=v138, disp=12, value=v141, kind=I8 } -> - + v143 Imm(12) -> x0 + v144 Imm(13) -> x0 + v145 Imm(0) -> x0 + v146 Imm(13) -> x0 + v147 Imm(1) -> x0 + v148 LocalAddr(-2) -> x0 + v149 Imm(13) -> x2 + v150 BinopI { op=add, lhs=v148, rhs_imm=13 } -> x2 + v151 Imm(0) -> x2 + v152 Store { addr=v148, disp=13, value=v151, kind=I8 } -> - + v153 Imm(13) -> x0 + v154 Imm(14) -> x0 + v155 Imm(0) -> x0 + v156 Imm(14) -> x0 + v157 Imm(1) -> x0 + v158 LocalAddr(-2) -> x0 + v159 Imm(14) -> x2 + v160 BinopI { op=add, lhs=v158, rhs_imm=14 } -> x2 + v161 Imm(0) -> x2 + v162 Store { addr=v158, disp=14, value=v161, kind=I8 } -> - + v163 Imm(14) -> x0 + v164 Imm(15) -> x0 + v165 Imm(0) -> x0 + v166 Imm(15) -> x0 + v167 Imm(1) -> x0 + v168 LocalAddr(-2) -> x0 + v169 Imm(15) -> x2 + v170 BinopI { op=add, lhs=v168, rhs_imm=15 } -> x2 + v171 Imm(0) -> x2 + v172 Store { addr=v168, disp=15, value=v171, kind=I8 } -> - + v173 Imm(15) -> x0 + v174 Imm(16) -> x0 + v175 Imm(0) -> x0 + v176 Imm(16) -> x0 + v177 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v177) block 4 start_pc=0 - v19 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x2 - v21 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v20) + v178 Imm(0) -> x0 + v179 Imm(0) -> x2 + terminator Jmp(b5) (exit_acc=v178) block 5 start_pc=0 - v22 LocalAddr(-2) -> x0 - v23 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x6 - v24 Binop { op=add, lhs=v22, rhs=v23 } -> x0 - v25 Imm(0) -> x6 - v26 Store { addr=v24, disp=0, value=v25, kind=I8 } -> - - terminator Jmp(b4) (exit_acc=v26) + v180 Imm(0) -> x0 + v181 Imm(1) -> x0 + v182 LocalAddr(-2) -> x0 + v183 Imm(0) -> x2 + v184 BinopI { op=add, lhs=v182, rhs_imm=0 } -> x0 + v185 LoadLocal { off=5, kind=I64 } -> x2 + v186 BinopI { op=add, lhs=v7, rhs_imm=0 } -> x2 + v187 Load { addr=v186, disp=0, kind=U8 } -> x2 + v188 Store { addr=v184, disp=0, value=v187, kind=I8 } -> - + v189 Imm(0) -> x0 + v190 Imm(1) -> x0 + v191 Imm(0) -> x0 + v192 Imm(1) -> x0 + v193 Imm(1) -> x0 + v194 LocalAddr(-2) -> x0 + v195 Imm(1) -> x2 + v196 BinopI { op=add, lhs=v194, rhs_imm=1 } -> x2 + v197 LoadLocal { off=5, kind=I64 } -> x2 + v198 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x2 + v199 Load { addr=v7, disp=1, kind=U8 } -> x2 + v200 Store { addr=v194, disp=1, value=v199, kind=I8 } -> - + v201 Imm(1) -> x0 + v202 Imm(2) -> x0 + v203 Imm(0) -> x0 + v204 Imm(2) -> x0 + v205 Imm(1) -> x0 + v206 LocalAddr(-2) -> x0 + v207 Imm(2) -> x2 + v208 BinopI { op=add, lhs=v206, rhs_imm=2 } -> x2 + v209 LoadLocal { off=5, kind=I64 } -> x2 + v210 BinopI { op=add, lhs=v7, rhs_imm=2 } -> x2 + v211 Load { addr=v7, disp=2, kind=U8 } -> x2 + v212 Store { addr=v206, disp=2, value=v211, kind=I8 } -> - + v213 Imm(2) -> x0 + v214 Imm(3) -> x0 + v215 Imm(0) -> x0 + v216 Imm(3) -> x0 + v217 Imm(1) -> x0 + v218 LocalAddr(-2) -> x0 + v219 Imm(3) -> x2 + v220 BinopI { op=add, lhs=v218, rhs_imm=3 } -> x2 + v221 LoadLocal { off=5, kind=I64 } -> x2 + v222 BinopI { op=add, lhs=v7, rhs_imm=3 } -> x2 + v223 Load { addr=v7, disp=3, kind=U8 } -> x2 + v224 Store { addr=v218, disp=3, value=v223, kind=I8 } -> - + v225 Imm(3) -> x0 + v226 Imm(4) -> x0 + v227 Imm(0) -> x0 + v228 Imm(4) -> x0 + v229 Imm(1) -> x0 + v230 LocalAddr(-2) -> x0 + v231 Imm(4) -> x2 + v232 BinopI { op=add, lhs=v230, rhs_imm=4 } -> x2 + v233 LoadLocal { off=5, kind=I64 } -> x2 + v234 BinopI { op=add, lhs=v7, rhs_imm=4 } -> x2 + v235 Load { addr=v7, disp=4, kind=U8 } -> x2 + v236 Store { addr=v230, disp=4, value=v235, kind=I8 } -> - + v237 Imm(4) -> x0 + v238 Imm(5) -> x0 + v239 Imm(0) -> x0 + v240 Imm(5) -> x0 + v241 Imm(1) -> x0 + v242 LocalAddr(-2) -> x0 + v243 Imm(5) -> x2 + v244 BinopI { op=add, lhs=v242, rhs_imm=5 } -> x2 + v245 LoadLocal { off=5, kind=I64 } -> x2 + v246 BinopI { op=add, lhs=v7, rhs_imm=5 } -> x2 + v247 Load { addr=v7, disp=5, kind=U8 } -> x2 + v248 Store { addr=v242, disp=5, value=v247, kind=I8 } -> - + v249 Imm(5) -> x0 + v250 Imm(6) -> x0 + v251 Imm(0) -> x0 + v252 Imm(6) -> x0 + v253 Imm(1) -> x0 + v254 LocalAddr(-2) -> x0 + v255 Imm(6) -> x2 + v256 BinopI { op=add, lhs=v254, rhs_imm=6 } -> x2 + v257 LoadLocal { off=5, kind=I64 } -> x2 + v258 BinopI { op=add, lhs=v7, rhs_imm=6 } -> x2 + v259 Load { addr=v7, disp=6, kind=U8 } -> x2 + v260 Store { addr=v254, disp=6, value=v259, kind=I8 } -> - + v261 Imm(6) -> x0 + v262 Imm(7) -> x0 + v263 Imm(0) -> x0 + v264 Imm(7) -> x0 + v265 Imm(1) -> x0 + v266 LocalAddr(-2) -> x0 + v267 Imm(7) -> x2 + v268 BinopI { op=add, lhs=v266, rhs_imm=7 } -> x2 + v269 LoadLocal { off=5, kind=I64 } -> x2 + v270 BinopI { op=add, lhs=v7, rhs_imm=7 } -> x2 + v271 Load { addr=v7, disp=7, kind=U8 } -> x1 + v272 Store { addr=v266, disp=7, value=v271, kind=I8 } -> - + v273 Imm(7) -> x0 + v274 Imm(8) -> x0 + v275 Imm(0) -> x0 + v276 Imm(8) -> x0 + v277 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v277) block 6 start_pc=0 - v27 Imm(0) -> x2 - v28 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v27) + terminator Jmp(b18) block 7 start_pc=0 - v29 Phi { incoming=[b6:v27, b8:v33], kind=I64 } -> x2 - v30 BinopI { op=and, lhs=v29, rhs_imm=4294967295 } -> x0 - v31 BinopI { op=ult, lhs=v30, rhs_imm=8 } -> x0 - terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) + v283 LocalAddr(-10) -> x7 + v284 LocalAddr(-2) -> x6 + v285 LoadLocal { off=6, kind=I64 } -> x0 + v286 ImmData(8) -> x1 + v287 Call { target_pc=1, args=[v283, v284, v9, v286], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v288 Imm(0) -> x1 + v289 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v288) block 8 start_pc=0 - v32 BinopI { op=and, lhs=v29, rhs_imm=4294967295 } -> x0 - v33 BinopI { op=add, lhs=v32, rhs_imm=1 } -> x2 - v34 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v33) + v297 LoadLocal { off=2, kind=I64 } -> x0 + v298 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x0 + v299 Binop { op=add, lhs=v278, rhs=v298 } -> x0 + v300 LoadLocal { off=3, kind=I64 } -> x2 + terminator Bz { cond=v279, target=b11, fall=b9 } (exit_acc=v279) block 9 start_pc=0 - v35 LocalAddr(-2) -> x0 - v36 BinopI { op=and, lhs=v29, rhs_imm=4294967295 } -> x6 - v37 Binop { op=add, lhs=v35, rhs=v36 } -> x0 - v38 LoadLocal { off=5, kind=I64 } -> x7 - v39 Binop { op=add, lhs=v7, rhs=v36 } -> x6 - v40 Load { addr=v39, disp=0, kind=U8 } -> x6 - v41 Store { addr=v37, disp=0, value=v40, kind=I8 } -> - - terminator Jmp(b8) (exit_acc=v41) + v308 LoadLocal { off=3, kind=I64 } -> x2 + v309 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x2 + v310 Binop { op=add, lhs=v279, rhs=v309 } -> x2 + v311 Load { addr=v310, disp=0, kind=U8 } -> x6 + v312 Imm(0) -> x2 + terminator Jmp(b10) (exit_acc=v311) block 10 start_pc=0 - terminator Jmp(b11) + v315 Phi { incoming=[b9:v311, b11:v313], kind=I64 } -> x6 + v316 LoadLocal { off=-16, kind=I64 } -> x2 + v317 LocalAddr(-10) -> x2 + v318 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x7 + v319 Binop { op=add, lhs=v317, rhs=v318 } -> x2 + v320 Load { addr=v319, disp=0, kind=U8 } -> x2 + v321 Binop { op=xor, lhs=v315, rhs=v320 } -> x2 + v322 Store { addr=v299, disp=0, value=v321, kind=I8 } -> - + v323 BinopI { op=and, lhs=v321, rhs_imm=255 } -> x0 + terminator Jmp(b12) (exit_acc=v323) block 11 start_pc=0 - v42 Phi { incoming=[b10:v1, b22:v69], kind=I64 } -> x12 - v43 Phi { incoming=[b10:v3, b22:v91], kind=I64 } -> x13 - v44 Phi { incoming=[b10:v5, b22:v66], kind=I64 } -> x14 - v45 LoadLocal { off=4, kind=I64 } -> x0 - v46 BinopI { op=uge, lhs=v44, rhs_imm=64 } -> x0 - terminator Bz { cond=v46, target=b13, fall=b12 } (exit_acc=v46) + v313 Imm(0) -> x6 + v314 Imm(0) -> x2 + terminator Jmp(b10) (exit_acc=v313) block 12 start_pc=0 - v47 LocalAddr(-10) -> x7 - v48 LocalAddr(-2) -> x6 - v49 LoadLocal { off=6, kind=I64 } -> x0 - v50 ImmData(8) -> x1 - v51 Call { target_pc=1, args=[v47, v48, v9, v50], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v52 Imm(0) -> x1 - v53 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v52) + v294 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x0 + v295 BinopI { op=add, lhs=v294, rhs_imm=1 } -> x1 + v296 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v295) block 13 start_pc=0 - v54 Imm(0) -> x0 - terminator Return(v54) (exit_acc=v54) + v291 Phi { incoming=[b7:v288, b12:v295], kind=I64 } -> x1 + v292 BinopI { op=and, lhs=v291, rhs_imm=4294967295 } -> x0 + v293 BinopI { op=ult, lhs=v292, rhs_imm=64 } -> x0 + terminator Bnz { cond=v293, target=b8, fall=b14 } (exit_acc=v293) block 14 start_pc=0 - v55 Phi { incoming=[b12:v52, b15:v59], kind=I64 } -> x1 - v56 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x0 - v57 BinopI { op=ult, lhs=v56, rhs_imm=64 } -> x0 - terminator Bz { cond=v57, target=b17, fall=b16 } (exit_acc=v57) + v301 LoadLocal { off=4, kind=I64 } -> x0 + v302 BinopI { op=sub, lhs=v280, rhs_imm=64 } -> x14 + v303 Imm(0) -> x0 + v304 LoadLocal { off=2, kind=I64 } -> x0 + v305 BinopI { op=add, lhs=v278, rhs_imm=64 } -> x12 + v306 Imm(0) -> x0 + v307 LoadLocal { off=3, kind=I64 } -> x0 + terminator Bz { cond=v279, target=b16, fall=b15 } (exit_acc=v279) block 15 start_pc=0 - v58 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x0 - v59 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x1 - v60 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v59) + v324 LoadLocal { off=3, kind=I64 } -> x0 + v325 BinopI { op=add, lhs=v279, rhs_imm=64 } -> x13 + v326 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v325) block 16 start_pc=0 - v61 LoadLocal { off=2, kind=I64 } -> x0 - v62 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x0 - v63 Binop { op=add, lhs=v42, rhs=v62 } -> x0 - v64 LoadLocal { off=3, kind=I64 } -> x2 - terminator Bz { cond=v43, target=b19, fall=b18 } (exit_acc=v43) + terminator Jmp(b17) block 17 start_pc=0 - v65 LoadLocal { off=4, kind=I64 } -> x0 - v66 BinopI { op=sub, lhs=v44, rhs_imm=64 } -> x14 - v67 Imm(0) -> x0 - v68 LoadLocal { off=2, kind=I64 } -> x0 - v69 BinopI { op=add, lhs=v42, rhs_imm=64 } -> x12 - v70 Imm(0) -> x0 - v71 LoadLocal { off=3, kind=I64 } -> x0 - terminator Bz { cond=v43, target=b23, fall=b21 } (exit_acc=v43) + v327 Phi { incoming=[b16:v279, b15:v325], kind=I64 } -> x13 + terminator Jmp(b18) block 18 start_pc=0 - v72 LoadLocal { off=3, kind=I64 } -> x2 - v73 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x2 - v74 Binop { op=add, lhs=v43, rhs=v73 } -> x2 - v75 Load { addr=v74, disp=0, kind=U8 } -> x6 - v76 Imm(0) -> x2 - terminator Jmp(b20) (exit_acc=v75) + v278 Phi { incoming=[b6:v1, b17:v305], kind=I64 } -> x12 + v279 Phi { incoming=[b6:v3, b17:v327], kind=I64 } -> x13 + v280 Phi { incoming=[b6:v5, b17:v302], kind=I64 } -> x14 + v281 LoadLocal { off=4, kind=I64 } -> x0 + v282 BinopI { op=uge, lhs=v280, rhs_imm=64 } -> x0 + terminator Bnz { cond=v282, target=b7, fall=b19 } (exit_acc=v282) block 19 start_pc=0 - v77 Imm(0) -> x6 - v78 Imm(0) -> x2 - terminator Jmp(b20) (exit_acc=v77) - block 20 start_pc=0 - v79 Phi { incoming=[b18:v75, b19:v77], kind=I64 } -> x6 - v80 LoadLocal { off=-16, kind=I64 } -> x2 - v81 LocalAddr(-10) -> x2 - v82 BinopI { op=and, lhs=v55, rhs_imm=4294967295 } -> x7 - v83 Binop { op=add, lhs=v81, rhs=v82 } -> x2 - v84 Load { addr=v83, disp=0, kind=U8 } -> x2 - v85 Binop { op=xor, lhs=v79, rhs=v84 } -> x2 - v86 Store { addr=v63, disp=0, value=v85, kind=I8 } -> - - v87 BinopI { op=and, lhs=v85, rhs_imm=255 } -> x0 - terminator Jmp(b15) (exit_acc=v87) - block 21 start_pc=0 - v88 LoadLocal { off=3, kind=I64 } -> x0 - v89 BinopI { op=add, lhs=v43, rhs_imm=64 } -> x13 - v90 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v89) - block 22 start_pc=0 - v91 Phi { incoming=[b23:v43, b21:v89], kind=I64 } -> x13 - terminator Jmp(b11) - block 23 start_pc=0 - terminator Jmp(b22) + v290 Imm(0) -> x0 + terminator Return(v290) (exit_acc=v290) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=20 @@ -421,24 +649,24 @@ fn ent_pc=3 n_params=0 variadic=false locals=20 v3 Mcpy { dst=v1, src=v2, size=8 } -> x0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 - v7 Extend { value=v6, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=32 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v12 LocalAddr(-13) -> x2 + v13 Extend { value=v6, kind=I32 } -> x6 + v14 Binop { op=add, lhs=v12, rhs=v7 } -> x2 + v15 BinopI { op=and, lhs=v7, rhs_imm=255 } -> x6 + v16 Store { addr=v14, disp=0, value=v15, kind=I8 } -> - + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v9 Extend { value=v6, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v9 Extend { value=v6, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + terminator Jmp(b3) (exit_acc=v10) block 3 start_pc=0 - v12 LocalAddr(-13) -> x0 - v13 Extend { value=v6, kind=I32 } -> x2 - v14 Binop { op=add, lhs=v12, rhs=v13 } -> x0 - v15 BinopI { op=and, lhs=v13, rhs_imm=255 } -> x2 - v16 Store { addr=v14, disp=0, value=v15, kind=I8 } -> - - terminator Jmp(b2) (exit_acc=v16) + v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 + v7 Extend { value=v6, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=32 } -> x2 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) block 4 start_pc=0 v17 LocalAddr(-8) -> x7 v18 Imm(0) -> x6 @@ -451,19 +679,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=20 v25 BinopI { op=xor, lhs=v24, rhs_imm=77 } -> x0 v26 BinopI { op=and, lhs=v25, rhs_imm=4294967295 } -> x0 v27 BinopI { op=eq, lhs=v26, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + terminator Bz { cond=v27, target=b7, fall=b5 } (exit_acc=v27) block 5 start_pc=0 v28 Imm(0) -> x1 v29 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v28) + terminator Jmp(b6) (exit_acc=v28) block 6 start_pc=0 - v30 Imm(1) -> x1 - v31 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v30) - block 7 start_pc=0 - v32 Phi { incoming=[b5:v28, b6:v30], kind=I64 } -> x1 + v32 Phi { incoming=[b5:v28, b7:v30], kind=I64 } -> x1 v33 LoadLocal { off=-20, kind=I64 } -> x0 terminator Return(v32) (exit_acc=v32) + block 7 start_pc=0 + v30 Imm(1) -> x1 + v31 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v30) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ssa_call_result_spill.ssa b/tests/snapshots/ssa/ssa_call_result_spill.ssa index 91113e71b..48a4ce851 100644 --- a/tests/snapshots/ssa/ssa_call_result_spill.ssa +++ b/tests/snapshots/ssa/ssa_call_result_spill.ssa @@ -48,41 +48,41 @@ fn ent_pc=2 n_params=1 variadic=false locals=2 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 Imm(14) -> x0 - v5 Imm(0) -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 Imm(0) -> x1 - v8 Binop { op=shru, lhs=v1, rhs=v6 } -> x1 - v9 Imm(64) -> x1 - v10 Binop { op=sub, lhs=v9, rhs=v6 } -> x1 - v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x2 - v12 Extend { value=v10, kind=I32 } -> x1 - v13 Binop { op=shl, lhs=v1, rhs=v12 } -> x1 - v14 Binop { op=ror, lhs=v1, rhs=v6 } -> x0 + v5 Imm(0) -> x0 + v6 Imm(14) -> x0 + v7 Imm(0) -> x0 + v8 BinopI { op=shru, lhs=v1, rhs_imm=14 } -> x0 + v9 Imm(64) -> x0 + v10 Imm(50) -> x0 + v11 Imm(214748364800) -> x0 + v12 Imm(50) -> x0 + v13 BinopI { op=shl, lhs=v1, rhs_imm=50 } -> x0 + v14 BinopI { op=ror, lhs=v1, rhs_imm=14 } -> x0 v15 LoadLocal { off=2, kind=I64 } -> x1 v16 Imm(18) -> x1 - v17 Imm(0) -> x2 - v18 Extend { value=v16, kind=I32 } -> x1 - v19 Imm(0) -> x2 - v20 Binop { op=shru, lhs=v1, rhs=v18 } -> x2 - v21 Imm(64) -> x2 - v22 Binop { op=sub, lhs=v21, rhs=v18 } -> x2 - v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x6 - v24 Extend { value=v22, kind=I32 } -> x2 - v25 Binop { op=shl, lhs=v1, rhs=v24 } -> x2 - v26 Binop { op=ror, lhs=v1, rhs=v18 } -> x1 + v17 Imm(0) -> x1 + v18 Imm(18) -> x1 + v19 Imm(0) -> x1 + v20 BinopI { op=shru, lhs=v1, rhs_imm=18 } -> x1 + v21 Imm(64) -> x1 + v22 Imm(46) -> x1 + v23 Imm(197568495616) -> x1 + v24 Imm(46) -> x1 + v25 BinopI { op=shl, lhs=v1, rhs_imm=46 } -> x1 + v26 BinopI { op=ror, lhs=v1, rhs_imm=18 } -> x1 v27 Binop { op=xor, lhs=v14, rhs=v26 } -> x0 v28 LoadLocal { off=2, kind=I64 } -> x1 v29 Imm(41) -> x1 - v30 Imm(0) -> x2 - v31 Extend { value=v29, kind=I32 } -> x1 - v32 Imm(0) -> x2 - v33 Binop { op=shru, lhs=v1, rhs=v31 } -> x2 - v34 Imm(64) -> x2 - v35 Binop { op=sub, lhs=v34, rhs=v31 } -> x2 - v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x6 - v37 Extend { value=v35, kind=I32 } -> x2 - v38 Binop { op=shl, lhs=v1, rhs=v37 } -> x2 - v39 Binop { op=ror, lhs=v1, rhs=v31 } -> x1 + v30 Imm(0) -> x1 + v31 Imm(41) -> x1 + v32 Imm(0) -> x1 + v33 BinopI { op=shru, lhs=v1, rhs_imm=41 } -> x1 + v34 Imm(64) -> x1 + v35 Imm(23) -> x1 + v36 Imm(98784247808) -> x1 + v37 Imm(23) -> x1 + v38 BinopI { op=shl, lhs=v1, rhs_imm=23 } -> x1 + v39 BinopI { op=ror, lhs=v1, rhs_imm=41 } -> x1 v40 Binop { op=xor, lhs=v27, rhs=v39 } -> x0 terminator Return(v40) (exit_acc=v40) ; --- SSA dump (ok=true) ent_pc=3 --- @@ -109,135 +109,135 @@ fn ent_pc=3 n_params=0 variadic=false locals=13 v16 Imm(0) -> x0 v17 Imm(0) -> x1 v18 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v17) + terminator Jmp(b3) (exit_acc=v17) block 1 start_pc=0 - v19 Phi { incoming=[b0:v17, b2:v31], kind=I64 } -> x1 - v20 Phi { incoming=[b0:v15, b2:v21], kind=I64 } -> x2 - v21 Phi { incoming=[b0:v13, b2:v22], kind=I64 } -> x6 - v22 Phi { incoming=[b0:v11, b2:v23], kind=I64 } -> x7 - v23 Phi { incoming=[b0:v9, b2:v130], kind=I64 } -> x8 - v24 Phi { incoming=[b0:v7, b2:v25], kind=I64 } -> x9 - v25 Phi { incoming=[b0:v5, b2:v26], kind=I64 } -> x3 - v26 Phi { incoming=[b0:v3, b2:v27], kind=I64 } -> x12 - v27 Phi { incoming=[b0:v1, b2:v139], kind=I64 } -> x13 - v28 Extend { value=v19, kind=I32 } -> x0 - v29 BinopI { op=lt, lhs=v28, rhs_imm=4 } -> x0 - terminator Bz { cond=v29, target=b4, fall=b3 } (exit_acc=v29) - block 2 start_pc=0 - v30 Extend { value=v19, kind=I32 } -> x0 - v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x1 - v32 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v31) - block 3 start_pc=0 - v33 LoadLocal { off=-5, kind=I64 } -> x0 - v34 Imm(0) -> x0 - v35 Imm(14) -> x0 + v33 LoadLocal { off=-5, kind=I64 } -> x14 + v34 Imm(0) -> x14 + v35 Imm(14) -> x14 v36 Imm(0) -> x14 - v37 Extend { value=v35, kind=I32 } -> x0 + v37 Imm(14) -> x14 v38 Imm(0) -> x14 - v39 Binop { op=shru, lhs=v23, rhs=v37 } -> x14 + v39 BinopI { op=shru, lhs=v23, rhs_imm=14 } -> x14 v40 Imm(64) -> x14 - v41 Binop { op=sub, lhs=v40, rhs=v37 } -> x14 - v42 BinopI { op=shl, lhs=v41, rhs_imm=32 } -> x15 - v43 Extend { value=v41, kind=I32 } -> x14 - v44 Binop { op=shl, lhs=v23, rhs=v43 } -> x14 - v45 Binop { op=ror, lhs=v23, rhs=v37 } -> x0 - v46 Imm(18) -> x14 + v41 Imm(50) -> x14 + v42 Imm(214748364800) -> x14 + v43 Imm(50) -> x14 + v44 BinopI { op=shl, lhs=v23, rhs_imm=50 } -> x14 + v45 BinopI { op=ror, lhs=v23, rhs_imm=14 } -> x14 + v46 Imm(18) -> x15 v47 Imm(0) -> x15 - v48 Extend { value=v46, kind=I32 } -> x14 + v48 Imm(18) -> x15 v49 Imm(0) -> x15 - v50 Binop { op=shru, lhs=v23, rhs=v48 } -> x15 + v50 BinopI { op=shru, lhs=v23, rhs_imm=18 } -> x15 v51 Imm(64) -> x15 - v52 Binop { op=sub, lhs=v51, rhs=v48 } -> x15 - v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> [spill 0] - v54 Extend { value=v52, kind=I32 } -> x15 - v55 Binop { op=shl, lhs=v23, rhs=v54 } -> x15 - v56 Binop { op=ror, lhs=v23, rhs=v48 } -> x14 - v57 Binop { op=xor, lhs=v45, rhs=v56 } -> x0 - v58 Imm(41) -> x14 + v52 Imm(46) -> x15 + v53 Imm(197568495616) -> x15 + v54 Imm(46) -> x15 + v55 BinopI { op=shl, lhs=v23, rhs_imm=46 } -> x15 + v56 BinopI { op=ror, lhs=v23, rhs_imm=18 } -> x15 + v57 Binop { op=xor, lhs=v45, rhs=v56 } -> x14 + v58 Imm(41) -> x15 v59 Imm(0) -> x15 - v60 Extend { value=v58, kind=I32 } -> x14 + v60 Imm(41) -> x15 v61 Imm(0) -> x15 - v62 Binop { op=shru, lhs=v23, rhs=v60 } -> x15 + v62 BinopI { op=shru, lhs=v23, rhs_imm=41 } -> x15 v63 Imm(64) -> x15 - v64 Binop { op=sub, lhs=v63, rhs=v60 } -> x15 - v65 BinopI { op=shl, lhs=v64, rhs_imm=32 } -> [spill 0] - v66 Extend { value=v64, kind=I32 } -> x15 - v67 Binop { op=shl, lhs=v23, rhs=v66 } -> x15 - v68 Binop { op=ror, lhs=v23, rhs=v60 } -> x14 - v69 Binop { op=xor, lhs=v57, rhs=v68 } -> x0 - v70 LoadLocal { off=-5, kind=I64 } -> x14 - v71 LoadLocal { off=-6, kind=I64 } -> x14 - v72 LoadLocal { off=-7, kind=I64 } -> x14 - v73 Imm(0) -> x14 - v74 Imm(0) -> x14 - v75 Imm(0) -> x14 - v76 Binop { op=and, lhs=v23, rhs=v22 } -> x14 - v77 BinopI { op=xor, lhs=v23, rhs_imm=-1 } -> x15 - v78 Binop { op=and, lhs=v77, rhs=v21 } -> x15 - v79 Binop { op=xor, lhs=v76, rhs=v78 } -> x14 - v80 Binop { op=add, lhs=v69, rhs=v79 } -> x0 - v81 LoadLocal { off=-8, kind=I64 } -> x14 - v82 Binop { op=add, lhs=v80, rhs=v20 } -> x0 - v83 Imm(0) -> x2 - v84 LoadLocal { off=-1, kind=I64 } -> x2 - v85 Imm(0) -> x2 - v86 Imm(14) -> x2 + v64 Imm(23) -> x15 + v65 Imm(98784247808) -> x15 + v66 Imm(23) -> x15 + v67 BinopI { op=shl, lhs=v23, rhs_imm=23 } -> x15 + v68 BinopI { op=ror, lhs=v23, rhs_imm=41 } -> x15 + v69 Binop { op=xor, lhs=v57, rhs=v68 } -> x14 + v70 LoadLocal { off=-5, kind=I64 } -> x15 + v71 LoadLocal { off=-6, kind=I64 } -> x15 + v72 LoadLocal { off=-7, kind=I64 } -> x15 + v73 Imm(0) -> x15 + v74 Imm(0) -> x15 + v75 Imm(0) -> x15 + v76 Binop { op=and, lhs=v23, rhs=v22 } -> x15 + v77 BinopI { op=xor, lhs=v23, rhs_imm=-1 } -> [spill 0] + v78 Binop { op=and, lhs=v77, rhs=v21 } -> [spill 0] + v79 Binop { op=xor, lhs=v76, rhs=v78 } -> x15 + v80 Binop { op=add, lhs=v69, rhs=v79 } -> x14 + v81 LoadLocal { off=-8, kind=I64 } -> x15 + v82 Binop { op=add, lhs=v80, rhs=v20 } -> x2 + v83 Imm(0) -> x14 + v84 LoadLocal { off=-1, kind=I64 } -> x14 + v85 Imm(0) -> x14 + v86 Imm(14) -> x14 v87 Imm(0) -> x14 - v88 Extend { value=v86, kind=I32 } -> x2 + v88 Imm(14) -> x14 v89 Imm(0) -> x14 - v90 Binop { op=shru, lhs=v27, rhs=v88 } -> x14 + v90 BinopI { op=shru, lhs=v27, rhs_imm=14 } -> x14 v91 Imm(64) -> x14 - v92 Binop { op=sub, lhs=v91, rhs=v88 } -> x14 - v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x15 - v94 Extend { value=v92, kind=I32 } -> x14 - v95 Binop { op=shl, lhs=v27, rhs=v94 } -> x14 - v96 Binop { op=ror, lhs=v27, rhs=v88 } -> x2 - v97 Imm(18) -> x14 + v92 Imm(50) -> x14 + v93 Imm(214748364800) -> x14 + v94 Imm(50) -> x14 + v95 BinopI { op=shl, lhs=v27, rhs_imm=50 } -> x14 + v96 BinopI { op=ror, lhs=v27, rhs_imm=14 } -> x14 + v97 Imm(18) -> x15 v98 Imm(0) -> x15 - v99 Extend { value=v97, kind=I32 } -> x14 + v99 Imm(18) -> x15 v100 Imm(0) -> x15 - v101 Binop { op=shru, lhs=v27, rhs=v99 } -> x15 + v101 BinopI { op=shru, lhs=v27, rhs_imm=18 } -> x15 v102 Imm(64) -> x15 - v103 Binop { op=sub, lhs=v102, rhs=v99 } -> x15 - v104 BinopI { op=shl, lhs=v103, rhs_imm=32 } -> [spill 0] - v105 Extend { value=v103, kind=I32 } -> x15 - v106 Binop { op=shl, lhs=v27, rhs=v105 } -> x15 - v107 Binop { op=ror, lhs=v27, rhs=v99 } -> x14 - v108 Binop { op=xor, lhs=v96, rhs=v107 } -> x2 - v109 Imm(41) -> x14 + v103 Imm(46) -> x15 + v104 Imm(197568495616) -> x15 + v105 Imm(46) -> x15 + v106 BinopI { op=shl, lhs=v27, rhs_imm=46 } -> x15 + v107 BinopI { op=ror, lhs=v27, rhs_imm=18 } -> x15 + v108 Binop { op=xor, lhs=v96, rhs=v107 } -> x14 + v109 Imm(41) -> x15 v110 Imm(0) -> x15 - v111 Extend { value=v109, kind=I32 } -> x14 + v111 Imm(41) -> x15 v112 Imm(0) -> x15 - v113 Binop { op=shru, lhs=v27, rhs=v111 } -> x15 + v113 BinopI { op=shru, lhs=v27, rhs_imm=41 } -> x15 v114 Imm(64) -> x15 - v115 Binop { op=sub, lhs=v114, rhs=v111 } -> x15 - v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> [spill 0] - v117 Extend { value=v115, kind=I32 } -> x15 - v118 Binop { op=shl, lhs=v27, rhs=v117 } -> x15 - v119 Binop { op=ror, lhs=v27, rhs=v111 } -> x14 - v120 Binop { op=xor, lhs=v108, rhs=v119 } -> x2 - v121 Imm(0) -> x14 - v122 LoadLocal { off=-7, kind=I64 } -> x14 - v123 Imm(0) -> x14 - v124 LoadLocal { off=-6, kind=I64 } -> x14 - v125 Imm(0) -> x14 - v126 LoadLocal { off=-5, kind=I64 } -> x14 - v127 Imm(0) -> x14 - v128 LoadLocal { off=-4, kind=I64 } -> x14 - v129 LoadLocal { off=-10, kind=I64 } -> x14 + v115 Imm(23) -> x15 + v116 Imm(98784247808) -> x15 + v117 Imm(23) -> x15 + v118 BinopI { op=shl, lhs=v27, rhs_imm=23 } -> x15 + v119 BinopI { op=ror, lhs=v27, rhs_imm=41 } -> x15 + v120 Binop { op=xor, lhs=v108, rhs=v119 } -> x14 + v121 Imm(0) -> x15 + v122 LoadLocal { off=-7, kind=I64 } -> x15 + v123 Imm(0) -> x15 + v124 LoadLocal { off=-6, kind=I64 } -> x15 + v125 Imm(0) -> x15 + v126 LoadLocal { off=-5, kind=I64 } -> x15 + v127 Imm(0) -> x15 + v128 LoadLocal { off=-4, kind=I64 } -> x15 + v129 LoadLocal { off=-10, kind=I64 } -> x15 v130 Binop { op=add, lhs=v24, rhs=v82 } -> x9 - v131 Imm(0) -> x14 - v132 LoadLocal { off=-3, kind=I64 } -> x14 - v133 Imm(0) -> x14 - v134 LoadLocal { off=-2, kind=I64 } -> x14 - v135 Imm(0) -> x14 - v136 LoadLocal { off=-1, kind=I64 } -> x14 - v137 Imm(0) -> x14 - v138 LoadLocal { off=-11, kind=I64 } -> x14 + v131 Imm(0) -> x15 + v132 LoadLocal { off=-3, kind=I64 } -> x15 + v133 Imm(0) -> x15 + v134 LoadLocal { off=-2, kind=I64 } -> x15 + v135 Imm(0) -> x15 + v136 LoadLocal { off=-1, kind=I64 } -> x15 + v137 Imm(0) -> x15 + v138 LoadLocal { off=-11, kind=I64 } -> x15 v139 Binop { op=add, lhs=v82, rhs=v120 } -> x2 - v140 Imm(0) -> x0 + v140 Imm(0) -> x14 terminator Jmp(b2) (exit_acc=v139) + block 2 start_pc=0 + v30 Extend { value=v19, kind=I32 } -> x1 + v31 BinopI { op=add, lhs=v28, rhs_imm=1 } -> x1 + v32 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v31) + block 3 start_pc=0 + v19 Phi { incoming=[b0:v17, b2:v31], kind=I64 } -> x1 + v20 Phi { incoming=[b0:v15, b2:v21], kind=I64 } -> x2 + v21 Phi { incoming=[b0:v13, b2:v22], kind=I64 } -> x6 + v22 Phi { incoming=[b0:v11, b2:v23], kind=I64 } -> x7 + v23 Phi { incoming=[b0:v9, b2:v130], kind=I64 } -> x8 + v24 Phi { incoming=[b0:v7, b2:v25], kind=I64 } -> x9 + v25 Phi { incoming=[b0:v5, b2:v26], kind=I64 } -> x3 + v26 Phi { incoming=[b0:v3, b2:v27], kind=I64 } -> x12 + v27 Phi { incoming=[b0:v1, b2:v139], kind=I64 } -> x13 + v28 Extend { value=v19, kind=I32 } -> x0 + v29 BinopI { op=lt, lhs=v28, rhs_imm=4 } -> x14 + terminator Bnz { cond=v29, target=b1, fall=b4 } (exit_acc=v29) block 4 start_pc=0 v141 LoadLocal { off=-1, kind=I64 } -> x0 v142 BinopI { op=ne, lhs=v27, rhs_imm=3505310727405681433 } -> x0 diff --git a/tests/snapshots/ssa/ssa_fp_compare_nan.ssa b/tests/snapshots/ssa/ssa_fp_compare_nan.ssa index 3428a4de5..7a0c99d1d 100644 --- a/tests/snapshots/ssa/ssa_fp_compare_nan.ssa +++ b/tests/snapshots/ssa/ssa_fp_compare_nan.ssa @@ -12,107 +12,107 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=4 - spill_count=1 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Call { target_pc=1, args=[], fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> [spill 0] + v1 Call { target_pc=1, args=[], fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 v2 Imm(0) -> x0 - v3 Imm(0) -> x3 + v3 Imm(0) -> x1 v4 Imm(0) -> x0 - v5 LoadLocal { off=-1, kind=F64 } -> d0 + v5 LoadLocal { off=-1, kind=F64 } -> d1 v6 Binop { op=flt, lhs=v1, rhs=v3 } -> x0 - terminator Bz { cond=v6, target=b19, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b26, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v7 LoadLocal { off=-2, kind=I32 } -> x0 - v8 BinopI { op=or, lhs=v3, rhs_imm=1 } -> x3 + v8 Imm(1) -> x1 v9 Imm(0) -> x0 - v10 Extend { value=v8, kind=I32 } -> x0 + v10 Imm(1) -> x0 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v11 Phi { incoming=[b19:v3, b1:v8], kind=I64 } -> x3 - v12 LoadLocal { off=-1, kind=F64 } -> d0 + v11 Phi { incoming=[b26:v3, b1:v8], kind=I64 } -> x1 + v12 LoadLocal { off=-1, kind=F64 } -> d1 v13 Imm(0) -> x0 v14 Binop { op=fgt, lhs=v1, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b20, fall=b3 } (exit_acc=v14) + terminator Bz { cond=v14, target=b25, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v15 Extend { value=v11, kind=I32 } -> x0 - v16 BinopI { op=or, lhs=v11, rhs_imm=2 } -> x3 + v16 BinopI { op=or, lhs=v11, rhs_imm=2 } -> x1 v17 Imm(0) -> x0 v18 Extend { value=v16, kind=I32 } -> x0 terminator Jmp(b4) (exit_acc=v18) block 4 start_pc=0 - v19 Phi { incoming=[b20:v11, b3:v16], kind=I64 } -> x3 - v20 LoadLocal { off=-1, kind=F64 } -> d0 + v19 Phi { incoming=[b25:v11, b3:v16], kind=I64 } -> x1 + v20 LoadLocal { off=-1, kind=F64 } -> d1 v21 Imm(0) -> x0 v22 Binop { op=fle, lhs=v1, rhs=v21 } -> x0 - terminator Bz { cond=v22, target=b21, fall=b5 } (exit_acc=v22) + terminator Bz { cond=v22, target=b24, fall=b5 } (exit_acc=v22) block 5 start_pc=0 v23 Extend { value=v19, kind=I32 } -> x0 - v24 BinopI { op=or, lhs=v19, rhs_imm=4 } -> x3 + v24 BinopI { op=or, lhs=v19, rhs_imm=4 } -> x1 v25 Imm(0) -> x0 v26 Extend { value=v24, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v27 Phi { incoming=[b21:v19, b5:v24], kind=I64 } -> x3 - v28 LoadLocal { off=-1, kind=F64 } -> d0 + v27 Phi { incoming=[b24:v19, b5:v24], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=F64 } -> d1 v29 Imm(0) -> x0 v30 Binop { op=fge, lhs=v1, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b22, fall=b7 } (exit_acc=v30) + terminator Bz { cond=v30, target=b23, fall=b7 } (exit_acc=v30) block 7 start_pc=0 v31 Extend { value=v27, kind=I32 } -> x0 - v32 BinopI { op=or, lhs=v27, rhs_imm=8 } -> x3 + v32 BinopI { op=or, lhs=v27, rhs_imm=8 } -> x1 v33 Imm(0) -> x0 v34 Extend { value=v32, kind=I32 } -> x0 terminator Jmp(b8) (exit_acc=v34) block 8 start_pc=0 - v35 Phi { incoming=[b22:v27, b7:v32], kind=I64 } -> x3 - v36 LoadLocal { off=-1, kind=F64 } -> d0 + v35 Phi { incoming=[b23:v27, b7:v32], kind=I64 } -> x1 + v36 LoadLocal { off=-1, kind=F64 } -> d1 v37 Imm(0) -> x0 v38 Binop { op=feq, lhs=v1, rhs=v37 } -> x0 - terminator Bz { cond=v38, target=b23, fall=b9 } (exit_acc=v38) + terminator Bz { cond=v38, target=b22, fall=b9 } (exit_acc=v38) block 9 start_pc=0 v39 Extend { value=v35, kind=I32 } -> x0 - v40 BinopI { op=or, lhs=v35, rhs_imm=16 } -> x3 + v40 BinopI { op=or, lhs=v35, rhs_imm=16 } -> x1 v41 Imm(0) -> x0 v42 Extend { value=v40, kind=I32 } -> x0 terminator Jmp(b10) (exit_acc=v42) block 10 start_pc=0 - v43 Phi { incoming=[b23:v35, b9:v40], kind=I64 } -> x3 - v44 LoadLocal { off=-1, kind=F64 } -> d0 + v43 Phi { incoming=[b22:v35, b9:v40], kind=I64 } -> x1 + v44 LoadLocal { off=-1, kind=F64 } -> d1 v45 Imm(0) -> x0 v46 Binop { op=fne, lhs=v1, rhs=v45 } -> x0 v47 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x0 - terminator Bz { cond=v47, target=b24, fall=b11 } (exit_acc=v47) + terminator Bz { cond=v47, target=b21, fall=b11 } (exit_acc=v47) block 11 start_pc=0 v48 Extend { value=v43, kind=I32 } -> x0 - v49 BinopI { op=or, lhs=v43, rhs_imm=32 } -> x3 + v49 BinopI { op=or, lhs=v43, rhs_imm=32 } -> x1 v50 Imm(0) -> x0 v51 Extend { value=v49, kind=I32 } -> x0 terminator Jmp(b12) (exit_acc=v51) block 12 start_pc=0 - v52 Phi { incoming=[b24:v43, b11:v49], kind=I64 } -> x3 - v53 LoadLocal { off=-1, kind=F64 } -> d0 + v52 Phi { incoming=[b21:v43, b11:v49], kind=I64 } -> x1 + v53 LoadLocal { off=-1, kind=F64 } -> d1 v54 Binop { op=flt, lhs=v1, rhs=v1 } -> x0 - terminator Bz { cond=v54, target=b25, fall=b13 } (exit_acc=v54) + terminator Bz { cond=v54, target=b20, fall=b13 } (exit_acc=v54) block 13 start_pc=0 v55 Extend { value=v52, kind=I32 } -> x0 - v56 BinopI { op=or, lhs=v52, rhs_imm=64 } -> x3 + v56 BinopI { op=or, lhs=v52, rhs_imm=64 } -> x1 v57 Imm(0) -> x0 v58 Extend { value=v56, kind=I32 } -> x0 terminator Jmp(b14) (exit_acc=v58) block 14 start_pc=0 - v59 Phi { incoming=[b25:v52, b13:v56], kind=I64 } -> x3 - v60 LoadLocal { off=-1, kind=F64 } -> d0 + v59 Phi { incoming=[b20:v52, b13:v56], kind=I64 } -> x1 + v60 LoadLocal { off=-1, kind=F64 } -> d1 v61 Binop { op=feq, lhs=v1, rhs=v1 } -> x0 - terminator Bz { cond=v61, target=b26, fall=b15 } (exit_acc=v61) + terminator Bz { cond=v61, target=b19, fall=b15 } (exit_acc=v61) block 15 start_pc=0 v62 Extend { value=v59, kind=I32 } -> x0 - v63 BinopI { op=or, lhs=v59, rhs_imm=128 } -> x3 + v63 BinopI { op=or, lhs=v59, rhs_imm=128 } -> x1 v64 Imm(0) -> x0 v65 Extend { value=v63, kind=I32 } -> x0 terminator Jmp(b16) (exit_acc=v65) block 16 start_pc=0 - v66 Phi { incoming=[b26:v59, b15:v63], kind=I64 } -> x3 + v66 Phi { incoming=[b19:v59, b15:v63], kind=I64 } -> x1 v67 Extend { value=v66, kind=I32 } -> x0 terminator Bz { cond=v67, target=b18, fall=b17 } (exit_acc=v67) block 17 start_pc=0 @@ -127,21 +127,21 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 v74 Imm(0) -> x0 terminator Return(v74) (exit_acc=v74) block 19 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b16) block 20 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b14) block 21 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b12) block 22 start_pc=0 - terminator Jmp(b8) - block 23 start_pc=0 terminator Jmp(b10) + block 23 start_pc=0 + terminator Jmp(b8) block 24 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b6) block 25 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b4) block 26 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ssa_fp_routing.ssa b/tests/snapshots/ssa/ssa_fp_routing.ssa index 22cb42bff..bd90f9043 100644 --- a/tests/snapshots/ssa/ssa_fp_routing.ssa +++ b/tests/snapshots/ssa/ssa_fp_routing.ssa @@ -404,7 +404,7 @@ fn ent_pc=15 n_params=0 variadic=false locals=2 terminator Return(v132) (exit_acc=v132) block 40 start_pc=0 v133 Imm(42) -> x0 - v134 Extend { value=v133, kind=I32 } -> x0 + v134 Imm(42) -> x0 v135 Imm(0) -> x1 v136 FpCast { kind=IntToFp, value=v134 } -> d0 v137 Imm(4631107791820423168) -> x0 @@ -415,7 +415,7 @@ fn ent_pc=15 n_params=0 variadic=false locals=2 terminator Return(v139) (exit_acc=v139) block 42 start_pc=0 v140 Imm(-3) -> x0 - v141 Extend { value=v140, kind=I32 } -> x0 + v141 Imm(-3) -> x0 v142 Imm(0) -> x1 v143 FpCast { kind=IntToFp, value=v141 } -> d0 v144 Imm(4613937818241073152) -> x0 diff --git a/tests/snapshots/ssa/ssa_va_arg_loop.ssa b/tests/snapshots/ssa/ssa_va_arg_loop.ssa index 0102a5164..74c38ca87 100644 --- a/tests/snapshots/ssa/ssa_va_arg_loop.ssa +++ b/tests/snapshots/ssa/ssa_va_arg_loop.ssa @@ -10,28 +10,28 @@ fn ent_pc=0 n_params=1 variadic=true locals=5 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 LoadLocal { off=-4, kind=I64 } -> x6 + v16 LocalAddr(-3) -> x6 + v17 Imm(8) -> x7 + v18 Intrinsic { kind=5, args=[v16, v17] } -> x6 + v19 Load { addr=v18, disp=0, kind=I64 } -> x6 + v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 + v21 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 LoadLocal { off=-4, kind=I64 } -> x2 - v16 LocalAddr(-3) -> x2 - v17 Imm(8) -> x6 - v18 Intrinsic { kind=5, args=[v16, v17] } -> x2 - v19 Load { addr=v18, disp=0, kind=I64 } -> x2 - v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 - v21 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v20) + v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 LoadLocal { off=2, kind=I32 } -> x6 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v22 LocalAddr(-3) -> x1 v23 Intrinsic { kind=6, args=[v22] } -> x1 diff --git a/tests/snapshots/ssa/static_assert_and_warning.ssa b/tests/snapshots/ssa/static_assert_and_warning.ssa index e6c59adda..dfb0ea41a 100644 --- a/tests/snapshots/ssa/static_assert_and_warning.ssa +++ b/tests/snapshots/ssa/static_assert_and_warning.ssa @@ -11,7 +11,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 v4 LoadLocal { off=-1, kind=I32 } -> x0 - v5 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x1 + v5 Imm(1) -> x1 v6 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v5) block 2 start_pc=0 diff --git a/tests/snapshots/ssa/static_assert_in_struct.ssa b/tests/snapshots/ssa/static_assert_in_struct.ssa index f68e71659..bd109a515 100644 --- a/tests/snapshots/ssa/static_assert_in_struct.ssa +++ b/tests/snapshots/ssa/static_assert_in_struct.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=7 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 @@ -11,41 +11,35 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v5 BinopI { op=add, lhs=v4, rhs_imm=4 } -> x1 v6 Imm(2) -> x1 v7 Store { addr=v4, disp=4, value=v6, kind=I32 } -> - - v8 Imm(4) -> x3 + v8 Imm(4) -> x0 v9 Imm(0) -> x0 v10 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v10) + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 LocalAddr(-1) -> x0 v13 Load { addr=v12, disp=0, kind=I32 } -> x0 - v14 BinopI { op=ne, lhs=v13, rhs_imm=1 } -> x12 + v14 BinopI { op=ne, lhs=v13, rhs_imm=1 } -> x1 v15 Imm(0) -> x0 - terminator Bnz { cond=v14, target=b9, fall=b3 } (exit_acc=v14) - block 3 start_pc=0 + terminator Bnz { cond=v14, target=b7, fall=b2 } (exit_acc=v14) + block 2 start_pc=0 v16 LocalAddr(-1) -> x0 v17 BinopI { op=add, lhs=v16, rhs_imm=4 } -> x1 v18 Load { addr=v16, disp=4, kind=I32 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=2 } -> x12 + v19 BinopI { op=ne, lhs=v18, rhs_imm=2 } -> x1 v20 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v19) - block 4 start_pc=0 - v21 Phi { incoming=[b9:v14, b3:v19], kind=I64 } -> x12 + terminator Jmp(b3) (exit_acc=v19) + block 3 start_pc=0 + v21 Phi { incoming=[b7:v14, b2:v19], kind=I64 } -> x1 v22 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) - block 5 start_pc=0 + terminator Bz { cond=v21, target=b5, fall=b4 } (exit_acc=v21) + block 4 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 + block 5 start_pc=0 v24 LoadLocal { off=-2, kind=I32 } -> x0 - v25 BinopI { op=le, lhs=v8, rhs_imm=0 } -> x0 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) - block 7 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) - block 8 start_pc=0 + v25 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v25) + block 6 start_pc=0 v27 ImmData(37) -> x7 v28 LocalAddr(-1) -> x0 v29 Load { addr=v28, disp=0, kind=I32 } -> x6 @@ -56,8 +50,14 @@ fn ent_pc=1 n_params=0 variadic=false locals=7 v34 CallExt { binding_idx=0, args=[v27, v29, v32, v33], fp_arg_mask=0x0 } -> x0 v35 Imm(0) -> x0 terminator Return(v35) (exit_acc=v35) + block 7 start_pc=0 + terminator Jmp(b3) + block 8 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 9 start_pc=0 - terminator Jmp(b4) + v26 Imm(3) -> x0 + terminator Return(v26) (exit_acc=v26) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/static_init_once_guard.ssa b/tests/snapshots/ssa/static_init_once_guard.ssa new file mode 100644 index 000000000..19bd3000f --- /dev/null +++ b/tests/snapshots/ssa/static_init_once_guard.ssa @@ -0,0 +1,239 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=step +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 ImmData(32) -> x0 + v4 Imm(16) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v6 Load { addr=v3, disp=16, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(0) -> x1 + v8 StoreLocal { off=-1, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) + block 2 start_pc=0 + v9 ImmData(32) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 Imm(1) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I8 } -> - + v21 Imm(72057594037927936) -> x2 + v22 StoreLocal { off=-1, value=v19, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v22) + block 3 start_pc=0 + v23 LoadLocal { off=-1, kind=I64 } -> x1 + v24 LoadLocal { off=2, kind=I32 } -> x1 + v25 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x1 + terminator Bz { cond=v25, target=b7, fall=b6 } (exit_acc=v25) + block 4 start_pc=0 + v50 Imm(10) -> x0 + terminator Return(v50) (exit_acc=v50) + block 5 start_pc=0 + v51 Imm(20) -> x0 + terminator Return(v51) (exit_acc=v51) + block 6 start_pc=0 + v26 ImmData(24) -> x1 + v27 ImmData(32) -> x2 + v28 Imm(0) -> x2 + v29 Load { addr=v3, disp=0, kind=I64 } -> x2 + v30 Store { addr=v26, disp=0, value=v29, kind=I64 } -> - + v31 Imm(8) -> x1 + v32 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v33 Load { addr=v3, disp=8, kind=I64 } -> x1 + v34 Store { addr=v3, disp=0, value=v33, kind=I64 } -> - + v35 Load { addr=v3, disp=8, kind=I64 } -> x0 + terminator GotoIndirect(v33) (exit_acc=v33) + block 7 start_pc=0 + v36 ImmData(32) -> x1 + v37 Imm(0) -> x1 + v38 Load { addr=v3, disp=0, kind=I64 } -> x1 + v39 Imm(8) -> x2 + v40 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 + v41 Load { addr=v3, disp=8, kind=I64 } -> x2 + v42 Binop { op=ne, lhs=v38, rhs=v41 } -> x1 + terminator Bz { cond=v42, target=b9, fall=b8 } (exit_acc=v42) + block 8 start_pc=0 + v43 Imm(1) -> x0 + terminator Return(v43) (exit_acc=v43) + block 9 start_pc=0 + v44 ImmData(32) -> x1 + v45 Imm(0) -> x1 + v46 ImmData(24) -> x1 + v47 Load { addr=v46, disp=0, kind=I64 } -> x1 + v48 Store { addr=v3, disp=0, value=v47, kind=I64 } -> - + v49 Load { addr=v3, disp=0, kind=I64 } -> x0 + terminator GotoIndirect(v47) (exit_acc=v47) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=flag_table +fn ent_pc=1 n_params=2 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 ImmData(56) -> x0 + v6 Imm(16) -> x1 + v7 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x1 + v8 Load { addr=v5, disp=16, kind=I8 } -> x1 + terminator Bz { cond=v8, target=b5, fall=b1 } (exit_acc=v8) + block 1 start_pc=0 + v9 Imm(0) -> x2 + v10 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 + v15 Phi { incoming=[b1:v9, b7:v30], kind=I64 } -> x2 + v16 LoadLocal { off=-1, kind=I64 } -> x1 + v17 LoadLocal { off=3, kind=I32 } -> x1 + terminator Bz { cond=v3, target=b4, fall=b3 } (exit_acc=v3) + block 3 start_pc=0 + v37 ImmData(56) -> x1 + v38 Imm(4) -> x1 + v39 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 + v40 Imm(7) -> x1 + v41 Store { addr=v5, disp=4, value=v40, kind=I32 } -> - + terminator Jmp(b4) (exit_acc=v41) + block 4 start_pc=0 + v42 ImmData(56) -> x1 + v43 LoadLocal { off=2, kind=I32 } -> x1 + v44 BinopI { op=shl, lhs=v1, rhs_imm=2 } -> x1 + v45 Binop { op=add, lhs=v5, rhs=v44 } -> x1 + v46 LoadIndexed { base=v5, index=v1, scale=4, kind=I32 } -> x0 + terminator Return(v46) (exit_acc=v46) + block 5 start_pc=0 + v11 ImmData(56) -> x1 + v12 Imm(0) -> x8 + v13 Imm(1) -> x1 + v14 Imm(0) -> x2 + terminator Jmp(b6) (exit_acc=v13) + block 6 start_pc=0 + v18 Imm(1) -> x8 + v19 Imm(0) -> x1 + terminator Jmp(b7) (exit_acc=v18) + block 7 start_pc=0 + v20 Phi { incoming=[b5:v12, b6:v18], kind=I64 } -> x8 + v21 LoadLocal { off=-2, kind=I64 } -> x1 + v22 Store { addr=v5, disp=0, value=v20, kind=I32 } -> - + v23 ImmData(56) -> x1 + v24 Imm(4) -> x1 + v25 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 + v26 Imm(0) -> x1 + v27 Store { addr=v5, disp=4, value=v26, kind=I32 } -> - + v28 Imm(8) -> x1 + v29 BinopI { op=add, lhs=v5, rhs_imm=8 } -> x1 + v30 Imm(1) -> x2 + v31 Store { addr=v5, disp=8, value=v30, kind=I32 } -> - + v32 Imm(16) -> x1 + v33 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x1 + v34 Store { addr=v5, disp=16, value=v30, kind=I8 } -> - + v35 Imm(72057594037927936) -> x1 + v36 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v30) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x7 + v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v3 BinopI { op=ne, lhs=v2, rhs_imm=20 } -> x0 + terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + block 1 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 2 start_pc=0 + v5 Imm(1) -> x7 + v6 Call { target_pc=0, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=ne, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + block 3 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + v9 Imm(1) -> x7 + v10 Call { target_pc=1, args=[v9, v9], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x0 + terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + block 5 start_pc=0 + v12 Imm(4) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 + v13 Imm(1) -> x7 + v14 Imm(0) -> x6 + v15 Call { target_pc=1, args=[v13, v14], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v16 BinopI { op=ne, lhs=v15, rhs_imm=7 } -> x0 + terminator Bz { cond=v16, target=b8, fall=b7 } (exit_acc=v16) + block 7 start_pc=0 + v17 Imm(5) -> x0 + terminator Return(v17) (exit_acc=v17) + block 8 start_pc=0 + v18 Imm(0) -> x7 + v19 Call { target_pc=1, args=[v18, v18], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v20 BinopI { op=ne, lhs=v19, rhs_imm=1 } -> x0 + terminator Bz { cond=v20, target=b10, fall=b9 } (exit_acc=v20) + block 9 start_pc=0 + v21 Imm(6) -> x0 + terminator Return(v21) (exit_acc=v21) + block 10 start_pc=0 + v22 Imm(0) -> x0 + terminator Return(v22) (exit_acc=v22) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/static_init_paren_relocation.ssa b/tests/snapshots/ssa/static_init_paren_relocation.ssa index bb7bd5f6d..dd4d3d9ed 100644 --- a/tests/snapshots/ssa/static_init_paren_relocation.ssa +++ b/tests/snapshots/ssa/static_init_paren_relocation.ssa @@ -44,18 +44,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 v16 ImmData(64) -> x0 v17 Load { addr=v16, disp=0, kind=I64 } -> x0 v18 ImmData(8) -> x1 - v19 Binop { op=ne, lhs=v17, rhs=v18 } -> x3 + v19 Binop { op=ne, lhs=v17, rhs=v18 } -> x1 v20 Imm(0) -> x0 terminator Bnz { cond=v19, target=b11, fall=b5 } (exit_acc=v19) block 5 start_pc=0 v21 ImmData(64) -> x0 v22 Load { addr=v21, disp=0, kind=I64 } -> x0 v23 Load { addr=v22, disp=0, kind=I32 } -> x0 - v24 BinopI { op=ne, lhs=v23, rhs_imm=99 } -> x3 + v24 BinopI { op=ne, lhs=v23, rhs_imm=99 } -> x1 v25 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v24) block 6 start_pc=0 - v26 Phi { incoming=[b11:v19, b5:v24], kind=I64 } -> x3 + v26 Phi { incoming=[b11:v19, b5:v24], kind=I64 } -> x1 v27 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) block 7 start_pc=0 diff --git a/tests/snapshots/ssa/static_inline_function.ssa b/tests/snapshots/ssa/static_inline_function.ssa index 3cd7b0412..0e245edb2 100644 --- a/tests/snapshots/ssa/static_inline_function.ssa +++ b/tests/snapshots/ssa/static_inline_function.ssa @@ -24,13 +24,8 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 Imm(0) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v3, b2:v11], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x7 - v7 LoadLocal { off=2, kind=I64 } -> x0 - terminator Bz { cond=v6, target=b3, fall=b2 } (exit_acc=v6) - block 2 start_pc=0 v8 LoadLocal { off=-1, kind=I64 } -> x0 v9 LoadLocal { off=2, kind=I64 } -> x0 v10 BinopI { op=and, lhs=v6, rhs_imm=1 } -> x0 @@ -38,7 +33,12 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v12 Imm(0) -> x0 v13 BinopI { op=shru, lhs=v6, rhs_imm=1 } -> x7 v14 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b2) (exit_acc=v13) + block 2 start_pc=0 + v5 Phi { incoming=[b0:v3, b1:v11], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v1, b1:v13], kind=I64 } -> x7 + v7 LoadLocal { off=2, kind=I64 } -> x0 + terminator Bnz { cond=v6, target=b1, fall=b3 } (exit_acc=v6) block 3 start_pc=0 v15 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v5) (exit_acc=v5) @@ -49,53 +49,53 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 - v3 Imm(0) -> x1 - v4 BinopI { op=mul, lhs=v1, rhs_imm=3 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x1 - v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x0 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x1 - v9 Extend { value=v7, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=7 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(2) -> x0 + v3 Imm(0) -> x0 + v4 Imm(6) -> x0 + v5 Imm(25769803776) -> x0 + v6 Imm(6) -> x0 + v7 Imm(7) -> x0 + v8 Imm(30064771072) -> x0 + v9 Imm(7) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(-1) -> x0 - v13 Extend { value=v12, kind=I32 } -> x1 - v14 Imm(0) -> x1 - v15 BinopI { op=mul, lhs=v12, rhs_imm=3 } -> x0 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 - v17 Extend { value=v15, kind=I32 } -> x1 - v18 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 - v19 BinopI { op=shl, lhs=v18, rhs_imm=32 } -> x1 - v20 Extend { value=v18, kind=I32 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=-2 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) - block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) - block 4 start_pc=0 + v13 Imm(-1) -> x0 + v14 Imm(0) -> x0 + v15 Imm(-3) -> x0 + v16 Imm(-12884901888) -> x0 + v17 Imm(-3) -> x0 + v18 Imm(-2) -> x0 + v19 Imm(-8589934592) -> x0 + v20 Imm(-2) -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 v23 Imm(3735928559) -> x7 v24 Call { target_pc=1, args=[v23], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v25 BinopI { op=ne, lhs=v24, rhs_imm=24 } -> x0 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) - block 5 start_pc=0 + terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + block 3 start_pc=0 v26 Imm(3) -> x0 terminator Return(v26) (exit_acc=v26) - block 6 start_pc=0 + block 4 start_pc=0 v27 Imm(0) -> x7 v28 Call { target_pc=1, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v29 BinopI { op=ne, lhs=v28, rhs_imm=0 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) - block 7 start_pc=0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) + block 5 start_pc=0 v30 Imm(4) -> x0 terminator Return(v30) (exit_acc=v30) - block 8 start_pc=0 + block 6 start_pc=0 v31 Imm(0) -> x0 terminator Return(v31) (exit_acc=v31) + block 7 start_pc=0 + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) + block 8 start_pc=0 + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/static_linked_list.ssa b/tests/snapshots/ssa/static_linked_list.ssa index 0f3bf7cc8..45892d390 100644 --- a/tests/snapshots/ssa/static_linked_list.ssa +++ b/tests/snapshots/ssa/static_linked_list.ssa @@ -24,14 +24,8 @@ fn ent_pc=5 n_params=0 variadic=false locals=2 v18 ImmData(8) -> x0 v19 Load { addr=v18, disp=0, kind=I64 } -> x1 v20 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v19) + terminator Jmp(b2) (exit_acc=v19) block 1 start_pc=0 - v21 Phi { incoming=[b0:v19, b2:v33], kind=I64 } -> x1 - v22 Phi { incoming=[b0:v15, b2:v28], kind=I64 } -> x2 - v23 LoadLocal { off=-2, kind=I64 } -> x0 - v24 BinopI { op=ne, lhs=v21, rhs_imm=0 } -> x0 - terminator Bz { cond=v24, target=b3, fall=b2 } (exit_acc=v24) - block 2 start_pc=0 v25 Extend { value=v22, kind=I32 } -> x0 v26 LoadLocal { off=-2, kind=I64 } -> x0 v27 Load { addr=v21, disp=0, kind=I32 } -> x0 @@ -42,7 +36,13 @@ fn ent_pc=5 n_params=0 variadic=false locals=2 v32 BinopI { op=add, lhs=v21, rhs_imm=8 } -> x0 v33 Load { addr=v21, disp=8, kind=I64 } -> x1 v34 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v33) + terminator Jmp(b2) (exit_acc=v33) + block 2 start_pc=0 + v21 Phi { incoming=[b0:v19, b1:v33], kind=I64 } -> x1 + v22 Phi { incoming=[b0:v15, b1:v28], kind=I64 } -> x2 + v23 LoadLocal { off=-2, kind=I64 } -> x0 + v24 BinopI { op=ne, lhs=v21, rhs_imm=0 } -> x0 + terminator Bnz { cond=v24, target=b1, fall=b3 } (exit_acc=v24) block 3 start_pc=0 v35 Extend { value=v22, kind=I32 } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=6 } -> x0 diff --git a/tests/snapshots/ssa/static_local_shadows_extern_fn.ssa b/tests/snapshots/ssa/static_local_shadows_extern_fn.ssa index d226f71e7..80aad0355 100644 --- a/tests/snapshots/ssa/static_local_shadows_extern_fn.ssa +++ b/tests/snapshots/ssa/static_local_shadows_extern_fn.ssa @@ -28,12 +28,26 @@ fn ent_pc=1 n_params=1 variadic=false locals=2 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v6, target=b4, fall=b5 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b5, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b7:v3, b2:v18, b8:v3, b3:v20], kind=I64 } -> x1 + v23 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v23, target=b4, fall=b2 } (exit_acc=v23) + block 2 start_pc=0 + terminator Jmp(b3) + block 3 start_pc=0 + v7 Phi { incoming=[b6:v3, b7:v18, b2:v3, b4:v20], kind=I64 } -> x1 v8 Extend { value=v7, kind=I32 } -> x0 terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 + block 4 start_pc=0 + v20 Imm(-1) -> x1 + v21 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v20) + block 5 start_pc=0 + v22 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bnz { cond=v22, target=b7, fall=b6 } (exit_acc=v22) + block 6 start_pc=0 + terminator Jmp(b3) + block 7 start_pc=0 v9 ImmData(8) -> x0 v10 Imm(0) -> x1 v11 Imm(0) -> x1 @@ -45,23 +59,9 @@ fn ent_pc=1 n_params=1 variadic=false locals=2 v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 v18 Extend { value=v16, kind=I32 } -> x1 v19 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v18) - block 3 start_pc=0 - v20 Imm(-1) -> x1 - v21 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v20) - block 4 start_pc=0 - v22 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v22, target=b2, fall=b7 } (exit_acc=v22) - block 5 start_pc=0 - v23 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v23, target=b3, fall=b8 } (exit_acc=v23) - block 6 start_pc=0 - terminator Jmp(b2) - block 7 start_pc=0 - terminator Jmp(b1) + terminator Jmp(b3) (exit_acc=v18) block 8 start_pc=0 - terminator Jmp(b1) + terminator Jmp(b7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/stdatomic_c11.ssa b/tests/snapshots/ssa/stdatomic_c11.ssa index 40072820a..6e795505c 100644 --- a/tests/snapshots/ssa/stdatomic_c11.ssa +++ b/tests/snapshots/ssa/stdatomic_c11.ssa @@ -112,19 +112,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 terminator Return(v71) (exit_acc=v71) block 18 start_pc=0 v72 Imm(32767) -> x0 - v73 Imm(0) -> x1 - v74 Imm(4294967295) -> x1 - v75 Imm(0) -> x2 - v76 Imm(0) -> x6 - v77 Imm(0) -> x2 + v73 Imm(0) -> x0 + v74 Imm(4294967295) -> x0 + v75 Imm(0) -> x0 + v76 Imm(0) -> x1 + v77 Imm(0) -> x0 terminator Jmp(b19) (exit_acc=v76) block 19 start_pc=0 - v78 LoadLocal { off=-7, kind=I16 } -> x2 - v79 BinopI { op=ne, lhs=v72, rhs_imm=32767 } -> x6 + v78 LoadLocal { off=-7, kind=I16 } -> x0 + v79 Imm(0) -> x1 v80 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v79) block 20 start_pc=0 - v81 Phi { incoming=[b18:v76, b19:v79], kind=I64 } -> x6 + v81 Phi { incoming=[b18:v76, b19:v79], kind=I64 } -> x1 v82 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v81, target=b22, fall=b21 } (exit_acc=v81) block 21 start_pc=0 @@ -132,20 +132,20 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 terminator Return(v83) (exit_acc=v83) block 22 start_pc=0 v84 LoadLocal { off=-8, kind=U32 } -> x0 - v85 BinopI { op=ne, lhs=v74, rhs_imm=4294967295 } -> x0 - terminator Bz { cond=v85, target=b24, fall=b23 } (exit_acc=v85) + v85 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v85) block 23 start_pc=0 - v86 Imm(11) -> x0 - terminator Return(v86) (exit_acc=v86) - block 24 start_pc=0 v87 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v87) + terminator Jmp(b24) (exit_acc=v87) + block 24 start_pc=0 + v89 Imm(0) -> x0 + terminator Return(v89) (exit_acc=v89) block 25 start_pc=0 + v86 Imm(11) -> x0 + terminator Return(v86) (exit_acc=v86) + block 26 start_pc=0 v88 Imm(12) -> x0 terminator Return(v88) (exit_acc=v88) - block 26 start_pc=0 - v89 Imm(0) -> x0 - terminator Return(v89) (exit_acc=v89) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/stdint_min_macros_type_and_value.ssa b/tests/snapshots/ssa/stdint_min_macros_type_and_value.ssa index 0eee05999..9b382f303 100644 --- a/tests/snapshots/ssa/stdint_min_macros_type_and_value.ssa +++ b/tests/snapshots/ssa/stdint_min_macros_type_and_value.ssa @@ -7,68 +7,68 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v1 Imm(-2147483648) -> x0 v2 Imm(-9223372036854775808) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(21) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(-2147483648) -> x0 v6 Imm(-9223372036854775808) -> x0 v7 Imm(-1) -> x0 v8 Imm(-4294967296) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v9) - block 3 start_pc=0 - v10 Imm(22) -> x0 - terminator Return(v10) (exit_acc=v10) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 v11 Imm(-9223372036854775808) -> x0 v12 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v12) - block 5 start_pc=0 - v13 Imm(10) -> x0 - terminator Return(v13) (exit_acc=v13) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v12) + block 3 start_pc=0 v14 Imm(-9223372036854775808) -> x0 v15 Imm(-1) -> x0 v16 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v16) - block 7 start_pc=0 - v17 Imm(11) -> x0 - terminator Return(v17) (exit_acc=v17) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v16) + block 4 start_pc=0 v18 Imm(-9223372036854775808) -> x0 v19 Imm(0) -> x0 v20 Imm(1) -> x2 v21 Imm(0) -> x1 - terminator Jmp(b9) (exit_acc=v19) - block 9 start_pc=0 + terminator Jmp(b5) (exit_acc=v19) + block 5 start_pc=0 v22 Imm(-9223372036854775808) -> x0 v23 Imm(0) -> x2 v24 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v23) - block 10 start_pc=0 - v25 Phi { incoming=[b8:v20, b9:v23], kind=I64 } -> x2 + terminator Jmp(b6) (exit_acc=v23) + block 6 start_pc=0 + v25 Phi { incoming=[b4:v20, b5:v23], kind=I64 } -> x2 v26 LoadLocal { off=-2, kind=I64 } -> x0 v27 Imm(0) -> x0 - terminator Bnz { cond=v25, target=b15, fall=b11 } (exit_acc=v25) - block 11 start_pc=0 + terminator Bnz { cond=v25, target=b11, fall=b7 } (exit_acc=v25) + block 7 start_pc=0 v28 Imm(-9223372036854775808) -> x0 v29 Imm(0) -> x2 v30 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v29) - block 12 start_pc=0 - v31 Phi { incoming=[b15:v25, b11:v29], kind=I64 } -> x2 + terminator Jmp(b8) (exit_acc=v29) + block 8 start_pc=0 + v31 Phi { incoming=[b11:v25, b7:v29], kind=I64 } -> x2 v32 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v31, target=b14, fall=b13 } (exit_acc=v31) - block 13 start_pc=0 + terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) + block 9 start_pc=0 v33 Imm(30) -> x0 terminator Return(v33) (exit_acc=v33) - block 14 start_pc=0 + block 10 start_pc=0 v34 Imm(0) -> x0 terminator Return(v34) (exit_acc=v34) + block 11 start_pc=0 + terminator Jmp(b8) + block 12 start_pc=0 + v4 Imm(21) -> x0 + terminator Return(v4) (exit_acc=v4) + block 13 start_pc=0 + v10 Imm(22) -> x0 + terminator Return(v10) (exit_acc=v10) + block 14 start_pc=0 + v13 Imm(10) -> x0 + terminator Return(v13) (exit_acc=v13) block 15 start_pc=0 - terminator Jmp(b12) + v17 Imm(11) -> x0 + terminator Return(v17) (exit_acc=v17) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/stdint_widths.ssa b/tests/snapshots/ssa/stdint_widths.ssa index 638f8adc3..69e1a751d 100644 --- a/tests/snapshots/ssa/stdint_widths.ssa +++ b/tests/snapshots/ssa/stdint_widths.ssa @@ -5,126 +5,126 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v11 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v11) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v13 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v13) block 7 start_pc=0 - v8 Imm(4) -> x0 - terminator Return(v8) (exit_acc=v8) + v15 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v15) block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) + v17 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v17) block 9 start_pc=0 - v10 Imm(5) -> x0 - terminator Return(v10) (exit_acc=v10) + v19 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v19) block 10 start_pc=0 - v11 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v11) + v21 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v21) block 11 start_pc=0 - v12 Imm(6) -> x0 - terminator Return(v12) (exit_acc=v12) + v23 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v23) block 12 start_pc=0 - v13 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v13) + v25 Imm(1234605616436508552) -> x0 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-1, kind=I64 } -> x0 + v28 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v28) block 13 start_pc=0 - v14 Imm(11) -> x0 - terminator Return(v14) (exit_acc=v14) + v30 Imm(-81985529216486896) -> x0 + v31 Imm(0) -> x0 + v32 LoadLocal { off=-2, kind=I64 } -> x0 + v33 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v33) block 14 start_pc=0 - v15 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v15) + v35 Imm(42) -> x0 + v36 StoreLocal { off=-3, value=v35, kind=I32 } -> - + v37 LocalAddr(-3) -> x0 + v38 Imm(0) -> x1 + v39 LoadLocal { off=-4, kind=I64 } -> x1 + v40 Imm(0) -> x1 + v41 LoadLocal { off=-5, kind=I64 } -> x1 + v42 Imm(0) -> x1 + v43 LoadLocal { off=-6, kind=I64 } -> x1 + v44 Load { addr=v37, disp=0, kind=I32 } -> x0 + v45 BinopI { op=ne, lhs=v44, rhs_imm=42 } -> x0 + terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) block 15 start_pc=0 - v16 Imm(12) -> x0 - terminator Return(v16) (exit_acc=v16) + v46 Imm(23) -> x0 + terminator Return(v46) (exit_acc=v46) block 16 start_pc=0 - v17 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v17) + v47 Imm(-1) -> x0 + v48 Imm(0) -> x0 + v49 LoadLocal { off=-7, kind=I16 } -> x0 + v50 Imm(0) -> x0 + v51 Imm(-1) -> x0 + v52 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v52) block 17 start_pc=0 - v18 Imm(13) -> x0 - terminator Return(v18) (exit_acc=v18) + v54 ImmData(36) -> x7 + v55 CallExt { binding_idx=0, args=[v54], fp_arg_mask=0x0 } -> x0 + v56 Imm(0) -> x0 + terminator Return(v56) (exit_acc=v56) block 18 start_pc=0 - v19 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v19) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 19 start_pc=0 - v20 Imm(14) -> x0 - terminator Return(v20) (exit_acc=v20) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 20 start_pc=0 - v21 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v21) + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) block 21 start_pc=0 - v22 Imm(15) -> x0 - terminator Return(v22) (exit_acc=v22) + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) block 22 start_pc=0 - v23 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v23) + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) block 23 start_pc=0 - v24 Imm(16) -> x0 - terminator Return(v24) (exit_acc=v24) + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) block 24 start_pc=0 - v25 Imm(1234605616436508552) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-1, kind=I64 } -> x1 - v28 BinopI { op=ne, lhs=v25, rhs_imm=1234605616436508552 } -> x0 - terminator Bz { cond=v28, target=b26, fall=b25 } (exit_acc=v28) + v14 Imm(11) -> x0 + terminator Return(v14) (exit_acc=v14) block 25 start_pc=0 - v29 Imm(21) -> x0 - terminator Return(v29) (exit_acc=v29) + v16 Imm(12) -> x0 + terminator Return(v16) (exit_acc=v16) block 26 start_pc=0 - v30 Imm(-81985529216486896) -> x0 - v31 Imm(0) -> x1 - v32 LoadLocal { off=-2, kind=I64 } -> x1 - v33 BinopI { op=ne, lhs=v30, rhs_imm=-81985529216486896 } -> x0 - terminator Bz { cond=v33, target=b28, fall=b27 } (exit_acc=v33) + v18 Imm(13) -> x0 + terminator Return(v18) (exit_acc=v18) block 27 start_pc=0 - v34 Imm(22) -> x0 - terminator Return(v34) (exit_acc=v34) + v20 Imm(14) -> x0 + terminator Return(v20) (exit_acc=v20) block 28 start_pc=0 - v35 Imm(42) -> x0 - v36 StoreLocal { off=-3, value=v35, kind=I32 } -> - - v37 LocalAddr(-3) -> x0 - v38 Imm(0) -> x1 - v39 LoadLocal { off=-4, kind=I64 } -> x1 - v40 Imm(0) -> x1 - v41 LoadLocal { off=-5, kind=I64 } -> x1 - v42 Imm(0) -> x1 - v43 LoadLocal { off=-6, kind=I64 } -> x1 - v44 Load { addr=v37, disp=0, kind=I32 } -> x0 - v45 BinopI { op=ne, lhs=v44, rhs_imm=42 } -> x0 - terminator Bz { cond=v45, target=b30, fall=b29 } (exit_acc=v45) + v22 Imm(15) -> x0 + terminator Return(v22) (exit_acc=v22) block 29 start_pc=0 - v46 Imm(23) -> x0 - terminator Return(v46) (exit_acc=v46) + v24 Imm(16) -> x0 + terminator Return(v24) (exit_acc=v24) block 30 start_pc=0 - v47 Imm(-1) -> x0 - v48 Imm(0) -> x1 - v49 LoadLocal { off=-7, kind=I16 } -> x1 - v50 Imm(0) -> x1 - v51 Extend { value=v47, kind=I32 } -> x0 - v52 BinopI { op=ne, lhs=v51, rhs_imm=-1 } -> x0 - terminator Bz { cond=v52, target=b32, fall=b31 } (exit_acc=v52) + v29 Imm(21) -> x0 + terminator Return(v29) (exit_acc=v29) block 31 start_pc=0 + v34 Imm(22) -> x0 + terminator Return(v34) (exit_acc=v34) + block 32 start_pc=0 v53 Imm(24) -> x0 terminator Return(v53) (exit_acc=v53) - block 32 start_pc=0 - v54 ImmData(36) -> x7 - v55 CallExt { binding_idx=0, args=[v54], fp_arg_mask=0x0 } -> x0 - v56 Imm(0) -> x0 - terminator Return(v56) (exit_acc=v56) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/store_forward_local_slot.ssa b/tests/snapshots/ssa/store_forward_local_slot.ssa new file mode 100644 index 000000000..0ab56b45a --- /dev/null +++ b/tests/snapshots/ssa/store_forward_local_slot.ssa @@ -0,0 +1,177 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=forwards +fn ent_pc=0 n_params=1 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 BlockAddr(block=1) -> x0 + v4 StoreLocal { off=-1, value=v3, kind=I64 } -> - + v5 Extend { value=v1, kind=I32 } -> x1 + v6 BinopI { op=mul, lhs=v5, rhs_imm=3 } -> x1 + v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x2 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 StoreLocal { off=-2, value=v6, kind=I32 } -> - + v10 Extend { value=v6, kind=I32 } -> x1 + v11 Binop { op=add, lhs=v10, rhs=v10 } -> x1 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x2 + v13 Extend { value=v11, kind=I32 } -> x2 + v14 StoreLocal { off=-3, value=v11, kind=I32 } -> - + v15 LoadLocal { off=-1, kind=I64 } -> x1 + terminator GotoIndirect(v3) (exit_acc=v3) + block 1 start_pc=0 + v16 LoadLocal { off=-3, kind=I32 } -> x0 + terminator Return(v16) (exit_acc=v16) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=volatile_kept +fn ent_pc=1 n_params=1 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 BlockAddr(block=1) -> x0 + v4 StoreLocal { off=-1, value=v3, kind=I64 } -> - + v5 Extend { value=v1, kind=I32 } -> x1 + v6 StoreLocal { off=-2, value=v5, kind=I32, volatile } -> - + v7 LoadLocal { off=-2, kind=I32, volatile } -> x1 + v8 StoreLocal { off=-3, value=v7, kind=I32 } -> - + v9 LoadLocal { off=-1, kind=I64 } -> x1 + terminator GotoIndirect(v3) (exit_acc=v3) + block 1 start_pc=0 + v10 LoadLocal { off=-3, kind=I32 } -> x0 + terminator Return(v10) (exit_acc=v10) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=aliased_kept +fn ent_pc=2 n_params=1 variadic=false locals=4 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 BlockAddr(block=1) -> x0 + v4 StoreLocal { off=-1, value=v3, kind=I64 } -> - + v5 LocalAddr(-2) -> x1 + v6 StoreLocal { off=-3, value=v5, kind=I64 } -> - + v7 Extend { value=v1, kind=I32 } -> x2 + v8 StoreLocal { off=-2, value=v7, kind=I32 } -> - + v9 LoadLocal { off=-3, kind=I64 } -> x6 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x2 + v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x6 + v12 Extend { value=v10, kind=I32 } -> x6 + v13 Store { addr=v5, disp=0, value=v10, kind=I32 } -> - + v14 LoadLocal { off=-2, kind=I32 } -> x1 + v15 StoreLocal { off=-4, value=v14, kind=I32 } -> - + v16 LoadLocal { off=-1, kind=I64 } -> x1 + terminator GotoIndirect(v3) (exit_acc=v3) + block 1 start_pc=0 + v17 LoadLocal { off=-4, kind=I32 } -> x0 + terminator Return(v17) (exit_acc=v17) +; --- SSA dump (ok=true) ent_pc=3 --- +; name=cross_block +fn ent_pc=3 n_params=1 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 BlockAddr(block=1) -> x0 + v4 StoreLocal { off=-1, value=v3, kind=I64 } -> - + v5 Extend { value=v1, kind=I32 } -> x1 + v6 BinopI { op=shl, lhs=v5, rhs_imm=1 } -> x1 + v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x2 + v8 Extend { value=v6, kind=I32 } -> x2 + v9 StoreLocal { off=-2, value=v6, kind=I32 } -> - + v10 LoadLocal { off=-1, kind=I64 } -> x1 + terminator GotoIndirect(v3) (exit_acc=v3) + block 1 start_pc=0 + v11 LoadLocal { off=-2, kind=I32 } -> x0 + terminator Return(v11) (exit_acc=v11) +; --- SSA dump (ok=true) ent_pc=4 --- +; name=main +fn ent_pc=4 n_params=0 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(5) -> x7 + v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v3 BinopI { op=ne, lhs=v2, rhs_imm=30 } -> x0 + terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + block 1 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) + block 2 start_pc=0 + v5 Imm(7) -> x7 + v6 Call { target_pc=1, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=ne, lhs=v6, rhs_imm=7 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + block 3 start_pc=0 + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + v9 Imm(9) -> x7 + v10 Call { target_pc=2, args=[v9], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 BinopI { op=ne, lhs=v10, rhs_imm=10 } -> x0 + terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + block 5 start_pc=0 + v12 Imm(3) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 + v13 Imm(6) -> x7 + v14 Call { target_pc=3, args=[v13], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v15 BinopI { op=ne, lhs=v14, rhs_imm=12 } -> x0 + terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) + block 7 start_pc=0 + v16 Imm(4) -> x0 + terminator Return(v16) (exit_acc=v16) + block 8 start_pc=0 + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/store_to_load_forward.ssa b/tests/snapshots/ssa/store_to_load_forward.ssa index 80ea0af00..ca62579cf 100644 --- a/tests/snapshots/ssa/store_to_load_forward.ssa +++ b/tests/snapshots/ssa/store_to_load_forward.ssa @@ -80,14 +80,14 @@ fn ent_pc=1 n_params=2 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=no_forward_across_call fn ent_pc=2 n_params=2 variadic=false locals=3 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x3 v2 Imm(0) -> x0 v3 ParamRef(1, kind=I64) -> x6 v4 Imm(0) -> x0 - v5 Imm(0) -> x12 + v5 Imm(0) -> x0 v6 Imm(0) -> x0 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 LoadLocal { off=3, kind=I64 } -> x0 @@ -96,7 +96,7 @@ fn ent_pc=2 n_params=2 variadic=false locals=3 v11 LoadLocal { off=2, kind=I64 } -> x0 v12 LoadLocal { off=3, kind=I64 } -> x0 v13 Call { target_pc=1, args=[v1, v3], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v14 Binop { op=add, lhs=v5, rhs=v13 } -> x0 + v14 BinopI { op=add, lhs=v13, rhs_imm=0 } -> x0 v15 Imm(0) -> x1 v16 LoadLocal { off=-1, kind=I64 } -> x1 v17 LoadLocal { off=2, kind=I64 } -> x1 diff --git a/tests/snapshots/ssa/strength_reduce_pow2_divmod.ssa b/tests/snapshots/ssa/strength_reduce_pow2_divmod.ssa index 10a1f0bfa..261f94845 100644 --- a/tests/snapshots/ssa/strength_reduce_pow2_divmod.ssa +++ b/tests/snapshots/ssa/strength_reduce_pow2_divmod.ssa @@ -14,7 +14,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v8 BinopI { op=shr, lhs=v7, rhs_imm=1 } -> x0 v9 BinopI { op=ne, lhs=v8, rhs_imm=-3 } -> x1 v10 Imm(0) -> x0 - terminator Bnz { cond=v9, target=b45, fall=b1 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b55, fall=b1 } (exit_acc=v9) block 1 start_pc=0 v11 LoadLocal { off=-1, kind=I32, volatile } -> x0 v12 Imm(2) -> x1 @@ -27,7 +27,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v19 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v20 Phi { incoming=[b45:v9, b1:v18], kind=I64 } -> x1 + v20 Phi { incoming=[b55:v9, b1:v18], kind=I64 } -> x1 v21 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) block 3 start_pc=0 @@ -44,7 +44,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v30 BinopI { op=shr, lhs=v29, rhs_imm=4 } -> x0 v31 BinopI { op=ne, lhs=v30, rhs_imm=-1 } -> x1 v32 Imm(0) -> x0 - terminator Bnz { cond=v31, target=b46, fall=b5 } (exit_acc=v31) + terminator Bnz { cond=v31, target=b54, fall=b5 } (exit_acc=v31) block 5 start_pc=0 v33 LoadLocal { off=-1, kind=I32, volatile } -> x0 v34 Imm(16) -> x1 @@ -57,7 +57,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v41 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v40) block 6 start_pc=0 - v42 Phi { incoming=[b46:v31, b5:v40], kind=I64 } -> x1 + v42 Phi { incoming=[b54:v31, b5:v40], kind=I64 } -> x1 v43 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) block 7 start_pc=0 @@ -74,7 +74,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v52 BinopI { op=shr, lhs=v51, rhs_imm=4 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=-1 } -> x1 v54 Imm(0) -> x0 - terminator Bnz { cond=v53, target=b47, fall=b9 } (exit_acc=v53) + terminator Bnz { cond=v53, target=b53, fall=b9 } (exit_acc=v53) block 9 start_pc=0 v55 LoadLocal { off=-1, kind=I32, volatile } -> x0 v56 Imm(16) -> x1 @@ -87,7 +87,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v63 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v62) block 10 start_pc=0 - v64 Phi { incoming=[b47:v53, b9:v62], kind=I64 } -> x1 + v64 Phi { incoming=[b53:v53, b9:v62], kind=I64 } -> x1 v65 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v64, target=b12, fall=b11 } (exit_acc=v64) block 11 start_pc=0 @@ -104,7 +104,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v74 BinopI { op=shr, lhs=v73, rhs_imm=3 } -> x0 v75 BinopI { op=ne, lhs=v74, rhs_imm=12 } -> x1 v76 Imm(0) -> x0 - terminator Bnz { cond=v75, target=b48, fall=b13 } (exit_acc=v75) + terminator Bnz { cond=v75, target=b52, fall=b13 } (exit_acc=v75) block 13 start_pc=0 v77 LoadLocal { off=-1, kind=I32, volatile } -> x0 v78 Imm(8) -> x1 @@ -117,7 +117,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v85 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v84) block 14 start_pc=0 - v86 Phi { incoming=[b48:v75, b13:v84], kind=I64 } -> x1 + v86 Phi { incoming=[b52:v75, b13:v84], kind=I64 } -> x1 v87 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v86, target=b16, fall=b15 } (exit_acc=v86) block 15 start_pc=0 @@ -135,7 +135,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v97 BinopI { op=shr, lhs=v96, rhs_imm=1 } -> x0 v98 BinopI { op=ne, lhs=v97, rhs_imm=-1073741824 } -> x1 v99 Imm(0) -> x0 - terminator Bnz { cond=v98, target=b49, fall=b17 } (exit_acc=v98) + terminator Bnz { cond=v98, target=b51, fall=b17 } (exit_acc=v98) block 17 start_pc=0 v100 LoadLocal { off=-1, kind=I32, volatile } -> x0 v101 Imm(2) -> x1 @@ -148,7 +148,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v108 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v107) block 18 start_pc=0 - v109 Phi { incoming=[b49:v98, b17:v107], kind=I64 } -> x1 + v109 Phi { incoming=[b51:v98, b17:v107], kind=I64 } -> x1 v110 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v109, target=b20, fall=b19 } (exit_acc=v109) block 19 start_pc=0 @@ -185,7 +185,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v131 BinopI { op=shru, lhs=v129, rhs_imm=4 } -> x0 v132 BinopI { op=ne, lhs=v131, rhs_imm=134217728 } -> x1 v133 Imm(0) -> x0 - terminator Bnz { cond=v132, target=b51, fall=b25 } (exit_acc=v132) + terminator Bnz { cond=v132, target=b49, fall=b25 } (exit_acc=v132) block 25 start_pc=0 v134 LoadLocal { off=-2, kind=U32, volatile } -> x0 v135 Imm(16) -> x1 @@ -194,7 +194,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v138 Imm(0) -> x0 terminator Jmp(b26) (exit_acc=v137) block 26 start_pc=0 - v139 Phi { incoming=[b51:v132, b25:v137], kind=I64 } -> x1 + v139 Phi { incoming=[b49:v132, b25:v137], kind=I64 } -> x1 v140 LoadLocal { off=-15, kind=I64 } -> x0 terminator Bz { cond=v139, target=b28, fall=b27 } (exit_acc=v139) block 27 start_pc=0 @@ -203,19 +203,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 block 28 start_pc=0 v142 Imm(-1234567) -> x0 v143 StoreLocal { off=-7, value=v142, kind=I64, volatile } -> - - v144 LoadLocal { off=-7, kind=I64, volatile } -> x1 - v145 Imm(1024) -> x2 - v146 BinopI { op=shr, lhs=v144, rhs_imm=63 } -> x2 - v147 BinopI { op=shru, lhs=v146, rhs_imm=54 } -> x2 - v148 Binop { op=add, lhs=v144, rhs=v147 } -> x1 - v149 BinopI { op=shr, lhs=v148, rhs_imm=10 } -> x1 - v150 Imm(-1) -> x2 - v151 Imm(1023) -> x2 - v152 Binop { op=add, lhs=v142, rhs=v151 } -> x0 - v153 BinopI { op=shr, lhs=v152, rhs_imm=10 } -> x0 - v154 Binop { op=ne, lhs=v149, rhs=v153 } -> x1 + v144 LoadLocal { off=-7, kind=I64, volatile } -> x0 + v145 Imm(1024) -> x1 + v146 BinopI { op=shr, lhs=v144, rhs_imm=63 } -> x1 + v147 BinopI { op=shru, lhs=v146, rhs_imm=54 } -> x1 + v148 Binop { op=add, lhs=v144, rhs=v147 } -> x0 + v149 BinopI { op=shr, lhs=v148, rhs_imm=10 } -> x0 + v150 Imm(-1) -> x1 + v151 Imm(1023) -> x1 + v152 Imm(-1233544) -> x1 + v153 Imm(-1205) -> x1 + v154 BinopI { op=ne, lhs=v149, rhs_imm=-1205 } -> x1 v155 Imm(0) -> x0 - terminator Bnz { cond=v154, target=b52, fall=b29 } (exit_acc=v154) + terminator Bnz { cond=v154, target=b48, fall=b29 } (exit_acc=v154) block 29 start_pc=0 v156 LoadLocal { off=-7, kind=I64, volatile } -> x0 v157 Imm(1024) -> x1 @@ -225,16 +225,16 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v161 BinopI { op=and, lhs=v160, rhs_imm=1023 } -> x0 v162 Binop { op=sub, lhs=v161, rhs=v159 } -> x0 v163 Imm(-1234567) -> x1 - v164 Imm(-1) -> x2 - v165 Imm(1023) -> x2 - v166 Binop { op=add, lhs=v163, rhs=v165 } -> x1 - v167 BinopI { op=and, lhs=v166, rhs_imm=1023 } -> x1 - v168 Binop { op=sub, lhs=v167, rhs=v165 } -> x1 - v169 Binop { op=ne, lhs=v162, rhs=v168 } -> x1 + v164 Imm(-1) -> x1 + v165 Imm(1023) -> x1 + v166 Imm(-1233544) -> x1 + v167 Imm(376) -> x1 + v168 Imm(-647) -> x1 + v169 BinopI { op=ne, lhs=v162, rhs_imm=-647 } -> x1 v170 Imm(0) -> x0 terminator Jmp(b30) (exit_acc=v169) block 30 start_pc=0 - v171 Phi { incoming=[b52:v154, b29:v169], kind=I64 } -> x1 + v171 Phi { incoming=[b48:v154, b29:v169], kind=I64 } -> x1 v172 LoadLocal { off=-16, kind=I64 } -> x0 terminator Bz { cond=v171, target=b32, fall=b31 } (exit_acc=v171) block 31 start_pc=0 @@ -251,7 +251,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v181 BinopI { op=shr, lhs=v180, rhs_imm=1 } -> x0 v182 BinopI { op=ne, lhs=v181, rhs_imm=-4611686018427387904 } -> x1 v183 Imm(0) -> x0 - terminator Bnz { cond=v182, target=b53, fall=b33 } (exit_acc=v182) + terminator Bnz { cond=v182, target=b47, fall=b33 } (exit_acc=v182) block 33 start_pc=0 v184 LoadLocal { off=-7, kind=I64, volatile } -> x0 v185 Imm(2) -> x1 @@ -264,7 +264,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v192 Imm(0) -> x0 terminator Jmp(b34) (exit_acc=v191) block 34 start_pc=0 - v193 Phi { incoming=[b53:v182, b33:v191], kind=I64 } -> x1 + v193 Phi { incoming=[b47:v182, b33:v191], kind=I64 } -> x1 v194 LoadLocal { off=-17, kind=I64 } -> x0 terminator Bz { cond=v193, target=b36, fall=b35 } (exit_acc=v193) block 35 start_pc=0 @@ -278,7 +278,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v200 BinopI { op=shru, lhs=v198, rhs_imm=1 } -> x0 v201 BinopI { op=ne, lhs=v200, rhs_imm=9223372036854775807 } -> x1 v202 Imm(0) -> x0 - terminator Bnz { cond=v201, target=b54, fall=b37 } (exit_acc=v201) + terminator Bnz { cond=v201, target=b46, fall=b37 } (exit_acc=v201) block 37 start_pc=0 v203 LoadLocal { off=-8, kind=I64, volatile } -> x0 v204 Imm(256) -> x1 @@ -287,7 +287,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v207 Imm(0) -> x0 terminator Jmp(b38) (exit_acc=v206) block 38 start_pc=0 - v208 Phi { incoming=[b54:v201, b37:v206], kind=I64 } -> x1 + v208 Phi { incoming=[b46:v201, b37:v206], kind=I64 } -> x1 v209 LoadLocal { off=-18, kind=I64 } -> x0 terminator Bz { cond=v208, target=b40, fall=b39 } (exit_acc=v208) block 39 start_pc=0 @@ -300,7 +300,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v214 Imm(1) -> x1 v215 BinopI { op=ne, lhs=v213, rhs_imm=-5 } -> x1 v216 Imm(0) -> x0 - terminator Bnz { cond=v215, target=b55, fall=b41 } (exit_acc=v215) + terminator Bnz { cond=v215, target=b45, fall=b41 } (exit_acc=v215) block 41 start_pc=0 v217 LoadLocal { off=-1, kind=I32, volatile } -> x0 v218 Imm(1) -> x0 @@ -308,7 +308,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v220 Imm(0) -> x0 terminator Jmp(b42) (exit_acc=v219) block 42 start_pc=0 - v221 Phi { incoming=[b55:v215, b41:v219], kind=I64 } -> x1 + v221 Phi { incoming=[b45:v215, b41:v219], kind=I64 } -> x1 v222 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v221, target=b44, fall=b43 } (exit_acc=v221) block 43 start_pc=0 @@ -318,27 +318,27 @@ fn ent_pc=0 n_params=0 variadic=false locals=19 v224 Imm(0) -> x0 terminator Return(v224) (exit_acc=v224) block 45 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b42) block 46 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b38) block 47 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b34) block 48 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b30) block 49 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b26) block 50 start_pc=0 terminator Jmp(b22) block 51 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b18) block 52 start_pc=0 - terminator Jmp(b30) + terminator Jmp(b14) block 53 start_pc=0 - terminator Jmp(b34) + terminator Jmp(b10) block 54 start_pc=0 - terminator Jmp(b38) + terminator Jmp(b6) block 55 start_pc=0 - terminator Jmp(b42) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/stringize_whitespace.ssa b/tests/snapshots/ssa/stringize_whitespace.ssa index d998a066a..e2eb171dc 100644 --- a/tests/snapshots/ssa/stringize_whitespace.ssa +++ b/tests/snapshots/ssa/stringize_whitespace.ssa @@ -10,68 +10,68 @@ fn ent_pc=0 n_params=2 variadic=false locals=3 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v12], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v15], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b6:v12], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b6:v15], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x0 v9 Imm(0) -> x2 v10 Imm(0) -> x1 - terminator Bz { cond=v8, target=b10, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b8, fall=b2 } (exit_acc=v8) block 2 start_pc=0 - v11 LoadLocal { off=2, kind=I64 } -> x0 - v12 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 - v13 Imm(0) -> x0 - v14 LoadLocal { off=3, kind=I64 } -> x0 - v15 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 - v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) - block 3 start_pc=0 - v17 LoadLocal { off=2, kind=I64 } -> x0 - v18 Load { addr=v5, disp=0, kind=I8 } -> x0 - v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x0 - v20 Imm(0) -> x2 - v21 Imm(0) -> x1 - terminator Bz { cond=v19, target=b11, fall=b8 } (exit_acc=v19) - block 4 start_pc=0 v22 LoadLocal { off=3, kind=I64 } -> x0 v23 Load { addr=v6, disp=0, kind=I8 } -> x0 v24 BinopI { op=ne, lhs=v23, rhs_imm=0 } -> x2 v25 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v24) - block 5 start_pc=0 - v26 Phi { incoming=[b10:v9, b4:v24], kind=I64 } -> x2 + terminator Jmp(b3) (exit_acc=v24) + block 3 start_pc=0 + v26 Phi { incoming=[b8:v9, b2:v24], kind=I64 } -> x2 v27 LoadLocal { off=-2, kind=I64 } -> x0 v28 Imm(0) -> x0 - terminator Bz { cond=v26, target=b12, fall=b6 } (exit_acc=v26) - block 6 start_pc=0 + terminator Bz { cond=v26, target=b7, fall=b4 } (exit_acc=v26) + block 4 start_pc=0 v29 LoadLocal { off=2, kind=I64 } -> x0 v30 Load { addr=v5, disp=0, kind=I8 } -> x0 v31 LoadLocal { off=3, kind=I64 } -> x1 v32 Load { addr=v6, disp=0, kind=I8 } -> x1 v33 Binop { op=eq, lhs=v30, rhs=v32 } -> x2 v34 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v33) - block 7 start_pc=0 - v35 Phi { incoming=[b12:v26, b6:v33], kind=I64 } -> x2 + terminator Jmp(b5) (exit_acc=v33) + block 5 start_pc=0 + v35 Phi { incoming=[b7:v26, b4:v33], kind=I64 } -> x2 v36 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v35, target=b3, fall=b2 } (exit_acc=v35) + terminator Bz { cond=v35, target=b9, fall=b6 } (exit_acc=v35) + block 6 start_pc=0 + v11 LoadLocal { off=2, kind=I64 } -> x0 + v12 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 + v13 Imm(0) -> x0 + v14 LoadLocal { off=3, kind=I64 } -> x0 + v15 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 + v16 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v15) + block 7 start_pc=0 + terminator Jmp(b5) block 8 start_pc=0 + terminator Jmp(b3) + block 9 start_pc=0 + v17 LoadLocal { off=2, kind=I64 } -> x0 + v18 Load { addr=v5, disp=0, kind=I8 } -> x0 + v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x0 + v20 Imm(0) -> x2 + v21 Imm(0) -> x1 + terminator Bz { cond=v19, target=b12, fall=b10 } (exit_acc=v19) + block 10 start_pc=0 v37 LoadLocal { off=3, kind=I64 } -> x0 v38 Load { addr=v6, disp=0, kind=I8 } -> x0 v39 BinopI { op=eq, lhs=v38, rhs_imm=0 } -> x0 v40 BinopI { op=ne, lhs=v39, rhs_imm=0 } -> x2 v41 Imm(0) -> x0 - terminator Jmp(b9) (exit_acc=v40) - block 9 start_pc=0 - v42 Phi { incoming=[b11:v20, b8:v40], kind=I64 } -> x2 + terminator Jmp(b11) (exit_acc=v40) + block 11 start_pc=0 + v42 Phi { incoming=[b12:v20, b10:v40], kind=I64 } -> x2 v43 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v42) (exit_acc=v42) - block 10 start_pc=0 - terminator Jmp(b5) - block 11 start_pc=0 - terminator Jmp(b9) block 12 start_pc=0 - terminator Jmp(b7) + terminator Jmp(b11) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=2 diff --git a/tests/snapshots/ssa/struct_2d_array_field.ssa b/tests/snapshots/ssa/struct_2d_array_field.ssa index 2dfedb09d..79f7a9169 100644 --- a/tests/snapshots/ssa/struct_2d_array_field.ssa +++ b/tests/snapshots/ssa/struct_2d_array_field.ssa @@ -6,104 +6,205 @@ fn ent_pc=5 n_params=0 variadic=false locals=10 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b4) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=3 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v9 Imm(0) -> x2 + v10 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v16 Imm(0) -> x2 + v17 Imm(1) -> x2 + v18 LocalAddr(-6) -> x2 + v19 Extend { value=v3, kind=I32 } -> x6 + v20 BinopI { op=shl, lhs=v4, rhs_imm=4 } -> x6 + v21 Binop { op=add, lhs=v18, rhs=v20 } -> x2 + v22 Imm(0) -> x6 + v23 Imm(0) -> x6 + v24 BinopI { op=add, lhs=v21, rhs_imm=0 } -> x2 + v25 BinopI { op=mul, lhs=v4, rhs_imm=10 } -> x6 + v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x7 + v27 Extend { value=v25, kind=I32 } -> x7 + v28 BinopI { op=add, lhs=v25, rhs_imm=0 } -> x6 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x7 + v30 Extend { value=v28, kind=I32 } -> x7 + v31 Store { addr=v24, disp=0, value=v28, kind=I32 } -> - + v32 Imm(0) -> x2 + v33 Imm(1) -> x2 + v34 Imm(0) -> x2 + v35 Imm(1) -> x2 + v36 Imm(1) -> x2 + v37 LocalAddr(-6) -> x2 + v38 Extend { value=v3, kind=I32 } -> x6 + v39 BinopI { op=shl, lhs=v4, rhs_imm=4 } -> x6 + v40 Binop { op=add, lhs=v37, rhs=v39 } -> x2 + v41 Imm(1) -> x6 + v42 Imm(4) -> x6 + v43 BinopI { op=add, lhs=v40, rhs_imm=4 } -> x6 + v44 BinopI { op=mul, lhs=v4, rhs_imm=10 } -> x6 + v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x7 + v46 Extend { value=v44, kind=I32 } -> x7 + v47 BinopI { op=add, lhs=v44, rhs_imm=1 } -> x6 + v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x7 + v49 Extend { value=v47, kind=I32 } -> x7 + v50 Store { addr=v40, disp=4, value=v47, kind=I32 } -> - + v51 Imm(1) -> x2 + v52 Imm(2) -> x2 + v53 Imm(0) -> x2 + v54 Imm(2) -> x2 + v55 Imm(1) -> x2 + v56 LocalAddr(-6) -> x2 + v57 Extend { value=v3, kind=I32 } -> x6 + v58 BinopI { op=shl, lhs=v4, rhs_imm=4 } -> x6 + v59 Binop { op=add, lhs=v56, rhs=v58 } -> x2 + v60 Imm(2) -> x6 + v61 Imm(8) -> x6 + v62 BinopI { op=add, lhs=v59, rhs_imm=8 } -> x6 + v63 BinopI { op=mul, lhs=v4, rhs_imm=10 } -> x6 + v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x7 + v65 Extend { value=v63, kind=I32 } -> x7 + v66 BinopI { op=add, lhs=v63, rhs_imm=2 } -> x6 + v67 BinopI { op=shl, lhs=v66, rhs_imm=32 } -> x7 + v68 Extend { value=v66, kind=I32 } -> x7 + v69 Store { addr=v59, disp=8, value=v66, kind=I32 } -> - + v70 Imm(2) -> x2 + v71 Imm(3) -> x2 + v72 Imm(0) -> x2 + v73 Imm(3) -> x2 + v74 Imm(1) -> x2 + v75 LocalAddr(-6) -> x2 + v76 Extend { value=v3, kind=I32 } -> x6 + v77 BinopI { op=shl, lhs=v4, rhs_imm=4 } -> x6 + v78 Binop { op=add, lhs=v75, rhs=v77 } -> x2 + v79 Imm(3) -> x6 + v80 Imm(12) -> x6 + v81 BinopI { op=add, lhs=v78, rhs_imm=12 } -> x6 + v82 BinopI { op=mul, lhs=v4, rhs_imm=10 } -> x6 + v83 BinopI { op=shl, lhs=v82, rhs_imm=32 } -> x7 + v84 Extend { value=v82, kind=I32 } -> x7 + v85 BinopI { op=add, lhs=v82, rhs_imm=3 } -> x6 + v86 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x7 + v87 Extend { value=v85, kind=I32 } -> x7 + v88 Store { addr=v78, disp=12, value=v85, kind=I32 } -> - + v89 Imm(3) -> x2 + v90 Imm(4) -> x2 + v91 Imm(0) -> x2 + v92 Imm(4) -> x2 + v93 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v93) block 3 start_pc=0 - v9 Imm(0) -> x2 - v10 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v9) + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 + v3 Phi { incoming=[b0:v1, b3:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=3 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b5 } (exit_acc=v5) + block 5 start_pc=0 v11 LocalAddr(-6) -> x0 v12 Imm(0) -> x1 v13 Imm(0) -> x2 v14 Imm(0) -> x1 v15 Imm(0) -> x1 terminator Jmp(b9) (exit_acc=v13) - block 5 start_pc=0 - v16 Phi { incoming=[b3:v9, b6:v20], kind=I64 } -> x2 - v17 Extend { value=v16, kind=I32 } -> x0 - v18 BinopI { op=lt, lhs=v17, rhs_imm=4 } -> x0 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) block 6 start_pc=0 - v19 Extend { value=v16, kind=I32 } -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x2 - v21 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v20) + v101 Imm(0) -> x7 + v102 Imm(0) -> x8 + terminator Jmp(b7) (exit_acc=v101) block 7 start_pc=0 - v22 LocalAddr(-6) -> x0 - v23 Extend { value=v3, kind=I32 } -> x6 - v24 BinopI { op=shl, lhs=v23, rhs_imm=4 } -> x7 - v25 Binop { op=add, lhs=v22, rhs=v24 } -> x0 - v26 Extend { value=v16, kind=I32 } -> x7 - v27 BinopI { op=shl, lhs=v26, rhs_imm=2 } -> x8 - v28 Binop { op=add, lhs=v25, rhs=v27 } -> x8 - v29 BinopI { op=mul, lhs=v23, rhs_imm=10 } -> x6 - v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x8 - v31 Extend { value=v29, kind=I32 } -> x8 - v32 Binop { op=add, lhs=v29, rhs=v26 } -> x6 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x8 - v34 Extend { value=v32, kind=I32 } -> x8 - v35 StoreIndexed { base=v25, index=v26, scale=4, value=v32, kind=I32 } -> - - terminator Jmp(b6) (exit_acc=v35) + v107 Imm(0) -> x7 + v108 Imm(1) -> x7 + v109 Extend { value=v94, kind=I32 } -> x7 + v110 LoadLocal { off=-9, kind=I64 } -> x7 + v111 Extend { value=v95, kind=I32 } -> x7 + v112 BinopI { op=shl, lhs=v96, rhs_imm=4 } -> x7 + v113 Binop { op=add, lhs=v11, rhs=v112 } -> x7 + v114 Imm(0) -> x8 + v115 Imm(0) -> x8 + v116 BinopI { op=add, lhs=v113, rhs_imm=0 } -> x7 + v117 Load { addr=v116, disp=0, kind=I32 } -> x7 + v118 Binop { op=add, lhs=v94, rhs=v117 } -> x2 + v119 Imm(0) -> x7 + v120 Extend { value=v118, kind=I32 } -> x7 + v121 Imm(0) -> x7 + v122 Imm(1) -> x7 + v123 Imm(0) -> x7 + v124 Imm(1) -> x7 + v125 Imm(1) -> x7 + v126 Extend { value=v118, kind=I32 } -> x7 + v127 LoadLocal { off=-9, kind=I64 } -> x7 + v128 Extend { value=v95, kind=I32 } -> x7 + v129 BinopI { op=shl, lhs=v96, rhs_imm=4 } -> x7 + v130 Binop { op=add, lhs=v11, rhs=v129 } -> x7 + v131 Imm(1) -> x8 + v132 Imm(4) -> x8 + v133 BinopI { op=add, lhs=v130, rhs_imm=4 } -> x8 + v134 Load { addr=v130, disp=4, kind=I32 } -> x7 + v135 Binop { op=add, lhs=v118, rhs=v134 } -> x2 + v136 Imm(0) -> x7 + v137 Extend { value=v135, kind=I32 } -> x7 + v138 Imm(1) -> x7 + v139 Imm(2) -> x7 + v140 Imm(0) -> x7 + v141 Imm(2) -> x7 + v142 Imm(1) -> x7 + v143 Extend { value=v135, kind=I32 } -> x7 + v144 LoadLocal { off=-9, kind=I64 } -> x7 + v145 Extend { value=v95, kind=I32 } -> x7 + v146 BinopI { op=shl, lhs=v96, rhs_imm=4 } -> x7 + v147 Binop { op=add, lhs=v11, rhs=v146 } -> x7 + v148 Imm(2) -> x8 + v149 Imm(8) -> x8 + v150 BinopI { op=add, lhs=v147, rhs_imm=8 } -> x8 + v151 Load { addr=v147, disp=8, kind=I32 } -> x7 + v152 Binop { op=add, lhs=v135, rhs=v151 } -> x2 + v153 Imm(0) -> x7 + v154 Extend { value=v152, kind=I32 } -> x7 + v155 Imm(2) -> x7 + v156 Imm(3) -> x7 + v157 Imm(0) -> x7 + v158 Imm(3) -> x7 + v159 Imm(1) -> x7 + v160 Extend { value=v152, kind=I32 } -> x7 + v161 LoadLocal { off=-9, kind=I64 } -> x7 + v162 Extend { value=v95, kind=I32 } -> x7 + v163 BinopI { op=shl, lhs=v96, rhs_imm=4 } -> x7 + v164 Binop { op=add, lhs=v11, rhs=v163 } -> x7 + v165 Imm(3) -> x8 + v166 Imm(12) -> x8 + v167 BinopI { op=add, lhs=v164, rhs_imm=12 } -> x8 + v168 Load { addr=v164, disp=12, kind=I32 } -> x7 + v169 Binop { op=add, lhs=v152, rhs=v168 } -> x2 + v170 Imm(0) -> x7 + v171 Extend { value=v169, kind=I32 } -> x7 + v172 Imm(3) -> x7 + v173 Imm(4) -> x7 + v174 Imm(0) -> x7 + v175 Imm(4) -> x7 + v176 Imm(0) -> x7 + terminator Jmp(b8) (exit_acc=v176) block 8 start_pc=0 - terminator Jmp(b2) + v98 Extend { value=v95, kind=I32 } -> x1 + v99 BinopI { op=add, lhs=v96, rhs_imm=1 } -> x1 + v100 Imm(0) -> x6 + terminator Jmp(b9) (exit_acc=v99) block 9 start_pc=0 - v36 Phi { incoming=[b4:v13, b10:v49], kind=I64 } -> x2 - v37 Phi { incoming=[b4:v13, b10:v41], kind=I64 } -> x1 - v38 Extend { value=v37, kind=I32 } -> x6 - v39 BinopI { op=lt, lhs=v38, rhs_imm=3 } -> x6 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) + v94 Phi { incoming=[b5:v13, b8:v169], kind=I64 } -> x2 + v95 Phi { incoming=[b5:v13, b8:v99], kind=I64 } -> x1 + v96 Extend { value=v95, kind=I32 } -> x6 + v97 BinopI { op=lt, lhs=v96, rhs_imm=3 } -> x7 + terminator Bnz { cond=v97, target=b6, fall=b10 } (exit_acc=v97) block 10 start_pc=0 - v40 Extend { value=v37, kind=I32 } -> x1 - v41 BinopI { op=add, lhs=v40, rhs_imm=1 } -> x1 - v42 Imm(0) -> x6 - terminator Jmp(b9) (exit_acc=v41) + v103 Extend { value=v94, kind=I32 } -> x0 + v104 BinopI { op=sub, lhs=v94, rhs_imm=111 } -> x0 + v105 BinopI { op=shl, lhs=v104, rhs_imm=32 } -> x1 + v106 Extend { value=v104, kind=I32 } -> x0 + terminator Return(v106) (exit_acc=v106) block 11 start_pc=0 - v43 Imm(0) -> x7 - v44 Imm(0) -> x6 - terminator Jmp(b13) (exit_acc=v43) + terminator Jmp(b3) block 12 start_pc=0 - v45 Extend { value=v36, kind=I32 } -> x0 - v46 BinopI { op=sub, lhs=v36, rhs_imm=111 } -> x0 - v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x1 - v48 Extend { value=v46, kind=I32 } -> x0 - terminator Return(v48) (exit_acc=v48) - block 13 start_pc=0 - v49 Phi { incoming=[b11:v36, b14:v65], kind=I64 } -> x2 - v50 Phi { incoming=[b11:v43, b14:v54], kind=I64 } -> x7 - v51 Extend { value=v50, kind=I32 } -> x6 - v52 BinopI { op=lt, lhs=v51, rhs_imm=4 } -> x6 - terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) - block 14 start_pc=0 - v53 Extend { value=v50, kind=I32 } -> x6 - v54 BinopI { op=add, lhs=v53, rhs_imm=1 } -> x7 - v55 Imm(0) -> x6 - terminator Jmp(b13) (exit_acc=v54) - block 15 start_pc=0 - v56 Extend { value=v49, kind=I32 } -> x6 - v57 LoadLocal { off=-9, kind=I64 } -> x6 - v58 Extend { value=v37, kind=I32 } -> x6 - v59 BinopI { op=shl, lhs=v58, rhs_imm=4 } -> x6 - v60 Binop { op=add, lhs=v11, rhs=v59 } -> x6 - v61 Extend { value=v50, kind=I32 } -> x8 - v62 BinopI { op=shl, lhs=v61, rhs_imm=2 } -> x9 - v63 Binop { op=add, lhs=v60, rhs=v62 } -> x9 - v64 LoadIndexed { base=v60, index=v61, scale=4, kind=I32 } -> x6 - v65 Binop { op=add, lhs=v49, rhs=v64 } -> x2 - v66 Imm(0) -> x6 - v67 Extend { value=v65, kind=I32 } -> x6 - terminator Jmp(b14) (exit_acc=v67) - block 16 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_arg_by_stack.ssa b/tests/snapshots/ssa/struct_arg_by_stack.ssa index 65bae0db0..b738e016e 100644 --- a/tests/snapshots/ssa/struct_arg_by_stack.ssa +++ b/tests/snapshots/ssa/struct_arg_by_stack.ssa @@ -72,7 +72,7 @@ fn ent_pc=1 n_params=1 variadic=false locals=4 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=14 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-4) -> x0 @@ -112,42 +112,42 @@ fn ent_pc=2 n_params=0 variadic=false locals=14 v31 ImmData(32) -> x0 v32 Load { addr=v31, disp=0, kind=I64 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=11 } -> x0 - v34 Imm(1) -> x3 + v34 Imm(1) -> x2 v35 Imm(0) -> x1 - terminator Bnz { cond=v33, target=b21, fall=b3 } (exit_acc=v33) + terminator Bnz { cond=v33, target=b25, fall=b3 } (exit_acc=v33) block 3 start_pc=0 v36 ImmData(40) -> x0 v37 Load { addr=v36, disp=0, kind=I64 } -> x0 v38 BinopI { op=ne, lhs=v37, rhs_imm=22 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x3 + v39 BinopI { op=ne, lhs=v38, rhs_imm=0 } -> x2 v40 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v39) block 4 start_pc=0 - v41 Phi { incoming=[b21:v34, b3:v39], kind=I64 } -> x3 + v41 Phi { incoming=[b25:v34, b3:v39], kind=I64 } -> x2 v42 LoadLocal { off=-12, kind=I64 } -> x0 - v43 Imm(1) -> x12 + v43 Imm(1) -> x1 v44 Imm(0) -> x0 - terminator Bnz { cond=v41, target=b22, fall=b5 } (exit_acc=v41) + terminator Bnz { cond=v41, target=b24, fall=b5 } (exit_acc=v41) block 5 start_pc=0 v45 ImmData(48) -> x0 v46 Load { addr=v45, disp=0, kind=I64 } -> x0 v47 BinopI { op=ne, lhs=v46, rhs_imm=33 } -> x0 - v48 BinopI { op=ne, lhs=v47, rhs_imm=0 } -> x12 + v48 BinopI { op=ne, lhs=v47, rhs_imm=0 } -> x1 v49 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v48) block 6 start_pc=0 - v50 Phi { incoming=[b22:v43, b5:v48], kind=I64 } -> x12 + v50 Phi { incoming=[b24:v43, b5:v48], kind=I64 } -> x1 v51 LoadLocal { off=-11, kind=I64 } -> x0 v52 Imm(0) -> x0 terminator Bnz { cond=v50, target=b23, fall=b7 } (exit_acc=v50) block 7 start_pc=0 v53 ImmData(56) -> x0 v54 Load { addr=v53, disp=0, kind=I64 } -> x0 - v55 BinopI { op=ne, lhs=v54, rhs_imm=44 } -> x12 + v55 BinopI { op=ne, lhs=v54, rhs_imm=44 } -> x1 v56 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v55) block 8 start_pc=0 - v57 Phi { incoming=[b23:v50, b7:v55], kind=I64 } -> x12 + v57 Phi { incoming=[b23:v50, b7:v55], kind=I64 } -> x1 v58 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v57, target=b10, fall=b9 } (exit_acc=v57) block 9 start_pc=0 @@ -156,17 +156,17 @@ fn ent_pc=2 n_params=0 variadic=false locals=14 block 10 start_pc=0 v60 ImmData(64) -> x0 v61 Load { addr=v60, disp=0, kind=I64 } -> x0 - v62 BinopI { op=ne, lhs=v61, rhs_imm=5 } -> x3 + v62 BinopI { op=ne, lhs=v61, rhs_imm=5 } -> x1 v63 Imm(0) -> x0 - terminator Bnz { cond=v62, target=b24, fall=b11 } (exit_acc=v62) + terminator Bnz { cond=v62, target=b22, fall=b11 } (exit_acc=v62) block 11 start_pc=0 v64 ImmData(72) -> x0 v65 Load { addr=v64, disp=0, kind=I64 } -> x0 - v66 BinopI { op=ne, lhs=v65, rhs_imm=6 } -> x3 + v66 BinopI { op=ne, lhs=v65, rhs_imm=6 } -> x1 v67 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v66) block 12 start_pc=0 - v68 Phi { incoming=[b24:v62, b11:v66], kind=I64 } -> x3 + v68 Phi { incoming=[b22:v62, b11:v66], kind=I64 } -> x1 v69 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v68, target=b14, fall=b13 } (exit_acc=v68) block 13 start_pc=0 @@ -197,7 +197,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=14 v88 Load { addr=v87, disp=0, kind=I64 } -> x0 v89 BinopI { op=ne, lhs=v88, rhs_imm=11 } -> x1 v90 Imm(0) -> x0 - terminator Bnz { cond=v89, target=b25, fall=b17 } (exit_acc=v89) + terminator Bnz { cond=v89, target=b21, fall=b17 } (exit_acc=v89) block 17 start_pc=0 v91 LocalAddr(-4) -> x0 v92 BinopI { op=add, lhs=v91, rhs_imm=24 } -> x1 @@ -206,7 +206,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=14 v95 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v94) block 18 start_pc=0 - v96 Phi { incoming=[b25:v89, b17:v94], kind=I64 } -> x1 + v96 Phi { incoming=[b21:v89, b17:v94], kind=I64 } -> x1 v97 LoadLocal { off=-14, kind=I64 } -> x0 terminator Bz { cond=v96, target=b20, fall=b19 } (exit_acc=v96) block 19 start_pc=0 @@ -216,15 +216,15 @@ fn ent_pc=2 n_params=0 variadic=false locals=14 v99 Imm(0) -> x0 terminator Return(v99) (exit_acc=v99) block 21 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b12) block 23 start_pc=0 terminator Jmp(b8) block 24 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b6) block 25 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_arg_in_registers.ssa b/tests/snapshots/ssa/struct_arg_in_registers.ssa index f4078997a..295fddf39 100644 --- a/tests/snapshots/ssa/struct_arg_in_registers.ssa +++ b/tests/snapshots/ssa/struct_arg_in_registers.ssa @@ -281,31 +281,31 @@ fn ent_pc=7 n_params=0 variadic=false locals=11 terminator Return(v91) (exit_acc=v91) block 8 start_pc=0 v92 Imm(9) -> x0 - v93 LocalAddr(-1) -> x1 - v94 Imm(2) -> x2 - v95 Extend { value=v92, kind=I32 } -> x6 - v96 Imm(0) -> x6 - v97 Extend { value=v94, kind=I32 } -> x6 - v98 Imm(0) -> x6 - v99 Load { addr=v93, disp=0, kind=I32 } -> x6 - v100 BinopI { op=mul, lhs=v99, rhs_imm=10 } -> x6 - v101 BinopI { op=shl, lhs=v100, rhs_imm=32 } -> x7 - v102 Extend { value=v100, kind=I32 } -> x7 - v103 Binop { op=add, lhs=v92, rhs=v100 } -> x0 - v104 BinopI { op=shl, lhs=v103, rhs_imm=32 } -> x6 - v105 Extend { value=v103, kind=I32 } -> x6 - v106 BinopI { op=add, lhs=v93, rhs_imm=4 } -> x6 - v107 Load { addr=v93, disp=4, kind=I32 } -> x1 - v108 BinopI { op=mul, lhs=v107, rhs_imm=100 } -> x1 - v109 BinopI { op=shl, lhs=v108, rhs_imm=32 } -> x6 - v110 Extend { value=v108, kind=I32 } -> x6 + v93 LocalAddr(-1) -> x0 + v94 Imm(2) -> x1 + v95 Imm(9) -> x1 + v96 Imm(0) -> x1 + v97 Imm(2) -> x1 + v98 Imm(0) -> x1 + v99 Load { addr=v93, disp=0, kind=I32 } -> x1 + v100 BinopI { op=mul, lhs=v99, rhs_imm=10 } -> x1 + v101 BinopI { op=shl, lhs=v100, rhs_imm=32 } -> x2 + v102 Extend { value=v100, kind=I32 } -> x2 + v103 BinopI { op=add, lhs=v100, rhs_imm=9 } -> x1 + v104 BinopI { op=shl, lhs=v103, rhs_imm=32 } -> x2 + v105 Extend { value=v103, kind=I32 } -> x2 + v106 BinopI { op=add, lhs=v93, rhs_imm=4 } -> x2 + v107 Load { addr=v93, disp=4, kind=I32 } -> x0 + v108 BinopI { op=mul, lhs=v107, rhs_imm=100 } -> x0 + v109 BinopI { op=shl, lhs=v108, rhs_imm=32 } -> x2 + v110 Extend { value=v108, kind=I32 } -> x2 v111 Binop { op=add, lhs=v103, rhs=v108 } -> x0 v112 BinopI { op=shl, lhs=v111, rhs_imm=32 } -> x1 v113 Extend { value=v111, kind=I32 } -> x1 - v114 BinopI { op=mul, lhs=v94, rhs_imm=1000 } -> x1 - v115 BinopI { op=shl, lhs=v114, rhs_imm=32 } -> x2 - v116 Extend { value=v114, kind=I32 } -> x2 - v117 Binop { op=add, lhs=v111, rhs=v114 } -> x0 + v114 Imm(2000) -> x1 + v115 Imm(8589934592000) -> x1 + v116 Imm(2000) -> x1 + v117 BinopI { op=add, lhs=v111, rhs_imm=2000 } -> x0 v118 BinopI { op=shl, lhs=v117, rhs_imm=32 } -> x1 v119 Extend { value=v117, kind=I32 } -> x0 v120 Imm(39) -> x1 diff --git a/tests/snapshots/ssa/struct_arg_indirect_subscript.ssa b/tests/snapshots/ssa/struct_arg_indirect_subscript.ssa index bb5e9c2a3..cc77314f5 100644 --- a/tests/snapshots/ssa/struct_arg_indirect_subscript.ssa +++ b/tests/snapshots/ssa/struct_arg_indirect_subscript.ssa @@ -21,34 +21,34 @@ fn ent_pc=0 n_params=4 variadic=false locals=4 v15 LoadLocal { off=5, kind=I32 } -> x6 v16 Binop { op=add, lhs=v14, rhs=v5 } -> x0 v17 LoadLocal { off=2, kind=I64 } -> x1 - terminator Bz { cond=v1, target=b2, fall=b1 } (exit_acc=v1) + terminator Bz { cond=v1, target=b6, fall=b1 } (exit_acc=v1) block 1 start_pc=0 v18 Imm(0) -> x6 v19 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v18) + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v20 Imm(0) -> x6 - v21 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v20) - block 3 start_pc=0 - v22 Phi { incoming=[b1:v18, b2:v20], kind=I64 } -> x6 + v22 Phi { incoming=[b1:v18, b6:v20], kind=I64 } -> x6 v23 LoadLocal { off=-3, kind=I64 } -> x1 v24 Binop { op=add, lhs=v16, rhs=v22 } -> x0 v25 LoadLocal { off=4, kind=I64 } -> x1 - terminator Bz { cond=v3, target=b5, fall=b4 } (exit_acc=v3) - block 4 start_pc=0 + terminator Bz { cond=v3, target=b5, fall=b3 } (exit_acc=v3) + block 3 start_pc=0 v26 Imm(1) -> x2 v27 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v26) + terminator Jmp(b4) (exit_acc=v26) + block 4 start_pc=0 + v30 Phi { incoming=[b3:v26, b5:v28], kind=I64 } -> x2 + v31 LoadLocal { off=-4, kind=I64 } -> x1 + v32 Binop { op=add, lhs=v24, rhs=v30 } -> x0 + terminator Return(v32) (exit_acc=v32) block 5 start_pc=0 v28 Imm(0) -> x2 v29 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v28) + terminator Jmp(b4) (exit_acc=v28) block 6 start_pc=0 - v30 Phi { incoming=[b4:v26, b5:v28], kind=I64 } -> x2 - v31 LoadLocal { off=-4, kind=I64 } -> x1 - v32 Binop { op=add, lhs=v24, rhs=v30 } -> x0 - terminator Return(v32) (exit_acc=v32) + v20 Imm(0) -> x6 + v21 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=take_vec fn ent_pc=1 n_params=2 variadic=false locals=2 @@ -162,85 +162,229 @@ fn ent_pc=5 n_params=0 variadic=false locals=25 v21 Imm(0) -> x0 terminator Jmp(b5) (exit_acc=v19) block 5 start_pc=0 - v22 Phi { incoming=[b4:v19, b6:v26], kind=I64 } -> x1 - v23 Extend { value=v22, kind=I32 } -> x0 - v24 BinopI { op=lt, lhs=v23, rhs_imm=8 } -> x0 - terminator Bz { cond=v24, target=b8, fall=b7 } (exit_acc=v24) + v22 Imm(0) -> x0 + v23 Imm(1) -> x0 + v24 LocalAddr(-19) -> x0 + v25 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x0 + v26 Imm(0) -> x1 + v27 Imm(0) -> x1 + v28 BinopI { op=add, lhs=v25, rhs_imm=0 } -> x0 + v29 Imm(1) -> x1 + v30 Imm(4294967296) -> x1 + v31 Imm(1) -> x1 + v32 Store { addr=v28, disp=0, value=v31, kind=I64 } -> - + v33 LocalAddr(-19) -> x0 + v34 BinopI { op=add, lhs=v33, rhs_imm=8 } -> x0 + v35 Imm(0) -> x1 + v36 Imm(0) -> x2 + v37 BinopI { op=add, lhs=v34, rhs_imm=0 } -> x0 + v38 BinopI { op=add, lhs=v37, rhs_imm=8 } -> x2 + v39 Store { addr=v37, disp=8, value=v35, kind=I64 } -> - + v40 Imm(0) -> x0 + v41 Imm(1) -> x0 + v42 Imm(0) -> x0 + v43 Imm(1) -> x0 + v44 Imm(1) -> x0 + v45 LocalAddr(-19) -> x0 + v46 BinopI { op=add, lhs=v45, rhs_imm=8 } -> x0 + v47 Imm(1) -> x1 + v48 Imm(16) -> x1 + v49 BinopI { op=add, lhs=v46, rhs_imm=16 } -> x1 + v50 Imm(2) -> x1 + v51 Imm(8589934592) -> x1 + v52 Imm(2) -> x1 + v53 Store { addr=v46, disp=16, value=v52, kind=I64 } -> - + v54 LocalAddr(-19) -> x0 + v55 BinopI { op=add, lhs=v54, rhs_imm=8 } -> x0 + v56 Imm(1) -> x1 + v57 Imm(16) -> x2 + v58 BinopI { op=add, lhs=v55, rhs_imm=16 } -> x0 + v59 BinopI { op=add, lhs=v58, rhs_imm=8 } -> x2 + v60 Store { addr=v58, disp=8, value=v56, kind=I64 } -> - + v61 Imm(1) -> x0 + v62 Imm(2) -> x0 + v63 Imm(0) -> x0 + v64 Imm(2) -> x0 + v65 Imm(1) -> x0 + v66 LocalAddr(-19) -> x0 + v67 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x0 + v68 Imm(2) -> x1 + v69 Imm(32) -> x1 + v70 BinopI { op=add, lhs=v67, rhs_imm=32 } -> x1 + v71 Imm(3) -> x1 + v72 Imm(12884901888) -> x1 + v73 Imm(3) -> x1 + v74 Store { addr=v67, disp=32, value=v73, kind=I64 } -> - + v75 LocalAddr(-19) -> x0 + v76 BinopI { op=add, lhs=v75, rhs_imm=8 } -> x0 + v77 Imm(2) -> x1 + v78 Imm(32) -> x2 + v79 BinopI { op=add, lhs=v76, rhs_imm=32 } -> x0 + v80 BinopI { op=add, lhs=v79, rhs_imm=8 } -> x2 + v81 Store { addr=v79, disp=8, value=v77, kind=I64 } -> - + v82 Imm(2) -> x0 + v83 Imm(3) -> x0 + v84 Imm(0) -> x0 + v85 Imm(3) -> x0 + v86 Imm(1) -> x0 + v87 LocalAddr(-19) -> x0 + v88 BinopI { op=add, lhs=v87, rhs_imm=8 } -> x0 + v89 Imm(3) -> x1 + v90 Imm(48) -> x1 + v91 BinopI { op=add, lhs=v88, rhs_imm=48 } -> x1 + v92 Imm(4) -> x1 + v93 Imm(17179869184) -> x1 + v94 Imm(4) -> x1 + v95 Store { addr=v88, disp=48, value=v94, kind=I64 } -> - + v96 LocalAddr(-19) -> x0 + v97 BinopI { op=add, lhs=v96, rhs_imm=8 } -> x0 + v98 Imm(3) -> x1 + v99 Imm(48) -> x2 + v100 BinopI { op=add, lhs=v97, rhs_imm=48 } -> x0 + v101 BinopI { op=add, lhs=v100, rhs_imm=8 } -> x2 + v102 Store { addr=v100, disp=8, value=v98, kind=I64 } -> - + v103 Imm(3) -> x0 + v104 Imm(4) -> x0 + v105 Imm(0) -> x0 + v106 Imm(4) -> x0 + v107 Imm(1) -> x0 + v108 LocalAddr(-19) -> x0 + v109 BinopI { op=add, lhs=v108, rhs_imm=8 } -> x0 + v110 Imm(4) -> x1 + v111 Imm(64) -> x1 + v112 BinopI { op=add, lhs=v109, rhs_imm=64 } -> x1 + v113 Imm(5) -> x1 + v114 Imm(21474836480) -> x1 + v115 Imm(5) -> x1 + v116 Store { addr=v109, disp=64, value=v115, kind=I64 } -> - + v117 LocalAddr(-19) -> x0 + v118 BinopI { op=add, lhs=v117, rhs_imm=8 } -> x0 + v119 Imm(4) -> x1 + v120 Imm(64) -> x2 + v121 BinopI { op=add, lhs=v118, rhs_imm=64 } -> x0 + v122 BinopI { op=add, lhs=v121, rhs_imm=8 } -> x2 + v123 Store { addr=v121, disp=8, value=v119, kind=I64 } -> - + v124 Imm(4) -> x0 + v125 Imm(5) -> x0 + v126 Imm(0) -> x0 + v127 Imm(5) -> x0 + v128 Imm(1) -> x0 + v129 LocalAddr(-19) -> x0 + v130 BinopI { op=add, lhs=v129, rhs_imm=8 } -> x0 + v131 Imm(5) -> x1 + v132 Imm(80) -> x1 + v133 BinopI { op=add, lhs=v130, rhs_imm=80 } -> x1 + v134 Imm(6) -> x1 + v135 Imm(25769803776) -> x1 + v136 Imm(6) -> x1 + v137 Store { addr=v130, disp=80, value=v136, kind=I64 } -> - + v138 LocalAddr(-19) -> x0 + v139 BinopI { op=add, lhs=v138, rhs_imm=8 } -> x0 + v140 Imm(5) -> x1 + v141 Imm(80) -> x2 + v142 BinopI { op=add, lhs=v139, rhs_imm=80 } -> x0 + v143 BinopI { op=add, lhs=v142, rhs_imm=8 } -> x2 + v144 Store { addr=v142, disp=8, value=v140, kind=I64 } -> - + v145 Imm(5) -> x0 + v146 Imm(6) -> x0 + v147 Imm(0) -> x0 + v148 Imm(6) -> x0 + v149 Imm(1) -> x0 + v150 LocalAddr(-19) -> x0 + v151 BinopI { op=add, lhs=v150, rhs_imm=8 } -> x0 + v152 Imm(6) -> x1 + v153 Imm(96) -> x1 + v154 BinopI { op=add, lhs=v151, rhs_imm=96 } -> x1 + v155 Imm(7) -> x1 + v156 Imm(30064771072) -> x1 + v157 Imm(7) -> x1 + v158 Store { addr=v151, disp=96, value=v157, kind=I64 } -> - + v159 LocalAddr(-19) -> x0 + v160 BinopI { op=add, lhs=v159, rhs_imm=8 } -> x0 + v161 Imm(6) -> x1 + v162 Imm(96) -> x2 + v163 BinopI { op=add, lhs=v160, rhs_imm=96 } -> x0 + v164 BinopI { op=add, lhs=v163, rhs_imm=8 } -> x2 + v165 Store { addr=v163, disp=8, value=v161, kind=I64 } -> - + v166 Imm(6) -> x0 + v167 Imm(7) -> x0 + v168 Imm(0) -> x0 + v169 Imm(7) -> x0 + v170 Imm(1) -> x0 + v171 LocalAddr(-19) -> x0 + v172 BinopI { op=add, lhs=v171, rhs_imm=8 } -> x0 + v173 Imm(7) -> x1 + v174 Imm(112) -> x1 + v175 BinopI { op=add, lhs=v172, rhs_imm=112 } -> x1 + v176 Imm(8) -> x1 + v177 Imm(34359738368) -> x1 + v178 Imm(8) -> x1 + v179 Store { addr=v172, disp=112, value=v178, kind=I64 } -> - + v180 LocalAddr(-19) -> x0 + v181 BinopI { op=add, lhs=v180, rhs_imm=8 } -> x0 + v182 Imm(7) -> x1 + v183 Imm(112) -> x2 + v184 BinopI { op=add, lhs=v181, rhs_imm=112 } -> x0 + v185 BinopI { op=add, lhs=v184, rhs_imm=8 } -> x2 + v186 Store { addr=v184, disp=8, value=v182, kind=I64 } -> - + v187 Imm(7) -> x0 + v188 Imm(8) -> x0 + v189 Imm(0) -> x0 + v190 Imm(8) -> x0 + v191 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v191) block 6 start_pc=0 - v25 Extend { value=v22, kind=I32 } -> x0 - v26 BinopI { op=add, lhs=v25, rhs_imm=1 } -> x1 - v27 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v26) + v192 LocalAddr(-19) -> x7 + v193 Imm(3) -> x6 + v194 Call { target_pc=4, args=[v192, v193], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v195 BinopI { op=ne, lhs=v194, rhs_imm=4034 } -> x0 + terminator Bz { cond=v195, target=b8, fall=b7 } (exit_acc=v195) block 7 start_pc=0 - v28 LocalAddr(-19) -> x0 - v29 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x0 - v30 Extend { value=v22, kind=I32 } -> x2 - v31 BinopI { op=shl, lhs=v30, rhs_imm=4 } -> x6 - v32 Binop { op=add, lhs=v29, rhs=v31 } -> x0 - v33 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x2 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x6 - v35 Extend { value=v33, kind=I32 } -> x2 - v36 Store { addr=v32, disp=0, value=v35, kind=I64 } -> - - v37 LocalAddr(-19) -> x0 - v38 BinopI { op=add, lhs=v37, rhs_imm=8 } -> x0 - v39 Extend { value=v22, kind=I32 } -> x2 - v40 BinopI { op=shl, lhs=v39, rhs_imm=4 } -> x6 - v41 Binop { op=add, lhs=v38, rhs=v40 } -> x0 - v42 BinopI { op=add, lhs=v41, rhs_imm=8 } -> x6 - v43 Store { addr=v41, disp=8, value=v39, kind=I64 } -> - - terminator Jmp(b6) (exit_acc=v43) + v196 Imm(3) -> x0 + terminator Return(v196) (exit_acc=v196) block 8 start_pc=0 - v44 LocalAddr(-19) -> x7 - v45 Imm(3) -> x6 - v46 Call { target_pc=4, args=[v44, v45], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v47 BinopI { op=ne, lhs=v46, rhs_imm=4034 } -> x0 - terminator Bz { cond=v47, target=b10, fall=b9 } (exit_acc=v47) + v197 LocalAddr(-22) -> x0 + v198 ImmData(32) -> x1 + v199 Mcpy { dst=v197, src=v198, size=16 } -> x0 + v200 LocalAddr(-22) -> x7 + v201 Imm(1) -> x6 + v202 Call { target_pc=1, args=[v200, v201], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 + v203 Imm(4609434218613702656) -> x0 + v204 Imm(4616189618054758400) -> x1 + v205 Binop { op=fmul, lhs=v203, rhs=v204 } -> d1 + v206 Imm(4612248968380809216) -> x2 + v207 Imm(4611686018427387904) -> x6 + v208 Binop { op=fmul, lhs=v206, rhs=v207 } -> d1 + v209 Fma { a=v203, b=v204, c=v208, neg_product=false, neg_addend=false } -> d1 + v210 Imm(4607182418800017408) -> x0 + v211 Binop { op=fadd, lhs=v209, rhs=v210 } -> d1 + v212 Binop { op=fne, lhs=v202, rhs=v211 } -> x0 + terminator Bz { cond=v212, target=b10, fall=b9 } (exit_acc=v212) block 9 start_pc=0 - v48 Imm(3) -> x0 - terminator Return(v48) (exit_acc=v48) + v213 Imm(4) -> x0 + terminator Return(v213) (exit_acc=v213) block 10 start_pc=0 - v49 LocalAddr(-22) -> x0 - v50 ImmData(32) -> x1 - v51 Mcpy { dst=v49, src=v50, size=16 } -> x0 - v52 LocalAddr(-22) -> x7 - v53 Imm(1) -> x6 - v54 Call { target_pc=1, args=[v52, v53], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v55 Imm(4609434218613702656) -> x0 - v56 Imm(4616189618054758400) -> x1 - v57 Binop { op=fmul, lhs=v55, rhs=v56 } -> d1 - v58 Imm(4612248968380809216) -> x2 - v59 Imm(4611686018427387904) -> x6 - v60 Binop { op=fmul, lhs=v58, rhs=v59 } -> d1 - v61 Fma { a=v55, b=v56, c=v60, neg_product=false, neg_addend=false } -> d1 - v62 Imm(4607182418800017408) -> x0 - v63 Binop { op=fadd, lhs=v61, rhs=v62 } -> d1 - v64 Binop { op=fne, lhs=v54, rhs=v63 } -> x0 - terminator Bz { cond=v64, target=b12, fall=b11 } (exit_acc=v64) + v214 ImmCode(ent_pc=1) -> x7 + v215 LocalAddr(-22) -> x6 + v216 Imm(1) -> x2 + v217 Call { target_pc=3, args=[v214, v215, v216], fixed_args=3, fp_return=true, fp_arg_mask=0x0 } -> d0 + v218 Imm(4609434218613702656) -> x0 + v219 Imm(4616189618054758400) -> x1 + v220 Binop { op=fmul, lhs=v218, rhs=v219 } -> d1 + v221 Imm(4612248968380809216) -> x2 + v222 Imm(4611686018427387904) -> x6 + v223 Binop { op=fmul, lhs=v221, rhs=v222 } -> d1 + v224 Fma { a=v218, b=v219, c=v223, neg_product=false, neg_addend=false } -> d1 + v225 Imm(4607182418800017408) -> x0 + v226 Binop { op=fadd, lhs=v224, rhs=v225 } -> d1 + v227 Binop { op=fne, lhs=v217, rhs=v226 } -> x0 + terminator Bz { cond=v227, target=b12, fall=b11 } (exit_acc=v227) block 11 start_pc=0 - v65 Imm(4) -> x0 - terminator Return(v65) (exit_acc=v65) + v228 Imm(5) -> x0 + terminator Return(v228) (exit_acc=v228) block 12 start_pc=0 - v66 ImmCode(ent_pc=1) -> x7 - v67 LocalAddr(-22) -> x6 - v68 Imm(1) -> x2 - v69 Call { target_pc=3, args=[v66, v67, v68], fixed_args=3, fp_return=true, fp_arg_mask=0x0 } -> d0 - v70 Imm(4609434218613702656) -> x0 - v71 Imm(4616189618054758400) -> x1 - v72 Binop { op=fmul, lhs=v70, rhs=v71 } -> d1 - v73 Imm(4612248968380809216) -> x2 - v74 Imm(4611686018427387904) -> x6 - v75 Binop { op=fmul, lhs=v73, rhs=v74 } -> d1 - v76 Fma { a=v70, b=v71, c=v75, neg_product=false, neg_addend=false } -> d1 - v77 Imm(4607182418800017408) -> x0 - v78 Binop { op=fadd, lhs=v76, rhs=v77 } -> d1 - v79 Binop { op=fne, lhs=v69, rhs=v78 } -> x0 - terminator Bz { cond=v79, target=b14, fall=b13 } (exit_acc=v79) - block 13 start_pc=0 - v80 Imm(5) -> x0 - terminator Return(v80) (exit_acc=v80) - block 14 start_pc=0 - v81 Imm(0) -> x0 - terminator Return(v81) (exit_acc=v81) + v229 Imm(0) -> x0 + terminator Return(v229) (exit_acc=v229) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_arg_two_eightbyte.ssa b/tests/snapshots/ssa/struct_arg_two_eightbyte.ssa index 664149b16..778d5370b 100644 --- a/tests/snapshots/ssa/struct_arg_two_eightbyte.ssa +++ b/tests/snapshots/ssa/struct_arg_two_eightbyte.ssa @@ -59,7 +59,7 @@ fn ent_pc=1 n_params=2 variadic=false locals=4 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=12 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 @@ -93,19 +93,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 block 2 start_pc=0 v26 ImmData(24) -> x0 v27 Load { addr=v26, disp=0, kind=I64 } -> x0 - v28 BinopI { op=ne, lhs=v27, rhs_imm=4369 } -> x3 + v28 BinopI { op=ne, lhs=v27, rhs_imm=4369 } -> x1 v29 Imm(0) -> x0 - terminator Bnz { cond=v28, target=b19, fall=b3 } (exit_acc=v28) + terminator Bnz { cond=v28, target=b22, fall=b3 } (exit_acc=v28) block 3 start_pc=0 v30 ImmData(40) -> x0 v31 Load { addr=v30, disp=0, kind=U32 } -> x0 v32 BinopI { op=xor, lhs=v31, rhs_imm=4 } -> x0 v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x0 - v34 BinopI { op=ne, lhs=v33, rhs_imm=0 } -> x3 + v34 BinopI { op=ne, lhs=v33, rhs_imm=0 } -> x1 v35 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v34) block 4 start_pc=0 - v36 Phi { incoming=[b19:v28, b3:v34], kind=I64 } -> x3 + v36 Phi { incoming=[b22:v28, b3:v34], kind=I64 } -> x1 v37 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v36, target=b6, fall=b5 } (exit_acc=v36) block 5 start_pc=0 @@ -114,19 +114,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 block 6 start_pc=0 v39 ImmData(32) -> x0 v40 Load { addr=v39, disp=0, kind=I64 } -> x0 - v41 BinopI { op=ne, lhs=v40, rhs_imm=8738 } -> x3 + v41 BinopI { op=ne, lhs=v40, rhs_imm=8738 } -> x1 v42 Imm(0) -> x0 - terminator Bnz { cond=v41, target=b20, fall=b7 } (exit_acc=v41) + terminator Bnz { cond=v41, target=b21, fall=b7 } (exit_acc=v41) block 7 start_pc=0 v43 ImmData(48) -> x0 v44 Load { addr=v43, disp=0, kind=U32 } -> x0 v45 BinopI { op=xor, lhs=v44, rhs_imm=6 } -> x0 v46 BinopI { op=and, lhs=v45, rhs_imm=4294967295 } -> x0 - v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x3 + v47 BinopI { op=ne, lhs=v46, rhs_imm=0 } -> x1 v48 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v47) block 8 start_pc=0 - v49 Phi { incoming=[b20:v41, b7:v47], kind=I64 } -> x3 + v49 Phi { incoming=[b21:v41, b7:v47], kind=I64 } -> x1 v50 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) block 9 start_pc=0 @@ -140,7 +140,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 v56 Load { addr=v55, disp=0, kind=I64 } -> x0 v57 BinopI { op=ne, lhs=v56, rhs_imm=4369 } -> x1 v58 Imm(0) -> x0 - terminator Bnz { cond=v57, target=b21, fall=b11 } (exit_acc=v57) + terminator Bnz { cond=v57, target=b20, fall=b11 } (exit_acc=v57) block 11 start_pc=0 v59 ImmData(80) -> x0 v60 Load { addr=v59, disp=0, kind=U32 } -> x0 @@ -150,7 +150,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 v64 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v63) block 12 start_pc=0 - v65 Phi { incoming=[b21:v57, b11:v63], kind=I64 } -> x1 + v65 Phi { incoming=[b20:v57, b11:v63], kind=I64 } -> x1 v66 LoadLocal { off=-11, kind=I64 } -> x0 terminator Bz { cond=v65, target=b14, fall=b13 } (exit_acc=v65) block 13 start_pc=0 @@ -161,7 +161,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 v69 Load { addr=v68, disp=0, kind=I64 } -> x0 v70 BinopI { op=ne, lhs=v69, rhs_imm=8738 } -> x1 v71 Imm(0) -> x0 - terminator Bnz { cond=v70, target=b22, fall=b15 } (exit_acc=v70) + terminator Bnz { cond=v70, target=b19, fall=b15 } (exit_acc=v70) block 15 start_pc=0 v72 ImmData(88) -> x0 v73 Load { addr=v72, disp=0, kind=U32 } -> x0 @@ -171,7 +171,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 v77 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v76) block 16 start_pc=0 - v78 Phi { incoming=[b22:v70, b15:v76], kind=I64 } -> x1 + v78 Phi { incoming=[b19:v70, b15:v76], kind=I64 } -> x1 v79 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v78, target=b18, fall=b17 } (exit_acc=v78) block 17 start_pc=0 @@ -181,13 +181,13 @@ fn ent_pc=2 n_params=0 variadic=false locals=12 v81 Imm(0) -> x0 terminator Return(v81) (exit_acc=v81) block 19 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b16) block 20 start_pc=0 - terminator Jmp(b8) - block 21 start_pc=0 terminator Jmp(b12) + block 21 start_pc=0 + terminator Jmp(b8) block 22 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_array_designator.ssa b/tests/snapshots/ssa/struct_array_designator.ssa index 66ebcbf91..68d746081 100644 --- a/tests/snapshots/ssa/struct_array_designator.ssa +++ b/tests/snapshots/ssa/struct_array_designator.ssa @@ -9,7 +9,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v3 Load { addr=v1, disp=0, kind=I32 } -> x1 v4 BinopI { op=ne, lhs=v3, rhs_imm=10 } -> x2 v5 Imm(0) -> x1 - terminator Bnz { cond=v4, target=b13, fall=b1 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b15, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v6 ImmData(8) -> x1 v7 Imm(0) -> x1 @@ -19,7 +19,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v11 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v10) block 2 start_pc=0 - v12 Phi { incoming=[b13:v4, b1:v10], kind=I64 } -> x2 + v12 Phi { incoming=[b15:v4, b1:v10], kind=I64 } -> x2 v13 LoadLocal { off=-1, kind=I64 } -> x1 terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) block 3 start_pc=0 @@ -56,7 +56,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v34 Load { addr=v1, disp=16, kind=I32 } -> x1 v35 BinopI { op=ne, lhs=v34, rhs_imm=30 } -> x2 v36 Imm(0) -> x1 - terminator Bnz { cond=v35, target=b15, fall=b9 } (exit_acc=v35) + terminator Bnz { cond=v35, target=b13, fall=b9 } (exit_acc=v35) block 9 start_pc=0 v37 ImmData(8) -> x1 v38 Imm(16) -> x1 @@ -67,7 +67,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v43 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v42) block 10 start_pc=0 - v44 Phi { incoming=[b15:v35, b9:v42], kind=I64 } -> x2 + v44 Phi { incoming=[b13:v35, b9:v42], kind=I64 } -> x2 v45 LoadLocal { off=-3, kind=I64 } -> x0 terminator Bz { cond=v44, target=b12, fall=b11 } (exit_acc=v44) block 11 start_pc=0 @@ -77,11 +77,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v47 Imm(0) -> x0 terminator Return(v47) (exit_acc=v47) block 13 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b10) block 14 start_pc=0 terminator Jmp(b6) block 15 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_array_elided_runtime.ssa b/tests/snapshots/ssa/struct_array_elided_runtime.ssa index 12d3cdb5c..faab65954 100644 --- a/tests/snapshots/ssa/struct_array_elided_runtime.ssa +++ b/tests/snapshots/ssa/struct_array_elided_runtime.ssa @@ -39,7 +39,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v33 LoadLocal { off=2, kind=I32 } -> x1 v34 Binop { op=ne, lhs=v32, rhs=v1 } -> x1 v35 Imm(0) -> x0 - terminator Bnz { cond=v34, target=b21, fall=b1 } (exit_acc=v34) + terminator Bnz { cond=v34, target=b25, fall=b1 } (exit_acc=v34) block 1 start_pc=0 v36 LocalAddr(-2) -> x0 v37 Imm(0) -> x1 @@ -53,7 +53,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v45 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v44) block 2 start_pc=0 - v46 Phi { incoming=[b21:v34, b1:v44], kind=I64 } -> x1 + v46 Phi { incoming=[b25:v34, b1:v44], kind=I64 } -> x1 v47 LoadLocal { off=-6, kind=I64 } -> x0 terminator Bz { cond=v46, target=b4, fall=b3 } (exit_acc=v46) block 3 start_pc=0 @@ -70,7 +70,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v56 Extend { value=v54, kind=I32 } -> x1 v57 Binop { op=ne, lhs=v52, rhs=v56 } -> x1 v58 Imm(0) -> x0 - terminator Bnz { cond=v57, target=b22, fall=b5 } (exit_acc=v57) + terminator Bnz { cond=v57, target=b24, fall=b5 } (exit_acc=v57) block 5 start_pc=0 v59 LocalAddr(-2) -> x0 v60 Imm(8) -> x1 @@ -85,7 +85,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v69 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v68) block 6 start_pc=0 - v70 Phi { incoming=[b22:v57, b5:v68], kind=I64 } -> x1 + v70 Phi { incoming=[b24:v57, b5:v68], kind=I64 } -> x1 v71 LoadLocal { off=-7, kind=I64 } -> x0 terminator Bz { cond=v70, target=b8, fall=b7 } (exit_acc=v70) block 7 start_pc=0 @@ -157,7 +157,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v127 Extend { value=v125, kind=I32 } -> x1 v128 Binop { op=ne, lhs=v123, rhs=v127 } -> x1 v129 Imm(0) -> x0 - terminator Bnz { cond=v128, target=b24, fall=b13 } (exit_acc=v128) + terminator Bnz { cond=v128, target=b22, fall=b13 } (exit_acc=v128) block 13 start_pc=0 v130 LocalAddr(-5) -> x0 v131 Imm(8) -> x1 @@ -172,7 +172,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v140 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v139) block 14 start_pc=0 - v141 Phi { incoming=[b24:v128, b13:v139], kind=I64 } -> x1 + v141 Phi { incoming=[b22:v128, b13:v139], kind=I64 } -> x1 v142 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v141, target=b16, fall=b15 } (exit_acc=v141) block 15 start_pc=0 @@ -185,7 +185,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v147 Load { addr=v144, disp=16, kind=I32 } -> x0 v148 BinopI { op=ne, lhs=v147, rhs_imm=7 } -> x1 v149 Imm(0) -> x0 - terminator Bnz { cond=v148, target=b25, fall=b17 } (exit_acc=v148) + terminator Bnz { cond=v148, target=b21, fall=b17 } (exit_acc=v148) block 17 start_pc=0 v150 LocalAddr(-5) -> x0 v151 Imm(16) -> x1 @@ -196,7 +196,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v156 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v155) block 18 start_pc=0 - v157 Phi { incoming=[b25:v148, b17:v155], kind=I64 } -> x1 + v157 Phi { incoming=[b21:v148, b17:v155], kind=I64 } -> x1 v158 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v157, target=b20, fall=b19 } (exit_acc=v157) block 19 start_pc=0 @@ -206,15 +206,15 @@ fn ent_pc=0 n_params=1 variadic=false locals=10 v160 Imm(0) -> x0 terminator Return(v160) (exit_acc=v160) block 21 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b14) block 23 start_pc=0 terminator Jmp(b10) block 24 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b6) block 25 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=2 @@ -223,21 +223,21 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x3 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=20 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v9 Extend { value=v3, kind=I32 } -> x0 + v10 Call { target_pc=0, args=[v3], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Bnz { cond=v10, target=b5, fall=b2 } (exit_acc=v10) block 2 start_pc=0 v6 Extend { value=v3, kind=I32 } -> x0 v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + terminator Jmp(b3) (exit_acc=v7) block 3 start_pc=0 - v9 Extend { value=v3, kind=I32 } -> x7 - v10 Call { target_pc=0, args=[v9], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x3 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=20 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) block 4 start_pc=0 v11 Imm(0) -> x0 terminator Return(v11) (exit_acc=v11) diff --git a/tests/snapshots/ssa/struct_array_init_from_lvalue.ssa b/tests/snapshots/ssa/struct_array_init_from_lvalue.ssa index 94313c73f..9c2276707 100644 --- a/tests/snapshots/ssa/struct_array_init_from_lvalue.ssa +++ b/tests/snapshots/ssa/struct_array_init_from_lvalue.ssa @@ -39,7 +39,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v16 Imm(4369) -> x1 v17 BinopI { op=ne, lhs=v15, rhs_imm=4369 } -> x1 v18 Imm(0) -> x0 - terminator Bnz { cond=v17, target=b29, fall=b1 } (exit_acc=v17) + terminator Bnz { cond=v17, target=b36, fall=b1 } (exit_acc=v17) block 1 start_pc=0 v19 LocalAddr(-6) -> x0 v20 Imm(0) -> x1 @@ -49,7 +49,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v24 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v23) block 2 start_pc=0 - v25 Phi { incoming=[b29:v17, b1:v23], kind=I64 } -> x1 + v25 Phi { incoming=[b36:v17, b1:v23], kind=I64 } -> x1 v26 LoadLocal { off=-22, kind=I64 } -> x0 terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) block 3 start_pc=0 @@ -85,7 +85,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v54 Imm(4369) -> x1 v55 BinopI { op=ne, lhs=v53, rhs_imm=4369 } -> x1 v56 Imm(0) -> x0 - terminator Bnz { cond=v55, target=b30, fall=b5 } (exit_acc=v55) + terminator Bnz { cond=v55, target=b35, fall=b5 } (exit_acc=v55) block 5 start_pc=0 v57 LocalAddr(-12) -> x0 v58 Imm(0) -> x1 @@ -95,7 +95,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v62 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v61) block 6 start_pc=0 - v63 Phi { incoming=[b30:v55, b5:v61], kind=I64 } -> x1 + v63 Phi { incoming=[b35:v55, b5:v61], kind=I64 } -> x1 v64 LoadLocal { off=-25, kind=I64 } -> x0 terminator Bz { cond=v63, target=b8, fall=b7 } (exit_acc=v63) block 7 start_pc=0 @@ -109,7 +109,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v70 Imm(8738) -> x1 v71 BinopI { op=ne, lhs=v69, rhs_imm=8738 } -> x1 v72 Imm(0) -> x0 - terminator Bnz { cond=v71, target=b31, fall=b9 } (exit_acc=v71) + terminator Bnz { cond=v71, target=b34, fall=b9 } (exit_acc=v71) block 9 start_pc=0 v73 LocalAddr(-12) -> x0 v74 Imm(16) -> x1 @@ -120,7 +120,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v79 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v78) block 10 start_pc=0 - v80 Phi { incoming=[b31:v71, b9:v78], kind=I64 } -> x1 + v80 Phi { incoming=[b34:v71, b9:v78], kind=I64 } -> x1 v81 LoadLocal { off=-26, kind=I64 } -> x0 terminator Bz { cond=v80, target=b12, fall=b11 } (exit_acc=v80) block 11 start_pc=0 @@ -134,7 +134,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v87 Imm(13107) -> x1 v88 BinopI { op=ne, lhs=v86, rhs_imm=13107 } -> x1 v89 Imm(0) -> x0 - terminator Bnz { cond=v88, target=b32, fall=b13 } (exit_acc=v88) + terminator Bnz { cond=v88, target=b33, fall=b13 } (exit_acc=v88) block 13 start_pc=0 v90 LocalAddr(-12) -> x0 v91 Imm(32) -> x1 @@ -145,7 +145,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v96 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v95) block 14 start_pc=0 - v97 Phi { incoming=[b32:v88, b13:v95], kind=I64 } -> x1 + v97 Phi { incoming=[b33:v88, b13:v95], kind=I64 } -> x1 v98 LoadLocal { off=-27, kind=I64 } -> x0 terminator Bz { cond=v97, target=b16, fall=b15 } (exit_acc=v97) block 15 start_pc=0 @@ -165,7 +165,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v110 Imm(0) -> x1 v111 BinopI { op=ne, lhs=v109, rhs_imm=0 } -> x1 v112 Imm(0) -> x0 - terminator Bnz { cond=v111, target=b33, fall=b17 } (exit_acc=v111) + terminator Bnz { cond=v111, target=b32, fall=b17 } (exit_acc=v111) block 17 start_pc=0 v113 LocalAddr(-18) -> x0 v114 Imm(16) -> x1 @@ -176,7 +176,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v119 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v118) block 18 start_pc=0 - v120 Phi { incoming=[b33:v111, b17:v118], kind=I64 } -> x1 + v120 Phi { incoming=[b32:v111, b17:v118], kind=I64 } -> x1 v121 LoadLocal { off=-28, kind=I64 } -> x0 terminator Bz { cond=v120, target=b20, fall=b19 } (exit_acc=v120) block 19 start_pc=0 @@ -209,7 +209,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v146 BinopI { op=ne, lhs=v145, rhs_imm=10 } -> x0 v147 Imm(1) -> x2 v148 Imm(0) -> x1 - terminator Bnz { cond=v146, target=b34, fall=b21 } (exit_acc=v146) + terminator Bnz { cond=v146, target=b31, fall=b21 } (exit_acc=v146) block 21 start_pc=0 v149 LocalAddr(-21) -> x0 v150 Imm(0) -> x1 @@ -220,11 +220,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v155 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v154) block 22 start_pc=0 - v156 Phi { incoming=[b34:v147, b21:v154], kind=I64 } -> x2 + v156 Phi { incoming=[b31:v147, b21:v154], kind=I64 } -> x2 v157 LoadLocal { off=-31, kind=I64 } -> x0 v158 Imm(1) -> x1 v159 Imm(0) -> x0 - terminator Bnz { cond=v156, target=b35, fall=b23 } (exit_acc=v156) + terminator Bnz { cond=v156, target=b30, fall=b23 } (exit_acc=v156) block 23 start_pc=0 v160 LocalAddr(-21) -> x0 v161 Imm(8) -> x1 @@ -235,10 +235,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v166 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v165) block 24 start_pc=0 - v167 Phi { incoming=[b35:v158, b23:v165], kind=I64 } -> x1 + v167 Phi { incoming=[b30:v158, b23:v165], kind=I64 } -> x1 v168 LoadLocal { off=-30, kind=I64 } -> x0 v169 Imm(0) -> x0 - terminator Bnz { cond=v167, target=b36, fall=b25 } (exit_acc=v167) + terminator Bnz { cond=v167, target=b29, fall=b25 } (exit_acc=v167) block 25 start_pc=0 v170 LocalAddr(-21) -> x0 v171 Imm(8) -> x1 @@ -249,7 +249,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v176 Imm(0) -> x0 terminator Jmp(b26) (exit_acc=v175) block 26 start_pc=0 - v177 Phi { incoming=[b36:v167, b25:v175], kind=I64 } -> x1 + v177 Phi { incoming=[b29:v167, b25:v175], kind=I64 } -> x1 v178 LoadLocal { off=-29, kind=I64 } -> x0 terminator Bz { cond=v177, target=b28, fall=b27 } (exit_acc=v177) block 27 start_pc=0 @@ -259,21 +259,21 @@ fn ent_pc=1 n_params=0 variadic=false locals=31 v180 Imm(0) -> x0 terminator Return(v180) (exit_acc=v180) block 29 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b26) block 30 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b24) block 31 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b22) block 32 start_pc=0 - terminator Jmp(b14) - block 33 start_pc=0 terminator Jmp(b18) + block 33 start_pc=0 + terminator Jmp(b14) block 34 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b10) block 35 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b6) block 36 start_pc=0 - terminator Jmp(b26) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_by_value_return.ssa b/tests/snapshots/ssa/struct_by_value_return.ssa index 4cc06173d..a918eacd9 100644 --- a/tests/snapshots/ssa/struct_by_value_return.ssa +++ b/tests/snapshots/ssa/struct_by_value_return.ssa @@ -26,28 +26,28 @@ fn ent_pc=1 n_params=1 variadic=false locals=4 v1 ParamRef(0, kind=I32) -> x7 v2 Imm(0) -> x0 v3 Imm(57005) -> x0 - v4 Imm(0) -> x1 - v5 Imm(48879) -> x1 - v6 Imm(0) -> x2 - v7 Imm(51966) -> x2 - v8 Imm(0) -> x6 - v9 Imm(1027311) -> x6 - v10 Imm(0) -> x8 - v11 LoadLocal { off=-1, kind=I32 } -> x8 - v12 LoadLocal { off=-2, kind=I32 } -> x8 - v13 Binop { op=add, lhs=v3, rhs=v5 } -> x0 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x1 - v15 Extend { value=v13, kind=I32 } -> x1 - v16 LoadLocal { off=-3, kind=I32 } -> x1 - v17 Binop { op=add, lhs=v13, rhs=v7 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x1 - v20 LoadLocal { off=-4, kind=I32 } -> x1 - v21 Binop { op=add, lhs=v17, rhs=v9 } -> x0 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x1 - v23 Extend { value=v21, kind=I32 } -> x1 - v24 LoadLocal { off=2, kind=I32 } -> x1 - v25 Binop { op=add, lhs=v21, rhs=v1 } -> x0 + v4 Imm(0) -> x0 + v5 Imm(48879) -> x0 + v6 Imm(0) -> x0 + v7 Imm(51966) -> x0 + v8 Imm(0) -> x0 + v9 Imm(1027311) -> x0 + v10 Imm(0) -> x0 + v11 LoadLocal { off=-1, kind=I32 } -> x0 + v12 LoadLocal { off=-2, kind=I32 } -> x0 + v13 Imm(105884) -> x0 + v14 Imm(454768317169664) -> x0 + v15 Imm(105884) -> x0 + v16 LoadLocal { off=-3, kind=I32 } -> x0 + v17 Imm(157850) -> x0 + v18 Imm(677960587673600) -> x0 + v19 Imm(157850) -> x0 + v20 LoadLocal { off=-4, kind=I32 } -> x0 + v21 Imm(1185161) -> x0 + v22 Imm(5090227735494656) -> x0 + v23 Imm(1185161) -> x0 + v24 LoadLocal { off=2, kind=I32 } -> x0 + v25 BinopI { op=add, lhs=v1, rhs_imm=1185161 } -> x0 v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x1 v27 Extend { value=v25, kind=I32 } -> x0 terminator Return(v27) (exit_acc=v27) @@ -88,188 +88,185 @@ fn ent_pc=3 n_params=0 variadic=false locals=24 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 v2 Imm(11) -> x1 - v3 Imm(22) -> x2 - v4 Extend { value=v2, kind=I32 } -> x6 - v5 Imm(0) -> x6 - v6 Extend { value=v3, kind=I32 } -> x6 + v3 Imm(22) -> x1 + v4 Imm(11) -> x1 + v5 Imm(0) -> x2 + v6 Imm(22) -> x2 v7 Imm(0) -> x6 v8 LocalAddr(-18) -> x6 - v9 Store { addr=v8, disp=0, value=v2, kind=I32 } -> - + v9 Store { addr=v8, disp=0, value=v4, kind=I32 } -> - v10 LocalAddr(-18) -> x1 v11 BinopI { op=add, lhs=v10, rhs_imm=4 } -> x6 - v12 Store { addr=v10, disp=4, value=v3, kind=I32 } -> - + v12 Store { addr=v10, disp=4, value=v6, kind=I32 } -> - v13 LocalAddr(-18) -> x1 v14 LocalAddr(-18) -> x1 v15 Mcpy { dst=v1, src=v14, size=8 } -> x0 v16 Imm(7) -> x0 - v17 Extend { value=v16, kind=I32 } -> x1 - v18 Imm(0) -> x1 - v19 Imm(57005) -> x1 - v20 Imm(0) -> x2 - v21 Imm(48879) -> x2 - v22 Imm(0) -> x6 - v23 Imm(51966) -> x6 - v24 Imm(0) -> x7 - v25 Imm(1027311) -> x7 - v26 Imm(0) -> x8 - v27 Binop { op=add, lhs=v19, rhs=v21 } -> x1 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x2 - v29 Extend { value=v27, kind=I32 } -> x2 - v30 Binop { op=add, lhs=v27, rhs=v23 } -> x1 - v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x2 - v32 Extend { value=v30, kind=I32 } -> x2 - v33 Binop { op=add, lhs=v30, rhs=v25 } -> x1 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x2 - v35 Extend { value=v33, kind=I32 } -> x2 - v36 Binop { op=add, lhs=v33, rhs=v16 } -> x0 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x1 - v38 Extend { value=v36, kind=I32 } -> x0 - v39 Imm(0) -> x1 - v40 Extend { value=v38, kind=I32 } -> x0 - v41 BinopI { op=eq, lhs=v40, rhs_imm=0 } -> x0 - terminator Bz { cond=v41, target=b2, fall=b1 } (exit_acc=v41) + v17 Imm(7) -> x0 + v18 Imm(0) -> x0 + v19 Imm(57005) -> x0 + v20 Imm(0) -> x0 + v21 Imm(48879) -> x0 + v22 Imm(0) -> x0 + v23 Imm(51966) -> x0 + v24 Imm(0) -> x0 + v25 Imm(1027311) -> x0 + v26 Imm(0) -> x0 + v27 Imm(105884) -> x0 + v28 Imm(454768317169664) -> x0 + v29 Imm(105884) -> x0 + v30 Imm(157850) -> x0 + v31 Imm(677960587673600) -> x0 + v32 Imm(157850) -> x0 + v33 Imm(1185161) -> x0 + v34 Imm(5090227735494656) -> x0 + v35 Imm(1185161) -> x0 + v36 Imm(1185168) -> x0 + v37 Imm(5090257800265728) -> x0 + v38 Imm(1185168) -> x0 + v39 Imm(0) -> x0 + v40 Imm(1185168) -> x0 + v41 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v41) block 1 start_pc=0 - v42 Imm(99) -> x0 - terminator Return(v42) (exit_acc=v42) - block 2 start_pc=0 v43 LocalAddr(-1) -> x0 v44 Load { addr=v43, disp=0, kind=I32 } -> x0 v45 BinopI { op=ne, lhs=v44, rhs_imm=11 } -> x0 - terminator Bz { cond=v45, target=b4, fall=b3 } (exit_acc=v45) - block 3 start_pc=0 + terminator Bz { cond=v45, target=b3, fall=b2 } (exit_acc=v45) + block 2 start_pc=0 v46 Imm(1) -> x0 terminator Return(v46) (exit_acc=v46) - block 4 start_pc=0 + block 3 start_pc=0 v47 LocalAddr(-1) -> x0 v48 BinopI { op=add, lhs=v47, rhs_imm=4 } -> x1 v49 Load { addr=v47, disp=4, kind=I32 } -> x0 v50 BinopI { op=ne, lhs=v49, rhs_imm=22 } -> x0 - terminator Bz { cond=v50, target=b6, fall=b5 } (exit_acc=v50) - block 5 start_pc=0 + terminator Bz { cond=v50, target=b5, fall=b4 } (exit_acc=v50) + block 4 start_pc=0 v51 Imm(2) -> x0 terminator Return(v51) (exit_acc=v51) - block 6 start_pc=0 + block 5 start_pc=0 v52 LocalAddr(-4) -> x0 v53 Imm(3) -> x1 - v54 Imm(4) -> x2 - v55 Extend { value=v53, kind=I32 } -> x6 - v56 Imm(0) -> x6 - v57 Extend { value=v54, kind=I32 } -> x6 + v54 Imm(4) -> x1 + v55 Imm(3) -> x1 + v56 Imm(0) -> x2 + v57 Imm(4) -> x2 v58 Imm(0) -> x6 v59 LocalAddr(-19) -> x6 - v60 Store { addr=v59, disp=0, value=v53, kind=I32 } -> - + v60 Store { addr=v59, disp=0, value=v55, kind=I32 } -> - v61 LocalAddr(-19) -> x1 v62 BinopI { op=add, lhs=v61, rhs_imm=4 } -> x6 - v63 Store { addr=v61, disp=4, value=v54, kind=I32 } -> - + v63 Store { addr=v61, disp=4, value=v57, kind=I32 } -> - v64 LocalAddr(-19) -> x1 v65 LocalAddr(-19) -> x1 v66 Mcpy { dst=v52, src=v65, size=8 } -> x0 v67 LocalAddr(-4) -> x0 v68 Load { addr=v67, disp=0, kind=I32 } -> x0 v69 BinopI { op=ne, lhs=v68, rhs_imm=3 } -> x0 - terminator Bz { cond=v69, target=b8, fall=b7 } (exit_acc=v69) - block 7 start_pc=0 + terminator Bz { cond=v69, target=b7, fall=b6 } (exit_acc=v69) + block 6 start_pc=0 v70 Imm(3) -> x0 terminator Return(v70) (exit_acc=v70) - block 8 start_pc=0 + block 7 start_pc=0 v71 LocalAddr(-4) -> x0 v72 BinopI { op=add, lhs=v71, rhs_imm=4 } -> x1 v73 Load { addr=v71, disp=4, kind=I32 } -> x0 v74 BinopI { op=ne, lhs=v73, rhs_imm=4 } -> x0 - terminator Bz { cond=v74, target=b10, fall=b9 } (exit_acc=v74) - block 9 start_pc=0 + terminator Bz { cond=v74, target=b9, fall=b8 } (exit_acc=v74) + block 8 start_pc=0 v75 Imm(4) -> x0 terminator Return(v75) (exit_acc=v75) - block 10 start_pc=0 + block 9 start_pc=0 v76 LocalAddr(-6) -> x0 v77 Imm(100) -> x1 - v78 Imm(200) -> x2 - v79 Extend { value=v77, kind=I32 } -> x6 - v80 Imm(0) -> x6 - v81 Extend { value=v78, kind=I32 } -> x6 + v78 Imm(200) -> x1 + v79 Imm(100) -> x1 + v80 Imm(0) -> x2 + v81 Imm(200) -> x2 v82 Imm(0) -> x6 v83 LocalAddr(-20) -> x6 - v84 Store { addr=v83, disp=0, value=v77, kind=I32 } -> - + v84 Store { addr=v83, disp=0, value=v79, kind=I32 } -> - v85 LocalAddr(-20) -> x1 v86 BinopI { op=add, lhs=v85, rhs_imm=4 } -> x6 - v87 Store { addr=v85, disp=4, value=v78, kind=I32 } -> - + v87 Store { addr=v85, disp=4, value=v81, kind=I32 } -> - v88 LocalAddr(-20) -> x1 v89 LocalAddr(-20) -> x1 v90 Mcpy { dst=v76, src=v89, size=8 } -> x0 v91 LocalAddr(-7) -> x0 v92 Imm(300) -> x1 - v93 Imm(400) -> x2 - v94 Extend { value=v92, kind=I32 } -> x6 - v95 Imm(0) -> x6 - v96 Extend { value=v93, kind=I32 } -> x6 + v93 Imm(400) -> x1 + v94 Imm(300) -> x1 + v95 Imm(0) -> x2 + v96 Imm(400) -> x2 v97 Imm(0) -> x6 v98 LocalAddr(-21) -> x6 - v99 Store { addr=v98, disp=0, value=v92, kind=I32 } -> - + v99 Store { addr=v98, disp=0, value=v94, kind=I32 } -> - v100 LocalAddr(-21) -> x1 v101 BinopI { op=add, lhs=v100, rhs_imm=4 } -> x6 - v102 Store { addr=v100, disp=4, value=v93, kind=I32 } -> - + v102 Store { addr=v100, disp=4, value=v96, kind=I32 } -> - v103 LocalAddr(-21) -> x1 v104 LocalAddr(-21) -> x1 v105 Mcpy { dst=v91, src=v104, size=8 } -> x0 v106 LocalAddr(-6) -> x0 v107 Load { addr=v106, disp=0, kind=I32 } -> x0 v108 BinopI { op=ne, lhs=v107, rhs_imm=100 } -> x0 - terminator Bz { cond=v108, target=b12, fall=b11 } (exit_acc=v108) - block 11 start_pc=0 + terminator Bz { cond=v108, target=b11, fall=b10 } (exit_acc=v108) + block 10 start_pc=0 v109 Imm(5) -> x0 terminator Return(v109) (exit_acc=v109) - block 12 start_pc=0 + block 11 start_pc=0 v110 LocalAddr(-6) -> x0 v111 BinopI { op=add, lhs=v110, rhs_imm=4 } -> x1 v112 Load { addr=v110, disp=4, kind=I32 } -> x0 v113 BinopI { op=ne, lhs=v112, rhs_imm=200 } -> x0 - terminator Bz { cond=v113, target=b14, fall=b13 } (exit_acc=v113) - block 13 start_pc=0 + terminator Bz { cond=v113, target=b13, fall=b12 } (exit_acc=v113) + block 12 start_pc=0 v114 Imm(6) -> x0 terminator Return(v114) (exit_acc=v114) - block 14 start_pc=0 + block 13 start_pc=0 v115 LocalAddr(-7) -> x0 v116 Load { addr=v115, disp=0, kind=I32 } -> x0 v117 BinopI { op=ne, lhs=v116, rhs_imm=300 } -> x0 - terminator Bz { cond=v117, target=b16, fall=b15 } (exit_acc=v117) - block 15 start_pc=0 + terminator Bz { cond=v117, target=b15, fall=b14 } (exit_acc=v117) + block 14 start_pc=0 v118 Imm(7) -> x0 terminator Return(v118) (exit_acc=v118) - block 16 start_pc=0 + block 15 start_pc=0 v119 LocalAddr(-7) -> x0 v120 BinopI { op=add, lhs=v119, rhs_imm=4 } -> x1 v121 Load { addr=v119, disp=4, kind=I32 } -> x0 v122 BinopI { op=ne, lhs=v121, rhs_imm=400 } -> x0 - terminator Bz { cond=v122, target=b18, fall=b17 } (exit_acc=v122) - block 17 start_pc=0 + terminator Bz { cond=v122, target=b17, fall=b16 } (exit_acc=v122) + block 16 start_pc=0 v123 Imm(8) -> x0 terminator Return(v123) (exit_acc=v123) - block 18 start_pc=0 + block 17 start_pc=0 v124 LocalAddr(-10) -> x0 v125 Imm(1) -> x1 - v126 Imm(2) -> x2 - v127 Extend { value=v125, kind=I32 } -> x6 - v128 Imm(0) -> x6 - v129 Extend { value=v126, kind=I32 } -> x6 + v126 Imm(2) -> x1 + v127 Imm(1) -> x1 + v128 Imm(0) -> x2 + v129 Imm(2) -> x2 v130 Imm(0) -> x6 v131 LocalAddr(-22) -> x6 - v132 Store { addr=v131, disp=0, value=v125, kind=I32 } -> - + v132 Store { addr=v131, disp=0, value=v127, kind=I32 } -> - v133 LocalAddr(-22) -> x1 v134 BinopI { op=add, lhs=v133, rhs_imm=4 } -> x6 - v135 Store { addr=v133, disp=4, value=v126, kind=I32 } -> - + v135 Store { addr=v133, disp=4, value=v129, kind=I32 } -> - v136 LocalAddr(-22) -> x1 v137 LocalAddr(-22) -> x1 v138 Imm(3) -> x2 - v139 Imm(4) -> x6 - v140 Extend { value=v138, kind=I32 } -> x7 - v141 Imm(0) -> x7 - v142 Extend { value=v139, kind=I32 } -> x7 + v139 Imm(4) -> x2 + v140 Imm(3) -> x2 + v141 Imm(0) -> x6 + v142 Imm(4) -> x6 v143 Imm(0) -> x7 v144 LocalAddr(-23) -> x7 - v145 Store { addr=v144, disp=0, value=v138, kind=I32 } -> - + v145 Store { addr=v144, disp=0, value=v140, kind=I32 } -> - v146 LocalAddr(-23) -> x2 v147 BinopI { op=add, lhs=v146, rhs_imm=4 } -> x7 - v148 Store { addr=v146, disp=4, value=v139, kind=I32 } -> - + v148 Store { addr=v146, disp=4, value=v142, kind=I32 } -> - v149 LocalAddr(-23) -> x2 v150 LocalAddr(-23) -> x2 v151 LocalAddr(-24) -> x6 @@ -295,22 +292,25 @@ fn ent_pc=3 n_params=0 variadic=false locals=24 v171 LocalAddr(-10) -> x0 v172 Load { addr=v171, disp=0, kind=I32 } -> x0 v173 BinopI { op=ne, lhs=v172, rhs_imm=4 } -> x0 - terminator Bz { cond=v173, target=b20, fall=b19 } (exit_acc=v173) - block 19 start_pc=0 + terminator Bz { cond=v173, target=b19, fall=b18 } (exit_acc=v173) + block 18 start_pc=0 v174 Imm(9) -> x0 terminator Return(v174) (exit_acc=v174) - block 20 start_pc=0 + block 19 start_pc=0 v175 LocalAddr(-10) -> x0 v176 BinopI { op=add, lhs=v175, rhs_imm=4 } -> x1 v177 Load { addr=v175, disp=4, kind=I32 } -> x0 v178 BinopI { op=ne, lhs=v177, rhs_imm=6 } -> x0 - terminator Bz { cond=v178, target=b22, fall=b21 } (exit_acc=v178) - block 21 start_pc=0 + terminator Bz { cond=v178, target=b21, fall=b20 } (exit_acc=v178) + block 20 start_pc=0 v179 Imm(10) -> x0 terminator Return(v179) (exit_acc=v179) - block 22 start_pc=0 + block 21 start_pc=0 v180 Imm(0) -> x0 terminator Return(v180) (exit_acc=v180) + block 22 start_pc=0 + v42 Imm(99) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_field_assign_from_call.ssa b/tests/snapshots/ssa/struct_field_assign_from_call.ssa index ac2169d13..76a1c5538 100644 --- a/tests/snapshots/ssa/struct_field_assign_from_call.ssa +++ b/tests/snapshots/ssa/struct_field_assign_from_call.ssa @@ -52,13 +52,13 @@ fn ent_pc=2 n_params=2 variadic=false locals=8 v13 BinopI { op=add, lhs=v1, rhs_imm=20 } -> x6 v14 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x0 v15 Load { addr=v1, disp=16, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x1 - v18 Extend { value=v16, kind=I32 } -> x2 + v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x2 + v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x0 + v18 Extend { value=v16, kind=I32 } -> x0 v19 Imm(16) -> x15 v20 Imm(32767) -> [spill 0] v21 LoadLocal { off=3, kind=I64 } -> x0 - v22 Call { target_pc=1, args=[v7, v13, v18, v19, v20, v3], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 + v22 Call { target_pc=1, args=[v7, v13, v16, v19, v20, v3], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 v23 Store { addr=v1, disp=8, value=v22, kind=I64 } -> - v24 LoadLocal { off=2, kind=I64 } -> x0 v25 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x0 @@ -66,11 +66,11 @@ fn ent_pc=2 n_params=2 variadic=false locals=8 v27 BinopI { op=add, lhs=v1, rhs_imm=36 } -> x6 v28 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x0 v29 Load { addr=v1, disp=32, kind=I32 } -> x0 - v30 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x0 - v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x1 - v32 Extend { value=v30, kind=I32 } -> x2 + v30 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x2 + v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x0 + v32 Extend { value=v30, kind=I32 } -> x0 v33 LoadLocal { off=3, kind=I64 } -> x0 - v34 Call { target_pc=1, args=[v26, v27, v32, v19, v20, v3], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 + v34 Call { target_pc=1, args=[v26, v27, v30, v19, v20, v3], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 v35 Store { addr=v1, disp=24, value=v34, kind=I64 } -> - v36 LoadLocal { off=-1, kind=I64 } -> x0 v37 LoadLocal { off=2, kind=I64 } -> x0 diff --git a/tests/snapshots/ssa/struct_layout.ssa b/tests/snapshots/ssa/struct_layout.ssa index 1b9549935..e07b14d8c 100644 --- a/tests/snapshots/ssa/struct_layout.ssa +++ b/tests/snapshots/ssa/struct_layout.ssa @@ -5,595 +5,595 @@ fn ent_pc=1 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 v6 Imm(4) -> x1 v7 Imm(17179869184) -> x1 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v8 Imm(3) -> x0 - terminator Return(v8) (exit_acc=v8) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v9 Imm(0) -> x0 v10 Imm(8) -> x1 v11 Imm(34359738368) -> x1 - terminator Jmp(b8) (exit_acc=v9) - block 7 start_pc=0 - v12 Imm(4) -> x0 - terminator Return(v12) (exit_acc=v12) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v9) + block 4 start_pc=0 v13 Imm(0) -> x0 v14 Imm(16) -> x1 v15 Imm(68719476736) -> x1 - terminator Jmp(b10) (exit_acc=v13) - block 9 start_pc=0 - v16 Imm(5) -> x0 - terminator Return(v16) (exit_acc=v16) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v13) + block 5 start_pc=0 v17 Imm(0) -> x0 v18 Imm(24) -> x1 v19 Imm(103079215104) -> x1 - terminator Jmp(b12) (exit_acc=v17) - block 11 start_pc=0 - v20 Imm(6) -> x0 - terminator Return(v20) (exit_acc=v20) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v17) + block 6 start_pc=0 v21 Imm(0) -> x0 v22 Imm(26) -> x1 v23 Imm(111669149696) -> x1 - terminator Jmp(b14) (exit_acc=v21) - block 13 start_pc=0 - v24 Imm(7) -> x0 - terminator Return(v24) (exit_acc=v24) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v21) + block 7 start_pc=0 v25 Imm(0) -> x0 v26 Imm(32) -> x1 v27 Imm(137438953472) -> x1 - terminator Jmp(b16) (exit_acc=v25) - block 15 start_pc=0 - v28 Imm(8) -> x0 - terminator Return(v28) (exit_acc=v28) - block 16 start_pc=0 + terminator Jmp(b8) (exit_acc=v25) + block 8 start_pc=0 v29 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v29) - block 17 start_pc=0 - v30 Imm(10) -> x0 - terminator Return(v30) (exit_acc=v30) - block 18 start_pc=0 + terminator Jmp(b9) (exit_acc=v29) + block 9 start_pc=0 v31 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v31) - block 19 start_pc=0 - v32 Imm(11) -> x0 - terminator Return(v32) (exit_acc=v32) - block 20 start_pc=0 + terminator Jmp(b10) (exit_acc=v31) + block 10 start_pc=0 v33 Imm(0) -> x0 v34 Imm(1) -> x1 v35 Imm(4294967296) -> x1 - terminator Jmp(b22) (exit_acc=v33) - block 21 start_pc=0 - v36 Imm(12) -> x0 - terminator Return(v36) (exit_acc=v36) - block 22 start_pc=0 + terminator Jmp(b11) (exit_acc=v33) + block 11 start_pc=0 v37 Imm(0) -> x0 v38 Imm(2) -> x1 v39 Imm(8589934592) -> x1 - terminator Jmp(b24) (exit_acc=v37) - block 23 start_pc=0 - v40 Imm(13) -> x0 - terminator Return(v40) (exit_acc=v40) - block 24 start_pc=0 + terminator Jmp(b12) (exit_acc=v37) + block 12 start_pc=0 v41 Imm(0) -> x0 v42 Imm(3) -> x1 v43 Imm(12884901888) -> x1 - terminator Jmp(b26) (exit_acc=v41) - block 25 start_pc=0 - v44 Imm(14) -> x0 - terminator Return(v44) (exit_acc=v44) - block 26 start_pc=0 + terminator Jmp(b13) (exit_acc=v41) + block 13 start_pc=0 v45 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v45) - block 27 start_pc=0 - v46 Imm(20) -> x0 - terminator Return(v46) (exit_acc=v46) - block 28 start_pc=0 + terminator Jmp(b14) (exit_acc=v45) + block 14 start_pc=0 v47 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v47) - block 29 start_pc=0 - v48 Imm(21) -> x0 - terminator Return(v48) (exit_acc=v48) - block 30 start_pc=0 + terminator Jmp(b15) (exit_acc=v47) + block 15 start_pc=0 v49 Imm(0) -> x0 v50 Imm(4) -> x1 v51 Imm(17179869184) -> x1 - terminator Jmp(b32) (exit_acc=v49) - block 31 start_pc=0 - v52 Imm(22) -> x0 - terminator Return(v52) (exit_acc=v52) - block 32 start_pc=0 + terminator Jmp(b16) (exit_acc=v49) + block 16 start_pc=0 v53 Imm(0) -> x0 v54 Imm(8) -> x1 v55 Imm(34359738368) -> x1 - terminator Jmp(b34) (exit_acc=v53) - block 33 start_pc=0 - v56 Imm(23) -> x0 - terminator Return(v56) (exit_acc=v56) - block 34 start_pc=0 + terminator Jmp(b17) (exit_acc=v53) + block 17 start_pc=0 v57 Imm(0) -> x0 - terminator Jmp(b36) (exit_acc=v57) - block 35 start_pc=0 - v58 Imm(30) -> x0 - terminator Return(v58) (exit_acc=v58) - block 36 start_pc=0 + terminator Jmp(b18) (exit_acc=v57) + block 18 start_pc=0 v59 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v59) - block 37 start_pc=0 - v60 Imm(31) -> x0 - terminator Return(v60) (exit_acc=v60) - block 38 start_pc=0 + terminator Jmp(b19) (exit_acc=v59) + block 19 start_pc=0 v61 Imm(0) -> x0 v62 Imm(4) -> x1 v63 Imm(17179869184) -> x1 - terminator Jmp(b40) (exit_acc=v61) - block 39 start_pc=0 - v64 Imm(32) -> x0 - terminator Return(v64) (exit_acc=v64) - block 40 start_pc=0 + terminator Jmp(b20) (exit_acc=v61) + block 20 start_pc=0 v65 Imm(0) -> x0 v66 Imm(16) -> x1 v67 Imm(68719476736) -> x1 - terminator Jmp(b42) (exit_acc=v65) - block 41 start_pc=0 - v68 Imm(33) -> x0 - terminator Return(v68) (exit_acc=v68) - block 42 start_pc=0 + terminator Jmp(b21) (exit_acc=v65) + block 21 start_pc=0 v69 Imm(0) -> x0 - terminator Jmp(b44) (exit_acc=v69) - block 43 start_pc=0 - v70 Imm(40) -> x0 - terminator Return(v70) (exit_acc=v70) - block 44 start_pc=0 + terminator Jmp(b22) (exit_acc=v69) + block 22 start_pc=0 v71 Imm(0) -> x0 - terminator Jmp(b46) (exit_acc=v71) - block 45 start_pc=0 - v72 Imm(41) -> x0 - terminator Return(v72) (exit_acc=v72) - block 46 start_pc=0 + terminator Jmp(b23) (exit_acc=v71) + block 23 start_pc=0 v73 Imm(0) -> x0 v74 Imm(8) -> x1 v75 Imm(34359738368) -> x1 - terminator Jmp(b48) (exit_acc=v73) - block 47 start_pc=0 - v76 Imm(42) -> x0 - terminator Return(v76) (exit_acc=v76) - block 48 start_pc=0 + terminator Jmp(b24) (exit_acc=v73) + block 24 start_pc=0 v77 Imm(0) -> x0 v78 Imm(32) -> x1 v79 Imm(137438953472) -> x1 - terminator Jmp(b50) (exit_acc=v77) - block 49 start_pc=0 - v80 Imm(43) -> x0 - terminator Return(v80) (exit_acc=v80) - block 50 start_pc=0 + terminator Jmp(b25) (exit_acc=v77) + block 25 start_pc=0 v81 Imm(0) -> x0 - terminator Jmp(b52) (exit_acc=v81) - block 51 start_pc=0 - v82 Imm(50) -> x0 - terminator Return(v82) (exit_acc=v82) - block 52 start_pc=0 + terminator Jmp(b26) (exit_acc=v81) + block 26 start_pc=0 v83 Imm(0) -> x0 - terminator Jmp(b54) (exit_acc=v83) - block 53 start_pc=0 - v84 Imm(51) -> x0 - terminator Return(v84) (exit_acc=v84) - block 54 start_pc=0 + terminator Jmp(b27) (exit_acc=v83) + block 27 start_pc=0 v85 Imm(0) -> x0 - terminator Jmp(b56) (exit_acc=v85) - block 55 start_pc=0 - v86 Imm(52) -> x0 - terminator Return(v86) (exit_acc=v86) - block 56 start_pc=0 + terminator Jmp(b28) (exit_acc=v85) + block 28 start_pc=0 v87 Imm(0) -> x0 v88 Imm(36) -> x1 v89 Imm(154618822656) -> x1 - terminator Jmp(b58) (exit_acc=v87) - block 57 start_pc=0 - v90 Imm(53) -> x0 - terminator Return(v90) (exit_acc=v90) - block 58 start_pc=0 + terminator Jmp(b29) (exit_acc=v87) + block 29 start_pc=0 v91 Imm(0) -> x0 - terminator Jmp(b60) (exit_acc=v91) - block 59 start_pc=0 - v92 Imm(60) -> x0 - terminator Return(v92) (exit_acc=v92) - block 60 start_pc=0 + terminator Jmp(b30) (exit_acc=v91) + block 30 start_pc=0 v93 Imm(0) -> x0 - terminator Jmp(b62) (exit_acc=v93) - block 61 start_pc=0 - v94 Imm(61) -> x0 - terminator Return(v94) (exit_acc=v94) - block 62 start_pc=0 + terminator Jmp(b31) (exit_acc=v93) + block 31 start_pc=0 v95 Imm(0) -> x0 - terminator Jmp(b64) (exit_acc=v95) - block 63 start_pc=0 - v96 Imm(62) -> x0 - terminator Return(v96) (exit_acc=v96) - block 64 start_pc=0 + terminator Jmp(b32) (exit_acc=v95) + block 32 start_pc=0 v97 Imm(0) -> x0 v98 Imm(8) -> x1 v99 Imm(34359738368) -> x1 - terminator Jmp(b66) (exit_acc=v97) - block 65 start_pc=0 - v100 Imm(63) -> x0 - terminator Return(v100) (exit_acc=v100) - block 66 start_pc=0 + terminator Jmp(b33) (exit_acc=v97) + block 33 start_pc=0 v101 Imm(0) -> x0 v102 Imm(24) -> x1 v103 Imm(103079215104) -> x1 - terminator Jmp(b68) (exit_acc=v101) - block 67 start_pc=0 - v104 Imm(64) -> x0 - terminator Return(v104) (exit_acc=v104) - block 68 start_pc=0 + terminator Jmp(b34) (exit_acc=v101) + block 34 start_pc=0 v105 Imm(0) -> x0 - terminator Jmp(b70) (exit_acc=v105) - block 69 start_pc=0 - v106 Imm(70) -> x0 - terminator Return(v106) (exit_acc=v106) - block 70 start_pc=0 + terminator Jmp(b35) (exit_acc=v105) + block 35 start_pc=0 v107 Imm(0) -> x0 - terminator Jmp(b72) (exit_acc=v107) - block 71 start_pc=0 - v108 Imm(71) -> x0 - terminator Return(v108) (exit_acc=v108) - block 72 start_pc=0 + terminator Jmp(b36) (exit_acc=v107) + block 36 start_pc=0 v109 Imm(0) -> x0 v110 Imm(1) -> x1 v111 Imm(4294967296) -> x1 - terminator Jmp(b74) (exit_acc=v109) - block 73 start_pc=0 - v112 Imm(72) -> x0 - terminator Return(v112) (exit_acc=v112) - block 74 start_pc=0 + terminator Jmp(b37) (exit_acc=v109) + block 37 start_pc=0 v113 Imm(0) -> x0 v114 Imm(5) -> x1 v115 Imm(21474836480) -> x1 - terminator Jmp(b76) (exit_acc=v113) - block 75 start_pc=0 - v116 Imm(73) -> x0 - terminator Return(v116) (exit_acc=v116) - block 76 start_pc=0 + terminator Jmp(b38) (exit_acc=v113) + block 38 start_pc=0 v117 Imm(0) -> x0 v118 Imm(6) -> x1 v119 Imm(25769803776) -> x1 - terminator Jmp(b78) (exit_acc=v117) - block 77 start_pc=0 - v120 Imm(74) -> x0 - terminator Return(v120) (exit_acc=v120) - block 78 start_pc=0 + terminator Jmp(b39) (exit_acc=v117) + block 39 start_pc=0 v121 Imm(0) -> x0 v122 Imm(14) -> x1 v123 Imm(60129542144) -> x1 - terminator Jmp(b80) (exit_acc=v121) - block 79 start_pc=0 - v124 Imm(75) -> x0 - terminator Return(v124) (exit_acc=v124) - block 80 start_pc=0 + terminator Jmp(b40) (exit_acc=v121) + block 40 start_pc=0 v125 Imm(0) -> x0 v126 Imm(16) -> x1 v127 Imm(68719476736) -> x1 - terminator Jmp(b82) (exit_acc=v125) - block 81 start_pc=0 - v128 Imm(76) -> x0 - terminator Return(v128) (exit_acc=v128) - block 82 start_pc=0 + terminator Jmp(b41) (exit_acc=v125) + block 41 start_pc=0 v129 Imm(0) -> x0 v130 Imm(17) -> x1 v131 Imm(73014444032) -> x1 - terminator Jmp(b84) (exit_acc=v129) - block 83 start_pc=0 - v132 Imm(77) -> x0 - terminator Return(v132) (exit_acc=v132) - block 84 start_pc=0 + terminator Jmp(b42) (exit_acc=v129) + block 42 start_pc=0 v133 Imm(0) -> x0 - terminator Jmp(b86) (exit_acc=v133) - block 85 start_pc=0 - v134 Imm(80) -> x0 - terminator Return(v134) (exit_acc=v134) - block 86 start_pc=0 + terminator Jmp(b43) (exit_acc=v133) + block 43 start_pc=0 v135 Imm(0) -> x0 - terminator Jmp(b88) (exit_acc=v135) - block 87 start_pc=0 - v136 Imm(81) -> x0 - terminator Return(v136) (exit_acc=v136) - block 88 start_pc=0 + terminator Jmp(b44) (exit_acc=v135) + block 44 start_pc=0 v137 Imm(0) -> x0 v138 Imm(1) -> x1 v139 Imm(4294967296) -> x1 - terminator Jmp(b90) (exit_acc=v137) - block 89 start_pc=0 - v140 Imm(82) -> x0 - terminator Return(v140) (exit_acc=v140) - block 90 start_pc=0 + terminator Jmp(b45) (exit_acc=v137) + block 45 start_pc=0 v141 Imm(0) -> x0 v142 Imm(26) -> x1 v143 Imm(111669149696) -> x1 - terminator Jmp(b92) (exit_acc=v141) - block 91 start_pc=0 - v144 Imm(83) -> x0 - terminator Return(v144) (exit_acc=v144) - block 92 start_pc=0 + terminator Jmp(b46) (exit_acc=v141) + block 46 start_pc=0 v145 Imm(0) -> x0 - terminator Jmp(b94) (exit_acc=v145) - block 93 start_pc=0 - v146 Imm(90) -> x0 - terminator Return(v146) (exit_acc=v146) - block 94 start_pc=0 + terminator Jmp(b47) (exit_acc=v145) + block 47 start_pc=0 v147 Imm(0) -> x0 - terminator Jmp(b96) (exit_acc=v147) - block 95 start_pc=0 - v148 Imm(91) -> x0 - terminator Return(v148) (exit_acc=v148) - block 96 start_pc=0 + terminator Jmp(b48) (exit_acc=v147) + block 48 start_pc=0 v149 Imm(0) -> x0 v150 Imm(2) -> x1 v151 Imm(8589934592) -> x1 - terminator Jmp(b98) (exit_acc=v149) - block 97 start_pc=0 - v152 Imm(92) -> x0 - terminator Return(v152) (exit_acc=v152) - block 98 start_pc=0 + terminator Jmp(b49) (exit_acc=v149) + block 49 start_pc=0 v153 Imm(0) -> x0 v154 Imm(6) -> x1 v155 Imm(25769803776) -> x1 - terminator Jmp(b100) (exit_acc=v153) - block 99 start_pc=0 - v156 Imm(93) -> x0 - terminator Return(v156) (exit_acc=v156) - block 100 start_pc=0 + terminator Jmp(b50) (exit_acc=v153) + block 50 start_pc=0 v157 Imm(0) -> x0 v158 Imm(8) -> x1 v159 Imm(34359738368) -> x1 - terminator Jmp(b102) (exit_acc=v157) - block 101 start_pc=0 - v160 Imm(94) -> x0 - terminator Return(v160) (exit_acc=v160) - block 102 start_pc=0 + terminator Jmp(b51) (exit_acc=v157) + block 51 start_pc=0 v161 Imm(0) -> x0 v162 Imm(16) -> x1 v163 Imm(68719476736) -> x1 - terminator Jmp(b104) (exit_acc=v161) - block 103 start_pc=0 - v164 Imm(95) -> x0 - terminator Return(v164) (exit_acc=v164) - block 104 start_pc=0 + terminator Jmp(b52) (exit_acc=v161) + block 52 start_pc=0 v165 Imm(0) -> x0 v166 Imm(18) -> x1 v167 Imm(77309411328) -> x1 - terminator Jmp(b106) (exit_acc=v165) - block 105 start_pc=0 - v168 Imm(96) -> x0 - terminator Return(v168) (exit_acc=v168) - block 106 start_pc=0 + terminator Jmp(b53) (exit_acc=v165) + block 53 start_pc=0 v169 Imm(0) -> x0 v170 Imm(20) -> x1 v171 Imm(85899345920) -> x1 - terminator Jmp(b108) (exit_acc=v169) - block 107 start_pc=0 - v172 Imm(97) -> x0 - terminator Return(v172) (exit_acc=v172) - block 108 start_pc=0 + terminator Jmp(b54) (exit_acc=v169) + block 54 start_pc=0 v173 Imm(0) -> x0 - terminator Jmp(b110) (exit_acc=v173) - block 109 start_pc=0 - v174 Imm(100) -> x0 - terminator Return(v174) (exit_acc=v174) - block 110 start_pc=0 + terminator Jmp(b55) (exit_acc=v173) + block 55 start_pc=0 v175 Imm(0) -> x0 - terminator Jmp(b112) (exit_acc=v175) - block 111 start_pc=0 - v176 Imm(101) -> x0 - terminator Return(v176) (exit_acc=v176) - block 112 start_pc=0 + terminator Jmp(b56) (exit_acc=v175) + block 56 start_pc=0 v177 Imm(0) -> x0 v178 Imm(4) -> x1 v179 Imm(17179869184) -> x1 - terminator Jmp(b114) (exit_acc=v177) - block 113 start_pc=0 - v180 Imm(102) -> x0 - terminator Return(v180) (exit_acc=v180) - block 114 start_pc=0 + terminator Jmp(b57) (exit_acc=v177) + block 57 start_pc=0 v181 Imm(0) -> x0 v182 Imm(8) -> x1 v183 Imm(34359738368) -> x1 - terminator Jmp(b116) (exit_acc=v181) - block 115 start_pc=0 - v184 Imm(103) -> x0 - terminator Return(v184) (exit_acc=v184) - block 116 start_pc=0 + terminator Jmp(b58) (exit_acc=v181) + block 58 start_pc=0 v185 Imm(0) -> x0 v186 Imm(12) -> x1 v187 Imm(51539607552) -> x1 - terminator Jmp(b118) (exit_acc=v185) - block 117 start_pc=0 - v188 Imm(104) -> x0 - terminator Return(v188) (exit_acc=v188) - block 118 start_pc=0 + terminator Jmp(b59) (exit_acc=v185) + block 59 start_pc=0 v189 Imm(0) -> x0 v190 Imm(20) -> x1 v191 Imm(85899345920) -> x1 - terminator Jmp(b120) (exit_acc=v189) - block 119 start_pc=0 - v192 Imm(105) -> x0 - terminator Return(v192) (exit_acc=v192) - block 120 start_pc=0 + terminator Jmp(b60) (exit_acc=v189) + block 60 start_pc=0 v193 Imm(0) -> x0 v194 Imm(22) -> x1 v195 Imm(94489280512) -> x1 - terminator Jmp(b122) (exit_acc=v193) - block 121 start_pc=0 - v196 Imm(106) -> x0 - terminator Return(v196) (exit_acc=v196) - block 122 start_pc=0 + terminator Jmp(b61) (exit_acc=v193) + block 61 start_pc=0 v197 Imm(0) -> x0 v198 Imm(24) -> x1 v199 Imm(103079215104) -> x1 - terminator Jmp(b124) (exit_acc=v197) - block 123 start_pc=0 - v200 Imm(107) -> x0 - terminator Return(v200) (exit_acc=v200) - block 124 start_pc=0 + terminator Jmp(b62) (exit_acc=v197) + block 62 start_pc=0 v201 Imm(0) -> x0 - terminator Jmp(b126) (exit_acc=v201) - block 125 start_pc=0 - v202 Imm(110) -> x0 - terminator Return(v202) (exit_acc=v202) - block 126 start_pc=0 + terminator Jmp(b63) (exit_acc=v201) + block 63 start_pc=0 v203 Imm(0) -> x0 v204 Imm(1) -> x1 v205 Imm(4294967296) -> x1 - terminator Jmp(b128) (exit_acc=v203) - block 127 start_pc=0 - v206 Imm(111) -> x0 - terminator Return(v206) (exit_acc=v206) - block 128 start_pc=0 + terminator Jmp(b64) (exit_acc=v203) + block 64 start_pc=0 v207 Imm(0) -> x0 - terminator Jmp(b130) (exit_acc=v207) - block 129 start_pc=0 - v208 Imm(120) -> x0 - terminator Return(v208) (exit_acc=v208) - block 130 start_pc=0 + terminator Jmp(b65) (exit_acc=v207) + block 65 start_pc=0 v209 Imm(0) -> x0 v210 Imm(4) -> x1 v211 Imm(17179869184) -> x1 - terminator Jmp(b132) (exit_acc=v209) - block 131 start_pc=0 - v212 Imm(121) -> x0 - terminator Return(v212) (exit_acc=v212) - block 132 start_pc=0 + terminator Jmp(b66) (exit_acc=v209) + block 66 start_pc=0 v213 Imm(0) -> x0 - terminator Jmp(b134) (exit_acc=v213) - block 133 start_pc=0 - v214 Imm(130) -> x0 - terminator Return(v214) (exit_acc=v214) - block 134 start_pc=0 + terminator Jmp(b67) (exit_acc=v213) + block 67 start_pc=0 v215 Imm(0) -> x0 v216 Imm(1) -> x1 v217 Imm(4294967296) -> x1 - terminator Jmp(b136) (exit_acc=v215) - block 135 start_pc=0 - v218 Imm(131) -> x0 - terminator Return(v218) (exit_acc=v218) - block 136 start_pc=0 + terminator Jmp(b68) (exit_acc=v215) + block 68 start_pc=0 v219 Imm(0) -> x0 - terminator Jmp(b138) (exit_acc=v219) - block 137 start_pc=0 - v220 Imm(140) -> x0 - terminator Return(v220) (exit_acc=v220) - block 138 start_pc=0 + terminator Jmp(b69) (exit_acc=v219) + block 69 start_pc=0 v221 Imm(0) -> x0 - terminator Jmp(b140) (exit_acc=v221) - block 139 start_pc=0 - v222 Imm(141) -> x0 - terminator Return(v222) (exit_acc=v222) - block 140 start_pc=0 + terminator Jmp(b70) (exit_acc=v221) + block 70 start_pc=0 v223 Imm(0) -> x0 v224 Imm(4) -> x1 v225 Imm(17179869184) -> x1 - terminator Jmp(b142) (exit_acc=v223) - block 141 start_pc=0 - v226 Imm(142) -> x0 - terminator Return(v226) (exit_acc=v226) - block 142 start_pc=0 + terminator Jmp(b71) (exit_acc=v223) + block 71 start_pc=0 v227 Imm(0) -> x0 v228 Imm(8) -> x1 v229 Imm(34359738368) -> x1 - terminator Jmp(b144) (exit_acc=v227) - block 143 start_pc=0 - v230 Imm(143) -> x0 - terminator Return(v230) (exit_acc=v230) - block 144 start_pc=0 + terminator Jmp(b72) (exit_acc=v227) + block 72 start_pc=0 v231 Imm(0) -> x0 - terminator Jmp(b146) (exit_acc=v231) - block 145 start_pc=0 - v232 Imm(150) -> x0 - terminator Return(v232) (exit_acc=v232) - block 146 start_pc=0 + terminator Jmp(b73) (exit_acc=v231) + block 73 start_pc=0 v233 Imm(0) -> x0 - terminator Jmp(b148) (exit_acc=v233) - block 147 start_pc=0 - v234 Imm(151) -> x0 - terminator Return(v234) (exit_acc=v234) - block 148 start_pc=0 + terminator Jmp(b74) (exit_acc=v233) + block 74 start_pc=0 v235 Imm(0) -> x0 - terminator Jmp(b150) (exit_acc=v235) - block 149 start_pc=0 - v236 Imm(152) -> x0 - terminator Return(v236) (exit_acc=v236) - block 150 start_pc=0 + terminator Jmp(b75) (exit_acc=v235) + block 75 start_pc=0 v237 Imm(0) -> x0 v238 Imm(1) -> x1 v239 Imm(4294967296) -> x1 - terminator Jmp(b152) (exit_acc=v237) - block 151 start_pc=0 - v240 Imm(153) -> x0 - terminator Return(v240) (exit_acc=v240) - block 152 start_pc=0 + terminator Jmp(b76) (exit_acc=v237) + block 76 start_pc=0 v241 Imm(0) -> x0 v242 Imm(9) -> x1 v243 Imm(38654705664) -> x1 - terminator Jmp(b154) (exit_acc=v241) - block 153 start_pc=0 - v244 Imm(154) -> x0 - terminator Return(v244) (exit_acc=v244) - block 154 start_pc=0 + terminator Jmp(b77) (exit_acc=v241) + block 77 start_pc=0 v245 Imm(0) -> x0 - terminator Jmp(b156) (exit_acc=v245) - block 155 start_pc=0 - v246 Imm(160) -> x0 - terminator Return(v246) (exit_acc=v246) - block 156 start_pc=0 + terminator Jmp(b78) (exit_acc=v245) + block 78 start_pc=0 v247 Imm(0) -> x0 - terminator Jmp(b158) (exit_acc=v247) - block 157 start_pc=0 - v248 Imm(161) -> x0 - terminator Return(v248) (exit_acc=v248) - block 158 start_pc=0 + terminator Jmp(b79) (exit_acc=v247) + block 79 start_pc=0 v249 Imm(0) -> x0 v250 Imm(2) -> x1 v251 Imm(8589934592) -> x1 - terminator Jmp(b160) (exit_acc=v249) - block 159 start_pc=0 - v252 Imm(162) -> x0 - terminator Return(v252) (exit_acc=v252) - block 160 start_pc=0 + terminator Jmp(b80) (exit_acc=v249) + block 80 start_pc=0 v253 Imm(0) -> x0 v254 Imm(10) -> x1 v255 Imm(42949672960) -> x1 - terminator Jmp(b162) (exit_acc=v253) - block 161 start_pc=0 - v256 Imm(163) -> x0 - terminator Return(v256) (exit_acc=v256) - block 162 start_pc=0 + terminator Jmp(b81) (exit_acc=v253) + block 81 start_pc=0 v257 Imm(0) -> x0 v258 Imm(12) -> x1 v259 Imm(51539607552) -> x1 - terminator Jmp(b164) (exit_acc=v257) + terminator Jmp(b82) (exit_acc=v257) + block 82 start_pc=0 + v261 Imm(0) -> x0 + terminator Return(v261) (exit_acc=v261) + block 83 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 84 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 85 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 86 start_pc=0 + v12 Imm(4) -> x0 + terminator Return(v12) (exit_acc=v12) + block 87 start_pc=0 + v16 Imm(5) -> x0 + terminator Return(v16) (exit_acc=v16) + block 88 start_pc=0 + v20 Imm(6) -> x0 + terminator Return(v20) (exit_acc=v20) + block 89 start_pc=0 + v24 Imm(7) -> x0 + terminator Return(v24) (exit_acc=v24) + block 90 start_pc=0 + v28 Imm(8) -> x0 + terminator Return(v28) (exit_acc=v28) + block 91 start_pc=0 + v30 Imm(10) -> x0 + terminator Return(v30) (exit_acc=v30) + block 92 start_pc=0 + v32 Imm(11) -> x0 + terminator Return(v32) (exit_acc=v32) + block 93 start_pc=0 + v36 Imm(12) -> x0 + terminator Return(v36) (exit_acc=v36) + block 94 start_pc=0 + v40 Imm(13) -> x0 + terminator Return(v40) (exit_acc=v40) + block 95 start_pc=0 + v44 Imm(14) -> x0 + terminator Return(v44) (exit_acc=v44) + block 96 start_pc=0 + v46 Imm(20) -> x0 + terminator Return(v46) (exit_acc=v46) + block 97 start_pc=0 + v48 Imm(21) -> x0 + terminator Return(v48) (exit_acc=v48) + block 98 start_pc=0 + v52 Imm(22) -> x0 + terminator Return(v52) (exit_acc=v52) + block 99 start_pc=0 + v56 Imm(23) -> x0 + terminator Return(v56) (exit_acc=v56) + block 100 start_pc=0 + v58 Imm(30) -> x0 + terminator Return(v58) (exit_acc=v58) + block 101 start_pc=0 + v60 Imm(31) -> x0 + terminator Return(v60) (exit_acc=v60) + block 102 start_pc=0 + v64 Imm(32) -> x0 + terminator Return(v64) (exit_acc=v64) + block 103 start_pc=0 + v68 Imm(33) -> x0 + terminator Return(v68) (exit_acc=v68) + block 104 start_pc=0 + v70 Imm(40) -> x0 + terminator Return(v70) (exit_acc=v70) + block 105 start_pc=0 + v72 Imm(41) -> x0 + terminator Return(v72) (exit_acc=v72) + block 106 start_pc=0 + v76 Imm(42) -> x0 + terminator Return(v76) (exit_acc=v76) + block 107 start_pc=0 + v80 Imm(43) -> x0 + terminator Return(v80) (exit_acc=v80) + block 108 start_pc=0 + v82 Imm(50) -> x0 + terminator Return(v82) (exit_acc=v82) + block 109 start_pc=0 + v84 Imm(51) -> x0 + terminator Return(v84) (exit_acc=v84) + block 110 start_pc=0 + v86 Imm(52) -> x0 + terminator Return(v86) (exit_acc=v86) + block 111 start_pc=0 + v90 Imm(53) -> x0 + terminator Return(v90) (exit_acc=v90) + block 112 start_pc=0 + v92 Imm(60) -> x0 + terminator Return(v92) (exit_acc=v92) + block 113 start_pc=0 + v94 Imm(61) -> x0 + terminator Return(v94) (exit_acc=v94) + block 114 start_pc=0 + v96 Imm(62) -> x0 + terminator Return(v96) (exit_acc=v96) + block 115 start_pc=0 + v100 Imm(63) -> x0 + terminator Return(v100) (exit_acc=v100) + block 116 start_pc=0 + v104 Imm(64) -> x0 + terminator Return(v104) (exit_acc=v104) + block 117 start_pc=0 + v106 Imm(70) -> x0 + terminator Return(v106) (exit_acc=v106) + block 118 start_pc=0 + v108 Imm(71) -> x0 + terminator Return(v108) (exit_acc=v108) + block 119 start_pc=0 + v112 Imm(72) -> x0 + terminator Return(v112) (exit_acc=v112) + block 120 start_pc=0 + v116 Imm(73) -> x0 + terminator Return(v116) (exit_acc=v116) + block 121 start_pc=0 + v120 Imm(74) -> x0 + terminator Return(v120) (exit_acc=v120) + block 122 start_pc=0 + v124 Imm(75) -> x0 + terminator Return(v124) (exit_acc=v124) + block 123 start_pc=0 + v128 Imm(76) -> x0 + terminator Return(v128) (exit_acc=v128) + block 124 start_pc=0 + v132 Imm(77) -> x0 + terminator Return(v132) (exit_acc=v132) + block 125 start_pc=0 + v134 Imm(80) -> x0 + terminator Return(v134) (exit_acc=v134) + block 126 start_pc=0 + v136 Imm(81) -> x0 + terminator Return(v136) (exit_acc=v136) + block 127 start_pc=0 + v140 Imm(82) -> x0 + terminator Return(v140) (exit_acc=v140) + block 128 start_pc=0 + v144 Imm(83) -> x0 + terminator Return(v144) (exit_acc=v144) + block 129 start_pc=0 + v146 Imm(90) -> x0 + terminator Return(v146) (exit_acc=v146) + block 130 start_pc=0 + v148 Imm(91) -> x0 + terminator Return(v148) (exit_acc=v148) + block 131 start_pc=0 + v152 Imm(92) -> x0 + terminator Return(v152) (exit_acc=v152) + block 132 start_pc=0 + v156 Imm(93) -> x0 + terminator Return(v156) (exit_acc=v156) + block 133 start_pc=0 + v160 Imm(94) -> x0 + terminator Return(v160) (exit_acc=v160) + block 134 start_pc=0 + v164 Imm(95) -> x0 + terminator Return(v164) (exit_acc=v164) + block 135 start_pc=0 + v168 Imm(96) -> x0 + terminator Return(v168) (exit_acc=v168) + block 136 start_pc=0 + v172 Imm(97) -> x0 + terminator Return(v172) (exit_acc=v172) + block 137 start_pc=0 + v174 Imm(100) -> x0 + terminator Return(v174) (exit_acc=v174) + block 138 start_pc=0 + v176 Imm(101) -> x0 + terminator Return(v176) (exit_acc=v176) + block 139 start_pc=0 + v180 Imm(102) -> x0 + terminator Return(v180) (exit_acc=v180) + block 140 start_pc=0 + v184 Imm(103) -> x0 + terminator Return(v184) (exit_acc=v184) + block 141 start_pc=0 + v188 Imm(104) -> x0 + terminator Return(v188) (exit_acc=v188) + block 142 start_pc=0 + v192 Imm(105) -> x0 + terminator Return(v192) (exit_acc=v192) + block 143 start_pc=0 + v196 Imm(106) -> x0 + terminator Return(v196) (exit_acc=v196) + block 144 start_pc=0 + v200 Imm(107) -> x0 + terminator Return(v200) (exit_acc=v200) + block 145 start_pc=0 + v202 Imm(110) -> x0 + terminator Return(v202) (exit_acc=v202) + block 146 start_pc=0 + v206 Imm(111) -> x0 + terminator Return(v206) (exit_acc=v206) + block 147 start_pc=0 + v208 Imm(120) -> x0 + terminator Return(v208) (exit_acc=v208) + block 148 start_pc=0 + v212 Imm(121) -> x0 + terminator Return(v212) (exit_acc=v212) + block 149 start_pc=0 + v214 Imm(130) -> x0 + terminator Return(v214) (exit_acc=v214) + block 150 start_pc=0 + v218 Imm(131) -> x0 + terminator Return(v218) (exit_acc=v218) + block 151 start_pc=0 + v220 Imm(140) -> x0 + terminator Return(v220) (exit_acc=v220) + block 152 start_pc=0 + v222 Imm(141) -> x0 + terminator Return(v222) (exit_acc=v222) + block 153 start_pc=0 + v226 Imm(142) -> x0 + terminator Return(v226) (exit_acc=v226) + block 154 start_pc=0 + v230 Imm(143) -> x0 + terminator Return(v230) (exit_acc=v230) + block 155 start_pc=0 + v232 Imm(150) -> x0 + terminator Return(v232) (exit_acc=v232) + block 156 start_pc=0 + v234 Imm(151) -> x0 + terminator Return(v234) (exit_acc=v234) + block 157 start_pc=0 + v236 Imm(152) -> x0 + terminator Return(v236) (exit_acc=v236) + block 158 start_pc=0 + v240 Imm(153) -> x0 + terminator Return(v240) (exit_acc=v240) + block 159 start_pc=0 + v244 Imm(154) -> x0 + terminator Return(v244) (exit_acc=v244) + block 160 start_pc=0 + v246 Imm(160) -> x0 + terminator Return(v246) (exit_acc=v246) + block 161 start_pc=0 + v248 Imm(161) -> x0 + terminator Return(v248) (exit_acc=v248) + block 162 start_pc=0 + v252 Imm(162) -> x0 + terminator Return(v252) (exit_acc=v252) block 163 start_pc=0 + v256 Imm(163) -> x0 + terminator Return(v256) (exit_acc=v256) + block 164 start_pc=0 v260 Imm(164) -> x0 terminator Return(v260) (exit_acc=v260) - block 164 start_pc=0 - v261 Imm(0) -> x0 - terminator Return(v261) (exit_acc=v261) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_linked_list.ssa b/tests/snapshots/ssa/struct_linked_list.ssa index c59ed1f7c..129972782 100644 --- a/tests/snapshots/ssa/struct_linked_list.ssa +++ b/tests/snapshots/ssa/struct_linked_list.ssa @@ -9,57 +9,121 @@ fn ent_pc=5 n_params=0 variadic=false locals=5 v3 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x3 - v5 Phi { incoming=[b0:v1, b2:v12], kind=I64 } -> x12 - v6 Extend { value=v4, kind=I32 } -> x0 - v7 BinopI { op=lt, lhs=v6, rhs_imm=5 } -> x0 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) - block 2 start_pc=0 - v8 Extend { value=v4, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x3 + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(16) -> x7 + v7 CallExt { binding_idx=0, args=[v6], fp_arg_mask=0x0 } -> x12 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-2, kind=I64 } -> x0 v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + v11 Store { addr=v7, disp=0, value=v10, kind=I32 } -> - + v12 LoadLocal { off=-2, kind=I64 } -> x0 + v13 BinopI { op=add, lhs=v7, rhs_imm=8 } -> x0 + v14 LoadLocal { off=-1, kind=I64 } -> x0 + v15 Store { addr=v7, disp=8, value=v1, kind=I64 } -> - + v16 LoadLocal { off=-2, kind=I64 } -> x0 + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + v19 Imm(1) -> x0 + v20 Imm(0) -> x0 + v21 Imm(1) -> x0 + v22 Imm(1) -> x0 + v23 Imm(16) -> x7 + v24 CallExt { binding_idx=0, args=[v23], fp_arg_mask=0x0 } -> x3 + v25 Imm(0) -> x0 + v26 LoadLocal { off=-2, kind=I64 } -> x0 + v27 Imm(1) -> x0 + v28 Store { addr=v24, disp=0, value=v27, kind=I32 } -> - + v29 LoadLocal { off=-2, kind=I64 } -> x0 + v30 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x0 + v31 LoadLocal { off=-1, kind=I64 } -> x0 + v32 Store { addr=v24, disp=8, value=v7, kind=I64 } -> - + v33 LoadLocal { off=-2, kind=I64 } -> x0 + v34 Imm(0) -> x0 + v35 Imm(1) -> x0 + v36 Imm(2) -> x0 + v37 Imm(0) -> x0 + v38 Imm(2) -> x0 + v39 Imm(1) -> x0 + v40 Imm(16) -> x7 + v41 CallExt { binding_idx=0, args=[v40], fp_arg_mask=0x0 } -> x12 + v42 Imm(0) -> x0 + v43 LoadLocal { off=-2, kind=I64 } -> x0 + v44 Imm(2) -> x0 + v45 Store { addr=v41, disp=0, value=v44, kind=I32 } -> - + v46 LoadLocal { off=-2, kind=I64 } -> x0 + v47 BinopI { op=add, lhs=v41, rhs_imm=8 } -> x0 + v48 LoadLocal { off=-1, kind=I64 } -> x0 + v49 Store { addr=v41, disp=8, value=v24, kind=I64 } -> - + v50 LoadLocal { off=-2, kind=I64 } -> x0 + v51 Imm(0) -> x0 + v52 Imm(2) -> x0 + v53 Imm(3) -> x0 + v54 Imm(0) -> x0 + v55 Imm(3) -> x0 + v56 Imm(1) -> x0 + v57 Imm(16) -> x7 + v58 CallExt { binding_idx=0, args=[v57], fp_arg_mask=0x0 } -> x3 + v59 Imm(0) -> x0 + v60 LoadLocal { off=-2, kind=I64 } -> x0 + v61 Imm(3) -> x0 + v62 Store { addr=v58, disp=0, value=v61, kind=I32 } -> - + v63 LoadLocal { off=-2, kind=I64 } -> x0 + v64 BinopI { op=add, lhs=v58, rhs_imm=8 } -> x0 + v65 LoadLocal { off=-1, kind=I64 } -> x0 + v66 Store { addr=v58, disp=8, value=v41, kind=I64 } -> - + v67 LoadLocal { off=-2, kind=I64 } -> x0 + v68 Imm(0) -> x0 + v69 Imm(3) -> x0 + v70 Imm(4) -> x0 + v71 Imm(0) -> x0 + v72 Imm(4) -> x0 + v73 Imm(1) -> x0 + v74 Imm(16) -> x7 + v75 CallExt { binding_idx=0, args=[v74], fp_arg_mask=0x0 } -> x2 + v76 Imm(0) -> x0 + v77 LoadLocal { off=-2, kind=I64 } -> x0 + v78 Imm(4) -> x0 + v79 Store { addr=v75, disp=0, value=v78, kind=I32 } -> - + v80 LoadLocal { off=-2, kind=I64 } -> x0 + v81 BinopI { op=add, lhs=v75, rhs_imm=8 } -> x0 + v82 LoadLocal { off=-1, kind=I64 } -> x0 + v83 Store { addr=v75, disp=8, value=v58, kind=I64 } -> - + v84 LoadLocal { off=-2, kind=I64 } -> x0 + v85 Imm(0) -> x0 + v86 Imm(4) -> x0 + v87 Imm(5) -> x0 + v88 Imm(0) -> x0 + v89 Imm(5) -> x0 + v90 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v90) + block 2 start_pc=0 + v91 Imm(0) -> x1 + v92 Imm(0) -> x0 + v93 LoadLocal { off=-1, kind=I64 } -> x0 + v94 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v75) block 3 start_pc=0 - v11 Imm(16) -> x7 - v12 CallExt { binding_idx=0, args=[v11], fp_arg_mask=0x0 } -> x1 - v13 Imm(0) -> x0 - v14 LoadLocal { off=-2, kind=I64 } -> x0 - v15 Extend { value=v4, kind=I32 } -> x0 - v16 Store { addr=v12, disp=0, value=v4, kind=I32 } -> - - v17 LoadLocal { off=-2, kind=I64 } -> x0 - v18 BinopI { op=add, lhs=v12, rhs_imm=8 } -> x0 - v19 LoadLocal { off=-1, kind=I64 } -> x0 - v20 Store { addr=v12, disp=8, value=v5, kind=I64 } -> - - v21 LoadLocal { off=-2, kind=I64 } -> x0 - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v12) + v99 Extend { value=v95, kind=I32 } -> x0 + v100 LoadLocal { off=-2, kind=I64 } -> x0 + v101 Load { addr=v96, disp=0, kind=I32 } -> x0 + v102 Binop { op=add, lhs=v95, rhs=v101 } -> x1 + v103 BinopI { op=shl, lhs=v102, rhs_imm=32 } -> x0 + v104 Extend { value=v102, kind=I32 } -> x0 + v105 Imm(0) -> x0 + v106 BinopI { op=add, lhs=v96, rhs_imm=8 } -> x0 + v107 Load { addr=v96, disp=8, kind=I64 } -> x2 + v108 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v107) block 4 start_pc=0 - v23 Imm(0) -> x1 - v24 Imm(0) -> x0 - v25 LoadLocal { off=-1, kind=I64 } -> x0 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v5) + v95 Phi { incoming=[b2:v91, b3:v102], kind=I64 } -> x1 + v96 Phi { incoming=[b2:v75, b3:v107], kind=I64 } -> x2 + v97 LoadLocal { off=-2, kind=I64 } -> x0 + v98 BinopI { op=ne, lhs=v96, rhs_imm=0 } -> x0 + terminator Bnz { cond=v98, target=b3, fall=b5 } (exit_acc=v98) block 5 start_pc=0 - v27 Phi { incoming=[b4:v23, b6:v34], kind=I64 } -> x1 - v28 Phi { incoming=[b4:v5, b6:v39], kind=I64 } -> x12 - v29 LoadLocal { off=-2, kind=I64 } -> x0 - v30 BinopI { op=ne, lhs=v28, rhs_imm=0 } -> x0 - terminator Bz { cond=v30, target=b7, fall=b6 } (exit_acc=v30) - block 6 start_pc=0 - v31 Extend { value=v27, kind=I32 } -> x0 - v32 LoadLocal { off=-2, kind=I64 } -> x0 - v33 Load { addr=v28, disp=0, kind=I32 } -> x0 - v34 Binop { op=add, lhs=v27, rhs=v33 } -> x1 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x0 - v36 Extend { value=v34, kind=I32 } -> x0 - v37 Imm(0) -> x0 - v38 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x0 - v39 Load { addr=v28, disp=8, kind=I64 } -> x12 - v40 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v39) - block 7 start_pc=0 - v41 Extend { value=v27, kind=I32 } -> x0 - terminator Return(v41) (exit_acc=v41) + v109 Extend { value=v95, kind=I32 } -> x0 + terminator Return(v109) (exit_acc=v109) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_member_brace_wrapped_string.ssa b/tests/snapshots/ssa/struct_member_brace_wrapped_string.ssa index cd8fc85cc..9ef4a0804 100644 --- a/tests/snapshots/ssa/struct_member_brace_wrapped_string.ssa +++ b/tests/snapshots/ssa/struct_member_brace_wrapped_string.ssa @@ -10,13 +10,25 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b6, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -24,31 +36,19 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 LoadLocal { off=3, kind=I64 } -> x1 v19 Load { addr=v6, disp=0, kind=I8 } -> x1 v20 Binop { op=eq, lhs=v17, rhs=v19 } -> x0 terminator Return(v20) (exit_acc=v20) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b6:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=40 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ImmData(8) -> x0 @@ -63,19 +63,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=40 block 2 start_pc=0 v7 ImmData(280) -> x0 v8 Load { addr=v7, disp=0, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=7 } -> x3 + v9 BinopI { op=ne, lhs=v8, rhs_imm=7 } -> x1 v10 Imm(0) -> x0 - terminator Bnz { cond=v9, target=b13, fall=b3 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b14, fall=b3 } (exit_acc=v9) block 3 start_pc=0 v11 ImmData(280) -> x0 v12 BinopI { op=add, lhs=v11, rhs_imm=4 } -> x7 v13 ImmData(317) -> x6 v14 Call { target_pc=0, args=[v12, v13], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x3 + v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x1 v16 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v15) block 4 start_pc=0 - v17 Phi { incoming=[b13:v9, b3:v15], kind=I64 } -> x3 + v17 Phi { incoming=[b14:v9, b3:v15], kind=I64 } -> x1 v18 LoadLocal { off=-39, kind=I64 } -> x0 terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) block 5 start_pc=0 @@ -102,7 +102,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=40 v33 Load { addr=v32, disp=0, kind=I32 } -> x0 v34 BinopI { op=ne, lhs=v33, rhs_imm=9 } -> x1 v35 Imm(0) -> x0 - terminator Bnz { cond=v34, target=b14, fall=b9 } (exit_acc=v34) + terminator Bnz { cond=v34, target=b13, fall=b9 } (exit_acc=v34) block 9 start_pc=0 v36 LocalAddr(-36) -> x0 v37 BinopI { op=add, lhs=v36, rhs_imm=4 } -> x7 @@ -112,7 +112,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=40 v41 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v40) block 10 start_pc=0 - v42 Phi { incoming=[b14:v34, b9:v40], kind=I64 } -> x1 + v42 Phi { incoming=[b13:v34, b9:v40], kind=I64 } -> x1 v43 LoadLocal { off=-40, kind=I64 } -> x0 terminator Bz { cond=v42, target=b12, fall=b11 } (exit_acc=v42) block 11 start_pc=0 @@ -122,9 +122,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=40 v45 Imm(0) -> x0 terminator Return(v45) (exit_acc=v45) block 13 start_pc=0 - terminator Jmp(b4) - block 14 start_pc=0 terminator Jmp(b10) + block 14 start_pc=0 + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_multi_byval.ssa b/tests/snapshots/ssa/struct_multi_byval.ssa index 7c33021a1..fd84f7b26 100644 --- a/tests/snapshots/ssa/struct_multi_byval.ssa +++ b/tests/snapshots/ssa/struct_multi_byval.ssa @@ -176,16 +176,16 @@ fn ent_pc=3 n_params=2 variadic=false locals=3 v2 LoadLocal { off=3, kind=I32 } -> x1 v3 Store { addr=v1, disp=0, value=v2, kind=I32 } -> - v4 LocalAddr(-3) -> x0 - v5 BinopI { op=add, lhs=v4, rhs_imm=4 } -> x1 - v6 LoadLocal { off=3, kind=I32 } -> x1 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x2 - v9 Extend { value=v7, kind=I32 } -> x2 + v5 BinopI { op=add, lhs=v4, rhs_imm=4 } -> x2 + v6 LoadLocal { off=3, kind=I32 } -> x2 + v7 BinopI { op=add, lhs=v2, rhs_imm=1 } -> x2 + v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x6 + v9 Extend { value=v7, kind=I32 } -> x6 v10 Store { addr=v4, disp=4, value=v7, kind=I32 } -> - v11 LocalAddr(-3) -> x0 - v12 BinopI { op=add, lhs=v11, rhs_imm=8 } -> x1 - v13 LoadLocal { off=3, kind=I32 } -> x1 - v14 BinopI { op=add, lhs=v13, rhs_imm=2 } -> x1 + v12 BinopI { op=add, lhs=v11, rhs_imm=8 } -> x2 + v13 LoadLocal { off=3, kind=I32 } -> x2 + v14 BinopI { op=add, lhs=v2, rhs_imm=2 } -> x1 v15 BinopI { op=shl, lhs=v14, rhs_imm=32 } -> x2 v16 Extend { value=v14, kind=I32 } -> x2 v17 Store { addr=v11, disp=8, value=v14, kind=I32 } -> - @@ -217,7 +217,7 @@ fn ent_pc=3 n_params=2 variadic=false locals=3 ; --- SSA dump (ok=true) ent_pc=4 --- ; name=main fn ent_pc=4 n_params=0 variadic=false locals=42 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 @@ -253,34 +253,34 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 terminator Return(v28) (exit_acc=v28) block 2 start_pc=0 v29 Imm(50) -> x0 - v30 Extend { value=v29, kind=I32 } -> x1 + v30 Imm(50) -> x0 v31 Imm(0) -> x1 v32 LocalAddr(-25) -> x1 - v33 Store { addr=v32, disp=0, value=v29, kind=I32 } -> - - v34 LocalAddr(-25) -> x1 - v35 BinopI { op=add, lhs=v34, rhs_imm=4 } -> x2 - v36 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x0 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x2 - v38 Extend { value=v36, kind=I32 } -> x2 - v39 Store { addr=v34, disp=4, value=v36, kind=I32 } -> - + v33 Store { addr=v32, disp=0, value=v30, kind=I32 } -> - + v34 LocalAddr(-25) -> x0 + v35 BinopI { op=add, lhs=v34, rhs_imm=4 } -> x1 + v36 Imm(51) -> x1 + v37 Imm(219043332096) -> x1 + v38 Imm(51) -> x1 + v39 Store { addr=v34, disp=4, value=v38, kind=I32 } -> - v40 LocalAddr(-25) -> x0 v41 LocalAddr(-25) -> x0 v42 LocalAddr(-10) -> x1 v43 Mcpy { dst=v42, src=v41, size=8 } -> x0 v44 LocalAddr(-10) -> x0 v45 Load { addr=v44, disp=0, kind=I32 } -> x0 - v46 BinopI { op=ne, lhs=v45, rhs_imm=50 } -> x3 + v46 BinopI { op=ne, lhs=v45, rhs_imm=50 } -> x1 v47 Imm(0) -> x0 - terminator Bnz { cond=v46, target=b31, fall=b3 } (exit_acc=v46) + terminator Bnz { cond=v46, target=b40, fall=b3 } (exit_acc=v46) block 3 start_pc=0 v48 LocalAddr(-10) -> x0 v49 BinopI { op=add, lhs=v48, rhs_imm=4 } -> x1 v50 Load { addr=v48, disp=4, kind=I32 } -> x0 - v51 BinopI { op=ne, lhs=v50, rhs_imm=51 } -> x3 + v51 BinopI { op=ne, lhs=v50, rhs_imm=51 } -> x1 v52 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v51) block 4 start_pc=0 - v53 Phi { incoming=[b31:v46, b3:v51], kind=I64 } -> x3 + v53 Phi { incoming=[b40:v46, b3:v51], kind=I64 } -> x1 v54 LoadLocal { off=-26, kind=I64 } -> x0 terminator Bz { cond=v53, target=b6, fall=b5 } (exit_acc=v53) block 5 start_pc=0 @@ -288,28 +288,28 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 terminator Return(v55) (exit_acc=v55) block 6 start_pc=0 v56 Imm(60) -> x0 - v57 Extend { value=v56, kind=I32 } -> x1 + v57 Imm(60) -> x0 v58 Imm(0) -> x1 v59 LocalAddr(-28) -> x1 - v60 Store { addr=v59, disp=0, value=v56, kind=I32 } -> - - v61 LocalAddr(-28) -> x1 - v62 BinopI { op=add, lhs=v61, rhs_imm=4 } -> x2 - v63 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x2 - v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x6 - v65 Extend { value=v63, kind=I32 } -> x6 - v66 Store { addr=v61, disp=4, value=v63, kind=I32 } -> - - v67 LocalAddr(-28) -> x1 - v68 BinopI { op=add, lhs=v67, rhs_imm=8 } -> x2 - v69 BinopI { op=add, lhs=v56, rhs_imm=2 } -> x2 - v70 BinopI { op=shl, lhs=v69, rhs_imm=32 } -> x6 - v71 Extend { value=v69, kind=I32 } -> x6 - v72 Store { addr=v67, disp=8, value=v69, kind=I32 } -> - - v73 LocalAddr(-28) -> x1 - v74 BinopI { op=add, lhs=v73, rhs_imm=12 } -> x2 - v75 BinopI { op=add, lhs=v56, rhs_imm=3 } -> x0 - v76 BinopI { op=shl, lhs=v75, rhs_imm=32 } -> x2 - v77 Extend { value=v75, kind=I32 } -> x2 - v78 Store { addr=v73, disp=12, value=v75, kind=I32 } -> - + v60 Store { addr=v59, disp=0, value=v57, kind=I32 } -> - + v61 LocalAddr(-28) -> x0 + v62 BinopI { op=add, lhs=v61, rhs_imm=4 } -> x1 + v63 Imm(61) -> x1 + v64 Imm(261993005056) -> x1 + v65 Imm(61) -> x1 + v66 Store { addr=v61, disp=4, value=v65, kind=I32 } -> - + v67 LocalAddr(-28) -> x0 + v68 BinopI { op=add, lhs=v67, rhs_imm=8 } -> x1 + v69 Imm(62) -> x1 + v70 Imm(266287972352) -> x1 + v71 Imm(62) -> x1 + v72 Store { addr=v67, disp=8, value=v71, kind=I32 } -> - + v73 LocalAddr(-28) -> x0 + v74 BinopI { op=add, lhs=v73, rhs_imm=12 } -> x1 + v75 Imm(63) -> x1 + v76 Imm(270582939648) -> x1 + v77 Imm(63) -> x1 + v78 Store { addr=v73, disp=12, value=v77, kind=I32 } -> - v79 LocalAddr(-28) -> x0 v80 LocalAddr(-28) -> x0 v81 LocalAddr(-13) -> x1 @@ -317,45 +317,45 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v83 LocalAddr(-13) -> x0 v84 Load { addr=v83, disp=0, kind=I32 } -> x0 v85 BinopI { op=ne, lhs=v84, rhs_imm=60 } -> x0 - v86 Imm(1) -> x3 + v86 Imm(1) -> x2 v87 Imm(0) -> x1 - terminator Bnz { cond=v85, target=b32, fall=b7 } (exit_acc=v85) + terminator Bnz { cond=v85, target=b39, fall=b7 } (exit_acc=v85) block 7 start_pc=0 v88 LocalAddr(-13) -> x0 v89 BinopI { op=add, lhs=v88, rhs_imm=4 } -> x1 v90 Load { addr=v88, disp=4, kind=I32 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=61 } -> x0 - v92 BinopI { op=ne, lhs=v91, rhs_imm=0 } -> x3 + v92 BinopI { op=ne, lhs=v91, rhs_imm=0 } -> x2 v93 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v92) block 8 start_pc=0 - v94 Phi { incoming=[b32:v86, b7:v92], kind=I64 } -> x3 + v94 Phi { incoming=[b39:v86, b7:v92], kind=I64 } -> x2 v95 LoadLocal { off=-31, kind=I64 } -> x0 - v96 Imm(1) -> x12 + v96 Imm(1) -> x1 v97 Imm(0) -> x0 - terminator Bnz { cond=v94, target=b33, fall=b9 } (exit_acc=v94) + terminator Bnz { cond=v94, target=b38, fall=b9 } (exit_acc=v94) block 9 start_pc=0 v98 LocalAddr(-13) -> x0 v99 BinopI { op=add, lhs=v98, rhs_imm=8 } -> x1 v100 Load { addr=v98, disp=8, kind=I32 } -> x0 v101 BinopI { op=ne, lhs=v100, rhs_imm=62 } -> x0 - v102 BinopI { op=ne, lhs=v101, rhs_imm=0 } -> x12 + v102 BinopI { op=ne, lhs=v101, rhs_imm=0 } -> x1 v103 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v102) block 10 start_pc=0 - v104 Phi { incoming=[b33:v96, b9:v102], kind=I64 } -> x12 + v104 Phi { incoming=[b38:v96, b9:v102], kind=I64 } -> x1 v105 LoadLocal { off=-30, kind=I64 } -> x0 v106 Imm(0) -> x0 - terminator Bnz { cond=v104, target=b34, fall=b11 } (exit_acc=v104) + terminator Bnz { cond=v104, target=b37, fall=b11 } (exit_acc=v104) block 11 start_pc=0 v107 LocalAddr(-13) -> x0 v108 BinopI { op=add, lhs=v107, rhs_imm=12 } -> x1 v109 Load { addr=v107, disp=12, kind=I32 } -> x0 - v110 BinopI { op=ne, lhs=v109, rhs_imm=63 } -> x12 + v110 BinopI { op=ne, lhs=v109, rhs_imm=63 } -> x1 v111 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v110) block 12 start_pc=0 - v112 Phi { incoming=[b34:v104, b11:v110], kind=I64 } -> x12 + v112 Phi { incoming=[b37:v104, b11:v110], kind=I64 } -> x1 v113 LoadLocal { off=-29, kind=I64 } -> x0 terminator Bz { cond=v112, target=b14, fall=b13 } (exit_acc=v112) block 13 start_pc=0 @@ -375,7 +375,7 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v125 BinopI { op=ne, lhs=v124, rhs_imm=70 } -> x0 v126 Imm(1) -> x2 v127 Imm(0) -> x1 - terminator Bnz { cond=v125, target=b35, fall=b15 } (exit_acc=v125) + terminator Bnz { cond=v125, target=b36, fall=b15 } (exit_acc=v125) block 15 start_pc=0 v128 LocalAddr(-18) -> x0 v129 BinopI { op=add, lhs=v128, rhs_imm=4 } -> x1 @@ -385,11 +385,11 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v133 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v132) block 16 start_pc=0 - v134 Phi { incoming=[b35:v126, b15:v132], kind=I64 } -> x2 + v134 Phi { incoming=[b36:v126, b15:v132], kind=I64 } -> x2 v135 LoadLocal { off=-40, kind=I64 } -> x0 v136 Imm(1) -> x1 v137 Imm(0) -> x0 - terminator Bnz { cond=v134, target=b36, fall=b17 } (exit_acc=v134) + terminator Bnz { cond=v134, target=b35, fall=b17 } (exit_acc=v134) block 17 start_pc=0 v138 LocalAddr(-18) -> x0 v139 BinopI { op=add, lhs=v138, rhs_imm=8 } -> x1 @@ -399,11 +399,11 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v143 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v142) block 18 start_pc=0 - v144 Phi { incoming=[b36:v136, b17:v142], kind=I64 } -> x1 + v144 Phi { incoming=[b35:v136, b17:v142], kind=I64 } -> x1 v145 LoadLocal { off=-39, kind=I64 } -> x0 v146 Imm(1) -> x2 v147 Imm(0) -> x0 - terminator Bnz { cond=v144, target=b37, fall=b19 } (exit_acc=v144) + terminator Bnz { cond=v144, target=b34, fall=b19 } (exit_acc=v144) block 19 start_pc=0 v148 LocalAddr(-18) -> x0 v149 BinopI { op=add, lhs=v148, rhs_imm=12 } -> x1 @@ -413,11 +413,11 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v153 Imm(0) -> x0 terminator Jmp(b20) (exit_acc=v152) block 20 start_pc=0 - v154 Phi { incoming=[b37:v146, b19:v152], kind=I64 } -> x2 + v154 Phi { incoming=[b34:v146, b19:v152], kind=I64 } -> x2 v155 LoadLocal { off=-38, kind=I64 } -> x0 v156 Imm(1) -> x1 v157 Imm(0) -> x0 - terminator Bnz { cond=v154, target=b38, fall=b21 } (exit_acc=v154) + terminator Bnz { cond=v154, target=b33, fall=b21 } (exit_acc=v154) block 21 start_pc=0 v158 LocalAddr(-18) -> x0 v159 BinopI { op=add, lhs=v158, rhs_imm=16 } -> x1 @@ -427,10 +427,10 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v163 Imm(0) -> x0 terminator Jmp(b22) (exit_acc=v162) block 22 start_pc=0 - v164 Phi { incoming=[b38:v156, b21:v162], kind=I64 } -> x1 + v164 Phi { incoming=[b33:v156, b21:v162], kind=I64 } -> x1 v165 LoadLocal { off=-37, kind=I64 } -> x0 v166 Imm(0) -> x0 - terminator Bnz { cond=v164, target=b39, fall=b23 } (exit_acc=v164) + terminator Bnz { cond=v164, target=b32, fall=b23 } (exit_acc=v164) block 23 start_pc=0 v167 LocalAddr(-18) -> x0 v168 BinopI { op=add, lhs=v167, rhs_imm=20 } -> x1 @@ -439,7 +439,7 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v171 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v170) block 24 start_pc=0 - v172 Phi { incoming=[b39:v164, b23:v170], kind=I64 } -> x1 + v172 Phi { incoming=[b32:v164, b23:v170], kind=I64 } -> x1 v173 LoadLocal { off=-36, kind=I64 } -> x0 terminator Bz { cond=v172, target=b26, fall=b25 } (exit_acc=v172) block 25 start_pc=0 @@ -472,7 +472,7 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v198 Load { addr=v197, disp=0, kind=I32 } -> x0 v199 BinopI { op=ne, lhs=v198, rhs_imm=101 } -> x1 v200 Imm(0) -> x0 - terminator Bnz { cond=v199, target=b40, fall=b27 } (exit_acc=v199) + terminator Bnz { cond=v199, target=b31, fall=b27 } (exit_acc=v199) block 27 start_pc=0 v201 LocalAddr(-22) -> x0 v202 BinopI { op=add, lhs=v201, rhs_imm=4 } -> x1 @@ -481,7 +481,7 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v205 Imm(0) -> x0 terminator Jmp(b28) (exit_acc=v204) block 28 start_pc=0 - v206 Phi { incoming=[b40:v199, b27:v204], kind=I64 } -> x1 + v206 Phi { incoming=[b31:v199, b27:v204], kind=I64 } -> x1 v207 LoadLocal { off=-42, kind=I64 } -> x0 terminator Bz { cond=v206, target=b30, fall=b29 } (exit_acc=v206) block 29 start_pc=0 @@ -491,25 +491,25 @@ fn ent_pc=4 n_params=0 variadic=false locals=42 v209 Imm(0) -> x0 terminator Return(v209) (exit_acc=v209) block 31 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b28) block 32 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b24) block 33 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b22) block 34 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b20) block 35 start_pc=0 - terminator Jmp(b16) - block 36 start_pc=0 terminator Jmp(b18) + block 36 start_pc=0 + terminator Jmp(b16) block 37 start_pc=0 - terminator Jmp(b20) + terminator Jmp(b12) block 38 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b10) block 39 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b8) block 40 start_pc=0 - terminator Jmp(b28) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_return_by_value.ssa b/tests/snapshots/ssa/struct_return_by_value.ssa index 28b1ba2a2..073832be3 100644 --- a/tests/snapshots/ssa/struct_return_by_value.ssa +++ b/tests/snapshots/ssa/struct_return_by_value.ssa @@ -28,14 +28,14 @@ fn ent_pc=1 n_params=2 variadic=false locals=3 v2 LoadLocal { off=3, kind=I64 } -> x1 v3 Store { addr=v1, disp=0, value=v2, kind=I64 } -> - v4 LocalAddr(-3) -> x0 - v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x1 - v6 LoadLocal { off=3, kind=I64 } -> x1 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 + v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x2 + v6 LoadLocal { off=3, kind=I64 } -> x2 + v7 BinopI { op=add, lhs=v2, rhs_imm=1 } -> x2 v8 Store { addr=v4, disp=8, value=v7, kind=I64 } -> - v9 LocalAddr(-3) -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x1 - v11 LoadLocal { off=3, kind=I64 } -> x1 - v12 BinopI { op=add, lhs=v11, rhs_imm=2 } -> x1 + v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x2 + v11 LoadLocal { off=3, kind=I64 } -> x2 + v12 BinopI { op=add, lhs=v2, rhs_imm=2 } -> x1 v13 Store { addr=v9, disp=16, value=v12, kind=I64 } -> - v14 LoadLocal { off=2, kind=I64 } -> x0 v15 LocalAddr(-3) -> x1 @@ -128,38 +128,38 @@ fn ent_pc=6 n_params=1 variadic=false locals=1 ; --- SSA dump (ok=true) ent_pc=7 --- ; name=main fn ent_pc=7 n_params=0 variadic=false locals=34 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Extend { value=v1, kind=I32 } -> x1 + v2 Imm(7) -> x0 v3 Imm(0) -> x1 v4 LocalAddr(-18) -> x1 - v5 Store { addr=v4, disp=0, value=v1, kind=I32 } -> - - v6 LocalAddr(-18) -> x1 - v7 BinopI { op=add, lhs=v6, rhs_imm=4 } -> x2 - v8 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v9 BinopI { op=shl, lhs=v8, rhs_imm=32 } -> x2 - v10 Extend { value=v8, kind=I32 } -> x2 - v11 Store { addr=v6, disp=4, value=v8, kind=I32 } -> - + v5 Store { addr=v4, disp=0, value=v2, kind=I32 } -> - + v6 LocalAddr(-18) -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=4 } -> x1 + v8 Imm(8) -> x1 + v9 Imm(34359738368) -> x1 + v10 Imm(8) -> x1 + v11 Store { addr=v6, disp=4, value=v10, kind=I32 } -> - v12 LocalAddr(-18) -> x0 v13 LocalAddr(-18) -> x0 v14 LocalAddr(-1) -> x1 v15 Mcpy { dst=v14, src=v13, size=8 } -> x0 v16 LocalAddr(-1) -> x0 v17 Load { addr=v16, disp=0, kind=I32 } -> x0 - v18 BinopI { op=ne, lhs=v17, rhs_imm=7 } -> x3 + v18 BinopI { op=ne, lhs=v17, rhs_imm=7 } -> x1 v19 Imm(0) -> x0 - terminator Bnz { cond=v18, target=b27, fall=b1 } (exit_acc=v18) + terminator Bnz { cond=v18, target=b31, fall=b1 } (exit_acc=v18) block 1 start_pc=0 v20 LocalAddr(-1) -> x0 v21 BinopI { op=add, lhs=v20, rhs_imm=4 } -> x1 v22 Load { addr=v20, disp=4, kind=I32 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=8 } -> x3 + v23 BinopI { op=ne, lhs=v22, rhs_imm=8 } -> x1 v24 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v23) block 2 start_pc=0 - v25 Phi { incoming=[b27:v18, b1:v23], kind=I64 } -> x3 + v25 Phi { incoming=[b31:v18, b1:v23], kind=I64 } -> x1 v26 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) block 3 start_pc=0 @@ -177,19 +177,19 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 v36 LocalAddr(-5) -> x0 v37 Load { addr=v36, disp=0, kind=I64 } -> x0 v38 BinopI { op=ne, lhs=v37, rhs_imm=10 } -> x0 - v39 Imm(1) -> x3 + v39 Imm(1) -> x2 v40 Imm(0) -> x1 - terminator Bnz { cond=v38, target=b28, fall=b5 } (exit_acc=v38) + terminator Bnz { cond=v38, target=b30, fall=b5 } (exit_acc=v38) block 5 start_pc=0 v41 LocalAddr(-5) -> x0 v42 BinopI { op=add, lhs=v41, rhs_imm=8 } -> x1 v43 Load { addr=v41, disp=8, kind=I64 } -> x0 v44 BinopI { op=ne, lhs=v43, rhs_imm=11 } -> x0 - v45 BinopI { op=ne, lhs=v44, rhs_imm=0 } -> x3 + v45 BinopI { op=ne, lhs=v44, rhs_imm=0 } -> x2 v46 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v45) block 6 start_pc=0 - v47 Phi { incoming=[b28:v39, b5:v45], kind=I64 } -> x3 + v47 Phi { incoming=[b30:v39, b5:v45], kind=I64 } -> x2 v48 LoadLocal { off=-25, kind=I64 } -> x0 v49 Imm(0) -> x0 terminator Bnz { cond=v47, target=b29, fall=b7 } (exit_acc=v47) @@ -197,11 +197,11 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 v50 LocalAddr(-5) -> x0 v51 BinopI { op=add, lhs=v50, rhs_imm=16 } -> x1 v52 Load { addr=v50, disp=16, kind=I64 } -> x0 - v53 BinopI { op=ne, lhs=v52, rhs_imm=12 } -> x3 + v53 BinopI { op=ne, lhs=v52, rhs_imm=12 } -> x2 v54 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v53) block 8 start_pc=0 - v55 Phi { incoming=[b29:v47, b7:v53], kind=I64 } -> x3 + v55 Phi { incoming=[b29:v47, b7:v53], kind=I64 } -> x2 v56 LoadLocal { off=-24, kind=I64 } -> x0 terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) block 9 start_pc=0 @@ -209,16 +209,16 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 terminator Return(v57) (exit_acc=v57) block 10 start_pc=0 v58 Imm(20) -> x0 - v59 Extend { value=v58, kind=I32 } -> x1 + v59 Imm(20) -> x0 v60 Imm(0) -> x1 v61 LocalAddr(-26) -> x1 - v62 Store { addr=v61, disp=0, value=v58, kind=I32 } -> - - v63 LocalAddr(-26) -> x1 - v64 BinopI { op=add, lhs=v63, rhs_imm=4 } -> x2 - v65 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x0 - v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x2 - v67 Extend { value=v65, kind=I32 } -> x2 - v68 Store { addr=v63, disp=4, value=v65, kind=I32 } -> - + v62 Store { addr=v61, disp=0, value=v59, kind=I32 } -> - + v63 LocalAddr(-26) -> x0 + v64 BinopI { op=add, lhs=v63, rhs_imm=4 } -> x1 + v65 Imm(21) -> x1 + v66 Imm(90194313216) -> x1 + v67 Imm(21) -> x1 + v68 Store { addr=v63, disp=4, value=v67, kind=I32 } -> - v69 LocalAddr(-26) -> x0 v70 LocalAddr(-26) -> x0 v71 Load { addr=v70, disp=0, kind=I32 } -> x0 @@ -244,33 +244,33 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 block 14 start_pc=0 v84 LocalAddr(-13) -> x0 v85 Imm(40) -> x1 - v86 Extend { value=v85, kind=I32 } -> x2 + v86 Imm(40) -> x1 v87 Imm(0) -> x2 v88 LocalAddr(-31) -> x2 - v89 Store { addr=v88, disp=0, value=v85, kind=I32 } -> - - v90 LocalAddr(-31) -> x2 - v91 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x6 - v92 BinopI { op=add, lhs=v85, rhs_imm=1 } -> x1 - v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x6 - v94 Extend { value=v92, kind=I32 } -> x6 - v95 Store { addr=v90, disp=4, value=v92, kind=I32 } -> - + v89 Store { addr=v88, disp=0, value=v86, kind=I32 } -> - + v90 LocalAddr(-31) -> x1 + v91 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x2 + v92 Imm(41) -> x2 + v93 Imm(176093659136) -> x2 + v94 Imm(41) -> x2 + v95 Store { addr=v90, disp=4, value=v94, kind=I32 } -> - v96 LocalAddr(-31) -> x1 v97 LocalAddr(-31) -> x1 v98 Mcpy { dst=v84, src=v97, size=8 } -> x0 v99 LocalAddr(-13) -> x0 v100 Load { addr=v99, disp=0, kind=I32 } -> x0 - v101 BinopI { op=ne, lhs=v100, rhs_imm=40 } -> x3 + v101 BinopI { op=ne, lhs=v100, rhs_imm=40 } -> x1 v102 Imm(0) -> x0 - terminator Bnz { cond=v101, target=b30, fall=b15 } (exit_acc=v101) + terminator Bnz { cond=v101, target=b28, fall=b15 } (exit_acc=v101) block 15 start_pc=0 v103 LocalAddr(-13) -> x0 v104 BinopI { op=add, lhs=v103, rhs_imm=4 } -> x1 v105 Load { addr=v103, disp=4, kind=I32 } -> x0 - v106 BinopI { op=ne, lhs=v105, rhs_imm=41 } -> x3 + v106 BinopI { op=ne, lhs=v105, rhs_imm=41 } -> x1 v107 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v106) block 16 start_pc=0 - v108 Phi { incoming=[b30:v101, b15:v106], kind=I64 } -> x3 + v108 Phi { incoming=[b28:v101, b15:v106], kind=I64 } -> x1 v109 LoadLocal { off=-32, kind=I64 } -> x0 terminator Bz { cond=v108, target=b18, fall=b17 } (exit_acc=v108) block 17 start_pc=0 @@ -302,7 +302,7 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 v125 Load { addr=v124, disp=0, kind=I32 } -> x0 v126 BinopI { op=ne, lhs=v125, rhs_imm=7 } -> x1 v127 Imm(0) -> x0 - terminator Bnz { cond=v126, target=b31, fall=b23 } (exit_acc=v126) + terminator Bnz { cond=v126, target=b27, fall=b23 } (exit_acc=v126) block 23 start_pc=0 v128 LocalAddr(-15) -> x0 v129 BinopI { op=add, lhs=v128, rhs_imm=4 } -> x1 @@ -311,7 +311,7 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 v132 Imm(0) -> x0 terminator Jmp(b24) (exit_acc=v131) block 24 start_pc=0 - v133 Phi { incoming=[b31:v126, b23:v131], kind=I64 } -> x1 + v133 Phi { incoming=[b27:v126, b23:v131], kind=I64 } -> x1 v134 LoadLocal { off=-34, kind=I64 } -> x0 terminator Bz { cond=v133, target=b26, fall=b25 } (exit_acc=v133) block 25 start_pc=0 @@ -321,15 +321,15 @@ fn ent_pc=7 n_params=0 variadic=false locals=34 v136 Imm(0) -> x0 terminator Return(v136) (exit_acc=v136) block 27 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b24) block 28 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b16) block 29 start_pc=0 terminator Jmp(b8) block 30 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) block 31 start_pc=0 - terminator Jmp(b24) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_return_reg_computed_goto.ssa b/tests/snapshots/ssa/struct_return_reg_computed_goto.ssa index de3ab14a5..86a83eeba 100644 --- a/tests/snapshots/ssa/struct_return_reg_computed_goto.ssa +++ b/tests/snapshots/ssa/struct_return_reg_computed_goto.ssa @@ -33,7 +33,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 block 1 start_pc=0 v13 Imm(7) -> x0 v14 StoreLocal { off=-1, value=v13, kind=I32 } -> - - v15 LoadLocal { off=-1, kind=I32 } -> x0 + v15 Extend { value=v13, kind=I32 } -> x0 v16 BinopI { op=eq, lhs=v15, rhs_imm=7 } -> x0 terminator Bz { cond=v16, target=b3, fall=b2 } (exit_acc=v16) block 2 start_pc=0 @@ -57,7 +57,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - v3 Imm(0) -> x0 v4 StoreLocal { off=-1, value=v3, kind=I32 } -> - - v5 LoadLocal { off=2, kind=I32 } -> x0 + v5 Extend { value=v1, kind=I32 } -> x0 terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 v6 BlockAddr(block=4) -> x0 @@ -86,7 +86,7 @@ fn ent_pc=2 n_params=1 variadic=false locals=7 block 5 start_pc=0 v22 Imm(2) -> x0 v23 StoreLocal { off=-1, value=v22, kind=I32 } -> - - v24 LoadLocal { off=-1, kind=I32 } -> x0 + v24 Extend { value=v22, kind=I32 } -> x0 v25 BinopI { op=eq, lhs=v24, rhs_imm=2 } -> x0 terminator Bz { cond=v25, target=b7, fall=b6 } (exit_acc=v25) block 6 start_pc=0 diff --git a/tests/snapshots/ssa/struct_return_to_global.ssa b/tests/snapshots/ssa/struct_return_to_global.ssa index 013b2b50f..6486a5dce 100644 --- a/tests/snapshots/ssa/struct_return_to_global.ssa +++ b/tests/snapshots/ssa/struct_return_to_global.ssa @@ -51,100 +51,144 @@ fn ent_pc=2 n_params=0 variadic=false locals=15 v17 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 v18 Load { addr=v3, disp=8, kind=I64 } -> x1 v19 Binop { op=add, lhs=v16, rhs=v18 } -> x0 - v20 Binop { op=add, lhs=v1, rhs=v19 } -> x12 - v21 Imm(0) -> x0 - v22 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + v20 BinopI { op=add, lhs=v19, rhs_imm=0 } -> x0 + v21 Imm(0) -> x1 + v22 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v23 Phi { incoming=[b0:v1, b2:v27], kind=I64 } -> x2 - v24 Extend { value=v23, kind=I32 } -> x0 - v25 BinopI { op=lt, lhs=v24, rhs_imm=4 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) - block 2 start_pc=0 - v26 Extend { value=v23, kind=I32 } -> x0 - v27 BinopI { op=add, lhs=v26, rhs_imm=1 } -> x2 - v28 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v27) - block 3 start_pc=0 - v29 ImmData(40) -> x0 - v30 Extend { value=v23, kind=I32 } -> x1 - v31 BinopI { op=shl, lhs=v30, rhs_imm=4 } -> x6 - v32 Binop { op=add, lhs=v29, rhs=v31 } -> x0 - v33 BinopI { op=mul, lhs=v30, rhs_imm=10 } -> x1 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x6 - v35 Extend { value=v33, kind=I32 } -> x1 - v36 Imm(0) -> x6 - v37 LocalAddr(-14) -> x6 + v29 ImmData(40) -> x6 + v30 Extend { value=v23, kind=I32 } -> x7 + v31 BinopI { op=shl, lhs=v24, rhs_imm=4 } -> x7 + v32 Binop { op=add, lhs=v29, rhs=v31 } -> x6 + v33 BinopI { op=mul, lhs=v24, rhs_imm=10 } -> x7 + v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x8 + v35 Extend { value=v33, kind=I32 } -> x7 + v36 Imm(0) -> x8 + v37 LocalAddr(-14) -> x8 v38 Store { addr=v37, disp=0, value=v35, kind=I64 } -> - - v39 LocalAddr(-14) -> x1 - v40 BinopI { op=add, lhs=v39, rhs_imm=8 } -> x6 - v41 Imm(1) -> x6 + v39 LocalAddr(-14) -> x7 + v40 BinopI { op=add, lhs=v39, rhs_imm=8 } -> x8 + v41 Imm(1) -> x8 v42 Store { addr=v39, disp=8, value=v41, kind=I64 } -> - - v43 LocalAddr(-14) -> x1 - v44 LocalAddr(-14) -> x1 - v45 Mcpy { dst=v32, src=v44, size=16 } -> x0 + v43 LocalAddr(-14) -> x7 + v44 LocalAddr(-14) -> x7 + v45 Mcpy { dst=v32, src=v44, size=16 } -> x6 terminator Jmp(b2) (exit_acc=v45) + block 2 start_pc=0 + v26 Extend { value=v23, kind=I32 } -> x2 + v27 BinopI { op=add, lhs=v24, rhs_imm=1 } -> x2 + v28 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v27) + block 3 start_pc=0 + v23 Phi { incoming=[b0:v1, b2:v27], kind=I64 } -> x2 + v24 Extend { value=v23, kind=I32 } -> x1 + v25 BinopI { op=lt, lhs=v24, rhs_imm=4 } -> x6 + terminator Bnz { cond=v25, target=b1, fall=b4 } (exit_acc=v25) block 4 start_pc=0 v46 Imm(0) -> x1 - v47 Imm(0) -> x0 + v47 Imm(0) -> x2 terminator Jmp(b5) (exit_acc=v46) block 5 start_pc=0 - v48 Phi { incoming=[b4:v46, b6:v53], kind=I64 } -> x1 - v49 Phi { incoming=[b4:v20, b6:v64], kind=I64 } -> x12 - v50 Extend { value=v48, kind=I32 } -> x0 - v51 BinopI { op=lt, lhs=v50, rhs_imm=4 } -> x0 - terminator Bz { cond=v51, target=b8, fall=b7 } (exit_acc=v51) + v48 Imm(0) -> x1 + v49 Imm(1) -> x1 + v50 LoadLocal { off=-1, kind=I64 } -> x1 + v51 ImmData(40) -> x1 + v52 Imm(0) -> x2 + v53 Imm(0) -> x2 + v54 BinopI { op=add, lhs=v51, rhs_imm=0 } -> x1 + v55 Load { addr=v54, disp=0, kind=I64 } -> x2 + v56 BinopI { op=add, lhs=v54, rhs_imm=8 } -> x6 + v57 Load { addr=v54, disp=8, kind=I64 } -> x1 + v58 Binop { op=add, lhs=v55, rhs=v57 } -> x1 + v59 Binop { op=add, lhs=v20, rhs=v58 } -> x0 + v60 Imm(0) -> x1 + v61 Imm(0) -> x1 + v62 Imm(1) -> x1 + v63 Imm(0) -> x1 + v64 Imm(1) -> x1 + v65 Imm(1) -> x1 + v66 LoadLocal { off=-1, kind=I64 } -> x1 + v67 ImmData(40) -> x1 + v68 Imm(1) -> x2 + v69 Imm(16) -> x2 + v70 BinopI { op=add, lhs=v67, rhs_imm=16 } -> x1 + v71 Load { addr=v70, disp=0, kind=I64 } -> x2 + v72 BinopI { op=add, lhs=v70, rhs_imm=8 } -> x6 + v73 Load { addr=v70, disp=8, kind=I64 } -> x1 + v74 Binop { op=add, lhs=v71, rhs=v73 } -> x1 + v75 Binop { op=add, lhs=v59, rhs=v74 } -> x0 + v76 Imm(0) -> x1 + v77 Imm(1) -> x1 + v78 Imm(2) -> x1 + v79 Imm(0) -> x1 + v80 Imm(2) -> x1 + v81 Imm(1) -> x1 + v82 LoadLocal { off=-1, kind=I64 } -> x1 + v83 ImmData(40) -> x1 + v84 Imm(2) -> x2 + v85 Imm(32) -> x2 + v86 BinopI { op=add, lhs=v83, rhs_imm=32 } -> x1 + v87 Load { addr=v86, disp=0, kind=I64 } -> x2 + v88 BinopI { op=add, lhs=v86, rhs_imm=8 } -> x6 + v89 Load { addr=v86, disp=8, kind=I64 } -> x1 + v90 Binop { op=add, lhs=v87, rhs=v89 } -> x1 + v91 Binop { op=add, lhs=v75, rhs=v90 } -> x0 + v92 Imm(0) -> x1 + v93 Imm(2) -> x1 + v94 Imm(3) -> x1 + v95 Imm(0) -> x1 + v96 Imm(3) -> x1 + v97 Imm(1) -> x1 + v98 LoadLocal { off=-1, kind=I64 } -> x1 + v99 ImmData(40) -> x1 + v100 Imm(3) -> x2 + v101 Imm(48) -> x2 + v102 BinopI { op=add, lhs=v99, rhs_imm=48 } -> x1 + v103 Load { addr=v102, disp=0, kind=I64 } -> x2 + v104 BinopI { op=add, lhs=v102, rhs_imm=8 } -> x6 + v105 Load { addr=v102, disp=8, kind=I64 } -> x1 + v106 Binop { op=add, lhs=v103, rhs=v105 } -> x1 + v107 Binop { op=add, lhs=v91, rhs=v106 } -> x12 + v108 Imm(0) -> x0 + v109 Imm(3) -> x0 + v110 Imm(4) -> x0 + v111 Imm(0) -> x0 + v112 Imm(4) -> x0 + v113 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v113) block 6 start_pc=0 - v52 Extend { value=v48, kind=I32 } -> x0 - v53 BinopI { op=add, lhs=v52, rhs_imm=1 } -> x1 - v54 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v53) + v114 LocalAddr(-9) -> x0 + v115 Imm(3) -> x1 + v116 Store { addr=v114, disp=0, value=v115, kind=I64 } -> - + v117 LocalAddr(-9) -> x0 + v118 BinopI { op=add, lhs=v117, rhs_imm=8 } -> x1 + v119 Imm(4) -> x1 + v120 Store { addr=v117, disp=8, value=v119, kind=I64 } -> - + v121 LocalAddr(-9) -> x7 + v122 Call { target_pc=1, args=[v121], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v123 LoadLocal { off=-1, kind=I64 } -> x0 + v124 ImmData(24) -> x0 + v125 Load { addr=v3, disp=0, kind=I64 } -> x0 + v126 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v127 Load { addr=v3, disp=8, kind=I64 } -> x1 + v128 Binop { op=add, lhs=v125, rhs=v127 } -> x0 + v129 Binop { op=add, lhs=v107, rhs=v128 } -> x0 + v130 Imm(0) -> x1 + v131 LoadLocal { off=-1, kind=I64 } -> x1 + v132 BinopI { op=eq, lhs=v129, rhs_imm=78 } -> x0 + terminator Bz { cond=v132, target=b9, fall=b7 } (exit_acc=v132) block 7 start_pc=0 - v55 LoadLocal { off=-1, kind=I64 } -> x0 - v56 ImmData(40) -> x0 - v57 Extend { value=v48, kind=I32 } -> x2 - v58 BinopI { op=shl, lhs=v57, rhs_imm=4 } -> x2 - v59 Binop { op=add, lhs=v56, rhs=v58 } -> x0 - v60 Load { addr=v59, disp=0, kind=I64 } -> x2 - v61 BinopI { op=add, lhs=v59, rhs_imm=8 } -> x6 - v62 Load { addr=v59, disp=8, kind=I64 } -> x0 - v63 Binop { op=add, lhs=v60, rhs=v62 } -> x0 - v64 Binop { op=add, lhs=v49, rhs=v63 } -> x12 - v65 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v64) + v133 Imm(0) -> x1 + v134 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v133) block 8 start_pc=0 - v66 LocalAddr(-9) -> x0 - v67 Imm(3) -> x1 - v68 Store { addr=v66, disp=0, value=v67, kind=I64 } -> - - v69 LocalAddr(-9) -> x0 - v70 BinopI { op=add, lhs=v69, rhs_imm=8 } -> x1 - v71 Imm(4) -> x1 - v72 Store { addr=v69, disp=8, value=v71, kind=I64 } -> - - v73 LocalAddr(-9) -> x7 - v74 Call { target_pc=1, args=[v73], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v75 LoadLocal { off=-1, kind=I64 } -> x0 - v76 ImmData(24) -> x0 - v77 Load { addr=v3, disp=0, kind=I64 } -> x0 - v78 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 - v79 Load { addr=v3, disp=8, kind=I64 } -> x1 - v80 Binop { op=add, lhs=v77, rhs=v79 } -> x0 - v81 Binop { op=add, lhs=v49, rhs=v80 } -> x0 - v82 Imm(0) -> x1 - v83 LoadLocal { off=-1, kind=I64 } -> x1 - v84 BinopI { op=eq, lhs=v81, rhs_imm=78 } -> x0 - terminator Bz { cond=v84, target=b10, fall=b9 } (exit_acc=v84) + v137 Phi { incoming=[b7:v133, b9:v135], kind=I64 } -> x1 + v138 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Return(v137) (exit_acc=v137) block 9 start_pc=0 - v85 Imm(0) -> x1 - v86 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v85) - block 10 start_pc=0 - v87 Imm(1) -> x1 - v88 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v87) - block 11 start_pc=0 - v89 Phi { incoming=[b9:v85, b10:v87], kind=I64 } -> x1 - v90 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Return(v89) (exit_acc=v89) + v135 Imm(1) -> x1 + v136 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v135) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_sizeof.ssa b/tests/snapshots/ssa/struct_sizeof.ssa index 1b4293b92..12ce1bd56 100644 --- a/tests/snapshots/ssa/struct_sizeof.ssa +++ b/tests/snapshots/ssa/struct_sizeof.ssa @@ -6,31 +6,31 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Return(v9) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(3) -> x0 - terminator Return(v6) (exit_acc=v6) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) block 7 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 8 start_pc=0 v8 Imm(4) -> x0 terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Return(v9) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_stack_arg_then_scalar.ssa b/tests/snapshots/ssa/struct_stack_arg_then_scalar.ssa index 9bab4333a..9019fcd2f 100644 --- a/tests/snapshots/ssa/struct_stack_arg_then_scalar.ssa +++ b/tests/snapshots/ssa/struct_stack_arg_then_scalar.ssa @@ -9,17 +9,13 @@ fn ent_pc=0 n_params=7 variadic=false locals=9 v3 ParamRef(2, kind=I32) -> x2 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I64 } -> x0 - terminator Bz { cond=v1, target=b2, fall=b1 } (exit_acc=v1) + terminator Bz { cond=v1, target=b3, fall=b1 } (exit_acc=v1) block 1 start_pc=0 v6 Imm(1) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 Imm(0) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v8], kind=I64 } -> x1 + v10 Phi { incoming=[b1:v6, b3:v8], kind=I64 } -> x1 v11 LoadLocal { off=-9, kind=I64 } -> x0 v12 BinopI { op=mul, lhs=v10, rhs_imm=1000000 } -> x0 v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 @@ -51,6 +47,10 @@ fn ent_pc=0 n_params=7 variadic=false locals=9 v39 LoadLocal { off=8, kind=I32 } -> x1 v40 Binop { op=add, lhs=v38, rhs=v39 } -> x0 terminator Return(v40) (exit_acc=v40) + block 3 start_pc=0 + v8 Imm(0) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=dp fn ent_pc=1 n_params=5 variadic=false locals=15 diff --git a/tests/snapshots/ssa/struct_stat_abi_size.ssa b/tests/snapshots/ssa/struct_stat_abi_size.ssa index e115aacf9..04a33f378 100644 --- a/tests/snapshots/ssa/struct_stat_abi_size.ssa +++ b/tests/snapshots/ssa/struct_stat_abi_size.ssa @@ -5,17 +5,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=30 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(2) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 LocalAddr(-8) -> x3 v6 ImmData(32) -> x12 v7 CallExt { binding_idx=138, args=[], fp_arg_mask=0x0 } -> x2 @@ -28,23 +22,23 @@ fn ent_pc=1 n_params=0 variadic=false locals=30 v14 Imm(0) -> x0 v15 Extend { value=v13, kind=I32 } -> x0 v16 BinopI { op=lt, lhs=v15, rhs_imm=0 } -> x0 - terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) - block 5 start_pc=0 + terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + block 3 start_pc=0 v17 Imm(3) -> x0 terminator Return(v17) (exit_acc=v17) - block 6 start_pc=0 + block 4 start_pc=0 v18 Extend { value=v13, kind=I32 } -> x7 v19 ImmData(49) -> x6 v20 Imm(16) -> x2 v21 CallExt { binding_idx=117, args=[v18, v19, v20], fp_arg_mask=0x0 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=16 } -> x0 - terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) - block 7 start_pc=0 + terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + block 5 start_pc=0 v23 LocalAddr(-8) -> x7 v24 CallExt { binding_idx=128, args=[v23], fp_arg_mask=0x0 } -> x0 v25 Imm(4) -> x0 terminator Return(v25) (exit_acc=v25) - block 8 start_pc=0 + block 6 start_pc=0 v26 LocalAddr(-27) -> x7 v27 Imm(0) -> x6 v28 Imm(144) -> x2 @@ -53,42 +47,48 @@ fn ent_pc=1 n_params=0 variadic=false locals=30 v31 LocalAddr(-27) -> x6 v32 CallExt { binding_idx=127, args=[v30, v31], fp_arg_mask=0x0 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=0 } -> x0 - terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) - block 9 start_pc=0 + terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) + block 7 start_pc=0 v34 LocalAddr(-8) -> x7 v35 CallExt { binding_idx=128, args=[v34], fp_arg_mask=0x0 } -> x0 v36 Imm(5) -> x0 terminator Return(v36) (exit_acc=v36) - block 10 start_pc=0 + block 8 start_pc=0 v37 LocalAddr(-27) -> x0 v38 BinopI { op=add, lhs=v37, rhs_imm=48 } -> x1 v39 Load { addr=v37, disp=48, kind=I64 } -> x0 v40 BinopI { op=ne, lhs=v39, rhs_imm=16 } -> x0 - terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) - block 11 start_pc=0 + terminator Bz { cond=v40, target=b10, fall=b9 } (exit_acc=v40) + block 9 start_pc=0 v41 LocalAddr(-8) -> x7 v42 CallExt { binding_idx=128, args=[v41], fp_arg_mask=0x0 } -> x0 v43 Imm(6) -> x0 terminator Return(v43) (exit_acc=v43) - block 12 start_pc=0 + block 10 start_pc=0 v44 LocalAddr(-27) -> x0 v45 BinopI { op=add, lhs=v44, rhs_imm=24 } -> x1 v46 Load { addr=v44, disp=24, kind=I32 } -> x0 v47 BinopI { op=and, lhs=v46, rhs_imm=61440 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=32768 } -> x0 - terminator Bz { cond=v48, target=b14, fall=b13 } (exit_acc=v48) - block 13 start_pc=0 + terminator Bz { cond=v48, target=b12, fall=b11 } (exit_acc=v48) + block 11 start_pc=0 v49 LocalAddr(-8) -> x7 v50 CallExt { binding_idx=128, args=[v49], fp_arg_mask=0x0 } -> x0 v51 Imm(7) -> x0 terminator Return(v51) (exit_acc=v51) - block 14 start_pc=0 + block 12 start_pc=0 v52 Extend { value=v13, kind=I32 } -> x7 v53 CallExt { binding_idx=114, args=[v52], fp_arg_mask=0x0 } -> x0 v54 LocalAddr(-8) -> x7 v55 CallExt { binding_idx=128, args=[v54], fp_arg_mask=0x0 } -> x0 v56 Imm(0) -> x0 terminator Return(v56) (exit_acc=v56) + block 13 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 14 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/struct_tm_tm_zone_offset.ssa b/tests/snapshots/ssa/struct_tm_tm_zone_offset.ssa index e82c475cd..57775a074 100644 --- a/tests/snapshots/ssa/struct_tm_tm_zone_offset.ssa +++ b/tests/snapshots/ssa/struct_tm_tm_zone_offset.ssa @@ -6,24 +6,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=10 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 v2 Imm(40) -> x1 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Imm(1) -> x0 - terminator Return(v3) (exit_acc=v3) - block 2 start_pc=0 v4 Imm(0) -> x0 v5 Imm(48) -> x1 - terminator Jmp(b4) (exit_acc=v4) - block 3 start_pc=0 - v6 Imm(2) -> x0 - terminator Return(v6) (exit_acc=v6) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v4) + block 2 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v7) - block 5 start_pc=0 - v8 Imm(3) -> x0 - terminator Return(v8) (exit_acc=v8) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 v9 Imm(0) -> x7 v10 CallExt { binding_idx=0, args=[v9], fp_arg_mask=0x0 } -> x0 v11 StoreLocal { off=-1, value=v10, kind=I64 } -> - @@ -31,32 +22,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=10 v13 LocalAddr(-8) -> x6 v14 CallExt { binding_idx=10, args=[v12, v13], fp_arg_mask=0x0 } -> x0 v15 BinopI { op=eq, lhs=v14, rhs_imm=0 } -> x0 - terminator Bz { cond=v15, target=b8, fall=b7 } (exit_acc=v15) - block 7 start_pc=0 + terminator Bz { cond=v15, target=b5, fall=b4 } (exit_acc=v15) + block 4 start_pc=0 v16 Imm(4) -> x0 terminator Return(v16) (exit_acc=v16) - block 8 start_pc=0 + block 5 start_pc=0 v17 LocalAddr(-8) -> x0 v18 BinopI { op=add, lhs=v17, rhs_imm=48 } -> x1 v19 Load { addr=v17, disp=48, kind=I64 } -> x0 v20 BinopI { op=eq, lhs=v19, rhs_imm=0 } -> x0 - terminator Bz { cond=v20, target=b10, fall=b9 } (exit_acc=v20) - block 9 start_pc=0 + terminator Bz { cond=v20, target=b7, fall=b6 } (exit_acc=v20) + block 6 start_pc=0 v21 Imm(5) -> x0 terminator Return(v21) (exit_acc=v21) - block 10 start_pc=0 + block 7 start_pc=0 v22 LocalAddr(-8) -> x0 v23 BinopI { op=add, lhs=v22, rhs_imm=48 } -> x1 v24 Load { addr=v22, disp=48, kind=I64 } -> x7 v25 CallExt { binding_idx=24, args=[v24], fp_arg_mask=0x0 } -> x0 v26 BinopI { op=gt, lhs=v25, rhs_imm=64 } -> x0 - terminator Bz { cond=v26, target=b12, fall=b11 } (exit_acc=v26) - block 11 start_pc=0 + terminator Bz { cond=v26, target=b9, fall=b8 } (exit_acc=v26) + block 8 start_pc=0 v27 Imm(6) -> x0 terminator Return(v27) (exit_acc=v27) - block 12 start_pc=0 + block 9 start_pc=0 v28 Imm(0) -> x0 terminator Return(v28) (exit_acc=v28) + block 10 start_pc=0 + v3 Imm(1) -> x0 + terminator Return(v3) (exit_acc=v3) + block 11 start_pc=0 + v6 Imm(2) -> x0 + terminator Return(v6) (exit_acc=v6) + block 12 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sub_word_return_narrow.ssa b/tests/snapshots/ssa/sub_word_return_narrow.ssa index e165309eb..da0cb6201 100644 --- a/tests/snapshots/ssa/sub_word_return_narrow.ssa +++ b/tests/snapshots/ssa/sub_word_return_narrow.ssa @@ -65,67 +65,67 @@ fn ent_pc=4 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(13330) -> x0 - v2 Imm(0) -> x1 - v3 BinopI { op=and, lhs=v1, rhs_imm=65535 } -> x0 - v4 BinopI { op=shru, lhs=v3, rhs_imm=8 } -> x1 - v5 BinopI { op=shl, lhs=v3, rhs_imm=8 } -> x0 - v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x2 - v7 Extend { value=v5, kind=I32 } -> x0 - v8 Binop { op=or, lhs=v4, rhs=v7 } -> x0 - v9 BinopI { op=and, lhs=v8, rhs_imm=65535 } -> x0 - v10 BinopI { op=xor, lhs=v9, rhs_imm=4660 } -> x0 - v11 BinopI { op=and, lhs=v10, rhs_imm=4294967295 } -> x0 - v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v2 Imm(0) -> x0 + v3 Imm(13330) -> x0 + v4 Imm(52) -> x0 + v5 Imm(3412480) -> x0 + v6 Imm(14656489998254080) -> x0 + v7 Imm(3412480) -> x0 + v8 Imm(3412532) -> x0 + v9 Imm(4660) -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v12) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) - block 2 start_pc=0 v14 Imm(100) -> x0 - v15 Imm(0) -> x1 - v16 BinopI { op=and, lhs=v14, rhs_imm=255 } -> x0 - v17 BinopI { op=add, lhs=v16, rhs_imm=200 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x0 - v20 BinopI { op=and, lhs=v19, rhs_imm=255 } -> x0 - v21 BinopI { op=xor, lhs=v20, rhs_imm=44 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v15 Imm(0) -> x0 + v16 Imm(100) -> x0 + v17 Imm(300) -> x0 + v18 Imm(1288490188800) -> x0 + v19 Imm(300) -> x0 + v20 Imm(44) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v25 Imm(320) -> x0 + v26 Imm(320) -> x0 + v27 Imm(0) -> x0 + v28 Imm(81920) -> x0 + v29 Imm(351843720888320) -> x0 + v30 Imm(81920) -> x0 + v31 Imm(4611686018427387904) -> x0 + v32 Imm(16384) -> x0 + v33 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v33) block 3 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v35 Imm(100) -> x0 + v36 Imm(100) -> x0 + v37 Imm(0) -> x0 + v38 Imm(200) -> x0 + v39 Imm(858993459200) -> x0 + v40 Imm(200) -> x0 + v41 Imm(-4035225266123964416) -> x0 + v42 Imm(-56) -> x0 + v43 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v43) block 4 start_pc=0 - v25 Imm(320) -> x0 - v26 Extend { value=v25, kind=I16 } -> x0 - v27 Imm(0) -> x1 - v28 BinopI { op=shl, lhs=v26, rhs_imm=8 } -> x0 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 - v30 Extend { value=v28, kind=I32 } -> x1 - v31 BinopI { op=shl, lhs=v28, rhs_imm=48 } -> x0 - v32 Extend { value=v30, kind=I16 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=16384 } -> x0 - terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) block 5 start_pc=0 - v34 Imm(3) -> x0 - terminator Return(v34) (exit_acc=v34) + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) block 6 start_pc=0 - v35 Imm(100) -> x0 - v36 Extend { value=v35, kind=I8 } -> x0 - v37 Imm(0) -> x1 - v38 BinopI { op=add, lhs=v36, rhs_imm=100 } -> x0 - v39 BinopI { op=shl, lhs=v38, rhs_imm=32 } -> x1 - v40 Extend { value=v38, kind=I32 } -> x1 - v41 BinopI { op=shl, lhs=v38, rhs_imm=56 } -> x0 - v42 Extend { value=v40, kind=I8 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=-56 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v24 Imm(2) -> x0 + terminator Return(v24) (exit_acc=v24) block 7 start_pc=0 + v34 Imm(3) -> x0 + terminator Return(v34) (exit_acc=v34) + block 8 start_pc=0 v44 Imm(4) -> x0 terminator Return(v44) (exit_acc=v44) - block 8 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_binary_search.ssa b/tests/snapshots/ssa/switch_binary_search.ssa index 258447720..99fa41e78 100644 --- a/tests/snapshots/ssa/switch_binary_search.ssa +++ b/tests/snapshots/ssa/switch_binary_search.ssa @@ -8,72 +8,72 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v4, target=b10, fall=b11 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b13, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v25 Imm(0) -> x0 - terminator Return(v25) (exit_acc=v25) + v10 BinopI { op=lt, lhs=v1, rhs_imm=42 } -> x0 + terminator Bnz { cond=v10, target=b8, fall=b2 } (exit_acc=v10) block 2 start_pc=0 - v17 Imm(1) -> x0 - terminator Return(v17) (exit_acc=v17) + v14 BinopI { op=lt, lhs=v1, rhs_imm=1000 } -> x0 + terminator Bnz { cond=v14, target=b6, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v18 Imm(2) -> x0 - terminator Return(v18) (exit_acc=v18) + v16 BinopI { op=eq, lhs=v1, rhs_imm=1000 } -> x0 + terminator Bnz { cond=v16, target=b5, fall=b4 } (exit_acc=v16) block 4 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v24 Imm(0) -> x0 + terminator Return(v24) (exit_acc=v24) block 5 start_pc=0 - v20 Imm(4) -> x0 - terminator Return(v20) (exit_acc=v20) + v23 Imm(7) -> x0 + terminator Return(v23) (exit_acc=v23) block 6 start_pc=0 - v21 Imm(5) -> x0 - terminator Return(v21) (exit_acc=v21) + v15 BinopI { op=eq, lhs=v1, rhs_imm=42 } -> x0 + terminator Bz { cond=v15, target=b4, fall=b7 } (exit_acc=v15) block 7 start_pc=0 v22 Imm(6) -> x0 terminator Return(v22) (exit_acc=v22) block 8 start_pc=0 - v23 Imm(7) -> x0 - terminator Return(v23) (exit_acc=v23) + v11 BinopI { op=lt, lhs=v1, rhs_imm=7 } -> x0 + terminator Bnz { cond=v11, target=b11, fall=b9 } (exit_acc=v11) block 9 start_pc=0 - v24 Imm(0) -> x0 - terminator Return(v24) (exit_acc=v24) + v13 BinopI { op=eq, lhs=v1, rhs_imm=7 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b10 } (exit_acc=v13) block 10 start_pc=0 - v5 BinopI { op=lt, lhs=v1, rhs_imm=-3 } -> x0 - terminator Bnz { cond=v5, target=b12, fall=b13 } (exit_acc=v5) + v21 Imm(5) -> x0 + terminator Return(v21) (exit_acc=v21) block 11 start_pc=0 - v10 BinopI { op=lt, lhs=v1, rhs_imm=42 } -> x0 - terminator Bnz { cond=v10, target=b16, fall=b17 } (exit_acc=v10) + v12 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v12, target=b4, fall=b12 } (exit_acc=v12) block 12 start_pc=0 - v6 BinopI { op=eq, lhs=v1, rhs_imm=-100 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b9 } (exit_acc=v6) + v20 Imm(4) -> x0 + terminator Return(v20) (exit_acc=v20) block 13 start_pc=0 - v7 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 - terminator Bnz { cond=v7, target=b14, fall=b15 } (exit_acc=v7) + v5 BinopI { op=lt, lhs=v1, rhs_imm=-3 } -> x0 + terminator Bnz { cond=v5, target=b19, fall=b14 } (exit_acc=v5) block 14 start_pc=0 - v8 BinopI { op=eq, lhs=v1, rhs_imm=-3 } -> x0 - terminator Bnz { cond=v8, target=b3, fall=b9 } (exit_acc=v8) + v7 BinopI { op=lt, lhs=v1, rhs_imm=0 } -> x0 + terminator Bnz { cond=v7, target=b17, fall=b15 } (exit_acc=v7) block 15 start_pc=0 v9 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 - terminator Bnz { cond=v9, target=b4, fall=b9 } (exit_acc=v9) + terminator Bz { cond=v9, target=b4, fall=b16 } (exit_acc=v9) block 16 start_pc=0 - v11 BinopI { op=lt, lhs=v1, rhs_imm=7 } -> x0 - terminator Bnz { cond=v11, target=b18, fall=b19 } (exit_acc=v11) + v19 Imm(3) -> x0 + terminator Return(v19) (exit_acc=v19) block 17 start_pc=0 - v14 BinopI { op=lt, lhs=v1, rhs_imm=1000 } -> x0 - terminator Bnz { cond=v14, target=b20, fall=b21 } (exit_acc=v14) + v8 BinopI { op=eq, lhs=v1, rhs_imm=-3 } -> x0 + terminator Bz { cond=v8, target=b4, fall=b18 } (exit_acc=v8) block 18 start_pc=0 - v12 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v12, target=b5, fall=b9 } (exit_acc=v12) + v18 Imm(2) -> x0 + terminator Return(v18) (exit_acc=v18) block 19 start_pc=0 - v13 BinopI { op=eq, lhs=v1, rhs_imm=7 } -> x0 - terminator Bnz { cond=v13, target=b6, fall=b9 } (exit_acc=v13) + v6 BinopI { op=eq, lhs=v1, rhs_imm=-100 } -> x0 + terminator Bz { cond=v6, target=b4, fall=b20 } (exit_acc=v6) block 20 start_pc=0 - v15 BinopI { op=eq, lhs=v1, rhs_imm=42 } -> x0 - terminator Bnz { cond=v15, target=b7, fall=b9 } (exit_acc=v15) + v17 Imm(1) -> x0 + terminator Return(v17) (exit_acc=v17) block 21 start_pc=0 - v16 BinopI { op=eq, lhs=v1, rhs_imm=1000 } -> x0 - terminator Bnz { cond=v16, target=b8, fall=b9 } (exit_acc=v16) + v25 Imm(0) -> x0 + terminator Return(v25) (exit_acc=v25) block 22 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b20) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=classify_unsigned fn ent_pc=1 n_params=1 variadic=false locals=0 @@ -84,54 +84,54 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 v4 BinopI { op=ult, lhs=v3, rhs_imm=2147483647 } -> x1 - terminator Bnz { cond=v4, target=b8, fall=b9 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b10, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v19 Imm(0) -> x0 - terminator Return(v19) (exit_acc=v19) + v8 BinopI { op=ult, lhs=v3, rhs_imm=2147483648 } -> x1 + terminator Bnz { cond=v8, target=b8, fall=b2 } (exit_acc=v8) block 2 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v10 BinopI { op=ult, lhs=v3, rhs_imm=4294967295 } -> x1 + terminator Bnz { cond=v10, target=b6, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v12 BinopI { op=eq, lhs=v3, rhs_imm=4294967295 } -> x0 + terminator Bnz { cond=v12, target=b5, fall=b4 } (exit_acc=v12) block 4 start_pc=0 - v15 Imm(3) -> x0 - terminator Return(v15) (exit_acc=v15) + v18 Imm(0) -> x0 + terminator Return(v18) (exit_acc=v18) block 5 start_pc=0 - v16 Imm(4) -> x0 - terminator Return(v16) (exit_acc=v16) - block 6 start_pc=0 v17 Imm(5) -> x0 terminator Return(v17) (exit_acc=v17) + block 6 start_pc=0 + v11 BinopI { op=eq, lhs=v3, rhs_imm=2147483648 } -> x0 + terminator Bz { cond=v11, target=b4, fall=b7 } (exit_acc=v11) block 7 start_pc=0 - v18 Imm(0) -> x0 - terminator Return(v18) (exit_acc=v18) + v16 Imm(4) -> x0 + terminator Return(v16) (exit_acc=v16) block 8 start_pc=0 - v5 BinopI { op=ult, lhs=v3, rhs_imm=5 } -> x1 - terminator Bnz { cond=v5, target=b10, fall=b11 } (exit_acc=v5) + v9 BinopI { op=eq, lhs=v3, rhs_imm=2147483647 } -> x0 + terminator Bz { cond=v9, target=b4, fall=b9 } (exit_acc=v9) block 9 start_pc=0 - v8 BinopI { op=ult, lhs=v3, rhs_imm=2147483648 } -> x1 - terminator Bnz { cond=v8, target=b12, fall=b13 } (exit_acc=v8) + v15 Imm(3) -> x0 + terminator Return(v15) (exit_acc=v15) block 10 start_pc=0 - v6 BinopI { op=eq, lhs=v3, rhs_imm=0 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b7 } (exit_acc=v6) + v5 BinopI { op=ult, lhs=v3, rhs_imm=5 } -> x1 + terminator Bnz { cond=v5, target=b13, fall=b11 } (exit_acc=v5) block 11 start_pc=0 v7 BinopI { op=eq, lhs=v3, rhs_imm=5 } -> x0 - terminator Bnz { cond=v7, target=b3, fall=b7 } (exit_acc=v7) + terminator Bz { cond=v7, target=b4, fall=b12 } (exit_acc=v7) block 12 start_pc=0 - v9 BinopI { op=eq, lhs=v3, rhs_imm=2147483647 } -> x0 - terminator Bnz { cond=v9, target=b4, fall=b7 } (exit_acc=v9) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 13 start_pc=0 - v10 BinopI { op=ult, lhs=v3, rhs_imm=4294967295 } -> x1 - terminator Bnz { cond=v10, target=b14, fall=b15 } (exit_acc=v10) + v6 BinopI { op=eq, lhs=v3, rhs_imm=0 } -> x0 + terminator Bz { cond=v6, target=b4, fall=b14 } (exit_acc=v6) block 14 start_pc=0 - v11 BinopI { op=eq, lhs=v3, rhs_imm=2147483648 } -> x0 - terminator Bnz { cond=v11, target=b5, fall=b7 } (exit_acc=v11) + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) block 15 start_pc=0 - v12 BinopI { op=eq, lhs=v3, rhs_imm=4294967295 } -> x0 - terminator Bnz { cond=v12, target=b6, fall=b7 } (exit_acc=v12) + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) block 16 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b14) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_break_calls.ssa b/tests/snapshots/ssa/switch_break_calls.ssa index 4404f5861..20df13867 100644 --- a/tests/snapshots/ssa/switch_break_calls.ssa +++ b/tests/snapshots/ssa/switch_break_calls.ssa @@ -42,41 +42,41 @@ fn ent_pc=4 n_params=1 variadic=false locals=1 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=lt, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v6, target=b6, fall=b7 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b8, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b5:v15, b2:v9, b3:v11, b4:v13], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v8) (exit_acc=v8) + v18 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v18, target=b6, fall=b2 } (exit_acc=v18) block 2 start_pc=0 - v9 Imm(100) -> x0 - v10 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v9) + v20 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v20, target=b5, fall=b3 } (exit_acc=v20) block 3 start_pc=0 - v11 Imm(200) -> x0 - v12 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v11) + v15 Imm(400) -> x0 + v16 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v15) block 4 start_pc=0 + v7 Phi { incoming=[b3:v15, b9:v9, b7:v11, b5:v13], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v8) (exit_acc=v8) + block 5 start_pc=0 v13 Imm(300) -> x0 v14 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v13) - block 5 start_pc=0 - v15 Imm(400) -> x0 - v16 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v15) + terminator Jmp(b4) (exit_acc=v13) block 6 start_pc=0 - v17 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 - terminator Bnz { cond=v17, target=b2, fall=b5 } (exit_acc=v17) + v19 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v19, target=b3, fall=b7 } (exit_acc=v19) block 7 start_pc=0 - v18 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v18, target=b8, fall=b9 } (exit_acc=v18) + v11 Imm(200) -> x0 + v12 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v11) block 8 start_pc=0 - v19 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v19, target=b3, fall=b5 } (exit_acc=v19) + v17 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 + terminator Bz { cond=v17, target=b3, fall=b9 } (exit_acc=v17) block 9 start_pc=0 - v20 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v20, target=b4, fall=b5 } (exit_acc=v20) + v9 Imm(100) -> x0 + v10 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v9) block 10 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b9) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=main fn ent_pc=5 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_case_label_promoted.ssa b/tests/snapshots/ssa/switch_case_label_promoted.ssa index e59f06333..2293a3ac4 100644 --- a/tests/snapshots/ssa/switch_case_label_promoted.ssa +++ b/tests/snapshots/ssa/switch_case_label_promoted.ssa @@ -5,92 +5,92 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(-2147483648) -> x0 - v2 Imm(-9223372036854775808) -> x1 - v3 Imm(0) -> x1 - v4 Imm(0) -> x1 - v5 Imm(0) -> x1 - v6 LoadLocal { off=-1, kind=I32 } -> x1 - v7 BinopI { op=eq, lhs=v1, rhs_imm=-2147483648 } -> x0 - terminator Bnz { cond=v7, target=b2, fall=b3 } (exit_acc=v7) + v2 Imm(-9223372036854775808) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-1, kind=I32 } -> x0 + v7 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Phi { incoming=[b2:v11, b3:v13], kind=I64 } -> x0 - v9 Extend { value=v8, kind=I32 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=1 } -> x0 - terminator Bz { cond=v10, target=b6, fall=b5 } (exit_acc=v10) - block 2 start_pc=0 v11 Imm(1) -> x0 v12 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v11) + terminator Jmp(b2) (exit_acc=v11) + block 2 start_pc=0 + v8 Phi { incoming=[b1:v11, b14:v13], kind=I64 } -> x0 + v9 Extend { value=v8, kind=I32 } -> x0 + v10 BinopI { op=ne, lhs=v9, rhs_imm=1 } -> x0 + terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v13 Imm(2) -> x0 - v14 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v13) - block 4 start_pc=0 - terminator Jmp(b2) - block 5 start_pc=0 v15 Imm(1) -> x0 terminator Return(v15) (exit_acc=v15) - block 6 start_pc=0 + block 4 start_pc=0 v16 Imm(4294967294) -> x0 - v17 Imm(0) -> x1 - v18 LoadLocal { off=-3, kind=U32 } -> x1 - v19 BinopI { op=eq, lhs=v16, rhs_imm=4294967294 } -> x0 - terminator Bnz { cond=v19, target=b8, fall=b9 } (exit_acc=v19) - block 7 start_pc=0 - v20 Phi { incoming=[b8:v23, b9:v25], kind=I64 } -> x0 + v17 Imm(0) -> x0 + v18 LoadLocal { off=-3, kind=U32 } -> x0 + v19 Imm(1) -> x0 + terminator Jmp(b5) (exit_acc=v19) + block 5 start_pc=0 + v23 Imm(3) -> x0 + v24 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v23) + block 6 start_pc=0 + v20 Phi { incoming=[b5:v23, b16:v25], kind=I64 } -> x0 v21 Extend { value=v20, kind=I32 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=3 } -> x0 - terminator Bz { cond=v22, target=b12, fall=b11 } (exit_acc=v22) + terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) + block 7 start_pc=0 + v27 Imm(2) -> x0 + terminator Return(v27) (exit_acc=v27) block 8 start_pc=0 - v23 Imm(3) -> x0 - v24 Imm(0) -> x1 - terminator Jmp(b7) (exit_acc=v23) + v28 Imm(-4294967296) -> x0 + v29 Imm(0) -> x0 + v30 LoadLocal { off=-4, kind=I64 } -> x0 + v31 Imm(1) -> x0 + terminator Jmp(b9) (exit_acc=v31) block 9 start_pc=0 - v25 Imm(4) -> x0 - v26 Imm(0) -> x1 - terminator Jmp(b7) (exit_acc=v25) + v41 Imm(1) -> x0 + terminator Jmp(b10) (exit_acc=v41) block 10 start_pc=0 - terminator Jmp(b8) + v35 Imm(5) -> x0 + v36 Imm(0) -> x1 + terminator Jmp(b11) (exit_acc=v35) block 11 start_pc=0 - v27 Imm(2) -> x0 - terminator Return(v27) (exit_acc=v27) - block 12 start_pc=0 - v28 Imm(-4294967296) -> x0 - v29 Imm(0) -> x1 - v30 LoadLocal { off=-4, kind=I64 } -> x1 - v31 BinopI { op=lt, lhs=v28, rhs_imm=2147483648 } -> x1 - terminator Bnz { cond=v31, target=b17, fall=b18 } (exit_acc=v31) - block 13 start_pc=0 - v32 Phi { incoming=[b16:v39, b14:v35, b15:v37], kind=I64 } -> x0 + v32 Phi { incoming=[b19:v39, b10:v35, b18:v37], kind=I64 } -> x0 v33 Extend { value=v32, kind=I32 } -> x0 v34 BinopI { op=ne, lhs=v33, rhs_imm=5 } -> x0 - terminator Bz { cond=v34, target=b21, fall=b20 } (exit_acc=v34) + terminator Bz { cond=v34, target=b13, fall=b12 } (exit_acc=v34) + block 12 start_pc=0 + v43 Imm(3) -> x0 + terminator Return(v43) (exit_acc=v43) + block 13 start_pc=0 + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) block 14 start_pc=0 - v35 Imm(5) -> x0 - v36 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v35) + v13 Imm(2) -> x0 + v14 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v13) block 15 start_pc=0 - v37 Imm(6) -> x0 - v38 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v37) + terminator Jmp(b1) block 16 start_pc=0 - v39 Imm(7) -> x0 - v40 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v39) + v25 Imm(4) -> x0 + v26 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v25) block 17 start_pc=0 - v41 BinopI { op=eq, lhs=v28, rhs_imm=-4294967296 } -> x0 - terminator Bnz { cond=v41, target=b14, fall=b16 } (exit_acc=v41) + terminator Jmp(b5) block 18 start_pc=0 - v42 BinopI { op=eq, lhs=v28, rhs_imm=2147483648 } -> x0 - terminator Bnz { cond=v42, target=b15, fall=b16 } (exit_acc=v42) + v37 Imm(6) -> x0 + v38 Imm(0) -> x1 + terminator Jmp(b11) (exit_acc=v37) block 19 start_pc=0 - terminator Jmp(b14) + v39 Imm(7) -> x0 + v40 Imm(0) -> x1 + terminator Jmp(b11) (exit_acc=v39) block 20 start_pc=0 - v43 Imm(3) -> x0 - terminator Return(v43) (exit_acc=v43) + v42 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v42) block 21 start_pc=0 - v44 Imm(0) -> x0 - terminator Return(v44) (exit_acc=v44) + terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_default_routing.ssa b/tests/snapshots/ssa/switch_default_routing.ssa index badfddf92..ceb6cce69 100644 --- a/tests/snapshots/ssa/switch_default_routing.ssa +++ b/tests/snapshots/ssa/switch_default_routing.ssa @@ -5,36 +5,36 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(99) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x1 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I32 } -> x1 - v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x1 - terminator Bnz { cond=v6, target=b5, fall=b6 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b4:v13, b2:v9, b3:v11], kind=I64 } -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v13 Imm(100) -> x0 + v14 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 + v7 Phi { incoming=[b2:v13, b4:v9, b5:v11], kind=I64 } -> x0 v8 Extend { value=v7, kind=I32 } -> x0 terminator Return(v8) (exit_acc=v8) - block 2 start_pc=0 + block 4 start_pc=0 v9 Imm(10) -> x0 v10 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 + terminator Jmp(b3) (exit_acc=v9) + block 5 start_pc=0 v11 Imm(20) -> x0 v12 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v11) - block 4 start_pc=0 - v13 Imm(100) -> x0 - v14 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v13) - block 5 start_pc=0 - v15 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v15, target=b2, fall=b4 } (exit_acc=v15) + terminator Jmp(b3) (exit_acc=v11) block 6 start_pc=0 - v16 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v16, target=b3, fall=b4 } (exit_acc=v16) + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_goto_label_into_case.ssa b/tests/snapshots/ssa/switch_goto_label_into_case.ssa index 108196e91..de4e0e2c2 100644 --- a/tests/snapshots/ssa/switch_goto_label_into_case.ssa +++ b/tests/snapshots/ssa/switch_goto_label_into_case.ssa @@ -8,64 +8,64 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=3 } -> x0 - terminator Bnz { cond=v4, target=b7, fall=b8 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b10, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v5 Imm(0) -> x0 - terminator Return(v5) (exit_acc=v5) + v13 BinopI { op=lt, lhs=v1, rhs_imm=4 } -> x0 + terminator Bnz { cond=v13, target=b9, fall=b2 } (exit_acc=v13) block 2 start_pc=0 - v6 Imm(10) -> x0 - terminator Return(v6) (exit_acc=v6) + v17 BinopI { op=eq, lhs=v1, rhs_imm=4 } -> x0 + terminator Bnz { cond=v17, target=b6, fall=b3 } (exit_acc=v17) block 3 start_pc=0 - v7 Imm(20) -> x0 - terminator Return(v7) (exit_acc=v7) + v9 LoadLocal { off=2, kind=I32 } -> x0 + v10 BinopI { op=ge, lhs=v1, rhs_imm=5 } -> x1 + v11 Imm(0) -> x0 + terminator Bz { cond=v10, target=b8, fall=b4 } (exit_acc=v10) block 4 start_pc=0 - terminator Jmp(b5) + v18 LoadLocal { off=2, kind=I32 } -> x0 + v19 BinopI { op=le, lhs=v1, rhs_imm=8 } -> x1 + v20 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v19) block 5 start_pc=0 + v21 Phi { incoming=[b8:v10, b4:v19], kind=I64 } -> x1 + v22 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v21, target=b7, fall=b6 } (exit_acc=v21) + block 6 start_pc=0 v8 Imm(30) -> x0 terminator Return(v8) (exit_acc=v8) - block 6 start_pc=0 - v9 LoadLocal { off=2, kind=I32 } -> x0 - v10 BinopI { op=ge, lhs=v1, rhs_imm=5 } -> x1 - v11 Imm(0) -> x0 - terminator Bz { cond=v10, target=b19, fall=b15 } (exit_acc=v10) block 7 start_pc=0 - v12 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v12, target=b9, fall=b10 } (exit_acc=v12) + v23 Imm(0) -> x0 + terminator Return(v23) (exit_acc=v23) block 8 start_pc=0 - v13 BinopI { op=lt, lhs=v1, rhs_imm=4 } -> x0 - terminator Bnz { cond=v13, target=b11, fall=b12 } (exit_acc=v13) + terminator Jmp(b5) block 9 start_pc=0 - v14 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v14, target=b2, fall=b6 } (exit_acc=v14) + v16 BinopI { op=eq, lhs=v1, rhs_imm=3 } -> x0 + terminator Bnz { cond=v16, target=b6, fall=b3 } (exit_acc=v16) block 10 start_pc=0 - v15 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v15, target=b3, fall=b6 } (exit_acc=v15) + v12 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 + terminator Bnz { cond=v12, target=b13, fall=b11 } (exit_acc=v12) block 11 start_pc=0 - v16 BinopI { op=eq, lhs=v1, rhs_imm=3 } -> x0 - terminator Bnz { cond=v16, target=b4, fall=b6 } (exit_acc=v16) + v15 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bz { cond=v15, target=b3, fall=b12 } (exit_acc=v15) block 12 start_pc=0 - v17 BinopI { op=eq, lhs=v1, rhs_imm=4 } -> x0 - terminator Bnz { cond=v17, target=b5, fall=b6 } (exit_acc=v17) + v7 Imm(20) -> x0 + terminator Return(v7) (exit_acc=v7) block 13 start_pc=0 - terminator Jmp(b2) + v14 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v14, target=b3, fall=b14 } (exit_acc=v14) block 14 start_pc=0 - terminator Jmp(b4) + v6 Imm(10) -> x0 + terminator Return(v6) (exit_acc=v6) block 15 start_pc=0 - v18 LoadLocal { off=2, kind=I32 } -> x0 - v19 BinopI { op=le, lhs=v1, rhs_imm=8 } -> x1 - v20 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v19) + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) block 16 start_pc=0 - v21 Phi { incoming=[b19:v10, b15:v19], kind=I64 } -> x1 - v22 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b18, fall=b17 } (exit_acc=v21) + terminator Jmp(b6) block 17 start_pc=0 terminator Jmp(b14) block 18 start_pc=0 - v23 Imm(0) -> x0 - terminator Return(v23) (exit_acc=v23) + terminator Jmp(b6) block 19 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_jump_table_dense.ssa b/tests/snapshots/ssa/switch_jump_table_dense.ssa new file mode 100644 index 000000000..fafe50365 --- /dev/null +++ b/tests/snapshots/ssa/switch_jump_table_dense.ssa @@ -0,0 +1,443 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=dense_signed +fn ent_pc=0 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 BinopI { op=sub, lhs=v1, rhs_imm=3 } -> x0 + v5 BinopI { op=ult, lhs=v4, rhs_imm=17 } -> x1 + terminator Bz { cond=v5, target=b14, fall=b1 } (exit_acc=v5) + block 1 start_pc=0 + terminator JumpTable { idx=v4, table=0 } [b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15, b16, b17, b18] (exit_acc=v4) + block 2 start_pc=0 + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) + block 3 start_pc=0 + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) + block 4 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 5 start_pc=0 + v9 Imm(4) -> x0 + terminator Return(v9) (exit_acc=v9) + block 6 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 7 start_pc=0 + v11 Imm(6) -> x0 + terminator Return(v11) (exit_acc=v11) + block 8 start_pc=0 + v12 Imm(7) -> x0 + terminator Return(v12) (exit_acc=v12) + block 9 start_pc=0 + v13 Imm(8) -> x0 + terminator Return(v13) (exit_acc=v13) + block 10 start_pc=0 + v14 Imm(9) -> x0 + terminator Return(v14) (exit_acc=v14) + block 11 start_pc=0 + v15 Imm(10) -> x0 + terminator Return(v15) (exit_acc=v15) + block 12 start_pc=0 + v16 Imm(11) -> x0 + terminator Return(v16) (exit_acc=v16) + block 13 start_pc=0 + v17 Imm(12) -> x0 + terminator Return(v17) (exit_acc=v17) + block 14 start_pc=0 + v22 Imm(-1) -> x0 + terminator Return(v22) (exit_acc=v22) + block 15 start_pc=0 + v18 Imm(13) -> x0 + terminator Return(v18) (exit_acc=v18) + block 16 start_pc=0 + v19 Imm(14) -> x0 + terminator Return(v19) (exit_acc=v19) + block 17 start_pc=0 + v20 Imm(15) -> x0 + terminator Return(v20) (exit_acc=v20) + block 18 start_pc=0 + v21 Imm(16) -> x0 + terminator Return(v21) (exit_acc=v21) + block 19 start_pc=0 + v23 Imm(0) -> x0 + terminator Return(v23) (exit_acc=v23) + block 20 start_pc=0 + terminator Jmp(b2) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=dense_negative_bias +fn ent_pc=1 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I64 } -> x0 + v4 BinopI { op=sub, lhs=v1, rhs_imm=-6 } -> x0 + v5 BinopI { op=ult, lhs=v4, rhs_imm=9 } -> x1 + terminator Bz { cond=v5, target=b11, fall=b1 } (exit_acc=v5) + block 1 start_pc=0 + terminator JumpTable { idx=v4, table=0 } [b2, b3, b4, b5, b6, b7, b8, b9, b10] (exit_acc=v4) + block 2 start_pc=0 + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) + block 3 start_pc=0 + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) + block 4 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 5 start_pc=0 + v9 Imm(4) -> x0 + terminator Return(v9) (exit_acc=v9) + block 6 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 7 start_pc=0 + v11 Imm(6) -> x0 + terminator Return(v11) (exit_acc=v11) + block 8 start_pc=0 + v12 Imm(7) -> x0 + terminator Return(v12) (exit_acc=v12) + block 9 start_pc=0 + v13 Imm(8) -> x0 + terminator Return(v13) (exit_acc=v13) + block 10 start_pc=0 + v14 Imm(9) -> x0 + terminator Return(v14) (exit_acc=v14) + block 11 start_pc=0 + v15 Imm(-1) -> x0 + terminator Return(v15) (exit_acc=v15) + block 12 start_pc=0 + v16 Imm(0) -> x0 + terminator Return(v16) (exit_acc=v16) + block 13 start_pc=0 + terminator Jmp(b2) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=dense_unsigned_high +fn ent_pc=2 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 + v4 BinopI { op=sub, lhs=v3, rhs_imm=4294967286 } -> x0 + v5 BinopI { op=ult, lhs=v4, rhs_imm=10 } -> x1 + terminator Bz { cond=v5, target=b12, fall=b1 } (exit_acc=v5) + block 1 start_pc=0 + terminator JumpTable { idx=v4, table=0 } [b2, b3, b4, b5, b6, b7, b8, b9, b10, b11] (exit_acc=v4) + block 2 start_pc=0 + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) + block 3 start_pc=0 + v7 Imm(2) -> x0 + terminator Return(v7) (exit_acc=v7) + block 4 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 5 start_pc=0 + v9 Imm(4) -> x0 + terminator Return(v9) (exit_acc=v9) + block 6 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 7 start_pc=0 + v11 Imm(6) -> x0 + terminator Return(v11) (exit_acc=v11) + block 8 start_pc=0 + v12 Imm(7) -> x0 + terminator Return(v12) (exit_acc=v12) + block 9 start_pc=0 + v13 Imm(8) -> x0 + terminator Return(v13) (exit_acc=v13) + block 10 start_pc=0 + v14 Imm(9) -> x0 + terminator Return(v14) (exit_acc=v14) + block 11 start_pc=0 + v15 Imm(10) -> x0 + terminator Return(v15) (exit_acc=v15) + block 12 start_pc=0 + v16 Imm(-1) -> x0 + terminator Return(v16) (exit_acc=v16) + block 13 start_pc=0 + v17 Imm(0) -> x0 + terminator Return(v17) (exit_acc=v17) + block 14 start_pc=0 + terminator Jmp(b2) +; --- SSA dump (ok=true) ent_pc=3 --- +; name=main +fn ent_pc=3 n_params=0 variadic=false locals=6 + spill_count=0 gpr_used=[3, 12] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(3) -> x3 + v2 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v1) + block 1 start_pc=0 + v9 Extend { value=v3, kind=I32 } -> x0 + v10 BinopI { op=eq, lhs=v9, rhs_imm=15 } -> x0 + terminator Bnz { cond=v10, target=b6, fall=b2 } (exit_acc=v10) + block 2 start_pc=0 + v14 Extend { value=v3, kind=I32 } -> x0 + v15 BinopI { op=lt, lhs=v14, rhs_imm=15 } -> x0 + terminator Bz { cond=v15, target=b5, fall=b3 } (exit_acc=v15) + block 3 start_pc=0 + v16 Extend { value=v3, kind=I32 } -> x0 + v17 BinopI { op=sub, lhs=v3, rhs_imm=2 } -> x0 + v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 + v19 Extend { value=v17, kind=I32 } -> x12 + v20 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v19) + block 4 start_pc=0 + v26 Phi { incoming=[b3:v19, b5:v24], kind=I64 } -> x12 + v27 LoadLocal { off=-6, kind=I64 } -> x0 + v28 Imm(0) -> x0 + v29 Extend { value=v3, kind=I32 } -> x0 + v30 Call { target_pc=0, args=[v3], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v31 Extend { value=v26, kind=I32 } -> x1 + v32 Binop { op=ne, lhs=v30, rhs=v31 } -> x0 + terminator Bz { cond=v32, target=b6, fall=b45 } (exit_acc=v32) + block 5 start_pc=0 + v21 Extend { value=v3, kind=I32 } -> x0 + v22 BinopI { op=sub, lhs=v3, rhs_imm=3 } -> x0 + v23 BinopI { op=shl, lhs=v22, rhs_imm=32 } -> x1 + v24 Extend { value=v22, kind=I32 } -> x12 + v25 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v24) + block 6 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 + v8 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v7) + block 7 start_pc=0 + v3 Phi { incoming=[b0:v1, b6:v7], kind=I64 } -> x3 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=le, lhs=v4, rhs_imm=19 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b8 } (exit_acc=v5) + block 8 start_pc=0 + v11 Imm(15) -> x7 + v12 Call { target_pc=0, args=[v11], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v13 BinopI { op=ne, lhs=v12, rhs_imm=-1 } -> x0 + terminator Bz { cond=v13, target=b10, fall=b9 } (exit_acc=v13) + block 9 start_pc=0 + v34 Imm(2) -> x0 + terminator Return(v34) (exit_acc=v34) + block 10 start_pc=0 + v35 Imm(2) -> x7 + v36 Call { target_pc=0, args=[v35], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v37 BinopI { op=ne, lhs=v36, rhs_imm=-1 } -> x0 + terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) + block 11 start_pc=0 + v38 Imm(3) -> x0 + terminator Return(v38) (exit_acc=v38) + block 12 start_pc=0 + v39 Imm(20) -> x7 + v40 Call { target_pc=0, args=[v39], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v41 BinopI { op=ne, lhs=v40, rhs_imm=-1 } -> x0 + terminator Bz { cond=v41, target=b14, fall=b13 } (exit_acc=v41) + block 13 start_pc=0 + v42 Imm(4) -> x0 + terminator Return(v42) (exit_acc=v42) + block 14 start_pc=0 + v43 Imm(-1) -> x7 + v44 Call { target_pc=0, args=[v43], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v45 BinopI { op=ne, lhs=v44, rhs_imm=-1 } -> x0 + terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) + block 15 start_pc=0 + v46 Imm(5) -> x0 + terminator Return(v46) (exit_acc=v46) + block 16 start_pc=0 + v47 Imm(-2147483648) -> x7 + v48 Imm(-9223372036854775808) -> x0 + v49 Call { target_pc=0, args=[v47], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v50 BinopI { op=ne, lhs=v49, rhs_imm=-1 } -> x0 + terminator Bz { cond=v50, target=b18, fall=b17 } (exit_acc=v50) + block 17 start_pc=0 + v51 Imm(6) -> x0 + terminator Return(v51) (exit_acc=v51) + block 18 start_pc=0 + v52 Imm(2147483647) -> x7 + v53 Call { target_pc=0, args=[v52], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v54 BinopI { op=ne, lhs=v53, rhs_imm=-1 } -> x0 + terminator Bz { cond=v54, target=b20, fall=b19 } (exit_acc=v54) + block 19 start_pc=0 + v55 Imm(7) -> x0 + terminator Return(v55) (exit_acc=v55) + block 20 start_pc=0 + v56 Imm(-6) -> x3 + v57 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v56) + block 21 start_pc=0 + v64 LoadLocal { off=-3, kind=I64 } -> x0 + v65 Call { target_pc=1, args=[v58], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v66 LoadLocal { off=-3, kind=I64 } -> x1 + v67 BinopI { op=add, lhs=v58, rhs_imm=7 } -> x1 + v68 BinopI { op=shl, lhs=v67, rhs_imm=32 } -> x2 + v69 Extend { value=v67, kind=I32 } -> x1 + v70 Binop { op=ne, lhs=v65, rhs=v69 } -> x0 + terminator Bnz { cond=v70, target=b44, fall=b22 } (exit_acc=v70) + block 22 start_pc=0 + v61 LoadLocal { off=-3, kind=I64 } -> x0 + v62 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x3 + v63 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v62) + block 23 start_pc=0 + v58 Phi { incoming=[b20:v56, b22:v62], kind=I64 } -> x3 + v59 LoadLocal { off=-3, kind=I64 } -> x0 + v60 BinopI { op=le, lhs=v58, rhs_imm=2 } -> x0 + terminator Bnz { cond=v60, target=b21, fall=b24 } (exit_acc=v60) + block 24 start_pc=0 + v71 Imm(-7) -> x7 + v72 Call { target_pc=1, args=[v71], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v73 BinopI { op=ne, lhs=v72, rhs_imm=-1 } -> x0 + terminator Bz { cond=v73, target=b26, fall=b25 } (exit_acc=v73) + block 25 start_pc=0 + v75 Imm(9) -> x0 + terminator Return(v75) (exit_acc=v75) + block 26 start_pc=0 + v76 Imm(3) -> x7 + v77 Call { target_pc=1, args=[v76], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v78 BinopI { op=ne, lhs=v77, rhs_imm=-1 } -> x0 + terminator Bz { cond=v78, target=b28, fall=b27 } (exit_acc=v78) + block 27 start_pc=0 + v79 Imm(10) -> x0 + terminator Return(v79) (exit_acc=v79) + block 28 start_pc=0 + v80 Imm(4294967296) -> x7 + v81 Call { target_pc=1, args=[v80], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v82 BinopI { op=ne, lhs=v81, rhs_imm=-1 } -> x0 + terminator Bz { cond=v82, target=b30, fall=b29 } (exit_acc=v82) + block 29 start_pc=0 + v83 Imm(11) -> x0 + terminator Return(v83) (exit_acc=v83) + block 30 start_pc=0 + v84 Imm(-4294967296) -> x7 + v85 Call { target_pc=1, args=[v84], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v86 BinopI { op=ne, lhs=v85, rhs_imm=-1 } -> x0 + terminator Bz { cond=v86, target=b32, fall=b31 } (exit_acc=v86) + block 31 start_pc=0 + v87 Imm(12) -> x0 + terminator Return(v87) (exit_acc=v87) + block 32 start_pc=0 + v88 Imm(0) -> x3 + v89 Imm(0) -> x0 + terminator Jmp(b35) (exit_acc=v88) + block 33 start_pc=0 + v96 Imm(4294967286) -> x0 + v97 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x0 + v98 BinopI { op=add, lhs=v97, rhs_imm=4294967286 } -> x0 + v99 BinopI { op=and, lhs=v98, rhs_imm=4294967295 } -> x7 + v100 Call { target_pc=2, args=[v99], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v101 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x1 + v102 BinopI { op=add, lhs=v101, rhs_imm=1 } -> x1 + v103 BinopI { op=and, lhs=v102, rhs_imm=4294967295 } -> x1 + v104 BinopI { op=shl, lhs=v103, rhs_imm=32 } -> x2 + v105 Extend { value=v103, kind=I32 } -> x1 + v106 Binop { op=ne, lhs=v100, rhs=v105 } -> x0 + terminator Bnz { cond=v106, target=b43, fall=b34 } (exit_acc=v106) + block 34 start_pc=0 + v93 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x0 + v94 BinopI { op=add, lhs=v93, rhs_imm=1 } -> x3 + v95 Imm(0) -> x0 + terminator Jmp(b35) (exit_acc=v94) + block 35 start_pc=0 + v90 Phi { incoming=[b32:v88, b34:v94], kind=I64 } -> x3 + v91 BinopI { op=and, lhs=v90, rhs_imm=4294967295 } -> x0 + v92 BinopI { op=ult, lhs=v91, rhs_imm=10 } -> x0 + terminator Bnz { cond=v92, target=b33, fall=b36 } (exit_acc=v92) + block 36 start_pc=0 + v107 Imm(4294967285) -> x7 + v108 Call { target_pc=2, args=[v107], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v109 BinopI { op=ne, lhs=v108, rhs_imm=-1 } -> x0 + terminator Bz { cond=v109, target=b38, fall=b37 } (exit_acc=v109) + block 37 start_pc=0 + v111 Imm(14) -> x0 + terminator Return(v111) (exit_acc=v111) + block 38 start_pc=0 + v112 Imm(0) -> x7 + v113 Call { target_pc=2, args=[v112], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v114 BinopI { op=ne, lhs=v113, rhs_imm=-1 } -> x0 + terminator Bz { cond=v114, target=b40, fall=b39 } (exit_acc=v114) + block 39 start_pc=0 + v115 Imm(15) -> x0 + terminator Return(v115) (exit_acc=v115) + block 40 start_pc=0 + v116 Imm(2147483647) -> x7 + v117 Call { target_pc=2, args=[v116], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v118 BinopI { op=ne, lhs=v117, rhs_imm=-1 } -> x0 + terminator Bz { cond=v118, target=b42, fall=b41 } (exit_acc=v118) + block 41 start_pc=0 + v119 Imm(16) -> x0 + terminator Return(v119) (exit_acc=v119) + block 42 start_pc=0 + v120 Imm(0) -> x0 + terminator Return(v120) (exit_acc=v120) + block 43 start_pc=0 + v110 Imm(13) -> x0 + terminator Return(v110) (exit_acc=v110) + block 44 start_pc=0 + v74 Imm(8) -> x0 + terminator Return(v74) (exit_acc=v74) + block 45 start_pc=0 + v33 Imm(1) -> x0 + terminator Return(v33) (exit_acc=v33) + block 46 start_pc=0 + terminator Jmp(b6) + block 47 start_pc=0 + terminator Jmp(b6) + block 48 start_pc=0 + terminator Jmp(b22) + block 49 start_pc=0 + terminator Jmp(b34) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/switch_jump_table_phi_join.ssa b/tests/snapshots/ssa/switch_jump_table_phi_join.ssa new file mode 100644 index 000000000..795593131 --- /dev/null +++ b/tests/snapshots/ssa/switch_jump_table_phi_join.ssa @@ -0,0 +1,287 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=chain +fn ent_pc=0 n_params=3 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I64) -> x2 + v6 Imm(0) -> x0 + v7 LoadLocal { off=3, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=4, kind=I64 } -> x0 + v10 Imm(0) -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x0 + v12 BinopI { op=ult, lhs=v1, rhs_imm=12 } -> x0 + terminator Bz { cond=v12, target=b24, fall=b1 } (exit_acc=v12) + block 1 start_pc=0 + terminator JumpTable { idx=v1, table=0 } [b2, b13, b14, b15, b16, b17, b18, b19, b20, b21, b22, b23] (exit_acc=v1) + block 2 start_pc=0 + v19 LoadLocal { off=3, kind=I64 } -> x0 + v20 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x6 + v21 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v20) + block 3 start_pc=0 + v22 Phi { incoming=[b13:v3, b2:v20], kind=I64 } -> x6 + v23 LoadLocal { off=-1, kind=I64 } -> x0 + v24 BinopI { op=add, lhs=v22, rhs_imm=2 } -> x2 + v25 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v24) + block 4 start_pc=0 + v26 Phi { incoming=[b14:v5, b3:v24], kind=I64 } -> x2 + v27 Phi { incoming=[b14:v3, b3:v22], kind=I64 } -> x6 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + v29 LoadLocal { off=-2, kind=I64 } -> x0 + v30 Binop { op=add, lhs=v27, rhs=v26 } -> x6 + v31 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v30) + block 5 start_pc=0 + v32 Phi { incoming=[b15:v5, b4:v26], kind=I64 } -> x2 + v33 Phi { incoming=[b15:v3, b4:v30], kind=I64 } -> x6 + v34 LoadLocal { off=-2, kind=I64 } -> x0 + v35 BinopI { op=mul, lhs=v32, rhs_imm=3 } -> x2 + v36 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) + block 6 start_pc=0 + v37 Phi { incoming=[b16:v5, b5:v35], kind=I64 } -> x2 + v38 Phi { incoming=[b16:v3, b5:v33], kind=I64 } -> x6 + v39 LoadLocal { off=-1, kind=I64 } -> x0 + v40 LoadLocal { off=-2, kind=I64 } -> x0 + v41 Binop { op=sub, lhs=v38, rhs=v37 } -> x6 + v42 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v41) + block 7 start_pc=0 + v43 Phi { incoming=[b17:v5, b6:v37], kind=I64 } -> x2 + v44 Phi { incoming=[b17:v3, b6:v41], kind=I64 } -> x6 + v45 LoadLocal { off=-2, kind=I64 } -> x0 + v46 LoadLocal { off=-1, kind=I64 } -> x0 + v47 Binop { op=add, lhs=v43, rhs=v44 } -> x2 + v48 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v47) + block 8 start_pc=0 + v49 Phi { incoming=[b18:v5, b7:v47], kind=I64 } -> x2 + v50 Phi { incoming=[b18:v3, b7:v44], kind=I64 } -> x6 + v51 LoadLocal { off=-1, kind=I64 } -> x0 + v52 BinopI { op=shl, lhs=v50, rhs_imm=1 } -> x6 + v53 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v52) + block 9 start_pc=0 + v54 Phi { incoming=[b19:v5, b8:v49], kind=I64 } -> x2 + v55 Phi { incoming=[b19:v3, b8:v52], kind=I64 } -> x6 + v56 LoadLocal { off=-2, kind=I64 } -> x0 + v57 BinopI { op=sub, lhs=v54, rhs_imm=1 } -> x2 + v58 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v57) + block 10 start_pc=0 + v59 Phi { incoming=[b20:v5, b9:v57], kind=I64 } -> x2 + v60 Phi { incoming=[b20:v3, b9:v55], kind=I64 } -> x6 + v61 LoadLocal { off=-1, kind=I64 } -> x0 + v62 BinopI { op=add, lhs=v60, rhs_imm=7 } -> x6 + v63 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v62) + block 11 start_pc=0 + v64 Phi { incoming=[b21:v5, b10:v59], kind=I64 } -> x2 + v65 Phi { incoming=[b21:v3, b10:v62], kind=I64 } -> x6 + v66 LoadLocal { off=-2, kind=I64 } -> x0 + v67 LoadLocal { off=-1, kind=I64 } -> x0 + v68 Binop { op=add, lhs=v64, rhs=v65 } -> x2 + v69 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v68) + block 12 start_pc=0 + v13 Phi { incoming=[b24:v78, b11:v68, b22:v5, b23:v74], kind=I64 } -> x2 + v14 Phi { incoming=[b24:v76, b11:v65, b22:v71, b23:v3], kind=I64 } -> x6 + v15 LoadLocal { off=-1, kind=I64 } -> x0 + v16 BinopI { op=mul, lhs=v14, rhs_imm=31 } -> x0 + v17 LoadLocal { off=-2, kind=I64 } -> x1 + v18 Binop { op=add, lhs=v16, rhs=v13 } -> x0 + terminator Return(v18) (exit_acc=v18) + block 13 start_pc=0 + terminator Jmp(b3) + block 14 start_pc=0 + terminator Jmp(b4) + block 15 start_pc=0 + terminator Jmp(b5) + block 16 start_pc=0 + terminator Jmp(b6) + block 17 start_pc=0 + terminator Jmp(b7) + block 18 start_pc=0 + terminator Jmp(b8) + block 19 start_pc=0 + terminator Jmp(b9) + block 20 start_pc=0 + terminator Jmp(b10) + block 21 start_pc=0 + terminator Jmp(b11) + block 22 start_pc=0 + v70 LoadLocal { off=3, kind=I64 } -> x0 + v71 BinopI { op=mul, lhs=v3, rhs_imm=-1 } -> x6 + v72 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v71) + block 23 start_pc=0 + v73 LoadLocal { off=4, kind=I64 } -> x0 + v74 BinopI { op=mul, lhs=v5, rhs_imm=-1 } -> x2 + v75 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v74) + block 24 start_pc=0 + v76 Imm(13) -> x6 + v77 Imm(0) -> x0 + v78 Imm(17) -> x2 + v79 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v78) + block 25 start_pc=0 + terminator Jmp(b2) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=8 + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x1 + v2 Imm(0) -> x0 + v3 Imm(-2) -> x3 + v4 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v3) + block 1 start_pc=0 + v12 Imm(-1) -> x12 + v13 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v12) + block 2 start_pc=0 + v23 Imm(0) -> x2 + v24 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v23) + block 3 start_pc=0 + v25 LoadLocal { off=-4, kind=I64 } -> x0 + v26 Imm(1) -> x0 + v27 LoadLocal { off=-1, kind=I64 } -> x0 + v28 BinopI { op=mul, lhs=v17, rhs_imm=33 } -> x13 + v29 Extend { value=v5, kind=I32 } -> x0 + v30 LoadLocal { off=-3, kind=I64 } -> x0 + v31 LoadLocal { off=-4, kind=I64 } -> x0 + v32 Call { target_pc=0, args=[v5, v16, v23], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v33 Binop { op=add, lhs=v28, rhs=v32 } -> x0 + v34 Imm(0) -> x1 + v35 LoadLocal { off=-4, kind=I64 } -> x1 + v36 Imm(1) -> x2 + v37 Imm(0) -> x1 + v38 LoadLocal { off=-4, kind=I64 } -> x1 + v39 Imm(1) -> x1 + v40 LoadLocal { off=-1, kind=I64 } -> x1 + v41 BinopI { op=mul, lhs=v33, rhs_imm=33 } -> x13 + v42 Extend { value=v5, kind=I32 } -> x0 + v43 LoadLocal { off=-3, kind=I64 } -> x0 + v44 LoadLocal { off=-4, kind=I64 } -> x0 + v45 Call { target_pc=0, args=[v5, v16, v36], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v46 Binop { op=add, lhs=v41, rhs=v45 } -> x0 + v47 Imm(0) -> x1 + v48 LoadLocal { off=-4, kind=I64 } -> x1 + v49 Imm(2) -> x2 + v50 Imm(0) -> x1 + v51 LoadLocal { off=-4, kind=I64 } -> x1 + v52 Imm(1) -> x1 + v53 LoadLocal { off=-1, kind=I64 } -> x1 + v54 BinopI { op=mul, lhs=v46, rhs_imm=33 } -> x13 + v55 Extend { value=v5, kind=I32 } -> x0 + v56 LoadLocal { off=-3, kind=I64 } -> x0 + v57 LoadLocal { off=-4, kind=I64 } -> x0 + v58 Call { target_pc=0, args=[v5, v16, v49], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 + v59 Binop { op=add, lhs=v54, rhs=v58 } -> x1 + v60 Imm(0) -> x0 + v61 LoadLocal { off=-4, kind=I64 } -> x0 + v62 Imm(3) -> x0 + v63 Imm(0) -> x0 + v64 LoadLocal { off=-4, kind=I64 } -> x0 + v65 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v65) + block 4 start_pc=0 + v20 LoadLocal { off=-3, kind=I64 } -> x0 + v21 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x12 + v22 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v21) + block 5 start_pc=0 + v16 Phi { incoming=[b1:v12, b4:v21], kind=I64 } -> x12 + v17 Phi { incoming=[b1:v6, b4:v59], kind=I64 } -> x1 + v18 LoadLocal { off=-3, kind=I64 } -> x0 + v19 BinopI { op=lt, lhs=v16, rhs_imm=3 } -> x0 + terminator Bnz { cond=v19, target=b2, fall=b6 } (exit_acc=v19) + block 6 start_pc=0 + v9 Extend { value=v5, kind=I32 } -> x0 + v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x3 + v11 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v10) + block 7 start_pc=0 + v5 Phi { incoming=[b0:v3, b6:v10], kind=I64 } -> x3 + v6 Phi { incoming=[b0:v1, b6:v17], kind=I64 } -> x1 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=14 } -> x0 + terminator Bnz { cond=v8, target=b1, fall=b8 } (exit_acc=v8) + block 8 start_pc=0 + v14 LoadLocal { off=-1, kind=I64 } -> x0 + v15 BinopI { op=eq, lhs=v6, rhs_imm=-3365603682695239840 } -> x0 + terminator Bz { cond=v15, target=b11, fall=b9 } (exit_acc=v15) + block 9 start_pc=0 + v66 Imm(0) -> x1 + v67 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v66) + block 10 start_pc=0 + v70 Phi { incoming=[b9:v66, b11:v68], kind=I64 } -> x1 + v71 LoadLocal { off=-8, kind=I64 } -> x0 + terminator Return(v70) (exit_acc=v70) + block 11 start_pc=0 + v68 Imm(1) -> x1 + v69 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v68) + block 12 start_pc=0 + terminator Jmp(b6) + block 13 start_pc=0 + terminator Jmp(b4) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/switch_jump_table_sparse_kept.ssa b/tests/snapshots/ssa/switch_jump_table_sparse_kept.ssa new file mode 100644 index 000000000..75d6a8127 --- /dev/null +++ b/tests/snapshots/ssa/switch_jump_table_sparse_kept.ssa @@ -0,0 +1,213 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=sparse +fn ent_pc=0 n_params=1 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 BinopI { op=lt, lhs=v1, rhs_imm=50 } -> x0 + terminator Bnz { cond=v4, target=b16, fall=b1 } (exit_acc=v4) + block 1 start_pc=0 + v14 BinopI { op=lt, lhs=v1, rhs_imm=70 } -> x0 + terminator Bnz { cond=v14, target=b11, fall=b2 } (exit_acc=v14) + block 2 start_pc=0 + v18 BinopI { op=lt, lhs=v1, rhs_imm=80 } -> x0 + terminator Bnz { cond=v18, target=b9, fall=b3 } (exit_acc=v18) + block 3 start_pc=0 + v20 BinopI { op=lt, lhs=v1, rhs_imm=90 } -> x0 + terminator Bnz { cond=v20, target=b7, fall=b4 } (exit_acc=v20) + block 4 start_pc=0 + v22 BinopI { op=eq, lhs=v1, rhs_imm=90 } -> x0 + terminator Bnz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + block 5 start_pc=0 + v33 Imm(-1) -> x0 + terminator Return(v33) (exit_acc=v33) + block 6 start_pc=0 + v32 Imm(10) -> x0 + terminator Return(v32) (exit_acc=v32) + block 7 start_pc=0 + v21 BinopI { op=eq, lhs=v1, rhs_imm=80 } -> x0 + terminator Bz { cond=v21, target=b5, fall=b8 } (exit_acc=v21) + block 8 start_pc=0 + v31 Imm(9) -> x0 + terminator Return(v31) (exit_acc=v31) + block 9 start_pc=0 + v19 BinopI { op=eq, lhs=v1, rhs_imm=70 } -> x0 + terminator Bz { cond=v19, target=b5, fall=b10 } (exit_acc=v19) + block 10 start_pc=0 + v30 Imm(8) -> x0 + terminator Return(v30) (exit_acc=v30) + block 11 start_pc=0 + v15 BinopI { op=lt, lhs=v1, rhs_imm=60 } -> x0 + terminator Bnz { cond=v15, target=b14, fall=b12 } (exit_acc=v15) + block 12 start_pc=0 + v17 BinopI { op=eq, lhs=v1, rhs_imm=60 } -> x0 + terminator Bz { cond=v17, target=b5, fall=b13 } (exit_acc=v17) + block 13 start_pc=0 + v29 Imm(7) -> x0 + terminator Return(v29) (exit_acc=v29) + block 14 start_pc=0 + v16 BinopI { op=eq, lhs=v1, rhs_imm=50 } -> x0 + terminator Bz { cond=v16, target=b5, fall=b15 } (exit_acc=v16) + block 15 start_pc=0 + v28 Imm(6) -> x0 + terminator Return(v28) (exit_acc=v28) + block 16 start_pc=0 + v5 BinopI { op=lt, lhs=v1, rhs_imm=20 } -> x0 + terminator Bnz { cond=v5, target=b25, fall=b17 } (exit_acc=v5) + block 17 start_pc=0 + v9 BinopI { op=lt, lhs=v1, rhs_imm=30 } -> x0 + terminator Bnz { cond=v9, target=b23, fall=b18 } (exit_acc=v9) + block 18 start_pc=0 + v11 BinopI { op=lt, lhs=v1, rhs_imm=40 } -> x0 + terminator Bnz { cond=v11, target=b21, fall=b19 } (exit_acc=v11) + block 19 start_pc=0 + v13 BinopI { op=eq, lhs=v1, rhs_imm=40 } -> x0 + terminator Bz { cond=v13, target=b5, fall=b20 } (exit_acc=v13) + block 20 start_pc=0 + v27 Imm(5) -> x0 + terminator Return(v27) (exit_acc=v27) + block 21 start_pc=0 + v12 BinopI { op=eq, lhs=v1, rhs_imm=30 } -> x0 + terminator Bz { cond=v12, target=b5, fall=b22 } (exit_acc=v12) + block 22 start_pc=0 + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) + block 23 start_pc=0 + v10 BinopI { op=eq, lhs=v1, rhs_imm=20 } -> x0 + terminator Bz { cond=v10, target=b5, fall=b24 } (exit_acc=v10) + block 24 start_pc=0 + v25 Imm(3) -> x0 + terminator Return(v25) (exit_acc=v25) + block 25 start_pc=0 + v6 BinopI { op=lt, lhs=v1, rhs_imm=10 } -> x0 + terminator Bnz { cond=v6, target=b28, fall=b26 } (exit_acc=v6) + block 26 start_pc=0 + v8 BinopI { op=eq, lhs=v1, rhs_imm=10 } -> x0 + terminator Bz { cond=v8, target=b5, fall=b27 } (exit_acc=v8) + block 27 start_pc=0 + v24 Imm(2) -> x0 + terminator Return(v24) (exit_acc=v24) + block 28 start_pc=0 + v7 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 + terminator Bz { cond=v7, target=b5, fall=b29 } (exit_acc=v7) + block 29 start_pc=0 + v23 Imm(1) -> x0 + terminator Return(v23) (exit_acc=v23) + block 30 start_pc=0 + v34 Imm(0) -> x0 + terminator Return(v34) (exit_acc=v34) + block 31 start_pc=0 + terminator Jmp(b29) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x3 + v2 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v1) + block 1 start_pc=0 + v9 Extend { value=v3, kind=I32 } -> x0 + v10 BinopI { op=mul, lhs=v3, rhs_imm=10 } -> x7 + v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x0 + v12 Extend { value=v10, kind=I32 } -> x0 + v13 Call { target_pc=0, args=[v10], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v14 Extend { value=v3, kind=I32 } -> x1 + v15 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x1 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x2 + v17 Extend { value=v15, kind=I32 } -> x1 + v18 Binop { op=ne, lhs=v13, rhs=v17 } -> x0 + terminator Bnz { cond=v18, target=b11, fall=b2 } (exit_acc=v18) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x3 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=10 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) + block 4 start_pc=0 + v19 Imm(5) -> x7 + v20 Call { target_pc=0, args=[v19], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v21 BinopI { op=ne, lhs=v20, rhs_imm=-1 } -> x0 + terminator Bz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) + block 5 start_pc=0 + v23 Imm(2) -> x0 + terminator Return(v23) (exit_acc=v23) + block 6 start_pc=0 + v24 Imm(-10) -> x7 + v25 Call { target_pc=0, args=[v24], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v26 BinopI { op=ne, lhs=v25, rhs_imm=-1 } -> x0 + terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) + block 7 start_pc=0 + v27 Imm(3) -> x0 + terminator Return(v27) (exit_acc=v27) + block 8 start_pc=0 + v28 Imm(100) -> x7 + v29 Call { target_pc=0, args=[v28], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v30 BinopI { op=ne, lhs=v29, rhs_imm=-1 } -> x0 + terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + block 9 start_pc=0 + v31 Imm(4) -> x0 + terminator Return(v31) (exit_acc=v31) + block 10 start_pc=0 + v32 Imm(0) -> x0 + terminator Return(v32) (exit_acc=v32) + block 11 start_pc=0 + v22 Imm(1) -> x0 + terminator Return(v22) (exit_acc=v22) + block 12 start_pc=0 + terminator Jmp(b2) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/switch_label_after_terminator.ssa b/tests/snapshots/ssa/switch_label_after_terminator.ssa index 8721c1050..57c1e7daf 100644 --- a/tests/snapshots/ssa/switch_label_after_terminator.ssa +++ b/tests/snapshots/ssa/switch_label_after_terminator.ssa @@ -10,46 +10,46 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v4 Imm(0) -> x0 v5 LoadLocal { off=2, kind=I32 } -> x0 v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v6, target=b6, fall=b7 } (exit_acc=v6) + terminator Bnz { cond=v6, target=b8, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v7 Imm(0) -> x0 - terminator Return(v7) (exit_acc=v7) + v16 BinopI { op=lt, lhs=v1, rhs_imm=3 } -> x0 + terminator Bnz { cond=v16, target=b6, fall=b2 } (exit_acc=v16) block 2 start_pc=0 - v8 Imm(1) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v8) + v18 BinopI { op=eq, lhs=v1, rhs_imm=3 } -> x0 + terminator Bnz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v10 Imm(2) -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v10) + v14 Imm(-1) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 v12 Imm(3) -> x1 v13 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v12) + terminator Jmp(b5) (exit_acc=v12) block 5 start_pc=0 - v14 Imm(-1) -> x0 - terminator Return(v14) (exit_acc=v14) + v19 Phi { incoming=[b9:v8, b7:v10, b4:v12], kind=I64 } -> x1 + v20 Extend { value=v19, kind=I32 } -> x0 + v21 BinopI { op=add, lhs=v19, rhs_imm=100 } -> x0 + v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x1 + v23 Extend { value=v21, kind=I32 } -> x0 + terminator Return(v23) (exit_acc=v23) block 6 start_pc=0 - v15 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v15, target=b2, fall=b5 } (exit_acc=v15) + v17 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 + terminator Bz { cond=v17, target=b3, fall=b7 } (exit_acc=v17) block 7 start_pc=0 - v16 BinopI { op=lt, lhs=v1, rhs_imm=3 } -> x0 - terminator Bnz { cond=v16, target=b8, fall=b9 } (exit_acc=v16) + v10 Imm(2) -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v10) block 8 start_pc=0 - v17 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v17, target=b3, fall=b5 } (exit_acc=v17) + v15 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 + terminator Bz { cond=v15, target=b3, fall=b9 } (exit_acc=v15) block 9 start_pc=0 - v18 BinopI { op=eq, lhs=v1, rhs_imm=3 } -> x0 - terminator Bnz { cond=v18, target=b4, fall=b5 } (exit_acc=v18) + v8 Imm(1) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v8) block 10 start_pc=0 - terminator Jmp(b2) + v7 Imm(0) -> x0 + terminator Return(v7) (exit_acc=v7) block 11 start_pc=0 - v19 Phi { incoming=[b2:v8, b3:v10, b4:v12], kind=I64 } -> x1 - v20 Extend { value=v19, kind=I32 } -> x0 - v21 BinopI { op=add, lhs=v19, rhs_imm=100 } -> x0 - v22 BinopI { op=shl, lhs=v21, rhs_imm=32 } -> x1 - v23 Extend { value=v21, kind=I32 } -> x0 - terminator Return(v23) (exit_acc=v23) + terminator Jmp(b9) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_multilabel.ssa b/tests/snapshots/ssa/switch_multilabel.ssa index ffd8018e3..51f5c2581 100644 --- a/tests/snapshots/ssa/switch_multilabel.ssa +++ b/tests/snapshots/ssa/switch_multilabel.ssa @@ -8,92 +8,92 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=66 } -> x0 - terminator Bnz { cond=v4, target=b13, fall=b14 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b13, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v14 BinopI { op=lt, lhs=v1, rhs_imm=98 } -> x0 + terminator Bnz { cond=v14, target=b9, fall=b2 } (exit_acc=v14) block 2 start_pc=0 - terminator Jmp(b3) + v18 BinopI { op=lt, lhs=v1, rhs_imm=99 } -> x0 + terminator Bnz { cond=v18, target=b8, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - terminator Jmp(b4) + v20 BinopI { op=lt, lhs=v1, rhs_imm=100 } -> x0 + terminator Bnz { cond=v20, target=b7, fall=b4 } (exit_acc=v20) block 4 start_pc=0 - terminator Jmp(b5) + v22 BinopI { op=eq, lhs=v1, rhs_imm=100 } -> x0 + terminator Bnz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) block 5 start_pc=0 + v26 Imm(0) -> x0 + terminator Return(v26) (exit_acc=v26) + block 6 start_pc=0 v23 Imm(1) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 - terminator Jmp(b7) block 7 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v21 BinopI { op=eq, lhs=v1, rhs_imm=99 } -> x0 + terminator Bnz { cond=v21, target=b6, fall=b5 } (exit_acc=v21) block 8 start_pc=0 - terminator Jmp(b9) + v19 BinopI { op=eq, lhs=v1, rhs_imm=98 } -> x0 + terminator Bnz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) block 9 start_pc=0 - terminator Jmp(b10) + v15 BinopI { op=lt, lhs=v1, rhs_imm=97 } -> x0 + terminator Bnz { cond=v15, target=b11, fall=b10 } (exit_acc=v15) block 10 start_pc=0 - terminator Jmp(b11) + v17 BinopI { op=eq, lhs=v1, rhs_imm=97 } -> x0 + terminator Bnz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) block 11 start_pc=0 - v25 Imm(3) -> x0 - terminator Return(v25) (exit_acc=v25) + v16 BinopI { op=eq, lhs=v1, rhs_imm=66 } -> x0 + terminator Bz { cond=v16, target=b5, fall=b12 } (exit_acc=v16) block 12 start_pc=0 - v26 Imm(0) -> x0 - terminator Return(v26) (exit_acc=v26) + v24 Imm(2) -> x0 + terminator Return(v24) (exit_acc=v24) block 13 start_pc=0 v5 BinopI { op=lt, lhs=v1, rhs_imm=50 } -> x0 - terminator Bnz { cond=v5, target=b15, fall=b16 } (exit_acc=v5) + terminator Bnz { cond=v5, target=b20, fall=b14 } (exit_acc=v5) block 14 start_pc=0 - v14 BinopI { op=lt, lhs=v1, rhs_imm=98 } -> x0 - terminator Bnz { cond=v14, target=b23, fall=b24 } (exit_acc=v14) + v9 BinopI { op=lt, lhs=v1, rhs_imm=51 } -> x0 + terminator Bnz { cond=v9, target=b19, fall=b15 } (exit_acc=v9) block 15 start_pc=0 - v6 BinopI { op=lt, lhs=v1, rhs_imm=49 } -> x0 - terminator Bnz { cond=v6, target=b17, fall=b18 } (exit_acc=v6) + v11 BinopI { op=lt, lhs=v1, rhs_imm=65 } -> x0 + terminator Bnz { cond=v11, target=b17, fall=b16 } (exit_acc=v11) block 16 start_pc=0 - v9 BinopI { op=lt, lhs=v1, rhs_imm=51 } -> x0 - terminator Bnz { cond=v9, target=b19, fall=b20 } (exit_acc=v9) + v13 BinopI { op=eq, lhs=v1, rhs_imm=65 } -> x0 + terminator Bnz { cond=v13, target=b12, fall=b5 } (exit_acc=v13) block 17 start_pc=0 - v7 BinopI { op=eq, lhs=v1, rhs_imm=48 } -> x0 - terminator Bnz { cond=v7, target=b8, fall=b12 } (exit_acc=v7) + v12 BinopI { op=eq, lhs=v1, rhs_imm=51 } -> x0 + terminator Bz { cond=v12, target=b5, fall=b18 } (exit_acc=v12) block 18 start_pc=0 - v8 BinopI { op=eq, lhs=v1, rhs_imm=49 } -> x0 - terminator Bnz { cond=v8, target=b9, fall=b12 } (exit_acc=v8) + v25 Imm(3) -> x0 + terminator Return(v25) (exit_acc=v25) block 19 start_pc=0 v10 BinopI { op=eq, lhs=v1, rhs_imm=50 } -> x0 - terminator Bnz { cond=v10, target=b10, fall=b12 } (exit_acc=v10) + terminator Bnz { cond=v10, target=b18, fall=b5 } (exit_acc=v10) block 20 start_pc=0 - v11 BinopI { op=lt, lhs=v1, rhs_imm=65 } -> x0 - terminator Bnz { cond=v11, target=b21, fall=b22 } (exit_acc=v11) + v6 BinopI { op=lt, lhs=v1, rhs_imm=49 } -> x0 + terminator Bnz { cond=v6, target=b22, fall=b21 } (exit_acc=v6) block 21 start_pc=0 - v12 BinopI { op=eq, lhs=v1, rhs_imm=51 } -> x0 - terminator Bnz { cond=v12, target=b11, fall=b12 } (exit_acc=v12) + v8 BinopI { op=eq, lhs=v1, rhs_imm=49 } -> x0 + terminator Bnz { cond=v8, target=b18, fall=b5 } (exit_acc=v8) block 22 start_pc=0 - v13 BinopI { op=eq, lhs=v1, rhs_imm=65 } -> x0 - terminator Bnz { cond=v13, target=b6, fall=b12 } (exit_acc=v13) + v7 BinopI { op=eq, lhs=v1, rhs_imm=48 } -> x0 + terminator Bnz { cond=v7, target=b18, fall=b5 } (exit_acc=v7) block 23 start_pc=0 - v15 BinopI { op=lt, lhs=v1, rhs_imm=97 } -> x0 - terminator Bnz { cond=v15, target=b25, fall=b26 } (exit_acc=v15) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 24 start_pc=0 - v18 BinopI { op=lt, lhs=v1, rhs_imm=99 } -> x0 - terminator Bnz { cond=v18, target=b27, fall=b28 } (exit_acc=v18) + terminator Jmp(b6) block 25 start_pc=0 - v16 BinopI { op=eq, lhs=v1, rhs_imm=66 } -> x0 - terminator Bnz { cond=v16, target=b7, fall=b12 } (exit_acc=v16) + terminator Jmp(b6) block 26 start_pc=0 - v17 BinopI { op=eq, lhs=v1, rhs_imm=97 } -> x0 - terminator Bnz { cond=v17, target=b2, fall=b12 } (exit_acc=v17) + terminator Jmp(b6) block 27 start_pc=0 - v19 BinopI { op=eq, lhs=v1, rhs_imm=98 } -> x0 - terminator Bnz { cond=v19, target=b3, fall=b12 } (exit_acc=v19) + terminator Jmp(b12) block 28 start_pc=0 - v20 BinopI { op=lt, lhs=v1, rhs_imm=100 } -> x0 - terminator Bnz { cond=v20, target=b29, fall=b30 } (exit_acc=v20) + terminator Jmp(b18) block 29 start_pc=0 - v21 BinopI { op=eq, lhs=v1, rhs_imm=99 } -> x0 - terminator Bnz { cond=v21, target=b4, fall=b12 } (exit_acc=v21) + terminator Jmp(b18) block 30 start_pc=0 - v22 BinopI { op=eq, lhs=v1, rhs_imm=100 } -> x0 - terminator Bnz { cond=v22, target=b5, fall=b12 } (exit_acc=v22) + terminator Jmp(b18) block 31 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_nested_case_in_compound.ssa b/tests/snapshots/ssa/switch_nested_case_in_compound.ssa index a3c33d829..8161c9e9c 100644 --- a/tests/snapshots/ssa/switch_nested_case_in_compound.ssa +++ b/tests/snapshots/ssa/switch_nested_case_in_compound.ssa @@ -1,33 +1,24 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x3 + v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(2) -> x0 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-2, kind=I32 } -> x1 - v6 BinopI { op=lt, lhs=v3, rhs_imm=2 } -> x1 - terminator Bnz { cond=v6, target=b5, fall=b6 } (exit_acc=v6) + v4 Imm(0) -> x0 + v5 LoadLocal { off=-2, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b3:v26, b29:v1, b12:v42, b31:v1, b32:v1, b4:v30], kind=I64 } -> x3 - v8 Extend { value=v7, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=7 } -> x0 - terminator Bz { cond=v9, target=b14, fall=b13 } (exit_acc=v9) + v34 Imm(1) -> x0 + terminator Jmp(b2) (exit_acc=v34) block 2 start_pc=0 - v10 Imm(100) -> x0 - v11 Imm(0) -> x1 - v12 LoadLocal { off=-1, kind=I32 } -> x1 - v13 LoadLocal { off=-3, kind=I32 } -> x1 - v14 Binop { op=add, lhs=v1, rhs=v10 } -> x1 - v15 Imm(0) -> x2 - v16 Extend { value=v14, kind=I32 } -> x2 - v17 BinopI { op=eq, lhs=v10, rhs_imm=100 } -> x0 - terminator Bz { cond=v17, target=b12, fall=b10 } (exit_acc=v17) + v35 Imm(1) -> x0 + terminator Jmp(b3) (exit_acc=v35) block 3 start_pc=0 - v18 Phi { incoming=[b11:v38, b30:v1], kind=I64 } -> x3 + v18 Phi { incoming=[b21:v38, b2:v1], kind=I64 } -> x1 v19 Extend { value=v18, kind=I32 } -> x0 v20 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x0 v21 Imm(0) -> x1 @@ -35,75 +26,52 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 v23 BinopI { op=add, lhs=v20, rhs_imm=2 } -> x0 v24 Imm(0) -> x1 v25 Extend { value=v23, kind=I32 } -> x1 - v26 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x3 + v26 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x1 v27 Imm(0) -> x0 v28 Extend { value=v26, kind=I32 } -> x0 - terminator Jmp(b1) (exit_acc=v28) + terminator Jmp(b4) (exit_acc=v28) block 4 start_pc=0 - v29 LoadLocal { off=-1, kind=I32 } -> x0 - v30 BinopI { op=or, lhs=v1, rhs_imm=16384 } -> x3 - v31 Imm(0) -> x0 - v32 Extend { value=v30, kind=I32 } -> x0 - terminator Jmp(b1) (exit_acc=v32) + v7 Phi { incoming=[b3:v26, b17:v1, b22:v42, b2:v1, b18:v1, b16:v30], kind=I64 } -> x1 + v8 Extend { value=v7, kind=I32 } -> x0 + v9 BinopI { op=ne, lhs=v8, rhs_imm=7 } -> x0 + terminator Bz { cond=v9, target=b6, fall=b5 } (exit_acc=v9) block 5 start_pc=0 - v33 BinopI { op=eq, lhs=v3, rhs_imm=1 } -> x0 - terminator Bnz { cond=v33, target=b2, fall=b29 } (exit_acc=v33) - block 6 start_pc=0 - v34 BinopI { op=lt, lhs=v3, rhs_imm=3 } -> x1 - terminator Bnz { cond=v34, target=b7, fall=b8 } (exit_acc=v34) - block 7 start_pc=0 - v35 BinopI { op=eq, lhs=v3, rhs_imm=2 } -> x0 - terminator Bnz { cond=v35, target=b30, fall=b31 } (exit_acc=v35) - block 8 start_pc=0 - v36 BinopI { op=eq, lhs=v3, rhs_imm=3 } -> x0 - terminator Bnz { cond=v36, target=b4, fall=b32 } (exit_acc=v36) - block 9 start_pc=0 - terminator Jmp(b2) - block 10 start_pc=0 - v37 Extend { value=v14, kind=I32 } -> x0 - v38 BinopI { op=or, lhs=v14, rhs_imm=4096 } -> x3 - v39 Imm(0) -> x0 - v40 Extend { value=v38, kind=I32 } -> x0 - terminator Jmp(b11) (exit_acc=v40) - block 11 start_pc=0 - terminator Jmp(b3) - block 12 start_pc=0 - v41 Extend { value=v14, kind=I32 } -> x0 - v42 BinopI { op=or, lhs=v14, rhs_imm=8192 } -> x3 - v43 Imm(0) -> x0 - v44 Extend { value=v42, kind=I32 } -> x0 - terminator Jmp(b1) (exit_acc=v44) - block 13 start_pc=0 v45 ImmData(36) -> x7 v46 Extend { value=v7, kind=I32 } -> x6 v47 CallExt { binding_idx=0, args=[v45, v46], fp_arg_mask=0x0 } -> x0 v48 Imm(1) -> x0 terminator Return(v48) (exit_acc=v48) - block 14 start_pc=0 - v49 Imm(0) -> x3 + block 6 start_pc=0 + v49 Imm(0) -> x1 v50 Imm(0) -> x0 v51 Imm(1) -> x0 - v52 Imm(0) -> x1 - v53 LoadLocal { off=-2, kind=I32 } -> x1 - v54 BinopI { op=lt, lhs=v51, rhs_imm=2 } -> x1 - terminator Bnz { cond=v54, target=b19, fall=b20 } (exit_acc=v54) - block 15 start_pc=0 - v55 Phi { incoming=[b17:v74, b33:v49, b26:v90, b35:v49, b36:v49, b18:v78], kind=I64 } -> x3 - v56 Extend { value=v55, kind=I32 } -> x0 - v57 BinopI { op=ne, lhs=v56, rhs_imm=4203 } -> x0 - terminator Bz { cond=v57, target=b28, fall=b27 } (exit_acc=v57) - block 16 start_pc=0 + v52 Imm(0) -> x0 + v53 LoadLocal { off=-2, kind=I32 } -> x0 + v54 Imm(1) -> x0 + terminator Jmp(b7) (exit_acc=v54) + block 7 start_pc=0 + v81 Imm(1) -> x0 + terminator Jmp(b8) (exit_acc=v81) + block 8 start_pc=0 v58 Imm(100) -> x0 - v59 Imm(0) -> x1 - v60 LoadLocal { off=-1, kind=I32 } -> x1 - v61 LoadLocal { off=-4, kind=I32 } -> x1 - v62 Binop { op=add, lhs=v49, rhs=v58 } -> x1 - v63 Imm(0) -> x2 - v64 Extend { value=v62, kind=I32 } -> x2 - v65 BinopI { op=eq, lhs=v58, rhs_imm=100 } -> x0 - terminator Bz { cond=v65, target=b26, fall=b24 } (exit_acc=v65) - block 17 start_pc=0 - v66 Phi { incoming=[b25:v86, b34:v49], kind=I64 } -> x3 + v59 Imm(0) -> x0 + v60 LoadLocal { off=-1, kind=I32 } -> x0 + v61 LoadLocal { off=-4, kind=I32 } -> x0 + v62 Imm(100) -> x0 + v63 Imm(0) -> x0 + v64 Imm(100) -> x0 + v65 Imm(1) -> x0 + terminator Jmp(b9) (exit_acc=v65) + block 9 start_pc=0 + v85 Imm(100) -> x0 + v86 Imm(4196) -> x1 + v87 Imm(0) -> x0 + v88 Imm(4196) -> x0 + terminator Jmp(b10) (exit_acc=v88) + block 10 start_pc=0 + terminator Jmp(b11) + block 11 start_pc=0 + v66 Phi { incoming=[b10:v86, b25:v49], kind=I64 } -> x1 v67 Extend { value=v66, kind=I32 } -> x0 v68 BinopI { op=add, lhs=v66, rhs_imm=1 } -> x0 v69 Imm(0) -> x1 @@ -111,69 +79,85 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 v71 BinopI { op=add, lhs=v68, rhs_imm=2 } -> x0 v72 Imm(0) -> x1 v73 Extend { value=v71, kind=I32 } -> x1 - v74 BinopI { op=add, lhs=v71, rhs_imm=4 } -> x3 + v74 BinopI { op=add, lhs=v71, rhs_imm=4 } -> x1 v75 Imm(0) -> x0 v76 Extend { value=v74, kind=I32 } -> x0 - terminator Jmp(b15) (exit_acc=v76) + terminator Jmp(b12) (exit_acc=v76) + block 12 start_pc=0 + v55 Phi { incoming=[b11:v74, b7:v49, b28:v90, b25:v49, b26:v49, b23:v78], kind=I64 } -> x1 + v56 Extend { value=v55, kind=I32 } -> x0 + v57 BinopI { op=ne, lhs=v56, rhs_imm=4203 } -> x0 + terminator Bz { cond=v57, target=b14, fall=b13 } (exit_acc=v57) + block 13 start_pc=0 + v93 ImmData(57) -> x7 + v94 Extend { value=v55, kind=I32 } -> x6 + v95 CallExt { binding_idx=0, args=[v93, v94], fp_arg_mask=0x0 } -> x0 + v96 Imm(2) -> x0 + terminator Return(v96) (exit_acc=v96) + block 14 start_pc=0 + v97 Imm(0) -> x0 + terminator Return(v97) (exit_acc=v97) + block 15 start_pc=0 + v10 Imm(100) -> x0 + v11 Imm(0) -> x0 + v12 LoadLocal { off=-1, kind=I32 } -> x0 + v13 LoadLocal { off=-3, kind=I32 } -> x0 + v14 Imm(100) -> x0 + v15 Imm(0) -> x0 + v16 Imm(100) -> x0 + v17 Imm(1) -> x0 + terminator Jmp(b20) (exit_acc=v17) + block 16 start_pc=0 + v29 LoadLocal { off=-1, kind=I32 } -> x0 + v30 Imm(16384) -> x1 + v31 Imm(0) -> x0 + v32 Imm(16384) -> x0 + terminator Jmp(b4) (exit_acc=v32) + block 17 start_pc=0 + v33 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v33) block 18 start_pc=0 - v77 LoadLocal { off=-1, kind=I32 } -> x0 - v78 BinopI { op=or, lhs=v49, rhs_imm=16384 } -> x3 - v79 Imm(0) -> x0 - v80 Extend { value=v78, kind=I32 } -> x0 - terminator Jmp(b15) (exit_acc=v80) + v36 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v36) block 19 start_pc=0 - v81 BinopI { op=eq, lhs=v51, rhs_imm=1 } -> x0 - terminator Bnz { cond=v81, target=b16, fall=b33 } (exit_acc=v81) + terminator Jmp(b15) block 20 start_pc=0 - v82 BinopI { op=lt, lhs=v51, rhs_imm=3 } -> x1 - terminator Bnz { cond=v82, target=b21, fall=b22 } (exit_acc=v82) + v37 Imm(100) -> x0 + v38 Imm(4196) -> x1 + v39 Imm(0) -> x0 + v40 Imm(4196) -> x0 + terminator Jmp(b21) (exit_acc=v40) block 21 start_pc=0 - v83 BinopI { op=eq, lhs=v51, rhs_imm=2 } -> x0 - terminator Bnz { cond=v83, target=b34, fall=b35 } (exit_acc=v83) + terminator Jmp(b3) block 22 start_pc=0 - v84 BinopI { op=eq, lhs=v51, rhs_imm=3 } -> x0 - terminator Bnz { cond=v84, target=b18, fall=b36 } (exit_acc=v84) + v41 Imm(100) -> x0 + v42 Imm(8292) -> x1 + v43 Imm(0) -> x0 + v44 Imm(8292) -> x0 + terminator Jmp(b4) (exit_acc=v44) block 23 start_pc=0 - terminator Jmp(b16) + v77 LoadLocal { off=-1, kind=I32 } -> x0 + v78 Imm(16384) -> x1 + v79 Imm(0) -> x0 + v80 Imm(16384) -> x0 + terminator Jmp(b12) (exit_acc=v80) block 24 start_pc=0 - v85 Extend { value=v62, kind=I32 } -> x0 - v86 BinopI { op=or, lhs=v62, rhs_imm=4096 } -> x3 - v87 Imm(0) -> x0 - v88 Extend { value=v86, kind=I32 } -> x0 - terminator Jmp(b25) (exit_acc=v88) + v82 Imm(1) -> x0 + terminator Jmp(b25) (exit_acc=v82) block 25 start_pc=0 - terminator Jmp(b17) + v83 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v83) block 26 start_pc=0 - v89 Extend { value=v62, kind=I32 } -> x0 - v90 BinopI { op=or, lhs=v62, rhs_imm=8192 } -> x3 - v91 Imm(0) -> x0 - v92 Extend { value=v90, kind=I32 } -> x0 - terminator Jmp(b15) (exit_acc=v92) + v84 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v84) block 27 start_pc=0 - v93 ImmData(57) -> x7 - v94 Extend { value=v55, kind=I32 } -> x6 - v95 CallExt { binding_idx=0, args=[v93, v94], fp_arg_mask=0x0 } -> x0 - v96 Imm(2) -> x0 - terminator Return(v96) (exit_acc=v96) + terminator Jmp(b8) block 28 start_pc=0 - v97 Imm(0) -> x0 - terminator Return(v97) (exit_acc=v97) - block 29 start_pc=0 - terminator Jmp(b1) - block 30 start_pc=0 - terminator Jmp(b3) - block 31 start_pc=0 - terminator Jmp(b1) - block 32 start_pc=0 - terminator Jmp(b1) - block 33 start_pc=0 - terminator Jmp(b15) - block 34 start_pc=0 - terminator Jmp(b17) - block 35 start_pc=0 - terminator Jmp(b15) - block 36 start_pc=0 - terminator Jmp(b15) + v89 Imm(100) -> x0 + v90 Imm(8292) -> x1 + v91 Imm(0) -> x0 + v92 Imm(8292) -> x0 + terminator Jmp(b12) (exit_acc=v92) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_statement.ssa b/tests/snapshots/ssa/switch_statement.ssa index cbbf4b2a7..d8136a3ca 100644 --- a/tests/snapshots/ssa/switch_statement.ssa +++ b/tests/snapshots/ssa/switch_statement.ssa @@ -5,52 +5,50 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(0) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x1 - v5 LoadLocal { off=-1, kind=I32 } -> x1 - v6 BinopI { op=lt, lhs=v1, rhs_imm=2 } -> x1 - terminator Bnz { cond=v6, target=b6, fall=b7 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(0) -> x1 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Phi { incoming=[b5:v19, b2:v9, b4:v17], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x0 - terminator Return(v8) (exit_acc=v8) + v22 Imm(1) -> x0 + terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 - v9 Imm(10) -> x0 - v10 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v9) + v23 Imm(1) -> x0 + terminator Jmp(b3) (exit_acc=v23) block 3 start_pc=0 - v11 Imm(20) -> x2 + v11 Imm(20) -> x1 v12 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v11) block 4 start_pc=0 - v13 Phi { incoming=[b3:v11, b11:v3], kind=I64 } -> x2 + v13 Phi { incoming=[b3:v11, b9:v3], kind=I64 } -> x1 v14 Extend { value=v13, kind=I32 } -> x0 v15 BinopI { op=add, lhs=v13, rhs_imm=5 } -> x0 v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 v17 Extend { value=v15, kind=I32 } -> x0 v18 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v17) + terminator Jmp(b5) (exit_acc=v17) block 5 start_pc=0 - v19 Imm(100) -> x0 - v20 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v19) + v7 Phi { incoming=[b7:v19, b6:v9, b4:v17], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x0 + terminator Return(v8) (exit_acc=v8) block 6 start_pc=0 - v21 BinopI { op=eq, lhs=v1, rhs_imm=1 } -> x0 - terminator Bnz { cond=v21, target=b2, fall=b5 } (exit_acc=v21) + v9 Imm(10) -> x0 + v10 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v9) block 7 start_pc=0 - v22 BinopI { op=lt, lhs=v1, rhs_imm=3 } -> x1 - terminator Bnz { cond=v22, target=b8, fall=b9 } (exit_acc=v22) + v19 Imm(100) -> x0 + v20 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v19) block 8 start_pc=0 - v23 BinopI { op=eq, lhs=v1, rhs_imm=2 } -> x0 - terminator Bnz { cond=v23, target=b3, fall=b5 } (exit_acc=v23) + v21 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v21) block 9 start_pc=0 - v24 BinopI { op=eq, lhs=v1, rhs_imm=3 } -> x0 - terminator Bnz { cond=v24, target=b11, fall=b5 } (exit_acc=v24) + v24 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v24) block 10 start_pc=0 - terminator Jmp(b2) - block 11 start_pc=0 - terminator Jmp(b4) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/switch_unsigned_negative_case.ssa b/tests/snapshots/ssa/switch_unsigned_negative_case.ssa index 04955a63f..fba7084e3 100644 --- a/tests/snapshots/ssa/switch_unsigned_negative_case.ssa +++ b/tests/snapshots/ssa/switch_unsigned_negative_case.ssa @@ -8,36 +8,36 @@ fn ent_pc=0 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 BinopI { op=and, lhs=v1, rhs_imm=4294967295 } -> x0 v4 BinopI { op=ult, lhs=v3, rhs_imm=4294967294 } -> x1 - terminator Bnz { cond=v4, target=b6, fall=b7 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b7, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v13 Imm(0) -> x0 - terminator Return(v13) (exit_acc=v13) + v6 BinopI { op=ult, lhs=v3, rhs_imm=4294967295 } -> x1 + terminator Bnz { cond=v6, target=b5, fall=b2 } (exit_acc=v6) block 2 start_pc=0 - v9 Imm(100) -> x0 - terminator Return(v9) (exit_acc=v9) + v8 BinopI { op=eq, lhs=v3, rhs_imm=4294967295 } -> x0 + terminator Bnz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) block 3 start_pc=0 - v10 Imm(200) -> x0 - terminator Return(v10) (exit_acc=v10) - block 4 start_pc=0 - v11 Imm(5) -> x0 - terminator Return(v11) (exit_acc=v11) - block 5 start_pc=0 v12 Imm(999) -> x0 terminator Return(v12) (exit_acc=v12) + block 4 start_pc=0 + v9 Imm(100) -> x0 + terminator Return(v9) (exit_acc=v9) + block 5 start_pc=0 + v7 BinopI { op=eq, lhs=v3, rhs_imm=4294967294 } -> x0 + terminator Bz { cond=v7, target=b3, fall=b6 } (exit_acc=v7) block 6 start_pc=0 - v5 BinopI { op=eq, lhs=v3, rhs_imm=5 } -> x0 - terminator Bnz { cond=v5, target=b4, fall=b5 } (exit_acc=v5) + v10 Imm(200) -> x0 + terminator Return(v10) (exit_acc=v10) block 7 start_pc=0 - v6 BinopI { op=ult, lhs=v3, rhs_imm=4294967295 } -> x1 - terminator Bnz { cond=v6, target=b8, fall=b9 } (exit_acc=v6) + v5 BinopI { op=eq, lhs=v3, rhs_imm=5 } -> x0 + terminator Bz { cond=v5, target=b3, fall=b8 } (exit_acc=v5) block 8 start_pc=0 - v7 BinopI { op=eq, lhs=v3, rhs_imm=4294967294 } -> x0 - terminator Bnz { cond=v7, target=b3, fall=b5 } (exit_acc=v7) + v11 Imm(5) -> x0 + terminator Return(v11) (exit_acc=v11) block 9 start_pc=0 - v8 BinopI { op=eq, lhs=v3, rhs_imm=4294967295 } -> x0 - terminator Bnz { cond=v8, target=b2, fall=b5 } (exit_acc=v8) + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) block 10 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=u16 fn ent_pc=1 n_params=1 variadic=false locals=0 @@ -48,27 +48,27 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 BinopI { op=and, lhs=v1, rhs_imm=65535 } -> x0 v4 BinopI { op=ult, lhs=v3, rhs_imm=-1 } -> x1 - terminator Bnz { cond=v4, target=b5, fall=b6 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b4, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v10 Imm(0) -> x0 - terminator Return(v10) (exit_acc=v10) + v6 BinopI { op=eq, lhs=v3, rhs_imm=-1 } -> x0 + terminator Bnz { cond=v6, target=b3, fall=b2 } (exit_acc=v6) block 2 start_pc=0 + v9 Imm(999) -> x0 + terminator Return(v9) (exit_acc=v9) + block 3 start_pc=0 v7 Imm(100) -> x0 terminator Return(v7) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(7) -> x0 - terminator Return(v8) (exit_acc=v8) block 4 start_pc=0 - v9 Imm(999) -> x0 - terminator Return(v9) (exit_acc=v9) - block 5 start_pc=0 v5 BinopI { op=eq, lhs=v3, rhs_imm=7 } -> x0 - terminator Bnz { cond=v5, target=b3, fall=b4 } (exit_acc=v5) + terminator Bz { cond=v5, target=b2, fall=b5 } (exit_acc=v5) + block 5 start_pc=0 + v8 Imm(7) -> x0 + terminator Return(v8) (exit_acc=v8) block 6 start_pc=0 - v6 BinopI { op=eq, lhs=v3, rhs_imm=-1 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b4 } (exit_acc=v6) + v10 Imm(0) -> x0 + terminator Return(v10) (exit_acc=v10) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=u8 fn ent_pc=2 n_params=1 variadic=false locals=0 @@ -79,27 +79,27 @@ fn ent_pc=2 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 BinopI { op=and, lhs=v1, rhs_imm=255 } -> x0 v4 BinopI { op=ult, lhs=v3, rhs_imm=-1 } -> x1 - terminator Bnz { cond=v4, target=b5, fall=b6 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b4, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v10 Imm(0) -> x0 - terminator Return(v10) (exit_acc=v10) + v6 BinopI { op=eq, lhs=v3, rhs_imm=-1 } -> x0 + terminator Bnz { cond=v6, target=b3, fall=b2 } (exit_acc=v6) block 2 start_pc=0 + v9 Imm(999) -> x0 + terminator Return(v9) (exit_acc=v9) + block 3 start_pc=0 v7 Imm(100) -> x0 terminator Return(v7) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(3) -> x0 - terminator Return(v8) (exit_acc=v8) block 4 start_pc=0 - v9 Imm(999) -> x0 - terminator Return(v9) (exit_acc=v9) - block 5 start_pc=0 v5 BinopI { op=eq, lhs=v3, rhs_imm=3 } -> x0 - terminator Bnz { cond=v5, target=b3, fall=b4 } (exit_acc=v5) + terminator Bz { cond=v5, target=b2, fall=b5 } (exit_acc=v5) + block 5 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) block 6 start_pc=0 - v6 BinopI { op=eq, lhs=v3, rhs_imm=-1 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b4 } (exit_acc=v6) + v10 Imm(0) -> x0 + terminator Return(v10) (exit_acc=v10) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=s32 fn ent_pc=3 n_params=1 variadic=false locals=0 @@ -110,27 +110,27 @@ fn ent_pc=3 n_params=1 variadic=false locals=0 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 BinopI { op=lt, lhs=v1, rhs_imm=-1 } -> x0 - terminator Bnz { cond=v4, target=b5, fall=b6 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b4, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v10 Imm(0) -> x0 - terminator Return(v10) (exit_acc=v10) + v6 BinopI { op=eq, lhs=v1, rhs_imm=-1 } -> x0 + terminator Bnz { cond=v6, target=b3, fall=b2 } (exit_acc=v6) block 2 start_pc=0 + v9 Imm(999) -> x0 + terminator Return(v9) (exit_acc=v9) + block 3 start_pc=0 v7 Imm(100) -> x0 terminator Return(v7) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(200) -> x0 - terminator Return(v8) (exit_acc=v8) block 4 start_pc=0 - v9 Imm(999) -> x0 - terminator Return(v9) (exit_acc=v9) - block 5 start_pc=0 v5 BinopI { op=eq, lhs=v1, rhs_imm=-2 } -> x0 - terminator Bnz { cond=v5, target=b3, fall=b4 } (exit_acc=v5) + terminator Bz { cond=v5, target=b2, fall=b5 } (exit_acc=v5) + block 5 start_pc=0 + v8 Imm(200) -> x0 + terminator Return(v8) (exit_acc=v8) block 6 start_pc=0 - v6 BinopI { op=eq, lhs=v1, rhs_imm=-1 } -> x0 - terminator Bnz { cond=v6, target=b2, fall=b4 } (exit_acc=v6) + v10 Imm(0) -> x0 + terminator Return(v10) (exit_acc=v10) block 7 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=4 --- ; name=main fn ent_pc=4 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/sxtw_fold_source_liveness.ssa b/tests/snapshots/ssa/sxtw_fold_source_liveness.ssa index cd0fb70af..efa032c8a 100644 --- a/tests/snapshots/ssa/sxtw_fold_source_liveness.ssa +++ b/tests/snapshots/ssa/sxtw_fold_source_liveness.ssa @@ -29,19 +29,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(7) -> x1 - v3 Imm(0) -> x2 - v4 Imm(0) -> x2 - v5 BinopI { op=shl, lhs=v1, rhs_imm=32 } -> x2 - v6 Imm(0) -> x6 - v7 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v8 Imm(0) -> x6 - v9 BinopI { op=shr, lhs=v5, rhs_imm=32 } -> x2 - v10 Imm(0) -> x6 - v11 Binop { op=add, lhs=v9, rhs=v7 } -> x0 - v12 Binop { op=add, lhs=v11, rhs=v2 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x0 + v2 Imm(7) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(8589934592) -> x0 + v6 Imm(0) -> x0 + v7 Imm(9) -> x0 + v8 Imm(0) -> x0 + v9 Imm(2) -> x0 + v10 Imm(0) -> x0 + v11 Imm(11) -> x0 + v12 Imm(18) -> x0 + v13 Imm(77309411328) -> x0 + v14 Imm(18) -> x0 terminator Return(v14) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/symbol_inner_array_size_no_leak.ssa b/tests/snapshots/ssa/symbol_inner_array_size_no_leak.ssa index d6dbe5330..8faf663c8 100644 --- a/tests/snapshots/ssa/symbol_inner_array_size_no_leak.ssa +++ b/tests/snapshots/ssa/symbol_inner_array_size_no_leak.ssa @@ -10,31 +10,31 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 v5 Imm(0) -> x1 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v7 Phi { incoming=[b0:v5, b2:v12], kind=I64 } -> x1 - v8 Extend { value=v7, kind=I32 } -> x0 - v9 LoadLocal { off=3, kind=I32 } -> x2 - v10 Binop { op=lt, lhs=v8, rhs=v3 } -> x0 - terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) - block 2 start_pc=0 - v11 Extend { value=v7, kind=I32 } -> x0 - v12 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 - v13 Imm(0) -> x0 - v14 Extend { value=v12, kind=I32 } -> x0 - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 - v15 LoadLocal { off=2, kind=I64 } -> x0 - v16 Extend { value=v7, kind=I32 } -> x0 - v17 BinopI { op=shl, lhs=v16, rhs_imm=1 } -> x2 + v15 LoadLocal { off=2, kind=I64 } -> x2 + v16 Extend { value=v7, kind=I32 } -> x2 + v17 BinopI { op=shl, lhs=v8, rhs_imm=1 } -> x2 v18 Binop { op=add, lhs=v1, rhs=v17 } -> x2 - v19 BinopI { op=mul, lhs=v16, rhs_imm=3 } -> x2 + v19 BinopI { op=mul, lhs=v8, rhs_imm=3 } -> x2 v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x8 v21 Extend { value=v19, kind=I32 } -> x8 v22 BinopI { op=shl, lhs=v19, rhs_imm=48 } -> x2 v23 Extend { value=v21, kind=I16 } -> x2 - v24 StoreIndexed { base=v1, index=v16, scale=2, value=v21, kind=I16 } -> - + v24 StoreIndexed { base=v1, index=v8, scale=2, value=v21, kind=I16 } -> - terminator Jmp(b2) (exit_acc=v24) + block 2 start_pc=0 + v11 Extend { value=v7, kind=I32 } -> x0 + v12 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v13 Imm(0) -> x0 + v14 Extend { value=v12, kind=I32 } -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v7 Phi { incoming=[b0:v5, b2:v12], kind=I64 } -> x1 + v8 Extend { value=v7, kind=I32 } -> x0 + v9 LoadLocal { off=3, kind=I32 } -> x2 + v10 Binop { op=lt, lhs=v8, rhs=v3 } -> x2 + terminator Bnz { cond=v10, target=b1, fall=b4 } (exit_acc=v10) block 4 start_pc=0 v25 LoadLocal { off=2, kind=I64 } -> x0 v26 LoadLocal { off=3, kind=I32 } -> x0 diff --git a/tests/snapshots/ssa/sysconf_pagesize.ssa b/tests/snapshots/ssa/sysconf_pagesize.ssa index d92b71989..00e92994e 100644 --- a/tests/snapshots/ssa/sysconf_pagesize.ssa +++ b/tests/snapshots/ssa/sysconf_pagesize.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=5 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(30) -> x7 @@ -24,16 +24,16 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 terminator Return(v11) (exit_acc=v11) block 4 start_pc=0 v12 LoadLocal { off=-1, kind=I64 } -> x1 - v13 BinopI { op=lt, lhs=v2, rhs_imm=4096 } -> x3 + v13 BinopI { op=lt, lhs=v2, rhs_imm=4096 } -> x2 v14 Imm(0) -> x1 terminator Bnz { cond=v13, target=b19, fall=b5 } (exit_acc=v13) block 5 start_pc=0 v15 LoadLocal { off=-1, kind=I64 } -> x1 - v16 BinopI { op=gt, lhs=v2, rhs_imm=1048576 } -> x3 + v16 BinopI { op=gt, lhs=v2, rhs_imm=1048576 } -> x2 v17 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v16) block 6 start_pc=0 - v18 Phi { incoming=[b19:v13, b5:v16], kind=I64 } -> x3 + v18 Phi { incoming=[b19:v13, b5:v16], kind=I64 } -> x2 v19 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) block 7 start_pc=0 diff --git a/tests/snapshots/ssa/syslimits_path_max.ssa b/tests/snapshots/ssa/syslimits_path_max.ssa index f736064ec..22e9e3d2d 100644 --- a/tests/snapshots/ssa/syslimits_path_max.ssa +++ b/tests/snapshots/ssa/syslimits_path_max.ssa @@ -25,19 +25,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=515 block 4 start_pc=0 v11 Phi { incoming=[b8:v6, b3:v9], kind=I64 } -> x2 v12 LoadLocal { off=-513, kind=I64 } -> x0 - terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + terminator Bz { cond=v11, target=b7, fall=b5 } (exit_acc=v11) block 5 start_pc=0 v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v13) + terminator Jmp(b6) (exit_acc=v13) block 6 start_pc=0 - v15 Imm(1) -> x1 - v16 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v15) - block 7 start_pc=0 - v17 Phi { incoming=[b5:v13, b6:v15], kind=I64 } -> x1 + v17 Phi { incoming=[b5:v13, b7:v15], kind=I64 } -> x1 v18 LoadLocal { off=-515, kind=I64 } -> x0 terminator Return(v17) (exit_acc=v17) + block 7 start_pc=0 + v15 Imm(1) -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v15) block 8 start_pc=0 terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/sysv_variadic_host_abi.ssa b/tests/snapshots/ssa/sysv_variadic_host_abi.ssa index 9339d0848..dfadac5d0 100644 --- a/tests/snapshots/ssa/sysv_variadic_host_abi.ssa +++ b/tests/snapshots/ssa/sysv_variadic_host_abi.ssa @@ -15,55 +15,55 @@ fn ent_pc=0 n_params=2 variadic=true locals=5 v9 Imm(0) -> x0 v10 Imm(0) -> x1 v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + terminator Jmp(b6) (exit_acc=v10) block 1 start_pc=0 - v12 Phi { incoming=[b0:v10, b2:v17], kind=I64 } -> x1 - v13 Phi { incoming=[b0:v8, b2:v37], kind=I64 } -> x2 - v14 Extend { value=v12, kind=I32 } -> x0 - v15 BinopI { op=lt, lhs=v14, rhs_imm=10 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) - block 2 start_pc=0 - v16 Extend { value=v12, kind=I32 } -> x0 - v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x1 - v18 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v17) - block 3 start_pc=0 - v19 Extend { value=v12, kind=I32 } -> x0 + v19 Extend { value=v12, kind=I32 } -> x6 v20 Imm(2) -> x6 - v21 BinopI { op=shr, lhs=v19, rhs_imm=63 } -> x6 + v21 BinopI { op=shr, lhs=v14, rhs_imm=63 } -> x6 v22 BinopI { op=shru, lhs=v21, rhs_imm=63 } -> x6 - v23 Binop { op=add, lhs=v19, rhs=v22 } -> x0 - v24 BinopI { op=and, lhs=v23, rhs_imm=1 } -> x0 - v25 Binop { op=sub, lhs=v24, rhs=v22 } -> x0 - v26 BinopI { op=eq, lhs=v25, rhs_imm=0 } -> x0 - terminator Bz { cond=v26, target=b7, fall=b5 } (exit_acc=v26) + v23 Binop { op=add, lhs=v14, rhs=v22 } -> x7 + v24 BinopI { op=and, lhs=v23, rhs_imm=1 } -> x7 + v25 Binop { op=sub, lhs=v24, rhs=v22 } -> x6 + v26 BinopI { op=eq, lhs=v25, rhs_imm=0 } -> x6 + terminator Bz { cond=v26, target=b4, fall=b2 } (exit_acc=v26) + block 2 start_pc=0 + v30 LoadLocal { off=-4, kind=I64 } -> x6 + v31 LocalAddr(-3) -> x6 + v32 Imm(8) -> x7 + v33 Intrinsic { kind=5, args=[v31, v32] } -> x6 + v34 Load { addr=v33, disp=0, kind=I64 } -> x6 + v35 Binop { op=add, lhs=v13, rhs=v34 } -> x2 + v36 Imm(0) -> x6 + terminator Jmp(b3) (exit_acc=v35) + block 3 start_pc=0 + v37 Phi { incoming=[b2:v35, b4:v44], kind=I64 } -> x2 + terminator Jmp(b5) block 4 start_pc=0 + v38 LoadLocal { off=-4, kind=I64 } -> x6 + v39 LocalAddr(-3) -> x6 + v40 Imm(65544) -> x7 + v41 Intrinsic { kind=5, args=[v39, v40] } -> x6 + v42 Load { addr=v41, disp=0, kind=F64 } -> d0 + v43 FpCast { kind=FpToInt, value=v42 } -> x6 + v44 Binop { op=add, lhs=v13, rhs=v43 } -> x2 + v45 Imm(0) -> x6 + terminator Jmp(b3) (exit_acc=v44) + block 5 start_pc=0 + v16 Extend { value=v12, kind=I32 } -> x1 + v17 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x1 + v18 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v17) + block 6 start_pc=0 + v12 Phi { incoming=[b0:v10, b5:v17], kind=I64 } -> x1 + v13 Phi { incoming=[b0:v8, b5:v37], kind=I64 } -> x2 + v14 Extend { value=v12, kind=I32 } -> x0 + v15 BinopI { op=lt, lhs=v14, rhs_imm=10 } -> x6 + terminator Bnz { cond=v15, target=b1, fall=b7 } (exit_acc=v15) + block 7 start_pc=0 v27 LocalAddr(-3) -> x0 v28 Intrinsic { kind=6, args=[v27] } -> x0 v29 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v13) (exit_acc=v13) - block 5 start_pc=0 - v30 LoadLocal { off=-4, kind=I64 } -> x0 - v31 LocalAddr(-3) -> x0 - v32 Imm(8) -> x6 - v33 Intrinsic { kind=5, args=[v31, v32] } -> x0 - v34 Load { addr=v33, disp=0, kind=I64 } -> x0 - v35 Binop { op=add, lhs=v13, rhs=v34 } -> x2 - v36 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v35) - block 6 start_pc=0 - v37 Phi { incoming=[b5:v35, b7:v44], kind=I64 } -> x2 - terminator Jmp(b2) - block 7 start_pc=0 - v38 LoadLocal { off=-4, kind=I64 } -> x0 - v39 LocalAddr(-3) -> x0 - v40 Imm(65544) -> x6 - v41 Intrinsic { kind=5, args=[v39, v40] } -> x0 - v42 Load { addr=v41, disp=0, kind=F64 } -> d0 - v43 FpCast { kind=FpToInt, value=v42 } -> x0 - v44 Binop { op=add, lhs=v13, rhs=v43 } -> x2 - v45 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v44) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=fsum fn ent_pc=1 n_params=1 variadic=true locals=5 @@ -77,29 +77,29 @@ fn ent_pc=1 n_params=1 variadic=true locals=5 v5 FpCast { kind=IntToFp, value=v4 } -> d0 v6 Imm(0) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 - v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 - v10 Extend { value=v8, kind=I32 } -> x0 - v11 LoadLocal { off=2, kind=I32 } -> x2 - v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) - block 2 start_pc=0 - v13 Extend { value=v8, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 v16 LoadLocal { off=-4, kind=F64 } -> d1 - v17 LocalAddr(-3) -> x0 - v18 Imm(65544) -> x2 - v19 Intrinsic { kind=5, args=[v17, v18] } -> x0 + v17 LocalAddr(-3) -> x2 + v18 Imm(65544) -> x6 + v19 Intrinsic { kind=5, args=[v17, v18] } -> x2 v20 Load { addr=v19, disp=0, kind=F64 } -> d1 v21 Binop { op=fadd, lhs=v9, rhs=v20 } -> d0 - v22 Imm(0) -> x0 + v22 Imm(0) -> x2 v23 LoadLocal { off=-4, kind=F64 } -> d1 terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x1 + v14 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x2 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x2 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v24 LocalAddr(-3) -> x0 v25 Intrinsic { kind=6, args=[v24] } -> x0 diff --git a/tests/snapshots/ssa/tail_call_args_from_spill.ssa b/tests/snapshots/ssa/tail_call_args_from_spill.ssa index 92070d1a5..0dd9150f7 100644 --- a/tests/snapshots/ssa/tail_call_args_from_spill.ssa +++ b/tests/snapshots/ssa/tail_call_args_from_spill.ssa @@ -213,19 +213,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v6 CallExt { binding_idx=0, args=[v4, v5], fp_arg_mask=0x0 } -> x0 v7 Extend { value=v2, kind=I32 } -> x0 v8 BinopI { op=eq, lhs=v7, rhs_imm=191 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + terminator Bz { cond=v8, target=b3, fall=b1 } (exit_acc=v8) block 1 start_pc=0 v9 Imm(0) -> x1 v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v9) + terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v11 Imm(1) -> x1 - v12 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v11) - block 3 start_pc=0 - v13 Phi { incoming=[b1:v9, b2:v11], kind=I64 } -> x1 + v13 Phi { incoming=[b1:v9, b3:v11], kind=I64 } -> x1 v14 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v13) (exit_acc=v13) + block 3 start_pc=0 + v11 Imm(1) -> x1 + v12 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v11) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/tail_call_no_address_escape.ssa b/tests/snapshots/ssa/tail_call_no_address_escape.ssa index 59d4bb514..7bdfbd673 100644 --- a/tests/snapshots/ssa/tail_call_no_address_escape.ssa +++ b/tests/snapshots/ssa/tail_call_no_address_escape.ssa @@ -9,19 +9,19 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v3 LoadLocal { off=2, kind=I64 } -> x0 v4 Load { addr=v1, disp=0, kind=I64 } -> x0 v5 BinopI { op=eq, lhs=v4, rhs_imm=17 } -> x0 - terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) + terminator Bz { cond=v5, target=b3, fall=b1 } (exit_acc=v5) block 1 start_pc=0 v6 Imm(0) -> x1 v7 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v6) + terminator Jmp(b2) (exit_acc=v6) block 2 start_pc=0 - v8 Imm(1) -> x1 - v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v8) - block 3 start_pc=0 - v10 Phi { incoming=[b1:v6, b2:v8], kind=I64 } -> x1 + v10 Phi { incoming=[b1:v6, b3:v8], kind=I64 } -> x1 v11 LoadLocal { off=-1, kind=I64 } -> x0 terminator Return(v10) (exit_acc=v10) + block 3 start_pc=0 + v8 Imm(1) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=wrap fn ent_pc=2 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/tentative_array_definition.ssa b/tests/snapshots/ssa/tentative_array_definition.ssa index dbb80e49f..db368b64c 100644 --- a/tests/snapshots/ssa/tentative_array_definition.ssa +++ b/tests/snapshots/ssa/tentative_array_definition.ssa @@ -9,105 +9,105 @@ fn ent_pc=1 n_params=0 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=4 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x12 + v1 Imm(0) -> x2 v2 Imm(0) -> x0 - v3 ImmData(100) -> x3 - v4 Load { addr=v3, disp=0, kind=I8 } -> x0 - v5 BinopI { op=ne, lhs=v4, rhs_imm=0 } -> x0 - terminator Bz { cond=v5, target=b15, fall=b1 } (exit_acc=v5) + v3 ImmData(100) -> x0 + v4 Load { addr=v3, disp=0, kind=I8 } -> x1 + v5 BinopI { op=ne, lhs=v4, rhs_imm=0 } -> x1 + terminator Bz { cond=v5, target=b18, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v6 LoadLocal { off=-1, kind=I32 } -> x0 - v7 BinopI { op=or, lhs=v1, rhs_imm=1 } -> x12 - v8 Imm(0) -> x0 - v9 Extend { value=v7, kind=I32 } -> x0 + v6 LoadLocal { off=-1, kind=I32 } -> x1 + v7 Imm(1) -> x2 + v8 Imm(0) -> x1 + v9 Imm(1) -> x1 terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v10 Phi { incoming=[b15:v1, b1:v7], kind=I64 } -> x12 - v11 ImmData(100) -> x0 - v12 ImmData(100) -> x0 + v10 Phi { incoming=[b18:v1, b1:v7], kind=I64 } -> x2 + v11 ImmData(100) -> x1 + v12 ImmData(100) -> x1 v13 Binop { op=ne, lhs=v3, rhs=v3 } -> x0 - terminator Bz { cond=v13, target=b16, fall=b3 } (exit_acc=v13) + terminator Bz { cond=v13, target=b17, fall=b3 } (exit_acc=v13) block 3 start_pc=0 v14 Extend { value=v10, kind=I32 } -> x0 - v15 BinopI { op=or, lhs=v10, rhs_imm=2 } -> x12 + v15 BinopI { op=or, lhs=v10, rhs_imm=2 } -> x2 v16 Imm(0) -> x0 v17 Extend { value=v15, kind=I32 } -> x0 terminator Jmp(b4) (exit_acc=v17) block 4 start_pc=0 - v18 Phi { incoming=[b16:v10, b3:v15], kind=I64 } -> x12 + v18 Phi { incoming=[b17:v10, b3:v15], kind=I64 } -> x2 v19 ImmData(44) -> x0 v20 Imm(0) -> x1 v21 Load { addr=v19, disp=0, kind=I8 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=104 } -> x0 - terminator Bz { cond=v22, target=b17, fall=b5 } (exit_acc=v22) + terminator Bz { cond=v22, target=b16, fall=b5 } (exit_acc=v22) block 5 start_pc=0 v23 Extend { value=v18, kind=I32 } -> x0 - v24 BinopI { op=or, lhs=v18, rhs_imm=4 } -> x12 + v24 BinopI { op=or, lhs=v18, rhs_imm=4 } -> x2 v25 Imm(0) -> x0 v26 Extend { value=v24, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v26) block 6 start_pc=0 - v27 Phi { incoming=[b17:v18, b5:v24], kind=I64 } -> x12 - v28 Imm(0) -> x3 + v27 Phi { incoming=[b16:v18, b5:v24], kind=I64 } -> x2 + v28 Imm(0) -> x1 v29 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v28) + terminator Jmp(b12) (exit_acc=v28) block 7 start_pc=0 - v30 Phi { incoming=[b6:v28, b8:v37], kind=I64 } -> x3 - v31 Phi { incoming=[b6:v27, b8:v52], kind=I64 } -> x12 - v32 ImmData(58) -> x0 - v33 Extend { value=v30, kind=I32 } -> x1 - v34 Binop { op=add, lhs=v32, rhs=v33 } -> x0 - v35 Load { addr=v34, disp=0, kind=I8 } -> x0 - terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) - block 8 start_pc=0 - v36 Extend { value=v30, kind=I32 } -> x0 - v37 BinopI { op=add, lhs=v36, rhs_imm=1 } -> x3 - v38 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v37) - block 9 start_pc=0 v39 ImmData(44) -> x0 - v40 Extend { value=v30, kind=I32 } -> x1 - v41 Binop { op=add, lhs=v39, rhs=v40 } -> x0 + v40 Extend { value=v30, kind=I32 } -> x7 + v41 Binop { op=add, lhs=v39, rhs=v33 } -> x0 v42 Load { addr=v41, disp=0, kind=I8 } -> x0 - v43 ImmData(64) -> x2 - v44 Binop { op=add, lhs=v43, rhs=v40 } -> x1 - v45 Load { addr=v44, disp=0, kind=I8 } -> x1 + v43 ImmData(64) -> x7 + v44 Binop { op=add, lhs=v43, rhs=v33 } -> x7 + v45 Load { addr=v44, disp=0, kind=I8 } -> x7 v46 Binop { op=ne, lhs=v42, rhs=v45 } -> x0 - terminator Bz { cond=v46, target=b18, fall=b11 } (exit_acc=v46) - block 10 start_pc=0 - v47 Extend { value=v31, kind=I32 } -> x0 - terminator Bz { cond=v47, target=b14, fall=b13 } (exit_acc=v47) - block 11 start_pc=0 + terminator Bz { cond=v46, target=b10, fall=b8 } (exit_acc=v46) + block 8 start_pc=0 v48 Extend { value=v31, kind=I32 } -> x0 - v49 BinopI { op=or, lhs=v31, rhs_imm=8 } -> x12 + v49 BinopI { op=or, lhs=v31, rhs_imm=8 } -> x2 v50 Imm(0) -> x0 v51 Extend { value=v49, kind=I32 } -> x0 - terminator Jmp(b12) (exit_acc=v51) + terminator Jmp(b9) (exit_acc=v51) + block 9 start_pc=0 + v52 Phi { incoming=[b10:v31, b8:v49], kind=I64 } -> x2 + terminator Jmp(b11) + block 10 start_pc=0 + terminator Jmp(b9) + block 11 start_pc=0 + v36 Extend { value=v30, kind=I32 } -> x0 + v37 BinopI { op=add, lhs=v33, rhs_imm=1 } -> x1 + v38 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v37) block 12 start_pc=0 - v52 Phi { incoming=[b18:v31, b11:v49], kind=I64 } -> x12 - terminator Jmp(b8) + v30 Phi { incoming=[b6:v28, b11:v37], kind=I64 } -> x1 + v31 Phi { incoming=[b6:v27, b11:v52], kind=I64 } -> x2 + v32 ImmData(58) -> x0 + v33 Extend { value=v30, kind=I32 } -> x6 + v34 Binop { op=add, lhs=v32, rhs=v33 } -> x0 + v35 Load { addr=v34, disp=0, kind=I8 } -> x0 + terminator Bnz { cond=v35, target=b7, fall=b13 } (exit_acc=v35) block 13 start_pc=0 + v47 Extend { value=v31, kind=I32 } -> x0 + terminator Bz { cond=v47, target=b15, fall=b14 } (exit_acc=v47) + block 14 start_pc=0 v53 ImmData(70) -> x7 v54 Extend { value=v31, kind=I32 } -> x6 v55 CallExt { binding_idx=0, args=[v53, v54], fp_arg_mask=0x0 } -> x0 v56 Imm(1) -> x0 terminator Return(v56) (exit_acc=v56) - block 14 start_pc=0 + block 15 start_pc=0 v57 ImmData(84) -> x7 v58 CallExt { binding_idx=0, args=[v57], fp_arg_mask=0x0 } -> x0 v59 Imm(0) -> x0 terminator Return(v59) (exit_acc=v59) - block 15 start_pc=0 - terminator Jmp(b2) block 16 start_pc=0 - terminator Jmp(b4) - block 17 start_pc=0 terminator Jmp(b6) + block 17 start_pc=0 + terminator Jmp(b4) block 18 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/tentative_array_use_before_init.ssa b/tests/snapshots/ssa/tentative_array_use_before_init.ssa index 229d3d780..38f098c59 100644 --- a/tests/snapshots/ssa/tentative_array_use_before_init.ssa +++ b/tests/snapshots/ssa/tentative_array_use_before_init.ssa @@ -7,27 +7,27 @@ fn ent_pc=0 n_params=0 variadic=false locals=2 v1 Imm(0) -> x1 v2 Imm(0) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 + v15 Extend { value=v5, kind=I32 } -> x0 + v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 + v17 Imm(0) -> x2 + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v12 Extend { value=v4, kind=I32 } -> x1 + v13 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 + v14 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v13) + block 3 start_pc=0 v4 Phi { incoming=[b0:v1, b2:v13], kind=I64 } -> x1 v5 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x0 v6 ImmData(8) -> x2 v7 Extend { value=v4, kind=I32 } -> x6 - v8 BinopI { op=shl, lhs=v7, rhs_imm=4 } -> x6 + v8 BinopI { op=shl, lhs=v7, rhs_imm=4 } -> x7 v9 Binop { op=add, lhs=v6, rhs=v8 } -> x2 v10 Load { addr=v9, disp=0, kind=I64 } -> x2 v11 BinopI { op=ne, lhs=v10, rhs_imm=0 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 Extend { value=v4, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 - v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) - block 3 start_pc=0 - v15 Extend { value=v5, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x0 - v17 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v16) + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v18 Extend { value=v5, kind=I32 } -> x0 terminator Return(v18) (exit_acc=v18) @@ -37,39 +37,77 @@ fn ent_pc=1 n_params=0 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v4 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v5 Phi { incoming=[b0:v1, b2:v17], kind=I64 } -> x0 - v6 Extend { value=v4, kind=I32 } -> x2 - v7 BinopI { op=lt, lhs=v6, rhs_imm=4 } -> x2 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v4 Imm(0) -> x0 + v5 Imm(1) -> x0 + v6 Imm(0) -> x0 + v7 ImmData(136) -> x0 + v8 Imm(0) -> x1 + v9 Imm(0) -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=0 } -> x0 + v11 Load { addr=v10, disp=0, kind=I32 } -> x0 + v12 BinopI { op=add, lhs=v11, rhs_imm=0 } -> x0 + v13 Imm(0) -> x1 + v14 Extend { value=v12, kind=I32 } -> x1 + v15 Imm(0) -> x1 + v16 Imm(1) -> x1 + v17 Imm(0) -> x1 + v18 Imm(1) -> x1 + v19 Imm(1) -> x1 + v20 Extend { value=v12, kind=I32 } -> x1 + v21 ImmData(136) -> x1 + v22 Imm(1) -> x2 + v23 Imm(4) -> x2 + v24 BinopI { op=add, lhs=v21, rhs_imm=4 } -> x2 + v25 Load { addr=v21, disp=4, kind=I32 } -> x1 + v26 Binop { op=add, lhs=v12, rhs=v25 } -> x0 + v27 Imm(0) -> x1 + v28 Extend { value=v26, kind=I32 } -> x1 + v29 Imm(1) -> x1 + v30 Imm(2) -> x1 + v31 Imm(0) -> x1 + v32 Imm(2) -> x1 + v33 Imm(1) -> x1 + v34 Extend { value=v26, kind=I32 } -> x1 + v35 ImmData(136) -> x1 + v36 Imm(2) -> x2 + v37 Imm(8) -> x2 + v38 BinopI { op=add, lhs=v35, rhs_imm=8 } -> x2 + v39 Load { addr=v35, disp=8, kind=I32 } -> x1 + v40 Binop { op=add, lhs=v26, rhs=v39 } -> x0 + v41 Imm(0) -> x1 + v42 Extend { value=v40, kind=I32 } -> x1 + v43 Imm(2) -> x1 + v44 Imm(3) -> x1 + v45 Imm(0) -> x1 + v46 Imm(3) -> x1 + v47 Imm(1) -> x1 + v48 Extend { value=v40, kind=I32 } -> x1 + v49 ImmData(136) -> x1 + v50 Imm(3) -> x2 + v51 Imm(12) -> x2 + v52 BinopI { op=add, lhs=v49, rhs_imm=12 } -> x2 + v53 Load { addr=v49, disp=12, kind=I32 } -> x1 + v54 Binop { op=add, lhs=v40, rhs=v53 } -> x0 + v55 Imm(0) -> x1 + v56 Extend { value=v54, kind=I32 } -> x1 + v57 Imm(3) -> x1 + v58 Imm(4) -> x1 + v59 Imm(0) -> x1 + v60 Imm(4) -> x1 + v61 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v61) block 2 start_pc=0 - v8 Extend { value=v4, kind=I32 } -> x1 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v9) - block 3 start_pc=0 - v11 Extend { value=v5, kind=I32 } -> x2 - v12 ImmData(136) -> x2 - v13 Extend { value=v4, kind=I32 } -> x6 - v14 BinopI { op=shl, lhs=v13, rhs_imm=2 } -> x7 - v15 Binop { op=add, lhs=v12, rhs=v14 } -> x7 - v16 LoadIndexed { base=v12, index=v13, scale=4, kind=I32 } -> x2 - v17 Binop { op=add, lhs=v5, rhs=v16 } -> x0 - v18 Imm(0) -> x2 - v19 Extend { value=v17, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v19) - block 4 start_pc=0 - v20 Extend { value=v5, kind=I32 } -> x0 - terminator Return(v20) (exit_acc=v20) + v62 Extend { value=v54, kind=I32 } -> x0 + terminator Return(v62) (exit_acc=v62) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=1 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Call { target_pc=0, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 @@ -83,7 +121,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 v5 Imm(0) -> x1 v6 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x1 v7 Load { addr=v4, disp=8, kind=I32 } -> x0 - v8 BinopI { op=ne, lhs=v7, rhs_imm=10 } -> x3 + v8 BinopI { op=ne, lhs=v7, rhs_imm=10 } -> x1 v9 Imm(0) -> x0 terminator Bnz { cond=v8, target=b9, fall=b3 } (exit_acc=v8) block 3 start_pc=0 @@ -92,11 +130,11 @@ fn ent_pc=2 n_params=0 variadic=false locals=1 v12 BinopI { op=add, lhs=v10, rhs_imm=32 } -> x1 v13 BinopI { op=add, lhs=v10, rhs_imm=40 } -> x1 v14 Load { addr=v10, disp=40, kind=I32 } -> x0 - v15 BinopI { op=ne, lhs=v14, rhs_imm=30 } -> x3 + v15 BinopI { op=ne, lhs=v14, rhs_imm=30 } -> x1 v16 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v15) block 4 start_pc=0 - v17 Phi { incoming=[b9:v8, b3:v15], kind=I64 } -> x3 + v17 Phi { incoming=[b9:v8, b3:v15], kind=I64 } -> x1 v18 LoadLocal { off=-1, kind=I64 } -> x0 terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) block 5 start_pc=0 diff --git a/tests/snapshots/ssa/ternary_arith_common_type.ssa b/tests/snapshots/ssa/ternary_arith_common_type.ssa index 0314ec40b..ad886ac01 100644 --- a/tests/snapshots/ssa/ternary_arith_common_type.ssa +++ b/tests/snapshots/ssa/ternary_arith_common_type.ssa @@ -5,100 +5,100 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x1 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v4) block 1 start_pc=0 - v5 Imm(1) -> x2 - v6 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v5) + v5 Imm(1) -> x1 + v6 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v5) block 2 start_pc=0 - v7 Imm(-1) -> x1 - v8 Imm(4294967295) -> x2 - v9 Imm(0) -> x1 - terminator Jmp(b3) (exit_acc=v8) + v10 Phi { incoming=[b1:v5, b17:v8], kind=I64 } -> x1 + v11 LoadLocal { off=-6, kind=I64 } -> x0 + v12 Imm(0) -> x0 + v13 LoadLocal { off=-2, kind=I64 } -> x0 + v14 BinopI { op=ne, lhs=v10, rhs_imm=1 } -> x0 + terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v10 Phi { incoming=[b1:v5, b2:v8], kind=I64 } -> x2 - v11 LoadLocal { off=-6, kind=I64 } -> x1 - v12 Imm(0) -> x1 - v13 LoadLocal { off=-2, kind=I64 } -> x1 - v14 BinopI { op=ne, lhs=v10, rhs_imm=1 } -> x1 - terminator Bz { cond=v14, target=b5, fall=b4 } (exit_acc=v14) - block 4 start_pc=0 v15 Imm(1) -> x0 terminator Return(v15) (exit_acc=v15) + block 4 start_pc=0 + v16 LoadLocal { off=-1, kind=U32 } -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v17) block 5 start_pc=0 - v16 LoadLocal { off=-1, kind=U32 } -> x1 - v17 BinopI { op=ne, lhs=v1, rhs_imm=0 } -> x1 - terminator Bz { cond=v17, target=b7, fall=b6 } (exit_acc=v17) + v20 Imm(-1) -> x0 + v21 Imm(4294967295) -> x1 + v22 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v21) block 6 start_pc=0 - v18 Imm(1) -> x2 - v19 Imm(0) -> x1 - terminator Jmp(b8) (exit_acc=v18) + v23 Phi { incoming=[b18:v18, b5:v21], kind=I64 } -> x1 + v24 LoadLocal { off=-7, kind=I64 } -> x0 + v25 Imm(0) -> x0 + v26 LoadLocal { off=-3, kind=I64 } -> x0 + v27 BinopI { op=ne, lhs=v23, rhs_imm=4294967295 } -> x0 + terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) block 7 start_pc=0 - v20 Imm(-1) -> x1 - v21 Imm(4294967295) -> x2 - v22 Imm(0) -> x1 - terminator Jmp(b8) (exit_acc=v21) - block 8 start_pc=0 - v23 Phi { incoming=[b6:v18, b7:v21], kind=I64 } -> x2 - v24 LoadLocal { off=-7, kind=I64 } -> x1 - v25 Imm(0) -> x1 - v26 LoadLocal { off=-3, kind=I64 } -> x1 - v27 BinopI { op=ne, lhs=v23, rhs_imm=4294967295 } -> x1 - terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) - block 9 start_pc=0 v28 Imm(2) -> x0 terminator Return(v28) (exit_acc=v28) + block 8 start_pc=0 + v29 LoadLocal { off=-1, kind=U32 } -> x0 + v30 Imm(1) -> x0 + terminator Jmp(b9) (exit_acc=v30) + block 9 start_pc=0 + v31 Imm(-1) -> x0 + v32 Imm(4294967295) -> x1 + v33 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v32) block 10 start_pc=0 - v29 LoadLocal { off=-1, kind=U32 } -> x1 - v30 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x1 - terminator Bz { cond=v30, target=b12, fall=b11 } (exit_acc=v30) + v36 Phi { incoming=[b9:v32, b19:v34], kind=I64 } -> x1 + v37 LoadLocal { off=-8, kind=I64 } -> x0 + v38 Imm(0) -> x0 + v39 LoadLocal { off=-4, kind=I64 } -> x0 + v40 BinopI { op=ne, lhs=v36, rhs_imm=4294967295 } -> x0 + terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) block 11 start_pc=0 - v31 Imm(-1) -> x1 - v32 Imm(4294967295) -> x2 - v33 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v32) - block 12 start_pc=0 - v34 Imm(1) -> x2 - v35 Imm(0) -> x1 - terminator Jmp(b13) (exit_acc=v34) - block 13 start_pc=0 - v36 Phi { incoming=[b11:v32, b12:v34], kind=I64 } -> x2 - v37 LoadLocal { off=-8, kind=I64 } -> x1 - v38 Imm(0) -> x1 - v39 LoadLocal { off=-4, kind=I64 } -> x1 - v40 BinopI { op=ne, lhs=v36, rhs_imm=4294967295 } -> x1 - terminator Bz { cond=v40, target=b15, fall=b14 } (exit_acc=v40) - block 14 start_pc=0 v41 Imm(3) -> x0 terminator Return(v41) (exit_acc=v41) - block 15 start_pc=0 - v42 LoadLocal { off=-1, kind=U32 } -> x1 - v43 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b17, fall=b16 } (exit_acc=v43) - block 16 start_pc=0 + block 12 start_pc=0 + v42 LoadLocal { off=-1, kind=U32 } -> x0 + v43 Imm(1) -> x0 + terminator Jmp(b13) (exit_acc=v43) + block 13 start_pc=0 v44 Imm(-1) -> x1 v45 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v44) - block 17 start_pc=0 - v46 Imm(0) -> x1 - v47 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v46) - block 18 start_pc=0 - v48 Phi { incoming=[b16:v44, b17:v46], kind=I64 } -> x1 + terminator Jmp(b14) (exit_acc=v44) + block 14 start_pc=0 + v48 Phi { incoming=[b13:v44, b20:v46], kind=I64 } -> x1 v49 LoadLocal { off=-9, kind=I64 } -> x0 v50 Imm(0) -> x0 v51 LoadLocal { off=-5, kind=I64 } -> x0 v52 BinopI { op=ne, lhs=v48, rhs_imm=-1 } -> x0 - terminator Bz { cond=v52, target=b20, fall=b19 } (exit_acc=v52) - block 19 start_pc=0 + terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) + block 15 start_pc=0 v53 Imm(4) -> x0 terminator Return(v53) (exit_acc=v53) - block 20 start_pc=0 + block 16 start_pc=0 v54 Imm(0) -> x0 terminator Return(v54) (exit_acc=v54) + block 17 start_pc=0 + v7 Imm(-1) -> x0 + v8 Imm(4294967295) -> x1 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v8) + block 18 start_pc=0 + v18 Imm(1) -> x1 + v19 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v18) + block 19 start_pc=0 + v34 Imm(1) -> x1 + v35 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v34) + block 20 start_pc=0 + v46 Imm(0) -> x1 + v47 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ternary_arith_conversion.ssa b/tests/snapshots/ssa/ternary_arith_conversion.ssa index f86ce101d..1bf851103 100644 --- a/tests/snapshots/ssa/ternary_arith_conversion.ssa +++ b/tests/snapshots/ssa/ternary_arith_conversion.ssa @@ -14,200 +14,204 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v6 Imm(1) -> x2 v7 FpCast { kind=IntToFp, value=v6 } -> d0 v8 StoreLocal { off=-4, value=v7, kind=F64 } -> - - terminator Jmp(b3) (exit_acc=v8) + terminator Jmp(b2) (exit_acc=v8) block 2 start_pc=0 - v9 Imm(4611686018427387904) -> x2 - v10 StoreLocal { off=-4, value=v9, kind=F64 } -> - - terminator Jmp(b3) (exit_acc=v10) - block 3 start_pc=0 v11 LoadLocal { off=-4, kind=F64 } -> d0 v12 Imm(4607182418800017408) -> x2 v13 Binop { op=fne, lhs=v11, rhs=v12 } -> x2 - terminator Bz { cond=v13, target=b5, fall=b4 } (exit_acc=v13) - block 4 start_pc=0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + block 3 start_pc=0 v14 Imm(11) -> x0 terminator Return(v14) (exit_acc=v14) - block 5 start_pc=0 + block 4 start_pc=0 v15 LoadLocal { off=-2, kind=I32 } -> x2 - terminator Jmp(b7) (exit_acc=v3) - block 6 start_pc=0 - v16 Imm(1) -> x2 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 StoreLocal { off=-5, value=v17, kind=F64 } -> - - terminator Jmp(b8) (exit_acc=v18) - block 7 start_pc=0 + terminator Jmp(b5) (exit_acc=v3) + block 5 start_pc=0 v19 Imm(4611686018427387904) -> x2 v20 StoreLocal { off=-5, value=v19, kind=F64 } -> - - terminator Jmp(b8) (exit_acc=v20) - block 8 start_pc=0 + terminator Jmp(b6) (exit_acc=v20) + block 6 start_pc=0 v21 LoadLocal { off=-5, kind=F64 } -> d0 v22 Imm(4611686018427387904) -> x2 v23 Binop { op=fne, lhs=v21, rhs=v22 } -> x2 - terminator Bz { cond=v23, target=b10, fall=b9 } (exit_acc=v23) - block 9 start_pc=0 + terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) + block 7 start_pc=0 v24 Imm(12) -> x0 terminator Return(v24) (exit_acc=v24) - block 10 start_pc=0 + block 8 start_pc=0 v25 LoadLocal { off=-1, kind=I32 } -> x2 - terminator Jmp(b11) (exit_acc=v1) - block 11 start_pc=0 + terminator Jmp(b9) (exit_acc=v1) + block 9 start_pc=0 v26 Imm(4607182418800017408) -> x2 v27 StoreLocal { off=-6, value=v26, kind=F64 } -> - - terminator Jmp(b13) (exit_acc=v27) - block 12 start_pc=0 - v28 Imm(2) -> x2 - v29 FpCast { kind=IntToFp, value=v28 } -> d0 - v30 StoreLocal { off=-6, value=v29, kind=F64 } -> - - terminator Jmp(b13) (exit_acc=v30) - block 13 start_pc=0 + terminator Jmp(b10) (exit_acc=v27) + block 10 start_pc=0 v31 LoadLocal { off=-6, kind=F64 } -> d0 v32 Imm(4607182418800017408) -> x2 v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x2 - terminator Bz { cond=v33, target=b15, fall=b14 } (exit_acc=v33) - block 14 start_pc=0 + terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) + block 11 start_pc=0 v34 Imm(13) -> x0 terminator Return(v34) (exit_acc=v34) - block 15 start_pc=0 + block 12 start_pc=0 v35 LoadLocal { off=-2, kind=I32 } -> x2 - terminator Jmp(b17) (exit_acc=v3) - block 16 start_pc=0 - v36 Imm(4607182418800017408) -> x2 - v37 StoreLocal { off=-7, value=v36, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v37) - block 17 start_pc=0 + terminator Jmp(b13) (exit_acc=v3) + block 13 start_pc=0 v38 Imm(2) -> x2 v39 FpCast { kind=IntToFp, value=v38 } -> d0 v40 StoreLocal { off=-7, value=v39, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v40) - block 18 start_pc=0 + terminator Jmp(b14) (exit_acc=v40) + block 14 start_pc=0 v41 LoadLocal { off=-7, kind=F64 } -> d0 v42 Imm(4611686018427387904) -> x2 v43 Binop { op=fne, lhs=v41, rhs=v42 } -> x2 - terminator Bz { cond=v43, target=b20, fall=b19 } (exit_acc=v43) - block 19 start_pc=0 + terminator Bz { cond=v43, target=b16, fall=b15 } (exit_acc=v43) + block 15 start_pc=0 v44 Imm(14) -> x0 terminator Return(v44) (exit_acc=v44) - block 20 start_pc=0 + block 16 start_pc=0 v45 LoadLocal { off=-1, kind=I32 } -> x2 - terminator Jmp(b21) (exit_acc=v1) + terminator Jmp(b17) (exit_acc=v1) + block 17 start_pc=0 + v46 Imm(1065353216) -> x2 [f32] + v47 FpCast { kind=F32ToF64, value=v46 } -> d0 + v48 StoreLocal { off=-8, value=v47, kind=F64 } -> - + terminator Jmp(b18) (exit_acc=v48) + block 18 start_pc=0 + v51 LoadLocal { off=-8, kind=F64 } -> d0 + v52 Imm(4607182418800017408) -> x2 + v53 Binop { op=fne, lhs=v51, rhs=v52 } -> x2 + terminator Bz { cond=v53, target=b20, fall=b19 } (exit_acc=v53) + block 19 start_pc=0 + v54 Imm(15) -> x0 + terminator Return(v54) (exit_acc=v54) + block 20 start_pc=0 + v55 LoadLocal { off=-2, kind=I32 } -> x2 + terminator Jmp(b21) (exit_acc=v3) block 21 start_pc=0 - v46 Imm(4607182418800017408) -> x2 - v47 StoreLocal { off=-8, value=v46, kind=F64 } -> - - terminator Jmp(b23) (exit_acc=v47) + v59 Imm(4611686018427387904) -> x2 + v60 StoreLocal { off=-9, value=v59, kind=F64 } -> - + terminator Jmp(b22) (exit_acc=v60) block 22 start_pc=0 - v48 Imm(4611686018427387904) -> x2 - v49 StoreLocal { off=-8, value=v48, kind=F64 } -> - - terminator Jmp(b23) (exit_acc=v49) + v61 LoadLocal { off=-9, kind=F64 } -> d0 + v62 Imm(4611686018427387904) -> x2 + v63 Binop { op=fne, lhs=v61, rhs=v62 } -> x2 + terminator Bz { cond=v63, target=b24, fall=b23 } (exit_acc=v63) block 23 start_pc=0 - v50 LoadLocal { off=-8, kind=F64 } -> d0 - v51 Imm(4607182418800017408) -> x2 - v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x2 - terminator Bz { cond=v52, target=b25, fall=b24 } (exit_acc=v52) + v64 Imm(16) -> x0 + terminator Return(v64) (exit_acc=v64) block 24 start_pc=0 - v53 Imm(15) -> x0 - terminator Return(v53) (exit_acc=v53) + v65 LoadLocal { off=-1, kind=I32 } -> x2 + terminator Jmp(b25) (exit_acc=v1) block 25 start_pc=0 - v54 LoadLocal { off=-2, kind=I32 } -> x2 - terminator Jmp(b27) (exit_acc=v3) + v66 Imm(1065353216) -> x2 [f32] + v67 StoreLocal { off=-10, value=v66, kind=F32 } -> - + terminator Jmp(b26) (exit_acc=v67) block 26 start_pc=0 - v55 Imm(4607182418800017408) -> x2 - v56 StoreLocal { off=-9, value=v55, kind=F64 } -> - - terminator Jmp(b28) (exit_acc=v56) + v72 LoadLocal { off=-10, kind=F32 } -> d0 [f32] + v73 Imm(1065353216) -> x2 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x2 + terminator Bz { cond=v74, target=b28, fall=b27 } (exit_acc=v74) block 27 start_pc=0 - v57 Imm(4611686018427387904) -> x2 - v58 StoreLocal { off=-9, value=v57, kind=F64 } -> - - terminator Jmp(b28) (exit_acc=v58) + v75 Imm(17) -> x0 + terminator Return(v75) (exit_acc=v75) block 28 start_pc=0 - v59 LoadLocal { off=-9, kind=F64 } -> d0 - v60 Imm(4611686018427387904) -> x2 - v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x2 - terminator Bz { cond=v61, target=b30, fall=b29 } (exit_acc=v61) + v76 LoadLocal { off=-2, kind=I32 } -> x2 + terminator Jmp(b29) (exit_acc=v3) block 29 start_pc=0 - v62 Imm(16) -> x0 - terminator Return(v62) (exit_acc=v62) + v79 Imm(2) -> x2 + v80 FpCast { kind=IntToFp, value=v79 } -> d0 + v81 FpCast { kind=F64ToF32, value=v80 } -> d0 [f32] + v82 StoreLocal { off=-11, value=v81, kind=F32 } -> - + terminator Jmp(b30) (exit_acc=v82) block 30 start_pc=0 - v63 LoadLocal { off=-1, kind=I32 } -> x2 - terminator Jmp(b31) (exit_acc=v1) + v83 LoadLocal { off=-11, kind=F32 } -> d0 [f32] + v84 Imm(1073741824) -> x2 [f32] + v85 Binop { op=fne, lhs=v83, rhs=v84 } -> x2 + terminator Bz { cond=v85, target=b32, fall=b31 } (exit_acc=v85) block 31 start_pc=0 - v64 Imm(4607182418800017408) -> x2 - v65 StoreLocal { off=-10, value=v64, kind=F64 } -> - - terminator Jmp(b33) (exit_acc=v65) + v86 Imm(18) -> x0 + terminator Return(v86) (exit_acc=v86) block 32 start_pc=0 - v66 Imm(2) -> x2 - v67 FpCast { kind=IntToFp, value=v66 } -> d0 - v68 StoreLocal { off=-10, value=v67, kind=F64 } -> - - terminator Jmp(b33) (exit_acc=v68) + v87 LoadLocal { off=-1, kind=I32 } -> x2 + terminator Jmp(b33) (exit_acc=v1) block 33 start_pc=0 - v69 LoadLocal { off=-10, kind=F64 } -> d0 - v70 Imm(4607182418800017408) -> x2 - v71 Binop { op=fne, lhs=v69, rhs=v70 } -> x2 - terminator Bz { cond=v71, target=b35, fall=b34 } (exit_acc=v71) + v88 Imm(10) -> x2 + v89 Imm(0) -> x0 + terminator Jmp(b34) (exit_acc=v88) block 34 start_pc=0 - v72 Imm(17) -> x0 - terminator Return(v72) (exit_acc=v72) + v92 Phi { incoming=[b33:v88, b49:v90], kind=I64 } -> x2 + v93 LoadLocal { off=-12, kind=I64 } -> x0 + v94 BinopI { op=ne, lhs=v92, rhs_imm=10 } -> x0 + terminator Bz { cond=v94, target=b36, fall=b35 } (exit_acc=v94) block 35 start_pc=0 - v73 LoadLocal { off=-2, kind=I32 } -> x2 - terminator Jmp(b37) (exit_acc=v3) + v95 Imm(21) -> x0 + terminator Return(v95) (exit_acc=v95) block 36 start_pc=0 - v74 Imm(4607182418800017408) -> x2 - v75 StoreLocal { off=-11, value=v74, kind=F64 } -> - - terminator Jmp(b38) (exit_acc=v75) + v96 LoadLocal { off=-2, kind=I32 } -> x0 + terminator Jmp(b37) (exit_acc=v3) block 37 start_pc=0 - v76 Imm(2) -> x2 - v77 FpCast { kind=IntToFp, value=v76 } -> d0 - v78 StoreLocal { off=-11, value=v77, kind=F64 } -> - - terminator Jmp(b38) (exit_acc=v78) + v99 Imm(2) -> x1 + v100 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v99) block 38 start_pc=0 - v79 LoadLocal { off=-11, kind=F64 } -> d0 - v80 Imm(4611686018427387904) -> x2 - v81 Binop { op=fne, lhs=v79, rhs=v80 } -> x2 - terminator Bz { cond=v81, target=b40, fall=b39 } (exit_acc=v81) + v101 Phi { incoming=[b50:v97, b37:v99], kind=I64 } -> x1 + v102 LoadLocal { off=-13, kind=I64 } -> x0 + v103 Imm(0) -> x0 + v104 LoadLocal { off=-3, kind=I64 } -> x0 + v105 BinopI { op=ne, lhs=v101, rhs_imm=2 } -> x0 + terminator Bz { cond=v105, target=b40, fall=b39 } (exit_acc=v105) block 39 start_pc=0 - v82 Imm(18) -> x0 - terminator Return(v82) (exit_acc=v82) + v106 Imm(22) -> x0 + terminator Return(v106) (exit_acc=v106) block 40 start_pc=0 - v83 LoadLocal { off=-1, kind=I32 } -> x2 - terminator Jmp(b41) (exit_acc=v1) + v107 Imm(0) -> x0 + terminator Return(v107) (exit_acc=v107) block 41 start_pc=0 - v84 Imm(10) -> x2 - v85 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v84) + v9 Imm(4611686018427387904) -> x2 + v10 StoreLocal { off=-4, value=v9, kind=F64 } -> - + terminator Jmp(b2) (exit_acc=v10) block 42 start_pc=0 - v86 Imm(20) -> x2 - v87 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v86) + v16 Imm(1) -> x2 + v17 FpCast { kind=IntToFp, value=v16 } -> d0 + v18 StoreLocal { off=-5, value=v17, kind=F64 } -> - + terminator Jmp(b6) (exit_acc=v18) block 43 start_pc=0 - v88 Phi { incoming=[b41:v84, b42:v86], kind=I64 } -> x2 - v89 LoadLocal { off=-12, kind=I64 } -> x0 - v90 BinopI { op=ne, lhs=v88, rhs_imm=10 } -> x0 - terminator Bz { cond=v90, target=b45, fall=b44 } (exit_acc=v90) + v28 Imm(2) -> x2 + v29 FpCast { kind=IntToFp, value=v28 } -> d0 + v30 StoreLocal { off=-6, value=v29, kind=F64 } -> - + terminator Jmp(b10) (exit_acc=v30) block 44 start_pc=0 - v91 Imm(21) -> x0 - terminator Return(v91) (exit_acc=v91) + v36 Imm(4607182418800017408) -> x2 + v37 StoreLocal { off=-7, value=v36, kind=F64 } -> - + terminator Jmp(b14) (exit_acc=v37) block 45 start_pc=0 - v92 LoadLocal { off=-2, kind=I32 } -> x0 - terminator Jmp(b47) (exit_acc=v3) + v49 Imm(4611686018427387904) -> x2 + v50 StoreLocal { off=-8, value=v49, kind=F64 } -> - + terminator Jmp(b18) (exit_acc=v50) block 46 start_pc=0 - v93 Imm(1) -> x1 - v94 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v93) + v56 Imm(1065353216) -> x2 [f32] + v57 FpCast { kind=F32ToF64, value=v56 } -> d0 + v58 StoreLocal { off=-9, value=v57, kind=F64 } -> - + terminator Jmp(b22) (exit_acc=v58) block 47 start_pc=0 - v95 Imm(2) -> x1 - v96 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v95) + v68 Imm(2) -> x2 + v69 FpCast { kind=IntToFp, value=v68 } -> d0 + v70 FpCast { kind=F64ToF32, value=v69 } -> d0 [f32] + v71 StoreLocal { off=-10, value=v70, kind=F32 } -> - + terminator Jmp(b26) (exit_acc=v71) block 48 start_pc=0 - v97 Phi { incoming=[b46:v93, b47:v95], kind=I64 } -> x1 - v98 LoadLocal { off=-13, kind=I64 } -> x0 - v99 Imm(0) -> x0 - v100 LoadLocal { off=-3, kind=I64 } -> x0 - v101 BinopI { op=ne, lhs=v97, rhs_imm=2 } -> x0 - terminator Bz { cond=v101, target=b50, fall=b49 } (exit_acc=v101) + v77 Imm(1065353216) -> x2 [f32] + v78 StoreLocal { off=-11, value=v77, kind=F32 } -> - + terminator Jmp(b30) (exit_acc=v78) block 49 start_pc=0 - v102 Imm(22) -> x0 - terminator Return(v102) (exit_acc=v102) + v90 Imm(20) -> x2 + v91 Imm(0) -> x0 + terminator Jmp(b34) (exit_acc=v90) block 50 start_pc=0 - v103 Imm(0) -> x0 - terminator Return(v103) (exit_acc=v103) + v97 Imm(1) -> x1 + v98 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v97) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ternary_middle_comma.ssa b/tests/snapshots/ssa/ternary_middle_comma.ssa index 26132458b..920f853e8 100644 --- a/tests/snapshots/ssa/ternary_middle_comma.ssa +++ b/tests/snapshots/ssa/ternary_middle_comma.ssa @@ -1,53 +1,49 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=28 - spill_count=1 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-1) -> x0 v2 ImmData(52) -> x1 v3 Mcpy { dst=v1, src=v2, size=4 } -> x0 - v4 Imm(42) -> x3 + v4 Imm(42) -> x0 v5 Imm(0) -> x0 v6 LoadLocal { off=-2, kind=I32 } -> x0 - v7 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v8 BinopI { op=ult, lhs=v7, rhs_imm=128 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v7 Imm(42) -> x0 + v8 Imm(1) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 v9 LocalAddr(-1) -> x0 v10 Imm(0) -> x1 v11 LoadLocal { off=-2, kind=I32 } -> x1 - v12 BinopI { op=and, lhs=v4, rhs_imm=255 } -> x1 + v12 Imm(42) -> x1 v13 Store { addr=v9, disp=0, value=v12, kind=I8 } -> - - v14 Imm(1) -> x12 + v14 Imm(1) -> x1 v15 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v14) + terminator Jmp(b2) (exit_acc=v14) block 2 start_pc=0 - v16 Imm(99) -> x12 - v17 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v16) - block 3 start_pc=0 - v18 Phi { incoming=[b1:v14, b2:v16], kind=I64 } -> x12 + v18 Phi { incoming=[b1:v14, b42:v16], kind=I64 } -> x1 v19 LoadLocal { off=-17, kind=I64 } -> x0 v20 Imm(0) -> x0 v21 Extend { value=v18, kind=I32 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=1 } -> x13 + v22 BinopI { op=ne, lhs=v21, rhs_imm=1 } -> x2 v23 Imm(0) -> x0 - terminator Bnz { cond=v22, target=b40, fall=b4 } (exit_acc=v22) - block 4 start_pc=0 + terminator Bnz { cond=v22, target=b41, fall=b3 } (exit_acc=v22) + block 3 start_pc=0 v24 LocalAddr(-1) -> x0 - v25 Imm(0) -> x1 + v25 Imm(0) -> x2 v26 Load { addr=v24, disp=0, kind=U8 } -> x0 v27 BinopI { op=xor, lhs=v26, rhs_imm=42 } -> x0 v28 BinopI { op=and, lhs=v27, rhs_imm=4294967295 } -> x0 - v29 BinopI { op=ne, lhs=v28, rhs_imm=0 } -> x13 + v29 BinopI { op=ne, lhs=v28, rhs_imm=0 } -> x2 v30 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v29) - block 5 start_pc=0 - v31 Phi { incoming=[b40:v22, b4:v29], kind=I64 } -> x13 + terminator Jmp(b4) (exit_acc=v29) + block 4 start_pc=0 + v31 Phi { incoming=[b41:v22, b3:v29], kind=I64 } -> x2 v32 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v31, target=b7, fall=b6 } (exit_acc=v31) - block 6 start_pc=0 + terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) + block 5 start_pc=0 v33 ImmData(56) -> x7 v34 Extend { value=v18, kind=I32 } -> x6 v35 LocalAddr(-1) -> x0 @@ -56,49 +52,45 @@ fn ent_pc=1 n_params=0 variadic=false locals=28 v38 CallExt { binding_idx=0, args=[v33, v34, v37], fp_arg_mask=0x0 } -> x0 v39 Imm(1) -> x0 terminator Return(v39) (exit_acc=v39) - block 7 start_pc=0 + block 6 start_pc=0 v40 LocalAddr(-4) -> x0 v41 ImmData(78) -> x1 v42 Mcpy { dst=v40, src=v41, size=4 } -> x0 v43 LoadLocal { off=-2, kind=I32 } -> x0 - v44 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v45 BinopI { op=ult, lhs=v44, rhs_imm=128 } -> x0 - terminator Bz { cond=v45, target=b9, fall=b8 } (exit_acc=v45) - block 8 start_pc=0 + v44 Imm(42) -> x0 + v45 Imm(1) -> x0 + terminator Jmp(b7) (exit_acc=v45) + block 7 start_pc=0 v46 LocalAddr(-4) -> x0 v47 Imm(0) -> x1 v48 LoadLocal { off=-2, kind=I32 } -> x1 - v49 BinopI { op=and, lhs=v4, rhs_imm=255 } -> x1 + v49 Imm(42) -> x1 v50 Store { addr=v46, disp=0, value=v49, kind=I8 } -> - - v51 Imm(1) -> x12 + v51 Imm(1) -> x1 v52 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v51) - block 9 start_pc=0 - v53 Imm(99) -> x12 - v54 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v53) - block 10 start_pc=0 - v55 Phi { incoming=[b8:v51, b9:v53], kind=I64 } -> x12 + terminator Jmp(b8) (exit_acc=v51) + block 8 start_pc=0 + v55 Phi { incoming=[b7:v51, b43:v53], kind=I64 } -> x1 v56 LoadLocal { off=-19, kind=I64 } -> x0 v57 Imm(0) -> x0 v58 Extend { value=v55, kind=I32 } -> x0 - v59 BinopI { op=ne, lhs=v58, rhs_imm=1 } -> x13 + v59 BinopI { op=ne, lhs=v58, rhs_imm=1 } -> x2 v60 Imm(0) -> x0 - terminator Bnz { cond=v59, target=b41, fall=b11 } (exit_acc=v59) - block 11 start_pc=0 + terminator Bnz { cond=v59, target=b40, fall=b9 } (exit_acc=v59) + block 9 start_pc=0 v61 LocalAddr(-4) -> x0 - v62 Imm(0) -> x1 + v62 Imm(0) -> x2 v63 Load { addr=v61, disp=0, kind=U8 } -> x0 v64 BinopI { op=xor, lhs=v63, rhs_imm=42 } -> x0 v65 BinopI { op=and, lhs=v64, rhs_imm=4294967295 } -> x0 - v66 BinopI { op=ne, lhs=v65, rhs_imm=0 } -> x13 + v66 BinopI { op=ne, lhs=v65, rhs_imm=0 } -> x2 v67 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v66) - block 12 start_pc=0 - v68 Phi { incoming=[b41:v59, b11:v66], kind=I64 } -> x13 + terminator Jmp(b10) (exit_acc=v66) + block 10 start_pc=0 + v68 Phi { incoming=[b40:v59, b9:v66], kind=I64 } -> x2 v69 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v68, target=b14, fall=b13 } (exit_acc=v68) - block 13 start_pc=0 + terminator Bz { cond=v68, target=b12, fall=b11 } (exit_acc=v68) + block 11 start_pc=0 v70 ImmData(82) -> x7 v71 Extend { value=v55, kind=I32 } -> x6 v72 LocalAddr(-4) -> x0 @@ -107,49 +99,45 @@ fn ent_pc=1 n_params=0 variadic=false locals=28 v75 CallExt { binding_idx=0, args=[v70, v71, v74], fp_arg_mask=0x0 } -> x0 v76 Imm(2) -> x0 terminator Return(v76) (exit_acc=v76) - block 14 start_pc=0 + block 12 start_pc=0 v77 LocalAddr(-6) -> x0 v78 ImmData(104) -> x1 v79 Mcpy { dst=v77, src=v78, size=4 } -> x0 v80 LoadLocal { off=-2, kind=I32 } -> x0 - v81 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v82 BinopI { op=ult, lhs=v81, rhs_imm=128 } -> x0 - terminator Bz { cond=v82, target=b16, fall=b15 } (exit_acc=v82) - block 15 start_pc=0 + v81 Imm(42) -> x0 + v82 Imm(1) -> x0 + terminator Jmp(b13) (exit_acc=v82) + block 13 start_pc=0 v83 LocalAddr(-6) -> x0 v84 Imm(0) -> x1 v85 LoadLocal { off=-2, kind=I32 } -> x1 - v86 BinopI { op=and, lhs=v4, rhs_imm=255 } -> x1 + v86 Imm(42) -> x1 v87 Store { addr=v83, disp=0, value=v86, kind=I8 } -> - - v88 Imm(1) -> x12 + v88 Imm(1) -> x1 v89 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v88) - block 16 start_pc=0 - v90 Imm(99) -> x12 - v91 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v90) - block 17 start_pc=0 - v92 Phi { incoming=[b15:v88, b16:v90], kind=I64 } -> x12 + terminator Jmp(b14) (exit_acc=v88) + block 14 start_pc=0 + v92 Phi { incoming=[b13:v88, b44:v90], kind=I64 } -> x1 v93 LoadLocal { off=-21, kind=I64 } -> x0 v94 Imm(0) -> x0 v95 Extend { value=v92, kind=I32 } -> x0 - v96 BinopI { op=ne, lhs=v95, rhs_imm=1 } -> x13 + v96 BinopI { op=ne, lhs=v95, rhs_imm=1 } -> x2 v97 Imm(0) -> x0 - terminator Bnz { cond=v96, target=b42, fall=b18 } (exit_acc=v96) - block 18 start_pc=0 + terminator Bnz { cond=v96, target=b39, fall=b15 } (exit_acc=v96) + block 15 start_pc=0 v98 LocalAddr(-6) -> x0 - v99 Imm(0) -> x1 + v99 Imm(0) -> x2 v100 Load { addr=v98, disp=0, kind=U8 } -> x0 v101 BinopI { op=xor, lhs=v100, rhs_imm=42 } -> x0 v102 BinopI { op=and, lhs=v101, rhs_imm=4294967295 } -> x0 - v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x13 + v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x2 v104 Imm(0) -> x0 - terminator Jmp(b19) (exit_acc=v103) - block 19 start_pc=0 - v105 Phi { incoming=[b42:v96, b18:v103], kind=I64 } -> x13 + terminator Jmp(b16) (exit_acc=v103) + block 16 start_pc=0 + v105 Phi { incoming=[b39:v96, b15:v103], kind=I64 } -> x2 v106 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v105, target=b21, fall=b20 } (exit_acc=v105) - block 20 start_pc=0 + terminator Bz { cond=v105, target=b18, fall=b17 } (exit_acc=v105) + block 17 start_pc=0 v107 ImmData(108) -> x7 v108 Extend { value=v92, kind=I32 } -> x6 v109 LocalAddr(-6) -> x0 @@ -158,132 +146,119 @@ fn ent_pc=1 n_params=0 variadic=false locals=28 v112 CallExt { binding_idx=0, args=[v107, v108, v111], fp_arg_mask=0x0 } -> x0 v113 Imm(3) -> x0 terminator Return(v113) (exit_acc=v113) - block 21 start_pc=0 - v114 Imm(0) -> x12 + block 18 start_pc=0 + v114 Imm(0) -> x2 v115 Imm(0) -> x0 v116 Imm(0) -> x0 v117 Imm(0) -> x0 v118 LoadLocal { off=-2, kind=I32 } -> x0 - v119 BinopI { op=gt, lhs=v4, rhs_imm=0 } -> x0 - terminator Bz { cond=v119, target=b23, fall=b22 } (exit_acc=v119) - block 22 start_pc=0 - v120 Imm(1) -> x14 + v119 Imm(1) -> x0 + terminator Jmp(b19) (exit_acc=v119) + block 19 start_pc=0 + v120 Imm(1) -> x7 v121 Imm(0) -> x0 - v122 Imm(2) -> x13 + v122 Imm(2) -> x6 v123 Imm(0) -> x0 - v124 Imm(3) -> x12 + v124 Imm(3) -> x2 v125 Imm(0) -> x0 v126 LoadLocal { off=-8, kind=I32 } -> x0 v127 LoadLocal { off=-9, kind=I32 } -> x0 - v128 Binop { op=add, lhs=v120, rhs=v122 } -> x0 - v129 BinopI { op=shl, lhs=v128, rhs_imm=32 } -> x1 - v130 Extend { value=v128, kind=I32 } -> x1 - v131 LoadLocal { off=-10, kind=I32 } -> x1 - v132 Binop { op=add, lhs=v128, rhs=v124 } -> x0 - v133 BinopI { op=shl, lhs=v132, rhs_imm=32 } -> x1 - v134 Extend { value=v132, kind=I32 } -> x3 + v128 Imm(3) -> x0 + v129 Imm(12884901888) -> x0 + v130 Imm(3) -> x0 + v131 LoadLocal { off=-10, kind=I32 } -> x0 + v132 Imm(6) -> x0 + v133 Imm(25769803776) -> x0 + v134 Imm(6) -> x1 v135 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v134) - block 23 start_pc=0 - v136 Imm(-1) -> x3 - v137 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v136) - block 24 start_pc=0 - v138 Phi { incoming=[b22:v134, b23:v136], kind=I64 } -> x3 - v139 Phi { incoming=[b22:v124, b23:v114], kind=I64 } -> x12 - v140 Phi { incoming=[b22:v122, b23:v114], kind=I64 } -> x13 - v141 Phi { incoming=[b22:v120, b23:v114], kind=I64 } -> x14 + terminator Jmp(b20) (exit_acc=v134) + block 20 start_pc=0 + v138 Phi { incoming=[b19:v134, b45:v136], kind=I64 } -> x1 + v139 Phi { incoming=[b19:v124, b45:v114], kind=I64 } -> x2 + v140 Phi { incoming=[b19:v122, b45:v114], kind=I64 } -> x6 + v141 Phi { incoming=[b19:v120, b45:v114], kind=I64 } -> x7 v142 LoadLocal { off=-23, kind=I64 } -> x0 v143 Imm(0) -> x0 v144 Extend { value=v138, kind=I32 } -> x0 v145 BinopI { op=ne, lhs=v144, rhs_imm=6 } -> x0 - v146 Imm(1) -> x15 - v147 Imm(0) -> x1 - terminator Bnz { cond=v145, target=b43, fall=b25 } (exit_acc=v145) - block 25 start_pc=0 + v146 Imm(1) -> x9 + v147 Imm(0) -> x8 + terminator Bnz { cond=v145, target=b38, fall=b21 } (exit_acc=v145) + block 21 start_pc=0 v148 Extend { value=v141, kind=I32 } -> x0 v149 BinopI { op=ne, lhs=v148, rhs_imm=1 } -> x0 - v150 BinopI { op=ne, lhs=v149, rhs_imm=0 } -> x15 + v150 BinopI { op=ne, lhs=v149, rhs_imm=0 } -> x9 v151 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v150) - block 26 start_pc=0 - v152 Phi { incoming=[b43:v146, b25:v150], kind=I64 } -> x15 + terminator Jmp(b22) (exit_acc=v150) + block 22 start_pc=0 + v152 Phi { incoming=[b38:v146, b21:v150], kind=I64 } -> x9 v153 LoadLocal { off=-26, kind=I64 } -> x0 - v154 Imm(1) -> [spill 0] + v154 Imm(1) -> x8 v155 Imm(0) -> x0 - terminator Bnz { cond=v152, target=b44, fall=b27 } (exit_acc=v152) - block 27 start_pc=0 + terminator Bnz { cond=v152, target=b37, fall=b23 } (exit_acc=v152) + block 23 start_pc=0 v156 Extend { value=v140, kind=I32 } -> x0 v157 BinopI { op=ne, lhs=v156, rhs_imm=2 } -> x0 - v158 BinopI { op=ne, lhs=v157, rhs_imm=0 } -> [spill 0] + v158 BinopI { op=ne, lhs=v157, rhs_imm=0 } -> x8 v159 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v158) - block 28 start_pc=0 - v160 Phi { incoming=[b44:v154, b27:v158], kind=I64 } -> [spill 0] + terminator Jmp(b24) (exit_acc=v158) + block 24 start_pc=0 + v160 Phi { incoming=[b37:v154, b23:v158], kind=I64 } -> x8 v161 LoadLocal { off=-25, kind=I64 } -> x0 v162 Imm(0) -> x0 - terminator Bnz { cond=v160, target=b45, fall=b29 } (exit_acc=v160) - block 29 start_pc=0 + terminator Bnz { cond=v160, target=b36, fall=b25 } (exit_acc=v160) + block 25 start_pc=0 v163 Extend { value=v139, kind=I32 } -> x0 - v164 BinopI { op=ne, lhs=v163, rhs_imm=3 } -> [spill 0] + v164 BinopI { op=ne, lhs=v163, rhs_imm=3 } -> x8 v165 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v164) - block 30 start_pc=0 - v166 Phi { incoming=[b45:v160, b29:v164], kind=I64 } -> [spill 0] + terminator Jmp(b26) (exit_acc=v164) + block 26 start_pc=0 + v166 Phi { incoming=[b36:v160, b25:v164], kind=I64 } -> x8 v167 LoadLocal { off=-24, kind=I64 } -> x0 - terminator Bz { cond=v166, target=b32, fall=b31 } (exit_acc=v166) - block 31 start_pc=0 - v168 ImmData(130) -> x7 - v169 Extend { value=v138, kind=I32 } -> x6 - v170 Extend { value=v141, kind=I32 } -> x2 - v171 Extend { value=v140, kind=I32 } -> x1 + terminator Bz { cond=v166, target=b28, fall=b27 } (exit_acc=v166) + block 27 start_pc=0 + v168 ImmData(130) -> x0 + v169 Extend { value=v138, kind=I32 } -> x1 + v170 Extend { value=v141, kind=I32 } -> x7 + v171 Extend { value=v140, kind=I32 } -> x6 v172 Extend { value=v139, kind=I32 } -> x8 v173 CallExt { binding_idx=0, args=[v168, v169, v170, v171, v172], fp_arg_mask=0x0 } -> x0 v174 Imm(4) -> x0 terminator Return(v174) (exit_acc=v174) - block 32 start_pc=0 + block 28 start_pc=0 v175 LocalAddr(-12) -> x0 v176 ImmData(159) -> x1 v177 Mcpy { dst=v175, src=v176, size=4 } -> x0 v178 Imm(200) -> x0 - v179 Imm(0) -> x1 - v180 LoadLocal { off=-2, kind=I32 } -> x1 - v181 BinopI { op=and, lhs=v178, rhs_imm=4294967295 } -> x1 - v182 BinopI { op=ult, lhs=v181, rhs_imm=128 } -> x1 - terminator Bz { cond=v182, target=b34, fall=b33 } (exit_acc=v182) - block 33 start_pc=0 - v183 LocalAddr(-12) -> x1 - v184 Imm(0) -> x2 - v185 LoadLocal { off=-2, kind=I32 } -> x2 - v186 BinopI { op=and, lhs=v178, rhs_imm=255 } -> x0 - v187 Store { addr=v183, disp=0, value=v186, kind=I8 } -> - - v188 Imm(1) -> x3 - v189 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v188) - block 34 start_pc=0 - v190 Imm(99) -> x3 + v179 Imm(0) -> x0 + v180 LoadLocal { off=-2, kind=I32 } -> x0 + v181 Imm(200) -> x0 + v182 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v182) + block 29 start_pc=0 + v190 Imm(99) -> x1 v191 Imm(0) -> x0 - terminator Jmp(b35) (exit_acc=v190) - block 35 start_pc=0 - v192 Phi { incoming=[b33:v188, b34:v190], kind=I64 } -> x3 + terminator Jmp(b30) (exit_acc=v190) + block 30 start_pc=0 + v192 Phi { incoming=[b46:v188, b29:v190], kind=I64 } -> x1 v193 LoadLocal { off=-27, kind=I64 } -> x0 v194 Imm(0) -> x0 v195 Extend { value=v192, kind=I32 } -> x0 - v196 BinopI { op=ne, lhs=v195, rhs_imm=99 } -> x12 + v196 BinopI { op=ne, lhs=v195, rhs_imm=99 } -> x2 v197 Imm(0) -> x0 - terminator Bnz { cond=v196, target=b46, fall=b36 } (exit_acc=v196) - block 36 start_pc=0 + terminator Bnz { cond=v196, target=b35, fall=b31 } (exit_acc=v196) + block 31 start_pc=0 v198 LocalAddr(-12) -> x0 - v199 Imm(0) -> x1 + v199 Imm(0) -> x2 v200 Load { addr=v198, disp=0, kind=U8 } -> x0 - v201 BinopI { op=ne, lhs=v200, rhs_imm=0 } -> x12 + v201 BinopI { op=ne, lhs=v200, rhs_imm=0 } -> x2 v202 Imm(0) -> x0 - terminator Jmp(b37) (exit_acc=v201) - block 37 start_pc=0 - v203 Phi { incoming=[b46:v196, b36:v201], kind=I64 } -> x12 + terminator Jmp(b32) (exit_acc=v201) + block 32 start_pc=0 + v203 Phi { incoming=[b35:v196, b31:v201], kind=I64 } -> x2 v204 LoadLocal { off=-28, kind=I64 } -> x0 - terminator Bz { cond=v203, target=b39, fall=b38 } (exit_acc=v203) - block 38 start_pc=0 + terminator Bz { cond=v203, target=b34, fall=b33 } (exit_acc=v203) + block 33 start_pc=0 v205 ImmData(163) -> x7 v206 Extend { value=v192, kind=I32 } -> x6 v207 LocalAddr(-12) -> x0 @@ -292,23 +267,48 @@ fn ent_pc=1 n_params=0 variadic=false locals=28 v210 CallExt { binding_idx=0, args=[v205, v206, v209], fp_arg_mask=0x0 } -> x0 v211 Imm(5) -> x0 terminator Return(v211) (exit_acc=v211) - block 39 start_pc=0 + block 34 start_pc=0 v212 Imm(0) -> x0 terminator Return(v212) (exit_acc=v212) + block 35 start_pc=0 + terminator Jmp(b32) + block 36 start_pc=0 + terminator Jmp(b26) + block 37 start_pc=0 + terminator Jmp(b24) + block 38 start_pc=0 + terminator Jmp(b22) + block 39 start_pc=0 + terminator Jmp(b16) block 40 start_pc=0 - terminator Jmp(b5) + terminator Jmp(b10) block 41 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b4) block 42 start_pc=0 - terminator Jmp(b19) + v16 Imm(99) -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) block 43 start_pc=0 - terminator Jmp(b26) + v53 Imm(99) -> x1 + v54 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v53) block 44 start_pc=0 - terminator Jmp(b28) + v90 Imm(99) -> x1 + v91 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v90) block 45 start_pc=0 - terminator Jmp(b30) + v136 Imm(-1) -> x1 + v137 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v136) block 46 start_pc=0 - terminator Jmp(b37) + v183 LocalAddr(-12) -> x0 + v184 Imm(0) -> x1 + v185 LoadLocal { off=-2, kind=I32 } -> x1 + v186 Imm(200) -> x1 + v187 Store { addr=v183, disp=0, value=v186, kind=I8 } -> - + v188 Imm(1) -> x1 + v189 Imm(0) -> x0 + terminator Jmp(b30) (exit_acc=v188) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/two_d_array_param_indexing.ssa b/tests/snapshots/ssa/two_d_array_param_indexing.ssa index ade564444..b6750d12d 100644 --- a/tests/snapshots/ssa/two_d_array_param_indexing.ssa +++ b/tests/snapshots/ssa/two_d_array_param_indexing.ssa @@ -93,32 +93,32 @@ fn ent_pc=4 n_params=0 variadic=false locals=151 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=256 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) - block 3 start_pc=0 - v9 LocalAddr(-128) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=2 } -> x2 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x0 - v13 Imm(0) -> x2 + v9 LocalAddr(-128) -> x2 + v10 Extend { value=v3, kind=I32 } -> x6 + v11 BinopI { op=shl, lhs=v4, rhs_imm=2 } -> x6 + v12 Binop { op=add, lhs=v9, rhs=v11 } -> x2 + v13 Imm(0) -> x6 v14 Store { addr=v12, disp=0, value=v13, kind=I16 } -> - - v15 LocalAddr(-128) -> x0 - v16 Extend { value=v3, kind=I32 } -> x6 - v17 BinopI { op=shl, lhs=v16, rhs_imm=2 } -> x6 - v18 Binop { op=add, lhs=v15, rhs=v17 } -> x0 - v19 Imm(2) -> x6 - v20 BinopI { op=add, lhs=v18, rhs_imm=2 } -> x6 + v15 LocalAddr(-128) -> x2 + v16 Extend { value=v3, kind=I32 } -> x7 + v17 BinopI { op=shl, lhs=v4, rhs_imm=2 } -> x7 + v18 Binop { op=add, lhs=v15, rhs=v17 } -> x2 + v19 Imm(2) -> x7 + v20 BinopI { op=add, lhs=v18, rhs_imm=2 } -> x7 v21 Store { addr=v18, disp=2, value=v13, kind=I16 } -> - terminator Jmp(b2) (exit_acc=v21) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=256 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) block 4 start_pc=0 v22 LocalAddr(-128) -> x0 v23 Imm(20) -> x1 @@ -134,11 +134,11 @@ fn ent_pc=4 n_params=0 variadic=false locals=151 v33 Store { addr=v28, disp=22, value=v32, kind=I16 } -> - v34 LocalAddr(-128) -> x0 v35 Imm(5) -> x1 - v36 Imm(0) -> x2 - v37 Extend { value=v35, kind=I32 } -> x1 - v38 Imm(0) -> x2 - v39 BinopI { op=shl, lhs=v37, rhs_imm=2 } -> x1 - v40 Binop { op=add, lhs=v34, rhs=v39 } -> x0 + v36 Imm(0) -> x1 + v37 Imm(5) -> x1 + v38 Imm(0) -> x1 + v39 Imm(20) -> x1 + v40 BinopI { op=add, lhs=v34, rhs_imm=20 } -> x0 v41 Imm(0) -> x1 v42 Load { addr=v40, disp=0, kind=U16 } -> x1 v43 Imm(2) -> x2 @@ -157,29 +157,90 @@ fn ent_pc=4 n_params=0 variadic=false locals=151 block 6 start_pc=0 v53 Imm(0) -> x1 v54 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v53) + terminator Jmp(b10) (exit_acc=v53) block 7 start_pc=0 - v55 Phi { incoming=[b6:v53, b8:v59], kind=I64 } -> x1 - v56 Extend { value=v55, kind=I32 } -> x0 - v57 BinopI { op=lt, lhs=v56, rhs_imm=10 } -> x0 - terminator Bz { cond=v57, target=b10, fall=b9 } (exit_acc=v57) + v61 Imm(0) -> x2 + v62 Imm(0) -> x6 + terminator Jmp(b8) (exit_acc=v61) block 8 start_pc=0 - v58 Extend { value=v55, kind=I32 } -> x0 - v59 BinopI { op=add, lhs=v58, rhs_imm=1 } -> x1 - v60 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v59) + v85 Imm(0) -> x2 + v86 Imm(1) -> x2 + v87 LocalAddr(-144) -> x2 + v88 Extend { value=v55, kind=I32 } -> x6 + v89 BinopI { op=mul, lhs=v56, rhs_imm=12 } -> x6 + v90 Binop { op=add, lhs=v87, rhs=v89 } -> x2 + v91 Imm(0) -> x6 + v92 Imm(0) -> x6 + v93 BinopI { op=add, lhs=v90, rhs_imm=0 } -> x2 + v94 BinopI { op=mul, lhs=v56, rhs_imm=100 } -> x6 + v95 BinopI { op=shl, lhs=v94, rhs_imm=32 } -> x7 + v96 Extend { value=v94, kind=I32 } -> x7 + v97 BinopI { op=add, lhs=v94, rhs_imm=0 } -> x6 + v98 BinopI { op=shl, lhs=v97, rhs_imm=32 } -> x7 + v99 Extend { value=v97, kind=I32 } -> x7 + v100 Store { addr=v93, disp=0, value=v97, kind=I32 } -> - + v101 Imm(0) -> x2 + v102 Imm(1) -> x2 + v103 Imm(0) -> x2 + v104 Imm(1) -> x2 + v105 Imm(1) -> x2 + v106 LocalAddr(-144) -> x2 + v107 Extend { value=v55, kind=I32 } -> x6 + v108 BinopI { op=mul, lhs=v56, rhs_imm=12 } -> x6 + v109 Binop { op=add, lhs=v106, rhs=v108 } -> x2 + v110 Imm(1) -> x6 + v111 Imm(4) -> x6 + v112 BinopI { op=add, lhs=v109, rhs_imm=4 } -> x6 + v113 BinopI { op=mul, lhs=v56, rhs_imm=100 } -> x6 + v114 BinopI { op=shl, lhs=v113, rhs_imm=32 } -> x7 + v115 Extend { value=v113, kind=I32 } -> x7 + v116 BinopI { op=add, lhs=v113, rhs_imm=1 } -> x6 + v117 BinopI { op=shl, lhs=v116, rhs_imm=32 } -> x7 + v118 Extend { value=v116, kind=I32 } -> x7 + v119 Store { addr=v109, disp=4, value=v116, kind=I32 } -> - + v120 Imm(1) -> x2 + v121 Imm(2) -> x2 + v122 Imm(0) -> x2 + v123 Imm(2) -> x2 + v124 Imm(1) -> x2 + v125 LocalAddr(-144) -> x2 + v126 Extend { value=v55, kind=I32 } -> x6 + v127 BinopI { op=mul, lhs=v56, rhs_imm=12 } -> x6 + v128 Binop { op=add, lhs=v125, rhs=v127 } -> x2 + v129 Imm(2) -> x6 + v130 Imm(8) -> x6 + v131 BinopI { op=add, lhs=v128, rhs_imm=8 } -> x6 + v132 BinopI { op=mul, lhs=v56, rhs_imm=100 } -> x6 + v133 BinopI { op=shl, lhs=v132, rhs_imm=32 } -> x7 + v134 Extend { value=v132, kind=I32 } -> x7 + v135 BinopI { op=add, lhs=v132, rhs_imm=2 } -> x6 + v136 BinopI { op=shl, lhs=v135, rhs_imm=32 } -> x7 + v137 Extend { value=v135, kind=I32 } -> x7 + v138 Store { addr=v128, disp=8, value=v135, kind=I32 } -> - + v139 Imm(2) -> x2 + v140 Imm(3) -> x2 + v141 Imm(0) -> x2 + v142 Imm(3) -> x2 + v143 Imm(0) -> x2 + terminator Jmp(b9) (exit_acc=v143) block 9 start_pc=0 - v61 Imm(0) -> x2 - v62 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v61) + v58 Extend { value=v55, kind=I32 } -> x1 + v59 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x1 + v60 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v59) block 10 start_pc=0 + v55 Phi { incoming=[b6:v53, b9:v59], kind=I64 } -> x1 + v56 Extend { value=v55, kind=I32 } -> x0 + v57 BinopI { op=lt, lhs=v56, rhs_imm=10 } -> x2 + terminator Bnz { cond=v57, target=b7, fall=b11 } (exit_acc=v57) + block 11 start_pc=0 v63 LocalAddr(-144) -> x0 v64 Imm(7) -> x1 - v65 Imm(0) -> x2 - v66 Extend { value=v64, kind=I32 } -> x1 - v67 Imm(0) -> x2 - v68 BinopI { op=mul, lhs=v66, rhs_imm=12 } -> x1 - v69 Binop { op=add, lhs=v63, rhs=v68 } -> x0 + v65 Imm(0) -> x1 + v66 Imm(7) -> x1 + v67 Imm(0) -> x1 + v68 Imm(84) -> x1 + v69 BinopI { op=add, lhs=v63, rhs_imm=84 } -> x0 v70 Imm(0) -> x1 v71 Load { addr=v69, disp=0, kind=I32 } -> x1 v72 Imm(4) -> x2 @@ -195,122 +256,156 @@ fn ent_pc=4 n_params=0 variadic=false locals=151 v82 BinopI { op=shl, lhs=v81, rhs_imm=32 } -> x1 v83 Extend { value=v81, kind=I32 } -> x0 v84 BinopI { op=ne, lhs=v83, rhs_imm=2103 } -> x0 - terminator Bz { cond=v84, target=b16, fall=b15 } (exit_acc=v84) - block 11 start_pc=0 - v85 Phi { incoming=[b9:v61, b12:v89], kind=I64 } -> x2 - v86 Extend { value=v85, kind=I32 } -> x0 - v87 BinopI { op=lt, lhs=v86, rhs_imm=3 } -> x0 - terminator Bz { cond=v87, target=b14, fall=b13 } (exit_acc=v87) + terminator Bz { cond=v84, target=b13, fall=b12 } (exit_acc=v84) block 12 start_pc=0 - v88 Extend { value=v85, kind=I32 } -> x0 - v89 BinopI { op=add, lhs=v88, rhs_imm=1 } -> x2 - v90 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v89) + v144 Imm(2) -> x0 + terminator Return(v144) (exit_acc=v144) block 13 start_pc=0 - v91 LocalAddr(-144) -> x0 - v92 Extend { value=v55, kind=I32 } -> x6 - v93 BinopI { op=mul, lhs=v92, rhs_imm=12 } -> x7 - v94 Binop { op=add, lhs=v91, rhs=v93 } -> x0 - v95 Extend { value=v85, kind=I32 } -> x7 - v96 BinopI { op=shl, lhs=v95, rhs_imm=2 } -> x8 - v97 Binop { op=add, lhs=v94, rhs=v96 } -> x8 - v98 BinopI { op=mul, lhs=v92, rhs_imm=100 } -> x6 - v99 BinopI { op=shl, lhs=v98, rhs_imm=32 } -> x8 - v100 Extend { value=v98, kind=I32 } -> x8 - v101 Binop { op=add, lhs=v98, rhs=v95 } -> x6 - v102 BinopI { op=shl, lhs=v101, rhs_imm=32 } -> x8 - v103 Extend { value=v101, kind=I32 } -> x8 - v104 StoreIndexed { base=v94, index=v95, scale=4, value=v101, kind=I32 } -> - - terminator Jmp(b12) (exit_acc=v104) + v145 Imm(0) -> x1 + v146 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v145) block 14 start_pc=0 - terminator Jmp(b8) + v153 Imm(0) -> x2 + v154 Imm(0) -> x6 + terminator Jmp(b15) (exit_acc=v153) block 15 start_pc=0 - v105 Imm(2) -> x0 - terminator Return(v105) (exit_acc=v105) + v183 Imm(0) -> x2 + v184 Imm(1) -> x2 + v185 LocalAddr(-149) -> x2 + v186 Extend { value=v147, kind=I32 } -> x6 + v187 BinopI { op=shl, lhs=v148, rhs_imm=2 } -> x6 + v188 Binop { op=add, lhs=v185, rhs=v187 } -> x2 + v189 Imm(0) -> x6 + v190 BinopI { op=add, lhs=v188, rhs_imm=0 } -> x2 + v191 Imm(65) -> x6 + v192 BinopI { op=add, lhs=v148, rhs_imm=65 } -> x6 + v193 BinopI { op=shl, lhs=v192, rhs_imm=32 } -> x7 + v194 Extend { value=v192, kind=I32 } -> x7 + v195 BinopI { op=add, lhs=v192, rhs_imm=0 } -> x6 + v196 BinopI { op=shl, lhs=v195, rhs_imm=32 } -> x7 + v197 Extend { value=v195, kind=I32 } -> x7 + v198 BinopI { op=shl, lhs=v195, rhs_imm=56 } -> x6 + v199 Extend { value=v197, kind=I8 } -> x6 + v200 Store { addr=v190, disp=0, value=v197, kind=I8 } -> - + v201 Imm(0) -> x2 + v202 Imm(1) -> x2 + v203 Imm(0) -> x2 + v204 Imm(1) -> x2 + v205 Imm(1) -> x2 + v206 LocalAddr(-149) -> x2 + v207 Extend { value=v147, kind=I32 } -> x6 + v208 BinopI { op=shl, lhs=v148, rhs_imm=2 } -> x6 + v209 Binop { op=add, lhs=v206, rhs=v208 } -> x2 + v210 Imm(1) -> x6 + v211 BinopI { op=add, lhs=v209, rhs_imm=1 } -> x6 + v212 Imm(65) -> x6 + v213 BinopI { op=add, lhs=v148, rhs_imm=65 } -> x6 + v214 BinopI { op=shl, lhs=v213, rhs_imm=32 } -> x7 + v215 Extend { value=v213, kind=I32 } -> x7 + v216 BinopI { op=add, lhs=v213, rhs_imm=1 } -> x6 + v217 BinopI { op=shl, lhs=v216, rhs_imm=32 } -> x7 + v218 Extend { value=v216, kind=I32 } -> x7 + v219 BinopI { op=shl, lhs=v216, rhs_imm=56 } -> x6 + v220 Extend { value=v218, kind=I8 } -> x6 + v221 Store { addr=v209, disp=1, value=v218, kind=I8 } -> - + v222 Imm(1) -> x2 + v223 Imm(2) -> x2 + v224 Imm(0) -> x2 + v225 Imm(2) -> x2 + v226 Imm(1) -> x2 + v227 LocalAddr(-149) -> x2 + v228 Extend { value=v147, kind=I32 } -> x6 + v229 BinopI { op=shl, lhs=v148, rhs_imm=2 } -> x6 + v230 Binop { op=add, lhs=v227, rhs=v229 } -> x2 + v231 Imm(2) -> x6 + v232 BinopI { op=add, lhs=v230, rhs_imm=2 } -> x6 + v233 Imm(65) -> x6 + v234 BinopI { op=add, lhs=v148, rhs_imm=65 } -> x6 + v235 BinopI { op=shl, lhs=v234, rhs_imm=32 } -> x7 + v236 Extend { value=v234, kind=I32 } -> x7 + v237 BinopI { op=add, lhs=v234, rhs_imm=2 } -> x6 + v238 BinopI { op=shl, lhs=v237, rhs_imm=32 } -> x7 + v239 Extend { value=v237, kind=I32 } -> x7 + v240 BinopI { op=shl, lhs=v237, rhs_imm=56 } -> x6 + v241 Extend { value=v239, kind=I8 } -> x6 + v242 Store { addr=v230, disp=2, value=v239, kind=I8 } -> - + v243 Imm(2) -> x2 + v244 Imm(3) -> x2 + v245 Imm(0) -> x2 + v246 Imm(3) -> x2 + v247 Imm(1) -> x2 + v248 LocalAddr(-149) -> x2 + v249 Extend { value=v147, kind=I32 } -> x6 + v250 BinopI { op=shl, lhs=v148, rhs_imm=2 } -> x6 + v251 Binop { op=add, lhs=v248, rhs=v250 } -> x2 + v252 Imm(3) -> x6 + v253 BinopI { op=add, lhs=v251, rhs_imm=3 } -> x6 + v254 Imm(65) -> x6 + v255 BinopI { op=add, lhs=v148, rhs_imm=65 } -> x6 + v256 BinopI { op=shl, lhs=v255, rhs_imm=32 } -> x7 + v257 Extend { value=v255, kind=I32 } -> x7 + v258 BinopI { op=add, lhs=v255, rhs_imm=3 } -> x6 + v259 BinopI { op=shl, lhs=v258, rhs_imm=32 } -> x7 + v260 Extend { value=v258, kind=I32 } -> x7 + v261 BinopI { op=shl, lhs=v258, rhs_imm=56 } -> x6 + v262 Extend { value=v260, kind=I8 } -> x6 + v263 Store { addr=v251, disp=3, value=v260, kind=I8 } -> - + v264 Imm(3) -> x2 + v265 Imm(4) -> x2 + v266 Imm(0) -> x2 + v267 Imm(4) -> x2 + v268 Imm(0) -> x2 + terminator Jmp(b16) (exit_acc=v268) block 16 start_pc=0 - v106 Imm(0) -> x1 - v107 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v106) + v150 Extend { value=v147, kind=I32 } -> x1 + v151 BinopI { op=add, lhs=v148, rhs_imm=1 } -> x1 + v152 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v151) block 17 start_pc=0 - v108 Phi { incoming=[b16:v106, b18:v112], kind=I64 } -> x1 - v109 Extend { value=v108, kind=I32 } -> x0 - v110 BinopI { op=lt, lhs=v109, rhs_imm=8 } -> x0 - terminator Bz { cond=v110, target=b20, fall=b19 } (exit_acc=v110) + v147 Phi { incoming=[b13:v145, b16:v151], kind=I64 } -> x1 + v148 Extend { value=v147, kind=I32 } -> x0 + v149 BinopI { op=lt, lhs=v148, rhs_imm=8 } -> x2 + terminator Bnz { cond=v149, target=b14, fall=b18 } (exit_acc=v149) block 18 start_pc=0 - v111 Extend { value=v108, kind=I32 } -> x0 - v112 BinopI { op=add, lhs=v111, rhs_imm=1 } -> x1 - v113 Imm(0) -> x0 - terminator Jmp(b17) (exit_acc=v112) + v155 LocalAddr(-149) -> x0 + v156 Imm(3) -> x1 + v157 Imm(0) -> x1 + v158 Imm(3) -> x1 + v159 Imm(0) -> x1 + v160 Imm(12) -> x1 + v161 BinopI { op=add, lhs=v155, rhs_imm=12 } -> x0 + v162 Imm(0) -> x1 + v163 Load { addr=v161, disp=0, kind=I8 } -> x1 + v164 Imm(1) -> x2 + v165 BinopI { op=add, lhs=v161, rhs_imm=1 } -> x2 + v166 Load { addr=v161, disp=1, kind=I8 } -> x2 + v167 Binop { op=add, lhs=v163, rhs=v166 } -> x1 + v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x2 + v169 Extend { value=v167, kind=I32 } -> x2 + v170 Imm(2) -> x2 + v171 BinopI { op=add, lhs=v161, rhs_imm=2 } -> x2 + v172 Load { addr=v161, disp=2, kind=I8 } -> x2 + v173 Binop { op=add, lhs=v167, rhs=v172 } -> x1 + v174 BinopI { op=shl, lhs=v173, rhs_imm=32 } -> x2 + v175 Extend { value=v173, kind=I32 } -> x2 + v176 Imm(3) -> x2 + v177 BinopI { op=add, lhs=v161, rhs_imm=3 } -> x2 + v178 Load { addr=v161, disp=3, kind=I8 } -> x0 + v179 Binop { op=add, lhs=v173, rhs=v178 } -> x0 + v180 BinopI { op=shl, lhs=v179, rhs_imm=32 } -> x1 + v181 Extend { value=v179, kind=I32 } -> x0 + v182 BinopI { op=ne, lhs=v181, rhs_imm=278 } -> x0 + terminator Bz { cond=v182, target=b20, fall=b19 } (exit_acc=v182) block 19 start_pc=0 - v114 Imm(0) -> x2 - v115 Imm(0) -> x0 - terminator Jmp(b21) (exit_acc=v114) + v269 Imm(3) -> x0 + terminator Return(v269) (exit_acc=v269) block 20 start_pc=0 - v116 LocalAddr(-149) -> x0 - v117 Imm(3) -> x1 - v118 Imm(0) -> x2 - v119 Extend { value=v117, kind=I32 } -> x1 - v120 Imm(0) -> x2 - v121 BinopI { op=shl, lhs=v119, rhs_imm=2 } -> x1 - v122 Binop { op=add, lhs=v116, rhs=v121 } -> x0 - v123 Imm(0) -> x1 - v124 Load { addr=v122, disp=0, kind=I8 } -> x1 - v125 Imm(1) -> x2 - v126 BinopI { op=add, lhs=v122, rhs_imm=1 } -> x2 - v127 Load { addr=v122, disp=1, kind=I8 } -> x2 - v128 Binop { op=add, lhs=v124, rhs=v127 } -> x1 - v129 BinopI { op=shl, lhs=v128, rhs_imm=32 } -> x2 - v130 Extend { value=v128, kind=I32 } -> x2 - v131 Imm(2) -> x2 - v132 BinopI { op=add, lhs=v122, rhs_imm=2 } -> x2 - v133 Load { addr=v122, disp=2, kind=I8 } -> x2 - v134 Binop { op=add, lhs=v128, rhs=v133 } -> x1 - v135 BinopI { op=shl, lhs=v134, rhs_imm=32 } -> x2 - v136 Extend { value=v134, kind=I32 } -> x2 - v137 Imm(3) -> x2 - v138 BinopI { op=add, lhs=v122, rhs_imm=3 } -> x2 - v139 Load { addr=v122, disp=3, kind=I8 } -> x0 - v140 Binop { op=add, lhs=v134, rhs=v139 } -> x0 - v141 BinopI { op=shl, lhs=v140, rhs_imm=32 } -> x1 - v142 Extend { value=v140, kind=I32 } -> x0 - v143 BinopI { op=ne, lhs=v142, rhs_imm=278 } -> x0 - terminator Bz { cond=v143, target=b26, fall=b25 } (exit_acc=v143) + v270 Imm(0) -> x0 + terminator Return(v270) (exit_acc=v270) block 21 start_pc=0 - v144 Phi { incoming=[b19:v114, b22:v148], kind=I64 } -> x2 - v145 Extend { value=v144, kind=I32 } -> x0 - v146 BinopI { op=lt, lhs=v145, rhs_imm=4 } -> x0 - terminator Bz { cond=v146, target=b24, fall=b23 } (exit_acc=v146) + terminator Jmp(b9) block 22 start_pc=0 - v147 Extend { value=v144, kind=I32 } -> x0 - v148 BinopI { op=add, lhs=v147, rhs_imm=1 } -> x2 - v149 Imm(0) -> x0 - terminator Jmp(b21) (exit_acc=v148) - block 23 start_pc=0 - v150 LocalAddr(-149) -> x0 - v151 Extend { value=v108, kind=I32 } -> x6 - v152 BinopI { op=shl, lhs=v151, rhs_imm=2 } -> x7 - v153 Binop { op=add, lhs=v150, rhs=v152 } -> x0 - v154 Extend { value=v144, kind=I32 } -> x7 - v155 Binop { op=add, lhs=v153, rhs=v154 } -> x0 - v156 Imm(65) -> x8 - v157 BinopI { op=add, lhs=v151, rhs_imm=65 } -> x6 - v158 BinopI { op=shl, lhs=v157, rhs_imm=32 } -> x8 - v159 Extend { value=v157, kind=I32 } -> x8 - v160 Binop { op=add, lhs=v157, rhs=v154 } -> x6 - v161 BinopI { op=shl, lhs=v160, rhs_imm=32 } -> x7 - v162 Extend { value=v160, kind=I32 } -> x7 - v163 BinopI { op=shl, lhs=v160, rhs_imm=56 } -> x6 - v164 Extend { value=v162, kind=I8 } -> x6 - v165 Store { addr=v155, disp=0, value=v162, kind=I8 } -> - - terminator Jmp(b22) (exit_acc=v165) - block 24 start_pc=0 - terminator Jmp(b18) - block 25 start_pc=0 - v166 Imm(3) -> x0 - terminator Return(v166) (exit_acc=v166) - block 26 start_pc=0 - v167 Imm(0) -> x0 - terminator Return(v167) (exit_acc=v167) + terminator Jmp(b16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa index 0f3ca366b..19cce3b95 100644 --- a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa +++ b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa @@ -67,55 +67,349 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 v2 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b6) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x3 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=12 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v9 Imm(0) -> x12 + v10 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v9) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x3 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v21 ImmData(56) -> x2 + v22 Extend { value=v3, kind=I32 } -> x6 + v23 BinopI { op=shl, lhs=v4, rhs_imm=4 } -> x6 + v24 Binop { op=add, lhs=v21, rhs=v23 } -> x2 + v25 Extend { value=v15, kind=I32 } -> x7 + v26 BinopI { op=shl, lhs=v16, rhs_imm=2 } -> x7 + v27 Binop { op=add, lhs=v24, rhs=v26 } -> x2 + v28 Load { addr=v27, disp=0, kind=F32 } -> d0 [f32] + v29 ImmData(248) -> x2 + v30 Binop { op=add, lhs=v29, rhs=v23 } -> x2 + v31 Binop { op=add, lhs=v30, rhs=v26 } -> x2 + v32 Load { addr=v31, disp=0, kind=F32 } -> d1 [f32] + v33 Binop { op=fne, lhs=v28, rhs=v32 } -> x2 + terminator Bnz { cond=v33, target=b12, fall=b3 } (exit_acc=v33) block 3 start_pc=0 - v9 Imm(0) -> x12 - v10 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v9) + v18 Extend { value=v15, kind=I32 } -> x2 + v19 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x12 + v20 Imm(0) -> x1 + terminator Jmp(b4) (exit_acc=v19) block 4 start_pc=0 - v11 Imm(0) -> x1 - v12 FpCast { kind=F64ToF32, value=v11 } -> d0 [f32] - v13 StoreLocal { off=-3, value=v12, kind=F32 } -> - - v14 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v11) + v15 Phi { incoming=[b1:v9, b3:v19], kind=I64 } -> x12 + v16 Extend { value=v15, kind=I32 } -> x1 + v17 BinopI { op=lt, lhs=v16, rhs_imm=4 } -> x2 + terminator Bnz { cond=v17, target=b2, fall=b5 } (exit_acc=v17) block 5 start_pc=0 - v15 Phi { incoming=[b3:v9, b6:v19], kind=I64 } -> x12 - v16 Extend { value=v15, kind=I32 } -> x0 - v17 BinopI { op=lt, lhs=v16, rhs_imm=4 } -> x0 - terminator Bz { cond=v17, target=b8, fall=b7 } (exit_acc=v17) + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x3 + v8 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v7) block 6 start_pc=0 - v18 Extend { value=v15, kind=I32 } -> x0 - v19 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x12 - v20 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v19) + v3 Phi { incoming=[b0:v1, b5:v7], kind=I64 } -> x3 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=12 } -> x1 + terminator Bnz { cond=v5, target=b1, fall=b7 } (exit_acc=v5) block 7 start_pc=0 - v21 ImmData(56) -> x0 - v22 Extend { value=v3, kind=I32 } -> x1 - v23 BinopI { op=shl, lhs=v22, rhs_imm=4 } -> x1 - v24 Binop { op=add, lhs=v21, rhs=v23 } -> x0 - v25 Extend { value=v15, kind=I32 } -> x2 - v26 BinopI { op=shl, lhs=v25, rhs_imm=2 } -> x2 - v27 Binop { op=add, lhs=v24, rhs=v26 } -> x0 - v28 Load { addr=v27, disp=0, kind=F32 } -> d0 [f32] - v29 ImmData(248) -> x0 - v30 Binop { op=add, lhs=v29, rhs=v23 } -> x0 - v31 Binop { op=add, lhs=v30, rhs=v26 } -> x0 - v32 Load { addr=v31, disp=0, kind=F32 } -> d1 [f32] - v33 Binop { op=fne, lhs=v28, rhs=v32 } -> x0 - terminator Bz { cond=v33, target=b10, fall=b9 } (exit_acc=v33) + v11 Imm(0) -> x0 [f32] + v12 StoreLocal { off=-3, value=v11, kind=F32 } -> - + v13 Imm(0) -> x0 + v14 Imm(0) -> x1 + terminator Jmp(b8) (exit_acc=v13) block 8 start_pc=0 - terminator Jmp(b2) + v53 Imm(0) -> x0 + v54 Imm(1) -> x0 + v55 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v56 ImmData(56) -> x0 + v57 Imm(0) -> x1 + v58 Imm(0) -> x1 + v59 BinopI { op=add, lhs=v56, rhs_imm=0 } -> x0 + v60 Imm(0) -> x1 + v61 Load { addr=v59, disp=0, kind=F32 } -> d1 [f32] + v62 Imm(4) -> x1 + v63 BinopI { op=add, lhs=v59, rhs_imm=4 } -> x1 + v64 Load { addr=v59, disp=4, kind=F32 } -> d2 [f32] + v65 Binop { op=fadd, lhs=v61, rhs=v64 } -> d1 [f32] + v66 Imm(8) -> x1 + v67 BinopI { op=add, lhs=v59, rhs_imm=8 } -> x1 + v68 Load { addr=v59, disp=8, kind=F32 } -> d2 [f32] + v69 Binop { op=fadd, lhs=v65, rhs=v68 } -> d1 [f32] + v70 Binop { op=fadd, lhs=v55, rhs=v69 } -> d0 [f32] + v71 StoreLocal { off=-3, value=v70, kind=F32 } -> - + v72 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v73 Imm(0) -> x0 + v74 Imm(1) -> x0 + v75 Imm(0) -> x0 + v76 Imm(1) -> x0 + v77 Imm(1) -> x0 + v78 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v79 ImmData(56) -> x0 + v80 Imm(1) -> x1 + v81 Imm(16) -> x1 + v82 BinopI { op=add, lhs=v79, rhs_imm=16 } -> x0 + v83 Imm(0) -> x1 + v84 Load { addr=v82, disp=0, kind=F32 } -> d1 [f32] + v85 Imm(4) -> x1 + v86 BinopI { op=add, lhs=v82, rhs_imm=4 } -> x1 + v87 Load { addr=v82, disp=4, kind=F32 } -> d2 [f32] + v88 Binop { op=fadd, lhs=v84, rhs=v87 } -> d1 [f32] + v89 Imm(8) -> x1 + v90 BinopI { op=add, lhs=v82, rhs_imm=8 } -> x1 + v91 Load { addr=v82, disp=8, kind=F32 } -> d2 [f32] + v92 Binop { op=fadd, lhs=v88, rhs=v91 } -> d1 [f32] + v93 Binop { op=fadd, lhs=v72, rhs=v92 } -> d0 [f32] + v94 StoreLocal { off=-3, value=v93, kind=F32 } -> - + v95 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v96 Imm(1) -> x0 + v97 Imm(2) -> x0 + v98 Imm(0) -> x0 + v99 Imm(2) -> x0 + v100 Imm(1) -> x0 + v101 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v102 ImmData(56) -> x0 + v103 Imm(2) -> x1 + v104 Imm(32) -> x1 + v105 BinopI { op=add, lhs=v102, rhs_imm=32 } -> x0 + v106 Imm(0) -> x1 + v107 Load { addr=v105, disp=0, kind=F32 } -> d1 [f32] + v108 Imm(4) -> x1 + v109 BinopI { op=add, lhs=v105, rhs_imm=4 } -> x1 + v110 Load { addr=v105, disp=4, kind=F32 } -> d2 [f32] + v111 Binop { op=fadd, lhs=v107, rhs=v110 } -> d1 [f32] + v112 Imm(8) -> x1 + v113 BinopI { op=add, lhs=v105, rhs_imm=8 } -> x1 + v114 Load { addr=v105, disp=8, kind=F32 } -> d2 [f32] + v115 Binop { op=fadd, lhs=v111, rhs=v114 } -> d1 [f32] + v116 Binop { op=fadd, lhs=v95, rhs=v115 } -> d0 [f32] + v117 StoreLocal { off=-3, value=v116, kind=F32 } -> - + v118 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v119 Imm(2) -> x0 + v120 Imm(3) -> x0 + v121 Imm(0) -> x0 + v122 Imm(3) -> x0 + v123 Imm(1) -> x0 + v124 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v125 ImmData(56) -> x0 + v126 Imm(3) -> x1 + v127 Imm(48) -> x1 + v128 BinopI { op=add, lhs=v125, rhs_imm=48 } -> x0 + v129 Imm(0) -> x1 + v130 Load { addr=v128, disp=0, kind=F32 } -> d1 [f32] + v131 Imm(4) -> x1 + v132 BinopI { op=add, lhs=v128, rhs_imm=4 } -> x1 + v133 Load { addr=v128, disp=4, kind=F32 } -> d2 [f32] + v134 Binop { op=fadd, lhs=v130, rhs=v133 } -> d1 [f32] + v135 Imm(8) -> x1 + v136 BinopI { op=add, lhs=v128, rhs_imm=8 } -> x1 + v137 Load { addr=v128, disp=8, kind=F32 } -> d2 [f32] + v138 Binop { op=fadd, lhs=v134, rhs=v137 } -> d1 [f32] + v139 Binop { op=fadd, lhs=v118, rhs=v138 } -> d0 [f32] + v140 StoreLocal { off=-3, value=v139, kind=F32 } -> - + v141 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v142 Imm(3) -> x0 + v143 Imm(4) -> x0 + v144 Imm(0) -> x0 + v145 Imm(4) -> x0 + v146 Imm(1) -> x0 + v147 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v148 ImmData(56) -> x0 + v149 Imm(4) -> x1 + v150 Imm(64) -> x1 + v151 BinopI { op=add, lhs=v148, rhs_imm=64 } -> x0 + v152 Imm(0) -> x1 + v153 Load { addr=v151, disp=0, kind=F32 } -> d1 [f32] + v154 Imm(4) -> x1 + v155 BinopI { op=add, lhs=v151, rhs_imm=4 } -> x1 + v156 Load { addr=v151, disp=4, kind=F32 } -> d2 [f32] + v157 Binop { op=fadd, lhs=v153, rhs=v156 } -> d1 [f32] + v158 Imm(8) -> x1 + v159 BinopI { op=add, lhs=v151, rhs_imm=8 } -> x1 + v160 Load { addr=v151, disp=8, kind=F32 } -> d2 [f32] + v161 Binop { op=fadd, lhs=v157, rhs=v160 } -> d1 [f32] + v162 Binop { op=fadd, lhs=v141, rhs=v161 } -> d0 [f32] + v163 StoreLocal { off=-3, value=v162, kind=F32 } -> - + v164 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v165 Imm(4) -> x0 + v166 Imm(5) -> x0 + v167 Imm(0) -> x0 + v168 Imm(5) -> x0 + v169 Imm(1) -> x0 + v170 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v171 ImmData(56) -> x0 + v172 Imm(5) -> x1 + v173 Imm(80) -> x1 + v174 BinopI { op=add, lhs=v171, rhs_imm=80 } -> x0 + v175 Imm(0) -> x1 + v176 Load { addr=v174, disp=0, kind=F32 } -> d1 [f32] + v177 Imm(4) -> x1 + v178 BinopI { op=add, lhs=v174, rhs_imm=4 } -> x1 + v179 Load { addr=v174, disp=4, kind=F32 } -> d2 [f32] + v180 Binop { op=fadd, lhs=v176, rhs=v179 } -> d1 [f32] + v181 Imm(8) -> x1 + v182 BinopI { op=add, lhs=v174, rhs_imm=8 } -> x1 + v183 Load { addr=v174, disp=8, kind=F32 } -> d2 [f32] + v184 Binop { op=fadd, lhs=v180, rhs=v183 } -> d1 [f32] + v185 Binop { op=fadd, lhs=v164, rhs=v184 } -> d0 [f32] + v186 StoreLocal { off=-3, value=v185, kind=F32 } -> - + v187 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v188 Imm(5) -> x0 + v189 Imm(6) -> x0 + v190 Imm(0) -> x0 + v191 Imm(6) -> x0 + v192 Imm(1) -> x0 + v193 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v194 ImmData(56) -> x0 + v195 Imm(6) -> x1 + v196 Imm(96) -> x1 + v197 BinopI { op=add, lhs=v194, rhs_imm=96 } -> x0 + v198 Imm(0) -> x1 + v199 Load { addr=v197, disp=0, kind=F32 } -> d1 [f32] + v200 Imm(4) -> x1 + v201 BinopI { op=add, lhs=v197, rhs_imm=4 } -> x1 + v202 Load { addr=v197, disp=4, kind=F32 } -> d2 [f32] + v203 Binop { op=fadd, lhs=v199, rhs=v202 } -> d1 [f32] + v204 Imm(8) -> x1 + v205 BinopI { op=add, lhs=v197, rhs_imm=8 } -> x1 + v206 Load { addr=v197, disp=8, kind=F32 } -> d2 [f32] + v207 Binop { op=fadd, lhs=v203, rhs=v206 } -> d1 [f32] + v208 Binop { op=fadd, lhs=v187, rhs=v207 } -> d0 [f32] + v209 StoreLocal { off=-3, value=v208, kind=F32 } -> - + v210 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v211 Imm(6) -> x0 + v212 Imm(7) -> x0 + v213 Imm(0) -> x0 + v214 Imm(7) -> x0 + v215 Imm(1) -> x0 + v216 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v217 ImmData(56) -> x0 + v218 Imm(7) -> x1 + v219 Imm(112) -> x1 + v220 BinopI { op=add, lhs=v217, rhs_imm=112 } -> x0 + v221 Imm(0) -> x1 + v222 Load { addr=v220, disp=0, kind=F32 } -> d1 [f32] + v223 Imm(4) -> x1 + v224 BinopI { op=add, lhs=v220, rhs_imm=4 } -> x1 + v225 Load { addr=v220, disp=4, kind=F32 } -> d2 [f32] + v226 Binop { op=fadd, lhs=v222, rhs=v225 } -> d1 [f32] + v227 Imm(8) -> x1 + v228 BinopI { op=add, lhs=v220, rhs_imm=8 } -> x1 + v229 Load { addr=v220, disp=8, kind=F32 } -> d2 [f32] + v230 Binop { op=fadd, lhs=v226, rhs=v229 } -> d1 [f32] + v231 Binop { op=fadd, lhs=v210, rhs=v230 } -> d0 [f32] + v232 StoreLocal { off=-3, value=v231, kind=F32 } -> - + v233 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v234 Imm(7) -> x0 + v235 Imm(8) -> x0 + v236 Imm(0) -> x0 + v237 Imm(8) -> x0 + v238 Imm(1) -> x0 + v239 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v240 ImmData(56) -> x0 + v241 Imm(8) -> x1 + v242 Imm(128) -> x1 + v243 BinopI { op=add, lhs=v240, rhs_imm=128 } -> x0 + v244 Imm(0) -> x1 + v245 Load { addr=v243, disp=0, kind=F32 } -> d1 [f32] + v246 Imm(4) -> x1 + v247 BinopI { op=add, lhs=v243, rhs_imm=4 } -> x1 + v248 Load { addr=v243, disp=4, kind=F32 } -> d2 [f32] + v249 Binop { op=fadd, lhs=v245, rhs=v248 } -> d1 [f32] + v250 Imm(8) -> x1 + v251 BinopI { op=add, lhs=v243, rhs_imm=8 } -> x1 + v252 Load { addr=v243, disp=8, kind=F32 } -> d2 [f32] + v253 Binop { op=fadd, lhs=v249, rhs=v252 } -> d1 [f32] + v254 Binop { op=fadd, lhs=v233, rhs=v253 } -> d0 [f32] + v255 StoreLocal { off=-3, value=v254, kind=F32 } -> - + v256 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v257 Imm(8) -> x0 + v258 Imm(9) -> x0 + v259 Imm(0) -> x0 + v260 Imm(9) -> x0 + v261 Imm(1) -> x0 + v262 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v263 ImmData(56) -> x0 + v264 Imm(9) -> x1 + v265 Imm(144) -> x1 + v266 BinopI { op=add, lhs=v263, rhs_imm=144 } -> x0 + v267 Imm(0) -> x1 + v268 Load { addr=v266, disp=0, kind=F32 } -> d1 [f32] + v269 Imm(4) -> x1 + v270 BinopI { op=add, lhs=v266, rhs_imm=4 } -> x1 + v271 Load { addr=v266, disp=4, kind=F32 } -> d2 [f32] + v272 Binop { op=fadd, lhs=v268, rhs=v271 } -> d1 [f32] + v273 Imm(8) -> x1 + v274 BinopI { op=add, lhs=v266, rhs_imm=8 } -> x1 + v275 Load { addr=v266, disp=8, kind=F32 } -> d2 [f32] + v276 Binop { op=fadd, lhs=v272, rhs=v275 } -> d1 [f32] + v277 Binop { op=fadd, lhs=v256, rhs=v276 } -> d0 [f32] + v278 StoreLocal { off=-3, value=v277, kind=F32 } -> - + v279 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v280 Imm(9) -> x0 + v281 Imm(10) -> x0 + v282 Imm(0) -> x0 + v283 Imm(10) -> x0 + v284 Imm(1) -> x0 + v285 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v286 ImmData(56) -> x0 + v287 Imm(10) -> x1 + v288 Imm(160) -> x1 + v289 BinopI { op=add, lhs=v286, rhs_imm=160 } -> x0 + v290 Imm(0) -> x1 + v291 Load { addr=v289, disp=0, kind=F32 } -> d1 [f32] + v292 Imm(4) -> x1 + v293 BinopI { op=add, lhs=v289, rhs_imm=4 } -> x1 + v294 Load { addr=v289, disp=4, kind=F32 } -> d2 [f32] + v295 Binop { op=fadd, lhs=v291, rhs=v294 } -> d1 [f32] + v296 Imm(8) -> x1 + v297 BinopI { op=add, lhs=v289, rhs_imm=8 } -> x1 + v298 Load { addr=v289, disp=8, kind=F32 } -> d2 [f32] + v299 Binop { op=fadd, lhs=v295, rhs=v298 } -> d1 [f32] + v300 Binop { op=fadd, lhs=v279, rhs=v299 } -> d0 [f32] + v301 StoreLocal { off=-3, value=v300, kind=F32 } -> - + v302 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v303 Imm(10) -> x0 + v304 Imm(11) -> x0 + v305 Imm(0) -> x0 + v306 Imm(11) -> x0 + v307 Imm(1) -> x0 + v308 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v309 ImmData(56) -> x0 + v310 Imm(11) -> x1 + v311 Imm(176) -> x1 + v312 BinopI { op=add, lhs=v309, rhs_imm=176 } -> x0 + v313 Imm(0) -> x1 + v314 Load { addr=v312, disp=0, kind=F32 } -> d1 [f32] + v315 Imm(4) -> x1 + v316 BinopI { op=add, lhs=v312, rhs_imm=4 } -> x1 + v317 Load { addr=v312, disp=4, kind=F32 } -> d2 [f32] + v318 Binop { op=fadd, lhs=v314, rhs=v317 } -> d1 [f32] + v319 Imm(8) -> x1 + v320 BinopI { op=add, lhs=v312, rhs_imm=8 } -> x1 + v321 Load { addr=v312, disp=8, kind=F32 } -> d2 [f32] + v322 Binop { op=fadd, lhs=v318, rhs=v321 } -> d1 [f32] + v323 Binop { op=fadd, lhs=v302, rhs=v322 } -> d0 [f32] + v324 StoreLocal { off=-3, value=v323, kind=F32 } -> - + v325 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v326 Imm(11) -> x0 + v327 Imm(12) -> x0 + v328 Imm(0) -> x0 + v329 Imm(12) -> x0 + v330 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v330) block 9 start_pc=0 + v331 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v332 Imm(0) -> x0 [f32] + v333 Binop { op=fne, lhs=v331, rhs=v332 } -> x0 + terminator Bz { cond=v333, target=b11, fall=b10 } (exit_acc=v333) + block 10 start_pc=0 + v334 Imm(2) -> x3 + v335 Call { target_pc=0, args=[v334], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v336 ImmData(470) -> x6 + v337 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v338 FpCast { kind=F32ToF64, value=v337 } -> d0 + v339 CallExt { binding_idx=1, args=[v335, v336, v338], fp_arg_mask=0x4 } -> x0 + terminator Return(v334) (exit_acc=v334) + block 11 start_pc=0 + v340 Imm(0) -> x0 + terminator Return(v340) (exit_acc=v340) + block 12 start_pc=0 v34 Imm(2) -> x7 v35 Call { target_pc=0, args=[v34], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v36 ImmData(440) -> x6 @@ -136,56 +430,10 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v51 CallExt { binding_idx=1, args=[v35, v36, v37, v38, v45, v50], fp_arg_mask=0x30 } -> x0 v52 Imm(1) -> x0 terminator Return(v52) (exit_acc=v52) - block 10 start_pc=0 - terminator Jmp(b6) - block 11 start_pc=0 - v53 Phi { incoming=[b4:v11, b12:v57], kind=I64 } -> x1 - v54 Extend { value=v53, kind=I32 } -> x0 - v55 BinopI { op=lt, lhs=v54, rhs_imm=12 } -> x0 - terminator Bz { cond=v55, target=b14, fall=b13 } (exit_acc=v55) - block 12 start_pc=0 - v56 Extend { value=v53, kind=I32 } -> x0 - v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x1 - v58 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v57) block 13 start_pc=0 - v59 LocalAddr(-3) -> x0 - v60 Load { addr=v59, disp=0, kind=F32 } -> d0 [f32] - v61 ImmData(56) -> x2 - v62 Extend { value=v53, kind=I32 } -> x6 - v63 BinopI { op=shl, lhs=v62, rhs_imm=4 } -> x6 - v64 Binop { op=add, lhs=v61, rhs=v63 } -> x2 - v65 Imm(0) -> x6 - v66 Load { addr=v64, disp=0, kind=F32 } -> d1 [f32] - v67 Imm(4) -> x6 - v68 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x6 - v69 Load { addr=v64, disp=4, kind=F32 } -> d2 [f32] - v70 Binop { op=fadd, lhs=v66, rhs=v69 } -> d1 [f32] - v71 Imm(8) -> x6 - v72 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x6 - v73 Load { addr=v64, disp=8, kind=F32 } -> d2 [f32] - v74 Binop { op=fadd, lhs=v70, rhs=v73 } -> d1 [f32] - v75 Binop { op=fadd, lhs=v60, rhs=v74 } -> d0 [f32] - v76 Store { addr=v59, disp=0, value=v75, kind=F32 } -> - - v77 Load { addr=v59, disp=0, kind=F32 } -> d0 [f32] - terminator Jmp(b12) (exit_acc=v77) + terminator Jmp(b5) block 14 start_pc=0 - v78 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v79 Imm(0) -> x0 - v80 FpCast { kind=F32ToF64, value=v78 } -> d0 - v81 Binop { op=fne, lhs=v80, rhs=v79 } -> x0 - terminator Bz { cond=v81, target=b16, fall=b15 } (exit_acc=v81) - block 15 start_pc=0 - v82 Imm(2) -> x3 - v83 Call { target_pc=0, args=[v82], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v84 ImmData(470) -> x6 - v85 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v86 FpCast { kind=F32ToF64, value=v85 } -> d0 - v87 CallExt { binding_idx=1, args=[v83, v84, v86], fp_arg_mask=0x4 } -> x0 - terminator Return(v82) (exit_acc=v82) - block 16 start_pc=0 - v88 Imm(0) -> x0 - terminator Return(v88) (exit_acc=v88) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa b/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa index cee3c4bbe..0f3c72833 100644 --- a/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa +++ b/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa @@ -39,64 +39,59 @@ fn ent_pc=2 n_params=0 variadic=false locals=163 block 2 start_pc=0 v18 Imm(0) -> x1 v19 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v18) + terminator Jmp(b5) (exit_acc=v18) block 3 start_pc=0 - v20 Phi { incoming=[b2:v18, b4:v24], kind=I64 } -> x1 - v21 Extend { value=v20, kind=I32 } -> x0 - v22 BinopI { op=lt, lhs=v21, rhs_imm=64 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v26 LocalAddr(-161) -> x2 + v27 Extend { value=v20, kind=I32 } -> x6 + v28 BinopI { op=shl, lhs=v21, rhs_imm=2 } -> x6 + v29 Binop { op=add, lhs=v26, rhs=v28 } -> x2 + v30 FpCast { kind=IntToFp, value=v21 } -> d0 + v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] + v32 Imm(1048576000) -> x6 [f32] + v33 Binop { op=fmul, lhs=v31, rhs=v32 } -> d0 [f32] + v34 Store { addr=v29, disp=0, value=v33, kind=F32 } -> - + terminator Jmp(b4) (exit_acc=v34) block 4 start_pc=0 - v23 Extend { value=v20, kind=I32 } -> x0 - v24 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x1 + v23 Extend { value=v20, kind=I32 } -> x1 + v24 BinopI { op=add, lhs=v21, rhs_imm=1 } -> x1 v25 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v24) + terminator Jmp(b5) (exit_acc=v24) block 5 start_pc=0 - v26 LocalAddr(-161) -> x0 - v27 Extend { value=v20, kind=I32 } -> x2 - v28 BinopI { op=shl, lhs=v27, rhs_imm=2 } -> x6 - v29 Binop { op=add, lhs=v26, rhs=v28 } -> x0 - v30 FpCast { kind=IntToFp, value=v27 } -> d0 - v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] - v32 Imm(4598175219545276416) -> x2 - v33 FpCast { kind=F32ToF64, value=v31 } -> d0 - v34 Binop { op=fmul, lhs=v33, rhs=v32 } -> d0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 Store { addr=v29, disp=0, value=v35, kind=F32 } -> - - terminator Jmp(b4) (exit_acc=v36) + v20 Phi { incoming=[b2:v18, b4:v24], kind=I64 } -> x1 + v21 Extend { value=v20, kind=I32 } -> x0 + v22 BinopI { op=lt, lhs=v21, rhs_imm=64 } -> x2 + terminator Bnz { cond=v22, target=b3, fall=b6 } (exit_acc=v22) block 6 start_pc=0 - v37 LocalAddr(-161) -> x0 - v38 Imm(32) -> x1 - v39 BinopI { op=add, lhs=v37, rhs_imm=32 } -> x1 - v40 Load { addr=v37, disp=32, kind=F32 } -> d0 [f32] - v41 Imm(4611686018427387904) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 - v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v35 LocalAddr(-161) -> x0 + v36 Imm(32) -> x1 + v37 BinopI { op=add, lhs=v35, rhs_imm=32 } -> x1 + v38 Load { addr=v35, disp=32, kind=F32 } -> d0 [f32] + v39 Imm(1073741824) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b8, fall=b7 } (exit_acc=v40) block 7 start_pc=0 - v44 Imm(2) -> x0 - terminator Return(v44) (exit_acc=v44) + v41 Imm(2) -> x0 + terminator Return(v41) (exit_acc=v41) block 8 start_pc=0 - v45 LocalAddr(-128) -> x0 - v46 Imm(0) -> x1 - v47 Imm(0) -> x1 - v48 Load { addr=v45, disp=0, kind=U16 } -> x0 - v49 Imm(0) -> x0 - v50 LocalAddr(-161) -> x0 - v51 Imm(0) -> x1 - v52 Imm(4636666922610458624) -> x1 - v53 FpCast { kind=F64ToF32, value=v52 } -> d0 [f32] - v54 Store { addr=v50, disp=0, value=v53, kind=F32 } -> - - v55 LocalAddr(-161) -> x0 - v56 Load { addr=v55, disp=0, kind=F32 } -> d0 [f32] - v57 FpCast { kind=F32ToF64, value=v56 } -> d0 - v58 Binop { op=fne, lhs=v57, rhs=v52 } -> x0 - terminator Bz { cond=v58, target=b10, fall=b9 } (exit_acc=v58) + v42 LocalAddr(-128) -> x0 + v43 Imm(0) -> x1 + v44 Imm(0) -> x1 + v45 Load { addr=v42, disp=0, kind=U16 } -> x0 + v46 Imm(0) -> x0 + v47 LocalAddr(-161) -> x0 + v48 Imm(0) -> x1 + v49 Imm(1120272384) -> x1 [f32] + v50 Store { addr=v47, disp=0, value=v49, kind=F32 } -> - + v51 LocalAddr(-161) -> x0 + v52 Load { addr=v51, disp=0, kind=F32 } -> d0 [f32] + v53 Binop { op=fne, lhs=v52, rhs=v49 } -> x0 + terminator Bz { cond=v53, target=b10, fall=b9 } (exit_acc=v53) block 9 start_pc=0 - v59 Imm(3) -> x0 - terminator Return(v59) (exit_acc=v59) + v54 Imm(3) -> x0 + terminator Return(v54) (exit_acc=v54) block 10 start_pc=0 - v60 Imm(0) -> x0 - terminator Return(v60) (exit_acc=v60) + v55 Imm(0) -> x0 + terminator Return(v55) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/type_warning_arity.ssa b/tests/snapshots/ssa/type_warning_arity.ssa index a5f7be029..5bd3e8813 100644 --- a/tests/snapshots/ssa/type_warning_arity.ssa +++ b/tests/snapshots/ssa/type_warning_arity.ssa @@ -21,22 +21,22 @@ fn ent_pc=0 n_params=2 variadic=false locals=0 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=5 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(1) -> x3 + v1 Imm(1) -> x7 v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v3 Imm(0) -> x0 v4 Imm(2) -> x0 - v5 Imm(3) -> x1 - v6 Imm(4) -> x1 - v7 Extend { value=v1, kind=I32 } -> x1 - v8 Imm(0) -> x1 - v9 Extend { value=v4, kind=I32 } -> x1 - v10 Imm(0) -> x1 - v11 Binop { op=add, lhs=v1, rhs=v4 } -> x0 - v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 - v13 Extend { value=v11, kind=I32 } -> x0 + v5 Imm(3) -> x0 + v6 Imm(4) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 Imm(2) -> x0 + v10 Imm(0) -> x0 + v11 Imm(3) -> x0 + v12 Imm(12884901888) -> x0 + v13 Imm(3) -> x0 v14 Imm(0) -> x0 v15 Imm(0) -> x0 terminator Return(v15) (exit_acc=v15) diff --git a/tests/snapshots/ssa/type_warning_silenced_by_cast.ssa b/tests/snapshots/ssa/type_warning_silenced_by_cast.ssa index b3a4af243..3cdbdc48c 100644 --- a/tests/snapshots/ssa/type_warning_silenced_by_cast.ssa +++ b/tests/snapshots/ssa/type_warning_silenced_by_cast.ssa @@ -5,9 +5,9 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(5) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 BinopI { op=eq, lhs=v1, rhs_imm=0 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(0) -> x0 terminator Return(v4) (exit_acc=v4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit diff --git a/tests/snapshots/ssa/typedef_array_comma_list.ssa b/tests/snapshots/ssa/typedef_array_comma_list.ssa index 659975f1c..c25ec20be 100644 --- a/tests/snapshots/ssa/typedef_array_comma_list.ssa +++ b/tests/snapshots/ssa/typedef_array_comma_list.ssa @@ -86,21 +86,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=65 v48 Imm(274877906944) -> x0 v49 Imm(2199023255552) -> x0 v50 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v50) + terminator Jmp(b17) (exit_acc=v50) block 17 start_pc=0 - v51 Imm(9) -> x0 - terminator Return(v51) (exit_acc=v51) - block 18 start_pc=0 v52 Imm(512) -> x0 v53 Imm(64) -> x0 v54 Imm(274877906944) -> x0 v55 Imm(2199023255552) -> x0 v56 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v56) - block 19 start_pc=0 - v57 Imm(10) -> x0 - terminator Return(v57) (exit_acc=v57) - block 20 start_pc=0 + terminator Jmp(b18) (exit_acc=v56) + block 18 start_pc=0 v58 ImmData(408) -> x0 v59 Imm(256) -> x1 v60 BinopI { op=add, lhs=v58, rhs_imm=256 } -> x1 @@ -117,11 +111,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=65 v71 Store { addr=v65, disp=504, value=v70, kind=I64 } -> - v72 Load { addr=v58, disp=312, kind=I64 } -> x0 v73 BinopI { op=ne, lhs=v72, rhs_imm=42 } -> x0 - terminator Bz { cond=v73, target=b22, fall=b21 } (exit_acc=v73) - block 21 start_pc=0 + terminator Bz { cond=v73, target=b20, fall=b19 } (exit_acc=v73) + block 19 start_pc=0 v74 Imm(11) -> x0 terminator Return(v74) (exit_acc=v74) - block 22 start_pc=0 + block 20 start_pc=0 v75 ImmData(920) -> x0 v76 Imm(384) -> x1 v77 BinopI { op=add, lhs=v75, rhs_imm=384 } -> x1 @@ -129,29 +123,29 @@ fn ent_pc=0 n_params=0 variadic=false locals=65 v79 BinopI { op=add, lhs=v75, rhs_imm=504 } -> x1 v80 Load { addr=v75, disp=504, kind=I64 } -> x0 v81 BinopI { op=ne, lhs=v80, rhs_imm=-1 } -> x0 - terminator Bz { cond=v81, target=b24, fall=b23 } (exit_acc=v81) - block 23 start_pc=0 + terminator Bz { cond=v81, target=b22, fall=b21 } (exit_acc=v81) + block 21 start_pc=0 v82 Imm(12) -> x0 terminator Return(v82) (exit_acc=v82) - block 24 start_pc=0 + block 22 start_pc=0 v83 ImmData(408) -> x0 v84 Imm(0) -> x1 v85 Load { addr=v83, disp=0, kind=I64 } -> x0 v86 BinopI { op=ne, lhs=v85, rhs_imm=0 } -> x0 - terminator Bz { cond=v86, target=b26, fall=b25 } (exit_acc=v86) - block 25 start_pc=0 + terminator Bz { cond=v86, target=b24, fall=b23 } (exit_acc=v86) + block 23 start_pc=0 v87 Imm(13) -> x0 terminator Return(v87) (exit_acc=v87) - block 26 start_pc=0 + block 24 start_pc=0 v88 ImmData(920) -> x0 v89 Imm(0) -> x1 v90 Load { addr=v88, disp=0, kind=I64 } -> x0 v91 BinopI { op=ne, lhs=v90, rhs_imm=0 } -> x0 - terminator Bz { cond=v91, target=b28, fall=b27 } (exit_acc=v91) - block 27 start_pc=0 + terminator Bz { cond=v91, target=b26, fall=b25 } (exit_acc=v91) + block 25 start_pc=0 v92 Imm(14) -> x0 terminator Return(v92) (exit_acc=v92) - block 28 start_pc=0 + block 26 start_pc=0 v93 LocalAddr(-65) -> x0 v94 BinopI { op=add, lhs=v93, rhs_imm=512 } -> x1 v95 Imm(99) -> x1 @@ -160,11 +154,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=65 v98 BinopI { op=add, lhs=v97, rhs_imm=512 } -> x1 v99 Load { addr=v97, disp=512, kind=I32 } -> x0 v100 BinopI { op=ne, lhs=v99, rhs_imm=99 } -> x0 - terminator Bz { cond=v100, target=b30, fall=b29 } (exit_acc=v100) - block 29 start_pc=0 + terminator Bz { cond=v100, target=b28, fall=b27 } (exit_acc=v100) + block 27 start_pc=0 v101 Imm(15) -> x0 terminator Return(v101) (exit_acc=v101) - block 30 start_pc=0 + block 28 start_pc=0 v102 Imm(520) -> x0 v103 Imm(64) -> x0 v104 Imm(8) -> x0 @@ -174,13 +168,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=65 v108 Imm(516) -> x0 v109 Imm(2216203124736) -> x0 v110 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v110) + terminator Jmp(b29) (exit_acc=v110) + block 29 start_pc=0 + v112 Imm(0) -> x0 + terminator Return(v112) (exit_acc=v112) + block 30 start_pc=0 + v51 Imm(9) -> x0 + terminator Return(v51) (exit_acc=v51) block 31 start_pc=0 + v57 Imm(10) -> x0 + terminator Return(v57) (exit_acc=v57) + block 32 start_pc=0 v111 Imm(16) -> x0 terminator Return(v111) (exit_acc=v111) - block 32 start_pc=0 - v112 Imm(0) -> x0 - terminator Return(v112) (exit_acc=v112) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_array_outer_dim.ssa b/tests/snapshots/ssa/typedef_array_outer_dim.ssa index 60fc9c113..65f0b2a37 100644 --- a/tests/snapshots/ssa/typedef_array_outer_dim.ssa +++ b/tests/snapshots/ssa/typedef_array_outer_dim.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=fill_and_sum fn ent_pc=0 n_params=1 variadic=false locals=3 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 @@ -9,65 +9,511 @@ fn ent_pc=0 n_params=1 variadic=false locals=3 v3 Imm(0) -> x1 v4 Imm(0) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b4) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v16], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v11], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x2 - v9 BinopI { op=lt, lhs=v8, rhs_imm=4 } -> x2 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v13 Imm(0) -> x6 + v14 Imm(0) -> x8 + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 + v16 Imm(0) -> x6 + v17 Imm(1) -> x6 + v18 LoadLocal { off=2, kind=I64 } -> x6 + v19 Extend { value=v7, kind=I32 } -> x6 + v20 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v21 Binop { op=add, lhs=v1, rhs=v20 } -> x6 + v22 Imm(0) -> x8 + v23 Imm(0) -> x8 + v24 BinopI { op=add, lhs=v21, rhs_imm=0 } -> x6 + v25 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x9 + v27 Extend { value=v25, kind=I32 } -> x9 + v28 BinopI { op=add, lhs=v25, rhs_imm=0 } -> x8 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x9 + v30 Extend { value=v28, kind=I32 } -> x8 + v31 Store { addr=v24, disp=0, value=v30, kind=I64 } -> - + v32 LoadLocal { off=-3, kind=I64 } -> x6 + v33 LoadLocal { off=2, kind=I64 } -> x6 + v34 Extend { value=v7, kind=I32 } -> x6 + v35 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v36 Binop { op=add, lhs=v1, rhs=v35 } -> x6 + v37 Imm(0) -> x8 + v38 Imm(0) -> x8 + v39 BinopI { op=add, lhs=v36, rhs_imm=0 } -> x6 + v40 Load { addr=v39, disp=0, kind=I64 } -> x6 + v41 Binop { op=add, lhs=v6, rhs=v40 } -> x1 + v42 Imm(0) -> x6 + v43 Imm(0) -> x6 + v44 Imm(1) -> x6 + v45 Imm(0) -> x6 + v46 Imm(1) -> x6 + v47 Imm(1) -> x6 + v48 LoadLocal { off=2, kind=I64 } -> x6 + v49 Extend { value=v7, kind=I32 } -> x6 + v50 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v51 Binop { op=add, lhs=v1, rhs=v50 } -> x6 + v52 Imm(1) -> x8 + v53 Imm(8) -> x8 + v54 BinopI { op=add, lhs=v51, rhs_imm=8 } -> x8 + v55 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x9 + v57 Extend { value=v55, kind=I32 } -> x9 + v58 BinopI { op=add, lhs=v55, rhs_imm=1 } -> x8 + v59 BinopI { op=shl, lhs=v58, rhs_imm=32 } -> x9 + v60 Extend { value=v58, kind=I32 } -> x8 + v61 Store { addr=v51, disp=8, value=v60, kind=I64 } -> - + v62 LoadLocal { off=-3, kind=I64 } -> x6 + v63 LoadLocal { off=2, kind=I64 } -> x6 + v64 Extend { value=v7, kind=I32 } -> x6 + v65 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v66 Binop { op=add, lhs=v1, rhs=v65 } -> x6 + v67 Imm(1) -> x8 + v68 Imm(8) -> x8 + v69 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x8 + v70 Load { addr=v66, disp=8, kind=I64 } -> x6 + v71 Binop { op=add, lhs=v41, rhs=v70 } -> x1 + v72 Imm(0) -> x6 + v73 Imm(1) -> x6 + v74 Imm(2) -> x6 + v75 Imm(0) -> x6 + v76 Imm(2) -> x6 + v77 Imm(1) -> x6 + v78 LoadLocal { off=2, kind=I64 } -> x6 + v79 Extend { value=v7, kind=I32 } -> x6 + v80 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v81 Binop { op=add, lhs=v1, rhs=v80 } -> x6 + v82 Imm(2) -> x8 + v83 Imm(16) -> x8 + v84 BinopI { op=add, lhs=v81, rhs_imm=16 } -> x8 + v85 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v86 BinopI { op=shl, lhs=v85, rhs_imm=32 } -> x9 + v87 Extend { value=v85, kind=I32 } -> x9 + v88 BinopI { op=add, lhs=v85, rhs_imm=2 } -> x8 + v89 BinopI { op=shl, lhs=v88, rhs_imm=32 } -> x9 + v90 Extend { value=v88, kind=I32 } -> x8 + v91 Store { addr=v81, disp=16, value=v90, kind=I64 } -> - + v92 LoadLocal { off=-3, kind=I64 } -> x6 + v93 LoadLocal { off=2, kind=I64 } -> x6 + v94 Extend { value=v7, kind=I32 } -> x6 + v95 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v96 Binop { op=add, lhs=v1, rhs=v95 } -> x6 + v97 Imm(2) -> x8 + v98 Imm(16) -> x8 + v99 BinopI { op=add, lhs=v96, rhs_imm=16 } -> x8 + v100 Load { addr=v96, disp=16, kind=I64 } -> x6 + v101 Binop { op=add, lhs=v71, rhs=v100 } -> x1 + v102 Imm(0) -> x6 + v103 Imm(2) -> x6 + v104 Imm(3) -> x6 + v105 Imm(0) -> x6 + v106 Imm(3) -> x6 + v107 Imm(1) -> x6 + v108 LoadLocal { off=2, kind=I64 } -> x6 + v109 Extend { value=v7, kind=I32 } -> x6 + v110 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v111 Binop { op=add, lhs=v1, rhs=v110 } -> x6 + v112 Imm(3) -> x8 + v113 Imm(24) -> x8 + v114 BinopI { op=add, lhs=v111, rhs_imm=24 } -> x8 + v115 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v116 BinopI { op=shl, lhs=v115, rhs_imm=32 } -> x9 + v117 Extend { value=v115, kind=I32 } -> x9 + v118 BinopI { op=add, lhs=v115, rhs_imm=3 } -> x8 + v119 BinopI { op=shl, lhs=v118, rhs_imm=32 } -> x9 + v120 Extend { value=v118, kind=I32 } -> x8 + v121 Store { addr=v111, disp=24, value=v120, kind=I64 } -> - + v122 LoadLocal { off=-3, kind=I64 } -> x6 + v123 LoadLocal { off=2, kind=I64 } -> x6 + v124 Extend { value=v7, kind=I32 } -> x6 + v125 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v126 Binop { op=add, lhs=v1, rhs=v125 } -> x6 + v127 Imm(3) -> x8 + v128 Imm(24) -> x8 + v129 BinopI { op=add, lhs=v126, rhs_imm=24 } -> x8 + v130 Load { addr=v126, disp=24, kind=I64 } -> x6 + v131 Binop { op=add, lhs=v101, rhs=v130 } -> x1 + v132 Imm(0) -> x6 + v133 Imm(3) -> x6 + v134 Imm(4) -> x6 + v135 Imm(0) -> x6 + v136 Imm(4) -> x6 + v137 Imm(1) -> x6 + v138 LoadLocal { off=2, kind=I64 } -> x6 + v139 Extend { value=v7, kind=I32 } -> x6 + v140 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v141 Binop { op=add, lhs=v1, rhs=v140 } -> x6 + v142 Imm(4) -> x8 + v143 Imm(32) -> x8 + v144 BinopI { op=add, lhs=v141, rhs_imm=32 } -> x8 + v145 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v146 BinopI { op=shl, lhs=v145, rhs_imm=32 } -> x9 + v147 Extend { value=v145, kind=I32 } -> x9 + v148 BinopI { op=add, lhs=v145, rhs_imm=4 } -> x8 + v149 BinopI { op=shl, lhs=v148, rhs_imm=32 } -> x9 + v150 Extend { value=v148, kind=I32 } -> x8 + v151 Store { addr=v141, disp=32, value=v150, kind=I64 } -> - + v152 LoadLocal { off=-3, kind=I64 } -> x6 + v153 LoadLocal { off=2, kind=I64 } -> x6 + v154 Extend { value=v7, kind=I32 } -> x6 + v155 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v156 Binop { op=add, lhs=v1, rhs=v155 } -> x6 + v157 Imm(4) -> x8 + v158 Imm(32) -> x8 + v159 BinopI { op=add, lhs=v156, rhs_imm=32 } -> x8 + v160 Load { addr=v156, disp=32, kind=I64 } -> x6 + v161 Binop { op=add, lhs=v131, rhs=v160 } -> x1 + v162 Imm(0) -> x6 + v163 Imm(4) -> x6 + v164 Imm(5) -> x6 + v165 Imm(0) -> x6 + v166 Imm(5) -> x6 + v167 Imm(1) -> x6 + v168 LoadLocal { off=2, kind=I64 } -> x6 + v169 Extend { value=v7, kind=I32 } -> x6 + v170 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v171 Binop { op=add, lhs=v1, rhs=v170 } -> x6 + v172 Imm(5) -> x8 + v173 Imm(40) -> x8 + v174 BinopI { op=add, lhs=v171, rhs_imm=40 } -> x8 + v175 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v176 BinopI { op=shl, lhs=v175, rhs_imm=32 } -> x9 + v177 Extend { value=v175, kind=I32 } -> x9 + v178 BinopI { op=add, lhs=v175, rhs_imm=5 } -> x8 + v179 BinopI { op=shl, lhs=v178, rhs_imm=32 } -> x9 + v180 Extend { value=v178, kind=I32 } -> x8 + v181 Store { addr=v171, disp=40, value=v180, kind=I64 } -> - + v182 LoadLocal { off=-3, kind=I64 } -> x6 + v183 LoadLocal { off=2, kind=I64 } -> x6 + v184 Extend { value=v7, kind=I32 } -> x6 + v185 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v186 Binop { op=add, lhs=v1, rhs=v185 } -> x6 + v187 Imm(5) -> x8 + v188 Imm(40) -> x8 + v189 BinopI { op=add, lhs=v186, rhs_imm=40 } -> x8 + v190 Load { addr=v186, disp=40, kind=I64 } -> x6 + v191 Binop { op=add, lhs=v161, rhs=v190 } -> x1 + v192 Imm(0) -> x6 + v193 Imm(5) -> x6 + v194 Imm(6) -> x6 + v195 Imm(0) -> x6 + v196 Imm(6) -> x6 + v197 Imm(1) -> x6 + v198 LoadLocal { off=2, kind=I64 } -> x6 + v199 Extend { value=v7, kind=I32 } -> x6 + v200 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v201 Binop { op=add, lhs=v1, rhs=v200 } -> x6 + v202 Imm(6) -> x8 + v203 Imm(48) -> x8 + v204 BinopI { op=add, lhs=v201, rhs_imm=48 } -> x8 + v205 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v206 BinopI { op=shl, lhs=v205, rhs_imm=32 } -> x9 + v207 Extend { value=v205, kind=I32 } -> x9 + v208 BinopI { op=add, lhs=v205, rhs_imm=6 } -> x8 + v209 BinopI { op=shl, lhs=v208, rhs_imm=32 } -> x9 + v210 Extend { value=v208, kind=I32 } -> x8 + v211 Store { addr=v201, disp=48, value=v210, kind=I64 } -> - + v212 LoadLocal { off=-3, kind=I64 } -> x6 + v213 LoadLocal { off=2, kind=I64 } -> x6 + v214 Extend { value=v7, kind=I32 } -> x6 + v215 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v216 Binop { op=add, lhs=v1, rhs=v215 } -> x6 + v217 Imm(6) -> x8 + v218 Imm(48) -> x8 + v219 BinopI { op=add, lhs=v216, rhs_imm=48 } -> x8 + v220 Load { addr=v216, disp=48, kind=I64 } -> x6 + v221 Binop { op=add, lhs=v191, rhs=v220 } -> x1 + v222 Imm(0) -> x6 + v223 Imm(6) -> x6 + v224 Imm(7) -> x6 + v225 Imm(0) -> x6 + v226 Imm(7) -> x6 + v227 Imm(1) -> x6 + v228 LoadLocal { off=2, kind=I64 } -> x6 + v229 Extend { value=v7, kind=I32 } -> x6 + v230 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v231 Binop { op=add, lhs=v1, rhs=v230 } -> x6 + v232 Imm(7) -> x8 + v233 Imm(56) -> x8 + v234 BinopI { op=add, lhs=v231, rhs_imm=56 } -> x8 + v235 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v236 BinopI { op=shl, lhs=v235, rhs_imm=32 } -> x9 + v237 Extend { value=v235, kind=I32 } -> x9 + v238 BinopI { op=add, lhs=v235, rhs_imm=7 } -> x8 + v239 BinopI { op=shl, lhs=v238, rhs_imm=32 } -> x9 + v240 Extend { value=v238, kind=I32 } -> x8 + v241 Store { addr=v231, disp=56, value=v240, kind=I64 } -> - + v242 LoadLocal { off=-3, kind=I64 } -> x6 + v243 LoadLocal { off=2, kind=I64 } -> x6 + v244 Extend { value=v7, kind=I32 } -> x6 + v245 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v246 Binop { op=add, lhs=v1, rhs=v245 } -> x6 + v247 Imm(7) -> x8 + v248 Imm(56) -> x8 + v249 BinopI { op=add, lhs=v246, rhs_imm=56 } -> x8 + v250 Load { addr=v246, disp=56, kind=I64 } -> x6 + v251 Binop { op=add, lhs=v221, rhs=v250 } -> x1 + v252 Imm(0) -> x6 + v253 Imm(7) -> x6 + v254 Imm(8) -> x6 + v255 Imm(0) -> x6 + v256 Imm(8) -> x6 + v257 Imm(1) -> x6 + v258 LoadLocal { off=2, kind=I64 } -> x6 + v259 Extend { value=v7, kind=I32 } -> x6 + v260 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v261 Binop { op=add, lhs=v1, rhs=v260 } -> x6 + v262 Imm(8) -> x8 + v263 Imm(64) -> x8 + v264 BinopI { op=add, lhs=v261, rhs_imm=64 } -> x8 + v265 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v266 BinopI { op=shl, lhs=v265, rhs_imm=32 } -> x9 + v267 Extend { value=v265, kind=I32 } -> x9 + v268 BinopI { op=add, lhs=v265, rhs_imm=8 } -> x8 + v269 BinopI { op=shl, lhs=v268, rhs_imm=32 } -> x9 + v270 Extend { value=v268, kind=I32 } -> x8 + v271 Store { addr=v261, disp=64, value=v270, kind=I64 } -> - + v272 LoadLocal { off=-3, kind=I64 } -> x6 + v273 LoadLocal { off=2, kind=I64 } -> x6 + v274 Extend { value=v7, kind=I32 } -> x6 + v275 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v276 Binop { op=add, lhs=v1, rhs=v275 } -> x6 + v277 Imm(8) -> x8 + v278 Imm(64) -> x8 + v279 BinopI { op=add, lhs=v276, rhs_imm=64 } -> x8 + v280 Load { addr=v276, disp=64, kind=I64 } -> x6 + v281 Binop { op=add, lhs=v251, rhs=v280 } -> x1 + v282 Imm(0) -> x6 + v283 Imm(8) -> x6 + v284 Imm(9) -> x6 + v285 Imm(0) -> x6 + v286 Imm(9) -> x6 + v287 Imm(1) -> x6 + v288 LoadLocal { off=2, kind=I64 } -> x6 + v289 Extend { value=v7, kind=I32 } -> x6 + v290 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v291 Binop { op=add, lhs=v1, rhs=v290 } -> x6 + v292 Imm(9) -> x8 + v293 Imm(72) -> x8 + v294 BinopI { op=add, lhs=v291, rhs_imm=72 } -> x8 + v295 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v296 BinopI { op=shl, lhs=v295, rhs_imm=32 } -> x9 + v297 Extend { value=v295, kind=I32 } -> x9 + v298 BinopI { op=add, lhs=v295, rhs_imm=9 } -> x8 + v299 BinopI { op=shl, lhs=v298, rhs_imm=32 } -> x9 + v300 Extend { value=v298, kind=I32 } -> x8 + v301 Store { addr=v291, disp=72, value=v300, kind=I64 } -> - + v302 LoadLocal { off=-3, kind=I64 } -> x6 + v303 LoadLocal { off=2, kind=I64 } -> x6 + v304 Extend { value=v7, kind=I32 } -> x6 + v305 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v306 Binop { op=add, lhs=v1, rhs=v305 } -> x6 + v307 Imm(9) -> x8 + v308 Imm(72) -> x8 + v309 BinopI { op=add, lhs=v306, rhs_imm=72 } -> x8 + v310 Load { addr=v306, disp=72, kind=I64 } -> x6 + v311 Binop { op=add, lhs=v281, rhs=v310 } -> x1 + v312 Imm(0) -> x6 + v313 Imm(9) -> x6 + v314 Imm(10) -> x6 + v315 Imm(0) -> x6 + v316 Imm(10) -> x6 + v317 Imm(1) -> x6 + v318 LoadLocal { off=2, kind=I64 } -> x6 + v319 Extend { value=v7, kind=I32 } -> x6 + v320 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v321 Binop { op=add, lhs=v1, rhs=v320 } -> x6 + v322 Imm(10) -> x8 + v323 Imm(80) -> x8 + v324 BinopI { op=add, lhs=v321, rhs_imm=80 } -> x8 + v325 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v326 BinopI { op=shl, lhs=v325, rhs_imm=32 } -> x9 + v327 Extend { value=v325, kind=I32 } -> x9 + v328 BinopI { op=add, lhs=v325, rhs_imm=10 } -> x8 + v329 BinopI { op=shl, lhs=v328, rhs_imm=32 } -> x9 + v330 Extend { value=v328, kind=I32 } -> x8 + v331 Store { addr=v321, disp=80, value=v330, kind=I64 } -> - + v332 LoadLocal { off=-3, kind=I64 } -> x6 + v333 LoadLocal { off=2, kind=I64 } -> x6 + v334 Extend { value=v7, kind=I32 } -> x6 + v335 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v336 Binop { op=add, lhs=v1, rhs=v335 } -> x6 + v337 Imm(10) -> x8 + v338 Imm(80) -> x8 + v339 BinopI { op=add, lhs=v336, rhs_imm=80 } -> x8 + v340 Load { addr=v336, disp=80, kind=I64 } -> x6 + v341 Binop { op=add, lhs=v311, rhs=v340 } -> x1 + v342 Imm(0) -> x6 + v343 Imm(10) -> x6 + v344 Imm(11) -> x6 + v345 Imm(0) -> x6 + v346 Imm(11) -> x6 + v347 Imm(1) -> x6 + v348 LoadLocal { off=2, kind=I64 } -> x6 + v349 Extend { value=v7, kind=I32 } -> x6 + v350 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v351 Binop { op=add, lhs=v1, rhs=v350 } -> x6 + v352 Imm(11) -> x8 + v353 Imm(88) -> x8 + v354 BinopI { op=add, lhs=v351, rhs_imm=88 } -> x8 + v355 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v356 BinopI { op=shl, lhs=v355, rhs_imm=32 } -> x9 + v357 Extend { value=v355, kind=I32 } -> x9 + v358 BinopI { op=add, lhs=v355, rhs_imm=11 } -> x8 + v359 BinopI { op=shl, lhs=v358, rhs_imm=32 } -> x9 + v360 Extend { value=v358, kind=I32 } -> x8 + v361 Store { addr=v351, disp=88, value=v360, kind=I64 } -> - + v362 LoadLocal { off=-3, kind=I64 } -> x6 + v363 LoadLocal { off=2, kind=I64 } -> x6 + v364 Extend { value=v7, kind=I32 } -> x6 + v365 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v366 Binop { op=add, lhs=v1, rhs=v365 } -> x6 + v367 Imm(11) -> x8 + v368 Imm(88) -> x8 + v369 BinopI { op=add, lhs=v366, rhs_imm=88 } -> x8 + v370 Load { addr=v366, disp=88, kind=I64 } -> x6 + v371 Binop { op=add, lhs=v341, rhs=v370 } -> x1 + v372 Imm(0) -> x6 + v373 Imm(11) -> x6 + v374 Imm(12) -> x6 + v375 Imm(0) -> x6 + v376 Imm(12) -> x6 + v377 Imm(1) -> x6 + v378 LoadLocal { off=2, kind=I64 } -> x6 + v379 Extend { value=v7, kind=I32 } -> x6 + v380 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v381 Binop { op=add, lhs=v1, rhs=v380 } -> x6 + v382 Imm(12) -> x8 + v383 Imm(96) -> x8 + v384 BinopI { op=add, lhs=v381, rhs_imm=96 } -> x8 + v385 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v386 BinopI { op=shl, lhs=v385, rhs_imm=32 } -> x9 + v387 Extend { value=v385, kind=I32 } -> x9 + v388 BinopI { op=add, lhs=v385, rhs_imm=12 } -> x8 + v389 BinopI { op=shl, lhs=v388, rhs_imm=32 } -> x9 + v390 Extend { value=v388, kind=I32 } -> x8 + v391 Store { addr=v381, disp=96, value=v390, kind=I64 } -> - + v392 LoadLocal { off=-3, kind=I64 } -> x6 + v393 LoadLocal { off=2, kind=I64 } -> x6 + v394 Extend { value=v7, kind=I32 } -> x6 + v395 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v396 Binop { op=add, lhs=v1, rhs=v395 } -> x6 + v397 Imm(12) -> x8 + v398 Imm(96) -> x8 + v399 BinopI { op=add, lhs=v396, rhs_imm=96 } -> x8 + v400 Load { addr=v396, disp=96, kind=I64 } -> x6 + v401 Binop { op=add, lhs=v371, rhs=v400 } -> x1 + v402 Imm(0) -> x6 + v403 Imm(12) -> x6 + v404 Imm(13) -> x6 + v405 Imm(0) -> x6 + v406 Imm(13) -> x6 + v407 Imm(1) -> x6 + v408 LoadLocal { off=2, kind=I64 } -> x6 + v409 Extend { value=v7, kind=I32 } -> x6 + v410 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v411 Binop { op=add, lhs=v1, rhs=v410 } -> x6 + v412 Imm(13) -> x8 + v413 Imm(104) -> x8 + v414 BinopI { op=add, lhs=v411, rhs_imm=104 } -> x8 + v415 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v416 BinopI { op=shl, lhs=v415, rhs_imm=32 } -> x9 + v417 Extend { value=v415, kind=I32 } -> x9 + v418 BinopI { op=add, lhs=v415, rhs_imm=13 } -> x8 + v419 BinopI { op=shl, lhs=v418, rhs_imm=32 } -> x9 + v420 Extend { value=v418, kind=I32 } -> x8 + v421 Store { addr=v411, disp=104, value=v420, kind=I64 } -> - + v422 LoadLocal { off=-3, kind=I64 } -> x6 + v423 LoadLocal { off=2, kind=I64 } -> x6 + v424 Extend { value=v7, kind=I32 } -> x6 + v425 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v426 Binop { op=add, lhs=v1, rhs=v425 } -> x6 + v427 Imm(13) -> x8 + v428 Imm(104) -> x8 + v429 BinopI { op=add, lhs=v426, rhs_imm=104 } -> x8 + v430 Load { addr=v426, disp=104, kind=I64 } -> x6 + v431 Binop { op=add, lhs=v401, rhs=v430 } -> x1 + v432 Imm(0) -> x6 + v433 Imm(13) -> x6 + v434 Imm(14) -> x6 + v435 Imm(0) -> x6 + v436 Imm(14) -> x6 + v437 Imm(1) -> x6 + v438 LoadLocal { off=2, kind=I64 } -> x6 + v439 Extend { value=v7, kind=I32 } -> x6 + v440 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v441 Binop { op=add, lhs=v1, rhs=v440 } -> x6 + v442 Imm(14) -> x8 + v443 Imm(112) -> x8 + v444 BinopI { op=add, lhs=v441, rhs_imm=112 } -> x8 + v445 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v446 BinopI { op=shl, lhs=v445, rhs_imm=32 } -> x9 + v447 Extend { value=v445, kind=I32 } -> x9 + v448 BinopI { op=add, lhs=v445, rhs_imm=14 } -> x8 + v449 BinopI { op=shl, lhs=v448, rhs_imm=32 } -> x9 + v450 Extend { value=v448, kind=I32 } -> x8 + v451 Store { addr=v441, disp=112, value=v450, kind=I64 } -> - + v452 LoadLocal { off=-3, kind=I64 } -> x6 + v453 LoadLocal { off=2, kind=I64 } -> x6 + v454 Extend { value=v7, kind=I32 } -> x6 + v455 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v456 Binop { op=add, lhs=v1, rhs=v455 } -> x6 + v457 Imm(14) -> x8 + v458 Imm(112) -> x8 + v459 BinopI { op=add, lhs=v456, rhs_imm=112 } -> x8 + v460 Load { addr=v456, disp=112, kind=I64 } -> x6 + v461 Binop { op=add, lhs=v431, rhs=v460 } -> x1 + v462 Imm(0) -> x6 + v463 Imm(14) -> x6 + v464 Imm(15) -> x6 + v465 Imm(0) -> x6 + v466 Imm(15) -> x6 + v467 Imm(1) -> x6 + v468 LoadLocal { off=2, kind=I64 } -> x6 + v469 Extend { value=v7, kind=I32 } -> x6 + v470 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v471 Binop { op=add, lhs=v1, rhs=v470 } -> x6 + v472 Imm(15) -> x8 + v473 Imm(120) -> x8 + v474 BinopI { op=add, lhs=v471, rhs_imm=120 } -> x8 + v475 BinopI { op=shl, lhs=v8, rhs_imm=4 } -> x8 + v476 BinopI { op=shl, lhs=v475, rhs_imm=32 } -> x9 + v477 Extend { value=v475, kind=I32 } -> x9 + v478 BinopI { op=add, lhs=v475, rhs_imm=15 } -> x8 + v479 BinopI { op=shl, lhs=v478, rhs_imm=32 } -> x9 + v480 Extend { value=v478, kind=I32 } -> x8 + v481 Store { addr=v471, disp=120, value=v480, kind=I64 } -> - + v482 LoadLocal { off=-3, kind=I64 } -> x6 + v483 LoadLocal { off=2, kind=I64 } -> x6 + v484 Extend { value=v7, kind=I32 } -> x6 + v485 BinopI { op=shl, lhs=v8, rhs_imm=7 } -> x6 + v486 Binop { op=add, lhs=v1, rhs=v485 } -> x6 + v487 Imm(15) -> x8 + v488 Imm(120) -> x8 + v489 BinopI { op=add, lhs=v486, rhs_imm=120 } -> x8 + v490 Load { addr=v486, disp=120, kind=I64 } -> x6 + v491 Binop { op=add, lhs=v461, rhs=v490 } -> x1 + v492 Imm(0) -> x6 + v493 Imm(15) -> x6 + v494 Imm(16) -> x6 + v495 Imm(0) -> x6 + v496 Imm(16) -> x6 + v497 Imm(0) -> x6 + terminator Jmp(b3) (exit_acc=v497) + block 3 start_pc=0 v10 Extend { value=v7, kind=I32 } -> x0 - v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x0 + v11 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x0 v12 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 - v13 Imm(0) -> x6 - v14 Imm(0) -> x2 - terminator Jmp(b5) (exit_acc=v13) + terminator Jmp(b4) (exit_acc=v11) block 4 start_pc=0 + v6 Phi { incoming=[b0:v3, b3:v491], kind=I64 } -> x1 + v7 Phi { incoming=[b0:v3, b3:v11], kind=I64 } -> x0 + v8 Extend { value=v7, kind=I32 } -> x2 + v9 BinopI { op=lt, lhs=v8, rhs_imm=4 } -> x6 + terminator Bnz { cond=v9, target=b1, fall=b5 } (exit_acc=v9) + block 5 start_pc=0 v15 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v6) (exit_acc=v6) - block 5 start_pc=0 - v16 Phi { incoming=[b3:v6, b6:v46], kind=I64 } -> x1 - v17 Phi { incoming=[b3:v13, b6:v21], kind=I64 } -> x6 - v18 Extend { value=v17, kind=I32 } -> x2 - v19 BinopI { op=lt, lhs=v18, rhs_imm=16 } -> x2 - terminator Bz { cond=v19, target=b8, fall=b7 } (exit_acc=v19) block 6 start_pc=0 - v20 Extend { value=v17, kind=I32 } -> x2 - v21 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x6 - v22 Imm(0) -> x2 - terminator Jmp(b5) (exit_acc=v21) - block 7 start_pc=0 - v23 LoadLocal { off=2, kind=I64 } -> x2 - v24 Extend { value=v7, kind=I32 } -> x2 - v25 BinopI { op=shl, lhs=v24, rhs_imm=7 } -> x8 - v26 Binop { op=add, lhs=v1, rhs=v25 } -> x8 - v27 Extend { value=v17, kind=I32 } -> x9 - v28 BinopI { op=shl, lhs=v27, rhs_imm=3 } -> x3 - v29 Binop { op=add, lhs=v26, rhs=v28 } -> x3 - v30 BinopI { op=shl, lhs=v24, rhs_imm=4 } -> x2 - v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x3 - v32 Extend { value=v30, kind=I32 } -> x3 - v33 Binop { op=add, lhs=v30, rhs=v27 } -> x2 - v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x3 - v35 Extend { value=v33, kind=I32 } -> x2 - v36 StoreIndexed { base=v26, index=v27, scale=8, value=v35, kind=I64 } -> - - v37 LoadLocal { off=-3, kind=I64 } -> x2 - v38 LoadLocal { off=2, kind=I64 } -> x2 - v39 Extend { value=v7, kind=I32 } -> x2 - v40 BinopI { op=shl, lhs=v39, rhs_imm=7 } -> x2 - v41 Binop { op=add, lhs=v1, rhs=v40 } -> x2 - v42 Extend { value=v17, kind=I32 } -> x8 - v43 BinopI { op=shl, lhs=v42, rhs_imm=3 } -> x9 - v44 Binop { op=add, lhs=v41, rhs=v43 } -> x9 - v45 LoadIndexed { base=v41, index=v42, scale=8, kind=I64 } -> x2 - v46 Binop { op=add, lhs=v16, rhs=v45 } -> x1 - v47 Imm(0) -> x2 - terminator Jmp(b6) (exit_acc=v46) - block 8 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b3) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=67 @@ -79,53 +525,50 @@ fn ent_pc=1 n_params=0 variadic=false locals=67 v3 Imm(274877906944) -> x0 v4 Imm(2199023255552) -> x0 v5 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v5) + terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v6 Imm(1) -> x0 - terminator Return(v6) (exit_acc=v6) - block 2 start_pc=0 v7 Imm(0) -> x1 v8 Imm(0) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v7) + terminator Jmp(b4) (exit_acc=v7) + block 2 start_pc=0 + v19 LoadLocal { off=-65, kind=I64 } -> x2 + v20 Extend { value=v10, kind=I32 } -> x2 + v21 Binop { op=add, lhs=v11, rhs=v12 } -> x3 + v22 Imm(0) -> x2 + terminator Jmp(b3) (exit_acc=v21) block 3 start_pc=0 - v10 Phi { incoming=[b2:v7, b4:v17], kind=I64 } -> x1 - v11 Phi { incoming=[b2:v7, b4:v21], kind=I64 } -> x3 + v16 Extend { value=v10, kind=I32 } -> x1 + v17 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v18 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v17) + block 4 start_pc=0 + v10 Phi { incoming=[b1:v7, b3:v17], kind=I64 } -> x1 + v11 Phi { incoming=[b1:v7, b3:v21], kind=I64 } -> x3 v12 Extend { value=v10, kind=I32 } -> x0 v13 Imm(64) -> x2 v14 Imm(274877906944) -> x2 - v15 BinopI { op=lt, lhs=v12, rhs_imm=64 } -> x0 - terminator Bz { cond=v15, target=b6, fall=b5 } (exit_acc=v15) - block 4 start_pc=0 - v16 Extend { value=v10, kind=I32 } -> x0 - v17 BinopI { op=add, lhs=v16, rhs_imm=1 } -> x1 - v18 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v17) + v15 BinopI { op=lt, lhs=v12, rhs_imm=64 } -> x2 + terminator Bnz { cond=v15, target=b2, fall=b5 } (exit_acc=v15) block 5 start_pc=0 - v19 LoadLocal { off=-65, kind=I64 } -> x0 - v20 Extend { value=v10, kind=I32 } -> x0 - v21 Binop { op=add, lhs=v11, rhs=v20 } -> x3 - v22 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v21) - block 6 start_pc=0 v23 LocalAddr(-64) -> x7 v24 Call { target_pc=0, args=[v23], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 v25 LoadLocal { off=-65, kind=I64 } -> x1 v26 Binop { op=ne, lhs=v24, rhs=v11 } -> x0 - terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) - block 7 start_pc=0 + terminator Bz { cond=v26, target=b7, fall=b6 } (exit_acc=v26) + block 6 start_pc=0 v27 Imm(2) -> x0 terminator Return(v27) (exit_acc=v27) - block 8 start_pc=0 + block 7 start_pc=0 v28 LocalAddr(-64) -> x0 v29 Imm(0) -> x1 v30 Load { addr=v28, disp=0, kind=I64 } -> x0 v31 BinopI { op=ne, lhs=v30, rhs_imm=0 } -> x0 - terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) - block 9 start_pc=0 + terminator Bz { cond=v31, target=b9, fall=b8 } (exit_acc=v31) + block 8 start_pc=0 v32 Imm(3) -> x0 terminator Return(v32) (exit_acc=v32) - block 10 start_pc=0 + block 9 start_pc=0 v33 LocalAddr(-64) -> x0 v34 Imm(384) -> x1 v35 BinopI { op=add, lhs=v33, rhs_imm=384 } -> x1 @@ -133,11 +576,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=67 v37 BinopI { op=add, lhs=v33, rhs_imm=504 } -> x1 v38 Load { addr=v33, disp=504, kind=I64 } -> x0 v39 BinopI { op=ne, lhs=v38, rhs_imm=63 } -> x0 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) - block 11 start_pc=0 + terminator Bz { cond=v39, target=b11, fall=b10 } (exit_acc=v39) + block 10 start_pc=0 v40 Imm(4) -> x0 terminator Return(v40) (exit_acc=v40) - block 12 start_pc=0 + block 11 start_pc=0 v41 LocalAddr(-64) -> x0 v42 Imm(128) -> x1 v43 BinopI { op=add, lhs=v41, rhs_imm=128 } -> x1 @@ -145,13 +588,16 @@ fn ent_pc=1 n_params=0 variadic=false locals=67 v45 BinopI { op=add, lhs=v41, rhs_imm=184 } -> x1 v46 Load { addr=v41, disp=184, kind=I64 } -> x0 v47 BinopI { op=ne, lhs=v46, rhs_imm=23 } -> x0 - terminator Bz { cond=v47, target=b14, fall=b13 } (exit_acc=v47) - block 13 start_pc=0 + terminator Bz { cond=v47, target=b13, fall=b12 } (exit_acc=v47) + block 12 start_pc=0 v48 Imm(5) -> x0 terminator Return(v48) (exit_acc=v48) - block 14 start_pc=0 + block 13 start_pc=0 v49 Imm(0) -> x0 terminator Return(v49) (exit_acc=v49) + block 14 start_pc=0 + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_array_param_decay.ssa b/tests/snapshots/ssa/typedef_array_param_decay.ssa index bf0c26d8a..7244f0729 100644 --- a/tests/snapshots/ssa/typedef_array_param_decay.ssa +++ b/tests/snapshots/ssa/typedef_array_param_decay.ssa @@ -8,32 +8,224 @@ fn ent_pc=0 n_params=2 variadic=false locals=1 v2 Imm(0) -> x0 v3 ParamRef(1, kind=I64) -> x6 v4 Imm(0) -> x0 - v5 Imm(0) -> x1 - v6 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v7 Phi { incoming=[b0:v5, b2:v11], kind=I64 } -> x1 - v8 Extend { value=v7, kind=I32 } -> x0 - v9 BinopI { op=lt, lhs=v8, rhs_imm=16 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v7 Imm(0) -> x0 + v8 Imm(1) -> x0 + v9 LoadLocal { off=2, kind=I64 } -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 + v13 LoadLocal { off=3, kind=I64 } -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=0 } -> x1 + v15 Load { addr=v14, disp=0, kind=I64 } -> x1 + v16 Store { addr=v12, disp=0, value=v15, kind=I64 } -> - + v17 Imm(0) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(1) -> x0 + v21 Imm(1) -> x0 + v22 LoadLocal { off=2, kind=I64 } -> x0 + v23 Imm(1) -> x0 + v24 Imm(8) -> x0 + v25 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x0 + v26 LoadLocal { off=3, kind=I64 } -> x0 + v27 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x0 + v28 Load { addr=v3, disp=8, kind=I64 } -> x0 + v29 Store { addr=v1, disp=8, value=v28, kind=I64 } -> - + v30 Imm(1) -> x0 + v31 Imm(2) -> x0 + v32 Imm(0) -> x0 + v33 Imm(2) -> x0 + v34 Imm(1) -> x0 + v35 LoadLocal { off=2, kind=I64 } -> x0 + v36 Imm(2) -> x0 + v37 Imm(16) -> x0 + v38 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x0 + v39 LoadLocal { off=3, kind=I64 } -> x0 + v40 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x0 + v41 Load { addr=v3, disp=16, kind=I64 } -> x0 + v42 Store { addr=v1, disp=16, value=v41, kind=I64 } -> - + v43 Imm(2) -> x0 + v44 Imm(3) -> x0 + v45 Imm(0) -> x0 + v46 Imm(3) -> x0 + v47 Imm(1) -> x0 + v48 LoadLocal { off=2, kind=I64 } -> x0 + v49 Imm(3) -> x0 + v50 Imm(24) -> x0 + v51 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x0 + v52 LoadLocal { off=3, kind=I64 } -> x0 + v53 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x0 + v54 Load { addr=v3, disp=24, kind=I64 } -> x0 + v55 Store { addr=v1, disp=24, value=v54, kind=I64 } -> - + v56 Imm(3) -> x0 + v57 Imm(4) -> x0 + v58 Imm(0) -> x0 + v59 Imm(4) -> x0 + v60 Imm(1) -> x0 + v61 LoadLocal { off=2, kind=I64 } -> x0 + v62 Imm(4) -> x0 + v63 Imm(32) -> x0 + v64 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x0 + v65 LoadLocal { off=3, kind=I64 } -> x0 + v66 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x0 + v67 Load { addr=v3, disp=32, kind=I64 } -> x0 + v68 Store { addr=v1, disp=32, value=v67, kind=I64 } -> - + v69 Imm(4) -> x0 + v70 Imm(5) -> x0 + v71 Imm(0) -> x0 + v72 Imm(5) -> x0 + v73 Imm(1) -> x0 + v74 LoadLocal { off=2, kind=I64 } -> x0 + v75 Imm(5) -> x0 + v76 Imm(40) -> x0 + v77 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x0 + v78 LoadLocal { off=3, kind=I64 } -> x0 + v79 BinopI { op=add, lhs=v3, rhs_imm=40 } -> x0 + v80 Load { addr=v3, disp=40, kind=I64 } -> x0 + v81 Store { addr=v1, disp=40, value=v80, kind=I64 } -> - + v82 Imm(5) -> x0 + v83 Imm(6) -> x0 + v84 Imm(0) -> x0 + v85 Imm(6) -> x0 + v86 Imm(1) -> x0 + v87 LoadLocal { off=2, kind=I64 } -> x0 + v88 Imm(6) -> x0 + v89 Imm(48) -> x0 + v90 BinopI { op=add, lhs=v1, rhs_imm=48 } -> x0 + v91 LoadLocal { off=3, kind=I64 } -> x0 + v92 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x0 + v93 Load { addr=v3, disp=48, kind=I64 } -> x0 + v94 Store { addr=v1, disp=48, value=v93, kind=I64 } -> - + v95 Imm(6) -> x0 + v96 Imm(7) -> x0 + v97 Imm(0) -> x0 + v98 Imm(7) -> x0 + v99 Imm(1) -> x0 + v100 LoadLocal { off=2, kind=I64 } -> x0 + v101 Imm(7) -> x0 + v102 Imm(56) -> x0 + v103 BinopI { op=add, lhs=v1, rhs_imm=56 } -> x0 + v104 LoadLocal { off=3, kind=I64 } -> x0 + v105 BinopI { op=add, lhs=v3, rhs_imm=56 } -> x0 + v106 Load { addr=v3, disp=56, kind=I64 } -> x0 + v107 Store { addr=v1, disp=56, value=v106, kind=I64 } -> - + v108 Imm(7) -> x0 + v109 Imm(8) -> x0 + v110 Imm(0) -> x0 + v111 Imm(8) -> x0 + v112 Imm(1) -> x0 + v113 LoadLocal { off=2, kind=I64 } -> x0 + v114 Imm(8) -> x0 + v115 Imm(64) -> x0 + v116 BinopI { op=add, lhs=v1, rhs_imm=64 } -> x0 + v117 LoadLocal { off=3, kind=I64 } -> x0 + v118 BinopI { op=add, lhs=v3, rhs_imm=64 } -> x0 + v119 Load { addr=v3, disp=64, kind=I64 } -> x0 + v120 Store { addr=v1, disp=64, value=v119, kind=I64 } -> - + v121 Imm(8) -> x0 + v122 Imm(9) -> x0 + v123 Imm(0) -> x0 + v124 Imm(9) -> x0 + v125 Imm(1) -> x0 + v126 LoadLocal { off=2, kind=I64 } -> x0 + v127 Imm(9) -> x0 + v128 Imm(72) -> x0 + v129 BinopI { op=add, lhs=v1, rhs_imm=72 } -> x0 + v130 LoadLocal { off=3, kind=I64 } -> x0 + v131 BinopI { op=add, lhs=v3, rhs_imm=72 } -> x0 + v132 Load { addr=v3, disp=72, kind=I64 } -> x0 + v133 Store { addr=v1, disp=72, value=v132, kind=I64 } -> - + v134 Imm(9) -> x0 + v135 Imm(10) -> x0 + v136 Imm(0) -> x0 + v137 Imm(10) -> x0 + v138 Imm(1) -> x0 + v139 LoadLocal { off=2, kind=I64 } -> x0 + v140 Imm(10) -> x0 + v141 Imm(80) -> x0 + v142 BinopI { op=add, lhs=v1, rhs_imm=80 } -> x0 + v143 LoadLocal { off=3, kind=I64 } -> x0 + v144 BinopI { op=add, lhs=v3, rhs_imm=80 } -> x0 + v145 Load { addr=v3, disp=80, kind=I64 } -> x0 + v146 Store { addr=v1, disp=80, value=v145, kind=I64 } -> - + v147 Imm(10) -> x0 + v148 Imm(11) -> x0 + v149 Imm(0) -> x0 + v150 Imm(11) -> x0 + v151 Imm(1) -> x0 + v152 LoadLocal { off=2, kind=I64 } -> x0 + v153 Imm(11) -> x0 + v154 Imm(88) -> x0 + v155 BinopI { op=add, lhs=v1, rhs_imm=88 } -> x0 + v156 LoadLocal { off=3, kind=I64 } -> x0 + v157 BinopI { op=add, lhs=v3, rhs_imm=88 } -> x0 + v158 Load { addr=v3, disp=88, kind=I64 } -> x0 + v159 Store { addr=v1, disp=88, value=v158, kind=I64 } -> - + v160 Imm(11) -> x0 + v161 Imm(12) -> x0 + v162 Imm(0) -> x0 + v163 Imm(12) -> x0 + v164 Imm(1) -> x0 + v165 LoadLocal { off=2, kind=I64 } -> x0 + v166 Imm(12) -> x0 + v167 Imm(96) -> x0 + v168 BinopI { op=add, lhs=v1, rhs_imm=96 } -> x0 + v169 LoadLocal { off=3, kind=I64 } -> x0 + v170 BinopI { op=add, lhs=v3, rhs_imm=96 } -> x0 + v171 Load { addr=v3, disp=96, kind=I64 } -> x0 + v172 Store { addr=v1, disp=96, value=v171, kind=I64 } -> - + v173 Imm(12) -> x0 + v174 Imm(13) -> x0 + v175 Imm(0) -> x0 + v176 Imm(13) -> x0 + v177 Imm(1) -> x0 + v178 LoadLocal { off=2, kind=I64 } -> x0 + v179 Imm(13) -> x0 + v180 Imm(104) -> x0 + v181 BinopI { op=add, lhs=v1, rhs_imm=104 } -> x0 + v182 LoadLocal { off=3, kind=I64 } -> x0 + v183 BinopI { op=add, lhs=v3, rhs_imm=104 } -> x0 + v184 Load { addr=v3, disp=104, kind=I64 } -> x0 + v185 Store { addr=v1, disp=104, value=v184, kind=I64 } -> - + v186 Imm(13) -> x0 + v187 Imm(14) -> x0 + v188 Imm(0) -> x0 + v189 Imm(14) -> x0 + v190 Imm(1) -> x0 + v191 LoadLocal { off=2, kind=I64 } -> x0 + v192 Imm(14) -> x0 + v193 Imm(112) -> x0 + v194 BinopI { op=add, lhs=v1, rhs_imm=112 } -> x0 + v195 LoadLocal { off=3, kind=I64 } -> x0 + v196 BinopI { op=add, lhs=v3, rhs_imm=112 } -> x0 + v197 Load { addr=v3, disp=112, kind=I64 } -> x0 + v198 Store { addr=v1, disp=112, value=v197, kind=I64 } -> - + v199 Imm(14) -> x0 + v200 Imm(15) -> x0 + v201 Imm(0) -> x0 + v202 Imm(15) -> x0 + v203 Imm(1) -> x0 + v204 LoadLocal { off=2, kind=I64 } -> x0 + v205 Imm(15) -> x0 + v206 Imm(120) -> x0 + v207 BinopI { op=add, lhs=v1, rhs_imm=120 } -> x0 + v208 LoadLocal { off=3, kind=I64 } -> x0 + v209 BinopI { op=add, lhs=v3, rhs_imm=120 } -> x0 + v210 Load { addr=v3, disp=120, kind=I64 } -> x0 + v211 Store { addr=v1, disp=120, value=v210, kind=I64 } -> - + v212 Imm(15) -> x0 + v213 Imm(16) -> x0 + v214 Imm(0) -> x0 + v215 Imm(16) -> x0 + v216 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v216) block 2 start_pc=0 - v10 Extend { value=v7, kind=I32 } -> x0 - v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 - v12 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 - v13 LoadLocal { off=2, kind=I64 } -> x0 - v14 Extend { value=v7, kind=I32 } -> x0 - v15 BinopI { op=shl, lhs=v14, rhs_imm=3 } -> x0 - v16 Binop { op=add, lhs=v1, rhs=v15 } -> x2 - v17 LoadLocal { off=3, kind=I64 } -> x8 - v18 Binop { op=add, lhs=v3, rhs=v15 } -> x0 - v19 Load { addr=v18, disp=0, kind=I64 } -> x0 - v20 Store { addr=v16, disp=0, value=v19, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v20) - block 4 start_pc=0 - v21 Imm(0) -> x0 - terminator Return(v21) (exit_acc=v21) + v217 Imm(0) -> x0 + terminator Return(v217) (exit_acc=v217) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=sum fn ent_pc=1 n_params=1 variadic=false locals=2 @@ -42,100 +234,453 @@ fn ent_pc=1 n_params=1 variadic=false locals=2 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 v2 Imm(0) -> x0 - v3 Imm(0) -> x1 - v4 Imm(0) -> x0 - v5 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x1 + v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v19], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v11], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x2 - v9 BinopI { op=lt, lhs=v8, rhs_imm=16 } -> x2 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 LoadLocal { off=-2, kind=I64 } -> x0 + v9 LoadLocal { off=2, kind=I64 } -> x0 + v10 Imm(0) -> x0 + v11 Imm(0) -> x0 + v12 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 + v13 Load { addr=v12, disp=0, kind=I64 } -> x0 + v14 BinopI { op=add, lhs=v13, rhs_imm=0 } -> x0 + v15 Imm(0) -> x1 + v16 Imm(0) -> x1 + v17 Imm(1) -> x1 + v18 Imm(0) -> x1 + v19 Imm(1) -> x1 + v20 Imm(1) -> x1 + v21 LoadLocal { off=-2, kind=I64 } -> x1 + v22 LoadLocal { off=2, kind=I64 } -> x1 + v23 Imm(1) -> x1 + v24 Imm(8) -> x1 + v25 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 + v26 Load { addr=v1, disp=8, kind=I64 } -> x1 + v27 Binop { op=add, lhs=v14, rhs=v26 } -> x0 + v28 Imm(0) -> x1 + v29 Imm(1) -> x1 + v30 Imm(2) -> x1 + v31 Imm(0) -> x1 + v32 Imm(2) -> x1 + v33 Imm(1) -> x1 + v34 LoadLocal { off=-2, kind=I64 } -> x1 + v35 LoadLocal { off=2, kind=I64 } -> x1 + v36 Imm(2) -> x1 + v37 Imm(16) -> x1 + v38 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x1 + v39 Load { addr=v1, disp=16, kind=I64 } -> x1 + v40 Binop { op=add, lhs=v27, rhs=v39 } -> x0 + v41 Imm(0) -> x1 + v42 Imm(2) -> x1 + v43 Imm(3) -> x1 + v44 Imm(0) -> x1 + v45 Imm(3) -> x1 + v46 Imm(1) -> x1 + v47 LoadLocal { off=-2, kind=I64 } -> x1 + v48 LoadLocal { off=2, kind=I64 } -> x1 + v49 Imm(3) -> x1 + v50 Imm(24) -> x1 + v51 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x1 + v52 Load { addr=v1, disp=24, kind=I64 } -> x1 + v53 Binop { op=add, lhs=v40, rhs=v52 } -> x0 + v54 Imm(0) -> x1 + v55 Imm(3) -> x1 + v56 Imm(4) -> x1 + v57 Imm(0) -> x1 + v58 Imm(4) -> x1 + v59 Imm(1) -> x1 + v60 LoadLocal { off=-2, kind=I64 } -> x1 + v61 LoadLocal { off=2, kind=I64 } -> x1 + v62 Imm(4) -> x1 + v63 Imm(32) -> x1 + v64 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x1 + v65 Load { addr=v1, disp=32, kind=I64 } -> x1 + v66 Binop { op=add, lhs=v53, rhs=v65 } -> x0 + v67 Imm(0) -> x1 + v68 Imm(4) -> x1 + v69 Imm(5) -> x1 + v70 Imm(0) -> x1 + v71 Imm(5) -> x1 + v72 Imm(1) -> x1 + v73 LoadLocal { off=-2, kind=I64 } -> x1 + v74 LoadLocal { off=2, kind=I64 } -> x1 + v75 Imm(5) -> x1 + v76 Imm(40) -> x1 + v77 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v78 Load { addr=v1, disp=40, kind=I64 } -> x1 + v79 Binop { op=add, lhs=v66, rhs=v78 } -> x0 + v80 Imm(0) -> x1 + v81 Imm(5) -> x1 + v82 Imm(6) -> x1 + v83 Imm(0) -> x1 + v84 Imm(6) -> x1 + v85 Imm(1) -> x1 + v86 LoadLocal { off=-2, kind=I64 } -> x1 + v87 LoadLocal { off=2, kind=I64 } -> x1 + v88 Imm(6) -> x1 + v89 Imm(48) -> x1 + v90 BinopI { op=add, lhs=v1, rhs_imm=48 } -> x1 + v91 Load { addr=v1, disp=48, kind=I64 } -> x1 + v92 Binop { op=add, lhs=v79, rhs=v91 } -> x0 + v93 Imm(0) -> x1 + v94 Imm(6) -> x1 + v95 Imm(7) -> x1 + v96 Imm(0) -> x1 + v97 Imm(7) -> x1 + v98 Imm(1) -> x1 + v99 LoadLocal { off=-2, kind=I64 } -> x1 + v100 LoadLocal { off=2, kind=I64 } -> x1 + v101 Imm(7) -> x1 + v102 Imm(56) -> x1 + v103 BinopI { op=add, lhs=v1, rhs_imm=56 } -> x1 + v104 Load { addr=v1, disp=56, kind=I64 } -> x1 + v105 Binop { op=add, lhs=v92, rhs=v104 } -> x0 + v106 Imm(0) -> x1 + v107 Imm(7) -> x1 + v108 Imm(8) -> x1 + v109 Imm(0) -> x1 + v110 Imm(8) -> x1 + v111 Imm(1) -> x1 + v112 LoadLocal { off=-2, kind=I64 } -> x1 + v113 LoadLocal { off=2, kind=I64 } -> x1 + v114 Imm(8) -> x1 + v115 Imm(64) -> x1 + v116 BinopI { op=add, lhs=v1, rhs_imm=64 } -> x1 + v117 Load { addr=v1, disp=64, kind=I64 } -> x1 + v118 Binop { op=add, lhs=v105, rhs=v117 } -> x0 + v119 Imm(0) -> x1 + v120 Imm(8) -> x1 + v121 Imm(9) -> x1 + v122 Imm(0) -> x1 + v123 Imm(9) -> x1 + v124 Imm(1) -> x1 + v125 LoadLocal { off=-2, kind=I64 } -> x1 + v126 LoadLocal { off=2, kind=I64 } -> x1 + v127 Imm(9) -> x1 + v128 Imm(72) -> x1 + v129 BinopI { op=add, lhs=v1, rhs_imm=72 } -> x1 + v130 Load { addr=v1, disp=72, kind=I64 } -> x1 + v131 Binop { op=add, lhs=v118, rhs=v130 } -> x0 + v132 Imm(0) -> x1 + v133 Imm(9) -> x1 + v134 Imm(10) -> x1 + v135 Imm(0) -> x1 + v136 Imm(10) -> x1 + v137 Imm(1) -> x1 + v138 LoadLocal { off=-2, kind=I64 } -> x1 + v139 LoadLocal { off=2, kind=I64 } -> x1 + v140 Imm(10) -> x1 + v141 Imm(80) -> x1 + v142 BinopI { op=add, lhs=v1, rhs_imm=80 } -> x1 + v143 Load { addr=v1, disp=80, kind=I64 } -> x1 + v144 Binop { op=add, lhs=v131, rhs=v143 } -> x0 + v145 Imm(0) -> x1 + v146 Imm(10) -> x1 + v147 Imm(11) -> x1 + v148 Imm(0) -> x1 + v149 Imm(11) -> x1 + v150 Imm(1) -> x1 + v151 LoadLocal { off=-2, kind=I64 } -> x1 + v152 LoadLocal { off=2, kind=I64 } -> x1 + v153 Imm(11) -> x1 + v154 Imm(88) -> x1 + v155 BinopI { op=add, lhs=v1, rhs_imm=88 } -> x1 + v156 Load { addr=v1, disp=88, kind=I64 } -> x1 + v157 Binop { op=add, lhs=v144, rhs=v156 } -> x0 + v158 Imm(0) -> x1 + v159 Imm(11) -> x1 + v160 Imm(12) -> x1 + v161 Imm(0) -> x1 + v162 Imm(12) -> x1 + v163 Imm(1) -> x1 + v164 LoadLocal { off=-2, kind=I64 } -> x1 + v165 LoadLocal { off=2, kind=I64 } -> x1 + v166 Imm(12) -> x1 + v167 Imm(96) -> x1 + v168 BinopI { op=add, lhs=v1, rhs_imm=96 } -> x1 + v169 Load { addr=v1, disp=96, kind=I64 } -> x1 + v170 Binop { op=add, lhs=v157, rhs=v169 } -> x0 + v171 Imm(0) -> x1 + v172 Imm(12) -> x1 + v173 Imm(13) -> x1 + v174 Imm(0) -> x1 + v175 Imm(13) -> x1 + v176 Imm(1) -> x1 + v177 LoadLocal { off=-2, kind=I64 } -> x1 + v178 LoadLocal { off=2, kind=I64 } -> x1 + v179 Imm(13) -> x1 + v180 Imm(104) -> x1 + v181 BinopI { op=add, lhs=v1, rhs_imm=104 } -> x1 + v182 Load { addr=v1, disp=104, kind=I64 } -> x1 + v183 Binop { op=add, lhs=v170, rhs=v182 } -> x0 + v184 Imm(0) -> x1 + v185 Imm(13) -> x1 + v186 Imm(14) -> x1 + v187 Imm(0) -> x1 + v188 Imm(14) -> x1 + v189 Imm(1) -> x1 + v190 LoadLocal { off=-2, kind=I64 } -> x1 + v191 LoadLocal { off=2, kind=I64 } -> x1 + v192 Imm(14) -> x1 + v193 Imm(112) -> x1 + v194 BinopI { op=add, lhs=v1, rhs_imm=112 } -> x1 + v195 Load { addr=v1, disp=112, kind=I64 } -> x1 + v196 Binop { op=add, lhs=v183, rhs=v195 } -> x0 + v197 Imm(0) -> x1 + v198 Imm(14) -> x1 + v199 Imm(15) -> x1 + v200 Imm(0) -> x1 + v201 Imm(15) -> x1 + v202 Imm(1) -> x1 + v203 LoadLocal { off=-2, kind=I64 } -> x1 + v204 LoadLocal { off=2, kind=I64 } -> x1 + v205 Imm(15) -> x1 + v206 Imm(120) -> x1 + v207 BinopI { op=add, lhs=v1, rhs_imm=120 } -> x1 + v208 Load { addr=v1, disp=120, kind=I64 } -> x1 + v209 Binop { op=add, lhs=v196, rhs=v208 } -> x0 + v210 Imm(0) -> x1 + v211 Imm(15) -> x1 + v212 Imm(16) -> x1 + v213 Imm(0) -> x1 + v214 Imm(16) -> x1 + v215 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v215) block 2 start_pc=0 - v10 Extend { value=v7, kind=I32 } -> x0 - v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x0 - v12 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 - v13 LoadLocal { off=-2, kind=I64 } -> x2 - v14 LoadLocal { off=2, kind=I64 } -> x2 - v15 Extend { value=v7, kind=I32 } -> x2 - v16 BinopI { op=shl, lhs=v15, rhs_imm=3 } -> x6 - v17 Binop { op=add, lhs=v1, rhs=v16 } -> x6 - v18 LoadIndexed { base=v1, index=v15, scale=8, kind=I64 } -> x2 - v19 Binop { op=add, lhs=v6, rhs=v18 } -> x1 - v20 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v19) - block 4 start_pc=0 - v21 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Return(v6) (exit_acc=v6) + v216 LoadLocal { off=-2, kind=I64 } -> x1 + terminator Return(v209) (exit_acc=v209) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=35 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 Imm(0) -> x0 + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 - v4 Extend { value=v3, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=16 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) + v3 Imm(0) -> x0 + v4 Imm(1) -> x0 + v5 LocalAddr(-16) -> x0 + v6 Imm(0) -> x1 + v7 Imm(0) -> x1 + v8 BinopI { op=add, lhs=v5, rhs_imm=0 } -> x0 + v9 Imm(1) -> x1 + v10 Store { addr=v8, disp=0, value=v9, kind=I64 } -> - + v11 Imm(0) -> x0 + v12 Imm(1) -> x0 + v13 Imm(0) -> x0 + v14 Imm(1) -> x0 + v15 Imm(1) -> x0 + v16 LocalAddr(-16) -> x0 + v17 Imm(1) -> x1 + v18 Imm(8) -> x1 + v19 BinopI { op=add, lhs=v16, rhs_imm=8 } -> x1 + v20 Imm(2) -> x1 + v21 Store { addr=v16, disp=8, value=v20, kind=I64 } -> - + v22 Imm(1) -> x0 + v23 Imm(2) -> x0 + v24 Imm(0) -> x0 + v25 Imm(2) -> x0 + v26 Imm(1) -> x0 + v27 LocalAddr(-16) -> x0 + v28 Imm(2) -> x1 + v29 Imm(16) -> x1 + v30 BinopI { op=add, lhs=v27, rhs_imm=16 } -> x1 + v31 Imm(3) -> x1 + v32 Store { addr=v27, disp=16, value=v31, kind=I64 } -> - + v33 Imm(2) -> x0 + v34 Imm(3) -> x0 + v35 Imm(0) -> x0 + v36 Imm(3) -> x0 + v37 Imm(1) -> x0 + v38 LocalAddr(-16) -> x0 + v39 Imm(3) -> x1 + v40 Imm(24) -> x1 + v41 BinopI { op=add, lhs=v38, rhs_imm=24 } -> x1 + v42 Imm(4) -> x1 + v43 Store { addr=v38, disp=24, value=v42, kind=I64 } -> - + v44 Imm(3) -> x0 + v45 Imm(4) -> x0 + v46 Imm(0) -> x0 + v47 Imm(4) -> x0 + v48 Imm(1) -> x0 + v49 LocalAddr(-16) -> x0 + v50 Imm(4) -> x1 + v51 Imm(32) -> x1 + v52 BinopI { op=add, lhs=v49, rhs_imm=32 } -> x1 + v53 Imm(5) -> x1 + v54 Store { addr=v49, disp=32, value=v53, kind=I64 } -> - + v55 Imm(4) -> x0 + v56 Imm(5) -> x0 + v57 Imm(0) -> x0 + v58 Imm(5) -> x0 + v59 Imm(1) -> x0 + v60 LocalAddr(-16) -> x0 + v61 Imm(5) -> x1 + v62 Imm(40) -> x1 + v63 BinopI { op=add, lhs=v60, rhs_imm=40 } -> x1 + v64 Imm(6) -> x1 + v65 Store { addr=v60, disp=40, value=v64, kind=I64 } -> - + v66 Imm(5) -> x0 + v67 Imm(6) -> x0 + v68 Imm(0) -> x0 + v69 Imm(6) -> x0 + v70 Imm(1) -> x0 + v71 LocalAddr(-16) -> x0 + v72 Imm(6) -> x1 + v73 Imm(48) -> x1 + v74 BinopI { op=add, lhs=v71, rhs_imm=48 } -> x1 + v75 Imm(7) -> x1 + v76 Store { addr=v71, disp=48, value=v75, kind=I64 } -> - + v77 Imm(6) -> x0 + v78 Imm(7) -> x0 + v79 Imm(0) -> x0 + v80 Imm(7) -> x0 + v81 Imm(1) -> x0 + v82 LocalAddr(-16) -> x0 + v83 Imm(7) -> x1 + v84 Imm(56) -> x1 + v85 BinopI { op=add, lhs=v82, rhs_imm=56 } -> x1 + v86 Imm(8) -> x1 + v87 Store { addr=v82, disp=56, value=v86, kind=I64 } -> - + v88 Imm(7) -> x0 + v89 Imm(8) -> x0 + v90 Imm(0) -> x0 + v91 Imm(8) -> x0 + v92 Imm(1) -> x0 + v93 LocalAddr(-16) -> x0 + v94 Imm(8) -> x1 + v95 Imm(64) -> x1 + v96 BinopI { op=add, lhs=v93, rhs_imm=64 } -> x1 + v97 Imm(9) -> x1 + v98 Store { addr=v93, disp=64, value=v97, kind=I64 } -> - + v99 Imm(8) -> x0 + v100 Imm(9) -> x0 + v101 Imm(0) -> x0 + v102 Imm(9) -> x0 + v103 Imm(1) -> x0 + v104 LocalAddr(-16) -> x0 + v105 Imm(9) -> x1 + v106 Imm(72) -> x1 + v107 BinopI { op=add, lhs=v104, rhs_imm=72 } -> x1 + v108 Imm(10) -> x1 + v109 Store { addr=v104, disp=72, value=v108, kind=I64 } -> - + v110 Imm(9) -> x0 + v111 Imm(10) -> x0 + v112 Imm(0) -> x0 + v113 Imm(10) -> x0 + v114 Imm(1) -> x0 + v115 LocalAddr(-16) -> x0 + v116 Imm(10) -> x1 + v117 Imm(80) -> x1 + v118 BinopI { op=add, lhs=v115, rhs_imm=80 } -> x1 + v119 Imm(11) -> x1 + v120 Store { addr=v115, disp=80, value=v119, kind=I64 } -> - + v121 Imm(10) -> x0 + v122 Imm(11) -> x0 + v123 Imm(0) -> x0 + v124 Imm(11) -> x0 + v125 Imm(1) -> x0 + v126 LocalAddr(-16) -> x0 + v127 Imm(11) -> x1 + v128 Imm(88) -> x1 + v129 BinopI { op=add, lhs=v126, rhs_imm=88 } -> x1 + v130 Imm(12) -> x1 + v131 Store { addr=v126, disp=88, value=v130, kind=I64 } -> - + v132 Imm(11) -> x0 + v133 Imm(12) -> x0 + v134 Imm(0) -> x0 + v135 Imm(12) -> x0 + v136 Imm(1) -> x0 + v137 LocalAddr(-16) -> x0 + v138 Imm(12) -> x1 + v139 Imm(96) -> x1 + v140 BinopI { op=add, lhs=v137, rhs_imm=96 } -> x1 + v141 Imm(13) -> x1 + v142 Store { addr=v137, disp=96, value=v141, kind=I64 } -> - + v143 Imm(12) -> x0 + v144 Imm(13) -> x0 + v145 Imm(0) -> x0 + v146 Imm(13) -> x0 + v147 Imm(1) -> x0 + v148 LocalAddr(-16) -> x0 + v149 Imm(13) -> x1 + v150 Imm(104) -> x1 + v151 BinopI { op=add, lhs=v148, rhs_imm=104 } -> x1 + v152 Imm(14) -> x1 + v153 Store { addr=v148, disp=104, value=v152, kind=I64 } -> - + v154 Imm(13) -> x0 + v155 Imm(14) -> x0 + v156 Imm(0) -> x0 + v157 Imm(14) -> x0 + v158 Imm(1) -> x0 + v159 LocalAddr(-16) -> x0 + v160 Imm(14) -> x1 + v161 Imm(112) -> x1 + v162 BinopI { op=add, lhs=v159, rhs_imm=112 } -> x1 + v163 Imm(15) -> x1 + v164 Store { addr=v159, disp=112, value=v163, kind=I64 } -> - + v165 Imm(14) -> x0 + v166 Imm(15) -> x0 + v167 Imm(0) -> x0 + v168 Imm(15) -> x0 + v169 Imm(1) -> x0 + v170 LocalAddr(-16) -> x0 + v171 Imm(15) -> x1 + v172 Imm(120) -> x1 + v173 BinopI { op=add, lhs=v170, rhs_imm=120 } -> x1 + v174 Imm(16) -> x1 + v175 Store { addr=v170, disp=120, value=v174, kind=I64 } -> - + v176 Imm(15) -> x0 + v177 Imm(16) -> x0 + v178 Imm(0) -> x0 + v179 Imm(16) -> x0 + v180 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v180) block 2 start_pc=0 - v6 Extend { value=v3, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + v181 LocalAddr(-32) -> x7 + v182 LocalAddr(-16) -> x6 + v183 Call { target_pc=0, args=[v181, v182], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v184 LocalAddr(-32) -> x7 + v185 Call { target_pc=1, args=[v184], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v186 Imm(272) -> x1 + v187 Imm(1168231104512) -> x1 + v188 Imm(2) -> x1 + v189 Imm(0) -> x1 + v190 Imm(272) -> x1 + v191 Imm(136) -> x1 + v192 BinopI { op=ne, lhs=v185, rhs_imm=136 } -> x0 + terminator Bz { cond=v192, target=b4, fall=b3 } (exit_acc=v192) block 3 start_pc=0 - v9 LocalAddr(-16) -> x0 - v10 Extend { value=v3, kind=I32 } -> x2 - v11 BinopI { op=shl, lhs=v10, rhs_imm=3 } -> x6 - v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 - v13 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x6 - v14 StoreIndexed { base=v9, index=v10, scale=8, value=v13, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v14) + v193 Imm(1) -> x0 + terminator Return(v193) (exit_acc=v193) block 4 start_pc=0 - v15 LocalAddr(-32) -> x7 - v16 LocalAddr(-16) -> x6 - v17 Call { target_pc=0, args=[v15, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 - v18 LocalAddr(-32) -> x7 - v19 Call { target_pc=1, args=[v18], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v20 Imm(272) -> x1 - v21 Imm(1168231104512) -> x2 - v22 Imm(2) -> x2 - v23 Imm(0) -> x2 - v24 Binop { op=add, lhs=v20, rhs=v23 } -> x1 - v25 BinopI { op=shr, lhs=v24, rhs_imm=1 } -> x1 - v26 Binop { op=ne, lhs=v19, rhs=v25 } -> x0 - terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) + v194 LocalAddr(-32) -> x0 + v195 Imm(0) -> x1 + v196 Load { addr=v194, disp=0, kind=I64 } -> x0 + v197 BinopI { op=ne, lhs=v196, rhs_imm=1 } -> x0 + terminator Bz { cond=v197, target=b6, fall=b5 } (exit_acc=v197) block 5 start_pc=0 - v27 Imm(1) -> x0 - terminator Return(v27) (exit_acc=v27) + v198 Imm(2) -> x0 + terminator Return(v198) (exit_acc=v198) block 6 start_pc=0 - v28 LocalAddr(-32) -> x0 - v29 Imm(0) -> x1 - v30 Load { addr=v28, disp=0, kind=I64 } -> x0 - v31 BinopI { op=ne, lhs=v30, rhs_imm=1 } -> x0 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) + v199 LocalAddr(-32) -> x0 + v200 Imm(120) -> x1 + v201 BinopI { op=add, lhs=v199, rhs_imm=120 } -> x1 + v202 Load { addr=v199, disp=120, kind=I64 } -> x0 + v203 BinopI { op=ne, lhs=v202, rhs_imm=16 } -> x0 + terminator Bz { cond=v203, target=b8, fall=b7 } (exit_acc=v203) block 7 start_pc=0 - v32 Imm(2) -> x0 - terminator Return(v32) (exit_acc=v32) + v204 Imm(3) -> x0 + terminator Return(v204) (exit_acc=v204) block 8 start_pc=0 - v33 LocalAddr(-32) -> x0 - v34 Imm(120) -> x1 - v35 BinopI { op=add, lhs=v33, rhs_imm=120 } -> x1 - v36 Load { addr=v33, disp=120, kind=I64 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=16 } -> x0 - terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) - block 9 start_pc=0 - v38 Imm(3) -> x0 - terminator Return(v38) (exit_acc=v38) - block 10 start_pc=0 - v39 Imm(0) -> x0 - terminator Return(v39) (exit_acc=v39) + v205 Imm(0) -> x0 + terminator Return(v205) (exit_acc=v205) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_basic.ssa b/tests/snapshots/ssa/typedef_basic.ssa index 3d344480c..19416a420 100644 --- a/tests/snapshots/ssa/typedef_basic.ssa +++ b/tests/snapshots/ssa/typedef_basic.ssa @@ -21,132 +21,132 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(100) -> x0 - v2 Imm(0) -> x1 - v3 Imm(65) -> x1 - v4 Imm(0) -> x2 - v5 Imm(1234567890) -> x2 - v6 Imm(0) -> x6 - v7 ImmData(8) -> x6 - v8 Imm(0) -> x7 - v9 LocalAddr(-6) -> x7 - v10 Imm(7) -> x8 + v2 Imm(0) -> x0 + v3 Imm(65) -> x0 + v4 Imm(0) -> x0 + v5 Imm(1234567890) -> x0 + v6 Imm(0) -> x0 + v7 ImmData(8) -> x0 + v8 Imm(0) -> x1 + v9 LocalAddr(-6) -> x1 + v10 Imm(7) -> x2 v11 Store { addr=v9, disp=0, value=v10, kind=I32 } -> - - v12 LocalAddr(-6) -> x7 - v13 BinopI { op=add, lhs=v12, rhs_imm=8 } -> x8 - v14 Imm(0) -> x8 + v12 LocalAddr(-6) -> x1 + v13 BinopI { op=add, lhs=v12, rhs_imm=8 } -> x2 + v14 Imm(0) -> x2 v15 Store { addr=v12, disp=8, value=v14, kind=I64 } -> - - v16 LocalAddr(-7) -> x7 - v17 Imm(11) -> x8 + v16 LocalAddr(-7) -> x1 + v17 Imm(11) -> x2 v18 Store { addr=v16, disp=0, value=v17, kind=I32 } -> - - v19 LocalAddr(-7) -> x7 - v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x8 - v21 Imm(22) -> x8 + v19 LocalAddr(-7) -> x1 + v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x2 + v21 Imm(22) -> x2 v22 Store { addr=v19, disp=4, value=v21, kind=I32 } -> - - v23 LocalAddr(-9) -> x7 - v24 Imm(1) -> x8 + v23 LocalAddr(-9) -> x1 + v24 Imm(1) -> x2 v25 Store { addr=v23, disp=0, value=v24, kind=I32 } -> - - v26 LocalAddr(-9) -> x7 - v27 BinopI { op=add, lhs=v26, rhs_imm=4 } -> x8 - v28 Imm(2) -> x8 + v26 LocalAddr(-9) -> x1 + v27 BinopI { op=add, lhs=v26, rhs_imm=4 } -> x2 + v28 Imm(2) -> x2 v29 Store { addr=v26, disp=4, value=v28, kind=I32 } -> - - v30 LocalAddr(-9) -> x7 - v31 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x8 - v32 Imm(3) -> x8 + v30 LocalAddr(-9) -> x1 + v31 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x2 + v32 Imm(3) -> x2 v33 Store { addr=v30, disp=8, value=v32, kind=I32 } -> - - v34 LoadLocal { off=-1, kind=I32 } -> x7 - v35 LoadLocal { off=-2, kind=U8 } -> x7 - v36 Extend { value=v1, kind=I32 } -> x7 - v37 Imm(0) -> x7 - v38 Extend { value=v3, kind=I32 } -> x7 - v39 Imm(0) -> x7 - v40 Binop { op=add, lhs=v1, rhs=v3 } -> x0 - v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x7 - v42 Extend { value=v40, kind=I32 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=165 } -> x0 - terminator Bz { cond=v43, target=b2, fall=b1 } (exit_acc=v43) + v34 LoadLocal { off=-1, kind=I32 } -> x1 + v35 LoadLocal { off=-2, kind=U8 } -> x1 + v36 Imm(100) -> x1 + v37 Imm(0) -> x1 + v38 Imm(65) -> x1 + v39 Imm(0) -> x1 + v40 Imm(165) -> x1 + v41 Imm(708669603840) -> x1 + v42 Imm(165) -> x1 + v43 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v43) block 1 start_pc=0 - v44 Imm(1) -> x0 - terminator Return(v44) (exit_acc=v44) - block 2 start_pc=0 - v45 LoadLocal { off=-4, kind=I64 } -> x0 - v46 Imm(0) -> x0 + v45 LoadLocal { off=-4, kind=I64 } -> x1 + v46 Imm(0) -> x1 v47 Load { addr=v7, disp=0, kind=I8 } -> x0 v48 BinopI { op=ne, lhs=v47, rhs_imm=104 } -> x0 - terminator Bz { cond=v48, target=b4, fall=b3 } (exit_acc=v48) - block 3 start_pc=0 + terminator Bz { cond=v48, target=b3, fall=b2 } (exit_acc=v48) + block 2 start_pc=0 v49 Imm(2) -> x0 terminator Return(v49) (exit_acc=v49) - block 4 start_pc=0 + block 3 start_pc=0 v50 LocalAddr(-6) -> x0 v51 Load { addr=v50, disp=0, kind=I32 } -> x0 v52 BinopI { op=ne, lhs=v51, rhs_imm=7 } -> x0 - terminator Bz { cond=v52, target=b6, fall=b5 } (exit_acc=v52) - block 5 start_pc=0 + terminator Bz { cond=v52, target=b5, fall=b4 } (exit_acc=v52) + block 4 start_pc=0 v53 Imm(3) -> x0 terminator Return(v53) (exit_acc=v53) - block 6 start_pc=0 + block 5 start_pc=0 v54 LocalAddr(-7) -> x0 v55 Load { addr=v54, disp=0, kind=I32 } -> x0 - v56 LocalAddr(-7) -> x6 - v57 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x7 - v58 Load { addr=v56, disp=4, kind=I32 } -> x6 + v56 LocalAddr(-7) -> x1 + v57 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x2 + v58 Load { addr=v56, disp=4, kind=I32 } -> x1 v59 Binop { op=add, lhs=v55, rhs=v58 } -> x0 - v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x6 + v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x1 v61 Extend { value=v59, kind=I32 } -> x0 v62 BinopI { op=ne, lhs=v61, rhs_imm=33 } -> x0 - terminator Bz { cond=v62, target=b8, fall=b7 } (exit_acc=v62) - block 7 start_pc=0 + terminator Bz { cond=v62, target=b7, fall=b6 } (exit_acc=v62) + block 6 start_pc=0 v63 Imm(4) -> x0 terminator Return(v63) (exit_acc=v63) - block 8 start_pc=0 + block 7 start_pc=0 v64 LocalAddr(-9) -> x0 v65 Load { addr=v64, disp=0, kind=I32 } -> x0 - v66 LocalAddr(-9) -> x6 - v67 BinopI { op=add, lhs=v66, rhs_imm=4 } -> x7 - v68 Load { addr=v66, disp=4, kind=I32 } -> x6 + v66 LocalAddr(-9) -> x1 + v67 BinopI { op=add, lhs=v66, rhs_imm=4 } -> x2 + v68 Load { addr=v66, disp=4, kind=I32 } -> x1 v69 Binop { op=add, lhs=v65, rhs=v68 } -> x0 - v70 BinopI { op=shl, lhs=v69, rhs_imm=32 } -> x6 - v71 Extend { value=v69, kind=I32 } -> x6 - v72 LocalAddr(-9) -> x6 - v73 BinopI { op=add, lhs=v72, rhs_imm=8 } -> x7 - v74 Load { addr=v72, disp=8, kind=I32 } -> x6 + v70 BinopI { op=shl, lhs=v69, rhs_imm=32 } -> x1 + v71 Extend { value=v69, kind=I32 } -> x1 + v72 LocalAddr(-9) -> x1 + v73 BinopI { op=add, lhs=v72, rhs_imm=8 } -> x2 + v74 Load { addr=v72, disp=8, kind=I32 } -> x1 v75 Binop { op=add, lhs=v69, rhs=v74 } -> x0 - v76 BinopI { op=shl, lhs=v75, rhs_imm=32 } -> x6 + v76 BinopI { op=shl, lhs=v75, rhs_imm=32 } -> x1 v77 Extend { value=v75, kind=I32 } -> x0 v78 BinopI { op=ne, lhs=v77, rhs_imm=6 } -> x0 - terminator Bz { cond=v78, target=b10, fall=b9 } (exit_acc=v78) - block 9 start_pc=0 + terminator Bz { cond=v78, target=b9, fall=b8 } (exit_acc=v78) + block 8 start_pc=0 v79 Imm(5) -> x0 terminator Return(v79) (exit_acc=v79) - block 10 start_pc=0 + block 9 start_pc=0 v80 LoadLocal { off=-3, kind=I64 } -> x0 - v81 BinopI { op=ne, lhs=v5, rhs_imm=1234567890 } -> x0 - terminator Bz { cond=v81, target=b12, fall=b11 } (exit_acc=v81) + v81 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v81) + block 10 start_pc=0 + v83 LoadLocal { off=-2, kind=U8 } -> x0 + v84 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v84) block 11 start_pc=0 - v82 Imm(6) -> x0 - terminator Return(v82) (exit_acc=v82) + v86 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v86) block 12 start_pc=0 - v83 LoadLocal { off=-2, kind=U8 } -> x0 - v84 BinopI { op=ne, lhs=v3, rhs_imm=65 } -> x0 - terminator Bz { cond=v84, target=b14, fall=b13 } (exit_acc=v84) + v88 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v88) block 13 start_pc=0 - v85 Imm(7) -> x0 - terminator Return(v85) (exit_acc=v85) + v90 Imm(0) -> x0 + terminator Return(v90) (exit_acc=v90) block 14 start_pc=0 - v86 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v86) + v44 Imm(1) -> x0 + terminator Return(v44) (exit_acc=v44) block 15 start_pc=0 - v87 Imm(8) -> x0 - terminator Return(v87) (exit_acc=v87) + v82 Imm(6) -> x0 + terminator Return(v82) (exit_acc=v82) block 16 start_pc=0 - v88 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v88) + v85 Imm(7) -> x0 + terminator Return(v85) (exit_acc=v85) block 17 start_pc=0 + v87 Imm(8) -> x0 + terminator Return(v87) (exit_acc=v87) + block 18 start_pc=0 v89 Imm(9) -> x0 terminator Return(v89) (exit_acc=v89) - block 18 start_pc=0 - v90 Imm(0) -> x0 - terminator Return(v90) (exit_acc=v90) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_in_function_body.ssa b/tests/snapshots/ssa/typedef_in_function_body.ssa index 76a0d6261..e144c46a6 100644 --- a/tests/snapshots/ssa/typedef_in_function_body.ssa +++ b/tests/snapshots/ssa/typedef_in_function_body.ssa @@ -5,10 +5,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 BinopI { op=shl, lhs=v1, rhs_imm=32 } -> x1 - v5 Extend { value=v1, kind=I32 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(30064771072) -> x0 + v5 Imm(7) -> x0 terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=k @@ -27,56 +27,56 @@ fn ent_pc=2 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x0 - v2 Imm(0) -> x1 - v3 Imm(1) -> x1 - v4 Imm(0) -> x2 - v5 Imm(0) -> x2 - v6 Imm(7) -> x2 - v7 Imm(0) -> x6 - v8 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x6 - v9 Extend { value=v6, kind=I32 } -> x2 - v10 BinopI { op=ne, lhs=v9, rhs_imm=7 } -> x2 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 Imm(0) -> x0 + v5 Imm(0) -> x0 + v6 Imm(7) -> x0 + v7 Imm(0) -> x0 + v8 Imm(30064771072) -> x0 + v9 Imm(7) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) + v12 Imm(5) -> x0 + v13 Imm(0) -> x0 + v14 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v14) block 2 start_pc=0 - v12 Imm(5) -> x2 - v13 Imm(0) -> x6 - v14 BinopI { op=ne, lhs=v12, rhs_imm=5 } -> x2 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v16 ImmData(8) -> x0 + v17 Load { addr=v16, disp=0, kind=I32 } -> x0 + v18 BinopI { op=ne, lhs=v17, rhs_imm=100 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) - block 4 start_pc=0 - v16 ImmData(8) -> x2 - v17 Load { addr=v16, disp=0, kind=I32 } -> x2 - v18 BinopI { op=ne, lhs=v17, rhs_imm=100 } -> x2 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) - block 5 start_pc=0 v19 Imm(3) -> x0 terminator Return(v19) (exit_acc=v19) + block 4 start_pc=0 + v20 LoadLocal { off=-1, kind=I32 } -> x0 + v21 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v21) + block 5 start_pc=0 + v23 LoadLocal { off=-1, kind=I32 } -> x0 + v24 LoadLocal { off=-2, kind=I32 } -> x0 + v25 Imm(3) -> x0 + v26 Imm(12884901888) -> x0 + v27 Imm(3) -> x0 + v28 LoadLocal { off=-3, kind=I32 } -> x0 + v29 Imm(5) -> x0 + v30 Imm(21474836480) -> x0 + v31 Imm(5) -> x0 + v32 Imm(0) -> x0 + v33 Imm(0) -> x0 + v34 Imm(0) -> x0 + terminator Return(v34) (exit_acc=v34) block 6 start_pc=0 - v20 LoadLocal { off=-1, kind=I32 } -> x2 - v21 BinopI { op=ne, lhs=v1, rhs_imm=2 } -> x2 - terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 7 start_pc=0 + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) + block 8 start_pc=0 v22 Imm(4) -> x0 terminator Return(v22) (exit_acc=v22) - block 8 start_pc=0 - v23 LoadLocal { off=-1, kind=I32 } -> x2 - v24 LoadLocal { off=-2, kind=I32 } -> x2 - v25 Binop { op=add, lhs=v1, rhs=v3 } -> x1 - v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x2 - v27 Extend { value=v25, kind=I32 } -> x2 - v28 LoadLocal { off=-3, kind=I32 } -> x2 - v29 Binop { op=add, lhs=v25, rhs=v1 } -> x0 - v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x1 - v31 Extend { value=v29, kind=I32 } -> x1 - v32 BinopI { op=sub, lhs=v29, rhs_imm=5 } -> x0 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 - v34 Extend { value=v32, kind=I32 } -> x0 - terminator Return(v34) (exit_acc=v34) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_name_as_declarator.ssa b/tests/snapshots/ssa/typedef_name_as_declarator.ssa index 2b7fdc1a5..a09759c27 100644 --- a/tests/snapshots/ssa/typedef_name_as_declarator.ssa +++ b/tests/snapshots/ssa/typedef_name_as_declarator.ssa @@ -24,50 +24,50 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v6 Imm(5) -> x1 v7 Store { addr=v4, disp=8, value=v6, kind=I64 } -> - v8 Imm(3) -> x0 - v9 Imm(0) -> x1 - v10 Imm(0) -> x1 - terminator Jmp(b2) (exit_acc=v10) + v9 Imm(0) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(11) -> x0 - terminator Return(v11) (exit_acc=v11) + v12 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v12 Imm(0) -> x1 - terminator Jmp(b4) (exit_acc=v12) + v14 LocalAddr(-2) -> x0 + v15 Load { addr=v14, disp=0, kind=U16 } -> x0 + v16 BinopI { op=xor, lhs=v15, rhs_imm=40000 } -> x0 + v17 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x0 + v18 BinopI { op=ne, lhs=v17, rhs_imm=0 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v13 Imm(12) -> x0 - terminator Return(v13) (exit_acc=v13) - block 4 start_pc=0 - v14 LocalAddr(-2) -> x1 - v15 Load { addr=v14, disp=0, kind=U16 } -> x1 - v16 BinopI { op=xor, lhs=v15, rhs_imm=40000 } -> x1 - v17 BinopI { op=and, lhs=v16, rhs_imm=4294967295 } -> x1 - v18 BinopI { op=ne, lhs=v17, rhs_imm=0 } -> x1 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) - block 5 start_pc=0 v19 Imm(13) -> x0 terminator Return(v19) (exit_acc=v19) + block 4 start_pc=0 + v20 LoadLocal { off=-3, kind=U16 } -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v23) + block 5 start_pc=0 + v25 Imm(7) -> x0 + v26 Imm(0) -> x0 + v27 Imm(30064771072) -> x0 + v28 Imm(7) -> x0 + v29 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v29) block 6 start_pc=0 - v20 LoadLocal { off=-3, kind=U16 } -> x1 - v21 BinopI { op=xor, lhs=v8, rhs_imm=3 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b8, fall=b7 } (exit_acc=v23) + v31 Imm(0) -> x0 + terminator Return(v31) (exit_acc=v31) block 7 start_pc=0 - v24 Imm(14) -> x0 - terminator Return(v24) (exit_acc=v24) + v11 Imm(11) -> x0 + terminator Return(v11) (exit_acc=v11) block 8 start_pc=0 - v25 Imm(7) -> x0 - v26 Imm(0) -> x1 - v27 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x1 - v28 Extend { value=v25, kind=I32 } -> x0 - v29 BinopI { op=ne, lhs=v28, rhs_imm=7 } -> x0 - terminator Bz { cond=v29, target=b10, fall=b9 } (exit_acc=v29) + v13 Imm(12) -> x0 + terminator Return(v13) (exit_acc=v13) block 9 start_pc=0 + v24 Imm(14) -> x0 + terminator Return(v24) (exit_acc=v24) + block 10 start_pc=0 v30 Imm(15) -> x0 terminator Return(v30) (exit_acc=v30) - block 10 start_pc=0 - v31 Imm(0) -> x0 - terminator Return(v31) (exit_acc=v31) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_shadowed_by_parameter_name.ssa b/tests/snapshots/ssa/typedef_shadowed_by_parameter_name.ssa index 0a6c227ac..fb144063a 100644 --- a/tests/snapshots/ssa/typedef_shadowed_by_parameter_name.ssa +++ b/tests/snapshots/ssa/typedef_shadowed_by_parameter_name.ssa @@ -8,29 +8,29 @@ fn ent_pc=0 n_params=0 variadic=false locals=128 v1 Imm(512) -> x0 v2 Imm(2199023255552) -> x0 v3 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v3) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v4 Imm(11) -> x0 - terminator Return(v4) (exit_acc=v4) - block 2 start_pc=0 v5 Imm(512) -> x0 v6 Imm(2199023255552) -> x0 v7 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v7) - block 3 start_pc=0 - v8 Imm(12) -> x0 - terminator Return(v8) (exit_acc=v8) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v7) + block 2 start_pc=0 v9 Imm(512) -> x0 v10 Imm(2199023255552) -> x0 v11 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v11) + terminator Jmp(b3) (exit_acc=v11) + block 3 start_pc=0 + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) + block 4 start_pc=0 + v4 Imm(11) -> x0 + terminator Return(v4) (exit_acc=v4) block 5 start_pc=0 + v8 Imm(12) -> x0 + terminator Return(v8) (exit_acc=v8) + block 6 start_pc=0 v12 Imm(13) -> x0 terminator Return(v12) (exit_acc=v12) - block 6 start_pc=0 - v13 Imm(0) -> x0 - terminator Return(v13) (exit_acc=v13) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/typedef_struct_carrier_reset.ssa b/tests/snapshots/ssa/typedef_struct_carrier_reset.ssa index 4fd33ee75..0b33da762 100644 --- a/tests/snapshots/ssa/typedef_struct_carrier_reset.ssa +++ b/tests/snapshots/ssa/typedef_struct_carrier_reset.ssa @@ -6,61 +6,363 @@ fn ent_pc=0 n_params=1 variadic=false locals=2 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I64) -> x7 v2 Imm(0) -> x0 - v3 Imm(0) -> x1 - v4 Imm(0) -> x0 - v5 Imm(0) -> x0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x1 + v5 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v6 Phi { incoming=[b0:v3, b2:v39], kind=I64 } -> x1 - v7 Phi { incoming=[b0:v3, b2:v11], kind=I64 } -> x0 - v8 Extend { value=v7, kind=I32 } -> x2 - v9 BinopI { op=lt, lhs=v8, rhs_imm=10 } -> x2 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 LoadLocal { off=2, kind=I64 } -> x0 + v9 Imm(0) -> x0 + v10 Imm(0) -> x1 + v11 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x1 + v12 Store { addr=v11, disp=0, value=v9, kind=I32 } -> - + v13 LoadLocal { off=2, kind=I64 } -> x0 + v14 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x0 + v15 Imm(0) -> x1 + v16 Imm(0) -> x1 + v17 BinopI { op=add, lhs=v14, rhs_imm=0 } -> x0 + v18 Imm(1) -> x1 + v19 Imm(4294967296) -> x1 + v20 Imm(1) -> x1 + v21 Store { addr=v17, disp=0, value=v20, kind=I32 } -> - + v22 Imm(0) -> x0 + v23 LoadLocal { off=2, kind=I64 } -> x0 + v24 Imm(0) -> x0 + v25 Imm(0) -> x0 + v26 BinopI { op=add, lhs=v1, rhs_imm=0 } -> x0 + v27 Load { addr=v26, disp=0, kind=I32 } -> x0 + v28 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v29 BinopI { op=add, lhs=v28, rhs_imm=0 } -> x1 + v30 Load { addr=v29, disp=0, kind=I32 } -> x1 + v31 Binop { op=add, lhs=v27, rhs=v30 } -> x0 + v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x1 + v33 Extend { value=v31, kind=I32 } -> x1 + v34 BinopI { op=add, lhs=v31, rhs_imm=0 } -> x0 + v35 Imm(0) -> x1 + v36 Extend { value=v34, kind=I32 } -> x1 + v37 Imm(0) -> x1 + v38 Imm(1) -> x1 + v39 Imm(0) -> x1 + v40 Imm(1) -> x1 + v41 Imm(1) -> x1 + v42 LoadLocal { off=2, kind=I64 } -> x1 + v43 Imm(1) -> x1 + v44 Imm(4) -> x2 + v45 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x2 + v46 Store { addr=v1, disp=4, value=v43, kind=I32 } -> - + v47 LoadLocal { off=2, kind=I64 } -> x1 + v48 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v49 Imm(1) -> x2 + v50 Imm(4) -> x2 + v51 BinopI { op=add, lhs=v48, rhs_imm=4 } -> x2 + v52 Imm(2) -> x2 + v53 Imm(8589934592) -> x2 + v54 Imm(2) -> x2 + v55 Store { addr=v48, disp=4, value=v54, kind=I32 } -> - + v56 Extend { value=v34, kind=I32 } -> x1 + v57 LoadLocal { off=2, kind=I64 } -> x1 + v58 Imm(1) -> x1 + v59 Imm(4) -> x1 + v60 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 + v61 Load { addr=v1, disp=4, kind=I32 } -> x1 + v62 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v63 BinopI { op=add, lhs=v62, rhs_imm=4 } -> x6 + v64 Load { addr=v62, disp=4, kind=I32 } -> x2 + v65 Binop { op=add, lhs=v61, rhs=v64 } -> x1 + v66 BinopI { op=shl, lhs=v65, rhs_imm=32 } -> x2 + v67 Extend { value=v65, kind=I32 } -> x2 + v68 Binop { op=add, lhs=v34, rhs=v65 } -> x0 + v69 Imm(0) -> x1 + v70 Extend { value=v68, kind=I32 } -> x1 + v71 Imm(1) -> x1 + v72 Imm(2) -> x1 + v73 Imm(0) -> x1 + v74 Imm(2) -> x1 + v75 Imm(1) -> x1 + v76 LoadLocal { off=2, kind=I64 } -> x1 + v77 Imm(2) -> x1 + v78 Imm(8) -> x2 + v79 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x2 + v80 Store { addr=v1, disp=8, value=v77, kind=I32 } -> - + v81 LoadLocal { off=2, kind=I64 } -> x1 + v82 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v83 Imm(2) -> x2 + v84 Imm(8) -> x2 + v85 BinopI { op=add, lhs=v82, rhs_imm=8 } -> x2 + v86 Imm(3) -> x2 + v87 Imm(12884901888) -> x2 + v88 Imm(3) -> x2 + v89 Store { addr=v82, disp=8, value=v88, kind=I32 } -> - + v90 Extend { value=v68, kind=I32 } -> x1 + v91 LoadLocal { off=2, kind=I64 } -> x1 + v92 Imm(2) -> x1 + v93 Imm(8) -> x1 + v94 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 + v95 Load { addr=v1, disp=8, kind=I32 } -> x1 + v96 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v97 BinopI { op=add, lhs=v96, rhs_imm=8 } -> x6 + v98 Load { addr=v96, disp=8, kind=I32 } -> x2 + v99 Binop { op=add, lhs=v95, rhs=v98 } -> x1 + v100 BinopI { op=shl, lhs=v99, rhs_imm=32 } -> x2 + v101 Extend { value=v99, kind=I32 } -> x2 + v102 Binop { op=add, lhs=v68, rhs=v99 } -> x0 + v103 Imm(0) -> x1 + v104 Extend { value=v102, kind=I32 } -> x1 + v105 Imm(2) -> x1 + v106 Imm(3) -> x1 + v107 Imm(0) -> x1 + v108 Imm(3) -> x1 + v109 Imm(1) -> x1 + v110 LoadLocal { off=2, kind=I64 } -> x1 + v111 Imm(3) -> x1 + v112 Imm(12) -> x2 + v113 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x2 + v114 Store { addr=v1, disp=12, value=v111, kind=I32 } -> - + v115 LoadLocal { off=2, kind=I64 } -> x1 + v116 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v117 Imm(3) -> x2 + v118 Imm(12) -> x2 + v119 BinopI { op=add, lhs=v116, rhs_imm=12 } -> x2 + v120 Imm(4) -> x2 + v121 Imm(17179869184) -> x2 + v122 Imm(4) -> x2 + v123 Store { addr=v116, disp=12, value=v122, kind=I32 } -> - + v124 Extend { value=v102, kind=I32 } -> x1 + v125 LoadLocal { off=2, kind=I64 } -> x1 + v126 Imm(3) -> x1 + v127 Imm(12) -> x1 + v128 BinopI { op=add, lhs=v1, rhs_imm=12 } -> x1 + v129 Load { addr=v1, disp=12, kind=I32 } -> x1 + v130 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v131 BinopI { op=add, lhs=v130, rhs_imm=12 } -> x6 + v132 Load { addr=v130, disp=12, kind=I32 } -> x2 + v133 Binop { op=add, lhs=v129, rhs=v132 } -> x1 + v134 BinopI { op=shl, lhs=v133, rhs_imm=32 } -> x2 + v135 Extend { value=v133, kind=I32 } -> x2 + v136 Binop { op=add, lhs=v102, rhs=v133 } -> x0 + v137 Imm(0) -> x1 + v138 Extend { value=v136, kind=I32 } -> x1 + v139 Imm(3) -> x1 + v140 Imm(4) -> x1 + v141 Imm(0) -> x1 + v142 Imm(4) -> x1 + v143 Imm(1) -> x1 + v144 LoadLocal { off=2, kind=I64 } -> x1 + v145 Imm(4) -> x1 + v146 Imm(16) -> x2 + v147 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x2 + v148 Store { addr=v1, disp=16, value=v145, kind=I32 } -> - + v149 LoadLocal { off=2, kind=I64 } -> x1 + v150 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v151 Imm(4) -> x2 + v152 Imm(16) -> x2 + v153 BinopI { op=add, lhs=v150, rhs_imm=16 } -> x2 + v154 Imm(5) -> x2 + v155 Imm(21474836480) -> x2 + v156 Imm(5) -> x2 + v157 Store { addr=v150, disp=16, value=v156, kind=I32 } -> - + v158 Extend { value=v136, kind=I32 } -> x1 + v159 LoadLocal { off=2, kind=I64 } -> x1 + v160 Imm(4) -> x1 + v161 Imm(16) -> x1 + v162 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x1 + v163 Load { addr=v1, disp=16, kind=I32 } -> x1 + v164 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v165 BinopI { op=add, lhs=v164, rhs_imm=16 } -> x6 + v166 Load { addr=v164, disp=16, kind=I32 } -> x2 + v167 Binop { op=add, lhs=v163, rhs=v166 } -> x1 + v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x2 + v169 Extend { value=v167, kind=I32 } -> x2 + v170 Binop { op=add, lhs=v136, rhs=v167 } -> x0 + v171 Imm(0) -> x1 + v172 Extend { value=v170, kind=I32 } -> x1 + v173 Imm(4) -> x1 + v174 Imm(5) -> x1 + v175 Imm(0) -> x1 + v176 Imm(5) -> x1 + v177 Imm(1) -> x1 + v178 LoadLocal { off=2, kind=I64 } -> x1 + v179 Imm(5) -> x1 + v180 Imm(20) -> x2 + v181 BinopI { op=add, lhs=v1, rhs_imm=20 } -> x2 + v182 Store { addr=v1, disp=20, value=v179, kind=I32 } -> - + v183 LoadLocal { off=2, kind=I64 } -> x1 + v184 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v185 Imm(5) -> x2 + v186 Imm(20) -> x2 + v187 BinopI { op=add, lhs=v184, rhs_imm=20 } -> x2 + v188 Imm(6) -> x2 + v189 Imm(25769803776) -> x2 + v190 Imm(6) -> x2 + v191 Store { addr=v184, disp=20, value=v190, kind=I32 } -> - + v192 Extend { value=v170, kind=I32 } -> x1 + v193 LoadLocal { off=2, kind=I64 } -> x1 + v194 Imm(5) -> x1 + v195 Imm(20) -> x1 + v196 BinopI { op=add, lhs=v1, rhs_imm=20 } -> x1 + v197 Load { addr=v1, disp=20, kind=I32 } -> x1 + v198 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v199 BinopI { op=add, lhs=v198, rhs_imm=20 } -> x6 + v200 Load { addr=v198, disp=20, kind=I32 } -> x2 + v201 Binop { op=add, lhs=v197, rhs=v200 } -> x1 + v202 BinopI { op=shl, lhs=v201, rhs_imm=32 } -> x2 + v203 Extend { value=v201, kind=I32 } -> x2 + v204 Binop { op=add, lhs=v170, rhs=v201 } -> x0 + v205 Imm(0) -> x1 + v206 Extend { value=v204, kind=I32 } -> x1 + v207 Imm(5) -> x1 + v208 Imm(6) -> x1 + v209 Imm(0) -> x1 + v210 Imm(6) -> x1 + v211 Imm(1) -> x1 + v212 LoadLocal { off=2, kind=I64 } -> x1 + v213 Imm(6) -> x1 + v214 Imm(24) -> x2 + v215 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x2 + v216 Store { addr=v1, disp=24, value=v213, kind=I32 } -> - + v217 LoadLocal { off=2, kind=I64 } -> x1 + v218 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v219 Imm(6) -> x2 + v220 Imm(24) -> x2 + v221 BinopI { op=add, lhs=v218, rhs_imm=24 } -> x2 + v222 Imm(7) -> x2 + v223 Imm(30064771072) -> x2 + v224 Imm(7) -> x2 + v225 Store { addr=v218, disp=24, value=v224, kind=I32 } -> - + v226 Extend { value=v204, kind=I32 } -> x1 + v227 LoadLocal { off=2, kind=I64 } -> x1 + v228 Imm(6) -> x1 + v229 Imm(24) -> x1 + v230 BinopI { op=add, lhs=v1, rhs_imm=24 } -> x1 + v231 Load { addr=v1, disp=24, kind=I32 } -> x1 + v232 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v233 BinopI { op=add, lhs=v232, rhs_imm=24 } -> x6 + v234 Load { addr=v232, disp=24, kind=I32 } -> x2 + v235 Binop { op=add, lhs=v231, rhs=v234 } -> x1 + v236 BinopI { op=shl, lhs=v235, rhs_imm=32 } -> x2 + v237 Extend { value=v235, kind=I32 } -> x2 + v238 Binop { op=add, lhs=v204, rhs=v235 } -> x0 + v239 Imm(0) -> x1 + v240 Extend { value=v238, kind=I32 } -> x1 + v241 Imm(6) -> x1 + v242 Imm(7) -> x1 + v243 Imm(0) -> x1 + v244 Imm(7) -> x1 + v245 Imm(1) -> x1 + v246 LoadLocal { off=2, kind=I64 } -> x1 + v247 Imm(7) -> x1 + v248 Imm(28) -> x2 + v249 BinopI { op=add, lhs=v1, rhs_imm=28 } -> x2 + v250 Store { addr=v1, disp=28, value=v247, kind=I32 } -> - + v251 LoadLocal { off=2, kind=I64 } -> x1 + v252 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v253 Imm(7) -> x2 + v254 Imm(28) -> x2 + v255 BinopI { op=add, lhs=v252, rhs_imm=28 } -> x2 + v256 Imm(8) -> x2 + v257 Imm(34359738368) -> x2 + v258 Imm(8) -> x2 + v259 Store { addr=v252, disp=28, value=v258, kind=I32 } -> - + v260 Extend { value=v238, kind=I32 } -> x1 + v261 LoadLocal { off=2, kind=I64 } -> x1 + v262 Imm(7) -> x1 + v263 Imm(28) -> x1 + v264 BinopI { op=add, lhs=v1, rhs_imm=28 } -> x1 + v265 Load { addr=v1, disp=28, kind=I32 } -> x1 + v266 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v267 BinopI { op=add, lhs=v266, rhs_imm=28 } -> x6 + v268 Load { addr=v266, disp=28, kind=I32 } -> x2 + v269 Binop { op=add, lhs=v265, rhs=v268 } -> x1 + v270 BinopI { op=shl, lhs=v269, rhs_imm=32 } -> x2 + v271 Extend { value=v269, kind=I32 } -> x2 + v272 Binop { op=add, lhs=v238, rhs=v269 } -> x0 + v273 Imm(0) -> x1 + v274 Extend { value=v272, kind=I32 } -> x1 + v275 Imm(7) -> x1 + v276 Imm(8) -> x1 + v277 Imm(0) -> x1 + v278 Imm(8) -> x1 + v279 Imm(1) -> x1 + v280 LoadLocal { off=2, kind=I64 } -> x1 + v281 Imm(8) -> x1 + v282 Imm(32) -> x2 + v283 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x2 + v284 Store { addr=v1, disp=32, value=v281, kind=I32 } -> - + v285 LoadLocal { off=2, kind=I64 } -> x1 + v286 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v287 Imm(8) -> x2 + v288 Imm(32) -> x2 + v289 BinopI { op=add, lhs=v286, rhs_imm=32 } -> x2 + v290 Imm(9) -> x2 + v291 Imm(38654705664) -> x2 + v292 Imm(9) -> x2 + v293 Store { addr=v286, disp=32, value=v292, kind=I32 } -> - + v294 Extend { value=v272, kind=I32 } -> x1 + v295 LoadLocal { off=2, kind=I64 } -> x1 + v296 Imm(8) -> x1 + v297 Imm(32) -> x1 + v298 BinopI { op=add, lhs=v1, rhs_imm=32 } -> x1 + v299 Load { addr=v1, disp=32, kind=I32 } -> x1 + v300 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v301 BinopI { op=add, lhs=v300, rhs_imm=32 } -> x6 + v302 Load { addr=v300, disp=32, kind=I32 } -> x2 + v303 Binop { op=add, lhs=v299, rhs=v302 } -> x1 + v304 BinopI { op=shl, lhs=v303, rhs_imm=32 } -> x2 + v305 Extend { value=v303, kind=I32 } -> x2 + v306 Binop { op=add, lhs=v272, rhs=v303 } -> x0 + v307 Imm(0) -> x1 + v308 Extend { value=v306, kind=I32 } -> x1 + v309 Imm(8) -> x1 + v310 Imm(9) -> x1 + v311 Imm(0) -> x1 + v312 Imm(9) -> x1 + v313 Imm(1) -> x1 + v314 LoadLocal { off=2, kind=I64 } -> x1 + v315 Imm(9) -> x1 + v316 Imm(36) -> x2 + v317 BinopI { op=add, lhs=v1, rhs_imm=36 } -> x2 + v318 Store { addr=v1, disp=36, value=v315, kind=I32 } -> - + v319 LoadLocal { off=2, kind=I64 } -> x1 + v320 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x1 + v321 Imm(9) -> x2 + v322 Imm(36) -> x2 + v323 BinopI { op=add, lhs=v320, rhs_imm=36 } -> x2 + v324 Imm(10) -> x2 + v325 Imm(42949672960) -> x2 + v326 Imm(10) -> x2 + v327 Store { addr=v320, disp=36, value=v326, kind=I32 } -> - + v328 Extend { value=v306, kind=I32 } -> x1 + v329 LoadLocal { off=2, kind=I64 } -> x1 + v330 Imm(9) -> x1 + v331 Imm(36) -> x1 + v332 BinopI { op=add, lhs=v1, rhs_imm=36 } -> x1 + v333 Load { addr=v1, disp=36, kind=I32 } -> x1 + v334 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 + v335 BinopI { op=add, lhs=v334, rhs_imm=36 } -> x6 + v336 Load { addr=v334, disp=36, kind=I32 } -> x2 + v337 Binop { op=add, lhs=v333, rhs=v336 } -> x1 + v338 BinopI { op=shl, lhs=v337, rhs_imm=32 } -> x2 + v339 Extend { value=v337, kind=I32 } -> x2 + v340 Binop { op=add, lhs=v306, rhs=v337 } -> x0 + v341 Imm(0) -> x1 + v342 Extend { value=v340, kind=I32 } -> x1 + v343 Imm(9) -> x1 + v344 Imm(10) -> x1 + v345 Imm(0) -> x1 + v346 Imm(10) -> x1 + v347 Imm(0) -> x1 + terminator Jmp(b2) (exit_acc=v347) block 2 start_pc=0 - v10 Extend { value=v7, kind=I32 } -> x0 - v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x0 - v12 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v11) - block 3 start_pc=0 - v13 LoadLocal { off=2, kind=I64 } -> x2 - v14 Extend { value=v7, kind=I32 } -> x2 - v15 BinopI { op=shl, lhs=v14, rhs_imm=2 } -> x6 - v16 Binop { op=add, lhs=v1, rhs=v15 } -> x6 - v17 StoreIndexed { base=v1, index=v14, scale=4, value=v7, kind=I32 } -> - - v18 LoadLocal { off=2, kind=I64 } -> x2 - v19 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x2 - v20 Extend { value=v7, kind=I32 } -> x6 - v21 BinopI { op=shl, lhs=v20, rhs_imm=2 } -> x8 - v22 Binop { op=add, lhs=v19, rhs=v21 } -> x8 - v23 BinopI { op=add, lhs=v20, rhs_imm=1 } -> x8 - v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x9 - v25 Extend { value=v23, kind=I32 } -> x9 - v26 StoreIndexed { base=v19, index=v20, scale=4, value=v23, kind=I32 } -> - - v27 Extend { value=v6, kind=I32 } -> x2 - v28 LoadLocal { off=2, kind=I64 } -> x2 - v29 Extend { value=v7, kind=I32 } -> x2 - v30 BinopI { op=shl, lhs=v29, rhs_imm=2 } -> x2 - v31 Binop { op=add, lhs=v1, rhs=v30 } -> x6 - v32 Load { addr=v31, disp=0, kind=I32 } -> x6 - v33 BinopI { op=add, lhs=v1, rhs_imm=40 } -> x8 - v34 Binop { op=add, lhs=v33, rhs=v30 } -> x2 - v35 Load { addr=v34, disp=0, kind=I32 } -> x2 - v36 Binop { op=add, lhs=v32, rhs=v35 } -> x2 - v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x6 - v38 Extend { value=v36, kind=I32 } -> x6 - v39 Binop { op=add, lhs=v6, rhs=v36 } -> x1 - v40 Imm(0) -> x2 - v41 Extend { value=v39, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v41) - block 4 start_pc=0 - v42 LoadLocal { off=2, kind=I64 } -> x0 - v43 BinopI { op=add, lhs=v1, rhs_imm=160 } -> x0 - v44 Extend { value=v6, kind=I32 } -> x0 - v45 Store { addr=v1, disp=160, value=v6, kind=I32 } -> - - v46 LoadLocal { off=2, kind=I64 } -> x0 - v47 BinopI { op=add, lhs=v1, rhs_imm=160 } -> x0 - v48 Extend { value=v6, kind=I32 } -> x0 - terminator Return(v48) (exit_acc=v48) + v348 LoadLocal { off=2, kind=I64 } -> x1 + v349 BinopI { op=add, lhs=v1, rhs_imm=160 } -> x1 + v350 Extend { value=v340, kind=I32 } -> x1 + v351 Store { addr=v1, disp=160, value=v340, kind=I32 } -> - + v352 LoadLocal { off=2, kind=I64 } -> x1 + v353 BinopI { op=add, lhs=v1, rhs_imm=160 } -> x1 + v354 Extend { value=v340, kind=I32 } -> x0 + terminator Return(v354) (exit_acc=v354) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=23 diff --git a/tests/snapshots/ssa/typeof_operator.ssa b/tests/snapshots/ssa/typeof_operator.ssa index 6bfab33eb..84b335424 100644 --- a/tests/snapshots/ssa/typeof_operator.ssa +++ b/tests/snapshots/ssa/typeof_operator.ssa @@ -30,14 +30,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 terminator Return(v10) (exit_acc=v10) block 2 start_pc=0 v11 Imm(100) -> x0 - v12 Imm(0) -> x1 - v13 LoadLocal { off=-3, kind=I64 } -> x1 - v14 BinopI { op=ne, lhs=v11, rhs_imm=100 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v12 Imm(0) -> x0 + v13 LoadLocal { off=-3, kind=I64 } -> x0 + v14 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v14) block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) - block 4 start_pc=0 v16 LocalAddr(-1) -> x0 v17 Imm(0) -> x0 v18 LocalAddr(-2) -> x0 @@ -45,71 +42,74 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 v20 LoadLocal { off=-5, kind=I64 } -> x1 v21 Load { addr=v18, disp=0, kind=I32 } -> x0 v22 BinopI { op=ne, lhs=v21, rhs_imm=8 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) - block 5 start_pc=0 + terminator Bz { cond=v22, target=b5, fall=b4 } (exit_acc=v22) + block 4 start_pc=0 v23 Imm(3) -> x0 terminator Return(v23) (exit_acc=v23) - block 6 start_pc=0 + block 5 start_pc=0 v24 LocalAddr(-1) -> x0 v25 Imm(0) -> x1 v26 LoadLocal { off=-6, kind=I64 } -> x1 v27 Load { addr=v24, disp=0, kind=I32 } -> x0 v28 BinopI { op=ne, lhs=v27, rhs_imm=5 } -> x0 - terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) - block 7 start_pc=0 + terminator Bz { cond=v28, target=b7, fall=b6 } (exit_acc=v28) + block 6 start_pc=0 v29 Imm(4) -> x0 terminator Return(v29) (exit_acc=v29) - block 8 start_pc=0 + block 7 start_pc=0 v30 LocalAddr(-7) -> x0 v31 Imm(8589934591) -> x0 - v32 Imm(0) -> x1 - v33 LocalAddr(-7) -> x1 - v34 Load { addr=v33, disp=0, kind=I64 } -> x1 - v35 BinopI { op=ne, lhs=v31, rhs_imm=8589934591 } -> x0 - terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) - block 9 start_pc=0 - v36 Imm(5) -> x0 - terminator Return(v36) (exit_acc=v36) - block 10 start_pc=0 + v32 Imm(0) -> x0 + v33 LocalAddr(-7) -> x0 + v34 Load { addr=v33, disp=0, kind=I64 } -> x0 + v35 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v35) + block 8 start_pc=0 v37 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v37) - block 11 start_pc=0 - v38 Imm(6) -> x0 - terminator Return(v38) (exit_acc=v38) - block 12 start_pc=0 + terminator Jmp(b9) (exit_acc=v37) + block 9 start_pc=0 v39 Imm(4294967297) -> x0 - v40 Imm(0) -> x1 - v41 LoadLocal { off=-8, kind=I64 } -> x1 - v42 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x1 - v43 Extend { value=v39, kind=I32 } -> x0 - v44 Imm(0) -> x1 - v45 LoadLocal { off=-9, kind=I32 } -> x1 - v46 BinopI { op=ne, lhs=v43, rhs_imm=1 } -> x0 - terminator Bz { cond=v46, target=b14, fall=b13 } (exit_acc=v46) - block 13 start_pc=0 - v47 Imm(7) -> x0 - terminator Return(v47) (exit_acc=v47) - block 14 start_pc=0 + v40 Imm(0) -> x0 + v41 LoadLocal { off=-8, kind=I64 } -> x0 + v42 Imm(4294967296) -> x0 + v43 Imm(1) -> x0 + v44 Imm(0) -> x0 + v45 LoadLocal { off=-9, kind=I32 } -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v46) + block 10 start_pc=0 v48 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v48) - block 15 start_pc=0 - v49 Imm(8) -> x0 - terminator Return(v49) (exit_acc=v49) - block 16 start_pc=0 + terminator Jmp(b11) (exit_acc=v48) + block 11 start_pc=0 v50 Imm(0) -> x0 - v51 Imm(0) -> x1 - v52 LoadLocal { off=-10, kind=I32 } -> x1 - v53 BinopI { op=and, lhs=v50, rhs_imm=255 } -> x0 + v51 Imm(0) -> x0 + v52 LoadLocal { off=-10, kind=I32 } -> x0 + v53 Imm(0) -> x0 v54 ImmData(24) -> x0 v55 Load { addr=v54, disp=0, kind=I32 } -> x0 v56 BinopI { op=ne, lhs=v55, rhs_imm=0 } -> x0 - terminator Bz { cond=v56, target=b18, fall=b17 } (exit_acc=v56) - block 17 start_pc=0 + terminator Bz { cond=v56, target=b13, fall=b12 } (exit_acc=v56) + block 12 start_pc=0 v57 Imm(9) -> x0 terminator Return(v57) (exit_acc=v57) - block 18 start_pc=0 + block 13 start_pc=0 v58 Imm(0) -> x0 terminator Return(v58) (exit_acc=v58) + block 14 start_pc=0 + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) + block 15 start_pc=0 + v36 Imm(5) -> x0 + terminator Return(v36) (exit_acc=v36) + block 16 start_pc=0 + v38 Imm(6) -> x0 + terminator Return(v38) (exit_acc=v38) + block 17 start_pc=0 + v47 Imm(7) -> x0 + terminator Return(v47) (exit_acc=v47) + block 18 start_pc=0 + v49 Imm(8) -> x0 + terminator Return(v49) (exit_acc=v49) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/u16_load_store.ssa b/tests/snapshots/ssa/u16_load_store.ssa index 622bd5489..2ac197a66 100644 --- a/tests/snapshots/ssa/u16_load_store.ssa +++ b/tests/snapshots/ssa/u16_load_store.ssa @@ -20,7 +20,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v14 Load { addr=v13, disp=0, kind=I8 } -> x0 v15 BinopI { op=ne, lhs=v14, rhs_imm=0 } -> x1 v16 Imm(0) -> x0 - terminator Bnz { cond=v15, target=b13, fall=b1 } (exit_acc=v15) + terminator Bnz { cond=v15, target=b14, fall=b1 } (exit_acc=v15) block 1 start_pc=0 v17 LocalAddr(-4) -> x0 v18 Imm(1) -> x1 @@ -30,7 +30,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v22 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 - v23 Phi { incoming=[b13:v15, b1:v21], kind=I64 } -> x1 + v23 Phi { incoming=[b14:v15, b1:v21], kind=I64 } -> x1 v24 LoadLocal { off=-8, kind=I64 } -> x0 terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 @@ -43,7 +43,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v29 Load { addr=v26, disp=2, kind=I8 } -> x0 v30 BinopI { op=ne, lhs=v29, rhs_imm=65 } -> x1 v31 Imm(0) -> x0 - terminator Bnz { cond=v30, target=b14, fall=b5 } (exit_acc=v30) + terminator Bnz { cond=v30, target=b13, fall=b5 } (exit_acc=v30) block 5 start_pc=0 v32 LocalAddr(-4) -> x0 v33 Imm(3) -> x1 @@ -53,7 +53,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v37 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v36) block 6 start_pc=0 - v38 Phi { incoming=[b14:v30, b5:v36], kind=I64 } -> x1 + v38 Phi { incoming=[b13:v30, b5:v36], kind=I64 } -> x1 v39 LoadLocal { off=-9, kind=I64 } -> x0 terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) block 7 start_pc=0 @@ -87,9 +87,9 @@ fn ent_pc=1 n_params=0 variadic=false locals=9 v57 Imm(0) -> x0 terminator Return(v57) (exit_acc=v57) block 13 start_pc=0 - terminator Jmp(b2) - block 14 start_pc=0 terminator Jmp(b6) + block 14 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/uint64_to_float.ssa b/tests/snapshots/ssa/uint64_to_float.ssa index e5e6f0a74..6da6bc882 100644 --- a/tests/snapshots/ssa/uint64_to_float.ssa +++ b/tests/snapshots/ssa/uint64_to_float.ssa @@ -62,16 +62,15 @@ fn ent_pc=1 n_params=0 variadic=false locals=5 v36 LoadLocal { off=-1, kind=I64 } -> x1 v37 FpCast { kind=UIntToFp, value=v1 } -> d0 v38 FpCast { kind=F64ToF32, value=v37 } -> d0 [f32] - v39 Imm(4890909195324358656) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) + v39 Imm(1593835520) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) block 11 start_pc=0 - v42 Imm(6) -> x0 - terminator Return(v42) (exit_acc=v42) + v41 Imm(6) -> x0 + terminator Return(v41) (exit_acc=v41) block 12 start_pc=0 - v43 Imm(0) -> x0 - terminator Return(v43) (exit_acc=v43) + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unary_minus_uint64_compare.ssa b/tests/snapshots/ssa/unary_minus_uint64_compare.ssa index 7af1251ae..e780a8133 100644 --- a/tests/snapshots/ssa/unary_minus_uint64_compare.ssa +++ b/tests/snapshots/ssa/unary_minus_uint64_compare.ssa @@ -5,15 +5,12 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(168) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I64 } -> x1 - v4 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x0 - v5 BinopI { op=ult, lhs=v4, rhs_imm=4096 } -> x0 - terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I64 } -> x0 + v4 Imm(-168) -> x0 + v5 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v6 Imm(11) -> x0 - terminator Return(v6) (exit_acc=v6) - block 2 start_pc=0 v7 LocalAddr(-2) -> x0 v8 ImmData(8) -> x1 v9 Mcpy { dst=v7, src=v8, size=8 } -> x0 @@ -25,48 +22,51 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 v15 LoadLocal { off=-3, kind=I64 } -> x1 v16 BinopI { op=mul, lhs=v13, rhs_imm=-1 } -> x0 v17 BinopI { op=ult, lhs=v16, rhs_imm=4096 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) - block 3 start_pc=0 + terminator Bz { cond=v17, target=b3, fall=b2 } (exit_acc=v17) + block 2 start_pc=0 v18 Imm(12) -> x0 terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 + block 3 start_pc=0 v19 Imm(168) -> x0 - v20 Imm(0) -> x1 - v21 LoadLocal { off=-4, kind=I64 } -> x1 - v22 BinopI { op=mul, lhs=v19, rhs_imm=-1 } -> x0 - v23 BinopI { op=ult, lhs=v22, rhs_imm=4096 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) - block 5 start_pc=0 - v24 Imm(1) -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v24) - block 6 start_pc=0 + v20 Imm(0) -> x0 + v21 LoadLocal { off=-4, kind=I64 } -> x0 + v22 Imm(-168) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v23) + block 4 start_pc=0 v26 Imm(2) -> x1 v27 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v26) - block 7 start_pc=0 - v28 Phi { incoming=[b5:v24, b6:v26], kind=I64 } -> x1 + terminator Jmp(b5) (exit_acc=v26) + block 5 start_pc=0 + v28 Phi { incoming=[b10:v24, b4:v26], kind=I64 } -> x1 v29 LoadLocal { off=-7, kind=I64 } -> x0 v30 Imm(0) -> x0 v31 Extend { value=v28, kind=I32 } -> x0 v32 BinopI { op=ne, lhs=v31, rhs_imm=2 } -> x0 - terminator Bz { cond=v32, target=b9, fall=b8 } (exit_acc=v32) - block 8 start_pc=0 + terminator Bz { cond=v32, target=b7, fall=b6 } (exit_acc=v32) + block 6 start_pc=0 v33 Imm(13) -> x0 terminator Return(v33) (exit_acc=v33) - block 9 start_pc=0 + block 7 start_pc=0 v34 Imm(8) -> x0 - v35 Imm(0) -> x1 - v36 LoadLocal { off=-6, kind=I64 } -> x1 - v37 BinopI { op=mul, lhs=v34, rhs_imm=-1 } -> x0 - v38 BinopI { op=ult, lhs=v37, rhs_imm=4096 } -> x0 - terminator Bz { cond=v38, target=b11, fall=b10 } (exit_acc=v38) + v35 Imm(0) -> x0 + v36 LoadLocal { off=-6, kind=I64 } -> x0 + v37 Imm(-8) -> x0 + v38 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v38) + block 8 start_pc=0 + v40 Imm(0) -> x0 + terminator Return(v40) (exit_acc=v40) + block 9 start_pc=0 + v6 Imm(11) -> x0 + terminator Return(v6) (exit_acc=v6) block 10 start_pc=0 + v24 Imm(1) -> x1 + v25 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v24) + block 11 start_pc=0 v39 Imm(14) -> x0 terminator Return(v39) (exit_acc=v39) - block 11 start_pc=0 - v40 Imm(0) -> x0 - terminator Return(v40) (exit_acc=v40) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unary_minus_unsigned_int_truncation.ssa b/tests/snapshots/ssa/unary_minus_unsigned_int_truncation.ssa index e396190ba..32668d08a 100644 --- a/tests/snapshots/ssa/unary_minus_unsigned_int_truncation.ssa +++ b/tests/snapshots/ssa/unary_minus_unsigned_int_truncation.ssa @@ -5,119 +5,119 @@ fn ent_pc=0 n_params=0 variadic=false locals=7 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x1 - v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x1 - v6 BinopI { op=ne, lhs=v5, rhs_imm=4294967295 } -> x1 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(-1) -> x0 + v5 Imm(4294967295) -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v8 LoadLocal { off=-1, kind=U32 } -> x0 + v9 Imm(-1) -> x0 + v10 Imm(4294967295) -> x0 + v11 Imm(4294967295) -> x0 + v12 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v8 LoadLocal { off=-1, kind=U32 } -> x1 - v9 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x1 - v10 BinopI { op=and, lhs=v9, rhs_imm=4294967295 } -> x1 - v11 Binop { op=or, lhs=v1, rhs=v10 } -> x1 - v12 BinopI { op=ne, lhs=v11, rhs_imm=4294967295 } -> x1 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v14 LoadLocal { off=-1, kind=U32 } -> x0 + v15 Imm(-1) -> x0 + v16 Imm(4294967295) -> x0 + v17 Imm(4294967295) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v19) block 3 start_pc=0 - v13 Imm(2) -> x0 - terminator Return(v13) (exit_acc=v13) + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 LoadLocal { off=-2, kind=U32 } -> x0 + v24 Imm(0) -> x0 + v25 Imm(0) -> x0 + v26 Imm(0) -> x0 + v27 Imm(0) -> x0 + v28 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v28) block 4 start_pc=0 - v14 LoadLocal { off=-1, kind=U32 } -> x1 - v15 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x1 - v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x1 - v17 Binop { op=or, lhs=v1, rhs=v16 } -> x1 - v18 BinopI { op=shru, lhs=v17, rhs_imm=31 } -> x1 - v19 BinopI { op=ne, lhs=v18, rhs_imm=1 } -> x1 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + v30 LoadLocal { off=-1, kind=U32 } -> x0 + v31 Imm(-1) -> x0 + v32 Imm(4294967295) -> x0 + v33 Imm(0) -> x0 + v34 Imm(4294967295) -> x0 + v35 Imm(4294967295) -> x0 + v36 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v36) block 5 start_pc=0 - v20 Imm(3) -> x0 - terminator Return(v20) (exit_acc=v20) + v38 LoadLocal { off=-1, kind=U32 } -> x0 + v39 Imm(4294967295) -> x0 + v40 Imm(4294967295) -> x0 + v41 Imm(1) -> x0 + v42 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v42) block 6 start_pc=0 - v21 Imm(0) -> x1 - v22 Imm(0) -> x2 - v23 LoadLocal { off=-2, kind=U32 } -> x2 - v24 BinopI { op=mul, lhs=v21, rhs_imm=-1 } -> x2 - v25 BinopI { op=and, lhs=v24, rhs_imm=4294967295 } -> x2 - v26 Binop { op=or, lhs=v21, rhs=v25 } -> x1 - v27 BinopI { op=shru, lhs=v26, rhs_imm=31 } -> x1 - v28 BinopI { op=ne, lhs=v27, rhs_imm=0 } -> x1 - terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) + v44 Imm(1) -> x0 + v45 Imm(0) -> x0 + v46 Imm(0) -> x0 + v47 Imm(0) -> x0 + v48 LoadLocal { off=-4, kind=U32 } -> x0 + v49 LoadLocal { off=-5, kind=U32 } -> x0 + v50 Imm(1) -> x0 + v51 Imm(0) -> x0 + v52 Imm(1) -> x0 + v53 Imm(-1) -> x0 + v54 Imm(4294967295) -> x0 + v55 Imm(4294967295) -> x0 + v56 Imm(1) -> x0 + v57 Imm(0) -> x0 + v58 Imm(0) -> x0 + v59 Imm(0) -> x0 + v60 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v60) block 7 start_pc=0 - v29 Imm(4) -> x0 - terminator Return(v29) (exit_acc=v29) + v62 Imm(5) -> x0 + v63 Imm(0) -> x0 + v64 Imm(0) -> x0 + v65 LoadLocal { off=-4, kind=U32 } -> x0 + v66 LoadLocal { off=-5, kind=U32 } -> x0 + v67 Imm(0) -> x0 + v68 Imm(0) -> x0 + v69 Imm(0) -> x0 + v70 Imm(0) -> x0 + v71 Imm(0) -> x0 + v72 Imm(0) -> x0 + v73 Imm(0) -> x0 + v74 Imm(0) -> x0 + v75 Imm(1) -> x0 + v76 Imm(0) -> x0 + v77 Imm(1) -> x0 + v78 Imm(1) -> x0 + v79 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v79) block 8 start_pc=0 - v30 LoadLocal { off=-1, kind=U32 } -> x1 - v31 BinopI { op=mul, lhs=v1, rhs_imm=-1 } -> x1 - v32 BinopI { op=and, lhs=v31, rhs_imm=4294967295 } -> x1 - v33 Imm(0) -> x2 - v34 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x2 - v35 Binop { op=or, lhs=v1, rhs=v34 } -> x2 - v36 BinopI { op=ne, lhs=v35, rhs_imm=4294967295 } -> x2 - terminator Bz { cond=v36, target=b10, fall=b9 } (exit_acc=v36) + v81 Imm(0) -> x0 + terminator Return(v81) (exit_acc=v81) block 9 start_pc=0 - v37 Imm(5) -> x0 - terminator Return(v37) (exit_acc=v37) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 10 start_pc=0 - v38 LoadLocal { off=-1, kind=U32 } -> x2 - v39 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x1 - v40 Binop { op=or, lhs=v1, rhs=v39 } -> x0 - v41 BinopI { op=shru, lhs=v40, rhs_imm=31 } -> x0 - v42 BinopI { op=ne, lhs=v41, rhs_imm=1 } -> x0 - terminator Bz { cond=v42, target=b12, fall=b11 } (exit_acc=v42) + v13 Imm(2) -> x0 + terminator Return(v13) (exit_acc=v13) block 11 start_pc=0 - v43 Imm(6) -> x0 - terminator Return(v43) (exit_acc=v43) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 12 start_pc=0 - v44 Imm(1) -> x0 - v45 Imm(0) -> x1 - v46 Imm(0) -> x1 - v47 Imm(0) -> x2 - v48 LoadLocal { off=-4, kind=U32 } -> x2 - v49 LoadLocal { off=-5, kind=U32 } -> x2 - v50 Binop { op=xor, lhs=v44, rhs=v46 } -> x0 - v51 Imm(0) -> x1 - v52 BinopI { op=and, lhs=v50, rhs_imm=4294967295 } -> x0 - v53 BinopI { op=mul, lhs=v52, rhs_imm=-1 } -> x1 - v54 BinopI { op=and, lhs=v53, rhs_imm=4294967295 } -> x1 - v55 Binop { op=or, lhs=v52, rhs=v54 } -> x0 - v56 BinopI { op=shru, lhs=v55, rhs_imm=31 } -> x0 - v57 BinopI { op=xor, lhs=v56, rhs_imm=1 } -> x0 - v58 Imm(0) -> x1 - v59 BinopI { op=and, lhs=v57, rhs_imm=4294967295 } -> x0 - v60 BinopI { op=ne, lhs=v59, rhs_imm=0 } -> x0 - terminator Bz { cond=v60, target=b14, fall=b13 } (exit_acc=v60) + v29 Imm(4) -> x0 + terminator Return(v29) (exit_acc=v29) block 13 start_pc=0 - v61 Imm(7) -> x0 - terminator Return(v61) (exit_acc=v61) + v37 Imm(5) -> x0 + terminator Return(v37) (exit_acc=v37) block 14 start_pc=0 - v62 Imm(5) -> x0 - v63 Imm(0) -> x1 - v64 Imm(0) -> x1 - v65 LoadLocal { off=-4, kind=U32 } -> x1 - v66 LoadLocal { off=-5, kind=U32 } -> x1 - v67 Binop { op=xor, lhs=v62, rhs=v62 } -> x0 - v68 Imm(0) -> x1 - v69 BinopI { op=and, lhs=v67, rhs_imm=4294967295 } -> x1 - v70 BinopI { op=and, lhs=v67, rhs_imm=4294967295 } -> x0 - v71 BinopI { op=mul, lhs=v70, rhs_imm=-1 } -> x1 - v72 BinopI { op=and, lhs=v71, rhs_imm=4294967295 } -> x1 - v73 Binop { op=or, lhs=v70, rhs=v72 } -> x0 - v74 BinopI { op=shru, lhs=v73, rhs_imm=31 } -> x0 - v75 BinopI { op=xor, lhs=v74, rhs_imm=1 } -> x0 - v76 Imm(0) -> x1 - v77 BinopI { op=and, lhs=v75, rhs_imm=4294967295 } -> x1 - v78 BinopI { op=and, lhs=v75, rhs_imm=4294967295 } -> x0 - v79 BinopI { op=ne, lhs=v78, rhs_imm=1 } -> x0 - terminator Bz { cond=v79, target=b16, fall=b15 } (exit_acc=v79) + v43 Imm(6) -> x0 + terminator Return(v43) (exit_acc=v43) block 15 start_pc=0 + v61 Imm(7) -> x0 + terminator Return(v61) (exit_acc=v61) + block 16 start_pc=0 v80 Imm(8) -> x0 terminator Return(v80) (exit_acc=v80) - block 16 start_pc=0 - v81 Imm(0) -> x0 - terminator Return(v81) (exit_acc=v81) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unary_plus_init_and_param_shadow.ssa b/tests/snapshots/ssa/unary_plus_init_and_param_shadow.ssa index 2e5cba929..7e375dc6f 100644 --- a/tests/snapshots/ssa/unary_plus_init_and_param_shadow.ssa +++ b/tests/snapshots/ssa/unary_plus_init_and_param_shadow.ssa @@ -118,7 +118,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=5 v48 LoadLocal { off=-5, kind=I64 } -> x0 v49 Imm(1) -> x1 v50 Imm(0) -> x0 - terminator Bnz { cond=v47, target=b22, fall=b11 } (exit_acc=v47) + terminator Bnz { cond=v47, target=b20, fall=b11 } (exit_acc=v47) block 11 start_pc=0 v51 ImmData(40) -> x0 v52 Imm(8) -> x1 @@ -129,10 +129,10 @@ fn ent_pc=2 n_params=0 variadic=false locals=5 v57 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v56) block 12 start_pc=0 - v58 Phi { incoming=[b22:v49, b11:v56], kind=I64 } -> x1 + v58 Phi { incoming=[b20:v49, b11:v56], kind=I64 } -> x1 v59 LoadLocal { off=-4, kind=I64 } -> x0 v60 Imm(0) -> x0 - terminator Bnz { cond=v58, target=b23, fall=b13 } (exit_acc=v58) + terminator Bnz { cond=v58, target=b19, fall=b13 } (exit_acc=v58) block 13 start_pc=0 v61 ImmData(40) -> x0 v62 Imm(12) -> x1 @@ -142,7 +142,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=5 v66 Imm(0) -> x0 terminator Jmp(b14) (exit_acc=v65) block 14 start_pc=0 - v67 Phi { incoming=[b23:v58, b13:v65], kind=I64 } -> x1 + v67 Phi { incoming=[b19:v58, b13:v65], kind=I64 } -> x1 v68 LoadLocal { off=-3, kind=I64 } -> x0 terminator Bz { cond=v67, target=b16, fall=b15 } (exit_acc=v67) block 15 start_pc=0 @@ -150,31 +150,31 @@ fn ent_pc=2 n_params=0 variadic=false locals=5 terminator Return(v69) (exit_acc=v69) block 16 start_pc=0 v70 Imm(0) -> x0 - v71 Extend { value=v70, kind=I32 } -> x0 - v72 Imm(0) -> x1 - v73 BinopI { op=ne, lhs=v71, rhs_imm=0 } -> x0 - terminator Bz { cond=v73, target=b18, fall=b17 } (exit_acc=v73) + v71 Imm(0) -> x0 + v72 Imm(0) -> x0 + v73 Imm(0) -> x0 + terminator Jmp(b17) (exit_acc=v73) block 17 start_pc=0 - v74 Imm(6) -> x0 - terminator Return(v74) (exit_acc=v74) - block 18 start_pc=0 v75 Imm(42) -> x0 - v76 Extend { value=v75, kind=I32 } -> x0 - v77 Imm(0) -> x1 - v78 BinopI { op=ne, lhs=v76, rhs_imm=42 } -> x0 - terminator Bz { cond=v78, target=b20, fall=b19 } (exit_acc=v78) - block 19 start_pc=0 - v79 Imm(7) -> x0 - terminator Return(v79) (exit_acc=v79) - block 20 start_pc=0 + v76 Imm(42) -> x0 + v77 Imm(0) -> x0 + v78 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v78) + block 18 start_pc=0 v80 Imm(0) -> x0 terminator Return(v80) (exit_acc=v80) + block 19 start_pc=0 + terminator Jmp(b14) + block 20 start_pc=0 + terminator Jmp(b12) block 21 start_pc=0 terminator Jmp(b10) block 22 start_pc=0 - terminator Jmp(b12) + v74 Imm(6) -> x0 + terminator Return(v74) (exit_acc=v74) block 23 start_pc=0 - terminator Jmp(b14) + v79 Imm(7) -> x0 + terminator Return(v79) (exit_acc=v79) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unary_plus_preserves_float.ssa b/tests/snapshots/ssa/unary_plus_preserves_float.ssa index 7c844b90f..59dc3d2c5 100644 --- a/tests/snapshots/ssa/unary_plus_preserves_float.ssa +++ b/tests/snapshots/ssa/unary_plus_preserves_float.ssa @@ -20,102 +20,86 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v10 Imm(0) -> x0 v11 FpCast { kind=IntToFp, value=v10 } -> d1 v12 Binop { op=flt, lhs=v9, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + terminator Bz { cond=v12, target=b30, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v13 Imm(4602678819172646912) -> x0 v14 Fneg(v13) -> d0 v15 StoreLocal { off=-7, value=v14, kind=F64 } -> - - terminator Jmp(b5) (exit_acc=v15) + terminator Jmp(b4) (exit_acc=v15) block 4 start_pc=0 - v16 Imm(4602678819172646912) -> x0 - v17 StoreLocal { off=-7, value=v16, kind=F64 } -> - - terminator Jmp(b5) (exit_acc=v17) - block 5 start_pc=0 v18 LoadLocal { off=-7, kind=F64 } -> d0 v19 Imm(0) -> x0 v20 LoadLocal { off=-2, kind=F64 } -> d1 v21 Imm(4602678819172646912) -> x0 v22 Binop { op=fne, lhs=v18, rhs=v21 } -> x0 - terminator Bz { cond=v22, target=b7, fall=b6 } (exit_acc=v22) - block 6 start_pc=0 + terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + block 5 start_pc=0 v23 Imm(2) -> x0 terminator Return(v23) (exit_acc=v23) - block 7 start_pc=0 + block 6 start_pc=0 v24 LoadLocal { off=-1, kind=F64 } -> d1 v25 LoadLocal { off=-2, kind=F64 } -> d2 v26 Binop { op=fadd, lhs=v24, rhs=v18 } -> d0 v27 Imm(4611686018427387904) -> x0 v28 Binop { op=fne, lhs=v26, rhs=v27 } -> x0 - terminator Bz { cond=v28, target=b9, fall=b8 } (exit_acc=v28) - block 8 start_pc=0 + terminator Bz { cond=v28, target=b8, fall=b7 } (exit_acc=v28) + block 7 start_pc=0 v29 Imm(3) -> x0 terminator Return(v29) (exit_acc=v29) - block 9 start_pc=0 + block 8 start_pc=0 v30 LoadLocal { off=-1, kind=F64 } -> d0 v31 Imm(0) -> x0 v32 FpCast { kind=IntToFp, value=v31 } -> d1 v33 Binop { op=flt, lhs=v30, rhs=v32 } -> x0 - terminator Bz { cond=v33, target=b11, fall=b10 } (exit_acc=v33) - block 10 start_pc=0 + terminator Bz { cond=v33, target=b29, fall=b9 } (exit_acc=v33) + block 9 start_pc=0 v34 Imm(4602678819172646912) -> x0 v35 Fneg(v34) -> d1 v36 StoreLocal { off=-8, value=v35, kind=F64 } -> - - terminator Jmp(b12) (exit_acc=v36) - block 11 start_pc=0 - v37 Imm(4602678819172646912) -> x0 - v38 StoreLocal { off=-8, value=v37, kind=F64 } -> - - terminator Jmp(b12) (exit_acc=v38) - block 12 start_pc=0 + terminator Jmp(b10) (exit_acc=v36) + block 10 start_pc=0 v39 LoadLocal { off=-8, kind=F64 } -> d1 v40 Binop { op=fadd, lhs=v30, rhs=v39 } -> d0 v41 Imm(4611686018427387904) -> x0 v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 - terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) - block 13 start_pc=0 + terminator Bz { cond=v42, target=b12, fall=b11 } (exit_acc=v42) + block 11 start_pc=0 v43 Imm(4) -> x0 terminator Return(v43) (exit_acc=v43) - block 14 start_pc=0 + block 12 start_pc=0 v44 LoadLocal { off=-1, kind=F64 } -> d0 v45 Imm(0) -> x0 v46 FpCast { kind=IntToFp, value=v45 } -> d1 v47 Binop { op=flt, lhs=v44, rhs=v46 } -> x0 - terminator Bz { cond=v47, target=b16, fall=b15 } (exit_acc=v47) - block 15 start_pc=0 + terminator Bz { cond=v47, target=b28, fall=b13 } (exit_acc=v47) + block 13 start_pc=0 v48 Imm(4602678819172646912) -> x0 v49 Fneg(v48) -> d1 v50 StoreLocal { off=-9, value=v49, kind=F64 } -> - - terminator Jmp(b17) (exit_acc=v50) - block 16 start_pc=0 - v51 Imm(4602678819172646912) -> x0 - v52 StoreLocal { off=-9, value=v51, kind=F64 } -> - - terminator Jmp(b17) (exit_acc=v52) - block 17 start_pc=0 + terminator Jmp(b14) (exit_acc=v50) + block 14 start_pc=0 v53 LoadLocal { off=-9, kind=F64 } -> d1 v54 Binop { op=fadd, lhs=v44, rhs=v53 } -> d0 v55 FpCast { kind=FpToInt, value=v54 } -> x0 v56 Imm(0) -> x1 v57 LoadLocal { off=-3, kind=I64 } -> x1 v58 BinopI { op=ne, lhs=v55, rhs_imm=2 } -> x0 - terminator Bz { cond=v58, target=b19, fall=b18 } (exit_acc=v58) - block 18 start_pc=0 + terminator Bz { cond=v58, target=b16, fall=b15 } (exit_acc=v58) + block 15 start_pc=0 v59 Imm(5) -> x0 terminator Return(v59) (exit_acc=v59) - block 19 start_pc=0 + block 16 start_pc=0 v60 LoadLocal { off=-1, kind=F64 } -> d0 v61 Imm(0) -> x0 v62 FpCast { kind=IntToFp, value=v61 } -> d1 v63 Binop { op=flt, lhs=v60, rhs=v62 } -> x0 - terminator Bz { cond=v63, target=b21, fall=b20 } (exit_acc=v63) - block 20 start_pc=0 + terminator Bz { cond=v63, target=b27, fall=b17 } (exit_acc=v63) + block 17 start_pc=0 v64 Imm(4602678819172646912) -> x0 v65 Fneg(v64) -> d1 v66 StoreLocal { off=-10, value=v65, kind=F64 } -> - - terminator Jmp(b22) (exit_acc=v66) - block 21 start_pc=0 - v67 Imm(4602678819172646912) -> x0 - v68 StoreLocal { off=-10, value=v67, kind=F64 } -> - - terminator Jmp(b22) (exit_acc=v68) - block 22 start_pc=0 + terminator Jmp(b18) (exit_acc=v66) + block 18 start_pc=0 v69 LoadLocal { off=-10, kind=F64 } -> d1 v70 Binop { op=fadd, lhs=v60, rhs=v69 } -> d0 v71 FpCast { kind=FpToInt, value=v70 } -> x0 @@ -124,11 +108,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v74 LoadLocal { off=-4, kind=F64 } -> d1 v75 Imm(4611686018427387904) -> x0 v76 Binop { op=fne, lhs=v72, rhs=v75 } -> x0 - terminator Bz { cond=v76, target=b24, fall=b23 } (exit_acc=v76) - block 23 start_pc=0 + terminator Bz { cond=v76, target=b20, fall=b19 } (exit_acc=v76) + block 19 start_pc=0 v77 Imm(6) -> x0 terminator Return(v77) (exit_acc=v77) - block 24 start_pc=0 + block 20 start_pc=0 v78 Imm(4609434218613702656) -> x0 v79 Fneg(v78) -> d0 v80 StoreLocal { off=-1, value=v79, kind=F64 } -> - @@ -136,17 +120,13 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v82 Imm(0) -> x0 v83 FpCast { kind=IntToFp, value=v82 } -> d1 v84 Binop { op=flt, lhs=v81, rhs=v83 } -> x0 - terminator Bz { cond=v84, target=b26, fall=b25 } (exit_acc=v84) - block 25 start_pc=0 + terminator Bz { cond=v84, target=b26, fall=b21 } (exit_acc=v84) + block 21 start_pc=0 v85 Imm(4602678819172646912) -> x0 v86 Fneg(v85) -> d1 v87 StoreLocal { off=-11, value=v86, kind=F64 } -> - - terminator Jmp(b27) (exit_acc=v87) - block 26 start_pc=0 - v88 Imm(4602678819172646912) -> x0 - v89 StoreLocal { off=-11, value=v88, kind=F64 } -> - - terminator Jmp(b27) (exit_acc=v89) - block 27 start_pc=0 + terminator Jmp(b22) (exit_acc=v87) + block 22 start_pc=0 v90 LoadLocal { off=-11, kind=F64 } -> d1 v91 Binop { op=fadd, lhs=v81, rhs=v90 } -> d0 v92 FpCast { kind=FpToInt, value=v91 } -> x0 @@ -156,22 +136,42 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v96 Imm(4611686018427387904) -> x0 v97 Fneg(v96) -> d1 v98 Binop { op=fne, lhs=v93, rhs=v97 } -> x0 - terminator Bz { cond=v98, target=b29, fall=b28 } (exit_acc=v98) - block 28 start_pc=0 + terminator Bz { cond=v98, target=b24, fall=b23 } (exit_acc=v98) + block 23 start_pc=0 v99 Imm(7) -> x0 terminator Return(v99) (exit_acc=v99) - block 29 start_pc=0 + block 24 start_pc=0 v100 Imm(7) -> x0 - v101 Imm(0) -> x1 - v102 LoadLocal { off=-6, kind=I32 } -> x1 - v103 BinopI { op=ne, lhs=v100, rhs_imm=7 } -> x0 - terminator Bz { cond=v103, target=b31, fall=b30 } (exit_acc=v103) + v101 Imm(0) -> x0 + v102 LoadLocal { off=-6, kind=I32 } -> x0 + v103 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v103) + block 25 start_pc=0 + v105 Imm(0) -> x0 + terminator Return(v105) (exit_acc=v105) + block 26 start_pc=0 + v88 Imm(4602678819172646912) -> x0 + v89 StoreLocal { off=-11, value=v88, kind=F64 } -> - + terminator Jmp(b22) (exit_acc=v89) + block 27 start_pc=0 + v67 Imm(4602678819172646912) -> x0 + v68 StoreLocal { off=-10, value=v67, kind=F64 } -> - + terminator Jmp(b18) (exit_acc=v68) + block 28 start_pc=0 + v51 Imm(4602678819172646912) -> x0 + v52 StoreLocal { off=-9, value=v51, kind=F64 } -> - + terminator Jmp(b14) (exit_acc=v52) + block 29 start_pc=0 + v37 Imm(4602678819172646912) -> x0 + v38 StoreLocal { off=-8, value=v37, kind=F64 } -> - + terminator Jmp(b10) (exit_acc=v38) block 30 start_pc=0 + v16 Imm(4602678819172646912) -> x0 + v17 StoreLocal { off=-7, value=v16, kind=F64 } -> - + terminator Jmp(b4) (exit_acc=v17) + block 31 start_pc=0 v104 Imm(8) -> x0 terminator Return(v104) (exit_acc=v104) - block 31 start_pc=0 - v105 Imm(0) -> x0 - terminator Return(v105) (exit_acc=v105) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unary_plus_preserves_type.ssa b/tests/snapshots/ssa/unary_plus_preserves_type.ssa index 717b21c8e..9d70d3349 100644 --- a/tests/snapshots/ssa/unary_plus_preserves_type.ssa +++ b/tests/snapshots/ssa/unary_plus_preserves_type.ssa @@ -5,38 +5,38 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - v2 Imm(0) -> x1 - v3 Imm(-1) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I64 } -> x2 - v6 LoadLocal { off=-2, kind=I8 } -> x2 - v7 Binop { op=uge, lhs=v1, rhs=v3 } -> x2 - v8 BinopI { op=ne, lhs=v7, rhs_imm=0 } -> x2 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v2 Imm(0) -> x0 + v3 Imm(-1) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I64 } -> x0 + v6 LoadLocal { off=-2, kind=I8 } -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 - v9 Imm(1) -> x0 - terminator Return(v9) (exit_acc=v9) + v10 LoadLocal { off=-1, kind=I64 } -> x0 + v11 LoadLocal { off=-2, kind=I8 } -> x0 + v12 Imm(0) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v10 LoadLocal { off=-1, kind=I64 } -> x2 - v11 LoadLocal { off=-2, kind=I8 } -> x2 - v12 Binop { op=uge, lhs=v1, rhs=v3 } -> x0 - v13 BinopI { op=ne, lhs=v12, rhs_imm=0 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v15 Imm(4294967296) -> x0 + v16 Imm(0) -> x0 + v17 LoadLocal { off=-3, kind=I64 } -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v18) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v20 Imm(0) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v15 Imm(4294967296) -> x0 - v16 Imm(0) -> x1 - v17 LoadLocal { off=-3, kind=I64 } -> x1 - v18 BinopI { op=ne, lhs=v15, rhs_imm=4294967296 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 5 start_pc=0 + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) + block 6 start_pc=0 v19 Imm(3) -> x0 terminator Return(v19) (exit_acc=v19) - block 6 start_pc=0 - v20 Imm(0) -> x0 - terminator Return(v20) (exit_acc=v20) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/union_bitfield_layout.ssa b/tests/snapshots/ssa/union_bitfield_layout.ssa index 074ec4a70..461e2bb31 100644 --- a/tests/snapshots/ssa/union_bitfield_layout.ssa +++ b/tests/snapshots/ssa/union_bitfield_layout.ssa @@ -5,50 +5,35 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(11) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) - block 3 start_pc=0 - v4 Imm(12) -> x0 - terminator Return(v4) (exit_acc=v4) - block 4 start_pc=0 + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) - block 5 start_pc=0 - v6 Imm(13) -> x0 - terminator Return(v6) (exit_acc=v6) - block 6 start_pc=0 + terminator Jmp(b3) (exit_acc=v5) + block 3 start_pc=0 v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) - block 7 start_pc=0 - v8 Imm(14) -> x0 - terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 + terminator Jmp(b4) (exit_acc=v7) + block 4 start_pc=0 v9 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v9) - block 9 start_pc=0 - v10 Imm(21) -> x0 - terminator Return(v10) (exit_acc=v10) - block 10 start_pc=0 + terminator Jmp(b5) (exit_acc=v9) + block 5 start_pc=0 v11 LocalAddr(-1) -> x0 v12 Imm(0) -> x1 v13 Imm(5) -> x1 - v14 Load { addr=v11, disp=0, kind=U32 } -> x2 - v15 BinopI { op=and, lhs=v14, rhs_imm=-16 } -> x2 - v16 Binop { op=or, lhs=v15, rhs=v13 } -> x1 + v14 Load { addr=v11, disp=0, kind=U32 } -> x1 + v15 BinopI { op=and, lhs=v14, rhs_imm=-16 } -> x1 + v16 BinopI { op=or, lhs=v15, rhs_imm=5 } -> x1 v17 Store { addr=v11, disp=0, value=v16, kind=I32 } -> - v18 Imm(5764607523034234880) -> x0 v19 LocalAddr(-1) -> x0 v20 Imm(4) -> x1 v21 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x1 v22 Imm(3) -> x1 - v23 Load { addr=v19, disp=4, kind=U32 } -> x2 - v24 BinopI { op=and, lhs=v23, rhs_imm=-16 } -> x2 - v25 Binop { op=or, lhs=v24, rhs=v22 } -> x1 + v23 Load { addr=v19, disp=4, kind=U32 } -> x1 + v24 BinopI { op=and, lhs=v23, rhs_imm=-16 } -> x1 + v25 BinopI { op=or, lhs=v24, rhs_imm=3 } -> x1 v26 Store { addr=v19, disp=4, value=v25, kind=I32 } -> - v27 Imm(3458764513820540928) -> x0 v28 LocalAddr(-1) -> x0 @@ -57,11 +42,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 v31 BinopI { op=shl, lhs=v30, rhs_imm=60 } -> x0 v32 BinopI { op=shr, lhs=v31, rhs_imm=60 } -> x0 v33 BinopI { op=ne, lhs=v32, rhs_imm=5 } -> x0 - terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) - block 11 start_pc=0 + terminator Bz { cond=v33, target=b7, fall=b6 } (exit_acc=v33) + block 6 start_pc=0 v34 Imm(31) -> x0 terminator Return(v34) (exit_acc=v34) - block 12 start_pc=0 + block 7 start_pc=0 v35 LocalAddr(-1) -> x0 v36 Imm(4) -> x1 v37 BinopI { op=add, lhs=v35, rhs_imm=4 } -> x1 @@ -70,13 +55,28 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 v40 BinopI { op=shl, lhs=v39, rhs_imm=60 } -> x0 v41 BinopI { op=shr, lhs=v40, rhs_imm=60 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=3 } -> x0 - terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) - block 13 start_pc=0 + terminator Bz { cond=v42, target=b9, fall=b8 } (exit_acc=v42) + block 8 start_pc=0 v43 Imm(32) -> x0 terminator Return(v43) (exit_acc=v43) - block 14 start_pc=0 + block 9 start_pc=0 v44 Imm(0) -> x0 terminator Return(v44) (exit_acc=v44) + block 10 start_pc=0 + v2 Imm(11) -> x0 + terminator Return(v2) (exit_acc=v2) + block 11 start_pc=0 + v4 Imm(12) -> x0 + terminator Return(v4) (exit_acc=v4) + block 12 start_pc=0 + v6 Imm(13) -> x0 + terminator Return(v6) (exit_acc=v6) + block 13 start_pc=0 + v8 Imm(14) -> x0 + terminator Return(v8) (exit_acc=v8) + block 14 start_pc=0 + v10 Imm(21) -> x0 + terminator Return(v10) (exit_acc=v10) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/union_fp_member_regs_return.ssa b/tests/snapshots/ssa/union_fp_member_regs_return.ssa index 62b1f8933..e0a63cee4 100644 --- a/tests/snapshots/ssa/union_fp_member_regs_return.ssa +++ b/tests/snapshots/ssa/union_fp_member_regs_return.ssa @@ -68,10 +68,10 @@ fn ent_pc=2 n_params=0 variadic=false locals=19 terminator Return(v21) (exit_acc=v21) block 4 start_pc=0 v22 Imm(4660) -> x0 - v23 Extend { value=v22, kind=I32 } -> x1 + v23 Imm(4660) -> x0 v24 Imm(0) -> x1 v25 LocalAddr(-17) -> x1 - v26 Store { addr=v25, disp=0, value=v22, kind=I32 } -> - + v26 Store { addr=v25, disp=0, value=v23, kind=I32 } -> - v27 LocalAddr(-17) -> x0 v28 BinopI { op=add, lhs=v27, rhs_imm=8 } -> x1 v29 Imm(22) -> x1 diff --git a/tests/snapshots/ssa/union_member_unbraced_init.ssa b/tests/snapshots/ssa/union_member_unbraced_init.ssa index c22c61c12..51e1a180c 100644 --- a/tests/snapshots/ssa/union_member_unbraced_init.ssa +++ b/tests/snapshots/ssa/union_member_unbraced_init.ssa @@ -9,7 +9,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v3 Imm(4613937818241073152) -> x1 v4 Binop { op=fne, lhs=v2, rhs=v3 } -> x2 v5 Imm(0) -> x1 - terminator Bnz { cond=v4, target=b37, fall=b1 } (exit_acc=v4) + terminator Bnz { cond=v4, target=b43, fall=b1 } (exit_acc=v4) block 1 start_pc=0 v6 ImmData(8) -> x1 v7 BinopI { op=add, lhs=v1, rhs_imm=16 } -> x1 @@ -18,7 +18,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v10 Imm(0) -> x1 terminator Jmp(b2) (exit_acc=v9) block 2 start_pc=0 - v11 Phi { incoming=[b37:v4, b1:v9], kind=I64 } -> x2 + v11 Phi { incoming=[b43:v4, b1:v9], kind=I64 } -> x2 v12 LoadLocal { off=-8, kind=I64 } -> x1 terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) block 3 start_pc=0 @@ -27,108 +27,103 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 block 4 start_pc=0 v14 Imm(8) -> x2 v15 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v14) + terminator Jmp(b7) (exit_acc=v14) block 5 start_pc=0 - v16 Phi { incoming=[b4:v14, b6:v20], kind=I64 } -> x2 - v17 Extend { value=v16, kind=I32 } -> x1 - v18 BinopI { op=lt, lhs=v17, rhs_imm=16 } -> x1 - terminator Bz { cond=v18, target=b8, fall=b7 } (exit_acc=v18) + v22 ImmData(8) -> x6 + v23 Extend { value=v16, kind=I32 } -> x6 + v24 Binop { op=add, lhs=v1, rhs=v17 } -> x6 + v25 Load { addr=v24, disp=0, kind=I8 } -> x6 + v26 BinopI { op=ne, lhs=v25, rhs_imm=0 } -> x6 + terminator Bnz { cond=v26, target=b42, fall=b6 } (exit_acc=v26) block 6 start_pc=0 - v19 Extend { value=v16, kind=I32 } -> x1 - v20 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x2 + v19 Extend { value=v16, kind=I32 } -> x2 + v20 BinopI { op=add, lhs=v17, rhs_imm=1 } -> x2 v21 Imm(0) -> x1 - terminator Jmp(b5) (exit_acc=v20) + terminator Jmp(b7) (exit_acc=v20) block 7 start_pc=0 - v22 ImmData(8) -> x1 - v23 Extend { value=v16, kind=I32 } -> x1 - v24 Binop { op=add, lhs=v1, rhs=v23 } -> x1 - v25 Load { addr=v24, disp=0, kind=I8 } -> x1 - v26 BinopI { op=ne, lhs=v25, rhs_imm=0 } -> x1 - terminator Bz { cond=v26, target=b10, fall=b9 } (exit_acc=v26) + v16 Phi { incoming=[b4:v14, b6:v20], kind=I64 } -> x2 + v17 Extend { value=v16, kind=I32 } -> x1 + v18 BinopI { op=lt, lhs=v17, rhs_imm=16 } -> x6 + terminator Bnz { cond=v18, target=b5, fall=b8 } (exit_acc=v18) block 8 start_pc=0 v27 ImmData(32) -> x0 v28 Load { addr=v27, disp=0, kind=F64 } -> d0 v29 Imm(4617315517961601024) -> x0 v30 Binop { op=fne, lhs=v28, rhs=v29 } -> x1 v31 Imm(0) -> x0 - terminator Bnz { cond=v30, target=b38, fall=b11 } (exit_acc=v30) + terminator Bnz { cond=v30, target=b41, fall=b9 } (exit_acc=v30) block 9 start_pc=0 - v32 Imm(2) -> x0 - terminator Return(v32) (exit_acc=v32) - block 10 start_pc=0 - terminator Jmp(b6) - block 11 start_pc=0 v33 ImmData(32) -> x0 v34 BinopI { op=add, lhs=v33, rhs_imm=8 } -> x1 v35 Load { addr=v33, disp=8, kind=I32 } -> x0 v36 BinopI { op=ne, lhs=v35, rhs_imm=43 } -> x1 v37 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v36) - block 12 start_pc=0 - v38 Phi { incoming=[b38:v30, b11:v36], kind=I64 } -> x1 + terminator Jmp(b10) (exit_acc=v36) + block 10 start_pc=0 + v38 Phi { incoming=[b41:v30, b9:v36], kind=I64 } -> x1 v39 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v38, target=b14, fall=b13 } (exit_acc=v38) - block 13 start_pc=0 + terminator Bz { cond=v38, target=b12, fall=b11 } (exit_acc=v38) + block 11 start_pc=0 v40 Imm(3) -> x0 terminator Return(v40) (exit_acc=v40) - block 14 start_pc=0 + block 12 start_pc=0 v41 ImmData(48) -> x0 v42 Load { addr=v41, disp=0, kind=I32 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=1 } -> x0 v44 Imm(1) -> x2 v45 Imm(0) -> x1 - terminator Bnz { cond=v43, target=b39, fall=b15 } (exit_acc=v43) - block 15 start_pc=0 + terminator Bnz { cond=v43, target=b40, fall=b13 } (exit_acc=v43) + block 13 start_pc=0 v46 ImmData(48) -> x0 v47 BinopI { op=add, lhs=v46, rhs_imm=4 } -> x1 v48 Load { addr=v46, disp=4, kind=I32 } -> x0 v49 BinopI { op=ne, lhs=v48, rhs_imm=2 } -> x0 v50 BinopI { op=ne, lhs=v49, rhs_imm=0 } -> x2 v51 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v50) - block 16 start_pc=0 - v52 Phi { incoming=[b39:v44, b15:v50], kind=I64 } -> x2 + terminator Jmp(b14) (exit_acc=v50) + block 14 start_pc=0 + v52 Phi { incoming=[b40:v44, b13:v50], kind=I64 } -> x2 v53 LoadLocal { off=-11, kind=I64 } -> x0 v54 Imm(0) -> x0 - terminator Bnz { cond=v52, target=b40, fall=b17 } (exit_acc=v52) - block 17 start_pc=0 + terminator Bnz { cond=v52, target=b39, fall=b15 } (exit_acc=v52) + block 15 start_pc=0 v55 ImmData(48) -> x0 v56 BinopI { op=add, lhs=v55, rhs_imm=8 } -> x1 v57 Load { addr=v55, disp=8, kind=I32 } -> x0 v58 BinopI { op=ne, lhs=v57, rhs_imm=9 } -> x2 v59 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v58) - block 18 start_pc=0 - v60 Phi { incoming=[b40:v52, b17:v58], kind=I64 } -> x2 + terminator Jmp(b16) (exit_acc=v58) + block 16 start_pc=0 + v60 Phi { incoming=[b39:v52, b15:v58], kind=I64 } -> x2 v61 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v60, target=b20, fall=b19 } (exit_acc=v60) - block 19 start_pc=0 + terminator Bz { cond=v60, target=b18, fall=b17 } (exit_acc=v60) + block 17 start_pc=0 v62 Imm(4) -> x0 terminator Return(v62) (exit_acc=v62) - block 20 start_pc=0 + block 18 start_pc=0 v63 ImmData(64) -> x0 v64 Imm(0) -> x1 v65 Load { addr=v63, disp=0, kind=F64 } -> d0 v66 Imm(4613937818241073152) -> x0 v67 Binop { op=fne, lhs=v65, rhs=v66 } -> x1 v68 Imm(0) -> x0 - terminator Bnz { cond=v67, target=b41, fall=b21 } (exit_acc=v67) - block 21 start_pc=0 + terminator Bnz { cond=v67, target=b38, fall=b19 } (exit_acc=v67) + block 19 start_pc=0 v69 ImmData(64) -> x0 v70 Imm(0) -> x1 v71 BinopI { op=add, lhs=v69, rhs_imm=16 } -> x1 v72 Load { addr=v69, disp=16, kind=I32 } -> x0 v73 BinopI { op=ne, lhs=v72, rhs_imm=42 } -> x1 v74 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v73) - block 22 start_pc=0 - v75 Phi { incoming=[b41:v67, b21:v73], kind=I64 } -> x1 + terminator Jmp(b20) (exit_acc=v73) + block 20 start_pc=0 + v75 Phi { incoming=[b38:v67, b19:v73], kind=I64 } -> x1 v76 LoadLocal { off=-12, kind=I64 } -> x0 - terminator Bz { cond=v75, target=b24, fall=b23 } (exit_acc=v75) - block 23 start_pc=0 + terminator Bz { cond=v75, target=b22, fall=b21 } (exit_acc=v75) + block 21 start_pc=0 v77 Imm(5) -> x0 terminator Return(v77) (exit_acc=v77) - block 24 start_pc=0 + block 22 start_pc=0 v78 ImmData(64) -> x0 v79 Imm(24) -> x1 v80 BinopI { op=add, lhs=v78, rhs_imm=24 } -> x1 @@ -136,8 +131,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v82 Imm(4616189618054758400) -> x0 v83 Binop { op=fne, lhs=v81, rhs=v82 } -> x1 v84 Imm(0) -> x0 - terminator Bnz { cond=v83, target=b42, fall=b25 } (exit_acc=v83) - block 25 start_pc=0 + terminator Bnz { cond=v83, target=b37, fall=b23 } (exit_acc=v83) + block 23 start_pc=0 v85 ImmData(64) -> x0 v86 Imm(24) -> x1 v87 BinopI { op=add, lhs=v85, rhs_imm=24 } -> x1 @@ -145,15 +140,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v89 Load { addr=v85, disp=40, kind=I32 } -> x0 v90 BinopI { op=ne, lhs=v89, rhs_imm=43 } -> x1 v91 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v90) - block 26 start_pc=0 - v92 Phi { incoming=[b42:v83, b25:v90], kind=I64 } -> x1 + terminator Jmp(b24) (exit_acc=v90) + block 24 start_pc=0 + v92 Phi { incoming=[b37:v83, b23:v90], kind=I64 } -> x1 v93 LoadLocal { off=-13, kind=I64 } -> x0 - terminator Bz { cond=v92, target=b28, fall=b27 } (exit_acc=v92) - block 27 start_pc=0 + terminator Bz { cond=v92, target=b26, fall=b25 } (exit_acc=v92) + block 25 start_pc=0 v94 Imm(6) -> x0 terminator Return(v94) (exit_acc=v94) - block 28 start_pc=0 + block 26 start_pc=0 v95 LocalAddr(-4) -> x0 v96 ImmData(112) -> x1 v97 Mcpy { dst=v95, src=v96, size=24 } -> x0 @@ -162,22 +157,22 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v100 Imm(4613937818241073152) -> x0 v101 Binop { op=fne, lhs=v99, rhs=v100 } -> x1 v102 Imm(0) -> x0 - terminator Bnz { cond=v101, target=b43, fall=b29 } (exit_acc=v101) - block 29 start_pc=0 + terminator Bnz { cond=v101, target=b36, fall=b27 } (exit_acc=v101) + block 27 start_pc=0 v103 LocalAddr(-4) -> x0 v104 BinopI { op=add, lhs=v103, rhs_imm=16 } -> x1 v105 Load { addr=v103, disp=16, kind=I32 } -> x0 v106 BinopI { op=ne, lhs=v105, rhs_imm=42 } -> x1 v107 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v106) - block 30 start_pc=0 - v108 Phi { incoming=[b43:v101, b29:v106], kind=I64 } -> x1 + terminator Jmp(b28) (exit_acc=v106) + block 28 start_pc=0 + v108 Phi { incoming=[b36:v101, b27:v106], kind=I64 } -> x1 v109 LoadLocal { off=-14, kind=I64 } -> x0 - terminator Bz { cond=v108, target=b32, fall=b31 } (exit_acc=v108) - block 31 start_pc=0 + terminator Bz { cond=v108, target=b30, fall=b29 } (exit_acc=v108) + block 29 start_pc=0 v110 Imm(7) -> x0 terminator Return(v110) (exit_acc=v110) - block 32 start_pc=0 + block 30 start_pc=0 v111 LocalAddr(-7) -> x0 v112 ImmData(136) -> x1 v113 Mcpy { dst=v111, src=v112, size=24 } -> x0 @@ -186,40 +181,45 @@ fn ent_pc=0 n_params=0 variadic=false locals=15 v116 Imm(4618441417868443648) -> x0 v117 Binop { op=fne, lhs=v115, rhs=v116 } -> x1 v118 Imm(0) -> x0 - terminator Bnz { cond=v117, target=b44, fall=b33 } (exit_acc=v117) - block 33 start_pc=0 + terminator Bnz { cond=v117, target=b35, fall=b31 } (exit_acc=v117) + block 31 start_pc=0 v119 LocalAddr(-7) -> x0 v120 BinopI { op=add, lhs=v119, rhs_imm=16 } -> x1 v121 Load { addr=v119, disp=16, kind=I32 } -> x0 v122 BinopI { op=ne, lhs=v121, rhs_imm=44 } -> x1 v123 Imm(0) -> x0 - terminator Jmp(b34) (exit_acc=v122) - block 34 start_pc=0 - v124 Phi { incoming=[b44:v117, b33:v122], kind=I64 } -> x1 + terminator Jmp(b32) (exit_acc=v122) + block 32 start_pc=0 + v124 Phi { incoming=[b35:v117, b31:v122], kind=I64 } -> x1 v125 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Bz { cond=v124, target=b36, fall=b35 } (exit_acc=v124) - block 35 start_pc=0 + terminator Bz { cond=v124, target=b34, fall=b33 } (exit_acc=v124) + block 33 start_pc=0 v126 Imm(8) -> x0 terminator Return(v126) (exit_acc=v126) - block 36 start_pc=0 + block 34 start_pc=0 v127 Imm(0) -> x0 terminator Return(v127) (exit_acc=v127) + block 35 start_pc=0 + terminator Jmp(b32) + block 36 start_pc=0 + terminator Jmp(b28) block 37 start_pc=0 - terminator Jmp(b2) + terminator Jmp(b24) block 38 start_pc=0 - terminator Jmp(b12) + terminator Jmp(b20) block 39 start_pc=0 terminator Jmp(b16) block 40 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b14) block 41 start_pc=0 - terminator Jmp(b22) + terminator Jmp(b10) block 42 start_pc=0 - terminator Jmp(b26) + v32 Imm(2) -> x0 + terminator Return(v32) (exit_acc=v32) block 43 start_pc=0 - terminator Jmp(b30) + terminator Jmp(b2) block 44 start_pc=0 - terminator Jmp(b34) + terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unions_basic.ssa b/tests/snapshots/ssa/unions_basic.ssa index e54af3516..f5eb48f38 100644 --- a/tests/snapshots/ssa/unions_basic.ssa +++ b/tests/snapshots/ssa/unions_basic.ssa @@ -63,11 +63,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 terminator Return(v38) (exit_acc=v38) block 10 start_pc=0 v39 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v39) + terminator Jmp(b11) (exit_acc=v39) block 11 start_pc=0 - v40 Imm(6) -> x0 - terminator Return(v40) (exit_acc=v40) - block 12 start_pc=0 v41 LocalAddr(-3) -> x0 v42 Imm(1) -> x1 v43 Store { addr=v41, disp=0, value=v42, kind=I32 } -> - @@ -78,20 +75,20 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v48 LocalAddr(-3) -> x0 v49 Load { addr=v48, disp=0, kind=I32 } -> x0 v50 BinopI { op=ne, lhs=v49, rhs_imm=1 } -> x0 - terminator Bz { cond=v50, target=b14, fall=b13 } (exit_acc=v50) - block 13 start_pc=0 + terminator Bz { cond=v50, target=b13, fall=b12 } (exit_acc=v50) + block 12 start_pc=0 v51 Imm(7) -> x0 terminator Return(v51) (exit_acc=v51) - block 14 start_pc=0 + block 13 start_pc=0 v52 LocalAddr(-3) -> x0 v53 BinopI { op=add, lhs=v52, rhs_imm=8 } -> x1 v54 Load { addr=v52, disp=8, kind=I32 } -> x0 v55 BinopI { op=ne, lhs=v54, rhs_imm=100 } -> x0 - terminator Bz { cond=v55, target=b16, fall=b15 } (exit_acc=v55) - block 15 start_pc=0 + terminator Bz { cond=v55, target=b15, fall=b14 } (exit_acc=v55) + block 14 start_pc=0 v56 Imm(8) -> x0 terminator Return(v56) (exit_acc=v56) - block 16 start_pc=0 + block 15 start_pc=0 v57 LocalAddr(-3) -> x0 v58 Imm(2) -> x1 v59 Store { addr=v57, disp=0, value=v58, kind=I32 } -> - @@ -102,30 +99,33 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 v64 LocalAddr(-3) -> x0 v65 Load { addr=v64, disp=0, kind=I32 } -> x0 v66 BinopI { op=ne, lhs=v65, rhs_imm=2 } -> x0 - terminator Bz { cond=v66, target=b18, fall=b17 } (exit_acc=v66) - block 17 start_pc=0 + terminator Bz { cond=v66, target=b17, fall=b16 } (exit_acc=v66) + block 16 start_pc=0 v67 Imm(9) -> x0 terminator Return(v67) (exit_acc=v67) - block 18 start_pc=0 + block 17 start_pc=0 v68 LocalAddr(-3) -> x0 v69 BinopI { op=add, lhs=v68, rhs_imm=8 } -> x1 v70 Load { addr=v68, disp=8, kind=I64 } -> x0 v71 Imm(0) -> x1 v72 Load { addr=v70, disp=0, kind=I8 } -> x0 v73 BinopI { op=ne, lhs=v72, rhs_imm=121 } -> x0 - terminator Bz { cond=v73, target=b20, fall=b19 } (exit_acc=v73) - block 19 start_pc=0 + terminator Bz { cond=v73, target=b19, fall=b18 } (exit_acc=v73) + block 18 start_pc=0 v74 Imm(10) -> x0 terminator Return(v74) (exit_acc=v74) - block 20 start_pc=0 + block 19 start_pc=0 v75 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v75) + terminator Jmp(b20) (exit_acc=v75) + block 20 start_pc=0 + v77 Imm(0) -> x0 + terminator Return(v77) (exit_acc=v77) block 21 start_pc=0 + v40 Imm(6) -> x0 + terminator Return(v40) (exit_acc=v40) + block 22 start_pc=0 v76 Imm(11) -> x0 terminator Return(v76) (exit_acc=v76) - block 22 start_pc=0 - v77 Imm(0) -> x0 - terminator Return(v77) (exit_acc=v77) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unistd_exposes_posix_types.ssa b/tests/snapshots/ssa/unistd_exposes_posix_types.ssa index f938077ff..b59362c5e 100644 --- a/tests/snapshots/ssa/unistd_exposes_posix_types.ssa +++ b/tests/snapshots/ssa/unistd_exposes_posix_types.ssa @@ -23,43 +23,43 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 v11 Imm(5) -> x0 v12 Imm(0) -> x0 v13 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v13) + terminator Jmp(b1) (exit_acc=v13) block 1 start_pc=0 - v14 Imm(11) -> x0 - terminator Return(v14) (exit_acc=v14) - block 2 start_pc=0 v15 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v15) + terminator Jmp(b2) (exit_acc=v15) + block 2 start_pc=0 + v17 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v17) block 3 start_pc=0 - v16 Imm(12) -> x0 - terminator Return(v16) (exit_acc=v16) + v19 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v19) block 4 start_pc=0 - v17 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v17) + v21 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v21) block 5 start_pc=0 - v18 Imm(13) -> x0 - terminator Return(v18) (exit_acc=v18) + v23 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v23) block 6 start_pc=0 - v19 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v19) + v25 Imm(0) -> x0 + terminator Return(v25) (exit_acc=v25) block 7 start_pc=0 - v20 Imm(14) -> x0 - terminator Return(v20) (exit_acc=v20) + v14 Imm(11) -> x0 + terminator Return(v14) (exit_acc=v14) block 8 start_pc=0 - v21 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v21) + v16 Imm(12) -> x0 + terminator Return(v16) (exit_acc=v16) block 9 start_pc=0 - v22 Imm(15) -> x0 - terminator Return(v22) (exit_acc=v22) + v18 Imm(13) -> x0 + terminator Return(v18) (exit_acc=v18) block 10 start_pc=0 - v23 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v23) + v20 Imm(14) -> x0 + terminator Return(v20) (exit_acc=v20) block 11 start_pc=0 + v22 Imm(15) -> x0 + terminator Return(v22) (exit_acc=v22) + block 12 start_pc=0 v24 Imm(16) -> x0 terminator Return(v24) (exit_acc=v24) - block 12 start_pc=0 - v25 Imm(0) -> x0 - terminator Return(v25) (exit_acc=v25) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unroll_const_trip_copy.ssa b/tests/snapshots/ssa/unroll_const_trip_copy.ssa new file mode 100644 index 000000000..5d2d760ac --- /dev/null +++ b/tests/snapshots/ssa/unroll_const_trip_copy.ssa @@ -0,0 +1,491 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + v2 Imm(0) -> x1 + v3 Imm(0) -> x1 + terminator Jmp(b1) (exit_acc=v1) + block 1 start_pc=0 + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 Imm(1) -> x0 + v6 ImmData(24) -> x0 + v7 LoadLocal { off=-1, kind=I64 } -> x1 + v8 Imm(0) -> x1 + v9 BinopI { op=add, lhs=v6, rhs_imm=0 } -> x0 + v10 Imm(0) -> x1 + v11 Imm(1) -> x1 + v12 Store { addr=v9, disp=0, value=v11, kind=I64 } -> - + v13 LoadLocal { off=-1, kind=I64 } -> x0 + v14 Imm(1) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-1, kind=I64 } -> x0 + v17 Imm(1) -> x0 + v18 ImmData(24) -> x0 + v19 LoadLocal { off=-1, kind=I64 } -> x1 + v20 Imm(8) -> x1 + v21 BinopI { op=add, lhs=v18, rhs_imm=8 } -> x1 + v22 Imm(3) -> x1 + v23 Imm(4) -> x1 + v24 Store { addr=v18, disp=8, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-1, kind=I64 } -> x0 + v26 Imm(2) -> x0 + v27 Imm(0) -> x0 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + v29 Imm(1) -> x0 + v30 ImmData(24) -> x0 + v31 LoadLocal { off=-1, kind=I64 } -> x1 + v32 Imm(16) -> x1 + v33 BinopI { op=add, lhs=v30, rhs_imm=16 } -> x1 + v34 Imm(6) -> x1 + v35 Imm(7) -> x1 + v36 Store { addr=v30, disp=16, value=v35, kind=I64 } -> - + v37 LoadLocal { off=-1, kind=I64 } -> x0 + v38 Imm(3) -> x0 + v39 Imm(0) -> x0 + v40 LoadLocal { off=-1, kind=I64 } -> x0 + v41 Imm(1) -> x0 + v42 ImmData(24) -> x0 + v43 LoadLocal { off=-1, kind=I64 } -> x1 + v44 Imm(24) -> x1 + v45 BinopI { op=add, lhs=v42, rhs_imm=24 } -> x1 + v46 Imm(9) -> x1 + v47 Imm(10) -> x1 + v48 Store { addr=v42, disp=24, value=v47, kind=I64 } -> - + v49 LoadLocal { off=-1, kind=I64 } -> x0 + v50 Imm(4) -> x0 + v51 Imm(0) -> x0 + v52 LoadLocal { off=-1, kind=I64 } -> x0 + v53 Imm(1) -> x0 + v54 ImmData(24) -> x0 + v55 LoadLocal { off=-1, kind=I64 } -> x1 + v56 Imm(32) -> x1 + v57 BinopI { op=add, lhs=v54, rhs_imm=32 } -> x1 + v58 Imm(12) -> x1 + v59 Imm(13) -> x1 + v60 Store { addr=v54, disp=32, value=v59, kind=I64 } -> - + v61 LoadLocal { off=-1, kind=I64 } -> x0 + v62 Imm(5) -> x0 + v63 Imm(0) -> x0 + v64 LoadLocal { off=-1, kind=I64 } -> x0 + v65 Imm(1) -> x0 + v66 ImmData(24) -> x0 + v67 LoadLocal { off=-1, kind=I64 } -> x1 + v68 Imm(40) -> x1 + v69 BinopI { op=add, lhs=v66, rhs_imm=40 } -> x1 + v70 Imm(15) -> x1 + v71 Imm(16) -> x1 + v72 Store { addr=v66, disp=40, value=v71, kind=I64 } -> - + v73 LoadLocal { off=-1, kind=I64 } -> x0 + v74 Imm(6) -> x0 + v75 Imm(0) -> x0 + v76 LoadLocal { off=-1, kind=I64 } -> x0 + v77 Imm(1) -> x0 + v78 ImmData(24) -> x0 + v79 LoadLocal { off=-1, kind=I64 } -> x1 + v80 Imm(48) -> x1 + v81 BinopI { op=add, lhs=v78, rhs_imm=48 } -> x1 + v82 Imm(18) -> x1 + v83 Imm(19) -> x1 + v84 Store { addr=v78, disp=48, value=v83, kind=I64 } -> - + v85 LoadLocal { off=-1, kind=I64 } -> x0 + v86 Imm(7) -> x0 + v87 Imm(0) -> x0 + v88 LoadLocal { off=-1, kind=I64 } -> x0 + v89 Imm(1) -> x0 + v90 ImmData(24) -> x0 + v91 LoadLocal { off=-1, kind=I64 } -> x1 + v92 Imm(56) -> x1 + v93 BinopI { op=add, lhs=v90, rhs_imm=56 } -> x1 + v94 Imm(21) -> x1 + v95 Imm(22) -> x1 + v96 Store { addr=v90, disp=56, value=v95, kind=I64 } -> - + v97 LoadLocal { off=-1, kind=I64 } -> x0 + v98 Imm(8) -> x0 + v99 Imm(0) -> x0 + v100 LoadLocal { off=-1, kind=I64 } -> x0 + v101 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v101) + block 2 start_pc=0 + v102 Imm(0) -> x0 + v103 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v102) + block 3 start_pc=0 + v104 LoadLocal { off=-1, kind=I64 } -> x0 + v105 Imm(1) -> x0 + v106 ImmData(88) -> x0 + v107 LoadLocal { off=-1, kind=I64 } -> x1 + v108 Imm(0) -> x1 + v109 BinopI { op=add, lhs=v106, rhs_imm=0 } -> x0 + v110 ImmData(24) -> x1 + v111 BinopI { op=add, lhs=v110, rhs_imm=0 } -> x1 + v112 Load { addr=v111, disp=0, kind=I64 } -> x1 + v113 Store { addr=v109, disp=0, value=v112, kind=I64 } -> - + v114 LoadLocal { off=-1, kind=I64 } -> x0 + v115 Imm(1) -> x0 + v116 Imm(0) -> x0 + v117 LoadLocal { off=-1, kind=I64 } -> x0 + v118 Imm(1) -> x0 + v119 ImmData(88) -> x0 + v120 LoadLocal { off=-1, kind=I64 } -> x1 + v121 Imm(8) -> x1 + v122 BinopI { op=add, lhs=v119, rhs_imm=8 } -> x1 + v123 ImmData(24) -> x1 + v124 BinopI { op=add, lhs=v123, rhs_imm=8 } -> x2 + v125 Load { addr=v123, disp=8, kind=I64 } -> x1 + v126 Store { addr=v119, disp=8, value=v125, kind=I64 } -> - + v127 LoadLocal { off=-1, kind=I64 } -> x0 + v128 Imm(2) -> x0 + v129 Imm(0) -> x0 + v130 LoadLocal { off=-1, kind=I64 } -> x0 + v131 Imm(1) -> x0 + v132 ImmData(88) -> x0 + v133 LoadLocal { off=-1, kind=I64 } -> x1 + v134 Imm(16) -> x1 + v135 BinopI { op=add, lhs=v132, rhs_imm=16 } -> x1 + v136 ImmData(24) -> x1 + v137 BinopI { op=add, lhs=v136, rhs_imm=16 } -> x2 + v138 Load { addr=v136, disp=16, kind=I64 } -> x1 + v139 Store { addr=v132, disp=16, value=v138, kind=I64 } -> - + v140 LoadLocal { off=-1, kind=I64 } -> x0 + v141 Imm(3) -> x0 + v142 Imm(0) -> x0 + v143 LoadLocal { off=-1, kind=I64 } -> x0 + v144 Imm(1) -> x0 + v145 ImmData(88) -> x0 + v146 LoadLocal { off=-1, kind=I64 } -> x1 + v147 Imm(24) -> x1 + v148 BinopI { op=add, lhs=v145, rhs_imm=24 } -> x1 + v149 ImmData(24) -> x1 + v150 BinopI { op=add, lhs=v149, rhs_imm=24 } -> x2 + v151 Load { addr=v149, disp=24, kind=I64 } -> x1 + v152 Store { addr=v145, disp=24, value=v151, kind=I64 } -> - + v153 LoadLocal { off=-1, kind=I64 } -> x0 + v154 Imm(4) -> x0 + v155 Imm(0) -> x0 + v156 LoadLocal { off=-1, kind=I64 } -> x0 + v157 Imm(1) -> x0 + v158 ImmData(88) -> x0 + v159 LoadLocal { off=-1, kind=I64 } -> x1 + v160 Imm(32) -> x1 + v161 BinopI { op=add, lhs=v158, rhs_imm=32 } -> x1 + v162 ImmData(24) -> x1 + v163 BinopI { op=add, lhs=v162, rhs_imm=32 } -> x2 + v164 Load { addr=v162, disp=32, kind=I64 } -> x1 + v165 Store { addr=v158, disp=32, value=v164, kind=I64 } -> - + v166 LoadLocal { off=-1, kind=I64 } -> x0 + v167 Imm(5) -> x0 + v168 Imm(0) -> x0 + v169 LoadLocal { off=-1, kind=I64 } -> x0 + v170 Imm(1) -> x0 + v171 ImmData(88) -> x0 + v172 LoadLocal { off=-1, kind=I64 } -> x1 + v173 Imm(40) -> x1 + v174 BinopI { op=add, lhs=v171, rhs_imm=40 } -> x1 + v175 ImmData(24) -> x1 + v176 BinopI { op=add, lhs=v175, rhs_imm=40 } -> x2 + v177 Load { addr=v175, disp=40, kind=I64 } -> x1 + v178 Store { addr=v171, disp=40, value=v177, kind=I64 } -> - + v179 LoadLocal { off=-1, kind=I64 } -> x0 + v180 Imm(6) -> x0 + v181 Imm(0) -> x0 + v182 LoadLocal { off=-1, kind=I64 } -> x0 + v183 Imm(1) -> x0 + v184 ImmData(88) -> x0 + v185 LoadLocal { off=-1, kind=I64 } -> x1 + v186 Imm(48) -> x1 + v187 BinopI { op=add, lhs=v184, rhs_imm=48 } -> x1 + v188 ImmData(24) -> x1 + v189 BinopI { op=add, lhs=v188, rhs_imm=48 } -> x2 + v190 Load { addr=v188, disp=48, kind=I64 } -> x1 + v191 Store { addr=v184, disp=48, value=v190, kind=I64 } -> - + v192 LoadLocal { off=-1, kind=I64 } -> x0 + v193 Imm(7) -> x0 + v194 Imm(0) -> x0 + v195 LoadLocal { off=-1, kind=I64 } -> x0 + v196 Imm(1) -> x0 + v197 ImmData(88) -> x0 + v198 LoadLocal { off=-1, kind=I64 } -> x1 + v199 Imm(56) -> x1 + v200 BinopI { op=add, lhs=v197, rhs_imm=56 } -> x1 + v201 ImmData(24) -> x1 + v202 BinopI { op=add, lhs=v201, rhs_imm=56 } -> x2 + v203 Load { addr=v201, disp=56, kind=I64 } -> x1 + v204 Store { addr=v197, disp=56, value=v203, kind=I64 } -> - + v205 LoadLocal { off=-1, kind=I64 } -> x0 + v206 Imm(8) -> x0 + v207 Imm(0) -> x0 + v208 LoadLocal { off=-1, kind=I64 } -> x0 + v209 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v209) + block 4 start_pc=0 + v210 Imm(0) -> x0 + v211 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v210) + block 5 start_pc=0 + v212 LoadLocal { off=-1, kind=I64 } -> x0 + v213 Imm(1) -> x0 + v214 LoadLocal { off=-2, kind=I64 } -> x0 + v215 ImmData(88) -> x0 + v216 LoadLocal { off=-1, kind=I64 } -> x1 + v217 Imm(1) -> x1 + v218 Imm(8) -> x1 + v219 Imm(0) -> x1 + v220 Imm(0) -> x1 + v221 Imm(1) -> x1 + v222 Imm(1) -> x1 + v223 Imm(1) -> x1 + v224 Imm(8) -> x1 + v225 BinopI { op=add, lhs=v215, rhs_imm=8 } -> x1 + v226 Load { addr=v215, disp=8, kind=I64 } -> x0 + v227 BinopI { op=mul, lhs=v226, rhs_imm=1 } -> x0 + v228 BinopI { op=add, lhs=v227, rhs_imm=0 } -> x0 + v229 Imm(0) -> x1 + v230 LoadLocal { off=-1, kind=I64 } -> x1 + v231 Imm(1) -> x1 + v232 Imm(0) -> x1 + v233 LoadLocal { off=-1, kind=I64 } -> x1 + v234 Imm(1) -> x1 + v235 LoadLocal { off=-2, kind=I64 } -> x1 + v236 ImmData(88) -> x1 + v237 LoadLocal { off=-1, kind=I64 } -> x2 + v238 Imm(2) -> x2 + v239 Imm(8) -> x2 + v240 Imm(0) -> x2 + v241 Imm(0) -> x2 + v242 Imm(2) -> x2 + v243 Imm(2) -> x2 + v244 Imm(2) -> x2 + v245 Imm(16) -> x2 + v246 BinopI { op=add, lhs=v236, rhs_imm=16 } -> x2 + v247 Load { addr=v236, disp=16, kind=I64 } -> x1 + v248 BinopI { op=mul, lhs=v247, rhs_imm=2 } -> x1 + v249 Binop { op=add, lhs=v228, rhs=v248 } -> x0 + v250 Imm(0) -> x1 + v251 LoadLocal { off=-1, kind=I64 } -> x1 + v252 Imm(2) -> x1 + v253 Imm(0) -> x1 + v254 LoadLocal { off=-1, kind=I64 } -> x1 + v255 Imm(1) -> x1 + v256 LoadLocal { off=-2, kind=I64 } -> x1 + v257 ImmData(88) -> x1 + v258 LoadLocal { off=-1, kind=I64 } -> x2 + v259 Imm(3) -> x2 + v260 Imm(8) -> x2 + v261 Imm(0) -> x2 + v262 Imm(0) -> x2 + v263 Imm(3) -> x2 + v264 Imm(3) -> x2 + v265 Imm(3) -> x2 + v266 Imm(24) -> x2 + v267 BinopI { op=add, lhs=v257, rhs_imm=24 } -> x2 + v268 Load { addr=v257, disp=24, kind=I64 } -> x1 + v269 BinopI { op=mul, lhs=v268, rhs_imm=3 } -> x1 + v270 Binop { op=add, lhs=v249, rhs=v269 } -> x0 + v271 Imm(0) -> x1 + v272 LoadLocal { off=-1, kind=I64 } -> x1 + v273 Imm(3) -> x1 + v274 Imm(0) -> x1 + v275 LoadLocal { off=-1, kind=I64 } -> x1 + v276 Imm(1) -> x1 + v277 LoadLocal { off=-2, kind=I64 } -> x1 + v278 ImmData(88) -> x1 + v279 LoadLocal { off=-1, kind=I64 } -> x2 + v280 Imm(4) -> x2 + v281 Imm(8) -> x2 + v282 Imm(0) -> x2 + v283 Imm(0) -> x2 + v284 Imm(4) -> x2 + v285 Imm(4) -> x2 + v286 Imm(4) -> x2 + v287 Imm(32) -> x2 + v288 BinopI { op=add, lhs=v278, rhs_imm=32 } -> x2 + v289 Load { addr=v278, disp=32, kind=I64 } -> x1 + v290 BinopI { op=mul, lhs=v289, rhs_imm=4 } -> x1 + v291 Binop { op=add, lhs=v270, rhs=v290 } -> x0 + v292 Imm(0) -> x1 + v293 LoadLocal { off=-1, kind=I64 } -> x1 + v294 Imm(4) -> x1 + v295 Imm(0) -> x1 + v296 LoadLocal { off=-1, kind=I64 } -> x1 + v297 Imm(1) -> x1 + v298 LoadLocal { off=-2, kind=I64 } -> x1 + v299 ImmData(88) -> x1 + v300 LoadLocal { off=-1, kind=I64 } -> x2 + v301 Imm(5) -> x2 + v302 Imm(8) -> x2 + v303 Imm(0) -> x2 + v304 Imm(0) -> x2 + v305 Imm(5) -> x2 + v306 Imm(5) -> x2 + v307 Imm(5) -> x2 + v308 Imm(40) -> x2 + v309 BinopI { op=add, lhs=v299, rhs_imm=40 } -> x2 + v310 Load { addr=v299, disp=40, kind=I64 } -> x1 + v311 BinopI { op=mul, lhs=v310, rhs_imm=5 } -> x1 + v312 Binop { op=add, lhs=v291, rhs=v311 } -> x0 + v313 Imm(0) -> x1 + v314 LoadLocal { off=-1, kind=I64 } -> x1 + v315 Imm(5) -> x1 + v316 Imm(0) -> x1 + v317 LoadLocal { off=-1, kind=I64 } -> x1 + v318 Imm(1) -> x1 + v319 LoadLocal { off=-2, kind=I64 } -> x1 + v320 ImmData(88) -> x1 + v321 LoadLocal { off=-1, kind=I64 } -> x2 + v322 Imm(6) -> x2 + v323 Imm(8) -> x2 + v324 Imm(0) -> x2 + v325 Imm(0) -> x2 + v326 Imm(6) -> x2 + v327 Imm(6) -> x2 + v328 Imm(6) -> x2 + v329 Imm(48) -> x2 + v330 BinopI { op=add, lhs=v320, rhs_imm=48 } -> x2 + v331 Load { addr=v320, disp=48, kind=I64 } -> x1 + v332 BinopI { op=mul, lhs=v331, rhs_imm=6 } -> x1 + v333 Binop { op=add, lhs=v312, rhs=v332 } -> x0 + v334 Imm(0) -> x1 + v335 LoadLocal { off=-1, kind=I64 } -> x1 + v336 Imm(6) -> x1 + v337 Imm(0) -> x1 + v338 LoadLocal { off=-1, kind=I64 } -> x1 + v339 Imm(1) -> x1 + v340 LoadLocal { off=-2, kind=I64 } -> x1 + v341 ImmData(88) -> x1 + v342 LoadLocal { off=-1, kind=I64 } -> x2 + v343 Imm(7) -> x2 + v344 Imm(8) -> x2 + v345 Imm(0) -> x2 + v346 Imm(0) -> x2 + v347 Imm(7) -> x2 + v348 Imm(7) -> x2 + v349 Imm(7) -> x2 + v350 Imm(56) -> x2 + v351 BinopI { op=add, lhs=v341, rhs_imm=56 } -> x2 + v352 Load { addr=v341, disp=56, kind=I64 } -> x1 + v353 BinopI { op=mul, lhs=v352, rhs_imm=7 } -> x1 + v354 Binop { op=add, lhs=v333, rhs=v353 } -> x0 + v355 Imm(0) -> x1 + v356 LoadLocal { off=-1, kind=I64 } -> x1 + v357 Imm(7) -> x1 + v358 Imm(0) -> x1 + v359 LoadLocal { off=-1, kind=I64 } -> x1 + v360 Imm(1) -> x1 + v361 LoadLocal { off=-2, kind=I64 } -> x1 + v362 ImmData(88) -> x1 + v363 LoadLocal { off=-1, kind=I64 } -> x2 + v364 Imm(8) -> x2 + v365 Imm(8) -> x2 + v366 Imm(0) -> x2 + v367 Imm(0) -> x2 + v368 Imm(8) -> x2 + v369 Imm(0) -> x2 + v370 Imm(0) -> x2 + v371 Imm(0) -> x2 + v372 BinopI { op=add, lhs=v362, rhs_imm=0 } -> x1 + v373 Load { addr=v372, disp=0, kind=I64 } -> x1 + v374 BinopI { op=mul, lhs=v373, rhs_imm=8 } -> x1 + v375 Binop { op=add, lhs=v354, rhs=v374 } -> x0 + v376 Imm(0) -> x1 + v377 LoadLocal { off=-1, kind=I64 } -> x1 + v378 Imm(8) -> x1 + v379 Imm(0) -> x1 + v380 LoadLocal { off=-1, kind=I64 } -> x1 + v381 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v381) + block 6 start_pc=0 + v382 LoadLocal { off=-2, kind=I64 } -> x1 + v383 Imm(4) -> x1 + v384 Imm(14) -> x1 + v385 Imm(60129542144) -> x1 + v386 Imm(18) -> x1 + v387 Imm(77309411328) -> x1 + v388 Imm(30) -> x1 + v389 Imm(128849018880) -> x1 + v390 Imm(48) -> x1 + v391 Imm(206158430208) -> x1 + v392 Imm(52) -> x1 + v393 Imm(223338299392) -> x1 + v394 Imm(100) -> x1 + v395 Imm(429496729600) -> x1 + v396 Imm(80) -> x1 + v397 Imm(343597383680) -> x1 + v398 Imm(180) -> x1 + v399 Imm(773094113280) -> x1 + v400 Imm(114) -> x1 + v401 Imm(489626271744) -> x1 + v402 Imm(294) -> x1 + v403 Imm(1262720385024) -> x1 + v404 Imm(154) -> x1 + v405 Imm(661424963584) -> x1 + v406 Imm(448) -> x1 + v407 Imm(1924145348608) -> x1 + v408 Imm(8) -> x1 + v409 Imm(34359738368) -> x1 + v410 Imm(456) -> x1 + v411 Imm(1958505086976) -> x1 + v412 BinopI { op=ne, lhs=v375, rhs_imm=456 } -> x0 + terminator Bz { cond=v412, target=b8, fall=b7 } (exit_acc=v412) + block 7 start_pc=0 + v413 Imm(1) -> x0 + terminator Return(v413) (exit_acc=v413) + block 8 start_pc=0 + v414 LoadLocal { off=-1, kind=I64 } -> x0 + v415 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v415) + block 9 start_pc=0 + v417 Imm(0) -> x0 + terminator Return(v417) (exit_acc=v417) + block 10 start_pc=0 + v416 Imm(2) -> x0 + terminator Return(v416) (exit_acc=v416) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/unroll_trip_17_stays_rolled.ssa b/tests/snapshots/ssa/unroll_trip_17_stays_rolled.ssa new file mode 100644 index 000000000..cfba7fe06 --- /dev/null +++ b/tests/snapshots/ssa/unroll_trip_17_stays_rolled.ssa @@ -0,0 +1,118 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x6 + v2 Imm(0) -> x0 + v3 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v1) + block 1 start_pc=0 + v10 ImmData(24) -> x1 + v11 LoadLocal { off=-1, kind=I64 } -> x2 + v12 BinopI { op=shl, lhs=v4, rhs_imm=3 } -> x2 + v13 Binop { op=add, lhs=v10, rhs=v12 } -> x2 + v14 StoreIndexed { base=v10, index=v4, scale=8, value=v4, kind=I64 } -> - + terminator Jmp(b2) (exit_acc=v14) + block 2 start_pc=0 + v7 LoadLocal { off=-1, kind=I64 } -> x1 + v8 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x0 + v9 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v8) + block 3 start_pc=0 + v4 Phi { incoming=[b0:v1, b2:v8], kind=I64 } -> x0 + v5 LoadLocal { off=-1, kind=I64 } -> x1 + v6 BinopI { op=lt, lhs=v4, rhs_imm=17 } -> x1 + terminator Bnz { cond=v6, target=b1, fall=b4 } (exit_acc=v6) + block 4 start_pc=0 + v15 Imm(0) -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v15) + block 5 start_pc=0 + v24 LoadLocal { off=-2, kind=I64 } -> x0 + v25 ImmData(24) -> x0 + v26 LoadLocal { off=-1, kind=I64 } -> x2 + v27 BinopI { op=shl, lhs=v18, rhs_imm=3 } -> x2 + v28 Binop { op=add, lhs=v25, rhs=v27 } -> x2 + v29 LoadIndexed { base=v25, index=v18, scale=8, kind=I64 } -> x0 + v30 Binop { op=add, lhs=v17, rhs=v29 } -> x6 + v31 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v30) + block 6 start_pc=0 + v21 LoadLocal { off=-1, kind=I64 } -> x0 + v22 BinopI { op=add, lhs=v18, rhs_imm=1 } -> x1 + v23 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v22) + block 7 start_pc=0 + v17 Phi { incoming=[b4:v1, b6:v30], kind=I64 } -> x6 + v18 Phi { incoming=[b4:v15, b6:v22], kind=I64 } -> x1 + v19 LoadLocal { off=-1, kind=I64 } -> x0 + v20 BinopI { op=lt, lhs=v18, rhs_imm=17 } -> x0 + terminator Bnz { cond=v20, target=b5, fall=b8 } (exit_acc=v20) + block 8 start_pc=0 + v32 LoadLocal { off=-2, kind=I64 } -> x0 + v33 BinopI { op=eq, lhs=v17, rhs_imm=136 } -> x0 + v34 Imm(0) -> x6 + v35 Imm(0) -> x2 + terminator Bz { cond=v33, target=b11, fall=b9 } (exit_acc=v33) + block 9 start_pc=0 + v36 LoadLocal { off=-1, kind=I64 } -> x0 + v37 BinopI { op=eq, lhs=v18, rhs_imm=17 } -> x0 + v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x6 + v39 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v38) + block 10 start_pc=0 + v40 Phi { incoming=[b11:v34, b9:v38], kind=I64 } -> x6 + v41 LoadLocal { off=-3, kind=I64 } -> x0 + v42 BinopI { op=eq, lhs=v40, rhs_imm=0 } -> x0 + terminator Return(v42) (exit_acc=v42) + block 11 start_pc=0 + terminator Jmp(b10) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/unroll_volatile_stays_rolled.ssa b/tests/snapshots/ssa/unroll_volatile_stays_rolled.ssa new file mode 100644 index 000000000..ace83e0ac --- /dev/null +++ b/tests/snapshots/ssa/unroll_volatile_stays_rolled.ssa @@ -0,0 +1,92 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x1 + v2 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v1) + block 1 start_pc=0 + v9 ImmData(24) -> x0 + v10 Load { addr=v9, disp=0, kind=I64, volatile } -> x2 + v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 + v12 Store { addr=v9, disp=0, value=v11, kind=I64, volatile } -> - + terminator Jmp(b2) (exit_acc=v12) + block 2 start_pc=0 + v6 LoadLocal { off=-1, kind=I64 } -> x0 + v7 BinopI { op=add, lhs=v3, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 BinopI { op=lt, lhs=v3, rhs_imm=4 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) + block 4 start_pc=0 + v13 ImmData(24) -> x0 + v14 Load { addr=v13, disp=0, kind=I64, volatile } -> x0 + v15 BinopI { op=eq, lhs=v14, rhs_imm=4 } -> x0 + v16 Imm(0) -> x6 + v17 Imm(0) -> x2 + terminator Bz { cond=v15, target=b7, fall=b5 } (exit_acc=v15) + block 5 start_pc=0 + v18 LoadLocal { off=-1, kind=I64 } -> x0 + v19 BinopI { op=eq, lhs=v3, rhs_imm=4 } -> x0 + v20 BinopI { op=ne, lhs=v19, rhs_imm=0 } -> x6 + v21 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v20) + block 6 start_pc=0 + v22 Phi { incoming=[b7:v16, b5:v20], kind=I64 } -> x6 + v23 LoadLocal { off=-2, kind=I64 } -> x0 + v24 BinopI { op=eq, lhs=v22, rhs_imm=0 } -> x0 + terminator Return(v24) (exit_acc=v24) + block 7 start_pc=0 + terminator Jmp(b6) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/unsigned_arith_high_half.ssa b/tests/snapshots/ssa/unsigned_arith_high_half.ssa index 0c1b5644c..d8ed10398 100644 --- a/tests/snapshots/ssa/unsigned_arith_high_half.ssa +++ b/tests/snapshots/ssa/unsigned_arith_high_half.ssa @@ -5,47 +5,47 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4278255360) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=xor, lhs=v1, rhs_imm=-1 } -> x0 - v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v6 BinopI { op=xor, lhs=v5, rhs_imm=16711935 } -> x0 - v7 BinopI { op=and, lhs=v6, rhs_imm=4294967295 } -> x0 - v8 BinopI { op=ne, lhs=v7, rhs_imm=0 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(-4278255361) -> x0 + v5 Imm(16711935) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 - v9 Imm(1) -> x0 - terminator Return(v9) (exit_acc=v9) - block 2 start_pc=0 v10 Imm(305419896) -> x0 - v11 Imm(0) -> x1 - v12 LoadLocal { off=-2, kind=U32 } -> x1 - v13 BinopI { op=shl, lhs=v10, rhs_imm=4 } -> x0 - v14 BinopI { op=and, lhs=v13, rhs_imm=4294967295 } -> x0 - v15 BinopI { op=xor, lhs=v14, rhs_imm=591751040 } -> x0 - v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x0 - v17 BinopI { op=ne, lhs=v16, rhs_imm=0 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) + v11 Imm(0) -> x0 + v12 LoadLocal { off=-2, kind=U32 } -> x0 + v13 Imm(4886718336) -> x0 + v14 Imm(591751040) -> x0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v17) + block 2 start_pc=0 + v19 Imm(1) -> x0 + v20 Imm(0) -> x0 + v21 Imm(2) -> x0 + v22 Imm(0) -> x0 + v23 LoadLocal { off=-3, kind=U32 } -> x0 + v24 LoadLocal { off=-4, kind=U32 } -> x0 + v25 Imm(-1) -> x0 + v26 Imm(4294967295) -> x0 + v27 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v27) block 3 start_pc=0 - v18 Imm(2) -> x0 - terminator Return(v18) (exit_acc=v18) + v29 Imm(0) -> x0 + terminator Return(v29) (exit_acc=v29) block 4 start_pc=0 - v19 Imm(1) -> x0 - v20 Imm(0) -> x1 - v21 Imm(2) -> x1 - v22 Imm(0) -> x2 - v23 LoadLocal { off=-3, kind=U32 } -> x2 - v24 LoadLocal { off=-4, kind=U32 } -> x2 - v25 Binop { op=sub, lhs=v19, rhs=v21 } -> x0 - v26 BinopI { op=and, lhs=v25, rhs_imm=4294967295 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=4294967295 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 5 start_pc=0 + v18 Imm(2) -> x0 + terminator Return(v18) (exit_acc=v18) + block 6 start_pc=0 v28 Imm(3) -> x0 terminator Return(v28) (exit_acc=v28) - block 6 start_pc=0 - v29 Imm(0) -> x0 - terminator Return(v29) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_char_array.ssa b/tests/snapshots/ssa/unsigned_char_array.ssa index 341b3d41a..21359cb92 100644 --- a/tests/snapshots/ssa/unsigned_char_array.ssa +++ b/tests/snapshots/ssa/unsigned_char_array.ssa @@ -1,65 +1,65 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=3 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 ImmData(36) -> x3 - v2 Imm(0) -> x0 - v3 Load { addr=v1, disp=0, kind=U8 } -> x0 - v4 BinopI { op=xor, lhs=v3, rhs_imm=1 } -> x0 - v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v6 BinopI { op=ne, lhs=v5, rhs_imm=0 } -> x0 + v1 ImmData(36) -> x0 + v2 Imm(0) -> x1 + v3 Load { addr=v1, disp=0, kind=U8 } -> x1 + v4 BinopI { op=xor, lhs=v3, rhs_imm=1 } -> x1 + v5 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x1 + v6 BinopI { op=ne, lhs=v5, rhs_imm=0 } -> x1 terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v7 ImmData(96) -> x7 - v8 ImmData(36) -> x0 - v9 Imm(0) -> x0 + v8 ImmData(36) -> x1 + v9 Imm(0) -> x1 v10 Load { addr=v1, disp=0, kind=U8 } -> x6 v11 CallExt { binding_idx=0, args=[v7, v10], fp_arg_mask=0x0 } -> x0 v12 Imm(1) -> x0 terminator Return(v12) (exit_acc=v12) block 2 start_pc=0 - v13 ImmData(36) -> x0 - v14 Imm(5) -> x0 - v15 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x0 - v16 Load { addr=v1, disp=5, kind=U8 } -> x0 - v17 BinopI { op=xor, lhs=v16, rhs_imm=6 } -> x0 - v18 BinopI { op=and, lhs=v17, rhs_imm=4294967295 } -> x0 - v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x0 + v13 ImmData(36) -> x1 + v14 Imm(5) -> x1 + v15 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x1 + v16 Load { addr=v1, disp=5, kind=U8 } -> x1 + v17 BinopI { op=xor, lhs=v16, rhs_imm=6 } -> x1 + v18 BinopI { op=and, lhs=v17, rhs_imm=4294967295 } -> x1 + v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x1 terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 v20 ImmData(115) -> x7 - v21 ImmData(36) -> x0 - v22 Imm(5) -> x0 - v23 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x0 + v21 ImmData(36) -> x1 + v22 Imm(5) -> x1 + v23 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x1 v24 Load { addr=v1, disp=5, kind=U8 } -> x6 v25 CallExt { binding_idx=0, args=[v20, v24], fp_arg_mask=0x0 } -> x0 v26 Imm(1) -> x0 terminator Return(v26) (exit_acc=v26) block 4 start_pc=0 - v27 ImmData(36) -> x0 - v28 Imm(9) -> x0 - v29 BinopI { op=add, lhs=v1, rhs_imm=9 } -> x0 - v30 Load { addr=v1, disp=9, kind=U8 } -> x0 - v31 BinopI { op=xor, lhs=v30, rhs_imm=10 } -> x0 - v32 BinopI { op=and, lhs=v31, rhs_imm=4294967295 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=0 } -> x0 + v27 ImmData(36) -> x1 + v28 Imm(9) -> x1 + v29 BinopI { op=add, lhs=v1, rhs_imm=9 } -> x1 + v30 Load { addr=v1, disp=9, kind=U8 } -> x1 + v31 BinopI { op=xor, lhs=v30, rhs_imm=10 } -> x1 + v32 BinopI { op=and, lhs=v31, rhs_imm=4294967295 } -> x1 + v33 BinopI { op=ne, lhs=v32, rhs_imm=0 } -> x1 terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) block 5 start_pc=0 v34 ImmData(134) -> x7 - v35 ImmData(36) -> x0 - v36 Imm(9) -> x0 - v37 BinopI { op=add, lhs=v1, rhs_imm=9 } -> x0 + v35 ImmData(36) -> x1 + v36 Imm(9) -> x1 + v37 BinopI { op=add, lhs=v1, rhs_imm=9 } -> x1 v38 Load { addr=v1, disp=9, kind=U8 } -> x6 v39 CallExt { binding_idx=0, args=[v34, v38], fp_arg_mask=0x0 } -> x0 v40 Imm(1) -> x0 terminator Return(v40) (exit_acc=v40) block 6 start_pc=0 - v41 ImmData(56) -> x0 - v42 Imm(0) -> x1 - v43 Load { addr=v41, disp=0, kind=I64 } -> x0 - v44 BinopI { op=ne, lhs=v43, rhs_imm=100 } -> x0 + v41 ImmData(56) -> x1 + v42 Imm(0) -> x2 + v43 Load { addr=v41, disp=0, kind=I64 } -> x1 + v44 BinopI { op=ne, lhs=v43, rhs_imm=100 } -> x1 terminator Bz { cond=v44, target=b8, fall=b7 } (exit_acc=v44) block 7 start_pc=0 v45 ImmData(153) -> x7 @@ -70,11 +70,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v50 Imm(1) -> x0 terminator Return(v50) (exit_acc=v50) block 8 start_pc=0 - v51 ImmData(56) -> x0 - v52 Imm(32) -> x1 - v53 BinopI { op=add, lhs=v51, rhs_imm=32 } -> x1 - v54 Load { addr=v51, disp=32, kind=I64 } -> x0 - v55 BinopI { op=ne, lhs=v54, rhs_imm=500 } -> x0 + v51 ImmData(56) -> x1 + v52 Imm(32) -> x2 + v53 BinopI { op=add, lhs=v51, rhs_imm=32 } -> x2 + v54 Load { addr=v51, disp=32, kind=I64 } -> x1 + v55 BinopI { op=ne, lhs=v54, rhs_imm=500 } -> x1 terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) block 9 start_pc=0 v56 ImmData(172) -> x7 @@ -86,12 +86,12 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v62 Imm(1) -> x0 terminator Return(v62) (exit_acc=v62) block 10 start_pc=0 - v63 Imm(5) -> x0 + v63 Imm(5) -> x1 v64 Imm(0) -> x1 v65 ImmData(36) -> x1 v66 LoadLocal { off=-1, kind=U8 } -> x1 - v67 Binop { op=add, lhs=v1, rhs=v63 } -> x1 - v68 Load { addr=v67, disp=0, kind=U8 } -> x1 + v67 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x1 + v68 Load { addr=v1, disp=5, kind=U8 } -> x1 v69 BinopI { op=xor, lhs=v68, rhs_imm=6 } -> x1 v70 BinopI { op=and, lhs=v69, rhs_imm=4294967295 } -> x1 v71 BinopI { op=ne, lhs=v70, rhs_imm=0 } -> x1 @@ -100,8 +100,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v72 ImmData(191) -> x7 v73 ImmData(36) -> x1 v74 LoadLocal { off=-1, kind=U8 } -> x1 - v75 Binop { op=add, lhs=v1, rhs=v63 } -> x0 - v76 Load { addr=v75, disp=0, kind=U8 } -> x6 + v75 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x1 + v76 Load { addr=v1, disp=5, kind=U8 } -> x6 v77 CallExt { binding_idx=0, args=[v72, v76], fp_arg_mask=0x0 } -> x0 v78 Imm(1) -> x0 terminator Return(v78) (exit_acc=v78) diff --git a/tests/snapshots/ssa/unsigned_compare.ssa b/tests/snapshots/ssa/unsigned_compare.ssa index 4ed4193ba..30bd33891 100644 --- a/tests/snapshots/ssa/unsigned_compare.ssa +++ b/tests/snapshots/ssa/unsigned_compare.ssa @@ -1,150 +1,150 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=13 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(1) -> x3 + v1 Imm(1) -> x0 v2 Imm(0) -> x0 - v3 Imm(4294967294) -> x12 + v3 Imm(4294967294) -> x0 v4 Imm(0) -> x0 v5 LoadLocal { off=-1, kind=U32 } -> x0 v6 LoadLocal { off=-2, kind=U32 } -> x0 - v7 Binop { op=ugt, lhs=v1, rhs=v3 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 + v11 LoadLocal { off=-2, kind=U32 } -> x0 + v12 LoadLocal { off=-1, kind=U32 } -> x0 + v13 Imm(1) -> x0 + v14 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v14) + block 2 start_pc=0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + v20 Imm(4294967294) -> x0 + v21 Imm(0) -> x0 + v22 LoadLocal { off=-3, kind=U32 } -> x0 + v23 LoadLocal { off=-4, kind=U32 } -> x0 + v24 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v24) + block 3 start_pc=0 + v28 LoadLocal { off=-4, kind=U32 } -> x0 + v29 LoadLocal { off=-3, kind=U32 } -> x0 + v30 Imm(1) -> x0 + v31 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v31) + block 4 start_pc=0 + v35 Imm(1) -> x0 + v36 Imm(0) -> x0 + v37 Imm(-2) -> x0 + v38 Imm(0) -> x0 + v39 LoadLocal { off=-5, kind=I64 } -> x0 + v40 LoadLocal { off=-6, kind=I64 } -> x0 + v41 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v41) + block 5 start_pc=0 + v45 LoadLocal { off=-6, kind=I64 } -> x0 + v46 LoadLocal { off=-5, kind=I64 } -> x0 + v47 Imm(1) -> x0 + v48 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v48) + block 6 start_pc=0 + v52 Imm(1) -> x0 + v53 Imm(0) -> x0 + v54 Imm(-2) -> x0 + v55 Imm(0) -> x0 + v56 LoadLocal { off=-7, kind=I64 } -> x0 + v57 LoadLocal { off=-8, kind=I64 } -> x0 + v58 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v58) + block 7 start_pc=0 + v62 LoadLocal { off=-8, kind=I64 } -> x0 + v63 LoadLocal { off=-7, kind=I64 } -> x0 + v64 Imm(1) -> x0 + v65 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v65) + block 8 start_pc=0 + v69 Imm(0) -> x0 + v70 Imm(0) -> x0 + v71 Imm(254) -> x0 + v72 Imm(0) -> x0 + v73 LoadLocal { off=-10, kind=U8 } -> x0 + v74 LoadLocal { off=-9, kind=U8 } -> x0 + v75 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v75) + block 9 start_pc=0 + v79 Imm(1) -> x0 + v80 Imm(0) -> x0 + v81 Imm(-2) -> x0 + v82 Imm(0) -> x0 + v83 LoadLocal { off=-11, kind=I32 } -> x0 + v84 LoadLocal { off=-12, kind=I32 } -> x0 + v85 Imm(1) -> x0 + v86 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v86) + block 10 start_pc=0 + v90 LoadLocal { off=-11, kind=I32 } -> x0 + v91 LoadLocal { off=-12, kind=I32 } -> x0 + v92 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v92) + block 11 start_pc=0 + v96 Imm(0) -> x0 + terminator Return(v96) (exit_acc=v96) + block 12 start_pc=0 v8 ImmData(36) -> x7 v9 CallExt { binding_idx=0, args=[v8], fp_arg_mask=0x0 } -> x0 v10 Imm(1) -> x0 terminator Return(v10) (exit_acc=v10) - block 2 start_pc=0 - v11 LoadLocal { off=-2, kind=U32 } -> x0 - v12 LoadLocal { off=-1, kind=U32 } -> x0 - v13 Binop { op=ugt, lhs=v3, rhs=v1 } -> x0 - v14 BinopI { op=eq, lhs=v13, rhs_imm=0 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) - block 3 start_pc=0 + block 13 start_pc=0 v15 ImmData(70) -> x7 v16 CallExt { binding_idx=0, args=[v15], fp_arg_mask=0x0 } -> x0 v17 Imm(1) -> x0 terminator Return(v17) (exit_acc=v17) - block 4 start_pc=0 - v18 Imm(1) -> x3 - v19 Imm(0) -> x0 - v20 Imm(4294967294) -> x12 - v21 Imm(0) -> x0 - v22 LoadLocal { off=-3, kind=U32 } -> x0 - v23 LoadLocal { off=-4, kind=U32 } -> x0 - v24 Binop { op=ugt, lhs=v18, rhs=v20 } -> x0 - terminator Bz { cond=v24, target=b6, fall=b5 } (exit_acc=v24) - block 5 start_pc=0 + block 14 start_pc=0 v25 ImmData(104) -> x7 v26 CallExt { binding_idx=0, args=[v25], fp_arg_mask=0x0 } -> x0 v27 Imm(1) -> x0 terminator Return(v27) (exit_acc=v27) - block 6 start_pc=0 - v28 LoadLocal { off=-4, kind=U32 } -> x0 - v29 LoadLocal { off=-3, kind=U32 } -> x0 - v30 Binop { op=ugt, lhs=v20, rhs=v18 } -> x0 - v31 BinopI { op=eq, lhs=v30, rhs_imm=0 } -> x0 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) - block 7 start_pc=0 + block 15 start_pc=0 v32 ImmData(139) -> x7 v33 CallExt { binding_idx=0, args=[v32], fp_arg_mask=0x0 } -> x0 v34 Imm(1) -> x0 terminator Return(v34) (exit_acc=v34) - block 8 start_pc=0 - v35 Imm(1) -> x3 - v36 Imm(0) -> x0 - v37 Imm(-2) -> x12 - v38 Imm(0) -> x0 - v39 LoadLocal { off=-5, kind=I64 } -> x0 - v40 LoadLocal { off=-6, kind=I64 } -> x0 - v41 Binop { op=ugt, lhs=v35, rhs=v37 } -> x0 - terminator Bz { cond=v41, target=b10, fall=b9 } (exit_acc=v41) - block 9 start_pc=0 + block 16 start_pc=0 v42 ImmData(174) -> x7 v43 CallExt { binding_idx=0, args=[v42], fp_arg_mask=0x0 } -> x0 v44 Imm(1) -> x0 terminator Return(v44) (exit_acc=v44) - block 10 start_pc=0 - v45 LoadLocal { off=-6, kind=I64 } -> x0 - v46 LoadLocal { off=-5, kind=I64 } -> x0 - v47 Binop { op=ugt, lhs=v37, rhs=v35 } -> x0 - v48 BinopI { op=eq, lhs=v47, rhs_imm=0 } -> x0 - terminator Bz { cond=v48, target=b12, fall=b11 } (exit_acc=v48) - block 11 start_pc=0 + block 17 start_pc=0 v49 ImmData(208) -> x7 v50 CallExt { binding_idx=0, args=[v49], fp_arg_mask=0x0 } -> x0 v51 Imm(1) -> x0 terminator Return(v51) (exit_acc=v51) - block 12 start_pc=0 - v52 Imm(1) -> x3 - v53 Imm(0) -> x0 - v54 Imm(-2) -> x12 - v55 Imm(0) -> x0 - v56 LoadLocal { off=-7, kind=I64 } -> x0 - v57 LoadLocal { off=-8, kind=I64 } -> x0 - v58 Binop { op=uge, lhs=v52, rhs=v54 } -> x0 - terminator Bz { cond=v58, target=b14, fall=b13 } (exit_acc=v58) - block 13 start_pc=0 + block 18 start_pc=0 v59 ImmData(242) -> x7 v60 CallExt { binding_idx=0, args=[v59], fp_arg_mask=0x0 } -> x0 v61 Imm(1) -> x0 terminator Return(v61) (exit_acc=v61) - block 14 start_pc=0 - v62 LoadLocal { off=-8, kind=I64 } -> x0 - v63 LoadLocal { off=-7, kind=I64 } -> x0 - v64 Binop { op=uge, lhs=v54, rhs=v52 } -> x0 - v65 BinopI { op=eq, lhs=v64, rhs_imm=0 } -> x0 - terminator Bz { cond=v65, target=b16, fall=b15 } (exit_acc=v65) - block 15 start_pc=0 + block 19 start_pc=0 v66 ImmData(279) -> x7 v67 CallExt { binding_idx=0, args=[v66], fp_arg_mask=0x0 } -> x0 v68 Imm(1) -> x0 terminator Return(v68) (exit_acc=v68) - block 16 start_pc=0 - v69 Imm(0) -> x0 - v70 Imm(0) -> x1 - v71 Imm(254) -> x1 - v72 Imm(0) -> x2 - v73 LoadLocal { off=-10, kind=U8 } -> x2 - v74 LoadLocal { off=-9, kind=U8 } -> x2 - v75 Binop { op=le, lhs=v71, rhs=v69 } -> x0 - terminator Bz { cond=v75, target=b18, fall=b17 } (exit_acc=v75) - block 17 start_pc=0 + block 20 start_pc=0 v76 ImmData(316) -> x7 v77 CallExt { binding_idx=0, args=[v76], fp_arg_mask=0x0 } -> x0 v78 Imm(1) -> x0 terminator Return(v78) (exit_acc=v78) - block 18 start_pc=0 - v79 Imm(1) -> x3 - v80 Imm(0) -> x0 - v81 Imm(-2) -> x12 - v82 Imm(0) -> x0 - v83 LoadLocal { off=-11, kind=I32 } -> x0 - v84 LoadLocal { off=-12, kind=I32 } -> x0 - v85 Binop { op=gt, lhs=v79, rhs=v81 } -> x0 - v86 BinopI { op=eq, lhs=v85, rhs_imm=0 } -> x0 - terminator Bz { cond=v86, target=b20, fall=b19 } (exit_acc=v86) - block 19 start_pc=0 + block 21 start_pc=0 v87 ImmData(347) -> x7 v88 CallExt { binding_idx=0, args=[v87], fp_arg_mask=0x0 } -> x0 v89 Imm(1) -> x0 terminator Return(v89) (exit_acc=v89) - block 20 start_pc=0 - v90 LoadLocal { off=-11, kind=I32 } -> x0 - v91 LoadLocal { off=-12, kind=I32 } -> x0 - v92 Binop { op=lt, lhs=v79, rhs=v81 } -> x0 - terminator Bz { cond=v92, target=b22, fall=b21 } (exit_acc=v92) - block 21 start_pc=0 + block 22 start_pc=0 v93 ImmData(368) -> x7 v94 CallExt { binding_idx=0, args=[v93], fp_arg_mask=0x0 } -> x0 v95 Imm(1) -> x0 terminator Return(v95) (exit_acc=v95) - block 22 start_pc=0 - v96 Imm(0) -> x0 - terminator Return(v96) (exit_acc=v96) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_compound_assign.ssa b/tests/snapshots/ssa/unsigned_compound_assign.ssa index affc52b0d..3e856efc9 100644 --- a/tests/snapshots/ssa/unsigned_compound_assign.ssa +++ b/tests/snapshots/ssa/unsigned_compound_assign.ssa @@ -1,94 +1,64 @@ ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=11 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(100) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=5 } -> x3 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(105) -> x0 v5 Imm(0) -> x0 - v6 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v7 BinopI { op=xor, lhs=v6, rhs_imm=105 } -> x0 - v8 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=0 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v6 Imm(105) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 ImmData(36) -> x7 - v11 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x6 - v12 CallExt { binding_idx=0, args=[v10, v11], fp_arg_mask=0x0 } -> x0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v14 Imm(105) -> x0 + v15 Imm(102) -> x0 + v16 Imm(0) -> x0 + v17 Imm(102) -> x0 + v18 Imm(0) -> x0 + v19 Imm(0) -> x0 + v20 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 - v14 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v15 BinopI { op=sub, lhs=v14, rhs_imm=3 } -> x0 - v16 Imm(0) -> x1 - v17 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x1 - v18 BinopI { op=xor, lhs=v17, rhs_imm=102 } -> x1 - v19 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x1 - v20 BinopI { op=ne, lhs=v19, rhs_imm=0 } -> x1 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) - block 3 start_pc=0 - v21 ImmData(58) -> x7 - v22 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x6 - v23 CallExt { binding_idx=0, args=[v21, v22], fp_arg_mask=0x0 } -> x0 - v24 Imm(1) -> x0 - terminator Return(v24) (exit_acc=v24) - block 4 start_pc=0 v25 Imm(1000) -> x0 - v26 Imm(0) -> x1 - v27 LoadLocal { off=-2, kind=I64 } -> x1 - v28 BinopI { op=add, lhs=v25, rhs_imm=415 } -> x6 + v26 Imm(0) -> x0 + v27 LoadLocal { off=-2, kind=I64 } -> x0 + v28 Imm(1415) -> x6 v29 Imm(0) -> x0 v30 LoadLocal { off=-2, kind=I64 } -> x0 - v31 BinopI { op=ne, lhs=v28, rhs_imm=1415 } -> x0 - terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) - block 5 start_pc=0 - v32 ImmData(80) -> x7 - v33 LoadLocal { off=-2, kind=I64 } -> x0 - v34 CallExt { binding_idx=0, args=[v32, v28], fp_arg_mask=0x0 } -> x0 - v35 Imm(1) -> x0 - terminator Return(v35) (exit_acc=v35) - block 6 start_pc=0 + v31 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v31) + block 3 start_pc=0 v36 Imm(1052) -> x0 - v37 Imm(0) -> x1 - v38 Imm(415) -> x1 - v39 Imm(1782411427840) -> x2 - v40 Imm(0) -> x2 - v41 LoadLocal { off=-3, kind=U32 } -> x2 - v42 LoadLocal { off=-4, kind=I32 } -> x2 - v43 Binop { op=add, lhs=v36, rhs=v38 } -> x0 - v44 Imm(0) -> x1 - v45 BinopI { op=and, lhs=v43, rhs_imm=4294967295 } -> x1 - v46 BinopI { op=xor, lhs=v45, rhs_imm=1467 } -> x1 - v47 BinopI { op=and, lhs=v46, rhs_imm=4294967295 } -> x1 - v48 BinopI { op=ne, lhs=v47, rhs_imm=0 } -> x1 - terminator Bz { cond=v48, target=b8, fall=b7 } (exit_acc=v48) - block 7 start_pc=0 - v49 ImmData(105) -> x7 - v50 BinopI { op=and, lhs=v43, rhs_imm=4294967295 } -> x6 - v51 CallExt { binding_idx=0, args=[v49, v50], fp_arg_mask=0x0 } -> x0 - v52 Imm(1) -> x0 - terminator Return(v52) (exit_acc=v52) - block 8 start_pc=0 + v37 Imm(0) -> x0 + v38 Imm(415) -> x0 + v39 Imm(1782411427840) -> x0 + v40 Imm(0) -> x0 + v41 LoadLocal { off=-3, kind=U32 } -> x0 + v42 LoadLocal { off=-4, kind=I32 } -> x0 + v43 Imm(1467) -> x0 + v44 Imm(0) -> x0 + v45 Imm(1467) -> x0 + v46 Imm(0) -> x0 + v47 Imm(0) -> x0 + v48 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v48) + block 4 start_pc=0 v53 Imm(200) -> x0 - v54 Imm(0) -> x1 - v55 LoadLocal { off=-5, kind=U8 } -> x1 - v56 BinopI { op=add, lhs=v53, rhs_imm=60 } -> x0 - v57 Imm(0) -> x1 - v58 BinopI { op=and, lhs=v56, rhs_imm=255 } -> x1 - v59 BinopI { op=xor, lhs=v58, rhs_imm=4 } -> x1 - v60 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x1 - v61 BinopI { op=ne, lhs=v60, rhs_imm=0 } -> x1 - terminator Bz { cond=v61, target=b10, fall=b9 } (exit_acc=v61) - block 9 start_pc=0 - v62 ImmData(138) -> x7 - v63 BinopI { op=and, lhs=v56, rhs_imm=255 } -> x6 - v64 CallExt { binding_idx=0, args=[v62, v63], fp_arg_mask=0x0 } -> x0 - v65 Imm(1) -> x0 - terminator Return(v65) (exit_acc=v65) - block 10 start_pc=0 + v54 Imm(0) -> x0 + v55 LoadLocal { off=-5, kind=U8 } -> x0 + v56 Imm(260) -> x0 + v57 Imm(0) -> x0 + v58 Imm(4) -> x0 + v59 Imm(0) -> x0 + v60 Imm(0) -> x0 + v61 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v61) + block 5 start_pc=0 v66 LocalAddr(-8) -> x0 v67 Imm(0) -> x1 v68 Store { addr=v66, disp=0, value=v67, kind=I32 } -> - @@ -120,17 +90,47 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 v94 LoadLocal { off=-9, kind=I64 } -> x1 v95 Load { addr=v89, disp=12, kind=I32 } -> x1 v96 BinopI { op=ne, lhs=v95, rhs_imm=30 } -> x1 - terminator Bz { cond=v96, target=b12, fall=b11 } (exit_acc=v96) - block 11 start_pc=0 + terminator Bz { cond=v96, target=b7, fall=b6 } (exit_acc=v96) + block 6 start_pc=0 v97 ImmData(166) -> x7 v98 LoadLocal { off=-9, kind=I64 } -> x1 v99 Load { addr=v89, disp=12, kind=I32 } -> x6 v100 CallExt { binding_idx=0, args=[v97, v99], fp_arg_mask=0x0 } -> x0 v101 Imm(1) -> x0 terminator Return(v101) (exit_acc=v101) - block 12 start_pc=0 + block 7 start_pc=0 v102 Imm(0) -> x0 terminator Return(v102) (exit_acc=v102) + block 8 start_pc=0 + v10 ImmData(36) -> x7 + v11 Imm(105) -> x6 + v12 CallExt { binding_idx=0, args=[v10, v11], fp_arg_mask=0x0 } -> x0 + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) + block 9 start_pc=0 + v21 ImmData(58) -> x7 + v22 Imm(102) -> x6 + v23 CallExt { binding_idx=0, args=[v21, v22], fp_arg_mask=0x0 } -> x0 + v24 Imm(1) -> x0 + terminator Return(v24) (exit_acc=v24) + block 10 start_pc=0 + v32 ImmData(80) -> x7 + v33 LoadLocal { off=-2, kind=I64 } -> x0 + v34 CallExt { binding_idx=0, args=[v32, v28], fp_arg_mask=0x0 } -> x0 + v35 Imm(1) -> x0 + terminator Return(v35) (exit_acc=v35) + block 11 start_pc=0 + v49 ImmData(105) -> x7 + v50 Imm(1467) -> x6 + v51 CallExt { binding_idx=0, args=[v49, v50], fp_arg_mask=0x0 } -> x0 + v52 Imm(1) -> x0 + terminator Return(v52) (exit_acc=v52) + block 12 start_pc=0 + v62 ImmData(138) -> x7 + v63 Imm(4) -> x6 + v64 CallExt { binding_idx=0, args=[v62, v63], fp_arg_mask=0x0 } -> x0 + v65 Imm(1) -> x0 + terminator Return(v65) (exit_acc=v65) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_div_in_assign.ssa b/tests/snapshots/ssa/unsigned_div_in_assign.ssa index 68d9c927a..09b00c8a3 100644 --- a/tests/snapshots/ssa/unsigned_div_in_assign.ssa +++ b/tests/snapshots/ssa/unsigned_div_in_assign.ssa @@ -60,19 +60,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x1 v25 Extend { value=v23, kind=I32 } -> x0 v26 BinopI { op=eq, lhs=v25, rhs_imm=1002 } -> x0 - terminator Bz { cond=v26, target=b2, fall=b1 } (exit_acc=v26) + terminator Bz { cond=v26, target=b3, fall=b1 } (exit_acc=v26) block 1 start_pc=0 v27 Imm(0) -> x1 v28 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v27) + terminator Jmp(b2) (exit_acc=v27) block 2 start_pc=0 - v29 Imm(1) -> x1 - v30 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v29) - block 3 start_pc=0 - v31 Phi { incoming=[b1:v27, b2:v29], kind=I64 } -> x1 + v31 Phi { incoming=[b1:v27, b3:v29], kind=I64 } -> x1 v32 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v31) (exit_acc=v31) + block 3 start_pc=0 + v29 Imm(1) -> x1 + v30 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v29) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_div_mod.ssa b/tests/snapshots/ssa/unsigned_div_mod.ssa index c6b5769f6..c6d47873a 100644 --- a/tests/snapshots/ssa/unsigned_div_mod.ssa +++ b/tests/snapshots/ssa/unsigned_div_mod.ssa @@ -5,54 +5,54 @@ fn ent_pc=1 n_params=0 variadic=false locals=11 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294967294) -> x0 - v2 Imm(0) -> x1 - v3 Imm(2) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=U32 } -> x2 - v6 LoadLocal { off=-2, kind=U32 } -> x2 - v7 Binop { op=divu, lhs=v1, rhs=v3 } -> x0 - v8 Imm(0) -> x1 - v9 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x0 - v10 BinopI { op=ne, lhs=v9, rhs_imm=2147483647 } -> x0 - terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) + v2 Imm(0) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U32 } -> x0 + v6 LoadLocal { off=-2, kind=U32 } -> x0 + v7 Imm(2147483647) -> x0 + v8 Imm(0) -> x0 + v9 Imm(2147483647) -> x0 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 1 start_pc=0 - v11 Imm(1) -> x0 - terminator Return(v11) (exit_acc=v11) - block 2 start_pc=0 v12 Imm(4294967295) -> x0 - v13 Imm(0) -> x1 - v14 Imm(7) -> x1 - v15 Imm(0) -> x2 - v16 LoadLocal { off=-5, kind=U32 } -> x2 - v17 LoadLocal { off=-6, kind=U32 } -> x2 - v18 Binop { op=modu, lhs=v12, rhs=v14 } -> x0 - v19 Imm(0) -> x1 - v20 BinopI { op=and, lhs=v18, rhs_imm=4294967295 } -> x0 - v21 BinopI { op=xor, lhs=v20, rhs_imm=3 } -> x0 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x0 - v23 BinopI { op=ne, lhs=v22, rhs_imm=0 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v13 Imm(0) -> x0 + v14 Imm(7) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-5, kind=U32 } -> x0 + v17 LoadLocal { off=-6, kind=U32 } -> x0 + v18 Imm(3) -> x0 + v19 Imm(0) -> x0 + v20 Imm(3) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v25 Imm(-2) -> x0 + v26 Imm(0) -> x0 + v27 Imm(2) -> x0 + v28 Imm(0) -> x0 + v29 LoadLocal { off=-9, kind=I64 } -> x0 + v30 LoadLocal { off=-10, kind=I64 } -> x0 + v31 Imm(9223372036854775807) -> x0 + v32 Imm(0) -> x0 + v33 LoadLocal { off=-11, kind=I64 } -> x0 + v34 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v34) block 3 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v36 Imm(0) -> x0 + terminator Return(v36) (exit_acc=v36) block 4 start_pc=0 - v25 Imm(-2) -> x0 - v26 Imm(0) -> x1 - v27 Imm(2) -> x1 - v28 Imm(0) -> x2 - v29 LoadLocal { off=-9, kind=I64 } -> x2 - v30 LoadLocal { off=-10, kind=I64 } -> x2 - v31 Binop { op=divu, lhs=v25, rhs=v27 } -> x0 - v32 Imm(0) -> x1 - v33 LoadLocal { off=-11, kind=I64 } -> x1 - v34 BinopI { op=ne, lhs=v31, rhs_imm=9223372036854775807 } -> x0 - terminator Bz { cond=v34, target=b6, fall=b5 } (exit_acc=v34) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 5 start_pc=0 + v24 Imm(2) -> x0 + terminator Return(v24) (exit_acc=v24) + block 6 start_pc=0 v35 Imm(3) -> x0 terminator Return(v35) (exit_acc=v35) - block 6 start_pc=0 - v36 Imm(0) -> x0 - terminator Return(v36) (exit_acc=v36) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_right_shift.ssa b/tests/snapshots/ssa/unsigned_right_shift.ssa index 645fb8b2a..d0162c5b8 100644 --- a/tests/snapshots/ssa/unsigned_right_shift.ssa +++ b/tests/snapshots/ssa/unsigned_right_shift.ssa @@ -5,33 +5,33 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2147483648) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=U32 } -> x1 - v4 BinopI { op=shru, lhs=v1, rhs_imm=1 } -> x0 - v5 Imm(0) -> x1 - v6 BinopI { op=and, lhs=v4, rhs_imm=4294967295 } -> x0 - v7 BinopI { op=xor, lhs=v6, rhs_imm=1073741824 } -> x0 - v8 BinopI { op=and, lhs=v7, rhs_imm=4294967295 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=0 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=U32 } -> x0 + v4 Imm(1073741824) -> x0 + v5 Imm(0) -> x0 + v6 Imm(1073741824) -> x0 + v7 Imm(0) -> x0 + v8 Imm(0) -> x0 + v9 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) - block 2 start_pc=0 v11 Imm(-9223372036854775808) -> x0 - v12 Imm(0) -> x1 - v13 LoadLocal { off=-3, kind=I64 } -> x1 - v14 BinopI { op=shru, lhs=v11, rhs_imm=1 } -> x0 - v15 Imm(0) -> x1 - v16 LoadLocal { off=-4, kind=I64 } -> x1 - v17 BinopI { op=ne, lhs=v14, rhs_imm=4611686018427387904 } -> x0 - terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) + v12 Imm(0) -> x0 + v13 LoadLocal { off=-3, kind=I64 } -> x0 + v14 Imm(4611686018427387904) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-4, kind=I64 } -> x0 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v17) + block 2 start_pc=0 + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) block 3 start_pc=0 + v10 Imm(1) -> x0 + terminator Return(v10) (exit_acc=v10) + block 4 start_pc=0 v18 Imm(2) -> x0 terminator Return(v18) (exit_acc=v18) - block 4 start_pc=0 - v19 Imm(0) -> x0 - terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/unsigned_signed_relational_compare.ssa b/tests/snapshots/ssa/unsigned_signed_relational_compare.ssa index a8203cf1b..138337dc4 100644 --- a/tests/snapshots/ssa/unsigned_signed_relational_compare.ssa +++ b/tests/snapshots/ssa/unsigned_signed_relational_compare.ssa @@ -5,120 +5,116 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4294967295) -> x0 - v2 Imm(0) -> x1 - v3 Imm(-1) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=U32 } -> x2 - v6 LoadLocal { off=-2, kind=I32 } -> x2 - v7 BinopI { op=and, lhs=v3, rhs_imm=4294967295 } -> x2 - v8 Binop { op=ult, lhs=v1, rhs=v7 } -> x2 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v2 Imm(0) -> x0 + v3 Imm(-1) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=U32 } -> x0 + v6 LoadLocal { off=-2, kind=I32 } -> x0 + v7 Imm(4294967295) -> x0 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v8) block 1 start_pc=0 - v9 Imm(1) -> x0 - terminator Return(v9) (exit_acc=v9) + v10 LoadLocal { off=-2, kind=I32 } -> x0 + v11 LoadLocal { off=-1, kind=U32 } -> x0 + v12 Imm(4294967295) -> x0 + v13 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v10 LoadLocal { off=-2, kind=I32 } -> x2 - v11 LoadLocal { off=-1, kind=U32 } -> x2 - v12 BinopI { op=and, lhs=v3, rhs_imm=4294967295 } -> x2 - v13 Binop { op=ult, lhs=v12, rhs=v1 } -> x2 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v15 LoadLocal { off=-1, kind=U32 } -> x0 + v16 LoadLocal { off=-2, kind=I32 } -> x0 + v17 Imm(4294967295) -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v19) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v21 LoadLocal { off=-1, kind=U32 } -> x0 + v22 LoadLocal { off=-2, kind=I32 } -> x0 + v23 Imm(4294967295) -> x0 + v24 Imm(1) -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v25) block 4 start_pc=0 - v15 LoadLocal { off=-1, kind=U32 } -> x2 - v16 LoadLocal { off=-2, kind=I32 } -> x2 - v17 BinopI { op=and, lhs=v3, rhs_imm=4294967295 } -> x2 - v18 Binop { op=ule, lhs=v1, rhs=v17 } -> x2 - v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x2 - terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) + v27 LoadLocal { off=-1, kind=U32 } -> x0 + v28 LoadLocal { off=-2, kind=I32 } -> x0 + v29 Imm(4294967295) -> x0 + v30 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v30) block 5 start_pc=0 - v20 Imm(3) -> x0 - terminator Return(v20) (exit_acc=v20) + v32 Imm(5) -> x0 + v33 Imm(0) -> x0 + v34 Imm(10) -> x0 + v35 Imm(0) -> x0 + v36 LoadLocal { off=-3, kind=U32 } -> x0 + v37 LoadLocal { off=-4, kind=U32 } -> x0 + v38 Imm(1) -> x0 + v39 Imm(0) -> x1 + v40 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v39) block 6 start_pc=0 - v21 LoadLocal { off=-1, kind=U32 } -> x2 - v22 LoadLocal { off=-2, kind=I32 } -> x2 - v23 BinopI { op=and, lhs=v3, rhs_imm=4294967295 } -> x2 - v24 Binop { op=uge, lhs=v1, rhs=v23 } -> x2 - v25 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x2 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) + v41 LoadLocal { off=-4, kind=U32 } -> x0 + v42 LoadLocal { off=-3, kind=U32 } -> x0 + v43 Imm(0) -> x1 + v44 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v43) block 7 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) + v45 Phi { incoming=[b5:v39, b6:v43], kind=I64 } -> x1 + v46 LoadLocal { off=-8, kind=I64 } -> x0 + terminator Bz { cond=v45, target=b9, fall=b8 } (exit_acc=v45) block 8 start_pc=0 - v27 LoadLocal { off=-1, kind=U32 } -> x2 - v28 LoadLocal { off=-2, kind=I32 } -> x2 - v29 BinopI { op=and, lhs=v3, rhs_imm=4294967295 } -> x2 - v30 Binop { op=ugt, lhs=v1, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v47 Imm(6) -> x0 + terminator Return(v47) (exit_acc=v47) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v48 Imm(-5) -> x0 + v49 Imm(0) -> x0 + v50 Imm(3) -> x0 + v51 Imm(0) -> x0 + v52 LoadLocal { off=-5, kind=I32 } -> x0 + v53 LoadLocal { off=-6, kind=I32 } -> x0 + v54 Imm(1) -> x0 + v55 Imm(0) -> x1 + v56 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v55) block 10 start_pc=0 - v32 Imm(5) -> x0 - v33 Imm(0) -> x2 - v34 Imm(10) -> x2 - v35 Imm(0) -> x6 - v36 LoadLocal { off=-3, kind=U32 } -> x6 - v37 LoadLocal { off=-4, kind=U32 } -> x6 - v38 Binop { op=ult, lhs=v32, rhs=v34 } -> x6 - v39 BinopI { op=eq, lhs=v38, rhs_imm=0 } -> x7 - v40 Imm(0) -> x6 - terminator Bnz { cond=v39, target=b21, fall=b11 } (exit_acc=v39) + v57 LoadLocal { off=-6, kind=I32 } -> x0 + v58 LoadLocal { off=-5, kind=I32 } -> x0 + v59 Imm(0) -> x1 + v60 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v59) block 11 start_pc=0 - v41 LoadLocal { off=-4, kind=U32 } -> x6 - v42 LoadLocal { off=-3, kind=U32 } -> x6 - v43 Binop { op=ult, lhs=v34, rhs=v32 } -> x7 - v44 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v43) + v61 Phi { incoming=[b9:v55, b10:v59], kind=I64 } -> x1 + v62 LoadLocal { off=-9, kind=I64 } -> x0 + terminator Bz { cond=v61, target=b13, fall=b12 } (exit_acc=v61) block 12 start_pc=0 - v45 Phi { incoming=[b21:v39, b11:v43], kind=I64 } -> x7 - v46 LoadLocal { off=-8, kind=I64 } -> x0 - terminator Bz { cond=v45, target=b14, fall=b13 } (exit_acc=v45) + v63 Imm(7) -> x0 + terminator Return(v63) (exit_acc=v63) block 13 start_pc=0 - v47 Imm(6) -> x0 - terminator Return(v47) (exit_acc=v47) + v64 Imm(-1) -> x0 + v65 Imm(0) -> x0 + v66 LoadLocal { off=-7, kind=I64 } -> x0 + v67 LoadLocal { off=-2, kind=I32 } -> x0 + v68 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v68) block 14 start_pc=0 - v48 Imm(-5) -> x0 - v49 Imm(0) -> x2 - v50 Imm(3) -> x2 - v51 Imm(0) -> x6 - v52 LoadLocal { off=-5, kind=I32 } -> x6 - v53 LoadLocal { off=-6, kind=I32 } -> x6 - v54 Binop { op=lt, lhs=v48, rhs=v50 } -> x6 - v55 BinopI { op=eq, lhs=v54, rhs_imm=0 } -> x7 - v56 Imm(0) -> x6 - terminator Bnz { cond=v55, target=b22, fall=b15 } (exit_acc=v55) + v70 Imm(0) -> x0 + terminator Return(v70) (exit_acc=v70) block 15 start_pc=0 - v57 LoadLocal { off=-6, kind=I32 } -> x6 - v58 LoadLocal { off=-5, kind=I32 } -> x6 - v59 Binop { op=lt, lhs=v50, rhs=v48 } -> x7 - v60 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v59) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 16 start_pc=0 - v61 Phi { incoming=[b22:v55, b15:v59], kind=I64 } -> x7 - v62 LoadLocal { off=-9, kind=I64 } -> x0 - terminator Bz { cond=v61, target=b18, fall=b17 } (exit_acc=v61) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 17 start_pc=0 - v63 Imm(7) -> x0 - terminator Return(v63) (exit_acc=v63) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 18 start_pc=0 - v64 Imm(-1) -> x0 - v65 Imm(0) -> x2 - v66 LoadLocal { off=-7, kind=I64 } -> x2 - v67 LoadLocal { off=-2, kind=I32 } -> x2 - v68 Binop { op=ult, lhs=v64, rhs=v3 } -> x0 - terminator Bz { cond=v68, target=b20, fall=b19 } (exit_acc=v68) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) block 19 start_pc=0 + v31 Imm(5) -> x0 + terminator Return(v31) (exit_acc=v31) + block 20 start_pc=0 v69 Imm(8) -> x0 terminator Return(v69) (exit_acc=v69) - block 20 start_pc=0 - v70 Imm(0) -> x0 - terminator Return(v70) (exit_acc=v70) - block 21 start_pc=0 - terminator Jmp(b12) - block 22 start_pc=0 - terminator Jmp(b16) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/va_arg_composite_straddle.ssa b/tests/snapshots/ssa/va_arg_composite_straddle.ssa index 117f77129..2998b4d27 100644 --- a/tests/snapshots/ssa/va_arg_composite_straddle.ssa +++ b/tests/snapshots/ssa/va_arg_composite_straddle.ssa @@ -9,24 +9,24 @@ fn ent_pc=1 n_params=1 variadic=true locals=8 v3 Intrinsic { kind=4, args=[v1, v2] } -> x0 v4 Imm(0) -> x1 v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 - v7 Extend { value=v6, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=6 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v12 LocalAddr(-3) -> x2 + v13 Imm(8) -> x6 + v14 Intrinsic { kind=5, args=[v12, v13] } -> x2 + v15 Load { addr=v14, disp=0, kind=I64 } -> x2 + v16 BinopI { op=and, lhs=v15, rhs_imm=255 } -> x2 + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v9 Extend { value=v6, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v9 Extend { value=v6, kind=I32 } -> x1 + v10 BinopI { op=add, lhs=v7, rhs_imm=1 } -> x1 v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + terminator Jmp(b3) (exit_acc=v10) block 3 start_pc=0 - v12 LocalAddr(-3) -> x0 - v13 Imm(8) -> x2 - v14 Intrinsic { kind=5, args=[v12, v13] } -> x0 - v15 Load { addr=v14, disp=0, kind=I64 } -> x0 - v16 BinopI { op=and, lhs=v15, rhs_imm=255 } -> x0 - terminator Jmp(b2) (exit_acc=v16) + v6 Phi { incoming=[b0:v4, b2:v10], kind=I64 } -> x1 + v7 Extend { value=v6, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=6 } -> x2 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) block 4 start_pc=0 v17 LocalAddr(-3) -> x0 v18 Imm(16) -> x1 diff --git a/tests/snapshots/ssa/va_arg_int_seq.ssa b/tests/snapshots/ssa/va_arg_int_seq.ssa index cb19622a6..8806a3df2 100644 --- a/tests/snapshots/ssa/va_arg_int_seq.ssa +++ b/tests/snapshots/ssa/va_arg_int_seq.ssa @@ -13,19 +13,8 @@ fn ent_pc=1 n_params=2 variadic=true locals=8 v7 CallExt { binding_idx=0, args=[v4, v5, v6], fp_arg_mask=0x0 } -> x0 v8 Imm(0) -> x3 v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v8) + terminator Jmp(b3) (exit_acc=v8) block 1 start_pc=0 - v10 Phi { incoming=[b0:v8, b2:v15], kind=I64 } -> x3 - v11 Extend { value=v10, kind=I32 } -> x0 - v12 LoadLocal { off=3, kind=I32 } -> x1 - v13 Binop { op=lt, lhs=v11, rhs=v12 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) - block 2 start_pc=0 - v14 Extend { value=v10, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x3 - v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) - block 3 start_pc=0 v17 LocalAddr(-3) -> x0 v18 Imm(4) -> x1 v19 Intrinsic { kind=5, args=[v17, v18] } -> x0 @@ -36,6 +25,17 @@ fn ent_pc=1 n_params=2 variadic=true locals=8 v24 Extend { value=v20, kind=I32 } -> x0 v25 CallExt { binding_idx=0, args=[v22, v23, v20], fp_arg_mask=0x0 } -> x0 terminator Jmp(b2) (exit_acc=v25) + block 2 start_pc=0 + v14 Extend { value=v10, kind=I32 } -> x0 + v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x3 + v16 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v15) + block 3 start_pc=0 + v10 Phi { incoming=[b0:v8, b2:v15], kind=I64 } -> x3 + v11 Extend { value=v10, kind=I32 } -> x0 + v12 LoadLocal { off=3, kind=I32 } -> x1 + v13 Binop { op=lt, lhs=v11, rhs=v12 } -> x0 + terminator Bnz { cond=v13, target=b1, fall=b4 } (exit_acc=v13) block 4 start_pc=0 v26 LocalAddr(-3) -> x0 v27 Intrinsic { kind=6, args=[v26] } -> x0 diff --git a/tests/snapshots/ssa/va_copy.ssa b/tests/snapshots/ssa/va_copy.ssa index 1ab61bbd7..74171ac3b 100644 --- a/tests/snapshots/ssa/va_copy.ssa +++ b/tests/snapshots/ssa/va_copy.ssa @@ -13,15 +13,8 @@ fn ent_pc=0 n_params=1 variadic=true locals=8 v7 Imm(0) -> x1 v8 Imm(0) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + terminator Jmp(b2) (exit_acc=v7) block 1 start_pc=0 - v10 Phi { incoming=[b0:v7, b2:v27], kind=I64 } -> x1 - v11 Phi { incoming=[b0:v7, b2:v20], kind=I64 } -> x0 - v12 Extend { value=v10, kind=I32 } -> x2 - v13 LoadLocal { off=2, kind=I32 } -> x6 - v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x2 - terminator Bz { cond=v14, target=b3, fall=b2 } (exit_acc=v14) - block 2 start_pc=0 v15 Extend { value=v11, kind=I32 } -> x2 v16 LocalAddr(-6) -> x2 v17 Imm(4) -> x6 @@ -36,7 +29,14 @@ fn ent_pc=0 n_params=1 variadic=true locals=8 v26 BinopI { op=shl, lhs=v25, rhs_imm=32 } -> x2 v27 Extend { value=v25, kind=I32 } -> x1 v28 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v27) + terminator Jmp(b2) (exit_acc=v27) + block 2 start_pc=0 + v10 Phi { incoming=[b0:v7, b1:v27], kind=I64 } -> x1 + v11 Phi { incoming=[b0:v7, b1:v20], kind=I64 } -> x0 + v12 Extend { value=v10, kind=I32 } -> x2 + v13 LoadLocal { off=2, kind=I32 } -> x6 + v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x2 + terminator Bnz { cond=v14, target=b1, fall=b3 } (exit_acc=v14) block 3 start_pc=0 v29 LocalAddr(-6) -> x1 v30 Intrinsic { kind=6, args=[v29] } -> x1 diff --git a/tests/snapshots/ssa/va_copy_under_pressure.ssa b/tests/snapshots/ssa/va_copy_under_pressure.ssa index 0e05542da..d18672477 100644 --- a/tests/snapshots/ssa/va_copy_under_pressure.ssa +++ b/tests/snapshots/ssa/va_copy_under_pressure.ssa @@ -122,24 +122,24 @@ fn ent_pc=1 n_params=0 variadic=false locals=5 v30 Imm(332) -> x1 v31 Imm(1425929142272) -> x1 v32 Imm(352) -> x1 - v33 Imm(1511828488192) -> x2 - v34 Imm(0) -> x2 - v35 LoadLocal { off=-1, kind=I64 } -> x2 - v36 LoadLocal { off=-2, kind=I64 } -> x2 - v37 Binop { op=eq, lhs=v4, rhs=v32 } -> x0 - terminator Bz { cond=v37, target=b2, fall=b1 } (exit_acc=v37) + v33 Imm(1511828488192) -> x1 + v34 Imm(0) -> x1 + v35 LoadLocal { off=-1, kind=I64 } -> x1 + v36 LoadLocal { off=-2, kind=I64 } -> x1 + v37 BinopI { op=eq, lhs=v4, rhs_imm=352 } -> x0 + terminator Bz { cond=v37, target=b3, fall=b1 } (exit_acc=v37) block 1 start_pc=0 v38 Imm(0) -> x1 v39 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v38) + terminator Jmp(b2) (exit_acc=v38) block 2 start_pc=0 - v40 Imm(1) -> x1 - v41 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v40) - block 3 start_pc=0 - v42 Phi { incoming=[b1:v38, b2:v40], kind=I64 } -> x1 + v42 Phi { incoming=[b1:v38, b3:v40], kind=I64 } -> x1 v43 LoadLocal { off=-5, kind=I64 } -> x0 terminator Return(v42) (exit_acc=v42) + block 3 start_pc=0 + v40 Imm(1) -> x1 + v41 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v40) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variable_shift_rcx_loop.ssa b/tests/snapshots/ssa/variable_shift_rcx_loop.ssa index 3907cb045..adc765195 100644 --- a/tests/snapshots/ssa/variable_shift_rcx_loop.ssa +++ b/tests/snapshots/ssa/variable_shift_rcx_loop.ssa @@ -15,14 +15,13 @@ fn ent_pc=0 n_params=4 variadic=false locals=2 v9 Imm(0) -> x8 v10 Imm(0) -> x1 v11 Imm(0) -> x1 - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v12 Phi { incoming=[b0:v9, b2:v21], kind=I64 } -> x8 - v13 Phi { incoming=[b0:v9, b2:v25], kind=I64 } -> x1 - v14 LoadLocal { off=-1, kind=I64 } -> x9 - v15 LoadLocal { off=2, kind=I64 } -> x9 - v16 Binop { op=lt, lhs=v13, rhs=v1 } -> x1 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + v23 LoadLocal { off=-2, kind=I64 } -> x1 + v24 LoadLocal { off=5, kind=I64 } -> x1 + v25 Binop { op=add, lhs=v12, rhs=v7 } -> x1 + v26 Imm(0) -> x9 + terminator Jmp(b2) (exit_acc=v25) block 2 start_pc=0 v17 LoadLocal { off=-2, kind=I64 } -> x9 v18 LoadLocal { off=3, kind=I64 } -> x9 @@ -30,13 +29,14 @@ fn ent_pc=0 n_params=4 variadic=false locals=2 v20 Binop { op=shl, lhs=v3, rhs=v5 } -> x9 v21 Binop { op=add, lhs=v12, rhs=v20 } -> x8 v22 Imm(0) -> x9 - terminator Jmp(b1) (exit_acc=v21) + terminator Jmp(b3) (exit_acc=v21) block 3 start_pc=0 - v23 LoadLocal { off=-2, kind=I64 } -> x1 - v24 LoadLocal { off=5, kind=I64 } -> x1 - v25 Binop { op=add, lhs=v12, rhs=v7 } -> x1 - v26 Imm(0) -> x9 - terminator Jmp(b2) (exit_acc=v25) + v12 Phi { incoming=[b0:v9, b2:v21], kind=I64 } -> x8 + v13 Phi { incoming=[b0:v9, b2:v25], kind=I64 } -> x1 + v14 LoadLocal { off=-1, kind=I64 } -> x9 + v15 LoadLocal { off=2, kind=I64 } -> x9 + v16 Binop { op=lt, lhs=v13, rhs=v1 } -> x1 + terminator Bnz { cond=v16, target=b1, fall=b4 } (exit_acc=v16) block 4 start_pc=0 v27 LoadLocal { off=5, kind=I64 } -> x1 terminator Return(v7) (exit_acc=v7) @@ -52,19 +52,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=5 v4 Imm(1) -> x1 v5 Call { target_pc=0, args=[v1, v2, v3, v4], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 v6 BinopI { op=eq, lhs=v5, rhs_imm=1 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + terminator Bz { cond=v6, target=b3, fall=b1 } (exit_acc=v6) block 1 start_pc=0 v7 Imm(0) -> x1 v8 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v7) + terminator Jmp(b2) (exit_acc=v7) block 2 start_pc=0 - v9 Imm(1) -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v9) - block 3 start_pc=0 - v11 Phi { incoming=[b1:v7, b2:v9], kind=I64 } -> x1 + v11 Phi { incoming=[b1:v7, b3:v9], kind=I64 } -> x1 v12 LoadLocal { off=-5, kind=I64 } -> x0 terminator Return(v11) (exit_acc=v11) + block 3 start_pc=0 + v9 Imm(1) -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variadic_agg_return_classes.ssa b/tests/snapshots/ssa/variadic_agg_return_classes.ssa index 28c1088ec..1d6990d1e 100644 --- a/tests/snapshots/ssa/variadic_agg_return_classes.ssa +++ b/tests/snapshots/ssa/variadic_agg_return_classes.ssa @@ -37,7 +37,7 @@ fn ent_pc=1 n_params=1 variadic=true locals=2 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=15 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(2) -> x7 @@ -48,19 +48,19 @@ fn ent_pc=2 n_params=0 variadic=false locals=15 v6 LocalAddr(-2) -> x0 v7 Load { addr=v6, disp=0, kind=F64 } -> d0 v8 Imm(4613937818241073152) -> x0 - v9 Binop { op=fne, lhs=v7, rhs=v8 } -> x3 + v9 Binop { op=fne, lhs=v7, rhs=v8 } -> x1 v10 Imm(0) -> x0 - terminator Bnz { cond=v9, target=b9, fall=b1 } (exit_acc=v9) + terminator Bnz { cond=v9, target=b10, fall=b1 } (exit_acc=v9) block 1 start_pc=0 v11 LocalAddr(-2) -> x0 v12 BinopI { op=add, lhs=v11, rhs_imm=8 } -> x1 v13 Load { addr=v11, disp=8, kind=F64 } -> d0 v14 Imm(4612248968380809216) -> x0 - v15 Binop { op=fne, lhs=v13, rhs=v14 } -> x3 + v15 Binop { op=fne, lhs=v13, rhs=v14 } -> x1 v16 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v17 Phi { incoming=[b9:v9, b1:v15], kind=I64 } -> x3 + v17 Phi { incoming=[b10:v9, b1:v15], kind=I64 } -> x1 v18 LoadLocal { off=-12, kind=I64 } -> x0 terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) block 3 start_pc=0 @@ -77,7 +77,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=15 v27 Imm(4602678819172646912) -> x0 v28 Binop { op=fne, lhs=v26, rhs=v27 } -> x1 v29 Imm(0) -> x0 - terminator Bnz { cond=v28, target=b10, fall=b5 } (exit_acc=v28) + terminator Bnz { cond=v28, target=b9, fall=b5 } (exit_acc=v28) block 5 start_pc=0 v30 LocalAddr(-6) -> x0 v31 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x1 @@ -86,7 +86,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=15 v34 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v33) block 6 start_pc=0 - v35 Phi { incoming=[b10:v28, b5:v33], kind=I64 } -> x1 + v35 Phi { incoming=[b9:v28, b5:v33], kind=I64 } -> x1 v36 LoadLocal { off=-15, kind=I64 } -> x0 terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) block 7 start_pc=0 @@ -96,9 +96,9 @@ fn ent_pc=2 n_params=0 variadic=false locals=15 v38 Imm(0) -> x0 terminator Return(v38) (exit_acc=v38) block 9 start_pc=0 - terminator Jmp(b2) - block 10 start_pc=0 terminator Jmp(b6) + block 10 start_pc=0 + terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variadic_fn_ptr_init.ssa b/tests/snapshots/ssa/variadic_fn_ptr_init.ssa index a5dc17975..8c86ab52a 100644 --- a/tests/snapshots/ssa/variadic_fn_ptr_init.ssa +++ b/tests/snapshots/ssa/variadic_fn_ptr_init.ssa @@ -10,29 +10,29 @@ fn ent_pc=0 n_params=2 variadic=true locals=5 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 LoadLocal { off=3, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 Extend { value=v8, kind=I32 } -> x6 + v16 LocalAddr(-3) -> x6 + v17 Imm(4) -> x7 + v18 Intrinsic { kind=5, args=[v16, v17] } -> x6 + v19 Load { addr=v18, disp=0, kind=I32 } -> x6 + v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 + v21 Imm(0) -> x6 + v22 Extend { value=v20, kind=I32 } -> x6 + terminator Jmp(b2) (exit_acc=v22) block 2 start_pc=0 v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 Extend { value=v8, kind=I32 } -> x2 - v16 LocalAddr(-3) -> x2 - v17 Imm(4) -> x6 - v18 Intrinsic { kind=5, args=[v16, v17] } -> x2 - v19 Load { addr=v18, disp=0, kind=I32 } -> x2 - v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 - v21 Imm(0) -> x2 - v22 Extend { value=v20, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v22) + v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 LoadLocal { off=3, kind=I32 } -> x6 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v23 LocalAddr(-3) -> x1 v24 Intrinsic { kind=6, args=[v23] } -> x1 diff --git a/tests/snapshots/ssa/variadic_fnptr_proto_erased.ssa b/tests/snapshots/ssa/variadic_fnptr_proto_erased.ssa index fc9bd9d9c..aa478d05b 100644 --- a/tests/snapshots/ssa/variadic_fnptr_proto_erased.ssa +++ b/tests/snapshots/ssa/variadic_fnptr_proto_erased.ssa @@ -10,28 +10,28 @@ fn ent_pc=0 n_params=1 variadic=true locals=5 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 LoadLocal { off=-4, kind=I64 } -> x6 + v16 LocalAddr(-3) -> x6 + v17 Imm(4) -> x7 + v18 Intrinsic { kind=5, args=[v16, v17] } -> x6 + v19 Load { addr=v18, disp=0, kind=I32 } -> x6 + v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 + v21 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 LoadLocal { off=-4, kind=I64 } -> x2 - v16 LocalAddr(-3) -> x2 - v17 Imm(4) -> x6 - v18 Intrinsic { kind=5, args=[v16, v17] } -> x2 - v19 Load { addr=v18, disp=0, kind=I32 } -> x2 - v20 Binop { op=add, lhs=v8, rhs=v19 } -> x0 - v21 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v20) + v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v20], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 LoadLocal { off=2, kind=I32 } -> x6 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v22 LocalAddr(-3) -> x1 v23 Intrinsic { kind=6, args=[v22] } -> x1 diff --git a/tests/snapshots/ssa/variadic_hfa_struct_arg.ssa b/tests/snapshots/ssa/variadic_hfa_struct_arg.ssa index af2581bf9..c0c13d5ba 100644 --- a/tests/snapshots/ssa/variadic_hfa_struct_arg.ssa +++ b/tests/snapshots/ssa/variadic_hfa_struct_arg.ssa @@ -39,19 +39,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=5 v10 Call { target_pc=0, args=[v8, v9], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 v11 Imm(4615626668101337088) -> x0 v12 Binop { op=feq, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + terminator Bz { cond=v12, target=b3, fall=b1 } (exit_acc=v12) block 1 start_pc=0 v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v13) + terminator Jmp(b2) (exit_acc=v13) block 2 start_pc=0 - v15 Imm(1) -> x1 - v16 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v15) - block 3 start_pc=0 - v17 Phi { incoming=[b1:v13, b2:v15], kind=I64 } -> x1 + v17 Phi { incoming=[b1:v13, b3:v15], kind=I64 } -> x1 v18 LoadLocal { off=-5, kind=I64 } -> x0 terminator Return(v17) (exit_acc=v17) + block 3 start_pc=0 + v15 Imm(1) -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variadic_macro_named_rest.ssa b/tests/snapshots/ssa/variadic_macro_named_rest.ssa index 69873d17d..244ede028 100644 --- a/tests/snapshots/ssa/variadic_macro_named_rest.ssa +++ b/tests/snapshots/ssa/variadic_macro_named_rest.ssa @@ -42,13 +42,25 @@ fn ent_pc=2 n_params=2 variadic=false locals=1 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v11], kind=I64 } -> x7 - v6 Phi { incoming=[b0:v3, b2:v14], kind=I64 } -> x6 + v5 Phi { incoming=[b0:v1, b4:v11], kind=I64 } -> x7 + v6 Phi { incoming=[b0:v3, b4:v14], kind=I64 } -> x6 v7 LoadLocal { off=2, kind=I64 } -> x0 v8 Load { addr=v5, disp=0, kind=I8 } -> x1 v9 Imm(0) -> x0 - terminator Bz { cond=v8, target=b6, fall=b4 } (exit_acc=v8) + terminator Bz { cond=v8, target=b5, fall=b2 } (exit_acc=v8) block 2 start_pc=0 + v21 LoadLocal { off=2, kind=I64 } -> x0 + v22 Load { addr=v5, disp=0, kind=I8 } -> x0 + v23 LoadLocal { off=3, kind=I64 } -> x1 + v24 Load { addr=v6, disp=0, kind=I8 } -> x1 + v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 + v26 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) + block 3 start_pc=0 + v27 Phi { incoming=[b5:v8, b2:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v27, target=b6, fall=b4 } (exit_acc=v27) + block 4 start_pc=0 v10 LoadLocal { off=2, kind=I64 } -> x0 v11 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x7 v12 Imm(0) -> x0 @@ -56,27 +68,15 @@ fn ent_pc=2 n_params=2 variadic=false locals=1 v14 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x6 v15 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 + block 5 start_pc=0 + terminator Jmp(b3) + block 6 start_pc=0 v16 LoadLocal { off=2, kind=I64 } -> x0 v17 Load { addr=v5, disp=0, kind=I8 } -> x0 v18 LoadLocal { off=3, kind=I64 } -> x1 v19 Load { addr=v6, disp=0, kind=I8 } -> x1 v20 Binop { op=eq, lhs=v17, rhs=v19 } -> x0 terminator Return(v20) (exit_acc=v20) - block 4 start_pc=0 - v21 LoadLocal { off=2, kind=I64 } -> x0 - v22 Load { addr=v5, disp=0, kind=I8 } -> x0 - v23 LoadLocal { off=3, kind=I64 } -> x1 - v24 Load { addr=v6, disp=0, kind=I8 } -> x1 - v25 Binop { op=eq, lhs=v22, rhs=v24 } -> x1 - v26 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v25) - block 5 start_pc=0 - v27 Phi { incoming=[b6:v8, b4:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) - block 6 start_pc=0 - terminator Jmp(b5) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=3 @@ -84,67 +84,67 @@ fn ent_pc=3 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(2) -> x1 - v3 Imm(3) -> x2 - v4 Extend { value=v1, kind=I32 } -> x6 - v5 Imm(0) -> x6 - v6 Extend { value=v2, kind=I32 } -> x6 - v7 Imm(0) -> x6 - v8 Extend { value=v3, kind=I32 } -> x6 - v9 Imm(0) -> x6 - v10 Binop { op=add, lhs=v1, rhs=v2 } -> x0 - v11 BinopI { op=shl, lhs=v10, rhs_imm=32 } -> x1 - v12 Extend { value=v10, kind=I32 } -> x1 - v13 Binop { op=add, lhs=v10, rhs=v3 } -> x0 - v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x1 - v15 Extend { value=v13, kind=I32 } -> x0 - v16 BinopI { op=ne, lhs=v15, rhs_imm=6 } -> x0 - terminator Bz { cond=v16, target=b2, fall=b1 } (exit_acc=v16) + v2 Imm(2) -> x0 + v3 Imm(3) -> x0 + v4 Imm(1) -> x0 + v5 Imm(0) -> x0 + v6 Imm(2) -> x0 + v7 Imm(0) -> x0 + v8 Imm(3) -> x0 + v9 Imm(0) -> x0 + v10 Imm(3) -> x0 + v11 Imm(12884901888) -> x0 + v12 Imm(3) -> x0 + v13 Imm(6) -> x0 + v14 Imm(25769803776) -> x0 + v15 Imm(6) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v16) block 1 start_pc=0 - v17 Imm(1) -> x0 - terminator Return(v17) (exit_acc=v17) - block 2 start_pc=0 v18 Imm(10) -> x0 - v19 Imm(-4) -> x1 - v20 Imm(-6) -> x2 - v21 Extend { value=v18, kind=I32 } -> x6 - v22 Imm(0) -> x6 - v23 Extend { value=v19, kind=I32 } -> x6 - v24 Imm(0) -> x6 - v25 Extend { value=v20, kind=I32 } -> x6 - v26 Imm(0) -> x6 - v27 Binop { op=add, lhs=v18, rhs=v19 } -> x0 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 - v29 Extend { value=v27, kind=I32 } -> x1 - v30 Binop { op=add, lhs=v27, rhs=v20 } -> x0 - v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x1 - v32 Extend { value=v30, kind=I32 } -> x0 - v33 BinopI { op=ne, lhs=v32, rhs_imm=0 } -> x0 - terminator Bz { cond=v33, target=b4, fall=b3 } (exit_acc=v33) - block 3 start_pc=0 - v34 Imm(2) -> x0 - terminator Return(v34) (exit_acc=v34) - block 4 start_pc=0 + v19 Imm(-4) -> x0 + v20 Imm(-6) -> x0 + v21 Imm(10) -> x0 + v22 Imm(0) -> x0 + v23 Imm(-4) -> x0 + v24 Imm(0) -> x0 + v25 Imm(-6) -> x0 + v26 Imm(0) -> x0 + v27 Imm(6) -> x0 + v28 Imm(25769803776) -> x0 + v29 Imm(6) -> x0 + v30 Imm(0) -> x0 + v31 Imm(0) -> x0 + v32 Imm(0) -> x0 + v33 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v33) + block 2 start_pc=0 v35 Imm(5) -> x0 - v36 Extend { value=v35, kind=I32 } -> x0 - v37 Imm(0) -> x1 - v38 BinopI { op=ne, lhs=v36, rhs_imm=5 } -> x0 - terminator Bz { cond=v38, target=b6, fall=b5 } (exit_acc=v38) - block 5 start_pc=0 - v39 Imm(3) -> x0 - terminator Return(v39) (exit_acc=v39) - block 6 start_pc=0 + v36 Imm(5) -> x0 + v37 Imm(0) -> x0 + v38 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v38) + block 3 start_pc=0 v40 ImmData(8) -> x7 v41 ImmData(13) -> x6 v42 Call { target_pc=2, args=[v40, v41], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 v43 BinopI { op=eq, lhs=v42, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) - block 7 start_pc=0 + terminator Bz { cond=v43, target=b5, fall=b4 } (exit_acc=v43) + block 4 start_pc=0 v44 Imm(4) -> x0 terminator Return(v44) (exit_acc=v44) - block 8 start_pc=0 + block 5 start_pc=0 v45 Imm(0) -> x0 terminator Return(v45) (exit_acc=v45) + block 6 start_pc=0 + v17 Imm(1) -> x0 + terminator Return(v17) (exit_acc=v17) + block 7 start_pc=0 + v34 Imm(2) -> x0 + terminator Return(v34) (exit_acc=v34) + block 8 start_pc=0 + v39 Imm(3) -> x0 + terminator Return(v39) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variadic_struct_arg.ssa b/tests/snapshots/ssa/variadic_struct_arg.ssa index 04ef77a15..071456513 100644 --- a/tests/snapshots/ssa/variadic_struct_arg.ssa +++ b/tests/snapshots/ssa/variadic_struct_arg.ssa @@ -10,38 +10,38 @@ fn ent_pc=0 n_params=1 variadic=true locals=6 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v29], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 LocalAddr(-3) -> x6 + v16 Imm(8) -> x7 + v17 Intrinsic { kind=5, args=[v15, v16] } -> x6 + v18 LocalAddr(-6) -> x7 + v19 Mcpy { dst=v18, src=v17, size=8 } -> x6 + v20 Extend { value=v8, kind=I32 } -> x6 + v21 LocalAddr(-6) -> x6 + v22 Load { addr=v21, disp=0, kind=I32 } -> x6 + v23 LocalAddr(-6) -> x7 + v24 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x8 + v25 Load { addr=v23, disp=4, kind=I32 } -> x7 + v26 Binop { op=add, lhs=v22, rhs=v25 } -> x6 + v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x7 + v28 Extend { value=v26, kind=I32 } -> x7 + v29 Binop { op=add, lhs=v8, rhs=v26 } -> x0 + v30 Imm(0) -> x6 + v31 Extend { value=v29, kind=I32 } -> x6 + terminator Jmp(b2) (exit_acc=v31) block 2 start_pc=0 v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 LocalAddr(-3) -> x2 - v16 Imm(8) -> x6 - v17 Intrinsic { kind=5, args=[v15, v16] } -> x2 - v18 LocalAddr(-6) -> x6 - v19 Mcpy { dst=v18, src=v17, size=8 } -> x2 - v20 Extend { value=v8, kind=I32 } -> x2 - v21 LocalAddr(-6) -> x2 - v22 Load { addr=v21, disp=0, kind=I32 } -> x2 - v23 LocalAddr(-6) -> x6 - v24 BinopI { op=add, lhs=v23, rhs_imm=4 } -> x7 - v25 Load { addr=v23, disp=4, kind=I32 } -> x6 - v26 Binop { op=add, lhs=v22, rhs=v25 } -> x2 - v27 BinopI { op=shl, lhs=v26, rhs_imm=32 } -> x6 - v28 Extend { value=v26, kind=I32 } -> x6 - v29 Binop { op=add, lhs=v8, rhs=v26 } -> x0 - v30 Imm(0) -> x2 - v31 Extend { value=v29, kind=I32 } -> x2 - terminator Jmp(b2) (exit_acc=v31) + v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v29], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 LoadLocal { off=2, kind=I32 } -> x6 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v32 LocalAddr(-3) -> x1 v33 Intrinsic { kind=6, args=[v32] } -> x1 diff --git a/tests/snapshots/ssa/variadic_struct_arg_16b.ssa b/tests/snapshots/ssa/variadic_struct_arg_16b.ssa index e0b9891bd..6630ed79c 100644 --- a/tests/snapshots/ssa/variadic_struct_arg_16b.ssa +++ b/tests/snapshots/ssa/variadic_struct_arg_16b.ssa @@ -10,36 +10,36 @@ fn ent_pc=0 n_params=1 variadic=true locals=7 v4 Imm(0) -> x1 v5 Imm(0) -> x0 v6 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v4) + terminator Jmp(b3) (exit_acc=v4) block 1 start_pc=0 - v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 - v8 Phi { incoming=[b0:v4, b2:v28], kind=I64 } -> x0 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 LoadLocal { off=2, kind=I32 } -> x6 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x2 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) + v15 LocalAddr(-3) -> x6 + v16 Imm(16) -> x7 + v17 Intrinsic { kind=5, args=[v15, v16] } -> x6 + v18 LocalAddr(-7) -> x7 + v19 Mcpy { dst=v18, src=v17, size=16 } -> x6 + v20 LoadLocal { off=-4, kind=I64 } -> x6 + v21 LocalAddr(-7) -> x6 + v22 Load { addr=v21, disp=0, kind=I64 } -> x6 + v23 LocalAddr(-7) -> x7 + v24 BinopI { op=add, lhs=v23, rhs_imm=8 } -> x8 + v25 Load { addr=v23, disp=8, kind=I64 } -> x7 + v26 BinopI { op=shl, lhs=v25, rhs_imm=1 } -> x7 + v27 Binop { op=add, lhs=v22, rhs=v26 } -> x6 + v28 Binop { op=add, lhs=v8, rhs=v27 } -> x0 + v29 Imm(0) -> x6 + terminator Jmp(b2) (exit_acc=v28) block 2 start_pc=0 v12 Extend { value=v7, kind=I32 } -> x1 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 + v13 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 v14 Imm(0) -> x2 - terminator Jmp(b1) (exit_acc=v13) + terminator Jmp(b3) (exit_acc=v13) block 3 start_pc=0 - v15 LocalAddr(-3) -> x2 - v16 Imm(16) -> x6 - v17 Intrinsic { kind=5, args=[v15, v16] } -> x2 - v18 LocalAddr(-7) -> x6 - v19 Mcpy { dst=v18, src=v17, size=16 } -> x2 - v20 LoadLocal { off=-4, kind=I64 } -> x2 - v21 LocalAddr(-7) -> x2 - v22 Load { addr=v21, disp=0, kind=I64 } -> x2 - v23 LocalAddr(-7) -> x6 - v24 BinopI { op=add, lhs=v23, rhs_imm=8 } -> x7 - v25 Load { addr=v23, disp=8, kind=I64 } -> x6 - v26 BinopI { op=shl, lhs=v25, rhs_imm=1 } -> x6 - v27 Binop { op=add, lhs=v22, rhs=v26 } -> x2 - v28 Binop { op=add, lhs=v8, rhs=v27 } -> x0 - v29 Imm(0) -> x2 - terminator Jmp(b2) (exit_acc=v28) + v7 Phi { incoming=[b0:v4, b2:v13], kind=I64 } -> x1 + v8 Phi { incoming=[b0:v4, b2:v28], kind=I64 } -> x0 + v9 Extend { value=v7, kind=I32 } -> x2 + v10 LoadLocal { off=2, kind=I32 } -> x6 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x6 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v30 LocalAddr(-3) -> x1 v31 Intrinsic { kind=6, args=[v30] } -> x1 diff --git a/tests/snapshots/ssa/variadic_struct_by_value_arg.ssa b/tests/snapshots/ssa/variadic_struct_by_value_arg.ssa index 1cce69dea..dbdb47773 100644 --- a/tests/snapshots/ssa/variadic_struct_by_value_arg.ssa +++ b/tests/snapshots/ssa/variadic_struct_by_value_arg.ssa @@ -45,7 +45,7 @@ fn ent_pc=1 n_params=3 variadic=true locals=7 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=7 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-2) -> x0 @@ -55,7 +55,7 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 v5 LocalAddr(-2) -> x6 v6 ImmData(68) -> x2 v7 Imm(99) -> x1 - v8 Call { target_pc=1, args=[v4, v5, v6, v7], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x3 + v8 Call { target_pc=1, args=[v4, v5, v6, v7], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x6 v9 Imm(0) -> x0 v10 LoadLocal { off=-3, kind=I64 } -> x0 v11 BinopI { op=ne, lhs=v8, rhs_imm=303 } -> x0 diff --git a/tests/snapshots/ssa/variadic_struct_return.ssa b/tests/snapshots/ssa/variadic_struct_return.ssa index d6dc67336..481b2ac82 100644 --- a/tests/snapshots/ssa/variadic_struct_return.ssa +++ b/tests/snapshots/ssa/variadic_struct_return.ssa @@ -44,28 +44,28 @@ fn ent_pc=2 n_params=1 variadic=true locals=6 v8 BinopI { op=add, lhs=v7, rhs_imm=8 } -> x1 v9 Store { addr=v7, disp=8, value=v5, kind=I64 } -> - v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v5) + terminator Jmp(b3) (exit_acc=v5) block 1 start_pc=0 - v11 Phi { incoming=[b0:v5, b2:v16], kind=I64 } -> x2 - v12 Extend { value=v11, kind=I32 } -> x0 - v13 LoadLocal { off=2, kind=I32 } -> x1 - v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v18 LocalAddr(-5) -> x1 + v19 Load { addr=v18, disp=0, kind=I64 } -> x6 + v20 LocalAddr(-3) -> x7 + v21 Imm(4) -> x8 + v22 Intrinsic { kind=5, args=[v20, v21] } -> x7 + v23 Load { addr=v22, disp=0, kind=I32 } -> x7 + v24 Binop { op=add, lhs=v19, rhs=v23 } -> x6 + v25 Store { addr=v18, disp=0, value=v24, kind=I64 } -> - + terminator Jmp(b2) (exit_acc=v25) block 2 start_pc=0 - v15 Extend { value=v11, kind=I32 } -> x0 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x2 + v15 Extend { value=v11, kind=I32 } -> x1 + v16 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x2 v17 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v16) + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - v18 LocalAddr(-5) -> x0 - v19 Load { addr=v18, disp=0, kind=I64 } -> x1 - v20 LocalAddr(-3) -> x6 - v21 Imm(4) -> x7 - v22 Intrinsic { kind=5, args=[v20, v21] } -> x6 - v23 Load { addr=v22, disp=0, kind=I32 } -> x6 - v24 Binop { op=add, lhs=v19, rhs=v23 } -> x1 - v25 Store { addr=v18, disp=0, value=v24, kind=I64 } -> - - terminator Jmp(b2) (exit_acc=v25) + v11 Phi { incoming=[b0:v5, b2:v16], kind=I64 } -> x2 + v12 Extend { value=v11, kind=I32 } -> x0 + v13 LoadLocal { off=2, kind=I32 } -> x1 + v14 Binop { op=lt, lhs=v12, rhs=v13 } -> x1 + terminator Bnz { cond=v14, target=b1, fall=b4 } (exit_acc=v14) block 4 start_pc=0 v26 LocalAddr(-3) -> x0 v27 Intrinsic { kind=6, args=[v26] } -> x0 @@ -78,7 +78,7 @@ fn ent_pc=2 n_params=1 variadic=true locals=6 ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=22 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x7 @@ -106,18 +106,18 @@ fn ent_pc=3 n_params=0 variadic=false locals=22 v19 Mcpy { dst=v18, src=v17, size=16 } -> x0 v20 LocalAddr(-4) -> x0 v21 Load { addr=v20, disp=0, kind=I64 } -> x0 - v22 BinopI { op=ne, lhs=v21, rhs_imm=11 } -> x3 + v22 BinopI { op=ne, lhs=v21, rhs_imm=11 } -> x1 v23 Imm(0) -> x0 - terminator Bnz { cond=v22, target=b11, fall=b3 } (exit_acc=v22) + terminator Bnz { cond=v22, target=b12, fall=b3 } (exit_acc=v22) block 3 start_pc=0 v24 LocalAddr(-4) -> x0 v25 BinopI { op=add, lhs=v24, rhs_imm=8 } -> x1 v26 Load { addr=v24, disp=8, kind=I64 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=22 } -> x3 + v27 BinopI { op=ne, lhs=v26, rhs_imm=22 } -> x1 v28 Imm(0) -> x0 terminator Jmp(b4) (exit_acc=v27) block 4 start_pc=0 - v29 Phi { incoming=[b11:v22, b3:v27], kind=I64 } -> x3 + v29 Phi { incoming=[b12:v22, b3:v27], kind=I64 } -> x1 v30 LoadLocal { off=-19, kind=I64 } -> x0 terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 @@ -137,7 +137,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=22 v42 Load { addr=v41, disp=0, kind=I64 } -> x0 v43 BinopI { op=ne, lhs=v42, rhs_imm=100 } -> x1 v44 Imm(0) -> x0 - terminator Bnz { cond=v43, target=b12, fall=b7 } (exit_acc=v43) + terminator Bnz { cond=v43, target=b11, fall=b7 } (exit_acc=v43) block 7 start_pc=0 v45 LocalAddr(-8) -> x0 v46 BinopI { op=add, lhs=v45, rhs_imm=8 } -> x1 @@ -146,7 +146,7 @@ fn ent_pc=3 n_params=0 variadic=false locals=22 v49 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v48) block 8 start_pc=0 - v50 Phi { incoming=[b12:v43, b7:v48], kind=I64 } -> x1 + v50 Phi { incoming=[b11:v43, b7:v48], kind=I64 } -> x1 v51 LoadLocal { off=-22, kind=I64 } -> x0 terminator Bz { cond=v50, target=b10, fall=b9 } (exit_acc=v50) block 9 start_pc=0 @@ -156,9 +156,9 @@ fn ent_pc=3 n_params=0 variadic=false locals=22 v53 Imm(0) -> x0 terminator Return(v53) (exit_acc=v53) block 11 start_pc=0 - terminator Jmp(b4) - block 12 start_pc=0 terminator Jmp(b8) + block 12 start_pc=0 + terminator Jmp(b4) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/variadic_union_struct_return.ssa b/tests/snapshots/ssa/variadic_union_struct_return.ssa index 356c99c2b..5bdb9655d 100644 --- a/tests/snapshots/ssa/variadic_union_struct_return.ssa +++ b/tests/snapshots/ssa/variadic_union_struct_return.ssa @@ -23,19 +23,15 @@ fn ent_pc=0 n_params=2 variadic=true locals=8 v16 LocalAddr(-7) -> x2 v17 LoadLocal { off=-4, kind=I64 } -> x6 v18 BinopI { op=ne, lhs=v7, rhs_imm=0 } -> x6 - terminator Bz { cond=v18, target=b2, fall=b1 } (exit_acc=v18) + terminator Bz { cond=v18, target=b3, fall=b1 } (exit_acc=v18) block 1 start_pc=0 v19 LoadLocal { off=-4, kind=I64 } -> x6 v20 Imm(0) -> x6 v21 Load { addr=v7, disp=0, kind=I8 } -> x6 v22 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v21) + terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 - v23 Imm(0) -> x6 - v24 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v23) - block 3 start_pc=0 - v25 Phi { incoming=[b1:v21, b2:v23], kind=I64 } -> x6 + v25 Phi { incoming=[b1:v21, b3:v23], kind=I64 } -> x6 v26 LoadLocal { off=-8, kind=I64 } -> x0 v27 Extend { value=v12, kind=I32 } -> x0 v28 Binop { op=add, lhs=v25, rhs=v12 } -> x0 @@ -48,6 +44,10 @@ fn ent_pc=0 n_params=2 variadic=true locals=8 v35 Store { addr=v32, disp=8, value=v34, kind=I64 } -> - v36 LocalAddr(-7) -> x0 terminator Return(v36) (exit_acc=v36) + block 3 start_pc=0 + v23 Imm(0) -> x6 + v24 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v23) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=17 diff --git a/tests/snapshots/ssa/vfork_shared_stack_slot_reuse.ssa b/tests/snapshots/ssa/vfork_shared_stack_slot_reuse.ssa new file mode 100644 index 000000000..30c77610e --- /dev/null +++ b/tests/snapshots/ssa/vfork_shared_stack_slot_reuse.ssa @@ -0,0 +1,850 @@ +; --- SSA dump (ok=true) ent_pc=6 --- +; name=child_exec +fn ent_pc=6 n_params=20 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 ParamRef(2, kind=I32) -> x2 + v6 Imm(0) -> x0 + v7 ParamRef(3, kind=I32) -> x1 + v8 Imm(0) -> x0 + v9 ParamRef(4, kind=I32) -> x8 + v10 Imm(0) -> x0 + v11 ParamRef(5, kind=I32) -> x9 + v12 Imm(0) -> x0 + v13 LoadLocal { off=2, kind=I32 } -> x0 + v14 LoadLocal { off=3, kind=I32 } -> x0 + v15 Binop { op=add, lhs=v1, rhs=v3 } -> x0 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x6 + v17 Extend { value=v15, kind=I32 } -> x6 + v18 LoadLocal { off=4, kind=I32 } -> x6 + v19 Binop { op=add, lhs=v15, rhs=v5 } -> x0 + v20 BinopI { op=shl, lhs=v19, rhs_imm=32 } -> x2 + v21 Extend { value=v19, kind=I32 } -> x2 + v22 LoadLocal { off=5, kind=I32 } -> x2 + v23 Binop { op=add, lhs=v19, rhs=v7 } -> x0 + v24 BinopI { op=shl, lhs=v23, rhs_imm=32 } -> x1 + v25 Extend { value=v23, kind=I32 } -> x1 + v26 LoadLocal { off=6, kind=I32 } -> x1 + v27 Binop { op=add, lhs=v23, rhs=v9 } -> x0 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 + v29 Extend { value=v27, kind=I32 } -> x1 + v30 LoadLocal { off=7, kind=I32 } -> x1 + v31 Binop { op=add, lhs=v27, rhs=v11 } -> x0 + v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x1 + v33 Extend { value=v31, kind=I32 } -> x1 + v34 LoadLocal { off=8, kind=I32 } -> x1 + v35 Binop { op=add, lhs=v31, rhs=v34 } -> x0 + v36 BinopI { op=shl, lhs=v35, rhs_imm=32 } -> x1 + v37 Extend { value=v35, kind=I32 } -> x1 + v38 LoadLocal { off=9, kind=I32 } -> x1 + v39 Binop { op=add, lhs=v35, rhs=v38 } -> x0 + v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x1 + v41 Extend { value=v39, kind=I32 } -> x1 + v42 LoadLocal { off=10, kind=I32 } -> x1 + v43 Binop { op=add, lhs=v39, rhs=v42 } -> x0 + v44 BinopI { op=shl, lhs=v43, rhs_imm=32 } -> x1 + v45 Extend { value=v43, kind=I32 } -> x1 + v46 LoadLocal { off=11, kind=I32 } -> x1 + v47 Binop { op=add, lhs=v43, rhs=v46 } -> x0 + v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x1 + v49 Extend { value=v47, kind=I32 } -> x1 + v50 LoadLocal { off=12, kind=I32 } -> x1 + v51 Binop { op=add, lhs=v47, rhs=v50 } -> x0 + v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x1 + v53 Extend { value=v51, kind=I32 } -> x1 + v54 LoadLocal { off=13, kind=I32 } -> x1 + v55 Binop { op=add, lhs=v51, rhs=v54 } -> x0 + v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 + v57 Extend { value=v55, kind=I32 } -> x1 + v58 LoadLocal { off=14, kind=I32 } -> x1 + v59 Binop { op=add, lhs=v55, rhs=v58 } -> x0 + v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x1 + v61 Extend { value=v59, kind=I32 } -> x1 + v62 LoadLocal { off=15, kind=I32 } -> x1 + v63 Binop { op=add, lhs=v59, rhs=v62 } -> x0 + v64 BinopI { op=shl, lhs=v63, rhs_imm=32 } -> x1 + v65 Extend { value=v63, kind=I32 } -> x1 + v66 LoadLocal { off=16, kind=I32 } -> x1 + v67 Binop { op=add, lhs=v63, rhs=v66 } -> x0 + v68 BinopI { op=shl, lhs=v67, rhs_imm=32 } -> x1 + v69 Extend { value=v67, kind=I32 } -> x1 + v70 LoadLocal { off=17, kind=I32 } -> x1 + v71 Binop { op=add, lhs=v67, rhs=v70 } -> x0 + v72 BinopI { op=shl, lhs=v71, rhs_imm=32 } -> x1 + v73 Extend { value=v71, kind=I32 } -> x1 + v74 LoadLocal { off=18, kind=I32 } -> x1 + v75 Binop { op=add, lhs=v71, rhs=v74 } -> x0 + v76 BinopI { op=shl, lhs=v75, rhs_imm=32 } -> x1 + v77 Extend { value=v75, kind=I32 } -> x1 + v78 LoadLocal { off=19, kind=I32 } -> x1 + v79 Binop { op=add, lhs=v75, rhs=v78 } -> x0 + v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x1 + v81 Extend { value=v79, kind=I32 } -> x1 + v82 LoadLocal { off=20, kind=I32 } -> x1 + v83 Binop { op=add, lhs=v79, rhs=v82 } -> x0 + v84 BinopI { op=shl, lhs=v83, rhs_imm=32 } -> x1 + v85 Extend { value=v83, kind=I32 } -> x1 + v86 LoadLocal { off=21, kind=I32 } -> x1 + v87 Binop { op=add, lhs=v83, rhs=v86 } -> x0 + v88 BinopI { op=shl, lhs=v87, rhs_imm=32 } -> x1 + v89 Extend { value=v87, kind=I32 } -> x0 + v90 BinopI { op=and, lhs=v89, rhs_imm=127 } -> x0 + terminator Return(v90) (exit_acc=v90) +; --- SSA dump (ok=true) ent_pc=7 --- +; name=main +fn ent_pc=7 n_params=0 variadic=false locals=57 + spill_count=118 gpr_used=[3, 12, 13, 14, 15] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x1 + v2 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v1) + block 1 start_pc=0 + v9 ImmData(80) -> x2 + v10 Extend { value=v3, kind=I32 } -> x6 + v11 BinopI { op=shl, lhs=v4, rhs_imm=2 } -> x6 + v12 Binop { op=add, lhs=v9, rhs=v11 } -> x6 + v13 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x6 + v14 BinopI { op=shl, lhs=v13, rhs_imm=32 } -> x7 + v15 Extend { value=v13, kind=I32 } -> x7 + v16 StoreIndexed { base=v9, index=v4, scale=4, value=v13, kind=I32 } -> - + terminator Jmp(b2) (exit_acc=v16) + block 2 start_pc=0 + v6 Extend { value=v3, kind=I32 } -> x1 + v7 BinopI { op=add, lhs=v4, rhs_imm=1 } -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v7) + block 3 start_pc=0 + v3 Phi { incoming=[b0:v1, b2:v7], kind=I64 } -> x1 + v4 Extend { value=v3, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=64 } -> x2 + terminator Bnz { cond=v5, target=b1, fall=b4 } (exit_acc=v5) + block 4 start_pc=0 + v17 ImmData(80) -> x0 + v18 Imm(0) -> x1 + v19 Load { addr=v17, disp=0, kind=I32 } -> x1 + v20 BinopI { op=mul, lhs=v19, rhs_imm=3 } -> x1 + v21 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x2 + v22 Extend { value=v20, kind=I32 } -> x2 + v23 BinopI { op=shl, lhs=v20, rhs_imm=32 } -> x1 + v24 Extend { value=v22, kind=I32 } -> x3 + v25 Imm(0) -> x1 + v26 Imm(4) -> x1 + v27 BinopI { op=add, lhs=v17, rhs_imm=4 } -> x1 + v28 Load { addr=v17, disp=4, kind=I32 } -> x1 + v29 BinopI { op=mul, lhs=v28, rhs_imm=3 } -> x1 + v30 BinopI { op=shl, lhs=v29, rhs_imm=32 } -> x2 + v31 Extend { value=v29, kind=I32 } -> x2 + v32 BinopI { op=add, lhs=v29, rhs_imm=1 } -> x1 + v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x2 + v34 Extend { value=v32, kind=I32 } -> x12 + v35 Imm(0) -> x1 + v36 Imm(8) -> x1 + v37 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x1 + v38 Load { addr=v17, disp=8, kind=I32 } -> x1 + v39 BinopI { op=mul, lhs=v38, rhs_imm=3 } -> x1 + v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x2 + v41 Extend { value=v39, kind=I32 } -> x2 + v42 BinopI { op=add, lhs=v39, rhs_imm=2 } -> x1 + v43 BinopI { op=shl, lhs=v42, rhs_imm=32 } -> x2 + v44 Extend { value=v42, kind=I32 } -> x13 + v45 Imm(0) -> x1 + v46 Imm(12) -> x1 + v47 BinopI { op=add, lhs=v17, rhs_imm=12 } -> x1 + v48 Load { addr=v17, disp=12, kind=I32 } -> x1 + v49 BinopI { op=mul, lhs=v48, rhs_imm=3 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=32 } -> x2 + v51 Extend { value=v49, kind=I32 } -> x2 + v52 BinopI { op=add, lhs=v49, rhs_imm=3 } -> x1 + v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> x2 + v54 Extend { value=v52, kind=I32 } -> x14 + v55 Imm(0) -> x1 + v56 Imm(16) -> x1 + v57 BinopI { op=add, lhs=v17, rhs_imm=16 } -> x1 + v58 Load { addr=v17, disp=16, kind=I32 } -> x1 + v59 BinopI { op=mul, lhs=v58, rhs_imm=3 } -> x1 + v60 BinopI { op=shl, lhs=v59, rhs_imm=32 } -> x2 + v61 Extend { value=v59, kind=I32 } -> x2 + v62 BinopI { op=add, lhs=v59, rhs_imm=4 } -> x1 + v63 BinopI { op=shl, lhs=v62, rhs_imm=32 } -> x2 + v64 Extend { value=v62, kind=I32 } -> x15 + v65 Imm(0) -> x1 + v66 Imm(20) -> x1 + v67 BinopI { op=add, lhs=v17, rhs_imm=20 } -> x1 + v68 Load { addr=v17, disp=20, kind=I32 } -> x1 + v69 BinopI { op=mul, lhs=v68, rhs_imm=3 } -> x1 + v70 BinopI { op=shl, lhs=v69, rhs_imm=32 } -> x2 + v71 Extend { value=v69, kind=I32 } -> x2 + v72 BinopI { op=add, lhs=v69, rhs_imm=5 } -> x1 + v73 BinopI { op=shl, lhs=v72, rhs_imm=32 } -> x2 + v74 Extend { value=v72, kind=I32 } -> [spill 0] + v75 Imm(0) -> x1 + v76 Imm(24) -> x1 + v77 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x1 + v78 Load { addr=v17, disp=24, kind=I32 } -> x1 + v79 BinopI { op=mul, lhs=v78, rhs_imm=3 } -> x1 + v80 BinopI { op=shl, lhs=v79, rhs_imm=32 } -> x2 + v81 Extend { value=v79, kind=I32 } -> x2 + v82 BinopI { op=add, lhs=v79, rhs_imm=6 } -> x1 + v83 BinopI { op=shl, lhs=v82, rhs_imm=32 } -> x2 + v84 Extend { value=v82, kind=I32 } -> [spill 1] + v85 Imm(0) -> x1 + v86 Imm(28) -> x1 + v87 BinopI { op=add, lhs=v17, rhs_imm=28 } -> x1 + v88 Load { addr=v17, disp=28, kind=I32 } -> x1 + v89 BinopI { op=mul, lhs=v88, rhs_imm=3 } -> x1 + v90 BinopI { op=shl, lhs=v89, rhs_imm=32 } -> x2 + v91 Extend { value=v89, kind=I32 } -> x2 + v92 BinopI { op=add, lhs=v89, rhs_imm=7 } -> x1 + v93 BinopI { op=shl, lhs=v92, rhs_imm=32 } -> x2 + v94 Extend { value=v92, kind=I32 } -> [spill 2] + v95 Imm(0) -> x1 + v96 Imm(32) -> x1 + v97 BinopI { op=add, lhs=v17, rhs_imm=32 } -> x1 + v98 Load { addr=v17, disp=32, kind=I32 } -> x1 + v99 BinopI { op=mul, lhs=v98, rhs_imm=3 } -> x1 + v100 BinopI { op=shl, lhs=v99, rhs_imm=32 } -> x2 + v101 Extend { value=v99, kind=I32 } -> x2 + v102 BinopI { op=add, lhs=v99, rhs_imm=8 } -> x1 + v103 BinopI { op=shl, lhs=v102, rhs_imm=32 } -> x2 + v104 Extend { value=v102, kind=I32 } -> [spill 3] + v105 Imm(0) -> x1 + v106 Imm(36) -> x1 + v107 BinopI { op=add, lhs=v17, rhs_imm=36 } -> x1 + v108 Load { addr=v17, disp=36, kind=I32 } -> x1 + v109 BinopI { op=mul, lhs=v108, rhs_imm=3 } -> x1 + v110 BinopI { op=shl, lhs=v109, rhs_imm=32 } -> x2 + v111 Extend { value=v109, kind=I32 } -> x2 + v112 BinopI { op=add, lhs=v109, rhs_imm=9 } -> x1 + v113 BinopI { op=shl, lhs=v112, rhs_imm=32 } -> x2 + v114 Extend { value=v112, kind=I32 } -> [spill 4] + v115 Imm(0) -> x1 + v116 Imm(40) -> x1 + v117 BinopI { op=add, lhs=v17, rhs_imm=40 } -> x1 + v118 Load { addr=v17, disp=40, kind=I32 } -> x1 + v119 BinopI { op=mul, lhs=v118, rhs_imm=3 } -> x1 + v120 BinopI { op=shl, lhs=v119, rhs_imm=32 } -> x2 + v121 Extend { value=v119, kind=I32 } -> x2 + v122 BinopI { op=add, lhs=v119, rhs_imm=10 } -> x1 + v123 BinopI { op=shl, lhs=v122, rhs_imm=32 } -> x2 + v124 Extend { value=v122, kind=I32 } -> [spill 5] + v125 Imm(0) -> x1 + v126 Imm(44) -> x1 + v127 BinopI { op=add, lhs=v17, rhs_imm=44 } -> x1 + v128 Load { addr=v17, disp=44, kind=I32 } -> x0 + v129 BinopI { op=mul, lhs=v128, rhs_imm=3 } -> x0 + v130 BinopI { op=shl, lhs=v129, rhs_imm=32 } -> x1 + v131 Extend { value=v129, kind=I32 } -> x1 + v132 BinopI { op=add, lhs=v129, rhs_imm=11 } -> x0 + v133 BinopI { op=shl, lhs=v132, rhs_imm=32 } -> x1 + v134 Extend { value=v132, kind=I32 } -> [spill 6] + v135 Imm(0) -> x0 + v136 CallExt { binding_idx=166, args=[], fp_arg_mask=0x0 } -> x0 + v137 Imm(0) -> x1 + v138 Extend { value=v136, kind=I32 } -> x1 + v139 BinopI { op=lt, lhs=v138, rhs_imm=0 } -> x2 + terminator Bz { cond=v139, target=b6, fall=b5 } (exit_acc=v139) + block 5 start_pc=0 + v140 ImmData(32) -> x7 + v141 CallExt { binding_idx=0, args=[v140], fp_arg_mask=0x0 } -> x0 + v142 Imm(2) -> x0 + terminator Return(v142) (exit_acc=v142) + block 6 start_pc=0 + v143 Extend { value=v136, kind=I32 } -> x2 + v144 BinopI { op=ne, lhs=v138, rhs_imm=0 } -> x1 + terminator Bz { cond=v144, target=b46, fall=b7 } (exit_acc=v144) + block 7 start_pc=0 + v145 Imm(0) -> [spill 117] + v146 StoreLocal { off=-15, value=v145, kind=I32 } -> - + v147 Extend { value=v136, kind=I32 } -> x7 + v148 LocalAddr(-15) -> x6 + v149 CallExt { binding_idx=264, args=[v147, v148, v145], fp_arg_mask=0x0 } -> x0 + v150 Imm(0) -> x0 + v151 LoadLocal { off=-2, kind=I32 } -> x0 + v152 ImmData(80) -> x0 + v153 Load { addr=v152, disp=0, kind=I32 } -> x0 + v154 BinopI { op=mul, lhs=v153, rhs_imm=3 } -> x0 + v155 BinopI { op=shl, lhs=v154, rhs_imm=32 } -> x1 + v156 Extend { value=v154, kind=I32 } -> x1 + v157 BinopI { op=shl, lhs=v154, rhs_imm=32 } -> x0 + v158 Extend { value=v156, kind=I32 } -> x0 + v159 Binop { op=ne, lhs=v24, rhs=v158 } -> x0 + terminator Bz { cond=v159, target=b45, fall=b8 } (exit_acc=v159) + block 8 start_pc=0 + v384 LoadLocal { off=-16, kind=I32 } -> x0 + v385 Imm(1) -> x0 + v386 Imm(4294967296) -> x0 + v387 Imm(1) -> [spill 117] + v388 Imm(0) -> x0 + v389 Imm(1) -> x0 + terminator Jmp(b9) (exit_acc=v389) + block 9 start_pc=0 + v390 Phi { incoming=[b45:v145, b8:v387], kind=I64 } -> [spill 117] + v391 LoadLocal { off=-3, kind=I32 } -> x0 + v392 ImmData(80) -> x0 + v393 Imm(4) -> x1 + v394 BinopI { op=add, lhs=v392, rhs_imm=4 } -> x1 + v395 Load { addr=v392, disp=4, kind=I32 } -> x0 + v396 BinopI { op=mul, lhs=v395, rhs_imm=3 } -> x0 + v397 BinopI { op=shl, lhs=v396, rhs_imm=32 } -> x1 + v398 Extend { value=v396, kind=I32 } -> x1 + v399 BinopI { op=add, lhs=v396, rhs_imm=1 } -> x0 + v400 BinopI { op=shl, lhs=v399, rhs_imm=32 } -> x1 + v401 Extend { value=v399, kind=I32 } -> x0 + v402 Binop { op=ne, lhs=v34, rhs=v401 } -> x0 + terminator Bz { cond=v402, target=b44, fall=b10 } (exit_acc=v402) + block 10 start_pc=0 + v403 Extend { value=v390, kind=I32 } -> x0 + v404 Imm(2) -> x0 + v405 Imm(8589934592) -> x0 + v406 BinopI { op=or, lhs=v390, rhs_imm=2 } -> [spill 117] + v407 Imm(0) -> x0 + v408 Extend { value=v406, kind=I32 } -> x0 + terminator Jmp(b11) (exit_acc=v408) + block 11 start_pc=0 + v409 Phi { incoming=[b44:v390, b10:v406], kind=I64 } -> [spill 117] + v410 LoadLocal { off=-4, kind=I32 } -> x0 + v411 ImmData(80) -> x0 + v412 Imm(8) -> x1 + v413 BinopI { op=add, lhs=v411, rhs_imm=8 } -> x1 + v414 Load { addr=v411, disp=8, kind=I32 } -> x0 + v415 BinopI { op=mul, lhs=v414, rhs_imm=3 } -> x0 + v416 BinopI { op=shl, lhs=v415, rhs_imm=32 } -> x1 + v417 Extend { value=v415, kind=I32 } -> x1 + v418 BinopI { op=add, lhs=v415, rhs_imm=2 } -> x0 + v419 BinopI { op=shl, lhs=v418, rhs_imm=32 } -> x1 + v420 Extend { value=v418, kind=I32 } -> x0 + v421 Binop { op=ne, lhs=v44, rhs=v420 } -> x0 + terminator Bz { cond=v421, target=b43, fall=b12 } (exit_acc=v421) + block 12 start_pc=0 + v422 Extend { value=v409, kind=I32 } -> x0 + v423 Imm(4) -> x0 + v424 Imm(17179869184) -> x0 + v425 BinopI { op=or, lhs=v409, rhs_imm=4 } -> [spill 117] + v426 Imm(0) -> x0 + v427 Extend { value=v425, kind=I32 } -> x0 + terminator Jmp(b13) (exit_acc=v427) + block 13 start_pc=0 + v428 Phi { incoming=[b43:v409, b12:v425], kind=I64 } -> [spill 117] + v429 LoadLocal { off=-5, kind=I32 } -> x0 + v430 ImmData(80) -> x0 + v431 Imm(12) -> x1 + v432 BinopI { op=add, lhs=v430, rhs_imm=12 } -> x1 + v433 Load { addr=v430, disp=12, kind=I32 } -> x0 + v434 BinopI { op=mul, lhs=v433, rhs_imm=3 } -> x0 + v435 BinopI { op=shl, lhs=v434, rhs_imm=32 } -> x1 + v436 Extend { value=v434, kind=I32 } -> x1 + v437 BinopI { op=add, lhs=v434, rhs_imm=3 } -> x0 + v438 BinopI { op=shl, lhs=v437, rhs_imm=32 } -> x1 + v439 Extend { value=v437, kind=I32 } -> x0 + v440 Binop { op=ne, lhs=v54, rhs=v439 } -> x0 + terminator Bz { cond=v440, target=b42, fall=b14 } (exit_acc=v440) + block 14 start_pc=0 + v441 Extend { value=v428, kind=I32 } -> x0 + v442 Imm(8) -> x0 + v443 Imm(34359738368) -> x0 + v444 BinopI { op=or, lhs=v428, rhs_imm=8 } -> [spill 117] + v445 Imm(0) -> x0 + v446 Extend { value=v444, kind=I32 } -> x0 + terminator Jmp(b15) (exit_acc=v446) + block 15 start_pc=0 + v447 Phi { incoming=[b42:v428, b14:v444], kind=I64 } -> [spill 117] + v448 LoadLocal { off=-6, kind=I32 } -> x0 + v449 ImmData(80) -> x0 + v450 Imm(16) -> x1 + v451 BinopI { op=add, lhs=v449, rhs_imm=16 } -> x1 + v452 Load { addr=v449, disp=16, kind=I32 } -> x0 + v453 BinopI { op=mul, lhs=v452, rhs_imm=3 } -> x0 + v454 BinopI { op=shl, lhs=v453, rhs_imm=32 } -> x1 + v455 Extend { value=v453, kind=I32 } -> x1 + v456 BinopI { op=add, lhs=v453, rhs_imm=4 } -> x0 + v457 BinopI { op=shl, lhs=v456, rhs_imm=32 } -> x1 + v458 Extend { value=v456, kind=I32 } -> x0 + v459 Binop { op=ne, lhs=v64, rhs=v458 } -> x0 + terminator Bz { cond=v459, target=b41, fall=b16 } (exit_acc=v459) + block 16 start_pc=0 + v460 Extend { value=v447, kind=I32 } -> x0 + v461 Imm(16) -> x0 + v462 Imm(68719476736) -> x0 + v463 BinopI { op=or, lhs=v447, rhs_imm=16 } -> [spill 117] + v464 Imm(0) -> x0 + v465 Extend { value=v463, kind=I32 } -> x0 + terminator Jmp(b17) (exit_acc=v465) + block 17 start_pc=0 + v466 Phi { incoming=[b41:v447, b16:v463], kind=I64 } -> [spill 117] + v467 LoadLocal { off=-7, kind=I32 } -> x0 + v468 ImmData(80) -> x0 + v469 Imm(20) -> x1 + v470 BinopI { op=add, lhs=v468, rhs_imm=20 } -> x1 + v471 Load { addr=v468, disp=20, kind=I32 } -> x0 + v472 BinopI { op=mul, lhs=v471, rhs_imm=3 } -> x0 + v473 BinopI { op=shl, lhs=v472, rhs_imm=32 } -> x1 + v474 Extend { value=v472, kind=I32 } -> x1 + v475 BinopI { op=add, lhs=v472, rhs_imm=5 } -> x0 + v476 BinopI { op=shl, lhs=v475, rhs_imm=32 } -> x1 + v477 Extend { value=v475, kind=I32 } -> x0 + v478 Binop { op=ne, lhs=v74, rhs=v477 } -> x0 + terminator Bz { cond=v478, target=b40, fall=b18 } (exit_acc=v478) + block 18 start_pc=0 + v479 Extend { value=v466, kind=I32 } -> x0 + v480 Imm(32) -> x0 + v481 Imm(137438953472) -> x0 + v482 BinopI { op=or, lhs=v466, rhs_imm=32 } -> [spill 117] + v483 Imm(0) -> x0 + v484 Extend { value=v482, kind=I32 } -> x0 + terminator Jmp(b19) (exit_acc=v484) + block 19 start_pc=0 + v485 Phi { incoming=[b40:v466, b18:v482], kind=I64 } -> [spill 117] + v486 LoadLocal { off=-8, kind=I32 } -> x0 + v487 ImmData(80) -> x0 + v488 Imm(24) -> x1 + v489 BinopI { op=add, lhs=v487, rhs_imm=24 } -> x1 + v490 Load { addr=v487, disp=24, kind=I32 } -> x0 + v491 BinopI { op=mul, lhs=v490, rhs_imm=3 } -> x0 + v492 BinopI { op=shl, lhs=v491, rhs_imm=32 } -> x1 + v493 Extend { value=v491, kind=I32 } -> x1 + v494 BinopI { op=add, lhs=v491, rhs_imm=6 } -> x0 + v495 BinopI { op=shl, lhs=v494, rhs_imm=32 } -> x1 + v496 Extend { value=v494, kind=I32 } -> x0 + v497 Binop { op=ne, lhs=v84, rhs=v496 } -> x0 + terminator Bz { cond=v497, target=b39, fall=b20 } (exit_acc=v497) + block 20 start_pc=0 + v498 Extend { value=v485, kind=I32 } -> x0 + v499 Imm(64) -> x0 + v500 Imm(274877906944) -> x0 + v501 BinopI { op=or, lhs=v485, rhs_imm=64 } -> [spill 117] + v502 Imm(0) -> x0 + v503 Extend { value=v501, kind=I32 } -> x0 + terminator Jmp(b21) (exit_acc=v503) + block 21 start_pc=0 + v504 Phi { incoming=[b39:v485, b20:v501], kind=I64 } -> [spill 117] + v505 LoadLocal { off=-9, kind=I32 } -> x0 + v506 ImmData(80) -> x0 + v507 Imm(28) -> x1 + v508 BinopI { op=add, lhs=v506, rhs_imm=28 } -> x1 + v509 Load { addr=v506, disp=28, kind=I32 } -> x0 + v510 BinopI { op=mul, lhs=v509, rhs_imm=3 } -> x0 + v511 BinopI { op=shl, lhs=v510, rhs_imm=32 } -> x1 + v512 Extend { value=v510, kind=I32 } -> x1 + v513 BinopI { op=add, lhs=v510, rhs_imm=7 } -> x0 + v514 BinopI { op=shl, lhs=v513, rhs_imm=32 } -> x1 + v515 Extend { value=v513, kind=I32 } -> x0 + v516 Binop { op=ne, lhs=v94, rhs=v515 } -> x0 + terminator Bz { cond=v516, target=b38, fall=b22 } (exit_acc=v516) + block 22 start_pc=0 + v517 Extend { value=v504, kind=I32 } -> x0 + v518 Imm(128) -> x0 + v519 Imm(549755813888) -> x0 + v520 BinopI { op=or, lhs=v504, rhs_imm=128 } -> [spill 117] + v521 Imm(0) -> x0 + v522 Extend { value=v520, kind=I32 } -> x0 + terminator Jmp(b23) (exit_acc=v522) + block 23 start_pc=0 + v523 Phi { incoming=[b38:v504, b22:v520], kind=I64 } -> [spill 117] + v524 LoadLocal { off=-10, kind=I32 } -> x0 + v525 ImmData(80) -> x0 + v526 Imm(32) -> x1 + v527 BinopI { op=add, lhs=v525, rhs_imm=32 } -> x1 + v528 Load { addr=v525, disp=32, kind=I32 } -> x0 + v529 BinopI { op=mul, lhs=v528, rhs_imm=3 } -> x0 + v530 BinopI { op=shl, lhs=v529, rhs_imm=32 } -> x1 + v531 Extend { value=v529, kind=I32 } -> x1 + v532 BinopI { op=add, lhs=v529, rhs_imm=8 } -> x0 + v533 BinopI { op=shl, lhs=v532, rhs_imm=32 } -> x1 + v534 Extend { value=v532, kind=I32 } -> x0 + v535 Binop { op=ne, lhs=v104, rhs=v534 } -> x0 + terminator Bz { cond=v535, target=b37, fall=b24 } (exit_acc=v535) + block 24 start_pc=0 + v536 Extend { value=v523, kind=I32 } -> x0 + v537 Imm(256) -> x0 + v538 Imm(1099511627776) -> x0 + v539 BinopI { op=or, lhs=v523, rhs_imm=256 } -> [spill 117] + v540 Imm(0) -> x0 + v541 Extend { value=v539, kind=I32 } -> x0 + terminator Jmp(b25) (exit_acc=v541) + block 25 start_pc=0 + v542 Phi { incoming=[b37:v523, b24:v539], kind=I64 } -> [spill 117] + v543 LoadLocal { off=-11, kind=I32 } -> x0 + v544 ImmData(80) -> x0 + v545 Imm(36) -> x1 + v546 BinopI { op=add, lhs=v544, rhs_imm=36 } -> x1 + v547 Load { addr=v544, disp=36, kind=I32 } -> x0 + v548 BinopI { op=mul, lhs=v547, rhs_imm=3 } -> x0 + v549 BinopI { op=shl, lhs=v548, rhs_imm=32 } -> x1 + v550 Extend { value=v548, kind=I32 } -> x1 + v551 BinopI { op=add, lhs=v548, rhs_imm=9 } -> x0 + v552 BinopI { op=shl, lhs=v551, rhs_imm=32 } -> x1 + v553 Extend { value=v551, kind=I32 } -> x0 + v554 Binop { op=ne, lhs=v114, rhs=v553 } -> x0 + terminator Bz { cond=v554, target=b36, fall=b26 } (exit_acc=v554) + block 26 start_pc=0 + v555 Extend { value=v542, kind=I32 } -> x0 + v556 Imm(512) -> x0 + v557 Imm(2199023255552) -> x0 + v558 BinopI { op=or, lhs=v542, rhs_imm=512 } -> [spill 117] + v559 Imm(0) -> x0 + v560 Extend { value=v558, kind=I32 } -> x0 + terminator Jmp(b27) (exit_acc=v560) + block 27 start_pc=0 + v561 Phi { incoming=[b36:v542, b26:v558], kind=I64 } -> [spill 117] + v562 LoadLocal { off=-12, kind=I32 } -> x0 + v563 ImmData(80) -> x0 + v564 Imm(40) -> x1 + v565 BinopI { op=add, lhs=v563, rhs_imm=40 } -> x1 + v566 Load { addr=v563, disp=40, kind=I32 } -> x0 + v567 BinopI { op=mul, lhs=v566, rhs_imm=3 } -> x0 + v568 BinopI { op=shl, lhs=v567, rhs_imm=32 } -> x1 + v569 Extend { value=v567, kind=I32 } -> x1 + v570 BinopI { op=add, lhs=v567, rhs_imm=10 } -> x0 + v571 BinopI { op=shl, lhs=v570, rhs_imm=32 } -> x1 + v572 Extend { value=v570, kind=I32 } -> x0 + v573 Binop { op=ne, lhs=v124, rhs=v572 } -> x0 + terminator Bz { cond=v573, target=b35, fall=b28 } (exit_acc=v573) + block 28 start_pc=0 + v574 Extend { value=v561, kind=I32 } -> x0 + v575 Imm(1024) -> x0 + v576 Imm(4398046511104) -> x0 + v577 BinopI { op=or, lhs=v561, rhs_imm=1024 } -> [spill 117] + v578 Imm(0) -> x0 + v579 Extend { value=v577, kind=I32 } -> x0 + terminator Jmp(b29) (exit_acc=v579) + block 29 start_pc=0 + v580 Phi { incoming=[b35:v561, b28:v577], kind=I64 } -> [spill 117] + v581 LoadLocal { off=-13, kind=I32 } -> x0 + v582 ImmData(80) -> x0 + v583 Imm(44) -> x1 + v584 BinopI { op=add, lhs=v582, rhs_imm=44 } -> x1 + v585 Load { addr=v582, disp=44, kind=I32 } -> x0 + v586 BinopI { op=mul, lhs=v585, rhs_imm=3 } -> x0 + v587 BinopI { op=shl, lhs=v586, rhs_imm=32 } -> x1 + v588 Extend { value=v586, kind=I32 } -> x1 + v589 BinopI { op=add, lhs=v586, rhs_imm=11 } -> x0 + v590 BinopI { op=shl, lhs=v589, rhs_imm=32 } -> x1 + v591 Extend { value=v589, kind=I32 } -> x0 + v592 Binop { op=ne, lhs=v134, rhs=v591 } -> x0 + terminator Bz { cond=v592, target=b34, fall=b30 } (exit_acc=v592) + block 30 start_pc=0 + v593 Extend { value=v580, kind=I32 } -> x0 + v594 Imm(2048) -> x0 + v595 Imm(8796093022208) -> x0 + v596 BinopI { op=or, lhs=v580, rhs_imm=2048 } -> [spill 117] + v597 Imm(0) -> x0 + v598 Extend { value=v596, kind=I32 } -> x0 + terminator Jmp(b31) (exit_acc=v598) + block 31 start_pc=0 + v599 Phi { incoming=[b34:v580, b30:v596], kind=I64 } -> [spill 117] + v600 Extend { value=v599, kind=I32 } -> x0 + terminator Bz { cond=v600, target=b33, fall=b32 } (exit_acc=v600) + block 32 start_pc=0 + v601 ImmData(46) -> x7 + v602 Extend { value=v599, kind=I32 } -> x6 + v603 CallExt { binding_idx=0, args=[v601, v602], fp_arg_mask=0x0 } -> x0 + v604 Imm(1) -> x0 + terminator Return(v604) (exit_acc=v604) + block 33 start_pc=0 + v605 ImmData(65) -> x7 + v606 CallExt { binding_idx=0, args=[v605], fp_arg_mask=0x0 } -> x0 + v607 Imm(0) -> x0 + terminator Return(v607) (exit_acc=v607) + block 34 start_pc=0 + terminator Jmp(b31) + block 35 start_pc=0 + terminator Jmp(b29) + block 36 start_pc=0 + terminator Jmp(b27) + block 37 start_pc=0 + terminator Jmp(b25) + block 38 start_pc=0 + terminator Jmp(b23) + block 39 start_pc=0 + terminator Jmp(b21) + block 40 start_pc=0 + terminator Jmp(b19) + block 41 start_pc=0 + terminator Jmp(b17) + block 42 start_pc=0 + terminator Jmp(b15) + block 43 start_pc=0 + terminator Jmp(b13) + block 44 start_pc=0 + terminator Jmp(b11) + block 45 start_pc=0 + terminator Jmp(b9) + block 46 start_pc=0 + v160 ImmData(80) -> x0 + v161 Imm(64) -> x1 + v162 BinopI { op=add, lhs=v160, rhs_imm=64 } -> x1 + v163 Load { addr=v160, disp=64, kind=I32 } -> x1 + v164 BinopI { op=mul, lhs=v163, rhs_imm=5 } -> x1 + v165 BinopI { op=shl, lhs=v164, rhs_imm=32 } -> x2 + v166 Extend { value=v164, kind=I32 } -> x2 + v167 BinopI { op=add, lhs=v164, rhs_imm=1 } -> x7 + v168 BinopI { op=shl, lhs=v167, rhs_imm=32 } -> x1 + v169 Extend { value=v167, kind=I32 } -> x1 + v170 Imm(0) -> x1 + v171 Imm(68) -> x1 + v172 BinopI { op=add, lhs=v160, rhs_imm=68 } -> x1 + v173 Load { addr=v160, disp=68, kind=I32 } -> x1 + v174 BinopI { op=mul, lhs=v173, rhs_imm=5 } -> x1 + v175 BinopI { op=shl, lhs=v174, rhs_imm=32 } -> x2 + v176 Extend { value=v174, kind=I32 } -> x2 + v177 BinopI { op=add, lhs=v174, rhs_imm=2 } -> x6 + v178 BinopI { op=shl, lhs=v177, rhs_imm=32 } -> x1 + v179 Extend { value=v177, kind=I32 } -> x1 + v180 Imm(0) -> x1 + v181 Imm(72) -> x1 + v182 BinopI { op=add, lhs=v160, rhs_imm=72 } -> x1 + v183 Load { addr=v160, disp=72, kind=I32 } -> x1 + v184 BinopI { op=mul, lhs=v183, rhs_imm=5 } -> x1 + v185 BinopI { op=shl, lhs=v184, rhs_imm=32 } -> x2 + v186 Extend { value=v184, kind=I32 } -> x2 + v187 BinopI { op=add, lhs=v184, rhs_imm=3 } -> x2 + v188 BinopI { op=shl, lhs=v187, rhs_imm=32 } -> x1 + v189 Extend { value=v187, kind=I32 } -> x1 + v190 Imm(0) -> x1 + v191 Imm(76) -> x1 + v192 BinopI { op=add, lhs=v160, rhs_imm=76 } -> x1 + v193 Load { addr=v160, disp=76, kind=I32 } -> x1 + v194 BinopI { op=mul, lhs=v193, rhs_imm=5 } -> x1 + v195 BinopI { op=shl, lhs=v194, rhs_imm=32 } -> x8 + v196 Extend { value=v194, kind=I32 } -> x8 + v197 BinopI { op=add, lhs=v194, rhs_imm=4 } -> x1 + v198 BinopI { op=shl, lhs=v197, rhs_imm=32 } -> x8 + v199 Extend { value=v197, kind=I32 } -> x8 + v200 Imm(0) -> x8 + v201 Imm(80) -> x8 + v202 BinopI { op=add, lhs=v160, rhs_imm=80 } -> x8 + v203 Load { addr=v160, disp=80, kind=I32 } -> x8 + v204 BinopI { op=mul, lhs=v203, rhs_imm=5 } -> x8 + v205 BinopI { op=shl, lhs=v204, rhs_imm=32 } -> x9 + v206 Extend { value=v204, kind=I32 } -> x9 + v207 BinopI { op=add, lhs=v204, rhs_imm=5 } -> x8 + v208 BinopI { op=shl, lhs=v207, rhs_imm=32 } -> x9 + v209 Extend { value=v207, kind=I32 } -> x9 + v210 Imm(0) -> x9 + v211 Imm(84) -> x9 + v212 BinopI { op=add, lhs=v160, rhs_imm=84 } -> x9 + v213 Load { addr=v160, disp=84, kind=I32 } -> x9 + v214 BinopI { op=mul, lhs=v213, rhs_imm=5 } -> x9 + v215 BinopI { op=shl, lhs=v214, rhs_imm=32 } -> x3 + v216 Extend { value=v214, kind=I32 } -> x3 + v217 BinopI { op=add, lhs=v214, rhs_imm=6 } -> x9 + v218 BinopI { op=shl, lhs=v217, rhs_imm=32 } -> x3 + v219 Extend { value=v217, kind=I32 } -> x3 + v220 Imm(0) -> x3 + v221 Imm(88) -> x3 + v222 BinopI { op=add, lhs=v160, rhs_imm=88 } -> x3 + v223 Load { addr=v160, disp=88, kind=I32 } -> x3 + v224 BinopI { op=mul, lhs=v223, rhs_imm=5 } -> x3 + v225 BinopI { op=shl, lhs=v224, rhs_imm=32 } -> x12 + v226 Extend { value=v224, kind=I32 } -> x12 + v227 BinopI { op=add, lhs=v224, rhs_imm=7 } -> x3 + v228 BinopI { op=shl, lhs=v227, rhs_imm=32 } -> x12 + v229 Extend { value=v227, kind=I32 } -> x3 + v230 Imm(0) -> x12 + v231 Imm(92) -> x12 + v232 BinopI { op=add, lhs=v160, rhs_imm=92 } -> x12 + v233 Load { addr=v160, disp=92, kind=I32 } -> x12 + v234 BinopI { op=mul, lhs=v233, rhs_imm=5 } -> x12 + v235 BinopI { op=shl, lhs=v234, rhs_imm=32 } -> x13 + v236 Extend { value=v234, kind=I32 } -> x13 + v237 BinopI { op=add, lhs=v234, rhs_imm=8 } -> x12 + v238 BinopI { op=shl, lhs=v237, rhs_imm=32 } -> x13 + v239 Extend { value=v237, kind=I32 } -> x12 + v240 Imm(0) -> x13 + v241 Imm(96) -> x13 + v242 BinopI { op=add, lhs=v160, rhs_imm=96 } -> x13 + v243 Load { addr=v160, disp=96, kind=I32 } -> x13 + v244 BinopI { op=mul, lhs=v243, rhs_imm=5 } -> x13 + v245 BinopI { op=shl, lhs=v244, rhs_imm=32 } -> x14 + v246 Extend { value=v244, kind=I32 } -> x14 + v247 BinopI { op=add, lhs=v244, rhs_imm=9 } -> x13 + v248 BinopI { op=shl, lhs=v247, rhs_imm=32 } -> x14 + v249 Extend { value=v247, kind=I32 } -> x13 + v250 Imm(0) -> x14 + v251 Imm(100) -> x14 + v252 BinopI { op=add, lhs=v160, rhs_imm=100 } -> x14 + v253 Load { addr=v160, disp=100, kind=I32 } -> x14 + v254 BinopI { op=mul, lhs=v253, rhs_imm=5 } -> x14 + v255 BinopI { op=shl, lhs=v254, rhs_imm=32 } -> x15 + v256 Extend { value=v254, kind=I32 } -> x15 + v257 BinopI { op=add, lhs=v254, rhs_imm=10 } -> x14 + v258 BinopI { op=shl, lhs=v257, rhs_imm=32 } -> x15 + v259 Extend { value=v257, kind=I32 } -> x14 + v260 Imm(0) -> x15 + v261 Imm(104) -> x15 + v262 BinopI { op=add, lhs=v160, rhs_imm=104 } -> x15 + v263 Load { addr=v160, disp=104, kind=I32 } -> x15 + v264 BinopI { op=mul, lhs=v263, rhs_imm=5 } -> x15 + v265 BinopI { op=shl, lhs=v264, rhs_imm=32 } -> [spill 7] + v266 Extend { value=v264, kind=I32 } -> [spill 8] + v267 BinopI { op=add, lhs=v264, rhs_imm=11 } -> x15 + v268 BinopI { op=shl, lhs=v267, rhs_imm=32 } -> [spill 9] + v269 Extend { value=v267, kind=I32 } -> x15 + v270 Imm(0) -> [spill 10] + v271 Imm(108) -> [spill 11] + v272 BinopI { op=add, lhs=v160, rhs_imm=108 } -> [spill 12] + v273 Load { addr=v160, disp=108, kind=I32 } -> [spill 13] + v274 BinopI { op=mul, lhs=v273, rhs_imm=5 } -> [spill 14] + v275 BinopI { op=shl, lhs=v274, rhs_imm=32 } -> [spill 15] + v276 Extend { value=v274, kind=I32 } -> [spill 16] + v277 BinopI { op=add, lhs=v274, rhs_imm=12 } -> [spill 17] + v278 BinopI { op=shl, lhs=v277, rhs_imm=32 } -> [spill 18] + v279 Extend { value=v277, kind=I32 } -> [spill 19] + v280 Imm(0) -> [spill 20] + v281 Imm(112) -> [spill 21] + v282 BinopI { op=add, lhs=v160, rhs_imm=112 } -> [spill 22] + v283 Load { addr=v160, disp=112, kind=I32 } -> [spill 23] + v284 BinopI { op=mul, lhs=v283, rhs_imm=5 } -> [spill 24] + v285 BinopI { op=shl, lhs=v284, rhs_imm=32 } -> [spill 25] + v286 Extend { value=v284, kind=I32 } -> [spill 26] + v287 BinopI { op=add, lhs=v284, rhs_imm=13 } -> [spill 27] + v288 BinopI { op=shl, lhs=v287, rhs_imm=32 } -> [spill 28] + v289 Extend { value=v287, kind=I32 } -> [spill 29] + v290 Imm(0) -> [spill 30] + v291 Imm(116) -> [spill 31] + v292 BinopI { op=add, lhs=v160, rhs_imm=116 } -> [spill 32] + v293 Load { addr=v160, disp=116, kind=I32 } -> [spill 33] + v294 BinopI { op=mul, lhs=v293, rhs_imm=5 } -> [spill 34] + v295 BinopI { op=shl, lhs=v294, rhs_imm=32 } -> [spill 35] + v296 Extend { value=v294, kind=I32 } -> [spill 36] + v297 BinopI { op=add, lhs=v294, rhs_imm=14 } -> [spill 37] + v298 BinopI { op=shl, lhs=v297, rhs_imm=32 } -> [spill 38] + v299 Extend { value=v297, kind=I32 } -> [spill 39] + v300 Imm(0) -> [spill 40] + v301 Imm(120) -> [spill 41] + v302 BinopI { op=add, lhs=v160, rhs_imm=120 } -> [spill 42] + v303 Load { addr=v160, disp=120, kind=I32 } -> [spill 43] + v304 BinopI { op=mul, lhs=v303, rhs_imm=5 } -> [spill 44] + v305 BinopI { op=shl, lhs=v304, rhs_imm=32 } -> [spill 45] + v306 Extend { value=v304, kind=I32 } -> [spill 46] + v307 BinopI { op=add, lhs=v304, rhs_imm=15 } -> [spill 47] + v308 BinopI { op=shl, lhs=v307, rhs_imm=32 } -> [spill 48] + v309 Extend { value=v307, kind=I32 } -> [spill 49] + v310 Imm(0) -> [spill 50] + v311 Imm(124) -> [spill 51] + v312 BinopI { op=add, lhs=v160, rhs_imm=124 } -> [spill 52] + v313 Load { addr=v160, disp=124, kind=I32 } -> [spill 53] + v314 BinopI { op=mul, lhs=v313, rhs_imm=5 } -> [spill 54] + v315 BinopI { op=shl, lhs=v314, rhs_imm=32 } -> [spill 55] + v316 Extend { value=v314, kind=I32 } -> [spill 56] + v317 BinopI { op=add, lhs=v314, rhs_imm=16 } -> [spill 57] + v318 BinopI { op=shl, lhs=v317, rhs_imm=32 } -> [spill 58] + v319 Extend { value=v317, kind=I32 } -> [spill 59] + v320 Imm(0) -> [spill 60] + v321 Imm(128) -> [spill 61] + v322 BinopI { op=add, lhs=v160, rhs_imm=128 } -> [spill 62] + v323 Load { addr=v160, disp=128, kind=I32 } -> [spill 63] + v324 BinopI { op=mul, lhs=v323, rhs_imm=5 } -> [spill 64] + v325 BinopI { op=shl, lhs=v324, rhs_imm=32 } -> [spill 65] + v326 Extend { value=v324, kind=I32 } -> [spill 66] + v327 BinopI { op=add, lhs=v324, rhs_imm=17 } -> [spill 67] + v328 BinopI { op=shl, lhs=v327, rhs_imm=32 } -> [spill 68] + v329 Extend { value=v327, kind=I32 } -> [spill 69] + v330 Imm(0) -> [spill 70] + v331 Imm(132) -> [spill 71] + v332 BinopI { op=add, lhs=v160, rhs_imm=132 } -> [spill 72] + v333 Load { addr=v160, disp=132, kind=I32 } -> [spill 73] + v334 BinopI { op=mul, lhs=v333, rhs_imm=5 } -> [spill 74] + v335 BinopI { op=shl, lhs=v334, rhs_imm=32 } -> [spill 75] + v336 Extend { value=v334, kind=I32 } -> [spill 76] + v337 BinopI { op=add, lhs=v334, rhs_imm=18 } -> [spill 77] + v338 BinopI { op=shl, lhs=v337, rhs_imm=32 } -> [spill 78] + v339 Extend { value=v337, kind=I32 } -> [spill 79] + v340 Imm(0) -> [spill 80] + v341 Imm(136) -> [spill 81] + v342 BinopI { op=add, lhs=v160, rhs_imm=136 } -> [spill 82] + v343 Load { addr=v160, disp=136, kind=I32 } -> [spill 83] + v344 BinopI { op=mul, lhs=v343, rhs_imm=5 } -> [spill 84] + v345 BinopI { op=shl, lhs=v344, rhs_imm=32 } -> [spill 85] + v346 Extend { value=v344, kind=I32 } -> [spill 86] + v347 BinopI { op=add, lhs=v344, rhs_imm=19 } -> [spill 87] + v348 BinopI { op=shl, lhs=v347, rhs_imm=32 } -> [spill 88] + v349 Extend { value=v347, kind=I32 } -> [spill 89] + v350 Imm(0) -> [spill 90] + v351 Imm(140) -> [spill 91] + v352 BinopI { op=add, lhs=v160, rhs_imm=140 } -> [spill 92] + v353 Load { addr=v160, disp=140, kind=I32 } -> x0 + v354 BinopI { op=mul, lhs=v353, rhs_imm=5 } -> x0 + v355 BinopI { op=shl, lhs=v354, rhs_imm=32 } -> [spill 93] + v356 Extend { value=v354, kind=I32 } -> [spill 94] + v357 BinopI { op=add, lhs=v354, rhs_imm=20 } -> x0 + v358 BinopI { op=shl, lhs=v357, rhs_imm=32 } -> [spill 95] + v359 Extend { value=v357, kind=I32 } -> x0 + v360 Imm(0) -> [spill 96] + v361 LoadLocal { off=-17, kind=I32 } -> [spill 97] + v362 LoadLocal { off=-18, kind=I32 } -> [spill 98] + v363 LoadLocal { off=-19, kind=I32 } -> [spill 99] + v364 LoadLocal { off=-20, kind=I32 } -> [spill 100] + v365 LoadLocal { off=-21, kind=I32 } -> [spill 101] + v366 LoadLocal { off=-22, kind=I32 } -> [spill 102] + v367 LoadLocal { off=-23, kind=I32 } -> [spill 103] + v368 LoadLocal { off=-24, kind=I32 } -> [spill 104] + v369 LoadLocal { off=-25, kind=I32 } -> [spill 105] + v370 LoadLocal { off=-26, kind=I32 } -> [spill 106] + v371 LoadLocal { off=-27, kind=I32 } -> [spill 107] + v372 LoadLocal { off=-28, kind=I32 } -> [spill 108] + v373 LoadLocal { off=-29, kind=I32 } -> [spill 109] + v374 LoadLocal { off=-30, kind=I32 } -> [spill 110] + v375 LoadLocal { off=-31, kind=I32 } -> [spill 111] + v376 LoadLocal { off=-32, kind=I32 } -> [spill 112] + v377 LoadLocal { off=-33, kind=I32 } -> [spill 113] + v378 LoadLocal { off=-34, kind=I32 } -> [spill 114] + v379 LoadLocal { off=-35, kind=I32 } -> [spill 115] + v380 LoadLocal { off=-36, kind=I32 } -> [spill 116] + v381 Call { target_pc=6, args=[v167, v177, v187, v197, v207, v217, v229, v239, v249, v259, v269, v279, v289, v299, v309, v319, v329, v339, v349, v359], fixed_args=20, fp_return=false, fp_arg_mask=0x0 } -> x7 + v382 CallExt { binding_idx=171, args=[v381], fp_arg_mask=0x0 } -> x0 + v383 Imm(3) -> x0 + terminator Return(v383) (exit_acc=v383) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/vla_basic_sum.ssa b/tests/snapshots/ssa/vla_basic_sum.ssa index 7834cfc38..c0af5648a 100644 --- a/tests/snapshots/ssa/vla_basic_sum.ssa +++ b/tests/snapshots/ssa/vla_basic_sum.ssa @@ -13,18 +13,8 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v7 StoreLocal { off=-1, value=v6, kind=I64 } -> - v8 Imm(0) -> x0 v9 StoreLocal { off=-3, value=v8, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v9) + terminator Jmp(b3) (exit_acc=v9) block 1 start_pc=0 - v10 LoadLocal { off=-3, kind=I32 } -> x0 - v11 LoadLocal { off=2, kind=I32 } -> x1 - v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) - block 2 start_pc=0 - v13 LoadLocal { off=-3, kind=I32 } -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x0 - v15 StoreLocal { off=-3, value=v14, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v15) - block 3 start_pc=0 v16 LoadLocal { off=-1, kind=I64 } -> x0 v17 LoadLocal { off=-3, kind=I32 } -> x1 v18 BinopI { op=shl, lhs=v17, rhs_imm=2 } -> x2 @@ -34,22 +24,22 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v22 Extend { value=v20, kind=I32 } -> x6 v23 StoreIndexed { base=v16, index=v17, scale=4, value=v20, kind=I32 } -> - terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v13 LoadLocal { off=-3, kind=I32 } -> x0 + v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x0 + v15 StoreLocal { off=-3, value=v14, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v15) + block 3 start_pc=0 + v10 LoadLocal { off=-3, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x1 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 + terminator Bnz { cond=v12, target=b1, fall=b4 } (exit_acc=v12) block 4 start_pc=0 v24 Imm(0) -> x0 v25 StoreLocal { off=-4, value=v24, kind=I32 } -> - v26 StoreLocal { off=-5, value=v24, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v26) + terminator Jmp(b7) (exit_acc=v26) block 5 start_pc=0 - v27 LoadLocal { off=-5, kind=I32 } -> x0 - v28 LoadLocal { off=2, kind=I32 } -> x1 - v29 Binop { op=lt, lhs=v27, rhs=v28 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) - block 6 start_pc=0 - v30 LoadLocal { off=-5, kind=I32 } -> x0 - v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x0 - v32 StoreLocal { off=-5, value=v31, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v32) - block 7 start_pc=0 v33 LoadLocal { off=-4, kind=I32 } -> x0 v34 LoadLocal { off=-1, kind=I64 } -> x1 v35 LoadLocal { off=-5, kind=I32 } -> x2 @@ -60,6 +50,16 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v40 StoreLocal { off=-4, value=v39, kind=I32 } -> - v41 LoadLocal { off=-4, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v41) + block 6 start_pc=0 + v30 LoadLocal { off=-5, kind=I32 } -> x0 + v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x0 + v32 StoreLocal { off=-5, value=v31, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v32) + block 7 start_pc=0 + v27 LoadLocal { off=-5, kind=I32 } -> x0 + v28 LoadLocal { off=2, kind=I32 } -> x1 + v29 Binop { op=lt, lhs=v27, rhs=v28 } -> x0 + terminator Bnz { cond=v29, target=b5, fall=b8 } (exit_acc=v29) block 8 start_pc=0 v42 LoadLocal { off=-4, kind=I32 } -> x0 terminator Return(v42) (exit_acc=v42) diff --git a/tests/snapshots/ssa/vla_param_decay.ssa b/tests/snapshots/ssa/vla_param_decay.ssa index 5575add63..03aed98dd 100644 --- a/tests/snapshots/ssa/vla_param_decay.ssa +++ b/tests/snapshots/ssa/vla_param_decay.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=dot fn ent_pc=0 n_params=3 variadic=false locals=2 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 @@ -13,36 +13,36 @@ fn ent_pc=0 n_params=3 variadic=false locals=2 v7 Imm(0) -> x1 v8 Imm(0) -> x0 v9 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + terminator Jmp(b3) (exit_acc=v7) block 1 start_pc=0 - v10 Phi { incoming=[b0:v7, b2:v16], kind=I64 } -> x1 - v11 Phi { incoming=[b0:v7, b2:v30], kind=I64 } -> x0 - v12 Extend { value=v10, kind=I32 } -> x8 - v13 LoadLocal { off=2, kind=I32 } -> x9 - v14 Binop { op=lt, lhs=v12, rhs=v1 } -> x8 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v18 Extend { value=v11, kind=I32 } -> x9 + v19 LoadLocal { off=3, kind=I64 } -> x9 + v20 Extend { value=v10, kind=I32 } -> x9 + v21 BinopI { op=shl, lhs=v12, rhs_imm=2 } -> x9 + v22 Binop { op=add, lhs=v3, rhs=v21 } -> x3 + v23 Load { addr=v22, disp=0, kind=I32 } -> x3 + v24 LoadLocal { off=4, kind=I64 } -> x12 + v25 Binop { op=add, lhs=v5, rhs=v21 } -> x9 + v26 Load { addr=v25, disp=0, kind=I32 } -> x9 + v27 Binop { op=mul, lhs=v23, rhs=v26 } -> x9 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x3 + v29 Extend { value=v27, kind=I32 } -> x3 + v30 Binop { op=add, lhs=v11, rhs=v27 } -> x0 + v31 Imm(0) -> x9 + v32 Extend { value=v30, kind=I32 } -> x9 + terminator Jmp(b2) (exit_acc=v32) block 2 start_pc=0 v15 Extend { value=v10, kind=I32 } -> x1 - v16 BinopI { op=add, lhs=v15, rhs_imm=1 } -> x1 + v16 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x1 v17 Imm(0) -> x8 - terminator Jmp(b1) (exit_acc=v16) + terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - v18 Extend { value=v11, kind=I32 } -> x8 - v19 LoadLocal { off=3, kind=I64 } -> x8 - v20 Extend { value=v10, kind=I32 } -> x8 - v21 BinopI { op=shl, lhs=v20, rhs_imm=2 } -> x8 - v22 Binop { op=add, lhs=v3, rhs=v21 } -> x9 - v23 Load { addr=v22, disp=0, kind=I32 } -> x9 - v24 LoadLocal { off=4, kind=I64 } -> x3 - v25 Binop { op=add, lhs=v5, rhs=v21 } -> x8 - v26 Load { addr=v25, disp=0, kind=I32 } -> x8 - v27 Binop { op=mul, lhs=v23, rhs=v26 } -> x8 - v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x9 - v29 Extend { value=v27, kind=I32 } -> x9 - v30 Binop { op=add, lhs=v11, rhs=v27 } -> x0 - v31 Imm(0) -> x8 - v32 Extend { value=v30, kind=I32 } -> x8 - terminator Jmp(b2) (exit_acc=v32) + v10 Phi { incoming=[b0:v7, b2:v16], kind=I64 } -> x1 + v11 Phi { incoming=[b0:v7, b2:v30], kind=I64 } -> x0 + v12 Extend { value=v10, kind=I32 } -> x8 + v13 LoadLocal { off=2, kind=I32 } -> x9 + v14 Binop { op=lt, lhs=v12, rhs=v1 } -> x9 + terminator Bnz { cond=v14, target=b1, fall=b4 } (exit_acc=v14) block 4 start_pc=0 v33 Extend { value=v11, kind=I32 } -> x0 terminator Return(v33) (exit_acc=v33) @@ -63,19 +63,19 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v9 LocalAddr(-4) -> x2 v10 Call { target_pc=0, args=[v7, v8, v9], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x0 v11 BinopI { op=eq, lhs=v10, rhs_imm=70 } -> x0 - terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) + terminator Bz { cond=v11, target=b3, fall=b1 } (exit_acc=v11) block 1 start_pc=0 v12 Imm(0) -> x1 v13 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v12) + terminator Jmp(b2) (exit_acc=v12) block 2 start_pc=0 - v14 Imm(1) -> x1 - v15 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v14) - block 3 start_pc=0 - v16 Phi { incoming=[b1:v12, b2:v14], kind=I64 } -> x1 + v16 Phi { incoming=[b1:v12, b3:v14], kind=I64 } -> x1 v17 LoadLocal { off=-8, kind=I64 } -> x0 terminator Return(v16) (exit_acc=v16) + block 3 start_pc=0 + v14 Imm(1) -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v14) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/vla_scope_reclaim_loop.ssa b/tests/snapshots/ssa/vla_scope_reclaim_loop.ssa index f240d8c33..7f9436e52 100644 --- a/tests/snapshots/ssa/vla_scope_reclaim_loop.ssa +++ b/tests/snapshots/ssa/vla_scope_reclaim_loop.ssa @@ -7,17 +7,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=1035 v1 Imm(0) -> x0 v2 StoreLocal { off=-1, value=v1, kind=I64 } -> - v3 StoreLocal { off=-2, value=v1, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v3) + terminator Jmp(b7) (exit_acc=v3) block 1 start_pc=0 - v4 LoadLocal { off=-2, kind=I32 } -> x0 - v5 BinopI { op=lt, lhs=v4, rhs_imm=100000 } -> x0 - terminator Bz { cond=v5, target=b4, fall=b3 } (exit_acc=v5) - block 2 start_pc=0 - v6 LoadLocal { off=-2, kind=I32 } -> x0 - v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x0 - v8 StoreLocal { off=-2, value=v7, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v8) - block 3 start_pc=0 v9 Intrinsic { kind=46, args=[] } -> x0 v10 StoreLocal { off=-7, value=v9, kind=I64 } -> - v11 Imm(64) -> x0 @@ -29,30 +20,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=1035 v17 StoreLocal { off=-4, value=v16, kind=I64 } -> - v18 Imm(0) -> x0 v19 StoreLocal { off=-6, value=v18, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v19) - block 4 start_pc=0 - v42 Imm(0) -> x0 - v43 StoreLocal { off=-8, value=v42, kind=I64 } -> - - v44 StoreLocal { off=-9, value=v42, kind=I32 } -> - - terminator Jmp(b9) (exit_acc=v44) - block 5 start_pc=0 - v20 LoadLocal { off=-6, kind=I32 } -> x0 - v21 LoadLocal { off=-3, kind=I32 } -> x1 - v22 Binop { op=lt, lhs=v20, rhs=v21 } -> x0 - terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) - block 6 start_pc=0 - v23 LoadLocal { off=-6, kind=I32 } -> x0 - v24 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x0 - v25 StoreLocal { off=-6, value=v24, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v25) - block 7 start_pc=0 + terminator Jmp(b4) (exit_acc=v19) + block 2 start_pc=0 v26 LoadLocal { off=-4, kind=I64 } -> x0 v27 LoadLocal { off=-6, kind=I32 } -> x1 v28 BinopI { op=shl, lhs=v27, rhs_imm=2 } -> x2 v29 Binop { op=add, lhs=v26, rhs=v28 } -> x2 v30 StoreIndexed { base=v26, index=v27, scale=4, value=v27, kind=I32 } -> - - terminator Jmp(b6) (exit_acc=v30) - block 8 start_pc=0 + terminator Jmp(b3) (exit_acc=v30) + block 3 start_pc=0 + v23 LoadLocal { off=-6, kind=I32 } -> x0 + v24 BinopI { op=add, lhs=v23, rhs_imm=1 } -> x0 + v25 StoreLocal { off=-6, value=v24, kind=I32 } -> - + terminator Jmp(b4) (exit_acc=v25) + block 4 start_pc=0 + v20 LoadLocal { off=-6, kind=I32 } -> x0 + v21 LoadLocal { off=-3, kind=I32 } -> x1 + v22 Binop { op=lt, lhs=v20, rhs=v21 } -> x0 + terminator Bnz { cond=v22, target=b2, fall=b5 } (exit_acc=v22) + block 5 start_pc=0 v31 LoadLocal { off=-1, kind=I64 } -> x0 v32 LoadLocal { off=-4, kind=I64 } -> x1 v33 LoadLocal { off=-2, kind=I32 } -> x2 @@ -64,39 +50,53 @@ fn ent_pc=0 n_params=0 variadic=false locals=1035 v39 StoreLocal { off=-1, value=v38, kind=I64 } -> - v40 LoadLocal { off=-7, kind=I64 } -> x0 v41 Intrinsic { kind=47, args=[v40] } -> x0 - terminator Jmp(b2) (exit_acc=v41) + terminator Jmp(b6) (exit_acc=v41) + block 6 start_pc=0 + v6 LoadLocal { off=-2, kind=I32 } -> x0 + v7 BinopI { op=add, lhs=v6, rhs_imm=1 } -> x0 + v8 StoreLocal { off=-2, value=v7, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v8) + block 7 start_pc=0 + v4 LoadLocal { off=-2, kind=I32 } -> x0 + v5 BinopI { op=lt, lhs=v4, rhs_imm=100000 } -> x0 + terminator Bnz { cond=v5, target=b1, fall=b8 } (exit_acc=v5) + block 8 start_pc=0 + v42 Imm(0) -> x0 + v43 StoreLocal { off=-8, value=v42, kind=I64 } -> - + v44 StoreLocal { off=-9, value=v42, kind=I32 } -> - + terminator Jmp(b11) (exit_acc=v44) block 9 start_pc=0 - v45 LoadLocal { off=-9, kind=I32 } -> x0 - v46 BinopI { op=lt, lhs=v45, rhs_imm=100000 } -> x0 - terminator Bz { cond=v46, target=b12, fall=b11 } (exit_acc=v46) - block 10 start_pc=0 - v47 LoadLocal { off=-9, kind=I32 } -> x0 - v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x0 - v49 StoreLocal { off=-9, value=v48, kind=I32 } -> - - terminator Jmp(b9) (exit_acc=v49) - block 11 start_pc=0 v50 LoadLocal { off=-8, kind=I64 } -> x0 v51 LoadLocal { off=-9, kind=I32 } -> x1 v52 BinopI { op=and, lhs=v51, rhs_imm=63 } -> x1 v53 Binop { op=add, lhs=v50, rhs=v52 } -> x0 v54 StoreLocal { off=-8, value=v53, kind=I64 } -> - terminator Jmp(b10) (exit_acc=v54) + block 10 start_pc=0 + v47 LoadLocal { off=-9, kind=I32 } -> x0 + v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x0 + v49 StoreLocal { off=-9, value=v48, kind=I32 } -> - + terminator Jmp(b11) (exit_acc=v49) + block 11 start_pc=0 + v45 LoadLocal { off=-9, kind=I32 } -> x0 + v46 BinopI { op=lt, lhs=v45, rhs_imm=100000 } -> x0 + terminator Bnz { cond=v46, target=b9, fall=b12 } (exit_acc=v46) block 12 start_pc=0 v55 LoadLocal { off=-1, kind=I64 } -> x0 v56 LoadLocal { off=-8, kind=I64 } -> x1 v57 Binop { op=eq, lhs=v55, rhs=v56 } -> x0 - terminator Bz { cond=v57, target=b14, fall=b13 } (exit_acc=v57) + terminator Bz { cond=v57, target=b15, fall=b13 } (exit_acc=v57) block 13 start_pc=0 v58 Imm(0) -> x0 v59 StoreLocal { off=-1035, value=v58, kind=I64 } -> - - terminator Jmp(b15) (exit_acc=v59) + terminator Jmp(b14) (exit_acc=v59) block 14 start_pc=0 - v60 Imm(1) -> x0 - v61 StoreLocal { off=-1035, value=v60, kind=I64 } -> - - terminator Jmp(b15) (exit_acc=v61) - block 15 start_pc=0 v62 LoadLocal { off=-1035, kind=I64 } -> x0 terminator Return(v62) (exit_acc=v62) + block 15 start_pc=0 + v60 Imm(1) -> x0 + v61 StoreLocal { off=-1035, value=v60, kind=I64 } -> - + terminator Jmp(b14) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/vla_size_from_arg.ssa b/tests/snapshots/ssa/vla_size_from_arg.ssa index c250f9f93..ebc921477 100644 --- a/tests/snapshots/ssa/vla_size_from_arg.ssa +++ b/tests/snapshots/ssa/vla_size_from_arg.ssa @@ -12,18 +12,8 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v6 StoreLocal { off=-1, value=v5, kind=I64 } -> - v7 Imm(0) -> x0 v8 StoreLocal { off=-3, value=v7, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v8) + terminator Jmp(b3) (exit_acc=v8) block 1 start_pc=0 - v9 LoadLocal { off=-3, kind=I32 } -> x0 - v10 LoadLocal { off=2, kind=I32 } -> x1 - v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x0 - terminator Bz { cond=v11, target=b4, fall=b3 } (exit_acc=v11) - block 2 start_pc=0 - v12 LoadLocal { off=-3, kind=I32 } -> x0 - v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x0 - v14 StoreLocal { off=-3, value=v13, kind=I32 } -> - - terminator Jmp(b1) (exit_acc=v14) - block 3 start_pc=0 v15 LoadLocal { off=-1, kind=I64 } -> x0 v16 LoadLocal { off=-3, kind=I32 } -> x1 v17 Binop { op=add, lhs=v15, rhs=v16 } -> x0 @@ -34,22 +24,22 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v22 Extend { value=v20, kind=I8 } -> x1 v23 Store { addr=v17, disp=0, value=v20, kind=I8 } -> - terminator Jmp(b2) (exit_acc=v23) + block 2 start_pc=0 + v12 LoadLocal { off=-3, kind=I32 } -> x0 + v13 BinopI { op=add, lhs=v12, rhs_imm=1 } -> x0 + v14 StoreLocal { off=-3, value=v13, kind=I32 } -> - + terminator Jmp(b3) (exit_acc=v14) + block 3 start_pc=0 + v9 LoadLocal { off=-3, kind=I32 } -> x0 + v10 LoadLocal { off=2, kind=I32 } -> x1 + v11 Binop { op=lt, lhs=v9, rhs=v10 } -> x0 + terminator Bnz { cond=v11, target=b1, fall=b4 } (exit_acc=v11) block 4 start_pc=0 v24 Imm(0) -> x0 v25 StoreLocal { off=-4, value=v24, kind=I32 } -> - v26 StoreLocal { off=-5, value=v24, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v26) + terminator Jmp(b7) (exit_acc=v26) block 5 start_pc=0 - v27 LoadLocal { off=-5, kind=I32 } -> x0 - v28 LoadLocal { off=2, kind=I32 } -> x1 - v29 Binop { op=lt, lhs=v27, rhs=v28 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) - block 6 start_pc=0 - v30 LoadLocal { off=-5, kind=I32 } -> x0 - v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x0 - v32 StoreLocal { off=-5, value=v31, kind=I32 } -> - - terminator Jmp(b5) (exit_acc=v32) - block 7 start_pc=0 v33 LoadLocal { off=-4, kind=I32 } -> x0 v34 LoadLocal { off=-1, kind=I64 } -> x1 v35 LoadLocal { off=-5, kind=I32 } -> x2 @@ -59,6 +49,16 @@ fn ent_pc=0 n_params=1 variadic=false locals=1030 v39 StoreLocal { off=-4, value=v38, kind=I32 } -> - v40 LoadLocal { off=-4, kind=I32 } -> x0 terminator Jmp(b6) (exit_acc=v40) + block 6 start_pc=0 + v30 LoadLocal { off=-5, kind=I32 } -> x0 + v31 BinopI { op=add, lhs=v30, rhs_imm=1 } -> x0 + v32 StoreLocal { off=-5, value=v31, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v32) + block 7 start_pc=0 + v27 LoadLocal { off=-5, kind=I32 } -> x0 + v28 LoadLocal { off=2, kind=I32 } -> x1 + v29 Binop { op=lt, lhs=v27, rhs=v28 } -> x0 + terminator Bnz { cond=v29, target=b5, fall=b8 } (exit_acc=v29) block 8 start_pc=0 v41 LoadLocal { off=-4, kind=I32 } -> x0 terminator Return(v41) (exit_acc=v41) diff --git a/tests/snapshots/ssa/void_function_produces_no_value.ssa b/tests/snapshots/ssa/void_function_produces_no_value.ssa index f01f7102c..caa87eda2 100644 --- a/tests/snapshots/ssa/void_function_produces_no_value.ssa +++ b/tests/snapshots/ssa/void_function_produces_no_value.ssa @@ -98,19 +98,19 @@ fn ent_pc=3 n_params=0 variadic=false locals=7 terminator Return(v41) (exit_acc=v41) block 6 start_pc=0 v42 Imm(2) -> x0 - v43 Imm(3) -> x1 - v44 Extend { value=v42, kind=I32 } -> x2 - v45 Imm(0) -> x2 - v46 Extend { value=v43, kind=I32 } -> x2 - v47 Imm(0) -> x2 - v48 Binop { op=mul, lhs=v42, rhs=v43 } -> x0 - v49 BinopI { op=shl, lhs=v48, rhs_imm=32 } -> x1 - v50 Extend { value=v48, kind=I32 } -> x1 - v51 BinopI { op=add, lhs=v48, rhs_imm=7 } -> x0 - v52 BinopI { op=shl, lhs=v51, rhs_imm=32 } -> x1 - v53 Extend { value=v51, kind=I32 } -> x1 - v54 Imm(0) -> x1 - v55 BinopI { op=and, lhs=v51, rhs_imm=255 } -> x0 + v43 Imm(3) -> x0 + v44 Imm(2) -> x0 + v45 Imm(0) -> x0 + v46 Imm(3) -> x0 + v47 Imm(0) -> x0 + v48 Imm(6) -> x0 + v49 Imm(25769803776) -> x0 + v50 Imm(6) -> x0 + v51 Imm(13) -> x0 + v52 Imm(55834574848) -> x0 + v53 Imm(13) -> x0 + v54 Imm(0) -> x0 + v55 Imm(13) -> x0 v56 Imm(0) -> x0 v57 Imm(0) -> x3 v58 Call { target_pc=2, args=[v57], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 diff --git a/tests/snapshots/ssa/volatile_param_classes.ssa b/tests/snapshots/ssa/volatile_param_classes.ssa index 837baf316..94d43d4d5 100644 --- a/tests/snapshots/ssa/volatile_param_classes.ssa +++ b/tests/snapshots/ssa/volatile_param_classes.ssa @@ -54,7 +54,7 @@ fn ent_pc=2 n_params=2 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=5 - spill_count=0 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-2) -> x0 @@ -72,36 +72,35 @@ fn ent_pc=3 n_params=0 variadic=false locals=5 v13 LocalAddr(-2) -> x0 v14 Load { addr=v13, disp=0, kind=F64 } -> d0 v15 Imm(4620130267728707584) -> x0 - v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x3 + v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x1 v17 Imm(0) -> x0 terminator Bnz { cond=v16, target=b7, fall=b1 } (exit_acc=v16) block 1 start_pc=0 v18 LocalAddr(-2) -> x0 v19 BinopI { op=add, lhs=v18, rhs_imm=8 } -> x1 v20 Load { addr=v18, disp=8, kind=I64 } -> x0 - v21 BinopI { op=ne, lhs=v20, rhs_imm=3 } -> x3 + v21 BinopI { op=ne, lhs=v20, rhs_imm=3 } -> x1 v22 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v21) block 2 start_pc=0 - v23 Phi { incoming=[b7:v16, b1:v21], kind=I64 } -> x3 + v23 Phi { incoming=[b7:v16, b1:v21], kind=I64 } -> x1 v24 LoadLocal { off=-5, kind=I64 } -> x0 terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 v25 Imm(1) -> x0 terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 - v26 Imm(4617315517961601024) -> x0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Call { target_pc=1, args=[v27], fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 - v29 Imm(4612811918334230528) -> x0 - v30 Binop { op=fne, lhs=v28, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + v26 Imm(1084227584) -> x7 [f32] + v27 Call { target_pc=1, args=[v26], fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 + v28 Imm(4612811918334230528) -> x0 + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v31 Imm(2) -> x0 - terminator Return(v31) (exit_acc=v31) + v30 Imm(2) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v32 Imm(0) -> x0 - terminator Return(v32) (exit_acc=v32) + v31 Imm(0) -> x0 + terminator Return(v31) (exit_acc=v31) block 7 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/volatile_ptr_alias_loop.ssa b/tests/snapshots/ssa/volatile_ptr_alias_loop.ssa index ced7a2a8b..2f6e00613 100644 --- a/tests/snapshots/ssa/volatile_ptr_alias_loop.ssa +++ b/tests/snapshots/ssa/volatile_ptr_alias_loop.ssa @@ -9,13 +9,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v3 LocalAddr(-1) -> x0 v4 StoreLocal { off=-2, value=v3, kind=I64, volatile } -> - v5 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b3) (exit_acc=v1) block 1 start_pc=0 - v6 Phi { incoming=[b0:v1, b5:v16], kind=I64 } -> x1 - v7 LoadLocal { off=-1, kind=I32, volatile } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=3 } -> x0 - terminator Bz { cond=v8, target=b3, fall=b2 } (exit_acc=v8) - block 2 start_pc=0 v9 LoadLocal { off=-2, kind=I64, volatile } -> x0 v10 LoadLocal { off=-1, kind=I32, volatile } -> x2 v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x2 @@ -27,28 +22,33 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v17 Imm(0) -> x0 v18 Extend { value=v16, kind=I32 } -> x0 v19 BinopI { op=gt, lhs=v18, rhs_imm=10 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b4 } (exit_acc=v19) + terminator Bnz { cond=v19, target=b8, fall=b2 } (exit_acc=v19) + block 2 start_pc=0 + terminator Jmp(b3) block 3 start_pc=0 + v6 Phi { incoming=[b0:v1, b2:v16], kind=I64 } -> x1 + v7 LoadLocal { off=-1, kind=I32, volatile } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=3 } -> x0 + terminator Bnz { cond=v8, target=b1, fall=b4 } (exit_acc=v8) + block 4 start_pc=0 v20 Extend { value=v6, kind=I32 } -> x0 v21 BinopI { op=eq, lhs=v20, rhs_imm=3 } -> x0 - terminator Bz { cond=v21, target=b7, fall=b6 } (exit_acc=v21) - block 4 start_pc=0 - v22 Imm(1) -> x0 - terminator Return(v22) (exit_acc=v22) + terminator Bz { cond=v21, target=b7, fall=b5 } (exit_acc=v21) block 5 start_pc=0 - terminator Jmp(b1) - block 6 start_pc=0 v23 Imm(0) -> x1 v24 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v23) + terminator Jmp(b6) (exit_acc=v23) + block 6 start_pc=0 + v27 Phi { incoming=[b5:v23, b7:v25], kind=I64 } -> x1 + v28 LoadLocal { off=-4, kind=I64 } -> x0 + terminator Return(v27) (exit_acc=v27) block 7 start_pc=0 v25 Imm(2) -> x1 v26 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v25) + terminator Jmp(b6) (exit_acc=v25) block 8 start_pc=0 - v27 Phi { incoming=[b6:v23, b7:v25], kind=I64 } -> x1 - v28 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Return(v27) (exit_acc=v27) + v22 Imm(1) -> x0 + terminator Return(v22) (exit_acc=v22) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/volatile_setjmp_longjmp.ssa b/tests/snapshots/ssa/volatile_setjmp_longjmp.ssa index f36a666e6..edd120422 100644 --- a/tests/snapshots/ssa/volatile_setjmp_longjmp.ssa +++ b/tests/snapshots/ssa/volatile_setjmp_longjmp.ssa @@ -20,19 +20,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 2 start_pc=0 v11 LoadLocal { off=-1, kind=I32, volatile } -> x0 v12 BinopI { op=eq, lhs=v11, rhs_imm=2 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + terminator Bz { cond=v12, target=b5, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v13) + terminator Jmp(b4) (exit_acc=v13) block 4 start_pc=0 - v15 Imm(1) -> x1 - v16 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v15) - block 5 start_pc=0 - v17 Phi { incoming=[b3:v13, b4:v15], kind=I64 } -> x1 + v17 Phi { incoming=[b3:v13, b5:v15], kind=I64 } -> x1 v18 LoadLocal { off=-4, kind=I64 } -> x0 terminator Return(v17) (exit_acc=v17) + block 5 start_pc=0 + v15 Imm(1) -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v15) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/volatile_unused_read.ssa b/tests/snapshots/ssa/volatile_unused_read.ssa index 510a98760..89c88bf85 100644 --- a/tests/snapshots/ssa/volatile_unused_read.ssa +++ b/tests/snapshots/ssa/volatile_unused_read.ssa @@ -21,19 +21,19 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 block 2 start_pc=0 v12 Phi { incoming=[b6:v7, b1:v10], kind=I64 } -> x1 v13 LoadLocal { off=-2, kind=I64 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + terminator Bz { cond=v12, target=b5, fall=b3 } (exit_acc=v12) block 3 start_pc=0 v14 Imm(0) -> x1 v15 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v14) + terminator Jmp(b4) (exit_acc=v14) block 4 start_pc=0 - v16 Imm(1) -> x1 - v17 Imm(0) -> x0 - terminator Jmp(b5) (exit_acc=v16) - block 5 start_pc=0 - v18 Phi { incoming=[b3:v14, b4:v16], kind=I64 } -> x1 + v18 Phi { incoming=[b3:v14, b5:v16], kind=I64 } -> x1 v19 LoadLocal { off=-3, kind=I64 } -> x0 terminator Return(v18) (exit_acc=v18) + block 5 start_pc=0 + v16 Imm(1) -> x1 + v17 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v16) block 6 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/warn_dead_store.ssa b/tests/snapshots/ssa/warn_dead_store.ssa index 1c62b5089..73fffbf4a 100644 --- a/tests/snapshots/ssa/warn_dead_store.ssa +++ b/tests/snapshots/ssa/warn_dead_store.ssa @@ -17,11 +17,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(5) -> x0 - v2 Imm(0) -> x1 - v3 LoadLocal { off=-1, kind=I32 } -> x1 - v4 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v5 BinopI { op=shl, lhs=v4, rhs_imm=32 } -> x1 - v6 Extend { value=v4, kind=I32 } -> x0 + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=I32 } -> x0 + v4 Imm(6) -> x0 + v5 Imm(25769803776) -> x0 + v6 Imm(6) -> x0 v7 Imm(0) -> x1 v8 LoadLocal { off=-1, kind=I32 } -> x1 terminator Return(v6) (exit_acc=v6) @@ -67,21 +67,21 @@ fn ent_pc=4 n_params=0 variadic=false locals=1 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x0 - v2 Imm(0) -> x1 - v3 Imm(2) -> x1 - v4 Imm(0) -> x1 - v5 Imm(5) -> x1 - v6 Imm(0) -> x2 - v7 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x1 - v8 BinopI { op=shl, lhs=v7, rhs_imm=32 } -> x2 - v9 Extend { value=v7, kind=I32 } -> x2 - v10 Imm(0) -> x2 - v11 Binop { op=add, lhs=v1, rhs=v7 } -> x3 - v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x0 - v13 Extend { value=v11, kind=I32 } -> x0 + v2 Imm(0) -> x0 + v3 Imm(2) -> x0 + v4 Imm(0) -> x0 + v5 Imm(5) -> x0 + v6 Imm(0) -> x0 + v7 Imm(6) -> x0 + v8 Imm(25769803776) -> x0 + v9 Imm(6) -> x0 + v10 Imm(0) -> x0 + v11 Imm(7) -> x0 + v12 Imm(30064771072) -> x0 + v13 Imm(7) -> x0 v14 Imm(1) -> x7 v15 Call { target_pc=2, args=[v14], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v16 Binop { op=add, lhs=v11, rhs=v15 } -> x3 + v16 BinopI { op=add, lhs=v15, rhs_imm=7 } -> x3 v17 BinopI { op=shl, lhs=v16, rhs_imm=32 } -> x0 v18 Extend { value=v16, kind=I32 } -> x0 v19 Call { target_pc=3, args=[], fixed_args=0, fp_return=false, fp_arg_mask=0x0 } -> x0 diff --git a/tests/snapshots/ssa/warn_unused_symbols.ssa b/tests/snapshots/ssa/warn_unused_symbols.ssa index 88772352d..f2bc09ccc 100644 --- a/tests/snapshots/ssa/warn_unused_symbols.ssa +++ b/tests/snapshots/ssa/warn_unused_symbols.ssa @@ -38,27 +38,27 @@ fn ent_pc=2 n_params=0 variadic=false locals=9 v3 Imm(99) -> x0 v4 Imm(0) -> x0 v5 Imm(5) -> x0 - v6 Imm(0) -> x1 - v7 Imm(1) -> x1 - v8 Imm(0) -> x1 - v9 Imm(2) -> x1 - v10 Imm(0) -> x1 - v11 LoadLocal { off=-4, kind=I32 } -> x1 - v12 BinopI { op=add, lhs=v5, rhs_imm=1 } -> x0 - v13 BinopI { op=shl, lhs=v12, rhs_imm=32 } -> x1 - v14 Extend { value=v12, kind=I32 } -> x1 - v15 Imm(0) -> x2 - v16 LoadLocal { off=-7, kind=I32 } -> x2 - v17 Imm(0) -> x2 - v18 Extend { value=v14, kind=I32 } -> x1 - v19 Imm(0) -> x2 - v20 Extend { value=v18, kind=I32 } -> x1 - v21 Imm(0) -> x1 - v22 Extend { value=v19, kind=I32 } -> x1 - v23 Imm(0) -> x1 - v24 BinopI { op=shl, lhs=v12, rhs_imm=1 } -> x0 - v25 BinopI { op=shl, lhs=v24, rhs_imm=32 } -> x1 - v26 Extend { value=v24, kind=I32 } -> x0 + v6 Imm(0) -> x0 + v7 Imm(1) -> x0 + v8 Imm(0) -> x0 + v9 Imm(2) -> x0 + v10 Imm(0) -> x0 + v11 LoadLocal { off=-4, kind=I32 } -> x0 + v12 Imm(6) -> x0 + v13 Imm(25769803776) -> x0 + v14 Imm(6) -> x0 + v15 Imm(0) -> x0 + v16 LoadLocal { off=-7, kind=I32 } -> x0 + v17 Imm(0) -> x0 + v18 Imm(6) -> x0 + v19 Imm(0) -> x0 + v20 Imm(6) -> x0 + v21 Imm(0) -> x0 + v22 Imm(0) -> x0 + v23 Imm(0) -> x0 + v24 Imm(12) -> x0 + v25 Imm(51539607552) -> x0 + v26 Imm(12) -> x0 v27 Imm(0) -> x1 v28 Imm(11) -> x1 v29 Imm(0) -> x1 diff --git a/tests/snapshots/ssa/wide_char_utf8.ssa b/tests/snapshots/ssa/wide_char_utf8.ssa index dd5a65693..f58e4b437 100644 --- a/tests/snapshots/ssa/wide_char_utf8.ssa +++ b/tests/snapshots/ssa/wide_char_utf8.ssa @@ -5,23 +5,17 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(225) -> x0 - v2 Imm(0) -> x1 - v3 Imm(8364) -> x1 - v4 Imm(0) -> x2 - v5 LoadLocal { off=-1, kind=I32 } -> x2 - v6 BinopI { op=ne, lhs=v1, rhs_imm=225 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v2 Imm(0) -> x0 + v3 Imm(8364) -> x0 + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=I32 } -> x0 + v6 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v6) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) - block 2 start_pc=0 v8 LoadLocal { off=-2, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v3, rhs_imm=8364 } -> x0 - terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) - block 3 start_pc=0 - v10 Imm(2) -> x0 - terminator Return(v10) (exit_acc=v10) - block 4 start_pc=0 + v9 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v9) + block 2 start_pc=0 v11 ImmData(11) -> x0 v12 Imm(0) -> x1 v13 Load { addr=v11, disp=0, kind=I8 } -> x0 @@ -29,11 +23,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v15 BinopI { op=xor, lhs=v14, rhs_imm=195 } -> x0 v16 BinopI { op=and, lhs=v15, rhs_imm=4294967295 } -> x0 v17 BinopI { op=ne, lhs=v16, rhs_imm=0 } -> x0 - terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) - block 5 start_pc=0 + terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) + block 3 start_pc=0 v18 Imm(3) -> x0 terminator Return(v18) (exit_acc=v18) - block 6 start_pc=0 + block 4 start_pc=0 v19 ImmData(11) -> x0 v20 Imm(1) -> x1 v21 BinopI { op=add, lhs=v19, rhs_imm=1 } -> x1 @@ -42,37 +36,34 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v24 BinopI { op=xor, lhs=v23, rhs_imm=161 } -> x0 v25 BinopI { op=and, lhs=v24, rhs_imm=4294967295 } -> x0 v26 BinopI { op=ne, lhs=v25, rhs_imm=0 } -> x0 - terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) - block 7 start_pc=0 + terminator Bz { cond=v26, target=b6, fall=b5 } (exit_acc=v26) + block 5 start_pc=0 v27 Imm(4) -> x0 terminator Return(v27) (exit_acc=v27) - block 8 start_pc=0 + block 6 start_pc=0 v28 ImmData(11) -> x0 v29 Imm(2) -> x1 v30 BinopI { op=add, lhs=v28, rhs_imm=2 } -> x1 v31 Load { addr=v28, disp=2, kind=I8 } -> x0 v32 BinopI { op=ne, lhs=v31, rhs_imm=0 } -> x0 - terminator Bz { cond=v32, target=b10, fall=b9 } (exit_acc=v32) - block 9 start_pc=0 + terminator Bz { cond=v32, target=b8, fall=b7 } (exit_acc=v32) + block 7 start_pc=0 v33 Imm(5) -> x0 terminator Return(v33) (exit_acc=v33) - block 10 start_pc=0 + block 8 start_pc=0 v34 Imm(16) -> x0 v35 Imm(68719476736) -> x0 v36 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v36) - block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) - block 12 start_pc=0 + terminator Jmp(b9) (exit_acc=v36) + block 9 start_pc=0 v38 ImmData(40) -> x0 v39 Imm(0) -> x1 v40 Load { addr=v38, disp=0, kind=I32 } -> x0 v41 BinopI { op=ne, lhs=v40, rhs_imm=97 } -> x0 v42 Imm(1) -> x2 v43 Imm(0) -> x1 - terminator Bnz { cond=v41, target=b31, fall=b13 } (exit_acc=v41) - block 13 start_pc=0 + terminator Bnz { cond=v41, target=b32, fall=b10 } (exit_acc=v41) + block 10 start_pc=0 v44 ImmData(40) -> x0 v45 Imm(4) -> x1 v46 BinopI { op=add, lhs=v44, rhs_imm=4 } -> x1 @@ -80,14 +71,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v48 BinopI { op=ne, lhs=v47, rhs_imm=225 } -> x0 v49 BinopI { op=ne, lhs=v48, rhs_imm=0 } -> x2 v50 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v49) - block 14 start_pc=0 - v51 Phi { incoming=[b31:v42, b13:v49], kind=I64 } -> x2 + terminator Jmp(b11) (exit_acc=v49) + block 11 start_pc=0 + v51 Phi { incoming=[b32:v42, b10:v49], kind=I64 } -> x2 v52 LoadLocal { off=-6, kind=I64 } -> x0 v53 Imm(1) -> x1 v54 Imm(0) -> x0 - terminator Bnz { cond=v51, target=b32, fall=b15 } (exit_acc=v51) - block 15 start_pc=0 + terminator Bnz { cond=v51, target=b31, fall=b12 } (exit_acc=v51) + block 12 start_pc=0 v55 ImmData(40) -> x0 v56 Imm(8) -> x1 v57 BinopI { op=add, lhs=v55, rhs_imm=8 } -> x1 @@ -95,34 +86,31 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v59 BinopI { op=ne, lhs=v58, rhs_imm=98 } -> x0 v60 BinopI { op=ne, lhs=v59, rhs_imm=0 } -> x1 v61 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v60) - block 16 start_pc=0 - v62 Phi { incoming=[b32:v53, b15:v60], kind=I64 } -> x1 + terminator Jmp(b13) (exit_acc=v60) + block 13 start_pc=0 + v62 Phi { incoming=[b31:v53, b12:v60], kind=I64 } -> x1 v63 LoadLocal { off=-5, kind=I64 } -> x0 v64 Imm(0) -> x0 - terminator Bnz { cond=v62, target=b33, fall=b17 } (exit_acc=v62) - block 17 start_pc=0 + terminator Bnz { cond=v62, target=b30, fall=b14 } (exit_acc=v62) + block 14 start_pc=0 v65 ImmData(40) -> x0 v66 Imm(12) -> x1 v67 BinopI { op=add, lhs=v65, rhs_imm=12 } -> x1 v68 Load { addr=v65, disp=12, kind=I32 } -> x0 v69 BinopI { op=ne, lhs=v68, rhs_imm=0 } -> x1 v70 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v69) - block 18 start_pc=0 - v71 Phi { incoming=[b33:v62, b17:v69], kind=I64 } -> x1 + terminator Jmp(b15) (exit_acc=v69) + block 15 start_pc=0 + v71 Phi { incoming=[b30:v62, b14:v69], kind=I64 } -> x1 v72 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v71, target=b20, fall=b19 } (exit_acc=v71) - block 19 start_pc=0 + terminator Bz { cond=v71, target=b17, fall=b16 } (exit_acc=v71) + block 16 start_pc=0 v73 Imm(7) -> x0 terminator Return(v73) (exit_acc=v73) - block 20 start_pc=0 + block 17 start_pc=0 v74 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v74) - block 21 start_pc=0 - v75 Imm(8) -> x0 - terminator Return(v75) (exit_acc=v75) - block 22 start_pc=0 + terminator Jmp(b18) (exit_acc=v74) + block 18 start_pc=0 v76 ImmData(56) -> x0 v77 Imm(0) -> x1 v78 LoadLocal { off=-3, kind=I64 } -> x1 @@ -131,8 +119,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v81 BinopI { op=ne, lhs=v80, rhs_imm=72 } -> x1 v82 Imm(1) -> x6 v83 Imm(0) -> x2 - terminator Bnz { cond=v81, target=b34, fall=b23 } (exit_acc=v81) - block 23 start_pc=0 + terminator Bnz { cond=v81, target=b29, fall=b19 } (exit_acc=v81) + block 19 start_pc=0 v84 LoadLocal { off=-3, kind=I64 } -> x1 v85 Imm(24) -> x1 v86 BinopI { op=add, lhs=v76, rhs_imm=24 } -> x1 @@ -140,14 +128,14 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v88 BinopI { op=ne, lhs=v87, rhs_imm=87 } -> x1 v89 BinopI { op=ne, lhs=v88, rhs_imm=0 } -> x6 v90 Imm(0) -> x1 - terminator Jmp(b24) (exit_acc=v89) - block 24 start_pc=0 - v91 Phi { incoming=[b34:v82, b23:v89], kind=I64 } -> x6 + terminator Jmp(b20) (exit_acc=v89) + block 20 start_pc=0 + v91 Phi { incoming=[b29:v82, b19:v89], kind=I64 } -> x6 v92 LoadLocal { off=-9, kind=I64 } -> x1 v93 Imm(1) -> x2 v94 Imm(0) -> x1 - terminator Bnz { cond=v91, target=b35, fall=b25 } (exit_acc=v91) - block 25 start_pc=0 + terminator Bnz { cond=v91, target=b28, fall=b21 } (exit_acc=v91) + block 21 start_pc=0 v95 LoadLocal { off=-3, kind=I64 } -> x1 v96 Imm(44) -> x1 v97 BinopI { op=add, lhs=v76, rhs_imm=44 } -> x1 @@ -155,42 +143,54 @@ fn ent_pc=0 n_params=0 variadic=false locals=9 v99 BinopI { op=ne, lhs=v98, rhs_imm=33 } -> x1 v100 BinopI { op=ne, lhs=v99, rhs_imm=0 } -> x2 v101 Imm(0) -> x1 - terminator Jmp(b26) (exit_acc=v100) - block 26 start_pc=0 - v102 Phi { incoming=[b35:v93, b25:v100], kind=I64 } -> x2 + terminator Jmp(b22) (exit_acc=v100) + block 22 start_pc=0 + v102 Phi { incoming=[b28:v93, b21:v100], kind=I64 } -> x2 v103 LoadLocal { off=-8, kind=I64 } -> x1 v104 Imm(0) -> x1 - terminator Bnz { cond=v102, target=b36, fall=b27 } (exit_acc=v102) - block 27 start_pc=0 + terminator Bnz { cond=v102, target=b27, fall=b23 } (exit_acc=v102) + block 23 start_pc=0 v105 LoadLocal { off=-3, kind=I64 } -> x1 v106 Imm(48) -> x1 v107 BinopI { op=add, lhs=v76, rhs_imm=48 } -> x1 v108 Load { addr=v76, disp=48, kind=I32 } -> x0 v109 BinopI { op=ne, lhs=v108, rhs_imm=0 } -> x2 v110 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v109) - block 28 start_pc=0 - v111 Phi { incoming=[b36:v102, b27:v109], kind=I64 } -> x2 + terminator Jmp(b24) (exit_acc=v109) + block 24 start_pc=0 + v111 Phi { incoming=[b27:v102, b23:v109], kind=I64 } -> x2 v112 LoadLocal { off=-7, kind=I64 } -> x0 - terminator Bz { cond=v111, target=b30, fall=b29 } (exit_acc=v111) - block 29 start_pc=0 + terminator Bz { cond=v111, target=b26, fall=b25 } (exit_acc=v111) + block 25 start_pc=0 v113 Imm(9) -> x0 terminator Return(v113) (exit_acc=v113) - block 30 start_pc=0 + block 26 start_pc=0 v114 Imm(0) -> x0 terminator Return(v114) (exit_acc=v114) + block 27 start_pc=0 + terminator Jmp(b24) + block 28 start_pc=0 + terminator Jmp(b22) + block 29 start_pc=0 + terminator Jmp(b20) + block 30 start_pc=0 + terminator Jmp(b15) block 31 start_pc=0 - terminator Jmp(b14) + terminator Jmp(b13) block 32 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b11) block 33 start_pc=0 - terminator Jmp(b18) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 34 start_pc=0 - terminator Jmp(b24) + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) block 35 start_pc=0 - terminator Jmp(b26) + v37 Imm(6) -> x0 + terminator Return(v37) (exit_acc=v37) block 36 start_pc=0 - terminator Jmp(b28) + v75 Imm(8) -> x0 + terminator Return(v75) (exit_acc=v75) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/wide_string_literal_size.ssa b/tests/snapshots/ssa/wide_string_literal_size.ssa index 0785b796b..0207120a1 100644 --- a/tests/snapshots/ssa/wide_string_literal_size.ssa +++ b/tests/snapshots/ssa/wide_string_literal_size.ssa @@ -5,87 +5,63 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(4) -> x0 - v2 Imm(0) -> x1 - v3 Imm(1) -> x1 - v4 LoadLocal { off=-1, kind=U32 } -> x1 - v5 BinopI { op=xor, lhs=v1, rhs_imm=4 } -> x1 - v6 BinopI { op=and, lhs=v5, rhs_imm=4294967295 } -> x1 - v7 BinopI { op=ne, lhs=v6, rhs_imm=0 } -> x1 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(0) -> x0 + v3 Imm(1) -> x0 + v4 LoadLocal { off=-1, kind=U32 } -> x0 + v5 Imm(0) -> x0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v9 Imm(8) -> x0 + v10 Imm(2) -> x0 + v11 LoadLocal { off=-1, kind=U32 } -> x0 + v12 Imm(8) -> x0 + v13 Imm(8) -> x0 + v14 Imm(0) -> x0 + v15 Imm(0) -> x0 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v9 Imm(8) -> x1 - v10 Imm(2) -> x1 - v11 LoadLocal { off=-1, kind=U32 } -> x1 - v12 BinopI { op=shl, lhs=v1, rhs_imm=1 } -> x1 - v13 BinopI { op=and, lhs=v12, rhs_imm=4294967295 } -> x1 - v14 BinopI { op=xor, lhs=v13, rhs_imm=8 } -> x1 - v15 BinopI { op=and, lhs=v14, rhs_imm=4294967295 } -> x1 - v16 BinopI { op=ne, lhs=v15, rhs_imm=0 } -> x1 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + v18 Imm(12) -> x0 + v19 Imm(3) -> x0 + v20 LoadLocal { off=-1, kind=U32 } -> x0 + v21 Imm(12) -> x0 + v22 Imm(12) -> x0 + v23 Imm(0) -> x0 + v24 Imm(0) -> x0 + v25 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v25) block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) + v27 Imm(12) -> x0 + v28 Imm(3) -> x0 + v29 LoadLocal { off=-1, kind=U32 } -> x0 + v30 Imm(12) -> x0 + v31 Imm(12) -> x0 + v32 Imm(0) -> x0 + v33 Imm(0) -> x0 + v34 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v34) block 4 start_pc=0 - v18 Imm(12) -> x1 - v19 Imm(3) -> x1 - v20 LoadLocal { off=-1, kind=U32 } -> x1 - v21 BinopI { op=mul, lhs=v1, rhs_imm=3 } -> x1 - v22 BinopI { op=and, lhs=v21, rhs_imm=4294967295 } -> x1 - v23 BinopI { op=xor, lhs=v22, rhs_imm=12 } -> x1 - v24 BinopI { op=and, lhs=v23, rhs_imm=4294967295 } -> x1 - v25 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x1 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) + v36 Imm(24) -> x0 + v37 Imm(6) -> x0 + v38 LoadLocal { off=-1, kind=U32 } -> x0 + v39 Imm(24) -> x0 + v40 Imm(24) -> x0 + v41 Imm(0) -> x0 + v42 Imm(0) -> x0 + v43 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v43) block 5 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) - block 6 start_pc=0 - v27 Imm(12) -> x1 - v28 Imm(3) -> x1 - v29 LoadLocal { off=-1, kind=U32 } -> x1 - v30 BinopI { op=mul, lhs=v1, rhs_imm=3 } -> x1 - v31 BinopI { op=and, lhs=v30, rhs_imm=4294967295 } -> x1 - v32 BinopI { op=xor, lhs=v31, rhs_imm=12 } -> x1 - v33 BinopI { op=and, lhs=v32, rhs_imm=4294967295 } -> x1 - v34 BinopI { op=ne, lhs=v33, rhs_imm=0 } -> x1 - terminator Bz { cond=v34, target=b8, fall=b7 } (exit_acc=v34) - block 7 start_pc=0 - v35 Imm(4) -> x0 - terminator Return(v35) (exit_acc=v35) - block 8 start_pc=0 - v36 Imm(24) -> x1 - v37 Imm(6) -> x1 - v38 LoadLocal { off=-1, kind=U32 } -> x1 - v39 BinopI { op=mul, lhs=v1, rhs_imm=6 } -> x0 - v40 BinopI { op=and, lhs=v39, rhs_imm=4294967295 } -> x0 - v41 BinopI { op=xor, lhs=v40, rhs_imm=24 } -> x0 - v42 BinopI { op=and, lhs=v41, rhs_imm=4294967295 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) - block 9 start_pc=0 - v44 Imm(5) -> x0 - terminator Return(v44) (exit_acc=v44) - block 10 start_pc=0 v45 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v45) - block 11 start_pc=0 - v46 Imm(6) -> x0 - terminator Return(v46) (exit_acc=v46) - block 12 start_pc=0 + terminator Jmp(b6) (exit_acc=v45) + block 6 start_pc=0 v47 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v47) - block 13 start_pc=0 - v48 Imm(7) -> x0 - terminator Return(v48) (exit_acc=v48) - block 14 start_pc=0 + terminator Jmp(b7) (exit_acc=v47) + block 7 start_pc=0 v49 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v49) - block 15 start_pc=0 - v50 Imm(8) -> x0 - terminator Return(v50) (exit_acc=v50) - block 16 start_pc=0 + terminator Jmp(b8) (exit_acc=v49) + block 8 start_pc=0 v51 ImmData(12) -> x0 v52 Imm(0) -> x1 v53 LoadLocal { off=-2, kind=I64 } -> x1 @@ -94,8 +70,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v56 BinopI { op=ne, lhs=v55, rhs_imm=97 } -> x1 v57 Imm(1) -> x6 v58 Imm(0) -> x2 - terminator Bnz { cond=v56, target=b23, fall=b17 } (exit_acc=v56) - block 17 start_pc=0 + terminator Bnz { cond=v56, target=b16, fall=b9 } (exit_acc=v56) + block 9 start_pc=0 v59 LoadLocal { off=-2, kind=I64 } -> x1 v60 Imm(4) -> x1 v61 BinopI { op=add, lhs=v51, rhs_imm=4 } -> x1 @@ -103,34 +79,58 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 v63 BinopI { op=ne, lhs=v62, rhs_imm=98 } -> x1 v64 BinopI { op=ne, lhs=v63, rhs_imm=0 } -> x6 v65 Imm(0) -> x1 - terminator Jmp(b18) (exit_acc=v64) - block 18 start_pc=0 - v66 Phi { incoming=[b23:v57, b17:v64], kind=I64 } -> x6 + terminator Jmp(b10) (exit_acc=v64) + block 10 start_pc=0 + v66 Phi { incoming=[b16:v57, b9:v64], kind=I64 } -> x6 v67 LoadLocal { off=-4, kind=I64 } -> x1 v68 Imm(0) -> x1 - terminator Bnz { cond=v66, target=b24, fall=b19 } (exit_acc=v66) - block 19 start_pc=0 + terminator Bnz { cond=v66, target=b15, fall=b11 } (exit_acc=v66) + block 11 start_pc=0 v69 LoadLocal { off=-2, kind=I64 } -> x1 v70 Imm(8) -> x1 v71 BinopI { op=add, lhs=v51, rhs_imm=8 } -> x1 v72 Load { addr=v51, disp=8, kind=I32 } -> x0 v73 BinopI { op=ne, lhs=v72, rhs_imm=0 } -> x6 v74 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v73) - block 20 start_pc=0 - v75 Phi { incoming=[b24:v66, b19:v73], kind=I64 } -> x6 + terminator Jmp(b12) (exit_acc=v73) + block 12 start_pc=0 + v75 Phi { incoming=[b15:v66, b11:v73], kind=I64 } -> x6 v76 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v75, target=b22, fall=b21 } (exit_acc=v75) - block 21 start_pc=0 + terminator Bz { cond=v75, target=b14, fall=b13 } (exit_acc=v75) + block 13 start_pc=0 v77 Imm(9) -> x0 terminator Return(v77) (exit_acc=v77) - block 22 start_pc=0 + block 14 start_pc=0 v78 Imm(0) -> x0 terminator Return(v78) (exit_acc=v78) + block 15 start_pc=0 + terminator Jmp(b12) + block 16 start_pc=0 + terminator Jmp(b10) + block 17 start_pc=0 + v8 Imm(1) -> x0 + terminator Return(v8) (exit_acc=v8) + block 18 start_pc=0 + v17 Imm(2) -> x0 + terminator Return(v17) (exit_acc=v17) + block 19 start_pc=0 + v26 Imm(3) -> x0 + terminator Return(v26) (exit_acc=v26) + block 20 start_pc=0 + v35 Imm(4) -> x0 + terminator Return(v35) (exit_acc=v35) + block 21 start_pc=0 + v44 Imm(5) -> x0 + terminator Return(v44) (exit_acc=v44) + block 22 start_pc=0 + v46 Imm(6) -> x0 + terminator Return(v46) (exit_acc=v46) block 23 start_pc=0 - terminator Jmp(b18) + v48 Imm(7) -> x0 + terminator Return(v48) (exit_acc=v48) block 24 start_pc=0 - terminator Jmp(b20) + v50 Imm(8) -> x0 + terminator Return(v50) (exit_acc=v50) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/width_typedefs.ssa b/tests/snapshots/ssa/width_typedefs.ssa index c5c7b24b4..f90d4e6a9 100644 --- a/tests/snapshots/ssa/width_typedefs.ssa +++ b/tests/snapshots/ssa/width_typedefs.ssa @@ -5,31 +5,31 @@ fn ent_pc=6 n_params=0 variadic=false locals=0 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(100) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v3) + terminator Jmp(b2) (exit_acc=v3) + block 2 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b3) (exit_acc=v5) block 3 start_pc=0 - v4 Imm(1) -> x0 - terminator Return(v4) (exit_acc=v4) + v7 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v7) block 4 start_pc=0 - v5 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v5) + v9 Imm(0) -> x0 + terminator Return(v9) (exit_acc=v9) block 5 start_pc=0 - v6 Imm(2) -> x0 - terminator Return(v6) (exit_acc=v6) + v2 Imm(100) -> x0 + terminator Return(v2) (exit_acc=v2) block 6 start_pc=0 - v7 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v7) + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) block 7 start_pc=0 + v6 Imm(2) -> x0 + terminator Return(v6) (exit_acc=v6) + block 8 start_pc=0 v8 Imm(3) -> x0 terminator Return(v8) (exit_acc=v8) - block 8 start_pc=0 - v9 Imm(0) -> x0 - terminator Return(v9) (exit_acc=v9) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/wmem_functions.ssa b/tests/snapshots/ssa/wmem_functions.ssa index e67a30416..be0193751 100644 --- a/tests/snapshots/ssa/wmem_functions.ssa +++ b/tests/snapshots/ssa/wmem_functions.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=0 --- ; name=main fn ent_pc=0 n_params=0 variadic=false locals=14 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 LocalAddr(-3) -> x0 @@ -51,35 +51,35 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v33 Imm(0) -> x1 v34 Load { addr=v32, disp=0, kind=I32 } -> x0 v35 BinopI { op=ne, lhs=v34, rhs_imm=7 } -> x0 - v36 Imm(1) -> x3 + v36 Imm(1) -> x2 v37 Imm(0) -> x1 - terminator Bnz { cond=v35, target=b21, fall=b7 } (exit_acc=v35) + terminator Bnz { cond=v35, target=b25, fall=b7 } (exit_acc=v35) block 7 start_pc=0 v38 LocalAddr(-6) -> x0 v39 Imm(4) -> x1 v40 BinopI { op=add, lhs=v38, rhs_imm=4 } -> x1 v41 Load { addr=v38, disp=4, kind=I32 } -> x0 v42 BinopI { op=ne, lhs=v41, rhs_imm=7 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=0 } -> x3 + v43 BinopI { op=ne, lhs=v42, rhs_imm=0 } -> x2 v44 Imm(0) -> x0 terminator Jmp(b8) (exit_acc=v43) block 8 start_pc=0 - v45 Phi { incoming=[b21:v36, b7:v43], kind=I64 } -> x3 + v45 Phi { incoming=[b25:v36, b7:v43], kind=I64 } -> x2 v46 LoadLocal { off=-12, kind=I64 } -> x0 - v47 Imm(1) -> x12 + v47 Imm(1) -> x1 v48 Imm(0) -> x0 - terminator Bnz { cond=v45, target=b22, fall=b9 } (exit_acc=v45) + terminator Bnz { cond=v45, target=b24, fall=b9 } (exit_acc=v45) block 9 start_pc=0 v49 LocalAddr(-6) -> x0 v50 Imm(8) -> x1 v51 BinopI { op=add, lhs=v49, rhs_imm=8 } -> x1 v52 Load { addr=v49, disp=8, kind=I32 } -> x0 v53 BinopI { op=ne, lhs=v52, rhs_imm=7 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x12 + v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x1 v55 Imm(0) -> x0 terminator Jmp(b10) (exit_acc=v54) block 10 start_pc=0 - v56 Phi { incoming=[b22:v47, b9:v54], kind=I64 } -> x12 + v56 Phi { incoming=[b24:v47, b9:v54], kind=I64 } -> x1 v57 LoadLocal { off=-11, kind=I64 } -> x0 v58 Imm(0) -> x0 terminator Bnz { cond=v56, target=b23, fall=b11 } (exit_acc=v56) @@ -88,11 +88,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v60 Imm(12) -> x1 v61 BinopI { op=add, lhs=v59, rhs_imm=12 } -> x1 v62 Load { addr=v59, disp=12, kind=I32 } -> x0 - v63 BinopI { op=ne, lhs=v62, rhs_imm=40 } -> x12 + v63 BinopI { op=ne, lhs=v62, rhs_imm=40 } -> x1 v64 Imm(0) -> x0 terminator Jmp(b12) (exit_acc=v63) block 12 start_pc=0 - v65 Phi { incoming=[b23:v56, b11:v63], kind=I64 } -> x12 + v65 Phi { incoming=[b23:v56, b11:v63], kind=I64 } -> x1 v66 LoadLocal { off=-10, kind=I64 } -> x0 terminator Bz { cond=v65, target=b14, fall=b13 } (exit_acc=v65) block 13 start_pc=0 @@ -111,7 +111,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v77 BinopI { op=ne, lhs=v76, rhs_imm=7 } -> x0 v78 Imm(1) -> x2 v79 Imm(0) -> x1 - terminator Bnz { cond=v77, target=b24, fall=b15 } (exit_acc=v77) + terminator Bnz { cond=v77, target=b22, fall=b15 } (exit_acc=v77) block 15 start_pc=0 v80 LocalAddr(-6) -> x0 v81 Imm(8) -> x1 @@ -122,10 +122,10 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v86 Imm(0) -> x0 terminator Jmp(b16) (exit_acc=v85) block 16 start_pc=0 - v87 Phi { incoming=[b24:v78, b15:v85], kind=I64 } -> x2 + v87 Phi { incoming=[b22:v78, b15:v85], kind=I64 } -> x2 v88 LoadLocal { off=-14, kind=I64 } -> x0 v89 Imm(0) -> x0 - terminator Bnz { cond=v87, target=b25, fall=b17 } (exit_acc=v87) + terminator Bnz { cond=v87, target=b21, fall=b17 } (exit_acc=v87) block 17 start_pc=0 v90 LocalAddr(-6) -> x0 v91 Imm(12) -> x1 @@ -135,7 +135,7 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v95 Imm(0) -> x0 terminator Jmp(b18) (exit_acc=v94) block 18 start_pc=0 - v96 Phi { incoming=[b25:v87, b17:v94], kind=I64 } -> x2 + v96 Phi { incoming=[b21:v87, b17:v94], kind=I64 } -> x2 v97 LoadLocal { off=-13, kind=I64 } -> x0 terminator Bz { cond=v96, target=b20, fall=b19 } (exit_acc=v96) block 19 start_pc=0 @@ -145,15 +145,15 @@ fn ent_pc=0 n_params=0 variadic=false locals=14 v99 Imm(0) -> x0 terminator Return(v99) (exit_acc=v99) block 21 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b18) block 22 start_pc=0 - terminator Jmp(b10) + terminator Jmp(b16) block 23 start_pc=0 terminator Jmp(b12) block 24 start_pc=0 - terminator Jmp(b16) + terminator Jmp(b10) block 25 start_pc=0 - terminator Jmp(b18) + terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/zero_length_array.ssa b/tests/snapshots/ssa/zero_length_array.ssa index e66a1a7a8..9ce515887 100644 --- a/tests/snapshots/ssa/zero_length_array.ssa +++ b/tests/snapshots/ssa/zero_length_array.ssa @@ -5,11 +5,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v2 Imm(1) -> x0 - terminator Return(v2) (exit_acc=v2) - block 2 start_pc=0 v3 ImmData(24) -> x0 v4 Imm(0) -> x1 v5 LoadLocal { off=-1, kind=I64 } -> x1 @@ -35,11 +32,11 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v25 LoadLocal { off=-1, kind=I64 } -> x1 v26 Load { addr=v3, disp=0, kind=I32 } -> x1 v27 BinopI { op=ne, lhs=v26, rhs_imm=3 } -> x1 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) - block 3 start_pc=0 + terminator Bz { cond=v27, target=b3, fall=b2 } (exit_acc=v27) + block 2 start_pc=0 v28 Imm(2) -> x0 terminator Return(v28) (exit_acc=v28) - block 4 start_pc=0 + block 3 start_pc=0 v29 LoadLocal { off=-1, kind=I64 } -> x1 v30 BinopI { op=add, lhs=v3, rhs_imm=4 } -> x1 v31 Imm(0) -> x1 @@ -49,8 +46,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v35 BinopI { op=ne, lhs=v34, rhs_imm=0 } -> x1 v36 Imm(1) -> x6 v37 Imm(0) -> x2 - terminator Bnz { cond=v35, target=b19, fall=b5 } (exit_acc=v35) - block 5 start_pc=0 + terminator Bnz { cond=v35, target=b20, fall=b4 } (exit_acc=v35) + block 4 start_pc=0 v38 LoadLocal { off=-1, kind=I64 } -> x1 v39 BinopI { op=add, lhs=v3, rhs_imm=4 } -> x1 v40 Imm(1) -> x1 @@ -61,13 +58,13 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v45 BinopI { op=ne, lhs=v44, rhs_imm=0 } -> x1 v46 BinopI { op=ne, lhs=v45, rhs_imm=0 } -> x6 v47 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v46) - block 6 start_pc=0 - v48 Phi { incoming=[b19:v36, b5:v46], kind=I64 } -> x6 + terminator Jmp(b5) (exit_acc=v46) + block 5 start_pc=0 + v48 Phi { incoming=[b20:v36, b4:v46], kind=I64 } -> x6 v49 LoadLocal { off=-4, kind=I64 } -> x1 v50 Imm(0) -> x1 - terminator Bnz { cond=v48, target=b20, fall=b7 } (exit_acc=v48) - block 7 start_pc=0 + terminator Bnz { cond=v48, target=b19, fall=b6 } (exit_acc=v48) + block 6 start_pc=0 v51 LoadLocal { off=-1, kind=I64 } -> x1 v52 BinopI { op=add, lhs=v3, rhs_imm=4 } -> x1 v53 Imm(2) -> x1 @@ -77,25 +74,25 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v57 BinopI { op=and, lhs=v56, rhs_imm=4294967295 } -> x1 v58 BinopI { op=ne, lhs=v57, rhs_imm=0 } -> x6 v59 Imm(0) -> x1 - terminator Jmp(b8) (exit_acc=v58) - block 8 start_pc=0 - v60 Phi { incoming=[b20:v48, b7:v58], kind=I64 } -> x6 + terminator Jmp(b7) (exit_acc=v58) + block 7 start_pc=0 + v60 Phi { incoming=[b19:v48, b6:v58], kind=I64 } -> x6 v61 LoadLocal { off=-3, kind=I64 } -> x1 - terminator Bz { cond=v60, target=b10, fall=b9 } (exit_acc=v60) - block 9 start_pc=0 + terminator Bz { cond=v60, target=b9, fall=b8 } (exit_acc=v60) + block 8 start_pc=0 v62 Imm(3) -> x0 terminator Return(v62) (exit_acc=v62) - block 10 start_pc=0 + block 9 start_pc=0 v63 LoadLocal { off=-1, kind=I64 } -> x1 v64 BinopI { op=add, lhs=v3, rhs_imm=4 } -> x0 v65 ImmData(24) -> x1 v66 BinopI { op=add, lhs=v65, rhs_imm=4 } -> x1 v67 Binop { op=ne, lhs=v64, rhs=v66 } -> x0 - terminator Bz { cond=v67, target=b12, fall=b11 } (exit_acc=v67) - block 11 start_pc=0 + terminator Bz { cond=v67, target=b11, fall=b10 } (exit_acc=v67) + block 10 start_pc=0 v68 Imm(4) -> x0 terminator Return(v68) (exit_acc=v68) - block 12 start_pc=0 + block 11 start_pc=0 v69 ImmData(40) -> x0 v70 Imm(0) -> x1 v71 LoadLocal { off=-2, kind=I64 } -> x1 @@ -118,8 +115,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v88 BinopI { op=and, lhs=v87, rhs_imm=4294967295 } -> x1 v89 BinopI { op=ne, lhs=v88, rhs_imm=0 } -> x2 v90 Imm(0) -> x1 - terminator Bnz { cond=v89, target=b21, fall=b13 } (exit_acc=v89) - block 13 start_pc=0 + terminator Bnz { cond=v89, target=b18, fall=b12 } (exit_acc=v89) + block 12 start_pc=0 v91 LoadLocal { off=-2, kind=I64 } -> x1 v92 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x1 v93 Imm(1) -> x1 @@ -129,34 +126,37 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 v97 BinopI { op=and, lhs=v96, rhs_imm=4294967295 } -> x1 v98 BinopI { op=ne, lhs=v97, rhs_imm=0 } -> x2 v99 Imm(0) -> x1 - terminator Jmp(b14) (exit_acc=v98) - block 14 start_pc=0 - v100 Phi { incoming=[b21:v89, b13:v98], kind=I64 } -> x2 + terminator Jmp(b13) (exit_acc=v98) + block 13 start_pc=0 + v100 Phi { incoming=[b18:v89, b12:v98], kind=I64 } -> x2 v101 LoadLocal { off=-5, kind=I64 } -> x1 - terminator Bz { cond=v100, target=b16, fall=b15 } (exit_acc=v100) - block 15 start_pc=0 + terminator Bz { cond=v100, target=b15, fall=b14 } (exit_acc=v100) + block 14 start_pc=0 v102 Imm(5) -> x0 terminator Return(v102) (exit_acc=v102) - block 16 start_pc=0 + block 15 start_pc=0 v103 LoadLocal { off=-2, kind=I64 } -> x1 v104 BinopI { op=add, lhs=v69, rhs_imm=4 } -> x1 v105 Imm(0) -> x1 v106 Load { addr=v69, disp=4, kind=U16 } -> x0 v107 BinopI { op=and, lhs=v106, rhs_imm=255 } -> x0 v108 BinopI { op=ne, lhs=v107, rhs_imm=171 } -> x0 - terminator Bz { cond=v108, target=b18, fall=b17 } (exit_acc=v108) - block 17 start_pc=0 + terminator Bz { cond=v108, target=b17, fall=b16 } (exit_acc=v108) + block 16 start_pc=0 v109 Imm(6) -> x0 terminator Return(v109) (exit_acc=v109) - block 18 start_pc=0 + block 17 start_pc=0 v110 Imm(0) -> x0 terminator Return(v110) (exit_acc=v110) + block 18 start_pc=0 + terminator Jmp(b13) block 19 start_pc=0 - terminator Jmp(b6) + terminator Jmp(b7) block 20 start_pc=0 - terminator Jmp(b8) + terminator Jmp(b5) block 21 start_pc=0 - terminator Jmp(b14) + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/zero_sign_extension_32bit.ssa b/tests/snapshots/ssa/zero_sign_extension_32bit.ssa index d2fa6737b..0c642b373 100644 --- a/tests/snapshots/ssa/zero_sign_extension_32bit.ssa +++ b/tests/snapshots/ssa/zero_sign_extension_32bit.ssa @@ -62,51 +62,345 @@ fn ent_pc=0 n_params=1 variadic=false locals=6 ; --- SSA dump (ok=true) ent_pc=6 --- ; name=main fn ent_pc=6 n_params=0 variadic=false locals=31 - spill_count=0 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(-1) -> x3 - v2 Imm(0) -> x0 - v3 LoadLocal { off=-1, kind=I32 } -> x0 - v4 Imm(0) -> x0 + v1 Imm(-1) -> x0 + v2 Imm(0) -> x1 + v3 LoadLocal { off=-1, kind=I32 } -> x1 + v4 Imm(0) -> x1 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 v5 LoadLocal { off=-2, kind=I64 } -> x0 - v6 BinopI { op=eq, lhs=v1, rhs_imm=-1 } -> x0 - v7 BinopI { op=eq, lhs=v6, rhs_imm=0 } -> x0 - terminator Bz { cond=v7, target=b5, fall=b4 } (exit_acc=v7) + v6 Imm(1) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v7) block 2 start_pc=0 v16 Imm(0) -> x0 terminator Jmp(b3) (exit_acc=v16) block 3 start_pc=0 - terminator Jmp(b6) + v17 LoadLocal { off=-1, kind=I32 } -> x0 + v18 Imm(1) -> x0 + v19 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v19) block 4 start_pc=0 + v27 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v27) + block 5 start_pc=0 + v28 Imm(4294967295) -> x0 + v29 Imm(0) -> x1 + v30 LoadLocal { off=-3, kind=U32 } -> x1 + v31 Imm(0) -> x1 + terminator Jmp(b6) (exit_acc=v28) + block 6 start_pc=0 + v32 LoadLocal { off=-4, kind=I64 } -> x0 + v33 Imm(1) -> x0 + v34 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v34) + block 7 start_pc=0 + v43 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v43) + block 8 start_pc=0 + v44 LoadLocal { off=-3, kind=U32 } -> x0 + v45 Imm(1) -> x0 + v46 Imm(0) -> x0 + terminator Jmp(b9) (exit_acc=v46) + block 9 start_pc=0 + v55 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v55) + block 10 start_pc=0 + v56 Imm(-7) -> x0 + v57 Imm(0) -> x0 + v58 LoadLocal { off=-5, kind=I32 } -> x0 + v59 Imm(4294967289) -> x0 + v60 Imm(0) -> x1 + terminator Jmp(b11) (exit_acc=v59) + block 11 start_pc=0 + v61 Imm(4294967289) -> x0 + v62 Imm(1) -> x0 + v63 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v63) + block 12 start_pc=0 + v72 Imm(0) -> x0 + terminator Jmp(b13) (exit_acc=v72) + block 13 start_pc=0 + v73 Imm(4294967289) -> x0 + v74 Imm(-30064771072) -> x0 + v75 Imm(-7) -> x0 + v76 Imm(0) -> x1 + terminator Jmp(b14) (exit_acc=v75) + block 14 start_pc=0 + v77 LoadLocal { off=-7, kind=I32 } -> x0 + v78 Imm(1) -> x0 + v79 Imm(0) -> x0 + terminator Jmp(b15) (exit_acc=v79) + block 15 start_pc=0 + v88 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v88) + block 16 start_pc=0 + v89 LoadLocal { off=-5, kind=I32 } -> x0 + v90 Imm(4294967289) -> x0 + v91 Imm(0) -> x1 + terminator Jmp(b17) (exit_acc=v90) + block 17 start_pc=0 + v92 LoadLocal { off=-8, kind=I64 } -> x0 + v93 Imm(1) -> x0 + v94 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v94) + block 18 start_pc=0 + v103 Imm(0) -> x0 + terminator Jmp(b19) (exit_acc=v103) + block 19 start_pc=0 + v104 Imm(1000000) -> x0 + v105 Imm(0) -> x0 + v106 Imm(3000) -> x0 + v107 Imm(0) -> x0 + v108 LoadLocal { off=-9, kind=I32 } -> x0 + v109 LoadLocal { off=-10, kind=I32 } -> x0 + v110 Imm(3000000000) -> x0 + v111 Imm(-5561842185709551616) -> x0 + v112 Imm(-1294967296) -> x0 + v113 Imm(0) -> x1 + terminator Jmp(b20) (exit_acc=v112) + block 20 start_pc=0 + v114 LoadLocal { off=-11, kind=I32 } -> x0 + v115 Imm(1) -> x0 + v116 Imm(0) -> x0 + terminator Jmp(b21) (exit_acc=v116) + block 21 start_pc=0 + v125 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v125) + block 22 start_pc=0 + v126 LoadLocal { off=-11, kind=I32 } -> x0 + v127 Imm(1) -> x0 + v128 Imm(0) -> x0 + terminator Jmp(b23) (exit_acc=v128) + block 23 start_pc=0 + v137 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v137) + block 24 start_pc=0 + v138 Imm(65536) -> x0 + v139 Imm(0) -> x0 + v140 Imm(0) -> x0 + v141 LoadLocal { off=-12, kind=U32 } -> x0 + v142 LoadLocal { off=-13, kind=U32 } -> x0 + v143 Imm(4294967296) -> x0 + v144 Imm(0) -> x0 + v145 Imm(0) -> x1 + terminator Jmp(b25) (exit_acc=v144) + block 25 start_pc=0 + v146 Imm(0) -> x0 + v147 Imm(1) -> x0 + v148 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v148) + block 26 start_pc=0 + v157 Imm(0) -> x0 + terminator Jmp(b27) (exit_acc=v157) + block 27 start_pc=0 + v158 Imm(0) -> x0 + v159 Imm(1) -> x0 + v160 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v160) + block 28 start_pc=0 + v169 Imm(0) -> x0 + terminator Jmp(b29) (exit_acc=v169) + block 29 start_pc=0 + v170 Imm(2147483648) -> x0 + v171 Imm(0) -> x0 + v172 LoadLocal { off=-15, kind=U32 } -> x0 + v173 Imm(1073741824) -> x0 + v174 Imm(0) -> x1 + terminator Jmp(b30) (exit_acc=v173) + block 30 start_pc=0 + v175 LoadLocal { off=-16, kind=I64 } -> x0 + v176 Imm(1) -> x0 + v177 Imm(0) -> x0 + terminator Jmp(b31) (exit_acc=v177) + block 31 start_pc=0 + v186 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v186) + block 32 start_pc=0 + v187 Imm(305419896) -> x0 + v188 Imm(0) -> x0 + v189 LoadLocal { off=-17, kind=U32 } -> x0 + v190 Imm(4886718336) -> x0 + v191 Imm(591751040) -> x0 + v192 Imm(0) -> x1 + terminator Jmp(b33) (exit_acc=v191) + block 33 start_pc=0 + v193 LoadLocal { off=-18, kind=I64 } -> x0 + v194 Imm(1) -> x0 + v195 Imm(0) -> x0 + terminator Jmp(b34) (exit_acc=v195) + block 34 start_pc=0 + v204 Imm(0) -> x0 + terminator Jmp(b35) (exit_acc=v204) + block 35 start_pc=0 + v205 Imm(0) -> x0 + v206 Imm(0) -> x0 + v207 LoadLocal { off=-19, kind=U32 } -> x0 + v208 Imm(-1) -> x0 + v209 Imm(4294967295) -> x0 + v210 Imm(0) -> x1 + terminator Jmp(b36) (exit_acc=v209) + block 36 start_pc=0 + v211 LoadLocal { off=-20, kind=I64 } -> x0 + v212 Imm(1) -> x0 + v213 Imm(0) -> x0 + terminator Jmp(b37) (exit_acc=v213) + block 37 start_pc=0 + v222 Imm(0) -> x0 + terminator Jmp(b38) (exit_acc=v222) + block 38 start_pc=0 + v223 ImmData(372) -> x7 + v224 CallExt { binding_idx=58, args=[v223], fp_arg_mask=0x0 } -> x3 + v225 Imm(0) -> x0 + terminator Jmp(b39) (exit_acc=v224) + block 39 start_pc=0 + v226 Extend { value=v224, kind=I32 } -> x0 + v227 BinopI { op=eq, lhs=v226, rhs_imm=-2147483647 } -> x0 + v228 BinopI { op=eq, lhs=v227, rhs_imm=0 } -> x0 + terminator Bz { cond=v228, target=b41, fall=b40 } (exit_acc=v228) + block 40 start_pc=0 + v229 ImmData(584) -> x0 + v230 Imm(40) -> x12 + v231 Store { addr=v229, disp=0, value=v230, kind=I32 } -> - + v232 Imm(2) -> x7 + v233 Call { target_pc=0, args=[v232], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v234 ImmData(384) -> x6 + v235 Imm(93) -> x2 + v236 CallExt { binding_idx=1, args=[v233, v234, v235, v230], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b41) (exit_acc=v236) + block 41 start_pc=0 + v237 Imm(0) -> x0 + terminator Jmp(b42) (exit_acc=v237) + block 42 start_pc=0 + v238 Extend { value=v224, kind=I32 } -> x0 + v239 BinopI { op=eq, lhs=v238, rhs_imm=-2147483647 } -> x0 + v240 BinopI { op=eq, lhs=v239, rhs_imm=0 } -> x0 + terminator Bz { cond=v240, target=b44, fall=b43 } (exit_acc=v240) + block 43 start_pc=0 + v241 ImmData(584) -> x0 + v242 Imm(41) -> x3 + v243 Store { addr=v241, disp=0, value=v242, kind=I32 } -> - + v244 Imm(2) -> x7 + v245 Call { target_pc=0, args=[v244], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v246 ImmData(406) -> x6 + v247 Imm(94) -> x2 + v248 CallExt { binding_idx=1, args=[v245, v246, v247, v242], fp_arg_mask=0x0 } -> x0 + terminator Jmp(b44) (exit_acc=v248) + block 44 start_pc=0 + v249 Imm(0) -> x0 + terminator Jmp(b45) (exit_acc=v249) + block 45 start_pc=0 + v250 Imm(-1) -> x0 + v251 Imm(0) -> x0 + v252 Imm(1) -> x0 + v253 Imm(0) -> x0 + v254 LoadLocal { off=-22, kind=I32 } -> x0 + v255 LoadLocal { off=-23, kind=U32 } -> x0 + v256 Imm(0) -> x0 + v257 Imm(0) -> x0 + v258 Imm(0) -> x1 + terminator Jmp(b46) (exit_acc=v257) + block 46 start_pc=0 + v259 LoadLocal { off=-24, kind=I64 } -> x0 + v260 Imm(1) -> x0 + v261 Imm(0) -> x0 + terminator Jmp(b47) (exit_acc=v261) + block 47 start_pc=0 + v270 Imm(0) -> x0 + terminator Jmp(b48) (exit_acc=v270) + block 48 start_pc=0 + v271 LoadLocal { off=-22, kind=I32 } -> x0 + v272 LoadLocal { off=-23, kind=U32 } -> x0 + v273 Imm(-2) -> x0 + v274 Imm(4294967294) -> x0 + v275 Imm(0) -> x1 + terminator Jmp(b49) (exit_acc=v274) + block 49 start_pc=0 + v276 LoadLocal { off=-25, kind=I64 } -> x0 + v277 Imm(1) -> x0 + v278 Imm(0) -> x0 + terminator Jmp(b50) (exit_acc=v278) + block 50 start_pc=0 + v287 Imm(0) -> x0 + terminator Jmp(b51) (exit_acc=v287) + block 51 start_pc=0 + v288 Imm(305419896) -> x3 + v289 Imm(0) -> x0 + terminator Jmp(b52) (exit_acc=v288) + block 52 start_pc=0 + v290 LoadLocal { off=-26, kind=I32 } -> x0 + v291 Imm(1) -> x0 + v292 Imm(0) -> x0 + terminator Jmp(b53) (exit_acc=v292) + block 53 start_pc=0 + v301 Imm(0) -> x0 + terminator Jmp(b54) (exit_acc=v301) + block 54 start_pc=0 + v302 LoadLocal { off=-26, kind=I32 } -> x0 + v303 Imm(0) -> x0 + terminator Jmp(b55) (exit_acc=v288) + block 55 start_pc=0 + v304 LoadLocal { off=-27, kind=I64 } -> x0 + v305 Imm(1) -> x0 + v306 Imm(0) -> x0 + terminator Jmp(b56) (exit_acc=v306) + block 56 start_pc=0 + v315 Imm(0) -> x0 + terminator Jmp(b57) (exit_acc=v315) + block 57 start_pc=0 + v316 Imm(-2000000000) -> x0 + v317 Imm(0) -> x1 + v318 LoadLocal { off=-26, kind=I32 } -> x1 + v319 Imm(0) -> x1 + terminator Jmp(b58) (exit_acc=v316) + block 58 start_pc=0 + v320 LoadLocal { off=-27, kind=I64 } -> x0 + v321 Imm(1) -> x0 + v322 Imm(0) -> x0 + terminator Jmp(b59) (exit_acc=v322) + block 59 start_pc=0 + v331 Imm(0) -> x0 + terminator Jmp(b60) (exit_acc=v331) + block 60 start_pc=0 + v332 LoadLocal { off=-26, kind=I32 } -> x0 + v333 Imm(1) -> x0 + v334 Imm(0) -> x0 + terminator Jmp(b61) (exit_acc=v334) + block 61 start_pc=0 + v343 Imm(0) -> x0 + terminator Jmp(b62) (exit_acc=v343) + block 62 start_pc=0 + v344 ImmData(584) -> x0 + v345 Load { addr=v344, disp=0, kind=I32 } -> x0 + v346 BinopI { op=eq, lhs=v345, rhs_imm=0 } -> x0 + terminator Bz { cond=v346, target=b64, fall=b63 } (exit_acc=v346) + block 63 start_pc=0 + v347 ImmData(560) -> x7 + v348 CallExt { binding_idx=0, args=[v347], fp_arg_mask=0x0 } -> x0 + v349 Imm(0) -> x0 + terminator Return(v349) (exit_acc=v349) + block 64 start_pc=0 + v350 ImmData(584) -> x0 + v351 Load { addr=v350, disp=0, kind=I32 } -> x0 + terminator Return(v351) (exit_acc=v351) + block 65 start_pc=0 + terminator Jmp(b3) + block 66 start_pc=0 v8 ImmData(584) -> x0 - v9 Imm(1) -> x12 + v9 Imm(1) -> x3 v10 Store { addr=v8, disp=0, value=v9, kind=I32 } -> - v11 Imm(2) -> x7 v12 Call { target_pc=0, args=[v11], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v13 ImmData(64) -> x6 v14 Imm(27) -> x2 v15 CallExt { binding_idx=1, args=[v12, v13, v14, v9], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b5) (exit_acc=v15) - block 5 start_pc=0 + terminator Jmp(b2) (exit_acc=v15) + block 67 start_pc=0 terminator Jmp(b2) - block 6 start_pc=0 - v17 LoadLocal { off=-1, kind=I32 } -> x0 - v18 BinopI { op=eq, lhs=v1, rhs_imm=-1 } -> x0 - v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x0 - terminator Bz { cond=v19, target=b10, fall=b9 } (exit_acc=v19) - block 7 start_pc=0 - v27 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v27) - block 8 start_pc=0 - v28 Imm(4294967295) -> x3 - v29 Imm(0) -> x0 - v30 LoadLocal { off=-3, kind=U32 } -> x0 - v31 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v28) - block 9 start_pc=0 + block 68 start_pc=0 v20 ImmData(584) -> x0 v21 Imm(2) -> x3 v22 Store { addr=v20, disp=0, value=v21, kind=I32 } -> - @@ -114,47 +408,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v24 ImmData(86) -> x6 v25 Imm(28) -> x2 v26 CallExt { binding_idx=1, args=[v23, v24, v25, v21], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b10) (exit_acc=v26) - block 10 start_pc=0 - terminator Jmp(b7) - block 11 start_pc=0 - v32 LoadLocal { off=-4, kind=I64 } -> x0 - v33 BinopI { op=eq, lhs=v28, rhs_imm=4294967295 } -> x0 - v34 BinopI { op=eq, lhs=v33, rhs_imm=0 } -> x0 - terminator Bz { cond=v34, target=b15, fall=b14 } (exit_acc=v34) - block 12 start_pc=0 - v43 Imm(0) -> x0 - terminator Jmp(b13) (exit_acc=v43) - block 13 start_pc=0 - terminator Jmp(b16) - block 14 start_pc=0 + terminator Jmp(b4) (exit_acc=v26) + block 69 start_pc=0 + terminator Jmp(b4) + block 70 start_pc=0 + terminator Jmp(b8) + block 71 start_pc=0 v35 ImmData(584) -> x0 - v36 Imm(3) -> x12 + v36 Imm(3) -> x3 v37 Store { addr=v35, disp=0, value=v36, kind=I32 } -> - v38 Imm(2) -> x7 v39 Call { target_pc=0, args=[v38], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v40 ImmData(108) -> x6 v41 Imm(32) -> x2 v42 CallExt { binding_idx=1, args=[v39, v40, v41, v36], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b15) (exit_acc=v42) - block 15 start_pc=0 - terminator Jmp(b12) - block 16 start_pc=0 - v44 LoadLocal { off=-3, kind=U32 } -> x0 - v45 BinopI { op=eq, lhs=v28, rhs_imm=4294967295 } -> x0 - v46 BinopI { op=eq, lhs=v45, rhs_imm=0 } -> x0 - terminator Bz { cond=v46, target=b20, fall=b19 } (exit_acc=v46) - block 17 start_pc=0 - v55 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v55) - block 18 start_pc=0 - v56 Imm(-7) -> x3 - v57 Imm(0) -> x0 - v58 LoadLocal { off=-5, kind=I32 } -> x0 - v59 BinopI { op=and, lhs=v56, rhs_imm=4294967295 } -> x12 - v60 Imm(0) -> x0 - terminator Jmp(b21) (exit_acc=v59) - block 19 start_pc=0 + terminator Jmp(b7) (exit_acc=v42) + block 72 start_pc=0 + terminator Jmp(b7) + block 73 start_pc=0 v47 ImmData(584) -> x0 v48 Imm(4) -> x3 v49 Store { addr=v47, disp=0, value=v48, kind=I32 } -> - @@ -163,81 +434,34 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v52 ImmData(130) -> x6 v53 Imm(33) -> x2 v54 CallExt { binding_idx=1, args=[v51, v52, v53, v48], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b20) (exit_acc=v54) - block 20 start_pc=0 - terminator Jmp(b17) - block 21 start_pc=0 - v61 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x0 - v62 BinopI { op=eq, lhs=v61, rhs_imm=4294967289 } -> x0 - v63 BinopI { op=eq, lhs=v62, rhs_imm=0 } -> x0 - terminator Bz { cond=v63, target=b25, fall=b24 } (exit_acc=v63) - block 22 start_pc=0 - v72 Imm(0) -> x0 - terminator Jmp(b23) (exit_acc=v72) - block 23 start_pc=0 - v73 BinopI { op=and, lhs=v59, rhs_imm=4294967295 } -> x0 - v74 BinopI { op=shl, lhs=v73, rhs_imm=32 } -> x1 - v75 Extend { value=v73, kind=I32 } -> x0 - v76 Imm(0) -> x1 - terminator Jmp(b26) (exit_acc=v75) - block 24 start_pc=0 + terminator Jmp(b9) (exit_acc=v54) + block 74 start_pc=0 + terminator Jmp(b9) + block 75 start_pc=0 v64 ImmData(584) -> x0 - v65 Imm(10) -> x13 + v65 Imm(10) -> x3 v66 Store { addr=v64, disp=0, value=v65, kind=I32 } -> - v67 Imm(2) -> x7 v68 Call { target_pc=0, args=[v67], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v69 ImmData(152) -> x6 v70 Imm(40) -> x2 v71 CallExt { binding_idx=1, args=[v68, v69, v70, v65], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b25) (exit_acc=v71) - block 25 start_pc=0 - terminator Jmp(b22) - block 26 start_pc=0 - v77 LoadLocal { off=-7, kind=I32 } -> x1 - v78 BinopI { op=eq, lhs=v75, rhs_imm=-7 } -> x0 - v79 BinopI { op=eq, lhs=v78, rhs_imm=0 } -> x0 - terminator Bz { cond=v79, target=b30, fall=b29 } (exit_acc=v79) - block 27 start_pc=0 - v88 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v88) - block 28 start_pc=0 - v89 LoadLocal { off=-5, kind=I32 } -> x0 - v90 BinopI { op=and, lhs=v56, rhs_imm=4294967295 } -> x0 - v91 Imm(0) -> x1 - terminator Jmp(b31) (exit_acc=v90) - block 29 start_pc=0 + terminator Jmp(b12) (exit_acc=v71) + block 76 start_pc=0 + terminator Jmp(b12) + block 77 start_pc=0 v80 ImmData(584) -> x0 - v81 Imm(11) -> x12 + v81 Imm(11) -> x3 v82 Store { addr=v80, disp=0, value=v81, kind=I32 } -> - v83 Imm(2) -> x7 v84 Call { target_pc=0, args=[v83], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v85 ImmData(174) -> x6 v86 Imm(42) -> x2 v87 CallExt { binding_idx=1, args=[v84, v85, v86, v81], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b30) (exit_acc=v87) - block 30 start_pc=0 - terminator Jmp(b27) - block 31 start_pc=0 - v92 LoadLocal { off=-8, kind=I64 } -> x1 - v93 BinopI { op=eq, lhs=v90, rhs_imm=4294967289 } -> x0 - v94 BinopI { op=eq, lhs=v93, rhs_imm=0 } -> x0 - terminator Bz { cond=v94, target=b35, fall=b34 } (exit_acc=v94) - block 32 start_pc=0 - v103 Imm(0) -> x0 - terminator Jmp(b33) (exit_acc=v103) - block 33 start_pc=0 - v104 Imm(1000000) -> x0 - v105 Imm(0) -> x1 - v106 Imm(3000) -> x1 - v107 Imm(0) -> x2 - v108 LoadLocal { off=-9, kind=I32 } -> x2 - v109 LoadLocal { off=-10, kind=I32 } -> x2 - v110 Binop { op=mul, lhs=v104, rhs=v106 } -> x0 - v111 BinopI { op=shl, lhs=v110, rhs_imm=32 } -> x1 - v112 Extend { value=v110, kind=I32 } -> x3 - v113 Imm(0) -> x0 - terminator Jmp(b36) (exit_acc=v112) - block 34 start_pc=0 + terminator Jmp(b15) (exit_acc=v87) + block 78 start_pc=0 + terminator Jmp(b15) + block 79 start_pc=0 v95 ImmData(584) -> x0 v96 Imm(12) -> x3 v97 Store { addr=v95, disp=0, value=v96, kind=I32 } -> - @@ -246,50 +470,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v100 ImmData(196) -> x6 v101 Imm(48) -> x2 v102 CallExt { binding_idx=1, args=[v99, v100, v101, v96], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b35) (exit_acc=v102) - block 35 start_pc=0 - terminator Jmp(b32) - block 36 start_pc=0 - v114 LoadLocal { off=-11, kind=I32 } -> x0 - v115 BinopI { op=eq, lhs=v112, rhs_imm=-1294967296 } -> x0 - v116 BinopI { op=eq, lhs=v115, rhs_imm=0 } -> x0 - terminator Bz { cond=v116, target=b40, fall=b39 } (exit_acc=v116) - block 37 start_pc=0 - v125 Imm(0) -> x0 - terminator Jmp(b38) (exit_acc=v125) - block 38 start_pc=0 - terminator Jmp(b41) - block 39 start_pc=0 + terminator Jmp(b18) (exit_acc=v102) + block 80 start_pc=0 + terminator Jmp(b18) + block 81 start_pc=0 + terminator Jmp(b22) + block 82 start_pc=0 v117 ImmData(584) -> x0 - v118 Imm(20) -> x12 + v118 Imm(20) -> x3 v119 Store { addr=v117, disp=0, value=v118, kind=I32 } -> - v120 Imm(2) -> x7 v121 Call { target_pc=0, args=[v120], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v122 ImmData(218) -> x6 v123 Imm(58) -> x2 v124 CallExt { binding_idx=1, args=[v121, v122, v123, v118], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b40) (exit_acc=v124) - block 40 start_pc=0 - terminator Jmp(b37) - block 41 start_pc=0 - v126 LoadLocal { off=-11, kind=I32 } -> x0 - v127 BinopI { op=eq, lhs=v112, rhs_imm=-1294967296 } -> x0 - v128 BinopI { op=eq, lhs=v127, rhs_imm=0 } -> x0 - terminator Bz { cond=v128, target=b45, fall=b44 } (exit_acc=v128) - block 42 start_pc=0 - v137 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v137) - block 43 start_pc=0 - v138 Imm(65536) -> x0 - v139 Imm(0) -> x1 - v140 Imm(0) -> x1 - v141 LoadLocal { off=-12, kind=U32 } -> x1 - v142 LoadLocal { off=-13, kind=U32 } -> x1 - v143 Binop { op=mul, lhs=v138, rhs=v138 } -> x0 - v144 BinopI { op=and, lhs=v143, rhs_imm=4294967295 } -> x3 - v145 Imm(0) -> x0 - terminator Jmp(b46) (exit_acc=v144) - block 44 start_pc=0 + terminator Jmp(b21) (exit_acc=v124) + block 83 start_pc=0 + terminator Jmp(b21) + block 84 start_pc=0 v129 ImmData(584) -> x0 v130 Imm(21) -> x3 v131 Store { addr=v129, disp=0, value=v130, kind=I32 } -> - @@ -298,47 +496,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v134 ImmData(240) -> x6 v135 Imm(59) -> x2 v136 CallExt { binding_idx=1, args=[v133, v134, v135, v130], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b45) (exit_acc=v136) - block 45 start_pc=0 - terminator Jmp(b42) - block 46 start_pc=0 - v146 BinopI { op=and, lhs=v144, rhs_imm=4294967295 } -> x0 - v147 BinopI { op=eq, lhs=v146, rhs_imm=0 } -> x0 - v148 BinopI { op=eq, lhs=v147, rhs_imm=0 } -> x0 - terminator Bz { cond=v148, target=b50, fall=b49 } (exit_acc=v148) - block 47 start_pc=0 - v157 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v157) - block 48 start_pc=0 - terminator Jmp(b51) - block 49 start_pc=0 + terminator Jmp(b23) (exit_acc=v136) + block 85 start_pc=0 + terminator Jmp(b23) + block 86 start_pc=0 + terminator Jmp(b27) + block 87 start_pc=0 v149 ImmData(584) -> x0 - v150 Imm(22) -> x12 + v150 Imm(22) -> x3 v151 Store { addr=v149, disp=0, value=v150, kind=I32 } -> - v152 Imm(2) -> x7 v153 Call { target_pc=0, args=[v152], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v154 ImmData(262) -> x6 v155 Imm(64) -> x2 v156 CallExt { binding_idx=1, args=[v153, v154, v155, v150], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b50) (exit_acc=v156) - block 50 start_pc=0 - terminator Jmp(b47) - block 51 start_pc=0 - v158 BinopI { op=and, lhs=v144, rhs_imm=4294967295 } -> x0 - v159 BinopI { op=eq, lhs=v158, rhs_imm=0 } -> x0 - v160 BinopI { op=eq, lhs=v159, rhs_imm=0 } -> x0 - terminator Bz { cond=v160, target=b55, fall=b54 } (exit_acc=v160) - block 52 start_pc=0 - v169 Imm(0) -> x0 - terminator Jmp(b53) (exit_acc=v169) - block 53 start_pc=0 - v170 Imm(2147483648) -> x0 - v171 Imm(0) -> x1 - v172 LoadLocal { off=-15, kind=U32 } -> x1 - v173 BinopI { op=shru, lhs=v170, rhs_imm=1 } -> x0 - v174 Imm(0) -> x1 - terminator Jmp(b56) (exit_acc=v173) - block 54 start_pc=0 + terminator Jmp(b26) (exit_acc=v156) + block 88 start_pc=0 + terminator Jmp(b26) + block 89 start_pc=0 v161 ImmData(584) -> x0 v162 Imm(23) -> x3 v163 Store { addr=v161, disp=0, value=v162, kind=I32 } -> - @@ -347,26 +522,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v166 ImmData(284) -> x6 v167 Imm(65) -> x2 v168 CallExt { binding_idx=1, args=[v165, v166, v167, v162], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b55) (exit_acc=v168) - block 55 start_pc=0 - terminator Jmp(b52) - block 56 start_pc=0 - v175 LoadLocal { off=-16, kind=I64 } -> x1 - v176 BinopI { op=eq, lhs=v173, rhs_imm=1073741824 } -> x0 - v177 BinopI { op=eq, lhs=v176, rhs_imm=0 } -> x0 - terminator Bz { cond=v177, target=b60, fall=b59 } (exit_acc=v177) - block 57 start_pc=0 - v186 Imm(0) -> x0 - terminator Jmp(b58) (exit_acc=v186) - block 58 start_pc=0 - v187 Imm(305419896) -> x0 - v188 Imm(0) -> x1 - v189 LoadLocal { off=-17, kind=U32 } -> x1 - v190 BinopI { op=shl, lhs=v187, rhs_imm=4 } -> x0 - v191 BinopI { op=and, lhs=v190, rhs_imm=4294967295 } -> x0 - v192 Imm(0) -> x1 - terminator Jmp(b61) (exit_acc=v191) - block 59 start_pc=0 + terminator Jmp(b28) (exit_acc=v168) + block 90 start_pc=0 + terminator Jmp(b28) + block 91 start_pc=0 v178 ImmData(584) -> x0 v179 Imm(30) -> x3 v180 Store { addr=v178, disp=0, value=v179, kind=I32 } -> - @@ -375,26 +534,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v183 ImmData(306) -> x6 v184 Imm(74) -> x2 v185 CallExt { binding_idx=1, args=[v182, v183, v184, v179], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b60) (exit_acc=v185) - block 60 start_pc=0 - terminator Jmp(b57) - block 61 start_pc=0 - v193 LoadLocal { off=-18, kind=I64 } -> x1 - v194 BinopI { op=eq, lhs=v191, rhs_imm=591751040 } -> x0 - v195 BinopI { op=eq, lhs=v194, rhs_imm=0 } -> x0 - terminator Bz { cond=v195, target=b65, fall=b64 } (exit_acc=v195) - block 62 start_pc=0 - v204 Imm(0) -> x0 - terminator Jmp(b63) (exit_acc=v204) - block 63 start_pc=0 - v205 Imm(0) -> x0 - v206 Imm(0) -> x1 - v207 LoadLocal { off=-19, kind=U32 } -> x1 - v208 BinopI { op=xor, lhs=v205, rhs_imm=-1 } -> x0 - v209 BinopI { op=and, lhs=v208, rhs_imm=4294967295 } -> x0 - v210 Imm(0) -> x1 - terminator Jmp(b66) (exit_acc=v209) - block 64 start_pc=0 + terminator Jmp(b31) (exit_acc=v185) + block 92 start_pc=0 + terminator Jmp(b31) + block 93 start_pc=0 v196 ImmData(584) -> x0 v197 Imm(31) -> x3 v198 Store { addr=v196, disp=0, value=v197, kind=I32 } -> - @@ -403,23 +546,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v201 ImmData(328) -> x6 v202 Imm(79) -> x2 v203 CallExt { binding_idx=1, args=[v200, v201, v202, v197], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b65) (exit_acc=v203) - block 65 start_pc=0 - terminator Jmp(b62) - block 66 start_pc=0 - v211 LoadLocal { off=-20, kind=I64 } -> x1 - v212 BinopI { op=eq, lhs=v209, rhs_imm=4294967295 } -> x0 - v213 BinopI { op=eq, lhs=v212, rhs_imm=0 } -> x0 - terminator Bz { cond=v213, target=b70, fall=b69 } (exit_acc=v213) - block 67 start_pc=0 - v222 Imm(0) -> x0 - terminator Jmp(b68) (exit_acc=v222) - block 68 start_pc=0 - v223 ImmData(372) -> x7 - v224 CallExt { binding_idx=58, args=[v223], fp_arg_mask=0x0 } -> x3 - v225 Imm(0) -> x0 - terminator Jmp(b71) (exit_acc=v224) - block 69 start_pc=0 + terminator Jmp(b34) (exit_acc=v203) + block 94 start_pc=0 + terminator Jmp(b34) + block 95 start_pc=0 v214 ImmData(584) -> x0 v215 Imm(32) -> x3 v216 Store { addr=v214, disp=0, value=v215, kind=I32 } -> - @@ -428,102 +558,28 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v219 ImmData(350) -> x6 v220 Imm(84) -> x2 v221 CallExt { binding_idx=1, args=[v218, v219, v220, v215], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b70) (exit_acc=v221) - block 70 start_pc=0 - terminator Jmp(b67) - block 71 start_pc=0 - v226 Extend { value=v224, kind=I32 } -> x0 - v227 BinopI { op=eq, lhs=v226, rhs_imm=-2147483647 } -> x0 - v228 BinopI { op=eq, lhs=v227, rhs_imm=0 } -> x0 - terminator Bz { cond=v228, target=b75, fall=b74 } (exit_acc=v228) - block 72 start_pc=0 - v237 Imm(0) -> x0 - terminator Jmp(b73) (exit_acc=v237) - block 73 start_pc=0 - terminator Jmp(b76) - block 74 start_pc=0 - v229 ImmData(584) -> x0 - v230 Imm(40) -> x12 - v231 Store { addr=v229, disp=0, value=v230, kind=I32 } -> - - v232 Imm(2) -> x7 - v233 Call { target_pc=0, args=[v232], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v234 ImmData(384) -> x6 - v235 Imm(93) -> x2 - v236 CallExt { binding_idx=1, args=[v233, v234, v235, v230], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b75) (exit_acc=v236) - block 75 start_pc=0 - terminator Jmp(b72) - block 76 start_pc=0 - v238 Extend { value=v224, kind=I32 } -> x0 - v239 BinopI { op=eq, lhs=v238, rhs_imm=-2147483647 } -> x0 - v240 BinopI { op=eq, lhs=v239, rhs_imm=0 } -> x0 - terminator Bz { cond=v240, target=b80, fall=b79 } (exit_acc=v240) - block 77 start_pc=0 - v249 Imm(0) -> x0 - terminator Jmp(b78) (exit_acc=v249) - block 78 start_pc=0 - v250 Imm(-1) -> x3 - v251 Imm(0) -> x0 - v252 Imm(1) -> x12 - v253 Imm(0) -> x0 - v254 LoadLocal { off=-22, kind=I32 } -> x0 - v255 LoadLocal { off=-23, kind=U32 } -> x0 - v256 Binop { op=add, lhs=v250, rhs=v252 } -> x0 - v257 BinopI { op=and, lhs=v256, rhs_imm=4294967295 } -> x0 - v258 Imm(0) -> x1 - terminator Jmp(b81) (exit_acc=v257) - block 79 start_pc=0 - v241 ImmData(584) -> x0 - v242 Imm(41) -> x3 - v243 Store { addr=v241, disp=0, value=v242, kind=I32 } -> - - v244 Imm(2) -> x7 - v245 Call { target_pc=0, args=[v244], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v246 ImmData(406) -> x6 - v247 Imm(94) -> x2 - v248 CallExt { binding_idx=1, args=[v245, v246, v247, v242], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b80) (exit_acc=v248) - block 80 start_pc=0 - terminator Jmp(b77) - block 81 start_pc=0 - v259 LoadLocal { off=-24, kind=I64 } -> x1 - v260 BinopI { op=eq, lhs=v257, rhs_imm=0 } -> x0 - v261 BinopI { op=eq, lhs=v260, rhs_imm=0 } -> x0 - terminator Bz { cond=v261, target=b85, fall=b84 } (exit_acc=v261) - block 82 start_pc=0 - v270 Imm(0) -> x0 - terminator Jmp(b83) (exit_acc=v270) - block 83 start_pc=0 - v271 LoadLocal { off=-22, kind=I32 } -> x0 - v272 LoadLocal { off=-23, kind=U32 } -> x0 - v273 Binop { op=sub, lhs=v250, rhs=v252 } -> x0 - v274 BinopI { op=and, lhs=v273, rhs_imm=4294967295 } -> x0 - v275 Imm(0) -> x1 - terminator Jmp(b86) (exit_acc=v274) - block 84 start_pc=0 + terminator Jmp(b37) (exit_acc=v221) + block 96 start_pc=0 + terminator Jmp(b37) + block 97 start_pc=0 + terminator Jmp(b42) + block 98 start_pc=0 + terminator Jmp(b41) + block 99 start_pc=0 + terminator Jmp(b44) + block 100 start_pc=0 v262 ImmData(584) -> x0 - v263 Imm(50) -> x13 + v263 Imm(50) -> x3 v264 Store { addr=v262, disp=0, value=v263, kind=I32 } -> - v265 Imm(2) -> x7 v266 Call { target_pc=0, args=[v265], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v267 ImmData(428) -> x6 v268 Imm(104) -> x2 v269 CallExt { binding_idx=1, args=[v266, v267, v268, v263], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b85) (exit_acc=v269) - block 85 start_pc=0 - terminator Jmp(b82) - block 86 start_pc=0 - v276 LoadLocal { off=-25, kind=I64 } -> x1 - v277 BinopI { op=eq, lhs=v274, rhs_imm=4294967294 } -> x0 - v278 BinopI { op=eq, lhs=v277, rhs_imm=0 } -> x0 - terminator Bz { cond=v278, target=b90, fall=b89 } (exit_acc=v278) - block 87 start_pc=0 - v287 Imm(0) -> x0 - terminator Jmp(b88) (exit_acc=v287) - block 88 start_pc=0 - v288 Imm(305419896) -> x3 - v289 Imm(0) -> x0 - terminator Jmp(b91) (exit_acc=v288) - block 89 start_pc=0 + terminator Jmp(b47) (exit_acc=v269) + block 101 start_pc=0 + terminator Jmp(b47) + block 102 start_pc=0 v279 ImmData(584) -> x0 v280 Imm(51) -> x3 v281 Store { addr=v279, disp=0, value=v280, kind=I32 } -> - @@ -532,22 +588,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v284 ImmData(450) -> x6 v285 Imm(108) -> x2 v286 CallExt { binding_idx=1, args=[v283, v284, v285, v280], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b90) (exit_acc=v286) - block 90 start_pc=0 - terminator Jmp(b87) - block 91 start_pc=0 - v290 LoadLocal { off=-26, kind=I32 } -> x0 - v291 BinopI { op=eq, lhs=v288, rhs_imm=305419896 } -> x0 - v292 BinopI { op=eq, lhs=v291, rhs_imm=0 } -> x0 - terminator Bz { cond=v292, target=b95, fall=b94 } (exit_acc=v292) - block 92 start_pc=0 - v301 Imm(0) -> x0 - terminator Jmp(b93) (exit_acc=v301) - block 93 start_pc=0 - v302 LoadLocal { off=-26, kind=I32 } -> x0 - v303 Imm(0) -> x0 - terminator Jmp(b96) (exit_acc=v288) - block 94 start_pc=0 + terminator Jmp(b50) (exit_acc=v286) + block 103 start_pc=0 + terminator Jmp(b50) + block 104 start_pc=0 v293 ImmData(584) -> x0 v294 Imm(60) -> x12 v295 Store { addr=v293, disp=0, value=v294, kind=I32 } -> - @@ -556,24 +600,10 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v298 ImmData(472) -> x6 v299 Imm(115) -> x2 v300 CallExt { binding_idx=1, args=[v297, v298, v299, v294], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b95) (exit_acc=v300) - block 95 start_pc=0 - terminator Jmp(b92) - block 96 start_pc=0 - v304 LoadLocal { off=-27, kind=I64 } -> x0 - v305 BinopI { op=eq, lhs=v288, rhs_imm=305419896 } -> x0 - v306 BinopI { op=eq, lhs=v305, rhs_imm=0 } -> x0 - terminator Bz { cond=v306, target=b100, fall=b99 } (exit_acc=v306) - block 97 start_pc=0 - v315 Imm(0) -> x0 - terminator Jmp(b98) (exit_acc=v315) - block 98 start_pc=0 - v316 Imm(-2000000000) -> x3 - v317 Imm(0) -> x0 - v318 LoadLocal { off=-26, kind=I32 } -> x0 - v319 Imm(0) -> x0 - terminator Jmp(b101) (exit_acc=v316) - block 99 start_pc=0 + terminator Jmp(b53) (exit_acc=v300) + block 105 start_pc=0 + terminator Jmp(b53) + block 106 start_pc=0 v307 ImmData(584) -> x0 v308 Imm(61) -> x3 v309 Store { addr=v307, disp=0, value=v308, kind=I32 } -> - @@ -582,45 +612,24 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v312 ImmData(494) -> x6 v313 Imm(117) -> x2 v314 CallExt { binding_idx=1, args=[v311, v312, v313, v308], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b100) (exit_acc=v314) - block 100 start_pc=0 - terminator Jmp(b97) - block 101 start_pc=0 - v320 LoadLocal { off=-27, kind=I64 } -> x0 - v321 BinopI { op=eq, lhs=v316, rhs_imm=-2000000000 } -> x0 - v322 BinopI { op=eq, lhs=v321, rhs_imm=0 } -> x0 - terminator Bz { cond=v322, target=b105, fall=b104 } (exit_acc=v322) - block 102 start_pc=0 - v331 Imm(0) -> x0 - terminator Jmp(b103) (exit_acc=v331) - block 103 start_pc=0 - terminator Jmp(b106) - block 104 start_pc=0 + terminator Jmp(b56) (exit_acc=v314) + block 107 start_pc=0 + terminator Jmp(b56) + block 108 start_pc=0 + terminator Jmp(b60) + block 109 start_pc=0 v323 ImmData(584) -> x0 - v324 Imm(62) -> x12 + v324 Imm(62) -> x3 v325 Store { addr=v323, disp=0, value=v324, kind=I32 } -> - v326 Imm(2) -> x7 v327 Call { target_pc=0, args=[v326], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v328 ImmData(516) -> x6 v329 Imm(122) -> x2 v330 CallExt { binding_idx=1, args=[v327, v328, v329, v324], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b105) (exit_acc=v330) - block 105 start_pc=0 - terminator Jmp(b102) - block 106 start_pc=0 - v332 LoadLocal { off=-26, kind=I32 } -> x0 - v333 BinopI { op=eq, lhs=v316, rhs_imm=-2000000000 } -> x0 - v334 BinopI { op=eq, lhs=v333, rhs_imm=0 } -> x0 - terminator Bz { cond=v334, target=b110, fall=b109 } (exit_acc=v334) - block 107 start_pc=0 - v343 Imm(0) -> x0 - terminator Jmp(b108) (exit_acc=v343) - block 108 start_pc=0 - v344 ImmData(584) -> x0 - v345 Load { addr=v344, disp=0, kind=I32 } -> x0 - v346 BinopI { op=eq, lhs=v345, rhs_imm=0 } -> x0 - terminator Bz { cond=v346, target=b112, fall=b111 } (exit_acc=v346) - block 109 start_pc=0 + terminator Jmp(b59) (exit_acc=v330) + block 110 start_pc=0 + terminator Jmp(b59) + block 111 start_pc=0 v335 ImmData(584) -> x0 v336 Imm(63) -> x3 v337 Store { addr=v335, disp=0, value=v336, kind=I32 } -> - @@ -629,18 +638,9 @@ fn ent_pc=6 n_params=0 variadic=false locals=31 v340 ImmData(538) -> x6 v341 Imm(123) -> x2 v342 CallExt { binding_idx=1, args=[v339, v340, v341, v336], fp_arg_mask=0x0 } -> x0 - terminator Jmp(b110) (exit_acc=v342) - block 110 start_pc=0 - terminator Jmp(b107) - block 111 start_pc=0 - v347 ImmData(560) -> x7 - v348 CallExt { binding_idx=0, args=[v347], fp_arg_mask=0x0 } -> x0 - v349 Imm(0) -> x0 - terminator Return(v349) (exit_acc=v349) + terminator Jmp(b61) (exit_acc=v342) block 112 start_pc=0 - v350 ImmData(584) -> x0 - v351 Load { addr=v350, disp=0, kind=I32 } -> x0 - terminator Return(v351) (exit_acc=v351) + terminator Jmp(b61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1