From 59ccf7f0d2dbdd3c1eedd822420eff77026e89d9 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 20:24:23 -0700 Subject: [PATCH 01/36] c5: keep float compound-assign targets on the StoreLocal fast path The RmwPlace::Slot exclusion of StoreKind::F32 dated from before the backends lowered fused F32 StoreLocal/LoadLocal; both do now, the SSA interpreter handles them, and the walker already narrows to single precision before every F32 store, so the slot promotes like the x = x op k form. Fixes #349 Co-Authored-By: Claude Fable 5 --- src/c5/ast/walk.rs | 32 +- src/c5/tests/jit.rs | 1 + src/c5/tests/native.rs | 1 + src/c5/tests/native_elf.rs | 1 + src/c5/tests/native_elf_x64.rs | 1 + src/c5/tests/native_pe_arm64.rs | 1 + src/c5/tests/native_pe_x64.rs | 1 + src/c5/tests/programs.rs | 8 + .../compound_assign_float_register_resident.c | 31 ++ ...assign_float_register_resident.aarch64.asm | 106 +++++ ...und_assign_float_register_resident.x64.asm | 129 +++++ .../asm/float_increment_decrement.aarch64.asm | 39 +- .../asm/float_increment_decrement.x64.asm | 33 +- .../asm/float_single_precision.aarch64.asm | 35 +- .../asm/float_single_precision.x64.asm | 27 +- ...two_d_float_array_partial_init.aarch64.asm | 69 ++- .../two_d_float_array_partial_init.x64.asm | 41 +- ...ompound_assign_float_register_resident.ssa | 155 ++++++ .../ssa/float_increment_decrement.ssa | 445 +++++++++--------- .../snapshots/ssa/float_single_precision.ssa | 58 +-- .../ssa/two_d_float_array_partial_init.ssa | 66 +-- 21 files changed, 826 insertions(+), 454 deletions(-) create mode 100644 tests/fixtures/c/compound_assign_float_register_resident.c create mode 100644 tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm create mode 100644 tests/snapshots/asm/compound_assign_float_register_resident.x64.asm create mode 100644 tests/snapshots/ssa/compound_assign_float_register_resident.ssa diff --git a/src/c5/ast/walk.rs b/src/c5/ast/walk.rs index 9e470cd89..0b2d39659 100644 --- a/src/c5/ast/walk.rs +++ b/src/c5/ast/walk.rs @@ -2993,7 +2993,7 @@ impl<'a> Walker<'a> { let load_kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lhs); - let place = self.rmw_place(b, *lhs, store_kind)?; + let place = self.rmw_place(b, *lhs)?; let old = place.load(b, load_kind, vol); // Constant-rhs short-circuit (mirror of the // `Expr::Binary` path): an integer-literal rhs @@ -3112,7 +3112,7 @@ impl<'a> Walker<'a> { let kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lvalue); - let place = self.rmw_place(b, *lvalue, store_kind)?; + let place = self.rmw_place(b, *lvalue)?; let old = place.load(b, kind, vol); let stepped = self.increment_value(b, old, *by, *ty); place.store(b, stepped, store_kind, vol); @@ -3139,7 +3139,7 @@ impl<'a> Walker<'a> { let kind = load_kind_for(*ty, self.target); let store_kind = store_kind_for(*ty, self.target); let vol = is_volatile_ty(*ty) || self.expr_is_volatile(*lvalue); - let place = self.rmw_place(b, *lvalue, store_kind)?; + let place = self.rmw_place(b, *lvalue)?; let old = place.load(b, kind, vol); let stepped = self.increment_value(b, old, *by, *ty); place.store(b, stepped, store_kind, vol); @@ -3508,18 +3508,15 @@ impl<'a> Walker<'a> { } /// Resolve where a read-modify-write operator targets its lvalue. A - /// non-thread-local `Token::Loc` Ident of integer-class storage width - /// keeps its frame slot so mem2reg can promote it; the float-stored - /// case (`StoreKind::F32`, which the fused `StoreLocal` does not - /// lower) and every non-local lvalue materialize an address through - /// `walk_expr_lvalue`. Mirrors the `Expr::Assign` local-target - /// shortcut so `i++` / `i += k` keep the counter register-resident, - /// not just `i = i + k`. + /// non-thread-local `Token::Loc` Ident keeps its frame slot so + /// mem2reg can promote it; every non-local lvalue materializes an + /// address through `walk_expr_lvalue`. Mirrors the `Expr::Assign` + /// local-target shortcut so `i++` / `i += k` keep the counter + /// register-resident, not just `i = i + k`. fn rmw_place( &mut self, b: &mut super::super::codegen::ssa::build::SsaBuilder, lvalue: ExprId, - store_kind: StoreKind, ) -> Result { // A bitfield member: compute the storage unit's address once so // the read and the write target the same unit (the object is @@ -3542,13 +3539,12 @@ impl<'a> Walker<'a> { }; return Ok(RmwPlace::Bitfield { addr, bf }); } - if !matches!(store_kind, StoreKind::F32) - && let Expr::Ident { - class, - val, - is_thread_local: false, - .. - } = self.ast.expr(lvalue) + if let Expr::Ident { + class, + val, + is_thread_local: false, + .. + } = self.ast.expr(lvalue) && *class == Token::Loc as i64 { return Ok(RmwPlace::Slot(*val)); diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index 487e119ed..b76455ece 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1447,6 +1447,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("libc_pread64_pwrite64.c", 0), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index decd95767..caf640afe 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -645,6 +645,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("libc_pread64_pwrite64.c", 0), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index fee4718aa..401c776b6 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -638,6 +638,7 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("fts_and_fd_set_headers.c", 0), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index 15407c8aa..dd1e449a3 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -590,6 +590,7 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("fts_and_fd_set_headers.c", 0), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index e003473ba..45ce3a8cd 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -869,6 +869,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("addr_of_intrinsic_math_float.c", 0), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index eb83de562..ef6a57b16 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -884,6 +884,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("global_init_paren_operand.c", 0), ("function_type_typedef_declaration.c", 0), ("float_increment_decrement.c", 0), + ("compound_assign_float_register_resident.c", 0), ("addr_of_libm_import.c", 0), ("addr_of_libc_strcmp.c", 0), ("addr_of_intrinsic_math_float.c", 0), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 2db15108f..0009847cf 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -378,6 +378,14 @@ fn float_increment_decrement() { assert_eq!(run_fixture("float_increment_decrement.c"), 0); } +#[test] +fn compound_assign_float_register_resident() { + // A float lvalue updated via `op=` / `++` / `--` (C99 6.5.16.2, + // 6.5.2.4, 6.5.3.1) stays promotable to an FP register, matching + // the `x = x op k` form. + assert_eq!(run_fixture("compound_assign_float_register_resident.c"), 0); +} + #[test] fn array_range_designator() { // GCC `[a ... b] = value` fills the inclusive range; covers constant diff --git a/tests/fixtures/c/compound_assign_float_register_resident.c b/tests/fixtures/c/compound_assign_float_register_resident.c new file mode 100644 index 000000000..de83d02f8 --- /dev/null +++ b/tests/fixtures/c/compound_assign_float_register_resident.c @@ -0,0 +1,31 @@ +// A float lvalue updated through compound assignment (C99 6.5.16.2) +// or `++` / `--` (6.5.2.4, 6.5.3.1) keeps its frame slot eligible for +// register promotion, the same as `x = x op k`: no address is taken, +// and the loop-carried value merges through an F32 phi. Asserted by +// return code. + +int main(void) { + float acc = 100.0f; + float step = 1.0f; + for (int i = 0; i < 8; i++) { + acc -= 2.0f; + acc += step; + step++; + } + // acc = 100 - 8*2 + (1+2+...+8); every value is exact in f32. + if (acc != 120.0f) return 1; + if (step != 9.0f) return 2; + + float post = 0.5f; + post--; + if (post != -0.5f) return 3; + + // Double rhs: the operation runs in double and the result narrows + // back to single precision before the store (C99 6.3.1.5). + float m = 3.0f; + m *= 4.0; + m /= 2.0f; + if (m != 6.0f) return 4; + + return 0; +} diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm new file mode 100644 index 000000000..ec09c765a --- /dev/null +++ b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm @@ -0,0 +1,106 @@ + +compound_assign_float_register_resident.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x30 + mov x0, #0x4059000000000000 // =4636737291354636288 + fmov d16, x0 + fcvt s1, d16 + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fmov d16, x0 + fcvt s0, d16 + mov x1, #0x0 // =0 + sxtw x0, w1 + cmp x0, #0x8 + b.ge + b + sxtw x0, w1 + add x1, x0, #0x1 + b + mov x0, #0x4000000000000000 // =4611686018427387904 + fcvt d1, s1 + fmov d17, x0 + fsub d1, d1, d17 + fcvt s1, d1 + fadd s1, s1, s0 + mov x0, #0x3ff0000000000000 // =4607182418800017408 + fcvt d0, s0 + fmov d17, x0 + fadd d0, d0, d17 + fcvt s0, d0 + b + mov x0, #0x405e000000000000 // =4638144666238189568 + fcvt d1, s1 + fmov d17, x0 + fcmp d1, d17 + cset x0, ne + cbz x0, + mov x0, #0x1 // =1 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4022000000000000 // =4621256167635550208 + fcvt d0, s0 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0x2 // =2 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x0 + fcvt s0, d16 + mov x1, #-0x4010000000000000 // =-4616189618054758400 + fcvt d0, s0 + fmov d17, x1 + fadd d0, d0, d17 + fcvt s0, d0 + fmov d16, x0 + fneg d1, d16 + fcvt d0, s0 + fcmp d0, d1 + cset x0, ne + cbz x0, + mov x0, #0x3 // =3 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4008000000000000 // =4613937818241073152 + fmov d16, x0 + fcvt s0, d16 + mov x0, #0x4010000000000000 // =4616189618054758400 + fcvt d0, s0 + fmov d17, x0 + fmul d0, d0, d17 + fcvt s0, d0 + mov x0, #0x4000000000000000 // =4611686018427387904 + fcvt d0, s0 + fmov d17, x0 + fdiv d0, d0, d17 + fcvt s0, d0 + mov x0, #0x4018000000000000 // =4618441417868443648 + fcvt d0, s0 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0x4 // =4 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x30 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm new file mode 100644 index 000000000..8c4ce195f --- /dev/null +++ b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm @@ -0,0 +1,129 @@ + +compound_assign_float_register_resident.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x30, %rsp + movabsq $0x4059000000000000, %rax # imm = 0x4059000000000000 + movq %rax, %xmm14 + cvtsd2ss %xmm14, %xmm1 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movq %rax, %xmm14 + cvtsd2ss %xmm14, %xmm0 + xorq %rcx, %rcx + movslq %ecx, %rax + cmpq $0x8, %rax + jge + jmp + movslq %ecx, %rax + leaq 0x1(%rax), %rcx + jmp + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + subsd %xmm15, %xmm1 + cvtsd2ss %xmm1, %xmm1 + addss %xmm0, %xmm1 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + addsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + jmp + movabsq $0x405e000000000000, %rax # imm = 0x405E000000000000 + cvtss2sd %xmm1, %xmm1 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm1 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x30, %rsp + popq %rbp + retq + movabsq $0x4022000000000000, %rax # imm = 0x4022000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x2, %eax + addq $0x30, %rsp + popq %rbp + retq + movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movq %rax, %xmm14 + cvtsd2ss %xmm14, %xmm0 + movabsq $-0x4010000000000000, %rcx # imm = 0xBFF0000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rcx, %xmm15 + addsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movq %rax, %xmm1 + movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + cvtss2sd %xmm0, %xmm0 + ucomisd %xmm1, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x3, %eax + addq $0x30, %rsp + popq %rbp + retq + movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movq %rax, %xmm14 + cvtsd2ss %xmm14, %xmm0 + movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + mulsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + divsd %xmm15, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 + cvtss2sd %xmm0, %xmm0 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x4, %eax + addq $0x30, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x30, %rsp + popq %rbp + retq diff --git a/tests/snapshots/asm/float_increment_decrement.aarch64.asm b/tests/snapshots/asm/float_increment_decrement.aarch64.asm index 10bb7e4dd..0979be229 100644 --- a/tests/snapshots/asm/float_increment_decrement.aarch64.asm +++ b/tests/snapshots/asm/float_increment_decrement.aarch64.asm @@ -16,25 +16,18 @@ Disassembly of section .text: mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d16, x0 fcvt s0, d16 - sub x17, x29, #0x8 - str s0, [x17] - sub x1, x29, #0x8 - ldr s0, [x1] - mov x2, #0x3ff0000000000000 // =4607182418800017408 + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d1, s0 - fmov d17, x2 + fmov d17, x1 fadd d1, d1, d17 fcvt s1, d1 - str s1, [x1] fcvt d0, s0 fmov d17, x0 fcmp d0, d17 cset x1, ne cbnz x1, - sub x16, x29, #0x8 - ldr s0, [x16] mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 + fcvt d0, s1 fmov d17, x0 fcmp d0, d17 cset x1, ne @@ -46,24 +39,17 @@ Disassembly of section .text: mov x0, #0x3ff8000000000000 // =4609434218613702656 fmov d16, x0 fcvt s0, d16 - sub x17, x29, #0x18 - str s0, [x17] - sub x0, x29, #0x18 - ldr s0, [x0] - mov x1, #0x3ff0000000000000 // =4607182418800017408 + mov x0, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x1 + fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x0] mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 + fcvt d1, s0 fmov d17, x0 - fcmp d0, d17 + fcmp d1, d17 cset x1, ne cbnz x1, - sub x16, x29, #0x18 - ldr s0, [x16] mov x0, #0x4004000000000000 // =4612811918334230528 fcvt d0, s0 fmov d17, x0 @@ -264,18 +250,11 @@ Disassembly of section .text: mov x0, #0x4170000000000000 // =4715268809856909312 fmov d16, x0 fcvt s0, d16 - sub x17, x29, #0x80 - str s0, [x17] - sub x1, x29, #0x80 - ldr s0, [x1] - mov x2, #0x3ff0000000000000 // =4607182418800017408 + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x2 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] - sub x16, x29, #0x80 - ldr s0, [x16] fcvt d0, s0 fmov d17, x0 fcmp d0, d17 diff --git a/tests/snapshots/asm/float_increment_decrement.x64.asm b/tests/snapshots/asm/float_increment_decrement.x64.asm index e3d4a4920..674287f30 100644 --- a/tests/snapshots/asm/float_increment_decrement.x64.asm +++ b/tests/snapshots/asm/float_increment_decrement.x64.asm @@ -17,15 +17,11 @@ Disassembly of section .text: movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 movq %rax, %xmm14 cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x8(%rbp,%riz) - leaq -0x8(%rbp), %rcx - movss (%rcx,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm1 - movq %rdx, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm1 cvtsd2ss %xmm1, %xmm1 - movss %xmm1, (%rcx,%riz) cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 @@ -36,9 +32,8 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movss -0x8(%rbp,%riz), %xmm0 movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm1, %xmm0 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 setne %cl @@ -55,19 +50,15 @@ Disassembly of section .text: movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 movq %rax, %xmm14 cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x18(%rbp,%riz) - leaq -0x18(%rbp), %rax - movss (%rax,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rcx, %xmm15 + movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rax,%riz) movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm0, %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomisd %xmm15, %xmm1 setne %cl movzbq %cl, %rcx setp %r10b @@ -75,7 +66,6 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movss -0x18(%rbp,%riz), %xmm0 movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 @@ -319,16 +309,11 @@ Disassembly of section .text: movabsq $0x4170000000000000, %rax # imm = 0x4170000000000000 movq %rax, %xmm14 cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x80(%rbp,%riz) - leaq -0x80(%rbp), %rcx - movss (%rcx,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rdx, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) - movss -0x80(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 diff --git a/tests/snapshots/asm/float_single_precision.aarch64.asm b/tests/snapshots/asm/float_single_precision.aarch64.asm index 67741d87f..d88dbd2b9 100644 --- a/tests/snapshots/asm/float_single_precision.aarch64.asm +++ b/tests/snapshots/asm/float_single_precision.aarch64.asm @@ -59,8 +59,6 @@ Disassembly of section .text: mov x1, #0x0 // =0 fmov d16, x1 fcvt s0, d16 - sub x17, x29, #0x8 - str s0, [x17] sxtw x0, w1 cmp x0, #0xa b.ge @@ -68,48 +66,41 @@ Disassembly of section .text: sxtw x0, w1 add x1, x0, #0x1 b - sub x0, x29, #0x8 - ldr s0, [x0] - mov x2, #0x999a // =39322 - movk x2, #0x9999, lsl #16 - movk x2, #0x9999, lsl #32 - movk x2, #0x3fb9, lsl #48 + mov x0, #0x999a // =39322 + movk x0, #0x9999, lsl #16 + movk x0, #0x9999, lsl #32 + movk x0, #0x3fb9, lsl #48 fcvt d0, s0 - fmov d17, x2 + fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x0] b mov x0, #0xf29b // =62107 movk x0, #0x1ad7, lsl #16 movk x0, #0x3ff0, lsl #48 fmov d16, x0 - fcvt s0, d16 - sub x16, x29, #0x8 - ldr s1, [x16] - fsub s1, s1, s0 + fcvt s1, d16 + fsub s2, s0, s1 mov x0, #0x0 // =0 - scvtf d0, x0 - fcvt s0, d0 - fcmp s1, s0 + scvtf d1, x0 + fcvt s1, d1 + fcmp s2, s1 cset x0, mi cbz x0, - fneg s1, s1 + fneg s2, s2 mov x0, #0xed8d // =60813 movk x0, #0xa0b5, lsl #16 movk x0, #0xc6f7, lsl #32 movk x0, #0x3eb0, lsl #48 - fcvt d0, s1 + fcvt d1, s2 fmov d17, x0 - fcmp d0, d17 + fcmp d1, d17 cset x0, gt cbz x0, mov x0, #0x2 // =2 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr s0, [x16] mov x0, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 fmov d17, x0 diff --git a/tests/snapshots/asm/float_single_precision.x64.asm b/tests/snapshots/asm/float_single_precision.x64.asm index 1c5e572d9..c7f3f4e9a 100644 --- a/tests/snapshots/asm/float_single_precision.x64.asm +++ b/tests/snapshots/asm/float_single_precision.x64.asm @@ -65,7 +65,6 @@ Disassembly of section .text: xorq %rcx, %rcx movq %rcx, %xmm14 cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x8(%rbp,%riz) movslq %ecx, %rax cmpq $0xa, %rax jge @@ -73,24 +72,21 @@ Disassembly of section .text: movslq %ecx, %rax leaq 0x1(%rax), %rcx jmp - leaq -0x8(%rbp), %rax - movss (%rax,%riz), %xmm0 - movabsq $0x3fb999999999999a, %rdx # imm = 0x3FB999999999999A + movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A cvtss2sd %xmm0, %xmm0 - movq %rdx, %xmm15 + movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rax,%riz) jmp movabsq $0x3ff000001ad7f29b, %rax # imm = 0x3FF000001AD7F29B movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss -0x8(%rbp,%riz), %xmm1 - subss %xmm0, %xmm1 + cvtsd2ss %xmm14, %xmm1 + movapd %xmm0, %xmm2 + subss %xmm1, %xmm2 xorq %rax, %rax - cvtsi2sd %rax, %xmm0 - cvtsd2ss %xmm0, %xmm0 - ucomiss %xmm0, %xmm1 + cvtsi2sd %rax, %xmm1 + cvtsd2ss %xmm1, %xmm1 + ucomiss %xmm1, %xmm2 setb %al movzbq %al, %rax setnp %r10b @@ -100,11 +96,11 @@ Disassembly of section .text: je movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 + xorpd %xmm15, %xmm2 movabsq $0x3eb0c6f7a0b5ed8d, %rax # imm = 0x3EB0C6F7A0B5ED8D - cvtss2sd %xmm1, %xmm0 + cvtss2sd %xmm2, %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomisd %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -113,7 +109,6 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movss -0x8(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm index 2291d318b..0a801748f 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm @@ -62,10 +62,11 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x60 - str x20, [sp] - str x21, [sp, #0x8] - str x19, [sp, #0x10] + sub sp, sp, #0x70 + str d8, [sp] + str x20, [sp, #0x10] + str x21, [sp, #0x18] + str x19, [sp, #0x20] mov x20, #0x0 // =0 sxtw x0, w20 cmp x0, #0xc @@ -78,9 +79,7 @@ Disassembly of section .text: b mov x1, #0x0 // =0 fmov d16, x1 - fcvt s0, d16 - sub x17, x29, #0x18 - str s0, [x17] + fcvt s8, d16 b sxtw x0, w21 cmp x0, #0x4 @@ -131,10 +130,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 + ldr x20, [sp, #0x10] + ldr x21, [sp, #0x18] + ldr d8, [sp] + ldr x19, [sp, #0x20] + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret b @@ -145,25 +145,20 @@ Disassembly of section .text: sxtw x0, w1 add x1, x0, #0x1 b - sub x0, x29, #0x18 + adrp x0, + add x0, x0, + sxtw x2, w1 + lsl x2, x2, #4 + add x0, x0, x2 ldr s0, [x0] - adrp x2, - add x2, x2, - sxtw x3, w1 - lsl x3, x3, #4 - add x2, x2, x3 - ldr s1, [x2] - ldr s2, [x2, #0x4] - fadd s1, s1, s2 - ldr s2, [x2, #0x8] - fadd s1, s1, s2 + ldr s1, [x0, #0x4] + fadd s0, s0, s1 + ldr s1, [x0, #0x8] fadd s0, s0, s1 - str s0, [x0] + fadd s8, s8, s0 b - sub x16, x29, #0x18 - ldr s0, [x16] mov x0, #0x0 // =0 - fcvt d0, s0 + fcvt d0, s8 fmov d17, x0 fcmp d0, d17 cset x0, ne @@ -173,22 +168,22 @@ Disassembly of section .text: bl adrp x1, add x1, x1, - sub x16, x29, #0x18 - ldr s0, [x16] - fcvt d0, s0 + fcvt d0, s8 bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 + ldr x20, [sp, #0x10] + ldr x21, [sp, #0x18] + ldr d8, [sp] + ldr x19, [sp, #0x20] + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp] - ldr x21, [sp, #0x8] - ldr x19, [sp, #0x10] - add sp, sp, #0x60 + ldr x20, [sp, #0x10] + ldr x21, [sp, #0x18] + ldr d8, [sp] + ldr x19, [sp, #0x20] + add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm index e92d89514..b30ea8024 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm @@ -56,7 +56,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x60, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rbx, %rbx @@ -71,8 +71,8 @@ Disassembly of section .text: jmp xorq %rcx, %rcx movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x18(%rbp,%riz) + cvtsd2ss %xmm14, %xmm14 + movsd %xmm14, 0x18(%rsp) jmp movslq %r12d, %rax cmpq $0x4, %rax @@ -129,7 +129,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x50, %rsp + addq $0x60, %rsp popq %rbp retq jmp @@ -140,23 +140,22 @@ Disassembly of section .text: movslq %ecx, %rax leaq 0x1(%rax), %rcx jmp - leaq -0x18(%rbp), %rax + leaq , %rax + movslq %ecx, %rdx + shlq $0x4, %rdx + addq %rdx, %rax movss (%rax,%riz), %xmm0 - leaq , %rdx - movslq %ecx, %rsi - shlq $0x4, %rsi - addq %rsi, %rdx - movss (%rdx,%riz), %xmm1 - movss 0x4(%rdx,%riz), %xmm2 - addss %xmm2, %xmm1 - movss 0x8(%rdx,%riz), %xmm2 - addss %xmm2, %xmm1 + movss 0x4(%rax,%riz), %xmm1 addss %xmm1, %xmm0 - movss %xmm0, (%rax,%riz) + movss 0x8(%rax,%riz), %xmm1 + addss %xmm1, %xmm0 + movsd 0x18(%rsp), %xmm14 + addss %xmm0, %xmm14 + movsd %xmm14, 0x18(%rsp) jmp - movss -0x18(%rbp,%riz), %xmm0 xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 + movsd 0x18(%rsp), %xmm14 + cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 setne %al @@ -171,20 +170,20 @@ Disassembly of section .text: callq movq %rax, %rdi leaq , %rsi - movss -0x18(%rbp,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 + movsd 0x18(%rsp), %xmm14 + cvtss2sd %xmm14, %xmm0 movb $0x1, %al callq movslq %eax, %rax movq %rbx, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x50, %rsp + addq $0x60, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x50, %rsp + addq $0x60, %rsp popq %rbp retq diff --git a/tests/snapshots/ssa/compound_assign_float_register_resident.ssa b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa new file mode 100644 index 000000000..3df1a0c72 --- /dev/null +++ b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa @@ -0,0 +1,155 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(4636737291354636288) -> x0 + v2 FpCast { kind=F64ToF32, value=v1 } -> d1 [f32] + v3 Imm(0) -> x0 + v4 Imm(4607182418800017408) -> x0 + v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] + v6 Imm(0) -> x0 + v7 Imm(0) -> x1 + v8 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v7) + block 1 start_pc=0 + v9 Phi { incoming=[b0:v7, b2:v15], kind=I64 } -> x1 + v10 Phi { incoming=[b0:v5, b2:v31], kind=F32 } -> d0 [f32] + v11 Phi { incoming=[b0:v2, b2:v25], kind=F32 } -> d1 [f32] + v12 Extend { value=v9, kind=I32 } -> x0 + v13 BinopI { op=lt, lhs=v12, rhs_imm=8 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + block 2 start_pc=0 + v14 Extend { value=v9, kind=I32 } -> x0 + v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v15) + block 3 start_pc=0 + v17 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v18 Imm(4611686018427387904) -> x0 + v19 FpCast { kind=F32ToF64, value=v11 } -> d1 + v20 Binop { op=fsub, lhs=v19, rhs=v18 } -> d1 + v21 FpCast { kind=F64ToF32, value=v20 } -> d1 [f32] + v22 Imm(0) -> x0 + v23 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v24 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v25 Binop { op=fadd, lhs=v21, rhs=v10 } -> d1 [f32] + v26 Imm(0) -> x0 + v27 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v28 Imm(4607182418800017408) -> x0 + v29 FpCast { kind=F32ToF64, value=v10 } -> d0 + v30 Binop { op=fadd, lhs=v29, rhs=v28 } -> d0 + v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] + v32 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v31) + block 4 start_pc=0 + v33 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v34 Imm(4638144666238189568) -> x0 + v35 FpCast { kind=F32ToF64, value=v11 } -> d1 + v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 + terminator Bz { cond=v36, target=b6, fall=b5 } (exit_acc=v36) + block 5 start_pc=0 + v37 Imm(1) -> x0 + terminator Return(v37) (exit_acc=v37) + block 6 start_pc=0 + v38 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v39 Imm(4621256167635550208) -> x0 + v40 FpCast { kind=F32ToF64, value=v10 } -> d0 + v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) + block 7 start_pc=0 + v42 Imm(2) -> x0 + terminator Return(v42) (exit_acc=v42) + block 8 start_pc=0 + v43 Imm(4602678819172646912) -> x0 + v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] + v45 Imm(0) -> x1 + v46 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v47 Imm(-4616189618054758400) -> x1 + v48 FpCast { kind=F32ToF64, value=v44 } -> d0 + v49 Binop { op=fadd, lhs=v48, rhs=v47 } -> d0 + v50 FpCast { kind=F64ToF32, value=v49 } -> d0 [f32] + v51 Imm(0) -> x1 + v52 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v53 Fneg(v43) -> d1 + v54 FpCast { kind=F32ToF64, value=v50 } -> d0 + v55 Binop { op=fne, lhs=v54, rhs=v53 } -> x0 + terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) + block 9 start_pc=0 + v56 Imm(3) -> x0 + terminator Return(v56) (exit_acc=v56) + block 10 start_pc=0 + v57 Imm(4613937818241073152) -> x0 + v58 FpCast { kind=F64ToF32, value=v57 } -> d0 [f32] + v59 Imm(0) -> x0 + v60 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v61 Imm(4616189618054758400) -> x0 + v62 FpCast { kind=F32ToF64, value=v58 } -> d0 + v63 Binop { op=fmul, lhs=v62, rhs=v61 } -> d0 + v64 FpCast { kind=F64ToF32, value=v63 } -> d0 [f32] + v65 Imm(0) -> x0 + v66 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v67 Imm(4611686018427387904) -> x0 + v68 FpCast { kind=F32ToF64, value=v64 } -> d0 + v69 Binop { op=fdiv, lhs=v68, rhs=v67 } -> d0 + v70 FpCast { kind=F64ToF32, value=v69 } -> d0 [f32] + v71 Imm(0) -> x0 + v72 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v73 Imm(4618441417868443648) -> x0 + v74 FpCast { kind=F32ToF64, value=v70 } -> d0 + v75 Binop { op=fne, lhs=v74, rhs=v73 } -> x0 + terminator Bz { cond=v75, target=b12, fall=b11 } (exit_acc=v75) + block 11 start_pc=0 + v76 Imm(4) -> x0 + terminator Return(v76) (exit_acc=v76) + block 12 start_pc=0 + v77 Imm(0) -> x0 + terminator Return(v77) (exit_acc=v77) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_increment_decrement.ssa b/tests/snapshots/ssa/float_increment_decrement.ssa index 971b50493..2991c24fb 100644 --- a/tests/snapshots/ssa/float_increment_decrement.ssa +++ b/tests/snapshots/ssa/float_increment_decrement.ssa @@ -6,260 +6,257 @@ fn ent_pc=0 n_params=0 variadic=false locals=22 v0 AllocaInit(0) -> - v1 Imm(4609434218613702656) -> x0 v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 StoreLocal { off=-1, value=v2, kind=F32 } -> - - v4 LocalAddr(-1) -> x1 - v5 Load { addr=v4, disp=0, kind=F32 } -> d0 [f32] - v6 Imm(4607182418800017408) -> x2 - v7 FpCast { kind=F32ToF64, value=v5 } -> d1 - v8 Binop { op=fadd, lhs=v7, rhs=v6 } -> d1 - v9 FpCast { kind=F64ToF32, value=v8 } -> d1 [f32] - v10 Store { addr=v4, disp=0, value=v9, kind=F32 } -> - - v11 Imm(0) -> x1 - v12 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v13 FpCast { kind=F32ToF64, value=v5 } -> d0 - v14 Binop { op=fne, lhs=v13, rhs=v1 } -> x1 - v15 Imm(0) -> x0 - terminator Bnz { cond=v14, target=b31, fall=b1 } (exit_acc=v14) + v3 Imm(0) -> x1 + v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v5 Imm(4607182418800017408) -> x1 + v6 FpCast { kind=F32ToF64, value=v2 } -> d1 + v7 Binop { op=fadd, lhs=v6, rhs=v5 } -> d1 + v8 FpCast { kind=F64ToF32, value=v7 } -> d1 [f32] + v9 Imm(0) -> x1 + v10 Imm(0) -> x1 + v11 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v12 FpCast { kind=F32ToF64, value=v2 } -> d0 + v13 Binop { op=fne, lhs=v12, rhs=v1 } -> x1 + v14 Imm(0) -> x0 + terminator Bnz { cond=v13, target=b31, fall=b1 } (exit_acc=v13) block 1 start_pc=0 - v16 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v17 Imm(4612811918334230528) -> x0 - v18 FpCast { kind=F32ToF64, value=v16 } -> d0 - v19 Binop { op=fne, lhs=v18, rhs=v17 } -> x1 - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v15 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v16 Imm(4612811918334230528) -> x0 + v17 FpCast { kind=F32ToF64, value=v8 } -> d0 + v18 Binop { op=fne, lhs=v17, rhs=v16 } -> x1 + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v21 Phi { incoming=[b31:v14, b1:v19], kind=I64 } -> x1 - v22 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) + v20 Phi { incoming=[b31:v13, b1:v18], kind=I64 } -> x1 + v21 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) block 3 start_pc=0 - v23 Imm(1) -> x0 - terminator Return(v23) (exit_acc=v23) + v22 Imm(1) -> x0 + terminator Return(v22) (exit_acc=v22) block 4 start_pc=0 - v24 Imm(4609434218613702656) -> x0 - v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] - v26 StoreLocal { off=-3, value=v25, kind=F32 } -> - - v27 LocalAddr(-3) -> x0 - v28 Load { addr=v27, disp=0, kind=F32 } -> d0 [f32] - v29 Imm(4607182418800017408) -> x1 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fadd, lhs=v30, rhs=v29 } -> d0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d0 [f32] - v33 Store { addr=v27, disp=0, value=v32, kind=F32 } -> - - v34 Imm(0) -> x0 - v35 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v36 Imm(4612811918334230528) -> x0 - v37 FpCast { kind=F32ToF64, value=v32 } -> d0 - v38 Binop { op=fne, lhs=v37, rhs=v36 } -> x1 - v39 Imm(0) -> x0 - terminator Bnz { cond=v38, target=b32, fall=b5 } (exit_acc=v38) + v23 Imm(4609434218613702656) -> x0 + v24 FpCast { kind=F64ToF32, value=v23 } -> d0 [f32] + v25 Imm(0) -> x0 + v26 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v27 Imm(4607182418800017408) -> x0 + v28 FpCast { kind=F32ToF64, value=v24 } -> d0 + v29 Binop { op=fadd, lhs=v28, rhs=v27 } -> d0 + v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] + v31 Imm(0) -> x0 + v32 Imm(0) -> x0 + v33 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v34 Imm(4612811918334230528) -> x0 + v35 FpCast { kind=F32ToF64, value=v30 } -> d1 + v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x1 + v37 Imm(0) -> x0 + terminator Bnz { cond=v36, target=b32, fall=b5 } (exit_acc=v36) block 5 start_pc=0 - v40 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v41 Imm(4612811918334230528) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 - v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x1 - v44 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v43) + v38 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v39 Imm(4612811918334230528) -> x0 + v40 FpCast { kind=F32ToF64, value=v30 } -> d0 + v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x1 + v42 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v41) block 6 start_pc=0 - v45 Phi { incoming=[b32:v38, b5:v43], kind=I64 } -> x1 - v46 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) + v43 Phi { incoming=[b32:v36, b5:v41], kind=I64 } -> x1 + v44 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) block 7 start_pc=0 - v47 Imm(2) -> x0 - terminator Return(v47) (exit_acc=v47) + v45 Imm(2) -> x0 + terminator Return(v45) (exit_acc=v45) block 8 start_pc=0 - v48 Imm(4614500768194494464) -> x0 - v49 StoreLocal { off=-5, value=v48, kind=F64 } -> - - v50 LoadLocal { off=-5, kind=F64 } -> d0 - v51 Imm(-4616189618054758400) -> x1 - v52 Binop { op=fadd, lhs=v50, rhs=v51 } -> d1 - v53 StoreLocal { off=-5, value=v52, kind=F64 } -> - - v54 Imm(0) -> x1 - v55 LoadLocal { off=-6, kind=F64 } -> d1 - v56 Binop { op=fne, lhs=v50, rhs=v48 } -> x1 - v57 Imm(0) -> x0 - terminator Bnz { cond=v56, target=b33, fall=b9 } (exit_acc=v56) + v46 Imm(4614500768194494464) -> x0 + v47 StoreLocal { off=-5, value=v46, kind=F64 } -> - + v48 LoadLocal { off=-5, kind=F64 } -> d0 + v49 Imm(-4616189618054758400) -> x1 + v50 Binop { op=fadd, lhs=v48, rhs=v49 } -> d1 + v51 StoreLocal { off=-5, value=v50, kind=F64 } -> - + v52 Imm(0) -> x1 + v53 LoadLocal { off=-6, kind=F64 } -> d1 + v54 Binop { op=fne, lhs=v48, rhs=v46 } -> x1 + v55 Imm(0) -> x0 + terminator Bnz { cond=v54, target=b33, fall=b9 } (exit_acc=v54) block 9 start_pc=0 - v58 LoadLocal { off=-5, kind=F64 } -> d0 - v59 Imm(4612248968380809216) -> x0 - v60 Binop { op=fne, lhs=v58, rhs=v59 } -> x1 - v61 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v60) + v56 LoadLocal { off=-5, kind=F64 } -> d0 + v57 Imm(4612248968380809216) -> x0 + v58 Binop { op=fne, lhs=v56, rhs=v57 } -> x1 + v59 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v58) block 10 start_pc=0 - v62 Phi { incoming=[b33:v56, b9:v60], kind=I64 } -> x1 - v63 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v62, target=b12, fall=b11 } (exit_acc=v62) + v60 Phi { incoming=[b33:v54, b9:v58], kind=I64 } -> x1 + v61 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v60, target=b12, fall=b11 } (exit_acc=v60) block 11 start_pc=0 - v64 Imm(3) -> x0 - terminator Return(v64) (exit_acc=v64) + v62 Imm(3) -> x0 + terminator Return(v62) (exit_acc=v62) block 12 start_pc=0 - v65 Imm(4614500768194494464) -> x0 - v66 StoreLocal { off=-7, value=v65, kind=F64 } -> - - v67 LoadLocal { off=-7, kind=F64 } -> d0 - v68 Imm(-4616189618054758400) -> x0 - v69 Binop { op=fadd, lhs=v67, rhs=v68 } -> d0 - v70 StoreLocal { off=-7, value=v69, kind=F64 } -> - - v71 Imm(0) -> x0 - v72 LoadLocal { off=-8, kind=F64 } -> d1 - v73 Imm(4612248968380809216) -> x0 - v74 Binop { op=fne, lhs=v69, rhs=v73 } -> x1 - v75 Imm(0) -> x0 - terminator Bnz { cond=v74, target=b34, fall=b13 } (exit_acc=v74) + v63 Imm(4614500768194494464) -> x0 + v64 StoreLocal { off=-7, value=v63, kind=F64 } -> - + v65 LoadLocal { off=-7, kind=F64 } -> d0 + v66 Imm(-4616189618054758400) -> x0 + v67 Binop { op=fadd, lhs=v65, rhs=v66 } -> d0 + v68 StoreLocal { off=-7, value=v67, kind=F64 } -> - + v69 Imm(0) -> x0 + v70 LoadLocal { off=-8, kind=F64 } -> d1 + v71 Imm(4612248968380809216) -> x0 + v72 Binop { op=fne, lhs=v67, rhs=v71 } -> x1 + v73 Imm(0) -> x0 + terminator Bnz { cond=v72, target=b34, fall=b13 } (exit_acc=v72) block 13 start_pc=0 - v76 LoadLocal { off=-7, kind=F64 } -> d0 - v77 Imm(4612248968380809216) -> x0 - v78 Binop { op=fne, lhs=v76, rhs=v77 } -> x1 - v79 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v78) + v74 LoadLocal { off=-7, kind=F64 } -> d0 + v75 Imm(4612248968380809216) -> x0 + v76 Binop { op=fne, lhs=v74, rhs=v75 } -> x1 + v77 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v76) block 14 start_pc=0 - v80 Phi { incoming=[b34:v74, b13:v78], kind=I64 } -> x1 - v81 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v80, target=b16, fall=b15 } (exit_acc=v80) + v78 Phi { incoming=[b34:v72, b13:v76], kind=I64 } -> x1 + v79 LoadLocal { off=-20, kind=I64 } -> x0 + terminator Bz { cond=v78, target=b16, fall=b15 } (exit_acc=v78) block 15 start_pc=0 - v82 Imm(4) -> x0 - terminator Return(v82) (exit_acc=v82) + v80 Imm(4) -> x0 + terminator Return(v80) (exit_acc=v80) block 16 start_pc=0 - v83 Imm(4607182418800017408) -> x0 - v84 FpCast { kind=F64ToF32, value=v83 } -> d0 [f32] - v85 StoreLocal { off=-9, value=v84, kind=F32 } -> - - v86 LocalAddr(-9) -> x1 - v87 Imm(0) -> x2 - v88 LoadLocal { off=-10, kind=I64 } -> x2 - v89 Load { addr=v86, disp=0, kind=F32 } -> d0 [f32] - v90 FpCast { kind=F32ToF64, value=v89 } -> d0 - v91 Binop { op=fadd, lhs=v90, rhs=v83 } -> d0 - v92 FpCast { kind=F64ToF32, value=v91 } -> d0 [f32] - v93 Store { addr=v86, disp=0, value=v92, kind=F32 } -> - - v94 LoadLocal { off=-10, kind=I64 } -> x2 - v95 Load { addr=v86, disp=0, kind=F32 } -> d0 [f32] - v96 FpCast { kind=F32ToF64, value=v95 } -> d0 - v97 Binop { op=fadd, lhs=v96, rhs=v83 } -> d0 - v98 FpCast { kind=F64ToF32, value=v97 } -> d0 [f32] - v99 Store { addr=v86, disp=0, value=v98, kind=F32 } -> - - v100 LoadLocal { off=-9, kind=F32 } -> d0 [f32] - v101 Imm(4613937818241073152) -> x0 - v102 FpCast { kind=F32ToF64, value=v100 } -> d0 - v103 Binop { op=fne, lhs=v102, rhs=v101 } -> x0 - terminator Bz { cond=v103, target=b18, fall=b17 } (exit_acc=v103) + v81 Imm(4607182418800017408) -> x0 + v82 FpCast { kind=F64ToF32, value=v81 } -> d0 [f32] + v83 StoreLocal { off=-9, value=v82, kind=F32 } -> - + v84 LocalAddr(-9) -> x1 + v85 Imm(0) -> x2 + v86 LoadLocal { off=-10, kind=I64 } -> x2 + v87 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] + v88 FpCast { kind=F32ToF64, value=v87 } -> d0 + v89 Binop { op=fadd, lhs=v88, rhs=v81 } -> d0 + v90 FpCast { kind=F64ToF32, value=v89 } -> d0 [f32] + v91 Store { addr=v84, disp=0, value=v90, kind=F32 } -> - + v92 LoadLocal { off=-10, kind=I64 } -> x2 + v93 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] + v94 FpCast { kind=F32ToF64, value=v93 } -> d0 + v95 Binop { op=fadd, lhs=v94, rhs=v81 } -> d0 + v96 FpCast { kind=F64ToF32, value=v95 } -> d0 [f32] + v97 Store { addr=v84, disp=0, value=v96, kind=F32 } -> - + v98 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v99 Imm(4613937818241073152) -> x0 + v100 FpCast { kind=F32ToF64, value=v98 } -> d0 + v101 Binop { op=fne, lhs=v100, rhs=v99 } -> x0 + terminator Bz { cond=v101, target=b18, fall=b17 } (exit_acc=v101) block 17 start_pc=0 - v104 Imm(5) -> x0 - terminator Return(v104) (exit_acc=v104) + v102 Imm(5) -> x0 + terminator Return(v102) (exit_acc=v102) block 18 start_pc=0 - v105 LocalAddr(-12) -> x0 - v106 ImmData(16) -> x1 - v107 Mcpy { dst=v105, src=v106, size=16 } -> x0 - v108 LocalAddr(-12) -> x0 - v109 Load { addr=v108, disp=0, kind=F32 } -> d0 [f32] - v110 Imm(4607182418800017408) -> x1 - v111 FpCast { kind=F32ToF64, value=v109 } -> d0 - v112 Binop { op=fadd, lhs=v111, rhs=v110 } -> d0 - v113 FpCast { kind=F64ToF32, value=v112 } -> d0 [f32] - v114 Store { addr=v108, disp=0, value=v113, kind=F32 } -> - - v115 LocalAddr(-12) -> x0 - v116 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x1 - v117 Load { addr=v115, disp=8, kind=F64 } -> d0 - v118 Imm(-4616189618054758400) -> x1 - v119 Binop { op=fadd, lhs=v117, rhs=v118 } -> d0 - v120 Store { addr=v115, disp=8, value=v119, kind=F64 } -> - - v121 LocalAddr(-12) -> x0 - v122 Load { addr=v121, disp=0, kind=F32 } -> d0 [f32] - v123 Imm(4612811918334230528) -> x0 - v124 FpCast { kind=F32ToF64, value=v122 } -> d0 - v125 Binop { op=fne, lhs=v124, rhs=v123 } -> x1 - v126 Imm(0) -> x0 - terminator Bnz { cond=v125, target=b35, fall=b19 } (exit_acc=v125) + v103 LocalAddr(-12) -> x0 + v104 ImmData(16) -> x1 + v105 Mcpy { dst=v103, src=v104, size=16 } -> x0 + v106 LocalAddr(-12) -> x0 + v107 Load { addr=v106, disp=0, kind=F32 } -> d0 [f32] + v108 Imm(4607182418800017408) -> x1 + v109 FpCast { kind=F32ToF64, value=v107 } -> d0 + v110 Binop { op=fadd, lhs=v109, rhs=v108 } -> d0 + v111 FpCast { kind=F64ToF32, value=v110 } -> d0 [f32] + v112 Store { addr=v106, disp=0, value=v111, kind=F32 } -> - + v113 LocalAddr(-12) -> x0 + v114 BinopI { op=add, lhs=v113, rhs_imm=8 } -> x1 + v115 Load { addr=v113, disp=8, kind=F64 } -> d0 + v116 Imm(-4616189618054758400) -> x1 + v117 Binop { op=fadd, lhs=v115, rhs=v116 } -> d0 + v118 Store { addr=v113, disp=8, value=v117, kind=F64 } -> - + v119 LocalAddr(-12) -> x0 + v120 Load { addr=v119, disp=0, kind=F32 } -> d0 [f32] + v121 Imm(4612811918334230528) -> x0 + v122 FpCast { kind=F32ToF64, value=v120 } -> d0 + v123 Binop { op=fne, lhs=v122, rhs=v121 } -> x1 + v124 Imm(0) -> x0 + terminator Bnz { cond=v123, target=b35, fall=b19 } (exit_acc=v123) block 19 start_pc=0 - v127 LocalAddr(-12) -> x0 - v128 BinopI { op=add, lhs=v127, rhs_imm=8 } -> x1 - v129 Load { addr=v127, disp=8, kind=F64 } -> d0 - v130 Imm(4609434218613702656) -> x0 - v131 Binop { op=fne, lhs=v129, rhs=v130 } -> x1 - v132 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v131) + v125 LocalAddr(-12) -> x0 + v126 BinopI { op=add, lhs=v125, rhs_imm=8 } -> x1 + v127 Load { addr=v125, disp=8, kind=F64 } -> d0 + v128 Imm(4609434218613702656) -> x0 + v129 Binop { op=fne, lhs=v127, rhs=v128 } -> x1 + v130 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v129) block 20 start_pc=0 - v133 Phi { incoming=[b35:v125, b19:v131], kind=I64 } -> x1 - v134 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v133, target=b22, fall=b21 } (exit_acc=v133) + v131 Phi { incoming=[b35:v123, b19:v129], kind=I64 } -> x1 + v132 LoadLocal { off=-21, kind=I64 } -> x0 + terminator Bz { cond=v131, target=b22, fall=b21 } (exit_acc=v131) block 21 start_pc=0 - v135 Imm(6) -> x0 - terminator Return(v135) (exit_acc=v135) + v133 Imm(6) -> x0 + terminator Return(v133) (exit_acc=v133) block 22 start_pc=0 - v136 ImmData(8) -> x0 - v137 Load { addr=v136, disp=0, kind=F64 } -> d0 - v138 Imm(4607182418800017408) -> x1 - v139 Binop { op=fadd, lhs=v137, rhs=v138 } -> d0 - v140 Store { addr=v136, disp=0, value=v139, kind=F64 } -> - - v141 Load { addr=v136, disp=0, kind=F64 } -> d0 - v142 Binop { op=fadd, lhs=v141, rhs=v138 } -> d0 - v143 Store { addr=v136, disp=0, value=v142, kind=F64 } -> - - v144 Load { addr=v136, disp=0, kind=F64 } -> d0 - v145 Imm(4619567317775286272) -> x0 - v146 Binop { op=fne, lhs=v144, rhs=v145 } -> x0 - terminator Bz { cond=v146, target=b24, fall=b23 } (exit_acc=v146) + v134 ImmData(8) -> x0 + v135 Load { addr=v134, disp=0, kind=F64 } -> d0 + v136 Imm(4607182418800017408) -> x1 + v137 Binop { op=fadd, lhs=v135, rhs=v136 } -> d0 + v138 Store { addr=v134, disp=0, value=v137, kind=F64 } -> - + v139 Load { addr=v134, disp=0, kind=F64 } -> d0 + v140 Binop { op=fadd, lhs=v139, rhs=v136 } -> d0 + v141 Store { addr=v134, disp=0, value=v140, kind=F64 } -> - + v142 Load { addr=v134, disp=0, kind=F64 } -> d0 + v143 Imm(4619567317775286272) -> x0 + v144 Binop { op=fne, lhs=v142, rhs=v143 } -> x0 + terminator Bz { cond=v144, target=b24, fall=b23 } (exit_acc=v144) block 23 start_pc=0 - v147 Imm(7) -> x0 - terminator Return(v147) (exit_acc=v147) + v145 Imm(7) -> x0 + terminator Return(v145) (exit_acc=v145) block 24 start_pc=0 - v148 LocalAddr(-15) -> x0 - v149 ImmData(32) -> x1 - v150 Mcpy { dst=v148, src=v149, size=24 } -> x0 - v151 LocalAddr(-15) -> x0 - v152 Imm(8) -> x1 - v153 BinopI { op=add, lhs=v151, rhs_imm=8 } -> x1 - v154 Load { addr=v151, disp=8, kind=F64 } -> d0 - v155 Imm(4607182418800017408) -> x1 - v156 Binop { op=fadd, lhs=v154, rhs=v155 } -> d0 - v157 Store { addr=v151, disp=8, value=v156, kind=F64 } -> - - v158 LocalAddr(-15) -> x0 - v159 Imm(16) -> x1 - v160 BinopI { op=add, lhs=v158, rhs_imm=16 } -> x1 - v161 Load { addr=v158, disp=16, kind=F64 } -> d0 - v162 Imm(-4616189618054758400) -> x1 - v163 Binop { op=fadd, lhs=v161, rhs=v162 } -> d0 - v164 Store { addr=v158, disp=16, value=v163, kind=F64 } -> - - v165 LocalAddr(-15) -> x0 - v166 BinopI { op=add, lhs=v165, rhs_imm=8 } -> x1 - v167 Load { addr=v165, disp=8, kind=F64 } -> d0 - v168 Imm(4611686018427387904) -> x0 - v169 Binop { op=fne, lhs=v167, rhs=v168 } -> x1 - v170 Imm(0) -> x0 - terminator Bnz { cond=v169, target=b36, fall=b25 } (exit_acc=v169) + v146 LocalAddr(-15) -> x0 + v147 ImmData(32) -> x1 + v148 Mcpy { dst=v146, src=v147, size=24 } -> x0 + v149 LocalAddr(-15) -> x0 + v150 Imm(8) -> x1 + v151 BinopI { op=add, lhs=v149, rhs_imm=8 } -> x1 + v152 Load { addr=v149, disp=8, kind=F64 } -> d0 + v153 Imm(4607182418800017408) -> x1 + v154 Binop { op=fadd, lhs=v152, rhs=v153 } -> d0 + v155 Store { addr=v149, disp=8, value=v154, kind=F64 } -> - + v156 LocalAddr(-15) -> x0 + v157 Imm(16) -> x1 + v158 BinopI { op=add, lhs=v156, rhs_imm=16 } -> x1 + v159 Load { addr=v156, disp=16, kind=F64 } -> d0 + v160 Imm(-4616189618054758400) -> x1 + v161 Binop { op=fadd, lhs=v159, rhs=v160 } -> d0 + v162 Store { addr=v156, disp=16, value=v161, kind=F64 } -> - + v163 LocalAddr(-15) -> x0 + v164 BinopI { op=add, lhs=v163, rhs_imm=8 } -> x1 + v165 Load { addr=v163, disp=8, kind=F64 } -> d0 + v166 Imm(4611686018427387904) -> x0 + v167 Binop { op=fne, lhs=v165, rhs=v166 } -> x1 + v168 Imm(0) -> x0 + terminator Bnz { cond=v167, target=b36, fall=b25 } (exit_acc=v167) block 25 start_pc=0 - v171 LocalAddr(-15) -> x0 - v172 Imm(16) -> x1 - v173 BinopI { op=add, lhs=v171, rhs_imm=16 } -> x1 - v174 Load { addr=v171, disp=16, kind=F64 } -> d0 - v175 Imm(4607182418800017408) -> x0 - v176 Binop { op=fne, lhs=v174, rhs=v175 } -> x1 - v177 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v176) + v169 LocalAddr(-15) -> x0 + v170 Imm(16) -> x1 + v171 BinopI { op=add, lhs=v169, rhs_imm=16 } -> x1 + v172 Load { addr=v169, disp=16, kind=F64 } -> d0 + v173 Imm(4607182418800017408) -> x0 + v174 Binop { op=fne, lhs=v172, rhs=v173 } -> x1 + v175 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v174) block 26 start_pc=0 - v178 Phi { incoming=[b36:v169, b25:v176], kind=I64 } -> x1 - v179 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v178, target=b28, fall=b27 } (exit_acc=v178) + v176 Phi { incoming=[b36:v167, b25:v174], kind=I64 } -> x1 + v177 LoadLocal { off=-22, kind=I64 } -> x0 + terminator Bz { cond=v176, target=b28, fall=b27 } (exit_acc=v176) block 27 start_pc=0 - v180 Imm(8) -> x0 - terminator Return(v180) (exit_acc=v180) + v178 Imm(8) -> x0 + terminator Return(v178) (exit_acc=v178) block 28 start_pc=0 - v181 Imm(4715268809856909312) -> x0 - v182 FpCast { kind=F64ToF32, value=v181 } -> d0 [f32] - v183 StoreLocal { off=-16, value=v182, kind=F32 } -> - - v184 LocalAddr(-16) -> x1 - v185 Load { addr=v184, disp=0, kind=F32 } -> d0 [f32] - v186 Imm(4607182418800017408) -> x2 - v187 FpCast { kind=F32ToF64, value=v185 } -> d0 - v188 Binop { op=fadd, lhs=v187, rhs=v186 } -> d0 - v189 FpCast { kind=F64ToF32, value=v188 } -> d0 [f32] - v190 Store { addr=v184, disp=0, value=v189, kind=F32 } -> - - v191 LoadLocal { off=-16, kind=F32 } -> d0 [f32] - v192 FpCast { kind=F32ToF64, value=v191 } -> d0 - v193 Binop { op=fne, lhs=v192, rhs=v181 } -> x0 - terminator Bz { cond=v193, target=b30, fall=b29 } (exit_acc=v193) + v179 Imm(4715268809856909312) -> x0 + v180 FpCast { kind=F64ToF32, value=v179 } -> d0 [f32] + v181 Imm(0) -> x1 + v182 LoadLocal { off=-16, kind=F32 } -> d1 [f32] + v183 Imm(4607182418800017408) -> x1 + v184 FpCast { kind=F32ToF64, value=v180 } -> d0 + v185 Binop { op=fadd, lhs=v184, rhs=v183 } -> d0 + v186 FpCast { kind=F64ToF32, value=v185 } -> d0 [f32] + v187 Imm(0) -> x1 + v188 LoadLocal { off=-16, kind=F32 } -> d1 [f32] + v189 FpCast { kind=F32ToF64, value=v186 } -> d0 + v190 Binop { op=fne, lhs=v189, rhs=v179 } -> x0 + terminator Bz { cond=v190, target=b30, fall=b29 } (exit_acc=v190) block 29 start_pc=0 - v194 Imm(9) -> x0 - terminator Return(v194) (exit_acc=v194) + v191 Imm(9) -> x0 + terminator Return(v191) (exit_acc=v191) block 30 start_pc=0 - v195 Imm(0) -> x0 - terminator Return(v195) (exit_acc=v195) + v192 Imm(0) -> x0 + terminator Return(v192) (exit_acc=v192) block 31 start_pc=0 terminator Jmp(b2) block 32 start_pc=0 diff --git a/tests/snapshots/ssa/float_single_precision.ssa b/tests/snapshots/ssa/float_single_precision.ssa index 28e982dde..9b26597b2 100644 --- a/tests/snapshots/ssa/float_single_precision.ssa +++ b/tests/snapshots/ssa/float_single_precision.ssa @@ -50,62 +50,62 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 v0 AllocaInit(0) -> - v1 Imm(0) -> x1 v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 StoreLocal { off=-1, value=v2, kind=F32 } -> - + v3 Imm(0) -> x0 v4 Imm(0) -> x0 terminator Jmp(b1) (exit_acc=v1) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v9], kind=I64 } -> x1 - v6 Extend { value=v5, kind=I32 } -> x0 - v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x0 - terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x1 + v6 Phi { incoming=[b0:v2, b2:v16], kind=F32 } -> d0 [f32] + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=lt, lhs=v7, rhs_imm=10 } -> x0 + terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) block 2 start_pc=0 - v8 Extend { value=v5, kind=I32 } -> x0 - v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 - v10 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v9) + v9 Extend { value=v5, kind=I32 } -> x0 + v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 + v11 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v10) block 3 start_pc=0 - v11 LocalAddr(-1) -> x0 - v12 Load { addr=v11, disp=0, kind=F32 } -> d0 [f32] - v13 Imm(4591870180066957722) -> x2 - v14 FpCast { kind=F32ToF64, value=v12 } -> d0 + v12 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v13 Imm(4591870180066957722) -> x0 + v14 FpCast { kind=F32ToF64, value=v6 } -> d0 v15 Binop { op=fadd, lhs=v14, rhs=v13 } -> d0 v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Store { addr=v11, disp=0, value=v16, kind=F32 } -> - - v18 Load { addr=v11, disp=0, kind=F32 } -> d0 [f32] - terminator Jmp(b2) (exit_acc=v18) + v17 Imm(0) -> x0 + v18 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + terminator Jmp(b2) (exit_acc=v16) block 4 start_pc=0 v19 Imm(4607182419250377371) -> x0 - v20 FpCast { kind=F64ToF32, value=v19 } -> d0 [f32] + v20 FpCast { kind=F64ToF32, value=v19 } -> d1 [f32] v21 Imm(0) -> x0 - v22 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v22 LoadLocal { off=-1, kind=F32 } -> d2 [f32] v23 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v24 Binop { op=fsub, lhs=v22, rhs=v20 } -> d1 [f32] + v24 Binop { op=fsub, lhs=v6, rhs=v20 } -> d2 [f32] v25 Imm(0) -> x0 - v26 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v26 LoadLocal { off=-4, kind=F32 } -> d1 [f32] v27 Imm(0) -> x0 - v28 FpCast { kind=IntToFp, value=v27 } -> d0 - v29 FpCast { kind=F64ToF32, value=v28 } -> d0 [f32] + v28 FpCast { kind=IntToFp, value=v27 } -> d1 + v29 FpCast { kind=F64ToF32, value=v28 } -> d1 [f32] v30 Binop { op=flt, lhs=v24, rhs=v29 } -> x0 terminator Bz { cond=v30, target=b11, fall=b5 } (exit_acc=v30) block 5 start_pc=0 - v31 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v32 Fneg(v24) -> d1 [f32] + v31 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v32 Fneg(v24) -> d2 [f32] v33 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v32) block 6 start_pc=0 - v34 Phi { incoming=[b11:v24, b5:v32], kind=F32 } -> d1 [f32] - v35 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v34 Phi { incoming=[b11:v24, b5:v32], kind=F32 } -> d2 [f32] + v35 LoadLocal { off=-4, kind=F32 } -> d1 [f32] v36 Imm(4517329193108106637) -> x0 - v37 FpCast { kind=F32ToF64, value=v34 } -> d0 + v37 FpCast { kind=F32ToF64, value=v34 } -> d1 v38 Binop { op=fgt, lhs=v37, rhs=v36 } -> x0 terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) block 7 start_pc=0 v39 Imm(2) -> x0 terminator Return(v39) (exit_acc=v39) block 8 start_pc=0 - v40 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v40 LoadLocal { off=-1, kind=F32 } -> d1 [f32] v41 Imm(4607182418800017408) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 + v42 FpCast { kind=F32ToF64, value=v6 } -> d0 v43 Binop { op=feq, lhs=v42, rhs=v41 } -> x0 terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) block 9 start_pc=0 diff --git a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa index 0f3ca366b..541fe722d 100644 --- a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa +++ b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa @@ -62,7 +62,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=6 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=8 - spill_count=0 gpr_used=[3, 12] fp_used=[] + spill_count=1 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 @@ -84,8 +84,8 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 terminator Jmp(b5) (exit_acc=v9) block 4 start_pc=0 v11 Imm(0) -> x1 - v12 FpCast { kind=F64ToF32, value=v11 } -> d0 [f32] - v13 StoreLocal { off=-3, value=v12, kind=F32 } -> - + v12 FpCast { kind=F64ToF32, value=v11 } -> [spill 0] [f32] + v13 Imm(0) -> x0 v14 Imm(0) -> x0 terminator Jmp(b11) (exit_acc=v11) block 5 start_pc=0 @@ -139,40 +139,40 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 block 10 start_pc=0 terminator Jmp(b6) block 11 start_pc=0 - v53 Phi { incoming=[b4:v11, b12:v57], kind=I64 } -> x1 - v54 Extend { value=v53, kind=I32 } -> x0 - v55 BinopI { op=lt, lhs=v54, rhs_imm=12 } -> x0 - terminator Bz { cond=v55, target=b14, fall=b13 } (exit_acc=v55) + v53 Phi { incoming=[b4:v12, b12:v75], kind=F32 } -> [spill 0] [f32] + v54 Phi { incoming=[b4:v11, b12:v58], kind=I64 } -> x1 + v55 Extend { value=v54, kind=I32 } -> x0 + v56 BinopI { op=lt, lhs=v55, rhs_imm=12 } -> x0 + terminator Bz { cond=v56, target=b14, fall=b13 } (exit_acc=v56) block 12 start_pc=0 - v56 Extend { value=v53, kind=I32 } -> x0 - v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x1 - v58 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v57) + v57 Extend { value=v54, kind=I32 } -> x0 + v58 BinopI { op=add, lhs=v57, rhs_imm=1 } -> x1 + v59 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v58) block 13 start_pc=0 - v59 LocalAddr(-3) -> x0 - v60 Load { addr=v59, disp=0, kind=F32 } -> d0 [f32] - v61 ImmData(56) -> x2 - v62 Extend { value=v53, kind=I32 } -> x6 - v63 BinopI { op=shl, lhs=v62, rhs_imm=4 } -> x6 - v64 Binop { op=add, lhs=v61, rhs=v63 } -> x2 - v65 Imm(0) -> x6 - v66 Load { addr=v64, disp=0, kind=F32 } -> d1 [f32] - v67 Imm(4) -> x6 - v68 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x6 - v69 Load { addr=v64, disp=4, kind=F32 } -> d2 [f32] - v70 Binop { op=fadd, lhs=v66, rhs=v69 } -> d1 [f32] - v71 Imm(8) -> x6 - v72 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x6 - v73 Load { addr=v64, disp=8, kind=F32 } -> d2 [f32] - v74 Binop { op=fadd, lhs=v70, rhs=v73 } -> d1 [f32] - v75 Binop { op=fadd, lhs=v60, rhs=v74 } -> d0 [f32] - v76 Store { addr=v59, disp=0, value=v75, kind=F32 } -> - - v77 Load { addr=v59, disp=0, kind=F32 } -> d0 [f32] - terminator Jmp(b12) (exit_acc=v77) + v60 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v61 ImmData(56) -> x0 + v62 Extend { value=v54, kind=I32 } -> x2 + v63 BinopI { op=shl, lhs=v62, rhs_imm=4 } -> x2 + v64 Binop { op=add, lhs=v61, rhs=v63 } -> x0 + v65 Imm(0) -> x2 + v66 Load { addr=v64, disp=0, kind=F32 } -> d0 [f32] + v67 Imm(4) -> x2 + v68 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x2 + v69 Load { addr=v64, disp=4, kind=F32 } -> d1 [f32] + v70 Binop { op=fadd, lhs=v66, rhs=v69 } -> d0 [f32] + v71 Imm(8) -> x2 + v72 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x2 + v73 Load { addr=v64, disp=8, kind=F32 } -> d1 [f32] + v74 Binop { op=fadd, lhs=v70, rhs=v73 } -> d0 [f32] + v75 Binop { op=fadd, lhs=v53, rhs=v74 } -> [spill 0] [f32] + v76 Imm(0) -> x0 + v77 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + terminator Jmp(b12) (exit_acc=v75) block 14 start_pc=0 v78 LoadLocal { off=-3, kind=F32 } -> d0 [f32] v79 Imm(0) -> x0 - v80 FpCast { kind=F32ToF64, value=v78 } -> d0 + v80 FpCast { kind=F32ToF64, value=v53 } -> d0 v81 Binop { op=fne, lhs=v80, rhs=v79 } -> x0 terminator Bz { cond=v81, target=b16, fall=b15 } (exit_acc=v81) block 15 start_pc=0 @@ -180,7 +180,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v83 Call { target_pc=0, args=[v82], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 v84 ImmData(470) -> x6 v85 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v86 FpCast { kind=F32ToF64, value=v85 } -> d0 + v86 FpCast { kind=F32ToF64, value=v53 } -> d0 v87 CallExt { binding_idx=1, args=[v83, v84, v86], fp_arg_mask=0x4 } -> x0 terminator Return(v82) (exit_acc=v82) block 16 start_pc=0 From 49ae8a804d1fa0d06fa0ef4dc58f43e377389e78 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 20:25:12 -0700 Subject: [PATCH 02/36] tests: refresh a stale data-offset snapshot The ImmData offsets drifted with earlier header/runtime binding changes; the current compiler already produces these values, so this is regeneration only, no codegen change. Co-Authored-By: Claude Fable 5 --- tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa index cd0d1043c..52d5add39 100644 --- a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa +++ b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa @@ -55,8 +55,8 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 v20 Imm(0) -> x0 terminator Jmp(b6) (exit_acc=v19) block 5 start_pc=0 - v21 ImmData(162) -> x7 - v22 ImmData(173) -> x6 + v21 ImmData(165) -> x7 + v22 ImmData(176) -> x6 v23 Imm(20) -> x2 v24 Call { target_pc=1, args=[v21, v22, v23], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x1 v25 Imm(0) -> x0 From b1633e3ee17643b3b99cfa04555dbc6a1e7b6d91 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 20:58:37 -0700 Subject: [PATCH 03/36] c5: type f/F-suffixed floating constants float C99 6.4.4.2p4: an unsuffixed floating constant has type double, f/F float, l/L long double (which c5 represents as double). The lexer consumed the suffix and discarded it, so every floating constant was typed double: sizeof(1.0f) reported 8, and float arithmetic against an f-suffixed literal ran a widen / op-in-double / narrow hop. The lexer now records the f/F suffix and rounds the constant to single precision at the literal (6.4.4.2p5), keeping the value as f64 bits so the const-expression evaluator and static initializers consume it unchanged. The parser types the literal Ty::Float; the walker emits it through the new SsaBuilder::imm_f32, cached apart from integer imms of equal payload because the f32 mark changes the value's materialisation. The SSA interpreter widens an f32-marked imm at its definition to match its f64-pattern register convention. Fixes #348 Co-Authored-By: Claude Fable 5 --- src/c5/ast/walk.rs | 4 +- src/c5/codegen/ssa/build.rs | 18 + src/c5/compiler/expr.rs | 17 +- src/c5/lexer.rs | 57 ++- src/c5/tests/jit.rs | 3 + src/c5/tests/native.rs | 3 + src/c5/tests/native_elf.rs | 3 + src/c5/tests/native_elf_x64.rs | 3 + src/c5/tests/native_pe_arm64.rs | 3 + src/c5/tests/native_pe_x64.rs | 3 + src/c5/tests/programs.rs | 22 +- src/c5/vm/ssa.rs | 11 +- .../c/float_literal_arith_single_precision.c | 28 + tests/fixtures/c/float_literal_f_suffix.c | 54 ++ .../c/float_literal_variadic_printf.c | 14 + tests/fixtures/c/float_long_double_suffix.c | 8 +- .../addr_of_intrinsic_math_float.aarch64.asm | 310 +++++------- .../asm/addr_of_intrinsic_math_float.x64.asm | 125 ++--- ...assign_float_register_resident.aarch64.asm | 108 ++-- ...und_assign_float_register_resident.x64.asm | 69 +-- .../asm/compound_assign_int_fp.aarch64.asm | 11 +- .../asm/compound_assign_int_fp.x64.asm | 9 +- .../asm/const_float_init_int_lead.aarch64.asm | 7 +- .../asm/const_float_init_int_lead.x64.asm | 6 +- .../float_arg_single_precision.aarch64.asm | 93 ++-- .../asm/float_arg_single_precision.x64.asm | 79 ++- .../float_arith_in_static_init.aarch64.asm | 23 +- .../asm/float_arith_in_static_init.x64.asm | 18 +- .../asm/float_double_mix.aarch64.asm | 74 ++- tests/snapshots/asm/float_double_mix.x64.asm | 30 +- .../asm/float_increment_decrement.aarch64.asm | 106 ++-- .../asm/float_increment_decrement.x64.asm | 73 +-- .../asm/float_is_four_bytes.aarch64.asm | 160 +++--- .../snapshots/asm/float_is_four_bytes.x64.asm | 127 ++--- ...literal_arith_single_precision.aarch64.asm | 121 +++++ ...oat_literal_arith_single_precision.x64.asm | 139 +++++ .../asm/float_literal_f_suffix.aarch64.asm | 236 +++++++++ .../asm/float_literal_f_suffix.x64.asm | 245 +++++++++ .../float_literal_variadic_printf.aarch64.asm | 46 ++ .../asm/float_literal_variadic_printf.x64.asm | 44 ++ .../asm/float_long_double_suffix.aarch64.asm | 21 +- .../asm/float_long_double_suffix.x64.asm | 14 +- .../asm/float_register_resident.aarch64.asm | 31 +- .../asm/float_register_resident.x64.asm | 29 +- .../asm/float_single_precision.aarch64.asm | 138 +++-- .../asm/float_single_precision.x64.asm | 83 ++- .../asm/float_ternary_promote.aarch64.asm | 107 ++-- .../asm/float_ternary_promote.x64.asm | 83 ++- .../asm/float_variadic_promotion.aarch64.asm | 80 +-- .../asm/float_variadic_promotion.x64.asm | 47 +- .../snapshots/asm/fma_contraction.aarch64.asm | 116 ++--- tests/snapshots/asm/fma_contraction.x64.asm | 104 ++-- .../asm/fn_ptr_float_arg.aarch64.asm | 32 +- tests/snapshots/asm/fn_ptr_float_arg.x64.asm | 27 +- .../asm/fn_ptr_float_arg_narrow.aarch64.asm | 150 ++---- .../asm/fn_ptr_float_arg_narrow.x64.asm | 108 ++-- .../asm/fn_ptr_float_return.aarch64.asm | 39 +- .../snapshots/asm/fn_ptr_float_return.x64.asm | 31 +- .../snapshots/asm/fp_const_return.aarch64.asm | 12 +- tests/snapshots/asm/fp_const_return.x64.asm | 10 +- .../asm/fp_load_folded_disp.aarch64.asm | 34 +- .../snapshots/asm/fp_load_folded_disp.x64.asm | 25 +- .../fp_param_float_before_double.aarch64.asm | 55 +- .../asm/fp_param_float_before_double.x64.asm | 47 +- .../asm/fp_param_ternary.aarch64.asm | 105 ++-- tests/snapshots/asm/fp_param_ternary.x64.asm | 85 ++-- .../snapshots/asm/fp_return_value.aarch64.asm | 39 +- tests/snapshots/asm/fp_return_value.x64.asm | 30 +- .../asm/fp_unary_intrinsic.aarch64.asm | 151 +++--- .../snapshots/asm/fp_unary_intrinsic.x64.asm | 103 ++-- .../asm/hex_float_literal.aarch64.asm | 10 +- tests/snapshots/asm/hex_float_literal.x64.asm | 9 +- .../asm/hfa_param_interleave.aarch64.asm | 36 +- .../asm/hfa_param_interleave.x64.asm | 31 +- .../asm/hfa_struct_return.aarch64.asm | 29 +- tests/snapshots/asm/hfa_struct_return.x64.asm | 24 +- .../asm/init_scalar_conversion.aarch64.asm | 54 +- .../asm/init_scalar_conversion.x64.asm | 42 +- ...int_to_float_assign_conversion.aarch64.asm | 66 +-- .../int_to_float_assign_conversion.x64.asm | 43 +- .../asm/leading_dot_float_literal.aarch64.asm | 24 +- .../asm/leading_dot_float_literal.x64.asm | 17 +- .../asm/libc_fp_classify.aarch64.asm | 20 +- tests/snapshots/asm/libc_fp_classify.x64.asm | 20 +- .../asm/libc_fp_return_value.aarch64.asm | 86 ++-- .../asm/libc_fp_return_value.x64.asm | 59 +-- .../asm/libc_math_fdim_scalbn.aarch64.asm | 32 +- .../asm/libc_math_fdim_scalbn.x64.asm | 30 +- .../asm/libc_math_hyperbolic.aarch64.asm | 16 +- .../asm/libc_math_hyperbolic.x64.asm | 16 +- .../snapshots/asm/libc_math_libm.aarch64.asm | 20 +- tests/snapshots/asm/libc_math_libm.x64.asm | 21 +- .../asm/libc_math_minmax.aarch64.asm | 47 +- tests/snapshots/asm/libc_math_minmax.x64.asm | 41 +- .../asm/libc_math_nextafter.aarch64.asm | 20 +- .../snapshots/asm/libc_math_nextafter.x64.asm | 20 +- .../snapshots/asm/libc_math_round.aarch64.asm | 24 +- tests/snapshots/asm/libc_math_round.x64.asm | 20 +- .../asm/libc_math_special.aarch64.asm | 13 +- tests/snapshots/asm/libc_math_special.x64.asm | 13 +- .../asm/local_init_int_to_float.aarch64.asm | 73 ++- .../asm/local_init_int_to_float.x64.asm | 36 +- .../asm/logical_not_float.aarch64.asm | 20 +- tests/snapshots/asm/logical_not_float.x64.asm | 18 +- .../out_pointer_return_float_args.aarch64.asm | 104 ++-- .../asm/out_pointer_return_float_args.x64.asm | 87 ++-- .../param_fp_before_int_pressure.aarch64.asm | 24 +- .../asm/param_fp_before_int_pressure.x64.asm | 35 +- .../asm/ternary_arith_conversion.aarch64.asm | 48 +- .../asm/ternary_arith_conversion.x64.asm | 36 +- ...two_d_float_array_partial_init.aarch64.asm | 67 +-- .../two_d_float_array_partial_init.x64.asm | 38 +- ..._d_stride_no_leak_across_exprs.aarch64.asm | 28 +- .../two_d_stride_no_leak_across_exprs.x64.asm | 20 +- .../snapshots/asm/uint64_to_float.aarch64.asm | 7 +- tests/snapshots/asm/uint64_to_float.x64.asm | 6 +- .../asm/volatile_param_classes.aarch64.asm | 5 +- .../asm/volatile_param_classes.x64.asm | 6 +- .../ssa/addr_of_intrinsic_math_float.ssa | 220 ++++---- ...ompound_assign_float_register_resident.ssa | 164 +++--- .../snapshots/ssa/compound_assign_int_fp.ssa | 177 +++---- .../ssa/const_float_init_int_lead.ssa | 17 +- .../ssa/float_arg_single_precision.ssa | 129 +++-- .../ssa/float_arith_in_static_init.ssa | 113 ++--- tests/snapshots/ssa/float_double_mix.ssa | 266 +++++----- .../ssa/float_increment_decrement.ssa | 422 ++++++++------- tests/snapshots/ssa/float_is_four_bytes.ssa | 479 +++++++++--------- .../float_literal_arith_single_precision.ssa | 150 ++++++ .../snapshots/ssa/float_literal_f_suffix.ssa | 219 ++++++++ .../ssa/float_literal_variadic_printf.ssa | 72 +++ .../ssa/float_long_double_suffix.ssa | 92 ++-- .../snapshots/ssa/float_register_resident.ssa | 68 ++- .../snapshots/ssa/float_single_precision.ssa | 225 ++++---- tests/snapshots/ssa/float_ternary_promote.ssa | 178 +++---- .../ssa/float_variadic_promotion.ssa | 107 ++-- tests/snapshots/ssa/fma_contraction.ssa | 224 ++++---- tests/snapshots/ssa/fn_ptr_float_arg.ssa | 90 ++-- .../snapshots/ssa/fn_ptr_float_arg_narrow.ssa | 236 ++++----- tests/snapshots/ssa/fn_ptr_float_return.ssa | 103 ++-- tests/snapshots/ssa/fp_const_return.ssa | 46 +- tests/snapshots/ssa/fp_load_folded_disp.ssa | 128 +++-- .../ssa/fp_param_float_before_double.ssa | 105 ++-- tests/snapshots/ssa/fp_param_ternary.ssa | 137 +++-- tests/snapshots/ssa/fp_return_value.ssa | 101 ++-- tests/snapshots/ssa/fp_unary_intrinsic.ssa | 271 +++++----- tests/snapshots/ssa/hex_float_literal.ssa | 52 +- tests/snapshots/ssa/hfa_param_interleave.ssa | 54 +- tests/snapshots/ssa/hfa_struct_return.ssa | 103 ++-- .../snapshots/ssa/init_scalar_conversion.ssa | 116 +++-- .../ssa/int_to_float_assign_conversion.ssa | 99 ++-- .../ssa/leading_dot_float_literal.ssa | 63 ++- tests/snapshots/ssa/libc_fp_classify.ssa | 129 +++-- tests/snapshots/ssa/libc_fp_return_value.ssa | 170 +++---- tests/snapshots/ssa/libc_math_fdim_scalbn.ssa | 41 +- tests/snapshots/ssa/libc_math_hyperbolic.ssa | 20 +- tests/snapshots/ssa/libc_math_libm.ssa | 40 +- tests/snapshots/ssa/libc_math_minmax.ssa | 57 +-- tests/snapshots/ssa/libc_math_nextafter.ssa | 34 +- tests/snapshots/ssa/libc_math_round.ssa | 36 +- tests/snapshots/ssa/libc_math_special.ssa | 41 +- .../snapshots/ssa/local_init_int_to_float.ssa | 251 +++++---- tests/snapshots/ssa/logical_not_float.ssa | 72 ++- .../ssa/out_pointer_return_float_args.ssa | 370 +++++++------- .../ssa/param_fp_before_int_pressure.ssa | 125 +++-- .../ssa/ternary_arith_conversion.ssa | 168 +++--- .../ssa/two_d_float_array_partial_init.ssa | 92 ++-- .../ssa/two_d_stride_no_leak_across_exprs.ssa | 65 ++- tests/snapshots/ssa/uint64_to_float.ssa | 15 +- .../snapshots/ssa/volatile_param_classes.ssa | 19 +- 169 files changed, 6700 insertions(+), 6078 deletions(-) create mode 100644 tests/fixtures/c/float_literal_arith_single_precision.c create mode 100644 tests/fixtures/c/float_literal_f_suffix.c create mode 100644 tests/fixtures/c/float_literal_variadic_printf.c create mode 100644 tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm create mode 100644 tests/snapshots/asm/float_literal_arith_single_precision.x64.asm create mode 100644 tests/snapshots/asm/float_literal_f_suffix.aarch64.asm create mode 100644 tests/snapshots/asm/float_literal_f_suffix.x64.asm create mode 100644 tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm create mode 100644 tests/snapshots/asm/float_literal_variadic_printf.x64.asm create mode 100644 tests/snapshots/ssa/float_literal_arith_single_precision.ssa create mode 100644 tests/snapshots/ssa/float_literal_f_suffix.ssa create mode 100644 tests/snapshots/ssa/float_literal_variadic_printf.ssa diff --git a/src/c5/ast/walk.rs b/src/c5/ast/walk.rs index 0b2d39659..2007db1f2 100644 --- a/src/c5/ast/walk.rs +++ b/src/c5/ast/walk.rs @@ -1447,9 +1447,7 @@ impl<'a> Walker<'a> { // f64 bits untagged. if is_float_ty(*ty) { let f32_bits = f64::from_bits(*bits) as f32; - let imm = f32_bits.to_bits() as i64; - let v = b.imm(imm); - return Ok(b.mark_f32(v)); + return Ok(b.imm_f32(f32_bits.to_bits())); } Ok(b.imm(*bits as i64)) } diff --git a/src/c5/codegen/ssa/build.rs b/src/c5/codegen/ssa/build.rs index 9884bd595..9a08f1ca0 100644 --- a/src/c5/codegen/ssa/build.rs +++ b/src/c5/codegen/ssa/build.rs @@ -64,6 +64,11 @@ struct LocalCacheEntry { #[derive(Clone, Copy, PartialEq, Eq, Hash)] enum PureKey { Imm(i64), + /// `Inst::Imm` holding an f32 bit pattern, tagged f32. Kept apart + /// from [`PureKey::Imm`]: the f32 mark changes the value's + /// materialisation, so an integer imm with an equal payload must + /// not unify with it. + ImmF32(i64), ImmData(i64), ImmCode(usize), TlsAddr(i64), @@ -408,6 +413,19 @@ impl SsaBuilder { id } + /// `Inst::Imm` carrying an f32 bit pattern, tagged f32 (a `float` + /// constant, C99 6.4.4.2p4). Cached under its own key so it never + /// unifies with an integer imm of equal payload. + pub(crate) fn imm_f32(&mut self, f32_bits: u32) -> ValueId { + let v = f32_bits as i64; + if let Some(cached) = self.lookup_pure(PureKey::ImmF32(v)) { + return cached; + } + let id = self.push(Inst::Imm(v)); + self.pure_cache.insert(PureKey::ImmF32(v), id); + self.mark_f32(id) + } + /// `Inst::ImmData` (data-segment offset). Same CSE shape as /// `imm`. Externally-resolved data offsets use /// `imm_data_extern`, which records a per-site reloc entry diff --git a/src/c5/compiler/expr.rs b/src/c5/compiler/expr.rs index dc32bba42..5f18968d8 100644 --- a/src/c5/compiler/expr.rs +++ b/src/c5/compiler/expr.rs @@ -448,15 +448,18 @@ impl Compiler { self.ast_emit_int_lit(val, self.ty); self.next()?; } else if self.lex.tk == Token::FloatNum { - // C99 6.4.4.2: floating constant. The lexer parsed - // `1.5` etc. into f64 and stored `f64::to_bits()` cast - // to i64 in `ival`. The byte pattern flows through - // the integer-literal emit unmodified; the codegen - // reads it back via `f64::from_bits` when the - // surrounding `self.ty` marks the value as floating. + // C99 6.4.4.2p4: an unsuffixed floating constant has + // type double, `f`/`F` float, `l`/`L` long double + // (represented as f64 in c5). The lexer stored the + // value -- already rounded to single precision for + // `f`/`F` -- as `f64::to_bits()` cast to i64 in `ival`. let bits = self.lex.ival as u64; self.emit_imm(self.lex.ival); - self.ty = Ty::Double as i64; + self.ty = if self.lex.float_suffix_f32 { + Ty::Float as i64 + } else { + Ty::Double as i64 + }; self.ast_emit_float_lit(bits, self.ty); self.next()?; } else if self.lex.tk == '"' { diff --git a/src/c5/lexer.rs b/src/c5/lexer.rs index 37c9ee851..eb22b3a64 100644 --- a/src/c5/lexer.rs +++ b/src/c5/lexer.rs @@ -240,6 +240,13 @@ pub(crate) struct Lexer { /// decimal constant with no `u` suffix stays signed. pub int_is_decimal: bool, + /// `true` when the most recent `Token::FloatNum` carried an `f`/`F` + /// suffix (C99 6.4.4.2p4: the constant has type `float`). `ival` + /// then holds the value already rounded to single precision, + /// re-widened to f64 bits. An `l`/`L` suffix keeps the flag false: + /// c5 represents long double as f64. + pub float_suffix_f32: bool, + /// `true` when the most recent `'"'` string-literal token came from /// a wide (`L"..."`) literal. The element width follows /// `wchar_bytes`; the initializer and expression parsers read this @@ -385,6 +392,7 @@ impl Lexer { int_suffix_long: 0, int_suffix_unsigned: false, int_is_decimal: true, + float_suffix_f32: false, str_is_wide: false, wchar_bytes: 4, char_signed: true, @@ -484,10 +492,11 @@ impl Lexer { ))); } let mut exp = if exp_neg { -exp } else { exp }; - // The `f`/`F`/`l`/`L` suffix only selects the type; c5 stores - // every floating constant as f64, so it is consumed and - // discarded. + // C99 6.4.4.2p4: `f`/`F` types the constant `float`, `l`/`L` + // long double (represented as f64 in c5). Record the float + // suffix; the value is rounded to single precision below. if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } // Scale by 2^exp through exact doubling / halving so the @@ -500,6 +509,11 @@ impl Lexer { mant *= 0.5; exp += 1; } + // An `f`-suffixed constant is a value of type float (C99 + // 6.4.4.2p4-5): round to single precision, kept as f64 bits. + if self.float_suffix_f32 { + mant = mant as f32 as f64; + } Ok(mant) } @@ -1000,6 +1014,7 @@ impl Lexer { self.int_suffix_long = 0; self.int_suffix_unsigned = false; self.int_is_decimal = true; + self.float_suffix_f32 = false; loop { if self.pos >= self.src.len() { self.tk = Tok::EOF; @@ -1269,11 +1284,10 @@ impl Lexer { if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { - // Consume the floating-point suffix per C99 - // 6.4.4.2: `f`/`F` is float, `l`/`L` is long - // double. The c5 dialect aliases long double - // to double, so every suffix lands in `f64` - // and the suffix is purely informational. + // Floating-point suffix per C99 6.4.4.2p4: + // `f`/`F` types the constant `float`, `l`/`L` + // long double (represented as f64 in c5). + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } let lit = @@ -1283,12 +1297,18 @@ impl Lexer { self.line ))) })?; - let f: f64 = lit.parse().map_err(|e| { + let mut f: f64 = lit.parse().map_err(|e| { C5Error::Compile(crate::c5::error::fmt_internal_err(&format!( "{}: malformed float literal `{lit}`: {e}", self.line ))) })?; + // An `f`-suffixed constant is a value of type float + // (C99 6.4.4.2p5): round to single precision, kept + // as f64 bits. + if self.float_suffix_f32 { + f = f as f32 as f64; + } self.ival = f.to_bits() as i64; self.tk = Tok(Token::FloatNum as i64); return self.end_number(); @@ -1633,12 +1653,11 @@ impl Lexer { if self.pos < self.src.len() && matches!(self.src[self.pos], b'f' | b'F' | b'l' | b'L') { - // Floating-point suffix (C99 6.4.4.2): - // `f`/`F` -> float, `l`/`L` -> long - // double. The c5 dialect aliases long - // double to double, so the suffix is - // informational and the bytes land in - // `f64`. + // Floating-point suffix per C99 + // 6.4.4.2p4: `f`/`F` types the constant + // `float`, `l`/`L` long double + // (represented as f64 in c5). + self.float_suffix_f32 = matches!(self.src[self.pos], b'f' | b'F'); self.pos += 1; } let lit = core::str::from_utf8(&self.src[int_start..body_end]) @@ -1648,12 +1667,18 @@ impl Lexer { self.line ))) })?; - let f: f64 = lit.parse().map_err(|e| { + let mut f: f64 = lit.parse().map_err(|e| { C5Error::Compile(crate::c5::error::fmt_internal_err(&format!( "{}: malformed float literal `{lit}`: {e}", self.line ))) })?; + // An `f`-suffixed constant is a value of + // type float (C99 6.4.4.2p5): round to + // single precision, kept as f64 bits. + if self.float_suffix_f32 { + f = f as f32 as f64; + } self.ival = f.to_bits() as i64; self.tk = Tok(Token::FloatNum as i64); } else { diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index b76455ece..49b1672b6 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1296,6 +1296,9 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ // VM and both codegens implement. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("fp_param_float_before_double.c", 0), ("float_arg_single_precision.c", 0), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index caf640afe..53114af44 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -798,6 +798,9 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ // host-platform smoke test for that pipeline. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_unary_intrinsic.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("fp_param_float_before_double.c", 0), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index 401c776b6..feb507ab5 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -506,6 +506,9 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ // Full FP arithmetic + comparisons + casts. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index dd1e449a3..27591bef6 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -457,6 +457,9 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ // cvttsd2si). ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index 45ce3a8cd..aebd032e9 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -752,6 +752,9 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ // as the ELF arm64 / macOS arm64 paths. ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index ef6a57b16..6ad2ece60 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -767,6 +767,9 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ // ABI, which this fixture doesn't exercise (no FP libc calls). ("float_arithmetic.c", 0), ("float_single_precision.c", 0), + ("float_literal_f_suffix.c", 0), + ("float_literal_arith_single_precision.c", 0), + ("float_literal_variadic_printf.c", 0), ("fp_arg_passed_in_fp_reg.c", 0), ("float_arg_single_precision.c", 0), ("fp_return_value.c", 0), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 0009847cf..5283bc6d4 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -386,6 +386,22 @@ fn compound_assign_float_register_resident() { assert_eq!(run_fixture("compound_assign_float_register_resident.c"), 0); } +#[test] +fn float_literal_f_suffix() { + // C99 6.4.4.2p4-5: an `f`/`F`-suffixed floating constant has type + // `float` and its value is rounded to single precision at the + // literal. Covers sizeof, widening, the variadic default argument + // promotion, and hex-float spellings. + assert_eq!(run_fixture("float_literal_f_suffix.c"), 0); +} + +#[test] +fn float_literal_arith_single_precision() { + // C99 6.3.1.8: `float` combined with an `f`-suffixed constant + // computes in single precision with no widen / narrow hop. + assert_eq!(run_fixture("float_literal_arith_single_precision.c"), 0); +} + #[test] fn array_range_designator() { // GCC `[a ... b] = value` fills the inclusive range; covers constant @@ -1712,9 +1728,9 @@ fn adjacent_string_literals_concatenate() { #[test] fn float_long_double_suffix_accepted() { // C99 6.4.4.2: the floating-suffix is one of `f`, `F`, `l`, - // `L`. The dialect stores every floating literal in `f64`, - // so the four spellings of the same value land identical at - // the bit level. The fixture also pins the integer-vs-float + // `L`. 1.0 is exact in every precision, so the four spellings + // of the value land identical at the bit level after conversion + // to double. The fixture also pins the integer-vs-float // disambiguator -- bare `7L` stays a `long` integer because // no `.` / `e` was seen. assert_eq!(run_fixture("float_long_double_suffix.c"), 0); diff --git a/src/c5/vm/ssa.rs b/src/c5/vm/ssa.rs index ae21313be..9d560fb8b 100644 --- a/src/c5/vm/ssa.rs +++ b/src/c5/vm/ssa.rs @@ -781,7 +781,16 @@ fn run_inst( let inst = &frame.func.insts[v as usize]; let name = match inst { Inst::Imm(k) => { - frame.regs[v as usize] = *k; + // An f32-marked imm carries the f32 bit pattern (the shape + // the native emit materialises); the interpreter's register + // convention keeps every f32 value as the f64 pattern of + // its single-precision value, so widen at the definition. + frame.regs[v as usize] = if matches!(frame.func.f32_values.get(v as usize), Some(true)) + { + (f32::from_bits(*k as u32) as f64).to_bits() as i64 + } else { + *k + }; return Ok(()); } Inst::ImmData(off) => { diff --git a/tests/fixtures/c/float_literal_arith_single_precision.c b/tests/fixtures/c/float_literal_arith_single_precision.c new file mode 100644 index 000000000..16a0ab31f --- /dev/null +++ b/tests/fixtures/c/float_literal_arith_single_precision.c @@ -0,0 +1,28 @@ +// C99 6.3.1.8: `float op float-constant` stays in single precision -- +// an `f`-suffixed literal has type float (6.4.4.2p4), so no widen / +// narrow hop brackets the operation. Runtime checks pin the values; +// the SSA snapshot pins the single-precision ops. + +static float step(float x) { + return x - 1.0f; +} + +static float blend(float x, float y) { + return x * 0.5f + y * 0.25f; +} + +int main(void) { + if (step(2.5f) != 1.5f) return 1; + if (blend(3.0f, 8.0f) != 3.5f) return 2; + + // Accumulation where f32 and f64 intermediates diverge: ten + // additions of 0.1f in f32 land at 1.0000001f, not 1.0f. + float sum = 0.0f; + for (int i = 0; i < 10; i++) { + sum = sum + 0.1f; + } + if (sum == 1.0f) return 3; + if (sum != 1.0000001f) return 4; + + return 0; +} diff --git a/tests/fixtures/c/float_literal_f_suffix.c b/tests/fixtures/c/float_literal_f_suffix.c new file mode 100644 index 000000000..4503538ab --- /dev/null +++ b/tests/fixtures/c/float_literal_f_suffix.c @@ -0,0 +1,54 @@ +// C99 6.4.4.2p4: an unsuffixed floating constant has type double, +// `f`/`F` float, `l`/`L` long double (which c5 represents as +// double). p5: the value is converted to the constant's type at +// the literal, so an `f`-suffixed constant carries single-precision +// rounding into any wider context. + +#include + +static double vsum(int n, ...) { + va_list ap; + va_start(ap, n); + double s = 0; + int i; + for (i = 0; i < n; i++) { + s += va_arg(ap, double); + } + va_end(ap); + return s; +} + +int main(void) { + // Constant types observed through sizeof (6.5.3.4). + if (sizeof(1.0f) != 4) return 1; + if (sizeof(1.0F) != 4) return 2; + if (sizeof(1.0) != 8) return 3; + if (sizeof(1.0l) != 8) return 4; + if (sizeof(1.0L) != 8) return 5; + if (sizeof(.5f) != 4) return 6; + if (sizeof(1e2f) != 4) return 7; + if (sizeof(0x1p0f) != 4) return 8; + + // 16777217 is the first integer with no f32 representation: the + // f-suffixed constant rounds to 16777216 at the literal, while + // the double constant holds it exactly. + if (16777217.0f != 16777216.0f) return 9; + if (16777217.0 == 16777216.0) return 10; + + // The f32 rounding survives widening (6.3.1.5): (double)0.1f is + // the exact value of the f32 nearest 0.1, not the double nearest. + if (0.1f == 0.1) return 11; + if (0.1f != 0.10000000149011611938476562500) return 12; + if (-0.1f != -0.10000000149011611938476562500) return 13; + + // Default argument promotion (6.5.2.2p6): an f-suffixed literal + // argument reaches the variadic callee as its exact double + // widening. + if (vsum(2, 1.5f, 0.25f) != 1.75) return 14; + if (vsum(1, 0.1f) != 0.10000000149011611938476562500) return 16; + + // A hex floating constant (6.4.4.2) takes the suffix too. + if (0x1.000002p24f != 16777218.0f) return 15; + + return 0; +} diff --git a/tests/fixtures/c/float_literal_variadic_printf.c b/tests/fixtures/c/float_literal_variadic_printf.c new file mode 100644 index 000000000..e83ccaf55 --- /dev/null +++ b/tests/fixtures/c/float_literal_variadic_printf.c @@ -0,0 +1,14 @@ +// C99 6.5.2.2p6: a `float` argument to a variadic function undergoes +// the default argument promotion to `double`; an `f`-suffixed literal +// (6.4.4.2p4) rides the same path. The formatted text pins the exact +// promoted values, including the single-precision rounding of 0.1f. + +#include +#include + +int main(void) { + char buf[64]; + snprintf(buf, sizeof buf, "%.1f %.8f", 1.5f, 0.1f); + if (strcmp(buf, "1.5 0.10000000") != 0) return 1; + return 0; +} diff --git a/tests/fixtures/c/float_long_double_suffix.c b/tests/fixtures/c/float_long_double_suffix.c index 766e6c744..af5175f8a 100644 --- a/tests/fixtures/c/float_long_double_suffix.c +++ b/tests/fixtures/c/float_long_double_suffix.c @@ -1,8 +1,8 @@ // Locks C99 6.4.4.2 -- the floating-suffix is one of f / F / l / L. -// `f`/`F` mark `float`, `l`/`L` mark `long double`. The c5 dialect -// stores every floating literal in `f64` and treats the suffix as -// informational, so the four spellings of the same value must all -// land at the same bit pattern. +// `f`/`F` type the constant `float`, `l`/`L` `long double` (which c5 +// represents as double). 1.0 is exact in every precision, so the +// four spellings of the value must all land at the same bit pattern +// after conversion to double. // // Returns 0 only when every check passes; each failure path // returns a distinct nonzero code. diff --git a/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm b/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm index aad4e05a0..6174985ca 100644 --- a/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm +++ b/tests/snapshots/asm/addr_of_intrinsic_math_float.aarch64.asm @@ -12,13 +12,11 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0xd0 - str d8, [sp] - str d9, [sp, #0x8] - str x20, [sp, #0x10] - str x21, [sp, #0x18] - str x22, [sp, #0x20] - str x19, [sp, #0x30] + sub sp, sp, #0xc0 + str x20, [sp] + str x21, [sp, #0x8] + str x22, [sp, #0x10] + str x19, [sp, #0x20] adrp x0, add x0, x0, adrp x20, @@ -27,140 +25,106 @@ Disassembly of section .text: add x21, x21, adrp x22, add x22, x22, - mov x1, #0x4030000000000000 // =4625196817309499392 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x41800000 // =1098907648 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 + str x0, [sp, #-0x10]! mov x9, x20 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x4000, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x6666 // =26214 + movk x0, #0x4006, lsl #16 + str x0, [sp, #-0x10]! mov x9, x21 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 + str x0, [sp, #-0x10]! mov x9, x22 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, - mov x20, #0x400c000000000000 // =4615063718147915776 - fmov d16, x20 - fneg d0, d16 - fcvt s0, d0 + mov x20, #0x40600000 // =1080033280 + fmov s16, w20 + fneg s0, s16 fmov x16, d0 str x16, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x40 @@ -174,143 +138,127 @@ Disassembly of section .text: ldr x10, [x1, #0x10] str x10, [x0, #0x10] ldr x10, [sp], #0x10 - mov x0, #0x400000000000 // =70368744177664 - movk x0, #0x4054, lsl #48 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4017, lsl #48 - fmov d16, x0 - fcvt s8, d16 + mov x0, #0x42a20000 // =1117913088 + fmov s16, w0 + sub x17, x29, #0x48 + str s16, [x17] mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x4000, lsl #48 - fmov d16, x0 - fcvt s9, d16 + movk x0, #0x40bc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x50 + str s16, [x17] + mov x0, #0x6666 // =26214 + movk x0, #0x4006, lsl #16 + fmov s16, w0 + sub x17, x29, #0x58 + str s16, [x17] sub x0, x29, #0x40 ldr x0, [x0] + sub x16, x29, #0x48 + ldr s0, [x16] fmov x16, d0 str x16, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4022000000000000 // =4621256167635550208 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41100000 // =1091567616 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x40 ldr x0, [x0, #0x8] - fmov x16, d8 + sub x16, x29, #0x50 + ldr s0, [x16] + fmov x16, d0 str x16, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x40 ldr x0, [x0, #0x10] - fmov x16, d9 + sub x16, x29, #0x58 + ldr s0, [x16] + fmov x16, d0 str x16, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40e00000 // =1088421888 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4048, lsl #48 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x42440000 // =1111752704 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40e00000 // =1088421888 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xa // =10 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr x22, [sp, #0x20] - ldr d8, [sp] - ldr d9, [sp, #0x8] - ldr x19, [sp, #0x30] - add sp, sp, #0xd0 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x22, [sp, #0x10] + ldr x19, [sp, #0x20] + add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm b/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm index ed602bc38..b79982bd2 100644 --- a/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm +++ b/tests/snapshots/asm/addr_of_intrinsic_math_float.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xc0, %rsp + subq $0xb0, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -21,14 +21,12 @@ Disassembly of section .text: leaq , %rbx # leaq , %r12 # leaq , %r13 # - movabsq $0x4030000000000000, %rcx # imm = 0x4030000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %edi # imm = 0x41800000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -40,18 +38,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x402ccccd, %edi # imm = 0x402CCCCD movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -63,18 +59,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4000cccccccccccd, %rax # imm = 0x4000CCCCCCCCCCCD - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40066666, %edi # imm = 0x40066666 movq %r12, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -86,18 +80,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x4039999a, %edi # imm = 0x4039999A movq %r13, %rax + movq %rdi, %xmm0 callq *%rax - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,20 +101,18 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq , %rax # - movabsq $0x400c000000000000, %rbx # imm = 0x400C000000000000 + movl $0x40600000, %ebx # imm = 0x40600000 movq %rbx, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 callq *%rax - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -134,7 +124,7 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax @@ -147,24 +137,22 @@ Disassembly of section .text: movq 0x10(%rcx), %rdx movq %rdx, 0x10(%rax) popq %rdx - movabsq $0x4054400000000000, %rax # imm = 0x4054400000000000 + movl $0x42a20000, %eax # imm = 0x42A20000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x401799999999999a, %rax # imm = 0x401799999999999A + movss %xmm14, -0x48(%rbp,%riz) + movl $0x40bccccd, %eax # imm = 0x40BCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x28(%rsp) - movabsq $0x4000cccccccccccd, %rax # imm = 0x4000CCCCCCCCCCCD + movss %xmm14, -0x50(%rbp,%riz) + movl $0x40066666, %eax # imm = 0x40066666 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x20(%rsp) + movss %xmm14, -0x58(%rbp,%riz) leaq -0x40(%rbp), %rax movq (%rax), %rax + movss -0x48(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4022000000000000, %rax # imm = 0x4022000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41100000, %eax # imm = 0x41100000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -176,17 +164,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax movq 0x8(%rax), %rax - movsd 0x28(%rsp), %xmm0 + movss -0x50(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -198,17 +185,16 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq leaq -0x40(%rbp), %rax movq 0x10(%rax), %rax - movsd 0x20(%rsp), %xmm0 + movss -0x58(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -220,21 +206,19 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -246,17 +230,15 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq - movabsq $0x4048800000000000, %rax # imm = 0x4048800000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x42440000, %eax # imm = 0x42440000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -268,14 +250,14 @@ Disassembly of section .text: movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 movq 0x10(%rsp), %r13 - addq $0xc0, %rsp + addq $0xb0, %rsp popq %rbp retq @@ -287,3 +269,4 @@ Disassembly of section .text: <__c5_sys_ceilf>: jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm index ec09c765a..f9840eab8 100644 --- a/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm +++ b/tests/snapshots/asm/compound_assign_float_register_resident.aarch64.asm @@ -13,12 +13,14 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - mov x0, #0x4059000000000000 // =4636737291354636288 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x42c80000 // =1120403456 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] mov x1, #0x0 // =0 sxtw x0, w1 cmp x0, #0x8 @@ -27,73 +29,99 @@ Disassembly of section .text: sxtw x0, w1 add x1, x0, #0x1 b - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d1, s1 - fmov d17, x0 - fsub d1, d1, d17 - fcvt s1, d1 - fadd s1, s1, s0 + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fsub s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x10 + ldr s1, [x16] + fadd s0, s0, s1 + sub x17, x29, #0x8 + str s0, [x17] mov x0, #0x3ff0000000000000 // =4607182418800017408 - fcvt d0, s0 + fcvt d0, s1 fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 + sub x17, x29, #0x10 + str s0, [x17] b - mov x0, #0x405e000000000000 // =4638144666238189568 - fcvt d1, s1 - fmov d17, x0 - fcmp d1, d17 + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x42f00000 // =1123024896 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4022000000000000 // =4621256167635550208 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x10 + ldr s0, [x16] + mov x0, #0x41100000 // =1091567616 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f000000 // =1056964608 + fmov s16, w0 + sub x17, x29, #0x20 + str s16, [x17] + sub x16, x29, #0x20 + ldr s0, [x16] mov x1, #-0x4010000000000000 // =-4616189618054758400 fcvt d0, s0 fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + sub x17, x29, #0x20 + str s0, [x17] + sub x16, x29, #0x20 + ldr s0, [x16] + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x3 // =3 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + sub x17, x29, #0x28 + str s16, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] mov x0, #0x4010000000000000 // =4616189618054758400 fcvt d0, s0 fmov d17, x0 fmul d0, d0, d17 fcvt s0, d0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fdiv d0, d0, d17 - fcvt s0, d0 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x17, x29, #0x28 + str s0, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fdiv s0, s0, s17 + sub x17, x29, #0x28 + str s0, [x17] + sub x16, x29, #0x28 + ldr s0, [x16] + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 diff --git a/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm index 8c4ce195f..fa4f7848a 100644 --- a/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm +++ b/tests/snapshots/asm/compound_assign_float_register_resident.x64.asm @@ -14,12 +14,12 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x4059000000000000, %rax # imm = 0x4059000000000000 + movl $0x42c80000, %eax # imm = 0x42C80000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movss %xmm14, -0x8(%rbp,%riz) + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x10(%rbp,%riz) xorq %rcx, %rcx movslq %ecx, %rax cmpq $0x8, %rax @@ -28,22 +28,26 @@ Disassembly of section .text: movslq %ecx, %rax leaq 0x1(%rax), %rcx jmp - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm1, %xmm1 + movss -0x8(%rbp,%riz), %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - subsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 - addss %xmm0, %xmm1 + subss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm1, %xmm0 movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x10(%rbp,%riz) jmp - movabsq $0x405e000000000000, %rax # imm = 0x405E000000000000 - cvtss2sd %xmm1, %xmm1 + movss -0x8(%rbp,%riz), %xmm0 + movl $0x42f00000, %eax # imm = 0x42F00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -55,10 +59,10 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4022000000000000, %rax # imm = 0x4022000000000000 - cvtss2sd %xmm0, %xmm0 + movss -0x10(%rbp,%riz), %xmm0 + movl $0x41100000, %eax # imm = 0x41100000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -70,20 +74,22 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x20(%rbp,%riz) + movss -0x20(%rbp,%riz), %xmm0 movabsq $-0x4010000000000000, %rcx # imm = 0xBFF0000000000000 cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x20(%rbp,%riz) + movss -0x20(%rbp,%riz), %xmm0 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -95,23 +101,25 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 mulsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movss %xmm0, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + divss %xmm15, %xmm0 + movss %xmm0, -0x28(%rbp,%riz) + movss -0x28(%rbp,%riz), %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -127,3 +135,4 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm b/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm index 1b8c8c987..7fabccda6 100644 --- a/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm +++ b/tests/snapshots/asm/compound_assign_int_fp.aarch64.asm @@ -66,12 +66,11 @@ Disassembly of section .text: ret mov x0, #0x7 // =7 scvtf d0, x0 - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d17, x0 - fadd d0, d0, d17 + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 + fmov s16, w0 + fcvt d1, s16 + fadd d0, d0, d1 fcvtzs x0, d0 sxtw x0, w0 cmp x0, #0x9 diff --git a/tests/snapshots/asm/compound_assign_int_fp.x64.asm b/tests/snapshots/asm/compound_assign_int_fp.x64.asm index e0566c713..a054b57df 100644 --- a/tests/snapshots/asm/compound_assign_int_fp.x64.asm +++ b/tests/snapshots/asm/compound_assign_int_fp.x64.asm @@ -64,9 +64,10 @@ Disassembly of section .text: retq movl $0x7, %eax cvtsi2sd %rax, %xmm0 - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm15 - addsd %xmm15, %xmm0 + movl $0x4039999a, %eax # imm = 0x4039999A + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + addsd %xmm1, %xmm0 cvttsd2si %xmm0, %rax movslq %eax, %rax cmpq $0x9, %rax @@ -161,5 +162,3 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm b/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm index 89fb258dd..57732d966 100644 --- a/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm +++ b/tests/snapshots/asm/const_float_init_int_lead.aarch64.asm @@ -35,10 +35,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, eq cmp x0, #0x0 b.ne diff --git a/tests/snapshots/asm/const_float_init_int_lead.x64.asm b/tests/snapshots/asm/const_float_init_int_lead.x64.asm index e3dbcb6d3..c9e104746 100644 --- a/tests/snapshots/asm/const_float_init_int_lead.x64.asm +++ b/tests/snapshots/asm/const_float_init_int_lead.x64.asm @@ -41,10 +41,9 @@ Disassembly of section .text: retq leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -56,4 +55,3 @@ Disassembly of section .text: retq xorq %rax, %rax retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/float_arg_single_precision.aarch64.asm b/tests/snapshots/asm/float_arg_single_precision.aarch64.asm index ace4c234e..ae66d3140 100644 --- a/tests/snapshots/asm/float_arg_single_precision.aarch64.asm +++ b/tests/snapshots/asm/float_arg_single_precision.aarch64.asm @@ -32,77 +32,64 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x40 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x3fd8000000000000 // =4600427019358961664 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + mov x1, #0x3e800000 // =1048576000 + fmov s16, w0 + fmov s17, w1 + fmul s0, s16, s17 + mov x0, #0x3ec00000 // =1052770304 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x4024000000000000 // =4621819117588971520 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fneg s0, s16 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x41200000 // =1092616192 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x2 // =2 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x0 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 - mov x0, #0x3fec000000000000 // =4606056518893174784 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + mov x2, #0x3e000000 // =1040187392 + fmov s16, w0 + fmov s17, w1 + fadd s0, s16, s17 + fmov s17, w2 + fadd s0, s0, s17 + mov x0, #0x3f600000 // =1063256064 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - mov x1, #0x4020000000000000 // =4620693217682128896 - fmov d16, x0 - fmov d17, x1 - fdiv d0, d16, d17 - fcvt s0, d0 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x41000000 // =1090519040 + fmov s16, w0 + fmov s17, w1 + fdiv s0, s16, s17 + mov x0, #0x41800000 // =1098907648 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 diff --git a/tests/snapshots/asm/float_arg_single_precision.x64.asm b/tests/snapshots/asm/float_arg_single_precision.x64.asm index 6dc7462b9..828186244 100644 --- a/tests/snapshots/asm/float_arg_single_precision.x64.asm +++ b/tests/snapshots/asm/float_arg_single_precision.x64.asm @@ -33,17 +33,14 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x40, %rsp - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x3fd8000000000000, %rax # imm = 0x3FD8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + mulss %xmm15, %xmm0 + movl $0x3ec00000, %eax # imm = 0x3EC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -55,23 +52,20 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -83,21 +77,17 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x3fc0000000000000, %rax # imm = 0x3FC0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 - movabsq $0x3fec000000000000, %rax # imm = 0x3FEC000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movl $0x3e000000, %edx # imm = 0x3E000000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 + movl $0x3f600000, %eax # imm = 0x3F600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,20 +99,17 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movabsq $0x4020000000000000, %rcx # imm = 0x4020000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x41000000, %ecx # imm = 0x41000000 movq %rcx, %xmm15 movq %rax, %xmm0 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + divss %xmm15, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm b/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm index faed97e86..8f6e023c5 100644 --- a/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm +++ b/tests/snapshots/asm/float_arith_in_static_init.aarch64.asm @@ -16,10 +16,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0] - mov x1, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + mov x1, #0x40000000 // =1073741824 + fmov s17, w1 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x1 // =1 @@ -27,11 +26,10 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldr s0, [x0, #0x4] - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x1, #0x40200000 // =1075838976 + fmov s16, w1 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x2 // =2 @@ -39,10 +37,9 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldr s0, [x0, #0x8] - mov x0, #0x4028000000000000 // =4622945017495814144 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41400000 // =1094713344 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/float_arith_in_static_init.x64.asm b/tests/snapshots/asm/float_arith_in_static_init.x64.asm index d58817a1d..030cb0b72 100644 --- a/tests/snapshots/asm/float_arith_in_static_init.x64.asm +++ b/tests/snapshots/asm/float_arith_in_static_init.x64.asm @@ -16,10 +16,9 @@ Disassembly of section .text: subq $0x10, %rsp leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %ecx # imm = 0x40000000 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -32,13 +31,12 @@ Disassembly of section .text: popq %rbp retq movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rcx # imm = 0x4004000000000000 + movl $0x40200000, %ecx # imm = 0x40200000 movq %rcx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -51,10 +49,9 @@ Disassembly of section .text: popq %rbp retq movss 0x8(%rax,%riz), %xmm0 - movabsq $0x4028000000000000, %rax # imm = 0x4028000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41400000, %eax # imm = 0x41400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -115,3 +112,4 @@ Disassembly of section .text: popq %rbp retq jmp + addb %al, (%rax) diff --git a/tests/snapshots/asm/float_double_mix.aarch64.asm b/tests/snapshots/asm/float_double_mix.aarch64.asm index 2e012e56b..0bdea6f8b 100644 --- a/tests/snapshots/asm/float_double_mix.aarch64.asm +++ b/tests/snapshots/asm/float_double_mix.aarch64.asm @@ -13,12 +13,11 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3fb9, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x0, #0x999a // =39322 movk x0, #0x9999, lsl #16 movk x0, #0x9999, lsl #32 @@ -26,6 +25,8 @@ Disassembly of section .text: fmov d16, x0 sub x17, x29, #0x10 str d16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] sub x16, x29, #0x10 ldr d1, [x16] fcvt d0, s0 @@ -64,12 +65,13 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3fb9, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] fcvt d0, s0 mov x0, #0xa0000000 // =2684354560 movk x0, #0x9999, lsl #32 @@ -114,12 +116,13 @@ Disassembly of section .text: sub x16, x29, #0x8 ldr d0, [x16] fcvt s0, d0 - mov x0, #0xe659 // =58969 - movk x0, #0x3b84, lsl #16 - movk x0, #0x9add, lsl #32 - movk x0, #0x3fbf, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0xd6ea // =55018 + movk x0, #0x3dfc, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s1, [x16] fsub s2, s0, s1 mov x0, #0x0 // =0 scvtf d1, x0 @@ -128,13 +131,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s2, s2 - mov x0, #0x8c3a // =35898 - movk x0, #0xe230, lsl #16 - movk x0, #0x798e, lsl #32 - movk x0, #0x3e45, lsl #48 - fcvt d1, s2 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0xcc77 // =52343 + movk x0, #0x322b, lsl #16 + fmov s17, w0 + fcmp s2, s17 cset x0, gt cbz x0, mov x0, #0x3 // =3 @@ -180,12 +180,13 @@ Disassembly of section .text: fmov d17, x1 fdiv d0, d16, d17 fcvt s0, d0 - mov x0, #0x7c87 // =31879 - movk x0, #0x5fb6, lsl #16 - movk x0, #0x5555, lsl #32 - movk x0, #0x3fd5, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0xaaab // =43691 + movk x0, #0x3eaa, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s1, [x16] fsub s1, s0, s1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -194,13 +195,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0xaf48 // =44872 - movk x0, #0x9abc, lsl #16 - movk x0, #0xd7f2, lsl #32 - movk x0, #0x3e7a, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xbf95 // =49045 + movk x0, #0x33d6, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x5 // =5 diff --git a/tests/snapshots/asm/float_double_mix.x64.asm b/tests/snapshots/asm/float_double_mix.x64.asm index 70efaa1e9..0445e0fd6 100644 --- a/tests/snapshots/asm/float_double_mix.x64.asm +++ b/tests/snapshots/asm/float_double_mix.x64.asm @@ -14,12 +14,13 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) movabsq $0x3fc999999999999a, %rax # imm = 0x3FC999999999999A movq %rax, %xmm14 movsd %xmm14, -0x10(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 movsd -0x10(%rbp,%riz), %xmm1 cvtss2sd %xmm0, %xmm0 addsd %xmm1, %xmm0 @@ -61,9 +62,10 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 movq %rax, %xmm15 @@ -108,9 +110,10 @@ Disassembly of section .text: movsd %xmm14, -0x8(%rbp,%riz) movsd -0x8(%rbp,%riz), %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fbf9add3b84e659, %rax # imm = 0x3FBF9ADD3B84E659 + movl $0x3dfcd6ea, %eax # imm = 0x3DFCD6EA movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm1 movapd %xmm0, %xmm2 subss %xmm1, %xmm2 xorq %rax, %rax @@ -127,10 +130,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm2 - movabsq $0x3e45798ee2308c3a, %rax # imm = 0x3E45798EE2308C3A - cvtss2sd %xmm2, %xmm1 + movl $0x322bcc77, %eax # imm = 0x322BCC77 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm2 seta %al movzbq %al, %rax testq %rax, %rax @@ -188,9 +190,10 @@ Disassembly of section .text: movq %rax, %xmm0 divsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd555555fb67c87, %rax # imm = 0x3FD555555FB67C87 + movl $0x3eaaaaab, %eax # imm = 0x3EAAAAAB movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm1 movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subss %xmm15, %xmm1 @@ -208,10 +211,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3e7ad7f29abcaf48, %rax # imm = 0x3E7AD7F29ABCAF48 - cvtss2sd %xmm1, %xmm0 + movl $0x33d6bf95, %eax # imm = 0x33D6BF95 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax diff --git a/tests/snapshots/asm/float_increment_decrement.aarch64.asm b/tests/snapshots/asm/float_increment_decrement.aarch64.asm index 0979be229..3675b1c54 100644 --- a/tests/snapshots/asm/float_increment_decrement.aarch64.asm +++ b/tests/snapshots/asm/float_increment_decrement.aarch64.asm @@ -13,47 +13,57 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0xb0 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d1, s0 fmov d17, x1 fadd d1, d1, d17 fcvt s1, d1 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x17, x29, #0x8 + str s1, [x17] + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x1 // =1 add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x18 + ldr s0, [x16] mov x0, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + sub x17, x29, #0x18 + str s0, [x17] + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x18 + ldr s0, [x16] + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x2 // =2 @@ -113,30 +123,29 @@ Disassembly of section .text: add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 sub x17, x29, #0x48 - str s0, [x17] - sub x1, x29, #0x48 - ldr s0, [x1] + str s16, [x17] + sub x0, x29, #0x48 + ldr s0, [x0] + mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 - fmov d17, x0 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] - ldr s0, [x1] + str s0, [x0] + ldr s0, [x0] fcvt d0, s0 - fmov d17, x0 + fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - str s0, [x1] + str s0, [x0] sub x16, x29, #0x48 ldr s0, [x16] - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 @@ -168,10 +177,9 @@ Disassembly of section .text: str d0, [x0, #0x8] sub x0, x29, #0x60 ldr s0, [x0] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbnz x1, sub x0, x29, #0x60 @@ -247,17 +255,23 @@ Disassembly of section .text: add sp, sp, #0xb0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4170000000000000 // =4715268809856909312 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x4b800000 // =1266679808 + fmov s16, w0 + sub x17, x29, #0x80 + str s16, [x17] + sub x16, x29, #0x80 + ldr s0, [x16] mov x1, #0x3ff0000000000000 // =4607182418800017408 fcvt d0, s0 fmov d17, x1 fadd d0, d0, d17 fcvt s0, d0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x17, x29, #0x80 + str s0, [x17] + sub x16, x29, #0x80 + ldr s0, [x16] + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 diff --git a/tests/snapshots/asm/float_increment_decrement.x64.asm b/tests/snapshots/asm/float_increment_decrement.x64.asm index 674287f30..7adb760d0 100644 --- a/tests/snapshots/asm/float_increment_decrement.x64.asm +++ b/tests/snapshots/asm/float_increment_decrement.x64.asm @@ -14,17 +14,18 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0xb0, %rsp - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm1 movq %rcx, %xmm15 addsd %xmm15, %xmm1 cvtsd2ss %xmm1, %xmm1 - cvtss2sd %xmm0, %xmm0 + movss %xmm1, -0x8(%rbp,%riz) movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -32,10 +33,10 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm1, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -47,18 +48,19 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x18(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm1 + movss %xmm0, -0x18(%rbp,%riz) + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -66,10 +68,10 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movss -0x18(%rbp,%riz), %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -147,28 +149,27 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x48(%rbp,%riz) - leaq -0x48(%rbp), %rcx - movss (%rcx,%riz), %xmm0 + movss %xmm14, -0x48(%rbp,%riz) + leaq -0x48(%rbp), %rax + movss (%rax,%riz), %xmm0 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) - movss (%rcx,%riz), %xmm0 + movss %xmm0, (%rax,%riz) + movss (%rax,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - movss %xmm0, (%rcx,%riz) + movss %xmm0, (%rax,%riz) movss -0x48(%rbp,%riz), %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -204,10 +205,9 @@ Disassembly of section .text: movsd %xmm0, 0x8(%rax,%riz) leaq -0x60(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -306,17 +306,19 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x4170000000000000, %rax # imm = 0x4170000000000000 + movl $0x4b800000, %eax # imm = 0x4B800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x80(%rbp,%riz) + movss -0x80(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 - cvtss2sd %xmm0, %xmm0 + movss %xmm0, -0x80(%rbp,%riz) + movss -0x80(%rbp,%riz), %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -338,4 +340,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_is_four_bytes.aarch64.asm b/tests/snapshots/asm/float_is_four_bytes.aarch64.asm index 9c028eee0..833d29284 100644 --- a/tests/snapshots/asm/float_is_four_bytes.aarch64.asm +++ b/tests/snapshots/asm/float_is_four_bytes.aarch64.asm @@ -56,10 +56,9 @@ Disassembly of section .text: sxtw x0, w0 mov x20, #0x3 // =3 sub x0, x29, #0x18 - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0] + mov x1, #0x3fc00000 // =1069547520 + fmov s16, w1 + str s16, [x0] sub x0, x29, #0x18 mov x1, #0x5678 // =22136 movk x1, #0x1234, lsl #16 @@ -81,10 +80,9 @@ Disassembly of section .text: sxtw x0, w0 sub x0, x29, #0x18 ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -113,10 +111,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0] - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -131,10 +128,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -149,10 +145,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0x8] - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -167,10 +162,9 @@ Disassembly of section .text: adrp x0, add x0, x0, ldr s0, [x0, #0xc] - mov x0, #0x4012000000000000 // =4616752568008179712 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40900000 // =1083179008 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -182,12 +176,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xa // =10 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, adrp x0, @@ -195,12 +187,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xb // =11 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, adrp x0, @@ -208,13 +198,11 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xc // =12 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 - fcmp s0, s1 + mov x0, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w1 + fcmp s16, s17 cset x0, eq cbz x0, adrp x0, @@ -222,56 +210,51 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xd // =13 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 - mov x0, #0x401a000000000000 // =4619004367821864960 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + mov x2, #0x40600000 // =1080033280 + fmov s16, w0 + fmov s17, w1 + fadd s0, s16, s17 + fmov s17, w2 + fadd s0, s0, s17 + mov x0, #0x40d00000 // =1087373312 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, add x0, x0, - mov x1, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x400c000000000000 // =4615063718147915776 - fmov d16, x1 - fcvt s2, d16 - fadd s0, s0, s1 - fadd s0, s0, s2 + mov x1, #0x3f800000 // =1065353216 + mov x2, #0x40000000 // =1073741824 + mov x3, #0x40600000 // =1080033280 + fmov s16, w1 + fmov s17, w2 + fadd s0, s16, s17 + fmov s17, w3 + fadd s0, s0, s17 fcvt d0, s0 bl sxtw x0, w0 mov x20, #0xe // =14 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - fmul s0, s0, s1 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fcvt d0, s0 - fmov d17, x0 - fadd d0, d0, d17 - fcvt s0, d0 - mov x0, #0x400a000000000000 // =4614500768194494464 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x30 + str s16, [x17] + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + sub x17, x29, #0x38 + str s16, [x17] + sub x16, x29, #0x30 + ldr s0, [x16] + sub x16, x29, #0x38 + ldr s1, [x16] + mov x0, #0x3e800000 // =1048576000 + fmov s18, w0 + fmadd s0, s0, s1, s18 + mov x0, #0x40500000 // =1078984704 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, adrp x0, @@ -280,11 +263,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x20, #0xf // =15 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 sub x17, x29, #0x48 - str s0, [x17] + str s16, [x17] sub x0, x29, #0x50 sub x1, x29, #0x48 mov x2, #0x4 // =4 diff --git a/tests/snapshots/asm/float_is_four_bytes.x64.asm b/tests/snapshots/asm/float_is_four_bytes.x64.asm index 309c468c1..8289f4603 100644 --- a/tests/snapshots/asm/float_is_four_bytes.x64.asm +++ b/tests/snapshots/asm/float_is_four_bytes.x64.asm @@ -56,10 +56,9 @@ Disassembly of section .text: movslq %eax, %rax movl $0x3, %ebx leaq -0x18(%rbp), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 + movl $0x3fc00000, %ecx # imm = 0x3FC00000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, (%rax,%riz) + movss %xmm14, (%rax,%riz) leaq -0x18(%rbp), %rax movl $0x12345678, %ecx # imm = 0x12345678 movl %ecx, 0x4(%rax) @@ -75,10 +74,9 @@ Disassembly of section .text: movslq %eax, %rax leaq -0x18(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -107,10 +105,9 @@ Disassembly of section .text: movl $0x6, %ebx leaq , %rax movss (%rax,%riz), %xmm0 - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -128,10 +125,9 @@ Disassembly of section .text: movl $0x7, %ebx leaq , %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -149,10 +145,9 @@ Disassembly of section .text: movl $0x8, %ebx leaq , %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -170,10 +165,9 @@ Disassembly of section .text: movl $0x9, %ebx leaq , %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -189,12 +183,10 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xa, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -207,12 +199,10 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xb, %ebx - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -225,13 +215,11 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xc, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movl $0x40200000, %ecx # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - ucomiss %xmm1, %xmm0 + movq %rcx, %xmm15 + ucomiss %xmm15, %xmm14 sete %al movzbq %al, %rax setnp %r10b @@ -244,21 +232,17 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xd, %ebx - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40000000, %ecx # imm = 0x40000000 + movl $0x40600000, %edx # imm = 0x40600000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -267,38 +251,35 @@ Disassembly of section .text: testq %rax, %rax je leaq , %rdi - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - addss %xmm1, %xmm0 - addss %xmm2, %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40000000, %ecx # imm = 0x40000000 + movl $0x40600000, %edx # imm = 0x40600000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + addss %xmm15, %xmm0 + movq %rdx, %xmm15 + addss %xmm15, %xmm0 cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movl $0xe, %ebx - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movss %xmm14, -0x30(%rbp,%riz) + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - mulss %xmm1, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x400a000000000000, %rax # imm = 0x400A000000000000 - cvtss2sd %xmm0, %xmm1 + movss %xmm14, -0x38(%rbp,%riz) + movss -0x30(%rbp,%riz), %xmm0 + movss -0x38(%rbp,%riz), %xmm1 + movl $0x3e800000, %eax # imm = 0x3E800000 + movapd %xmm0, %xmm14 + movapd %xmm1, %xmm15 + movq %rax, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x40500000, %eax # imm = 0x40500000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -312,10 +293,9 @@ Disassembly of section .text: callq movslq %eax, %rax movl $0xf, %ebx - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, -0x48(%rbp,%riz) + movss %xmm14, -0x48(%rbp,%riz) leaq -0x50(%rbp), %rdi leaq -0x48(%rbp), %rsi movl $0x4, %edx @@ -350,4 +330,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm b/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm new file mode 100644 index 000000000..ac2822e39 --- /dev/null +++ b/tests/snapshots/asm/float_literal_arith_single_precision.aarch64.asm @@ -0,0 +1,121 @@ + +float_literal_arith_single_precision.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fsub s0, s0, s17 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + fmov s17, w1 + fmul s1, s1, s17 + fmov s17, w0 + fmadd s0, s0, s17, s1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, #0x40200000 // =1075838976 + mov x1, #0x3f800000 // =1065353216 + fmov s16, w0 + fmov s17, w1 + fsub s0, s16, s17 + mov x0, #0x3fc00000 // =1069547520 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x40400000 // =1077936128 + mov x1, #0x41000000 // =1090519040 + mov x2, #0x3f000000 // =1056964608 + mov x3, #0x3e800000 // =1048576000 + fmov s16, w1 + fmov s17, w3 + fmul s0, s16, s17 + fmov s16, w0 + fmov s17, w2 + fmadd s0, s16, s17, s0 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x2 // =2 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x1, #0x0 // =0 + sxtw x0, w1 + cmp x0, #0xa + b.ge + b + sxtw x0, w1 + add x1, x0, #0x1 + b + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] + b + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fcmp s0, s17 + cset x0, eq + cbz x0, + mov x0, #0x3 // =3 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x1 // =1 + movk x0, #0x3f80, lsl #16 + fmov s17, w0 + fcmp s0, s17 + cset x0, ne + cbz x0, + mov x0, #0x4 // =4 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm b/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm new file mode 100644 index 000000000..cdee3e619 --- /dev/null +++ b/tests/snapshots/asm/float_literal_arith_single_precision.x64.asm @@ -0,0 +1,139 @@ + +float_literal_arith_single_precision.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl $0x3f800000, %eax # imm = 0x3F800000 + movq %rax, %xmm15 + subss %xmm15, %xmm0 + addq $0x10, %rsp + popq %rbp + retq + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movq %rcx, %xmm15 + mulss %xmm15, %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + addq $0x10, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl $0x40200000, %eax # imm = 0x40200000 + movl $0x3f800000, %ecx # imm = 0x3F800000 + movq %rcx, %xmm15 + movq %rax, %xmm0 + subss %xmm15, %xmm0 + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + retq + movl $0x40400000, %eax # imm = 0x40400000 + movl $0x41000000, %ecx # imm = 0x41000000 + movl $0x3f000000, %edx # imm = 0x3F000000 + movl $0x3e800000, %esi # imm = 0x3E800000 + movq %rsi, %xmm15 + movq %rcx, %xmm0 + mulss %xmm15, %xmm0 + movq %rax, %xmm14 + movq %rdx, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x40600000, %eax # imm = 0x40600000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x2, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) + xorq %rcx, %rcx + movslq %ecx, %rax + cmpq $0xa, %rax + jge + jmp + movslq %ecx, %rax + leaq 0x1(%rax), %rcx + jmp + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm15 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) + jmp + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0x3, %eax + addq $0x10, %rsp + popq %rbp + retq + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3f800001, %eax # imm = 0x3F800001 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x4, %eax + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm b/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm new file mode 100644 index 000000000..65fea3fac --- /dev/null +++ b/tests/snapshots/asm/float_literal_f_suffix.aarch64.asm @@ -0,0 +1,236 @@ + +float_literal_f_suffix.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + sub sp, sp, #0xc0 + str x0, [sp] + str x1, [sp, #0x8] + str x2, [sp, #0x10] + str x3, [sp, #0x18] + str x4, [sp, #0x20] + str x5, [sp, #0x28] + str x6, [sp, #0x30] + str x7, [sp, #0x38] + str d0, [sp, #0x40] + str d1, [sp, #0x50] + str d2, [sp, #0x60] + str d3, [sp, #0x70] + str d4, [sp, #0x80] + str d5, [sp, #0x90] + str d6, [sp, #0xa0] + str d7, [sp, #0xb0] + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x40 + str x19, [sp] + sub x0, x29, #0x20 + add x1, x29, #0x10 + mov x16, x0 + add x17, x29, #0xd0 + str x17, [x16] + add x17, x29, #0x50 + str x17, [x16, #0x8] + add x17, x29, #0xd0 + str x17, [x16, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x18] + mov x17, #0xff80 // =65408 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + str w17, [x16, #0x1c] + mov x1, #0x0 // =0 + scvtf d0, x1 + sxtw x0, w1 + ldursw x2, [x29, #0x10] + cmp x0, x2 + b.ge + b + sxtw x0, w1 + add x1, x0, #0x1 + b + sub x0, x29, #0x20 + mov x17, x0 + str x9, [sp, #-0x10]! + ldrsw x16, [x17, #0x1c] + cmp x16, #0x0 + b.ge + ldr x9, [x17, #0x10] + add x9, x9, x16 + add x16, x16, #0x10 + str w16, [x17, #0x1c] + cmp x16, #0x0 + b.gt + mov x16, x9 + b + ldr x16, [x17] + add x9, x16, #0x8 + str x9, [x17] + ldr x9, [sp], #0x10 + mov x0, x16 + ldr d1, [x0] + fadd d0, d0, d1 + b + sub x0, x29, #0x20 + ldr x19, [sp] + add sp, sp, #0x40 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0xc0 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + b + mov x0, #0x1 // =1 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x5 // =5 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x6 // =6 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x7 // =7 + ldp x29, x30, [sp], #0x10 + ret + b + mov x0, #0x8 // =8 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x4b800000 // =1266679808 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 + cset x0, ne + cbz x0, + mov x0, #0x9 // =9 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x10000000 // =268435456 + movk x0, #0x4170, lsl #48 + mov x1, #0x4170000000000000 // =4715268809856909312 + fmov d16, x0 + fmov d17, x1 + fcmp d16, d17 + cset x0, eq + cbz x0, + mov x0, #0xa // =10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + mov x1, #0x999a // =39322 + movk x1, #0x9999, lsl #16 + movk x1, #0x9999, lsl #32 + movk x1, #0x3fb9, lsl #48 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 + cset x0, eq + cbz x0, + mov x0, #0xb // =11 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + mov x1, #0xa0000000 // =2684354560 + movk x1, #0x9999, lsl #32 + movk x1, #0x3fb9, lsl #48 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0xc // =12 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s16, w0 + fneg s0, s16 + mov x0, #0xa0000000 // =2684354560 + movk x0, #0x9999, lsl #32 + movk x0, #0x3fb9, lsl #48 + fmov d16, x0 + fneg d1, d16 + fcvt d0, s0 + fcmp d0, d1 + cset x0, ne + cbz x0, + mov x0, #0xd // =13 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x2 // =2 + mov x1, #0x3fc00000 // =1069547520 + fmov s16, w1 + fcvt d0, s16 + mov x1, #0x3e800000 // =1048576000 + fmov s16, w1 + fcvt d1, s16 + bl + mov x0, #0x3ffc000000000000 // =4610560118520545280 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0xe // =14 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, #0xcccd // =52429 + movk x1, #0x3dcc, lsl #16 + fmov s16, w1 + fcvt d0, s16 + bl + mov x0, #0xa0000000 // =2684354560 + movk x0, #0x9999, lsl #32 + movk x0, #0x3fb9, lsl #48 + fmov d17, x0 + fcmp d0, d17 + cset x0, ne + cbz x0, + mov x0, #0x10 // =16 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + movk x0, #0x4b80, lsl #16 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 + cset x0, ne + cbz x0, + mov x0, #0xf // =15 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/float_literal_f_suffix.x64.asm b/tests/snapshots/asm/float_literal_f_suffix.x64.asm new file mode 100644 index 000000000..4bf1f41f6 --- /dev/null +++ b/tests/snapshots/asm/float_literal_f_suffix.x64.asm @@ -0,0 +1,245 @@ + +float_literal_f_suffix.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + pushq %rbp + movq %rsp, %rbp + subq $0xe0, %rsp + movq %rdi, -0xe0(%rbp) + movq %rsi, -0xd8(%rbp) + movq %rdx, -0xd0(%rbp) + movq %rcx, -0xc8(%rbp) + movq %r8, -0xc0(%rbp) + movq %r9, -0xb8(%rbp) + testb %al, %al + je + movsd %xmm0, -0xb0(%rbp,%riz) + movsd %xmm1, -0xa0(%rbp,%riz) + movsd %xmm2, -0x90(%rbp,%riz) + movsd %xmm3, -0x80(%rbp,%riz) + movsd %xmm4, -0x70(%rbp,%riz) + movsd %xmm5, -0x60(%rbp,%riz) + movsd %xmm6, -0x50(%rbp,%riz) + movsd %xmm7, -0x40(%rbp,%riz) + leaq -0x18(%rbp), %rax + leaq -0xe0(%rbp), %rcx + movl $0x8, (%rax) + movl $0x30, 0x4(%rax) + leaq 0x10(%rbp), %r10 + movq %r10, 0x8(%rax) + leaq -0xe0(%rbp), %r10 + movq %r10, 0x10(%rax) + xorq %rcx, %rcx + cvtsi2sd %rcx, %xmm0 + movslq %ecx, %rax + movslq -0xe0(%rbp), %rdx + cmpq %rdx, %rax + jge + jmp + movslq %ecx, %rax + leaq 0x1(%rax), %rcx + jmp + leaq -0x18(%rbp), %rax + movq %rax, %r11 + movl 0x4(%r11), %r10d + cmpq $0xb0, %r10 + jae + addq 0x10(%r11), %r10 + addl $0x10, 0x4(%r11) + jmp + movq 0x8(%r11), %r10 + addq $0x8, 0x8(%r11) + movq %r10, %rax + movsd (%rax,%riz), %xmm1 + addsd %xmm1, %xmm0 + jmp + leaq -0x18(%rbp), %rax + addq $0xe0, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + jmp + movl $0x1, %eax + popq %rbp + retq + jmp + movl $0x2, %eax + popq %rbp + retq + jmp + movl $0x3, %eax + popq %rbp + retq + jmp + movl $0x4, %eax + popq %rbp + retq + jmp + movl $0x5, %eax + popq %rbp + retq + jmp + movl $0x6, %eax + popq %rbp + retq + jmp + movl $0x7, %eax + popq %rbp + retq + jmp + movl $0x8, %eax + popq %rbp + retq + movl $0x4b800000, %eax # imm = 0x4B800000 + movq %rax, %xmm14 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x9, %eax + popq %rbp + retq + movabsq $0x4170000010000000, %rax # imm = 0x4170000010000000 + movabsq $0x4170000000000000, %rcx # imm = 0x4170000000000000 + movq %rax, %xmm14 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm14 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0xa, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movabsq $0x3fb999999999999a, %rcx # imm = 0x3FB999999999999A + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 + sete %al + movzbq %al, %rax + setnp %r10b + movzbq %r10b, %r10 + andq %r10, %rax + testq %rax, %rax + je + movl $0xb, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movabsq $0x3fb99999a0000000, %rcx # imm = 0x3FB99999A0000000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xc, %eax + popq %rbp + retq + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm0 + movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 + movq %rax, %xmm1 + movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movq %r10, %xmm15 + xorpd %xmm15, %xmm1 + cvtss2sd %xmm0, %xmm0 + ucomisd %xmm1, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xd, %eax + popq %rbp + retq + movl $0x2, %edi + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movl $0x3e800000, %eax # imm = 0x3E800000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + movb $0x2, %al + callq + movabsq $0x3ffc000000000000, %rax # imm = 0x3FFC000000000000 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xe, %eax + popq %rbp + retq + movl $0x1, %edi + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movb $0x1, %al + callq + movabsq $0x3fb99999a0000000, %rax # imm = 0x3FB99999A0000000 + movq %rax, %xmm15 + ucomisd %xmm15, %xmm0 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0x10, %eax + popq %rbp + retq + movl $0x4b800001, %eax # imm = 0x4B800001 + movq %rax, %xmm14 + movq %rax, %xmm15 + ucomiss %xmm15, %xmm14 + setne %al + movzbq %al, %rax + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rax + testq %rax, %rax + je + movl $0xf, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq diff --git a/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm b/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm new file mode 100644 index 000000000..a50befbee --- /dev/null +++ b/tests/snapshots/asm/float_literal_variadic_printf.aarch64.asm @@ -0,0 +1,46 @@ + +float_literal_variadic_printf.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x2b0 // =688 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x80 + str x19, [sp] + sub x0, x29, #0x40 + mov x1, #0x40 // =64 + adrp x2, + add x2, x2, + mov x3, #0x3fc00000 // =1069547520 + fmov s16, w3 + fcvt d0, s16 + mov x3, #0xcccd // =52429 + movk x3, #0x3dcc, lsl #16 + fmov s16, w3 + fcvt d1, s16 + bl + sxtw x0, w0 + sub x0, x29, #0x40 + adrp x1, + add x1, x1, + bl + sxtw x0, w0 + cmp x0, #0x0 + b.eq + mov x0, #0x1 // =1 + ldr x19, [sp] + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldr x19, [sp] + add sp, sp, #0x80 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/float_literal_variadic_printf.x64.asm b/tests/snapshots/asm/float_literal_variadic_printf.x64.asm new file mode 100644 index 000000000..85eecf23c --- /dev/null +++ b/tests/snapshots/asm/float_literal_variadic_printf.x64.asm @@ -0,0 +1,44 @@ + +float_literal_variadic_printf.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x70, %rsp + leaq -0x40(%rbp), %rdi + movl $0x40, %esi + leaq , %rdx + movl $0x3fc00000, %eax # imm = 0x3FC00000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + movb $0x2, %al + callq + movslq %eax, %rax + leaq -0x40(%rbp), %rdi + leaq , %rsi + xorl %eax, %eax + callq + movslq %eax, %rax + testq %rax, %rax + je + movl $0x1, %eax + addq $0x70, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x70, %rsp + popq %rbp + retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_long_double_suffix.aarch64.asm b/tests/snapshots/asm/float_long_double_suffix.aarch64.asm index d65021b9f..07f39f972 100644 --- a/tests/snapshots/asm/float_long_double_suffix.aarch64.asm +++ b/tests/snapshots/asm/float_long_double_suffix.aarch64.asm @@ -13,32 +13,23 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 + mov x0, #0x3f800000 // =1065353216 + fmov s16, w0 + fcvt d0, s16 mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d16, x0 - sub x17, x29, #0x8 - str d16, [x17] - fmov d16, x0 - sub x17, x29, #0x10 - str d16, [x17] - fmov d16, x0 sub x17, x29, #0x18 str d16, [x17] fmov d16, x0 sub x17, x29, #0x20 str d16, [x17] - sub x16, x29, #0x8 - ldr d0, [x16] - sub x16, x29, #0x10 - ldr d1, [x16] - fcmp d0, d1 + fcmp d0, d0 cset x0, ne cbz x0, mov x0, #0xb // =11 add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] sub x16, x29, #0x18 ldr d1, [x16] fcmp d0, d1 @@ -48,8 +39,6 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] sub x16, x29, #0x20 ldr d1, [x16] fcmp d0, d1 @@ -59,8 +48,6 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - sub x16, x29, #0x8 - ldr d0, [x16] mov x0, #0x3ff0000000000000 // =4607182418800017408 fmov d17, x0 fcmp d0, d17 diff --git a/tests/snapshots/asm/float_long_double_suffix.x64.asm b/tests/snapshots/asm/float_long_double_suffix.x64.asm index 254f4746e..0d29c2886 100644 --- a/tests/snapshots/asm/float_long_double_suffix.x64.asm +++ b/tests/snapshots/asm/float_long_double_suffix.x64.asm @@ -14,18 +14,15 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - movsd %xmm14, -0x8(%rbp,%riz) + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm14 - movsd %xmm14, -0x10(%rbp,%riz) + cvtss2sd %xmm14, %xmm0 + movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 movq %rax, %xmm14 movsd %xmm14, -0x18(%rbp,%riz) movq %rax, %xmm14 movsd %xmm14, -0x20(%rbp,%riz) - movsd -0x8(%rbp,%riz), %xmm0 - movsd -0x10(%rbp,%riz), %xmm1 - ucomisd %xmm1, %xmm0 + ucomisd %xmm0, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -37,7 +34,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movsd -0x18(%rbp,%riz), %xmm1 ucomisd %xmm1, %xmm0 setne %al @@ -51,7 +47,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movsd -0x20(%rbp,%riz), %xmm1 ucomisd %xmm1, %xmm0 setne %al @@ -65,7 +60,6 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movsd -0x8(%rbp,%riz), %xmm0 movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 diff --git a/tests/snapshots/asm/float_register_resident.aarch64.asm b/tests/snapshots/asm/float_register_resident.aarch64.asm index 1a11c3dc8..3f9a34553 100644 --- a/tests/snapshots/asm/float_register_resident.aarch64.asm +++ b/tests/snapshots/asm/float_register_resident.aarch64.asm @@ -22,9 +22,11 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s0, d16 sxtw x0, w1 cmp x0, #0xa b.ge @@ -33,18 +35,21 @@ Disassembly of section .text: add x1, x0, #0x1 b sxtw x0, w1 - scvtf d1, x0 - fcvt s1, d1 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d1, s1 - fmov d17, x0 - fmul d1, d1, d17 - fcvt s1, d1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s1, s2, s0 + scvtf d0, x0 + fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 + mov x0, #0x40000000 // =1073741824 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fmadd s0, s0, s17, s1 + sub x17, x29, #0x8 + str s0, [x17] b + sub x16, x29, #0x8 + ldr s0, [x16] fcvt d0, s0 fcvtzs x0, d0 add sp, sp, #0x30 diff --git a/tests/snapshots/asm/float_register_resident.x64.asm b/tests/snapshots/asm/float_register_resident.x64.asm index de37e093a..4ac5f6a4a 100644 --- a/tests/snapshots/asm/float_register_resident.x64.asm +++ b/tests/snapshots/asm/float_register_resident.x64.asm @@ -26,9 +26,10 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 movslq %ecx, %rax cmpq $0xa, %rax jge @@ -37,24 +38,22 @@ Disassembly of section .text: leaq 0x1(%rax), %rcx jmp movslq %ecx, %rax - cvtsi2sd %rax, %xmm1 - cvtsd2ss %xmm1, %xmm1 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm1, %xmm1 + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm15 - mulsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm1, %xmm14 - movapd %xmm2, %xmm15 + mulss %xmm15, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 + movss -0x8(%rbp,%riz), %xmm1 + movapd %xmm0, %xmm14 + movq %rax, %xmm15 + movapd %xmm1, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movss %xmm0, -0x8(%rbp,%riz) jmp + movss -0x8(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax addq $0x30, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_single_precision.aarch64.asm b/tests/snapshots/asm/float_single_precision.aarch64.asm index d88dbd2b9..06a3501c4 100644 --- a/tests/snapshots/asm/float_single_precision.aarch64.asm +++ b/tests/snapshots/asm/float_single_precision.aarch64.asm @@ -13,18 +13,18 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x3ff0000000000000 // =4607182418800017408 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fmov d17, x1 - fdiv d0, d16, d17 - fcvt s0, d0 - mov x0, #0x7c87 // =31879 - movk x0, #0x5fb6, lsl #16 - movk x0, #0x5555, lsl #32 - movk x0, #0x3fd5, lsl #48 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x40400000 // =1077936128 + fmov s16, w0 + fmov s17, w1 + fdiv s0, s16, s17 + mov x0, #0xaaab // =43691 + movk x0, #0x3eaa, lsl #16 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] + sub x16, x29, #0x10 + ldr s1, [x16] fsub s1, s0, s1 mov x0, #0x0 // =0 scvtf d0, x0 @@ -33,13 +33,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0xaf48 // =44872 - movk x0, #0x9abc, lsl #16 - movk x0, #0xd7f2, lsl #32 - movk x0, #0x3e7a, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xbf95 // =49045 + movk x0, #0x33d6, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x1 // =1 @@ -56,9 +53,11 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s0, d16 sxtw x0, w1 cmp x0, #0xa b.ge @@ -66,45 +65,47 @@ Disassembly of section .text: sxtw x0, w1 add x1, x0, #0x1 b - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3fb9, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fadd d0, d0, d17 - fcvt s0, d0 + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0xcccd // =52429 + movk x0, #0x3dcc, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 + sub x17, x29, #0x8 + str s0, [x17] b - mov x0, #0xf29b // =62107 - movk x0, #0x1ad7, lsl #16 - movk x0, #0x3ff0, lsl #48 - fmov d16, x0 - fcvt s1, d16 - fsub s2, s0, s1 + mov x0, #0x1 // =1 + movk x0, #0x3f80, lsl #16 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] + sub x16, x29, #0x18 + ldr s1, [x16] + fsub s1, s0, s1 mov x0, #0x0 // =0 - scvtf d1, x0 - fcvt s1, d1 - fcmp s2, s1 + scvtf d0, x0 + fcvt s0, d0 + fcmp s1, s0 cset x0, mi cbz x0, - fneg s2, s2 - mov x0, #0xed8d // =60813 - movk x0, #0xa0b5, lsl #16 - movk x0, #0xc6f7, lsl #32 - movk x0, #0x3eb0, lsl #48 - fcvt d1, s2 - fmov d17, x0 - fcmp d1, d17 + fneg s1, s1 + mov x0, #0x37bd // =14269 + movk x0, #0x3586, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x2 // =2 add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x8 + ldr s0, [x16] + mov x0, #0x3f800000 // =1065353216 + fmov s17, w0 + fcmp s0, s17 cset x0, eq cbz x0, mov x0, #0x3 // =3 @@ -121,23 +122,19 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x20 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x3ff1, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x3f8c, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] fmul s1, s0, s0 fmul s1, s1, s0 - fmul s0, s1, s0 - mov x0, #0x2012 // =8210 - movk x0, #0x39f9, lsl #16 - movk x0, #0x6cf4, lsl #32 - movk x0, #0x3ff7, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fsub d0, d0, d17 - fcvt s1, d0 + mov x0, #0x67a2 // =26530 + movk x0, #0x3fbb, lsl #16 + fmov s18, w0 + fnmsub s1, s1, s0, s18 mov x0, #0x0 // =0 scvtf d0, x0 fcvt s0, d0 @@ -145,13 +142,10 @@ Disassembly of section .text: cset x0, mi cbz x0, fneg s1, s1 - mov x0, #0x68f1 // =26865 - movk x0, #0x88e3, lsl #16 - movk x0, #0xf8b5, lsl #32 - movk x0, #0x3ee4, lsl #48 - fcvt d0, s1 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xc5ac // =50604 + movk x0, #0x3727, lsl #16 + fmov s17, w0 + fcmp s1, s17 cset x0, gt cbz x0, mov x0, #0x4 // =4 diff --git a/tests/snapshots/asm/float_single_precision.x64.asm b/tests/snapshots/asm/float_single_precision.x64.asm index c7f3f4e9a..690c4b2f1 100644 --- a/tests/snapshots/asm/float_single_precision.x64.asm +++ b/tests/snapshots/asm/float_single_precision.x64.asm @@ -14,15 +14,15 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movl $0x40400000, %ecx # imm = 0x40400000 movq %rcx, %xmm15 movq %rax, %xmm0 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd555555fb67c87, %rax # imm = 0x3FD555555FB67C87 + divss %xmm15, %xmm0 + movl $0x3eaaaaab, %eax # imm = 0x3EAAAAAB movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movss %xmm14, -0x10(%rbp,%riz) + movss -0x10(%rbp,%riz), %xmm1 movapd %xmm1, %xmm15 movapd %xmm0, %xmm1 subss %xmm15, %xmm1 @@ -40,10 +40,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3e7ad7f29abcaf48, %rax # imm = 0x3E7AD7F29ABCAF48 - cvtss2sd %xmm1, %xmm0 + movl $0x33d6bf95, %eax # imm = 0x33D6BF95 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -62,9 +61,10 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 movslq %ecx, %rax cmpq $0xa, %rax jge @@ -72,21 +72,24 @@ Disassembly of section .text: movslq %ecx, %rax leaq 0x1(%rax), %rcx jmp - movabsq $0x3fb999999999999a, %rax # imm = 0x3FB999999999999A - cvtss2sd %xmm0, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3dcccccd, %eax # imm = 0x3DCCCCCD movq %rax, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + addss %xmm15, %xmm0 + movss %xmm0, -0x8(%rbp,%riz) jmp - movabsq $0x3ff000001ad7f29b, %rax # imm = 0x3FF000001AD7F29B + movl $0x3f800001, %eax # imm = 0x3F800001 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movapd %xmm0, %xmm2 - subss %xmm1, %xmm2 + movss %xmm14, -0x18(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 + movss -0x18(%rbp,%riz), %xmm1 + movapd %xmm1, %xmm15 + movapd %xmm0, %xmm1 + subss %xmm15, %xmm1 xorq %rax, %rax - cvtsi2sd %rax, %xmm1 - cvtsd2ss %xmm1, %xmm1 - ucomiss %xmm1, %xmm2 + cvtsi2sd %rax, %xmm0 + cvtsd2ss %xmm0, %xmm0 + ucomiss %xmm0, %xmm1 setb %al movzbq %al, %rax setnp %r10b @@ -96,11 +99,10 @@ Disassembly of section .text: je movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm2 - movabsq $0x3eb0c6f7a0b5ed8d, %rax # imm = 0x3EB0C6F7A0B5ED8D - cvtss2sd %xmm2, %xmm1 + xorpd %xmm15, %xmm1 + movl $0x358637bd, %eax # imm = 0x358637BD movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -109,10 +111,10 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - cvtss2sd %xmm0, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + movl $0x3f800000, %eax # imm = 0x3F800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 sete %al movzbq %al, %rax setnp %r10b @@ -134,20 +136,18 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x20, %rsp - movabsq $0x3ff199999999999a, %rax # imm = 0x3FF199999999999A + movl $0x3f8ccccd, %eax # imm = 0x3F8CCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 movapd %xmm0, %xmm1 mulss %xmm0, %xmm1 mulss %xmm0, %xmm1 + movl $0x3fbb67a2, %eax # imm = 0x3FBB67A2 + movapd %xmm1, %xmm14 movapd %xmm0, %xmm15 - movapd %xmm1, %xmm0 - mulss %xmm15, %xmm0 - movabsq $0x3ff76cf439f92012, %rax # imm = 0x3FF76CF439F92012 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - subsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm1 + movq %rax, %xmm1 + vfmsub231ss %xmm15, %xmm14, %xmm1 # xmm1 = (xmm14 * xmm15) - xmm1 xorq %rax, %rax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 @@ -162,10 +162,9 @@ Disassembly of section .text: movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - movabsq $0x3ee4f8b588e368f1, %rax # imm = 0x3EE4F8B588E368F1 - cvtss2sd %xmm1, %xmm0 + movl $0x3727c5ac, %eax # imm = 0x3727C5AC movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm1 seta %al movzbq %al, %rax testq %rax, %rax @@ -204,4 +203,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_ternary_promote.aarch64.asm b/tests/snapshots/asm/float_ternary_promote.aarch64.asm index 5000596d4..eac2914f9 100644 --- a/tests/snapshots/asm/float_ternary_promote.aarch64.asm +++ b/tests/snapshots/asm/float_ternary_promote.aarch64.asm @@ -30,17 +30,15 @@ Disassembly of section .text: str d8, [sp] str x20, [sp, #0x10] mov x0, #0x1 // =1 - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d1, d16 - fcvt s1, d1 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov s16, w1 + fneg s0, s16 + fmov d1, d0 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -50,16 +48,14 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4004000000000000 // =4612811918334230528 - fmov d16, x1 - fneg d8, d16 - fcvt s1, d8 + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40200000 // =1075838976 + fmov s16, w2 + fneg s8, s16 + fmov d1, d8 + fmov d0, x1 bl - fcvt d0, s0 - fcmp d0, d8 + fcmp s0, s8 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -68,31 +64,40 @@ Disassembly of section .text: add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400a000000000000 // =4614500768194494464 - fmov d16, x0 - fcvt s2, d16 + mov x0, #0x40500000 // =1078984704 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + sub x16, x29, #0x8 + ldr s0, [x16] mov x0, #0x0 // =0 - fcvt d0, s2 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, gt cbz x0, - fmov d0, d2 + sub x16, x29, #0x8 + ldr s0, [x16] b - fneg s0, s2 + sub x16, x29, #0x8 + ldr s0, [x16] + fneg s0, s0 + sub x16, x29, #0x8 + ldr s1, [x16] mov x0, #0x0 // =0 - fcvt d1, s2 - fmov d17, x0 - fcmp d1, d17 + fmov s17, w0 + fcmp s1, s17 cset x0, mi cbz x0, - fneg s2, s2 + sub x16, x29, #0x8 + ldr s1, [x16] + fneg s1, s1 b - fadd s0, s0, s2 - mov x0, #0x401a000000000000 // =4619004367821864960 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x8 + ldr s1, [x16] + fadd s0, s0, s1 + mov x0, #0x40d00000 // =1087373312 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 @@ -105,36 +110,34 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x0 // =0 - fmov d16, x0 + fmov s16, w0 sub x17, x29, #0x38 - str d16, [x17] + str s16, [x17] b cmp x0, #0x1 b.ne b sub x16, x29, #0x38 - ldr d0, [x16] - fcvt s0, d0 - mov x0, #0x4034000000000000 // =4626322717216342016 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + ldr s0, [x16] + mov x0, #0x41a00000 // =1101004800 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, b - mov x0, #0x4024000000000000 // =4621819117588971520 - fmov d16, x0 + mov x0, #0x41200000 // =1092616192 + fmov s16, w0 sub x17, x29, #0x40 - str d16, [x17] + str s16, [x17] b - mov x0, #0x4034000000000000 // =4626322717216342016 - fmov d16, x0 + mov x0, #0x41a00000 // =1101004800 + fmov s16, w0 sub x17, x29, #0x40 - str d16, [x17] + str s16, [x17] sub x16, x29, #0x40 - ldr d0, [x16] + ldr s0, [x16] sub x17, x29, #0x38 - str d0, [x17] + str s0, [x17] b mov x0, #0x4 // =4 ldr x20, [sp, #0x10] diff --git a/tests/snapshots/asm/float_ternary_promote.x64.asm b/tests/snapshots/asm/float_ternary_promote.x64.asm index 4baa9b1e4..81e8c6d18 100644 --- a/tests/snapshots/asm/float_ternary_promote.x64.asm +++ b/tests/snapshots/asm/float_ternary_promote.x64.asm @@ -31,19 +31,17 @@ Disassembly of section .text: subq $0x60, %rsp movq %rbx, (%rsp) movl $0x1, %edi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %eax # imm = 0x40200000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 + movapd %xmm0, %xmm1 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -57,21 +55,18 @@ Disassembly of section .text: popq %rbp retq xorq %rdi, %rdi - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x3fc00000, %esi # imm = 0x3FC00000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm14 movsd %xmm14, 0x18(%rsp) - movsd 0x18(%rsp), %xmm14 - cvtsd2ss %xmm14, %xmm1 + movq %rsi, %xmm0 + movsd 0x18(%rsp), %xmm1 callq - cvtss2sd %xmm0, %xmm0 movsd 0x18(%rsp), %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -84,27 +79,27 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movabsq $0x400a000000000000, %rax # imm = 0x400A000000000000 + movl $0x40500000, %eax # imm = 0x40500000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 + movss %xmm14, -0x8(%rbp,%riz) + movss -0x8(%rbp,%riz), %xmm0 xorq %rax, %rax - cvtss2sd %xmm2, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 seta %al movzbq %al, %rax testq %rax, %rax je - movapd %xmm2, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 jmp - movapd %xmm2, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 + movss -0x8(%rbp,%riz), %xmm1 xorq %rax, %rax - cvtss2sd %xmm2, %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm1 setb %al movzbq %al, %rax setnp %r10b @@ -112,15 +107,16 @@ Disassembly of section .text: andq %r10, %rax testq %rax, %rax je + movss -0x8(%rbp,%riz), %xmm1 movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm2 + xorpd %xmm15, %xmm1 jmp - addss %xmm2, %xmm0 - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 - cvtss2sd %xmm0, %xmm0 + movss -0x8(%rbp,%riz), %xmm1 + addss %xmm1, %xmm0 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -138,17 +134,15 @@ Disassembly of section .text: jne xorq %rax, %rax movq %rax, %xmm14 - movsd %xmm14, -0x38(%rbp,%riz) + movss %xmm14, -0x38(%rbp,%riz) jmp cmpq $0x1, %rax jne jmp - movsd -0x38(%rbp,%riz), %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4034000000000000, %rax # imm = 0x4034000000000000 - cvtss2sd %xmm0, %xmm0 + movss -0x38(%rbp,%riz), %xmm0 + movl $0x41a00000, %eax # imm = 0x41A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -157,15 +151,15 @@ Disassembly of section .text: testq %rax, %rax je jmp - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) + movss %xmm14, -0x40(%rbp,%riz) jmp - movabsq $0x4034000000000000, %rax # imm = 0x4034000000000000 + movl $0x41a00000, %eax # imm = 0x41A00000 movq %rax, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) - movsd -0x40(%rbp,%riz), %xmm0 - movsd %xmm0, -0x38(%rbp,%riz) + movss %xmm14, -0x40(%rbp,%riz) + movss -0x40(%rbp,%riz), %xmm0 + movss %xmm0, -0x38(%rbp,%riz) jmp movl $0x4, %eax movq (%rsp), %rbx @@ -178,4 +172,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/float_variadic_promotion.aarch64.asm b/tests/snapshots/asm/float_variadic_promotion.aarch64.asm index e0ea58670..14da75eef 100644 --- a/tests/snapshots/asm/float_variadic_promotion.aarch64.asm +++ b/tests/snapshots/asm/float_variadic_promotion.aarch64.asm @@ -115,31 +115,33 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x60 - str d8, [sp] - str d9, [sp, #0x8] - str x20, [sp, #0x10] - mov x20, #0xe148 // =57672 - movk x20, #0x147a, lsl #16 - movk x20, #0x47ae, lsl #32 - movk x20, #0x4051, lsl #48 - fmov d16, x20 - fcvt s8, d16 - mov x0, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x0 - fcvt s9, d16 + sub sp, sp, #0x50 + str x20, [sp] + mov x0, #0x3d71 // =15729 + movk x0, #0x428a, lsl #16 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] + mov x0, #0x3fc00000 // =1069547520 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] mov x0, #0x1 // =1 - fcvt d0, s8 + sub x16, x29, #0x8 + ldr s0, [x16] + fcvt d0, s0 bl - fmov d1, x20 + mov x0, #0xe148 // =57672 + movk x0, #0x147a, lsl #16 + movk x0, #0x47ae, lsl #32 + movk x0, #0x4051, lsl #48 + fmov d1, x0 bl cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 + ldr x20, [sp] + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 @@ -153,15 +155,17 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x2 // =2 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 + ldr x20, [sp] + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x2 // =2 - fcvt d0, s8 - fcvt d1, s9 + sub x16, x29, #0x8 + ldr s0, [x16] + fcvt d0, s0 + sub x16, x29, #0x10 + ldr s1, [x16] + fcvt d1, s1 bl mov x0, #0xe148 // =57672 movk x0, #0x147a, lsl #16 @@ -172,17 +176,19 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x3 // =3 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 + ldr x20, [sp] + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 mov x1, #0xa // =10 scvtf d0, x1 - fcvt d1, s8 - fcvt d2, s9 + sub x16, x29, #0x8 + ldr s1, [x16] + fcvt d1, s1 + sub x16, x29, #0x10 + ldr s2, [x16] + fcvt d2, s2 bl mov x0, #0xe148 // =57672 movk x0, #0x147a, lsl #16 @@ -193,16 +199,12 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x4 // =4 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 + ldr x20, [sp] + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr d8, [sp] - ldr d9, [sp, #0x8] - add sp, sp, #0x60 + ldr x20, [sp] + add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/float_variadic_promotion.x64.asm b/tests/snapshots/asm/float_variadic_promotion.x64.asm index 43f790af3..85fabba1f 100644 --- a/tests/snapshots/asm/float_variadic_promotion.x64.asm +++ b/tests/snapshots/asm/float_variadic_promotion.x64.asm @@ -103,28 +103,27 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x50, %rsp movq %rbx, (%rsp) - movabsq $0x405147ae147ae148, %rbx # imm = 0x405147AE147AE148 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x18(%rsp) - movabsq $0x3ff8000000000000, %rax # imm = 0x3FF8000000000000 + movl $0x428a3d71, %eax # imm = 0x428A3D71 + movq %rax, %xmm14 + movss %xmm14, -0x8(%rbp,%riz) + movl $0x3fc00000, %eax # imm = 0x3FC00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x10(%rsp) + movss %xmm14, -0x10(%rbp,%riz) movl $0x1, %edi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movss -0x8(%rbp,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq - movq %rbx, %xmm1 + movabsq $0x405147ae147ae148, %rdi # imm = 0x405147AE147AE148 + movq %rdi, %xmm1 callq testq %rax, %rax jne movl $0x1, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x1, %edi @@ -140,14 +139,14 @@ Disassembly of section .text: jne movl $0x2, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x2, %edi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 - movsd 0x10(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm1 + movss -0x8(%rbp,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 + movss -0x10(%rbp,%riz), %xmm1 + cvtss2sd %xmm1, %xmm1 movb $0x2, %al callq movabsq $0x4051a7ae147ae148, %rdi # imm = 0x4051A7AE147AE148 @@ -157,16 +156,16 @@ Disassembly of section .text: jne movl $0x3, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq movl $0x3, %edi movl $0xa, %eax cvtsi2sd %rax, %xmm0 - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm1 - movsd 0x10(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm2 + movss -0x8(%rbp,%riz), %xmm1 + cvtss2sd %xmm1, %xmm1 + movss -0x10(%rbp,%riz), %xmm2 + cvtss2sd %xmm2, %xmm2 movb $0x3, %al callq movabsq $0x405427ae147ae148, %rdi # imm = 0x405427AE147AE148 @@ -176,12 +175,12 @@ Disassembly of section .text: jne movl $0x4, %eax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/fma_contraction.aarch64.asm b/tests/snapshots/asm/fma_contraction.aarch64.asm index d722c4b08..184056814 100644 --- a/tests/snapshots/asm/fma_contraction.aarch64.asm +++ b/tests/snapshots/asm/fma_contraction.aarch64.asm @@ -90,55 +90,43 @@ Disassembly of section .text: cbz x0, mov x0, #0x3 // =3 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s2, d16 - fnmsub s0, s0, s1, s2 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fnmsub s0, s16, s17, s18 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s2, d16 - fmsub s0, s0, s1, s2 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmsub s0, s16, s17, s18 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x6 // =6 @@ -156,19 +144,15 @@ Disassembly of section .text: cbz x0, mov x0, #0x7 // =7 ret - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s1, d16 - mov x1, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x1 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + mov x1, #0x3e800000 // =1048576000 + mov x2, #0x3e000000 // =1040187392 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 @@ -200,20 +184,16 @@ Disassembly of section .text: cbz x0, mov x0, #0xa // =10 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s2, d16 - fmadd s0, s0, s1, s2 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + mov x2, #0x40800000 // =1082130432 + fmov s16, w0 + fmov s17, w1 + fmov s18, w2 + fmadd s0, s16, s17, s18 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xb // =11 diff --git a/tests/snapshots/asm/fma_contraction.x64.asm b/tests/snapshots/asm/fma_contraction.x64.asm index 5ccfa7191..f98520e9f 100644 --- a/tests/snapshots/asm/fma_contraction.x64.asm +++ b/tests/snapshots/asm/fma_contraction.x64.asm @@ -126,23 +126,16 @@ Disassembly of section .text: je movl $0x3, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -152,22 +145,15 @@ Disassembly of section .text: je movl $0x4, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmsub231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) - xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,25 +163,18 @@ Disassembly of section .text: je movl $0x5, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfnmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = -(xmm14 * xmm15) + xmm0 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -223,22 +202,15 @@ Disassembly of section .text: je movl $0x7, %eax retq - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3f000000, %eax # imm = 0x3F000000 + movl $0x3e800000, %ecx # imm = 0x3E800000 + movl $0x3e000000, %edx # imm = 0x3E000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x3fc0000000000000, %rcx # imm = 0x3FC0000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + movq %rcx, %xmm15 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -285,23 +257,16 @@ Disassembly of section .text: je movl $0xa, %eax retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movl $0x40000000, %eax # imm = 0x40000000 + movl $0x40400000, %ecx # imm = 0x40400000 + movl $0x40800000, %edx # imm = 0x40800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movapd %xmm0, %xmm14 - movapd %xmm1, %xmm15 - movapd %xmm2, %xmm0 + movq %rcx, %xmm15 + movq %rdx, %xmm0 vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -336,4 +301,3 @@ Disassembly of section .text: xorq %rax, %rax retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm index 3f5f29da9..d55259124 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg.aarch64.asm @@ -13,10 +13,10 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fmul s0, s0, s17 fcvt d0, s0 - fmov d17, x0 - fmul d0, d0, d17 fcvtzs x0, d0 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 @@ -74,11 +74,8 @@ Disassembly of section .text: str x19, [sp, #0x10] adrp x20, add x20, x20, - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x40200000 // =1075838976 + str x0, [sp, #-0x10]! mov x9, x20 ldr d0, [sp] blr x9 @@ -95,11 +92,8 @@ Disassembly of section .text: adrp x0, add x0, x0, mov x1, #0x3 // =3 - mov x2, #0x4012000000000000 // =4616752568008179712 - fmov d16, x2 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x2, #0x40900000 // =1083179008 + str x2, [sp, #-0x10]! str x1, [sp, #-0x10]! mov x9, x0 ldr x0, [sp] @@ -118,9 +112,8 @@ Disassembly of section .text: mov x0, #0xa // =10 adrp x1, add x1, x1, - mov x2, #0x4004000000000000 // =4612811918334230528 - fmov d16, x2 - fcvt s0, d16 + mov x2, #0x40200000 // =1075838976 + fmov d0, x2 bl cmp x0, #0xc b.eq @@ -130,11 +123,8 @@ Disassembly of section .text: add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x0, #0x40600000 // =1080033280 + str x0, [sp, #-0x10]! mov x9, x20 ldr d0, [sp] blr x9 diff --git a/tests/snapshots/asm/fn_ptr_float_arg.x64.asm b/tests/snapshots/asm/fn_ptr_float_arg.x64.asm index 450fb0832..dcb59fe32 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg.x64.asm @@ -14,10 +14,10 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - mulsd %xmm15, %xmm0 + mulss %xmm15, %xmm0 + cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax addq $0x10, %rsp popq %rbp @@ -65,10 +65,9 @@ Disassembly of section .text: subq $0x40, %rsp movq %rbx, (%rsp) leaq -, %rbx # - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edi # imm = 0x40200000 movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x5, %rax @@ -80,9 +79,8 @@ Disassembly of section .text: retq leaq -, %rax # movl $0x3, %edi - movabsq $0x4012000000000000, %rcx # imm = 0x4012000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40900000, %esi # imm = 0x40900000 + movq %rsi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x7, %rax @@ -94,9 +92,8 @@ Disassembly of section .text: retq movl $0xa, %edi leaq -, %rsi # - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edx # imm = 0x40200000 + movq %rdx, %xmm0 callq cmpq $0xc, %rax je @@ -105,10 +102,9 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40600000, %edi # imm = 0x40600000 movq %rbx, %rax + movq %rdi, %xmm0 callq *%rax movslq %eax, %rax cmpq $0x7, %rax @@ -124,3 +120,4 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm index fd5140825..9d2a4c8fb 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg_narrow.aarch64.asm @@ -13,11 +13,9 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x10 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fmul d0, d0, d17 - fcvt s0, d0 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fmul s0, s0, s17 add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret @@ -57,19 +55,15 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x10 ldr x0, [x0] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -80,19 +74,15 @@ Disassembly of section .text: ret sub x0, x29, #0x10 ldr x0, [x0, #0x8] - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x20, #0x40400000 // =1077936128 + str x20, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -104,19 +94,15 @@ Disassembly of section .text: mov x0, #0x0 // =0 sub x1, x29, #0x10 ldr x0, [x1, x0, lsl #3] - mov x1, #0x4010000000000000 // =4616189618054758400 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40800000 // =1082130432 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4020000000000000 // =4620693217682128896 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41000000 // =1090519040 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 @@ -134,25 +120,18 @@ Disassembly of section .text: ldr x10, [sp], #0x10 sub x0, x29, #0x50 ldr x0, [x0] - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - fmov x16, d1 - str x16, [sp, #-0x10]! - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40000000 // =1073741824 + str x2, [sp, #-0x10]! + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] ldr d1, [sp, #0x10] blr x9 add sp, sp, #0x20 - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 @@ -163,19 +142,15 @@ Disassembly of section .text: ret adrp x0, add x0, x0, - mov x1, #0x4014000000000000 // =4617315517961601024 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40a00000 // =1084227584 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x5 // =5 @@ -184,21 +159,23 @@ Disassembly of section .text: add sp, sp, #0x110 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40e00000 // =1088421888 + fmov s16, w0 + sub x17, x29, #0x88 + str s16, [x17] sub x0, x29, #0x10 ldr x0, [x0] + sub x16, x29, #0x88 + ldr s0, [x16] fmov x16, d0 str x16, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x402c000000000000 // =4624070917402656768 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41600000 // =1096810496 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 @@ -219,19 +196,15 @@ Disassembly of section .text: sub x20, x29, #0xa8 sub x0, x29, #0xa8 ldr x0, [x0] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 @@ -241,19 +214,15 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldr x0, [x20] - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s0, d16 - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x40400000 // =1077936128 + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4018000000000000 // =4618441417868443648 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40c00000 // =1086324736 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 @@ -263,25 +232,18 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret ldr x0, [x20, #0x8] - mov x1, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4000000000000000 // =4611686018427387904 - fmov d16, x1 - fcvt s1, d16 - fmov x16, d1 - str x16, [sp, #-0x10]! - fmov x16, d0 - str x16, [sp, #-0x10]! + mov x1, #0x3fc00000 // =1069547520 + mov x2, #0x40000000 // =1073741824 + str x2, [sp, #-0x10]! + str x1, [sp, #-0x10]! mov x9, x0 ldr d0, [sp] ldr d1, [sp, #0x10] blr x9 add sp, sp, #0x20 - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 diff --git a/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm b/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm index d10e5f1ad..343e9c029 100644 --- a/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_arg_narrow.x64.asm @@ -14,11 +14,9 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x10, %rsp - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - mulsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + mulss %xmm15, %xmm0 addq $0x10, %rsp popq %rbp retq @@ -58,14 +56,12 @@ Disassembly of section .text: popq %rdx leaq -0x10(%rbp), %rax movq (%rax), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -80,16 +76,14 @@ Disassembly of section .text: retq leaq -0x10(%rbp), %rax movq 0x8(%rax), %rax - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %ebx # imm = 0x40400000 + movq %rbx, %xmm0 callq *%rax movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -105,14 +99,12 @@ Disassembly of section .text: xorq %rax, %rax leaq -0x10(%rbp), %rcx movq (%rcx,%rax,8), %rax - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40800000, %edi # imm = 0x40800000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4020000000000000, %rax # imm = 0x4020000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41000000, %eax # imm = 0x41000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -133,17 +125,14 @@ Disassembly of section .text: popq %rdx leaq -0x50(%rbp), %rax movq (%rax), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %edi # imm = 0x3FC00000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq *%rax - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -157,14 +146,12 @@ Disassembly of section .text: popq %rbp retq leaq -, %rax # - movabsq $0x4014000000000000, %rcx # imm = 0x4014000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,16 +164,16 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x88(%rbp,%riz) leaq -0x10(%rbp), %rax movq (%rax), %rax + movss -0x88(%rbp,%riz), %xmm0 callq *%rax - movabsq $0x402c000000000000, %rax # imm = 0x402C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41600000, %eax # imm = 0x41600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -210,14 +197,12 @@ Disassembly of section .text: leaq -0xa8(%rbp), %rbx leaq -0xa8(%rbp), %rax movq (%rax), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -231,14 +216,12 @@ Disassembly of section .text: popq %rbp retq movq (%rbx), %rax - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40400000, %edi # imm = 0x40400000 + movq %rdi, %xmm0 callq *%rax - movabsq $0x4018000000000000, %rax # imm = 0x4018000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40c00000, %eax # imm = 0x40C00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -252,17 +235,14 @@ Disassembly of section .text: popq %rbp retq movq 0x8(%rbx), %rax - movabsq $0x3ff8000000000000, %rcx # imm = 0x3FF8000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %edi # imm = 0x3FC00000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq *%rax - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -280,4 +260,4 @@ Disassembly of section .text: addq $0x100, %rsp # imm = 0x100 popq %rbp retq - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm b/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm index 206e7029b..6073d0bc7 100644 --- a/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm +++ b/tests/snapshots/asm/fn_ptr_float_return.aarch64.asm @@ -10,18 +10,17 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40200000 // =1075838976 + fmov d0, x0 ret : sxtw x0, w0 scvtf d0, x0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d17, x0 - fmul d0, d0, d17 fcvt s0, d0 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fmul s0, s0, s17 ret : @@ -49,10 +48,9 @@ Disassembly of section .text: add x20, x20, mov x9, x20 blr x9 - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -69,10 +67,9 @@ Disassembly of section .text: ldr x0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -89,10 +86,9 @@ Disassembly of section .text: ldr d0, [sp] blr x9 add sp, sp, #0x10 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 @@ -103,10 +99,9 @@ Disassembly of section .text: ret mov x9, x20 blr x9 - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 diff --git a/tests/snapshots/asm/fn_ptr_float_return.x64.asm b/tests/snapshots/asm/fn_ptr_float_return.x64.asm index 2bd89bee7..11223ab74 100644 --- a/tests/snapshots/asm/fn_ptr_float_return.x64.asm +++ b/tests/snapshots/asm/fn_ptr_float_return.x64.asm @@ -11,18 +11,18 @@ Disassembly of section .text: ud2 : - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movapd %xmm14, %xmm0 retq : movslq %edi, %rdi cvtsi2sd %rdi, %xmm0 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - movq %rax, %xmm15 - mulsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 + movq %rax, %xmm15 + mulss %xmm15, %xmm0 retq : @@ -48,10 +48,9 @@ Disassembly of section .text: leaq -, %rbx # movq %rbx, %rax callq *%rax - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -67,10 +66,9 @@ Disassembly of section .text: leaq -, %rax # movl $0xa, %edi callq *%rax - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -87,10 +85,9 @@ Disassembly of section .text: movabsq $0x4000000000000000, %rdi # imm = 0x4000000000000000 movq %rdi, %xmm0 callq *%rax - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -105,10 +102,9 @@ Disassembly of section .text: retq movq %rbx, %rax callq *%rax - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -144,4 +140,3 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/fp_const_return.aarch64.asm b/tests/snapshots/asm/fp_const_return.aarch64.asm index 389391b90..b10afceab 100644 --- a/tests/snapshots/asm/fp_const_return.aarch64.asm +++ b/tests/snapshots/asm/fp_const_return.aarch64.asm @@ -54,9 +54,8 @@ Disassembly of section .text: ret : - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3e800000 // =1048576000 + fmov d0, x0 ret : @@ -177,10 +176,9 @@ Disassembly of section .text: sub x0, x29, #0x10 mov x1, #0x2 // =2 bl - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 + mov x0, #0x3e800000 // =1048576000 + fmov s16, w0 + fcvt d0, s16 mov x0, #0x3fd0000000000000 // =4598175219545276416 fmov d17, x0 fcmp d0, d17 diff --git a/tests/snapshots/asm/fp_const_return.x64.asm b/tests/snapshots/asm/fp_const_return.x64.asm index 78b7fdb33..2606614c8 100644 --- a/tests/snapshots/asm/fp_const_return.x64.asm +++ b/tests/snapshots/asm/fp_const_return.x64.asm @@ -55,9 +55,9 @@ Disassembly of section .text: retq : - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3e800000, %eax # imm = 0x3E800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movapd %xmm14, %xmm0 retq : @@ -195,10 +195,9 @@ Disassembly of section .text: leaq -0x10(%rbp), %rdi movl $0x2, %esi callq - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 + movl $0x3e800000, %eax # imm = 0x3E800000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 movq %rax, %xmm15 ucomisd %xmm15, %xmm0 @@ -237,4 +236,5 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm b/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm index e27ae1726..73a3b2902 100644 --- a/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm +++ b/tests/snapshots/asm/fp_load_folded_disp.aarch64.asm @@ -41,31 +41,28 @@ Disassembly of section .text: movk x1, #0xffff, lsl #48 str x1, [x0] sub x0, x29, #0x28 - mov x1, #0x3ff4000000000000 // =4608308318706860032 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0, #0x8] + mov x1, #0x3fa00000 // =1067450368 + fmov s16, w1 + str s16, [x0, #0x8] sub x0, x29, #0x28 mov x2, #0x4004000000000000 // =4612811918334230528 fmov d16, x2 str d16, [x0, #0x10] sub x0, x29, #0x28 mov x2, #0x0 // =0 - fmov d16, x2 - fcvt s0, d16 - str s0, [x0, #0x18] + fmov s16, w2 + str s16, [x0, #0x18] sub x0, x29, #0x28 - str s0, [x0, #0x1c] + fmov s16, w2 + str s16, [x0, #0x1c] sub x0, x29, #0x28 - mov x2, #0x4013000000000000 // =4617034042984890368 - fmov d16, x2 - fcvt s0, d16 - str s0, [x0, #0x20] + mov x2, #0x40980000 // =1083703296 + fmov s16, w2 + str s16, [x0, #0x20] sub x0, x29, #0x28 ldr s0, [x0, #0x8] - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -85,10 +82,9 @@ Disassembly of section .text: ret sub x0, x29, #0x28 ldr s0, [x0, #0x20] - mov x0, #0x4013000000000000 // =4617034042984890368 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40980000 // =1083703296 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/fp_load_folded_disp.x64.asm b/tests/snapshots/asm/fp_load_folded_disp.x64.asm index e20c64f57..e8f521500 100644 --- a/tests/snapshots/asm/fp_load_folded_disp.x64.asm +++ b/tests/snapshots/asm/fp_load_folded_disp.x64.asm @@ -39,10 +39,9 @@ Disassembly of section .text: movabsq $-0x1, %rcx movq %rcx, (%rax) leaq -0x28(%rbp), %rax - movabsq $0x3ff4000000000000, %rcx # imm = 0x3FF4000000000000 + movl $0x3fa00000, %ecx # imm = 0x3FA00000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x8(%rax,%riz) + movss %xmm14, 0x8(%rax,%riz) leaq -0x28(%rbp), %rax movabsq $0x4004000000000000, %rdx # imm = 0x4004000000000000 movq %rdx, %xmm14 @@ -50,20 +49,18 @@ Disassembly of section .text: leaq -0x28(%rbp), %rax xorq %rdx, %rdx movq %rdx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x18(%rax,%riz) + movss %xmm14, 0x18(%rax,%riz) leaq -0x28(%rbp), %rax - movss %xmm0, 0x1c(%rax,%riz) + movq %rdx, %xmm14 + movss %xmm14, 0x1c(%rax,%riz) leaq -0x28(%rbp), %rax - movabsq $0x4013000000000000, %rdx # imm = 0x4013000000000000 + movl $0x40980000, %edx # imm = 0x40980000 movq %rdx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, 0x20(%rax,%riz) + movss %xmm14, 0x20(%rax,%riz) leaq -0x28(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -93,10 +90,9 @@ Disassembly of section .text: retq leaq -0x28(%rbp), %rax movss 0x20(%rax,%riz), %xmm0 - movabsq $0x4013000000000000, %rax # imm = 0x4013000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40980000, %eax # imm = 0x40980000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -131,4 +127,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm b/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm index 8db5ed786..9799a3378 100644 --- a/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm +++ b/tests/snapshots/asm/fp_param_float_before_double.aarch64.asm @@ -52,40 +52,36 @@ Disassembly of section .text: ret
: - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s16, w0 + fmov s17, w0 + fcmp s16, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 ret - mov x0, #0x401a000000000000 // =4619004367821864960 - fmov d16, x0 - fcvt s0, d16 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40d00000 // =1087373312 + fmov s16, w0 + fcvt d0, s16 + fmov s16, w0 + fcvt d1, s16 + fcmp d0, d1 cset x0, ne cbz x0, mov x0, #0x2 // =2 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - mov x1, #0x4008000000000000 // =4613937818241073152 - fmov d16, x1 - fcvt s1, d16 - mov x1, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x4000000000000000 // =4611686018427387904 + mov x2, #0x40400000 // =1077936128 + mov x3, #0x4010000000000000 // =4616189618054758400 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fadd d0, d0, d17 - fcvt d1, s1 + fmov s16, w2 + fcvt d1, s16 fadd d0, d0, d1 - fmov d17, x1 + fmov d17, x3 fadd d0, d0, d17 mov x0, #0x4024000000000000 // =4621819117588971520 fmov d17, x0 @@ -95,13 +91,12 @@ Disassembly of section .text: mov x0, #0x3 // =3 ret mov x0, #0x4014000000000000 // =4617315517961601024 - mov x1, #0x4018000000000000 // =4618441417868443648 - fmov d16, x1 - fcvt s0, d16 - mov x1, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 + mov x1, #0x40c00000 // =1086324736 + mov x2, #0x4024000000000000 // =4621819117588971520 + fmov s16, w1 + fcvt d0, s16 fmov d16, x0 - fmov d17, x1 + fmov d17, x2 fmadd d0, d16, d17, d0 mov x0, #0x404c000000000000 // =4633078116657397760 fmov d17, x0 diff --git a/tests/snapshots/asm/fp_param_float_before_double.x64.asm b/tests/snapshots/asm/fp_param_float_before_double.x64.asm index e5973e9d2..6f2442f58 100644 --- a/tests/snapshots/asm/fp_param_float_before_double.x64.asm +++ b/tests/snapshots/asm/fp_param_float_before_double.x64.asm @@ -55,12 +55,10 @@ Disassembly of section .text: retq
: - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setne %al movzbq %al, %rax setp %r10b @@ -70,12 +68,12 @@ Disassembly of section .text: je movl $0x1, %eax retq - movabsq $0x401a000000000000, %rax # imm = 0x401A000000000000 + movl $0x40d00000, %eax # imm = 0x40D00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + cvtss2sd %xmm14, %xmm0 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 + ucomisd %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -85,20 +83,18 @@ Disassembly of section .text: je movl $0x2, %eax retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movabsq $0x4000000000000000, %rcx # imm = 0x4000000000000000 + movl $0x40400000, %edx # imm = 0x40400000 + movabsq $0x4010000000000000, %rsi # imm = 0x4010000000000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 addsd %xmm15, %xmm0 - cvtss2sd %xmm1, %xmm1 + movq %rdx, %xmm14 + cvtss2sd %xmm14, %xmm1 addsd %xmm1, %xmm0 - movq %rcx, %xmm15 + movq %rsi, %xmm15 addsd %xmm15, %xmm0 movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 movq %rax, %xmm15 @@ -113,13 +109,12 @@ Disassembly of section .text: movl $0x3, %eax retq movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movabsq $0x4018000000000000, %rcx # imm = 0x4018000000000000 + movl $0x40c00000, %ecx # imm = 0x40C00000 + movabsq $0x4024000000000000, %rdx # imm = 0x4024000000000000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4024000000000000, %rcx # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %rax, %xmm14 - movq %rcx, %xmm15 + movq %rdx, %xmm15 vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 movabsq $0x404c000000000000, %rax # imm = 0x404C000000000000 movq %rax, %xmm15 @@ -135,3 +130,5 @@ Disassembly of section .text: retq xorq %rax, %rax retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/fp_param_ternary.aarch64.asm b/tests/snapshots/asm/fp_param_ternary.aarch64.asm index f6301b43a..1ceffc1b1 100644 --- a/tests/snapshots/asm/fp_param_ternary.aarch64.asm +++ b/tests/snapshots/asm/fp_param_ternary.aarch64.asm @@ -53,14 +53,12 @@ Disassembly of section .text: str x20, [sp] str x21, [sp, #0x8] mov x0, #0x0 // =0 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -70,13 +68,11 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -86,14 +82,12 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x2 // =2 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x3 // =3 @@ -103,13 +97,11 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 - mov x20, #0x4014000000000000 // =4617315517961601024 - fmov d16, x20 - fcvt s0, d16 + mov x20, #0x40a00000 // =1084227584 + fmov d0, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 @@ -119,19 +111,16 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x4004000000000000 // =4612811918334230528 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x21, #0x40200000 // =1075838976 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x21 - fneg d1, d16 - fmov d16, x20 - fadd d1, d16, d1 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w21 + fneg s1, s16 + fmov s16, w20 + fadd s1, s16, s1 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x5 // =5 @@ -141,19 +130,16 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x2 // =2 - mov x20, #0x401d000000000000 // =4619848792751996928 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x3fc0000000000000 // =4593671619917905920 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x40e80000 // =1088946176 + mov x21, #0x3e000000 // =1040187392 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x20 - fneg d1, d16 - fmov d17, x21 - fadd d1, d1, d17 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fmov s17, w21 + fadd s1, s1, s17 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x6 // =6 @@ -163,18 +149,15 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s0, d16 - mov x21, #0x4010000000000000 // =4616189618054758400 - fmov d16, x21 - fcvt s1, d16 + mov x20, #0x40400000 // =1077936128 + mov x21, #0x40800000 // =1082130432 + fmov d0, x20 + fmov d1, x21 bl - fmov d16, x20 - fmov d17, x21 - fadd d1, d16, d17 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fmov s17, w21 + fadd s1, s16, s17 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x7 // =7 diff --git a/tests/snapshots/asm/fp_param_ternary.x64.asm b/tests/snapshots/asm/fp_param_ternary.x64.asm index 69f2cee19..e057d6315 100644 --- a/tests/snapshots/asm/fp_param_ternary.x64.asm +++ b/tests/snapshots/asm/fp_param_ternary.x64.asm @@ -64,16 +64,14 @@ Disassembly of section .text: movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -88,13 +86,11 @@ Disassembly of section .text: popq %rbp retq movl $0x1, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,16 +105,14 @@ Disassembly of section .text: popq %rbp retq movl $0x2, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -133,13 +127,11 @@ Disassembly of section .text: popq %rbp retq movl $0x3, %edi - movabsq $0x4014000000000000, %rbx # imm = 0x4014000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %ebx # imm = 0x40A00000 + movq %rbx, %xmm0 callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -154,22 +146,19 @@ Disassembly of section .text: popq %rbp retq movl $0x1, %edi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %r12 # imm = 0x4004000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %r12d # imm = 0x40200000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %r12, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 movapd %xmm1, %xmm15 movq %rbx, %xmm1 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -184,21 +173,18 @@ Disassembly of section .text: popq %rbp retq movl $0x2, %edi - movabsq $0x401d000000000000, %rbx # imm = 0x401D000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x3fc0000000000000, %r12 # imm = 0x3FC0000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40e80000, %ebx # imm = 0x40E80000 + movl $0x3e000000, %r12d # imm = 0x3E000000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 movq %r12, %xmm15 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -213,18 +199,15 @@ Disassembly of section .text: popq %rbp retq movl $0x3, %edi - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %r12 # imm = 0x4010000000000000 - movq %r12, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40400000, %ebx # imm = 0x40400000 + movl $0x40800000, %r12d # imm = 0x40800000 + movq %rbx, %xmm0 + movq %r12, %xmm1 callq movq %r12, %xmm15 movq %rbx, %xmm1 - addsd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + addss %xmm15, %xmm1 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/fp_return_value.aarch64.asm b/tests/snapshots/asm/fp_return_value.aarch64.asm index 4306327ab..d467f8e54 100644 --- a/tests/snapshots/asm/fp_return_value.aarch64.asm +++ b/tests/snapshots/asm/fp_return_value.aarch64.asm @@ -21,11 +21,9 @@ Disassembly of section .text: sxtw x0, w0 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fdiv d0, d0, d17 - fcvt s0, d0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s0, s0, s17 ret
: @@ -58,25 +56,20 @@ Disassembly of section .text: sxtw x0, w0 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fdiv d0, d0, d17 - fcvt s0, d0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s0, s0, s17 mov x0, #0x5 // =5 sxtw x0, w0 scvtf d1, x0 fcvt s1, d1 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x0 - fdiv d1, d1, d17 - fcvt s1, d1 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fdiv s1, s1, s17 fadd s0, s0, s1 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -94,11 +87,9 @@ Disassembly of section .text: sxtw x1, w1 scvtf d1, x1 fcvt s1, d1 - mov x1, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x1 - fdiv d1, d1, d17 - fcvt s1, d1 + mov x1, #0x40800000 // =1082130432 + fmov s17, w1 + fdiv s1, s1, s17 fcvt d1, s1 fmov d17, x0 fmadd d0, d0, d17, d1 diff --git a/tests/snapshots/asm/fp_return_value.x64.asm b/tests/snapshots/asm/fp_return_value.x64.asm index 53562e005..3828e085d 100644 --- a/tests/snapshots/asm/fp_return_value.x64.asm +++ b/tests/snapshots/asm/fp_return_value.x64.asm @@ -22,11 +22,9 @@ Disassembly of section .text: movslq %edi, %rdi cvtsi2sd %rdi, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + divss %xmm15, %xmm0 retq
: @@ -64,25 +62,20 @@ Disassembly of section .text: movslq %eax, %rax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + divss %xmm15, %xmm0 movl $0x5, %eax movslq %eax, %rax cvtsi2sd %rax, %xmm1 cvtsd2ss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - divsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + divss %xmm15, %xmm1 addss %xmm1, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -105,11 +98,9 @@ Disassembly of section .text: movslq %ecx, %rcx cvtsi2sd %rcx, %xmm1 cvtsd2ss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rcx # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + movl $0x40800000, %ecx # imm = 0x40800000 movq %rcx, %xmm15 - divsd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + divss %xmm15, %xmm1 cvtss2sd %xmm1, %xmm1 movapd %xmm0, %xmm14 movq %rax, %xmm15 @@ -133,4 +124,3 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm b/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm index d519d9694..81f2beb1b 100644 --- a/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm +++ b/tests/snapshots/asm/fp_unary_intrinsic.aarch64.asm @@ -14,14 +14,12 @@ Disassembly of section .text: mov x29, sp sub sp, sp, #0x40 str x19, [sp] - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -29,14 +27,12 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3e800000 // =1048576000 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -57,14 +53,12 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40600000 // =1080033280 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x4 // =4 @@ -85,10 +79,9 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fsqrt s0, s16 fcvt d0, s0 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d17, x0 @@ -111,19 +104,15 @@ Disassembly of section .text: fcmp d0, d17 cset x1, ne cbnz x1, - mov x0, #0x6666 // =26214 - movk x0, #0x6666, lsl #16 - movk x0, #0x6666, lsl #32 - movk x0, #0x4002, lsl #48 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x3333 // =13107 + movk x0, #0x4013, lsl #16 + fmov s16, w0 + fneg s0, s16 frintm s0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x7 // =7 @@ -142,19 +131,15 @@ Disassembly of section .text: fcmp d0, d17 cset x1, ne cbnz x1, - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 + fmov s16, w0 + fneg s0, s16 frintp s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x1, ne cbz x1, mov x0, #0x8 // =8 @@ -175,17 +160,13 @@ Disassembly of section .text: fcmp d0, d1 cset x1, ne cbnz x1, - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0x3333, lsl #32 - movk x0, #0x4007, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintz s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x999a // =39322 + movk x0, #0x4039, lsl #16 + fmov s16, w0 + frintz s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x1, ne cbz x1, mov x0, #0x9 // =9 @@ -193,19 +174,18 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fneg d1, d16 - fcvt s1, d1 - fabs s1, s1 - fsqrt s1, s1 - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d1, s1 - fmov d17, x0 - fcmp d1, d17 + mov x0, #0x40000000 // =1073741824 + fmov s16, w0 + sub x17, x29, #0x10 + str s16, [x17] + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fneg s0, s16 + fabs s0, s0 + fsqrt s0, s0 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xa // =10 @@ -213,21 +193,18 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret + sub x16, x29, #0x10 + ldr s0, [x16] fmul s0, s0, s0 fsqrt s0, s0 - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xcccc, lsl #32 - movk x0, #0x3fec, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fadd d0, d0, d17 - fcvt s0, d0 + mov x0, #0x6666 // =26214 + movk x0, #0x3f66, lsl #16 + fmov s17, w0 + fadd s0, s0, s17 frintm s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0xb // =11 diff --git a/tests/snapshots/asm/fp_unary_intrinsic.x64.asm b/tests/snapshots/asm/fp_unary_intrinsic.x64.asm index a5eb60930..3783ac30e 100644 --- a/tests/snapshots/asm/fp_unary_intrinsic.x64.asm +++ b/tests/snapshots/asm/fp_unary_intrinsic.x64.asm @@ -14,14 +14,12 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -33,14 +31,12 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x3e800000, %eax # imm = 0x3E800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -69,18 +65,16 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -113,9 +107,8 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 @@ -145,20 +138,18 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4002666666666666, %rax # imm = 0x4002666666666666 + movl $0x40133333, %eax # imm = 0x40133333 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -183,20 +174,18 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A + movl $0x402ccccd, %eax # imm = 0x402CCCCD movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 roundss $0xa, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -227,14 +216,12 @@ Disassembly of section .text: orq %r10, %rcx testq %rcx, %rcx jne - movabsq $0x4007333333333333, %rax # imm = 0x4007333333333333 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x4039999a, %eax # imm = 0x4039999A + movq %rax, %xmm0 roundss $0xb, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %cl movzbq %cl, %rcx setp %r10b @@ -246,23 +233,21 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movss %xmm14, -0x10(%rbp,%riz) + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 - andpd %xmm15, %xmm1 - sqrtss %xmm1, %xmm1 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm1, %xmm1 + andpd %xmm15, %xmm0 + sqrtss %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -274,19 +259,17 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + movss -0x10(%rbp,%riz), %xmm0 movapd %xmm0, %xmm15 mulss %xmm15, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x3feccccccccccccd, %rax # imm = 0x3FECCCCCCCCCCCCD - cvtss2sd %xmm0, %xmm0 + movl $0x3f666666, %eax # imm = 0x3F666666 movq %rax, %xmm15 - addsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + addss %xmm15, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -305,3 +288,5 @@ Disassembly of section .text: jmp jmp jmp + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hex_float_literal.aarch64.asm b/tests/snapshots/asm/hex_float_literal.aarch64.asm index ea6b29c21..34dd5b362 100644 --- a/tests/snapshots/asm/hex_float_literal.aarch64.asm +++ b/tests/snapshots/asm/hex_float_literal.aarch64.asm @@ -83,10 +83,12 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fmov d17, x0 - fcmp d16, d17 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x3ff0000000000000 // =4607182418800017408 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 + fcmp d0, d17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/hex_float_literal.x64.asm b/tests/snapshots/asm/hex_float_literal.x64.asm index ee7d8ce0a..9e4a160ce 100644 --- a/tests/snapshots/asm/hex_float_literal.x64.asm +++ b/tests/snapshots/asm/hex_float_literal.x64.asm @@ -119,10 +119,12 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 + movl $0x3f800000, %eax # imm = 0x3F800000 + movabsq $0x3ff0000000000000, %rcx # imm = 0x3FF0000000000000 movq %rax, %xmm14 - movq %rax, %xmm15 - ucomisd %xmm15, %xmm14 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -187,5 +189,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hfa_param_interleave.aarch64.asm b/tests/snapshots/asm/hfa_param_interleave.aarch64.asm index 2f9edcf26..a9f033c9d 100644 --- a/tests/snapshots/asm/hfa_param_interleave.aarch64.asm +++ b/tests/snapshots/asm/hfa_param_interleave.aarch64.asm @@ -124,12 +124,10 @@ Disassembly of section .text: sub x1, x29, #0x10 sub x2, x29, #0x18 sub x3, x29, #0x20 - mov x4, #0x4023000000000000 // =4621537642612260864 - fmov d16, x4 - fcvt s0, d16 - sub x4, x29, #0x28 + mov x4, #0x41180000 // =1092091904 + sub x5, x29, #0x28 sub sp, sp, #0x10 - str d0, [sp] + str x4, [sp] ldr s0, [x0] ldr s1, [x0, #0x4] ldr s2, [x1] @@ -138,15 +136,13 @@ Disassembly of section .text: ldr s5, [x2, #0x4] ldr s6, [x3] ldr s7, [x3, #0x4] - mov x0, x4 + mov x0, x5 ldr x0, [x0] bl add sp, sp, #0x10 - mov x0, #0xc00000000000 // =211106232532992 - movk x0, #0x404b, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x425e0000 // =1113456640 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x1 // =1 @@ -164,12 +160,10 @@ Disassembly of section .text: sub x1, x29, #0x30 sub x2, x29, #0x30 sub x3, x29, #0x30 - mov x4, #0x3fd0000000000000 // =4598175219545276416 - fmov d16, x4 - fcvt s0, d16 - sub x4, x29, #0x28 + mov x4, #0x3e800000 // =1048576000 + sub x5, x29, #0x28 sub sp, sp, #0x10 - str d0, [sp] + str x4, [sp] ldr s0, [x0] ldr s1, [x0, #0x4] ldr s2, [x1] @@ -178,15 +172,13 @@ Disassembly of section .text: ldr s5, [x2, #0x4] ldr s6, [x3] ldr s7, [x3, #0x4] - mov x0, x4 + mov x0, x5 ldr x0, [x0] bl add sp, sp, #0x10 - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4024, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41240000 // =1092878336 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 diff --git a/tests/snapshots/asm/hfa_param_interleave.x64.asm b/tests/snapshots/asm/hfa_param_interleave.x64.asm index f7058c209..2fbd17c0c 100644 --- a/tests/snapshots/asm/hfa_param_interleave.x64.asm +++ b/tests/snapshots/asm/hfa_param_interleave.x64.asm @@ -115,11 +115,9 @@ Disassembly of section .text: leaq -0x10(%rbp), %rsi leaq -0x18(%rbp), %rdx leaq -0x20(%rbp), %rcx - movabsq $0x4023000000000000, %rax # imm = 0x4023000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - leaq -0x28(%rbp), %r8 - movapd %xmm0, %xmm4 + movl $0x41180000, %r8d # imm = 0x41180000 + leaq -0x28(%rbp), %r9 + movq %r8, %xmm4 movq %rdi, %r10 movsd (%r10,%riz), %xmm0 movq %rsi, %r10 @@ -128,13 +126,12 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm2 movq %rcx, %r10 movsd (%r10,%riz), %xmm3 - movq %r8, %rdi + movq %r9, %rdi movq (%rdi), %rdi callq - movabsq $0x404bc00000000000, %rax # imm = 0x404BC00000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x425e0000, %eax # imm = 0x425E0000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -156,11 +153,9 @@ Disassembly of section .text: leaq -0x30(%rbp), %rsi leaq -0x30(%rbp), %rdx leaq -0x30(%rbp), %rcx - movabsq $0x3fd0000000000000, %rax # imm = 0x3FD0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - leaq -0x28(%rbp), %r8 - movapd %xmm0, %xmm4 + movl $0x3e800000, %r8d # imm = 0x3E800000 + leaq -0x28(%rbp), %r9 + movq %r8, %xmm4 movq %rdi, %r10 movsd (%r10,%riz), %xmm0 movq %rsi, %r10 @@ -169,13 +164,12 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm2 movq %rcx, %r10 movsd (%r10,%riz), %xmm3 - movq %r8, %rdi + movq %r9, %rdi movq (%rdi), %rdi callq - movabsq $0x4024800000000000, %rax # imm = 0x4024800000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41240000, %eax # imm = 0x41240000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -191,4 +185,5 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/hfa_struct_return.aarch64.asm b/tests/snapshots/asm/hfa_struct_return.aarch64.asm index 0fcdc0bb9..8fc8bdcfd 100644 --- a/tests/snapshots/asm/hfa_struct_return.aarch64.asm +++ b/tests/snapshots/asm/hfa_struct_return.aarch64.asm @@ -348,12 +348,10 @@ Disassembly of section .text: add sp, sp, #0x170 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + fmov d0, x20 + fmov d1, x1 bl sub x16, x29, #0x150 str s0, [x16] @@ -367,17 +365,15 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0xa8 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x20, ne cbnz x20, sub x0, x29, #0xa8 ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x20, ne cbz x20, mov x0, #0x5 // =5 @@ -433,10 +429,9 @@ Disassembly of section .text: ldr s2, [x0, #0x8] ldr s3, [x0, #0xc] bl - mov x0, #0x4024000000000000 // =4621819117588971520 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x41200000 // =1092616192 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/hfa_struct_return.x64.asm b/tests/snapshots/asm/hfa_struct_return.x64.asm index eae9f0c0b..801a512e3 100644 --- a/tests/snapshots/asm/hfa_struct_return.x64.asm +++ b/tests/snapshots/asm/hfa_struct_return.x64.asm @@ -439,12 +439,10 @@ Disassembly of section .text: addq $0x180, %rsp # imm = 0x180 popq %rbp retq - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 + movl $0x40200000, %esi # imm = 0x40200000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 callq movsd %xmm0, -0x160(%rbp,%riz) leaq -0x160(%rbp), %rax @@ -456,9 +454,8 @@ Disassembly of section .text: movq %rcx, %rax leaq -0xa8(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %bl movzbq %bl, %rbx setp %r10b @@ -468,10 +465,9 @@ Disassembly of section .text: jne leaq -0xa8(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %bl movzbq %bl, %rbx setp %r10b @@ -548,10 +544,9 @@ Disassembly of section .text: movsd (%r10,%riz), %xmm0 movsd 0x8(%r10,%riz), %xmm1 callq - movabsq $0x4024000000000000, %rax # imm = 0x4024000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x41200000, %eax # imm = 0x41200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -578,3 +573,4 @@ Disassembly of section .text: jmp jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/init_scalar_conversion.aarch64.asm b/tests/snapshots/asm/init_scalar_conversion.aarch64.asm index e43a47c5d..04ed82699 100644 --- a/tests/snapshots/asm/init_scalar_conversion.aarch64.asm +++ b/tests/snapshots/asm/init_scalar_conversion.aarch64.asm @@ -238,21 +238,25 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - sub x1, x29, #0x70 - adrp x2, - add x2, x2, + fmov s16, w0 + sub x17, x29, #0x68 + str s16, [x17] + sub x0, x29, #0x70 + adrp x1, + add x1, x1, str x10, [sp, #-0x10]! - ldrb w10, [x2] - strb w10, [x1] - ldrb w10, [x2, #0x1] - strb w10, [x1, #0x1] - ldrb w10, [x2, #0x2] - strb w10, [x1, #0x2] - ldrb w10, [x2, #0x3] - strb w10, [x1, #0x3] + ldrb w10, [x1] + strb w10, [x0] + ldrb w10, [x1, #0x1] + strb w10, [x0, #0x1] + ldrb w10, [x1, #0x2] + strb w10, [x0, #0x2] + ldrb w10, [x1, #0x3] + strb w10, [x0, #0x3] ldr x10, [sp], #0x10 sub x16, x29, #0x58 ldr d0, [x16] + mov x0, #0x0 // =0 fmov d17, x0 fadd d0, d0, d17 fcvt s0, d0 @@ -260,22 +264,22 @@ Disassembly of section .text: str s0, [x0] sub x0, x29, #0x70 ldr s0, [x0] - mov x0, #0x851f // =34079 - movk x0, #0x51eb, lsl #16 - movk x0, #0x1eb8, lsl #32 - movk x0, #0x400f, lsl #48 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + sub x17, x29, #0x68 + str s0, [x17] + sub x16, x29, #0x68 + ldr s0, [x16] + mov x0, #0xf5c3 // =62915 + movk x0, #0x4078, lsl #16 + fmov s17, w0 + fcmp s0, s17 cset x22, mi cbnz x22, - mov x0, #0xe148 // =57672 - movk x0, #0x147a, lsl #16 - movk x0, #0x47ae, lsl #32 - movk x0, #0x400f, lsl #48 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + sub x16, x29, #0x68 + ldr s0, [x16] + mov x0, #0x3d71 // =15729 + movk x0, #0x407a, lsl #16 + fmov s17, w0 + fcmp s0, s17 cset x22, gt cbz x22, mov x0, #0x5 // =5 diff --git a/tests/snapshots/asm/init_scalar_conversion.x64.asm b/tests/snapshots/asm/init_scalar_conversion.x64.asm index 8e043c803..2fa9c4638 100644 --- a/tests/snapshots/asm/init_scalar_conversion.x64.asm +++ b/tests/snapshots/asm/init_scalar_conversion.x64.asm @@ -285,19 +285,22 @@ Disassembly of section .text: popq %rbp retq xorq %rax, %rax - leaq -0x70(%rbp), %rcx - leaq , %rdx - pushq %rax - movzbq (%rdx), %rax - movb %al, (%rcx) - movzbq 0x1(%rdx), %rax - movb %al, 0x1(%rcx) - movzbq 0x2(%rdx), %rax - movb %al, 0x2(%rcx) - movzbq 0x3(%rdx), %rax - movb %al, 0x3(%rcx) - popq %rax + movq %rax, %xmm14 + movss %xmm14, -0x68(%rbp,%riz) + leaq -0x70(%rbp), %rax + leaq , %rcx + pushq %rdx + movzbq (%rcx), %rdx + movb %dl, (%rax) + movzbq 0x1(%rcx), %rdx + movb %dl, 0x1(%rax) + movzbq 0x2(%rcx), %rdx + movb %dl, 0x2(%rax) + movzbq 0x3(%rcx), %rdx + movb %dl, 0x3(%rax) + popq %rdx movsd -0x58(%rbp,%riz), %xmm0 + xorq %rax, %rax movq %rax, %xmm15 addsd %xmm15, %xmm0 cvtsd2ss %xmm0, %xmm0 @@ -305,10 +308,11 @@ Disassembly of section .text: movss %xmm0, (%rax,%riz) leaq -0x70(%rbp), %rax movss (%rax,%riz), %xmm0 - movabsq $0x400f1eb851eb851f, %rax # imm = 0x400F1EB851EB851F - cvtss2sd %xmm0, %xmm1 + movss %xmm0, -0x68(%rbp,%riz) + movss -0x68(%rbp,%riz), %xmm0 + movl $0x4078f5c3, %eax # imm = 0x4078F5C3 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm0 setb %r13b movzbq %r13b, %r13 setnp %r10b @@ -316,10 +320,10 @@ Disassembly of section .text: andq %r10, %r13 testq %r13, %r13 jne - movabsq $0x400f47ae147ae148, %rax # imm = 0x400F47AE147AE148 - cvtss2sd %xmm0, %xmm0 + movss -0x68(%rbp,%riz), %xmm0 + movl $0x407a3d71, %eax # imm = 0x407A3D71 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 seta %r13b movzbq %r13b, %r13 testq %r13, %r13 @@ -411,4 +415,4 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm b/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm index 4127980a5..a343f53aa 100644 --- a/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm +++ b/tests/snapshots/asm/int_to_float_assign_conversion.aarch64.asm @@ -96,44 +96,31 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4189 // =16777 - movk x0, #0xe560, lsl #16 - movk x0, #0x22d0, lsl #32 - movk x0, #0x3fd3, lsl #48 - fcvt d0, s0 - mov x1, #0x1062 // =4194 - movk x1, #0x3958, lsl #16 - movk x1, #0xc8b4, lsl #32 - movk x1, #0x3fe2, lsl #48 - fcvt d1, s1 - fmov d16, x1 - fmul d1, d16, d1 - fmov d16, x0 - fmadd d0, d16, d0, d1 - mov x0, #0x76c9 // =30409 - movk x0, #0x9fbe, lsl #16 - movk x0, #0x2f1a, lsl #32 - movk x0, #0x3fbd, lsl #48 - fcvt d1, s2 - fmov d16, x0 - fmadd d0, d16, d1, d0 - mov x0, #0x4060000000000000 // =4638707616191610880 - fmov d17, x0 - fsub d0, d0, d17 - fcvt s0, d0 - mov x0, #0x800000000000 // =140737488355328 - movk x0, #0x4045, lsl #48 - fmov d16, x0 - fneg d1, d16 - fcvt d2, s0 - fcmp d2, d1 + mov x0, #0x1687 // =5767 + movk x0, #0x3e99, lsl #16 + mov x1, #0x45a2 // =17826 + movk x1, #0x3f16, lsl #16 + fmov s16, w1 + fmul s1, s16, s1 + fmov s16, w0 + fmadd s0, s16, s0, s1 + mov x0, #0x78d5 // =30933 + movk x0, #0x3de9, lsl #16 + fmov s16, w0 + fmadd s0, s16, s2, s0 + mov x0, #0x43000000 // =1124073472 + fmov s17, w0 + fsub s0, s0, s17 + mov x0, #0x422c0000 // =1110179840 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x20, gt cbnz x20, - mov x0, #0x4046000000000000 // =4631389266797133824 - fmov d16, x0 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + mov x0, #0x42300000 // =1110441984 + fmov s16, w0 + fneg s1, s16 + fcmp s0, s1 cset x20, mi cbz x20, mov x0, #0x5 // =5 @@ -145,10 +132,9 @@ Disassembly of section .text: mov x0, #0x7 // =7 scvtf d0, x0 fcvt s0, d0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40e00000 // =1088421888 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 diff --git a/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm b/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm index 7c5fc29c5..571c06a19 100644 --- a/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm +++ b/tests/snapshots/asm/int_to_float_assign_conversion.x64.asm @@ -97,44 +97,38 @@ Disassembly of section .text: addq $0x60, %rsp popq %rbp retq - movabsq $0x3fd322d0e5604189, %rax # imm = 0x3FD322D0E5604189 - cvtss2sd %xmm0, %xmm0 - movabsq $0x3fe2c8b439581062, %rcx # imm = 0x3FE2C8B439581062 - cvtss2sd %xmm1, %xmm1 + movl $0x3e991687, %eax # imm = 0x3E991687 + movl $0x3f1645a2, %ecx # imm = 0x3F1645A2 movapd %xmm1, %xmm15 movq %rcx, %xmm1 - mulsd %xmm15, %xmm1 + mulss %xmm15, %xmm1 movq %rax, %xmm14 movapd %xmm0, %xmm15 movapd %xmm1, %xmm0 - vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x3fbd2f1a9fbe76c9, %rax # imm = 0x3FBD2F1A9FBE76C9 - cvtss2sd %xmm2, %xmm1 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x3de978d5, %eax # imm = 0x3DE978D5 movq %rax, %xmm14 - movapd %xmm1, %xmm15 - vfmadd231sd %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 - movabsq $0x4060000000000000, %rax # imm = 0x4060000000000000 + movapd %xmm2, %xmm15 + vfmadd231ss %xmm15, %xmm14, %xmm0 # xmm0 = (xmm14 * xmm15) + xmm0 + movl $0x43000000, %eax # imm = 0x43000000 movq %rax, %xmm15 - subsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 - movabsq $0x4045800000000000, %rax # imm = 0x4045800000000000 + subss %xmm15, %xmm0 + movl $0x422c0000, %eax # imm = 0x422C0000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm2 - ucomisd %xmm1, %xmm2 + ucomiss %xmm1, %xmm0 seta %bl movzbq %bl, %rbx testq %rbx, %rbx jne - movabsq $0x4046000000000000, %rax # imm = 0x4046000000000000 + movl $0x42300000, %eax # imm = 0x42300000 movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setb %bl movzbq %bl, %rbx setnp %r10b @@ -150,10 +144,9 @@ Disassembly of section .text: movl $0x7, %eax cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40e00000, %eax # imm = 0x40E00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -176,4 +169,4 @@ Disassembly of section .text: popq %rbp retq jmp - addb %al, 0x41(%rdx) + addb %al, (%rax) diff --git a/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm b/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm index 36edb6468..3e112daad 100644 --- a/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm +++ b/tests/snapshots/asm/leading_dot_float_literal.aarch64.asm @@ -13,9 +13,10 @@ Disassembly of section .text: stp x29, x30, [sp, #-0x10]! mov x29, sp sub sp, sp, #0x30 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x3f000000 // =1056964608 + fmov s16, w0 + sub x17, x29, #0x8 + str s16, [x17] mov x1, #0x3fd0000000000000 // =4598175219545276416 fmov d16, x1 sub x17, x29, #0x10 @@ -24,10 +25,14 @@ Disassembly of section .text: fmov d16, x1 sub x17, x29, #0x18 str d16, [x17] + mov x1, #0x3fe0000000000000 // =4602678819172646912 + fmov d16, x1 + fcvt s0, d16 mov x2, #0x1 // =1 - fcvt d1, s0 - fmov d17, x0 - fcmp d1, d17 + sub x16, x29, #0x8 + ldr s1, [x16] + fmov s17, w0 + fcmp s1, s17 cset x0, ne cbz x0, mov x2, #0x0 // =0 @@ -47,10 +52,9 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x2, #0x0 // =0 - mov x0, #0x3fe0000000000000 // =4602678819172646912 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3f000000 // =1056964608 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x2, #0x0 // =0 diff --git a/tests/snapshots/asm/leading_dot_float_literal.x64.asm b/tests/snapshots/asm/leading_dot_float_literal.x64.asm index 143c480ac..93bef801d 100644 --- a/tests/snapshots/asm/leading_dot_float_literal.x64.asm +++ b/tests/snapshots/asm/leading_dot_float_literal.x64.asm @@ -14,19 +14,22 @@ Disassembly of section .text: pushq %rbp movq %rsp, %rbp subq $0x30, %rsp - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x8(%rbp,%riz) movabsq $0x3fd0000000000000, %rcx # imm = 0x3FD0000000000000 movq %rcx, %xmm14 movsd %xmm14, -0x10(%rbp,%riz) movabsq $0x4039000000000000, %rcx # imm = 0x4039000000000000 movq %rcx, %xmm14 movsd %xmm14, -0x18(%rbp,%riz) + movabsq $0x3fe0000000000000, %rcx # imm = 0x3FE0000000000000 + movq %rcx, %xmm14 + cvtsd2ss %xmm14, %xmm0 movl $0x1, %edx - cvtss2sd %xmm0, %xmm1 + movss -0x8(%rbp,%riz), %xmm1 movq %rax, %xmm15 - ucomisd %xmm15, %xmm1 + ucomiss %xmm15, %xmm1 setne %al movzbq %al, %rax setp %r10b @@ -59,10 +62,9 @@ Disassembly of section .text: testq %rax, %rax je xorq %rdx, %rdx - movabsq $0x3fe0000000000000, %rax # imm = 0x3FE0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3f000000, %eax # imm = 0x3F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -85,4 +87,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/libc_fp_classify.aarch64.asm b/tests/snapshots/asm/libc_fp_classify.aarch64.asm index c71127733..f9a6c8561 100644 --- a/tests/snapshots/asm/libc_fp_classify.aarch64.asm +++ b/tests/snapshots/asm/libc_fp_classify.aarch64.asm @@ -148,18 +148,16 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x4000000000000000 // =4611686018427387904 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fneg d1, d16 - fcvt s1, d1 + mov x20, #0x40000000 // =1073741824 + mov x0, #0x40a00000 // =1084227584 + fmov s16, w0 + fneg s0, s16 + fmov d1, d0 + fmov d0, x20 bl - fmov d16, x20 - fneg d1, d16 - fcvt d0, s0 - fcmp d0, d1 + fmov s16, w20 + fneg s1, s16 + fcmp s0, s1 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/libc_fp_classify.x64.asm b/tests/snapshots/asm/libc_fp_classify.x64.asm index fdc7cc245..6a53c4723 100644 --- a/tests/snapshots/asm/libc_fp_classify.x64.asm +++ b/tests/snapshots/asm/libc_fp_classify.x64.asm @@ -158,22 +158,20 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rbx # imm = 0x4000000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x40000000, %ebx # imm = 0x40000000 + movl $0x40a00000, %eax # imm = 0x40A00000 + movq %rax, %xmm0 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 - xorpd %xmm15, %xmm1 - cvtsd2ss %xmm1, %xmm1 + xorpd %xmm15, %xmm0 + movapd %xmm0, %xmm1 + movq %rbx, %xmm0 callq movq %rbx, %xmm1 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm1 - cvtss2sd %xmm0, %xmm0 - ucomisd %xmm1, %xmm0 + ucomiss %xmm1, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_fp_return_value.aarch64.asm b/tests/snapshots/asm/libc_fp_return_value.aarch64.asm index f231dc9a1..d331b9222 100644 --- a/tests/snapshots/asm/libc_fp_return_value.aarch64.asm +++ b/tests/snapshots/asm/libc_fp_return_value.aarch64.asm @@ -69,32 +69,27 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s16, w0 + fsqrt s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fneg d0, d16 - fcvt s0, d0 + mov x0, #0x40600000 // =1080033280 + fmov s16, w0 + fneg s0, s16 fabs s0, s0 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 - fsqrt s0, s0 + mov x0, #0x41800000 // =1098907648 + fmov s16, w0 + fsqrt s0, s16 fcvt d0, s0 mov x0, #0x4010000000000000 // =4616189618054758400 fmov d17, x0 @@ -102,45 +97,34 @@ Disassembly of section .text: cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x4005, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintm s0, s0 - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xcccd // =52429 + movk x0, #0x402c, lsl #16 + fmov s16, w0 + frintm s0, s16 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x6666 // =26214 - movk x0, #0x6666, lsl #16 - movk x0, #0x6666, lsl #32 - movk x0, #0x4002, lsl #48 - fmov d16, x0 - fcvt s0, d16 - frintp s0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x3333 // =13107 + movk x0, #0x4013, lsl #16 + fmov s16, w0 + frintp s0, s16 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 - mov x0, #0x401c000000000000 // =4619567317775286272 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40e00000 // =1088421888 + mov x1, #0x40800000 // =1082130432 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x0 // =0 diff --git a/tests/snapshots/asm/libc_fp_return_value.x64.asm b/tests/snapshots/asm/libc_fp_return_value.x64.asm index cd8d99241..1121786ed 100644 --- a/tests/snapshots/asm/libc_fp_return_value.x64.asm +++ b/tests/snapshots/asm/libc_fp_return_value.x64.asm @@ -93,14 +93,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -109,18 +107,16 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm0 - movabsq $-0x8000000000000000, %r10 # imm = 0x8000000000000000 + movl $0x80000000, %r10d # imm = 0x80000000 movq %r10, %xmm15 xorpd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF movq %r10, %xmm15 andpd %xmm15, %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -129,9 +125,8 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %eax # imm = 0x41800000 + movq %rax, %xmm0 sqrtss %xmm0, %xmm0 cvtss2sd %xmm0, %xmm0 movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 @@ -145,14 +140,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x400599999999999a, %rax # imm = 0x400599999999999A - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x402ccccd, %eax # imm = 0x402CCCCD + movq %rax, %xmm0 roundss $0x9, %xmm0, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -161,14 +154,12 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x4002666666666666, %rax # imm = 0x4002666666666666 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40133333, %eax # imm = 0x40133333 + movq %rax, %xmm0 roundss $0xa, %xmm0, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -177,18 +168,15 @@ Disassembly of section .text: testq %rax, %rax je xorq %rbx, %rbx - movabsq $0x401c000000000000, %rax # imm = 0x401C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40e00000, %edi # imm = 0x40E00000 + movl $0x40800000, %esi # imm = 0x40800000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -219,4 +207,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm b/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm index f49999c40..2510deb00 100644 --- a/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm +++ b/tests/snapshots/asm/libc_math_fdim_scalbn.aarch64.asm @@ -174,31 +174,27 @@ Disassembly of section .text: mov x0, #0x6 // =6 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x2 // =2 + mov x0, #0x3f800000 // =1065353216 + mov x1, #0x2 // =2 + fmov d0, x0 + mov x0, x1 bl - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40a00000 // =1084227584 + mov x1, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm b/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm index 582d52781..6a0042fb9 100644 --- a/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm +++ b/tests/snapshots/asm/libc_math_fdim_scalbn.x64.asm @@ -205,15 +205,14 @@ Disassembly of section .text: movl $0x6, %eax popq %rbp retq - movabsq $0x3ff0000000000000, %rax # imm = 0x3FF0000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movl $0x2, %edi + movl $0x3f800000, %edi # imm = 0x3F800000 + movl $0x2, %esi + movq %rdi, %xmm0 + movq %rsi, %rdi callq - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -224,17 +223,14 @@ Disassembly of section .text: movl $0x7, %eax popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40a00000, %edi # imm = 0x40A00000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 callq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -248,3 +244,5 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm b/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm index efe380f82..6c7147a8a 100644 --- a/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm +++ b/tests/snapshots/asm/libc_math_hyperbolic.aarch64.asm @@ -120,12 +120,12 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne @@ -135,12 +135,12 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne diff --git a/tests/snapshots/asm/libc_math_hyperbolic.x64.asm b/tests/snapshots/asm/libc_math_hyperbolic.x64.asm index 7038ffb82..81a2380f0 100644 --- a/tests/snapshots/asm/libc_math_hyperbolic.x64.asm +++ b/tests/snapshots/asm/libc_math_hyperbolic.x64.asm @@ -133,13 +133,13 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne @@ -148,13 +148,13 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne diff --git a/tests/snapshots/asm/libc_math_libm.aarch64.asm b/tests/snapshots/asm/libc_math_libm.aarch64.asm index d791528ac..84dca0c1b 100644 --- a/tests/snapshots/asm/libc_math_libm.aarch64.asm +++ b/tests/snapshots/asm/libc_math_libm.aarch64.asm @@ -135,13 +135,13 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x403b000000000000 // =4628293042053316608 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x41d80000 // =1104674816 + fmov d0, x0 bl fcvt d0, s0 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d1, x0 + mov x0, #0x40400000 // =1077936128 + fmov s16, w0 + fcvt d1, s16 bl cmp x0, #0x0 b.ne @@ -151,12 +151,10 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40a00000 // =1084227584 + mov x1, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x1 bl fcvt d0, s0 mov x0, #0x3ff0000000000000 // =4607182418800017408 diff --git a/tests/snapshots/asm/libc_math_libm.x64.asm b/tests/snapshots/asm/libc_math_libm.x64.asm index 72b88b63a..67c4beef7 100644 --- a/tests/snapshots/asm/libc_math_libm.x64.asm +++ b/tests/snapshots/asm/libc_math_libm.x64.asm @@ -151,14 +151,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x403b000000000000, %rax # imm = 0x403B000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41d80000, %edi # imm = 0x41D80000 + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movabsq $0x4008000000000000, %rdi # imm = 0x4008000000000000 - movq %rdi, %xmm1 + movl $0x40400000, %eax # imm = 0x40400000 + movq %rax, %xmm14 + cvtss2sd %xmm14, %xmm1 callq testq %rax, %rax jne @@ -167,12 +167,10 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40a00000, %edi # imm = 0x40A00000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 @@ -194,4 +192,5 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_minmax.aarch64.asm b/tests/snapshots/asm/libc_math_minmax.aarch64.asm index a379e3dcf..67353384c 100644 --- a/tests/snapshots/asm/libc_math_minmax.aarch64.asm +++ b/tests/snapshots/asm/libc_math_minmax.aarch64.asm @@ -96,17 +96,14 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s1, d16 + mov x0, #0x40400000 // =1077936128 + mov x1, #0x40800000 // =1082130432 + fmov d0, x0 + fmov d1, x1 bl - mov x0, #0x4014000000000000 // =4617315517961601024 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40a00000 // =1084227584 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 @@ -115,16 +112,13 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x4000000000000000 // =4611686018427387904 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x40000000 // =1073741824 + mov x1, #0x40400000 // =1077936128 + fmov d0, x20 + fmov d1, x1 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x7 // =7 @@ -133,16 +127,13 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s0, d16 - mov x20, #0x4008000000000000 // =4613937818241073152 - fmov d16, x20 - fcvt s1, d16 + mov x0, #0x40000000 // =1073741824 + mov x20, #0x40400000 // =1077936128 + fmov d0, x0 + fmov d1, x20 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 diff --git a/tests/snapshots/asm/libc_math_minmax.x64.asm b/tests/snapshots/asm/libc_math_minmax.x64.asm index ede97aeca..680d8a979 100644 --- a/tests/snapshots/asm/libc_math_minmax.x64.asm +++ b/tests/snapshots/asm/libc_math_minmax.x64.asm @@ -121,18 +121,15 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40400000, %edi # imm = 0x40400000 + movl $0x40800000, %esi # imm = 0x40800000 + movq %rdi, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40a00000, %eax # imm = 0x40A00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -145,17 +142,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rbx # imm = 0x4000000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40000000, %ebx # imm = 0x40000000 + movl $0x40400000, %esi # imm = 0x40400000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -168,17 +162,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4008000000000000, %rbx # imm = 0x4008000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x40000000, %edi # imm = 0x40000000 + movl $0x40400000, %ebx # imm = 0x40400000 + movq %rdi, %xmm0 + movq %rbx, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_math_nextafter.aarch64.asm b/tests/snapshots/asm/libc_math_nextafter.aarch64.asm index 614167329..5100b3a47 100644 --- a/tests/snapshots/asm/libc_math_nextafter.aarch64.asm +++ b/tests/snapshots/asm/libc_math_nextafter.aarch64.asm @@ -99,16 +99,13 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 + mov x20, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + fmov d0, x20 + fmov d1, x1 bl - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ls cbz x0, mov x0, #0x7 // =7 @@ -117,9 +114,8 @@ Disassembly of section .text: add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4030000000000000 // =4625196817309499392 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x41800000 // =1098907648 + fmov d0, x0 bl sxtw x0, w0 cmp x0, #0x4 diff --git a/tests/snapshots/asm/libc_math_nextafter.x64.asm b/tests/snapshots/asm/libc_math_nextafter.x64.asm index 39de0d513..6d486b415 100644 --- a/tests/snapshots/asm/libc_math_nextafter.x64.asm +++ b/tests/snapshots/asm/libc_math_nextafter.x64.asm @@ -107,17 +107,14 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rbx # imm = 0x3FF0000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 + movl $0x3f800000, %ebx # imm = 0x3F800000 + movl $0x40000000, %esi # imm = 0x40000000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 xorl %eax, %eax callq - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setbe %al movzbq %al, %rax setnp %r10b @@ -130,9 +127,8 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x4030000000000000, %rax # imm = 0x4030000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x41800000, %edi # imm = 0x41800000 + movq %rdi, %xmm0 xorl %eax, %eax callq movslq %eax, %rax @@ -148,4 +144,4 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/libc_math_round.aarch64.asm b/tests/snapshots/asm/libc_math_round.aarch64.asm index 29d230192..0e852e564 100644 --- a/tests/snapshots/asm/libc_math_round.aarch64.asm +++ b/tests/snapshots/asm/libc_math_round.aarch64.asm @@ -109,14 +109,12 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40200000 // =1075838976 + fmov d0, x0 bl - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x8 // =8 @@ -124,14 +122,12 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40600000 // =1080033280 + fmov d0, x0 bl - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x9 // =9 diff --git a/tests/snapshots/asm/libc_math_round.x64.asm b/tests/snapshots/asm/libc_math_round.x64.asm index df23af437..f49bedaf1 100644 --- a/tests/snapshots/asm/libc_math_round.x64.asm +++ b/tests/snapshots/asm/libc_math_round.x64.asm @@ -107,15 +107,13 @@ Disassembly of section .text: movl $0x7, %eax popq %rbp retq - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40200000, %edi # imm = 0x40200000 + movq %rdi, %xmm0 xorl %eax, %eax callq - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -126,15 +124,13 @@ Disassembly of section .text: movl $0x8, %eax popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40600000, %edi # imm = 0x40600000 + movq %rdi, %xmm0 xorl %eax, %eax callq - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b diff --git a/tests/snapshots/asm/libc_math_special.aarch64.asm b/tests/snapshots/asm/libc_math_special.aarch64.asm index d18cfdb9d..1ca23d719 100644 --- a/tests/snapshots/asm/libc_math_special.aarch64.asm +++ b/tests/snapshots/asm/libc_math_special.aarch64.asm @@ -115,9 +115,8 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40a00000 // =1084227584 + fmov d0, x0 bl fcvt d0, s0 mov x0, #0x4038000000000000 // =4627448617123184640 @@ -132,12 +131,12 @@ Disassembly of section .text: add sp, sp, #0x30 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x0 // =0 - fmov d16, x20 - fcvt s0, d16 + mov x0, #0x0 // =0 + fmov d0, x0 bl fcvt d0, s0 - fmov d1, x20 + mov x0, #0x0 // =0 + fmov d1, x0 bl cmp x0, #0x0 b.ne diff --git a/tests/snapshots/asm/libc_math_special.x64.asm b/tests/snapshots/asm/libc_math_special.x64.asm index 66dedf738..63941b6b4 100644 --- a/tests/snapshots/asm/libc_math_special.x64.asm +++ b/tests/snapshots/asm/libc_math_special.x64.asm @@ -122,9 +122,8 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 @@ -138,13 +137,13 @@ Disassembly of section .text: addq $0x20, %rsp popq %rbp retq - xorq %rbx, %rbx - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 + xorq %rdi, %rdi + movq %rdi, %xmm0 xorl %eax, %eax callq cvtss2sd %xmm0, %xmm0 - movq %rbx, %xmm1 + xorq %rdi, %rdi + movq %rdi, %xmm1 callq testq %rax, %rax jne diff --git a/tests/snapshots/asm/local_init_int_to_float.aarch64.asm b/tests/snapshots/asm/local_init_int_to_float.aarch64.asm index b3937b0d7..8d79276fa 100644 --- a/tests/snapshots/asm/local_init_int_to_float.aarch64.asm +++ b/tests/snapshots/asm/local_init_int_to_float.aarch64.asm @@ -33,22 +33,16 @@ Disassembly of section .text: ldrb w0, [x0] scvtf d0, x0 fcvt s8, d0 - mov x0, #0x3333 // =13107 - movk x0, #0x3333, lsl #16 - movk x0, #0xf333, lsl #32 - movk x0, #0x4044, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x999a // =39322 + movk x0, #0x4227, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, mi cbnz x20, - mov x0, #0xcccd // =52429 - movk x0, #0xcccc, lsl #16 - movk x0, #0xccc, lsl #32 - movk x0, #0x4045, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x6666 // =26214 + movk x0, #0x4228, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, gt cbz x20, adrp x0, @@ -66,18 +60,16 @@ Disassembly of section .text: mov x0, #0x3039 // =12345 scvtf d0, x0 fcvt s8, d0 - mov x0, #0x1c4000000000 // =31061203484672 - movk x0, #0x40c8, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xe200 // =57856 + movk x0, #0x4640, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, mi cbnz x20, - mov x0, #0x1cc000000000 // =31610959298560 - movk x0, #0x40c8, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xe600 // =58880 + movk x0, #0x4640, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, gt cbz x20, adrp x0, @@ -125,20 +117,16 @@ Disassembly of section .text: movk x0, #0xffff, lsl #16 scvtf d0, x0 fcvt s8, d0 - mov x0, #0x90000000 // =2415919104 - movk x0, #0xf686, lsl #32 - movk x0, #0x41ef, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0xb434 // =46132 + movk x0, #0x4f7f, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, mi cbnz x20, - mov x0, #0xb0000000 // =2952790016 - movk x0, #0x4cc, lsl #32 - movk x0, #0x41f0, lsl #48 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x2666 // =9830 + movk x0, #0x4f80, lsl #16 + fmov s17, w0 + fcmp s8, s17 cset x20, gt cbz x20, adrp x0, @@ -153,12 +141,13 @@ Disassembly of section .text: add sp, sp, #0xc0 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x999a // =39322 - movk x0, #0x9999, lsl #16 - movk x0, #0x9999, lsl #32 - movk x0, #0x400d, lsl #48 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0xcccd // =52429 + movk x0, #0x406c, lsl #16 + fmov s16, w0 + sub x17, x29, #0x48 + str s16, [x17] + sub x16, x29, #0x48 + ldr s0, [x16] fcvt d0, s0 fcvtzs x0, d0 sxtw x1, w0 diff --git a/tests/snapshots/asm/local_init_int_to_float.x64.asm b/tests/snapshots/asm/local_init_int_to_float.x64.asm index afb7abe35..0df1ba7bc 100644 --- a/tests/snapshots/asm/local_init_int_to_float.x64.asm +++ b/tests/snapshots/asm/local_init_int_to_float.x64.asm @@ -32,11 +32,10 @@ Disassembly of section .text: cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm14 movsd %xmm14, 0x18(%rsp) - movabsq $0x4044f33333333333, %rax # imm = 0x4044F33333333333 + movl $0x4227999a, %eax # imm = 0x4227999A movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setb %bl movzbq %bl, %rbx setnp %r10b @@ -44,11 +43,10 @@ Disassembly of section .text: andq %r10, %rbx testq %rbx, %rbx jne - movabsq $0x40450ccccccccccd, %rax # imm = 0x40450CCCCCCCCCCD + movl $0x42286666, %eax # imm = 0x42286666 movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 seta %bl movzbq %bl, %rbx testq %rbx, %rbx @@ -68,11 +66,10 @@ Disassembly of section .text: cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm14 movsd %xmm14, 0x18(%rsp) - movabsq $0x40c81c4000000000, %rax # imm = 0x40C81C4000000000 + movl $0x4640e200, %eax # imm = 0x4640E200 movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setb %bl movzbq %bl, %rbx setnp %r10b @@ -80,11 +77,10 @@ Disassembly of section .text: andq %r10, %rbx testq %rbx, %rbx jne - movabsq $0x40c81cc000000000, %rax # imm = 0x40C81CC000000000 + movl $0x4640e600, %eax # imm = 0x4640E600 movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 seta %bl movzbq %bl, %rbx testq %rbx, %rbx @@ -142,11 +138,10 @@ Disassembly of section .text: cvtsi2sd %rax, %xmm0 cvtsd2ss %xmm0, %xmm14 movsd %xmm14, 0x18(%rsp) - movabsq $0x41eff68690000000, %rax # imm = 0x41EFF68690000000 + movl $0x4f7fb434, %eax # imm = 0x4F7FB434 movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 setb %bl movzbq %bl, %rbx setnp %r10b @@ -154,11 +149,10 @@ Disassembly of section .text: andq %r10, %rbx testq %rbx, %rbx jne - movabsq $0x41f004ccb0000000, %rax # imm = 0x41F004CCB0000000 + movl $0x4f802666, %eax # imm = 0x4F802666 movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm14 seta %bl movzbq %bl, %rbx testq %rbx, %rbx @@ -174,9 +168,10 @@ Disassembly of section .text: addq $0xb0, %rsp popq %rbp retq - movabsq $0x400d99999999999a, %rax # imm = 0x400D99999999999A + movl $0x406ccccd, %eax # imm = 0x406CCCCD movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movss %xmm14, -0x48(%rbp,%riz) + movss -0x48(%rbp,%riz), %xmm0 cvtss2sd %xmm0, %xmm0 cvttsd2si %xmm0, %rax movslq %eax, %rcx @@ -221,3 +216,4 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/logical_not_float.aarch64.asm b/tests/snapshots/asm/logical_not_float.aarch64.asm index f1fc69365..6ea79e1f3 100644 --- a/tests/snapshots/asm/logical_not_float.aarch64.asm +++ b/tests/snapshots/asm/logical_not_float.aarch64.asm @@ -86,11 +86,10 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x0 // =0 - fcvt d0, s0 - fmov d17, x0 + mov x1, #0x0 // =0 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fcmp d0, d17 cset x0, eq cmp x0, #0x1 @@ -99,12 +98,11 @@ Disassembly of section .text: add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s0, d16 - mov x0, #0x0 // =0 - fcvt d0, s0 - fmov d17, x0 + mov x0, #0x40600000 // =1080033280 + mov x1, #0x0 // =0 + fmov s16, w0 + fcvt d0, s16 + fmov d17, x1 fcmp d0, d17 cset x0, eq cmp x0, #0x0 diff --git a/tests/snapshots/asm/logical_not_float.x64.asm b/tests/snapshots/asm/logical_not_float.x64.asm index b3587c9d1..f3d6a3ca7 100644 --- a/tests/snapshots/asm/logical_not_float.x64.asm +++ b/tests/snapshots/asm/logical_not_float.x64.asm @@ -110,11 +110,10 @@ Disassembly of section .text: popq %rbp retq xorq %rax, %rax + xorq %rcx, %rcx movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 ucomisd %xmm15, %xmm0 sete %al movzbq %al, %rax @@ -127,12 +126,11 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 + xorq %rcx, %rcx movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - xorq %rax, %rax - cvtss2sd %xmm0, %xmm0 - movq %rax, %xmm15 + cvtss2sd %xmm14, %xmm0 + movq %rcx, %xmm15 ucomisd %xmm15, %xmm0 sete %al movzbq %al, %rax @@ -184,5 +182,3 @@ Disassembly of section .text: addq $0x10, %rsp popq %rbp retq - addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm b/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm index bee1fb173..23de2d848 100644 --- a/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm +++ b/tests/snapshots/asm/out_pointer_return_float_args.aarch64.asm @@ -93,18 +93,14 @@ Disassembly of section .text: sub sp, sp, #0x130 str x20, [sp] str x21, [sp, #0x8] - mov x20, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4000000000000000 // =4611686018427387904 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x4008000000000000 // =4613937818241073152 - fmov d16, x0 - fcvt s2, d16 - mov x0, #0x4010000000000000 // =4616189618054758400 - fmov d16, x0 - fcvt s3, d16 + mov x20, #0x3f800000 // =1065353216 + mov x1, #0x40000000 // =1073741824 + mov x2, #0x40400000 // =1077936128 + mov x3, #0x40800000 // =1082130432 + fmov d0, x20 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 bl sub x16, x29, #0xa8 str s0, [x16] @@ -122,18 +118,16 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0x10 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne mov x20, #0x1 // =1 cbnz x0, sub x0, x29, #0x10 ldr s0, [x0, #0x4] - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 cset x20, ne @@ -141,20 +135,18 @@ Disassembly of section .text: cbnz x20, sub x0, x29, #0x10 ldr s0, [x0, #0x8] - mov x0, #0x4008000000000000 // =4613937818241073152 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40400000 // =1077936128 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 cset x21, ne cbnz x21, sub x0, x29, #0x10 ldr s0, [x0, #0xc] - mov x0, #0x4010000000000000 // =4616189618054758400 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40800000 // =1082130432 + fmov s17, w0 + fcmp s0, s17 cset x21, ne cbz x21, mov x0, #0x1 // =1 @@ -163,21 +155,16 @@ Disassembly of section .text: add sp, sp, #0x130 ldp x29, x30, [sp], #0x10 ret - mov x20, #0x3ff8000000000000 // =4609434218613702656 - fmov d16, x20 - fcvt s0, d16 - mov x0, #0x4004000000000000 // =4612811918334230528 - fmov d16, x0 - fcvt s1, d16 - mov x0, #0x400c000000000000 // =4615063718147915776 - fmov d16, x0 - fcvt s2, d16 - mov x0, #0x4012000000000000 // =4616752568008179712 - fmov d16, x0 - fcvt s3, d16 - mov x0, #0x4016000000000000 // =4617878467915022336 - fmov d16, x0 - fcvt s4, d16 + mov x20, #0x3fc00000 // =1069547520 + mov x1, #0x40200000 // =1075838976 + mov x2, #0x40600000 // =1080033280 + mov x3, #0x40900000 // =1083179008 + mov x4, #0x40b00000 // =1085276160 + fmov d0, x20 + fmov d1, x1 + fmov d2, x2 + fmov d3, x3 + fmov d4, x4 sub x8, x29, #0xd8 bl sub x0, x29, #0xd8 @@ -199,18 +186,16 @@ Disassembly of section .text: mov x0, x1 sub x0, x29, #0x38 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x20 - fcmp d0, d17 + fmov s17, w20 + fcmp s0, s17 cset x0, ne mov x20, #0x1 // =1 cbnz x0, sub x0, x29, #0x38 ldr s0, [x0, #0x4] - mov x0, #0x4004000000000000 // =4612811918334230528 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40200000 // =1075838976 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 cset x20, ne @@ -218,10 +203,9 @@ Disassembly of section .text: cbnz x20, sub x0, x29, #0x38 ldr s0, [x0, #0x8] - mov x0, #0x400c000000000000 // =4615063718147915776 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40600000 // =1080033280 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 cset x21, ne @@ -229,20 +213,18 @@ Disassembly of section .text: cbnz x21, sub x0, x29, #0x38 ldr s0, [x0, #0xc] - mov x0, #0x4012000000000000 // =4616752568008179712 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40900000 // =1083179008 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cmp x0, #0x0 cset x20, ne cbnz x20, sub x0, x29, #0x38 ldr s0, [x0, #0x10] - mov x0, #0x4016000000000000 // =4617878467915022336 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40b00000 // =1085276160 + fmov s17, w0 + fcmp s0, s17 cset x20, ne cbz x20, mov x0, #0x2 // =2 diff --git a/tests/snapshots/asm/out_pointer_return_float_args.x64.asm b/tests/snapshots/asm/out_pointer_return_float_args.x64.asm index b49b87843..fb30fd8f5 100644 --- a/tests/snapshots/asm/out_pointer_return_float_args.x64.asm +++ b/tests/snapshots/asm/out_pointer_return_float_args.x64.asm @@ -146,18 +146,14 @@ Disassembly of section .text: subq $0x170, %rsp # imm = 0x170 movq %rbx, (%rsp) movq %r12, 0x8(%rsp) - movabsq $0x3ff0000000000000, %rbx # imm = 0x3FF0000000000000 - movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm1 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm2 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm3 + movl $0x3f800000, %ebx # imm = 0x3F800000 + movl $0x40000000, %esi # imm = 0x40000000 + movl $0x40400000, %edx # imm = 0x40400000 + movl $0x40800000, %ecx # imm = 0x40800000 + movq %rbx, %xmm0 + movq %rsi, %xmm1 + movq %rdx, %xmm2 + movq %rcx, %xmm3 callq movsd %xmm0, -0xa8(%rbp,%riz) movsd %xmm1, -0xa0(%rbp,%riz) @@ -172,9 +168,8 @@ Disassembly of section .text: movq %rcx, %rax leaq -0x10(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -185,10 +180,9 @@ Disassembly of section .text: jne leaq -0x10(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -202,10 +196,9 @@ Disassembly of section .text: jne leaq -0x10(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x4008000000000000, %rax # imm = 0x4008000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40400000, %eax # imm = 0x40400000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -218,10 +211,9 @@ Disassembly of section .text: jne leaq -0x10(%rbp), %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4010000000000000, %rax # imm = 0x4010000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40800000, %eax # imm = 0x40800000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %r12b movzbq %r12b, %r12 setp %r10b @@ -236,38 +228,33 @@ Disassembly of section .text: popq %rbp retq leaq -0xd8(%rbp), %rdi - movabsq $0x3ff8000000000000, %rbx # imm = 0x3FF8000000000000 + movl $0x3fc00000, %ebx # imm = 0x3FC00000 movq %rbx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0xe8(%rbp) movq -0xe8(%rbp), %rsi - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0xf0(%rbp) movq -0xf0(%rbp), %rdx - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0xf8(%rbp) movq -0xf8(%rbp), %rcx - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0x100(%rbp) movq -0x100(%rbp), %r8 - movabsq $0x4016000000000000, %rax # imm = 0x4016000000000000 + movl $0x40b00000, %eax # imm = 0x40B00000 movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 - cvtss2sd %xmm0, %xmm0 + cvtss2sd %xmm14, %xmm0 movq %xmm0, %r10 movq %r10, -0x108(%rbp) movq -0x108(%rbp), %r9 @@ -291,9 +278,8 @@ Disassembly of section .text: movq %rcx, %rax leaq -0x38(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rbx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -304,10 +290,9 @@ Disassembly of section .text: jne leaq -0x38(%rbp), %rax movss 0x4(%rax,%riz), %xmm0 - movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40200000, %eax # imm = 0x40200000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -321,10 +306,9 @@ Disassembly of section .text: jne leaq -0x38(%rbp), %rax movss 0x8(%rax,%riz), %xmm0 - movabsq $0x400c000000000000, %rax # imm = 0x400C000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40600000, %eax # imm = 0x40600000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -338,10 +322,9 @@ Disassembly of section .text: jne leaq -0x38(%rbp), %rax movss 0xc(%rax,%riz), %xmm0 - movabsq $0x4012000000000000, %rax # imm = 0x4012000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40900000, %eax # imm = 0x40900000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -354,10 +337,9 @@ Disassembly of section .text: jne leaq -0x38(%rbp), %rax movss 0x10(%rax,%riz), %xmm0 - movabsq $0x4016000000000000, %rax # imm = 0x4016000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40b00000, %eax # imm = 0x40B00000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %bl movzbq %bl, %rbx setp %r10b @@ -448,3 +430,4 @@ Disassembly of section .text: jmp jmp jmp + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm b/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm index 6fb5cfdc9..e8430ce89 100644 --- a/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm +++ b/tests/snapshots/asm/param_fp_before_int_pressure.aarch64.asm @@ -41,29 +41,29 @@ Disassembly of section .text: sub sp, sp, #0x50 mov x0, #0x7 // =7 stur w0, [x29, #-0x8] - mov x0, #0x1 // =1 - mov x1, #0x2 // =2 - mov x2, #0x3 // =3 - sub x3, x29, #0x8 - mov x4, #0x4 // =4 - mov x5, #0x5 // =5 + mov x1, #0x1 // =1 + mov x2, #0x2 // =2 + mov x3, #0x3 // =3 + sub x4, x29, #0x8 + mov x5, #0x4 // =4 + mov x6, #0x5 // =5 mov x17, #0x86a0 // =34464 movk x17, #0x1, lsl #16 - mul x0, x0, x17 + mul x0, x1, x17 mov x17, #0x2710 // =10000 - mul x1, x1, x17 + mul x1, x2, x17 add x0, x0, x1 mov x17, #0x3e8 // =1000 - mul x1, x2, x17 + mul x1, x3, x17 add x0, x0, x1 - ldrsw x1, [x3] + ldrsw x1, [x4] mov x17, #0x64 // =100 mul x1, x1, x17 add x0, x0, x1 mov x17, #0xa // =10 - mul x1, x4, x17 + mul x1, x5, x17 add x0, x0, x1 - add x0, x0, x5 + add x0, x0, x6 sxtw x0, w0 mov x17, #0xe361 // =58209 movk x17, #0x1, lsl #16 diff --git a/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm b/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm index e907fd96d..598d6a17f 100644 --- a/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm +++ b/tests/snapshots/asm/param_fp_before_int_pressure.x64.asm @@ -33,34 +33,39 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x50, %rsp + subq $0x60, %rsp + movq %rbx, (%rsp) movl $0x7, %eax movl %eax, -0x8(%rbp) - movl $0x1, %eax - movl $0x2, %ecx - movl $0x3, %edx - leaq -0x8(%rbp), %rsi - movl $0x4, %edi - movl $0x5, %r8d - imulq $0x186a0, %rax, %rax # imm = 0x186A0 - imulq $0x2710, %rcx, %rcx # imm = 0x2710 + movl $0x1, %ecx + movl $0x2, %edx + movl $0x3, %esi + leaq -0x8(%rbp), %rdi + movl $0x4, %r8d + movl $0x5, %r9d + imulq $0x186a0, %rcx, %rax # imm = 0x186A0 + imulq $0x2710, %rdx, %rcx # imm = 0x2710 addq %rcx, %rax - imulq $0x3e8, %rdx, %rcx # imm = 0x3E8 + imulq $0x3e8, %rsi, %rcx # imm = 0x3E8 addq %rcx, %rax - movslq (%rsi), %rcx + movslq (%rdi), %rcx imulq $0x64, %rcx, %rcx addq %rcx, %rax - imulq $0xa, %rdi, %rcx + imulq $0xa, %r8, %rcx addq %rcx, %rax - addq %r8, %rax + addq %r9, %rax movslq %eax, %rax cmpq $0x1e361, %rax # imm = 0x1E361 je movl $0x1, %eax - addq $0x50, %rsp + movq (%rsp), %rbx + addq $0x60, %rsp popq %rbp retq xorq %rax, %rax - addq $0x50, %rsp + movq (%rsp), %rbx + addq $0x60, %rsp popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm b/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm index cdef9ff71..f22655e29 100644 --- a/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm +++ b/tests/snapshots/asm/ternary_arith_conversion.aarch64.asm @@ -95,10 +95,11 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 + fcvt d0, s16 sub x17, x29, #0x40 - str d16, [x17] + str d0, [x17] b mov x2, #0x4000000000000000 // =4611686018427387904 fmov d16, x2 @@ -116,10 +117,11 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret b - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 + fcvt d0, s16 sub x17, x29, #0x48 - str d16, [x17] + str d0, [x17] b mov x2, #0x4000000000000000 // =4611686018427387904 fmov d16, x2 @@ -136,20 +138,21 @@ Disassembly of section .text: add sp, sp, #0x70 ldp x29, x30, [sp], #0x10 ret - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 sub x17, x29, #0x50 - str d16, [x17] + str s16, [x17] b mov x2, #0x2 // =2 scvtf d0, x2 + fcvt s0, d0 sub x17, x29, #0x50 - str d0, [x17] + str s0, [x17] sub x16, x29, #0x50 - ldr d0, [x16] - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d17, x2 - fcmp d0, d17 + ldr s0, [x16] + mov x2, #0x3f800000 // =1065353216 + fmov s17, w2 + fcmp s0, s17 cset x2, ne cbz x2, mov x0, #0x11 // =17 @@ -157,20 +160,21 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret b - mov x2, #0x3ff0000000000000 // =4607182418800017408 - fmov d16, x2 + mov x2, #0x3f800000 // =1065353216 + fmov s16, w2 sub x17, x29, #0x58 - str d16, [x17] + str s16, [x17] b mov x2, #0x2 // =2 scvtf d0, x2 + fcvt s0, d0 sub x17, x29, #0x58 - str d0, [x17] + str s0, [x17] sub x16, x29, #0x58 - ldr d0, [x16] - mov x2, #0x4000000000000000 // =4611686018427387904 - fmov d17, x2 - fcmp d0, d17 + ldr s0, [x16] + mov x2, #0x40000000 // =1073741824 + fmov s17, w2 + fcmp s0, s17 cset x2, ne cbz x2, mov x0, #0x12 // =18 diff --git a/tests/snapshots/asm/ternary_arith_conversion.x64.asm b/tests/snapshots/asm/ternary_arith_conversion.x64.asm index df10a6466..36c8c7ee2 100644 --- a/tests/snapshots/asm/ternary_arith_conversion.x64.asm +++ b/tests/snapshots/asm/ternary_arith_conversion.x64.asm @@ -104,9 +104,10 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x40(%rbp,%riz) + cvtss2sd %xmm14, %xmm0 + movsd %xmm0, -0x40(%rbp,%riz) jmp movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 movq %rdx, %xmm14 @@ -127,9 +128,10 @@ Disassembly of section .text: popq %rbp retq jmp - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x48(%rbp,%riz) + cvtss2sd %xmm14, %xmm0 + movsd %xmm0, -0x48(%rbp,%riz) jmp movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 movq %rdx, %xmm14 @@ -149,17 +151,18 @@ Disassembly of section .text: addq $0x70, %rsp popq %rbp retq - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x50(%rbp,%riz) + movss %xmm14, -0x50(%rbp,%riz) jmp movl $0x2, %edx cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x50(%rbp,%riz) - movsd -0x50(%rbp,%riz), %xmm0 - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x50(%rbp,%riz) + movss -0x50(%rbp,%riz), %xmm0 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %dl movzbq %dl, %rdx setp %r10b @@ -172,17 +175,18 @@ Disassembly of section .text: popq %rbp retq jmp - movabsq $0x3ff0000000000000, %rdx # imm = 0x3FF0000000000000 + movl $0x3f800000, %edx # imm = 0x3F800000 movq %rdx, %xmm14 - movsd %xmm14, -0x58(%rbp,%riz) + movss %xmm14, -0x58(%rbp,%riz) jmp movl $0x2, %edx cvtsi2sd %rdx, %xmm0 - movsd %xmm0, -0x58(%rbp,%riz) - movsd -0x58(%rbp,%riz), %xmm0 - movabsq $0x4000000000000000, %rdx # imm = 0x4000000000000000 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, -0x58(%rbp,%riz) + movss -0x58(%rbp,%riz), %xmm0 + movl $0x40000000, %edx # imm = 0x40000000 movq %rdx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %dl movzbq %dl, %rdx setp %r10b diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm index 0a801748f..73eedd8ee 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.aarch64.asm @@ -62,11 +62,10 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x70 - str d8, [sp] - str x20, [sp, #0x10] - str x21, [sp, #0x18] - str x19, [sp, #0x20] + sub sp, sp, #0x60 + str x20, [sp] + str x21, [sp, #0x8] + str x19, [sp, #0x10] mov x20, #0x0 // =0 sxtw x0, w20 cmp x0, #0xc @@ -77,9 +76,11 @@ Disassembly of section .text: b mov x21, #0x0 // =0 b + mov x0, #0x0 // =0 + fmov s16, w0 + sub x17, x29, #0x18 + str s16, [x17] mov x1, #0x0 // =0 - fmov d16, x1 - fcvt s8, d16 b sxtw x0, w21 cmp x0, #0x4 @@ -130,11 +131,10 @@ Disassembly of section .text: bl sxtw x0, w0 mov x0, #0x1 // =1 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x19, [sp, #0x10] + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret b @@ -145,22 +145,27 @@ Disassembly of section .text: sxtw x0, w1 add x1, x0, #0x1 b + sub x16, x29, #0x18 + ldr s0, [x16] adrp x0, add x0, x0, sxtw x2, w1 lsl x2, x2, #4 add x0, x0, x2 - ldr s0, [x0] - ldr s1, [x0, #0x4] - fadd s0, s0, s1 - ldr s1, [x0, #0x8] + ldr s1, [x0] + ldr s2, [x0, #0x4] + fadd s1, s1, s2 + ldr s2, [x0, #0x8] + fadd s1, s1, s2 fadd s0, s0, s1 - fadd s8, s8, s0 + sub x17, x29, #0x18 + str s0, [x17] b + sub x16, x29, #0x18 + ldr s0, [x16] mov x0, #0x0 // =0 - fcvt d0, s8 - fmov d17, x0 - fcmp d0, d17 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x20, #0x2 // =2 @@ -168,22 +173,22 @@ Disassembly of section .text: bl adrp x1, add x1, x1, - fcvt d0, s8 + sub x16, x29, #0x18 + ldr s0, [x16] + fcvt d0, s0 bl sxtw x0, w0 mov x0, x20 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x19, [sp, #0x10] + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - ldr x20, [sp, #0x10] - ldr x21, [sp, #0x18] - ldr d8, [sp] - ldr x19, [sp, #0x20] - add sp, sp, #0x70 + ldr x20, [sp] + ldr x21, [sp, #0x8] + ldr x19, [sp, #0x10] + add sp, sp, #0x60 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm index b30ea8024..0f30d2b9f 100644 --- a/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm +++ b/tests/snapshots/asm/two_d_float_array_partial_init.x64.asm @@ -56,7 +56,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x50, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rbx, %rbx @@ -69,10 +69,10 @@ Disassembly of section .text: jmp xorq %r12, %r12 jmp + xorq %rax, %rax + movq %rax, %xmm14 + movss %xmm14, -0x18(%rbp,%riz) xorq %rcx, %rcx - movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm14 - movsd %xmm14, 0x18(%rsp) jmp movslq %r12d, %rax cmpq $0x4, %rax @@ -129,7 +129,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq jmp @@ -140,24 +140,23 @@ Disassembly of section .text: movslq %ecx, %rax leaq 0x1(%rax), %rcx jmp + movss -0x18(%rbp,%riz), %xmm0 leaq , %rax movslq %ecx, %rdx shlq $0x4, %rdx addq %rdx, %rax - movss (%rax,%riz), %xmm0 - movss 0x4(%rax,%riz), %xmm1 - addss %xmm1, %xmm0 - movss 0x8(%rax,%riz), %xmm1 + movss (%rax,%riz), %xmm1 + movss 0x4(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 + movss 0x8(%rax,%riz), %xmm2 + addss %xmm2, %xmm1 addss %xmm1, %xmm0 - movsd 0x18(%rsp), %xmm14 - addss %xmm0, %xmm14 - movsd %xmm14, 0x18(%rsp) + movss %xmm0, -0x18(%rbp,%riz) jmp + movss -0x18(%rbp,%riz), %xmm0 xorq %rax, %rax - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -170,20 +169,21 @@ Disassembly of section .text: callq movq %rax, %rdi leaq , %rsi - movsd 0x18(%rsp), %xmm14 - cvtss2sd %xmm14, %xmm0 + movss -0x18(%rbp,%riz), %xmm0 + cvtss2sd %xmm0, %xmm0 movb $0x1, %al callq movslq %eax, %rax movq %rbx, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x60, %rsp + addq $0x50, %rsp popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm index 457e43b43..0b81cf616 100644 --- a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm +++ b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.aarch64.asm @@ -46,19 +46,16 @@ Disassembly of section .text: add x0, x0, x3 scvtf d0, x2 fcvt s0, d0 - mov x2, #0x3fd0000000000000 // =4598175219545276416 - fcvt d0, s0 - fmov d17, x2 - fmul d0, d0, d17 - fcvt s0, d0 + mov x2, #0x3e800000 // =1048576000 + fmov s17, w2 + fmul s0, s0, s17 str s0, [x0] b sub x0, x29, #0x508 ldr s0, [x0, #0x20] - mov x0, #0x4000000000000000 // =4611686018427387904 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x40000000 // =1073741824 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x2 // =2 @@ -66,16 +63,13 @@ Disassembly of section .text: ldp x29, x30, [sp], #0x10 ret sub x0, x29, #0x508 - mov x1, #0xc00000000000 // =211106232532992 - movk x1, #0x4058, lsl #48 - fmov d16, x1 - fcvt s0, d16 - str s0, [x0] + mov x1, #0x42c60000 // =1120272384 + fmov s16, w1 + str s16, [x0] sub x0, x29, #0x508 ldr s0, [x0] - fcvt d0, s0 - fmov d17, x1 - fcmp d0, d17 + fmov s17, w1 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x3 // =3 diff --git a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm index 89100c389..2706d42d4 100644 --- a/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm +++ b/tests/snapshots/asm/two_d_stride_no_leak_across_exprs.x64.asm @@ -48,19 +48,16 @@ Disassembly of section .text: addq %rsi, %rax cvtsi2sd %rdx, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x3fd0000000000000, %rdx # imm = 0x3FD0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x3e800000, %edx # imm = 0x3E800000 movq %rdx, %xmm15 - mulsd %xmm15, %xmm0 - cvtsd2ss %xmm0, %xmm0 + mulss %xmm15, %xmm0 movss %xmm0, (%rax,%riz) jmp leaq -0x508(%rbp), %rax movss 0x20(%rax,%riz), %xmm0 - movabsq $0x4000000000000000, %rax # imm = 0x4000000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x40000000, %eax # imm = 0x40000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -73,15 +70,13 @@ Disassembly of section .text: popq %rbp retq leaq -0x508(%rbp), %rax - movabsq $0x4058c00000000000, %rcx # imm = 0x4058C00000000000 + movl $0x42c60000, %ecx # imm = 0x42C60000 movq %rcx, %xmm14 - cvtsd2ss %xmm14, %xmm0 - movss %xmm0, (%rax,%riz) + movss %xmm14, (%rax,%riz) leaq -0x508(%rbp), %rax movss (%rax,%riz), %xmm0 - cvtss2sd %xmm0, %xmm0 movq %rcx, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -97,3 +92,4 @@ Disassembly of section .text: addq $0x520, %rsp # imm = 0x520 popq %rbp retq + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/uint64_to_float.aarch64.asm b/tests/snapshots/asm/uint64_to_float.aarch64.asm index 6be1cf4a9..0aab28804 100644 --- a/tests/snapshots/asm/uint64_to_float.aarch64.asm +++ b/tests/snapshots/asm/uint64_to_float.aarch64.asm @@ -79,10 +79,9 @@ Disassembly of section .text: ret ucvtf d0, x0 fcvt s0, d0 - mov x0, #0x43e0000000000000 // =4890909195324358656 - fcvt d0, s0 - fmov d17, x0 - fcmp d0, d17 + mov x0, #0x5f000000 // =1593835520 + fmov s17, w0 + fcmp s0, s17 cset x0, ne cbz x0, mov x0, #0x6 // =6 diff --git a/tests/snapshots/asm/uint64_to_float.x64.asm b/tests/snapshots/asm/uint64_to_float.x64.asm index 6c45131dc..6b1e2d147 100644 --- a/tests/snapshots/asm/uint64_to_float.x64.asm +++ b/tests/snapshots/asm/uint64_to_float.x64.asm @@ -148,10 +148,9 @@ Disassembly of section .text: cvtsi2sd %r11, %xmm0 addsd %xmm0, %xmm0 cvtsd2ss %xmm0, %xmm0 - movabsq $0x43e0000000000000, %rax # imm = 0x43E0000000000000 - cvtss2sd %xmm0, %xmm0 + movl $0x5f000000, %eax # imm = 0x5F000000 movq %rax, %xmm15 - ucomisd %xmm15, %xmm0 + ucomiss %xmm15, %xmm0 setne %al movzbq %al, %rax setp %r10b @@ -167,4 +166,5 @@ Disassembly of section .text: addq $0x30, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/volatile_param_classes.aarch64.asm b/tests/snapshots/asm/volatile_param_classes.aarch64.asm index 904d6827a..36a72fe4a 100644 --- a/tests/snapshots/asm/volatile_param_classes.aarch64.asm +++ b/tests/snapshots/asm/volatile_param_classes.aarch64.asm @@ -104,9 +104,8 @@ Disassembly of section .text: add sp, sp, #0x40 ldp x29, x30, [sp], #0x10 ret - mov x0, #0x4014000000000000 // =4617315517961601024 - fmov d16, x0 - fcvt s0, d16 + mov x0, #0x40a00000 // =1084227584 + fmov d0, x0 bl mov x0, #0x4004000000000000 // =4612811918334230528 fmov d17, x0 diff --git a/tests/snapshots/asm/volatile_param_classes.x64.asm b/tests/snapshots/asm/volatile_param_classes.x64.asm index 48e885f7b..d857099c3 100644 --- a/tests/snapshots/asm/volatile_param_classes.x64.asm +++ b/tests/snapshots/asm/volatile_param_classes.x64.asm @@ -111,9 +111,8 @@ Disassembly of section .text: addq $0x40, %rsp popq %rbp retq - movabsq $0x4014000000000000, %rax # imm = 0x4014000000000000 - movq %rax, %xmm14 - cvtsd2ss %xmm14, %xmm0 + movl $0x40a00000, %edi # imm = 0x40A00000 + movq %rdi, %xmm0 callq movabsq $0x4004000000000000, %rax # imm = 0x4004000000000000 movq %rax, %xmm15 @@ -136,5 +135,4 @@ Disassembly of section .text: popq %rbp retq jmp - addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa b/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa index 979d55492..978fb78e6 100644 --- a/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa +++ b/tests/snapshots/ssa/addr_of_intrinsic_math_float.ssa @@ -1,7 +1,7 @@ ; --- SSA dump (ok=true) ent_pc=13 --- ; name=main fn ent_pc=13 n_params=0 variadic=false locals=17 - spill_count=2 gpr_used=[3, 12, 13] fp_used=[] + spill_count=0 gpr_used=[3, 12, 13] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ImmExtCode(binding=48) -> x0 @@ -12,145 +12,125 @@ fn ent_pc=13 n_params=0 variadic=false locals=17 v6 Imm(0) -> x1 v7 ImmExtCode(binding=52) -> x13 v8 Imm(0) -> x1 - v9 Imm(4625196817309499392) -> x1 - v10 FpCast { kind=F64ToF32, value=v9 } -> d0 [f32] - v11 LoadLocal { off=-1, kind=I64 } -> x1 - v12 CallIndirect { target=v1, args=[v10], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v13 Imm(4616189618054758400) -> x0 - v14 FpCast { kind=F32ToF64, value=v12 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v13 } -> x0 - terminator Bz { cond=v15, target=b2, fall=b1 } (exit_acc=v15) + v9 Imm(1098907648) -> x7 [f32] + v10 LoadLocal { off=-1, kind=I64 } -> x1 + v11 CallIndirect { target=v1, args=[v9], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v12 Imm(1082130432) -> x0 [f32] + v13 Binop { op=fne, lhs=v11, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b2, fall=b1 } (exit_acc=v13) block 1 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 2 start_pc=0 - v17 Imm(4613262278296967578) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 LoadLocal { off=-2, kind=I64 } -> x0 - v20 CallIndirect { target=v3, args=[v18], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v21 Imm(4611686018427387904) -> x0 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v15 Imm(1076677837) -> x7 [f32] + v16 LoadLocal { off=-2, kind=I64 } -> x0 + v17 CallIndirect { target=v3, args=[v15], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v18 Imm(1073741824) -> x0 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v24 Imm(3) -> x0 - terminator Return(v24) (exit_acc=v24) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v25 Imm(4611911198408756429) -> x0 - v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] - v27 LoadLocal { off=-3, kind=I64 } -> x0 - v28 CallIndirect { target=v5, args=[v26], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v29 Imm(4613937818241073152) -> x0 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fne, lhs=v30, rhs=v29 } -> x0 - terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) + v21 Imm(1074161254) -> x7 [f32] + v22 LoadLocal { off=-3, kind=I64 } -> x0 + v23 CallIndirect { target=v5, args=[v21], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v24 Imm(1077936128) -> x0 [f32] + v25 Binop { op=fne, lhs=v23, rhs=v24 } -> x0 + terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) block 5 start_pc=0 - v32 Imm(4) -> x0 - terminator Return(v32) (exit_acc=v32) + v26 Imm(4) -> x0 + terminator Return(v26) (exit_acc=v26) block 6 start_pc=0 - v33 Imm(4613712638259704627) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d0 [f32] - v35 LoadLocal { off=-4, kind=I64 } -> x0 - v36 CallIndirect { target=v7, args=[v34], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v37 Imm(4611686018427387904) -> x0 - v38 FpCast { kind=F32ToF64, value=v36 } -> d0 - v39 Binop { op=fne, lhs=v38, rhs=v37 } -> x0 - terminator Bz { cond=v39, target=b8, fall=b7 } (exit_acc=v39) + v27 Imm(1077516698) -> x7 [f32] + v28 LoadLocal { off=-4, kind=I64 } -> x0 + v29 CallIndirect { target=v7, args=[v27], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v30 Imm(1073741824) -> x0 [f32] + v31 Binop { op=fne, lhs=v29, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v32 Imm(5) -> x0 + terminator Return(v32) (exit_acc=v32) block 8 start_pc=0 - v41 ImmExtCode(binding=49) -> x0 - v42 Imm(0) -> x1 - v43 Imm(4615063718147915776) -> x3 - v44 Fneg(v43) -> d0 - v45 FpCast { kind=F64ToF32, value=v44 } -> d0 [f32] - v46 LoadLocal { off=-5, kind=I64 } -> x1 - v47 CallIndirect { target=v41, args=[v45], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v48 FpCast { kind=F32ToF64, value=v47 } -> d0 - v49 Binop { op=fne, lhs=v48, rhs=v43 } -> x0 - terminator Bz { cond=v49, target=b10, fall=b9 } (exit_acc=v49) + v33 ImmExtCode(binding=49) -> x0 + v34 Imm(0) -> x1 + v35 Imm(1080033280) -> x3 [f32] + v36 Fneg(v35) -> d0 [f32] + v37 LoadLocal { off=-5, kind=I64 } -> x1 + v38 CallIndirect { target=v33, args=[v36], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v39 Binop { op=fne, lhs=v38, rhs=v35 } -> x0 + terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) block 9 start_pc=0 - v50 Imm(1) -> x0 - terminator Return(v50) (exit_acc=v50) + v40 Imm(1) -> x0 + terminator Return(v40) (exit_acc=v40) block 10 start_pc=0 - v51 LocalAddr(-8) -> x0 - v52 ImmData(8) -> x1 - v53 Mcpy { dst=v51, src=v52, size=24 } -> x0 - v54 Imm(4635400285215260672) -> x0 - v55 FpCast { kind=F64ToF32, value=v54 } -> d0 [f32] - v56 Imm(0) -> x0 - v57 Imm(4618328827877759386) -> x0 - v58 FpCast { kind=F64ToF32, value=v57 } -> [spill 0] [f32] - v59 Imm(0) -> x0 - v60 Imm(4611911198408756429) -> x0 - v61 FpCast { kind=F64ToF32, value=v60 } -> [spill 1] [f32] - v62 Imm(0) -> x0 - v63 LocalAddr(-8) -> x0 - v64 Imm(0) -> x1 - v65 Load { addr=v63, disp=0, kind=I64 } -> x0 - v66 LoadLocal { off=-9, kind=F32 } -> d1 [f32] - v67 CallIndirect { target=v65, args=[v55], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v68 Imm(4621256167635550208) -> x0 - v69 FpCast { kind=F32ToF64, value=v67 } -> d0 - v70 Binop { op=fne, lhs=v69, rhs=v68 } -> x0 - terminator Bz { cond=v70, target=b12, fall=b11 } (exit_acc=v70) + v41 LocalAddr(-8) -> x0 + v42 ImmData(8) -> x1 + v43 Mcpy { dst=v41, src=v42, size=24 } -> x0 + v44 Imm(1117913088) -> x0 [f32] + v45 StoreLocal { off=-9, value=v44, kind=F32 } -> - + v46 Imm(1086115021) -> x0 [f32] + v47 StoreLocal { off=-10, value=v46, kind=F32 } -> - + v48 Imm(1074161254) -> x0 [f32] + v49 StoreLocal { off=-11, value=v48, kind=F32 } -> - + v50 LocalAddr(-8) -> x0 + v51 Imm(0) -> x1 + v52 Load { addr=v50, disp=0, kind=I64 } -> x0 + v53 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v54 CallIndirect { target=v52, args=[v53], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v55 Imm(1091567616) -> x0 [f32] + v56 Binop { op=fne, lhs=v54, rhs=v55 } -> x0 + terminator Bz { cond=v56, target=b12, fall=b11 } (exit_acc=v56) block 11 start_pc=0 - v71 Imm(6) -> x0 - terminator Return(v71) (exit_acc=v71) + v57 Imm(6) -> x0 + terminator Return(v57) (exit_acc=v57) block 12 start_pc=0 - v72 LocalAddr(-8) -> x0 - v73 Imm(8) -> x1 - v74 BinopI { op=add, lhs=v72, rhs_imm=8 } -> x1 - v75 Load { addr=v72, disp=8, kind=I64 } -> x0 - v76 LoadLocal { off=-10, kind=F32 } -> d0 [f32] - v77 CallIndirect { target=v75, args=[v58], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v78 Imm(4617315517961601024) -> x0 - v79 FpCast { kind=F32ToF64, value=v77 } -> d0 - v80 Binop { op=fne, lhs=v79, rhs=v78 } -> x0 - terminator Bz { cond=v80, target=b14, fall=b13 } (exit_acc=v80) + v58 LocalAddr(-8) -> x0 + v59 Imm(8) -> x1 + v60 BinopI { op=add, lhs=v58, rhs_imm=8 } -> x1 + v61 Load { addr=v58, disp=8, kind=I64 } -> x0 + v62 LoadLocal { off=-10, kind=F32 } -> d0 [f32] + v63 CallIndirect { target=v61, args=[v62], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v64 Imm(1084227584) -> x0 [f32] + v65 Binop { op=fne, lhs=v63, rhs=v64 } -> x0 + terminator Bz { cond=v65, target=b14, fall=b13 } (exit_acc=v65) block 13 start_pc=0 - v81 Imm(7) -> x0 - terminator Return(v81) (exit_acc=v81) + v66 Imm(7) -> x0 + terminator Return(v66) (exit_acc=v66) block 14 start_pc=0 - v82 LocalAddr(-8) -> x0 - v83 Imm(16) -> x1 - v84 BinopI { op=add, lhs=v82, rhs_imm=16 } -> x1 - v85 Load { addr=v82, disp=16, kind=I64 } -> x0 - v86 LoadLocal { off=-11, kind=F32 } -> d0 [f32] - v87 CallIndirect { target=v85, args=[v61], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v88 Imm(4613937818241073152) -> x0 - v89 FpCast { kind=F32ToF64, value=v87 } -> d0 - v90 Binop { op=fne, lhs=v89, rhs=v88 } -> x0 - terminator Bz { cond=v90, target=b16, fall=b15 } (exit_acc=v90) + v67 LocalAddr(-8) -> x0 + v68 Imm(16) -> x1 + v69 BinopI { op=add, lhs=v67, rhs_imm=16 } -> x1 + v70 Load { addr=v67, disp=16, kind=I64 } -> x0 + v71 LoadLocal { off=-11, kind=F32 } -> d0 [f32] + v72 CallIndirect { target=v70, args=[v71], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v73 Imm(1077936128) -> x0 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x0 + terminator Bz { cond=v74, target=b16, fall=b15 } (exit_acc=v74) block 15 start_pc=0 - v91 Imm(8) -> x0 - terminator Return(v91) (exit_acc=v91) + v75 Imm(8) -> x0 + terminator Return(v75) (exit_acc=v75) block 16 start_pc=0 - v92 Imm(4619567317775286272) -> x0 - v93 Fneg(v92) -> d0 - v94 FpCast { kind=F64ToF32, value=v93 } -> d0 [f32] - v95 Intrinsic { kind=14, args=[v94] } -> d0 [f32] - v96 FpCast { kind=F32ToF64, value=v95 } -> d0 - v97 Binop { op=fne, lhs=v96, rhs=v92 } -> x0 - terminator Bz { cond=v97, target=b18, fall=b17 } (exit_acc=v97) + v76 Imm(1088421888) -> x0 [f32] + v77 Fneg(v76) -> d0 [f32] + v78 Intrinsic { kind=14, args=[v77] } -> d0 [f32] + v79 Binop { op=fne, lhs=v78, rhs=v76 } -> x0 + terminator Bz { cond=v79, target=b18, fall=b17 } (exit_acc=v79) block 17 start_pc=0 - v98 Imm(9) -> x0 - terminator Return(v98) (exit_acc=v98) + v80 Imm(9) -> x0 + terminator Return(v80) (exit_acc=v80) block 18 start_pc=0 - v99 Imm(4632092954238910464) -> x0 - v100 FpCast { kind=F64ToF32, value=v99 } -> d0 [f32] - v101 Intrinsic { kind=12, args=[v100] } -> d0 [f32] - v102 Imm(4619567317775286272) -> x0 - v103 FpCast { kind=F32ToF64, value=v101 } -> d0 - v104 Binop { op=fne, lhs=v103, rhs=v102 } -> x0 - terminator Bz { cond=v104, target=b20, fall=b19 } (exit_acc=v104) + v81 Imm(1111752704) -> x0 [f32] + v82 Intrinsic { kind=12, args=[v81] } -> d0 [f32] + v83 Imm(1088421888) -> x0 [f32] + v84 Binop { op=fne, lhs=v82, rhs=v83 } -> x0 + terminator Bz { cond=v84, target=b20, fall=b19 } (exit_acc=v84) block 19 start_pc=0 - v105 Imm(10) -> x0 - terminator Return(v105) (exit_acc=v105) + v85 Imm(10) -> x0 + terminator Return(v85) (exit_acc=v85) block 20 start_pc=0 - v106 Imm(0) -> x0 - terminator Return(v106) (exit_acc=v106) + v86 Imm(0) -> x0 + terminator Return(v86) (exit_acc=v86) ; --- SSA dump (ok=true) ent_pc=14 --- ; name=__c5_sys_sqrtf fn ent_pc=14 n_params=0 variadic=false locals=0 diff --git a/tests/snapshots/ssa/compound_assign_float_register_resident.ssa b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa index 3df1a0c72..d4f087ea9 100644 --- a/tests/snapshots/ssa/compound_assign_float_register_resident.ssa +++ b/tests/snapshots/ssa/compound_assign_float_register_resident.ssa @@ -4,108 +4,94 @@ fn ent_pc=0 n_params=0 variadic=false locals=5 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4636737291354636288) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d1 [f32] - v3 Imm(0) -> x0 - v4 Imm(4607182418800017408) -> x0 - v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] + v1 Imm(1120403456) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(1065353216) -> x0 [f32] + v4 StoreLocal { off=-2, value=v3, kind=F32 } -> - + v5 Imm(0) -> x1 v6 Imm(0) -> x0 - v7 Imm(0) -> x1 - v8 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v7) + terminator Jmp(b1) (exit_acc=v5) block 1 start_pc=0 - v9 Phi { incoming=[b0:v7, b2:v15], kind=I64 } -> x1 - v10 Phi { incoming=[b0:v5, b2:v31], kind=F32 } -> d0 [f32] - v11 Phi { incoming=[b0:v2, b2:v25], kind=F32 } -> d1 [f32] - v12 Extend { value=v9, kind=I32 } -> x0 - v13 BinopI { op=lt, lhs=v12, rhs_imm=8 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v7 Phi { incoming=[b0:v5, b2:v11], kind=I64 } -> x1 + v8 Extend { value=v7, kind=I32 } -> x0 + v9 BinopI { op=lt, lhs=v8, rhs_imm=8 } -> x0 + terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) block 2 start_pc=0 - v14 Extend { value=v9, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v14, rhs_imm=1 } -> x1 - v16 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v15) + v10 Extend { value=v7, kind=I32 } -> x0 + v11 BinopI { op=add, lhs=v10, rhs_imm=1 } -> x1 + v12 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v11) block 3 start_pc=0 - v17 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v18 Imm(4611686018427387904) -> x0 - v19 FpCast { kind=F32ToF64, value=v11 } -> d1 - v20 Binop { op=fsub, lhs=v19, rhs=v18 } -> d1 - v21 FpCast { kind=F64ToF32, value=v20 } -> d1 [f32] - v22 Imm(0) -> x0 - v23 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v24 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v25 Binop { op=fadd, lhs=v21, rhs=v10 } -> d1 [f32] - v26 Imm(0) -> x0 - v27 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v28 Imm(4607182418800017408) -> x0 - v29 FpCast { kind=F32ToF64, value=v10 } -> d0 - v30 Binop { op=fadd, lhs=v29, rhs=v28 } -> d0 - v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] - v32 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v31) + v13 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v14 Imm(1073741824) -> x0 [f32] + v15 Binop { op=fsub, lhs=v13, rhs=v14 } -> d0 [f32] + v16 StoreLocal { off=-1, value=v15, kind=F32 } -> - + v17 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v18 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v19 Binop { op=fadd, lhs=v17, rhs=v18 } -> d0 [f32] + v20 StoreLocal { off=-1, value=v19, kind=F32 } -> - + v21 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v22 Imm(4607182418800017408) -> x0 + v23 FpCast { kind=F32ToF64, value=v18 } -> d0 + v24 Binop { op=fadd, lhs=v23, rhs=v22 } -> d0 + v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] + v26 StoreLocal { off=-2, value=v25, kind=F32 } -> - + terminator Jmp(b2) (exit_acc=v26) block 4 start_pc=0 - v33 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v34 Imm(4638144666238189568) -> x0 - v35 FpCast { kind=F32ToF64, value=v11 } -> d1 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 - terminator Bz { cond=v36, target=b6, fall=b5 } (exit_acc=v36) + v27 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v28 Imm(1123024896) -> x0 [f32] + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v37 Imm(1) -> x0 - terminator Return(v37) (exit_acc=v37) + v30 Imm(1) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v38 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v39 Imm(4621256167635550208) -> x0 - v40 FpCast { kind=F32ToF64, value=v10 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) + v31 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v32 Imm(1091567616) -> x0 [f32] + v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x0 + terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) block 7 start_pc=0 - v42 Imm(2) -> x0 - terminator Return(v42) (exit_acc=v42) + v34 Imm(2) -> x0 + terminator Return(v34) (exit_acc=v34) block 8 start_pc=0 - v43 Imm(4602678819172646912) -> x0 - v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] - v45 Imm(0) -> x1 - v46 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v47 Imm(-4616189618054758400) -> x1 - v48 FpCast { kind=F32ToF64, value=v44 } -> d0 - v49 Binop { op=fadd, lhs=v48, rhs=v47 } -> d0 - v50 FpCast { kind=F64ToF32, value=v49 } -> d0 [f32] - v51 Imm(0) -> x1 - v52 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v53 Fneg(v43) -> d1 - v54 FpCast { kind=F32ToF64, value=v50 } -> d0 - v55 Binop { op=fne, lhs=v54, rhs=v53 } -> x0 - terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) + v35 Imm(1056964608) -> x0 [f32] + v36 StoreLocal { off=-4, value=v35, kind=F32 } -> - + v37 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v38 Imm(-4616189618054758400) -> x1 + v39 FpCast { kind=F32ToF64, value=v37 } -> d0 + v40 Binop { op=fadd, lhs=v39, rhs=v38 } -> d0 + v41 FpCast { kind=F64ToF32, value=v40 } -> d0 [f32] + v42 StoreLocal { off=-4, value=v41, kind=F32 } -> - + v43 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v44 Fneg(v35) -> d1 [f32] + v45 Binop { op=fne, lhs=v43, rhs=v44 } -> x0 + terminator Bz { cond=v45, target=b10, fall=b9 } (exit_acc=v45) block 9 start_pc=0 - v56 Imm(3) -> x0 - terminator Return(v56) (exit_acc=v56) + v46 Imm(3) -> x0 + terminator Return(v46) (exit_acc=v46) block 10 start_pc=0 - v57 Imm(4613937818241073152) -> x0 - v58 FpCast { kind=F64ToF32, value=v57 } -> d0 [f32] - v59 Imm(0) -> x0 - v60 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v61 Imm(4616189618054758400) -> x0 - v62 FpCast { kind=F32ToF64, value=v58 } -> d0 - v63 Binop { op=fmul, lhs=v62, rhs=v61 } -> d0 - v64 FpCast { kind=F64ToF32, value=v63 } -> d0 [f32] - v65 Imm(0) -> x0 - v66 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v67 Imm(4611686018427387904) -> x0 - v68 FpCast { kind=F32ToF64, value=v64 } -> d0 - v69 Binop { op=fdiv, lhs=v68, rhs=v67 } -> d0 - v70 FpCast { kind=F64ToF32, value=v69 } -> d0 [f32] - v71 Imm(0) -> x0 - v72 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v73 Imm(4618441417868443648) -> x0 - v74 FpCast { kind=F32ToF64, value=v70 } -> d0 - v75 Binop { op=fne, lhs=v74, rhs=v73 } -> x0 - terminator Bz { cond=v75, target=b12, fall=b11 } (exit_acc=v75) + v47 Imm(1077936128) -> x0 [f32] + v48 StoreLocal { off=-5, value=v47, kind=F32 } -> - + v49 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v50 Imm(4616189618054758400) -> x0 + v51 FpCast { kind=F32ToF64, value=v49 } -> d0 + v52 Binop { op=fmul, lhs=v51, rhs=v50 } -> d0 + v53 FpCast { kind=F64ToF32, value=v52 } -> d0 [f32] + v54 StoreLocal { off=-5, value=v53, kind=F32 } -> - + v55 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v56 Imm(1073741824) -> x0 [f32] + v57 Binop { op=fdiv, lhs=v55, rhs=v56 } -> d0 [f32] + v58 StoreLocal { off=-5, value=v57, kind=F32 } -> - + v59 LoadLocal { off=-5, kind=F32 } -> d0 [f32] + v60 Imm(1086324736) -> x0 [f32] + v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x0 + terminator Bz { cond=v61, target=b12, fall=b11 } (exit_acc=v61) block 11 start_pc=0 - v76 Imm(4) -> x0 - terminator Return(v76) (exit_acc=v76) + v62 Imm(4) -> x0 + terminator Return(v62) (exit_acc=v62) block 12 start_pc=0 - v77 Imm(0) -> x0 - terminator Return(v77) (exit_acc=v77) + v63 Imm(0) -> x0 + terminator Return(v63) (exit_acc=v63) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/compound_assign_int_fp.ssa b/tests/snapshots/ssa/compound_assign_int_fp.ssa index 47eabbacf..83a53b2d9 100644 --- a/tests/snapshots/ssa/compound_assign_int_fp.ssa +++ b/tests/snapshots/ssa/compound_assign_int_fp.ssa @@ -68,106 +68,107 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v46 Imm(0) -> x1 v47 LoadLocal { off=-5, kind=I32 } -> x1 v48 FpCast { kind=IntToFp, value=v45 } -> d0 - v49 Imm(4613712638259704627) -> x0 - v50 Binop { op=fadd, lhs=v48, rhs=v49 } -> d0 - v51 FpCast { kind=FpToInt, value=v50 } -> x0 - v52 Imm(0) -> x1 - v53 Extend { value=v51, kind=I32 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=9 } -> x0 - terminator Bz { cond=v54, target=b10, fall=b9 } (exit_acc=v54) + v49 Imm(1077516698) -> x0 [f32] + v50 FpCast { kind=F32ToF64, value=v49 } -> d1 + v51 Binop { op=fadd, lhs=v48, rhs=v50 } -> d0 + v52 FpCast { kind=FpToInt, value=v51 } -> x0 + v53 Imm(0) -> x1 + v54 Extend { value=v52, kind=I32 } -> x0 + v55 BinopI { op=ne, lhs=v54, rhs_imm=9 } -> x0 + terminator Bz { cond=v55, target=b10, fall=b9 } (exit_acc=v55) block 9 start_pc=0 - v55 Imm(5) -> x0 - terminator Return(v55) (exit_acc=v55) + v56 Imm(5) -> x0 + terminator Return(v56) (exit_acc=v56) block 10 start_pc=0 - v56 Imm(-10) -> x0 - v57 Imm(0) -> x1 - v58 LoadLocal { off=-6, kind=I64 } -> x1 - v59 FpCast { kind=IntToFp, value=v56 } -> d0 - v60 Imm(4636786549475560653) -> x0 - v61 Binop { op=fadd, lhs=v59, rhs=v60 } -> d0 - v62 FpCast { kind=FpToInt, value=v61 } -> x0 - v63 Imm(0) -> x1 - v64 LoadLocal { off=-6, kind=I64 } -> x1 - v65 BinopI { op=ne, lhs=v62, rhs_imm=90 } -> x0 - terminator Bz { cond=v65, target=b12, fall=b11 } (exit_acc=v65) + v57 Imm(-10) -> x0 + v58 Imm(0) -> x1 + v59 LoadLocal { off=-6, kind=I64 } -> x1 + v60 FpCast { kind=IntToFp, value=v57 } -> d0 + v61 Imm(4636786549475560653) -> x0 + v62 Binop { op=fadd, lhs=v60, rhs=v61 } -> d0 + v63 FpCast { kind=FpToInt, value=v62 } -> x0 + v64 Imm(0) -> x1 + v65 LoadLocal { off=-6, kind=I64 } -> x1 + v66 BinopI { op=ne, lhs=v63, rhs_imm=90 } -> x0 + terminator Bz { cond=v66, target=b12, fall=b11 } (exit_acc=v66) block 11 start_pc=0 - v66 Imm(6) -> x0 - terminator Return(v66) (exit_acc=v66) + v67 Imm(6) -> x0 + terminator Return(v67) (exit_acc=v67) block 12 start_pc=0 - v67 Imm(5) -> x0 - v68 Imm(0) -> x1 - v69 LoadLocal { off=-7, kind=I64 } -> x1 - v70 FpCast { kind=IntToFp, value=v67 } -> d0 - v71 Imm(4615063718147915776) -> x0 - v72 Binop { op=fmul, lhs=v70, rhs=v71 } -> d0 - v73 FpCast { kind=FpToInt, value=v72 } -> x0 - v74 Imm(0) -> x1 - v75 LoadLocal { off=-7, kind=I64 } -> x1 - v76 BinopI { op=ne, lhs=v73, rhs_imm=17 } -> x0 - terminator Bz { cond=v76, target=b14, fall=b13 } (exit_acc=v76) + v68 Imm(5) -> x0 + v69 Imm(0) -> x1 + v70 LoadLocal { off=-7, kind=I64 } -> x1 + v71 FpCast { kind=IntToFp, value=v68 } -> d0 + v72 Imm(4615063718147915776) -> x0 + v73 Binop { op=fmul, lhs=v71, rhs=v72 } -> d0 + v74 FpCast { kind=FpToInt, value=v73 } -> x0 + v75 Imm(0) -> x1 + v76 LoadLocal { off=-7, kind=I64 } -> x1 + v77 BinopI { op=ne, lhs=v74, rhs_imm=17 } -> x0 + terminator Bz { cond=v77, target=b14, fall=b13 } (exit_acc=v77) block 13 start_pc=0 - v77 Imm(7) -> x0 - terminator Return(v77) (exit_acc=v77) + v78 Imm(7) -> x0 + terminator Return(v78) (exit_acc=v78) block 14 start_pc=0 - v78 Imm(100) -> x0 - v79 Imm(0) -> x1 - v80 LoadLocal { off=-8, kind=I16 } -> x1 - v81 FpCast { kind=IntToFp, value=v78 } -> d0 - v82 Imm(4632318134220278989) -> x0 - v83 Binop { op=fadd, lhs=v81, rhs=v82 } -> d0 - v84 FpCast { kind=FpToInt, value=v83 } -> x0 - v85 Imm(0) -> x1 - v86 Extend { value=v84, kind=I16 } -> x0 - v87 BinopI { op=ne, lhs=v86, rhs_imm=150 } -> x0 - terminator Bz { cond=v87, target=b16, fall=b15 } (exit_acc=v87) + v79 Imm(100) -> x0 + v80 Imm(0) -> x1 + v81 LoadLocal { off=-8, kind=I16 } -> x1 + v82 FpCast { kind=IntToFp, value=v79 } -> d0 + v83 Imm(4632318134220278989) -> x0 + v84 Binop { op=fadd, lhs=v82, rhs=v83 } -> d0 + v85 FpCast { kind=FpToInt, value=v84 } -> x0 + v86 Imm(0) -> x1 + v87 Extend { value=v85, kind=I16 } -> x0 + v88 BinopI { op=ne, lhs=v87, rhs_imm=150 } -> x0 + terminator Bz { cond=v88, target=b16, fall=b15 } (exit_acc=v88) block 15 start_pc=0 - v88 Imm(8) -> x0 - terminator Return(v88) (exit_acc=v88) + v89 Imm(8) -> x0 + terminator Return(v89) (exit_acc=v89) block 16 start_pc=0 - v89 Imm(100) -> x0 - v90 Imm(0) -> x1 - v91 Imm(4613937818241073152) -> x1 - v92 StoreLocal { off=-10, value=v91, kind=F64 } -> - - v93 LoadLocal { off=-9, kind=I64 } -> x1 - v94 FpCast { kind=IntToFp, value=v89 } -> d0 - v95 Imm(1) -> x0 - v96 FpCast { kind=IntToFp, value=v95 } -> d1 - v97 LoadLocal { off=-10, kind=F64 } -> d2 - v98 Binop { op=fdiv, lhs=v96, rhs=v97 } -> d1 - v99 Binop { op=fadd, lhs=v94, rhs=v98 } -> d0 - v100 FpCast { kind=FpToInt, value=v99 } -> x0 - v101 Imm(0) -> x1 - v102 LoadLocal { off=-9, kind=I64 } -> x1 - v103 BinopI { op=ne, lhs=v100, rhs_imm=100 } -> x0 - terminator Bz { cond=v103, target=b18, fall=b17 } (exit_acc=v103) + v90 Imm(100) -> x0 + v91 Imm(0) -> x1 + v92 Imm(4613937818241073152) -> x1 + v93 StoreLocal { off=-10, value=v92, kind=F64 } -> - + v94 LoadLocal { off=-9, kind=I64 } -> x1 + v95 FpCast { kind=IntToFp, value=v90 } -> d0 + v96 Imm(1) -> x0 + v97 FpCast { kind=IntToFp, value=v96 } -> d1 + v98 LoadLocal { off=-10, kind=F64 } -> d2 + v99 Binop { op=fdiv, lhs=v97, rhs=v98 } -> d1 + v100 Binop { op=fadd, lhs=v95, rhs=v99 } -> d0 + v101 FpCast { kind=FpToInt, value=v100 } -> x0 + v102 Imm(0) -> x1 + v103 LoadLocal { off=-9, kind=I64 } -> x1 + v104 BinopI { op=ne, lhs=v101, rhs_imm=100 } -> x0 + terminator Bz { cond=v104, target=b18, fall=b17 } (exit_acc=v104) block 17 start_pc=0 - v104 Imm(9) -> x0 - terminator Return(v104) (exit_acc=v104) + v105 Imm(9) -> x0 + terminator Return(v105) (exit_acc=v105) block 18 start_pc=0 - v105 Imm(4609434218613702656) -> x0 - v106 StoreLocal { off=-12, value=v105, kind=F64 } -> - - v107 Imm(3) -> x0 - v108 Imm(0) -> x1 - v109 LoadLocal { off=-12, kind=F64 } -> d0 - v110 LoadLocal { off=-13, kind=I32 } -> x1 - v111 FpCast { kind=IntToFp, value=v107 } -> d1 - v112 Binop { op=fadd, lhs=v109, rhs=v111 } -> d0 - v113 StoreLocal { off=-12, value=v112, kind=F64 } -> - - v114 LoadLocal { off=-12, kind=F64 } -> d0 - v115 Imm(2) -> x0 - v116 FpCast { kind=IntToFp, value=v115 } -> d1 - v117 Binop { op=fmul, lhs=v114, rhs=v116 } -> d0 - v118 StoreLocal { off=-12, value=v117, kind=F64 } -> - - v119 LoadLocal { off=-12, kind=F64 } -> d0 - v120 Imm(4621256167635550208) -> x0 - v121 Binop { op=fne, lhs=v119, rhs=v120 } -> x0 - terminator Bz { cond=v121, target=b20, fall=b19 } (exit_acc=v121) + v106 Imm(4609434218613702656) -> x0 + v107 StoreLocal { off=-12, value=v106, kind=F64 } -> - + v108 Imm(3) -> x0 + v109 Imm(0) -> x1 + v110 LoadLocal { off=-12, kind=F64 } -> d0 + v111 LoadLocal { off=-13, kind=I32 } -> x1 + v112 FpCast { kind=IntToFp, value=v108 } -> d1 + v113 Binop { op=fadd, lhs=v110, rhs=v112 } -> d0 + v114 StoreLocal { off=-12, value=v113, kind=F64 } -> - + v115 LoadLocal { off=-12, kind=F64 } -> d0 + v116 Imm(2) -> x0 + v117 FpCast { kind=IntToFp, value=v116 } -> d1 + v118 Binop { op=fmul, lhs=v115, rhs=v117 } -> d0 + v119 StoreLocal { off=-12, value=v118, kind=F64 } -> - + v120 LoadLocal { off=-12, kind=F64 } -> d0 + v121 Imm(4621256167635550208) -> x0 + v122 Binop { op=fne, lhs=v120, rhs=v121 } -> x0 + terminator Bz { cond=v122, target=b20, fall=b19 } (exit_acc=v122) block 19 start_pc=0 - v122 Imm(10) -> x0 - terminator Return(v122) (exit_acc=v122) - block 20 start_pc=0 - v123 Imm(0) -> x0 + v123 Imm(10) -> x0 terminator Return(v123) (exit_acc=v123) + block 20 start_pc=0 + v124 Imm(0) -> x0 + terminator Return(v124) (exit_acc=v124) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/const_float_init_int_lead.ssa b/tests/snapshots/ssa/const_float_init_int_lead.ssa index 596275ffc..605067f2d 100644 --- a/tests/snapshots/ssa/const_float_init_int_lead.ssa +++ b/tests/snapshots/ssa/const_float_init_int_lead.ssa @@ -26,17 +26,16 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 block 4 start_pc=0 v13 ImmData(24) -> x0 v14 Load { addr=v13, disp=0, kind=F32 } -> d0 [f32] - v15 Imm(4609434218613702656) -> x0 - v16 FpCast { kind=F32ToF64, value=v14 } -> d0 - v17 Binop { op=feq, lhs=v16, rhs=v15 } -> x0 - v18 BinopI { op=eq, lhs=v17, rhs_imm=0 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v15 Imm(1069547520) -> x0 [f32] + v16 Binop { op=feq, lhs=v14, rhs=v15 } -> x0 + v17 BinopI { op=eq, lhs=v16, rhs_imm=0 } -> x0 + terminator Bz { cond=v17, target=b6, fall=b5 } (exit_acc=v17) block 5 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v18 Imm(3) -> x0 + terminator Return(v18) (exit_acc=v18) block 6 start_pc=0 - v20 Imm(0) -> x0 - terminator Return(v20) (exit_acc=v20) + v19 Imm(0) -> x0 + terminator Return(v19) (exit_acc=v19) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_arg_single_precision.ssa b/tests/snapshots/ssa/float_arg_single_precision.ssa index d1bd069b6..eeaae9d5d 100644 --- a/tests/snapshots/ssa/float_arg_single_precision.ssa +++ b/tests/snapshots/ssa/float_arg_single_precision.ssa @@ -36,86 +36,73 @@ fn ent_pc=2 n_params=0 variadic=false locals=7 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4609434218613702656) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4598175219545276416) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d1 [f32] - v5 Imm(0) -> x0 + v1 Imm(1069547520) -> x0 [f32] + v2 Imm(1048576000) -> x1 [f32] + v3 Imm(0) -> x2 + v4 Imm(0) -> x2 + v5 Binop { op=fmul, lhs=v1, rhs=v2 } -> d0 [f32] v6 Imm(0) -> x0 - v7 Binop { op=fmul, lhs=v2, rhs=v4 } -> d0 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v10 Imm(4600427019358961664) -> x0 - v11 FpCast { kind=F32ToF64, value=v7 } -> d0 - v12 Binop { op=fne, lhs=v11, rhs=v10 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v7 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v8 Imm(1052770304) -> x0 [f32] + v9 Binop { op=fne, lhs=v5, rhs=v8 } -> x0 + terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v10 Imm(1) -> x0 + terminator Return(v10) (exit_acc=v10) block 2 start_pc=0 - v14 Imm(4612811918334230528) -> x0 - v15 Fneg(v14) -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Imm(4616189618054758400) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Imm(0) -> x0 - v20 Imm(0) -> x0 - v21 Binop { op=fmul, lhs=v16, rhs=v18 } -> d0 [f32] - v22 Imm(0) -> x0 - v23 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v24 Imm(4621819117588971520) -> x0 - v25 Fneg(v24) -> d1 - v26 FpCast { kind=F32ToF64, value=v21 } -> d0 - v27 Binop { op=fne, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v11 Imm(1075838976) -> x0 [f32] + v12 Fneg(v11) -> d0 [f32] + v13 Imm(1082130432) -> x0 [f32] + v14 Imm(0) -> x1 + v15 Imm(0) -> x1 + v16 Binop { op=fmul, lhs=v12, rhs=v13 } -> d0 [f32] + v17 Imm(0) -> x0 + v18 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v19 Imm(1092616192) -> x0 [f32] + v20 Fneg(v19) -> d1 [f32] + v21 Binop { op=fne, lhs=v16, rhs=v20 } -> x0 + terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) block 3 start_pc=0 - v28 Imm(2) -> x0 - terminator Return(v28) (exit_acc=v28) + v22 Imm(2) -> x0 + terminator Return(v22) (exit_acc=v22) block 4 start_pc=0 - v29 Imm(4602678819172646912) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 Imm(4598175219545276416) -> x0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 Imm(4593671619917905920) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d2 [f32] - v35 Imm(0) -> x0 - v36 Imm(0) -> x0 - v37 Imm(0) -> x0 - v38 Binop { op=fadd, lhs=v30, rhs=v32 } -> d0 [f32] - v39 Binop { op=fadd, lhs=v38, rhs=v34 } -> d0 [f32] - v40 Imm(0) -> x0 - v41 LoadLocal { off=-3, kind=F32 } -> d1 [f32] - v42 Imm(4606056518893174784) -> x0 - v43 FpCast { kind=F32ToF64, value=v39 } -> d0 - v44 Binop { op=fne, lhs=v43, rhs=v42 } -> x0 - terminator Bz { cond=v44, target=b6, fall=b5 } (exit_acc=v44) + v23 Imm(1056964608) -> x0 [f32] + v24 Imm(1048576000) -> x1 [f32] + v25 Imm(1040187392) -> x2 [f32] + v26 Imm(0) -> x6 + v27 Imm(0) -> x6 + v28 Imm(0) -> x6 + v29 Binop { op=fadd, lhs=v23, rhs=v24 } -> d0 [f32] + v30 Binop { op=fadd, lhs=v29, rhs=v25 } -> d0 [f32] + v31 Imm(0) -> x0 + v32 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v33 Imm(1063256064) -> x0 [f32] + v34 Binop { op=fne, lhs=v30, rhs=v33 } -> x0 + terminator Bz { cond=v34, target=b6, fall=b5 } (exit_acc=v34) block 5 start_pc=0 - v45 Imm(3) -> x0 - terminator Return(v45) (exit_acc=v45) + v35 Imm(3) -> x0 + terminator Return(v35) (exit_acc=v35) block 6 start_pc=0 - v46 Imm(4607182418800017408) -> x0 - v47 Imm(4620693217682128896) -> x1 - v48 Binop { op=fdiv, lhs=v46, rhs=v47 } -> d0 - v49 FpCast { kind=F64ToF32, value=v48 } -> d0 [f32] - v50 Imm(0) -> x0 - v51 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v52 Imm(4625196817309499392) -> x0 - v53 FpCast { kind=F64ToF32, value=v52 } -> d1 [f32] - v54 Imm(0) -> x0 - v55 Imm(0) -> x0 - v56 Binop { op=fmul, lhs=v49, rhs=v53 } -> d0 [f32] - v57 Imm(0) -> x0 - v58 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v59 Imm(4611686018427387904) -> x0 - v60 FpCast { kind=F32ToF64, value=v56 } -> d0 - v61 Binop { op=fne, lhs=v60, rhs=v59 } -> x0 - terminator Bz { cond=v61, target=b8, fall=b7 } (exit_acc=v61) + v36 Imm(1065353216) -> x0 [f32] + v37 Imm(1090519040) -> x1 [f32] + v38 Binop { op=fdiv, lhs=v36, rhs=v37 } -> d0 [f32] + v39 Imm(0) -> x0 + v40 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v41 Imm(1098907648) -> x0 [f32] + v42 Imm(0) -> x1 + v43 Imm(0) -> x1 + v44 Binop { op=fmul, lhs=v38, rhs=v41 } -> d0 [f32] + v45 Imm(0) -> x0 + v46 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v47 Imm(1073741824) -> x0 [f32] + v48 Binop { op=fne, lhs=v44, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b8, fall=b7 } (exit_acc=v48) block 7 start_pc=0 - v62 Imm(4) -> x0 - terminator Return(v62) (exit_acc=v62) + v49 Imm(4) -> x0 + terminator Return(v49) (exit_acc=v49) block 8 start_pc=0 - v63 Imm(0) -> x0 - terminator Return(v63) (exit_acc=v63) + v50 Imm(0) -> x0 + terminator Return(v50) (exit_acc=v50) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_arith_in_static_init.ssa b/tests/snapshots/ssa/float_arith_in_static_init.ssa index 02f921fd9..f41bed584 100644 --- a/tests/snapshots/ssa/float_arith_in_static_init.ssa +++ b/tests/snapshots/ssa/float_arith_in_static_init.ssa @@ -7,76 +7,73 @@ fn ent_pc=1 n_params=0 variadic=false locals=1 v1 ImmData(40) -> x0 v2 Imm(0) -> x1 v3 Load { addr=v1, disp=0, kind=F32 } -> d0 [f32] - v4 Imm(4611686018427387904) -> x1 - v5 FpCast { kind=F32ToF64, value=v3 } -> d0 - v6 Binop { op=fne, lhs=v5, rhs=v4 } -> x1 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v4 Imm(1073741824) -> x1 [f32] + v5 Binop { op=fne, lhs=v3, rhs=v4 } -> x1 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v8 ImmData(40) -> x1 - v9 Imm(4) -> x1 - v10 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 - v11 Load { addr=v1, disp=4, kind=F32 } -> d0 [f32] - v12 Imm(4612811918334230528) -> x1 - v13 Fneg(v12) -> d1 - v14 FpCast { kind=F32ToF64, value=v11 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v13 } -> x1 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v7 ImmData(40) -> x1 + v8 Imm(4) -> x1 + v9 BinopI { op=add, lhs=v1, rhs_imm=4 } -> x1 + v10 Load { addr=v1, disp=4, kind=F32 } -> d0 [f32] + v11 Imm(1075838976) -> x1 [f32] + v12 Fneg(v11) -> d1 [f32] + v13 Binop { op=fne, lhs=v10, rhs=v12 } -> x1 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v17 ImmData(40) -> x1 - v18 Imm(8) -> x1 - v19 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 - v20 Load { addr=v1, disp=8, kind=F32 } -> d0 [f32] - v21 Imm(4622945017495814144) -> x0 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b6, fall=b5 } (exit_acc=v23) + v15 ImmData(40) -> x1 + v16 Imm(8) -> x1 + v17 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x1 + v18 Load { addr=v1, disp=8, kind=F32 } -> d0 [f32] + v19 Imm(1094713344) -> x0 [f32] + v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x0 + terminator Bz { cond=v20, target=b6, fall=b5 } (exit_acc=v20) block 5 start_pc=0 - v24 Imm(3) -> x0 - terminator Return(v24) (exit_acc=v24) + v21 Imm(3) -> x0 + terminator Return(v21) (exit_acc=v21) block 6 start_pc=0 - v25 ImmData(56) -> x0 - v26 Imm(0) -> x1 - v27 Load { addr=v25, disp=0, kind=F64 } -> d0 - v28 Imm(4616009474069663580) -> x0 - v29 Binop { op=flt, lhs=v27, rhs=v28 } -> x1 - v30 Imm(0) -> x0 - terminator Bnz { cond=v29, target=b13, fall=b7 } (exit_acc=v29) + v22 ImmData(56) -> x0 + v23 Imm(0) -> x1 + v24 Load { addr=v22, disp=0, kind=F64 } -> d0 + v25 Imm(4616009474069663580) -> x0 + v26 Binop { op=flt, lhs=v24, rhs=v25 } -> x1 + v27 Imm(0) -> x0 + terminator Bnz { cond=v26, target=b13, fall=b7 } (exit_acc=v26) block 7 start_pc=0 - v31 ImmData(56) -> x0 - v32 Imm(0) -> x1 - v33 Load { addr=v31, disp=0, kind=F64 } -> d0 - v34 Imm(4616031992067800433) -> x0 - v35 Binop { op=fgt, lhs=v33, rhs=v34 } -> x1 - v36 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v35) + v28 ImmData(56) -> x0 + v29 Imm(0) -> x1 + v30 Load { addr=v28, disp=0, kind=F64 } -> d0 + v31 Imm(4616031992067800433) -> x0 + v32 Binop { op=fgt, lhs=v30, rhs=v31 } -> x1 + v33 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v32) block 8 start_pc=0 - v37 Phi { incoming=[b13:v29, b7:v35], kind=I64 } -> x1 - v38 LoadLocal { off=-1, kind=I64 } -> x0 - terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) + v34 Phi { incoming=[b13:v26, b7:v32], kind=I64 } -> x1 + v35 LoadLocal { off=-1, kind=I64 } -> x0 + terminator Bz { cond=v34, target=b10, fall=b9 } (exit_acc=v34) block 9 start_pc=0 - v39 Imm(4) -> x0 - terminator Return(v39) (exit_acc=v39) + v36 Imm(4) -> x0 + terminator Return(v36) (exit_acc=v36) block 10 start_pc=0 - v40 ImmData(56) -> x0 - v41 Imm(8) -> x1 - v42 BinopI { op=add, lhs=v40, rhs_imm=8 } -> x1 - v43 Load { addr=v40, disp=8, kind=F64 } -> d0 - v44 Imm(4604930618986332160) -> x0 - v45 Fneg(v44) -> d1 - v46 Binop { op=fne, lhs=v43, rhs=v45 } -> x0 - terminator Bz { cond=v46, target=b12, fall=b11 } (exit_acc=v46) + v37 ImmData(56) -> x0 + v38 Imm(8) -> x1 + v39 BinopI { op=add, lhs=v37, rhs_imm=8 } -> x1 + v40 Load { addr=v37, disp=8, kind=F64 } -> d0 + v41 Imm(4604930618986332160) -> x0 + v42 Fneg(v41) -> d1 + v43 Binop { op=fne, lhs=v40, rhs=v42 } -> x0 + terminator Bz { cond=v43, target=b12, fall=b11 } (exit_acc=v43) block 11 start_pc=0 - v47 Imm(5) -> x0 - terminator Return(v47) (exit_acc=v47) + v44 Imm(5) -> x0 + terminator Return(v44) (exit_acc=v44) block 12 start_pc=0 - v48 Imm(0) -> x0 - terminator Return(v48) (exit_acc=v48) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) block 13 start_pc=0 terminator Jmp(b8) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/float_double_mix.ssa b/tests/snapshots/ssa/float_double_mix.ssa index 6f5e7c228..799ed0c8a 100644 --- a/tests/snapshots/ssa/float_double_mix.ssa +++ b/tests/snapshots/ssa/float_double_mix.ssa @@ -4,42 +4,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4591870180066957722) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 Imm(4596373779694328218) -> x0 - v5 StoreLocal { off=-2, value=v4, kind=F64 } -> - - v6 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 FpCast { kind=F32ToF64, value=v2 } -> d0 - v9 Binop { op=fadd, lhs=v8, rhs=v7 } -> d0 - v10 Imm(0) -> x0 - v11 LoadLocal { off=-3, kind=F64 } -> d1 - v12 Imm(4599075939497594061) -> x0 - v13 Binop { op=fsub, lhs=v9, rhs=v12 } -> d1 - v14 Imm(0) -> x0 - v15 LoadLocal { off=-4, kind=F64 } -> d0 - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 Binop { op=flt, lhs=v13, rhs=v17 } -> x0 - terminator Bz { cond=v18, target=b5, fall=b1 } (exit_acc=v18) + v1 Imm(1036831949) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(4596373779694328218) -> x0 + v4 StoreLocal { off=-2, value=v3, kind=F64 } -> - + v5 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v6 LoadLocal { off=-2, kind=F64 } -> d1 + v7 FpCast { kind=F32ToF64, value=v5 } -> d0 + v8 Binop { op=fadd, lhs=v7, rhs=v6 } -> d0 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-3, kind=F64 } -> d1 + v11 Imm(4599075939497594061) -> x0 + v12 Binop { op=fsub, lhs=v8, rhs=v11 } -> d1 + v13 Imm(0) -> x0 + v14 LoadLocal { off=-4, kind=F64 } -> d0 + v15 Imm(0) -> x0 + v16 FpCast { kind=IntToFp, value=v15 } -> d0 + v17 Binop { op=flt, lhs=v12, rhs=v16 } -> x0 + terminator Bz { cond=v17, target=b5, fall=b1 } (exit_acc=v17) block 1 start_pc=0 - v19 LoadLocal { off=-4, kind=F64 } -> d0 - v20 Fneg(v13) -> d1 - v21 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v20) + v18 LoadLocal { off=-4, kind=F64 } -> d0 + v19 Fneg(v12) -> d1 + v20 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v22 Phi { incoming=[b5:v13, b1:v20], kind=F64 } -> d1 - v23 LoadLocal { off=-4, kind=F64 } -> d0 - v24 Imm(4382569440205035030) -> x0 - v25 Binop { op=fgt, lhs=v22, rhs=v24 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v21 Phi { incoming=[b5:v12, b1:v19], kind=F64 } -> d1 + v22 LoadLocal { off=-4, kind=F64 } -> d0 + v23 Imm(4382569440205035030) -> x0 + v24 Binop { op=fgt, lhs=v21, rhs=v23 } -> x0 + terminator Bz { cond=v24, target=b4, fall=b3 } (exit_acc=v24) block 3 start_pc=0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v25 Imm(1) -> x0 + terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v26 Imm(0) -> x0 + terminator Return(v26) (exit_acc=v26) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -48,38 +47,37 @@ fn ent_pc=1 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4591870180066957722) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v5 FpCast { kind=F32ToF64, value=v2 } -> d0 - v6 Imm(0) -> x0 - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 Imm(4591870180174331904) -> x0 - v9 Binop { op=fsub, lhs=v5, rhs=v8 } -> d1 - v10 Imm(0) -> x0 - v11 LoadLocal { off=-3, kind=F64 } -> d0 - v12 Imm(0) -> x0 - v13 FpCast { kind=IntToFp, value=v12 } -> d0 - v14 Binop { op=flt, lhs=v9, rhs=v13 } -> x0 - terminator Bz { cond=v14, target=b5, fall=b1 } (exit_acc=v14) + v1 Imm(1036831949) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 FpCast { kind=F32ToF64, value=v3 } -> d0 + v5 Imm(0) -> x0 + v6 LoadLocal { off=-2, kind=F64 } -> d1 + v7 Imm(4591870180174331904) -> x0 + v8 Binop { op=fsub, lhs=v4, rhs=v7 } -> d1 + v9 Imm(0) -> x0 + v10 LoadLocal { off=-3, kind=F64 } -> d0 + v11 Imm(0) -> x0 + v12 FpCast { kind=IntToFp, value=v11 } -> d0 + v13 Binop { op=flt, lhs=v8, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b5, fall=b1 } (exit_acc=v13) block 1 start_pc=0 - v15 LoadLocal { off=-3, kind=F64 } -> d0 - v16 Fneg(v9) -> d1 - v17 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v16) + v14 LoadLocal { off=-3, kind=F64 } -> d0 + v15 Fneg(v8) -> d1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v18 Phi { incoming=[b5:v9, b1:v16], kind=F64 } -> d1 - v19 LoadLocal { off=-3, kind=F64 } -> d0 - v20 Imm(4352464011485697175) -> x0 - v21 Binop { op=fgt, lhs=v18, rhs=v20 } -> x0 - terminator Bz { cond=v21, target=b4, fall=b3 } (exit_acc=v21) + v17 Phi { incoming=[b5:v8, b1:v15], kind=F64 } -> d1 + v18 LoadLocal { off=-3, kind=F64 } -> d0 + v19 Imm(4352464011485697175) -> x0 + v20 Binop { op=fgt, lhs=v17, rhs=v19 } -> x0 + terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) block 3 start_pc=0 - v22 Imm(2) -> x0 - terminator Return(v22) (exit_acc=v22) + v21 Imm(2) -> x0 + terminator Return(v21) (exit_acc=v21) block 4 start_pc=0 - v23 Imm(0) -> x0 - terminator Return(v23) (exit_acc=v23) + v22 Imm(0) -> x0 + terminator Return(v22) (exit_acc=v22) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -93,64 +91,62 @@ fn ent_pc=2 n_params=0 variadic=false locals=6 v3 LoadLocal { off=-1, kind=F64 } -> d0 v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] v5 Imm(0) -> x0 - v6 Imm(4593560419918210649) -> x0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v10 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v11 Binop { op=fsub, lhs=v4, rhs=v7 } -> d2 [f32] - v12 Imm(0) -> x0 - v13 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 FpCast { kind=IntToFp, value=v14 } -> d1 - v16 FpCast { kind=F64ToF32, value=v15 } -> d1 [f32] - v17 Binop { op=flt, lhs=v11, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b9, fall=b1 } (exit_acc=v17) + v6 Imm(1039980266) -> x0 [f32] + v7 StoreLocal { off=-3, value=v6, kind=F32 } -> - + v8 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v9 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v10 Binop { op=fsub, lhs=v4, rhs=v9 } -> d2 [f32] + v11 Imm(0) -> x0 + v12 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v13 Imm(0) -> x0 + v14 FpCast { kind=IntToFp, value=v13 } -> d1 + v15 FpCast { kind=F64ToF32, value=v14 } -> d1 [f32] + v16 Binop { op=flt, lhs=v10, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b9, fall=b1 } (exit_acc=v16) block 1 start_pc=0 - v18 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v19 Fneg(v11) -> d2 [f32] - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v17 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v18 Fneg(v10) -> d2 [f32] + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v21 Phi { incoming=[b9:v11, b1:v19], kind=F32 } -> d2 [f32] - v22 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v23 Imm(4487126258331716666) -> x0 - v24 FpCast { kind=F32ToF64, value=v21 } -> d1 - v25 Binop { op=fgt, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v20 Phi { incoming=[b9:v10, b1:v18], kind=F32 } -> d2 [f32] + v21 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v22 Imm(841731191) -> x0 [f32] + v23 Binop { op=fgt, lhs=v20, rhs=v22 } -> x0 + terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) + v24 Imm(3) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v27 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v28 FpCast { kind=F32ToF64, value=v4 } -> d0 - v29 Imm(0) -> x0 - v30 LoadLocal { off=-5, kind=F64 } -> d1 - v31 LoadLocal { off=-1, kind=F64 } -> d1 - v32 Binop { op=fsub, lhs=v28, rhs=v31 } -> d1 + v25 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v26 FpCast { kind=F32ToF64, value=v4 } -> d0 + v27 Imm(0) -> x0 + v28 LoadLocal { off=-5, kind=F64 } -> d1 + v29 LoadLocal { off=-1, kind=F64 } -> d1 + v30 Binop { op=fsub, lhs=v26, rhs=v29 } -> d1 + v31 Imm(0) -> x0 + v32 LoadLocal { off=-6, kind=F64 } -> d0 v33 Imm(0) -> x0 - v34 LoadLocal { off=-6, kind=F64 } -> d0 - v35 Imm(0) -> x0 - v36 FpCast { kind=IntToFp, value=v35 } -> d0 - v37 Binop { op=flt, lhs=v32, rhs=v36 } -> x0 - terminator Bz { cond=v37, target=b10, fall=b5 } (exit_acc=v37) + v34 FpCast { kind=IntToFp, value=v33 } -> d0 + v35 Binop { op=flt, lhs=v30, rhs=v34 } -> x0 + terminator Bz { cond=v35, target=b10, fall=b5 } (exit_acc=v35) block 5 start_pc=0 - v38 LoadLocal { off=-6, kind=F64 } -> d0 - v39 Fneg(v32) -> d1 - v40 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v39) + v36 LoadLocal { off=-6, kind=F64 } -> d0 + v37 Fneg(v30) -> d1 + v38 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v37) block 6 start_pc=0 - v41 Phi { incoming=[b10:v32, b5:v39], kind=F64 } -> d1 - v42 LoadLocal { off=-6, kind=F64 } -> d0 - v43 Imm(4472406533629990549) -> x0 - v44 Binop { op=flt, lhs=v41, rhs=v43 } -> x0 - terminator Bz { cond=v44, target=b8, fall=b7 } (exit_acc=v44) + v39 Phi { incoming=[b10:v30, b5:v37], kind=F64 } -> d1 + v40 LoadLocal { off=-6, kind=F64 } -> d0 + v41 Imm(4472406533629990549) -> x0 + v42 Binop { op=flt, lhs=v39, rhs=v41 } -> x0 + terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) block 7 start_pc=0 - v45 Imm(4) -> x0 - terminator Return(v45) (exit_acc=v45) + v43 Imm(4) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v46 Imm(0) -> x0 - terminator Return(v46) (exit_acc=v46) + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) block 9 start_pc=0 terminator Jmp(b2) block 10 start_pc=0 @@ -168,37 +164,35 @@ fn ent_pc=3 n_params=0 variadic=false locals=4 v5 LoadLocal { off=-1, kind=F64 } -> d1 v6 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] v7 Imm(0) -> x0 - v8 Imm(4599676419595205767) -> x0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d1 [f32] - v10 Imm(0) -> x0 - v11 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v12 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v13 Binop { op=fsub, lhs=v6, rhs=v9 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Binop { op=flt, lhs=v13, rhs=v18 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b1 } (exit_acc=v19) + v8 Imm(1051372203) -> x0 [f32] + v9 StoreLocal { off=-3, value=v8, kind=F32 } -> - + v10 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v11 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v12 Binop { op=fsub, lhs=v6, rhs=v11 } -> d1 [f32] + v13 Imm(0) -> x0 + v14 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v15 Imm(0) -> x0 + v16 FpCast { kind=IntToFp, value=v15 } -> d0 + v17 FpCast { kind=F64ToF32, value=v16 } -> d0 [f32] + v18 Binop { op=flt, lhs=v12, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b5, fall=b1 } (exit_acc=v18) block 1 start_pc=0 - v20 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v21 Fneg(v13) -> d1 [f32] - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v21) + v19 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v20 Fneg(v12) -> d1 [f32] + v21 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v20) block 2 start_pc=0 - v23 Phi { incoming=[b5:v13, b1:v21], kind=F32 } -> d1 [f32] - v24 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v25 Imm(4502148214488346440) -> x0 - v26 FpCast { kind=F32ToF64, value=v23 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v22 Phi { incoming=[b5:v12, b1:v20], kind=F32 } -> d1 [f32] + v23 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v24 Imm(869711765) -> x0 [f32] + v25 Binop { op=fgt, lhs=v22, rhs=v24 } -> x0 + terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) block 3 start_pc=0 - v28 Imm(5) -> x0 - terminator Return(v28) (exit_acc=v28) + v26 Imm(5) -> x0 + terminator Return(v26) (exit_acc=v26) block 4 start_pc=0 - v29 Imm(0) -> x0 - terminator Return(v29) (exit_acc=v29) + v27 Imm(0) -> x0 + terminator Return(v27) (exit_acc=v27) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=4 --- diff --git a/tests/snapshots/ssa/float_increment_decrement.ssa b/tests/snapshots/ssa/float_increment_decrement.ssa index 2991c24fb..ebdd8c850 100644 --- a/tests/snapshots/ssa/float_increment_decrement.ssa +++ b/tests/snapshots/ssa/float_increment_decrement.ssa @@ -4,259 +4,249 @@ fn ent_pc=0 n_params=0 variadic=false locals=22 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4609434218613702656) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x1 - v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v5 Imm(4607182418800017408) -> x1 - v6 FpCast { kind=F32ToF64, value=v2 } -> d1 - v7 Binop { op=fadd, lhs=v6, rhs=v5 } -> d1 - v8 FpCast { kind=F64ToF32, value=v7 } -> d1 [f32] + v1 Imm(1069547520) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 Imm(4607182418800017408) -> x1 + v5 FpCast { kind=F32ToF64, value=v3 } -> d1 + v6 Binop { op=fadd, lhs=v5, rhs=v4 } -> d1 + v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] + v8 StoreLocal { off=-1, value=v7, kind=F32 } -> - v9 Imm(0) -> x1 - v10 Imm(0) -> x1 - v11 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v12 FpCast { kind=F32ToF64, value=v2 } -> d0 - v13 Binop { op=fne, lhs=v12, rhs=v1 } -> x1 - v14 Imm(0) -> x0 - terminator Bnz { cond=v13, target=b31, fall=b1 } (exit_acc=v13) + v10 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v11 Binop { op=fne, lhs=v3, rhs=v1 } -> x1 + v12 Imm(0) -> x0 + terminator Bnz { cond=v11, target=b31, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v15 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v16 Imm(4612811918334230528) -> x0 - v17 FpCast { kind=F32ToF64, value=v8 } -> d0 - v18 Binop { op=fne, lhs=v17, rhs=v16 } -> x1 - v19 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v18) + v13 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v14 Imm(1075838976) -> x0 [f32] + v15 Binop { op=fne, lhs=v13, rhs=v14 } -> x1 + v16 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v15) block 2 start_pc=0 - v20 Phi { incoming=[b31:v13, b1:v18], kind=I64 } -> x1 - v21 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v17 Phi { incoming=[b31:v11, b1:v15], kind=I64 } -> x1 + v18 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v17, target=b4, fall=b3 } (exit_acc=v17) block 3 start_pc=0 - v22 Imm(1) -> x0 - terminator Return(v22) (exit_acc=v22) + v19 Imm(1) -> x0 + terminator Return(v19) (exit_acc=v19) block 4 start_pc=0 - v23 Imm(4609434218613702656) -> x0 - v24 FpCast { kind=F64ToF32, value=v23 } -> d0 [f32] - v25 Imm(0) -> x0 - v26 LoadLocal { off=-3, kind=F32 } -> d1 [f32] - v27 Imm(4607182418800017408) -> x0 - v28 FpCast { kind=F32ToF64, value=v24 } -> d0 - v29 Binop { op=fadd, lhs=v28, rhs=v27 } -> d0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 Imm(0) -> x0 + v20 Imm(1069547520) -> x0 [f32] + v21 StoreLocal { off=-3, value=v20, kind=F32 } -> - + v22 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v23 Imm(4607182418800017408) -> x0 + v24 FpCast { kind=F32ToF64, value=v22 } -> d0 + v25 Binop { op=fadd, lhs=v24, rhs=v23 } -> d0 + v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] + v27 StoreLocal { off=-3, value=v26, kind=F32 } -> - + v28 Imm(0) -> x0 + v29 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v30 Imm(1075838976) -> x0 [f32] + v31 Binop { op=fne, lhs=v26, rhs=v30 } -> x1 v32 Imm(0) -> x0 - v33 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v34 Imm(4612811918334230528) -> x0 - v35 FpCast { kind=F32ToF64, value=v30 } -> d1 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x1 - v37 Imm(0) -> x0 - terminator Bnz { cond=v36, target=b32, fall=b5 } (exit_acc=v36) + terminator Bnz { cond=v31, target=b32, fall=b5 } (exit_acc=v31) block 5 start_pc=0 - v38 LoadLocal { off=-3, kind=F32 } -> d1 [f32] - v39 Imm(4612811918334230528) -> x0 - v40 FpCast { kind=F32ToF64, value=v30 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x1 - v42 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v41) + v33 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v34 Imm(1075838976) -> x0 [f32] + v35 Binop { op=fne, lhs=v33, rhs=v34 } -> x1 + v36 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v35) block 6 start_pc=0 - v43 Phi { incoming=[b32:v36, b5:v41], kind=I64 } -> x1 - v44 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v37 Phi { incoming=[b32:v31, b5:v35], kind=I64 } -> x1 + v38 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) block 7 start_pc=0 - v45 Imm(2) -> x0 - terminator Return(v45) (exit_acc=v45) + v39 Imm(2) -> x0 + terminator Return(v39) (exit_acc=v39) block 8 start_pc=0 - v46 Imm(4614500768194494464) -> x0 - v47 StoreLocal { off=-5, value=v46, kind=F64 } -> - - v48 LoadLocal { off=-5, kind=F64 } -> d0 - v49 Imm(-4616189618054758400) -> x1 - v50 Binop { op=fadd, lhs=v48, rhs=v49 } -> d1 - v51 StoreLocal { off=-5, value=v50, kind=F64 } -> - - v52 Imm(0) -> x1 - v53 LoadLocal { off=-6, kind=F64 } -> d1 - v54 Binop { op=fne, lhs=v48, rhs=v46 } -> x1 - v55 Imm(0) -> x0 - terminator Bnz { cond=v54, target=b33, fall=b9 } (exit_acc=v54) + v40 Imm(4614500768194494464) -> x0 + v41 StoreLocal { off=-5, value=v40, kind=F64 } -> - + v42 LoadLocal { off=-5, kind=F64 } -> d0 + v43 Imm(-4616189618054758400) -> x1 + v44 Binop { op=fadd, lhs=v42, rhs=v43 } -> d1 + v45 StoreLocal { off=-5, value=v44, kind=F64 } -> - + v46 Imm(0) -> x1 + v47 LoadLocal { off=-6, kind=F64 } -> d1 + v48 Binop { op=fne, lhs=v42, rhs=v40 } -> x1 + v49 Imm(0) -> x0 + terminator Bnz { cond=v48, target=b33, fall=b9 } (exit_acc=v48) block 9 start_pc=0 - v56 LoadLocal { off=-5, kind=F64 } -> d0 - v57 Imm(4612248968380809216) -> x0 - v58 Binop { op=fne, lhs=v56, rhs=v57 } -> x1 - v59 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v58) + v50 LoadLocal { off=-5, kind=F64 } -> d0 + v51 Imm(4612248968380809216) -> x0 + v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x1 + v53 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v52) block 10 start_pc=0 - v60 Phi { incoming=[b33:v54, b9:v58], kind=I64 } -> x1 - v61 LoadLocal { off=-19, kind=I64 } -> x0 - terminator Bz { cond=v60, target=b12, fall=b11 } (exit_acc=v60) + v54 Phi { incoming=[b33:v48, b9:v52], kind=I64 } -> x1 + v55 LoadLocal { off=-19, kind=I64 } -> x0 + terminator Bz { cond=v54, target=b12, fall=b11 } (exit_acc=v54) block 11 start_pc=0 - v62 Imm(3) -> x0 - terminator Return(v62) (exit_acc=v62) + v56 Imm(3) -> x0 + terminator Return(v56) (exit_acc=v56) block 12 start_pc=0 - v63 Imm(4614500768194494464) -> x0 - v64 StoreLocal { off=-7, value=v63, kind=F64 } -> - - v65 LoadLocal { off=-7, kind=F64 } -> d0 - v66 Imm(-4616189618054758400) -> x0 - v67 Binop { op=fadd, lhs=v65, rhs=v66 } -> d0 - v68 StoreLocal { off=-7, value=v67, kind=F64 } -> - - v69 Imm(0) -> x0 - v70 LoadLocal { off=-8, kind=F64 } -> d1 - v71 Imm(4612248968380809216) -> x0 - v72 Binop { op=fne, lhs=v67, rhs=v71 } -> x1 - v73 Imm(0) -> x0 - terminator Bnz { cond=v72, target=b34, fall=b13 } (exit_acc=v72) + v57 Imm(4614500768194494464) -> x0 + v58 StoreLocal { off=-7, value=v57, kind=F64 } -> - + v59 LoadLocal { off=-7, kind=F64 } -> d0 + v60 Imm(-4616189618054758400) -> x0 + v61 Binop { op=fadd, lhs=v59, rhs=v60 } -> d0 + v62 StoreLocal { off=-7, value=v61, kind=F64 } -> - + v63 Imm(0) -> x0 + v64 LoadLocal { off=-8, kind=F64 } -> d1 + v65 Imm(4612248968380809216) -> x0 + v66 Binop { op=fne, lhs=v61, rhs=v65 } -> x1 + v67 Imm(0) -> x0 + terminator Bnz { cond=v66, target=b34, fall=b13 } (exit_acc=v66) block 13 start_pc=0 - v74 LoadLocal { off=-7, kind=F64 } -> d0 - v75 Imm(4612248968380809216) -> x0 - v76 Binop { op=fne, lhs=v74, rhs=v75 } -> x1 - v77 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v76) + v68 LoadLocal { off=-7, kind=F64 } -> d0 + v69 Imm(4612248968380809216) -> x0 + v70 Binop { op=fne, lhs=v68, rhs=v69 } -> x1 + v71 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v70) block 14 start_pc=0 - v78 Phi { incoming=[b34:v72, b13:v76], kind=I64 } -> x1 - v79 LoadLocal { off=-20, kind=I64 } -> x0 - terminator Bz { cond=v78, target=b16, fall=b15 } (exit_acc=v78) + v72 Phi { incoming=[b34:v66, b13:v70], kind=I64 } -> x1 + v73 LoadLocal { off=-20, kind=I64 } -> x0 + terminator Bz { cond=v72, target=b16, fall=b15 } (exit_acc=v72) block 15 start_pc=0 - v80 Imm(4) -> x0 - terminator Return(v80) (exit_acc=v80) + v74 Imm(4) -> x0 + terminator Return(v74) (exit_acc=v74) block 16 start_pc=0 - v81 Imm(4607182418800017408) -> x0 - v82 FpCast { kind=F64ToF32, value=v81 } -> d0 [f32] - v83 StoreLocal { off=-9, value=v82, kind=F32 } -> - - v84 LocalAddr(-9) -> x1 - v85 Imm(0) -> x2 + v75 Imm(1065353216) -> x0 [f32] + v76 StoreLocal { off=-9, value=v75, kind=F32 } -> - + v77 LocalAddr(-9) -> x0 + v78 Imm(0) -> x1 + v79 LoadLocal { off=-10, kind=I64 } -> x1 + v80 Load { addr=v77, disp=0, kind=F32 } -> d0 [f32] + v81 Imm(4607182418800017408) -> x1 + v82 FpCast { kind=F32ToF64, value=v80 } -> d0 + v83 Binop { op=fadd, lhs=v82, rhs=v81 } -> d0 + v84 FpCast { kind=F64ToF32, value=v83 } -> d0 [f32] + v85 Store { addr=v77, disp=0, value=v84, kind=F32 } -> - v86 LoadLocal { off=-10, kind=I64 } -> x2 - v87 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] + v87 Load { addr=v77, disp=0, kind=F32 } -> d0 [f32] v88 FpCast { kind=F32ToF64, value=v87 } -> d0 v89 Binop { op=fadd, lhs=v88, rhs=v81 } -> d0 v90 FpCast { kind=F64ToF32, value=v89 } -> d0 [f32] - v91 Store { addr=v84, disp=0, value=v90, kind=F32 } -> - - v92 LoadLocal { off=-10, kind=I64 } -> x2 - v93 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] - v94 FpCast { kind=F32ToF64, value=v93 } -> d0 - v95 Binop { op=fadd, lhs=v94, rhs=v81 } -> d0 - v96 FpCast { kind=F64ToF32, value=v95 } -> d0 [f32] - v97 Store { addr=v84, disp=0, value=v96, kind=F32 } -> - - v98 LoadLocal { off=-9, kind=F32 } -> d0 [f32] - v99 Imm(4613937818241073152) -> x0 - v100 FpCast { kind=F32ToF64, value=v98 } -> d0 - v101 Binop { op=fne, lhs=v100, rhs=v99 } -> x0 - terminator Bz { cond=v101, target=b18, fall=b17 } (exit_acc=v101) + v91 Store { addr=v77, disp=0, value=v90, kind=F32 } -> - + v92 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v93 Imm(1077936128) -> x0 [f32] + v94 Binop { op=fne, lhs=v92, rhs=v93 } -> x0 + terminator Bz { cond=v94, target=b18, fall=b17 } (exit_acc=v94) block 17 start_pc=0 - v102 Imm(5) -> x0 - terminator Return(v102) (exit_acc=v102) + v95 Imm(5) -> x0 + terminator Return(v95) (exit_acc=v95) block 18 start_pc=0 - v103 LocalAddr(-12) -> x0 - v104 ImmData(16) -> x1 - v105 Mcpy { dst=v103, src=v104, size=16 } -> x0 + v96 LocalAddr(-12) -> x0 + v97 ImmData(16) -> x1 + v98 Mcpy { dst=v96, src=v97, size=16 } -> x0 + v99 LocalAddr(-12) -> x0 + v100 Load { addr=v99, disp=0, kind=F32 } -> d0 [f32] + v101 Imm(4607182418800017408) -> x1 + v102 FpCast { kind=F32ToF64, value=v100 } -> d0 + v103 Binop { op=fadd, lhs=v102, rhs=v101 } -> d0 + v104 FpCast { kind=F64ToF32, value=v103 } -> d0 [f32] + v105 Store { addr=v99, disp=0, value=v104, kind=F32 } -> - v106 LocalAddr(-12) -> x0 - v107 Load { addr=v106, disp=0, kind=F32 } -> d0 [f32] - v108 Imm(4607182418800017408) -> x1 - v109 FpCast { kind=F32ToF64, value=v107 } -> d0 - v110 Binop { op=fadd, lhs=v109, rhs=v108 } -> d0 - v111 FpCast { kind=F64ToF32, value=v110 } -> d0 [f32] - v112 Store { addr=v106, disp=0, value=v111, kind=F32 } -> - - v113 LocalAddr(-12) -> x0 - v114 BinopI { op=add, lhs=v113, rhs_imm=8 } -> x1 - v115 Load { addr=v113, disp=8, kind=F64 } -> d0 - v116 Imm(-4616189618054758400) -> x1 - v117 Binop { op=fadd, lhs=v115, rhs=v116 } -> d0 - v118 Store { addr=v113, disp=8, value=v117, kind=F64 } -> - - v119 LocalAddr(-12) -> x0 - v120 Load { addr=v119, disp=0, kind=F32 } -> d0 [f32] - v121 Imm(4612811918334230528) -> x0 - v122 FpCast { kind=F32ToF64, value=v120 } -> d0 - v123 Binop { op=fne, lhs=v122, rhs=v121 } -> x1 - v124 Imm(0) -> x0 - terminator Bnz { cond=v123, target=b35, fall=b19 } (exit_acc=v123) + v107 BinopI { op=add, lhs=v106, rhs_imm=8 } -> x1 + v108 Load { addr=v106, disp=8, kind=F64 } -> d0 + v109 Imm(-4616189618054758400) -> x1 + v110 Binop { op=fadd, lhs=v108, rhs=v109 } -> d0 + v111 Store { addr=v106, disp=8, value=v110, kind=F64 } -> - + v112 LocalAddr(-12) -> x0 + v113 Load { addr=v112, disp=0, kind=F32 } -> d0 [f32] + v114 Imm(1075838976) -> x0 [f32] + v115 Binop { op=fne, lhs=v113, rhs=v114 } -> x1 + v116 Imm(0) -> x0 + terminator Bnz { cond=v115, target=b35, fall=b19 } (exit_acc=v115) block 19 start_pc=0 - v125 LocalAddr(-12) -> x0 - v126 BinopI { op=add, lhs=v125, rhs_imm=8 } -> x1 - v127 Load { addr=v125, disp=8, kind=F64 } -> d0 - v128 Imm(4609434218613702656) -> x0 - v129 Binop { op=fne, lhs=v127, rhs=v128 } -> x1 - v130 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v129) + v117 LocalAddr(-12) -> x0 + v118 BinopI { op=add, lhs=v117, rhs_imm=8 } -> x1 + v119 Load { addr=v117, disp=8, kind=F64 } -> d0 + v120 Imm(4609434218613702656) -> x0 + v121 Binop { op=fne, lhs=v119, rhs=v120 } -> x1 + v122 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v121) block 20 start_pc=0 - v131 Phi { incoming=[b35:v123, b19:v129], kind=I64 } -> x1 - v132 LoadLocal { off=-21, kind=I64 } -> x0 - terminator Bz { cond=v131, target=b22, fall=b21 } (exit_acc=v131) + v123 Phi { incoming=[b35:v115, b19:v121], kind=I64 } -> x1 + v124 LoadLocal { off=-21, kind=I64 } -> x0 + terminator Bz { cond=v123, target=b22, fall=b21 } (exit_acc=v123) block 21 start_pc=0 - v133 Imm(6) -> x0 - terminator Return(v133) (exit_acc=v133) + v125 Imm(6) -> x0 + terminator Return(v125) (exit_acc=v125) block 22 start_pc=0 - v134 ImmData(8) -> x0 - v135 Load { addr=v134, disp=0, kind=F64 } -> d0 - v136 Imm(4607182418800017408) -> x1 - v137 Binop { op=fadd, lhs=v135, rhs=v136 } -> d0 - v138 Store { addr=v134, disp=0, value=v137, kind=F64 } -> - - v139 Load { addr=v134, disp=0, kind=F64 } -> d0 - v140 Binop { op=fadd, lhs=v139, rhs=v136 } -> d0 - v141 Store { addr=v134, disp=0, value=v140, kind=F64 } -> - - v142 Load { addr=v134, disp=0, kind=F64 } -> d0 - v143 Imm(4619567317775286272) -> x0 - v144 Binop { op=fne, lhs=v142, rhs=v143 } -> x0 - terminator Bz { cond=v144, target=b24, fall=b23 } (exit_acc=v144) + v126 ImmData(8) -> x0 + v127 Load { addr=v126, disp=0, kind=F64 } -> d0 + v128 Imm(4607182418800017408) -> x1 + v129 Binop { op=fadd, lhs=v127, rhs=v128 } -> d0 + v130 Store { addr=v126, disp=0, value=v129, kind=F64 } -> - + v131 Load { addr=v126, disp=0, kind=F64 } -> d0 + v132 Binop { op=fadd, lhs=v131, rhs=v128 } -> d0 + v133 Store { addr=v126, disp=0, value=v132, kind=F64 } -> - + v134 Load { addr=v126, disp=0, kind=F64 } -> d0 + v135 Imm(4619567317775286272) -> x0 + v136 Binop { op=fne, lhs=v134, rhs=v135 } -> x0 + terminator Bz { cond=v136, target=b24, fall=b23 } (exit_acc=v136) block 23 start_pc=0 - v145 Imm(7) -> x0 - terminator Return(v145) (exit_acc=v145) + v137 Imm(7) -> x0 + terminator Return(v137) (exit_acc=v137) block 24 start_pc=0 - v146 LocalAddr(-15) -> x0 - v147 ImmData(32) -> x1 - v148 Mcpy { dst=v146, src=v147, size=24 } -> x0 - v149 LocalAddr(-15) -> x0 - v150 Imm(8) -> x1 - v151 BinopI { op=add, lhs=v149, rhs_imm=8 } -> x1 - v152 Load { addr=v149, disp=8, kind=F64 } -> d0 - v153 Imm(4607182418800017408) -> x1 - v154 Binop { op=fadd, lhs=v152, rhs=v153 } -> d0 - v155 Store { addr=v149, disp=8, value=v154, kind=F64 } -> - - v156 LocalAddr(-15) -> x0 - v157 Imm(16) -> x1 - v158 BinopI { op=add, lhs=v156, rhs_imm=16 } -> x1 - v159 Load { addr=v156, disp=16, kind=F64 } -> d0 - v160 Imm(-4616189618054758400) -> x1 - v161 Binop { op=fadd, lhs=v159, rhs=v160 } -> d0 - v162 Store { addr=v156, disp=16, value=v161, kind=F64 } -> - - v163 LocalAddr(-15) -> x0 - v164 BinopI { op=add, lhs=v163, rhs_imm=8 } -> x1 - v165 Load { addr=v163, disp=8, kind=F64 } -> d0 - v166 Imm(4611686018427387904) -> x0 - v167 Binop { op=fne, lhs=v165, rhs=v166 } -> x1 - v168 Imm(0) -> x0 - terminator Bnz { cond=v167, target=b36, fall=b25 } (exit_acc=v167) + v138 LocalAddr(-15) -> x0 + v139 ImmData(32) -> x1 + v140 Mcpy { dst=v138, src=v139, size=24 } -> x0 + v141 LocalAddr(-15) -> x0 + v142 Imm(8) -> x1 + v143 BinopI { op=add, lhs=v141, rhs_imm=8 } -> x1 + v144 Load { addr=v141, disp=8, kind=F64 } -> d0 + v145 Imm(4607182418800017408) -> x1 + v146 Binop { op=fadd, lhs=v144, rhs=v145 } -> d0 + v147 Store { addr=v141, disp=8, value=v146, kind=F64 } -> - + v148 LocalAddr(-15) -> x0 + v149 Imm(16) -> x1 + v150 BinopI { op=add, lhs=v148, rhs_imm=16 } -> x1 + v151 Load { addr=v148, disp=16, kind=F64 } -> d0 + v152 Imm(-4616189618054758400) -> x1 + v153 Binop { op=fadd, lhs=v151, rhs=v152 } -> d0 + v154 Store { addr=v148, disp=16, value=v153, kind=F64 } -> - + v155 LocalAddr(-15) -> x0 + v156 BinopI { op=add, lhs=v155, rhs_imm=8 } -> x1 + v157 Load { addr=v155, disp=8, kind=F64 } -> d0 + v158 Imm(4611686018427387904) -> x0 + v159 Binop { op=fne, lhs=v157, rhs=v158 } -> x1 + v160 Imm(0) -> x0 + terminator Bnz { cond=v159, target=b36, fall=b25 } (exit_acc=v159) block 25 start_pc=0 - v169 LocalAddr(-15) -> x0 - v170 Imm(16) -> x1 - v171 BinopI { op=add, lhs=v169, rhs_imm=16 } -> x1 - v172 Load { addr=v169, disp=16, kind=F64 } -> d0 - v173 Imm(4607182418800017408) -> x0 - v174 Binop { op=fne, lhs=v172, rhs=v173 } -> x1 - v175 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v174) + v161 LocalAddr(-15) -> x0 + v162 Imm(16) -> x1 + v163 BinopI { op=add, lhs=v161, rhs_imm=16 } -> x1 + v164 Load { addr=v161, disp=16, kind=F64 } -> d0 + v165 Imm(4607182418800017408) -> x0 + v166 Binop { op=fne, lhs=v164, rhs=v165 } -> x1 + v167 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v166) block 26 start_pc=0 - v176 Phi { incoming=[b36:v167, b25:v174], kind=I64 } -> x1 - v177 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v176, target=b28, fall=b27 } (exit_acc=v176) + v168 Phi { incoming=[b36:v159, b25:v166], kind=I64 } -> x1 + v169 LoadLocal { off=-22, kind=I64 } -> x0 + terminator Bz { cond=v168, target=b28, fall=b27 } (exit_acc=v168) block 27 start_pc=0 - v178 Imm(8) -> x0 - terminator Return(v178) (exit_acc=v178) + v170 Imm(8) -> x0 + terminator Return(v170) (exit_acc=v170) block 28 start_pc=0 - v179 Imm(4715268809856909312) -> x0 - v180 FpCast { kind=F64ToF32, value=v179 } -> d0 [f32] - v181 Imm(0) -> x1 - v182 LoadLocal { off=-16, kind=F32 } -> d1 [f32] - v183 Imm(4607182418800017408) -> x1 - v184 FpCast { kind=F32ToF64, value=v180 } -> d0 - v185 Binop { op=fadd, lhs=v184, rhs=v183 } -> d0 - v186 FpCast { kind=F64ToF32, value=v185 } -> d0 [f32] - v187 Imm(0) -> x1 - v188 LoadLocal { off=-16, kind=F32 } -> d1 [f32] - v189 FpCast { kind=F32ToF64, value=v186 } -> d0 - v190 Binop { op=fne, lhs=v189, rhs=v179 } -> x0 - terminator Bz { cond=v190, target=b30, fall=b29 } (exit_acc=v190) + v171 Imm(1266679808) -> x0 [f32] + v172 StoreLocal { off=-16, value=v171, kind=F32 } -> - + v173 LoadLocal { off=-16, kind=F32 } -> d0 [f32] + v174 Imm(4607182418800017408) -> x1 + v175 FpCast { kind=F32ToF64, value=v173 } -> d0 + v176 Binop { op=fadd, lhs=v175, rhs=v174 } -> d0 + v177 FpCast { kind=F64ToF32, value=v176 } -> d0 [f32] + v178 StoreLocal { off=-16, value=v177, kind=F32 } -> - + v179 LoadLocal { off=-16, kind=F32 } -> d0 [f32] + v180 Binop { op=fne, lhs=v179, rhs=v171 } -> x0 + terminator Bz { cond=v180, target=b30, fall=b29 } (exit_acc=v180) block 29 start_pc=0 - v191 Imm(9) -> x0 - terminator Return(v191) (exit_acc=v191) + v181 Imm(9) -> x0 + terminator Return(v181) (exit_acc=v181) block 30 start_pc=0 - v192 Imm(0) -> x0 - terminator Return(v192) (exit_acc=v192) + v182 Imm(0) -> x0 + terminator Return(v182) (exit_acc=v182) block 31 start_pc=0 terminator Jmp(b2) block 32 start_pc=0 diff --git a/tests/snapshots/ssa/float_is_four_bytes.ssa b/tests/snapshots/ssa/float_is_four_bytes.ssa index 7eb9e802f..a9fde5c34 100644 --- a/tests/snapshots/ssa/float_is_four_bytes.ssa +++ b/tests/snapshots/ssa/float_is_four_bytes.ssa @@ -56,10 +56,10 @@ fn ent_pc=3 n_params=0 variadic=false locals=13 terminator Jmp(b4) (exit_acc=v13) block 4 start_pc=0 v15 Phi { incoming=[b2:v8, b3:v13], kind=I64 } -> x3 - v16 Imm(0) -> x0 - v17 FpCast { kind=F64ToF32, value=v16 } -> d0 [f32] - v18 Imm(0) -> x1 - terminator Jmp(b6) (exit_acc=v16) + v16 Imm(0) -> x0 [f32] + v17 Imm(0) -> x0 + v18 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v18) block 5 start_pc=0 v19 ImmData(105) -> x7 v20 Imm(4) -> x6 @@ -70,280 +70,255 @@ fn ent_pc=3 n_params=0 variadic=false locals=13 block 6 start_pc=0 v24 Phi { incoming=[b4:v15, b5:v22], kind=I64 } -> x3 v25 LocalAddr(-3) -> x0 - v26 Imm(4609434218613702656) -> x1 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Store { addr=v25, disp=0, value=v27, kind=F32 } -> - - v29 LocalAddr(-3) -> x0 - v30 BinopI { op=add, lhs=v29, rhs_imm=4 } -> x1 - v31 Imm(305419896) -> x1 - v32 Store { addr=v29, disp=4, value=v31, kind=I32 } -> - - v33 LocalAddr(-3) -> x0 - v34 Imm(0) -> x1 - v35 LoadLocal { off=-4, kind=I64 } -> x1 - v36 Imm(4) -> x1 - v37 BinopI { op=add, lhs=v33, rhs_imm=4 } -> x1 - v38 Load { addr=v33, disp=4, kind=I32 } -> x1 - v39 BinopI { op=ne, lhs=v38, rhs_imm=305419896 } -> x1 - terminator Bz { cond=v39, target=b33, fall=b7 } (exit_acc=v39) + v26 Imm(1069547520) -> x1 [f32] + v27 Store { addr=v25, disp=0, value=v26, kind=F32 } -> - + v28 LocalAddr(-3) -> x0 + v29 BinopI { op=add, lhs=v28, rhs_imm=4 } -> x1 + v30 Imm(305419896) -> x1 + v31 Store { addr=v28, disp=4, value=v30, kind=I32 } -> - + v32 LocalAddr(-3) -> x0 + v33 Imm(0) -> x1 + v34 LoadLocal { off=-4, kind=I64 } -> x1 + v35 Imm(4) -> x1 + v36 BinopI { op=add, lhs=v32, rhs_imm=4 } -> x1 + v37 Load { addr=v32, disp=4, kind=I32 } -> x1 + v38 BinopI { op=ne, lhs=v37, rhs_imm=305419896 } -> x1 + terminator Bz { cond=v38, target=b33, fall=b7 } (exit_acc=v38) block 7 start_pc=0 - v40 ImmData(126) -> x7 - v41 LoadLocal { off=-4, kind=I64 } -> x1 - v42 Imm(4) -> x3 - v43 BinopI { op=add, lhs=v33, rhs_imm=4 } -> x1 - v44 Load { addr=v33, disp=4, kind=I32 } -> x6 - v45 CallExt { binding_idx=0, args=[v40, v44], fp_arg_mask=0x0 } -> x0 - v46 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v42) + v39 ImmData(126) -> x7 + v40 LoadLocal { off=-4, kind=I64 } -> x1 + v41 Imm(4) -> x3 + v42 BinopI { op=add, lhs=v32, rhs_imm=4 } -> x1 + v43 Load { addr=v32, disp=4, kind=I32 } -> x6 + v44 CallExt { binding_idx=0, args=[v39, v43], fp_arg_mask=0x0 } -> x0 + v45 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v41) block 8 start_pc=0 - v47 Phi { incoming=[b33:v24, b7:v42], kind=I64 } -> x3 - v48 LocalAddr(-3) -> x0 - v49 Load { addr=v48, disp=0, kind=F32 } -> d0 [f32] - v50 Imm(4609434218613702656) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b34, fall=b9 } (exit_acc=v52) + v46 Phi { incoming=[b33:v24, b7:v41], kind=I64 } -> x3 + v47 LocalAddr(-3) -> x0 + v48 Load { addr=v47, disp=0, kind=F32 } -> d0 [f32] + v49 Imm(1069547520) -> x0 [f32] + v50 Binop { op=fne, lhs=v48, rhs=v49 } -> x0 + terminator Bz { cond=v50, target=b34, fall=b9 } (exit_acc=v50) block 9 start_pc=0 - v53 ImmData(163) -> x7 - v54 CallExt { binding_idx=0, args=[v53], fp_arg_mask=0x0 } -> x0 - v55 Imm(5) -> x3 - v56 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v55) + v51 ImmData(163) -> x7 + v52 CallExt { binding_idx=0, args=[v51], fp_arg_mask=0x0 } -> x0 + v53 Imm(5) -> x3 + v54 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v53) block 10 start_pc=0 - v57 Phi { incoming=[b34:v47, b9:v55], kind=I64 } -> x3 - v58 ImmData(40) -> x0 - v59 Imm(0) -> x1 - v60 Imm(4) -> x1 - v61 BinopI { op=add, lhs=v58, rhs_imm=4 } -> x1 - v62 LoadLocal { off=-5, kind=I64 } -> x2 - v63 Binop { op=sub, lhs=v61, rhs=v58 } -> x1 - v64 BinopI { op=ne, lhs=v63, rhs_imm=4 } -> x1 - terminator Bz { cond=v64, target=b35, fall=b11 } (exit_acc=v64) + v55 Phi { incoming=[b34:v46, b9:v53], kind=I64 } -> x3 + v56 ImmData(40) -> x0 + v57 Imm(0) -> x1 + v58 Imm(4) -> x1 + v59 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x1 + v60 LoadLocal { off=-5, kind=I64 } -> x2 + v61 Binop { op=sub, lhs=v59, rhs=v56 } -> x1 + v62 BinopI { op=ne, lhs=v61, rhs_imm=4 } -> x1 + terminator Bz { cond=v62, target=b35, fall=b11 } (exit_acc=v62) block 11 start_pc=0 - v65 ImmData(189) -> x7 - v66 ImmData(40) -> x1 - v67 Imm(4) -> x2 - v68 BinopI { op=add, lhs=v66, rhs_imm=4 } -> x1 - v69 LoadLocal { off=-5, kind=I64 } -> x2 - v70 Binop { op=sub, lhs=v68, rhs=v58 } -> x6 - v71 CallExt { binding_idx=0, args=[v65, v70], fp_arg_mask=0x0 } -> x0 - v72 Imm(6) -> x3 - v73 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v72) + v63 ImmData(189) -> x7 + v64 ImmData(40) -> x1 + v65 Imm(4) -> x2 + v66 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x1 + v67 LoadLocal { off=-5, kind=I64 } -> x2 + v68 Binop { op=sub, lhs=v66, rhs=v56 } -> x6 + v69 CallExt { binding_idx=0, args=[v63, v68], fp_arg_mask=0x0 } -> x0 + v70 Imm(6) -> x3 + v71 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v70) block 12 start_pc=0 - v74 Phi { incoming=[b35:v57, b11:v72], kind=I64 } -> x3 - v75 ImmData(40) -> x0 - v76 Imm(0) -> x1 - v77 Load { addr=v75, disp=0, kind=F32 } -> d0 [f32] - v78 Imm(4609434218613702656) -> x0 - v79 FpCast { kind=F32ToF64, value=v77 } -> d0 - v80 Binop { op=fne, lhs=v79, rhs=v78 } -> x0 - terminator Bz { cond=v80, target=b36, fall=b13 } (exit_acc=v80) + v72 Phi { incoming=[b35:v55, b11:v70], kind=I64 } -> x3 + v73 ImmData(40) -> x0 + v74 Imm(0) -> x1 + v75 Load { addr=v73, disp=0, kind=F32 } -> d0 [f32] + v76 Imm(1069547520) -> x0 [f32] + v77 Binop { op=fne, lhs=v75, rhs=v76 } -> x0 + terminator Bz { cond=v77, target=b36, fall=b13 } (exit_acc=v77) block 13 start_pc=0 - v81 ImmData(212) -> x7 - v82 ImmData(40) -> x0 - v83 Imm(0) -> x1 - v84 Load { addr=v82, disp=0, kind=F32 } -> d0 [f32] - v85 FpCast { kind=F32ToF64, value=v84 } -> d0 - v86 CallExt { binding_idx=0, args=[v81, v85], fp_arg_mask=0x2 } -> x0 - v87 Imm(7) -> x3 - v88 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v87) + v78 ImmData(212) -> x7 + v79 ImmData(40) -> x0 + v80 Imm(0) -> x1 + v81 Load { addr=v79, disp=0, kind=F32 } -> d0 [f32] + v82 FpCast { kind=F32ToF64, value=v81 } -> d0 + v83 CallExt { binding_idx=0, args=[v78, v82], fp_arg_mask=0x2 } -> x0 + v84 Imm(7) -> x3 + v85 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v84) block 14 start_pc=0 - v89 Phi { incoming=[b36:v74, b13:v87], kind=I64 } -> x3 - v90 ImmData(40) -> x0 - v91 Imm(4) -> x1 - v92 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x1 - v93 Load { addr=v90, disp=4, kind=F32 } -> d0 [f32] - v94 Imm(4612811918334230528) -> x0 - v95 FpCast { kind=F32ToF64, value=v93 } -> d0 - v96 Binop { op=fne, lhs=v95, rhs=v94 } -> x0 - terminator Bz { cond=v96, target=b37, fall=b15 } (exit_acc=v96) + v86 Phi { incoming=[b36:v72, b13:v84], kind=I64 } -> x3 + v87 ImmData(40) -> x0 + v88 Imm(4) -> x1 + v89 BinopI { op=add, lhs=v87, rhs_imm=4 } -> x1 + v90 Load { addr=v87, disp=4, kind=F32 } -> d0 [f32] + v91 Imm(1075838976) -> x0 [f32] + v92 Binop { op=fne, lhs=v90, rhs=v91 } -> x0 + terminator Bz { cond=v92, target=b37, fall=b15 } (exit_acc=v92) block 15 start_pc=0 - v97 ImmData(232) -> x7 - v98 ImmData(40) -> x0 - v99 Imm(4) -> x1 - v100 BinopI { op=add, lhs=v98, rhs_imm=4 } -> x1 - v101 Load { addr=v98, disp=4, kind=F32 } -> d0 [f32] - v102 FpCast { kind=F32ToF64, value=v101 } -> d0 - v103 CallExt { binding_idx=0, args=[v97, v102], fp_arg_mask=0x2 } -> x0 - v104 Imm(8) -> x3 - v105 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v104) + v93 ImmData(232) -> x7 + v94 ImmData(40) -> x0 + v95 Imm(4) -> x1 + v96 BinopI { op=add, lhs=v94, rhs_imm=4 } -> x1 + v97 Load { addr=v94, disp=4, kind=F32 } -> d0 [f32] + v98 FpCast { kind=F32ToF64, value=v97 } -> d0 + v99 CallExt { binding_idx=0, args=[v93, v98], fp_arg_mask=0x2 } -> x0 + v100 Imm(8) -> x3 + v101 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v100) block 16 start_pc=0 - v106 Phi { incoming=[b37:v89, b15:v104], kind=I64 } -> x3 - v107 ImmData(40) -> x0 - v108 Imm(8) -> x1 - v109 BinopI { op=add, lhs=v107, rhs_imm=8 } -> x1 - v110 Load { addr=v107, disp=8, kind=F32 } -> d0 [f32] - v111 Imm(4615063718147915776) -> x0 - v112 FpCast { kind=F32ToF64, value=v110 } -> d0 - v113 Binop { op=fne, lhs=v112, rhs=v111 } -> x0 - terminator Bz { cond=v113, target=b38, fall=b17 } (exit_acc=v113) + v102 Phi { incoming=[b37:v86, b15:v100], kind=I64 } -> x3 + v103 ImmData(40) -> x0 + v104 Imm(8) -> x1 + v105 BinopI { op=add, lhs=v103, rhs_imm=8 } -> x1 + v106 Load { addr=v103, disp=8, kind=F32 } -> d0 [f32] + v107 Imm(1080033280) -> x0 [f32] + v108 Binop { op=fne, lhs=v106, rhs=v107 } -> x0 + terminator Bz { cond=v108, target=b38, fall=b17 } (exit_acc=v108) block 17 start_pc=0 - v114 ImmData(252) -> x7 - v115 ImmData(40) -> x0 - v116 Imm(8) -> x1 - v117 BinopI { op=add, lhs=v115, rhs_imm=8 } -> x1 - v118 Load { addr=v115, disp=8, kind=F32 } -> d0 [f32] - v119 FpCast { kind=F32ToF64, value=v118 } -> d0 - v120 CallExt { binding_idx=0, args=[v114, v119], fp_arg_mask=0x2 } -> x0 - v121 Imm(9) -> x3 - v122 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v121) + v109 ImmData(252) -> x7 + v110 ImmData(40) -> x0 + v111 Imm(8) -> x1 + v112 BinopI { op=add, lhs=v110, rhs_imm=8 } -> x1 + v113 Load { addr=v110, disp=8, kind=F32 } -> d0 [f32] + v114 FpCast { kind=F32ToF64, value=v113 } -> d0 + v115 CallExt { binding_idx=0, args=[v109, v114], fp_arg_mask=0x2 } -> x0 + v116 Imm(9) -> x3 + v117 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v116) block 18 start_pc=0 - v123 Phi { incoming=[b38:v106, b17:v121], kind=I64 } -> x3 - v124 ImmData(40) -> x0 - v125 Imm(12) -> x1 - v126 BinopI { op=add, lhs=v124, rhs_imm=12 } -> x1 - v127 Load { addr=v124, disp=12, kind=F32 } -> d0 [f32] - v128 Imm(4616752568008179712) -> x0 - v129 FpCast { kind=F32ToF64, value=v127 } -> d0 - v130 Binop { op=fne, lhs=v129, rhs=v128 } -> x0 - terminator Bz { cond=v130, target=b39, fall=b19 } (exit_acc=v130) + v118 Phi { incoming=[b38:v102, b17:v116], kind=I64 } -> x3 + v119 ImmData(40) -> x0 + v120 Imm(12) -> x1 + v121 BinopI { op=add, lhs=v119, rhs_imm=12 } -> x1 + v122 Load { addr=v119, disp=12, kind=F32 } -> d0 [f32] + v123 Imm(1083179008) -> x0 [f32] + v124 Binop { op=fne, lhs=v122, rhs=v123 } -> x0 + terminator Bz { cond=v124, target=b39, fall=b19 } (exit_acc=v124) block 19 start_pc=0 - v131 ImmData(272) -> x7 - v132 ImmData(40) -> x0 - v133 Imm(12) -> x1 - v134 BinopI { op=add, lhs=v132, rhs_imm=12 } -> x1 - v135 Load { addr=v132, disp=12, kind=F32 } -> d0 [f32] - v136 FpCast { kind=F32ToF64, value=v135 } -> d0 - v137 CallExt { binding_idx=0, args=[v131, v136], fp_arg_mask=0x2 } -> x0 - v138 Imm(10) -> x3 - v139 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v138) + v125 ImmData(272) -> x7 + v126 ImmData(40) -> x0 + v127 Imm(12) -> x1 + v128 BinopI { op=add, lhs=v126, rhs_imm=12 } -> x1 + v129 Load { addr=v126, disp=12, kind=F32 } -> d0 [f32] + v130 FpCast { kind=F32ToF64, value=v129 } -> d0 + v131 CallExt { binding_idx=0, args=[v125, v130], fp_arg_mask=0x2 } -> x0 + v132 Imm(10) -> x3 + v133 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v132) block 20 start_pc=0 - v140 Phi { incoming=[b39:v123, b19:v138], kind=I64 } -> x3 - v141 Imm(4609434218613702656) -> x0 - v142 FpCast { kind=F64ToF32, value=v141 } -> d0 [f32] - v143 Imm(0) -> x1 - v144 FpCast { kind=F32ToF64, value=v142 } -> d0 - v145 Binop { op=fne, lhs=v144, rhs=v141 } -> x0 - terminator Bz { cond=v145, target=b40, fall=b21 } (exit_acc=v145) + v134 Phi { incoming=[b39:v118, b19:v132], kind=I64 } -> x3 + v135 Imm(1069547520) -> x0 [f32] + v136 Imm(0) -> x1 + v137 Binop { op=fne, lhs=v135, rhs=v135 } -> x0 + terminator Bz { cond=v137, target=b40, fall=b21 } (exit_acc=v137) block 21 start_pc=0 - v146 ImmData(292) -> x7 - v147 CallExt { binding_idx=0, args=[v146], fp_arg_mask=0x0 } -> x0 - v148 Imm(11) -> x3 - v149 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v148) + v138 ImmData(292) -> x7 + v139 CallExt { binding_idx=0, args=[v138], fp_arg_mask=0x0 } -> x0 + v140 Imm(11) -> x3 + v141 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v140) block 22 start_pc=0 - v150 Phi { incoming=[b40:v140, b21:v148], kind=I64 } -> x3 - v151 Imm(4612811918334230528) -> x0 - v152 FpCast { kind=F64ToF32, value=v151 } -> d0 [f32] - v153 Imm(0) -> x1 - v154 FpCast { kind=F32ToF64, value=v152 } -> d0 - v155 Binop { op=fne, lhs=v154, rhs=v151 } -> x0 - terminator Bz { cond=v155, target=b41, fall=b23 } (exit_acc=v155) + v142 Phi { incoming=[b40:v134, b21:v140], kind=I64 } -> x3 + v143 Imm(1075838976) -> x0 [f32] + v144 Imm(0) -> x1 + v145 Binop { op=fne, lhs=v143, rhs=v143 } -> x0 + terminator Bz { cond=v145, target=b41, fall=b23 } (exit_acc=v145) block 23 start_pc=0 - v156 ImmData(315) -> x7 - v157 CallExt { binding_idx=0, args=[v156], fp_arg_mask=0x0 } -> x0 - v158 Imm(12) -> x3 - v159 Imm(0) -> x0 - terminator Jmp(b24) (exit_acc=v158) + v146 ImmData(315) -> x7 + v147 CallExt { binding_idx=0, args=[v146], fp_arg_mask=0x0 } -> x0 + v148 Imm(12) -> x3 + v149 Imm(0) -> x0 + terminator Jmp(b24) (exit_acc=v148) block 24 start_pc=0 - v160 Phi { incoming=[b41:v150, b23:v158], kind=I64 } -> x3 - v161 Imm(4609434218613702656) -> x0 - v162 FpCast { kind=F64ToF32, value=v161 } -> d0 [f32] - v163 Imm(0) -> x0 - v164 Imm(4612811918334230528) -> x0 - v165 FpCast { kind=F64ToF32, value=v164 } -> d1 [f32] - v166 Imm(0) -> x0 - v167 Binop { op=feq, lhs=v162, rhs=v165 } -> x0 - terminator Bz { cond=v167, target=b42, fall=b25 } (exit_acc=v167) + v150 Phi { incoming=[b41:v142, b23:v148], kind=I64 } -> x3 + v151 Imm(1069547520) -> x0 [f32] + v152 Imm(0) -> x1 + v153 Imm(1075838976) -> x1 [f32] + v154 Imm(0) -> x2 + v155 Binop { op=feq, lhs=v151, rhs=v153 } -> x0 + terminator Bz { cond=v155, target=b42, fall=b25 } (exit_acc=v155) block 25 start_pc=0 - v168 ImmData(338) -> x7 - v169 CallExt { binding_idx=0, args=[v168], fp_arg_mask=0x0 } -> x0 - v170 Imm(13) -> x3 - v171 Imm(0) -> x0 - terminator Jmp(b26) (exit_acc=v170) + v156 ImmData(338) -> x7 + v157 CallExt { binding_idx=0, args=[v156], fp_arg_mask=0x0 } -> x0 + v158 Imm(13) -> x3 + v159 Imm(0) -> x0 + terminator Jmp(b26) (exit_acc=v158) block 26 start_pc=0 - v172 Phi { incoming=[b42:v160, b25:v170], kind=I64 } -> x3 - v173 Imm(4607182418800017408) -> x0 - v174 FpCast { kind=F64ToF32, value=v173 } -> d0 [f32] - v175 Imm(4611686018427387904) -> x0 - v176 FpCast { kind=F64ToF32, value=v175 } -> d1 [f32] - v177 Imm(4615063718147915776) -> x0 - v178 FpCast { kind=F64ToF32, value=v177 } -> d2 [f32] - v179 Imm(0) -> x0 - v180 Imm(0) -> x0 - v181 Imm(0) -> x0 - v182 Binop { op=fadd, lhs=v174, rhs=v176 } -> d0 [f32] - v183 Binop { op=fadd, lhs=v182, rhs=v178 } -> d0 [f32] - v184 Imm(4619004367821864960) -> x0 - v185 FpCast { kind=F32ToF64, value=v183 } -> d0 - v186 Binop { op=fne, lhs=v185, rhs=v184 } -> x0 - terminator Bz { cond=v186, target=b43, fall=b27 } (exit_acc=v186) + v160 Phi { incoming=[b42:v150, b25:v158], kind=I64 } -> x3 + v161 Imm(1065353216) -> x0 [f32] + v162 Imm(1073741824) -> x1 [f32] + v163 Imm(1080033280) -> x2 [f32] + v164 Imm(0) -> x6 + v165 Imm(0) -> x6 + v166 Imm(0) -> x6 + v167 Binop { op=fadd, lhs=v161, rhs=v162 } -> d0 [f32] + v168 Binop { op=fadd, lhs=v167, rhs=v163 } -> d0 [f32] + v169 Imm(1087373312) -> x0 [f32] + v170 Binop { op=fne, lhs=v168, rhs=v169 } -> x0 + terminator Bz { cond=v170, target=b43, fall=b27 } (exit_acc=v170) block 27 start_pc=0 - v187 ImmData(380) -> x7 - v188 Imm(4607182418800017408) -> x0 - v189 FpCast { kind=F64ToF32, value=v188 } -> d0 [f32] - v190 Imm(4611686018427387904) -> x0 - v191 FpCast { kind=F64ToF32, value=v190 } -> d1 [f32] - v192 Imm(4615063718147915776) -> x0 - v193 FpCast { kind=F64ToF32, value=v192 } -> d2 [f32] - v194 Imm(0) -> x0 - v195 Imm(0) -> x0 - v196 Imm(0) -> x0 - v197 Binop { op=fadd, lhs=v189, rhs=v191 } -> d0 [f32] - v198 Binop { op=fadd, lhs=v197, rhs=v193 } -> d0 [f32] - v199 FpCast { kind=F32ToF64, value=v198 } -> d0 - v200 CallExt { binding_idx=0, args=[v187, v199], fp_arg_mask=0x2 } -> x0 - v201 Imm(14) -> x3 - v202 Imm(0) -> x0 - terminator Jmp(b28) (exit_acc=v201) + v171 ImmData(380) -> x7 + v172 Imm(1065353216) -> x0 [f32] + v173 Imm(1073741824) -> x1 [f32] + v174 Imm(1080033280) -> x2 [f32] + v175 Imm(0) -> x6 + v176 Imm(0) -> x6 + v177 Imm(0) -> x6 + v178 Binop { op=fadd, lhs=v172, rhs=v173 } -> d0 [f32] + v179 Binop { op=fadd, lhs=v178, rhs=v174 } -> d0 [f32] + v180 FpCast { kind=F32ToF64, value=v179 } -> d0 + v181 CallExt { binding_idx=0, args=[v171, v180], fp_arg_mask=0x2 } -> x0 + v182 Imm(14) -> x3 + v183 Imm(0) -> x0 + terminator Jmp(b28) (exit_acc=v182) block 28 start_pc=0 - v203 Phi { incoming=[b43:v172, b27:v201], kind=I64 } -> x3 - v204 Imm(4609434218613702656) -> x0 - v205 FpCast { kind=F64ToF32, value=v204 } -> d0 [f32] - v206 Imm(0) -> x0 - v207 Imm(4611686018427387904) -> x0 - v208 FpCast { kind=F64ToF32, value=v207 } -> d1 [f32] - v209 Imm(0) -> x0 - v210 LoadLocal { off=-6, kind=F32 } -> d2 [f32] - v211 LoadLocal { off=-7, kind=F32 } -> d2 [f32] - v212 Binop { op=fmul, lhs=v205, rhs=v208 } -> d0 [f32] - v213 Imm(4598175219545276416) -> x0 - v214 FpCast { kind=F32ToF64, value=v212 } -> d0 - v215 Binop { op=fadd, lhs=v214, rhs=v213 } -> d0 - v216 FpCast { kind=F64ToF32, value=v215 } -> d0 [f32] - v217 Imm(0) -> x0 - v218 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v219 Imm(4614500768194494464) -> x0 - v220 FpCast { kind=F32ToF64, value=v216 } -> d1 - v221 Binop { op=fne, lhs=v220, rhs=v219 } -> x0 - terminator Bz { cond=v221, target=b44, fall=b29 } (exit_acc=v221) + v184 Phi { incoming=[b43:v160, b27:v182], kind=I64 } -> x3 + v185 Imm(1069547520) -> x0 [f32] + v186 StoreLocal { off=-6, value=v185, kind=F32 } -> - + v187 Imm(1073741824) -> x0 [f32] + v188 StoreLocal { off=-7, value=v187, kind=F32 } -> - + v189 LoadLocal { off=-6, kind=F32 } -> d0 [f32] + v190 LoadLocal { off=-7, kind=F32 } -> d1 [f32] + v191 Binop { op=fmul, lhs=v189, rhs=v190 } -> d2 [f32] + v192 Imm(1048576000) -> x0 [f32] + v193 Fma { a=v189, b=v190, c=v192, neg_product=false, neg_addend=false } -> d0 [f32] + v194 Imm(0) -> x0 + v195 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v196 Imm(1078984704) -> x0 [f32] + v197 Binop { op=fne, lhs=v193, rhs=v196 } -> x0 + terminator Bz { cond=v197, target=b44, fall=b29 } (exit_acc=v197) block 29 start_pc=0 - v222 ImmData(396) -> x7 - v223 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v224 FpCast { kind=F32ToF64, value=v216 } -> d0 - v225 CallExt { binding_idx=0, args=[v222, v224], fp_arg_mask=0x2 } -> x0 - v226 Imm(15) -> x3 - v227 Imm(0) -> x0 - terminator Jmp(b30) (exit_acc=v226) + v198 ImmData(396) -> x7 + v199 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v200 FpCast { kind=F32ToF64, value=v193 } -> d0 + v201 CallExt { binding_idx=0, args=[v198, v200], fp_arg_mask=0x2 } -> x0 + v202 Imm(15) -> x3 + v203 Imm(0) -> x0 + terminator Jmp(b30) (exit_acc=v202) block 30 start_pc=0 - v228 Phi { incoming=[b44:v203, b29:v226], kind=I64 } -> x3 - v229 Imm(4607182418800017408) -> x0 - v230 FpCast { kind=F64ToF32, value=v229 } -> d0 [f32] - v231 StoreLocal { off=-9, value=v230, kind=F32 } -> - - v232 LocalAddr(-10) -> x7 - v233 LocalAddr(-9) -> x6 - v234 Imm(4) -> x2 - v235 CallExt { binding_idx=56, args=[v232, v233, v234], fp_arg_mask=0x0 } -> x0 - v236 LoadLocal { off=-10, kind=U32 } -> x0 - v237 BinopI { op=xor, lhs=v236, rhs_imm=1065353216 } -> x0 - v238 BinopI { op=and, lhs=v237, rhs_imm=4294967295 } -> x0 - v239 BinopI { op=ne, lhs=v238, rhs_imm=0 } -> x0 - terminator Bz { cond=v239, target=b45, fall=b31 } (exit_acc=v239) + v204 Phi { incoming=[b44:v184, b29:v202], kind=I64 } -> x3 + v205 Imm(1065353216) -> x0 [f32] + v206 StoreLocal { off=-9, value=v205, kind=F32 } -> - + v207 LocalAddr(-10) -> x7 + v208 LocalAddr(-9) -> x6 + v209 Imm(4) -> x2 + v210 CallExt { binding_idx=56, args=[v207, v208, v209], fp_arg_mask=0x0 } -> x0 + v211 LoadLocal { off=-10, kind=U32 } -> x0 + v212 BinopI { op=xor, lhs=v211, rhs_imm=1065353216 } -> x0 + v213 BinopI { op=and, lhs=v212, rhs_imm=4294967295 } -> x0 + v214 BinopI { op=ne, lhs=v213, rhs_imm=0 } -> x0 + terminator Bz { cond=v214, target=b45, fall=b31 } (exit_acc=v214) block 31 start_pc=0 - v240 ImmData(417) -> x7 - v241 LoadLocal { off=-10, kind=U32 } -> x6 - v242 CallExt { binding_idx=0, args=[v240, v241], fp_arg_mask=0x0 } -> x0 - v243 Imm(16) -> x3 - v244 Imm(0) -> x0 - terminator Jmp(b32) (exit_acc=v243) + v215 ImmData(417) -> x7 + v216 LoadLocal { off=-10, kind=U32 } -> x6 + v217 CallExt { binding_idx=0, args=[v215, v216], fp_arg_mask=0x0 } -> x0 + v218 Imm(16) -> x3 + v219 Imm(0) -> x0 + terminator Jmp(b32) (exit_acc=v218) block 32 start_pc=0 - v245 Phi { incoming=[b45:v228, b31:v243], kind=I64 } -> x3 - v246 Extend { value=v245, kind=I32 } -> x0 - terminator Return(v246) (exit_acc=v246) + v220 Phi { incoming=[b45:v204, b31:v218], kind=I64 } -> x3 + v221 Extend { value=v220, kind=I32 } -> x0 + terminator Return(v221) (exit_acc=v221) block 33 start_pc=0 terminator Jmp(b8) block 34 start_pc=0 diff --git a/tests/snapshots/ssa/float_literal_arith_single_precision.ssa b/tests/snapshots/ssa/float_literal_arith_single_precision.ssa new file mode 100644 index 000000000..1a55bed55 --- /dev/null +++ b/tests/snapshots/ssa/float_literal_arith_single_precision.ssa @@ -0,0 +1,150 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=step +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=F32) -> d0 [f32] + v2 Imm(0) -> x0 + v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v4 Imm(1065353216) -> x0 [f32] + v5 Binop { op=fsub, lhs=v1, rhs=v4 } -> d0 [f32] + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=blend +fn ent_pc=1 n_params=2 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=F32) -> d0 [f32] + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=F32) -> d1 [f32] + v4 Imm(0) -> x0 + v5 LoadLocal { off=-1, kind=F32 } -> d2 [f32] + v6 Imm(1056964608) -> x0 [f32] + v7 Binop { op=fmul, lhs=v1, rhs=v6 } -> d2 [f32] + v8 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v9 Imm(1048576000) -> x1 [f32] + v10 Binop { op=fmul, lhs=v3, rhs=v9 } -> d1 [f32] + v11 Fma { a=v1, b=v6, c=v10, neg_product=false, neg_addend=false } -> d0 [f32] + terminator Return(v11) (exit_acc=v11) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1075838976) -> x0 [f32] + v2 Imm(0) -> x1 + v3 Imm(1065353216) -> x1 [f32] + v4 Binop { op=fsub, lhs=v1, rhs=v3 } -> d0 [f32] + v5 Imm(1069547520) -> x0 [f32] + v6 Binop { op=fne, lhs=v4, rhs=v5 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) + block 2 start_pc=0 + v8 Imm(1077936128) -> x0 [f32] + v9 Imm(1090519040) -> x1 [f32] + v10 Imm(0) -> x2 + v11 Imm(0) -> x2 + v12 Imm(1056964608) -> x2 [f32] + v13 Binop { op=fmul, lhs=v8, rhs=v12 } -> d0 [f32] + v14 Imm(1048576000) -> x6 [f32] + v15 Binop { op=fmul, lhs=v9, rhs=v14 } -> d0 [f32] + v16 Fma { a=v8, b=v12, c=v15, neg_product=false, neg_addend=false } -> d0 [f32] + v17 Imm(1080033280) -> x0 [f32] + v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) + block 3 start_pc=0 + v19 Imm(2) -> x0 + terminator Return(v19) (exit_acc=v19) + block 4 start_pc=0 + v20 Imm(0) -> x0 [f32] + v21 StoreLocal { off=-1, value=v20, kind=F32 } -> - + v22 Imm(0) -> x1 + v23 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v22) + block 5 start_pc=0 + v24 Phi { incoming=[b4:v22, b6:v28], kind=I64 } -> x1 + v25 Extend { value=v24, kind=I32 } -> x0 + v26 BinopI { op=lt, lhs=v25, rhs_imm=10 } -> x0 + terminator Bz { cond=v26, target=b8, fall=b7 } (exit_acc=v26) + block 6 start_pc=0 + v27 Extend { value=v24, kind=I32 } -> x0 + v28 BinopI { op=add, lhs=v27, rhs_imm=1 } -> x1 + v29 Imm(0) -> x0 + terminator Jmp(b5) (exit_acc=v28) + block 7 start_pc=0 + v30 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v31 Imm(1036831949) -> x0 [f32] + v32 Binop { op=fadd, lhs=v30, rhs=v31 } -> d0 [f32] + v33 StoreLocal { off=-1, value=v32, kind=F32 } -> - + terminator Jmp(b6) (exit_acc=v33) + block 8 start_pc=0 + v34 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v35 Imm(1065353216) -> x0 [f32] + v36 Binop { op=feq, lhs=v34, rhs=v35 } -> x0 + terminator Bz { cond=v36, target=b10, fall=b9 } (exit_acc=v36) + block 9 start_pc=0 + v37 Imm(3) -> x0 + terminator Return(v37) (exit_acc=v37) + block 10 start_pc=0 + v38 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v39 Imm(1065353217) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) + block 11 start_pc=0 + v41 Imm(4) -> x0 + terminator Return(v41) (exit_acc=v41) + block 12 start_pc=0 + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_literal_f_suffix.ssa b/tests/snapshots/ssa/float_literal_f_suffix.ssa new file mode 100644 index 000000000..0dd4376c7 --- /dev/null +++ b/tests/snapshots/ssa/float_literal_f_suffix.ssa @@ -0,0 +1,219 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=vsum +fn ent_pc=0 n_params=1 variadic=true locals=5 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-3) -> x0 + v2 LocalAddr(2) -> x1 + v3 Intrinsic { kind=4, args=[v1, v2] } -> x0 + v4 Imm(0) -> x1 + v5 FpCast { kind=IntToFp, value=v4 } -> d0 + v6 Imm(0) -> x0 + v7 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v4) + block 1 start_pc=0 + v8 Phi { incoming=[b0:v4, b2:v14], kind=I64 } -> x1 + v9 Phi { incoming=[b0:v5, b2:v21], kind=F64 } -> d0 + v10 Extend { value=v8, kind=I32 } -> x0 + v11 LoadLocal { off=2, kind=I32 } -> x2 + v12 Binop { op=lt, lhs=v10, rhs=v11 } -> x0 + terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + block 2 start_pc=0 + v13 Extend { value=v8, kind=I32 } -> x0 + v14 BinopI { op=add, lhs=v13, rhs_imm=1 } -> x1 + v15 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v14) + block 3 start_pc=0 + v16 LoadLocal { off=-4, kind=F64 } -> d1 + v17 LocalAddr(-3) -> x0 + v18 Imm(65544) -> x2 + v19 Intrinsic { kind=5, args=[v17, v18] } -> x0 + v20 Load { addr=v19, disp=0, kind=F64 } -> d1 + v21 Binop { op=fadd, lhs=v9, rhs=v20 } -> d0 + v22 Imm(0) -> x0 + v23 LoadLocal { off=-4, kind=F64 } -> d1 + terminator Jmp(b2) (exit_acc=v21) + block 4 start_pc=0 + v24 LocalAddr(-3) -> x0 + v25 Intrinsic { kind=6, args=[v24] } -> x0 + v26 LoadLocal { off=-4, kind=F64 } -> d1 + terminator Return(v9) (exit_acc=v9) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v1) + block 1 start_pc=0 + v2 Imm(1) -> x0 + terminator Return(v2) (exit_acc=v2) + block 2 start_pc=0 + v3 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v3) + block 3 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 4 start_pc=0 + v5 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v5) + block 5 start_pc=0 + v6 Imm(3) -> x0 + terminator Return(v6) (exit_acc=v6) + block 6 start_pc=0 + v7 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v7) + block 7 start_pc=0 + v8 Imm(4) -> x0 + terminator Return(v8) (exit_acc=v8) + block 8 start_pc=0 + v9 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v9) + block 9 start_pc=0 + v10 Imm(5) -> x0 + terminator Return(v10) (exit_acc=v10) + block 10 start_pc=0 + v11 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v11) + block 11 start_pc=0 + v12 Imm(6) -> x0 + terminator Return(v12) (exit_acc=v12) + block 12 start_pc=0 + v13 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v13) + block 13 start_pc=0 + v14 Imm(7) -> x0 + terminator Return(v14) (exit_acc=v14) + block 14 start_pc=0 + v15 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v15) + block 15 start_pc=0 + v16 Imm(8) -> x0 + terminator Return(v16) (exit_acc=v16) + block 16 start_pc=0 + v17 Imm(1266679808) -> x0 [f32] + v18 Binop { op=fne, lhs=v17, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b18, fall=b17 } (exit_acc=v18) + block 17 start_pc=0 + v19 Imm(9) -> x0 + terminator Return(v19) (exit_acc=v19) + block 18 start_pc=0 + v20 Imm(4715268810125344768) -> x0 + v21 Imm(4715268809856909312) -> x1 + v22 Binop { op=feq, lhs=v20, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b20, fall=b19 } (exit_acc=v22) + block 19 start_pc=0 + v23 Imm(10) -> x0 + terminator Return(v23) (exit_acc=v23) + block 20 start_pc=0 + v24 Imm(1036831949) -> x0 [f32] + v25 Imm(4591870180066957722) -> x1 + v26 FpCast { kind=F32ToF64, value=v24 } -> d0 + v27 Binop { op=feq, lhs=v26, rhs=v25 } -> x0 + terminator Bz { cond=v27, target=b22, fall=b21 } (exit_acc=v27) + block 21 start_pc=0 + v28 Imm(11) -> x0 + terminator Return(v28) (exit_acc=v28) + block 22 start_pc=0 + v29 Imm(1036831949) -> x0 [f32] + v30 Imm(4591870180174331904) -> x1 + v31 FpCast { kind=F32ToF64, value=v29 } -> d0 + v32 Binop { op=fne, lhs=v31, rhs=v30 } -> x0 + terminator Bz { cond=v32, target=b24, fall=b23 } (exit_acc=v32) + block 23 start_pc=0 + v33 Imm(12) -> x0 + terminator Return(v33) (exit_acc=v33) + block 24 start_pc=0 + v34 Imm(1036831949) -> x0 [f32] + v35 Fneg(v34) -> d0 [f32] + v36 Imm(4591870180174331904) -> x0 + v37 Fneg(v36) -> d1 + v38 FpCast { kind=F32ToF64, value=v35 } -> d0 + v39 Binop { op=fne, lhs=v38, rhs=v37 } -> x0 + terminator Bz { cond=v39, target=b26, fall=b25 } (exit_acc=v39) + block 25 start_pc=0 + v40 Imm(13) -> x0 + terminator Return(v40) (exit_acc=v40) + block 26 start_pc=0 + v41 Imm(2) -> x7 + v42 Imm(1069547520) -> x0 [f32] + v43 FpCast { kind=F32ToF64, value=v42 } -> d0 + v44 Imm(1048576000) -> x0 [f32] + v45 FpCast { kind=F32ToF64, value=v44 } -> d1 + v46 Call { target_pc=0, args=[v41, v43, v45], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 + v47 Imm(4610560118520545280) -> x0 + v48 Binop { op=fne, lhs=v46, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b28, fall=b27 } (exit_acc=v48) + block 27 start_pc=0 + v49 Imm(14) -> x0 + terminator Return(v49) (exit_acc=v49) + block 28 start_pc=0 + v50 Imm(1) -> x7 + v51 Imm(1036831949) -> x0 [f32] + v52 FpCast { kind=F32ToF64, value=v51 } -> d0 + v53 Call { target_pc=0, args=[v50, v52], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v54 Imm(4591870180174331904) -> x0 + v55 Binop { op=fne, lhs=v53, rhs=v54 } -> x0 + terminator Bz { cond=v55, target=b30, fall=b29 } (exit_acc=v55) + block 29 start_pc=0 + v56 Imm(16) -> x0 + terminator Return(v56) (exit_acc=v56) + block 30 start_pc=0 + v57 Imm(1266679809) -> x0 [f32] + v58 Binop { op=fne, lhs=v57, rhs=v57 } -> x0 + terminator Bz { cond=v58, target=b32, fall=b31 } (exit_acc=v58) + block 31 start_pc=0 + v59 Imm(15) -> x0 + terminator Return(v59) (exit_acc=v59) + block 32 start_pc=0 + v60 Imm(0) -> x0 + terminator Return(v60) (exit_acc=v60) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_literal_variadic_printf.ssa b/tests/snapshots/ssa/float_literal_variadic_printf.ssa new file mode 100644 index 000000000..7483cabab --- /dev/null +++ b/tests/snapshots/ssa/float_literal_variadic_printf.ssa @@ -0,0 +1,72 @@ +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=13 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-8) -> x7 + v2 Imm(64) -> x6 + v3 ImmData(36) -> x2 + v4 Imm(1069547520) -> x0 [f32] + v5 FpCast { kind=F32ToF64, value=v4 } -> d0 + v6 Imm(1036831949) -> x0 [f32] + v7 FpCast { kind=F32ToF64, value=v6 } -> d1 + v8 CallExt { binding_idx=3, args=[v1, v2, v3, v5, v7], fp_arg_mask=0x18 } -> x0 + v9 LocalAddr(-8) -> x7 + v10 ImmData(46) -> x6 + v11 CallExt { binding_idx=62, args=[v9, v10], fp_arg_mask=0x0 } -> x0 + v12 BinopI { op=ne, lhs=v11, rhs_imm=0 } -> x0 + terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + block 1 start_pc=0 + v13 Imm(1) -> x0 + terminator Return(v13) (exit_acc=v13) + block 2 start_pc=0 + v14 Imm(0) -> x0 + terminator Return(v14) (exit_acc=v14) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/float_long_double_suffix.ssa b/tests/snapshots/ssa/float_long_double_suffix.ssa index d873f207a..8fb70e899 100644 --- a/tests/snapshots/ssa/float_long_double_suffix.ssa +++ b/tests/snapshots/ssa/float_long_double_suffix.ssa @@ -4,63 +4,65 @@ fn ent_pc=0 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x0 - v2 StoreLocal { off=-1, value=v1, kind=F64 } -> - - v3 StoreLocal { off=-2, value=v1, kind=F64 } -> - - v4 StoreLocal { off=-3, value=v1, kind=F64 } -> - - v5 StoreLocal { off=-4, value=v1, kind=F64 } -> - - v6 LoadLocal { off=-1, kind=F64 } -> d0 - v7 LoadLocal { off=-2, kind=F64 } -> d1 - v8 Binop { op=fne, lhs=v6, rhs=v7 } -> x0 - terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + v1 Imm(1065353216) -> x0 [f32] + v2 FpCast { kind=F32ToF64, value=v1 } -> d0 + v3 Imm(0) -> x0 + v4 Imm(0) -> x0 + v5 Imm(4607182418800017408) -> x0 + v6 StoreLocal { off=-3, value=v5, kind=F64 } -> - + v7 StoreLocal { off=-4, value=v5, kind=F64 } -> - + v8 LoadLocal { off=-1, kind=F64 } -> d1 + v9 LoadLocal { off=-2, kind=F64 } -> d1 + v10 Binop { op=fne, lhs=v2, rhs=v2 } -> x0 + terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) block 1 start_pc=0 - v9 Imm(11) -> x0 - terminator Return(v9) (exit_acc=v9) + v11 Imm(11) -> x0 + terminator Return(v11) (exit_acc=v11) block 2 start_pc=0 - v10 LoadLocal { off=-1, kind=F64 } -> d0 - v11 LoadLocal { off=-3, kind=F64 } -> d1 - v12 Binop { op=fne, lhs=v10, rhs=v11 } -> x0 - terminator Bz { cond=v12, target=b4, fall=b3 } (exit_acc=v12) + v12 LoadLocal { off=-1, kind=F64 } -> d1 + v13 LoadLocal { off=-3, kind=F64 } -> d1 + v14 Binop { op=fne, lhs=v2, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v13 Imm(12) -> x0 - terminator Return(v13) (exit_acc=v13) + v15 Imm(12) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v14 LoadLocal { off=-1, kind=F64 } -> d0 - v15 LoadLocal { off=-4, kind=F64 } -> d1 - v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x0 - terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) + v16 LoadLocal { off=-1, kind=F64 } -> d1 + v17 LoadLocal { off=-4, kind=F64 } -> d1 + v18 Binop { op=fne, lhs=v2, rhs=v17 } -> x0 + terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) block 5 start_pc=0 - v17 Imm(13) -> x0 - terminator Return(v17) (exit_acc=v17) + v19 Imm(13) -> x0 + terminator Return(v19) (exit_acc=v19) block 6 start_pc=0 - v18 LoadLocal { off=-1, kind=F64 } -> d0 - v19 Imm(4607182418800017408) -> x0 - v20 Binop { op=fne, lhs=v18, rhs=v19 } -> x0 - terminator Bz { cond=v20, target=b8, fall=b7 } (exit_acc=v20) + v20 LoadLocal { off=-1, kind=F64 } -> d1 + v21 Imm(4607182418800017408) -> x0 + v22 Binop { op=fne, lhs=v2, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b8, fall=b7 } (exit_acc=v22) block 7 start_pc=0 - v21 Imm(14) -> x0 - terminator Return(v21) (exit_acc=v21) + v23 Imm(14) -> x0 + terminator Return(v23) (exit_acc=v23) block 8 start_pc=0 - v22 Imm(4759161926875873280) -> x0 - v23 StoreLocal { off=-5, value=v22, kind=F64 } -> - - v24 LoadLocal { off=-5, kind=F64 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v22 } -> x0 - terminator Bz { cond=v25, target=b10, fall=b9 } (exit_acc=v25) + v24 Imm(4759161926875873280) -> x0 + v25 StoreLocal { off=-5, value=v24, kind=F64 } -> - + v26 LoadLocal { off=-5, kind=F64 } -> d0 + v27 Binop { op=fne, lhs=v26, rhs=v24 } -> x0 + terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) block 9 start_pc=0 - v26 Imm(15) -> x0 - terminator Return(v26) (exit_acc=v26) + v28 Imm(15) -> x0 + terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v27 Imm(7) -> x0 - v28 Imm(0) -> x1 - v29 LoadLocal { off=-6, kind=I64 } -> x1 - v30 BinopI { op=ne, lhs=v27, rhs_imm=7 } -> x0 - terminator Bz { cond=v30, target=b12, fall=b11 } (exit_acc=v30) + v29 Imm(7) -> x0 + v30 Imm(0) -> x1 + v31 LoadLocal { off=-6, kind=I64 } -> x1 + v32 BinopI { op=ne, lhs=v29, rhs_imm=7 } -> x0 + terminator Bz { cond=v32, target=b12, fall=b11 } (exit_acc=v32) block 11 start_pc=0 - v31 Imm(16) -> x0 - terminator Return(v31) (exit_acc=v31) + v33 Imm(16) -> x0 + terminator Return(v33) (exit_acc=v33) block 12 start_pc=0 - v32 Imm(0) -> x0 - terminator Return(v32) (exit_acc=v32) + v34 Imm(0) -> x0 + terminator Return(v34) (exit_acc=v34) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_register_resident.ssa b/tests/snapshots/ssa/float_register_resident.ssa index 6da90bfc7..ef8119974 100644 --- a/tests/snapshots/ssa/float_register_resident.ssa +++ b/tests/snapshots/ssa/float_register_resident.ssa @@ -22,47 +22,43 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(0) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v2, b2:v28], kind=F32 } -> d0 [f32] - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=10 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v5 Phi { incoming=[b0:v3, b2:v9], kind=I64 } -> x1 + v6 Extend { value=v5, kind=I32 } -> x0 + v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) block 2 start_pc=0 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + v8 Extend { value=v5, kind=I32 } -> x0 + v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 3 start_pc=0 - v12 Extend { value=v5, kind=I32 } -> x0 - v13 FpCast { kind=IntToFp, value=v12 } -> d1 - v14 FpCast { kind=F64ToF32, value=v13 } -> d1 [f32] - v15 Imm(4602678819172646912) -> x0 - v16 FpCast { kind=F32ToF64, value=v14 } -> d1 - v17 Binop { op=fmul, lhs=v16, rhs=v15 } -> d1 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Imm(0) -> x0 - v20 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v21 Imm(4611686018427387904) -> x0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d2 [f32] - v23 LoadLocal { off=-1, kind=F32 } -> d3 [f32] - v24 Imm(0) -> x0 - v25 Imm(0) -> x0 - v26 Imm(0) -> x0 - v27 Binop { op=fmul, lhs=v18, rhs=v22 } -> d3 [f32] - v28 Fma { a=v18, b=v22, c=v6, neg_product=false, neg_addend=false } -> d0 [f32] - v29 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v28) + v11 Extend { value=v5, kind=I32 } -> x0 + v12 FpCast { kind=IntToFp, value=v11 } -> d0 + v13 FpCast { kind=F64ToF32, value=v12 } -> d0 [f32] + v14 Imm(1056964608) -> x0 [f32] + v15 Binop { op=fmul, lhs=v13, rhs=v14 } -> d0 [f32] + v16 Imm(0) -> x0 + v17 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v18 Imm(1073741824) -> x0 [f32] + v19 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v20 Imm(0) -> x2 + v21 Imm(0) -> x2 + v22 Imm(0) -> x2 + v23 Binop { op=fmul, lhs=v15, rhs=v18 } -> d2 [f32] + v24 Fma { a=v15, b=v18, c=v19, neg_product=false, neg_addend=false } -> d0 [f32] + v25 StoreLocal { off=-1, value=v24, kind=F32 } -> - + terminator Jmp(b2) (exit_acc=v25) block 4 start_pc=0 - v30 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v31 FpCast { kind=F32ToF64, value=v6 } -> d0 - v32 FpCast { kind=FpToInt, value=v31 } -> x0 - terminator Return(v32) (exit_acc=v32) + v26 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v27 FpCast { kind=F32ToF64, value=v26 } -> d0 + v28 FpCast { kind=FpToInt, value=v27 } -> x0 + terminator Return(v28) (exit_acc=v28) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_single_precision.ssa b/tests/snapshots/ssa/float_single_precision.ssa index 9b26597b2..16e0779b7 100644 --- a/tests/snapshots/ssa/float_single_precision.ssa +++ b/tests/snapshots/ssa/float_single_precision.ssa @@ -4,42 +4,39 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x0 - v2 Imm(4613937818241073152) -> x1 - v3 Binop { op=fdiv, lhs=v1, rhs=v2 } -> d0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 Imm(0) -> x0 - v6 Imm(4599676419595205767) -> x0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d1 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v10 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v11 Binop { op=fsub, lhs=v4, rhs=v7 } -> d1 [f32] + v1 Imm(1065353216) -> x0 [f32] + v2 Imm(1077936128) -> x1 [f32] + v3 Binop { op=fdiv, lhs=v1, rhs=v2 } -> d0 [f32] + v4 Imm(0) -> x0 + v5 Imm(1051372203) -> x0 [f32] + v6 StoreLocal { off=-2, value=v5, kind=F32 } -> - + v7 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v8 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v9 Binop { op=fsub, lhs=v3, rhs=v8 } -> d1 [f32] + v10 Imm(0) -> x0 + v11 LoadLocal { off=-3, kind=F32 } -> d0 [f32] v12 Imm(0) -> x0 - v13 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v14 Imm(0) -> x0 - v15 FpCast { kind=IntToFp, value=v14 } -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Binop { op=flt, lhs=v11, rhs=v16 } -> x0 - terminator Bz { cond=v17, target=b5, fall=b1 } (exit_acc=v17) + v13 FpCast { kind=IntToFp, value=v12 } -> d0 + v14 FpCast { kind=F64ToF32, value=v13 } -> d0 [f32] + v15 Binop { op=flt, lhs=v9, rhs=v14 } -> x0 + terminator Bz { cond=v15, target=b5, fall=b1 } (exit_acc=v15) block 1 start_pc=0 - v18 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v19 Fneg(v11) -> d1 [f32] - v20 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v19) + v16 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v17 Fneg(v9) -> d1 [f32] + v18 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v17) block 2 start_pc=0 - v21 Phi { incoming=[b5:v11, b1:v19], kind=F32 } -> d1 [f32] - v22 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v23 Imm(4502148214488346440) -> x0 - v24 FpCast { kind=F32ToF64, value=v21 } -> d0 - v25 Binop { op=fgt, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b4, fall=b3 } (exit_acc=v25) + v19 Phi { incoming=[b5:v9, b1:v17], kind=F32 } -> d1 [f32] + v20 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v21 Imm(869711765) -> x0 [f32] + v22 Binop { op=fgt, lhs=v19, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b4, fall=b3 } (exit_acc=v22) block 3 start_pc=0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v23 Imm(1) -> x0 + terminator Return(v23) (exit_acc=v23) block 4 start_pc=0 - v27 Imm(0) -> x0 - terminator Return(v27) (exit_acc=v27) + v24 Imm(0) -> x0 + terminator Return(v24) (exit_acc=v24) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -48,72 +45,66 @@ fn ent_pc=1 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(0) -> x1 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 + v1 Imm(0) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(0) -> x1 v4 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v1) + terminator Jmp(b1) (exit_acc=v3) block 1 start_pc=0 - v5 Phi { incoming=[b0:v1, b2:v10], kind=I64 } -> x1 - v6 Phi { incoming=[b0:v2, b2:v16], kind=F32 } -> d0 [f32] - v7 Extend { value=v5, kind=I32 } -> x0 - v8 BinopI { op=lt, lhs=v7, rhs_imm=10 } -> x0 - terminator Bz { cond=v8, target=b4, fall=b3 } (exit_acc=v8) + v5 Phi { incoming=[b0:v3, b2:v9], kind=I64 } -> x1 + v6 Extend { value=v5, kind=I32 } -> x0 + v7 BinopI { op=lt, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) block 2 start_pc=0 - v9 Extend { value=v5, kind=I32 } -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=1 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b1) (exit_acc=v10) + v8 Extend { value=v5, kind=I32 } -> x0 + v9 BinopI { op=add, lhs=v8, rhs_imm=1 } -> x1 + v10 Imm(0) -> x0 + terminator Jmp(b1) (exit_acc=v9) block 3 start_pc=0 - v12 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v13 Imm(4591870180066957722) -> x0 - v14 FpCast { kind=F32ToF64, value=v6 } -> d0 - v15 Binop { op=fadd, lhs=v14, rhs=v13 } -> d0 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Imm(0) -> x0 - v18 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - terminator Jmp(b2) (exit_acc=v16) + v11 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v12 Imm(1036831949) -> x0 [f32] + v13 Binop { op=fadd, lhs=v11, rhs=v12 } -> d0 [f32] + v14 StoreLocal { off=-1, value=v13, kind=F32 } -> - + v15 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + terminator Jmp(b2) (exit_acc=v15) block 4 start_pc=0 - v19 Imm(4607182419250377371) -> x0 - v20 FpCast { kind=F64ToF32, value=v19 } -> d1 [f32] + v16 Imm(1065353217) -> x0 [f32] + v17 StoreLocal { off=-3, value=v16, kind=F32 } -> - + v18 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v19 LoadLocal { off=-3, kind=F32 } -> d1 [f32] + v20 Binop { op=fsub, lhs=v18, rhs=v19 } -> d1 [f32] v21 Imm(0) -> x0 - v22 LoadLocal { off=-1, kind=F32 } -> d2 [f32] - v23 LoadLocal { off=-3, kind=F32 } -> d2 [f32] - v24 Binop { op=fsub, lhs=v6, rhs=v20 } -> d2 [f32] - v25 Imm(0) -> x0 - v26 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v27 Imm(0) -> x0 - v28 FpCast { kind=IntToFp, value=v27 } -> d1 - v29 FpCast { kind=F64ToF32, value=v28 } -> d1 [f32] - v30 Binop { op=flt, lhs=v24, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b11, fall=b5 } (exit_acc=v30) + v22 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v23 Imm(0) -> x0 + v24 FpCast { kind=IntToFp, value=v23 } -> d0 + v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] + v26 Binop { op=flt, lhs=v20, rhs=v25 } -> x0 + terminator Bz { cond=v26, target=b11, fall=b5 } (exit_acc=v26) block 5 start_pc=0 - v31 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v32 Fneg(v24) -> d2 [f32] - v33 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v32) + v27 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v28 Fneg(v20) -> d1 [f32] + v29 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v28) block 6 start_pc=0 - v34 Phi { incoming=[b11:v24, b5:v32], kind=F32 } -> d2 [f32] - v35 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v36 Imm(4517329193108106637) -> x0 - v37 FpCast { kind=F32ToF64, value=v34 } -> d1 - v38 Binop { op=fgt, lhs=v37, rhs=v36 } -> x0 - terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + v30 Phi { incoming=[b11:v20, b5:v28], kind=F32 } -> d1 [f32] + v31 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v32 Imm(897988541) -> x0 [f32] + v33 Binop { op=fgt, lhs=v30, rhs=v32 } -> x0 + terminator Bz { cond=v33, target=b8, fall=b7 } (exit_acc=v33) block 7 start_pc=0 - v39 Imm(2) -> x0 - terminator Return(v39) (exit_acc=v39) + v34 Imm(2) -> x0 + terminator Return(v34) (exit_acc=v34) block 8 start_pc=0 - v40 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v41 Imm(4607182418800017408) -> x0 - v42 FpCast { kind=F32ToF64, value=v6 } -> d0 - v43 Binop { op=feq, lhs=v42, rhs=v41 } -> x0 - terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) + v35 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v36 Imm(1065353216) -> x0 [f32] + v37 Binop { op=feq, lhs=v35, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b10, fall=b9 } (exit_acc=v37) block 9 start_pc=0 - v44 Imm(3) -> x0 - terminator Return(v44) (exit_acc=v44) + v38 Imm(3) -> x0 + terminator Return(v38) (exit_acc=v38) block 10 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) + v39 Imm(0) -> x0 + terminator Return(v39) (exit_acc=v39) block 11 start_pc=0 terminator Jmp(b6) ; --- SSA dump (ok=true) ent_pc=2 --- @@ -122,44 +113,40 @@ fn ent_pc=2 n_params=0 variadic=false locals=3 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607632778762754458) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x0 - v4 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v5 Binop { op=fmul, lhs=v2, rhs=v2 } -> d1 [f32] - v6 Binop { op=fmul, lhs=v5, rhs=v2 } -> d1 [f32] - v7 Binop { op=fmul, lhs=v6, rhs=v2 } -> d0 [f32] - v8 Imm(0) -> x0 - v9 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v10 Imm(4609272539837440018) -> x0 - v11 FpCast { kind=F32ToF64, value=v7 } -> d0 - v12 Binop { op=fsub, lhs=v11, rhs=v10 } -> d0 - v13 FpCast { kind=F64ToF32, value=v12 } -> d1 [f32] - v14 Imm(0) -> x0 - v15 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v16 Imm(0) -> x0 - v17 FpCast { kind=IntToFp, value=v16 } -> d0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Binop { op=flt, lhs=v13, rhs=v18 } -> x0 - terminator Bz { cond=v19, target=b5, fall=b1 } (exit_acc=v19) + v1 Imm(1066192077) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v4 Binop { op=fmul, lhs=v3, rhs=v3 } -> d1 [f32] + v5 Binop { op=fmul, lhs=v4, rhs=v3 } -> d1 [f32] + v6 Binop { op=fmul, lhs=v5, rhs=v3 } -> d2 [f32] + v7 Imm(0) -> x0 + v8 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v9 Imm(1069246370) -> x0 [f32] + v10 Fma { a=v5, b=v3, c=v9, neg_product=false, neg_addend=true } -> d1 [f32] + v11 Imm(0) -> x0 + v12 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v13 Imm(0) -> x0 + v14 FpCast { kind=IntToFp, value=v13 } -> d0 + v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] + v16 Binop { op=flt, lhs=v10, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b5, fall=b1 } (exit_acc=v16) block 1 start_pc=0 - v20 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v21 Fneg(v13) -> d1 [f32] - v22 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v21) + v17 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v18 Fneg(v10) -> d1 [f32] + v19 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v18) block 2 start_pc=0 - v23 Phi { incoming=[b5:v13, b1:v21], kind=F32 } -> d1 [f32] - v24 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v25 Imm(4532020583610935537) -> x0 - v26 FpCast { kind=F32ToF64, value=v23 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b4, fall=b3 } (exit_acc=v27) + v20 Phi { incoming=[b5:v10, b1:v18], kind=F32 } -> d1 [f32] + v21 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v22 Imm(925353388) -> x0 [f32] + v23 Binop { op=fgt, lhs=v20, rhs=v22 } -> x0 + terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) block 3 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) + v24 Imm(4) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v29 Imm(0) -> x0 - terminator Return(v29) (exit_acc=v29) + v25 Imm(0) -> x0 + terminator Return(v25) (exit_acc=v25) block 5 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=3 --- diff --git a/tests/snapshots/ssa/float_ternary_promote.ssa b/tests/snapshots/ssa/float_ternary_promote.ssa index 4d9fc570f..411d2d10b 100644 --- a/tests/snapshots/ssa/float_ternary_promote.ssa +++ b/tests/snapshots/ssa/float_ternary_promote.ssa @@ -33,121 +33,109 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(1) -> x7 - v2 Imm(4609434218613702656) -> x3 - v3 FpCast { kind=F64ToF32, value=v2 } -> d0 [f32] - v4 Imm(4612811918334230528) -> x0 - v5 Fneg(v4) -> d1 - v6 FpCast { kind=F64ToF32, value=v5 } -> d1 [f32] - v7 Call { target_pc=0, args=[v1, v3, v6], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v8 FpCast { kind=F32ToF64, value=v7 } -> d0 - v9 Binop { op=fne, lhs=v8, rhs=v2 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v2 Imm(1069547520) -> x3 [f32] + v3 Imm(1075838976) -> x0 [f32] + v4 Fneg(v3) -> d0 [f32] + v5 Call { target_pc=0, args=[v1, v2, v4], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v6 Binop { op=fne, lhs=v5, rhs=v2 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 2 start_pc=0 - v11 Imm(0) -> x7 - v12 Imm(4609434218613702656) -> x0 - v13 FpCast { kind=F64ToF32, value=v12 } -> d0 [f32] - v14 Imm(4612811918334230528) -> x0 - v15 Fneg(v14) -> [spill 0] - v16 FpCast { kind=F64ToF32, value=v15 } -> d1 [f32] - v17 Call { target_pc=0, args=[v11, v13, v16], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v18 FpCast { kind=F32ToF64, value=v17 } -> d0 - v19 Binop { op=fne, lhs=v18, rhs=v15 } -> x0 - terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) + v8 Imm(0) -> x7 + v9 Imm(1069547520) -> x6 [f32] + v10 Imm(1075838976) -> x0 [f32] + v11 Fneg(v10) -> [spill 0] [f32] + v12 Call { target_pc=0, args=[v8, v9, v11], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v13 Binop { op=fne, lhs=v12, rhs=v11 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v20 Imm(2) -> x0 - terminator Return(v20) (exit_acc=v20) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v21 Imm(4614500768194494464) -> x0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d2 [f32] - v23 Imm(0) -> x0 - v24 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v25 Imm(0) -> x0 - v26 FpCast { kind=F32ToF64, value=v22 } -> d0 - v27 Binop { op=fgt, lhs=v26, rhs=v25 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v15 Imm(1078984704) -> x0 [f32] + v16 StoreLocal { off=-1, value=v15, kind=F32 } -> - + v17 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v18 Imm(0) -> x0 [f32] + v19 Binop { op=fgt, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) block 5 start_pc=0 - v28 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v29 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v22) + v20 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v21 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v20) block 6 start_pc=0 - v30 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v31 Fneg(v22) -> d0 [f32] - v32 Imm(0) -> x0 - terminator Jmp(b7) (exit_acc=v31) + v22 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v23 Fneg(v22) -> d0 [f32] + v24 Imm(0) -> x0 + terminator Jmp(b7) (exit_acc=v23) block 7 start_pc=0 - v33 Phi { incoming=[b5:v22, b6:v31], kind=F32 } -> d0 [f32] - v34 LoadLocal { off=-5, kind=F32 } -> d1 [f32] - v35 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v36 Imm(0) -> x0 - v37 FpCast { kind=F32ToF64, value=v22 } -> d1 - v38 Binop { op=flt, lhs=v37, rhs=v36 } -> x0 - terminator Bz { cond=v38, target=b9, fall=b8 } (exit_acc=v38) + v25 Phi { incoming=[b5:v20, b6:v23], kind=F32 } -> d0 [f32] + v26 LoadLocal { off=-5, kind=F32 } -> d1 [f32] + v27 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v28 Imm(0) -> x0 [f32] + v29 Binop { op=flt, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b9, fall=b8 } (exit_acc=v29) block 8 start_pc=0 - v39 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v40 Fneg(v22) -> d2 [f32] - v41 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v40) + v30 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v31 Fneg(v30) -> d1 [f32] + v32 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v31) block 9 start_pc=0 - v42 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v43 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v22) + v33 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v34 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v33) block 10 start_pc=0 - v44 Phi { incoming=[b8:v40, b9:v22], kind=F32 } -> d2 [f32] - v45 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v46 Binop { op=fadd, lhs=v33, rhs=v44 } -> d0 [f32] - v47 Imm(0) -> x0 - v48 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v49 Imm(4619004367821864960) -> x0 - v50 FpCast { kind=F32ToF64, value=v46 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) + v35 Phi { incoming=[b8:v31, b9:v33], kind=F32 } -> d1 [f32] + v36 LoadLocal { off=-6, kind=F32 } -> d2 [f32] + v37 Binop { op=fadd, lhs=v25, rhs=v35 } -> d0 [f32] + v38 Imm(0) -> x0 + v39 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v40 Imm(1087373312) -> x0 [f32] + v41 Binop { op=fne, lhs=v37, rhs=v40 } -> x0 + terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) block 11 start_pc=0 - v52 Imm(3) -> x0 - terminator Return(v52) (exit_acc=v52) + v42 Imm(3) -> x0 + terminator Return(v42) (exit_acc=v42) block 12 start_pc=0 - v53 Imm(2) -> x0 - v54 Imm(0) -> x1 - v55 LoadLocal { off=-3, kind=I32 } -> x1 - v56 BinopI { op=eq, lhs=v53, rhs_imm=0 } -> x1 - terminator Bz { cond=v56, target=b14, fall=b13 } (exit_acc=v56) + v43 Imm(2) -> x0 + v44 Imm(0) -> x1 + v45 LoadLocal { off=-3, kind=I32 } -> x1 + v46 BinopI { op=eq, lhs=v43, rhs_imm=0 } -> x1 + terminator Bz { cond=v46, target=b14, fall=b13 } (exit_acc=v46) block 13 start_pc=0 - v57 Imm(0) -> x0 - v58 StoreLocal { off=-7, value=v57, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v58) + v47 Imm(0) -> x0 [f32] + v48 StoreLocal { off=-7, value=v47, kind=F32 } -> - + terminator Jmp(b15) (exit_acc=v48) block 14 start_pc=0 - v59 LoadLocal { off=-3, kind=I32 } -> x1 - v60 BinopI { op=eq, lhs=v53, rhs_imm=1 } -> x0 - terminator Bz { cond=v60, target=b17, fall=b16 } (exit_acc=v60) + v49 LoadLocal { off=-3, kind=I32 } -> x1 + v50 BinopI { op=eq, lhs=v43, rhs_imm=1 } -> x0 + terminator Bz { cond=v50, target=b17, fall=b16 } (exit_acc=v50) block 15 start_pc=0 - v61 LoadLocal { off=-7, kind=F64 } -> d0 - v62 FpCast { kind=F64ToF32, value=v61 } -> d0 [f32] - v63 Imm(0) -> x0 - v64 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v65 Imm(4626322717216342016) -> x0 - v66 FpCast { kind=F32ToF64, value=v62 } -> d0 - v67 Binop { op=fne, lhs=v66, rhs=v65 } -> x0 - terminator Bz { cond=v67, target=b20, fall=b19 } (exit_acc=v67) + v51 LoadLocal { off=-7, kind=F32 } -> d0 [f32] + v52 Imm(0) -> x0 + v53 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v54 Imm(1101004800) -> x0 [f32] + v55 Binop { op=fne, lhs=v51, rhs=v54 } -> x0 + terminator Bz { cond=v55, target=b20, fall=b19 } (exit_acc=v55) block 16 start_pc=0 - v68 Imm(4621819117588971520) -> x0 - v69 StoreLocal { off=-8, value=v68, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v69) + v56 Imm(1092616192) -> x0 [f32] + v57 StoreLocal { off=-8, value=v56, kind=F32 } -> - + terminator Jmp(b18) (exit_acc=v57) block 17 start_pc=0 - v70 Imm(4626322717216342016) -> x0 - v71 StoreLocal { off=-8, value=v70, kind=F64 } -> - - terminator Jmp(b18) (exit_acc=v71) + v58 Imm(1101004800) -> x0 [f32] + v59 StoreLocal { off=-8, value=v58, kind=F32 } -> - + terminator Jmp(b18) (exit_acc=v59) block 18 start_pc=0 - v72 LoadLocal { off=-8, kind=F64 } -> d0 - v73 StoreLocal { off=-7, value=v72, kind=F64 } -> - - terminator Jmp(b15) (exit_acc=v73) + v60 LoadLocal { off=-8, kind=F32 } -> d0 [f32] + v61 StoreLocal { off=-7, value=v60, kind=F32 } -> - + terminator Jmp(b15) (exit_acc=v61) block 19 start_pc=0 - v74 Imm(4) -> x0 - terminator Return(v74) (exit_acc=v74) + v62 Imm(4) -> x0 + terminator Return(v62) (exit_acc=v62) block 20 start_pc=0 - v75 Imm(0) -> x0 - terminator Return(v75) (exit_acc=v75) + v63 Imm(0) -> x0 + terminator Return(v63) (exit_acc=v63) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/float_variadic_promotion.ssa b/tests/snapshots/ssa/float_variadic_promotion.ssa index 38b4ff1ea..cba5d17bc 100644 --- a/tests/snapshots/ssa/float_variadic_promotion.ssa +++ b/tests/snapshots/ssa/float_variadic_promotion.ssa @@ -74,70 +74,69 @@ fn ent_pc=1 n_params=1 variadic=true locals=5 ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=7 - spill_count=2 gpr_used=[3] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4634564304534430024) -> x3 - v2 FpCast { kind=F64ToF32, value=v1 } -> [spill 0] [f32] - v3 Imm(0) -> x0 - v4 Imm(4609434218613702656) -> x0 - v5 FpCast { kind=F64ToF32, value=v4 } -> [spill 1] [f32] - v6 Imm(0) -> x0 - v7 Imm(1) -> x7 - v8 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v9 FpCast { kind=F32ToF64, value=v2 } -> d0 - v10 Call { target_pc=1, args=[v7, v9], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 - v11 Call { target_pc=0, args=[v10, v1], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v12 BinopI { op=eq, lhs=v11, rhs_imm=0 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v1 Imm(1116355953) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(1069547520) -> x0 [f32] + v4 StoreLocal { off=-2, value=v3, kind=F32 } -> - + v5 Imm(1) -> x7 + v6 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v7 FpCast { kind=F32ToF64, value=v6 } -> d0 + v8 Call { target_pc=1, args=[v5, v7], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v9 Imm(4634564304534430024) -> x7 + v10 Call { target_pc=0, args=[v8, v9], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v11 BinopI { op=eq, lhs=v10, rhs_imm=0 } -> x0 + terminator Bz { cond=v11, target=b2, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v12 Imm(1) -> x0 + terminator Return(v12) (exit_acc=v12) block 2 start_pc=0 - v14 Imm(1) -> x7 - v15 Imm(4612811918334230528) -> x3 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 FpCast { kind=F32ToF64, value=v16 } -> d0 - v18 Call { target_pc=1, args=[v14, v17], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 - v19 Call { target_pc=0, args=[v18, v15], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v20 BinopI { op=eq, lhs=v19, rhs_imm=0 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v13 Imm(1) -> x7 + v14 Imm(4612811918334230528) -> x3 + v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] + v16 FpCast { kind=F32ToF64, value=v15 } -> d0 + v17 Call { target_pc=1, args=[v13, v16], fixed_args=1, fp_return=true, fp_arg_mask=0x2 } -> d0 + v18 Call { target_pc=0, args=[v17, v14], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v19 BinopI { op=eq, lhs=v18, rhs_imm=0 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v21 Imm(2) -> x0 - terminator Return(v21) (exit_acc=v21) + v20 Imm(2) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v22 Imm(2) -> x7 - v23 LoadLocal { off=-1, kind=F32 } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v2 } -> d0 - v25 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v26 FpCast { kind=F32ToF64, value=v5 } -> d1 - v27 Call { target_pc=1, args=[v22, v24, v26], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 - v28 Imm(4634669857650696520) -> x7 - v29 Call { target_pc=0, args=[v27, v28], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v30 BinopI { op=eq, lhs=v29, rhs_imm=0 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + v21 Imm(2) -> x7 + v22 LoadLocal { off=-1, kind=F32 } -> d0 [f32] + v23 FpCast { kind=F32ToF64, value=v22 } -> d0 + v24 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v25 FpCast { kind=F32ToF64, value=v24 } -> d1 + v26 Call { target_pc=1, args=[v21, v23, v25], fixed_args=1, fp_return=true, fp_arg_mask=0x6 } -> d0 + v27 Imm(4634669857650696520) -> x7 + v28 Call { target_pc=0, args=[v26, v27], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v29 BinopI { op=eq, lhs=v28, rhs_imm=0 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v31 Imm(3) -> x0 - terminator Return(v31) (exit_acc=v31) + v30 Imm(3) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v32 Imm(3) -> x7 - v33 Imm(10) -> x0 - v34 FpCast { kind=IntToFp, value=v33 } -> d0 - v35 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v36 FpCast { kind=F32ToF64, value=v2 } -> d1 - v37 LoadLocal { off=-2, kind=F32 } -> d2 [f32] - v38 FpCast { kind=F32ToF64, value=v5 } -> d2 - v39 Call { target_pc=1, args=[v32, v34, v36, v38], fixed_args=1, fp_return=true, fp_arg_mask=0xe } -> d0 - v40 Imm(4635373545092473160) -> x7 - v41 Call { target_pc=0, args=[v39, v40], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v42 BinopI { op=eq, lhs=v41, rhs_imm=0 } -> x0 - terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) + v31 Imm(3) -> x7 + v32 Imm(10) -> x0 + v33 FpCast { kind=IntToFp, value=v32 } -> d0 + v34 LoadLocal { off=-1, kind=F32 } -> d1 [f32] + v35 FpCast { kind=F32ToF64, value=v34 } -> d1 + v36 LoadLocal { off=-2, kind=F32 } -> d2 [f32] + v37 FpCast { kind=F32ToF64, value=v36 } -> d2 + v38 Call { target_pc=1, args=[v31, v33, v35, v37], fixed_args=1, fp_return=true, fp_arg_mask=0xe } -> d0 + v39 Imm(4635373545092473160) -> x7 + v40 Call { target_pc=0, args=[v38, v39], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v41 BinopI { op=eq, lhs=v40, rhs_imm=0 } -> x0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) block 7 start_pc=0 - v43 Imm(4) -> x0 - terminator Return(v43) (exit_acc=v43) + v42 Imm(4) -> x0 + terminator Return(v42) (exit_acc=v42) block 8 start_pc=0 - v44 Imm(0) -> x0 - terminator Return(v44) (exit_acc=v44) + v43 Imm(0) -> x0 + terminator Return(v43) (exit_acc=v43) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fma_contraction.ssa b/tests/snapshots/ssa/fma_contraction.ssa index fd47422c1..57b4996d5 100644 --- a/tests/snapshots/ssa/fma_contraction.ssa +++ b/tests/snapshots/ssa/fma_contraction.ssa @@ -156,146 +156,126 @@ fn ent_pc=6 n_params=0 variadic=false locals=3 v32 Imm(3) -> x0 terminator Return(v32) (exit_acc=v32) block 6 start_pc=0 - v33 Imm(4611686018427387904) -> x0 - v34 FpCast { kind=F64ToF32, value=v33 } -> d0 [f32] - v35 Imm(4613937818241073152) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d1 [f32] - v37 Imm(4616189618054758400) -> x0 - v38 FpCast { kind=F64ToF32, value=v37 } -> d2 [f32] - v39 Imm(0) -> x0 - v40 Imm(0) -> x0 - v41 Imm(0) -> x0 - v42 Binop { op=fmul, lhs=v34, rhs=v36 } -> d3 [f32] - v43 Fma { a=v34, b=v36, c=v38, neg_product=false, neg_addend=false } -> d0 [f32] - v44 Imm(4621819117588971520) -> x0 - v45 FpCast { kind=F32ToF64, value=v43 } -> d0 - v46 Binop { op=fne, lhs=v45, rhs=v44 } -> x0 - terminator Bz { cond=v46, target=b8, fall=b7 } (exit_acc=v46) + v33 Imm(1073741824) -> x0 [f32] + v34 Imm(1077936128) -> x1 [f32] + v35 Imm(1082130432) -> x2 [f32] + v36 Imm(0) -> x6 + v37 Imm(0) -> x6 + v38 Imm(0) -> x6 + v39 Binop { op=fmul, lhs=v33, rhs=v34 } -> d0 [f32] + v40 Fma { a=v33, b=v34, c=v35, neg_product=false, neg_addend=false } -> d0 [f32] + v41 Imm(1092616192) -> x0 [f32] + v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 + terminator Bz { cond=v42, target=b8, fall=b7 } (exit_acc=v42) block 7 start_pc=0 - v47 Imm(4) -> x0 - terminator Return(v47) (exit_acc=v47) + v43 Imm(4) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v48 Imm(4611686018427387904) -> x0 - v49 FpCast { kind=F64ToF32, value=v48 } -> d0 [f32] - v50 Imm(4613937818241073152) -> x1 - v51 FpCast { kind=F64ToF32, value=v50 } -> d1 [f32] - v52 Imm(4616189618054758400) -> x1 - v53 FpCast { kind=F64ToF32, value=v52 } -> d2 [f32] - v54 Imm(0) -> x1 - v55 Imm(0) -> x1 - v56 Imm(0) -> x1 - v57 Binop { op=fmul, lhs=v49, rhs=v51 } -> d3 [f32] - v58 Fma { a=v49, b=v51, c=v53, neg_product=false, neg_addend=true } -> d0 [f32] - v59 FpCast { kind=F32ToF64, value=v58 } -> d0 - v60 Binop { op=fne, lhs=v59, rhs=v48 } -> x0 - terminator Bz { cond=v60, target=b10, fall=b9 } (exit_acc=v60) + v44 Imm(1073741824) -> x0 [f32] + v45 Imm(1077936128) -> x1 [f32] + v46 Imm(1082130432) -> x2 [f32] + v47 Imm(0) -> x6 + v48 Imm(0) -> x6 + v49 Imm(0) -> x6 + v50 Binop { op=fmul, lhs=v44, rhs=v45 } -> d0 [f32] + v51 Fma { a=v44, b=v45, c=v46, neg_product=false, neg_addend=true } -> d0 [f32] + v52 Binop { op=fne, lhs=v51, rhs=v44 } -> x0 + terminator Bz { cond=v52, target=b10, fall=b9 } (exit_acc=v52) block 9 start_pc=0 - v61 Imm(5) -> x0 - terminator Return(v61) (exit_acc=v61) + v53 Imm(5) -> x0 + terminator Return(v53) (exit_acc=v53) block 10 start_pc=0 - v62 Imm(4611686018427387904) -> x0 - v63 FpCast { kind=F64ToF32, value=v62 } -> d0 [f32] - v64 Imm(4613937818241073152) -> x1 - v65 FpCast { kind=F64ToF32, value=v64 } -> d1 [f32] - v66 Imm(4616189618054758400) -> x1 - v67 FpCast { kind=F64ToF32, value=v66 } -> d2 [f32] - v68 Imm(0) -> x1 - v69 Imm(0) -> x1 - v70 Imm(0) -> x1 - v71 Binop { op=fmul, lhs=v63, rhs=v65 } -> d3 [f32] - v72 Fma { a=v63, b=v65, c=v67, neg_product=true, neg_addend=false } -> d0 [f32] - v73 Fneg(v62) -> d1 - v74 FpCast { kind=F32ToF64, value=v72 } -> d0 - v75 Binop { op=fne, lhs=v74, rhs=v73 } -> x0 - terminator Bz { cond=v75, target=b12, fall=b11 } (exit_acc=v75) + v54 Imm(1073741824) -> x0 [f32] + v55 Imm(1077936128) -> x1 [f32] + v56 Imm(1082130432) -> x2 [f32] + v57 Imm(0) -> x6 + v58 Imm(0) -> x6 + v59 Imm(0) -> x6 + v60 Binop { op=fmul, lhs=v54, rhs=v55 } -> d0 [f32] + v61 Fma { a=v54, b=v55, c=v56, neg_product=true, neg_addend=false } -> d0 [f32] + v62 Fneg(v54) -> d1 [f32] + v63 Binop { op=fne, lhs=v61, rhs=v62 } -> x0 + terminator Bz { cond=v63, target=b12, fall=b11 } (exit_acc=v63) block 11 start_pc=0 - v76 Imm(6) -> x0 - terminator Return(v76) (exit_acc=v76) + v64 Imm(6) -> x0 + terminator Return(v64) (exit_acc=v64) block 12 start_pc=0 - v77 Imm(4602678819172646912) -> x0 - v78 Imm(4598175219545276416) -> x1 - v79 Imm(4593671619917905920) -> x2 - v80 Imm(0) -> x6 - v81 Imm(0) -> x6 - v82 Imm(0) -> x6 - v83 Binop { op=fmul, lhs=v77, rhs=v78 } -> d0 - v84 Fma { a=v77, b=v78, c=v79, neg_product=false, neg_addend=false } -> d0 - v85 Binop { op=fne, lhs=v84, rhs=v78 } -> x0 - terminator Bz { cond=v85, target=b14, fall=b13 } (exit_acc=v85) + v65 Imm(4602678819172646912) -> x0 + v66 Imm(4598175219545276416) -> x1 + v67 Imm(4593671619917905920) -> x2 + v68 Imm(0) -> x6 + v69 Imm(0) -> x6 + v70 Imm(0) -> x6 + v71 Binop { op=fmul, lhs=v65, rhs=v66 } -> d0 + v72 Fma { a=v65, b=v66, c=v67, neg_product=false, neg_addend=false } -> d0 + v73 Binop { op=fne, lhs=v72, rhs=v66 } -> x0 + terminator Bz { cond=v73, target=b14, fall=b13 } (exit_acc=v73) block 13 start_pc=0 - v86 Imm(7) -> x0 - terminator Return(v86) (exit_acc=v86) + v74 Imm(7) -> x0 + terminator Return(v74) (exit_acc=v74) block 14 start_pc=0 - v87 Imm(4602678819172646912) -> x0 - v88 FpCast { kind=F64ToF32, value=v87 } -> d0 [f32] - v89 Imm(4598175219545276416) -> x0 - v90 FpCast { kind=F64ToF32, value=v89 } -> d1 [f32] - v91 Imm(4593671619917905920) -> x1 - v92 FpCast { kind=F64ToF32, value=v91 } -> d2 [f32] - v93 Imm(0) -> x1 - v94 Imm(0) -> x1 - v95 Imm(0) -> x1 - v96 Binop { op=fmul, lhs=v88, rhs=v90 } -> d3 [f32] - v97 Fma { a=v88, b=v90, c=v92, neg_product=false, neg_addend=false } -> d0 [f32] - v98 FpCast { kind=F32ToF64, value=v97 } -> d0 - v99 Binop { op=fne, lhs=v98, rhs=v89 } -> x0 - terminator Bz { cond=v99, target=b16, fall=b15 } (exit_acc=v99) + v75 Imm(1056964608) -> x0 [f32] + v76 Imm(1048576000) -> x1 [f32] + v77 Imm(1040187392) -> x2 [f32] + v78 Imm(0) -> x6 + v79 Imm(0) -> x6 + v80 Imm(0) -> x6 + v81 Binop { op=fmul, lhs=v75, rhs=v76 } -> d0 [f32] + v82 Fma { a=v75, b=v76, c=v77, neg_product=false, neg_addend=false } -> d0 [f32] + v83 Binop { op=fne, lhs=v82, rhs=v76 } -> x0 + terminator Bz { cond=v83, target=b16, fall=b15 } (exit_acc=v83) block 15 start_pc=0 - v100 Imm(8) -> x0 - terminator Return(v100) (exit_acc=v100) + v84 Imm(8) -> x0 + terminator Return(v84) (exit_acc=v84) block 16 start_pc=0 - v101 Imm(4611686018427387904) -> x0 - v102 Imm(4613937818241073152) -> x1 - v103 Imm(4616189618054758400) -> x2 - v104 Fma { a=v101, b=v102, c=v103, neg_product=false, neg_addend=false } -> d0 - v105 Imm(4621819117588971520) -> x0 - v106 Binop { op=fne, lhs=v104, rhs=v105 } -> x0 - terminator Bz { cond=v106, target=b18, fall=b17 } (exit_acc=v106) + v85 Imm(4611686018427387904) -> x0 + v86 Imm(4613937818241073152) -> x1 + v87 Imm(4616189618054758400) -> x2 + v88 Fma { a=v85, b=v86, c=v87, neg_product=false, neg_addend=false } -> d0 + v89 Imm(4621819117588971520) -> x0 + v90 Binop { op=fne, lhs=v88, rhs=v89 } -> x0 + terminator Bz { cond=v90, target=b18, fall=b17 } (exit_acc=v90) block 17 start_pc=0 - v107 Imm(9) -> x0 - terminator Return(v107) (exit_acc=v107) + v91 Imm(9) -> x0 + terminator Return(v91) (exit_acc=v91) block 18 start_pc=0 - v108 Imm(4602678819172646912) -> x0 - v109 Imm(4598175219545276416) -> x1 - v110 Imm(4593671619917905920) -> x2 - v111 Fma { a=v108, b=v109, c=v110, neg_product=false, neg_addend=false } -> d0 - v112 Binop { op=fne, lhs=v111, rhs=v109 } -> x0 - terminator Bz { cond=v112, target=b20, fall=b19 } (exit_acc=v112) + v92 Imm(4602678819172646912) -> x0 + v93 Imm(4598175219545276416) -> x1 + v94 Imm(4593671619917905920) -> x2 + v95 Fma { a=v92, b=v93, c=v94, neg_product=false, neg_addend=false } -> d0 + v96 Binop { op=fne, lhs=v95, rhs=v93 } -> x0 + terminator Bz { cond=v96, target=b20, fall=b19 } (exit_acc=v96) block 19 start_pc=0 - v113 Imm(10) -> x0 - terminator Return(v113) (exit_acc=v113) + v97 Imm(10) -> x0 + terminator Return(v97) (exit_acc=v97) block 20 start_pc=0 - v114 Imm(4611686018427387904) -> x0 - v115 FpCast { kind=F64ToF32, value=v114 } -> d0 [f32] - v116 Imm(4613937818241073152) -> x0 - v117 FpCast { kind=F64ToF32, value=v116 } -> d1 [f32] - v118 Imm(4616189618054758400) -> x0 - v119 FpCast { kind=F64ToF32, value=v118 } -> d2 [f32] - v120 Fma { a=v115, b=v117, c=v119, neg_product=false, neg_addend=false } -> d0 [f32] - v121 Imm(4621819117588971520) -> x0 - v122 FpCast { kind=F32ToF64, value=v120 } -> d0 - v123 Binop { op=fne, lhs=v122, rhs=v121 } -> x0 - terminator Bz { cond=v123, target=b22, fall=b21 } (exit_acc=v123) + v98 Imm(1073741824) -> x0 [f32] + v99 Imm(1077936128) -> x1 [f32] + v100 Imm(1082130432) -> x2 [f32] + v101 Fma { a=v98, b=v99, c=v100, neg_product=false, neg_addend=false } -> d0 [f32] + v102 Imm(1092616192) -> x0 [f32] + v103 Binop { op=fne, lhs=v101, rhs=v102 } -> x0 + terminator Bz { cond=v103, target=b22, fall=b21 } (exit_acc=v103) block 21 start_pc=0 - v124 Imm(11) -> x0 - terminator Return(v124) (exit_acc=v124) + v104 Imm(11) -> x0 + terminator Return(v104) (exit_acc=v104) block 22 start_pc=0 - v125 Imm(2) -> x0 - v126 FpCast { kind=IntToFp, value=v125 } -> d0 - v127 Imm(3) -> x0 - v128 FpCast { kind=IntToFp, value=v127 } -> d1 - v129 Imm(4) -> x0 - v130 FpCast { kind=IntToFp, value=v129 } -> d2 - v131 Fma { a=v126, b=v128, c=v130, neg_product=false, neg_addend=false } -> d0 - v132 Imm(4621819117588971520) -> x0 - v133 Binop { op=fne, lhs=v131, rhs=v132 } -> x0 - terminator Bz { cond=v133, target=b24, fall=b23 } (exit_acc=v133) + v105 Imm(2) -> x0 + v106 FpCast { kind=IntToFp, value=v105 } -> d0 + v107 Imm(3) -> x0 + v108 FpCast { kind=IntToFp, value=v107 } -> d1 + v109 Imm(4) -> x0 + v110 FpCast { kind=IntToFp, value=v109 } -> d2 + v111 Fma { a=v106, b=v108, c=v110, neg_product=false, neg_addend=false } -> d0 + v112 Imm(4621819117588971520) -> x0 + v113 Binop { op=fne, lhs=v111, rhs=v112 } -> x0 + terminator Bz { cond=v113, target=b24, fall=b23 } (exit_acc=v113) block 23 start_pc=0 - v134 Imm(12) -> x0 - terminator Return(v134) (exit_acc=v134) + v114 Imm(12) -> x0 + terminator Return(v114) (exit_acc=v114) block 24 start_pc=0 - v135 Imm(0) -> x0 - terminator Return(v135) (exit_acc=v135) + v115 Imm(0) -> x0 + terminator Return(v115) (exit_acc=v115) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_arg.ssa b/tests/snapshots/ssa/fn_ptr_float_arg.ssa index 5a1c5f3d7..a8c5b282c 100644 --- a/tests/snapshots/ssa/fn_ptr_float_arg.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_arg.ssa @@ -7,9 +7,9 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v1 ParamRef(0, kind=F32) -> d0 [f32] v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v1 } -> d0 - v6 Binop { op=fmul, lhs=v5, rhs=v4 } -> d0 + v4 Imm(1073741824) -> x0 [f32] + v5 Binop { op=fmul, lhs=v1, rhs=v4 } -> d0 [f32] + v6 FpCast { kind=F32ToF64, value=v5 } -> d0 v7 FpCast { kind=FpToInt, value=v6 } -> x0 terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=1 --- @@ -75,58 +75,54 @@ fn ent_pc=4 n_params=0 variadic=false locals=5 v0 AllocaInit(0) -> - v1 ImmCode(ent_pc=0) -> x3 v2 Imm(0) -> x0 - v3 Imm(4612811918334230528) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 LoadLocal { off=-1, kind=I64 } -> x0 - v6 CallIndirect { target=v1, args=[v4], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v7 BinopI { op=shl, lhs=v6, rhs_imm=32 } -> x1 - v8 Extend { value=v6, kind=I32 } -> x0 - v9 BinopI { op=ne, lhs=v8, rhs_imm=5 } -> x0 - terminator Bz { cond=v9, target=b2, fall=b1 } (exit_acc=v9) + v3 Imm(1075838976) -> x7 [f32] + v4 LoadLocal { off=-1, kind=I64 } -> x0 + v5 CallIndirect { target=v1, args=[v3], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v6 BinopI { op=shl, lhs=v5, rhs_imm=32 } -> x1 + v7 Extend { value=v5, kind=I32 } -> x0 + v8 BinopI { op=ne, lhs=v7, rhs_imm=5 } -> x0 + terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) block 1 start_pc=0 - v10 Imm(1) -> x0 - terminator Return(v10) (exit_acc=v10) + v9 Imm(1) -> x0 + terminator Return(v9) (exit_acc=v9) block 2 start_pc=0 - v11 ImmCode(ent_pc=1) -> x0 - v12 Imm(0) -> x1 - v13 Imm(3) -> x7 - v14 Imm(4616752568008179712) -> x1 - v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] - v16 LoadLocal { off=-2, kind=I64 } -> x1 - v17 CallIndirect { target=v11, args=[v13, v15], callee_variadic=false, fixed_args=2, fp_return=false, fp_arg_mask=0x2 } -> x0 - v18 BinopI { op=shl, lhs=v17, rhs_imm=32 } -> x1 - v19 Extend { value=v17, kind=I32 } -> x0 - v20 BinopI { op=ne, lhs=v19, rhs_imm=7 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v10 ImmCode(ent_pc=1) -> x0 + v11 Imm(0) -> x1 + v12 Imm(3) -> x7 + v13 Imm(1083179008) -> x6 [f32] + v14 LoadLocal { off=-2, kind=I64 } -> x1 + v15 CallIndirect { target=v10, args=[v12, v13], callee_variadic=false, fixed_args=2, fp_return=false, fp_arg_mask=0x2 } -> x0 + v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 + v17 Extend { value=v15, kind=I32 } -> x0 + v18 BinopI { op=ne, lhs=v17, rhs_imm=7 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v21 Imm(2) -> x0 - terminator Return(v21) (exit_acc=v21) + v19 Imm(2) -> x0 + terminator Return(v19) (exit_acc=v19) block 4 start_pc=0 - v22 Imm(10) -> x7 - v23 ImmCode(ent_pc=3) -> x6 - v24 Imm(4612811918334230528) -> x0 - v25 FpCast { kind=F64ToF32, value=v24 } -> d0 [f32] - v26 Call { target_pc=2, args=[v22, v23, v25], fixed_args=3, fp_return=false, fp_arg_mask=0x4 } -> x0 - v27 BinopI { op=ne, lhs=v26, rhs_imm=12 } -> x0 - terminator Bz { cond=v27, target=b6, fall=b5 } (exit_acc=v27) + v20 Imm(10) -> x7 + v21 ImmCode(ent_pc=3) -> x6 + v22 Imm(1075838976) -> x2 [f32] + v23 Call { target_pc=2, args=[v20, v21, v22], fixed_args=3, fp_return=false, fp_arg_mask=0x4 } -> x0 + v24 BinopI { op=ne, lhs=v23, rhs_imm=12 } -> x0 + terminator Bz { cond=v24, target=b6, fall=b5 } (exit_acc=v24) block 5 start_pc=0 - v28 Imm(3) -> x0 - terminator Return(v28) (exit_acc=v28) + v25 Imm(3) -> x0 + terminator Return(v25) (exit_acc=v25) block 6 start_pc=0 - v29 Imm(4615063718147915776) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 LoadLocal { off=-1, kind=I64 } -> x0 - v32 CallIndirect { target=v1, args=[v30], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v33 BinopI { op=shl, lhs=v32, rhs_imm=32 } -> x1 - v34 Extend { value=v32, kind=I32 } -> x0 - v35 BinopI { op=ne, lhs=v34, rhs_imm=7 } -> x0 - terminator Bz { cond=v35, target=b8, fall=b7 } (exit_acc=v35) + v26 Imm(1080033280) -> x7 [f32] + v27 LoadLocal { off=-1, kind=I64 } -> x0 + v28 CallIndirect { target=v1, args=[v26], callee_variadic=false, fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x1 + v30 Extend { value=v28, kind=I32 } -> x0 + v31 BinopI { op=ne, lhs=v30, rhs_imm=7 } -> x0 + terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v36 Imm(4) -> x0 - terminator Return(v36) (exit_acc=v36) + v32 Imm(4) -> x0 + terminator Return(v32) (exit_acc=v32) block 8 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) + v33 Imm(0) -> x0 + terminator Return(v33) (exit_acc=v33) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa b/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa index eed53e27e..a6d047b2a 100644 --- a/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_arg_narrow.ssa @@ -7,11 +7,9 @@ fn ent_pc=0 n_params=1 variadic=false locals=1 v1 ParamRef(0, kind=F32) -> d0 [f32] v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v1 } -> d0 - v6 Binop { op=fmul, lhs=v5, rhs=v4 } -> d0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] - terminator Return(v7) (exit_acc=v7) + v4 Imm(1073741824) -> x0 [f32] + v5 Binop { op=fmul, lhs=v1, rhs=v4 } -> d0 [f32] + terminator Return(v5) (exit_acc=v5) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=negf fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -49,148 +47,128 @@ fn ent_pc=3 n_params=0 variadic=false locals=29 v4 LocalAddr(-2) -> x0 v5 Imm(0) -> x1 v6 Load { addr=v4, disp=0, kind=I64 } -> x0 - v7 Imm(4613937818241073152) -> x1 - v8 FpCast { kind=F64ToF32, value=v7 } -> d0 [f32] - v9 CallIndirect { target=v6, args=[v8], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v10 Imm(4618441417868443648) -> x0 - v11 FpCast { kind=F32ToF64, value=v9 } -> d0 - v12 Binop { op=fne, lhs=v11, rhs=v10 } -> x0 - terminator Bz { cond=v12, target=b2, fall=b1 } (exit_acc=v12) + v7 Imm(1077936128) -> x7 [f32] + v8 CallIndirect { target=v6, args=[v7], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v9 Imm(1086324736) -> x0 [f32] + v10 Binop { op=fne, lhs=v8, rhs=v9 } -> x0 + terminator Bz { cond=v10, target=b2, fall=b1 } (exit_acc=v10) block 1 start_pc=0 - v13 Imm(1) -> x0 - terminator Return(v13) (exit_acc=v13) + v11 Imm(1) -> x0 + terminator Return(v11) (exit_acc=v11) block 2 start_pc=0 - v14 LocalAddr(-2) -> x0 - v15 Imm(8) -> x1 - v16 BinopI { op=add, lhs=v14, rhs_imm=8 } -> x1 - v17 Load { addr=v14, disp=8, kind=I64 } -> x0 - v18 Imm(4613937818241073152) -> x3 - v19 FpCast { kind=F64ToF32, value=v18 } -> d0 [f32] - v20 CallIndirect { target=v17, args=[v19], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v21 Fneg(v18) -> d1 - v22 FpCast { kind=F32ToF64, value=v20 } -> d0 - v23 Binop { op=fne, lhs=v22, rhs=v21 } -> x0 - terminator Bz { cond=v23, target=b4, fall=b3 } (exit_acc=v23) + v12 LocalAddr(-2) -> x0 + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v12, rhs_imm=8 } -> x1 + v15 Load { addr=v12, disp=8, kind=I64 } -> x0 + v16 Imm(1077936128) -> x3 [f32] + v17 CallIndirect { target=v15, args=[v16], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v18 Fneg(v16) -> d1 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b4, fall=b3 } (exit_acc=v19) block 3 start_pc=0 - v24 Imm(2) -> x0 - terminator Return(v24) (exit_acc=v24) + v20 Imm(2) -> x0 + terminator Return(v20) (exit_acc=v20) block 4 start_pc=0 - v25 Imm(0) -> x0 - v26 Imm(0) -> x1 - v27 LocalAddr(-2) -> x1 - v28 LoadLocal { off=-7, kind=I32 } -> x2 - v29 BinopI { op=shl, lhs=v25, rhs_imm=3 } -> x2 - v30 Binop { op=add, lhs=v27, rhs=v29 } -> x2 - v31 LoadIndexed { base=v27, index=v25, scale=8, kind=I64 } -> x0 - v32 Imm(4616189618054758400) -> x1 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 CallIndirect { target=v31, args=[v33], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v35 Imm(4620693217682128896) -> x0 - v36 FpCast { kind=F32ToF64, value=v34 } -> d0 - v37 Binop { op=fne, lhs=v36, rhs=v35 } -> x0 - terminator Bz { cond=v37, target=b6, fall=b5 } (exit_acc=v37) + v21 Imm(0) -> x0 + v22 Imm(0) -> x1 + v23 LocalAddr(-2) -> x1 + v24 LoadLocal { off=-7, kind=I32 } -> x2 + v25 BinopI { op=shl, lhs=v21, rhs_imm=3 } -> x2 + v26 Binop { op=add, lhs=v23, rhs=v25 } -> x2 + v27 LoadIndexed { base=v23, index=v21, scale=8, kind=I64 } -> x0 + v28 Imm(1082130432) -> x7 [f32] + v29 CallIndirect { target=v27, args=[v28], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v30 Imm(1090519040) -> x0 [f32] + v31 Binop { op=fne, lhs=v29, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b6, fall=b5 } (exit_acc=v31) block 5 start_pc=0 - v38 Imm(3) -> x0 - terminator Return(v38) (exit_acc=v38) + v32 Imm(3) -> x0 + terminator Return(v32) (exit_acc=v32) block 6 start_pc=0 - v39 LocalAddr(-10) -> x0 - v40 ImmData(24) -> x1 - v41 Mcpy { dst=v39, src=v40, size=8 } -> x0 - v42 LocalAddr(-10) -> x0 - v43 Imm(0) -> x1 - v44 Load { addr=v42, disp=0, kind=I64 } -> x0 - v45 Imm(4609434218613702656) -> x1 - v46 FpCast { kind=F64ToF32, value=v45 } -> d0 [f32] - v47 Imm(4611686018427387904) -> x1 - v48 FpCast { kind=F64ToF32, value=v47 } -> d1 [f32] - v49 CallIndirect { target=v44, args=[v46, v48], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v50 Imm(4615063718147915776) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b8, fall=b7 } (exit_acc=v52) + v33 LocalAddr(-10) -> x0 + v34 ImmData(24) -> x1 + v35 Mcpy { dst=v33, src=v34, size=8 } -> x0 + v36 LocalAddr(-10) -> x0 + v37 Imm(0) -> x1 + v38 Load { addr=v36, disp=0, kind=I64 } -> x0 + v39 Imm(1069547520) -> x7 [f32] + v40 Imm(1073741824) -> x6 [f32] + v41 CallIndirect { target=v38, args=[v39, v40], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v42 Imm(1080033280) -> x0 [f32] + v43 Binop { op=fne, lhs=v41, rhs=v42 } -> x0 + terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) block 7 start_pc=0 - v53 Imm(4) -> x0 - terminator Return(v53) (exit_acc=v53) + v44 Imm(4) -> x0 + terminator Return(v44) (exit_acc=v44) block 8 start_pc=0 - v54 ImmCode(ent_pc=0) -> x0 - v55 Imm(0) -> x1 - v56 Imm(4617315517961601024) -> x1 - v57 FpCast { kind=F64ToF32, value=v56 } -> d0 [f32] - v58 LoadLocal { off=-14, kind=I64 } -> x1 - v59 CallIndirect { target=v54, args=[v57], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v60 Imm(4621819117588971520) -> x0 - v61 FpCast { kind=F32ToF64, value=v59 } -> d0 - v62 Binop { op=fne, lhs=v61, rhs=v60 } -> x0 - terminator Bz { cond=v62, target=b10, fall=b9 } (exit_acc=v62) + v45 ImmCode(ent_pc=0) -> x0 + v46 Imm(0) -> x1 + v47 Imm(1084227584) -> x7 [f32] + v48 LoadLocal { off=-14, kind=I64 } -> x1 + v49 CallIndirect { target=v45, args=[v47], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v50 Imm(1092616192) -> x0 [f32] + v51 Binop { op=fne, lhs=v49, rhs=v50 } -> x0 + terminator Bz { cond=v51, target=b10, fall=b9 } (exit_acc=v51) block 9 start_pc=0 - v63 Imm(5) -> x0 - terminator Return(v63) (exit_acc=v63) + v52 Imm(5) -> x0 + terminator Return(v52) (exit_acc=v52) block 10 start_pc=0 - v64 Imm(4619567317775286272) -> x0 - v65 FpCast { kind=F64ToF32, value=v64 } -> d0 [f32] - v66 Imm(0) -> x0 - v67 LocalAddr(-2) -> x0 - v68 Imm(0) -> x1 - v69 Load { addr=v67, disp=0, kind=I64 } -> x0 - v70 LoadLocal { off=-17, kind=F32 } -> d1 [f32] - v71 CallIndirect { target=v69, args=[v65], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v72 Imm(4624070917402656768) -> x0 - v73 FpCast { kind=F32ToF64, value=v71 } -> d0 - v74 Binop { op=fne, lhs=v73, rhs=v72 } -> x0 - terminator Bz { cond=v74, target=b12, fall=b11 } (exit_acc=v74) + v53 Imm(1088421888) -> x0 [f32] + v54 StoreLocal { off=-17, value=v53, kind=F32 } -> - + v55 LocalAddr(-2) -> x0 + v56 Imm(0) -> x1 + v57 Load { addr=v55, disp=0, kind=I64 } -> x0 + v58 LoadLocal { off=-17, kind=F32 } -> d0 [f32] + v59 CallIndirect { target=v57, args=[v58], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v60 Imm(1096810496) -> x0 [f32] + v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x0 + terminator Bz { cond=v61, target=b12, fall=b11 } (exit_acc=v61) block 11 start_pc=0 - v75 Imm(6) -> x0 - terminator Return(v75) (exit_acc=v75) + v62 Imm(6) -> x0 + terminator Return(v62) (exit_acc=v62) block 12 start_pc=0 - v76 LocalAddr(-21) -> x0 - v77 ImmData(32) -> x1 - v78 Mcpy { dst=v76, src=v77, size=16 } -> x0 - v79 LocalAddr(-21) -> x3 - v80 Imm(0) -> x0 - v81 LocalAddr(-21) -> x0 - v82 Load { addr=v81, disp=0, kind=I64 } -> x0 - v83 Imm(4613937818241073152) -> x1 - v84 FpCast { kind=F64ToF32, value=v83 } -> d0 [f32] - v85 CallIndirect { target=v82, args=[v84], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v86 Imm(4618441417868443648) -> x0 - v87 FpCast { kind=F32ToF64, value=v85 } -> d0 - v88 Binop { op=fne, lhs=v87, rhs=v86 } -> x0 - terminator Bz { cond=v88, target=b14, fall=b13 } (exit_acc=v88) + v63 LocalAddr(-21) -> x0 + v64 ImmData(32) -> x1 + v65 Mcpy { dst=v63, src=v64, size=16 } -> x0 + v66 LocalAddr(-21) -> x3 + v67 Imm(0) -> x0 + v68 LocalAddr(-21) -> x0 + v69 Load { addr=v68, disp=0, kind=I64 } -> x0 + v70 Imm(1077936128) -> x7 [f32] + v71 CallIndirect { target=v69, args=[v70], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v72 Imm(1086324736) -> x0 [f32] + v73 Binop { op=fne, lhs=v71, rhs=v72 } -> x0 + terminator Bz { cond=v73, target=b14, fall=b13 } (exit_acc=v73) block 13 start_pc=0 - v89 Imm(7) -> x0 - terminator Return(v89) (exit_acc=v89) + v74 Imm(7) -> x0 + terminator Return(v74) (exit_acc=v74) block 14 start_pc=0 - v90 LoadLocal { off=-22, kind=I64 } -> x0 - v91 Load { addr=v79, disp=0, kind=I64 } -> x0 - v92 Imm(4613937818241073152) -> x1 - v93 FpCast { kind=F64ToF32, value=v92 } -> d0 [f32] - v94 CallIndirect { target=v91, args=[v93], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v95 Imm(4618441417868443648) -> x0 - v96 FpCast { kind=F32ToF64, value=v94 } -> d0 - v97 Binop { op=fne, lhs=v96, rhs=v95 } -> x0 - terminator Bz { cond=v97, target=b16, fall=b15 } (exit_acc=v97) + v75 LoadLocal { off=-22, kind=I64 } -> x0 + v76 Load { addr=v66, disp=0, kind=I64 } -> x0 + v77 Imm(1077936128) -> x7 [f32] + v78 CallIndirect { target=v76, args=[v77], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v79 Imm(1086324736) -> x0 [f32] + v80 Binop { op=fne, lhs=v78, rhs=v79 } -> x0 + terminator Bz { cond=v80, target=b16, fall=b15 } (exit_acc=v80) block 15 start_pc=0 - v98 Imm(8) -> x0 - terminator Return(v98) (exit_acc=v98) + v81 Imm(8) -> x0 + terminator Return(v81) (exit_acc=v81) block 16 start_pc=0 - v99 LoadLocal { off=-22, kind=I64 } -> x0 - v100 BinopI { op=add, lhs=v79, rhs_imm=8 } -> x0 - v101 Load { addr=v79, disp=8, kind=I64 } -> x0 - v102 Imm(4609434218613702656) -> x1 - v103 FpCast { kind=F64ToF32, value=v102 } -> d0 [f32] - v104 Imm(4611686018427387904) -> x1 - v105 FpCast { kind=F64ToF32, value=v104 } -> d1 [f32] - v106 CallIndirect { target=v101, args=[v103, v105], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v107 Imm(4615063718147915776) -> x0 - v108 FpCast { kind=F32ToF64, value=v106 } -> d0 - v109 Binop { op=fne, lhs=v108, rhs=v107 } -> x0 - terminator Bz { cond=v109, target=b18, fall=b17 } (exit_acc=v109) + v82 LoadLocal { off=-22, kind=I64 } -> x0 + v83 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x0 + v84 Load { addr=v66, disp=8, kind=I64 } -> x0 + v85 Imm(1069547520) -> x7 [f32] + v86 Imm(1073741824) -> x6 [f32] + v87 CallIndirect { target=v84, args=[v85, v86], callee_variadic=false, fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v88 Imm(1080033280) -> x0 [f32] + v89 Binop { op=fne, lhs=v87, rhs=v88 } -> x0 + terminator Bz { cond=v89, target=b18, fall=b17 } (exit_acc=v89) block 17 start_pc=0 - v110 Imm(9) -> x0 - terminator Return(v110) (exit_acc=v110) + v90 Imm(9) -> x0 + terminator Return(v90) (exit_acc=v90) block 18 start_pc=0 - v111 Imm(0) -> x0 - terminator Return(v111) (exit_acc=v111) + v91 Imm(0) -> x0 + terminator Return(v91) (exit_acc=v91) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fn_ptr_float_return.ssa b/tests/snapshots/ssa/fn_ptr_float_return.ssa index cccfbf012..e2474327c 100644 --- a/tests/snapshots/ssa/fn_ptr_float_return.ssa +++ b/tests/snapshots/ssa/fn_ptr_float_return.ssa @@ -4,9 +4,8 @@ fn ent_pc=0 n_params=0 variadic=false locals=0 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4612811918334230528) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - terminator Return(v2) (exit_acc=v2) + v1 Imm(1075838976) -> x0 [f32] + terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=f_int fn ent_pc=1 n_params=1 variadic=false locals=1 @@ -17,9 +16,9 @@ fn ent_pc=1 n_params=1 variadic=false locals=1 v2 Imm(0) -> x0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 FpCast { kind=IntToFp, value=v1 } -> d0 - v5 Imm(4602678819172646912) -> x0 - v6 Binop { op=fmul, lhs=v4, rhs=v5 } -> d0 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] + v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] + v6 Imm(1056964608) -> x0 [f32] + v7 Binop { op=fmul, lhs=v5, rhs=v6 } -> d0 [f32] terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=f_double @@ -57,64 +56,60 @@ fn ent_pc=4 n_params=0 variadic=false locals=5 v2 Imm(0) -> x0 v3 LoadLocal { off=-1, kind=I64 } -> x0 v4 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v5 Imm(4612811918334230528) -> x0 - v6 FpCast { kind=F32ToF64, value=v4 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v5 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Imm(1075838976) -> x0 [f32] + v6 Binop { op=fne, lhs=v4, rhs=v5 } -> x0 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v7 Imm(1) -> x0 + terminator Return(v7) (exit_acc=v7) block 2 start_pc=0 - v9 ImmCode(ent_pc=1) -> x0 - v10 Imm(0) -> x1 - v11 Imm(10) -> x7 - v12 LoadLocal { off=-2, kind=I64 } -> x1 - v13 CallIndirect { target=v9, args=[v11], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v14 Imm(4617315517961601024) -> x0 - v15 FpCast { kind=F32ToF64, value=v13 } -> d0 - v16 Binop { op=fne, lhs=v15, rhs=v14 } -> x0 - terminator Bz { cond=v16, target=b4, fall=b3 } (exit_acc=v16) + v8 ImmCode(ent_pc=1) -> x0 + v9 Imm(0) -> x1 + v10 Imm(10) -> x7 + v11 LoadLocal { off=-2, kind=I64 } -> x1 + v12 CallIndirect { target=v8, args=[v10], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v13 Imm(1084227584) -> x0 [f32] + v14 Binop { op=fne, lhs=v12, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) block 3 start_pc=0 - v17 Imm(2) -> x0 - terminator Return(v17) (exit_acc=v17) + v15 Imm(2) -> x0 + terminator Return(v15) (exit_acc=v15) block 4 start_pc=0 - v18 ImmCode(ent_pc=2) -> x0 - v19 Imm(0) -> x1 - v20 Imm(4611686018427387904) -> x7 - v21 LoadLocal { off=-3, kind=I64 } -> x1 - v22 CallIndirect { target=v18, args=[v20], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v23 Imm(4613937818241073152) -> x0 - v24 FpCast { kind=F32ToF64, value=v22 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v23 } -> x0 - terminator Bz { cond=v25, target=b6, fall=b5 } (exit_acc=v25) + v16 ImmCode(ent_pc=2) -> x0 + v17 Imm(0) -> x1 + v18 Imm(4611686018427387904) -> x7 + v19 LoadLocal { off=-3, kind=I64 } -> x1 + v20 CallIndirect { target=v16, args=[v18], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v21 Imm(1077936128) -> x0 [f32] + v22 Binop { op=fne, lhs=v20, rhs=v21 } -> x0 + terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) block 5 start_pc=0 - v26 Imm(3) -> x0 - terminator Return(v26) (exit_acc=v26) + v23 Imm(3) -> x0 + terminator Return(v23) (exit_acc=v23) block 6 start_pc=0 - v27 LoadLocal { off=-1, kind=I64 } -> x0 - v28 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v29 Imm(4612811918334230528) -> x0 - v30 FpCast { kind=F32ToF64, value=v28 } -> d0 - v31 Binop { op=fne, lhs=v30, rhs=v29 } -> x0 - terminator Bz { cond=v31, target=b8, fall=b7 } (exit_acc=v31) + v24 LoadLocal { off=-1, kind=I64 } -> x0 + v25 CallIndirect { target=v1, args=[], callee_variadic=false, fixed_args=0, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v26 Imm(1075838976) -> x0 [f32] + v27 Binop { op=fne, lhs=v25, rhs=v26 } -> x0 + terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) block 7 start_pc=0 - v32 Imm(4) -> x0 - terminator Return(v32) (exit_acc=v32) + v28 Imm(4) -> x0 + terminator Return(v28) (exit_acc=v28) block 8 start_pc=0 - v33 ImmCode(ent_pc=3) -> x0 - v34 Imm(0) -> x1 - v35 Imm(8) -> x7 - v36 LoadLocal { off=-4, kind=I64 } -> x1 - v37 CallIndirect { target=v33, args=[v35], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v38 Imm(4611686018427387904) -> x0 - v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 - terminator Bz { cond=v39, target=b10, fall=b9 } (exit_acc=v39) + v29 ImmCode(ent_pc=3) -> x0 + v30 Imm(0) -> x1 + v31 Imm(8) -> x7 + v32 LoadLocal { off=-4, kind=I64 } -> x1 + v33 CallIndirect { target=v29, args=[v31], callee_variadic=false, fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v34 Imm(4611686018427387904) -> x0 + v35 Binop { op=fne, lhs=v33, rhs=v34 } -> x0 + terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) block 9 start_pc=0 - v40 Imm(5) -> x0 - terminator Return(v40) (exit_acc=v40) + v36 Imm(5) -> x0 + terminator Return(v36) (exit_acc=v36) block 10 start_pc=0 - v41 Imm(0) -> x0 - terminator Return(v41) (exit_acc=v41) + v37 Imm(0) -> x0 + terminator Return(v37) (exit_acc=v37) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_const_return.ssa b/tests/snapshots/ssa/fp_const_return.ssa index 3d6d810e7..de0cb8193 100644 --- a/tests/snapshots/ssa/fp_const_return.ssa +++ b/tests/snapshots/ssa/fp_const_return.ssa @@ -67,9 +67,8 @@ fn ent_pc=4 n_params=0 variadic=false locals=0 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4598175219545276416) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - terminator Return(v2) (exit_acc=v2) + v1 Imm(1048576000) -> x0 [f32] + terminator Return(v1) (exit_acc=v1) ; --- SSA dump (ok=true) ent_pc=5 --- ; name=sum_zero fn ent_pc=5 n_params=2 variadic=false locals=2 @@ -181,31 +180,30 @@ fn ent_pc=6 n_params=0 variadic=false locals=12 v31 LocalAddr(-2) -> x7 v32 Imm(2) -> x6 v33 Call { target_pc=0, args=[v31, v32], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v34 Imm(4598175219545276416) -> x0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 FpCast { kind=F32ToF64, value=v35 } -> d0 - v37 Imm(4598175219545276416) -> x0 - v38 Binop { op=fne, lhs=v36, rhs=v37 } -> x0 - terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + v34 Imm(1048576000) -> x0 [f32] + v35 FpCast { kind=F32ToF64, value=v34 } -> d0 + v36 Imm(4598175219545276416) -> x0 + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b8, fall=b7 } (exit_acc=v37) block 7 start_pc=0 - v39 Imm(4) -> x0 - terminator Return(v39) (exit_acc=v39) + v38 Imm(4) -> x0 + terminator Return(v38) (exit_acc=v38) block 8 start_pc=0 - v40 LocalAddr(-2) -> x7 - v41 Imm(2) -> x6 - v42 Call { target_pc=0, args=[v40, v41], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v43 LocalAddr(-10) -> x7 - v44 Imm(8) -> x6 - v45 Call { target_pc=5, args=[v43, v44], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 - v46 Imm(0) -> x0 - v47 Binop { op=fne, lhs=v45, rhs=v46 } -> x0 - terminator Bz { cond=v47, target=b10, fall=b9 } (exit_acc=v47) + v39 LocalAddr(-2) -> x7 + v40 Imm(2) -> x6 + v41 Call { target_pc=0, args=[v39, v40], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 + v42 LocalAddr(-10) -> x7 + v43 Imm(8) -> x6 + v44 Call { target_pc=5, args=[v42, v43], fixed_args=2, fp_return=true, fp_arg_mask=0x0 } -> d0 + v45 Imm(0) -> x0 + v46 Binop { op=fne, lhs=v44, rhs=v45 } -> x0 + terminator Bz { cond=v46, target=b10, fall=b9 } (exit_acc=v46) block 9 start_pc=0 - v48 Imm(5) -> x0 - terminator Return(v48) (exit_acc=v48) + v47 Imm(5) -> x0 + terminator Return(v47) (exit_acc=v47) block 10 start_pc=0 - v49 Imm(0) -> x0 - terminator Return(v49) (exit_acc=v49) + v48 Imm(0) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_load_folded_disp.ssa b/tests/snapshots/ssa/fp_load_folded_disp.ssa index 6a6ed4450..d98c17ffb 100644 --- a/tests/snapshots/ssa/fp_load_folded_disp.ssa +++ b/tests/snapshots/ssa/fp_load_folded_disp.ssa @@ -63,80 +63,76 @@ fn ent_pc=4 n_params=0 variadic=false locals=6 v3 Store { addr=v1, disp=0, value=v2, kind=I64 } -> - v4 LocalAddr(-5) -> x0 v5 BinopI { op=add, lhs=v4, rhs_imm=8 } -> x1 - v6 Imm(4608308318706860032) -> x1 - v7 FpCast { kind=F64ToF32, value=v6 } -> d0 [f32] - v8 Store { addr=v4, disp=8, value=v7, kind=F32 } -> - - v9 LocalAddr(-5) -> x0 - v10 BinopI { op=add, lhs=v9, rhs_imm=16 } -> x2 - v11 Imm(4612811918334230528) -> x2 - v12 Store { addr=v9, disp=16, value=v11, kind=F64 } -> - - v13 LocalAddr(-5) -> x0 - v14 BinopI { op=add, lhs=v13, rhs_imm=24 } -> x2 - v15 Imm(0) -> x2 - v16 FpCast { kind=F64ToF32, value=v15 } -> d0 [f32] - v17 Store { addr=v13, disp=24, value=v16, kind=F32 } -> - - v18 LocalAddr(-5) -> x0 - v19 BinopI { op=add, lhs=v18, rhs_imm=24 } -> x2 - v20 Imm(4) -> x2 - v21 BinopI { op=add, lhs=v18, rhs_imm=28 } -> x2 - v22 Store { addr=v18, disp=28, value=v16, kind=F32 } -> - - v23 LocalAddr(-5) -> x0 - v24 BinopI { op=add, lhs=v23, rhs_imm=24 } -> x2 - v25 Imm(8) -> x2 - v26 BinopI { op=add, lhs=v23, rhs_imm=32 } -> x2 - v27 Imm(4617034042984890368) -> x2 - v28 FpCast { kind=F64ToF32, value=v27 } -> d0 [f32] - v29 Store { addr=v23, disp=32, value=v28, kind=F32 } -> - - v30 LocalAddr(-5) -> x0 - v31 Imm(0) -> x2 - v32 BinopI { op=add, lhs=v30, rhs_imm=8 } -> x2 - v33 Load { addr=v30, disp=8, kind=F32 } -> d0 [f32] - v34 FpCast { kind=F32ToF64, value=v33 } -> d0 - v35 Binop { op=fne, lhs=v34, rhs=v6 } -> x0 - terminator Bz { cond=v35, target=b2, fall=b1 } (exit_acc=v35) + v6 Imm(1067450368) -> x1 [f32] + v7 Store { addr=v4, disp=8, value=v6, kind=F32 } -> - + v8 LocalAddr(-5) -> x0 + v9 BinopI { op=add, lhs=v8, rhs_imm=16 } -> x2 + v10 Imm(4612811918334230528) -> x2 + v11 Store { addr=v8, disp=16, value=v10, kind=F64 } -> - + v12 LocalAddr(-5) -> x0 + v13 BinopI { op=add, lhs=v12, rhs_imm=24 } -> x2 + v14 Imm(0) -> x2 + v15 Imm(0) -> x2 [f32] + v16 Store { addr=v12, disp=24, value=v15, kind=F32 } -> - + v17 LocalAddr(-5) -> x0 + v18 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x6 + v19 Imm(4) -> x6 + v20 BinopI { op=add, lhs=v17, rhs_imm=28 } -> x6 + v21 Store { addr=v17, disp=28, value=v15, kind=F32 } -> - + v22 LocalAddr(-5) -> x0 + v23 BinopI { op=add, lhs=v22, rhs_imm=24 } -> x2 + v24 Imm(8) -> x2 + v25 BinopI { op=add, lhs=v22, rhs_imm=32 } -> x2 + v26 Imm(1083703296) -> x2 [f32] + v27 Store { addr=v22, disp=32, value=v26, kind=F32 } -> - + v28 LocalAddr(-5) -> x0 + v29 Imm(0) -> x2 + v30 BinopI { op=add, lhs=v28, rhs_imm=8 } -> x2 + v31 Load { addr=v28, disp=8, kind=F32 } -> d0 [f32] + v32 Binop { op=fne, lhs=v31, rhs=v6 } -> x0 + terminator Bz { cond=v32, target=b2, fall=b1 } (exit_acc=v32) block 1 start_pc=0 - v36 Imm(1) -> x0 - terminator Return(v36) (exit_acc=v36) + v33 Imm(1) -> x0 + terminator Return(v33) (exit_acc=v33) block 2 start_pc=0 - v37 LocalAddr(-5) -> x0 - v38 Imm(0) -> x1 - v39 BinopI { op=add, lhs=v37, rhs_imm=16 } -> x1 - v40 Load { addr=v37, disp=16, kind=F64 } -> d0 - v41 Imm(4612811918334230528) -> x0 - v42 Binop { op=fne, lhs=v40, rhs=v41 } -> x0 - terminator Bz { cond=v42, target=b4, fall=b3 } (exit_acc=v42) + v34 LocalAddr(-5) -> x0 + v35 Imm(0) -> x1 + v36 BinopI { op=add, lhs=v34, rhs_imm=16 } -> x1 + v37 Load { addr=v34, disp=16, kind=F64 } -> d0 + v38 Imm(4612811918334230528) -> x0 + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 + terminator Bz { cond=v39, target=b4, fall=b3 } (exit_acc=v39) block 3 start_pc=0 - v43 Imm(2) -> x0 - terminator Return(v43) (exit_acc=v43) + v40 Imm(2) -> x0 + terminator Return(v40) (exit_acc=v40) block 4 start_pc=0 - v44 LocalAddr(-5) -> x0 - v45 Imm(0) -> x1 - v46 BinopI { op=add, lhs=v44, rhs_imm=24 } -> x1 - v47 Imm(8) -> x1 - v48 BinopI { op=add, lhs=v44, rhs_imm=32 } -> x1 - v49 Load { addr=v44, disp=32, kind=F32 } -> d0 [f32] - v50 Imm(4617034042984890368) -> x0 - v51 FpCast { kind=F32ToF64, value=v49 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v50 } -> x0 - terminator Bz { cond=v52, target=b6, fall=b5 } (exit_acc=v52) + v41 LocalAddr(-5) -> x0 + v42 Imm(0) -> x1 + v43 BinopI { op=add, lhs=v41, rhs_imm=24 } -> x1 + v44 Imm(8) -> x1 + v45 BinopI { op=add, lhs=v41, rhs_imm=32 } -> x1 + v46 Load { addr=v41, disp=32, kind=F32 } -> d0 [f32] + v47 Imm(1083703296) -> x0 [f32] + v48 Binop { op=fne, lhs=v46, rhs=v47 } -> x0 + terminator Bz { cond=v48, target=b6, fall=b5 } (exit_acc=v48) block 5 start_pc=0 - v53 Imm(3) -> x0 - terminator Return(v53) (exit_acc=v53) + v49 Imm(3) -> x0 + terminator Return(v49) (exit_acc=v49) block 6 start_pc=0 - v54 LocalAddr(-5) -> x7 - v55 Call { target_pc=3, args=[v54], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v56 LocalAddr(-5) -> x0 - v57 BinopI { op=add, lhs=v56, rhs_imm=16 } -> x1 - v58 Load { addr=v56, disp=16, kind=F64 } -> d0 - v59 Imm(4613937818241073152) -> x0 - v60 Binop { op=fne, lhs=v58, rhs=v59 } -> x0 - terminator Bz { cond=v60, target=b8, fall=b7 } (exit_acc=v60) + v50 LocalAddr(-5) -> x7 + v51 Call { target_pc=3, args=[v50], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v52 LocalAddr(-5) -> x0 + v53 BinopI { op=add, lhs=v52, rhs_imm=16 } -> x1 + v54 Load { addr=v52, disp=16, kind=F64 } -> d0 + v55 Imm(4613937818241073152) -> x0 + v56 Binop { op=fne, lhs=v54, rhs=v55 } -> x0 + terminator Bz { cond=v56, target=b8, fall=b7 } (exit_acc=v56) block 7 start_pc=0 - v61 Imm(4) -> x0 - terminator Return(v61) (exit_acc=v61) + v57 Imm(4) -> x0 + terminator Return(v57) (exit_acc=v57) block 8 start_pc=0 - v62 Imm(0) -> x0 - terminator Return(v62) (exit_acc=v62) + v58 Imm(0) -> x0 + terminator Return(v58) (exit_acc=v58) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_param_float_before_double.ssa b/tests/snapshots/ssa/fp_param_float_before_double.ssa index 201e45d43..59e52a562 100644 --- a/tests/snapshots/ssa/fp_param_float_before_double.ssa +++ b/tests/snapshots/ssa/fp_param_float_before_double.ssa @@ -71,70 +71,65 @@ fn ent_pc=4 n_params=0 variadic=false locals=4 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4612811918334230528) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4616752568008179712) -> x1 + v1 Imm(1075838976) -> x0 [f32] + v2 Imm(4616752568008179712) -> x1 + v3 Imm(0) -> x1 v4 Imm(0) -> x1 - v5 Imm(0) -> x1 - v6 FpCast { kind=F32ToF64, value=v2 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v1 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v5 Binop { op=fne, lhs=v1, rhs=v1 } -> x0 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v9 Imm(4620974692658839552) -> x0 - v10 Imm(4619004367821864960) -> x0 - v11 FpCast { kind=F64ToF32, value=v10 } -> d0 [f32] - v12 Imm(0) -> x1 - v13 Imm(0) -> x1 - v14 FpCast { kind=F32ToF64, value=v11 } -> d0 - v15 Binop { op=fne, lhs=v14, rhs=v10 } -> x0 - terminator Bz { cond=v15, target=b4, fall=b3 } (exit_acc=v15) + v7 Imm(4620974692658839552) -> x0 + v8 Imm(1087373312) -> x0 [f32] + v9 Imm(0) -> x1 + v10 Imm(0) -> x1 + v11 FpCast { kind=F32ToF64, value=v8 } -> d0 + v12 FpCast { kind=F32ToF64, value=v8 } -> d1 + v13 Binop { op=fne, lhs=v11, rhs=v12 } -> x0 + terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) block 3 start_pc=0 - v16 Imm(2) -> x0 - terminator Return(v16) (exit_acc=v16) + v14 Imm(2) -> x0 + terminator Return(v14) (exit_acc=v14) block 4 start_pc=0 - v17 Imm(4607182418800017408) -> x0 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Imm(4611686018427387904) -> x0 - v20 Imm(4613937818241073152) -> x1 - v21 FpCast { kind=F64ToF32, value=v20 } -> d1 [f32] - v22 Imm(4616189618054758400) -> x1 - v23 Imm(0) -> x2 - v24 Imm(0) -> x2 - v25 Imm(0) -> x2 - v26 Imm(0) -> x2 - v27 FpCast { kind=F32ToF64, value=v18 } -> d0 - v28 Binop { op=fadd, lhs=v27, rhs=v19 } -> d0 - v29 FpCast { kind=F32ToF64, value=v21 } -> d1 - v30 Binop { op=fadd, lhs=v28, rhs=v29 } -> d0 - v31 Binop { op=fadd, lhs=v30, rhs=v22 } -> d0 - v32 Imm(4621819117588971520) -> x0 - v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x0 - terminator Bz { cond=v33, target=b6, fall=b5 } (exit_acc=v33) + v15 Imm(1065353216) -> x0 [f32] + v16 Imm(4611686018427387904) -> x1 + v17 Imm(1077936128) -> x2 [f32] + v18 Imm(4616189618054758400) -> x6 + v19 Imm(0) -> x7 + v20 Imm(0) -> x7 + v21 Imm(0) -> x7 + v22 Imm(0) -> x7 + v23 FpCast { kind=F32ToF64, value=v15 } -> d0 + v24 Binop { op=fadd, lhs=v23, rhs=v16 } -> d0 + v25 FpCast { kind=F32ToF64, value=v17 } -> d1 + v26 Binop { op=fadd, lhs=v24, rhs=v25 } -> d0 + v27 Binop { op=fadd, lhs=v26, rhs=v18 } -> d0 + v28 Imm(4621819117588971520) -> x0 + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v34 Imm(3) -> x0 - terminator Return(v34) (exit_acc=v34) + v30 Imm(3) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v35 Imm(4617315517961601024) -> x0 - v36 Imm(4618441417868443648) -> x1 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 Imm(0) -> x1 - v39 Imm(0) -> x1 - v40 Imm(4621819117588971520) -> x1 - v41 Binop { op=fmul, lhs=v35, rhs=v40 } -> d1 - v42 FpCast { kind=F32ToF64, value=v37 } -> d0 - v43 Fma { a=v35, b=v40, c=v42, neg_product=false, neg_addend=false } -> d0 - v44 Imm(4633078116657397760) -> x0 - v45 Binop { op=fne, lhs=v43, rhs=v44 } -> x0 - terminator Bz { cond=v45, target=b8, fall=b7 } (exit_acc=v45) + v31 Imm(4617315517961601024) -> x0 + v32 Imm(1086324736) -> x1 [f32] + v33 Imm(0) -> x2 + v34 Imm(0) -> x2 + v35 Imm(4621819117588971520) -> x2 + v36 Binop { op=fmul, lhs=v31, rhs=v35 } -> d0 + v37 FpCast { kind=F32ToF64, value=v32 } -> d0 + v38 Fma { a=v31, b=v35, c=v37, neg_product=false, neg_addend=false } -> d0 + v39 Imm(4633078116657397760) -> x0 + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b8, fall=b7 } (exit_acc=v40) block 7 start_pc=0 - v46 Imm(4) -> x0 - terminator Return(v46) (exit_acc=v46) + v41 Imm(4) -> x0 + terminator Return(v41) (exit_acc=v41) block 8 start_pc=0 - v47 Imm(0) -> x0 - terminator Return(v47) (exit_acc=v47) + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_param_ternary.ssa b/tests/snapshots/ssa/fp_param_ternary.ssa index c239b7da6..6d42475a5 100644 --- a/tests/snapshots/ssa/fp_param_ternary.ssa +++ b/tests/snapshots/ssa/fp_param_ternary.ssa @@ -79,97 +79,80 @@ fn ent_pc=3 n_params=0 variadic=false locals=3 block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x7 - v2 Imm(4617315517961601024) -> x3 - v3 FpCast { kind=F64ToF32, value=v2 } -> d0 [f32] - v4 Call { target_pc=1, args=[v1, v3], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v5 Fneg(v2) -> d1 - v6 FpCast { kind=F32ToF64, value=v4 } -> d0 - v7 Binop { op=fne, lhs=v6, rhs=v5 } -> x0 - terminator Bz { cond=v7, target=b2, fall=b1 } (exit_acc=v7) + v2 Imm(1084227584) -> x3 [f32] + v3 Call { target_pc=1, args=[v1, v2], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v4 Fneg(v2) -> d1 [f32] + v5 Binop { op=fne, lhs=v3, rhs=v4 } -> x0 + terminator Bz { cond=v5, target=b2, fall=b1 } (exit_acc=v5) block 1 start_pc=0 - v8 Imm(1) -> x0 - terminator Return(v8) (exit_acc=v8) + v6 Imm(1) -> x0 + terminator Return(v6) (exit_acc=v6) block 2 start_pc=0 - v9 Imm(1) -> x7 - v10 Imm(4617315517961601024) -> x3 - v11 FpCast { kind=F64ToF32, value=v10 } -> d0 [f32] - v12 Call { target_pc=1, args=[v9, v11], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v13 FpCast { kind=F32ToF64, value=v12 } -> d0 - v14 Binop { op=fne, lhs=v13, rhs=v10 } -> x0 - terminator Bz { cond=v14, target=b4, fall=b3 } (exit_acc=v14) + v7 Imm(1) -> x7 + v8 Imm(1084227584) -> x3 [f32] + v9 Call { target_pc=1, args=[v7, v8], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v10 Binop { op=fne, lhs=v9, rhs=v8 } -> x0 + terminator Bz { cond=v10, target=b4, fall=b3 } (exit_acc=v10) block 3 start_pc=0 - v15 Imm(2) -> x0 - terminator Return(v15) (exit_acc=v15) + v11 Imm(2) -> x0 + terminator Return(v11) (exit_acc=v11) block 4 start_pc=0 - v16 Imm(2) -> x7 - v17 Imm(4617315517961601024) -> x3 - v18 FpCast { kind=F64ToF32, value=v17 } -> d0 [f32] - v19 Call { target_pc=1, args=[v16, v18], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v20 Fneg(v17) -> d1 - v21 FpCast { kind=F32ToF64, value=v19 } -> d0 - v22 Binop { op=fne, lhs=v21, rhs=v20 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v12 Imm(2) -> x7 + v13 Imm(1084227584) -> x3 [f32] + v14 Call { target_pc=1, args=[v12, v13], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v15 Fneg(v13) -> d1 [f32] + v16 Binop { op=fne, lhs=v14, rhs=v15 } -> x0 + terminator Bz { cond=v16, target=b6, fall=b5 } (exit_acc=v16) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v17 Imm(3) -> x0 + terminator Return(v17) (exit_acc=v17) block 6 start_pc=0 - v24 Imm(3) -> x7 - v25 Imm(4617315517961601024) -> x3 - v26 FpCast { kind=F64ToF32, value=v25 } -> d0 [f32] - v27 Call { target_pc=1, args=[v24, v26], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] - v28 FpCast { kind=F32ToF64, value=v27 } -> d0 - v29 Binop { op=fne, lhs=v28, rhs=v25 } -> x0 - terminator Bz { cond=v29, target=b8, fall=b7 } (exit_acc=v29) + v18 Imm(3) -> x7 + v19 Imm(1084227584) -> x3 [f32] + v20 Call { target_pc=1, args=[v18, v19], fixed_args=2, fp_return=true, fp_arg_mask=0x2 } -> d0 [f32] + v21 Binop { op=fne, lhs=v20, rhs=v19 } -> x0 + terminator Bz { cond=v21, target=b8, fall=b7 } (exit_acc=v21) block 7 start_pc=0 - v30 Imm(4) -> x0 - terminator Return(v30) (exit_acc=v30) + v22 Imm(4) -> x0 + terminator Return(v22) (exit_acc=v22) block 8 start_pc=0 - v31 Imm(1) -> x7 - v32 Imm(4609434218613702656) -> x3 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 Imm(4612811918334230528) -> x12 - v35 FpCast { kind=F64ToF32, value=v34 } -> d1 [f32] - v36 Call { target_pc=2, args=[v31, v33, v35], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v37 Fneg(v34) -> d1 - v38 Binop { op=fadd, lhs=v32, rhs=v37 } -> d1 - v39 FpCast { kind=F32ToF64, value=v36 } -> d0 - v40 Binop { op=fne, lhs=v39, rhs=v38 } -> x0 - terminator Bz { cond=v40, target=b10, fall=b9 } (exit_acc=v40) + v23 Imm(1) -> x7 + v24 Imm(1069547520) -> x3 [f32] + v25 Imm(1075838976) -> x12 [f32] + v26 Call { target_pc=2, args=[v23, v24, v25], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v27 Fneg(v25) -> d1 [f32] + v28 Binop { op=fadd, lhs=v24, rhs=v27 } -> d1 [f32] + v29 Binop { op=fne, lhs=v26, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b10, fall=b9 } (exit_acc=v29) block 9 start_pc=0 - v41 Imm(5) -> x0 - terminator Return(v41) (exit_acc=v41) + v30 Imm(5) -> x0 + terminator Return(v30) (exit_acc=v30) block 10 start_pc=0 - v42 Imm(2) -> x7 - v43 Imm(4619848792751996928) -> x3 - v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] - v45 Imm(4593671619917905920) -> x12 - v46 FpCast { kind=F64ToF32, value=v45 } -> d1 [f32] - v47 Call { target_pc=2, args=[v42, v44, v46], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v48 Fneg(v43) -> d1 - v49 Binop { op=fadd, lhs=v48, rhs=v45 } -> d1 - v50 FpCast { kind=F32ToF64, value=v47 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b12, fall=b11 } (exit_acc=v51) + v31 Imm(2) -> x7 + v32 Imm(1088946176) -> x3 [f32] + v33 Imm(1040187392) -> x12 [f32] + v34 Call { target_pc=2, args=[v31, v32, v33], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v35 Fneg(v32) -> d1 [f32] + v36 Binop { op=fadd, lhs=v35, rhs=v33 } -> d1 [f32] + v37 Binop { op=fne, lhs=v34, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b12, fall=b11 } (exit_acc=v37) block 11 start_pc=0 - v52 Imm(6) -> x0 - terminator Return(v52) (exit_acc=v52) + v38 Imm(6) -> x0 + terminator Return(v38) (exit_acc=v38) block 12 start_pc=0 - v53 Imm(3) -> x7 - v54 Imm(4613937818241073152) -> x3 - v55 FpCast { kind=F64ToF32, value=v54 } -> d0 [f32] - v56 Imm(4616189618054758400) -> x12 - v57 FpCast { kind=F64ToF32, value=v56 } -> d1 [f32] - v58 Call { target_pc=2, args=[v53, v55, v57], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] - v59 Binop { op=fadd, lhs=v54, rhs=v56 } -> d1 - v60 FpCast { kind=F32ToF64, value=v58 } -> d0 - v61 Binop { op=fne, lhs=v60, rhs=v59 } -> x0 - terminator Bz { cond=v61, target=b14, fall=b13 } (exit_acc=v61) + v39 Imm(3) -> x7 + v40 Imm(1077936128) -> x3 [f32] + v41 Imm(1082130432) -> x12 [f32] + v42 Call { target_pc=2, args=[v39, v40, v41], fixed_args=3, fp_return=true, fp_arg_mask=0x6 } -> d0 [f32] + v43 Binop { op=fadd, lhs=v40, rhs=v41 } -> d1 [f32] + v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) block 13 start_pc=0 - v62 Imm(7) -> x0 - terminator Return(v62) (exit_acc=v62) + v45 Imm(7) -> x0 + terminator Return(v45) (exit_acc=v45) block 14 start_pc=0 - v63 Imm(0) -> x0 - terminator Return(v63) (exit_acc=v63) + v46 Imm(0) -> x0 + terminator Return(v46) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_return_value.ssa b/tests/snapshots/ssa/fp_return_value.ssa index 5b8af9f28..0bee6b648 100644 --- a/tests/snapshots/ssa/fp_return_value.ssa +++ b/tests/snapshots/ssa/fp_return_value.ssa @@ -22,11 +22,9 @@ fn ent_pc=1 n_params=1 variadic=false locals=0 v3 LoadLocal { off=2, kind=I32 } -> x0 v4 FpCast { kind=IntToFp, value=v1 } -> d0 v5 FpCast { kind=F64ToF32, value=v4 } -> d0 [f32] - v6 Imm(4616189618054758400) -> x0 - v7 FpCast { kind=F32ToF64, value=v5 } -> d0 - v8 Binop { op=fdiv, lhs=v7, rhs=v6 } -> d0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d0 [f32] - terminator Return(v9) (exit_acc=v9) + v6 Imm(1082130432) -> x0 [f32] + v7 Binop { op=fdiv, lhs=v5, rhs=v6 } -> d0 [f32] + terminator Return(v7) (exit_acc=v7) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=4 @@ -60,60 +58,53 @@ fn ent_pc=2 n_params=0 variadic=false locals=4 v21 Imm(0) -> x1 v22 FpCast { kind=IntToFp, value=v20 } -> d0 v23 FpCast { kind=F64ToF32, value=v22 } -> d0 [f32] - v24 Imm(4616189618054758400) -> x0 - v25 FpCast { kind=F32ToF64, value=v23 } -> d0 - v26 Binop { op=fdiv, lhs=v25, rhs=v24 } -> d0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Imm(5) -> x0 - v29 Extend { value=v28, kind=I32 } -> x0 - v30 Imm(0) -> x1 - v31 FpCast { kind=IntToFp, value=v29 } -> d1 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 Imm(4616189618054758400) -> x0 - v34 FpCast { kind=F32ToF64, value=v32 } -> d1 - v35 Binop { op=fdiv, lhs=v34, rhs=v33 } -> d1 - v36 FpCast { kind=F64ToF32, value=v35 } -> d1 [f32] - v37 Binop { op=fadd, lhs=v27, rhs=v36 } -> d0 [f32] - v38 Imm(0) -> x0 - v39 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v40 Imm(4611686018427387904) -> x0 - v41 FpCast { kind=F32ToF64, value=v37 } -> d0 - v42 Binop { op=fne, lhs=v41, rhs=v40 } -> x0 - terminator Bz { cond=v42, target=b4, fall=b3 } (exit_acc=v42) + v24 Imm(1082130432) -> x0 [f32] + v25 Binop { op=fdiv, lhs=v23, rhs=v24 } -> d0 [f32] + v26 Imm(5) -> x0 + v27 Extend { value=v26, kind=I32 } -> x0 + v28 Imm(0) -> x1 + v29 FpCast { kind=IntToFp, value=v27 } -> d1 + v30 FpCast { kind=F64ToF32, value=v29 } -> d1 [f32] + v31 Imm(1082130432) -> x0 [f32] + v32 Binop { op=fdiv, lhs=v30, rhs=v31 } -> d1 [f32] + v33 Binop { op=fadd, lhs=v25, rhs=v32 } -> d0 [f32] + v34 Imm(0) -> x0 + v35 LoadLocal { off=-2, kind=F32 } -> d1 [f32] + v36 Imm(1073741824) -> x0 [f32] + v37 Binop { op=fne, lhs=v33, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b4, fall=b3 } (exit_acc=v37) block 3 start_pc=0 - v43 Imm(2) -> x0 - terminator Return(v43) (exit_acc=v43) + v38 Imm(2) -> x0 + terminator Return(v38) (exit_acc=v38) block 4 start_pc=0 - v44 Imm(1) -> x0 - v45 Extend { value=v44, kind=I32 } -> x0 - v46 Imm(0) -> x1 - v47 FpCast { kind=IntToFp, value=v45 } -> d0 - v48 Imm(4602678819172646912) -> x0 - v49 Binop { op=fadd, lhs=v47, rhs=v48 } -> d0 - v50 Imm(4611686018427387904) -> x0 - v51 Binop { op=fmul, lhs=v49, rhs=v50 } -> d1 - v52 Imm(6) -> x1 - v53 Extend { value=v52, kind=I32 } -> x1 - v54 Imm(0) -> x2 - v55 FpCast { kind=IntToFp, value=v53 } -> d1 - v56 FpCast { kind=F64ToF32, value=v55 } -> d1 [f32] - v57 Imm(4616189618054758400) -> x1 - v58 FpCast { kind=F32ToF64, value=v56 } -> d1 - v59 Binop { op=fdiv, lhs=v58, rhs=v57 } -> d1 - v60 FpCast { kind=F64ToF32, value=v59 } -> d1 [f32] - v61 FpCast { kind=F32ToF64, value=v60 } -> d1 - v62 Fma { a=v49, b=v50, c=v61, neg_product=false, neg_addend=false } -> d0 - v63 Imm(0) -> x0 - v64 LoadLocal { off=-3, kind=F64 } -> d1 - v65 Imm(4616752568008179712) -> x0 - v66 Binop { op=fne, lhs=v62, rhs=v65 } -> x0 - terminator Bz { cond=v66, target=b6, fall=b5 } (exit_acc=v66) + v39 Imm(1) -> x0 + v40 Extend { value=v39, kind=I32 } -> x0 + v41 Imm(0) -> x1 + v42 FpCast { kind=IntToFp, value=v40 } -> d0 + v43 Imm(4602678819172646912) -> x0 + v44 Binop { op=fadd, lhs=v42, rhs=v43 } -> d0 + v45 Imm(4611686018427387904) -> x0 + v46 Binop { op=fmul, lhs=v44, rhs=v45 } -> d1 + v47 Imm(6) -> x1 + v48 Extend { value=v47, kind=I32 } -> x1 + v49 Imm(0) -> x2 + v50 FpCast { kind=IntToFp, value=v48 } -> d1 + v51 FpCast { kind=F64ToF32, value=v50 } -> d1 [f32] + v52 Imm(1082130432) -> x1 [f32] + v53 Binop { op=fdiv, lhs=v51, rhs=v52 } -> d1 [f32] + v54 FpCast { kind=F32ToF64, value=v53 } -> d1 + v55 Fma { a=v44, b=v45, c=v54, neg_product=false, neg_addend=false } -> d0 + v56 Imm(0) -> x0 + v57 LoadLocal { off=-3, kind=F64 } -> d1 + v58 Imm(4616752568008179712) -> x0 + v59 Binop { op=fne, lhs=v55, rhs=v58 } -> x0 + terminator Bz { cond=v59, target=b6, fall=b5 } (exit_acc=v59) block 5 start_pc=0 - v67 Imm(3) -> x0 - terminator Return(v67) (exit_acc=v67) + v60 Imm(3) -> x0 + terminator Return(v60) (exit_acc=v60) block 6 start_pc=0 - v68 Imm(0) -> x0 - terminator Return(v68) (exit_acc=v68) + v61 Imm(0) -> x0 + terminator Return(v61) (exit_acc=v61) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/fp_unary_intrinsic.ssa b/tests/snapshots/ssa/fp_unary_intrinsic.ssa index 4152438ec..7fdc60de8 100644 --- a/tests/snapshots/ssa/fp_unary_intrinsic.ssa +++ b/tests/snapshots/ssa/fp_unary_intrinsic.ssa @@ -4,179 +4,160 @@ fn ent_pc=13 n_params=0 variadic=false locals=5 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4616189618054758400) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Intrinsic { kind=12, args=[v2] } -> d0 [f32] - v4 Imm(4611686018427387904) -> x0 - v5 FpCast { kind=F32ToF64, value=v3 } -> d0 - v6 Binop { op=fne, lhs=v5, rhs=v4 } -> x0 - terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + v1 Imm(1082130432) -> x0 [f32] + v2 Intrinsic { kind=12, args=[v1] } -> d0 [f32] + v3 Imm(1073741824) -> x0 [f32] + v4 Binop { op=fne, lhs=v2, rhs=v3 } -> x0 + terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) block 1 start_pc=0 - v7 Imm(1) -> x0 - terminator Return(v7) (exit_acc=v7) + v5 Imm(1) -> x0 + terminator Return(v5) (exit_acc=v5) block 2 start_pc=0 - v8 Imm(4598175219545276416) -> x0 - v9 FpCast { kind=F64ToF32, value=v8 } -> d0 [f32] - v10 Intrinsic { kind=12, args=[v9] } -> d0 [f32] - v11 Imm(4602678819172646912) -> x0 - v12 FpCast { kind=F32ToF64, value=v10 } -> d0 - v13 Binop { op=fne, lhs=v12, rhs=v11 } -> x0 - terminator Bz { cond=v13, target=b4, fall=b3 } (exit_acc=v13) + v6 Imm(1048576000) -> x0 [f32] + v7 Intrinsic { kind=12, args=[v6] } -> d0 [f32] + v8 Imm(1056964608) -> x0 [f32] + v9 Binop { op=fne, lhs=v7, rhs=v8 } -> x0 + terminator Bz { cond=v9, target=b4, fall=b3 } (exit_acc=v9) block 3 start_pc=0 - v14 Imm(2) -> x0 - terminator Return(v14) (exit_acc=v14) + v10 Imm(2) -> x0 + terminator Return(v10) (exit_acc=v10) block 4 start_pc=0 - v15 Imm(4621256167635550208) -> x0 - v16 Intrinsic { kind=11, args=[v15] } -> d0 - v17 Imm(4613937818241073152) -> x0 - v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 - terminator Bz { cond=v18, target=b6, fall=b5 } (exit_acc=v18) + v11 Imm(4621256167635550208) -> x0 + v12 Intrinsic { kind=11, args=[v11] } -> d0 + v13 Imm(4613937818241073152) -> x0 + v14 Binop { op=fne, lhs=v12, rhs=v13 } -> x0 + terminator Bz { cond=v14, target=b6, fall=b5 } (exit_acc=v14) block 5 start_pc=0 - v19 Imm(3) -> x0 - terminator Return(v19) (exit_acc=v19) + v15 Imm(3) -> x0 + terminator Return(v15) (exit_acc=v15) block 6 start_pc=0 - v20 Imm(4615063718147915776) -> x0 - v21 Fneg(v20) -> d0 - v22 FpCast { kind=F64ToF32, value=v21 } -> d0 [f32] - v23 Intrinsic { kind=14, args=[v22] } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v23 } -> d0 - v25 Binop { op=fne, lhs=v24, rhs=v20 } -> x0 - terminator Bz { cond=v25, target=b8, fall=b7 } (exit_acc=v25) + v16 Imm(1080033280) -> x0 [f32] + v17 Fneg(v16) -> d0 [f32] + v18 Intrinsic { kind=14, args=[v17] } -> d0 [f32] + v19 Binop { op=fne, lhs=v18, rhs=v16 } -> x0 + terminator Bz { cond=v19, target=b8, fall=b7 } (exit_acc=v19) block 7 start_pc=0 - v26 Imm(4) -> x0 - terminator Return(v26) (exit_acc=v26) + v20 Imm(4) -> x0 + terminator Return(v20) (exit_acc=v20) block 8 start_pc=0 - v27 Imm(4615063718147915776) -> x0 - v28 Fneg(v27) -> d0 - v29 Intrinsic { kind=13, args=[v28] } -> d0 - v30 Binop { op=fne, lhs=v29, rhs=v27 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v21 Imm(4615063718147915776) -> x0 + v22 Fneg(v21) -> d0 + v23 Intrinsic { kind=13, args=[v22] } -> d0 + v24 Binop { op=fne, lhs=v23, rhs=v21 } -> x0 + terminator Bz { cond=v24, target=b10, fall=b9 } (exit_acc=v24) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v25 Imm(5) -> x0 + terminator Return(v25) (exit_acc=v25) block 10 start_pc=0 - v32 Imm(4625196817309499392) -> x0 - v33 FpCast { kind=F64ToF32, value=v32 } -> d0 [f32] - v34 Intrinsic { kind=12, args=[v33] } -> d0 [f32] - v35 FpCast { kind=F32ToF64, value=v34 } -> d0 - v36 Imm(0) -> x0 - v37 LoadLocal { off=-1, kind=F64 } -> d1 - v38 Imm(4616189618054758400) -> x0 - v39 Binop { op=fne, lhs=v35, rhs=v38 } -> x0 - terminator Bz { cond=v39, target=b12, fall=b11 } (exit_acc=v39) + v26 Imm(1098907648) -> x0 [f32] + v27 Intrinsic { kind=12, args=[v26] } -> d0 [f32] + v28 FpCast { kind=F32ToF64, value=v27 } -> d0 + v29 Imm(0) -> x0 + v30 LoadLocal { off=-1, kind=F64 } -> d1 + v31 Imm(4616189618054758400) -> x0 + v32 Binop { op=fne, lhs=v28, rhs=v31 } -> x0 + terminator Bz { cond=v32, target=b12, fall=b11 } (exit_acc=v32) block 11 start_pc=0 - v40 Imm(6) -> x0 - terminator Return(v40) (exit_acc=v40) + v33 Imm(6) -> x0 + terminator Return(v33) (exit_acc=v33) block 12 start_pc=0 - v41 Imm(4613262278296967578) -> x0 - v42 Intrinsic { kind=15, args=[v41] } -> d0 - v43 Imm(4611686018427387904) -> x0 - v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x1 - v45 Imm(0) -> x0 - terminator Bnz { cond=v44, target=b29, fall=b13 } (exit_acc=v44) + v34 Imm(4613262278296967578) -> x0 + v35 Intrinsic { kind=15, args=[v34] } -> d0 + v36 Imm(4611686018427387904) -> x0 + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x1 + v38 Imm(0) -> x0 + terminator Bnz { cond=v37, target=b29, fall=b13 } (exit_acc=v37) block 13 start_pc=0 - v46 Imm(4612361558371493478) -> x0 - v47 Fneg(v46) -> d0 - v48 FpCast { kind=F64ToF32, value=v47 } -> d0 [f32] - v49 Intrinsic { kind=16, args=[v48] } -> d0 [f32] - v50 Imm(4613937818241073152) -> x0 - v51 Fneg(v50) -> d1 - v52 FpCast { kind=F32ToF64, value=v49 } -> d0 - v53 Binop { op=fne, lhs=v52, rhs=v51 } -> x1 - v54 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v53) + v39 Imm(1075000115) -> x0 [f32] + v40 Fneg(v39) -> d0 [f32] + v41 Intrinsic { kind=16, args=[v40] } -> d0 [f32] + v42 Imm(1077936128) -> x0 [f32] + v43 Fneg(v42) -> d1 [f32] + v44 Binop { op=fne, lhs=v41, rhs=v43 } -> x1 + v45 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v44) block 14 start_pc=0 - v55 Phi { incoming=[b29:v44, b13:v53], kind=I64 } -> x1 - v56 LoadLocal { off=-3, kind=I64 } -> x0 - terminator Bz { cond=v55, target=b16, fall=b15 } (exit_acc=v55) + v46 Phi { incoming=[b29:v37, b13:v44], kind=I64 } -> x1 + v47 LoadLocal { off=-3, kind=I64 } -> x0 + terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) block 15 start_pc=0 - v57 Imm(7) -> x0 - terminator Return(v57) (exit_acc=v57) + v48 Imm(7) -> x0 + terminator Return(v48) (exit_acc=v48) block 16 start_pc=0 - v58 Imm(4612361558371493478) -> x0 - v59 Intrinsic { kind=17, args=[v58] } -> d0 - v60 Imm(4613937818241073152) -> x0 - v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x1 - v62 Imm(0) -> x0 - terminator Bnz { cond=v61, target=b30, fall=b17 } (exit_acc=v61) + v49 Imm(4612361558371493478) -> x0 + v50 Intrinsic { kind=17, args=[v49] } -> d0 + v51 Imm(4613937818241073152) -> x0 + v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x1 + v53 Imm(0) -> x0 + terminator Bnz { cond=v52, target=b30, fall=b17 } (exit_acc=v52) block 17 start_pc=0 - v63 Imm(4613262278296967578) -> x0 - v64 Fneg(v63) -> d0 - v65 FpCast { kind=F64ToF32, value=v64 } -> d0 [f32] - v66 Intrinsic { kind=18, args=[v65] } -> d0 [f32] - v67 Imm(4611686018427387904) -> x0 - v68 Fneg(v67) -> d1 - v69 FpCast { kind=F32ToF64, value=v66 } -> d0 - v70 Binop { op=fne, lhs=v69, rhs=v68 } -> x1 - v71 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v70) + v54 Imm(1076677837) -> x0 [f32] + v55 Fneg(v54) -> d0 [f32] + v56 Intrinsic { kind=18, args=[v55] } -> d0 [f32] + v57 Imm(1073741824) -> x0 [f32] + v58 Fneg(v57) -> d1 [f32] + v59 Binop { op=fne, lhs=v56, rhs=v58 } -> x1 + v60 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v59) block 18 start_pc=0 - v72 Phi { incoming=[b30:v61, b17:v70], kind=I64 } -> x1 - v73 LoadLocal { off=-4, kind=I64 } -> x0 - terminator Bz { cond=v72, target=b20, fall=b19 } (exit_acc=v72) + v61 Phi { incoming=[b30:v52, b17:v59], kind=I64 } -> x1 + v62 LoadLocal { off=-4, kind=I64 } -> x0 + terminator Bz { cond=v61, target=b20, fall=b19 } (exit_acc=v61) block 19 start_pc=0 - v74 Imm(8) -> x0 - terminator Return(v74) (exit_acc=v74) + v63 Imm(8) -> x0 + terminator Return(v63) (exit_acc=v63) block 20 start_pc=0 - v75 Imm(4613262278296967578) -> x0 - v76 Fneg(v75) -> d0 - v77 Intrinsic { kind=19, args=[v76] } -> d0 - v78 Imm(4611686018427387904) -> x0 - v79 Fneg(v78) -> d1 - v80 Binop { op=fne, lhs=v77, rhs=v79 } -> x1 - v81 Imm(0) -> x0 - terminator Bnz { cond=v80, target=b31, fall=b21 } (exit_acc=v80) + v64 Imm(4613262278296967578) -> x0 + v65 Fneg(v64) -> d0 + v66 Intrinsic { kind=19, args=[v65] } -> d0 + v67 Imm(4611686018427387904) -> x0 + v68 Fneg(v67) -> d1 + v69 Binop { op=fne, lhs=v66, rhs=v68 } -> x1 + v70 Imm(0) -> x0 + terminator Bnz { cond=v69, target=b31, fall=b21 } (exit_acc=v69) block 21 start_pc=0 - v82 Imm(4613712638259704627) -> x0 - v83 FpCast { kind=F64ToF32, value=v82 } -> d0 [f32] - v84 Intrinsic { kind=20, args=[v83] } -> d0 [f32] - v85 Imm(4611686018427387904) -> x0 - v86 FpCast { kind=F32ToF64, value=v84 } -> d0 - v87 Binop { op=fne, lhs=v86, rhs=v85 } -> x1 - v88 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v87) + v71 Imm(1077516698) -> x0 [f32] + v72 Intrinsic { kind=20, args=[v71] } -> d0 [f32] + v73 Imm(1073741824) -> x0 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x1 + v75 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v74) block 22 start_pc=0 - v89 Phi { incoming=[b31:v80, b21:v87], kind=I64 } -> x1 - v90 LoadLocal { off=-5, kind=I64 } -> x0 - terminator Bz { cond=v89, target=b24, fall=b23 } (exit_acc=v89) + v76 Phi { incoming=[b31:v69, b21:v74], kind=I64 } -> x1 + v77 LoadLocal { off=-5, kind=I64 } -> x0 + terminator Bz { cond=v76, target=b24, fall=b23 } (exit_acc=v76) block 23 start_pc=0 - v91 Imm(9) -> x0 - terminator Return(v91) (exit_acc=v91) + v78 Imm(9) -> x0 + terminator Return(v78) (exit_acc=v78) block 24 start_pc=0 - v92 Imm(4611686018427387904) -> x0 - v93 FpCast { kind=F64ToF32, value=v92 } -> d0 [f32] - v94 Imm(0) -> x0 - v95 Imm(4625196817309499392) -> x0 - v96 Fneg(v95) -> d1 - v97 FpCast { kind=F64ToF32, value=v96 } -> d1 [f32] - v98 Intrinsic { kind=14, args=[v97] } -> d1 [f32] - v99 Intrinsic { kind=12, args=[v98] } -> d1 [f32] - v100 Imm(4616189618054758400) -> x0 - v101 FpCast { kind=F32ToF64, value=v99 } -> d1 - v102 Binop { op=fne, lhs=v101, rhs=v100 } -> x0 - terminator Bz { cond=v102, target=b26, fall=b25 } (exit_acc=v102) + v79 Imm(1073741824) -> x0 [f32] + v80 StoreLocal { off=-2, value=v79, kind=F32 } -> - + v81 Imm(1098907648) -> x0 [f32] + v82 Fneg(v81) -> d0 [f32] + v83 Intrinsic { kind=14, args=[v82] } -> d0 [f32] + v84 Intrinsic { kind=12, args=[v83] } -> d0 [f32] + v85 Imm(1082130432) -> x0 [f32] + v86 Binop { op=fne, lhs=v84, rhs=v85 } -> x0 + terminator Bz { cond=v86, target=b26, fall=b25 } (exit_acc=v86) block 25 start_pc=0 - v103 Imm(10) -> x0 - terminator Return(v103) (exit_acc=v103) + v87 Imm(10) -> x0 + terminator Return(v87) (exit_acc=v87) block 26 start_pc=0 - v104 LoadLocal { off=-2, kind=F32 } -> d1 [f32] - v105 Binop { op=fmul, lhs=v93, rhs=v93 } -> d0 [f32] - v106 Intrinsic { kind=12, args=[v105] } -> d0 [f32] - v107 Imm(4606281698874543309) -> x0 - v108 FpCast { kind=F32ToF64, value=v106 } -> d0 - v109 Binop { op=fadd, lhs=v108, rhs=v107 } -> d0 - v110 FpCast { kind=F64ToF32, value=v109 } -> d0 [f32] - v111 Intrinsic { kind=16, args=[v110] } -> d0 [f32] - v112 Imm(4611686018427387904) -> x0 - v113 FpCast { kind=F32ToF64, value=v111 } -> d0 - v114 Binop { op=fne, lhs=v113, rhs=v112 } -> x0 - terminator Bz { cond=v114, target=b28, fall=b27 } (exit_acc=v114) + v88 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v89 Binop { op=fmul, lhs=v88, rhs=v88 } -> d0 [f32] + v90 Intrinsic { kind=12, args=[v89] } -> d0 [f32] + v91 Imm(1063675494) -> x0 [f32] + v92 Binop { op=fadd, lhs=v90, rhs=v91 } -> d0 [f32] + v93 Intrinsic { kind=16, args=[v92] } -> d0 [f32] + v94 Imm(1073741824) -> x0 [f32] + v95 Binop { op=fne, lhs=v93, rhs=v94 } -> x0 + terminator Bz { cond=v95, target=b28, fall=b27 } (exit_acc=v95) block 27 start_pc=0 - v115 Imm(11) -> x0 - terminator Return(v115) (exit_acc=v115) + v96 Imm(11) -> x0 + terminator Return(v96) (exit_acc=v96) block 28 start_pc=0 - v116 Imm(0) -> x0 - terminator Return(v116) (exit_acc=v116) + v97 Imm(0) -> x0 + terminator Return(v97) (exit_acc=v97) block 29 start_pc=0 terminator Jmp(b14) block 30 start_pc=0 diff --git a/tests/snapshots/ssa/hex_float_literal.ssa b/tests/snapshots/ssa/hex_float_literal.ssa index 86d20e9a1..8b5445b1f 100644 --- a/tests/snapshots/ssa/hex_float_literal.ssa +++ b/tests/snapshots/ssa/hex_float_literal.ssa @@ -53,39 +53,41 @@ fn ent_pc=0 n_params=0 variadic=false locals=1 v21 Imm(7) -> x0 terminator Return(v21) (exit_acc=v21) block 14 start_pc=0 - v22 Imm(4607182418800017408) -> x0 - v23 Binop { op=fne, lhs=v22, rhs=v22 } -> x0 - terminator Bz { cond=v23, target=b16, fall=b15 } (exit_acc=v23) + v22 Imm(1065353216) -> x0 [f32] + v23 Imm(4607182418800017408) -> x1 + v24 FpCast { kind=F32ToF64, value=v22 } -> d0 + v25 Binop { op=fne, lhs=v24, rhs=v23 } -> x0 + terminator Bz { cond=v25, target=b16, fall=b15 } (exit_acc=v25) block 15 start_pc=0 - v24 Imm(8) -> x0 - terminator Return(v24) (exit_acc=v24) + v26 Imm(8) -> x0 + terminator Return(v26) (exit_acc=v26) block 16 start_pc=0 - v25 Imm(4614254477589872640) -> x0 - v26 Binop { op=fne, lhs=v25, rhs=v25 } -> x0 - terminator Bz { cond=v26, target=b18, fall=b17 } (exit_acc=v26) + v27 Imm(4614254477589872640) -> x0 + v28 Binop { op=fne, lhs=v27, rhs=v27 } -> x0 + terminator Bz { cond=v28, target=b18, fall=b17 } (exit_acc=v28) block 17 start_pc=0 - v27 Imm(9) -> x0 - terminator Return(v27) (exit_acc=v27) + v29 Imm(9) -> x0 + terminator Return(v29) (exit_acc=v29) block 18 start_pc=0 - v28 Imm(4602678819172646912) -> x0 - v29 Fneg(v28) -> d0 - v30 Binop { op=fne, lhs=v29, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b20, fall=b19 } (exit_acc=v30) + v30 Imm(4602678819172646912) -> x0 + v31 Fneg(v30) -> d0 + v32 Binop { op=fne, lhs=v31, rhs=v31 } -> x0 + terminator Bz { cond=v32, target=b20, fall=b19 } (exit_acc=v32) block 19 start_pc=0 - v31 Imm(10) -> x0 - terminator Return(v31) (exit_acc=v31) + v33 Imm(10) -> x0 + terminator Return(v33) (exit_acc=v33) block 20 start_pc=0 - v32 Imm(4621819117588971520) -> x0 - v33 StoreLocal { off=-1, value=v32, kind=F64 } -> - - v34 LoadLocal { off=-1, kind=F64 } -> d0 - v35 Binop { op=fne, lhs=v34, rhs=v32 } -> x0 - terminator Bz { cond=v35, target=b22, fall=b21 } (exit_acc=v35) + v34 Imm(4621819117588971520) -> x0 + v35 StoreLocal { off=-1, value=v34, kind=F64 } -> - + v36 LoadLocal { off=-1, kind=F64 } -> d0 + v37 Binop { op=fne, lhs=v36, rhs=v34 } -> x0 + terminator Bz { cond=v37, target=b22, fall=b21 } (exit_acc=v37) block 21 start_pc=0 - v36 Imm(11) -> x0 - terminator Return(v36) (exit_acc=v36) + v38 Imm(11) -> x0 + terminator Return(v38) (exit_acc=v38) block 22 start_pc=0 - v37 Imm(0) -> x0 - terminator Return(v37) (exit_acc=v37) + v39 Imm(0) -> x0 + terminator Return(v39) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hfa_param_interleave.ssa b/tests/snapshots/ssa/hfa_param_interleave.ssa index 9df4cfbe4..a04eaf215 100644 --- a/tests/snapshots/ssa/hfa_param_interleave.ssa +++ b/tests/snapshots/ssa/hfa_param_interleave.ssa @@ -84,39 +84,35 @@ fn ent_pc=1 n_params=0 variadic=false locals=12 v17 LocalAddr(-2) -> x6 v18 LocalAddr(-3) -> x2 v19 LocalAddr(-4) -> x1 - v20 Imm(4621537642612260864) -> x0 - v21 FpCast { kind=F64ToF32, value=v20 } -> d0 [f32] - v22 LocalAddr(-5) -> x8 - v23 Call { target_pc=0, args=[v16, v17, v18, v19, v21, v22], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] - v24 Imm(4633007747913220096) -> x0 - v25 FpCast { kind=F32ToF64, value=v23 } -> d0 - v26 Binop { op=fne, lhs=v25, rhs=v24 } -> x0 - terminator Bz { cond=v26, target=b2, fall=b1 } (exit_acc=v26) + v20 Imm(1092091904) -> x8 [f32] + v21 LocalAddr(-5) -> x9 + v22 Call { target_pc=0, args=[v16, v17, v18, v19, v20, v21], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] + v23 Imm(1113456640) -> x0 [f32] + v24 Binop { op=fne, lhs=v22, rhs=v23 } -> x0 + terminator Bz { cond=v24, target=b2, fall=b1 } (exit_acc=v24) block 1 start_pc=0 - v27 Imm(1) -> x0 - terminator Return(v27) (exit_acc=v27) + v25 Imm(1) -> x0 + terminator Return(v25) (exit_acc=v25) block 2 start_pc=0 - v28 LocalAddr(-6) -> x0 - v29 ImmData(44) -> x1 - v30 Mcpy { dst=v28, src=v29, size=8 } -> x0 - v31 LocalAddr(-6) -> x7 - v32 LocalAddr(-6) -> x6 - v33 LocalAddr(-6) -> x2 - v34 LocalAddr(-6) -> x1 - v35 Imm(4598175219545276416) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 LocalAddr(-5) -> x8 - v38 Call { target_pc=0, args=[v31, v32, v33, v34, v36, v37], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] - v39 Imm(4621959855077326848) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b4, fall=b3 } (exit_acc=v41) + v26 LocalAddr(-6) -> x0 + v27 ImmData(44) -> x1 + v28 Mcpy { dst=v26, src=v27, size=8 } -> x0 + v29 LocalAddr(-6) -> x7 + v30 LocalAddr(-6) -> x6 + v31 LocalAddr(-6) -> x2 + v32 LocalAddr(-6) -> x1 + v33 Imm(1048576000) -> x8 [f32] + v34 LocalAddr(-5) -> x9 + v35 Call { target_pc=0, args=[v29, v30, v31, v32, v33, v34], fixed_args=6, fp_return=true, fp_arg_mask=0x10 } -> d0 [f32] + v36 Imm(1092878336) -> x0 [f32] + v37 Binop { op=fne, lhs=v35, rhs=v36 } -> x0 + terminator Bz { cond=v37, target=b4, fall=b3 } (exit_acc=v37) block 3 start_pc=0 - v42 Imm(2) -> x0 - terminator Return(v42) (exit_acc=v42) + v38 Imm(2) -> x0 + terminator Return(v38) (exit_acc=v38) block 4 start_pc=0 - v43 Imm(0) -> x0 - terminator Return(v43) (exit_acc=v43) + v39 Imm(0) -> x0 + terminator Return(v39) (exit_acc=v39) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/hfa_struct_return.ssa b/tests/snapshots/ssa/hfa_struct_return.ssa index 8c8399831..77b4b84a9 100644 --- a/tests/snapshots/ssa/hfa_struct_return.ssa +++ b/tests/snapshots/ssa/hfa_struct_return.ssa @@ -304,70 +304,65 @@ fn ent_pc=8 n_params=0 variadic=false locals=45 v108 Imm(4) -> x0 terminator Return(v108) (exit_acc=v108) block 20 start_pc=0 - v109 Imm(4609434218613702656) -> x3 - v110 FpCast { kind=F64ToF32, value=v109 } -> d0 [f32] - v111 Imm(4612811918334230528) -> x0 - v112 FpCast { kind=F64ToF32, value=v111 } -> d1 [f32] - v113 Call { target_pc=4, args=[v110, v112], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v114 LocalAddr(-44) -> x0 - v115 LocalAddr(-21) -> x1 - v116 Mcpy { dst=v115, src=v114, size=8 } -> x0 - v117 LocalAddr(-21) -> x0 - v118 Load { addr=v117, disp=0, kind=F32 } -> d0 [f32] - v119 FpCast { kind=F32ToF64, value=v118 } -> d0 - v120 Binop { op=fne, lhs=v119, rhs=v109 } -> x3 - v121 Imm(0) -> x0 - terminator Bnz { cond=v120, target=b37, fall=b21 } (exit_acc=v120) + v109 Imm(1069547520) -> x3 [f32] + v110 Imm(1075838976) -> x6 [f32] + v111 Call { target_pc=4, args=[v109, v110], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v112 LocalAddr(-44) -> x0 + v113 LocalAddr(-21) -> x1 + v114 Mcpy { dst=v113, src=v112, size=8 } -> x0 + v115 LocalAddr(-21) -> x0 + v116 Load { addr=v115, disp=0, kind=F32 } -> d0 [f32] + v117 Binop { op=fne, lhs=v116, rhs=v109 } -> x3 + v118 Imm(0) -> x0 + terminator Bnz { cond=v117, target=b37, fall=b21 } (exit_acc=v117) block 21 start_pc=0 - v122 LocalAddr(-21) -> x0 - v123 BinopI { op=add, lhs=v122, rhs_imm=4 } -> x1 - v124 Load { addr=v122, disp=4, kind=F32 } -> d0 [f32] - v125 Imm(4612811918334230528) -> x0 - v126 FpCast { kind=F32ToF64, value=v124 } -> d0 - v127 Binop { op=fne, lhs=v126, rhs=v125 } -> x3 - v128 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v127) + v119 LocalAddr(-21) -> x0 + v120 BinopI { op=add, lhs=v119, rhs_imm=4 } -> x1 + v121 Load { addr=v119, disp=4, kind=F32 } -> d0 [f32] + v122 Imm(1075838976) -> x0 [f32] + v123 Binop { op=fne, lhs=v121, rhs=v122 } -> x3 + v124 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v123) block 22 start_pc=0 - v129 Phi { incoming=[b37:v120, b21:v127], kind=I64 } -> x3 - v130 LoadLocal { off=-45, kind=I64 } -> x0 - terminator Bz { cond=v129, target=b24, fall=b23 } (exit_acc=v129) + v125 Phi { incoming=[b37:v117, b21:v123], kind=I64 } -> x3 + v126 LoadLocal { off=-45, kind=I64 } -> x0 + terminator Bz { cond=v125, target=b24, fall=b23 } (exit_acc=v125) block 23 start_pc=0 - v131 Imm(5) -> x0 - terminator Return(v131) (exit_acc=v131) + v127 Imm(5) -> x0 + terminator Return(v127) (exit_acc=v127) block 24 start_pc=0 - v132 LocalAddr(-24) -> x0 - v133 ImmData(8) -> x1 - v134 Mcpy { dst=v132, src=v133, size=16 } -> x0 - v135 LocalAddr(-4) -> x7 - v136 Call { target_pc=5, args=[v135], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v137 Imm(4604930618986332160) -> x0 - v138 Binop { op=fne, lhs=v136, rhs=v137 } -> x0 - terminator Bz { cond=v138, target=b26, fall=b25 } (exit_acc=v138) + v128 LocalAddr(-24) -> x0 + v129 ImmData(8) -> x1 + v130 Mcpy { dst=v128, src=v129, size=16 } -> x0 + v131 LocalAddr(-4) -> x7 + v132 Call { target_pc=5, args=[v131], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v133 Imm(4604930618986332160) -> x0 + v134 Binop { op=fne, lhs=v132, rhs=v133 } -> x0 + terminator Bz { cond=v134, target=b26, fall=b25 } (exit_acc=v134) block 25 start_pc=0 - v139 Imm(6) -> x0 - terminator Return(v139) (exit_acc=v139) + v135 Imm(6) -> x0 + terminator Return(v135) (exit_acc=v135) block 26 start_pc=0 - v140 LocalAddr(-16) -> x7 - v141 Call { target_pc=6, args=[v140], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 - v142 Imm(4636737291354636288) -> x0 - v143 Binop { op=fne, lhs=v141, rhs=v142 } -> x0 - terminator Bz { cond=v143, target=b28, fall=b27 } (exit_acc=v143) + v136 LocalAddr(-16) -> x7 + v137 Call { target_pc=6, args=[v136], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 + v138 Imm(4636737291354636288) -> x0 + v139 Binop { op=fne, lhs=v137, rhs=v138 } -> x0 + terminator Bz { cond=v139, target=b28, fall=b27 } (exit_acc=v139) block 27 start_pc=0 - v144 Imm(7) -> x0 - terminator Return(v144) (exit_acc=v144) + v140 Imm(7) -> x0 + terminator Return(v140) (exit_acc=v140) block 28 start_pc=0 - v145 LocalAddr(-24) -> x7 - v146 Call { target_pc=7, args=[v145], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] - v147 Imm(4621819117588971520) -> x0 - v148 FpCast { kind=F32ToF64, value=v146 } -> d0 - v149 Binop { op=fne, lhs=v148, rhs=v147 } -> x0 - terminator Bz { cond=v149, target=b30, fall=b29 } (exit_acc=v149) + v141 LocalAddr(-24) -> x7 + v142 Call { target_pc=7, args=[v141], fixed_args=1, fp_return=true, fp_arg_mask=0x0 } -> d0 [f32] + v143 Imm(1092616192) -> x0 [f32] + v144 Binop { op=fne, lhs=v142, rhs=v143 } -> x0 + terminator Bz { cond=v144, target=b30, fall=b29 } (exit_acc=v144) block 29 start_pc=0 - v150 Imm(8) -> x0 - terminator Return(v150) (exit_acc=v150) + v145 Imm(8) -> x0 + terminator Return(v145) (exit_acc=v145) block 30 start_pc=0 - v151 Imm(0) -> x0 - terminator Return(v151) (exit_acc=v151) + v146 Imm(0) -> x0 + terminator Return(v146) (exit_acc=v146) block 31 start_pc=0 terminator Jmp(b4) block 32 start_pc=0 diff --git a/tests/snapshots/ssa/init_scalar_conversion.ssa b/tests/snapshots/ssa/init_scalar_conversion.ssa index ddf079a52..8a8352d2a 100644 --- a/tests/snapshots/ssa/init_scalar_conversion.ssa +++ b/tests/snapshots/ssa/init_scalar_conversion.ssa @@ -217,79 +217,77 @@ fn ent_pc=1 n_params=0 variadic=false locals=24 v119 Imm(4) -> x0 terminator Return(v119) (exit_acc=v119) block 16 start_pc=0 - v120 Imm(0) -> x0 - v121 FpCast { kind=F64ToF32, value=v120 } -> d0 [f32] - v122 Imm(0) -> x1 - v123 LocalAddr(-14) -> x1 - v124 ImmData(80) -> x2 - v125 Mcpy { dst=v123, src=v124, size=4 } -> x1 - v126 LoadLocal { off=-11, kind=F64 } -> d0 - v127 Binop { op=fadd, lhs=v126, rhs=v120 } -> d0 + v120 Imm(0) -> x0 [f32] + v121 StoreLocal { off=-13, value=v120, kind=F32 } -> - + v122 LocalAddr(-14) -> x0 + v123 ImmData(80) -> x1 + v124 Mcpy { dst=v122, src=v123, size=4 } -> x0 + v125 LoadLocal { off=-11, kind=F64 } -> d0 + v126 Imm(0) -> x0 + v127 Binop { op=fadd, lhs=v125, rhs=v126 } -> d0 v128 FpCast { kind=F64ToF32, value=v127 } -> d0 [f32] v129 LocalAddr(-14) -> x0 v130 Store { addr=v129, disp=0, value=v128, kind=F32 } -> - v131 LocalAddr(-14) -> x0 v132 Load { addr=v131, disp=0, kind=F32 } -> d0 [f32] - v133 Imm(0) -> x0 - v134 LoadLocal { off=-13, kind=F32 } -> d1 [f32] - v135 Imm(4615941920075253023) -> x0 - v136 FpCast { kind=F32ToF64, value=v132 } -> d1 - v137 Binop { op=flt, lhs=v136, rhs=v135 } -> x13 - v138 Imm(0) -> x0 - terminator Bnz { cond=v137, target=b29, fall=b17 } (exit_acc=v137) + v133 StoreLocal { off=-13, value=v132, kind=F32 } -> - + v134 LoadLocal { off=-13, kind=F32 } -> d0 [f32] + v135 Imm(1081669059) -> x0 [f32] + v136 Binop { op=flt, lhs=v134, rhs=v135 } -> x13 + v137 Imm(0) -> x0 + terminator Bnz { cond=v136, target=b29, fall=b17 } (exit_acc=v136) block 17 start_pc=0 - v139 LoadLocal { off=-13, kind=F32 } -> d1 [f32] - v140 Imm(4615986956071526728) -> x0 - v141 FpCast { kind=F32ToF64, value=v132 } -> d0 - v142 Binop { op=fgt, lhs=v141, rhs=v140 } -> x13 - v143 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v142) + v138 LoadLocal { off=-13, kind=F32 } -> d0 [f32] + v139 Imm(1081752945) -> x0 [f32] + v140 Binop { op=fgt, lhs=v138, rhs=v139 } -> x13 + v141 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v140) block 18 start_pc=0 - v144 Phi { incoming=[b29:v137, b17:v142], kind=I64 } -> x13 - v145 LoadLocal { off=-24, kind=I64 } -> x0 - terminator Bz { cond=v144, target=b20, fall=b19 } (exit_acc=v144) + v142 Phi { incoming=[b29:v136, b17:v140], kind=I64 } -> x13 + v143 LoadLocal { off=-24, kind=I64 } -> x0 + terminator Bz { cond=v142, target=b20, fall=b19 } (exit_acc=v142) block 19 start_pc=0 - v146 Imm(5) -> x0 - terminator Return(v146) (exit_acc=v146) + v144 Imm(5) -> x0 + terminator Return(v144) (exit_acc=v144) block 20 start_pc=0 - v147 LocalAddr(-8) -> x7 - v148 Call { target_pc=0, args=[v147], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v149 BinopI { op=eq, lhs=v148, rhs_imm=0 } -> x0 - terminator Bz { cond=v149, target=b22, fall=b21 } (exit_acc=v149) + v145 LocalAddr(-8) -> x7 + v146 Call { target_pc=0, args=[v145], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v147 BinopI { op=eq, lhs=v146, rhs_imm=0 } -> x0 + terminator Bz { cond=v147, target=b22, fall=b21 } (exit_acc=v147) block 21 start_pc=0 - v150 Imm(6) -> x0 - terminator Return(v150) (exit_acc=v150) + v148 Imm(6) -> x0 + terminator Return(v148) (exit_acc=v148) block 22 start_pc=0 - v151 LocalAddr(-19) -> x0 - v152 ImmData(84) -> x1 - v153 Mcpy { dst=v151, src=v152, size=32 } -> x0 - v154 Imm(0) -> x0 - v155 FpCast { kind=IntToFp, value=v154 } -> d0 + v149 LocalAddr(-19) -> x0 + v150 ImmData(84) -> x1 + v151 Mcpy { dst=v149, src=v150, size=32 } -> x0 + v152 Imm(0) -> x0 + v153 FpCast { kind=IntToFp, value=v152 } -> d0 + v154 LocalAddr(-19) -> x0 + v155 Store { addr=v154, disp=0, value=v153, kind=F64 } -> - v156 LocalAddr(-19) -> x0 - v157 Store { addr=v156, disp=0, value=v155, kind=F64 } -> - - v158 LocalAddr(-19) -> x0 - v159 BinopI { op=add, lhs=v158, rhs_imm=8 } -> x1 - v160 Store { addr=v158, disp=8, value=v155, kind=F64 } -> - - v161 LoadLocal { off=-1, kind=I32 } -> x0 - v162 FpCast { kind=IntToFp, value=v1 } -> d0 - v163 LocalAddr(-19) -> x0 - v164 BinopI { op=add, lhs=v163, rhs_imm=16 } -> x1 - v165 Store { addr=v163, disp=16, value=v162, kind=F64 } -> - - v166 LoadLocal { off=-2, kind=I32 } -> x0 - v167 FpCast { kind=IntToFp, value=v3 } -> d0 - v168 LocalAddr(-19) -> x0 - v169 BinopI { op=add, lhs=v168, rhs_imm=24 } -> x1 - v170 Store { addr=v168, disp=24, value=v167, kind=F64 } -> - - v171 LocalAddr(-19) -> x7 - v172 Call { target_pc=0, args=[v171], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 - v173 BinopI { op=eq, lhs=v172, rhs_imm=0 } -> x0 - terminator Bz { cond=v173, target=b24, fall=b23 } (exit_acc=v173) + v157 BinopI { op=add, lhs=v156, rhs_imm=8 } -> x1 + v158 Store { addr=v156, disp=8, value=v153, kind=F64 } -> - + v159 LoadLocal { off=-1, kind=I32 } -> x0 + v160 FpCast { kind=IntToFp, value=v1 } -> d0 + v161 LocalAddr(-19) -> x0 + v162 BinopI { op=add, lhs=v161, rhs_imm=16 } -> x1 + v163 Store { addr=v161, disp=16, value=v160, kind=F64 } -> - + v164 LoadLocal { off=-2, kind=I32 } -> x0 + v165 FpCast { kind=IntToFp, value=v3 } -> d0 + v166 LocalAddr(-19) -> x0 + v167 BinopI { op=add, lhs=v166, rhs_imm=24 } -> x1 + v168 Store { addr=v166, disp=24, value=v165, kind=F64 } -> - + v169 LocalAddr(-19) -> x7 + v170 Call { target_pc=0, args=[v169], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v171 BinopI { op=eq, lhs=v170, rhs_imm=0 } -> x0 + terminator Bz { cond=v171, target=b24, fall=b23 } (exit_acc=v171) block 23 start_pc=0 - v174 Imm(7) -> x0 - terminator Return(v174) (exit_acc=v174) + v172 Imm(7) -> x0 + terminator Return(v172) (exit_acc=v172) block 24 start_pc=0 - v175 Imm(0) -> x0 - terminator Return(v175) (exit_acc=v175) + v173 Imm(0) -> x0 + terminator Return(v173) (exit_acc=v173) block 25 start_pc=0 terminator Jmp(b2) block 26 start_pc=0 diff --git a/tests/snapshots/ssa/int_to_float_assign_conversion.ssa b/tests/snapshots/ssa/int_to_float_assign_conversion.ssa index 4dda0dff3..c7fe19224 100644 --- a/tests/snapshots/ssa/int_to_float_assign_conversion.ssa +++ b/tests/snapshots/ssa/int_to_float_assign_conversion.ssa @@ -93,66 +93,59 @@ fn ent_pc=1 n_params=0 variadic=false locals=10 v73 Imm(4) -> x0 terminator Return(v73) (exit_acc=v73) block 8 start_pc=0 - v74 Imm(4599057925072241033) -> x0 + v74 Imm(1050220167) -> x0 [f32] v75 LoadLocal { off=-2, kind=F32 } -> d3 [f32] - v76 FpCast { kind=F32ToF64, value=v18 } -> d0 - v77 Binop { op=fmul, lhs=v74, rhs=v76 } -> d3 - v78 Imm(4603462445507809378) -> x1 - v79 LoadLocal { off=-3, kind=F32 } -> d3 [f32] - v80 FpCast { kind=F32ToF64, value=v24 } -> d1 - v81 Binop { op=fmul, lhs=v78, rhs=v80 } -> d1 - v82 Fma { a=v74, b=v76, c=v81, neg_product=false, neg_addend=false } -> d0 - v83 Imm(4592878986383488713) -> x0 - v84 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v85 FpCast { kind=F32ToF64, value=v30 } -> d1 - v86 Binop { op=fmul, lhs=v83, rhs=v85 } -> d2 - v87 Fma { a=v83, b=v85, c=v82, neg_product=false, neg_addend=false } -> d0 - v88 Imm(4638707616191610880) -> x0 - v89 Binop { op=fsub, lhs=v87, rhs=v88 } -> d0 - v90 FpCast { kind=F64ToF32, value=v89 } -> d0 [f32] - v91 Imm(0) -> x0 - v92 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v93 Imm(4631248529308778496) -> x0 - v94 Fneg(v93) -> d1 - v95 FpCast { kind=F32ToF64, value=v90 } -> d2 - v96 Binop { op=fgt, lhs=v95, rhs=v94 } -> x3 - v97 Imm(0) -> x0 - terminator Bnz { cond=v96, target=b15, fall=b9 } (exit_acc=v96) + v76 Binop { op=fmul, lhs=v74, rhs=v18 } -> d3 [f32] + v77 Imm(1058424226) -> x1 [f32] + v78 LoadLocal { off=-3, kind=F32 } -> d3 [f32] + v79 Binop { op=fmul, lhs=v77, rhs=v24 } -> d1 [f32] + v80 Fma { a=v74, b=v18, c=v79, neg_product=false, neg_addend=false } -> d0 [f32] + v81 Imm(1038710997) -> x0 [f32] + v82 LoadLocal { off=-4, kind=F32 } -> d1 [f32] + v83 Binop { op=fmul, lhs=v81, rhs=v30 } -> d1 [f32] + v84 Fma { a=v81, b=v30, c=v80, neg_product=false, neg_addend=false } -> d0 [f32] + v85 Imm(1124073472) -> x0 [f32] + v86 Binop { op=fsub, lhs=v84, rhs=v85 } -> d0 [f32] + v87 Imm(0) -> x0 + v88 LoadLocal { off=-6, kind=F32 } -> d1 [f32] + v89 Imm(1110179840) -> x0 [f32] + v90 Fneg(v89) -> d1 [f32] + v91 Binop { op=fgt, lhs=v86, rhs=v90 } -> x3 + v92 Imm(0) -> x0 + terminator Bnz { cond=v91, target=b15, fall=b9 } (exit_acc=v91) block 9 start_pc=0 - v98 LoadLocal { off=-6, kind=F32 } -> d1 [f32] - v99 Imm(4631389266797133824) -> x0 - v100 Fneg(v99) -> d1 - v101 FpCast { kind=F32ToF64, value=v90 } -> d0 - v102 Binop { op=flt, lhs=v101, rhs=v100 } -> x3 - v103 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v102) + v93 LoadLocal { off=-6, kind=F32 } -> d1 [f32] + v94 Imm(1110441984) -> x0 [f32] + v95 Fneg(v94) -> d1 [f32] + v96 Binop { op=flt, lhs=v86, rhs=v95 } -> x3 + v97 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v96) block 10 start_pc=0 - v104 Phi { incoming=[b15:v96, b9:v102], kind=I64 } -> x3 - v105 LoadLocal { off=-10, kind=I64 } -> x0 - terminator Bz { cond=v104, target=b12, fall=b11 } (exit_acc=v104) + v98 Phi { incoming=[b15:v91, b9:v96], kind=I64 } -> x3 + v99 LoadLocal { off=-10, kind=I64 } -> x0 + terminator Bz { cond=v98, target=b12, fall=b11 } (exit_acc=v98) block 11 start_pc=0 - v106 Imm(5) -> x0 - terminator Return(v106) (exit_acc=v106) + v100 Imm(5) -> x0 + terminator Return(v100) (exit_acc=v100) block 12 start_pc=0 - v107 Imm(7) -> x0 - v108 Imm(0) -> x1 - v109 LoadLocal { off=-7, kind=I32 } -> x1 - v110 FpCast { kind=IntToFp, value=v107 } -> d0 - v111 FpCast { kind=F64ToF32, value=v110 } -> d0 [f32] - v112 Imm(0) -> x0 - v113 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v114 Imm(4619567317775286272) -> x0 - v115 FpCast { kind=F32ToF64, value=v111 } -> d0 - v116 Binop { op=fne, lhs=v115, rhs=v114 } -> x0 - terminator Bz { cond=v116, target=b14, fall=b13 } (exit_acc=v116) + v101 Imm(7) -> x0 + v102 Imm(0) -> x1 + v103 LoadLocal { off=-7, kind=I32 } -> x1 + v104 FpCast { kind=IntToFp, value=v101 } -> d0 + v105 FpCast { kind=F64ToF32, value=v104 } -> d0 [f32] + v106 Imm(0) -> x0 + v107 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v108 Imm(1088421888) -> x0 [f32] + v109 Binop { op=fne, lhs=v105, rhs=v108 } -> x0 + terminator Bz { cond=v109, target=b14, fall=b13 } (exit_acc=v109) block 13 start_pc=0 - v117 Imm(6) -> x0 - terminator Return(v117) (exit_acc=v117) + v110 Imm(6) -> x0 + terminator Return(v110) (exit_acc=v110) block 14 start_pc=0 - v118 ImmData(36) -> x7 - v119 CallExt { binding_idx=0, args=[v118], fp_arg_mask=0x0 } -> x0 - v120 Imm(0) -> x0 - terminator Return(v120) (exit_acc=v120) + v111 ImmData(36) -> x7 + v112 CallExt { binding_idx=0, args=[v111], fp_arg_mask=0x0 } -> x0 + v113 Imm(0) -> x0 + terminator Return(v113) (exit_acc=v113) block 15 start_pc=0 terminator Jmp(b10) ; --- SSA dump (ok=true) ent_pc=0 --- diff --git a/tests/snapshots/ssa/leading_dot_float_literal.ssa b/tests/snapshots/ssa/leading_dot_float_literal.ssa index 9f2d9791c..726cd3e91 100644 --- a/tests/snapshots/ssa/leading_dot_float_literal.ssa +++ b/tests/snapshots/ssa/leading_dot_float_literal.ssa @@ -4,18 +4,18 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4602678819172646912) -> x0 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(0) -> x1 - v4 Imm(4598175219545276416) -> x1 - v5 StoreLocal { off=-2, value=v4, kind=F64 } -> - - v6 Imm(4627730092099895296) -> x1 - v7 StoreLocal { off=-3, value=v6, kind=F64 } -> - - v8 Imm(0) -> x1 - v9 Imm(1) -> x2 - v10 Imm(0) -> x1 - v11 LoadLocal { off=-1, kind=F32 } -> d1 [f32] - v12 FpCast { kind=F32ToF64, value=v2 } -> d1 + v1 Imm(1056964608) -> x0 [f32] + v2 StoreLocal { off=-1, value=v1, kind=F32 } -> - + v3 Imm(4598175219545276416) -> x1 + v4 StoreLocal { off=-2, value=v3, kind=F64 } -> - + v5 Imm(4627730092099895296) -> x1 + v6 StoreLocal { off=-3, value=v5, kind=F64 } -> - + v7 Imm(4602678819172646912) -> x1 + v8 FpCast { kind=F64ToF32, value=v7 } -> d0 [f32] + v9 Imm(0) -> x1 + v10 Imm(1) -> x2 + v11 Imm(0) -> x1 + v12 LoadLocal { off=-1, kind=F32 } -> d1 [f32] v13 Binop { op=fne, lhs=v12, rhs=v1 } -> x0 terminator Bz { cond=v13, target=b12, fall=b1 } (exit_acc=v13) block 1 start_pc=0 @@ -23,7 +23,7 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 v15 Imm(0) -> x0 terminator Jmp(b2) (exit_acc=v14) block 2 start_pc=0 - v16 Phi { incoming=[b12:v9, b1:v14], kind=I64 } -> x2 + v16 Phi { incoming=[b12:v10, b1:v14], kind=I64 } -> x2 v17 LoadLocal { off=-2, kind=F64 } -> d1 v18 Imm(4598175219545276416) -> x0 v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 @@ -45,30 +45,29 @@ fn ent_pc=1 n_params=0 variadic=false locals=6 block 6 start_pc=0 v28 Phi { incoming=[b14:v22, b5:v26], kind=I64 } -> x2 v29 LoadLocal { off=-4, kind=F32 } -> d1 [f32] - v30 Imm(4602678819172646912) -> x0 - v31 FpCast { kind=F32ToF64, value=v2 } -> d0 - v32 Binop { op=fne, lhs=v31, rhs=v30 } -> x0 - terminator Bz { cond=v32, target=b15, fall=b7 } (exit_acc=v32) + v30 Imm(1056964608) -> x0 [f32] + v31 Binop { op=fne, lhs=v8, rhs=v30 } -> x0 + terminator Bz { cond=v31, target=b15, fall=b7 } (exit_acc=v31) block 7 start_pc=0 - v33 Imm(0) -> x2 - v34 Imm(0) -> x0 - terminator Jmp(b8) (exit_acc=v33) + v32 Imm(0) -> x2 + v33 Imm(0) -> x0 + terminator Jmp(b8) (exit_acc=v32) block 8 start_pc=0 - v35 Phi { incoming=[b15:v28, b7:v33], kind=I64 } -> x2 - v36 Extend { value=v35, kind=I32 } -> x0 - terminator Bz { cond=v36, target=b10, fall=b9 } (exit_acc=v36) + v34 Phi { incoming=[b15:v28, b7:v32], kind=I64 } -> x2 + v35 Extend { value=v34, kind=I32 } -> x0 + terminator Bz { cond=v35, target=b10, fall=b9 } (exit_acc=v35) block 9 start_pc=0 - v37 Imm(7) -> x1 - v38 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v37) + v36 Imm(7) -> x1 + v37 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v36) block 10 start_pc=0 - v39 Imm(0) -> x1 - v40 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v39) + v38 Imm(0) -> x1 + v39 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v38) block 11 start_pc=0 - v41 Phi { incoming=[b9:v37, b10:v39], kind=I64 } -> x1 - v42 LoadLocal { off=-6, kind=I64 } -> x0 - terminator Return(v41) (exit_acc=v41) + v40 Phi { incoming=[b9:v36, b10:v38], kind=I64 } -> x1 + v41 LoadLocal { off=-6, kind=I64 } -> x0 + terminator Return(v40) (exit_acc=v40) block 12 start_pc=0 terminator Jmp(b2) block 13 start_pc=0 diff --git a/tests/snapshots/ssa/libc_fp_classify.ssa b/tests/snapshots/ssa/libc_fp_classify.ssa index 72af75b50..79fe9b1c8 100644 --- a/tests/snapshots/ssa/libc_fp_classify.ssa +++ b/tests/snapshots/ssa/libc_fp_classify.ssa @@ -149,90 +149,87 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v13 Imm(2) -> x0 terminator Return(v13) (exit_acc=v13) block 4 start_pc=0 - v14 Imm(4611686018427387904) -> x3 - v15 FpCast { kind=F64ToF32, value=v14 } -> d0 [f32] - v16 Imm(4617315517961601024) -> x0 - v17 Fneg(v16) -> d1 - v18 FpCast { kind=F64ToF32, value=v17 } -> d1 [f32] - v19 Call { target_pc=6, args=[v15, v18], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v20 Fneg(v14) -> d1 - v21 FpCast { kind=F32ToF64, value=v19 } -> d0 - v22 Binop { op=fne, lhs=v21, rhs=v20 } -> x0 - terminator Bz { cond=v22, target=b6, fall=b5 } (exit_acc=v22) + v14 Imm(1073741824) -> x3 [f32] + v15 Imm(1084227584) -> x0 [f32] + v16 Fneg(v15) -> d0 [f32] + v17 Call { target_pc=6, args=[v14, v16], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v18 Fneg(v14) -> d1 [f32] + v19 Binop { op=fne, lhs=v17, rhs=v18 } -> x0 + terminator Bz { cond=v19, target=b6, fall=b5 } (exit_acc=v19) block 5 start_pc=0 - v23 Imm(3) -> x0 - terminator Return(v23) (exit_acc=v23) + v20 Imm(3) -> x0 + terminator Return(v20) (exit_acc=v20) block 6 start_pc=0 - v24 Imm(4607182418800017408) -> x0 - v25 Fneg(v24) -> d0 - v26 Call { target_pc=4, args=[v25], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v27 BinopI { op=eq, lhs=v26, rhs_imm=0 } -> x0 - terminator Bz { cond=v27, target=b8, fall=b7 } (exit_acc=v27) + v21 Imm(4607182418800017408) -> x0 + v22 Fneg(v21) -> d0 + v23 Call { target_pc=4, args=[v22], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v24 BinopI { op=eq, lhs=v23, rhs_imm=0 } -> x0 + terminator Bz { cond=v24, target=b8, fall=b7 } (exit_acc=v24) block 7 start_pc=0 - v28 Imm(4) -> x0 - terminator Return(v28) (exit_acc=v28) + v25 Imm(4) -> x0 + terminator Return(v25) (exit_acc=v25) block 8 start_pc=0 - v29 Imm(4607182418800017408) -> x7 - v30 Call { target_pc=4, args=[v29], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - terminator Bz { cond=v30, target=b10, fall=b9 } (exit_acc=v30) + v26 Imm(4607182418800017408) -> x7 + v27 Call { target_pc=4, args=[v26], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + terminator Bz { cond=v27, target=b10, fall=b9 } (exit_acc=v27) block 9 start_pc=0 - v31 Imm(5) -> x0 - terminator Return(v31) (exit_acc=v31) + v28 Imm(5) -> x0 + terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v32 Imm(0) -> x0 - v33 Fneg(v32) -> d0 - v34 Call { target_pc=4, args=[v33], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v35 BinopI { op=eq, lhs=v34, rhs_imm=0 } -> x0 - terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) + v29 Imm(0) -> x0 + v30 Fneg(v29) -> d0 + v31 Call { target_pc=4, args=[v30], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v32 BinopI { op=eq, lhs=v31, rhs_imm=0 } -> x0 + terminator Bz { cond=v32, target=b12, fall=b11 } (exit_acc=v32) block 11 start_pc=0 - v36 Imm(6) -> x0 - terminator Return(v36) (exit_acc=v36) + v33 Imm(6) -> x0 + terminator Return(v33) (exit_acc=v33) block 12 start_pc=0 - v37 Imm(0) -> x7 - v38 Call { target_pc=0, args=[v37], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v39 BinopI { op=ne, lhs=v38, rhs_imm=2 } -> x0 - terminator Bz { cond=v39, target=b14, fall=b13 } (exit_acc=v39) + v34 Imm(0) -> x7 + v35 Call { target_pc=0, args=[v34], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v36 BinopI { op=ne, lhs=v35, rhs_imm=2 } -> x0 + terminator Bz { cond=v36, target=b14, fall=b13 } (exit_acc=v36) block 13 start_pc=0 - v40 Imm(7) -> x0 - terminator Return(v40) (exit_acc=v40) + v37 Imm(7) -> x0 + terminator Return(v37) (exit_acc=v37) block 14 start_pc=0 - v41 Imm(4607182418800017408) -> x7 - v42 Call { target_pc=0, args=[v41], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v43 BinopI { op=ne, lhs=v42, rhs_imm=4 } -> x0 - terminator Bz { cond=v43, target=b16, fall=b15 } (exit_acc=v43) + v38 Imm(4607182418800017408) -> x7 + v39 Call { target_pc=0, args=[v38], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v40 BinopI { op=ne, lhs=v39, rhs_imm=4 } -> x0 + terminator Bz { cond=v40, target=b16, fall=b15 } (exit_acc=v40) block 15 start_pc=0 - v44 Imm(8) -> x0 - terminator Return(v44) (exit_acc=v44) + v41 Imm(8) -> x0 + terminator Return(v41) (exit_acc=v41) block 16 start_pc=0 - v45 Imm(9214871658872686752) -> x0 - v46 Imm(4621819117588971520) -> x1 - v47 Binop { op=fmul, lhs=v45, rhs=v46 } -> d0 - v48 Call { target_pc=0, args=[v47], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v49 BinopI { op=ne, lhs=v48, rhs_imm=1 } -> x0 - terminator Bz { cond=v49, target=b18, fall=b17 } (exit_acc=v49) + v42 Imm(9214871658872686752) -> x0 + v43 Imm(4621819117588971520) -> x1 + v44 Binop { op=fmul, lhs=v42, rhs=v43 } -> d0 + v45 Call { target_pc=0, args=[v44], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v46 BinopI { op=ne, lhs=v45, rhs_imm=1 } -> x0 + terminator Bz { cond=v46, target=b18, fall=b17 } (exit_acc=v46) block 17 start_pc=0 - v50 Imm(9) -> x0 - terminator Return(v50) (exit_acc=v50) + v47 Imm(9) -> x0 + terminator Return(v47) (exit_acc=v47) block 18 start_pc=0 - v51 Imm(0) -> x0 - v52 Binop { op=fdiv, lhs=v51, rhs=v51 } -> d0 - v53 Call { target_pc=0, args=[v52], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v54 BinopI { op=ne, lhs=v53, rhs_imm=0 } -> x0 - terminator Bz { cond=v54, target=b20, fall=b19 } (exit_acc=v54) + v48 Imm(0) -> x0 + v49 Binop { op=fdiv, lhs=v48, rhs=v48 } -> d0 + v50 Call { target_pc=0, args=[v49], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v51 BinopI { op=ne, lhs=v50, rhs_imm=0 } -> x0 + terminator Bz { cond=v51, target=b20, fall=b19 } (exit_acc=v51) block 19 start_pc=0 - v55 Imm(10) -> x0 - terminator Return(v55) (exit_acc=v55) + v52 Imm(10) -> x0 + terminator Return(v52) (exit_acc=v52) block 20 start_pc=0 - v56 Imm(20240225330731) -> x7 - v57 Call { target_pc=0, args=[v56], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 - v58 BinopI { op=ne, lhs=v57, rhs_imm=3 } -> x0 - terminator Bz { cond=v58, target=b22, fall=b21 } (exit_acc=v58) + v53 Imm(20240225330731) -> x7 + v54 Call { target_pc=0, args=[v53], fixed_args=1, fp_return=false, fp_arg_mask=0x1 } -> x0 + v55 BinopI { op=ne, lhs=v54, rhs_imm=3 } -> x0 + terminator Bz { cond=v55, target=b22, fall=b21 } (exit_acc=v55) block 21 start_pc=0 - v59 Imm(11) -> x0 - terminator Return(v59) (exit_acc=v59) + v56 Imm(11) -> x0 + terminator Return(v56) (exit_acc=v56) block 22 start_pc=0 - v60 Imm(0) -> x0 - terminator Return(v60) (exit_acc=v60) + v57 Imm(0) -> x0 + terminator Return(v57) (exit_acc=v57) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_fp_return_value.ssa b/tests/snapshots/ssa/libc_fp_return_value.ssa index 51ff01001..ec2ecd5dc 100644 --- a/tests/snapshots/ssa/libc_fp_return_value.ssa +++ b/tests/snapshots/ssa/libc_fp_return_value.ssa @@ -72,112 +72,100 @@ fn ent_pc=14 n_params=0 variadic=false locals=15 terminator Jmp(b10) (exit_acc=v46) block 10 start_pc=0 v48 Phi { incoming=[b30:v38, b9:v46], kind=I64 } -> x3 - v49 Imm(4616189618054758400) -> x0 - v50 FpCast { kind=F64ToF32, value=v49 } -> d0 [f32] - v51 Intrinsic { kind=12, args=[v50] } -> d0 [f32] - v52 Imm(0) -> x0 - v53 LoadLocal { off=-7, kind=F32 } -> d1 [f32] - v54 Imm(4611686018427387904) -> x0 - v55 FpCast { kind=F32ToF64, value=v51 } -> d0 - v56 Binop { op=fne, lhs=v55, rhs=v54 } -> x0 - terminator Bz { cond=v56, target=b31, fall=b11 } (exit_acc=v56) + v49 Imm(1082130432) -> x0 [f32] + v50 Intrinsic { kind=12, args=[v49] } -> d0 [f32] + v51 Imm(0) -> x0 + v52 LoadLocal { off=-7, kind=F32 } -> d1 [f32] + v53 Imm(1073741824) -> x0 [f32] + v54 Binop { op=fne, lhs=v50, rhs=v53 } -> x0 + terminator Bz { cond=v54, target=b31, fall=b11 } (exit_acc=v54) block 11 start_pc=0 - v57 Imm(0) -> x3 - v58 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v57) + v55 Imm(0) -> x3 + v56 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v55) block 12 start_pc=0 - v59 Phi { incoming=[b31:v48, b11:v57], kind=I64 } -> x3 - v60 Imm(4615063718147915776) -> x0 - v61 Fneg(v60) -> d0 - v62 FpCast { kind=F64ToF32, value=v61 } -> d0 [f32] - v63 Intrinsic { kind=14, args=[v62] } -> d0 [f32] - v64 Imm(0) -> x1 - v65 LoadLocal { off=-8, kind=F32 } -> d1 [f32] - v66 FpCast { kind=F32ToF64, value=v63 } -> d0 - v67 Binop { op=fne, lhs=v66, rhs=v60 } -> x0 - terminator Bz { cond=v67, target=b32, fall=b13 } (exit_acc=v67) + v57 Phi { incoming=[b31:v48, b11:v55], kind=I64 } -> x3 + v58 Imm(1080033280) -> x0 [f32] + v59 Fneg(v58) -> d0 [f32] + v60 Intrinsic { kind=14, args=[v59] } -> d0 [f32] + v61 Imm(0) -> x1 + v62 LoadLocal { off=-8, kind=F32 } -> d1 [f32] + v63 Binop { op=fne, lhs=v60, rhs=v58 } -> x0 + terminator Bz { cond=v63, target=b32, fall=b13 } (exit_acc=v63) block 13 start_pc=0 - v68 Imm(0) -> x3 - v69 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v68) + v64 Imm(0) -> x3 + v65 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v64) block 14 start_pc=0 - v70 Phi { incoming=[b32:v59, b13:v68], kind=I64 } -> x3 - v71 Imm(4625196817309499392) -> x0 - v72 FpCast { kind=F64ToF32, value=v71 } -> d0 [f32] - v73 Intrinsic { kind=12, args=[v72] } -> d0 [f32] - v74 FpCast { kind=F32ToF64, value=v73 } -> d0 - v75 Imm(0) -> x0 - v76 LoadLocal { off=-9, kind=F64 } -> d1 - v77 Imm(4616189618054758400) -> x0 - v78 Binop { op=fne, lhs=v74, rhs=v77 } -> x0 - terminator Bz { cond=v78, target=b33, fall=b15 } (exit_acc=v78) + v66 Phi { incoming=[b32:v57, b13:v64], kind=I64 } -> x3 + v67 Imm(1098907648) -> x0 [f32] + v68 Intrinsic { kind=12, args=[v67] } -> d0 [f32] + v69 FpCast { kind=F32ToF64, value=v68 } -> d0 + v70 Imm(0) -> x0 + v71 LoadLocal { off=-9, kind=F64 } -> d1 + v72 Imm(4616189618054758400) -> x0 + v73 Binop { op=fne, lhs=v69, rhs=v72 } -> x0 + terminator Bz { cond=v73, target=b33, fall=b15 } (exit_acc=v73) block 15 start_pc=0 - v79 Imm(0) -> x3 - v80 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v79) + v74 Imm(0) -> x3 + v75 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v74) block 16 start_pc=0 - v81 Phi { incoming=[b33:v70, b15:v79], kind=I64 } -> x3 - v82 Imm(4613262278296967578) -> x0 - v83 FpCast { kind=F64ToF32, value=v82 } -> d0 [f32] - v84 Intrinsic { kind=16, args=[v83] } -> d0 [f32] - v85 Imm(0) -> x0 - v86 LoadLocal { off=-10, kind=F32 } -> d1 [f32] - v87 Imm(4611686018427387904) -> x0 - v88 FpCast { kind=F32ToF64, value=v84 } -> d0 - v89 Binop { op=fne, lhs=v88, rhs=v87 } -> x0 - terminator Bz { cond=v89, target=b34, fall=b17 } (exit_acc=v89) + v76 Phi { incoming=[b33:v66, b15:v74], kind=I64 } -> x3 + v77 Imm(1076677837) -> x0 [f32] + v78 Intrinsic { kind=16, args=[v77] } -> d0 [f32] + v79 Imm(0) -> x0 + v80 LoadLocal { off=-10, kind=F32 } -> d1 [f32] + v81 Imm(1073741824) -> x0 [f32] + v82 Binop { op=fne, lhs=v78, rhs=v81 } -> x0 + terminator Bz { cond=v82, target=b34, fall=b17 } (exit_acc=v82) block 17 start_pc=0 - v90 Imm(0) -> x3 - v91 Imm(0) -> x0 - terminator Jmp(b18) (exit_acc=v90) + v83 Imm(0) -> x3 + v84 Imm(0) -> x0 + terminator Jmp(b18) (exit_acc=v83) block 18 start_pc=0 - v92 Phi { incoming=[b34:v81, b17:v90], kind=I64 } -> x3 - v93 Imm(4612361558371493478) -> x0 - v94 FpCast { kind=F64ToF32, value=v93 } -> d0 [f32] - v95 Intrinsic { kind=18, args=[v94] } -> d0 [f32] - v96 Imm(0) -> x0 - v97 LoadLocal { off=-11, kind=F32 } -> d1 [f32] - v98 Imm(4613937818241073152) -> x0 - v99 FpCast { kind=F32ToF64, value=v95 } -> d0 - v100 Binop { op=fne, lhs=v99, rhs=v98 } -> x0 - terminator Bz { cond=v100, target=b35, fall=b19 } (exit_acc=v100) + v85 Phi { incoming=[b34:v76, b17:v83], kind=I64 } -> x3 + v86 Imm(1075000115) -> x0 [f32] + v87 Intrinsic { kind=18, args=[v86] } -> d0 [f32] + v88 Imm(0) -> x0 + v89 LoadLocal { off=-11, kind=F32 } -> d1 [f32] + v90 Imm(1077936128) -> x0 [f32] + v91 Binop { op=fne, lhs=v87, rhs=v90 } -> x0 + terminator Bz { cond=v91, target=b35, fall=b19 } (exit_acc=v91) block 19 start_pc=0 - v101 Imm(0) -> x3 - v102 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v101) + v92 Imm(0) -> x3 + v93 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v92) block 20 start_pc=0 - v103 Phi { incoming=[b35:v92, b19:v101], kind=I64 } -> x3 - v104 Imm(4619567317775286272) -> x0 - v105 FpCast { kind=F64ToF32, value=v104 } -> d0 [f32] - v106 Imm(4616189618054758400) -> x0 - v107 FpCast { kind=F64ToF32, value=v106 } -> d1 [f32] - v108 CallExt { binding_idx=113, args=[v105, v107], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v109 Imm(0) -> x0 - v110 LoadLocal { off=-12, kind=F32 } -> d1 [f32] - v111 Imm(4613937818241073152) -> x0 - v112 FpCast { kind=F32ToF64, value=v108 } -> d0 - v113 Binop { op=fne, lhs=v112, rhs=v111 } -> x0 - terminator Bz { cond=v113, target=b36, fall=b21 } (exit_acc=v113) + v94 Phi { incoming=[b35:v85, b19:v92], kind=I64 } -> x3 + v95 Imm(1088421888) -> x7 [f32] + v96 Imm(1082130432) -> x6 [f32] + v97 CallExt { binding_idx=113, args=[v95, v96], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v98 Imm(0) -> x0 + v99 LoadLocal { off=-12, kind=F32 } -> d1 [f32] + v100 Imm(1077936128) -> x0 [f32] + v101 Binop { op=fne, lhs=v97, rhs=v100 } -> x0 + terminator Bz { cond=v101, target=b36, fall=b21 } (exit_acc=v101) block 21 start_pc=0 - v114 Imm(0) -> x3 - v115 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v114) + v102 Imm(0) -> x3 + v103 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v102) block 22 start_pc=0 - v116 Phi { incoming=[b36:v103, b21:v114], kind=I64 } -> x3 - v117 Extend { value=v116, kind=I32 } -> x0 - terminator Bz { cond=v117, target=b24, fall=b23 } (exit_acc=v117) + v104 Phi { incoming=[b36:v94, b21:v102], kind=I64 } -> x3 + v105 Extend { value=v104, kind=I32 } -> x0 + terminator Bz { cond=v105, target=b24, fall=b23 } (exit_acc=v105) block 23 start_pc=0 - v118 Imm(11) -> x1 - v119 Imm(0) -> x0 - terminator Jmp(b25) (exit_acc=v118) + v106 Imm(11) -> x1 + v107 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v106) block 24 start_pc=0 - v120 Imm(0) -> x1 - v121 Imm(0) -> x0 - terminator Jmp(b25) (exit_acc=v120) + v108 Imm(0) -> x1 + v109 Imm(0) -> x0 + terminator Jmp(b25) (exit_acc=v108) block 25 start_pc=0 - v122 Phi { incoming=[b23:v118, b24:v120], kind=I64 } -> x1 - v123 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Return(v122) (exit_acc=v122) + v110 Phi { incoming=[b23:v106, b24:v108], kind=I64 } -> x1 + v111 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Return(v110) (exit_acc=v110) block 26 start_pc=0 terminator Jmp(b2) block 27 start_pc=0 diff --git a/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa b/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa index e7c0d86cd..cad523525 100644 --- a/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa +++ b/tests/snapshots/ssa/libc_math_fdim_scalbn.ssa @@ -179,33 +179,28 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v35 Imm(6) -> x0 terminator Return(v35) (exit_acc=v35) block 12 start_pc=0 - v36 Imm(4607182418800017408) -> x0 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 Imm(2) -> x7 - v39 Call { target_pc=11, args=[v37, v38], fixed_args=2, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] - v40 Imm(4616189618054758400) -> x0 - v41 FpCast { kind=F32ToF64, value=v39 } -> d0 - v42 Binop { op=fne, lhs=v41, rhs=v40 } -> x0 - terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) + v36 Imm(1065353216) -> x7 [f32] + v37 Imm(2) -> x6 + v38 Call { target_pc=11, args=[v36, v37], fixed_args=2, fp_return=true, fp_arg_mask=0x1 } -> d0 [f32] + v39 Imm(1082130432) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b14, fall=b13 } (exit_acc=v40) block 13 start_pc=0 - v43 Imm(7) -> x0 - terminator Return(v43) (exit_acc=v43) + v41 Imm(7) -> x0 + terminator Return(v41) (exit_acc=v41) block 14 start_pc=0 - v44 Imm(4617315517961601024) -> x0 - v45 FpCast { kind=F64ToF32, value=v44 } -> d0 [f32] - v46 Imm(4613937818241073152) -> x0 - v47 FpCast { kind=F64ToF32, value=v46 } -> d1 [f32] - v48 Call { target_pc=8, args=[v45, v47], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] - v49 Imm(4611686018427387904) -> x0 - v50 FpCast { kind=F32ToF64, value=v48 } -> d0 - v51 Binop { op=fne, lhs=v50, rhs=v49 } -> x0 - terminator Bz { cond=v51, target=b16, fall=b15 } (exit_acc=v51) + v42 Imm(1084227584) -> x7 [f32] + v43 Imm(1077936128) -> x6 [f32] + v44 Call { target_pc=8, args=[v42, v43], fixed_args=2, fp_return=true, fp_arg_mask=0x3 } -> d0 [f32] + v45 Imm(1073741824) -> x0 [f32] + v46 Binop { op=fne, lhs=v44, rhs=v45 } -> x0 + terminator Bz { cond=v46, target=b16, fall=b15 } (exit_acc=v46) block 15 start_pc=0 - v52 Imm(8) -> x0 - terminator Return(v52) (exit_acc=v52) + v47 Imm(8) -> x0 + terminator Return(v47) (exit_acc=v47) block 16 start_pc=0 - v53 Imm(0) -> x0 - terminator Return(v53) (exit_acc=v53) + v48 Imm(0) -> x0 + terminator Return(v48) (exit_acc=v48) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_hyperbolic.ssa b/tests/snapshots/ssa/libc_math_hyperbolic.ssa index 89903de75..d938c762f 100644 --- a/tests/snapshots/ssa/libc_math_hyperbolic.ssa +++ b/tests/snapshots/ssa/libc_math_hyperbolic.ssa @@ -94,22 +94,22 @@ fn ent_pc=14 n_params=0 variadic=false locals=3 v34 Imm(6) -> x0 terminator Return(v34) (exit_acc=v34) block 12 start_pc=0 - v35 Imm(0) -> x3 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 CallExt { binding_idx=68, args=[v36], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v38 FpCast { kind=F32ToF64, value=v37 } -> d0 - v39 Call { target_pc=13, args=[v38, v35], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v35 Imm(0) -> x7 [f32] + v36 CallExt { binding_idx=68, args=[v35], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v37 FpCast { kind=F32ToF64, value=v36 } -> d0 + v38 Imm(0) -> x7 + v39 Call { target_pc=13, args=[v37, v38], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v40 BinopI { op=eq, lhs=v39, rhs_imm=0 } -> x0 terminator Bz { cond=v40, target=b14, fall=b13 } (exit_acc=v40) block 13 start_pc=0 v41 Imm(7) -> x0 terminator Return(v41) (exit_acc=v41) block 14 start_pc=0 - v42 Imm(0) -> x3 - v43 FpCast { kind=F64ToF32, value=v42 } -> d0 [f32] - v44 CallExt { binding_idx=70, args=[v43], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v45 FpCast { kind=F32ToF64, value=v44 } -> d0 - v46 Call { target_pc=13, args=[v45, v42], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v42 Imm(0) -> x7 [f32] + v43 CallExt { binding_idx=70, args=[v42], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v44 FpCast { kind=F32ToF64, value=v43 } -> d0 + v45 Imm(0) -> x7 + v46 Call { target_pc=13, args=[v44, v45], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v47 BinopI { op=eq, lhs=v46, rhs_imm=0 } -> x0 terminator Bz { cond=v47, target=b16, fall=b15 } (exit_acc=v47) block 15 start_pc=0 diff --git a/tests/snapshots/ssa/libc_math_libm.ssa b/tests/snapshots/ssa/libc_math_libm.ssa index b190a3db6..332773a90 100644 --- a/tests/snapshots/ssa/libc_math_libm.ssa +++ b/tests/snapshots/ssa/libc_math_libm.ssa @@ -102,35 +102,33 @@ fn ent_pc=14 n_params=0 variadic=false locals=3 v38 Imm(7) -> x0 terminator Return(v38) (exit_acc=v38) block 14 start_pc=0 - v39 Imm(4628293042053316608) -> x0 - v40 FpCast { kind=F64ToF32, value=v39 } -> d0 [f32] - v41 CallExt { binding_idx=79, args=[v40], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v42 FpCast { kind=F32ToF64, value=v41 } -> d0 - v43 Imm(4613937818241073152) -> x7 - v44 Call { target_pc=13, args=[v42, v43], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v39 Imm(1104674816) -> x7 [f32] + v40 CallExt { binding_idx=79, args=[v39], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v41 FpCast { kind=F32ToF64, value=v40 } -> d0 + v42 Imm(1077936128) -> x0 [f32] + v43 FpCast { kind=F32ToF64, value=v42 } -> d1 + v44 Call { target_pc=13, args=[v41, v43], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 v45 BinopI { op=eq, lhs=v44, rhs_imm=0 } -> x0 terminator Bz { cond=v45, target=b16, fall=b15 } (exit_acc=v45) block 15 start_pc=0 v46 Imm(8) -> x0 terminator Return(v46) (exit_acc=v46) block 16 start_pc=0 - v47 Imm(4617315517961601024) -> x0 - v48 FpCast { kind=F64ToF32, value=v47 } -> d0 [f32] - v49 Imm(4613937818241073152) -> x0 - v50 FpCast { kind=F64ToF32, value=v49 } -> d1 [f32] - v51 CallExt { binding_idx=82, args=[v48, v50], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v52 FpCast { kind=F32ToF64, value=v51 } -> d0 - v53 Imm(4607182418800017408) -> x0 - v54 Fneg(v53) -> d1 - v55 Call { target_pc=13, args=[v52, v54], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v56 BinopI { op=eq, lhs=v55, rhs_imm=0 } -> x0 - terminator Bz { cond=v56, target=b18, fall=b17 } (exit_acc=v56) + v47 Imm(1084227584) -> x7 [f32] + v48 Imm(1077936128) -> x6 [f32] + v49 CallExt { binding_idx=82, args=[v47, v48], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v50 FpCast { kind=F32ToF64, value=v49 } -> d0 + v51 Imm(4607182418800017408) -> x0 + v52 Fneg(v51) -> d1 + v53 Call { target_pc=13, args=[v50, v52], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v54 BinopI { op=eq, lhs=v53, rhs_imm=0 } -> x0 + terminator Bz { cond=v54, target=b18, fall=b17 } (exit_acc=v54) block 17 start_pc=0 - v57 Imm(9) -> x0 - terminator Return(v57) (exit_acc=v57) + v55 Imm(9) -> x0 + terminator Return(v55) (exit_acc=v55) block 18 start_pc=0 - v58 Imm(0) -> x0 - terminator Return(v58) (exit_acc=v58) + v56 Imm(0) -> x0 + terminator Return(v56) (exit_acc=v56) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_minmax.ssa b/tests/snapshots/ssa/libc_math_minmax.ssa index e6781124e..b7ab32dbf 100644 --- a/tests/snapshots/ssa/libc_math_minmax.ssa +++ b/tests/snapshots/ssa/libc_math_minmax.ssa @@ -52,45 +52,36 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v28 Imm(5) -> x0 terminator Return(v28) (exit_acc=v28) block 10 start_pc=0 - v29 Imm(4613937818241073152) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d0 [f32] - v31 Imm(4616189618054758400) -> x0 - v32 FpCast { kind=F64ToF32, value=v31 } -> d1 [f32] - v33 CallExt { binding_idx=74, args=[v30, v32], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v34 Imm(4617315517961601024) -> x0 - v35 FpCast { kind=F32ToF64, value=v33 } -> d0 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) + v29 Imm(1077936128) -> x7 [f32] + v30 Imm(1082130432) -> x6 [f32] + v31 CallExt { binding_idx=74, args=[v29, v30], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v32 Imm(1084227584) -> x0 [f32] + v33 Binop { op=fne, lhs=v31, rhs=v32 } -> x0 + terminator Bz { cond=v33, target=b12, fall=b11 } (exit_acc=v33) block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) + v34 Imm(6) -> x0 + terminator Return(v34) (exit_acc=v34) block 12 start_pc=0 - v38 Imm(4611686018427387904) -> x3 - v39 FpCast { kind=F64ToF32, value=v38 } -> d0 [f32] - v40 Imm(4613937818241073152) -> x0 - v41 FpCast { kind=F64ToF32, value=v40 } -> d1 [f32] - v42 CallExt { binding_idx=75, args=[v39, v41], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v43 FpCast { kind=F32ToF64, value=v42 } -> d0 - v44 Binop { op=fne, lhs=v43, rhs=v38 } -> x0 - terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) + v35 Imm(1073741824) -> x3 [f32] + v36 Imm(1077936128) -> x6 [f32] + v37 CallExt { binding_idx=75, args=[v35, v36], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v38 Binop { op=fne, lhs=v37, rhs=v35 } -> x0 + terminator Bz { cond=v38, target=b14, fall=b13 } (exit_acc=v38) block 13 start_pc=0 - v45 Imm(7) -> x0 - terminator Return(v45) (exit_acc=v45) + v39 Imm(7) -> x0 + terminator Return(v39) (exit_acc=v39) block 14 start_pc=0 - v46 Imm(4611686018427387904) -> x0 - v47 FpCast { kind=F64ToF32, value=v46 } -> d0 [f32] - v48 Imm(4613937818241073152) -> x3 - v49 FpCast { kind=F64ToF32, value=v48 } -> d1 [f32] - v50 CallExt { binding_idx=76, args=[v47, v49], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v51 FpCast { kind=F32ToF64, value=v50 } -> d0 - v52 Binop { op=fne, lhs=v51, rhs=v48 } -> x0 - terminator Bz { cond=v52, target=b16, fall=b15 } (exit_acc=v52) + v40 Imm(1073741824) -> x7 [f32] + v41 Imm(1077936128) -> x3 [f32] + v42 CallExt { binding_idx=76, args=[v40, v41], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x0 + terminator Bz { cond=v43, target=b16, fall=b15 } (exit_acc=v43) block 15 start_pc=0 - v53 Imm(8) -> x0 - terminator Return(v53) (exit_acc=v53) + v44 Imm(8) -> x0 + terminator Return(v44) (exit_acc=v44) block 16 start_pc=0 - v54 Imm(0) -> x0 - terminator Return(v54) (exit_acc=v54) + v45 Imm(0) -> x0 + terminator Return(v45) (exit_acc=v45) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_nextafter.ssa b/tests/snapshots/ssa/libc_math_nextafter.ssa index 8c8cc1a5e..ff7aefdb3 100644 --- a/tests/snapshots/ssa/libc_math_nextafter.ssa +++ b/tests/snapshots/ssa/libc_math_nextafter.ssa @@ -54,29 +54,25 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v26 Imm(6) -> x0 terminator Return(v26) (exit_acc=v26) block 12 start_pc=0 - v27 Imm(4607182418800017408) -> x3 - v28 FpCast { kind=F64ToF32, value=v27 } -> d0 [f32] - v29 Imm(4611686018427387904) -> x0 - v30 FpCast { kind=F64ToF32, value=v29 } -> d1 [f32] - v31 CallExt { binding_idx=59, args=[v28, v30], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] - v32 FpCast { kind=F32ToF64, value=v31 } -> d0 - v33 Binop { op=fle, lhs=v32, rhs=v27 } -> x0 - terminator Bz { cond=v33, target=b14, fall=b13 } (exit_acc=v33) + v27 Imm(1065353216) -> x3 [f32] + v28 Imm(1073741824) -> x6 [f32] + v29 CallExt { binding_idx=59, args=[v27, v28], fp_arg_mask=0x3, fp_return=true } -> d0 [f32] + v30 Binop { op=fle, lhs=v29, rhs=v27 } -> x0 + terminator Bz { cond=v30, target=b14, fall=b13 } (exit_acc=v30) block 13 start_pc=0 - v34 Imm(7) -> x0 - terminator Return(v34) (exit_acc=v34) + v31 Imm(7) -> x0 + terminator Return(v31) (exit_acc=v31) block 14 start_pc=0 - v35 Imm(4625196817309499392) -> x0 - v36 FpCast { kind=F64ToF32, value=v35 } -> d0 [f32] - v37 CallExt { binding_idx=60, args=[v36], fp_arg_mask=0x1 } -> x0 - v38 BinopI { op=ne, lhs=v37, rhs_imm=4 } -> x0 - terminator Bz { cond=v38, target=b16, fall=b15 } (exit_acc=v38) + v32 Imm(1098907648) -> x7 [f32] + v33 CallExt { binding_idx=60, args=[v32], fp_arg_mask=0x1 } -> x0 + v34 BinopI { op=ne, lhs=v33, rhs_imm=4 } -> x0 + terminator Bz { cond=v34, target=b16, fall=b15 } (exit_acc=v34) block 15 start_pc=0 - v39 Imm(8) -> x0 - terminator Return(v39) (exit_acc=v39) + v35 Imm(8) -> x0 + terminator Return(v35) (exit_acc=v35) block 16 start_pc=0 - v40 Imm(0) -> x0 - terminator Return(v40) (exit_acc=v40) + v36 Imm(0) -> x0 + terminator Return(v36) (exit_acc=v36) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_round.ssa b/tests/snapshots/ssa/libc_math_round.ssa index dbe78076b..bc9c3080f 100644 --- a/tests/snapshots/ssa/libc_math_round.ssa +++ b/tests/snapshots/ssa/libc_math_round.ssa @@ -67,30 +67,26 @@ fn ent_pc=13 n_params=0 variadic=false locals=2 v35 Imm(7) -> x0 terminator Return(v35) (exit_acc=v35) block 14 start_pc=0 - v36 Imm(4612811918334230528) -> x0 - v37 FpCast { kind=F64ToF32, value=v36 } -> d0 [f32] - v38 CallExt { binding_idx=77, args=[v37], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v39 Imm(4611686018427387904) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b16, fall=b15 } (exit_acc=v41) + v36 Imm(1075838976) -> x7 [f32] + v37 CallExt { binding_idx=77, args=[v36], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v38 Imm(1073741824) -> x0 [f32] + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x0 + terminator Bz { cond=v39, target=b16, fall=b15 } (exit_acc=v39) block 15 start_pc=0 - v42 Imm(8) -> x0 - terminator Return(v42) (exit_acc=v42) + v40 Imm(8) -> x0 + terminator Return(v40) (exit_acc=v40) block 16 start_pc=0 - v43 Imm(4615063718147915776) -> x0 - v44 FpCast { kind=F64ToF32, value=v43 } -> d0 [f32] - v45 CallExt { binding_idx=78, args=[v44], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v46 Imm(4616189618054758400) -> x0 - v47 FpCast { kind=F32ToF64, value=v45 } -> d0 - v48 Binop { op=fne, lhs=v47, rhs=v46 } -> x0 - terminator Bz { cond=v48, target=b18, fall=b17 } (exit_acc=v48) + v41 Imm(1080033280) -> x7 [f32] + v42 CallExt { binding_idx=78, args=[v41], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v43 Imm(1082130432) -> x0 [f32] + v44 Binop { op=fne, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b18, fall=b17 } (exit_acc=v44) block 17 start_pc=0 - v49 Imm(9) -> x0 - terminator Return(v49) (exit_acc=v49) + v45 Imm(9) -> x0 + terminator Return(v45) (exit_acc=v45) block 18 start_pc=0 - v50 Imm(0) -> x0 - terminator Return(v50) (exit_acc=v50) + v46 Imm(0) -> x0 + terminator Return(v46) (exit_acc=v46) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/libc_math_special.ssa b/tests/snapshots/ssa/libc_math_special.ssa index 1a040e754..f68d66bce 100644 --- a/tests/snapshots/ssa/libc_math_special.ssa +++ b/tests/snapshots/ssa/libc_math_special.ssa @@ -85,31 +85,30 @@ fn ent_pc=14 n_params=0 variadic=false locals=2 v29 Imm(5) -> x0 terminator Return(v29) (exit_acc=v29) block 10 start_pc=0 - v30 Imm(4617315517961601024) -> x0 - v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] - v32 CallExt { binding_idx=71, args=[v31], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v33 FpCast { kind=F32ToF64, value=v32 } -> d0 - v34 Imm(4627448617123184640) -> x7 - v35 Call { target_pc=13, args=[v33, v34], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v36 BinopI { op=eq, lhs=v35, rhs_imm=0 } -> x0 - terminator Bz { cond=v36, target=b12, fall=b11 } (exit_acc=v36) + v30 Imm(1084227584) -> x7 [f32] + v31 CallExt { binding_idx=71, args=[v30], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v32 FpCast { kind=F32ToF64, value=v31 } -> d0 + v33 Imm(4627448617123184640) -> x7 + v34 Call { target_pc=13, args=[v32, v33], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v35 BinopI { op=eq, lhs=v34, rhs_imm=0 } -> x0 + terminator Bz { cond=v35, target=b12, fall=b11 } (exit_acc=v35) block 11 start_pc=0 - v37 Imm(6) -> x0 - terminator Return(v37) (exit_acc=v37) + v36 Imm(6) -> x0 + terminator Return(v36) (exit_acc=v36) block 12 start_pc=0 - v38 Imm(0) -> x3 - v39 FpCast { kind=F64ToF32, value=v38 } -> d0 [f32] - v40 CallExt { binding_idx=72, args=[v39], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] - v41 FpCast { kind=F32ToF64, value=v40 } -> d0 - v42 Call { target_pc=13, args=[v41, v38], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 - v43 BinopI { op=eq, lhs=v42, rhs_imm=0 } -> x0 - terminator Bz { cond=v43, target=b14, fall=b13 } (exit_acc=v43) + v37 Imm(0) -> x7 [f32] + v38 CallExt { binding_idx=72, args=[v37], fp_arg_mask=0x1, fp_return=true } -> d0 [f32] + v39 FpCast { kind=F32ToF64, value=v38 } -> d0 + v40 Imm(0) -> x7 + v41 Call { target_pc=13, args=[v39, v40], fixed_args=2, fp_return=false, fp_arg_mask=0x3 } -> x0 + v42 BinopI { op=eq, lhs=v41, rhs_imm=0 } -> x0 + terminator Bz { cond=v42, target=b14, fall=b13 } (exit_acc=v42) block 13 start_pc=0 - v44 Imm(7) -> x0 - terminator Return(v44) (exit_acc=v44) + v43 Imm(7) -> x0 + terminator Return(v43) (exit_acc=v43) block 14 start_pc=0 - v45 Imm(0) -> x0 - terminator Return(v45) (exit_acc=v45) + v44 Imm(0) -> x0 + terminator Return(v44) (exit_acc=v44) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/local_init_int_to_float.ssa b/tests/snapshots/ssa/local_init_int_to_float.ssa index 547074d33..6a663e4bc 100644 --- a/tests/snapshots/ssa/local_init_int_to_float.ssa +++ b/tests/snapshots/ssa/local_init_int_to_float.ssa @@ -14,156 +14,149 @@ fn ent_pc=1 n_params=0 variadic=false locals=18 v8 FpCast { kind=F64ToF32, value=v7 } -> [spill 0] [f32] v9 Imm(0) -> x0 v10 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v11 Imm(4631093718071587635) -> x0 - v12 FpCast { kind=F32ToF64, value=v8 } -> d0 - v13 Binop { op=flt, lhs=v12, rhs=v11 } -> x3 - v14 Imm(0) -> x0 - terminator Bnz { cond=v13, target=b21, fall=b1 } (exit_acc=v13) + v11 Imm(1109891482) -> x0 [f32] + v12 Binop { op=flt, lhs=v8, rhs=v11 } -> x3 + v13 Imm(0) -> x0 + terminator Bnz { cond=v12, target=b21, fall=b1 } (exit_acc=v12) block 1 start_pc=0 - v15 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v16 Imm(4631121865569258701) -> x0 - v17 FpCast { kind=F32ToF64, value=v8 } -> d0 - v18 Binop { op=fgt, lhs=v17, rhs=v16 } -> x3 - v19 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v18) + v14 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v15 Imm(1109943910) -> x0 [f32] + v16 Binop { op=fgt, lhs=v8, rhs=v15 } -> x3 + v17 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v16) block 2 start_pc=0 - v20 Phi { incoming=[b21:v13, b1:v18], kind=I64 } -> x3 - v21 LoadLocal { off=-15, kind=I64 } -> x0 - terminator Bz { cond=v20, target=b4, fall=b3 } (exit_acc=v20) + v18 Phi { incoming=[b21:v12, b1:v16], kind=I64 } -> x3 + v19 LoadLocal { off=-15, kind=I64 } -> x0 + terminator Bz { cond=v18, target=b4, fall=b3 } (exit_acc=v18) block 3 start_pc=0 - v22 ImmData(56) -> x7 - v23 LoadLocal { off=-2, kind=F32 } -> d0 [f32] - v24 FpCast { kind=F32ToF64, value=v8 } -> d0 - v25 CallExt { binding_idx=0, args=[v22, v24], fp_arg_mask=0x2 } -> x0 - v26 Imm(1) -> x0 - terminator Return(v26) (exit_acc=v26) + v20 ImmData(56) -> x7 + v21 LoadLocal { off=-2, kind=F32 } -> d0 [f32] + v22 FpCast { kind=F32ToF64, value=v8 } -> d0 + v23 CallExt { binding_idx=0, args=[v20, v22], fp_arg_mask=0x2 } -> x0 + v24 Imm(1) -> x0 + terminator Return(v24) (exit_acc=v24) block 4 start_pc=0 - v27 Imm(12345) -> x0 - v28 Imm(0) -> x1 - v29 LoadLocal { off=-3, kind=I32 } -> x1 - v30 FpCast { kind=IntToFp, value=v27 } -> d0 - v31 FpCast { kind=F64ToF32, value=v30 } -> [spill 0] [f32] - v32 Imm(0) -> x0 - v33 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v34 Imm(4668012074973003776) -> x0 - v35 FpCast { kind=F32ToF64, value=v31 } -> d0 - v36 Binop { op=flt, lhs=v35, rhs=v34 } -> x3 - v37 Imm(0) -> x0 - terminator Bnz { cond=v36, target=b22, fall=b5 } (exit_acc=v36) + v25 Imm(12345) -> x0 + v26 Imm(0) -> x1 + v27 LoadLocal { off=-3, kind=I32 } -> x1 + v28 FpCast { kind=IntToFp, value=v25 } -> d0 + v29 FpCast { kind=F64ToF32, value=v28 } -> [spill 0] [f32] + v30 Imm(0) -> x0 + v31 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v32 Imm(1178657280) -> x0 [f32] + v33 Binop { op=flt, lhs=v29, rhs=v32 } -> x3 + v34 Imm(0) -> x0 + terminator Bnz { cond=v33, target=b22, fall=b5 } (exit_acc=v33) block 5 start_pc=0 - v38 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v39 Imm(4668012624728817664) -> x0 - v40 FpCast { kind=F32ToF64, value=v31 } -> d0 - v41 Binop { op=fgt, lhs=v40, rhs=v39 } -> x3 - v42 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v41) + v35 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v36 Imm(1178658304) -> x0 [f32] + v37 Binop { op=fgt, lhs=v29, rhs=v36 } -> x3 + v38 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v37) block 6 start_pc=0 - v43 Phi { incoming=[b22:v36, b5:v41], kind=I64 } -> x3 - v44 LoadLocal { off=-16, kind=I64 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v39 Phi { incoming=[b22:v33, b5:v37], kind=I64 } -> x3 + v40 LoadLocal { off=-16, kind=I64 } -> x0 + terminator Bz { cond=v39, target=b8, fall=b7 } (exit_acc=v39) block 7 start_pc=0 - v45 ImmData(78) -> x7 - v46 LoadLocal { off=-4, kind=F32 } -> d0 [f32] - v47 FpCast { kind=F32ToF64, value=v31 } -> d0 - v48 CallExt { binding_idx=0, args=[v45, v47], fp_arg_mask=0x2 } -> x0 - v49 Imm(2) -> x0 - terminator Return(v49) (exit_acc=v49) + v41 ImmData(78) -> x7 + v42 LoadLocal { off=-4, kind=F32 } -> d0 [f32] + v43 FpCast { kind=F32ToF64, value=v29 } -> d0 + v44 CallExt { binding_idx=0, args=[v41, v43], fp_arg_mask=0x2 } -> x0 + v45 Imm(2) -> x0 + terminator Return(v45) (exit_acc=v45) block 8 start_pc=0 - v50 Imm(-7) -> x0 - v51 Imm(0) -> x1 - v52 LoadLocal { off=-5, kind=I32 } -> x1 - v53 FpCast { kind=IntToFp, value=v50 } -> [spill 0] - v54 Imm(0) -> x0 - v55 LoadLocal { off=-6, kind=F64 } -> d0 - v56 Imm(4620130267728707584) -> x0 - v57 Fneg(v56) -> d0 - v58 Binop { op=flt, lhs=v53, rhs=v57 } -> x3 - v59 Imm(0) -> x0 - terminator Bnz { cond=v58, target=b23, fall=b9 } (exit_acc=v58) + v46 Imm(-7) -> x0 + v47 Imm(0) -> x1 + v48 LoadLocal { off=-5, kind=I32 } -> x1 + v49 FpCast { kind=IntToFp, value=v46 } -> [spill 0] + v50 Imm(0) -> x0 + v51 LoadLocal { off=-6, kind=F64 } -> d0 + v52 Imm(4620130267728707584) -> x0 + v53 Fneg(v52) -> d0 + v54 Binop { op=flt, lhs=v49, rhs=v53 } -> x3 + v55 Imm(0) -> x0 + terminator Bnz { cond=v54, target=b23, fall=b9 } (exit_acc=v54) block 9 start_pc=0 - v60 LoadLocal { off=-6, kind=F64 } -> d0 - v61 Imm(4619004367821864960) -> x0 - v62 Fneg(v61) -> d0 - v63 Binop { op=fgt, lhs=v53, rhs=v62 } -> x3 - v64 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v63) + v56 LoadLocal { off=-6, kind=F64 } -> d0 + v57 Imm(4619004367821864960) -> x0 + v58 Fneg(v57) -> d0 + v59 Binop { op=fgt, lhs=v49, rhs=v58 } -> x3 + v60 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v59) block 10 start_pc=0 - v65 Phi { incoming=[b23:v58, b9:v63], kind=I64 } -> x3 - v66 LoadLocal { off=-17, kind=I64 } -> x0 - terminator Bz { cond=v65, target=b12, fall=b11 } (exit_acc=v65) + v61 Phi { incoming=[b23:v54, b9:v59], kind=I64 } -> x3 + v62 LoadLocal { off=-17, kind=I64 } -> x0 + terminator Bz { cond=v61, target=b12, fall=b11 } (exit_acc=v61) block 11 start_pc=0 - v67 ImmData(102) -> x7 - v68 LoadLocal { off=-6, kind=F64 } -> d0 - v69 CallExt { binding_idx=0, args=[v67, v53], fp_arg_mask=0x2 } -> x0 - v70 Imm(3) -> x0 - terminator Return(v70) (exit_acc=v70) + v63 ImmData(102) -> x7 + v64 LoadLocal { off=-6, kind=F64 } -> d0 + v65 CallExt { binding_idx=0, args=[v63, v49], fp_arg_mask=0x2 } -> x0 + v66 Imm(3) -> x0 + terminator Return(v66) (exit_acc=v66) block 12 start_pc=0 - v71 Imm(4294967295) -> x0 - v72 Imm(0) -> x1 - v73 LoadLocal { off=-7, kind=U32 } -> x1 - v74 FpCast { kind=IntToFp, value=v71 } -> d0 - v75 FpCast { kind=F64ToF32, value=v74 } -> [spill 0] [f32] + v67 Imm(4294967295) -> x0 + v68 Imm(0) -> x1 + v69 LoadLocal { off=-7, kind=U32 } -> x1 + v70 FpCast { kind=IntToFp, value=v67 } -> d0 + v71 FpCast { kind=F64ToF32, value=v70 } -> [spill 0] [f32] + v72 Imm(0) -> x0 + v73 LoadLocal { off=-8, kind=F32 } -> d0 [f32] + v74 Imm(1333769268) -> x0 [f32] + v75 Binop { op=flt, lhs=v71, rhs=v74 } -> x3 v76 Imm(0) -> x0 - v77 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v78 Imm(4751287189701132288) -> x0 - v79 FpCast { kind=F32ToF64, value=v75 } -> d0 - v80 Binop { op=flt, lhs=v79, rhs=v78 } -> x3 - v81 Imm(0) -> x0 - terminator Bnz { cond=v80, target=b24, fall=b13 } (exit_acc=v80) + terminator Bnz { cond=v75, target=b24, fall=b13 } (exit_acc=v75) block 13 start_pc=0 - v82 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v83 Imm(4751302884048502784) -> x0 - v84 FpCast { kind=F32ToF64, value=v75 } -> d0 - v85 Binop { op=fgt, lhs=v84, rhs=v83 } -> x3 - v86 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v85) + v77 LoadLocal { off=-8, kind=F32 } -> d0 [f32] + v78 Imm(1333798502) -> x0 [f32] + v79 Binop { op=fgt, lhs=v71, rhs=v78 } -> x3 + v80 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v79) block 14 start_pc=0 - v87 Phi { incoming=[b24:v80, b13:v85], kind=I64 } -> x3 - v88 LoadLocal { off=-18, kind=I64 } -> x0 - terminator Bz { cond=v87, target=b16, fall=b15 } (exit_acc=v87) + v81 Phi { incoming=[b24:v75, b13:v79], kind=I64 } -> x3 + v82 LoadLocal { off=-18, kind=I64 } -> x0 + terminator Bz { cond=v81, target=b16, fall=b15 } (exit_acc=v81) block 15 start_pc=0 - v89 ImmData(127) -> x7 - v90 LoadLocal { off=-8, kind=F32 } -> d0 [f32] - v91 FpCast { kind=F32ToF64, value=v75 } -> d0 - v92 CallExt { binding_idx=0, args=[v89, v91], fp_arg_mask=0x2 } -> x0 - v93 Imm(4) -> x0 - terminator Return(v93) (exit_acc=v93) + v83 ImmData(127) -> x7 + v84 LoadLocal { off=-8, kind=F32 } -> d0 [f32] + v85 FpCast { kind=F32ToF64, value=v71 } -> d0 + v86 CallExt { binding_idx=0, args=[v83, v85], fp_arg_mask=0x2 } -> x0 + v87 Imm(4) -> x0 + terminator Return(v87) (exit_acc=v87) block 16 start_pc=0 - v94 Imm(4615514078110652826) -> x0 - v95 FpCast { kind=F64ToF32, value=v94 } -> d0 [f32] - v96 Imm(0) -> x0 - v97 LoadLocal { off=-9, kind=F32 } -> d1 [f32] - v98 FpCast { kind=F32ToF64, value=v95 } -> d0 - v99 FpCast { kind=FpToInt, value=v98 } -> x0 - v100 Imm(0) -> x1 - v101 Extend { value=v99, kind=I32 } -> x1 - v102 BinopI { op=ne, lhs=v101, rhs_imm=3 } -> x1 - terminator Bz { cond=v102, target=b18, fall=b17 } (exit_acc=v102) + v88 Imm(1080872141) -> x0 [f32] + v89 StoreLocal { off=-9, value=v88, kind=F32 } -> - + v90 LoadLocal { off=-9, kind=F32 } -> d0 [f32] + v91 FpCast { kind=F32ToF64, value=v90 } -> d0 + v92 FpCast { kind=FpToInt, value=v91 } -> x0 + v93 Imm(0) -> x1 + v94 Extend { value=v92, kind=I32 } -> x1 + v95 BinopI { op=ne, lhs=v94, rhs_imm=3 } -> x1 + terminator Bz { cond=v95, target=b18, fall=b17 } (exit_acc=v95) block 17 start_pc=0 - v103 ImmData(151) -> x7 - v104 Extend { value=v99, kind=I32 } -> x6 - v105 CallExt { binding_idx=0, args=[v103, v104], fp_arg_mask=0x0 } -> x0 - v106 Imm(5) -> x0 - terminator Return(v106) (exit_acc=v106) + v96 ImmData(151) -> x7 + v97 Extend { value=v92, kind=I32 } -> x6 + v98 CallExt { binding_idx=0, args=[v96, v97], fp_arg_mask=0x0 } -> x0 + v99 Imm(5) -> x0 + terminator Return(v99) (exit_acc=v99) block 18 start_pc=0 - v107 Imm(4613712638259704627) -> x0 - v108 Fneg(v107) -> d0 - v109 Imm(0) -> x0 - v110 LoadLocal { off=-11, kind=F64 } -> d1 - v111 FpCast { kind=FpToInt, value=v108 } -> x0 - v112 Imm(0) -> x1 - v113 Extend { value=v111, kind=I32 } -> x1 - v114 BinopI { op=ne, lhs=v113, rhs_imm=-2 } -> x1 - terminator Bz { cond=v114, target=b20, fall=b19 } (exit_acc=v114) + v100 Imm(4613712638259704627) -> x0 + v101 Fneg(v100) -> d0 + v102 Imm(0) -> x0 + v103 LoadLocal { off=-11, kind=F64 } -> d1 + v104 FpCast { kind=FpToInt, value=v101 } -> x0 + v105 Imm(0) -> x1 + v106 Extend { value=v104, kind=I32 } -> x1 + v107 BinopI { op=ne, lhs=v106, rhs_imm=-2 } -> x1 + terminator Bz { cond=v107, target=b20, fall=b19 } (exit_acc=v107) block 19 start_pc=0 - v115 ImmData(174) -> x7 - v116 Extend { value=v111, kind=I32 } -> x6 - v117 CallExt { binding_idx=0, args=[v115, v116], fp_arg_mask=0x0 } -> x0 - v118 Imm(6) -> x0 - terminator Return(v118) (exit_acc=v118) + v108 ImmData(174) -> x7 + v109 Extend { value=v104, kind=I32 } -> x6 + v110 CallExt { binding_idx=0, args=[v108, v109], fp_arg_mask=0x0 } -> x0 + v111 Imm(6) -> x0 + terminator Return(v111) (exit_acc=v111) block 20 start_pc=0 - v119 Imm(0) -> x0 - terminator Return(v119) (exit_acc=v119) + v112 Imm(0) -> x0 + terminator Return(v112) (exit_acc=v112) block 21 start_pc=0 terminator Jmp(b2) block 22 start_pc=0 diff --git a/tests/snapshots/ssa/logical_not_float.ssa b/tests/snapshots/ssa/logical_not_float.ssa index 69c0c0289..6f4b9129d 100644 --- a/tests/snapshots/ssa/logical_not_float.ssa +++ b/tests/snapshots/ssa/logical_not_float.ssa @@ -70,51 +70,49 @@ fn ent_pc=2 n_params=0 variadic=false locals=2 v25 Imm(4) -> x0 terminator Return(v25) (exit_acc=v25) block 8 start_pc=0 - v26 Imm(0) -> x0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Imm(0) -> x0 - v29 Imm(0) -> x0 - v30 FpCast { kind=F32ToF64, value=v27 } -> d0 - v31 Binop { op=feq, lhs=v30, rhs=v29 } -> x0 - v32 BinopI { op=ne, lhs=v31, rhs_imm=1 } -> x0 - terminator Bz { cond=v32, target=b10, fall=b9 } (exit_acc=v32) + v26 Imm(0) -> x0 [f32] + v27 Imm(0) -> x1 + v28 Imm(0) -> x1 + v29 FpCast { kind=F32ToF64, value=v26 } -> d0 + v30 Binop { op=feq, lhs=v29, rhs=v28 } -> x0 + v31 BinopI { op=ne, lhs=v30, rhs_imm=1 } -> x0 + terminator Bz { cond=v31, target=b10, fall=b9 } (exit_acc=v31) block 9 start_pc=0 - v33 Imm(5) -> x0 - terminator Return(v33) (exit_acc=v33) + v32 Imm(5) -> x0 + terminator Return(v32) (exit_acc=v32) block 10 start_pc=0 - v34 Imm(4615063718147915776) -> x0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 Imm(0) -> x0 - v37 Imm(0) -> x0 - v38 FpCast { kind=F32ToF64, value=v35 } -> d0 - v39 Binop { op=feq, lhs=v38, rhs=v37 } -> x0 - v40 BinopI { op=ne, lhs=v39, rhs_imm=0 } -> x0 - terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) + v33 Imm(1080033280) -> x0 [f32] + v34 Imm(0) -> x1 + v35 Imm(0) -> x1 + v36 FpCast { kind=F32ToF64, value=v33 } -> d0 + v37 Binop { op=feq, lhs=v36, rhs=v35 } -> x0 + v38 BinopI { op=ne, lhs=v37, rhs_imm=0 } -> x0 + terminator Bz { cond=v38, target=b12, fall=b11 } (exit_acc=v38) block 11 start_pc=0 - v41 Imm(6) -> x0 - terminator Return(v41) (exit_acc=v41) + v39 Imm(6) -> x0 + terminator Return(v39) (exit_acc=v39) block 12 start_pc=0 - v42 Imm(4611686018427387904) -> x0 - v43 StoreLocal { off=-1, value=v42, kind=F64 } -> - - v44 LoadLocal { off=-1, kind=F64 } -> d0 - v45 Imm(0) -> x0 - v46 Binop { op=feq, lhs=v44, rhs=v45 } -> x0 - terminator Bz { cond=v46, target=b14, fall=b13 } (exit_acc=v46) + v40 Imm(4611686018427387904) -> x0 + v41 StoreLocal { off=-1, value=v40, kind=F64 } -> - + v42 LoadLocal { off=-1, kind=F64 } -> d0 + v43 Imm(0) -> x0 + v44 Binop { op=feq, lhs=v42, rhs=v43 } -> x0 + terminator Bz { cond=v44, target=b14, fall=b13 } (exit_acc=v44) block 13 start_pc=0 - v47 Imm(7) -> x0 - terminator Return(v47) (exit_acc=v47) + v45 Imm(7) -> x0 + terminator Return(v45) (exit_acc=v45) block 14 start_pc=0 - v48 Imm(0) -> x0 - v49 StoreLocal { off=-2, value=v48, kind=F64 } -> - - v50 LoadLocal { off=-2, kind=F64 } -> d0 - v51 Binop { op=feq, lhs=v50, rhs=v48 } -> x0 - terminator Bz { cond=v51, target=b16, fall=b15 } (exit_acc=v51) + v46 Imm(0) -> x0 + v47 StoreLocal { off=-2, value=v46, kind=F64 } -> - + v48 LoadLocal { off=-2, kind=F64 } -> d0 + v49 Binop { op=feq, lhs=v48, rhs=v46 } -> x0 + terminator Bz { cond=v49, target=b16, fall=b15 } (exit_acc=v49) block 15 start_pc=0 - v52 Imm(0) -> x0 - terminator Return(v52) (exit_acc=v52) + v50 Imm(0) -> x0 + terminator Return(v50) (exit_acc=v50) block 16 start_pc=0 - v53 Imm(8) -> x0 - terminator Return(v53) (exit_acc=v53) + v51 Imm(8) -> x0 + terminator Return(v51) (exit_acc=v51) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/out_pointer_return_float_args.ssa b/tests/snapshots/ssa/out_pointer_return_float_args.ssa index 4ddff7ed4..02c6470c5 100644 --- a/tests/snapshots/ssa/out_pointer_return_float_args.ssa +++ b/tests/snapshots/ssa/out_pointer_return_float_args.ssa @@ -95,224 +95,206 @@ fn ent_pc=3 n_params=0 variadic=false locals=43 spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(4607182418800017408) -> x3 - v2 FpCast { kind=F64ToF32, value=v1 } -> d0 [f32] - v3 Imm(4611686018427387904) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d1 [f32] - v5 Imm(4613937818241073152) -> x0 - v6 FpCast { kind=F64ToF32, value=v5 } -> d2 [f32] - v7 Imm(4616189618054758400) -> x0 - v8 FpCast { kind=F64ToF32, value=v7 } -> d3 [f32] - v9 Call { target_pc=0, args=[v2, v4, v6, v8], fixed_args=4, fp_return=false, fp_arg_mask=0xf } -> x0 - v10 LocalAddr(-21) -> x0 - v11 LocalAddr(-2) -> x1 - v12 Mcpy { dst=v11, src=v10, size=16 } -> x0 - v13 LocalAddr(-2) -> x0 - v14 Load { addr=v13, disp=0, kind=F32 } -> d0 [f32] - v15 FpCast { kind=F32ToF64, value=v14 } -> d0 - v16 Binop { op=fne, lhs=v15, rhs=v1 } -> x0 - v17 Imm(1) -> x3 - v18 Imm(0) -> x1 - terminator Bnz { cond=v16, target=b25, fall=b1 } (exit_acc=v16) + v1 Imm(1065353216) -> x3 [f32] + v2 Imm(1073741824) -> x6 [f32] + v3 Imm(1077936128) -> x2 [f32] + v4 Imm(1082130432) -> x1 [f32] + v5 Call { target_pc=0, args=[v1, v2, v3, v4], fixed_args=4, fp_return=false, fp_arg_mask=0xf } -> x0 + v6 LocalAddr(-21) -> x0 + v7 LocalAddr(-2) -> x1 + v8 Mcpy { dst=v7, src=v6, size=16 } -> x0 + v9 LocalAddr(-2) -> x0 + v10 Load { addr=v9, disp=0, kind=F32 } -> d0 [f32] + v11 Binop { op=fne, lhs=v10, rhs=v1 } -> x0 + v12 Imm(1) -> x3 + v13 Imm(0) -> x1 + terminator Bnz { cond=v11, target=b25, fall=b1 } (exit_acc=v11) block 1 start_pc=0 - v19 LocalAddr(-2) -> x0 - v20 BinopI { op=add, lhs=v19, rhs_imm=4 } -> x1 - v21 Load { addr=v19, disp=4, kind=F32 } -> d0 [f32] - v22 Imm(4611686018427387904) -> x0 - v23 FpCast { kind=F32ToF64, value=v21 } -> d0 - v24 Binop { op=fne, lhs=v23, rhs=v22 } -> x0 - v25 BinopI { op=ne, lhs=v24, rhs_imm=0 } -> x3 - v26 Imm(0) -> x0 - terminator Jmp(b2) (exit_acc=v25) + v14 LocalAddr(-2) -> x0 + v15 BinopI { op=add, lhs=v14, rhs_imm=4 } -> x1 + v16 Load { addr=v14, disp=4, kind=F32 } -> d0 [f32] + v17 Imm(1073741824) -> x0 [f32] + v18 Binop { op=fne, lhs=v16, rhs=v17 } -> x0 + v19 BinopI { op=ne, lhs=v18, rhs_imm=0 } -> x3 + v20 Imm(0) -> x0 + terminator Jmp(b2) (exit_acc=v19) block 2 start_pc=0 - v27 Phi { incoming=[b25:v17, b1:v25], kind=I64 } -> x3 - v28 LoadLocal { off=-24, kind=I64 } -> x0 - v29 Imm(1) -> x12 - v30 Imm(0) -> x0 - terminator Bnz { cond=v27, target=b26, fall=b3 } (exit_acc=v27) + v21 Phi { incoming=[b25:v12, b1:v19], kind=I64 } -> x3 + v22 LoadLocal { off=-24, kind=I64 } -> x0 + v23 Imm(1) -> x12 + v24 Imm(0) -> x0 + terminator Bnz { cond=v21, target=b26, fall=b3 } (exit_acc=v21) block 3 start_pc=0 - v31 LocalAddr(-2) -> x0 - v32 BinopI { op=add, lhs=v31, rhs_imm=8 } -> x1 - v33 Load { addr=v31, disp=8, kind=F32 } -> d0 [f32] - v34 Imm(4613937818241073152) -> x0 - v35 FpCast { kind=F32ToF64, value=v33 } -> d0 - v36 Binop { op=fne, lhs=v35, rhs=v34 } -> x0 - v37 BinopI { op=ne, lhs=v36, rhs_imm=0 } -> x12 - v38 Imm(0) -> x0 - terminator Jmp(b4) (exit_acc=v37) + v25 LocalAddr(-2) -> x0 + v26 BinopI { op=add, lhs=v25, rhs_imm=8 } -> x1 + v27 Load { addr=v25, disp=8, kind=F32 } -> d0 [f32] + v28 Imm(1077936128) -> x0 [f32] + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + v30 BinopI { op=ne, lhs=v29, rhs_imm=0 } -> x12 + v31 Imm(0) -> x0 + terminator Jmp(b4) (exit_acc=v30) block 4 start_pc=0 - v39 Phi { incoming=[b26:v29, b3:v37], kind=I64 } -> x12 - v40 LoadLocal { off=-23, kind=I64 } -> x0 - v41 Imm(0) -> x0 - terminator Bnz { cond=v39, target=b27, fall=b5 } (exit_acc=v39) + v32 Phi { incoming=[b26:v23, b3:v30], kind=I64 } -> x12 + v33 LoadLocal { off=-23, kind=I64 } -> x0 + v34 Imm(0) -> x0 + terminator Bnz { cond=v32, target=b27, fall=b5 } (exit_acc=v32) block 5 start_pc=0 - v42 LocalAddr(-2) -> x0 - v43 BinopI { op=add, lhs=v42, rhs_imm=12 } -> x1 - v44 Load { addr=v42, disp=12, kind=F32 } -> d0 [f32] - v45 Imm(4616189618054758400) -> x0 - v46 FpCast { kind=F32ToF64, value=v44 } -> d0 - v47 Binop { op=fne, lhs=v46, rhs=v45 } -> x12 - v48 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v47) + v35 LocalAddr(-2) -> x0 + v36 BinopI { op=add, lhs=v35, rhs_imm=12 } -> x1 + v37 Load { addr=v35, disp=12, kind=F32 } -> d0 [f32] + v38 Imm(1082130432) -> x0 [f32] + v39 Binop { op=fne, lhs=v37, rhs=v38 } -> x12 + v40 Imm(0) -> x0 + terminator Jmp(b6) (exit_acc=v39) block 6 start_pc=0 - v49 Phi { incoming=[b27:v39, b5:v47], kind=I64 } -> x12 - v50 LoadLocal { off=-22, kind=I64 } -> x0 - terminator Bz { cond=v49, target=b8, fall=b7 } (exit_acc=v49) + v41 Phi { incoming=[b27:v32, b5:v39], kind=I64 } -> x12 + v42 LoadLocal { off=-22, kind=I64 } -> x0 + terminator Bz { cond=v41, target=b8, fall=b7 } (exit_acc=v41) block 7 start_pc=0 - v51 Imm(1) -> x0 - terminator Return(v51) (exit_acc=v51) + v43 Imm(1) -> x0 + terminator Return(v43) (exit_acc=v43) block 8 start_pc=0 - v52 LocalAddr(-27) -> x7 - v53 Imm(0) -> x0 - v54 LoadLocal { off=-28, kind=I64 } -> x0 - v55 Imm(4609434218613702656) -> x3 - v56 FpCast { kind=F64ToF32, value=v55 } -> d0 [f32] - v57 FpCast { kind=F32ToF64, value=v56 } -> d0 - v58 StoreLocal { off=-29, value=v57, kind=I64 } -> - - v59 LoadLocal { off=-29, kind=I64 } -> x6 - v60 Imm(4612811918334230528) -> x0 - v61 FpCast { kind=F64ToF32, value=v60 } -> d0 [f32] - v62 FpCast { kind=F32ToF64, value=v61 } -> d0 - v63 StoreLocal { off=-30, value=v62, kind=I64 } -> - - v64 LoadLocal { off=-30, kind=I64 } -> x2 - v65 Imm(4615063718147915776) -> x0 - v66 FpCast { kind=F64ToF32, value=v65 } -> d0 [f32] - v67 FpCast { kind=F32ToF64, value=v66 } -> d0 - v68 StoreLocal { off=-31, value=v67, kind=I64 } -> - - v69 LoadLocal { off=-31, kind=I64 } -> x1 - v70 Imm(4616752568008179712) -> x0 - v71 FpCast { kind=F64ToF32, value=v70 } -> d0 [f32] - v72 FpCast { kind=F32ToF64, value=v71 } -> d0 - v73 StoreLocal { off=-32, value=v72, kind=I64 } -> - - v74 LoadLocal { off=-32, kind=I64 } -> x8 - v75 Imm(4617878467915022336) -> x0 - v76 FpCast { kind=F64ToF32, value=v75 } -> d0 [f32] - v77 FpCast { kind=F32ToF64, value=v76 } -> d0 - v78 StoreLocal { off=-33, value=v77, kind=I64 } -> - - v79 LoadLocal { off=-33, kind=I64 } -> x9 - v80 Call { target_pc=1, args=[v52, v59, v64, v69, v74, v79], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 - v81 LocalAddr(-27) -> x0 - v82 LocalAddr(-7) -> x1 - v83 Mcpy { dst=v82, src=v81, size=20 } -> x0 - v84 LocalAddr(-7) -> x0 - v85 Load { addr=v84, disp=0, kind=F32 } -> d0 [f32] - v86 FpCast { kind=F32ToF64, value=v85 } -> d0 - v87 Binop { op=fne, lhs=v86, rhs=v55 } -> x0 - v88 Imm(1) -> x3 - v89 Imm(0) -> x1 - terminator Bnz { cond=v87, target=b28, fall=b9 } (exit_acc=v87) + v44 LocalAddr(-27) -> x7 + v45 Imm(0) -> x0 + v46 LoadLocal { off=-28, kind=I64 } -> x0 + v47 Imm(1069547520) -> x3 [f32] + v48 FpCast { kind=F32ToF64, value=v47 } -> d0 + v49 StoreLocal { off=-29, value=v48, kind=I64 } -> - + v50 LoadLocal { off=-29, kind=I64 } -> x6 + v51 Imm(1075838976) -> x0 [f32] + v52 FpCast { kind=F32ToF64, value=v51 } -> d0 + v53 StoreLocal { off=-30, value=v52, kind=I64 } -> - + v54 LoadLocal { off=-30, kind=I64 } -> x2 + v55 Imm(1080033280) -> x0 [f32] + v56 FpCast { kind=F32ToF64, value=v55 } -> d0 + v57 StoreLocal { off=-31, value=v56, kind=I64 } -> - + v58 LoadLocal { off=-31, kind=I64 } -> x1 + v59 Imm(1083179008) -> x0 [f32] + v60 FpCast { kind=F32ToF64, value=v59 } -> d0 + v61 StoreLocal { off=-32, value=v60, kind=I64 } -> - + v62 LoadLocal { off=-32, kind=I64 } -> x8 + v63 Imm(1085276160) -> x0 [f32] + v64 FpCast { kind=F32ToF64, value=v63 } -> d0 + v65 StoreLocal { off=-33, value=v64, kind=I64 } -> - + v66 LoadLocal { off=-33, kind=I64 } -> x9 + v67 Call { target_pc=1, args=[v44, v50, v54, v58, v62, v66], fixed_args=6, fp_return=false, fp_arg_mask=0x0 } -> x0 + v68 LocalAddr(-27) -> x0 + v69 LocalAddr(-7) -> x1 + v70 Mcpy { dst=v69, src=v68, size=20 } -> x0 + v71 LocalAddr(-7) -> x0 + v72 Load { addr=v71, disp=0, kind=F32 } -> d0 [f32] + v73 Binop { op=fne, lhs=v72, rhs=v47 } -> x0 + v74 Imm(1) -> x3 + v75 Imm(0) -> x1 + terminator Bnz { cond=v73, target=b28, fall=b9 } (exit_acc=v73) block 9 start_pc=0 - v90 LocalAddr(-7) -> x0 - v91 BinopI { op=add, lhs=v90, rhs_imm=4 } -> x1 - v92 Load { addr=v90, disp=4, kind=F32 } -> d0 [f32] - v93 Imm(4612811918334230528) -> x0 - v94 FpCast { kind=F32ToF64, value=v92 } -> d0 - v95 Binop { op=fne, lhs=v94, rhs=v93 } -> x0 - v96 BinopI { op=ne, lhs=v95, rhs_imm=0 } -> x3 - v97 Imm(0) -> x0 - terminator Jmp(b10) (exit_acc=v96) + v76 LocalAddr(-7) -> x0 + v77 BinopI { op=add, lhs=v76, rhs_imm=4 } -> x1 + v78 Load { addr=v76, disp=4, kind=F32 } -> d0 [f32] + v79 Imm(1075838976) -> x0 [f32] + v80 Binop { op=fne, lhs=v78, rhs=v79 } -> x0 + v81 BinopI { op=ne, lhs=v80, rhs_imm=0 } -> x3 + v82 Imm(0) -> x0 + terminator Jmp(b10) (exit_acc=v81) block 10 start_pc=0 - v98 Phi { incoming=[b28:v88, b9:v96], kind=I64 } -> x3 - v99 LoadLocal { off=-37, kind=I64 } -> x0 - v100 Imm(1) -> x12 - v101 Imm(0) -> x0 - terminator Bnz { cond=v98, target=b29, fall=b11 } (exit_acc=v98) + v83 Phi { incoming=[b28:v74, b9:v81], kind=I64 } -> x3 + v84 LoadLocal { off=-37, kind=I64 } -> x0 + v85 Imm(1) -> x12 + v86 Imm(0) -> x0 + terminator Bnz { cond=v83, target=b29, fall=b11 } (exit_acc=v83) block 11 start_pc=0 - v102 LocalAddr(-7) -> x0 - v103 BinopI { op=add, lhs=v102, rhs_imm=8 } -> x1 - v104 Load { addr=v102, disp=8, kind=F32 } -> d0 [f32] - v105 Imm(4615063718147915776) -> x0 - v106 FpCast { kind=F32ToF64, value=v104 } -> d0 - v107 Binop { op=fne, lhs=v106, rhs=v105 } -> x0 - v108 BinopI { op=ne, lhs=v107, rhs_imm=0 } -> x12 - v109 Imm(0) -> x0 - terminator Jmp(b12) (exit_acc=v108) + v87 LocalAddr(-7) -> x0 + v88 BinopI { op=add, lhs=v87, rhs_imm=8 } -> x1 + v89 Load { addr=v87, disp=8, kind=F32 } -> d0 [f32] + v90 Imm(1080033280) -> x0 [f32] + v91 Binop { op=fne, lhs=v89, rhs=v90 } -> x0 + v92 BinopI { op=ne, lhs=v91, rhs_imm=0 } -> x12 + v93 Imm(0) -> x0 + terminator Jmp(b12) (exit_acc=v92) block 12 start_pc=0 - v110 Phi { incoming=[b29:v100, b11:v108], kind=I64 } -> x12 - v111 LoadLocal { off=-36, kind=I64 } -> x0 - v112 Imm(1) -> x3 - v113 Imm(0) -> x0 - terminator Bnz { cond=v110, target=b30, fall=b13 } (exit_acc=v110) + v94 Phi { incoming=[b29:v85, b11:v92], kind=I64 } -> x12 + v95 LoadLocal { off=-36, kind=I64 } -> x0 + v96 Imm(1) -> x3 + v97 Imm(0) -> x0 + terminator Bnz { cond=v94, target=b30, fall=b13 } (exit_acc=v94) block 13 start_pc=0 - v114 LocalAddr(-7) -> x0 - v115 BinopI { op=add, lhs=v114, rhs_imm=12 } -> x1 - v116 Load { addr=v114, disp=12, kind=F32 } -> d0 [f32] - v117 Imm(4616752568008179712) -> x0 - v118 FpCast { kind=F32ToF64, value=v116 } -> d0 - v119 Binop { op=fne, lhs=v118, rhs=v117 } -> x0 - v120 BinopI { op=ne, lhs=v119, rhs_imm=0 } -> x3 - v121 Imm(0) -> x0 - terminator Jmp(b14) (exit_acc=v120) + v98 LocalAddr(-7) -> x0 + v99 BinopI { op=add, lhs=v98, rhs_imm=12 } -> x1 + v100 Load { addr=v98, disp=12, kind=F32 } -> d0 [f32] + v101 Imm(1083179008) -> x0 [f32] + v102 Binop { op=fne, lhs=v100, rhs=v101 } -> x0 + v103 BinopI { op=ne, lhs=v102, rhs_imm=0 } -> x3 + v104 Imm(0) -> x0 + terminator Jmp(b14) (exit_acc=v103) block 14 start_pc=0 - v122 Phi { incoming=[b30:v112, b13:v120], kind=I64 } -> x3 - v123 LoadLocal { off=-35, kind=I64 } -> x0 - v124 Imm(0) -> x0 - terminator Bnz { cond=v122, target=b31, fall=b15 } (exit_acc=v122) + v105 Phi { incoming=[b30:v96, b13:v103], kind=I64 } -> x3 + v106 LoadLocal { off=-35, kind=I64 } -> x0 + v107 Imm(0) -> x0 + terminator Bnz { cond=v105, target=b31, fall=b15 } (exit_acc=v105) block 15 start_pc=0 - v125 LocalAddr(-7) -> x0 - v126 BinopI { op=add, lhs=v125, rhs_imm=16 } -> x1 - v127 Load { addr=v125, disp=16, kind=F32 } -> d0 [f32] - v128 Imm(4617878467915022336) -> x0 - v129 FpCast { kind=F32ToF64, value=v127 } -> d0 - v130 Binop { op=fne, lhs=v129, rhs=v128 } -> x3 - v131 Imm(0) -> x0 - terminator Jmp(b16) (exit_acc=v130) + v108 LocalAddr(-7) -> x0 + v109 BinopI { op=add, lhs=v108, rhs_imm=16 } -> x1 + v110 Load { addr=v108, disp=16, kind=F32 } -> d0 [f32] + v111 Imm(1085276160) -> x0 [f32] + v112 Binop { op=fne, lhs=v110, rhs=v111 } -> x3 + v113 Imm(0) -> x0 + terminator Jmp(b16) (exit_acc=v112) block 16 start_pc=0 - v132 Phi { incoming=[b31:v122, b15:v130], kind=I64 } -> x3 - v133 LoadLocal { off=-34, kind=I64 } -> x0 - terminator Bz { cond=v132, target=b18, fall=b17 } (exit_acc=v132) + v114 Phi { incoming=[b31:v105, b15:v112], kind=I64 } -> x3 + v115 LoadLocal { off=-34, kind=I64 } -> x0 + terminator Bz { cond=v114, target=b18, fall=b17 } (exit_acc=v114) block 17 start_pc=0 - v134 Imm(2) -> x0 - terminator Return(v134) (exit_acc=v134) + v116 Imm(2) -> x0 + terminator Return(v116) (exit_acc=v116) block 18 start_pc=0 - v135 LocalAddr(-40) -> x7 - v136 Imm(0) -> x0 - v137 LoadLocal { off=-41, kind=I64 } -> x0 - v138 Imm(4621819117588971520) -> x3 - v139 Imm(4626322717216342016) -> x2 - v140 Imm(4629137466983448576) -> x1 - v141 Call { target_pc=2, args=[v135, v138, v139, v140], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 - v142 LocalAddr(-40) -> x0 - v143 LocalAddr(-13) -> x1 - v144 Mcpy { dst=v143, src=v142, size=24 } -> x0 - v145 LocalAddr(-13) -> x0 - v146 Load { addr=v145, disp=0, kind=F64 } -> d0 - v147 Binop { op=fne, lhs=v146, rhs=v138 } -> x0 - v148 Imm(1) -> x2 - v149 Imm(0) -> x1 - terminator Bnz { cond=v147, target=b32, fall=b19 } (exit_acc=v147) + v117 LocalAddr(-40) -> x7 + v118 Imm(0) -> x0 + v119 LoadLocal { off=-41, kind=I64 } -> x0 + v120 Imm(4621819117588971520) -> x3 + v121 Imm(4626322717216342016) -> x2 + v122 Imm(4629137466983448576) -> x1 + v123 Call { target_pc=2, args=[v117, v120, v121, v122], fixed_args=4, fp_return=false, fp_arg_mask=0x0 } -> x0 + v124 LocalAddr(-40) -> x0 + v125 LocalAddr(-13) -> x1 + v126 Mcpy { dst=v125, src=v124, size=24 } -> x0 + v127 LocalAddr(-13) -> x0 + v128 Load { addr=v127, disp=0, kind=F64 } -> d0 + v129 Binop { op=fne, lhs=v128, rhs=v120 } -> x0 + v130 Imm(1) -> x2 + v131 Imm(0) -> x1 + terminator Bnz { cond=v129, target=b32, fall=b19 } (exit_acc=v129) block 19 start_pc=0 - v150 LocalAddr(-13) -> x0 - v151 BinopI { op=add, lhs=v150, rhs_imm=8 } -> x1 - v152 Load { addr=v150, disp=8, kind=F64 } -> d0 - v153 Imm(4626322717216342016) -> x0 - v154 Binop { op=fne, lhs=v152, rhs=v153 } -> x0 - v155 BinopI { op=ne, lhs=v154, rhs_imm=0 } -> x2 - v156 Imm(0) -> x0 - terminator Jmp(b20) (exit_acc=v155) + v132 LocalAddr(-13) -> x0 + v133 BinopI { op=add, lhs=v132, rhs_imm=8 } -> x1 + v134 Load { addr=v132, disp=8, kind=F64 } -> d0 + v135 Imm(4626322717216342016) -> x0 + v136 Binop { op=fne, lhs=v134, rhs=v135 } -> x0 + v137 BinopI { op=ne, lhs=v136, rhs_imm=0 } -> x2 + v138 Imm(0) -> x0 + terminator Jmp(b20) (exit_acc=v137) block 20 start_pc=0 - v157 Phi { incoming=[b32:v148, b19:v155], kind=I64 } -> x2 - v158 LoadLocal { off=-43, kind=I64 } -> x0 - v159 Imm(0) -> x0 - terminator Bnz { cond=v157, target=b33, fall=b21 } (exit_acc=v157) + v139 Phi { incoming=[b32:v130, b19:v137], kind=I64 } -> x2 + v140 LoadLocal { off=-43, kind=I64 } -> x0 + v141 Imm(0) -> x0 + terminator Bnz { cond=v139, target=b33, fall=b21 } (exit_acc=v139) block 21 start_pc=0 - v160 LocalAddr(-13) -> x0 - v161 BinopI { op=add, lhs=v160, rhs_imm=16 } -> x1 - v162 Load { addr=v160, disp=16, kind=F64 } -> d0 - v163 Imm(4629137466983448576) -> x0 - v164 Binop { op=fne, lhs=v162, rhs=v163 } -> x2 - v165 Imm(0) -> x0 - terminator Jmp(b22) (exit_acc=v164) + v142 LocalAddr(-13) -> x0 + v143 BinopI { op=add, lhs=v142, rhs_imm=16 } -> x1 + v144 Load { addr=v142, disp=16, kind=F64 } -> d0 + v145 Imm(4629137466983448576) -> x0 + v146 Binop { op=fne, lhs=v144, rhs=v145 } -> x2 + v147 Imm(0) -> x0 + terminator Jmp(b22) (exit_acc=v146) block 22 start_pc=0 - v166 Phi { incoming=[b33:v157, b21:v164], kind=I64 } -> x2 - v167 LoadLocal { off=-42, kind=I64 } -> x0 - terminator Bz { cond=v166, target=b24, fall=b23 } (exit_acc=v166) + v148 Phi { incoming=[b33:v139, b21:v146], kind=I64 } -> x2 + v149 LoadLocal { off=-42, kind=I64 } -> x0 + terminator Bz { cond=v148, target=b24, fall=b23 } (exit_acc=v148) block 23 start_pc=0 - v168 Imm(3) -> x0 - terminator Return(v168) (exit_acc=v168) + v150 Imm(3) -> x0 + terminator Return(v150) (exit_acc=v150) block 24 start_pc=0 - v169 Imm(0) -> x0 - terminator Return(v169) (exit_acc=v169) + v151 Imm(0) -> x0 + terminator Return(v151) (exit_acc=v151) block 25 start_pc=0 terminator Jmp(b2) block 26 start_pc=0 diff --git a/tests/snapshots/ssa/param_fp_before_int_pressure.ssa b/tests/snapshots/ssa/param_fp_before_int_pressure.ssa index c3680483f..f8706193d 100644 --- a/tests/snapshots/ssa/param_fp_before_int_pressure.ssa +++ b/tests/snapshots/ssa/param_fp_before_int_pressure.ssa @@ -67,75 +67,74 @@ fn ent_pc=0 n_params=8 variadic=false locals=2 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=9 - spill_count=0 gpr_used=[] fp_used=[] + spill_count=0 gpr_used=[3] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(7) -> x0 v2 StoreLocal { off=-1, value=v1, kind=I32 } -> - - v3 Imm(0) -> x0 - v4 FpCast { kind=F64ToF32, value=v3 } -> d0 [f32] - v5 Imm(1) -> x0 - v6 Imm(2) -> x1 - v7 Imm(3) -> x2 - v8 LocalAddr(-1) -> x6 - v9 Imm(4) -> x7 - v10 Imm(5) -> x8 - v11 Extend { value=v5, kind=I32 } -> x9 - v12 Imm(0) -> x9 - v13 Extend { value=v6, kind=I32 } -> x9 - v14 Imm(0) -> x9 - v15 Extend { value=v7, kind=I32 } -> x9 - v16 Imm(0) -> x9 - v17 Imm(0) -> x9 - v18 Extend { value=v9, kind=I32 } -> x9 - v19 Imm(0) -> x9 - v20 Extend { value=v10, kind=I32 } -> x9 - v21 Imm(0) -> x9 - v22 Imm(0) -> x9 - v23 Imm(0) -> x9 - v24 FpCast { kind=F32ToF64, value=v4 } -> d1 - v25 FpCast { kind=FpToInt, value=v24 } -> x9 - v26 FpCast { kind=F32ToF64, value=v4 } -> d0 - v27 FpCast { kind=FpToInt, value=v26 } -> x9 - v28 BinopI { op=mul, lhs=v5, rhs_imm=100000 } -> x0 - v29 BinopI { op=shl, lhs=v28, rhs_imm=32 } -> x9 - v30 Extend { value=v28, kind=I32 } -> x9 - v31 BinopI { op=mul, lhs=v6, rhs_imm=10000 } -> x1 - v32 BinopI { op=shl, lhs=v31, rhs_imm=32 } -> x9 - v33 Extend { value=v31, kind=I32 } -> x9 - v34 Binop { op=add, lhs=v28, rhs=v31 } -> x0 - v35 BinopI { op=shl, lhs=v34, rhs_imm=32 } -> x1 - v36 Extend { value=v34, kind=I32 } -> x1 - v37 BinopI { op=mul, lhs=v7, rhs_imm=1000 } -> x1 - v38 BinopI { op=shl, lhs=v37, rhs_imm=32 } -> x2 - v39 Extend { value=v37, kind=I32 } -> x2 - v40 Binop { op=add, lhs=v34, rhs=v37 } -> x0 - v41 BinopI { op=shl, lhs=v40, rhs_imm=32 } -> x1 - v42 Extend { value=v40, kind=I32 } -> x1 - v43 Load { addr=v8, disp=0, kind=I32 } -> x1 - v44 BinopI { op=mul, lhs=v43, rhs_imm=100 } -> x1 - v45 BinopI { op=shl, lhs=v44, rhs_imm=32 } -> x2 - v46 Extend { value=v44, kind=I32 } -> x2 - v47 Binop { op=add, lhs=v40, rhs=v44 } -> x0 - v48 BinopI { op=shl, lhs=v47, rhs_imm=32 } -> x1 - v49 Extend { value=v47, kind=I32 } -> x1 - v50 BinopI { op=mul, lhs=v9, rhs_imm=10 } -> x1 - v51 BinopI { op=shl, lhs=v50, rhs_imm=32 } -> x2 - v52 Extend { value=v50, kind=I32 } -> x2 - v53 Binop { op=add, lhs=v47, rhs=v50 } -> x0 - v54 BinopI { op=shl, lhs=v53, rhs_imm=32 } -> x1 - v55 Extend { value=v53, kind=I32 } -> x1 - v56 Binop { op=add, lhs=v53, rhs=v10 } -> x0 - v57 BinopI { op=shl, lhs=v56, rhs_imm=32 } -> x1 - v58 Extend { value=v56, kind=I32 } -> x0 - v59 BinopI { op=ne, lhs=v58, rhs_imm=123745 } -> x0 - terminator Bz { cond=v59, target=b2, fall=b1 } (exit_acc=v59) + v3 Imm(0) -> x0 [f32] + v4 Imm(1) -> x1 + v5 Imm(2) -> x2 + v6 Imm(3) -> x6 + v7 LocalAddr(-1) -> x7 + v8 Imm(4) -> x8 + v9 Imm(5) -> x9 + v10 Extend { value=v4, kind=I32 } -> x3 + v11 Imm(0) -> x3 + v12 Extend { value=v5, kind=I32 } -> x3 + v13 Imm(0) -> x3 + v14 Extend { value=v6, kind=I32 } -> x3 + v15 Imm(0) -> x3 + v16 Imm(0) -> x3 + v17 Extend { value=v8, kind=I32 } -> x3 + v18 Imm(0) -> x3 + v19 Extend { value=v9, kind=I32 } -> x3 + v20 Imm(0) -> x3 + v21 Imm(0) -> x3 + v22 Imm(0) -> x3 + v23 FpCast { kind=F32ToF64, value=v3 } -> d0 + v24 FpCast { kind=FpToInt, value=v23 } -> x3 + v25 FpCast { kind=F32ToF64, value=v3 } -> d0 + v26 FpCast { kind=FpToInt, value=v25 } -> x0 + v27 BinopI { op=mul, lhs=v4, rhs_imm=100000 } -> x0 + v28 BinopI { op=shl, lhs=v27, rhs_imm=32 } -> x1 + v29 Extend { value=v27, kind=I32 } -> x1 + v30 BinopI { op=mul, lhs=v5, rhs_imm=10000 } -> x1 + v31 BinopI { op=shl, lhs=v30, rhs_imm=32 } -> x2 + v32 Extend { value=v30, kind=I32 } -> x2 + v33 Binop { op=add, lhs=v27, rhs=v30 } -> x0 + v34 BinopI { op=shl, lhs=v33, rhs_imm=32 } -> x1 + v35 Extend { value=v33, kind=I32 } -> x1 + v36 BinopI { op=mul, lhs=v6, rhs_imm=1000 } -> x1 + v37 BinopI { op=shl, lhs=v36, rhs_imm=32 } -> x2 + v38 Extend { value=v36, kind=I32 } -> x2 + v39 Binop { op=add, lhs=v33, rhs=v36 } -> x0 + v40 BinopI { op=shl, lhs=v39, rhs_imm=32 } -> x1 + v41 Extend { value=v39, kind=I32 } -> x1 + v42 Load { addr=v7, disp=0, kind=I32 } -> x1 + v43 BinopI { op=mul, lhs=v42, rhs_imm=100 } -> x1 + v44 BinopI { op=shl, lhs=v43, rhs_imm=32 } -> x2 + v45 Extend { value=v43, kind=I32 } -> x2 + v46 Binop { op=add, lhs=v39, rhs=v43 } -> x0 + v47 BinopI { op=shl, lhs=v46, rhs_imm=32 } -> x1 + v48 Extend { value=v46, kind=I32 } -> x1 + v49 BinopI { op=mul, lhs=v8, rhs_imm=10 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=32 } -> x2 + v51 Extend { value=v49, kind=I32 } -> x2 + v52 Binop { op=add, lhs=v46, rhs=v49 } -> x0 + v53 BinopI { op=shl, lhs=v52, rhs_imm=32 } -> x1 + v54 Extend { value=v52, kind=I32 } -> x1 + v55 Binop { op=add, lhs=v52, rhs=v9 } -> x0 + v56 BinopI { op=shl, lhs=v55, rhs_imm=32 } -> x1 + v57 Extend { value=v55, kind=I32 } -> x0 + v58 BinopI { op=ne, lhs=v57, rhs_imm=123745 } -> x0 + terminator Bz { cond=v58, target=b2, fall=b1 } (exit_acc=v58) block 1 start_pc=0 - v60 Imm(1) -> x0 - terminator Return(v60) (exit_acc=v60) + v59 Imm(1) -> x0 + terminator Return(v59) (exit_acc=v59) block 2 start_pc=0 - v61 Imm(0) -> x0 - terminator Return(v61) (exit_acc=v61) + v60 Imm(0) -> x0 + terminator Return(v60) (exit_acc=v60) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/ternary_arith_conversion.ssa b/tests/snapshots/ssa/ternary_arith_conversion.ssa index f86ce101d..dc6edf271 100644 --- a/tests/snapshots/ssa/ternary_arith_conversion.ssa +++ b/tests/snapshots/ssa/ternary_arith_conversion.ssa @@ -91,123 +91,127 @@ fn ent_pc=0 n_params=0 variadic=false locals=13 v45 LoadLocal { off=-1, kind=I32 } -> x2 terminator Jmp(b21) (exit_acc=v1) block 21 start_pc=0 - v46 Imm(4607182418800017408) -> x2 - v47 StoreLocal { off=-8, value=v46, kind=F64 } -> - - terminator Jmp(b23) (exit_acc=v47) + v46 Imm(1065353216) -> x2 [f32] + v47 FpCast { kind=F32ToF64, value=v46 } -> d0 + v48 StoreLocal { off=-8, value=v47, kind=F64 } -> - + terminator Jmp(b23) (exit_acc=v48) block 22 start_pc=0 - v48 Imm(4611686018427387904) -> x2 - v49 StoreLocal { off=-8, value=v48, kind=F64 } -> - - terminator Jmp(b23) (exit_acc=v49) + v49 Imm(4611686018427387904) -> x2 + v50 StoreLocal { off=-8, value=v49, kind=F64 } -> - + terminator Jmp(b23) (exit_acc=v50) block 23 start_pc=0 - v50 LoadLocal { off=-8, kind=F64 } -> d0 - v51 Imm(4607182418800017408) -> x2 - v52 Binop { op=fne, lhs=v50, rhs=v51 } -> x2 - terminator Bz { cond=v52, target=b25, fall=b24 } (exit_acc=v52) + v51 LoadLocal { off=-8, kind=F64 } -> d0 + v52 Imm(4607182418800017408) -> x2 + v53 Binop { op=fne, lhs=v51, rhs=v52 } -> x2 + terminator Bz { cond=v53, target=b25, fall=b24 } (exit_acc=v53) block 24 start_pc=0 - v53 Imm(15) -> x0 - terminator Return(v53) (exit_acc=v53) + v54 Imm(15) -> x0 + terminator Return(v54) (exit_acc=v54) block 25 start_pc=0 - v54 LoadLocal { off=-2, kind=I32 } -> x2 + v55 LoadLocal { off=-2, kind=I32 } -> x2 terminator Jmp(b27) (exit_acc=v3) block 26 start_pc=0 - v55 Imm(4607182418800017408) -> x2 - v56 StoreLocal { off=-9, value=v55, kind=F64 } -> - - terminator Jmp(b28) (exit_acc=v56) - block 27 start_pc=0 - v57 Imm(4611686018427387904) -> x2 + v56 Imm(1065353216) -> x2 [f32] + v57 FpCast { kind=F32ToF64, value=v56 } -> d0 v58 StoreLocal { off=-9, value=v57, kind=F64 } -> - terminator Jmp(b28) (exit_acc=v58) + block 27 start_pc=0 + v59 Imm(4611686018427387904) -> x2 + v60 StoreLocal { off=-9, value=v59, kind=F64 } -> - + terminator Jmp(b28) (exit_acc=v60) block 28 start_pc=0 - v59 LoadLocal { off=-9, kind=F64 } -> d0 - v60 Imm(4611686018427387904) -> x2 - v61 Binop { op=fne, lhs=v59, rhs=v60 } -> x2 - terminator Bz { cond=v61, target=b30, fall=b29 } (exit_acc=v61) + v61 LoadLocal { off=-9, kind=F64 } -> d0 + v62 Imm(4611686018427387904) -> x2 + v63 Binop { op=fne, lhs=v61, rhs=v62 } -> x2 + terminator Bz { cond=v63, target=b30, fall=b29 } (exit_acc=v63) block 29 start_pc=0 - v62 Imm(16) -> x0 - terminator Return(v62) (exit_acc=v62) + v64 Imm(16) -> x0 + terminator Return(v64) (exit_acc=v64) block 30 start_pc=0 - v63 LoadLocal { off=-1, kind=I32 } -> x2 + v65 LoadLocal { off=-1, kind=I32 } -> x2 terminator Jmp(b31) (exit_acc=v1) block 31 start_pc=0 - v64 Imm(4607182418800017408) -> x2 - v65 StoreLocal { off=-10, value=v64, kind=F64 } -> - - terminator Jmp(b33) (exit_acc=v65) + v66 Imm(1065353216) -> x2 [f32] + v67 StoreLocal { off=-10, value=v66, kind=F32 } -> - + terminator Jmp(b33) (exit_acc=v67) block 32 start_pc=0 - v66 Imm(2) -> x2 - v67 FpCast { kind=IntToFp, value=v66 } -> d0 - v68 StoreLocal { off=-10, value=v67, kind=F64 } -> - - terminator Jmp(b33) (exit_acc=v68) + v68 Imm(2) -> x2 + v69 FpCast { kind=IntToFp, value=v68 } -> d0 + v70 FpCast { kind=F64ToF32, value=v69 } -> d0 [f32] + v71 StoreLocal { off=-10, value=v70, kind=F32 } -> - + terminator Jmp(b33) (exit_acc=v71) block 33 start_pc=0 - v69 LoadLocal { off=-10, kind=F64 } -> d0 - v70 Imm(4607182418800017408) -> x2 - v71 Binop { op=fne, lhs=v69, rhs=v70 } -> x2 - terminator Bz { cond=v71, target=b35, fall=b34 } (exit_acc=v71) + v72 LoadLocal { off=-10, kind=F32 } -> d0 [f32] + v73 Imm(1065353216) -> x2 [f32] + v74 Binop { op=fne, lhs=v72, rhs=v73 } -> x2 + terminator Bz { cond=v74, target=b35, fall=b34 } (exit_acc=v74) block 34 start_pc=0 - v72 Imm(17) -> x0 - terminator Return(v72) (exit_acc=v72) + v75 Imm(17) -> x0 + terminator Return(v75) (exit_acc=v75) block 35 start_pc=0 - v73 LoadLocal { off=-2, kind=I32 } -> x2 + v76 LoadLocal { off=-2, kind=I32 } -> x2 terminator Jmp(b37) (exit_acc=v3) block 36 start_pc=0 - v74 Imm(4607182418800017408) -> x2 - v75 StoreLocal { off=-11, value=v74, kind=F64 } -> - - terminator Jmp(b38) (exit_acc=v75) - block 37 start_pc=0 - v76 Imm(2) -> x2 - v77 FpCast { kind=IntToFp, value=v76 } -> d0 - v78 StoreLocal { off=-11, value=v77, kind=F64 } -> - + v77 Imm(1065353216) -> x2 [f32] + v78 StoreLocal { off=-11, value=v77, kind=F32 } -> - terminator Jmp(b38) (exit_acc=v78) + block 37 start_pc=0 + v79 Imm(2) -> x2 + v80 FpCast { kind=IntToFp, value=v79 } -> d0 + v81 FpCast { kind=F64ToF32, value=v80 } -> d0 [f32] + v82 StoreLocal { off=-11, value=v81, kind=F32 } -> - + terminator Jmp(b38) (exit_acc=v82) block 38 start_pc=0 - v79 LoadLocal { off=-11, kind=F64 } -> d0 - v80 Imm(4611686018427387904) -> x2 - v81 Binop { op=fne, lhs=v79, rhs=v80 } -> x2 - terminator Bz { cond=v81, target=b40, fall=b39 } (exit_acc=v81) + v83 LoadLocal { off=-11, kind=F32 } -> d0 [f32] + v84 Imm(1073741824) -> x2 [f32] + v85 Binop { op=fne, lhs=v83, rhs=v84 } -> x2 + terminator Bz { cond=v85, target=b40, fall=b39 } (exit_acc=v85) block 39 start_pc=0 - v82 Imm(18) -> x0 - terminator Return(v82) (exit_acc=v82) + v86 Imm(18) -> x0 + terminator Return(v86) (exit_acc=v86) block 40 start_pc=0 - v83 LoadLocal { off=-1, kind=I32 } -> x2 + v87 LoadLocal { off=-1, kind=I32 } -> x2 terminator Jmp(b41) (exit_acc=v1) block 41 start_pc=0 - v84 Imm(10) -> x2 - v85 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v84) + v88 Imm(10) -> x2 + v89 Imm(0) -> x0 + terminator Jmp(b43) (exit_acc=v88) block 42 start_pc=0 - v86 Imm(20) -> x2 - v87 Imm(0) -> x0 - terminator Jmp(b43) (exit_acc=v86) + v90 Imm(20) -> x2 + v91 Imm(0) -> x0 + terminator Jmp(b43) (exit_acc=v90) block 43 start_pc=0 - v88 Phi { incoming=[b41:v84, b42:v86], kind=I64 } -> x2 - v89 LoadLocal { off=-12, kind=I64 } -> x0 - v90 BinopI { op=ne, lhs=v88, rhs_imm=10 } -> x0 - terminator Bz { cond=v90, target=b45, fall=b44 } (exit_acc=v90) + v92 Phi { incoming=[b41:v88, b42:v90], kind=I64 } -> x2 + v93 LoadLocal { off=-12, kind=I64 } -> x0 + v94 BinopI { op=ne, lhs=v92, rhs_imm=10 } -> x0 + terminator Bz { cond=v94, target=b45, fall=b44 } (exit_acc=v94) block 44 start_pc=0 - v91 Imm(21) -> x0 - terminator Return(v91) (exit_acc=v91) + v95 Imm(21) -> x0 + terminator Return(v95) (exit_acc=v95) block 45 start_pc=0 - v92 LoadLocal { off=-2, kind=I32 } -> x0 + v96 LoadLocal { off=-2, kind=I32 } -> x0 terminator Jmp(b47) (exit_acc=v3) block 46 start_pc=0 - v93 Imm(1) -> x1 - v94 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v93) + v97 Imm(1) -> x1 + v98 Imm(0) -> x0 + terminator Jmp(b48) (exit_acc=v97) block 47 start_pc=0 - v95 Imm(2) -> x1 - v96 Imm(0) -> x0 - terminator Jmp(b48) (exit_acc=v95) + v99 Imm(2) -> x1 + v100 Imm(0) -> x0 + terminator Jmp(b48) (exit_acc=v99) block 48 start_pc=0 - v97 Phi { incoming=[b46:v93, b47:v95], kind=I64 } -> x1 - v98 LoadLocal { off=-13, kind=I64 } -> x0 - v99 Imm(0) -> x0 - v100 LoadLocal { off=-3, kind=I64 } -> x0 - v101 BinopI { op=ne, lhs=v97, rhs_imm=2 } -> x0 - terminator Bz { cond=v101, target=b50, fall=b49 } (exit_acc=v101) + v101 Phi { incoming=[b46:v97, b47:v99], kind=I64 } -> x1 + v102 LoadLocal { off=-13, kind=I64 } -> x0 + v103 Imm(0) -> x0 + v104 LoadLocal { off=-3, kind=I64 } -> x0 + v105 BinopI { op=ne, lhs=v101, rhs_imm=2 } -> x0 + terminator Bz { cond=v105, target=b50, fall=b49 } (exit_acc=v105) block 49 start_pc=0 - v102 Imm(22) -> x0 - terminator Return(v102) (exit_acc=v102) + v106 Imm(22) -> x0 + terminator Return(v106) (exit_acc=v106) block 50 start_pc=0 - v103 Imm(0) -> x0 - terminator Return(v103) (exit_acc=v103) + v107 Imm(0) -> x0 + terminator Return(v107) (exit_acc=v107) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa index 541fe722d..ba6088bae 100644 --- a/tests/snapshots/ssa/two_d_float_array_partial_init.ssa +++ b/tests/snapshots/ssa/two_d_float_array_partial_init.ssa @@ -62,7 +62,7 @@ fn ent_pc=0 n_params=1 variadic=false locals=6 ; --- SSA dump (ok=true) ent_pc=1 --- ; name=main fn ent_pc=1 n_params=0 variadic=false locals=8 - spill_count=1 gpr_used=[3, 12] fp_used=[] + spill_count=0 gpr_used=[3, 12] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 Imm(0) -> x3 @@ -83,11 +83,11 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 v10 Imm(0) -> x0 terminator Jmp(b5) (exit_acc=v9) block 4 start_pc=0 - v11 Imm(0) -> x1 - v12 FpCast { kind=F64ToF32, value=v11 } -> [spill 0] [f32] - v13 Imm(0) -> x0 + v11 Imm(0) -> x0 [f32] + v12 StoreLocal { off=-3, value=v11, kind=F32 } -> - + v13 Imm(0) -> x1 v14 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v11) + terminator Jmp(b11) (exit_acc=v13) block 5 start_pc=0 v15 Phi { incoming=[b3:v9, b6:v19], kind=I64 } -> x12 v16 Extend { value=v15, kind=I32 } -> x0 @@ -139,53 +139,51 @@ fn ent_pc=1 n_params=0 variadic=false locals=8 block 10 start_pc=0 terminator Jmp(b6) block 11 start_pc=0 - v53 Phi { incoming=[b4:v12, b12:v75], kind=F32 } -> [spill 0] [f32] - v54 Phi { incoming=[b4:v11, b12:v58], kind=I64 } -> x1 - v55 Extend { value=v54, kind=I32 } -> x0 - v56 BinopI { op=lt, lhs=v55, rhs_imm=12 } -> x0 - terminator Bz { cond=v56, target=b14, fall=b13 } (exit_acc=v56) + v53 Phi { incoming=[b4:v13, b12:v57], kind=I64 } -> x1 + v54 Extend { value=v53, kind=I32 } -> x0 + v55 BinopI { op=lt, lhs=v54, rhs_imm=12 } -> x0 + terminator Bz { cond=v55, target=b14, fall=b13 } (exit_acc=v55) block 12 start_pc=0 - v57 Extend { value=v54, kind=I32 } -> x0 - v58 BinopI { op=add, lhs=v57, rhs_imm=1 } -> x1 - v59 Imm(0) -> x0 - terminator Jmp(b11) (exit_acc=v58) + v56 Extend { value=v53, kind=I32 } -> x0 + v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x1 + v58 Imm(0) -> x0 + terminator Jmp(b11) (exit_acc=v57) block 13 start_pc=0 - v60 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v61 ImmData(56) -> x0 - v62 Extend { value=v54, kind=I32 } -> x2 - v63 BinopI { op=shl, lhs=v62, rhs_imm=4 } -> x2 - v64 Binop { op=add, lhs=v61, rhs=v63 } -> x0 - v65 Imm(0) -> x2 - v66 Load { addr=v64, disp=0, kind=F32 } -> d0 [f32] - v67 Imm(4) -> x2 - v68 BinopI { op=add, lhs=v64, rhs_imm=4 } -> x2 - v69 Load { addr=v64, disp=4, kind=F32 } -> d1 [f32] - v70 Binop { op=fadd, lhs=v66, rhs=v69 } -> d0 [f32] - v71 Imm(8) -> x2 - v72 BinopI { op=add, lhs=v64, rhs_imm=8 } -> x2 - v73 Load { addr=v64, disp=8, kind=F32 } -> d1 [f32] - v74 Binop { op=fadd, lhs=v70, rhs=v73 } -> d0 [f32] - v75 Binop { op=fadd, lhs=v53, rhs=v74 } -> [spill 0] [f32] - v76 Imm(0) -> x0 - v77 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - terminator Jmp(b12) (exit_acc=v75) + v59 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v60 ImmData(56) -> x0 + v61 Extend { value=v53, kind=I32 } -> x2 + v62 BinopI { op=shl, lhs=v61, rhs_imm=4 } -> x2 + v63 Binop { op=add, lhs=v60, rhs=v62 } -> x0 + v64 Imm(0) -> x2 + v65 Load { addr=v63, disp=0, kind=F32 } -> d1 [f32] + v66 Imm(4) -> x2 + v67 BinopI { op=add, lhs=v63, rhs_imm=4 } -> x2 + v68 Load { addr=v63, disp=4, kind=F32 } -> d2 [f32] + v69 Binop { op=fadd, lhs=v65, rhs=v68 } -> d1 [f32] + v70 Imm(8) -> x2 + v71 BinopI { op=add, lhs=v63, rhs_imm=8 } -> x2 + v72 Load { addr=v63, disp=8, kind=F32 } -> d2 [f32] + v73 Binop { op=fadd, lhs=v69, rhs=v72 } -> d1 [f32] + v74 Binop { op=fadd, lhs=v59, rhs=v73 } -> d0 [f32] + v75 StoreLocal { off=-3, value=v74, kind=F32 } -> - + v76 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + terminator Jmp(b12) (exit_acc=v76) block 14 start_pc=0 - v78 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v79 Imm(0) -> x0 - v80 FpCast { kind=F32ToF64, value=v53 } -> d0 - v81 Binop { op=fne, lhs=v80, rhs=v79 } -> x0 - terminator Bz { cond=v81, target=b16, fall=b15 } (exit_acc=v81) + v77 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v78 Imm(0) -> x0 [f32] + v79 Binop { op=fne, lhs=v77, rhs=v78 } -> x0 + terminator Bz { cond=v79, target=b16, fall=b15 } (exit_acc=v79) block 15 start_pc=0 - v82 Imm(2) -> x3 - v83 Call { target_pc=0, args=[v82], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 - v84 ImmData(470) -> x6 - v85 LoadLocal { off=-3, kind=F32 } -> d0 [f32] - v86 FpCast { kind=F32ToF64, value=v53 } -> d0 - v87 CallExt { binding_idx=1, args=[v83, v84, v86], fp_arg_mask=0x4 } -> x0 - terminator Return(v82) (exit_acc=v82) + v80 Imm(2) -> x3 + v81 Call { target_pc=0, args=[v80], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x7 + v82 ImmData(470) -> x6 + v83 LoadLocal { off=-3, kind=F32 } -> d0 [f32] + v84 FpCast { kind=F32ToF64, value=v83 } -> d0 + v85 CallExt { binding_idx=1, args=[v81, v82, v84], fp_arg_mask=0x4 } -> x0 + terminator Return(v80) (exit_acc=v80) block 16 start_pc=0 - v88 Imm(0) -> x0 - terminator Return(v88) (exit_acc=v88) + v86 Imm(0) -> x0 + terminator Return(v86) (exit_acc=v86) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa b/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa index cee3c4bbe..635dcef2c 100644 --- a/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa +++ b/tests/snapshots/ssa/two_d_stride_no_leak_across_exprs.ssa @@ -57,46 +57,41 @@ fn ent_pc=2 n_params=0 variadic=false locals=163 v29 Binop { op=add, lhs=v26, rhs=v28 } -> x0 v30 FpCast { kind=IntToFp, value=v27 } -> d0 v31 FpCast { kind=F64ToF32, value=v30 } -> d0 [f32] - v32 Imm(4598175219545276416) -> x2 - v33 FpCast { kind=F32ToF64, value=v31 } -> d0 - v34 Binop { op=fmul, lhs=v33, rhs=v32 } -> d0 - v35 FpCast { kind=F64ToF32, value=v34 } -> d0 [f32] - v36 Store { addr=v29, disp=0, value=v35, kind=F32 } -> - - terminator Jmp(b4) (exit_acc=v36) + v32 Imm(1048576000) -> x2 [f32] + v33 Binop { op=fmul, lhs=v31, rhs=v32 } -> d0 [f32] + v34 Store { addr=v29, disp=0, value=v33, kind=F32 } -> - + terminator Jmp(b4) (exit_acc=v34) block 6 start_pc=0 - v37 LocalAddr(-161) -> x0 - v38 Imm(32) -> x1 - v39 BinopI { op=add, lhs=v37, rhs_imm=32 } -> x1 - v40 Load { addr=v37, disp=32, kind=F32 } -> d0 [f32] - v41 Imm(4611686018427387904) -> x0 - v42 FpCast { kind=F32ToF64, value=v40 } -> d0 - v43 Binop { op=fne, lhs=v42, rhs=v41 } -> x0 - terminator Bz { cond=v43, target=b8, fall=b7 } (exit_acc=v43) + v35 LocalAddr(-161) -> x0 + v36 Imm(32) -> x1 + v37 BinopI { op=add, lhs=v35, rhs_imm=32 } -> x1 + v38 Load { addr=v35, disp=32, kind=F32 } -> d0 [f32] + v39 Imm(1073741824) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b8, fall=b7 } (exit_acc=v40) block 7 start_pc=0 - v44 Imm(2) -> x0 - terminator Return(v44) (exit_acc=v44) + v41 Imm(2) -> x0 + terminator Return(v41) (exit_acc=v41) block 8 start_pc=0 - v45 LocalAddr(-128) -> x0 - v46 Imm(0) -> x1 - v47 Imm(0) -> x1 - v48 Load { addr=v45, disp=0, kind=U16 } -> x0 - v49 Imm(0) -> x0 - v50 LocalAddr(-161) -> x0 - v51 Imm(0) -> x1 - v52 Imm(4636666922610458624) -> x1 - v53 FpCast { kind=F64ToF32, value=v52 } -> d0 [f32] - v54 Store { addr=v50, disp=0, value=v53, kind=F32 } -> - - v55 LocalAddr(-161) -> x0 - v56 Load { addr=v55, disp=0, kind=F32 } -> d0 [f32] - v57 FpCast { kind=F32ToF64, value=v56 } -> d0 - v58 Binop { op=fne, lhs=v57, rhs=v52 } -> x0 - terminator Bz { cond=v58, target=b10, fall=b9 } (exit_acc=v58) + v42 LocalAddr(-128) -> x0 + v43 Imm(0) -> x1 + v44 Imm(0) -> x1 + v45 Load { addr=v42, disp=0, kind=U16 } -> x0 + v46 Imm(0) -> x0 + v47 LocalAddr(-161) -> x0 + v48 Imm(0) -> x1 + v49 Imm(1120272384) -> x1 [f32] + v50 Store { addr=v47, disp=0, value=v49, kind=F32 } -> - + v51 LocalAddr(-161) -> x0 + v52 Load { addr=v51, disp=0, kind=F32 } -> d0 [f32] + v53 Binop { op=fne, lhs=v52, rhs=v49 } -> x0 + terminator Bz { cond=v53, target=b10, fall=b9 } (exit_acc=v53) block 9 start_pc=0 - v59 Imm(3) -> x0 - terminator Return(v59) (exit_acc=v59) + v54 Imm(3) -> x0 + terminator Return(v54) (exit_acc=v54) block 10 start_pc=0 - v60 Imm(0) -> x0 - terminator Return(v60) (exit_acc=v60) + v55 Imm(0) -> x0 + terminator Return(v55) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/uint64_to_float.ssa b/tests/snapshots/ssa/uint64_to_float.ssa index e5e6f0a74..6da6bc882 100644 --- a/tests/snapshots/ssa/uint64_to_float.ssa +++ b/tests/snapshots/ssa/uint64_to_float.ssa @@ -62,16 +62,15 @@ fn ent_pc=1 n_params=0 variadic=false locals=5 v36 LoadLocal { off=-1, kind=I64 } -> x1 v37 FpCast { kind=UIntToFp, value=v1 } -> d0 v38 FpCast { kind=F64ToF32, value=v37 } -> d0 [f32] - v39 Imm(4890909195324358656) -> x0 - v40 FpCast { kind=F32ToF64, value=v38 } -> d0 - v41 Binop { op=fne, lhs=v40, rhs=v39 } -> x0 - terminator Bz { cond=v41, target=b12, fall=b11 } (exit_acc=v41) + v39 Imm(1593835520) -> x0 [f32] + v40 Binop { op=fne, lhs=v38, rhs=v39 } -> x0 + terminator Bz { cond=v40, target=b12, fall=b11 } (exit_acc=v40) block 11 start_pc=0 - v42 Imm(6) -> x0 - terminator Return(v42) (exit_acc=v42) + v41 Imm(6) -> x0 + terminator Return(v41) (exit_acc=v41) block 12 start_pc=0 - v43 Imm(0) -> x0 - terminator Return(v43) (exit_acc=v43) + v42 Imm(0) -> x0 + terminator Return(v42) (exit_acc=v42) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 diff --git a/tests/snapshots/ssa/volatile_param_classes.ssa b/tests/snapshots/ssa/volatile_param_classes.ssa index 837baf316..f54777689 100644 --- a/tests/snapshots/ssa/volatile_param_classes.ssa +++ b/tests/snapshots/ssa/volatile_param_classes.ssa @@ -90,18 +90,17 @@ fn ent_pc=3 n_params=0 variadic=false locals=5 v25 Imm(1) -> x0 terminator Return(v25) (exit_acc=v25) block 4 start_pc=0 - v26 Imm(4617315517961601024) -> x0 - v27 FpCast { kind=F64ToF32, value=v26 } -> d0 [f32] - v28 Call { target_pc=1, args=[v27], fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 - v29 Imm(4612811918334230528) -> x0 - v30 Binop { op=fne, lhs=v28, rhs=v29 } -> x0 - terminator Bz { cond=v30, target=b6, fall=b5 } (exit_acc=v30) + v26 Imm(1084227584) -> x7 [f32] + v27 Call { target_pc=1, args=[v26], fixed_args=1, fp_return=true, fp_arg_mask=0x1 } -> d0 + v28 Imm(4612811918334230528) -> x0 + v29 Binop { op=fne, lhs=v27, rhs=v28 } -> x0 + terminator Bz { cond=v29, target=b6, fall=b5 } (exit_acc=v29) block 5 start_pc=0 - v31 Imm(2) -> x0 - terminator Return(v31) (exit_acc=v31) + v30 Imm(2) -> x0 + terminator Return(v30) (exit_acc=v30) block 6 start_pc=0 - v32 Imm(0) -> x0 - terminator Return(v32) (exit_acc=v32) + v31 Imm(0) -> x0 + terminator Return(v31) (exit_acc=v31) block 7 start_pc=0 terminator Jmp(b2) ; --- SSA dump (ok=true) ent_pc=0 --- From b8cddb220a78d24da562dbdac904fa599dfff7ae Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 20:59:24 -0700 Subject: [PATCH 04/36] placeholders for the link to the perf runs --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index a55f7b3c9..8b3b5b27e 100644 --- a/README.md +++ b/README.md @@ -52,6 +52,8 @@ SSA snapshots of the test fixtures. The optimized binaries will run on any moder ARM64 processor, and on x86_64 processors not older than Intel Haswell and AMD Zen (circa 2013, the optimizer uses FMA3 instructions). +Here are the links the the perf run in CI: TODO + `badc` emits position-independent code and the real native binaries (macOS Mach-O, Linux ELF, or Windows PE32+), on any of five targets, from any host: From 223a2aff7102726c9da27497d505ec379a7ed636 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 21:06:05 -0700 Subject: [PATCH 05/36] tests: define NDEBUG in the optimized legs of the perf comparisons The badc -O / clang -O2 / cl /O2 rows of tests/perf/run.py and both -O legs of demos/python/compare_compilers.py now build with NDEBUG, matching release-build practice; unoptimized legs keep asserts live. Perf-table history is not comparable across this commit for the assert-carrying fixtures (sqlite, quickjs, compress, CPython). Co-Authored-By: Claude Fable 5 --- demos/python/compare_compilers.py | 7 ++++--- tests/perf/run.py | 9 ++++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/demos/python/compare_compilers.py b/demos/python/compare_compilers.py index 960965e12..5d09a0310 100644 --- a/demos/python/compare_compilers.py +++ b/demos/python/compare_compilers.py @@ -1,6 +1,7 @@ #!/usr/bin/env python3 """Build CPython from the same recipe with badc and the platform reference -compiler (clang on POSIX, cl on Windows), at -O and without, and report +compiler (clang on POSIX, cl on Windows), at -O and without (the -O legs +define NDEBUG, matching release-build practice), and report per-binary section sizes plus a runtime microbenchmark. The recipe -- the per-TU source list, defines, and includes -- comes from @@ -71,11 +72,11 @@ def _compile_cmd(cc_kind, cc, target, src, defs, incs, obj, opt, reenable): lacks); the reference compiler has those headers, so re-enable them to give it its natural build of the same module set.""" if cc_kind == "badc": - o = ["-O"] if opt else [] + o = ["-O", "-DNDEBUG"] if opt else [] return [cc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", '-DCOMPILER="[badc]"', *o, *defs, *incs, src, "-o", obj] if cc_kind == "clang": - o = ["-O2"] if opt else ["-O0"] + o = ["-O2", "-DNDEBUG"] if opt else ["-O0"] redef = [f"-D{m}=1" for m in reenable] # Force the same no-__int128 path badc takes, so the bigint code is # identical and the comparison isolates the compiler, not the dialect. diff --git a/tests/perf/run.py b/tests/perf/run.py index 13b715689..145f8ad22 100755 --- a/tests/perf/run.py +++ b/tests/perf/run.py @@ -20,6 +20,9 @@ * cl /Od -- MSVC cl.exe on Windows. * cl /O2 -- MSVC cl.exe on Windows. +The optimized entries (badc -O, clang -O2, cl /O2) define NDEBUG, matching +release-build practice; the unoptimized entries keep asserts live. + Override the badc binary via $BADC; override the tcc binary via $TCC. """ @@ -155,7 +158,7 @@ def probe_compilers() -> list[Compiler]: badc = REPO_ROOT / "target" / "release" / f"badc{EXE}" if badc.is_file(): found.append(Compiler("badc", [str(badc)])) - found.append(Compiler("badc -O", [str(badc), "-O"])) + found.append(Compiler("badc -O", [str(badc), "-O", "-DNDEBUG"])) else: print(f"info: badc not at {badc}; skipping badc rows", file=sys.stderr) @@ -213,7 +216,7 @@ def probe_compilers() -> list[Compiler]: # libSystem. Without `-lm` clang fails to link quickjs_bench. clang_trailing = ("-lm",) if sys.platform == "linux" else () found.append(Compiler("clang -O0", ["clang", "-O0"], trailing=clang_trailing)) - found.append(Compiler("clang -O2", ["clang", "-O2"], trailing=clang_trailing)) + found.append(Compiler("clang -O2", ["clang", "-O2", "-DNDEBUG"], trailing=clang_trailing)) if WIN and shutil.which("cl"): found.append( @@ -226,7 +229,7 @@ def probe_compilers() -> list[Compiler]: found.append( Compiler( "cl /O2", - ["cl", "/nologo", "/O2"], + ["cl", "/nologo", "/O2", "/DNDEBUG"], output_dash_o=False, ) ) From 3fc9901ea90f955a37fd6c2904eb7a6bb1835cb1 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 21:22:32 -0700 Subject: [PATCH 06/36] c5: apply intermediate casts in brace initializer elements The brace-element parser skipped a leading (TYPE) cast and recursed on the operand, so every intermediate conversion was lost: (long)(int)0x92492493 stored the unextended 0x92492493 in static and automatic arrays and structs, (int)2.75 kept the float bits, and a binary operator after the cast folded before it instead of after. Route a cast of an arithmetic operand through the constant-expression evaluator, which converts at each cast's width and signedness per C99 6.5.4/6.3.1.3 before the 6.7.8p11 conversion to the member type; only a cast of a relocation-bearing leaf keeps the skip-and-recurse path where the value is the leaf's address. The shared reloc-leaf probe now sees through grouping parens plus nested casts and restores string bytes it lexed while scanning. Fixes #366 Co-Authored-By: Claude Fable 5 --- src/c5/compiler/const_expr.rs | 9 +- src/c5/compiler/global_init.rs | 33 +- src/c5/compiler/initializer.rs | 22 +- src/c5/tests/jit.rs | 1 + src/c5/tests/native.rs | 1 + src/c5/tests/native_elf.rs | 1 + src/c5/tests/native_elf_x64.rs | 1 + src/c5/tests/native_pe_arm64.rs | 1 + src/c5/tests/native_pe_x64.rs | 1 + src/c5/tests/programs.rs | 9 + .../fixtures/c/init_brace_intermediate_cast.c | 77 ++++ .../init_brace_intermediate_cast.aarch64.asm | 394 ++++++++++++++++++ .../asm/init_brace_intermediate_cast.x64.asm | 288 +++++++++++++ .../ssa/init_brace_intermediate_cast.ssa | 330 +++++++++++++++ 14 files changed, 1160 insertions(+), 8 deletions(-) create mode 100644 tests/fixtures/c/init_brace_intermediate_cast.c create mode 100644 tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm create mode 100644 tests/snapshots/asm/init_brace_intermediate_cast.x64.asm create mode 100644 tests/snapshots/ssa/init_brace_intermediate_cast.ssa diff --git a/src/c5/compiler/const_expr.rs b/src/c5/compiler/const_expr.rs index 29881569b..fc307d5ed 100644 --- a/src/c5/compiler/const_expr.rs +++ b/src/c5/compiler/const_expr.rs @@ -374,7 +374,7 @@ impl Compiler { /// contributes to the resulting value, matching clang/gcc. /// The `:` arm recurses back into `parse_const_expr_cond_val` so /// `a ? b : c ? d : e` parses right-associatively. - fn parse_const_expr_cond_val(&mut self) -> Result { + pub(super) fn parse_const_expr_cond_val(&mut self) -> Result { let cond = self.parse_const_expr_or_val()?; if self.lex.tk == Token::Cond { self.next()?; @@ -880,6 +880,13 @@ impl Compiler { // the cast clamps it back to integer per C99 6.3.1.4. if self.lex_is_type_start() { let mut target_ty = self.parse_decl_base_type()?; + // The type is consumed as a cast, not bound through a + // declarator; drop the declarator side channels it may set. + self.pending.base_is_function_type = false; + self.pending.bare_function_type_declarator = false; + self.pending.fn_ptr_indirection = None; + self.pending.typedef_fn_proto = None; + self.pending.fn_ptr_param_types = None; while self.lex.tk == Token::MulOp { self.next()?; target_ty += Ty::Ptr as i64; diff --git a/src/c5/compiler/global_init.rs b/src/c5/compiler/global_init.rs index d01a61ef1..15cd3752c 100644 --- a/src/c5/compiler/global_init.rs +++ b/src/c5/compiler/global_init.rs @@ -26,15 +26,19 @@ use super::types::{ }; impl Compiler { - /// After a leading `(TYPE)` cast in a global initializer, returns - /// true when the cast applies to a relocation-bearing leaf (`&x`, a + /// After a leading `(TYPE)` cast in an initializer, returns true + /// when the cast applies to a relocation-bearing leaf (`&x`, a /// string literal, or a function / global-array name) rather than an /// arithmetic value. Reloc leaves keep the address-folding path; an /// arithmetic cast must instead reach the const-expr evaluator, which /// narrows per C99 6.3.1.3. Entry is positioned just inside the cast /// paren (depth 1); the lexer is restored before returning. - fn post_cast_is_reloc_leaf(&mut self) -> Result { + pub(super) fn post_cast_is_reloc_leaf(&mut self) -> Result { let snap = self.lex.snapshot(); + // The scan may lex a string literal, whose bytes the lexer + // appends to the data segment; the snapshot does not cover + // the data segment, so truncate it back before returning. + let data_snap = self.data.len(); let mut depth: i64 = 1; while depth > 0 && self.lex.tk != 0 { if self.lex.tk == '(' { @@ -48,8 +52,28 @@ impl Compiler { } self.next()?; } - while self.lex.tk == '(' { + // The leaf may sit behind grouping parens and further casts + // (`(T)(((U)(fn)))`); skip both to reach it. + loop { + if self.lex.tk != '(' { + break; + } self.next()?; + if self.lex_is_type_start() { + let mut d: i64 = 1; + while d > 0 && self.lex.tk != 0 { + if self.lex.tk == '(' { + d += 1; + } else if self.lex.tk == ')' { + d -= 1; + if d == 0 { + self.next()?; + break; + } + } + self.next()?; + } + } } let reloc = self.lex.tk == Token::AndOp || self.lex.tk == '"' @@ -61,6 +85,7 @@ impl Compiler { && self.symbols[self.lex.curr_id_idx].array_size != 0) }); self.lex.restore(snap); + self.data.truncate(data_snap); Ok(reloc) } diff --git a/src/c5/compiler/initializer.rs b/src/c5/compiler/initializer.rs index 46ee6fd82..eacf4da95 100644 --- a/src/c5/compiler/initializer.rs +++ b/src/c5/compiler/initializer.rs @@ -955,9 +955,10 @@ impl Compiler { } // `(type)expr` cast or `(expr)` parenthesized constant in a // static initializer. After consuming `(`, peek the next - // token: if it starts a type, treat as a cast and recurse on - // the value (c5's i64-shaped representation makes integer / - // pointer casts no-ops). Otherwise it's a parenthesized + // token: if it starts a type, treat as a cast -- arithmetic + // operands go through the const-expr evaluator (which applies + // the cast's conversion), relocation-bearing leaves recurse + // with the cast dropped. Otherwise it's a parenthesized // constant expression -- evaluate it and expect `)`. if self.lex.tk == '(' { // Cast / float-content detection both need to look @@ -996,6 +997,21 @@ impl Compiler { if self.lex.tk == Token::Brak { return self.parse_array_compound_literal(cast_ty); } + // A cast of an arithmetic operand converts to the target + // type (C99 6.5.4, 6.3.1.3); route the element through the + // constant-expression evaluator, which applies every cast + // in the chain at its own width, so + // `(long)(int)0x92492493` sign-extends through `int`. + // Only a cast of a relocation-bearing leaf keeps the + // skip-and-recurse path below, where the value is the + // leaf's address and the cast merely retypes it. + if !self.post_cast_is_reloc_leaf()? { + self.lex.restore(snap); + return Ok(match self.parse_const_expr_cond_val()? { + ConstVal::Float(f) => (f.to_bits() as i64, InitElemReloc::Float64Bits), + v @ ConstVal::Int { .. } => (v.as_int(), InitElemReloc::None), + }); + } // Optional function-pointer abstract declarator // `(*)(args)` after the base type. Same treatment // as in the expression-level cast handler: scan diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index 49b1672b6..c273810ff 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1194,6 +1194,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index 53114af44..fb25793bf 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -472,6 +472,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index feb507ab5..de8f97ade 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -400,6 +400,7 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index 27591bef6..1cea28fb9 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -353,6 +353,7 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index aebd032e9..576ba013d 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -681,6 +681,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index 6ad2ece60..0baa31558 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -694,6 +694,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("union_bitfield_layout.c", 0), ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), + ("init_brace_intermediate_cast.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 5283bc6d4..4fe326f2c 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -2065,6 +2065,15 @@ fn global_init_midexpr_cast_narrow() { assert_eq!(run_fixture("global_init_midexpr_cast_narrow.c"), 0); } +#[test] +fn init_brace_intermediate_cast() { + // C99 6.5.4 + 6.7.8p11: a brace-enclosed initializer element applies + // every cast in its chain -- `(long)(int)0x92492493` sign-extends + // through `int` -- in static and automatic storage, for array + // elements and struct members alike. + assert_eq!(run_fixture("init_brace_intermediate_cast.c"), 0); +} + #[test] fn enum_tag_types() { // `enum Foo { ... };` registers a tag whose constants diff --git a/tests/fixtures/c/init_brace_intermediate_cast.c b/tests/fixtures/c/init_brace_intermediate_cast.c new file mode 100644 index 000000000..8b49bae84 --- /dev/null +++ b/tests/fixtures/c/init_brace_intermediate_cast.c @@ -0,0 +1,77 @@ +// C99 6.5.4: a cast converts the operand to the named type, so an +// intermediate cast narrows before any outer widening. 6.7.8p11: an +// initializer is converted to the object's type as by assignment +// after the expression's own conversions. Brace-enclosed elements +// must apply every cast in the chain, in static and automatic +// storage, for array and struct members alike. + +struct box { + long l; + unsigned long ul; + int i; +}; + +long sa[4] = { + (long)(int)0x92492493, + (long)(unsigned)0x1FFFFFFFFLL, + (long)(short)0xFFFF, + (long)(char)0x1FF, +}; +unsigned long sua[2] = { (unsigned long)(short)0xFFFF, (unsigned long)(int)0x92492493 }; +int sia[2] = { (int)(char)200, (int)(short)0x18000 }; +struct box sb = { (long)(int)0x92492493, (unsigned long)(short)0xFFFF, (int)(char)200 }; + +// Scalar wrapped in the optional brace pair (6.7.8p11). +long sscal = { (long)(int)0x92492493 }; + +// The cast binds tighter than a following binary operator (6.5.4). +long sprec[2] = { (int)0x100000000LL / 2, (int)0xFFFFFFFF >> 4 }; + +// Casts converting between integer and floating values (6.3.1.4). +int sfi[1] = { (int)2.75 }; +double sfd[1] = { (long)3.9 }; + +int main(void) { + long aa[4] = { + (long)(int)0x92492493, + (long)(unsigned)0x1FFFFFFFFLL, + (long)(short)0xFFFF, + (long)(char)0x1FF, + }; + unsigned long aua[2] = { (unsigned long)(short)0xFFFF, (unsigned long)(int)0x92492493 }; + int aia[2] = { (int)(char)200, (int)(short)0x18000 }; + struct box ab = { (long)(int)0x92492493, (unsigned long)(short)0xFFFF, (int)(char)200 }; + long ascal = { (long)(int)0x92492493 }; + + if (sa[0] != -1840700269L) return 1; + if (sa[1] != 4294967295L) return 2; + if (sa[2] != -1L) return 3; + if (sa[3] != -1L) return 4; + if (sua[0] != 0xFFFFFFFFFFFFFFFFUL) return 5; + if (sua[1] != 0xFFFFFFFF92492493UL) return 6; + if (sia[0] != -56) return 7; + if (sia[1] != -32768) return 8; + if (sb.l != -1840700269L) return 9; + if (sb.ul != 0xFFFFFFFFFFFFFFFFUL) return 10; + if (sb.i != -56) return 11; + if (sscal != -1840700269L) return 12; + if (sprec[0] != 0L) return 13; + if (sprec[1] != -1L) return 14; + if (sfi[0] != 2) return 15; + if (sfd[0] != 3.0) return 16; + + if (aa[0] != -1840700269L) return 17; + if (aa[1] != 4294967295L) return 18; + if (aa[2] != -1L) return 19; + if (aa[3] != -1L) return 20; + if (aua[0] != 0xFFFFFFFFFFFFFFFFUL) return 21; + if (aua[1] != 0xFFFFFFFF92492493UL) return 22; + if (aia[0] != -56) return 23; + if (aia[1] != -32768) return 24; + if (ab.l != -1840700269L) return 25; + if (ab.ul != 0xFFFFFFFFFFFFFFFFUL) return 26; + if (ab.i != -56) return 27; + if (ascal != -1840700269L) return 28; + + return 0; +} diff --git a/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm b/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm new file mode 100644 index 000000000..530af1dab --- /dev/null +++ b/tests/snapshots/asm/init_brace_intermediate_cast.aarch64.asm @@ -0,0 +1,394 @@ + +init_brace_intermediate_cast.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x60 + sub x0, x29, #0x20 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [x1, #0x10] + str x10, [x0, #0x10] + ldr x10, [x1, #0x18] + str x10, [x0, #0x18] + ldr x10, [sp], #0x10 + sub x0, x29, #0x30 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [sp], #0x10 + sub x0, x29, #0x38 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [sp], #0x10 + sub x0, x29, #0x50 + adrp x1, + add x1, x1, + str x10, [sp, #-0x10]! + ldr x10, [x1] + str x10, [x0] + ldr x10, [x1, #0x8] + str x10, [x0, #0x8] + ldr x10, [x1, #0x10] + str x10, [x0, #0x10] + ldr x10, [sp], #0x10 + mov x0, #0x2493 // =9363 + movk x0, #0x9249, lsl #16 + movk x0, #0xffff, lsl #32 + movk x0, #0xffff, lsl #48 + adrp x1, + add x1, x1, + ldr x2, [x1] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x2, x17 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x2, [x1, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + cmp x2, x17 + b.eq + mov x0, #0x2 // =2 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x2, [x1, #0x10] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x2, x17 + b.eq + mov x0, #0x3 // =3 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + ldr x1, [x1, #0x18] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x4 // =4 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x5 // =5 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1, #0x8] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x6 // =6 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldrsw x1, [x1] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x7 // =7 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldrsw x1, [x1, #0x4] + mov x17, #0x8000 // =32768 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x8 // =8 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x9 // =9 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0xa // =10 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldrsw x1, [x1, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0xb // =11 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0xc // =12 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + cmp x1, #0x0 + b.eq + mov x0, #0xd // =13 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0xe // =14 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldrsw x1, [x1] + cmp x1, #0x2 + b.eq + mov x0, #0xf // =15 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + adrp x1, + add x1, x1, + ldr d0, [x1] + mov x1, #0x4008000000000000 // =4613937818241073152 + fmov d17, x1 + fcmp d0, d17 + cset x1, ne + cbz x1, + mov x0, #0x10 // =16 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x20 + ldr x1, [x1] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x11 // =17 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x20 + ldr x1, [x1, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + cmp x1, x17 + b.eq + mov x0, #0x12 // =18 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x20 + ldr x1, [x1, #0x10] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x13 // =19 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x20 + ldr x1, [x1, #0x18] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x14 // =20 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x30 + ldr x1, [x1] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x15 // =21 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x30 + ldr x1, [x1, #0x8] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x16 // =22 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x38 + ldrsw x1, [x1] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x17 // =23 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x38 + ldrsw x1, [x1, #0x4] + mov x17, #0x8000 // =32768 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x18 // =24 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x50 + ldr x1, [x1] + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x19 // =25 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x50 + ldr x1, [x1, #0x8] + mov x17, #0xffff // =65535 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x1a // =26 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + sub x1, x29, #0x50 + ldrsw x1, [x1, #0x10] + mov x17, #0xffc8 // =65480 + movk x17, #0xffff, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x1, x17 + b.eq + mov x0, #0x1b // =27 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x17, #0x2493 // =9363 + movk x17, #0x9249, lsl #16 + movk x17, #0xffff, lsl #32 + movk x17, #0xffff, lsl #48 + cmp x0, x17 + b.eq + mov x0, #0x1c // =28 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + add sp, sp, #0x60 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm b/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm new file mode 100644 index 000000000..e52b7458f --- /dev/null +++ b/tests/snapshots/asm/init_brace_intermediate_cast.x64.asm @@ -0,0 +1,288 @@ + +init_brace_intermediate_cast.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x60, %rsp + leaq -0x20(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + movq 0x10(%rcx), %rdx + movq %rdx, 0x10(%rax) + movq 0x18(%rcx), %rdx + movq %rdx, 0x18(%rax) + popq %rdx + leaq -0x30(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + popq %rdx + leaq -0x38(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + popq %rdx + leaq -0x50(%rbp), %rax + leaq , %rcx + pushq %rdx + movq (%rcx), %rdx + movq %rdx, (%rax) + movq 0x8(%rcx), %rdx + movq %rdx, 0x8(%rax) + movq 0x10(%rcx), %rdx + movq %rdx, 0x10(%rax) + popq %rdx + movabsq $-0x6db6db6d, %rax # imm = 0x92492493 + leaq , %rcx + movq (%rcx), %rdx + cmpq $-0x6db6db6d, %rdx # imm = 0x92492493 + je + movl $0x1, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x8(%rcx), %rdx + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + cmpq %r11, %rdx + je + movl $0x2, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x10(%rcx), %rdx + cmpq $-0x1, %rdx + je + movl $0x3, %eax + addq $0x60, %rsp + popq %rbp + retq + movq 0x18(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x4, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq (%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x5, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq 0x8(%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x6, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movslq (%rcx), %rcx + cmpq $-0x38, %rcx + je + movl $0x7, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movslq 0x4(%rcx), %rcx + cmpq $-0x8000, %rcx # imm = 0x8000 + je + movl $0x8, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq (%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x9, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq 0x8(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0xa, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movslq 0x10(%rcx), %rcx + cmpq $-0x38, %rcx + je + movl $0xb, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq (%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0xc, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq (%rcx), %rcx + testq %rcx, %rcx + je + movl $0xd, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movq 0x8(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0xe, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movslq (%rcx), %rcx + cmpq $0x2, %rcx + je + movl $0xf, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq , %rcx + movsd (%rcx,%riz), %xmm0 + movabsq $0x4008000000000000, %rcx # imm = 0x4008000000000000 + movq %rcx, %xmm15 + ucomisd %xmm15, %xmm0 + setne %cl + movzbq %cl, %rcx + setp %r10b + movzbq %r10b, %r10 + orq %r10, %rcx + testq %rcx, %rcx + je + movl $0x10, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rcx + movq (%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x11, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rcx + movq 0x8(%rcx), %rcx + movl $0xffffffff, %r11d # imm = 0xFFFFFFFF + cmpq %r11, %rcx + je + movl $0x12, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rcx + movq 0x10(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x13, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x20(%rbp), %rcx + movq 0x18(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x14, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x30(%rbp), %rcx + movq (%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x15, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x30(%rbp), %rcx + movq 0x8(%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x16, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x38(%rbp), %rcx + movslq (%rcx), %rcx + cmpq $-0x38, %rcx + je + movl $0x17, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x38(%rbp), %rcx + movslq 0x4(%rcx), %rcx + cmpq $-0x8000, %rcx # imm = 0x8000 + je + movl $0x18, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rcx + movq (%rcx), %rcx + cmpq $-0x6db6db6d, %rcx # imm = 0x92492493 + je + movl $0x19, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rcx + movq 0x8(%rcx), %rcx + cmpq $-0x1, %rcx + je + movl $0x1a, %eax + addq $0x60, %rsp + popq %rbp + retq + leaq -0x50(%rbp), %rcx + movslq 0x10(%rcx), %rcx + cmpq $-0x38, %rcx + je + movl $0x1b, %eax + addq $0x60, %rsp + popq %rbp + retq + cmpq $-0x6db6db6d, %rax # imm = 0x92492493 + je + movl $0x1c, %eax + addq $0x60, %rsp + popq %rbp + retq + xorq %rax, %rax + addq $0x60, %rsp + popq %rbp + retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/ssa/init_brace_intermediate_cast.ssa b/tests/snapshots/ssa/init_brace_intermediate_cast.ssa new file mode 100644 index 000000000..93e33547d --- /dev/null +++ b/tests/snapshots/ssa/init_brace_intermediate_cast.ssa @@ -0,0 +1,330 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=11 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 LocalAddr(-4) -> x0 + v2 ImmData(128) -> x1 + v3 Mcpy { dst=v1, src=v2, size=32 } -> x0 + v4 LocalAddr(-6) -> x0 + v5 ImmData(160) -> x1 + v6 Mcpy { dst=v4, src=v5, size=16 } -> x0 + v7 LocalAddr(-7) -> x0 + v8 ImmData(176) -> x1 + v9 Mcpy { dst=v7, src=v8, size=8 } -> x0 + v10 LocalAddr(-10) -> x0 + v11 ImmData(184) -> x1 + v12 Mcpy { dst=v10, src=v11, size=24 } -> x0 + v13 Imm(2454267027) -> x0 + v14 Imm(-7905747457093402624) -> x0 + v15 Imm(-1840700269) -> x0 + v16 Imm(0) -> x1 + v17 ImmData(8) -> x1 + v18 Imm(0) -> x2 + v19 Load { addr=v17, disp=0, kind=I64 } -> x2 + v20 BinopI { op=ne, lhs=v19, rhs_imm=-1840700269 } -> x2 + terminator Bz { cond=v20, target=b2, fall=b1 } (exit_acc=v20) + block 1 start_pc=0 + v21 Imm(1) -> x0 + terminator Return(v21) (exit_acc=v21) + block 2 start_pc=0 + v22 ImmData(8) -> x2 + v23 Imm(8) -> x2 + v24 BinopI { op=add, lhs=v17, rhs_imm=8 } -> x2 + v25 Load { addr=v17, disp=8, kind=I64 } -> x2 + v26 BinopI { op=ne, lhs=v25, rhs_imm=4294967295 } -> x2 + terminator Bz { cond=v26, target=b4, fall=b3 } (exit_acc=v26) + block 3 start_pc=0 + v27 Imm(2) -> x0 + terminator Return(v27) (exit_acc=v27) + block 4 start_pc=0 + v28 ImmData(8) -> x2 + v29 Imm(16) -> x2 + v30 BinopI { op=add, lhs=v17, rhs_imm=16 } -> x2 + v31 Load { addr=v17, disp=16, kind=I64 } -> x2 + v32 BinopI { op=ne, lhs=v31, rhs_imm=-1 } -> x2 + terminator Bz { cond=v32, target=b6, fall=b5 } (exit_acc=v32) + block 5 start_pc=0 + v33 Imm(3) -> x0 + terminator Return(v33) (exit_acc=v33) + block 6 start_pc=0 + v34 ImmData(8) -> x2 + v35 Imm(24) -> x2 + v36 BinopI { op=add, lhs=v17, rhs_imm=24 } -> x2 + v37 Load { addr=v17, disp=24, kind=I64 } -> x1 + v38 BinopI { op=ne, lhs=v37, rhs_imm=-1 } -> x1 + terminator Bz { cond=v38, target=b8, fall=b7 } (exit_acc=v38) + block 7 start_pc=0 + v39 Imm(4) -> x0 + terminator Return(v39) (exit_acc=v39) + block 8 start_pc=0 + v40 ImmData(40) -> x1 + v41 Imm(0) -> x2 + v42 Load { addr=v40, disp=0, kind=I64 } -> x1 + v43 BinopI { op=ne, lhs=v42, rhs_imm=-1 } -> x1 + terminator Bz { cond=v43, target=b10, fall=b9 } (exit_acc=v43) + block 9 start_pc=0 + v44 Imm(5) -> x0 + terminator Return(v44) (exit_acc=v44) + block 10 start_pc=0 + v45 ImmData(40) -> x1 + v46 Imm(8) -> x2 + v47 BinopI { op=add, lhs=v45, rhs_imm=8 } -> x2 + v48 Load { addr=v45, disp=8, kind=I64 } -> x1 + v49 BinopI { op=ne, lhs=v48, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v49, target=b12, fall=b11 } (exit_acc=v49) + block 11 start_pc=0 + v50 Imm(6) -> x0 + terminator Return(v50) (exit_acc=v50) + block 12 start_pc=0 + v51 ImmData(56) -> x1 + v52 Imm(0) -> x2 + v53 Load { addr=v51, disp=0, kind=I32 } -> x1 + v54 BinopI { op=ne, lhs=v53, rhs_imm=-56 } -> x1 + terminator Bz { cond=v54, target=b14, fall=b13 } (exit_acc=v54) + block 13 start_pc=0 + v55 Imm(7) -> x0 + terminator Return(v55) (exit_acc=v55) + block 14 start_pc=0 + v56 ImmData(56) -> x1 + v57 Imm(4) -> x2 + v58 BinopI { op=add, lhs=v56, rhs_imm=4 } -> x2 + v59 Load { addr=v56, disp=4, kind=I32 } -> x1 + v60 BinopI { op=ne, lhs=v59, rhs_imm=-32768 } -> x1 + terminator Bz { cond=v60, target=b16, fall=b15 } (exit_acc=v60) + block 15 start_pc=0 + v61 Imm(8) -> x0 + terminator Return(v61) (exit_acc=v61) + block 16 start_pc=0 + v62 ImmData(64) -> x1 + v63 Load { addr=v62, disp=0, kind=I64 } -> x1 + v64 BinopI { op=ne, lhs=v63, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v64, target=b18, fall=b17 } (exit_acc=v64) + block 17 start_pc=0 + v65 Imm(9) -> x0 + terminator Return(v65) (exit_acc=v65) + block 18 start_pc=0 + v66 ImmData(64) -> x1 + v67 BinopI { op=add, lhs=v66, rhs_imm=8 } -> x2 + v68 Load { addr=v66, disp=8, kind=I64 } -> x1 + v69 BinopI { op=ne, lhs=v68, rhs_imm=-1 } -> x1 + terminator Bz { cond=v69, target=b20, fall=b19 } (exit_acc=v69) + block 19 start_pc=0 + v70 Imm(10) -> x0 + terminator Return(v70) (exit_acc=v70) + block 20 start_pc=0 + v71 ImmData(64) -> x1 + v72 BinopI { op=add, lhs=v71, rhs_imm=16 } -> x2 + v73 Load { addr=v71, disp=16, kind=I32 } -> x1 + v74 BinopI { op=ne, lhs=v73, rhs_imm=-56 } -> x1 + terminator Bz { cond=v74, target=b22, fall=b21 } (exit_acc=v74) + block 21 start_pc=0 + v75 Imm(11) -> x0 + terminator Return(v75) (exit_acc=v75) + block 22 start_pc=0 + v76 ImmData(88) -> x1 + v77 Load { addr=v76, disp=0, kind=I64 } -> x1 + v78 BinopI { op=ne, lhs=v77, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v78, target=b24, fall=b23 } (exit_acc=v78) + block 23 start_pc=0 + v79 Imm(12) -> x0 + terminator Return(v79) (exit_acc=v79) + block 24 start_pc=0 + v80 ImmData(96) -> x1 + v81 Imm(0) -> x2 + v82 Load { addr=v80, disp=0, kind=I64 } -> x1 + v83 BinopI { op=ne, lhs=v82, rhs_imm=0 } -> x1 + terminator Bz { cond=v83, target=b26, fall=b25 } (exit_acc=v83) + block 25 start_pc=0 + v84 Imm(13) -> x0 + terminator Return(v84) (exit_acc=v84) + block 26 start_pc=0 + v85 ImmData(96) -> x1 + v86 Imm(8) -> x2 + v87 BinopI { op=add, lhs=v85, rhs_imm=8 } -> x2 + v88 Load { addr=v85, disp=8, kind=I64 } -> x1 + v89 BinopI { op=ne, lhs=v88, rhs_imm=-1 } -> x1 + terminator Bz { cond=v89, target=b28, fall=b27 } (exit_acc=v89) + block 27 start_pc=0 + v90 Imm(14) -> x0 + terminator Return(v90) (exit_acc=v90) + block 28 start_pc=0 + v91 ImmData(112) -> x1 + v92 Imm(0) -> x2 + v93 Load { addr=v91, disp=0, kind=I32 } -> x1 + v94 BinopI { op=ne, lhs=v93, rhs_imm=2 } -> x1 + terminator Bz { cond=v94, target=b30, fall=b29 } (exit_acc=v94) + block 29 start_pc=0 + v95 Imm(15) -> x0 + terminator Return(v95) (exit_acc=v95) + block 30 start_pc=0 + v96 ImmData(120) -> x1 + v97 Imm(0) -> x2 + v98 Load { addr=v96, disp=0, kind=F64 } -> d0 + v99 Imm(4613937818241073152) -> x1 + v100 Binop { op=fne, lhs=v98, rhs=v99 } -> x1 + terminator Bz { cond=v100, target=b32, fall=b31 } (exit_acc=v100) + block 31 start_pc=0 + v101 Imm(16) -> x0 + terminator Return(v101) (exit_acc=v101) + block 32 start_pc=0 + v102 LocalAddr(-4) -> x1 + v103 Imm(0) -> x2 + v104 Load { addr=v102, disp=0, kind=I64 } -> x1 + v105 BinopI { op=ne, lhs=v104, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v105, target=b34, fall=b33 } (exit_acc=v105) + block 33 start_pc=0 + v106 Imm(17) -> x0 + terminator Return(v106) (exit_acc=v106) + block 34 start_pc=0 + v107 LocalAddr(-4) -> x1 + v108 Imm(8) -> x2 + v109 BinopI { op=add, lhs=v107, rhs_imm=8 } -> x2 + v110 Load { addr=v107, disp=8, kind=I64 } -> x1 + v111 BinopI { op=ne, lhs=v110, rhs_imm=4294967295 } -> x1 + terminator Bz { cond=v111, target=b36, fall=b35 } (exit_acc=v111) + block 35 start_pc=0 + v112 Imm(18) -> x0 + terminator Return(v112) (exit_acc=v112) + block 36 start_pc=0 + v113 LocalAddr(-4) -> x1 + v114 Imm(16) -> x2 + v115 BinopI { op=add, lhs=v113, rhs_imm=16 } -> x2 + v116 Load { addr=v113, disp=16, kind=I64 } -> x1 + v117 BinopI { op=ne, lhs=v116, rhs_imm=-1 } -> x1 + terminator Bz { cond=v117, target=b38, fall=b37 } (exit_acc=v117) + block 37 start_pc=0 + v118 Imm(19) -> x0 + terminator Return(v118) (exit_acc=v118) + block 38 start_pc=0 + v119 LocalAddr(-4) -> x1 + v120 Imm(24) -> x2 + v121 BinopI { op=add, lhs=v119, rhs_imm=24 } -> x2 + v122 Load { addr=v119, disp=24, kind=I64 } -> x1 + v123 BinopI { op=ne, lhs=v122, rhs_imm=-1 } -> x1 + terminator Bz { cond=v123, target=b40, fall=b39 } (exit_acc=v123) + block 39 start_pc=0 + v124 Imm(20) -> x0 + terminator Return(v124) (exit_acc=v124) + block 40 start_pc=0 + v125 LocalAddr(-6) -> x1 + v126 Imm(0) -> x2 + v127 Load { addr=v125, disp=0, kind=I64 } -> x1 + v128 BinopI { op=ne, lhs=v127, rhs_imm=-1 } -> x1 + terminator Bz { cond=v128, target=b42, fall=b41 } (exit_acc=v128) + block 41 start_pc=0 + v129 Imm(21) -> x0 + terminator Return(v129) (exit_acc=v129) + block 42 start_pc=0 + v130 LocalAddr(-6) -> x1 + v131 Imm(8) -> x2 + v132 BinopI { op=add, lhs=v130, rhs_imm=8 } -> x2 + v133 Load { addr=v130, disp=8, kind=I64 } -> x1 + v134 BinopI { op=ne, lhs=v133, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v134, target=b44, fall=b43 } (exit_acc=v134) + block 43 start_pc=0 + v135 Imm(22) -> x0 + terminator Return(v135) (exit_acc=v135) + block 44 start_pc=0 + v136 LocalAddr(-7) -> x1 + v137 Imm(0) -> x2 + v138 Load { addr=v136, disp=0, kind=I32 } -> x1 + v139 BinopI { op=ne, lhs=v138, rhs_imm=-56 } -> x1 + terminator Bz { cond=v139, target=b46, fall=b45 } (exit_acc=v139) + block 45 start_pc=0 + v140 Imm(23) -> x0 + terminator Return(v140) (exit_acc=v140) + block 46 start_pc=0 + v141 LocalAddr(-7) -> x1 + v142 Imm(4) -> x2 + v143 BinopI { op=add, lhs=v141, rhs_imm=4 } -> x2 + v144 Load { addr=v141, disp=4, kind=I32 } -> x1 + v145 BinopI { op=ne, lhs=v144, rhs_imm=-32768 } -> x1 + terminator Bz { cond=v145, target=b48, fall=b47 } (exit_acc=v145) + block 47 start_pc=0 + v146 Imm(24) -> x0 + terminator Return(v146) (exit_acc=v146) + block 48 start_pc=0 + v147 LocalAddr(-10) -> x1 + v148 Load { addr=v147, disp=0, kind=I64 } -> x1 + v149 BinopI { op=ne, lhs=v148, rhs_imm=-1840700269 } -> x1 + terminator Bz { cond=v149, target=b50, fall=b49 } (exit_acc=v149) + block 49 start_pc=0 + v150 Imm(25) -> x0 + terminator Return(v150) (exit_acc=v150) + block 50 start_pc=0 + v151 LocalAddr(-10) -> x1 + v152 BinopI { op=add, lhs=v151, rhs_imm=8 } -> x2 + v153 Load { addr=v151, disp=8, kind=I64 } -> x1 + v154 BinopI { op=ne, lhs=v153, rhs_imm=-1 } -> x1 + terminator Bz { cond=v154, target=b52, fall=b51 } (exit_acc=v154) + block 51 start_pc=0 + v155 Imm(26) -> x0 + terminator Return(v155) (exit_acc=v155) + block 52 start_pc=0 + v156 LocalAddr(-10) -> x1 + v157 BinopI { op=add, lhs=v156, rhs_imm=16 } -> x2 + v158 Load { addr=v156, disp=16, kind=I32 } -> x1 + v159 BinopI { op=ne, lhs=v158, rhs_imm=-56 } -> x1 + terminator Bz { cond=v159, target=b54, fall=b53 } (exit_acc=v159) + block 53 start_pc=0 + v160 Imm(27) -> x0 + terminator Return(v160) (exit_acc=v160) + block 54 start_pc=0 + v161 LoadLocal { off=-11, kind=I64 } -> x1 + v162 BinopI { op=ne, lhs=v15, rhs_imm=-1840700269 } -> x0 + terminator Bz { cond=v162, target=b56, fall=b55 } (exit_acc=v162) + block 55 start_pc=0 + v163 Imm(28) -> x0 + terminator Return(v163) (exit_acc=v163) + block 56 start_pc=0 + v164 Imm(0) -> x0 + terminator Return(v164) (exit_acc=v164) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) From 7e144505735fb9d000c112bfeef65c5aa2e993a1 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 21:25:31 -0700 Subject: [PATCH 07/36] c5: run a static-local runtime array initializer exactly once A static-local array initializer carrying a `&&` token (a `&&label` element, or logical AND inside a constant element) routes to emit_static_array_init_runtime, which emitted unguarded per-element stores at the declaration point: the initializer re-ran on every call, clobbering user writes to the table. C99 6.2.4p3 gives an object with static storage duration exactly one initialization, before program startup, for the whole program run. Wrap the stores in a hidden once-guard byte allocated directly after the array in the same data object (so data DCE and linker rebase move it with the array), lowered as the single statement `guard ? 0 : (stores..., guard = 1)`; the guard is ordinary loads, stores, and branches in the IR, so the native backends, the JIT, and the SSA interpreter all honor it. quickjs_bench -O on the arm64 host: 325.2 -> 207.7 ms median of 5 (-36%). The generic form -- resolving `&&label` elements in the data image via label relocations at translation time, removing the runtime stores entirely -- remains as follow-up work on the issue. Fixes #365 Co-Authored-By: Claude Fable 5 --- src/c5/compiler/locals.rs | 75 +++++- src/c5/tests/jit.rs | 2 + src/c5/tests/native.rs | 2 + src/c5/tests/native_elf.rs | 2 + src/c5/tests/native_elf_x64.rs | 2 + src/c5/tests/native_pe_arm64.rs | 2 + src/c5/tests/native_pe_x64.rs | 2 + src/c5/tests/programs.rs | 15 ++ tests/fixtures/c/computed_goto_static_table.c | 34 +++ tests/fixtures/c/static_init_once_guard.c | 43 ++++ .../asm/array_range_designator.aarch64.asm | 12 + .../asm/array_range_designator.x64.asm | 13 + .../computed_goto_static_table.aarch64.asm | 135 ++++++++++ .../asm/computed_goto_static_table.x64.asm | 140 ++++++++++ .../asm/label_addr_array_init.aarch64.asm | 40 ++- .../asm/label_addr_array_init.x64.asm | 42 ++- .../asm/static_init_once_guard.aarch64.asm | 144 +++++++++++ .../asm/static_init_once_guard.x64.asm | 153 +++++++++++ .../snapshots/ssa/array_range_designator.ssa | 106 ++++---- .../ssa/computed_goto_static_table.ssa | 197 +++++++++++++++ tests/snapshots/ssa/label_addr_array_init.ssa | 160 +++++++----- .../snapshots/ssa/static_init_once_guard.ssa | 239 ++++++++++++++++++ 22 files changed, 1430 insertions(+), 130 deletions(-) create mode 100644 tests/fixtures/c/computed_goto_static_table.c create mode 100644 tests/fixtures/c/static_init_once_guard.c create mode 100644 tests/snapshots/asm/computed_goto_static_table.aarch64.asm create mode 100644 tests/snapshots/asm/computed_goto_static_table.x64.asm create mode 100644 tests/snapshots/asm/static_init_once_guard.aarch64.asm create mode 100644 tests/snapshots/asm/static_init_once_guard.x64.asm create mode 100644 tests/snapshots/ssa/computed_goto_static_table.ssa create mode 100644 tests/snapshots/ssa/static_init_once_guard.ssa diff --git a/src/c5/compiler/locals.rs b/src/c5/compiler/locals.rs index 4d775f630..5a5af4a7b 100644 --- a/src/c5/compiler/locals.rs +++ b/src/c5/compiler/locals.rs @@ -496,8 +496,19 @@ impl Compiler { /// element with runtime stores at the declaration point. The data /// image holds zeros; each element is parsed through the expression /// grammar (so `&&label` yields a block-address node) and stored into - /// `arr[i]` via an `Expr::Assign` statement the walker lowers to a - /// global address store. A constant element is stored the same way. + /// `arr[i]` via an `Expr::Assign` the walker lowers to a global + /// address store. A constant element is stored the same way. + /// + /// C99 6.2.4p3: static storage duration means one initialization for + /// the whole program run, so the stores are wrapped in a hidden + /// once-guard: a guard byte placed directly after the array's storage + /// (same data object -- no object start in between -- so data DCE and + /// linker rebase move it with the array). The whole declaration + /// lowers to a single statement `guard ? 0 : (e0, ..., en, guard = 1)` + /// because the enclosing declaration parse captures every pushed + /// stmt id as a top-level block item. + /// TODO: the generic fix resolves `&&label` elements in the data + /// image via label relocations, removing the runtime stores. pub(super) fn emit_static_array_init_runtime( &mut self, loc_idx: usize, @@ -522,12 +533,17 @@ impl Compiler { } c }; + let guard_off = self.data.len() as i64 - self.symbols[loc_idx].val; + for _ in 0..8 { + self.data.push(0); + } debug_assert!(self.lex.tk == '{'); self.next()?; // consume `{` // The array Ident decays to its base address; the index is the // element's byte offset, matching the walker's pre-scaled // `Expr::Index` convention. let arr_ty = ty + Ty::Ptr as i64; + let mut assigns: alloc::vec::Vec = alloc::vec::Vec::new(); let mut i: i64 = 0; while self.lex.tk != '}' { // Optional designator: `[N] = ...` (C99 6.7.8p6) or the GCC @@ -595,14 +611,65 @@ impl Compiler { }, pos, ); - self.ast - .push_stmt(super::super::ast::Stmt::Expr(assign_id), pos); + assigns.push(assign_id); } } i = range_end + 1; self.accept(',')?; } self.next()?; // consume `}` + if let Some(&first) = assigns.first() { + use super::super::ast::Expr; + let g_ty = Ty::Char as i64; + let guard_at = |c: &mut Self| { + let base = c.ast_emit_ident(loc_idx as u32, arr_ty); + let idx = c.ast_emit_int_lit(guard_off, Ty::Int as i64); + let pos = c.ast_src_pos(); + c.ast.push_expr( + Expr::Index { + array: base, + idx, + ty: g_ty, + }, + pos, + ) + }; + let guard_read = guard_at(self); + let guard_lhs = guard_at(self); + let one = self.ast_emit_int_lit(1, Ty::Int as i64); + let pos = self.ast_src_pos(); + let guard_set = self.ast.push_expr( + Expr::Assign { + lhs: guard_lhs, + rhs: one, + ty: g_ty, + }, + pos, + ); + let mut chain = first; + for &e in assigns.iter().skip(1).chain(core::iter::once(&guard_set)) { + chain = self.ast.push_expr( + Expr::Comma { + lhs: chain, + rhs: e, + ty: g_ty, + }, + pos, + ); + } + let zero = self.ast_emit_int_lit(0, Ty::Int as i64); + let guarded = self.ast.push_expr( + Expr::Ternary { + cond: guard_read, + then_e: zero, + else_e: chain, + ty: Ty::Int as i64, + }, + pos, + ); + self.ast + .push_stmt(super::super::ast::Stmt::Expr(guarded), pos); + } self.ast_acc = None; Ok(()) } diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index b76455ece..50df154c7 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1317,6 +1317,8 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index caf640afe..1f709e7d1 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -520,6 +520,8 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index 401c776b6..65fb5c22b 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -523,6 +523,8 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index dd1e449a3..66dbf4189 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -474,6 +474,8 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index 45ce3a8cd..b1b89f55e 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -769,6 +769,8 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index ef6a57b16..3079e3f69 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -784,6 +784,8 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("aggregate_init_struct_member_copy.c", 0), ("computed_goto.c", 0), ("label_addr_array_init.c", 0), + ("static_init_once_guard.c", 0), + ("computed_goto_static_table.c", 0), ("sieve_of_eratosthenes.c", 0), ("static_neg_infinity_init.c", 0), ("sub_word_return_narrow.c", 0), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 0009847cf..c62e2bc13 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -166,6 +166,21 @@ fn label_addr_array_init() { assert_eq!(run_fixture("label_addr_array_init.c"), 0); } +#[test] +fn static_init_once_guard() { + // C99 6.2.4p3: a static-local initialized by runtime stores + // (`&&label` elements) runs its initializer once; later calls + // must not clobber user writes to the table. + assert_eq!(run_fixture("static_init_once_guard.c"), 0); +} + +#[test] +fn computed_goto_static_table() { + // A static `&&label` dispatch table across repeated calls: the + // once-guard skip path must leave correct label addresses. + assert_eq!(run_fixture("computed_goto_static_table.c"), 0); +} + #[test] fn sieve_of_eratosthenes() { // Dense array write/read loop with a multiplicative inner stride; diff --git a/tests/fixtures/c/computed_goto_static_table.c b/tests/fixtures/c/computed_goto_static_table.c new file mode 100644 index 000000000..a1a862103 --- /dev/null +++ b/tests/fixtures/c/computed_goto_static_table.c @@ -0,0 +1,34 @@ +// A static `&&label` dispatch table driven across repeated calls: after +// the first call initializes the table, later calls take the once-guard +// skip path and must still dispatch through correct label addresses. +// The interpreter sums operands until halt; a second program re-enters +// the same function. + +static int interp(const unsigned char *code) { + static void *tbl[] = { &&op_add, &&op_sub, &&op_dup, &&op_halt }; + int acc = 0; + int pc = 0; + goto *tbl[code[pc++]]; +op_add: + acc += code[pc++]; + goto *tbl[code[pc++]]; +op_sub: + acc -= code[pc++]; + goto *tbl[code[pc++]]; +op_dup: + acc += acc; + goto *tbl[code[pc++]]; +op_halt: + return acc; +} + +int main(void) { + // ADD 5, DUP, SUB 3, HALT => (5*2)-3 = 7 + static const unsigned char p1[] = { 0, 5, 2, 1, 3, 3 }; + // ADD 9, SUB 4, DUP, HALT => (9-4)*2 = 10 + static const unsigned char p2[] = { 0, 9, 1, 4, 2, 3 }; + if (interp(p1) != 7) return 1; + if (interp(p2) != 10) return 2; + if (interp(p1) != 7) return 3; + return 0; +} diff --git a/tests/fixtures/c/static_init_once_guard.c b/tests/fixtures/c/static_init_once_guard.c new file mode 100644 index 000000000..896e69ec2 --- /dev/null +++ b/tests/fixtures/c/static_init_once_guard.c @@ -0,0 +1,43 @@ +// C99 6.2.4p3: an object with static storage duration is initialized +// exactly once, before program startup semantics apply to its lifetime. +// A static-local array whose initializer carries `&&label` elements is +// filled by runtime stores at the declaration point; those stores must +// not re-run on later calls, or they clobber user writes to the table. + +static void *saved; + +static int step(int n) { + static void *tbl[] = { &&l1, &&l2 }; + if (n == 0) { + // First call: record the original entry, then redirect slot 0. + saved = tbl[0]; + tbl[0] = tbl[1]; + goto *tbl[1]; + } + // Second call: the redirect must have survived the re-entry. + if (tbl[0] != tbl[1]) return 1; + tbl[0] = saved; + goto *tbl[0]; +l1: + return 10; +l2: + return 20; +} + +// A logical AND inside a constant element routes to the same runtime +// path (the initializer scan keys on the `&&` token), so its once +// semantics are locked too. +static int flag_table(int n, int set) { + static int flags[3] = { 1 && 1, 0, 1 }; + if (set) flags[1] = 7; + return flags[n]; +} + +int main(void) { + if (step(0) != 20) return 2; + if (step(1) != 10) return 3; + if (flag_table(1, 1) != 7) return 4; + if (flag_table(1, 0) != 7) return 5; + if (flag_table(0, 0) != 1) return 6; + return 0; +} diff --git a/tests/snapshots/asm/array_range_designator.aarch64.asm b/tests/snapshots/asm/array_range_designator.aarch64.asm index fbd50faaf..92ab35a09 100644 --- a/tests/snapshots/asm/array_range_designator.aarch64.asm +++ b/tests/snapshots/asm/array_range_designator.aarch64.asm @@ -84,9 +84,15 @@ Disassembly of section .text: str x0, [sp, #-0x10]! stp x29, x30, [sp, #-0x10]! mov x29, sp + sub sp, sp, #0x10 stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x40] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x8] + b adr x1, str x1, [x0] adr x1, @@ -103,18 +109,24 @@ Disassembly of section .text: str x1, [x0, #0x30] adr x1, str x1, [x0, #0x38] + mov x1, #0x1 // =1 + strb w1, [x0, #0x40] + stur x1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] br x0 mov x0, #0x64 // =100 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret mov x0, #0xc8 // =200 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret mov x0, #0x3e7 // =999 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 add sp, sp, #0x10 ret diff --git a/tests/snapshots/asm/array_range_designator.x64.asm b/tests/snapshots/asm/array_range_designator.x64.asm index f65c82e32..e0b5d688f 100644 --- a/tests/snapshots/asm/array_range_designator.x64.asm +++ b/tests/snapshots/asm/array_range_designator.x64.asm @@ -99,8 +99,15 @@ Disassembly of section .text: pushq %r10 pushq %rbp movq %rsp, %rbp + subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x40(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x8(%rbp) + jmp leaq , %rcx # movq %rcx, (%rax) leaq , %rcx # @@ -117,22 +124,28 @@ Disassembly of section .text: movq %rcx, 0x30(%rax) leaq , %rcx # movq %rcx, 0x38(%rax) + movl $0x1, %ecx + movb %cl, 0x40(%rax) + movq %rcx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax jmpq *%rax movl $0x64, %eax + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq movl $0xc8, %eax + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp pushq %r11 retq movl $0x3e7, %eax # imm = 0x3E7 + addq $0x10, %rsp popq %rbp popq %r11 addq $0x10, %rsp diff --git a/tests/snapshots/asm/computed_goto_static_table.aarch64.asm b/tests/snapshots/asm/computed_goto_static_table.aarch64.asm new file mode 100644 index 000000000..f82a917cb --- /dev/null +++ b/tests/snapshots/asm/computed_goto_static_table.aarch64.asm @@ -0,0 +1,135 @@ + +computed_goto_static_table.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + stur x0, [x29, #0x10] + adrp x0, + add x0, x0, + ldrsb x1, [x0, #0x20] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x18] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + adr x1, + str x1, [x0, #0x18] + mov x1, #0x1 // =1 + strb w1, [x0, #0x20] + stur x1, [x29, #-0x18] + mov x1, #0x0 // =0 + stur w1, [x29, #-0x8] + stur w1, [x29, #-0x10] + ldur x1, [x29, #0x10] + ldursw x2, [x29, #-0x10] + add x3, x2, #0x1 + stur w3, [x29, #-0x10] + add x1, x1, x2 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + ldur x2, [x29, #0x10] + ldursw x3, [x29, #-0x10] + add x4, x3, #0x1 + stur w4, [x29, #-0x10] + add x3, x2, x3 + ldrb w3, [x3] + add x1, x1, x3 + stur w1, [x29, #-0x8] + ldursw x1, [x29, #-0x10] + add x3, x1, #0x1 + stur w3, [x29, #-0x10] + add x1, x2, x1 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + ldur x2, [x29, #0x10] + ldursw x3, [x29, #-0x10] + add x4, x3, #0x1 + stur w4, [x29, #-0x10] + add x3, x2, x3 + ldrb w3, [x3] + sub x1, x1, x3 + stur w1, [x29, #-0x8] + ldursw x1, [x29, #-0x10] + add x3, x1, #0x1 + stur w3, [x29, #-0x10] + add x1, x2, x1 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x1, [x29, #-0x8] + add x1, x1, x1 + stur w1, [x29, #-0x8] + ldur x1, [x29, #0x10] + ldursw x2, [x29, #-0x10] + add x3, x2, #0x1 + stur w3, [x29, #-0x10] + add x1, x1, x2 + ldrb w1, [x1] + ldr x1, [x0, x1, lsl #3] + br x1 + ldursw x0, [x29, #-0x8] + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + str x20, [sp] + adrp x20, + add x20, x20, + mov x0, x20 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x1 // =1 + ldr x20, [sp] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + adrp x0, + add x0, x0, + bl + cmp x0, #0xa + b.eq + mov x0, #0x2 // =2 + ldr x20, [sp] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, x20 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x3 // =3 + ldr x20, [sp] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldr x20, [sp] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/computed_goto_static_table.x64.asm b/tests/snapshots/asm/computed_goto_static_table.x64.asm new file mode 100644 index 000000000..e119495e5 --- /dev/null +++ b/tests/snapshots/asm/computed_goto_static_table.x64.asm @@ -0,0 +1,140 @@ + +computed_goto_static_table.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x20, %rsp + movq %rdi, 0x10(%rbp) + leaq , %rax + movsbq 0x20(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x18(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + leaq , %rcx # + movq %rcx, 0x18(%rax) + movl $0x1, %ecx + movb %cl, 0x20(%rax) + movq %rcx, -0x18(%rbp) + xorq %rcx, %rcx + movl %ecx, -0x8(%rbp) + movl %ecx, -0x10(%rbp) + movq 0x10(%rbp), %rcx + movslq -0x10(%rbp), %rdx + leaq 0x1(%rdx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + movq 0x10(%rbp), %rdx + movslq -0x10(%rbp), %rsi + leaq 0x1(%rsi), %rdi + movl %edi, -0x10(%rbp) + addq %rdx, %rsi + movzbq (%rsi), %rsi + addq %rsi, %rcx + movl %ecx, -0x8(%rbp) + movslq -0x10(%rbp), %rcx + leaq 0x1(%rcx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + movq 0x10(%rbp), %rdx + movslq -0x10(%rbp), %rsi + leaq 0x1(%rsi), %rdi + movl %edi, -0x10(%rbp) + addq %rdx, %rsi + movzbq (%rsi), %rsi + subq %rsi, %rcx + movl %ecx, -0x8(%rbp) + movslq -0x10(%rbp), %rcx + leaq 0x1(%rcx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rcx + addq %rcx, %rcx + movl %ecx, -0x8(%rbp) + movq 0x10(%rbp), %rcx + movslq -0x10(%rbp), %rdx + leaq 0x1(%rdx), %rsi + movl %esi, -0x10(%rbp) + addq %rdx, %rcx + movzbq (%rcx), %rcx + movq (%rax,%rcx,8), %rcx + jmpq *%rcx + movslq -0x8(%rbp), %rax + addq $0x20, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + +
: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movq %rbx, (%rsp) + leaq , %rbx + movq %rbx, %rdi + callq + cmpq $0x7, %rax + je + movl $0x1, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + leaq , %rdi + callq + cmpq $0xa, %rax + je + movl $0x2, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + movq %rbx, %rdi + callq + cmpq $0x7, %rax + je + movl $0x3, %eax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + xorq %rax, %rax + movq (%rsp), %rbx + addq $0x10, %rsp + popq %rbp + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/label_addr_array_init.aarch64.asm b/tests/snapshots/asm/label_addr_array_init.aarch64.asm index 8d5081aa9..dff5c095a 100644 --- a/tests/snapshots/asm/label_addr_array_init.aarch64.asm +++ b/tests/snapshots/asm/label_addr_array_init.aarch64.asm @@ -52,13 +52,21 @@ Disassembly of section .text: stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x18] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x10] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + mov x1, #0x1 // =1 + strb w1, [x0, #0x18] + stur x1, [x29, #-0x10] mov x1, #0x0 // =0 - adr x2, - str x2, [x0] - adr x2, - str x2, [x0, #0x8] - adr x2, - str x2, [x0, #0x10] stur w1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] @@ -85,13 +93,21 @@ Disassembly of section .text: stur w0, [x29, #0x10] adrp x0, add x0, x0, + ldrsb x1, [x0, #0x18] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x10] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + adr x1, + str x1, [x0, #0x10] + mov x1, #0x1 // =1 + strb w1, [x0, #0x18] + stur x1, [x29, #-0x10] mov x1, #0x0 // =0 - adr x2, - str x2, [x0] - adr x2, - str x2, [x0, #0x8] - adr x2, - str x2, [x0, #0x10] stur w1, [x29, #-0x8] ldursw x1, [x29, #0x10] ldr x0, [x0, x1, lsl #3] diff --git a/tests/snapshots/asm/label_addr_array_init.x64.asm b/tests/snapshots/asm/label_addr_array_init.x64.asm index 0930f8ae9..29b8260c4 100644 --- a/tests/snapshots/asm/label_addr_array_init.x64.asm +++ b/tests/snapshots/asm/label_addr_array_init.x64.asm @@ -60,13 +60,22 @@ Disassembly of section .text: subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x18(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x10(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + movl $0x1, %ecx + movb %cl, 0x18(%rax) + movq %rcx, -0x10(%rbp) xorq %rcx, %rcx - leaq , %rdx # - movq %rdx, (%rax) - leaq , %rdx # - movq %rdx, 0x8(%rax) - leaq , %rdx # - movq %rdx, 0x10(%rax) movl %ecx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax @@ -97,13 +106,22 @@ Disassembly of section .text: subq $0x10, %rsp movl %edi, 0x10(%rbp) leaq , %rax + movsbq 0x18(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x10(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + leaq , %rcx # + movq %rcx, 0x10(%rax) + movl $0x1, %ecx + movb %cl, 0x18(%rax) + movq %rcx, -0x10(%rbp) xorq %rcx, %rcx - leaq , %rdx # - movq %rdx, (%rax) - leaq , %rdx # - movq %rdx, 0x8(%rax) - leaq , %rdx # - movq %rdx, 0x10(%rax) movl %ecx, -0x8(%rbp) movslq 0x10(%rbp), %rcx movq (%rax,%rcx,8), %rax diff --git a/tests/snapshots/asm/static_init_once_guard.aarch64.asm b/tests/snapshots/asm/static_init_once_guard.aarch64.asm new file mode 100644 index 000000000..fe313a8ce --- /dev/null +++ b/tests/snapshots/asm/static_init_once_guard.aarch64.asm @@ -0,0 +1,144 @@ + +static_init_once_guard.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + str x0, [sp, #-0x10]! + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + stur w0, [x29, #0x10] + adrp x0, + add x0, x0, + ldrsb x1, [x0, #0x10] + cbz x1, + mov x1, #0x0 // =0 + stur x1, [x29, #-0x8] + b + adr x1, + str x1, [x0] + adr x1, + str x1, [x0, #0x8] + mov x1, #0x1 // =1 + strb w1, [x0, #0x10] + stur x1, [x29, #-0x8] + ldursw x1, [x29, #0x10] + cmp x1, #0x0 + b.ne + b + mov x0, #0xa // =10 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + mov x0, #0x14 // =20 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + adrp x1, + add x1, x1, + ldr x2, [x0] + str x2, [x1] + ldr x1, [x0, #0x8] + str x1, [x0] + ldr x0, [x0, #0x8] + br x0 + ldr x1, [x0] + ldr x2, [x0, #0x8] + cmp x1, x2 + b.eq + mov x0, #0x1 // =1 + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + add sp, sp, #0x10 + ret + adrp x1, + add x1, x1, + ldr x1, [x1] + str x1, [x0] + ldr x0, [x0] + br x0 + +: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + sxtw x0, w0 + sxtw x1, w1 + adrp x2, + add x2, x2, + ldrsb x3, [x2, #0x10] + cbz x3, + mov x4, #0x0 // =0 + b + mov x5, #0x0 // =0 + b + cbz x1, + b + mov x5, #0x1 // =1 + str w5, [x2] + mov x3, #0x0 // =0 + str w3, [x2, #0x4] + mov x4, #0x1 // =1 + str w4, [x2, #0x8] + strb w4, [x2, #0x10] + b + mov x1, #0x7 // =7 + str w1, [x2, #0x4] + ldrsw x0, [x2, x0, lsl #2] + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret + +
: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x0, #0x0 // =0 + bl + cmp x0, #0x14 + b.eq + mov x0, #0x2 // =2 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + bl + cmp x0, #0xa + b.eq + mov x0, #0x3 // =3 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, x0 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x4 // =4 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x1 // =1 + mov x1, #0x0 // =0 + bl + cmp x0, #0x7 + b.eq + mov x0, #0x5 // =5 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + mov x1, x0 + bl + cmp x0, #0x1 + b.eq + mov x0, #0x6 // =6 + ldp x29, x30, [sp], #0x10 + ret + mov x0, #0x0 // =0 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/snapshots/asm/static_init_once_guard.x64.asm b/tests/snapshots/asm/static_init_once_guard.x64.asm new file mode 100644 index 000000000..2b5721a94 --- /dev/null +++ b/tests/snapshots/asm/static_init_once_guard.x64.asm @@ -0,0 +1,153 @@ + +static_init_once_guard.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +: + popq %r10 + subq $0x10, %rsp + movq %rdi, (%rsp) + pushq %r10 + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movl %edi, 0x10(%rbp) + leaq , %rax + movsbq 0x10(%rax), %rcx + testq %rcx, %rcx + je + xorq %rcx, %rcx + movq %rcx, -0x8(%rbp) + jmp + leaq , %rcx # + movq %rcx, (%rax) + leaq , %rcx # + movq %rcx, 0x8(%rax) + movl $0x1, %ecx + movb %cl, 0x10(%rax) + movq %rcx, -0x8(%rbp) + movslq 0x10(%rbp), %rcx + testq %rcx, %rcx + jne + jmp + movl $0xa, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + movl $0x14, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + leaq , %rcx + movq (%rax), %rdx + movq %rdx, (%rcx) + movq 0x8(%rax), %rcx + movq %rcx, (%rax) + movq 0x8(%rax), %rax + jmpq *%rax + movq (%rax), %rcx + movq 0x8(%rax), %rdx + cmpq %rdx, %rcx + je + movl $0x1, %eax + addq $0x10, %rsp + popq %rbp + popq %r11 + addq $0x10, %rsp + pushq %r11 + retq + leaq , %rcx + movq (%rcx), %rcx + movq %rcx, (%rax) + movq (%rax), %rax + jmpq *%rax + +: + pushq %rbp + movq %rsp, %rbp + subq $0x10, %rsp + movslq %edi, %rdi + movslq %esi, %rsi + leaq , %rax + movsbq 0x10(%rax), %rcx + testq %rcx, %rcx + je + xorq %rdx, %rdx + jmp + xorq %r8, %r8 + jmp + testq %rsi, %rsi + je + jmp + movl $0x1, %r8d + movl %r8d, (%rax) + xorq %rcx, %rcx + movl %ecx, 0x4(%rax) + movl $0x1, %edx + movl %edx, 0x8(%rax) + movb %dl, 0x10(%rax) + jmp + movl $0x7, %ecx + movl %ecx, 0x4(%rax) + movslq (%rax,%rdi,4), %rax + addq $0x10, %rsp + popq %rbp + retq + +
: + pushq %rbp + movq %rsp, %rbp + xorq %rdi, %rdi + callq + cmpq $0x14, %rax + je + movl $0x2, %eax + popq %rbp + retq + movl $0x1, %edi + callq + cmpq $0xa, %rax + je + movl $0x3, %eax + popq %rbp + retq + movl $0x1, %edi + movq %rdi, %rsi + callq + cmpq $0x7, %rax + je + movl $0x4, %eax + popq %rbp + retq + movl $0x1, %edi + xorq %rsi, %rsi + callq + cmpq $0x7, %rax + je + movl $0x5, %eax + popq %rbp + retq + xorq %rdi, %rdi + movq %rdi, %rsi + callq + cmpq $0x1, %rax + je + movl $0x6, %eax + popq %rbp + retq + xorq %rax, %rax + popq %rbp + retq diff --git a/tests/snapshots/ssa/array_range_designator.ssa b/tests/snapshots/ssa/array_range_designator.ssa index 63513624c..cc74d3e03 100644 --- a/tests/snapshots/ssa/array_range_designator.ssa +++ b/tests/snapshots/ssa/array_range_designator.ssa @@ -112,58 +112,78 @@ fn ent_pc=0 n_params=0 variadic=false locals=3 terminator Jmp(b16) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=dispatch -fn ent_pc=1 n_params=1 variadic=false locals=0 +fn ent_pc=1 n_params=1 variadic=false locals=1 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - v3 ImmData(72) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x1 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x1 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 - v9 BlockAddr(block=2) -> x1 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x1 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 - v13 BlockAddr(block=3) -> x1 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 Imm(24) -> x1 - v16 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 - v17 BlockAddr(block=3) -> x1 - v18 Store { addr=v3, disp=24, value=v17, kind=I64 } -> - - v19 Imm(32) -> x1 - v20 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 - v21 BlockAddr(block=3) -> x1 - v22 Store { addr=v3, disp=32, value=v21, kind=I64 } -> - - v23 Imm(40) -> x1 - v24 BinopI { op=add, lhs=v3, rhs_imm=40 } -> x1 - v25 BlockAddr(block=3) -> x1 - v26 Store { addr=v3, disp=40, value=v25, kind=I64 } -> - - v27 Imm(48) -> x1 - v28 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x1 - v29 BlockAddr(block=3) -> x1 - v30 Store { addr=v3, disp=48, value=v29, kind=I64 } -> - - v31 Imm(56) -> x1 - v32 BinopI { op=add, lhs=v3, rhs_imm=56 } -> x1 - v33 BlockAddr(block=3) -> x1 - v34 Store { addr=v3, disp=56, value=v33, kind=I64 } -> - - v35 LoadLocal { off=2, kind=I32 } -> x1 - v36 BinopI { op=shl, lhs=v35, rhs_imm=3 } -> x2 - v37 Binop { op=add, lhs=v3, rhs=v36 } -> x2 - v38 LoadIndexed { base=v3, index=v35, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v38) (exit_acc=v38) + v4 Imm(64) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=64 } -> x1 + v6 Load { addr=v3, disp=64, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v39 Imm(100) -> x0 - terminator Return(v39) (exit_acc=v39) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-1, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v40 Imm(200) -> x0 - terminator Return(v40) (exit_acc=v40) + v9 ImmData(72) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 BlockAddr(block=6) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I64 } -> - + v25 Imm(32) -> x1 + v26 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v27 BlockAddr(block=6) -> x1 + v28 Store { addr=v3, disp=32, value=v27, kind=I64 } -> - + v29 Imm(40) -> x1 + v30 BinopI { op=add, lhs=v3, rhs_imm=40 } -> x1 + v31 BlockAddr(block=6) -> x1 + v32 Store { addr=v3, disp=40, value=v31, kind=I64 } -> - + v33 Imm(48) -> x1 + v34 BinopI { op=add, lhs=v3, rhs_imm=48 } -> x1 + v35 BlockAddr(block=6) -> x1 + v36 Store { addr=v3, disp=48, value=v35, kind=I64 } -> - + v37 Imm(56) -> x1 + v38 BinopI { op=add, lhs=v3, rhs_imm=56 } -> x1 + v39 BlockAddr(block=6) -> x1 + v40 Store { addr=v3, disp=56, value=v39, kind=I64 } -> - + v41 Imm(64) -> x1 + v42 BinopI { op=add, lhs=v3, rhs_imm=64 } -> x1 + v43 Imm(1) -> x1 + v44 Store { addr=v3, disp=64, value=v43, kind=I8 } -> - + v45 Imm(72057594037927936) -> x2 + v46 StoreLocal { off=-1, value=v43, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v46) block 3 start_pc=0 - v41 Imm(999) -> x0 - terminator Return(v41) (exit_acc=v41) + v47 LoadLocal { off=-1, kind=I64 } -> x1 + v48 ImmData(72) -> x1 + v49 LoadLocal { off=2, kind=I32 } -> x1 + v50 BinopI { op=shl, lhs=v49, rhs_imm=3 } -> x2 + v51 Binop { op=add, lhs=v3, rhs=v50 } -> x2 + v52 LoadIndexed { base=v3, index=v49, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v52) (exit_acc=v52) + block 4 start_pc=0 + v53 Imm(100) -> x0 + terminator Return(v53) (exit_acc=v53) + block 5 start_pc=0 + v54 Imm(200) -> x0 + terminator Return(v54) (exit_acc=v54) + block 6 start_pc=0 + v55 Imm(999) -> x0 + terminator Return(v55) (exit_acc=v55) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main fn ent_pc=2 n_params=0 variadic=false locals=2 diff --git a/tests/snapshots/ssa/computed_goto_static_table.ssa b/tests/snapshots/ssa/computed_goto_static_table.ssa new file mode 100644 index 000000000..a83c6c2a7 --- /dev/null +++ b/tests/snapshots/ssa/computed_goto_static_table.ssa @@ -0,0 +1,197 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=interp +fn ent_pc=0 n_params=1 variadic=false locals=3 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I64 } -> - + v3 ImmData(8) -> x0 + v4 Imm(32) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v6 Load { addr=v3, disp=32, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(0) -> x1 + v8 StoreLocal { off=-3, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) + block 2 start_pc=0 + v9 ImmData(8) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 BlockAddr(block=7) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I64 } -> - + v25 Imm(32) -> x1 + v26 BinopI { op=add, lhs=v3, rhs_imm=32 } -> x1 + v27 Imm(1) -> x1 + v28 Store { addr=v3, disp=32, value=v27, kind=I8 } -> - + v29 Imm(72057594037927936) -> x2 + v30 StoreLocal { off=-3, value=v27, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v30) + block 3 start_pc=0 + v31 LoadLocal { off=-3, kind=I64 } -> x1 + v32 Imm(0) -> x1 + v33 StoreLocal { off=-1, value=v32, kind=I32 } -> - + v34 StoreLocal { off=-2, value=v32, kind=I32 } -> - + v35 ImmData(8) -> x1 + v36 LoadLocal { off=2, kind=I64 } -> x1 + v37 LoadLocal { off=-2, kind=I32 } -> x2 + v38 BinopI { op=add, lhs=v37, rhs_imm=1 } -> x6 + v39 StoreLocal { off=-2, value=v38, kind=I32 } -> - + v40 Binop { op=add, lhs=v36, rhs=v37 } -> x1 + v41 Load { addr=v40, disp=0, kind=U8 } -> x1 + v42 BinopI { op=shl, lhs=v41, rhs_imm=3 } -> x2 + v43 Binop { op=add, lhs=v3, rhs=v42 } -> x2 + v44 LoadIndexed { base=v3, index=v41, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v44) (exit_acc=v44) + block 4 start_pc=0 + v45 LoadLocal { off=-1, kind=I32 } -> x1 + v46 LoadLocal { off=2, kind=I64 } -> x2 + v47 LoadLocal { off=-2, kind=I32 } -> x6 + v48 BinopI { op=add, lhs=v47, rhs_imm=1 } -> x7 + v49 StoreLocal { off=-2, value=v48, kind=I32 } -> - + v50 Binop { op=add, lhs=v46, rhs=v47 } -> x6 + v51 Load { addr=v50, disp=0, kind=U8 } -> x6 + v52 Binop { op=add, lhs=v45, rhs=v51 } -> x1 + v53 StoreLocal { off=-1, value=v52, kind=I32 } -> - + v54 LoadLocal { off=-1, kind=I32 } -> x1 + v55 ImmData(8) -> x1 + v56 LoadLocal { off=-2, kind=I32 } -> x1 + v57 BinopI { op=add, lhs=v56, rhs_imm=1 } -> x6 + v58 StoreLocal { off=-2, value=v57, kind=I32 } -> - + v59 Binop { op=add, lhs=v46, rhs=v56 } -> x1 + v60 Load { addr=v59, disp=0, kind=U8 } -> x1 + v61 BinopI { op=shl, lhs=v60, rhs_imm=3 } -> x2 + v62 Binop { op=add, lhs=v3, rhs=v61 } -> x2 + v63 LoadIndexed { base=v3, index=v60, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v63) (exit_acc=v63) + block 5 start_pc=0 + v64 LoadLocal { off=-1, kind=I32 } -> x1 + v65 LoadLocal { off=2, kind=I64 } -> x2 + v66 LoadLocal { off=-2, kind=I32 } -> x6 + v67 BinopI { op=add, lhs=v66, rhs_imm=1 } -> x7 + v68 StoreLocal { off=-2, value=v67, kind=I32 } -> - + v69 Binop { op=add, lhs=v65, rhs=v66 } -> x6 + v70 Load { addr=v69, disp=0, kind=U8 } -> x6 + v71 Binop { op=sub, lhs=v64, rhs=v70 } -> x1 + v72 StoreLocal { off=-1, value=v71, kind=I32 } -> - + v73 LoadLocal { off=-1, kind=I32 } -> x1 + v74 ImmData(8) -> x1 + v75 LoadLocal { off=-2, kind=I32 } -> x1 + v76 BinopI { op=add, lhs=v75, rhs_imm=1 } -> x6 + v77 StoreLocal { off=-2, value=v76, kind=I32 } -> - + v78 Binop { op=add, lhs=v65, rhs=v75 } -> x1 + v79 Load { addr=v78, disp=0, kind=U8 } -> x1 + v80 BinopI { op=shl, lhs=v79, rhs_imm=3 } -> x2 + v81 Binop { op=add, lhs=v3, rhs=v80 } -> x2 + v82 LoadIndexed { base=v3, index=v79, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v82) (exit_acc=v82) + block 6 start_pc=0 + v83 LoadLocal { off=-1, kind=I32 } -> x1 + v84 Binop { op=add, lhs=v83, rhs=v83 } -> x1 + v85 StoreLocal { off=-1, value=v84, kind=I32 } -> - + v86 LoadLocal { off=-1, kind=I32 } -> x1 + v87 ImmData(8) -> x1 + v88 LoadLocal { off=2, kind=I64 } -> x1 + v89 LoadLocal { off=-2, kind=I32 } -> x2 + v90 BinopI { op=add, lhs=v89, rhs_imm=1 } -> x6 + v91 StoreLocal { off=-2, value=v90, kind=I32 } -> - + v92 Binop { op=add, lhs=v88, rhs=v89 } -> x1 + v93 Load { addr=v92, disp=0, kind=U8 } -> x1 + v94 BinopI { op=shl, lhs=v93, rhs_imm=3 } -> x2 + v95 Binop { op=add, lhs=v3, rhs=v94 } -> x2 + v96 LoadIndexed { base=v3, index=v93, scale=8, kind=I64 } -> x1 + terminator GotoIndirect(v96) (exit_acc=v96) + block 7 start_pc=0 + v97 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v97) (exit_acc=v97) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=main +fn ent_pc=1 n_params=0 variadic=false locals=1 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ImmData(48) -> x3 + v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v3 BinopI { op=ne, lhs=v2, rhs_imm=7 } -> x0 + terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + block 1 start_pc=0 + v4 Imm(1) -> x0 + terminator Return(v4) (exit_acc=v4) + block 2 start_pc=0 + v5 ImmData(56) -> x7 + v6 Call { target_pc=0, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=ne, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + block 3 start_pc=0 + v8 Imm(2) -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + v9 ImmData(48) -> x0 + v10 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x0 + terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + block 5 start_pc=0 + v12 Imm(3) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 + v13 Imm(0) -> x0 + terminator Return(v13) (exit_acc=v13) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/label_addr_array_init.ssa b/tests/snapshots/ssa/label_addr_array_init.ssa index 547f2b214..f6f3a593f 100644 --- a/tests/snapshots/ssa/label_addr_array_init.ssa +++ b/tests/snapshots/ssa/label_addr_array_init.ssa @@ -42,86 +42,128 @@ fn ent_pc=0 n_params=1 variadic=false locals=4 terminator Return(v27) (exit_acc=v27) ; --- SSA dump (ok=true) ent_pc=1 --- ; name=run_static -fn ent_pc=1 n_params=1 variadic=false locals=1 +fn ent_pc=1 n_params=1 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - v3 ImmData(8) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x2 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x2 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 - v9 BlockAddr(block=2) -> x2 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x2 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x2 - v13 BlockAddr(block=3) -> x2 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 StoreLocal { off=-1, value=v4, kind=I32 } -> - - v16 LoadLocal { off=2, kind=I32 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=3 } -> x2 - v18 Binop { op=add, lhs=v3, rhs=v17 } -> x2 - v19 LoadIndexed { base=v3, index=v16, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v19) (exit_acc=v19) + v4 Imm(24) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v6 Load { addr=v3, disp=24, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v20 Imm(1) -> x0 - v21 StoreLocal { off=-1, value=v20, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v21) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-2, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v22 Imm(2) -> x0 - v23 StoreLocal { off=-1, value=v22, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v23) + v9 ImmData(8) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 Imm(1) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I8 } -> - + v25 Imm(72057594037927936) -> x2 + v26 StoreLocal { off=-2, value=v23, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v26) block 3 start_pc=0 - v24 Imm(3) -> x0 - v25 StoreLocal { off=-1, value=v24, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v25) + v27 LoadLocal { off=-2, kind=I64 } -> x1 + v28 Imm(0) -> x1 + v29 StoreLocal { off=-1, value=v28, kind=I32 } -> - + v30 ImmData(8) -> x1 + v31 LoadLocal { off=2, kind=I32 } -> x1 + v32 BinopI { op=shl, lhs=v31, rhs_imm=3 } -> x2 + v33 Binop { op=add, lhs=v3, rhs=v32 } -> x2 + v34 LoadIndexed { base=v3, index=v31, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v34) (exit_acc=v34) block 4 start_pc=0 - v26 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v26) (exit_acc=v26) + v35 Imm(1) -> x0 + v36 StoreLocal { off=-1, value=v35, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v36) + block 5 start_pc=0 + v37 Imm(2) -> x0 + v38 StoreLocal { off=-1, value=v37, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v38) + block 6 start_pc=0 + v39 Imm(3) -> x0 + v40 StoreLocal { off=-1, value=v39, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v40) + block 7 start_pc=0 + v41 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=2 --- ; name=run_static_const -fn ent_pc=2 n_params=1 variadic=false locals=1 +fn ent_pc=2 n_params=1 variadic=false locals=2 spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - v1 ParamRef(0, kind=I32) -> x7 v2 StoreLocal { off=2, value=v1, kind=I32 } -> - - v3 ImmData(32) -> x0 - v4 Imm(0) -> x1 - v5 BlockAddr(block=1) -> x2 - v6 Store { addr=v3, disp=0, value=v5, kind=I64 } -> - - v7 Imm(8) -> x2 - v8 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 - v9 BlockAddr(block=2) -> x2 - v10 Store { addr=v3, disp=8, value=v9, kind=I64 } -> - - v11 Imm(16) -> x2 - v12 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x2 - v13 BlockAddr(block=3) -> x2 - v14 Store { addr=v3, disp=16, value=v13, kind=I64 } -> - - v15 StoreLocal { off=-1, value=v4, kind=I32 } -> - - v16 LoadLocal { off=2, kind=I32 } -> x1 - v17 BinopI { op=shl, lhs=v16, rhs_imm=3 } -> x2 - v18 Binop { op=add, lhs=v3, rhs=v17 } -> x2 - v19 LoadIndexed { base=v3, index=v16, scale=8, kind=I64 } -> x0 - terminator GotoIndirect(v19) (exit_acc=v19) + v3 ImmData(40) -> x0 + v4 Imm(24) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v6 Load { addr=v3, disp=24, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) block 1 start_pc=0 - v20 Imm(100) -> x0 - v21 StoreLocal { off=-1, value=v20, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v21) + v7 Imm(0) -> x1 + v8 StoreLocal { off=-2, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) block 2 start_pc=0 - v22 Imm(200) -> x0 - v23 StoreLocal { off=-1, value=v22, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v23) + v9 ImmData(40) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 BlockAddr(block=6) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I64 } -> - + v21 Imm(24) -> x1 + v22 BinopI { op=add, lhs=v3, rhs_imm=24 } -> x1 + v23 Imm(1) -> x1 + v24 Store { addr=v3, disp=24, value=v23, kind=I8 } -> - + v25 Imm(72057594037927936) -> x2 + v26 StoreLocal { off=-2, value=v23, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v26) block 3 start_pc=0 - v24 Imm(300) -> x0 - v25 StoreLocal { off=-1, value=v24, kind=I32 } -> - - terminator Jmp(b4) (exit_acc=v25) + v27 LoadLocal { off=-2, kind=I64 } -> x1 + v28 Imm(0) -> x1 + v29 StoreLocal { off=-1, value=v28, kind=I32 } -> - + v30 ImmData(40) -> x1 + v31 LoadLocal { off=2, kind=I32 } -> x1 + v32 BinopI { op=shl, lhs=v31, rhs_imm=3 } -> x2 + v33 Binop { op=add, lhs=v3, rhs=v32 } -> x2 + v34 LoadIndexed { base=v3, index=v31, scale=8, kind=I64 } -> x0 + terminator GotoIndirect(v34) (exit_acc=v34) block 4 start_pc=0 - v26 LoadLocal { off=-1, kind=I32 } -> x0 - terminator Return(v26) (exit_acc=v26) + v35 Imm(100) -> x0 + v36 StoreLocal { off=-1, value=v35, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v36) + block 5 start_pc=0 + v37 Imm(200) -> x0 + v38 StoreLocal { off=-1, value=v37, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v38) + block 6 start_pc=0 + v39 Imm(300) -> x0 + v40 StoreLocal { off=-1, value=v39, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v40) + block 7 start_pc=0 + v41 LoadLocal { off=-1, kind=I32 } -> x0 + terminator Return(v41) (exit_acc=v41) ; --- SSA dump (ok=true) ent_pc=3 --- ; name=main fn ent_pc=3 n_params=0 variadic=false locals=1 diff --git a/tests/snapshots/ssa/static_init_once_guard.ssa b/tests/snapshots/ssa/static_init_once_guard.ssa new file mode 100644 index 000000000..b2c457ee6 --- /dev/null +++ b/tests/snapshots/ssa/static_init_once_guard.ssa @@ -0,0 +1,239 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=step +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 StoreLocal { off=2, value=v1, kind=I32 } -> - + v3 ImmData(32) -> x0 + v4 Imm(16) -> x1 + v5 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v6 Load { addr=v3, disp=16, kind=I8 } -> x1 + terminator Bz { cond=v6, target=b2, fall=b1 } (exit_acc=v6) + block 1 start_pc=0 + v7 Imm(0) -> x1 + v8 StoreLocal { off=-1, value=v7, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v8) + block 2 start_pc=0 + v9 ImmData(32) -> x1 + v10 Imm(0) -> x1 + v11 BlockAddr(block=4) -> x1 + v12 Store { addr=v3, disp=0, value=v11, kind=I64 } -> - + v13 Imm(8) -> x1 + v14 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v15 BlockAddr(block=5) -> x1 + v16 Store { addr=v3, disp=8, value=v15, kind=I64 } -> - + v17 Imm(16) -> x1 + v18 BinopI { op=add, lhs=v3, rhs_imm=16 } -> x1 + v19 Imm(1) -> x1 + v20 Store { addr=v3, disp=16, value=v19, kind=I8 } -> - + v21 Imm(72057594037927936) -> x2 + v22 StoreLocal { off=-1, value=v19, kind=I64 } -> - + terminator Jmp(b3) (exit_acc=v22) + block 3 start_pc=0 + v23 LoadLocal { off=-1, kind=I64 } -> x1 + v24 LoadLocal { off=2, kind=I32 } -> x1 + v25 BinopI { op=eq, lhs=v24, rhs_imm=0 } -> x1 + terminator Bz { cond=v25, target=b7, fall=b6 } (exit_acc=v25) + block 4 start_pc=0 + v50 Imm(10) -> x0 + terminator Return(v50) (exit_acc=v50) + block 5 start_pc=0 + v51 Imm(20) -> x0 + terminator Return(v51) (exit_acc=v51) + block 6 start_pc=0 + v26 ImmData(24) -> x1 + v27 ImmData(32) -> x2 + v28 Imm(0) -> x2 + v29 Load { addr=v3, disp=0, kind=I64 } -> x2 + v30 Store { addr=v26, disp=0, value=v29, kind=I64 } -> - + v31 Imm(8) -> x1 + v32 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x1 + v33 Load { addr=v3, disp=8, kind=I64 } -> x1 + v34 Store { addr=v3, disp=0, value=v33, kind=I64 } -> - + v35 Load { addr=v3, disp=8, kind=I64 } -> x0 + terminator GotoIndirect(v35) (exit_acc=v33) + block 7 start_pc=0 + v36 ImmData(32) -> x1 + v37 Imm(0) -> x1 + v38 Load { addr=v3, disp=0, kind=I64 } -> x1 + v39 Imm(8) -> x2 + v40 BinopI { op=add, lhs=v3, rhs_imm=8 } -> x2 + v41 Load { addr=v3, disp=8, kind=I64 } -> x2 + v42 Binop { op=ne, lhs=v38, rhs=v41 } -> x1 + terminator Bz { cond=v42, target=b9, fall=b8 } (exit_acc=v42) + block 8 start_pc=0 + v43 Imm(1) -> x0 + terminator Return(v43) (exit_acc=v43) + block 9 start_pc=0 + v44 ImmData(32) -> x1 + v45 Imm(0) -> x1 + v46 ImmData(24) -> x1 + v47 Load { addr=v46, disp=0, kind=I64 } -> x1 + v48 Store { addr=v3, disp=0, value=v47, kind=I64 } -> - + v49 Load { addr=v3, disp=0, kind=I64 } -> x0 + terminator GotoIndirect(v49) (exit_acc=v47) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=flag_table +fn ent_pc=1 n_params=2 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I32) -> x6 + v4 Imm(0) -> x0 + v5 ImmData(56) -> x0 + v6 Imm(16) -> x1 + v7 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x1 + v8 Load { addr=v5, disp=16, kind=I8 } -> x1 + terminator Bz { cond=v8, target=b2, fall=b1 } (exit_acc=v8) + block 1 start_pc=0 + v9 Imm(0) -> x2 + v10 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v9) + block 2 start_pc=0 + v11 ImmData(56) -> x1 + v12 Imm(0) -> x8 + v13 Imm(1) -> x1 + v14 Imm(0) -> x2 + terminator Jmp(b4) (exit_acc=v13) + block 3 start_pc=0 + v15 Phi { incoming=[b1:v9, b5:v30], kind=I64 } -> x2 + v16 LoadLocal { off=-1, kind=I64 } -> x1 + v17 LoadLocal { off=3, kind=I32 } -> x1 + terminator Bz { cond=v3, target=b7, fall=b6 } (exit_acc=v3) + block 4 start_pc=0 + v18 Imm(1) -> x8 + v19 Imm(0) -> x1 + terminator Jmp(b5) (exit_acc=v18) + block 5 start_pc=0 + v20 Phi { incoming=[b2:v12, b4:v18], kind=I64 } -> x8 + v21 LoadLocal { off=-2, kind=I64 } -> x1 + v22 Store { addr=v5, disp=0, value=v20, kind=I32 } -> - + v23 ImmData(56) -> x1 + v24 Imm(4) -> x1 + v25 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 + v26 Imm(0) -> x1 + v27 Store { addr=v5, disp=4, value=v26, kind=I32 } -> - + v28 Imm(8) -> x1 + v29 BinopI { op=add, lhs=v5, rhs_imm=8 } -> x1 + v30 Imm(1) -> x2 + v31 Store { addr=v5, disp=8, value=v30, kind=I32 } -> - + v32 Imm(16) -> x1 + v33 BinopI { op=add, lhs=v5, rhs_imm=16 } -> x1 + v34 Store { addr=v5, disp=16, value=v30, kind=I8 } -> - + v35 Imm(72057594037927936) -> x1 + v36 Imm(0) -> x1 + terminator Jmp(b3) (exit_acc=v30) + block 6 start_pc=0 + v37 ImmData(56) -> x1 + v38 Imm(4) -> x1 + v39 BinopI { op=add, lhs=v5, rhs_imm=4 } -> x1 + v40 Imm(7) -> x1 + v41 Store { addr=v5, disp=4, value=v40, kind=I32 } -> - + terminator Jmp(b7) (exit_acc=v41) + block 7 start_pc=0 + v42 ImmData(56) -> x1 + v43 LoadLocal { off=2, kind=I32 } -> x1 + v44 BinopI { op=shl, lhs=v1, rhs_imm=2 } -> x1 + v45 Binop { op=add, lhs=v5, rhs=v44 } -> x1 + v46 LoadIndexed { base=v5, index=v1, scale=4, kind=I32 } -> x0 + terminator Return(v46) (exit_acc=v46) +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=2 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x7 + v2 Call { target_pc=0, args=[v1], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v3 BinopI { op=ne, lhs=v2, rhs_imm=20 } -> x0 + terminator Bz { cond=v3, target=b2, fall=b1 } (exit_acc=v3) + block 1 start_pc=0 + v4 Imm(2) -> x0 + terminator Return(v4) (exit_acc=v4) + block 2 start_pc=0 + v5 Imm(1) -> x7 + v6 Call { target_pc=0, args=[v5], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + v7 BinopI { op=ne, lhs=v6, rhs_imm=10 } -> x0 + terminator Bz { cond=v7, target=b4, fall=b3 } (exit_acc=v7) + block 3 start_pc=0 + v8 Imm(3) -> x0 + terminator Return(v8) (exit_acc=v8) + block 4 start_pc=0 + v9 Imm(1) -> x7 + v10 Call { target_pc=1, args=[v9, v9], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v11 BinopI { op=ne, lhs=v10, rhs_imm=7 } -> x0 + terminator Bz { cond=v11, target=b6, fall=b5 } (exit_acc=v11) + block 5 start_pc=0 + v12 Imm(4) -> x0 + terminator Return(v12) (exit_acc=v12) + block 6 start_pc=0 + v13 Imm(1) -> x7 + v14 Imm(0) -> x6 + v15 Call { target_pc=1, args=[v13, v14], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v16 BinopI { op=ne, lhs=v15, rhs_imm=7 } -> x0 + terminator Bz { cond=v16, target=b8, fall=b7 } (exit_acc=v16) + block 7 start_pc=0 + v17 Imm(5) -> x0 + terminator Return(v17) (exit_acc=v17) + block 8 start_pc=0 + v18 Imm(0) -> x7 + v19 Call { target_pc=1, args=[v18, v18], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x0 + v20 BinopI { op=ne, lhs=v19, rhs_imm=1 } -> x0 + terminator Bz { cond=v20, target=b10, fall=b9 } (exit_acc=v20) + block 9 start_pc=0 + v21 Imm(6) -> x0 + terminator Return(v21) (exit_acc=v21) + block 10 start_pc=0 + v22 Imm(0) -> x0 + terminator Return(v22) (exit_acc=v22) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) From 9ea42e33b470a07a5e4ed6377e473d19e2291eb9 Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 21:39:05 -0700 Subject: [PATCH 08/36] c5: -O predefines NDEBUG and __OPTIMIZE__; demos build at -O A single -O now selects release semantics: the optimization passes plus NDEBUG=1 and __OPTIMIZE__=1 predefines, installed ahead of the CLI -D/-U lists so an explicit -D NDEBUG= keeps the user's value and -U NDEBUG re-enables assert. Demo builds that compiled without optimization now pass -O on every badc compile (dual-lane demos keep both lanes); the perf harnesses drop the now-redundant -DNDEBUG from their badc rows. Co-Authored-By: Claude Fable 5 --- demos/chibicc/smoke.py | 3 +- demos/gui_hello/smoke.py | 2 +- demos/nt_loader/smoke.py | 2 +- demos/python/build.py | 4 +- demos/python/compare_compilers.py | 6 +- demos/python/smoke.py | 9 +-- demos/quickjs/smoke.py | 4 +- demos/raylib/smoke.py | 8 +-- demos/tcl/smoke.py | 4 +- demos/tinycc/smoke.py | 4 +- src/c5/compiler/mod.rs | 15 ++++ src/c5/tests/jit.rs | 1 + src/c5/tests/native.rs | 1 + src/c5/tests/native_elf.rs | 1 + src/c5/tests/native_elf_x64.rs | 1 + src/c5/tests/native_pe_arm64.rs | 1 + src/c5/tests/native_pe_x64.rs | 1 + src/c5/tests/programs.rs | 8 +++ src/main.rs | 10 ++- tests/cli_fixture_smoke.rs | 58 ++++++++++++++++ tests/fixtures/c/ndebug_optimize_predefine.c | 13 ++++ .../c/ndebug_undef_reenables_assert.c | 10 +++ tests/perf/run.py | 6 +- .../asm/ndebug_optimize_predefine.aarch64.asm | 14 ++++ .../asm/ndebug_optimize_predefine.x64.asm | 16 +++++ .../ndebug_undef_reenables_assert.aarch64.asm | 14 ++++ .../asm/ndebug_undef_reenables_assert.x64.asm | 15 ++++ ...bject_macro_to_fn_macro_rescan.aarch64.asm | 62 +---------------- .../object_macro_to_fn_macro_rescan.x64.asm | 55 --------------- .../ssa/ndebug_optimize_predefine.ssa | 55 +++++++++++++++ .../ssa/ndebug_undef_reenables_assert.ssa | 55 +++++++++++++++ .../ssa/object_macro_to_fn_macro_rescan.ssa | 69 ++----------------- 32 files changed, 320 insertions(+), 207 deletions(-) create mode 100644 tests/fixtures/c/ndebug_optimize_predefine.c create mode 100644 tests/fixtures/c/ndebug_undef_reenables_assert.c create mode 100644 tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm create mode 100644 tests/snapshots/asm/ndebug_optimize_predefine.x64.asm create mode 100644 tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm create mode 100644 tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm create mode 100644 tests/snapshots/ssa/ndebug_optimize_predefine.ssa create mode 100644 tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa diff --git a/demos/chibicc/smoke.py b/demos/chibicc/smoke.py index 7349c44db..84c248aa6 100644 --- a/demos/chibicc/smoke.py +++ b/demos/chibicc/smoke.py @@ -73,6 +73,7 @@ def compile_one(badc: Path, src: Path, out: Path) -> tuple[bool, str]: proc = subprocess.run( [ str(badc), + "-O", "-I", str(CHIBICC_DIR), "-c", @@ -160,7 +161,7 @@ def main() -> int: src_files = [str(CHIBICC_DIR / name) for name in TU_STATE] out_path = work / ("chibicc.exe" if WIN else "chibicc") proc = subprocess.run( - [str(badc), "-I", str(CHIBICC_DIR), "-o", str(out_path), *src_files], + [str(badc), "-O", "-I", str(CHIBICC_DIR), "-o", str(out_path), *src_files], capture_output=True, text=True, check=False, diff --git a/demos/gui_hello/smoke.py b/demos/gui_hello/smoke.py index 8b2e071ff..09cc37f47 100755 --- a/demos/gui_hello/smoke.py +++ b/demos/gui_hello/smoke.py @@ -78,7 +78,7 @@ def main() -> int: for target, source, suffix in BUILDS: src = GUI_DIR / source out = work / f"hello-{target}{suffix}" - cmd = [str(badc), f"--target={target}", str(src), "-o", str(out)] + cmd = [str(badc), "-O", f"--target={target}", str(src), "-o", str(out)] if target.startswith("windows"): cmd.extend(["-include", "msvc_compat.h"]) proc = subprocess.run(cmd, capture_output=True, text=True) diff --git a/demos/nt_loader/smoke.py b/demos/nt_loader/smoke.py index 52f1f5bd5..dd42cf372 100644 --- a/demos/nt_loader/smoke.py +++ b/demos/nt_loader/smoke.py @@ -70,7 +70,7 @@ def pe_subsystem(path: Path) -> int: def build_pe(badc: Path, target: str, source: Path, out: Path) -> None: - cmd = [str(badc), f"--target={target}", str(source), "-o", str(out)] + cmd = [str(badc), "-O", f"--target={target}", str(source), "-o", str(out)] proc = subprocess.run(cmd, capture_output=True, text=True) if proc.returncode != 0: print( diff --git a/demos/python/build.py b/demos/python/build.py index f991d37d6..d14920646 100644 --- a/demos/python/build.py +++ b/demos/python/build.py @@ -446,7 +446,7 @@ def build(target: str, do_link: bool, log) -> Path | None: out = PY_DIR / ".cache" / f"obj-{target}" out.mkdir(parents=True, exist_ok=True) dbg = ["-g"] if os.environ.get("BADC_PY_G") else [] - opt = ["-O"] if os.environ.get("BADC_PY_O") else [] + opt = ["-O"] entries = _entries(target) jobs = [(badc, target, src, defs, incs, dbg, opt, str(out), str(SRC)) for src, defs, incs in entries] @@ -473,7 +473,7 @@ def build(target: str, do_link: bool, log) -> Path | None: # the core defines (no CPython includes needed). for helper in _WIN_HELPERS: hobj = out / (helper[:-2] + ".o") - hcmd = [badc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", *dbg, + hcmd = [badc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", *dbg, *opt, *[f"-D{d}" for d in _WIN_DEFINES], str(PY_DIR / helper), "-o", str(hobj)] r = run(hcmd, timeout=120) if r.returncode != 0: diff --git a/demos/python/compare_compilers.py b/demos/python/compare_compilers.py index 5d09a0310..60478e221 100644 --- a/demos/python/compare_compilers.py +++ b/demos/python/compare_compilers.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 """Build CPython from the same recipe with badc and the platform reference -compiler (clang on POSIX, cl on Windows), at -O and without (the -O legs -define NDEBUG, matching release-build practice), and report +compiler (clang on POSIX, cl on Windows), at -O and without (badc -O +implies NDEBUG; the clang/cl -O legs define it explicitly), and report per-binary section sizes plus a runtime microbenchmark. The recipe -- the per-TU source list, defines, and includes -- comes from @@ -72,7 +72,7 @@ def _compile_cmd(cc_kind, cc, target, src, defs, incs, obj, opt, reenable): lacks); the reference compiler has those headers, so re-enable them to give it its natural build of the same module set.""" if cc_kind == "badc": - o = ["-O", "-DNDEBUG"] if opt else [] + o = ["-O"] if opt else [] return [cc, "--gnu", "-c", f"--target={target}", "-UHAVE_GCC_UINT128_T", '-DCOMPILER="[badc]"', *o, *defs, *incs, src, "-o", obj] if cc_kind == "clang": diff --git a/demos/python/smoke.py b/demos/python/smoke.py index e09867b40..3abba19da 100644 --- a/demos/python/smoke.py +++ b/demos/python/smoke.py @@ -183,13 +183,10 @@ def compile_and_link(badc: str, trace: Path, out: Path, log) -> Path: src, flags = compiles[obj] dst = out / (obj.replace("/", "_")) dbg = ["-g"] if os.environ.get("BADC_PY_G") else [] - # BADC_PY_O builds each TU with the optimizer, for a benchmarkable - # interpreter and to exercise the optimization passes across the - # whole source. The host build trace's own -O flags are dropped by + # Each TU builds with the optimizer (badc -O also implies NDEBUG). + # The host build trace's own -O flags are dropped by # parse_commands, so this is the only optimization control. - do_opt = bool(os.environ.get("BADC_PY_O")) - if do_opt and opt_only is not None: - do_opt = os.path.basename(src) in opt_only + do_opt = opt_only is None or os.path.basename(src) in opt_only opt = ["-O"] if do_opt else [] # `--gnu` mirrors the reference clang build: __GNUC__ makes the # struct layouts (packed tracemalloc) match the clang-built diff --git a/demos/quickjs/smoke.py b/demos/quickjs/smoke.py index d29b242f8..5f5664266 100644 --- a/demos/quickjs/smoke.py +++ b/demos/quickjs/smoke.py @@ -97,7 +97,7 @@ def main() -> int: # `--export-all` puts the engine's API in the executable's dynamic # symbol table so a dlopen'd native module resolves its references to # the host (JS_NewObject, JS_ToIndex, ...) from the global scope. - cmd = [str(badc), "--export-all"] + cmd = [str(badc), "-O", "--export-all"] for d in DEFINES: cmd += ["-D", d] cmd += ["-I", str(QJS_DIR)] @@ -158,7 +158,7 @@ def main() -> int: ) module_passed = 0 for src, so, test, cwd in modules: - build = [str(badc), "--export-all", "--shared"] + build = [str(badc), "-O", "--export-all", "--shared"] for d in DEFINES: build += ["-D", d] build += ["-D", "JS_SHARED_LIBRARY", "-I", str(QJS_DIR), str(src), "-o", str(so)] diff --git a/demos/raylib/smoke.py b/demos/raylib/smoke.py index d0a1af36b..3c7ef8149 100644 --- a/demos/raylib/smoke.py +++ b/demos/raylib/smoke.py @@ -166,7 +166,7 @@ def platform_build(badc: Path, work: Path) -> bool: objs = [] for mod in modules: obj = work / f"{mod}.o" - cmd = [str(badc), "-c", *defines] + cmd = [str(badc), "-O", "-c", *defines] if mod == "rcore": cmd += rcore_extra if mod == "raudio": @@ -183,7 +183,7 @@ def platform_build(badc: Path, work: Path) -> bool: return False logic_obj = work / "loderunner_logic.o" - if run([str(badc), "-c", "-I", str(RAYLIB_DIR), + if run([str(badc), "-O", "-c", "-I", str(RAYLIB_DIR), "-o", str(logic_obj), str(RAYLIB_DIR / "loderunner_logic.c")]).returncode != 0: return False @@ -192,7 +192,7 @@ def platform_build(badc: Path, work: Path) -> bool: # `#pragma subsystem(windows)` drives the PE subsystem (a pragma in a # separately-compiled object is not visible at link). loderunner_logic.c # is still separately compiled to exercise the multi-object link. - if run([str(badc), *defines, "-I", str(inc), "-I", str(src), + if run([str(badc), "-O", *defines, "-I", str(inc), "-I", str(src), str(RAYLIB_DIR / "loderunner.c"), str(logic_obj), str(archive), "-o", str(game)]).returncode != 0: print("smoke FAIL: standalone link", file=sys.stderr) @@ -283,7 +283,7 @@ def _validate_win_imports(badc: Path, game: Path, work: Path) -> bool: lines.append("return miss?1:0;}") src.write_text("\n".join(lines) + "\n") exe = work / f"import_probe{EXE}" - if run([str(badc), str(src), "-o", str(exe)]).returncode != 0: + if run([str(badc), "-O", str(src), "-o", str(exe)]).returncode != 0: print("smoke FAIL: could not build the import probe", file=sys.stderr) return False p = run([str(exe)], capture_output=True, text=True) diff --git a/demos/tcl/smoke.py b/demos/tcl/smoke.py index 04df77777..be41dd699 100644 --- a/demos/tcl/smoke.py +++ b/demos/tcl/smoke.py @@ -114,7 +114,7 @@ def compile_units(badc: str, unix: Path, generic: Path, out: Path, log) -> list[ objs, fails = [], [] for src, obj, flags in cmds: objp = out / f"{obj}.o" - cmd = [badc, "-c", "-UHAVE_CPUID", *extra, *flags, *includes, src, "-o", str(objp)] + cmd = [badc, "-O", "-c", "-UHAVE_CPUID", *extra, *flags, *includes, src, "-o", str(objp)] r = run(cmd, timeout=180) if r.returncode != 0: msg = (r.stderr.strip().splitlines() or [f"rc{r.returncode}"])[-1] @@ -127,7 +127,7 @@ def compile_units(badc: str, unix: Path, generic: Path, out: Path, log) -> list[ zflags = ["-DHAVE_ZLIB=1", "-DBUILD_tcl", "-DSTDC", "-I" + str(zdir)] for name in ZLIB_UNITS: objp = out / f"Z{name}.o" - r = run([badc, "-c", *zflags, str(zdir / f"{name}.c"), "-o", str(objp)], timeout=180) + r = run([badc, "-O", "-c", *zflags, str(zdir / f"{name}.c"), "-o", str(objp)], timeout=180) if r.returncode != 0: fails.append((f"zlib {name}", (r.stderr.strip().splitlines() or ["rc"])[-1][:160])) else: diff --git a/demos/tinycc/smoke.py b/demos/tinycc/smoke.py index 657fec13d..0275aec52 100644 --- a/demos/tinycc/smoke.py +++ b/demos/tinycc/smoke.py @@ -252,7 +252,7 @@ def compile_one( target: str | None, ) -> tuple[bool, str]: """Run badc -c against `src`. Returns (ok, captured_stderr_head).""" - cmd = [str(badc), "-q", "-I", str(TINYCC_DIR)] + cmd = [str(badc), "-q", "-O", "-I", str(TINYCC_DIR)] if target is not None: cmd.append(f"--target={target}") for d in cpp_defs: @@ -373,7 +373,7 @@ def main() -> int: src_files = [str(TINYCC_DIR / name) for name in active] link_target_is_win = key[0] == "Windows" out_path = work / ("tcc.exe" if link_target_is_win else "tcc") - cmd = [str(badc), "-q", "-I", str(TINYCC_DIR)] + cmd = [str(badc), "-q", "-O", "-I", str(TINYCC_DIR)] if target is not None: cmd.append(f"--target={target}") for d in cpp_defs: diff --git a/src/c5/compiler/mod.rs b/src/c5/compiler/mod.rs index df0952b57..31c02e980 100644 --- a/src/c5/compiler/mod.rs +++ b/src/c5/compiler/mod.rs @@ -220,6 +220,10 @@ pub struct CompileOptions { /// for auto-included names another input defines, so the user's /// definition wins over the header's library binding. pub implicit_extern_fns: Vec, + /// `-O` -- predefine `NDEBUG` and `__OPTIMIZE__`, both `1`, so a + /// single flag selects release semantics (optimization passes plus + /// asserts compiled out). Explicit `-D` / `-U` flags override. + pub optimize: bool, } impl CompileOptions { @@ -238,6 +242,11 @@ impl CompileOptions { self.undefines = undefines; self } + /// Enable the `-O` predefines. See [`Self::optimize`]. + pub fn with_optimize(mut self, on: bool) -> Self { + self.optimize = on; + self + } /// Replace the `-I` include-search-path list. pub fn with_include_paths(mut self, include_paths: Vec) -> Self { self.include_paths = include_paths; @@ -1219,6 +1228,12 @@ impl Compiler { for name in &opts.force_includes { pp.add_force_include(name); } + // `-O` predefines, installed before the CLI lists so an explicit + // `-D NDEBUG=` overrides the value and `-U NDEBUG` removes it. + if opts.optimize { + pp.define("NDEBUG", "1"); + pp.define("__OPTIMIZE__", "1"); + } for (name, body) in &opts.defines { pp.define(name, body); } diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index 487e119ed..b35d858bc 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1199,6 +1199,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index decd95767..993a06334 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -477,6 +477,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index fee4718aa..2706cd1b1 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -405,6 +405,7 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index 15407c8aa..bcee46c11 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -358,6 +358,7 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index e003473ba..bb3fa8943 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -686,6 +686,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index eb83de562..71b304be0 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -699,6 +699,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("const_expr_conditional.c", 27), ("comma_operator_in_loops.c", 3), ("size_t_via_stdio.c", 3), + ("ndebug_optimize_predefine.c", 100), ("leading_dot_float_literal.c", 7), ("libc_fp_return_value.c", 11), ("libc_fp_classify.c", 0), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 2db15108f..7574840f7 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -2331,3 +2331,11 @@ fn darwin_enotsup_is_distinct_from_eopnotsupp() { && ENOTSUP!=EOPNOTSUPP) ? 0 : 1; }"; assert_eq!(super::run_str(src), 0); } + +#[test] +fn ndebug_optimize_predefine() { + // The library harness never sets the driver's `-O`, so neither + // NDEBUG nor __OPTIMIZE__ is predefined here; the CLI-level + // `-O` semantics are locked by `tests/cli_fixture_smoke.rs`. + assert_eq!(run_fixture("ndebug_optimize_predefine.c"), 100); +} diff --git a/src/main.rs b/src/main.rs index 1dced89cd..3cc507f8a 100644 --- a/src/main.rs +++ b/src/main.rs @@ -57,7 +57,9 @@ Multi-TU knobs: Compile knobs: -O, --optimize Run the SSA optimization passes (mem2reg, inlining, rotate and branch const-fold, - immediate dedup). Off by default. The + immediate dedup) and predefine `NDEBUG=1` + and `__OPTIMIZE__=1` (override with `-D` / + `-U`). Off by default. The `-O1`/`-O2`/`-O3`/`-Os`/`-Oz`/`-Ofast`/`-Og` forms all select this single level; `-O0` disables it. @@ -745,6 +747,7 @@ fn run() { }; let copts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(defines.clone()) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -829,6 +832,7 @@ fn run() { }; let opts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(defines.clone()) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -922,6 +926,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_export_all_functions(export_all) .with_implicit_extern_fns(implicit_externs.to_vec()) .with_no_entry_point(true); @@ -967,6 +972,7 @@ fn run() { } let copts = badc::CompileOptions::default() .with_gnu(gnu) + .with_optimize(optimize_flag) .with_defines(copts_defines) .with_undefines(undefines.clone()) .with_include_paths(include_paths.clone()) @@ -1458,6 +1464,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_no_entry_point(true); let mut compiler = Compiler::with_options(src_bytes, target, copts); if show_includes { @@ -1563,6 +1570,7 @@ fn run() { .with_source_label(src_path.to_string()) .with_show_includes(show_includes) .with_warn_dead_store(warn_dead_store) + .with_optimize(optimize_flag) .with_no_entry_point(true); let mut compiler = Compiler::with_options(src_bytes, target, copts); if show_includes { diff --git a/tests/cli_fixture_smoke.rs b/tests/cli_fixture_smoke.rs index 345404de6..b25bac009 100644 --- a/tests/cli_fixture_smoke.rs +++ b/tests/cli_fixture_smoke.rs @@ -219,6 +219,64 @@ fn opt_level_flags_map_to_the_single_level() { assert_eq!(os, o, "-Os should match -O"); } +// `-O` predefines `NDEBUG=1` and `__OPTIMIZE__=1` (release semantics). +// The predefines land before the CLI `-D` / `-U` lists, so an explicit +// `-D NDEBUG=` keeps the user's value and `-U NDEBUG` removes the +// implied one, re-enabling `assert`. +#[cfg(any(target_os = "linux", target_os = "macos"))] +#[test] +fn optimize_flag_predefines_ndebug() { + let badc = env!("CARGO_BIN_EXE_badc"); + let manifest = env!("CARGO_MANIFEST_DIR"); + let fixtures = PathBuf::from(manifest) + .join("tests") + .join("fixtures") + .join("c"); + let dir = std::env::temp_dir().join(format!("badc-ndebug-{}", std::process::id())); + let _ = std::fs::remove_dir_all(&dir); + std::fs::create_dir_all(&dir).expect("create temp dir"); + + let run = |tag: &str, flags: &[&str], src: &std::path::Path| -> std::process::ExitStatus { + let exe = dir.join(tag); + let mut cmd = Command::new(badc); + for f in flags { + cmd.arg(f); + } + let out = cmd.arg(src).arg("-o").arg(&exe).output().expect("run badc"); + assert!( + out.status.success(), + "compile {tag} failed: {}", + String::from_utf8_lossy(&out.stderr) + ); + Command::new(&exe).output().expect("run prog").status + }; + + // Exit codes: both predefines -> NDEBUG's value, exactly one -> 101, + // neither -> 100 (see the fixture). + let probe = fixtures.join("ndebug_optimize_predefine.c"); + assert_eq!(run("plain", &[], &probe).code(), Some(100)); + assert_eq!(run("opt", &["-O"], &probe).code(), Some(1)); + assert_eq!( + run("opt-dval", &["-O", "-DNDEBUG=7"], &probe).code(), + Some(7) + ); + assert_eq!( + run("opt-undef", &["-O", "-UNDEBUG"], &probe).code(), + Some(101) + ); + + // Under `-O` the assert(0) is compiled out; `-U NDEBUG` re-enables + // it and the program traps instead of exiting 0. + let trap = fixtures.join("ndebug_undef_reenables_assert.c"); + assert_eq!(run("assert-off", &["-O"], &trap).code(), Some(0)); + let fired = run("assert-on", &["-O", "-UNDEBUG"], &trap); + assert!( + !fired.success(), + "-U NDEBUG under -O must re-enable assert (got {fired:?})" + ); + let _ = std::fs::remove_dir_all(&dir); +} + // `--install ` writes every embedded header under /include // (recreating subdirectories) and the runtime source under /lib. #[test] diff --git a/tests/fixtures/c/ndebug_optimize_predefine.c b/tests/fixtures/c/ndebug_optimize_predefine.c new file mode 100644 index 000000000..c1f2b9918 --- /dev/null +++ b/tests/fixtures/c/ndebug_optimize_predefine.c @@ -0,0 +1,13 @@ +// `-O` predefines `NDEBUG` and `__OPTIMIZE__` (both 1, following the +// gcc/clang convention for the latter); explicit `-D` / `-U` flags +// override the implied values. The exit code reports what the +// preprocessor saw: both defined -> the NDEBUG value, exactly one +// defined -> 101, neither -> 100. + +#if defined(NDEBUG) && defined(__OPTIMIZE__) +int main(void) { return NDEBUG; } +#elif defined(NDEBUG) || defined(__OPTIMIZE__) +int main(void) { return 101; } +#else +int main(void) { return 100; } +#endif diff --git a/tests/fixtures/c/ndebug_undef_reenables_assert.c b/tests/fixtures/c/ndebug_undef_reenables_assert.c new file mode 100644 index 000000000..3e3b5e158 --- /dev/null +++ b/tests/fixtures/c/ndebug_undef_reenables_assert.c @@ -0,0 +1,10 @@ +// With `-O` the implied `NDEBUG` compiles the assert out and the +// program exits 0; `-U NDEBUG` on top of `-O` removes the predefine, +// so the false assertion fires and the program traps. + +#include + +int main(void) { + assert(0); + return 0; +} diff --git a/tests/perf/run.py b/tests/perf/run.py index 145f8ad22..ba48e4f07 100755 --- a/tests/perf/run.py +++ b/tests/perf/run.py @@ -20,8 +20,8 @@ * cl /Od -- MSVC cl.exe on Windows. * cl /O2 -- MSVC cl.exe on Windows. -The optimized entries (badc -O, clang -O2, cl /O2) define NDEBUG, matching -release-build practice; the unoptimized entries keep asserts live. +badc -O implies NDEBUG; the clang -O2 and cl /O2 rows pass -DNDEBUG +explicitly to match. The unoptimized entries keep asserts live. Override the badc binary via $BADC; override the tcc binary via $TCC. """ @@ -158,7 +158,7 @@ def probe_compilers() -> list[Compiler]: badc = REPO_ROOT / "target" / "release" / f"badc{EXE}" if badc.is_file(): found.append(Compiler("badc", [str(badc)])) - found.append(Compiler("badc -O", [str(badc), "-O", "-DNDEBUG"])) + found.append(Compiler("badc -O", [str(badc), "-O"])) else: print(f"info: badc not at {badc}; skipping badc rows", file=sys.stderr) diff --git a/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm b/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm new file mode 100644 index 000000000..c50a33f1b --- /dev/null +++ b/tests/snapshots/asm/ndebug_optimize_predefine.aarch64.asm @@ -0,0 +1,14 @@ + +ndebug_optimize_predefine.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x220 // =544 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x1 // =1 + ret diff --git a/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm b/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm new file mode 100644 index 000000000..0869f692c --- /dev/null +++ b/tests/snapshots/asm/ndebug_optimize_predefine.x64.asm @@ -0,0 +1,16 @@ + +ndebug_optimize_predefine.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + movl $0x1, %eax + retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm b/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm new file mode 100644 index 000000000..d237ce617 --- /dev/null +++ b/tests/snapshots/asm/ndebug_undef_reenables_assert.aarch64.asm @@ -0,0 +1,14 @@ + +ndebug_undef_reenables_assert.aarch64: file format elf64-littleaarch64 + +Disassembly of section .text: + +<.text>: + mov x29, #0x0 // =0 + mov x0, sp + mov x1, #0x230 // =560 + movk x1, #0x0, lsl #16 + b + brk #: + mov x0, #0x0 // =0 + ret diff --git a/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm b/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm new file mode 100644 index 000000000..b14dd7ff9 --- /dev/null +++ b/tests/snapshots/asm/ndebug_undef_reenables_assert.x64.asm @@ -0,0 +1,15 @@ + +ndebug_undef_reenables_assert.x64: file format elf64-x86-64 + +Disassembly of section .text: + +<.text>: + xorl %ebp, %ebp + movq %rsp, %rdi + movl $, %esi + callq + ud2 + +
: + xorq %rax, %rax + retq diff --git a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm index 4f73df7fa..673b2ab06 100644 --- a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm +++ b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.aarch64.asm @@ -6,69 +6,9 @@ Disassembly of section .text: <.text>: mov x29, #0x0 // =0 mov x0, sp - mov x1, #0x2b0 // =688 + mov x1, #0x230 // =560 movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 - str x20, [sp] - str x19, [sp, #0x10] - sxtw x2, w2 - adrp x3, - add x3, x3, - mov x16, x3 - mov x3, x2 - mov x2, x1 - mov x1, x0 - mov x0, x16 - bl - sxtw x0, w0 - mov x20, #0x0 // =0 - mov x0, x20 - bl - sxtw x0, w0 - brk #0 - mov x0, x20 - ldr x20, [sp] - ldr x19, [sp, #0x10] - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 - ret - -
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 - str x20, [sp] - mov x20, #0x7 // =7 - cmp x20, #0x7 - b.ne - mov x1, #0x0 // =0 - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - mov x2, #0x13 // =19 - bl - mov x1, x0 - add x0, x20, #0x1 - sxtw x0, w0 - cmp x0, #0x8 - b.ne - mov x1, #0x0 // =0 - b - adrp x0, - add x0, x0, - adrp x1, - add x1, x1, - mov x2, #0x14 // =20 - bl - mov x1, x0 mov x0, #0x0 // =0 - ldr x20, [sp] - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm index e6496832e..3362c8253 100644 --- a/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm +++ b/tests/snapshots/asm/object_macro_to_fn_macro_rescan.x64.asm @@ -10,61 +10,6 @@ Disassembly of section .text: callq ud2 -<__c5_assert_fail>: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp - movq %rbx, (%rsp) - movslq %edx, %rdx - leaq , %rax - movq %rdx, %rcx - movq %rsi, %rdx - movq %rdi, %rsi - movq %rax, %rdi - movb $0x0, %al - callq - movslq %eax, %rax - xorq %rbx, %rbx - movq %rbx, %rdi - xorl %eax, %eax - callq - movslq %eax, %rax - ud2 - movq %rbx, %rax - movq (%rsp), %rbx - addq $0x10, %rsp - popq %rbp - retq -
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp - movq %rbx, (%rsp) - movl $0x7, %ebx - cmpq $0x7, %rbx - jne - xorq %rcx, %rcx - jmp - leaq , %rdi - leaq , %rsi - movl $0x13, %edx - callq - movq %rax, %rcx - leaq 0x1(%rbx), %rax - movslq %eax, %rax - cmpq $0x8, %rax - jne - xorq %rcx, %rcx - jmp - leaq , %rdi - leaq , %rsi - movl $0x14, %edx - callq - movq %rax, %rcx xorq %rax, %rax - movq (%rsp), %rbx - addq $0x40, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/ssa/ndebug_optimize_predefine.ssa b/tests/snapshots/ssa/ndebug_optimize_predefine.ssa new file mode 100644 index 000000000..b2afb98cf --- /dev/null +++ b/tests/snapshots/ssa/ndebug_optimize_predefine.ssa @@ -0,0 +1,55 @@ +; --- SSA dump (ok=true) ent_pc=0 --- +; name=main +fn ent_pc=0 n_params=0 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(1) -> x0 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa b/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa new file mode 100644 index 000000000..a198b25d4 --- /dev/null +++ b/tests/snapshots/ssa/ndebug_undef_reenables_assert.ssa @@ -0,0 +1,55 @@ +; --- SSA dump (ok=true) ent_pc=2 --- +; name=main +fn ent_pc=2 n_params=0 variadic=false locals=0 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 Imm(0) -> x0 + terminator Return(v1) (exit_acc=v1) +; --- SSA dump (ok=true) ent_pc=0 --- +; name=__c5_exit +fn ent_pc=0 n_params=1 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I32) -> x7 + v2 Imm(0) -> x0 + v3 LoadLocal { off=2, kind=I32 } -> x0 + v4 CallExt { binding_idx=0, args=[v1], fp_arg_mask=0x0 } -> x0 + v5 Imm(0) -> x0 + terminator Return(v5) (exit_acc=v5) +; --- SSA dump (ok=true) ent_pc=1 --- +; name=__c5_entry +fn ent_pc=1 n_params=2 variadic=false locals=6 + spill_count=0 gpr_used=[3] fp_used=[] + block 0 start_pc=0 + v0 AllocaInit(0) -> - + v1 ParamRef(0, kind=I64) -> x7 + v2 Imm(0) -> x0 + v3 ParamRef(1, kind=I64) -> x6 + v4 Imm(0) -> x0 + v5 LoadLocal { off=3, kind=I64 } -> x0 + v6 BinopI { op=and, lhs=v3, rhs_imm=255 } -> x0 + v7 LoadLocal { off=2, kind=I64 } -> x0 + v8 Imm(0) -> x0 + v9 LoadLocal { off=-1, kind=I64 } -> x0 + v10 Imm(0) -> x3 + v11 Load { addr=v1, disp=0, kind=I64 } -> x0 + v12 BinopI { op=shl, lhs=v11, rhs_imm=32 } -> x1 + v13 Extend { value=v11, kind=I32 } -> x0 + v14 Imm(0) -> x1 + v15 Imm(8) -> x1 + v16 BinopI { op=add, lhs=v1, rhs_imm=8 } -> x6 + v17 Imm(0) -> x1 + v18 ImmData(24) -> x1 + v19 LoadLocal { off=-3, kind=I64 } -> x2 + v20 LoadLocal { off=-2, kind=I32 } -> x2 + v21 BinopI { op=shl, lhs=v13, rhs_imm=3 } -> x2 + v22 Binop { op=add, lhs=v16, rhs=v21 } -> x2 + v23 BinopI { op=add, lhs=v22, rhs_imm=8 } -> x2 + v24 Store { addr=v18, disp=0, value=v23, kind=I64 } -> - + v25 LoadLocal { off=-2, kind=I32 } -> x1 + v26 LoadLocal { off=-3, kind=I64 } -> x1 + v27 Call { target_pc=3, args=[v13, v16], fixed_args=2, fp_return=false, fp_arg_mask=0x0 } -> x7 + v28 Call { target_pc=0, args=[v27], fixed_args=1, fp_return=false, fp_arg_mask=0x0 } -> x0 + terminator Return(v10) (exit_acc=v10) diff --git a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa index cd0d1043c..9aa088703 100644 --- a/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa +++ b/tests/snapshots/ssa/object_macro_to_fn_macro_rescan.ssa @@ -1,71 +1,14 @@ -; --- SSA dump (ok=true) ent_pc=1 --- -; name=__c5_assert_fail -fn ent_pc=1 n_params=3 variadic=false locals=4 - spill_count=0 gpr_used=[3] fp_used=[] - block 0 start_pc=0 - v0 AllocaInit(0) -> - - v1 ParamRef(0, kind=I64) -> x7 - v2 Imm(0) -> x0 - v3 ParamRef(1, kind=I64) -> x6 - v4 Imm(0) -> x0 - v5 ParamRef(2, kind=I32) -> x2 - v6 Imm(0) -> x0 - v7 ImmData(36) -> x0 - v8 LoadLocal { off=2, kind=I64 } -> x1 - v9 LoadLocal { off=3, kind=I64 } -> x1 - v10 LoadLocal { off=4, kind=I32 } -> x1 - v11 CallExt { binding_idx=0, args=[v7, v1, v3, v5], fp_arg_mask=0x0 } -> x0 - v12 Imm(0) -> x3 - v13 CallExt { binding_idx=37, args=[v12], fp_arg_mask=0x0 } -> x0 - v14 Intrinsic { kind=10, args=[] } -> x0 - terminator Return(v12) (exit_acc=v12) +object_macro_to_fn_macro_rescan.c:18: warning: unused variable `x` ; --- SSA dump (ok=true) ent_pc=2 --- ; name=main -fn ent_pc=2 n_params=0 variadic=false locals=6 - spill_count=0 gpr_used=[3] fp_used=[] +fn ent_pc=2 n_params=0 variadic=false locals=1 + spill_count=0 gpr_used=[] fp_used=[] block 0 start_pc=0 v0 AllocaInit(0) -> - - v1 Imm(7) -> x3 + v1 Imm(7) -> x0 v2 Imm(0) -> x0 - v3 LoadLocal { off=-1, kind=I32 } -> x0 - v4 BinopI { op=eq, lhs=v1, rhs_imm=7 } -> x0 - terminator Bz { cond=v4, target=b2, fall=b1 } (exit_acc=v4) - block 1 start_pc=0 - v5 Imm(0) -> x1 - v6 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v5) - block 2 start_pc=0 - v7 ImmData(76) -> x7 - v8 ImmData(83) -> x6 - v9 Imm(19) -> x2 - v10 Call { target_pc=1, args=[v7, v8, v9], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x1 - v11 Imm(0) -> x0 - terminator Jmp(b3) (exit_acc=v10) - block 3 start_pc=0 - v12 Phi { incoming=[b1:v5, b2:v10], kind=I64 } -> x1 - v13 LoadLocal { off=-5, kind=I64 } -> x0 - v14 LoadLocal { off=-1, kind=I32 } -> x0 - v15 BinopI { op=add, lhs=v1, rhs_imm=1 } -> x0 - v16 BinopI { op=shl, lhs=v15, rhs_imm=32 } -> x1 - v17 Extend { value=v15, kind=I32 } -> x0 - v18 BinopI { op=eq, lhs=v17, rhs_imm=8 } -> x0 - terminator Bz { cond=v18, target=b5, fall=b4 } (exit_acc=v18) - block 4 start_pc=0 - v19 Imm(0) -> x1 - v20 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v19) - block 5 start_pc=0 - v21 ImmData(162) -> x7 - v22 ImmData(173) -> x6 - v23 Imm(20) -> x2 - v24 Call { target_pc=1, args=[v21, v22, v23], fixed_args=3, fp_return=false, fp_arg_mask=0x0 } -> x1 - v25 Imm(0) -> x0 - terminator Jmp(b6) (exit_acc=v24) - block 6 start_pc=0 - v26 Phi { incoming=[b4:v19, b5:v24], kind=I64 } -> x1 - v27 LoadLocal { off=-6, kind=I64 } -> x0 - v28 Imm(0) -> x0 - terminator Return(v28) (exit_acc=v28) + v3 Imm(0) -> x0 + terminator Return(v3) (exit_acc=v3) ; --- SSA dump (ok=true) ent_pc=0 --- ; name=__c5_exit fn ent_pc=0 n_params=1 variadic=false locals=1 From 1590377f7d666312af5ef4fc9cf82849009094fe Mon Sep 17 00:00:00 2001 From: kromych Date: Sun, 5 Jul 2026 21:43:39 -0700 Subject: [PATCH 09/36] codegen: ignore dead-pure slot loads when sizing the locals region compute_frame_base counted every LoadLocal / StoreLocal / LocalAddr as a local access, so a promotion-orphaned LoadLocal with no consumers -- which the per-inst emit dispatch skips via is_dead_pure and which produces no machine code -- still forced frame_bytes != 0 and a full prologue on an otherwise frameless leaf. Gate the scan with the same is_dead_pure predicate the emit uses, so the frame decision and the emit skip cannot diverge. The rewritten scan also counts locals-region references that reach the emit outside the slot-access instructions: AllocaInit's arena bookkeeping slot, a call's aggregate-return result temp (ret_slot_local), and the by-value aggregate parameter scatter into a body local (param_aggs / param_local_slots), alongside the existing indirect_result_slot case. Volatile slot accesses are not pure and keep the frame. Snapshot drift: 512 asm files, 616 functions; every change is a frame loss (424) or a frame allocation shrink (192), no function gains code. Fixes #352 Co-Authored-By: Claude Fable 5 --- src/c5/codegen/ssa/emit_common.rs | 49 ++++-- src/c5/tests/jit.rs | 1 + src/c5/tests/native.rs | 1 + src/c5/tests/native_elf.rs | 1 + src/c5/tests/native_elf_x64.rs | 1 + src/c5/tests/native_pe_arm64.rs | 1 + src/c5/tests/native_pe_x64.rs | 1 + src/c5/tests/programs.rs | 8 + .../fixtures/c/dead_local_load_frame_elide.c | 29 ++++ .../asm/aapcs64_variadic_host_abi.aarch64.asm | 4 +- .../asm/aapcs64_variadic_host_abi.x64.asm | 4 +- .../asm/addr_of_libc_strcmp.aarch64.asm | 12 +- .../snapshots/asm/addr_of_libc_strcmp.x64.asm | 12 +- .../asm/adjacent_strings.aarch64.asm | 5 - tests/snapshots/asm/adjacent_strings.x64.asm | 7 +- .../snapshots/asm/anon_union_init.aarch64.asm | 13 -- tests/snapshots/asm/anon_union_init.x64.asm | 14 -- .../asm/array_2d_struct_init.aarch64.asm | 11 -- .../asm/array_2d_struct_init.x64.asm | 12 -- ...y_compound_literal_static_init.aarch64.asm | 27 ---- ...array_compound_literal_static_init.x64.asm | 28 ---- .../array_of_struct_brace_elision.aarch64.asm | 11 -- .../asm/array_of_struct_brace_elision.x64.asm | 12 -- .../asm/array_range_designator.aarch64.asm | 17 -- .../asm/array_range_designator.x64.asm | 18 +-- .../assign_expr_value_narrowed.aarch64.asm | 13 -- .../asm/assign_expr_value_narrowed.x64.asm | 15 +- ...atomic_operand_in_working_regs.aarch64.asm | 2 - .../atomic_operand_in_working_regs.x64.asm | 4 +- .../auto_include_undeclared_libc.aarch64.asm | 4 +- .../asm/auto_include_undeclared_libc.x64.asm | 3 +- .../asm/binary_integer_literal.aarch64.asm | 17 -- .../asm/binary_integer_literal.x64.asm | 18 --- .../asm/binary_search_tree.aarch64.asm | 10 +- .../snapshots/asm/binary_search_tree.x64.asm | 10 +- .../asm/binop_imm_chain_fold.aarch64.asm | 4 +- .../asm/binop_imm_chain_fold.x64.asm | 4 +- .../asm/bitop_common_type.aarch64.asm | 19 --- tests/snapshots/asm/bitop_common_type.x64.asm | 21 +-- .../bitop_common_type_sign_extend.aarch64.asm | 5 - .../asm/bitop_common_type_sign_extend.x64.asm | 6 - .../block_extern_shadows_local.aarch64.asm | 22 --- .../asm/block_extern_shadows_local.x64.asm | 23 --- .../asm/block_scope_extern.aarch64.asm | 13 -- .../snapshots/asm/block_scope_extern.x64.asm | 14 -- ...block_scope_extern_forward_ref.aarch64.asm | 5 - .../block_scope_extern_forward_ref.x64.asm | 6 - ...ock_scope_function_declaration.aarch64.asm | 21 +-- .../block_scope_function_declaration.x64.asm | 23 ++- ...brace_elided_struct_array_init.aarch64.asm | 17 -- .../brace_elided_struct_array_init.x64.asm | 19 +-- tests/snapshots/asm/bst_free.aarch64.asm | 4 +- tests/snapshots/asm/bst_free.x64.asm | 4 +- tests/snapshots/asm/c4.aarch64.asm | 50 +++--- tests/snapshots/asm/c4.x64.asm | 50 +++--- .../asm/c99_arith_common_width.aarch64.asm | 6 +- .../asm/c99_arith_common_width.x64.asm | 6 +- .../snapshots/asm/c99_qualifiers.aarch64.asm | 5 - tests/snapshots/asm/c99_qualifiers.x64.asm | 6 - ...l_arg_int_to_double_conversion.aarch64.asm | 18 +-- .../call_arg_int_to_double_conversion.x64.asm | 18 +-- .../call_sp_adjust_imm12_overflow.aarch64.asm | 17 +- .../asm/call_sp_adjust_imm12_overflow.x64.asm | 14 +- .../asm/case_label_declaration.aarch64.asm | 5 - .../asm/case_label_declaration.x64.asm | 6 - .../asm/cast_fn_ptr_call.aarch64.asm | 10 +- tests/snapshots/asm/cast_fn_ptr_call.x64.asm | 10 +- .../asm/cast_to_struct_pointer.aarch64.asm | 4 +- .../asm/cast_to_struct_pointer.x64.asm | 3 - .../asm/char_limits_consistency.aarch64.asm | 13 -- .../asm/char_limits_consistency.x64.asm | 15 +- tests/snapshots/asm/code_as_data.aarch64.asm | 5 - tests/snapshots/asm/code_as_data.x64.asm | 9 +- .../asm/commutative_imm_lhs_swap.aarch64.asm | 23 --- .../asm/commutative_imm_lhs_swap.x64.asm | 25 +-- .../asm/comparison_imm_lhs_swap.aarch64.asm | 8 +- .../asm/comparison_imm_lhs_swap.x64.asm | 8 +- .../asm/complement_preserves_type.aarch64.asm | 17 -- .../asm/complement_preserves_type.x64.asm | 19 +-- .../compound_assign_unsigned_div.aarch64.asm | 17 -- .../asm/compound_assign_unsigned_div.x64.asm | 18 --- .../asm/compound_literal_block.aarch64.asm | 10 -- .../asm/compound_literal_block.x64.asm | 11 -- .../compound_literal_file_scope.aarch64.asm | 17 -- .../asm/compound_literal_file_scope.x64.asm | 18 --- ...const_addr_multidim_array_elem.aarch64.asm | 15 -- .../const_addr_multidim_array_elem.x64.asm | 17 +- .../asm/const_expr_cast_narrowing.aarch64.asm | 11 -- .../asm/const_expr_cast_narrowing.x64.asm | 13 +- .../asm/const_expr_unsigned_fold.aarch64.asm | 21 --- .../asm/const_expr_unsigned_fold.x64.asm | 23 +-- .../asm/const_float_div_zero.aarch64.asm | 13 -- .../asm/const_float_div_zero.x64.asm | 15 +- .../asm/data_reloc_one_past_end.aarch64.asm | 5 - .../asm/data_reloc_one_past_end.x64.asm | 6 - .../dead_local_load_frame_elide.aarch64.asm | 79 ++++++++++ .../asm/dead_local_load_frame_elide.x64.asm | 77 +++++++++ ...deferred_outer_2d_array_stride.aarch64.asm | 29 ---- .../deferred_outer_2d_array_stride.x64.asm | 30 ---- ...tor_override_and_braced_string.aarch64.asm | 5 - ...ignator_override_and_braced_string.x64.asm | 7 +- .../snapshots/asm/dirent_readdir.aarch64.asm | 6 +- tests/snapshots/asm/dirent_readdir.x64.asm | 6 +- .../asm/divmod_preserves_rdx.aarch64.asm | 4 +- .../asm/divmod_preserves_rdx.x64.asm | 4 +- tests/snapshots/asm/dlopen_atoi.aarch64.asm | 8 +- tests/snapshots/asm/dlopen_atoi.x64.asm | 8 +- tests/snapshots/asm/dlopen_strlen.aarch64.asm | 4 +- tests/snapshots/asm/dlopen_strlen.x64.asm | 3 +- tests/snapshots/asm/do_while.aarch64.asm | 5 - tests/snapshots/asm/do_while.x64.asm | 7 +- .../asm/do_while_zero_returns.aarch64.asm | 9 -- .../asm/do_while_zero_returns.x64.asm | 10 -- tests/snapshots/asm/double_free.aarch64.asm | 4 +- tests/snapshots/asm/double_free.x64.asm | 4 +- ...mpty_macro_arg_and_string_rows.aarch64.asm | 13 -- .../empty_macro_arg_and_string_rows.x64.asm | 14 -- .../snapshots/asm/enum_tag_types.aarch64.asm | 27 ---- tests/snapshots/asm/enum_tag_types.x64.asm | 28 ---- .../asm/environ_single_tu.aarch64.asm | 4 +- tests/snapshots/asm/environ_single_tu.x64.asm | 3 +- ...n_incomplete_struct_completion.aarch64.asm | 13 -- ...xtern_incomplete_struct_completion.x64.asm | 14 -- tests/snapshots/asm/fib.aarch64.asm | 3 - tests/snapshots/asm/fib.x64.asm | 4 +- tests/snapshots/asm/file_io.aarch64.asm | 6 +- tests/snapshots/asm/file_io.x64.asm | 6 +- .../float_arg_single_precision.aarch64.asm | 23 --- .../asm/float_arg_single_precision.x64.asm | 24 +-- .../float_arith_in_static_init.aarch64.asm | 15 -- .../asm/float_arith_in_static_init.x64.asm | 17 +- .../asm/float_global_init.aarch64.asm | 5 - tests/snapshots/asm/float_global_init.x64.asm | 6 - .../asm/float_is_four_bytes.aarch64.asm | 10 -- .../snapshots/asm/float_is_four_bytes.x64.asm | 11 -- ...literal_arith_single_precision.aarch64.asm | 10 -- ...oat_literal_arith_single_precision.x64.asm | 11 -- .../asm/float_pointer_basics.aarch64.asm | 16 +- .../asm/float_pointer_basics.x64.asm | 16 +- .../asm/float_register_resident.aarch64.asm | 5 - .../asm/float_register_resident.x64.asm | 7 +- .../asm/float_ternary_promote.aarch64.asm | 5 - .../asm/float_ternary_promote.x64.asm | 7 +- .../asm/float_variadic_promotion.aarch64.asm | 5 - .../asm/float_variadic_promotion.x64.asm | 6 - .../snapshots/asm/fma_contraction.aarch64.asm | 15 -- tests/snapshots/asm/fma_contraction.x64.asm | 16 +- .../asm/fma_numeric_kernels.aarch64.asm | 15 -- .../snapshots/asm/fma_numeric_kernels.x64.asm | 17 +- ...fn_arg_decay_then_deref_assign.aarch64.asm | 2 - .../fn_arg_decay_then_deref_assign.x64.asm | 3 +- .../asm/fn_ptr_float_arg.aarch64.asm | 31 +--- tests/snapshots/asm/fn_ptr_float_arg.x64.asm | 30 +--- .../asm/fn_ptr_float_arg_narrow.aarch64.asm | 15 -- .../asm/fn_ptr_float_arg_narrow.x64.asm | 16 +- .../asm/fn_ptr_float_return.aarch64.asm | 14 +- .../snapshots/asm/fn_ptr_float_return.x64.asm | 14 +- .../asm/fn_ptr_return_type.aarch64.asm | 12 +- .../snapshots/asm/fn_ptr_return_type.x64.asm | 12 +- .../asm/fn_ptr_struct_return.aarch64.asm | 16 +- .../asm/fn_ptr_struct_return.x64.asm | 16 +- .../fn_ptr_ternary_call_return.aarch64.asm | 8 +- .../asm/fn_ptr_ternary_call_return.x64.asm | 8 +- .../asm/fn_returning_fn_ptr.aarch64.asm | 17 +- .../snapshots/asm/fn_returning_fn_ptr.x64.asm | 13 +- .../fnptr_typedef_return_proto.aarch64.asm | 4 +- .../asm/fnptr_typedef_return_proto.x64.asm | 3 +- .../asm/for_init_declaration.aarch64.asm | 10 -- .../asm/for_init_declaration.x64.asm | 11 -- .../for_init_multiple_declarators.aarch64.asm | 13 -- .../asm/for_init_multiple_declarators.x64.asm | 15 +- .../asm/forge_code_pointer.aarch64.asm | 4 +- .../snapshots/asm/forge_code_pointer.x64.asm | 3 - .../snapshots/asm/fp_const_return.aarch64.asm | 7 - tests/snapshots/asm/fp_const_return.x64.asm | 8 - .../fp_param_after_int_overflow.aarch64.asm | 4 - .../asm/fp_param_after_int_overflow.x64.asm | 8 +- .../fp_param_float_before_double.aarch64.asm | 20 --- .../asm/fp_param_float_before_double.x64.asm | 20 --- .../asm/fp_param_ternary.aarch64.asm | 10 -- tests/snapshots/asm/fp_param_ternary.x64.asm | 11 +- .../snapshots/asm/fp_return_value.aarch64.asm | 11 -- tests/snapshots/asm/fp_return_value.x64.asm | 13 +- .../snapshots/asm/func_name_array.aarch64.asm | 9 -- tests/snapshots/asm/func_name_array.x64.asm | 11 +- .../asm/func_name_in_initializer.aarch64.asm | 5 - .../asm/func_name_in_initializer.x64.asm | 7 +- .../snapshots/asm/function_macro.aarch64.asm | 19 +-- tests/snapshots/asm/function_macro.x64.asm | 20 +-- .../asm/function_pointers.aarch64.asm | 4 +- tests/snapshots/asm/function_pointers.x64.asm | 4 +- ...ction_type_typedef_declaration.aarch64.asm | 14 +- .../function_type_typedef_declaration.x64.asm | 8 +- tests/snapshots/asm/getenv_value.aarch64.asm | 6 +- tests/snapshots/asm/getenv_value.x64.asm | 5 - ...lobal_init_midexpr_cast_narrow.aarch64.asm | 18 +-- .../global_init_midexpr_cast_narrow.x64.asm | 18 +-- .../asm/gnu_extension_keyword.aarch64.asm | 10 +- .../asm/gnu_extension_keyword.x64.asm | 7 +- .../hex_constant_unsigned_type.aarch64.asm | 11 -- .../asm/hex_constant_unsigned_type.x64.asm | 12 -- .../asm/include_macro_operand.aarch64.asm | 10 +- .../asm/include_macro_operand.x64.asm | 10 +- .../asm/indexed_load_store.aarch64.asm | 5 - .../snapshots/asm/indexed_load_store.x64.asm | 4 +- .../asm/indexed_swap_shared_addr.aarch64.asm | 5 - .../asm/indexed_swap_shared_addr.x64.asm | 6 - ..._call_target_scratch_exhausted.aarch64.asm | 8 +- ...rect_call_target_scratch_exhausted.x64.asm | 8 +- .../asm/init_float_to_int.aarch64.asm | 13 -- tests/snapshots/asm/init_float_to_int.x64.asm | 15 +- .../asm/inline_arg_count_mismatch.aarch64.asm | 4 +- .../asm/inline_arg_count_mismatch.x64.asm | 4 +- .../asm/inline_forward_ref_value.aarch64.asm | 8 +- .../asm/inline_forward_ref_value.x64.asm | 8 +- .../asm/inline_keyword_uncaps.aarch64.asm | 10 -- .../asm/inline_keyword_uncaps.x64.asm | 11 -- .../snapshots/asm/inline_linkage.aarch64.asm | 5 - tests/snapshots/asm/inline_linkage.x64.asm | 7 +- ...ine_multi_block_result_forward.aarch64.asm | 5 - .../inline_multi_block_result_forward.x64.asm | 7 +- .../asm/inline_one_word_struct.aarch64.asm | 5 - .../asm/inline_one_word_struct.x64.asm | 6 - .../inline_one_word_struct_return.aarch64.asm | 5 - .../asm/inline_one_word_struct_return.x64.asm | 7 +- ...inline_phi_narrow_param_return.aarch64.asm | 7 - .../inline_phi_narrow_param_return.x64.asm | 9 +- .../asm/int32_sign_extend_elision.aarch64.asm | 15 -- .../asm/int32_sign_extend_elision.x64.asm | 17 -- .../int_literal_boundary_types.aarch64.asm | 21 --- .../asm/int_literal_boundary_types.x64.asm | 23 +-- .../asm/integer_boundary_c99.aarch64.asm | 6 +- .../asm/integer_boundary_c99.x64.asm | 6 +- .../asm/integer_literal_suffix.aarch64.asm | 17 -- .../asm/integer_literal_suffix.x64.asm | 19 +-- .../integer_negate_shift_overflow.aarch64.asm | 19 --- .../asm/integer_negate_shift_overflow.x64.asm | 21 +-- .../asm/integer_ops_exhaustive.aarch64.asm | 106 ++++++------- .../asm/integer_ops_exhaustive.x64.asm | 106 ++++++------- .../asm/integer_suffixes.aarch64.asm | 35 ----- tests/snapshots/asm/integer_suffixes.x64.asm | 34 ++-- ...arge_int_literal_auto_promotes.aarch64.asm | 15 -- .../large_int_literal_auto_promotes.x64.asm | 16 -- .../asm/large_stack_frame.aarch64.asm | 7 - tests/snapshots/asm/large_stack_frame.x64.asm | 7 +- .../asm/libc_data_globals.aarch64.asm | 16 +- tests/snapshots/asm/libc_data_globals.x64.asm | 16 +- .../asm/libc_fileno_isblank.aarch64.asm | 5 - .../snapshots/asm/libc_fileno_isblank.x64.asm | 7 +- .../asm/libc_fp_classify.aarch64.asm | 2 - tests/snapshots/asm/libc_fp_classify.x64.asm | 3 - .../asm/libc_fp_return_value.aarch64.asm | 4 +- .../asm/libc_fp_return_value.x64.asm | 4 +- .../snapshots/asm/libc_int_arith.aarch64.asm | 15 -- tests/snapshots/asm/libc_int_arith.x64.asm | 17 +- .../asm/libc_math_fdim_scalbn.aarch64.asm | 6 +- .../asm/libc_math_fdim_scalbn.x64.asm | 4 - .../asm/libc_math_hyperbolic.aarch64.asm | 5 - .../asm/libc_math_hyperbolic.x64.asm | 7 +- .../snapshots/asm/libc_math_libm.aarch64.asm | 5 - tests/snapshots/asm/libc_math_libm.x64.asm | 6 - .../asm/libc_math_special.aarch64.asm | 5 - tests/snapshots/asm/libc_math_special.x64.asm | 7 +- tests/snapshots/asm/linked_list.aarch64.asm | 4 +- tests/snapshots/asm/linked_list.x64.asm | 4 +- .../local_struct_array_brace_init.aarch64.asm | 5 - .../asm/local_struct_array_brace_init.x64.asm | 7 +- .../asm/logical_not_float.aarch64.asm | 5 - tests/snapshots/asm/logical_not_float.x64.asm | 7 +- .../asm/logical_op_normalize.aarch64.asm | 20 --- .../asm/logical_op_normalize.x64.asm | 20 --- .../asm/long_double_libc_return.aarch64.asm | 10 +- .../asm/long_double_libc_return.x64.asm | 6 - .../snapshots/asm/lp64_predefine.aarch64.asm | 7 - tests/snapshots/asm/lp64_predefine.x64.asm | 8 - .../snapshots/asm/macro_operators.aarch64.asm | 20 +-- tests/snapshots/asm/macro_operators.x64.asm | 11 -- ...cro_paste_stringize_unexpanded.aarch64.asm | 13 -- .../macro_paste_stringize_unexpanded.x64.asm | 14 +- tests/snapshots/asm/many_fp_args.aarch64.asm | 4 - tests/snapshots/asm/many_fp_args.x64.asm | 8 +- .../asm/mem2reg_cross_block.aarch64.asm | 5 - .../snapshots/asm/mem2reg_cross_block.x64.asm | 6 - .../asm/mem2reg_i64_local.aarch64.asm | 5 - tests/snapshots/asm/mem2reg_i64_local.x64.asm | 6 - .../mem2reg_narrow_store_trunc.aarch64.asm | 5 - .../asm/mem2reg_narrow_store_trunc.x64.asm | 6 - .../asm/mem2reg_unsigned_narrow.aarch64.asm | 5 - .../asm/mem2reg_unsigned_narrow.x64.asm | 7 +- .../asm/mem2reg_value_across_call.aarch64.asm | 4 +- .../asm/mem2reg_value_across_call.x64.asm | 4 +- tests/snapshots/asm/memcpy_basic.aarch64.asm | 4 +- tests/snapshots/asm/memcpy_basic.x64.asm | 4 +- .../snapshots/asm/memcpy_oob_dst.aarch64.asm | 4 +- tests/snapshots/asm/memcpy_oob_dst.x64.asm | 4 +- .../snapshots/asm/memcpy_oob_src.aarch64.asm | 4 +- tests/snapshots/asm/memcpy_oob_src.x64.asm | 4 +- tests/snapshots/asm/memory_ops.aarch64.asm | 8 +- tests/snapshots/asm/memory_ops.x64.asm | 8 +- tests/snapshots/asm/memset_mcmp.aarch64.asm | 6 +- tests/snapshots/asm/memset_mcmp.x64.asm | 6 +- tests/snapshots/asm/memset_oob.aarch64.asm | 4 +- tests/snapshots/asm/memset_oob.x64.asm | 4 +- .../asm/mixed_signed_unsigned_div.aarch64.asm | 9 -- .../asm/mixed_signed_unsigned_div.x64.asm | 10 -- .../snapshots/asm/mmap_anonymous.aarch64.asm | 10 +- tests/snapshots/asm/mmap_anonymous.x64.asm | 10 +- tests/snapshots/asm/msvc_callconv.aarch64.asm | 4 +- tests/snapshots/asm/msvc_callconv.x64.asm | 4 +- .../asm/mul_pow2_to_shift.aarch64.asm | 4 +- tests/snapshots/asm/mul_pow2_to_shift.x64.asm | 4 +- .../asm/multichar_constant.aarch64.asm | 17 -- .../snapshots/asm/multichar_constant.x64.asm | 19 +-- .../asm/multidim_array_init.aarch64.asm | 27 ---- .../snapshots/asm/multidim_array_init.x64.asm | 28 +--- .../asm/natural_width_local.aarch64.asm | 5 - .../snapshots/asm/natural_width_local.x64.asm | 7 +- .../negative_float_in_array_init.aarch64.asm | 13 -- .../asm/negative_float_in_array_init.x64.asm | 14 -- .../asm/negative_size_memset.aarch64.asm | 4 +- .../asm/negative_size_memset.x64.asm | 4 +- ...ested_designator_string_member.aarch64.asm | 5 - .../nested_designator_string_member.x64.asm | 7 +- ...bject_macro_to_fn_macro_rescan.aarch64.asm | 4 +- .../object_macro_to_fn_macro_rescan.x64.asm | 4 +- tests/snapshots/asm/oob_read.aarch64.asm | 4 +- tests/snapshots/asm/oob_read.x64.asm | 3 +- .../param_fp_before_int_pressure.aarch64.asm | 5 - .../asm/param_fp_before_int_pressure.x64.asm | 6 - .../paren_string_char_array_init.aarch64.asm | 17 -- .../asm/paren_string_char_array_init.x64.asm | 18 +-- ...enthesized_function_declarator.aarch64.asm | 8 +- .../parenthesized_function_declarator.x64.asm | 8 +- .../asm/pointer_arithmetic.aarch64.asm | 4 +- .../snapshots/asm/pointer_arithmetic.x64.asm | 3 +- .../pointer_arithmetic_scaling.aarch64.asm | 5 - .../asm/pointer_arithmetic_scaling.x64.asm | 7 +- .../pointer_to_array_arithmetic.aarch64.asm | 19 --- .../asm/pointer_to_array_arithmetic.x64.asm | 20 --- .../snapshots/asm/pragma_operator.aarch64.asm | 11 -- tests/snapshots/asm/pragma_operator.x64.asm | 12 -- .../asm/predefined_macros.aarch64.asm | 23 --- tests/snapshots/asm/predefined_macros.x64.asm | 25 +-- .../preinc_narrow_lvalue_wraps.aarch64.asm | 29 +--- .../asm/preinc_narrow_lvalue_wraps.x64.asm | 31 +--- .../asm/pthread_key_once_width.aarch64.asm | 13 -- .../asm/pthread_key_once_width.x64.asm | 15 +- tests/snapshots/asm/queens.aarch64.asm | 9 -- tests/snapshots/asm/queens.x64.asm | 8 +- tests/snapshots/asm/quicksort.aarch64.asm | 14 +- tests/snapshots/asm/quicksort.x64.asm | 14 +- .../asm/return_callee_saved_value.aarch64.asm | 4 +- .../asm/return_callee_saved_value.x64.asm | 4 +- .../asm/return_void_expression.aarch64.asm | 2 - .../asm/return_void_expression.x64.asm | 3 +- .../asm/rotate_variable_count.aarch64.asm | 5 - .../asm/rotate_variable_count.x64.asm | 7 +- .../asm/scalar_brace_initializer.aarch64.asm | 19 --- .../asm/scalar_brace_initializer.x64.asm | 20 +-- .../snapshots/asm/setenv_then_get.aarch64.asm | 6 +- tests/snapshots/asm/setenv_then_get.x64.asm | 4 +- .../asm/setjmp_value_live_across.aarch64.asm | 8 +- .../asm/setjmp_value_live_across.x64.asm | 9 +- .../asm/setlocale_decimal_point.aarch64.asm | 10 +- .../asm/setlocale_decimal_point.x64.asm | 10 +- .../shift_result_promoted_type.aarch64.asm | 15 -- .../asm/shift_result_promoted_type.x64.asm | 16 -- .../shift_result_type_signedness.aarch64.asm | 15 -- .../asm/shift_result_type_signedness.x64.asm | 16 -- .../asm/sieve_of_eratosthenes.aarch64.asm | 5 - .../asm/sieve_of_eratosthenes.x64.asm | 6 - tests/snapshots/asm/signal_sig_t.aarch64.asm | 9 -- tests/snapshots/asm/signal_sig_t.x64.asm | 13 +- .../asm/size_t_is_unsigned.aarch64.asm | 13 -- .../snapshots/asm/size_t_is_unsigned.x64.asm | 15 +- ...izeof_function_call_truncation.aarch64.asm | 5 - .../sizeof_function_call_truncation.x64.asm | 6 - .../asm/sizeof_with_write.aarch64.asm | 4 +- tests/snapshots/asm/sizeof_with_write.x64.asm | 4 +- .../asm/slot_coalesce_declared.aarch64.asm | 10 -- .../asm/slot_coalesce_declared.x64.asm | 11 +- .../slot_coalesce_disjoint_temps.aarch64.asm | 5 - .../asm/slot_coalesce_disjoint_temps.x64.asm | 7 +- ...pill_slot_reuse_disjoint_calls.aarch64.asm | 4 +- .../spill_slot_reuse_disjoint_calls.x64.asm | 4 +- .../asm/ssa_c5_internal_fp_arg.aarch64.asm | 12 +- .../asm/ssa_c5_internal_fp_arg.x64.asm | 7 - .../asm/ssa_call_result_spill.aarch64.asm | 9 -- .../asm/ssa_call_result_spill.x64.asm | 8 +- .../asm/ssa_fp_compare_nan.aarch64.asm | 6 +- .../snapshots/asm/ssa_fp_compare_nan.x64.asm | 6 +- .../snapshots/asm/ssa_fp_routing.aarch64.asm | 5 - tests/snapshots/asm/ssa_fp_routing.x64.asm | 7 +- .../ssa_va_start_va_copy_aliasing.aarch64.asm | 8 +- .../asm/ssa_va_start_va_copy_aliasing.x64.asm | 4 - .../asm/static_assert_and_warning.aarch64.asm | 5 - .../asm/static_assert_and_warning.x64.asm | 6 - .../static_init_paren_relocation.aarch64.asm | 12 +- .../asm/static_init_paren_relocation.x64.asm | 12 +- .../static_init_struct_fp_call.aarch64.asm | 8 +- .../asm/static_init_struct_fp_call.x64.asm | 8 +- .../asm/static_inline_function.aarch64.asm | 5 - .../asm/static_inline_function.x64.asm | 6 - .../asm/static_linked_list.aarch64.asm | 7 - .../snapshots/asm/static_linked_list.x64.asm | 8 - .../asm/static_neg_infinity_init.aarch64.asm | 5 - .../asm/static_neg_infinity_init.x64.asm | 6 - ...dint_min_macros_type_and_value.aarch64.asm | 15 -- .../stdint_min_macros_type_and_value.x64.asm | 17 +- .../asm/store_to_load_forward.aarch64.asm | 9 +- .../asm/store_to_load_forward.x64.asm | 11 +- .../asm/stringize_whitespace.aarch64.asm | 5 - .../asm/stringize_whitespace.x64.asm | 7 +- .../asm/struct_array_designator.aarch64.asm | 11 -- .../asm/struct_array_designator.x64.asm | 12 +- tests/snapshots/asm/struct_basic.aarch64.asm | 4 +- tests/snapshots/asm/struct_basic.x64.asm | 3 - .../asm/struct_by_value_return.aarch64.asm | 5 - .../asm/struct_by_value_return.x64.asm | 6 - .../struct_field_assign_from_call.aarch64.asm | 16 +- .../asm/struct_field_assign_from_call.x64.asm | 16 +- ...struct_fn_ptr_field_deref_call.aarch64.asm | 12 +- .../struct_fn_ptr_field_deref_call.x64.asm | 12 +- .../asm/struct_initializers.aarch64.asm | 32 ++-- .../snapshots/asm/struct_initializers.x64.asm | 32 ++-- .../asm/struct_linked_list.aarch64.asm | 4 +- .../snapshots/asm/struct_linked_list.x64.asm | 4 +- ...ct_member_brace_wrapped_string.aarch64.asm | 5 - ...struct_member_brace_wrapped_string.x64.asm | 7 +- .../switch_case_label_promoted.aarch64.asm | 11 -- .../asm/switch_case_label_promoted.x64.asm | 12 -- .../asm/switch_default_routing.aarch64.asm | 5 - .../asm/switch_default_routing.x64.asm | 7 +- .../switch_goto_label_into_case.aarch64.asm | 13 -- .../asm/switch_goto_label_into_case.x64.asm | 14 +- ...switch_nested_case_in_compound.aarch64.asm | 8 +- .../switch_nested_case_in_compound.x64.asm | 8 +- .../asm/switch_statement.aarch64.asm | 5 - tests/snapshots/asm/switch_statement.x64.asm | 7 +- .../asm/sxtw_fold_source_liveness.aarch64.asm | 5 - .../asm/sxtw_fold_source_liveness.x64.asm | 6 - .../asm/sys_addr_zero_arg.aarch64.asm | 6 +- tests/snapshots/asm/sys_addr_zero_arg.x64.asm | 5 +- .../asm/sysconf_pagesize.aarch64.asm | 20 +-- tests/snapshots/asm/sysconf_pagesize.x64.asm | 20 +-- .../asm/syslimits_path_max.aarch64.asm | 7 - .../snapshots/asm/syslimits_path_max.x64.asm | 7 +- .../asm/sysv_variadic_host_abi.aarch64.asm | 4 - .../asm/sysv_variadic_host_abi.x64.asm | 8 +- .../asm/tail_call_args_from_spill.aarch64.asm | 10 +- .../asm/tail_call_args_from_spill.x64.asm | 10 +- .../tail_call_no_address_escape.aarch64.asm | 5 - .../asm/tail_call_no_address_escape.x64.asm | 6 - .../tentative_array_definition.aarch64.asm | 6 +- .../asm/tentative_array_definition.x64.asm | 6 +- ...entative_array_use_before_init.aarch64.asm | 10 +- .../tentative_array_use_before_init.x64.asm | 10 +- ...tentative_deferred_array_grows.aarch64.asm | 13 -- .../tentative_deferred_array_grows.x64.asm | 15 +- .../asm/ternary_arith_common_type.aarch64.asm | 13 -- .../asm/ternary_arith_common_type.x64.asm | 14 -- .../type_warning_silenced_by_cast.aarch64.asm | 5 - .../asm/type_warning_silenced_by_cast.x64.asm | 7 +- .../asm/typedef_array_outer_dim.aarch64.asm | 5 - .../asm/typedef_array_outer_dim.x64.asm | 4 +- .../asm/typedef_array_param_decay.aarch64.asm | 5 - .../asm/typedef_array_param_decay.x64.asm | 7 +- .../asm/typedef_in_function_body.aarch64.asm | 23 --- .../asm/typedef_in_function_body.x64.asm | 24 +-- .../snapshots/asm/uint64_to_float.aarch64.asm | 17 -- tests/snapshots/asm/uint64_to_float.x64.asm | 18 --- ..._minus_unsigned_int_truncation.aarch64.asm | 21 --- ...nary_minus_unsigned_int_truncation.x64.asm | 23 +-- ...ary_plus_init_and_param_shadow.aarch64.asm | 23 ++- .../unary_plus_init_and_param_shadow.x64.asm | 25 ++- .../asm/unary_plus_preserves_type.aarch64.asm | 11 -- .../asm/unary_plus_preserves_type.x64.asm | 12 -- .../asm/unsigned_arith_high_half.aarch64.asm | 11 -- .../asm/unsigned_arith_high_half.x64.asm | 13 +- .../asm/unsigned_char_array.aarch64.asm | 16 +- .../snapshots/asm/unsigned_char_array.x64.asm | 16 +- .../asm/unsigned_compare.aarch64.asm | 26 ++-- tests/snapshots/asm/unsigned_compare.x64.asm | 26 ++-- .../asm/unsigned_div_mod.aarch64.asm | 11 -- tests/snapshots/asm/unsigned_div_mod.x64.asm | 12 -- .../asm/unsigned_right_shift.aarch64.asm | 9 -- .../asm/unsigned_right_shift.x64.asm | 10 -- ...gned_signed_relational_compare.aarch64.asm | 21 --- ...unsigned_signed_relational_compare.x64.asm | 22 +-- .../snapshots/asm/use_after_free.aarch64.asm | 4 +- tests/snapshots/asm/use_after_free.x64.asm | 4 +- .../asm/va_arg_through_pointer.aarch64.asm | 5 - .../asm/va_arg_through_pointer.x64.asm | 7 +- .../asm/va_copy_under_pressure.aarch64.asm | 2 - .../asm/va_copy_under_pressure.x64.asm | 3 - .../asm/variable_shadowing.aarch64.asm | 5 - .../snapshots/asm/variable_shadowing.x64.asm | 6 - .../asm/variable_shift_rcx_loop.aarch64.asm | 7 - .../asm/variable_shift_rcx_loop.x64.asm | 9 -- .../asm/variadic_macro_named_rest.aarch64.asm | 5 - .../asm/variadic_macro_named_rest.x64.asm | 7 +- .../asm/variadic_sprintf.aarch64.asm | 8 +- tests/snapshots/asm/variadic_sprintf.x64.asm | 8 +- .../asm/variadic_via_fnptr.aarch64.asm | 10 +- .../snapshots/asm/variadic_via_fnptr.x64.asm | 6 - ...oid_function_produces_no_value.aarch64.asm | 15 +- .../void_function_produces_no_value.x64.asm | 16 +- .../snapshots/asm/warn_dead_store.aarch64.asm | 5 - tests/snapshots/asm/warn_dead_store.x64.asm | 6 - .../asm/warn_unused_symbols.aarch64.asm | 10 -- .../snapshots/asm/warn_unused_symbols.x64.asm | 11 -- .../snapshots/asm/wide_char_utf8.aarch64.asm | 23 --- tests/snapshots/asm/wide_char_utf8.x64.asm | 24 --- .../wide_string_literal_alignment.aarch64.asm | 10 +- .../asm/wide_string_literal_alignment.x64.asm | 10 +- .../asm/wide_string_literal_size.aarch64.asm | 23 --- .../asm/wide_string_literal_size.x64.asm | 24 --- tests/snapshots/asm/write_stdout.aarch64.asm | 4 +- tests/snapshots/asm/write_stdout.x64.asm | 4 +- .../asm/zero_length_array.aarch64.asm | 17 -- tests/snapshots/asm/zero_length_array.x64.asm | 18 --- .../asm/zero_sign_extension_32bit.aarch64.asm | 6 +- .../asm/zero_sign_extension_32bit.x64.asm | 6 +- .../ssa/dead_local_load_frame_elide.ssa | 147 ++++++++++++++++++ 524 files changed, 1461 insertions(+), 4599 deletions(-) create mode 100644 tests/fixtures/c/dead_local_load_frame_elide.c create mode 100644 tests/snapshots/asm/dead_local_load_frame_elide.aarch64.asm create mode 100644 tests/snapshots/asm/dead_local_load_frame_elide.x64.asm create mode 100644 tests/snapshots/ssa/dead_local_load_frame_elide.ssa diff --git a/src/c5/codegen/ssa/emit_common.rs b/src/c5/codegen/ssa/emit_common.rs index ab7375724..ae058f271 100644 --- a/src/c5/codegen/ssa/emit_common.rs +++ b/src/c5/codegen/ssa/emit_common.rs @@ -47,28 +47,53 @@ pub(crate) fn slots16(n_slots: u32) -> u32 { align16(n_slots * 8) } +/// True when the emitted form of `inst` addresses the locals region +/// (negative slot offset): slot loads / stores / address-takes, the +/// alloca-arena bookkeeping store, and a call gathering an aggregate +/// return into its result-temp slot. Purely structural; whether the +/// instruction is emitted at all is `is_dead_pure`'s decision, and the +/// frame gate below combines the two so it cannot disagree with the +/// per-inst emit skip. +fn inst_addresses_local(inst: &super::super::ir::Inst) -> bool { + use super::super::ir::Inst; + match inst { + Inst::LoadLocal { off, .. } | Inst::StoreLocal { off, .. } | Inst::LocalAddr(off) => { + *off < 0 + } + Inst::AllocaInit(slot) => *slot != 0, + Inst::Call { ret_slot_local, .. } + | Inst::CallIndirect { ret_slot_local, .. } + | Inst::CallExt { ret_slot_local, .. } => *ret_slot_local < 0, + _ => false, + } +} + /// The frame regions both targets size identically: the locals region, the /// allocator spill region, and the saved callee-GPR region, each a 16-byte -/// aligned byte count. The locals region is zero when no surviving instruction +/// aligned byte count. The locals region is zero when no emitted instruction /// references a user local (negative `off`); after mem2reg and dead-store /// elimination such an object is never observed and needs no storage -/// (C99 6.2.4p2). Param cells use non-negative `off` and are sized separately. +/// (C99 6.2.4p2). An instruction the per-inst dispatch skips as dead pure +/// (`is_dead_pure`) produces no machine code and therefore no access; the +/// same predicate gates both decisions. Param cells use non-negative `off` +/// and are sized separately. pub(crate) fn compute_frame_base( func: &super::super::ir::FunctionSsa, alloc: &super::reg_alloc::Allocation, ) -> (u32, u32, u32) { - use super::super::ir::Inst; let declared_locals_bytes = slots16(func.locals.max(0) as u32); - // A function returning an aggregate larger than 16 bytes saves the - // caller-supplied indirect-result pointer into its `indirect_result_slot` - // in the prologue and reads it on return; that slot is reached through a - // FunctionSsa field rather than an instruction, so it counts as a local - // access even when no LoadLocal / StoreLocal / LocalAddr references it. + // Two prologue paths reach the locals region through FunctionSsa fields + // rather than instructions and count as accesses on their own: saving + // the caller-supplied indirect-result pointer into `indirect_result_slot`, + // and scattering a by-value aggregate parameter into its body local. let any_local_access = func.indirect_result_slot < 0 - || func.insts.iter().any(|i| match i { - Inst::LoadLocal { off, .. } | Inst::StoreLocal { off, .. } => *off < 0, - Inst::LocalAddr(off) => *off < 0, - _ => false, + || func + .param_aggs + .iter() + .zip(func.param_local_slots.iter()) + .any(|(agg, slot)| agg.is_some() && *slot < 0) + || func.insts.iter().enumerate().any(|(idx, i)| { + inst_addresses_local(i) && !is_dead_pure(i, idx as super::super::ir::ValueId, alloc) }); let locals_bytes = if any_local_access { declared_locals_bytes diff --git a/src/c5/tests/jit.rs b/src/c5/tests/jit.rs index c273810ff..6e95020a9 100644 --- a/src/c5/tests/jit.rs +++ b/src/c5/tests/jit.rs @@ -1195,6 +1195,7 @@ const JIT_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native.rs b/src/c5/tests/native.rs index fb25793bf..9ca75fd58 100644 --- a/src/c5/tests/native.rs +++ b/src/c5/tests/native.rs @@ -473,6 +473,7 @@ const NATIVE_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_elf.rs b/src/c5/tests/native_elf.rs index de8f97ade..3b766813c 100644 --- a/src/c5/tests/native_elf.rs +++ b/src/c5/tests/native_elf.rs @@ -401,6 +401,7 @@ const NATIVE_ELF_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_elf_x64.rs b/src/c5/tests/native_elf_x64.rs index 1cea28fb9..dd39f1d81 100644 --- a/src/c5/tests/native_elf_x64.rs +++ b/src/c5/tests/native_elf_x64.rs @@ -354,6 +354,7 @@ const NATIVE_ELF_X64_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_pe_arm64.rs b/src/c5/tests/native_pe_arm64.rs index 576ba013d..2b2a048a6 100644 --- a/src/c5/tests/native_pe_arm64.rs +++ b/src/c5/tests/native_pe_arm64.rs @@ -682,6 +682,7 @@ const NATIVE_PE_ARM64_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/native_pe_x64.rs b/src/c5/tests/native_pe_x64.rs index 0baa31558..8ac6a9207 100644 --- a/src/c5/tests/native_pe_x64.rs +++ b/src/c5/tests/native_pe_x64.rs @@ -695,6 +695,7 @@ const NATIVE_PE_X64_FIXTURES: &[(&str, i32)] = &[ ("init_float_to_int.c", 0), ("global_init_midexpr_cast_narrow.c", 0), ("init_brace_intermediate_cast.c", 0), + ("dead_local_load_frame_elide.c", 0), ("ternary_arith_conversion.c", 0), ("struct_layout.c", 0), ("const_expr_conditional.c", 27), diff --git a/src/c5/tests/programs.rs b/src/c5/tests/programs.rs index 4fe326f2c..2334bbe29 100644 --- a/src/c5/tests/programs.rs +++ b/src/c5/tests/programs.rs @@ -2074,6 +2074,14 @@ fn init_brace_intermediate_cast() { assert_eq!(run_fixture("init_brace_intermediate_cast.c"), 0); } +#[test] +fn dead_local_load_frame_elide() { + // C99 6.2.4p2: a local that is never observed needs no storage. A + // promotion-orphaned slot load with no consumers emits no code and + // must not force a frame; a volatile access (5.1.2.3p2) keeps it. + assert_eq!(run_fixture("dead_local_load_frame_elide.c"), 0); +} + #[test] fn enum_tag_types() { // `enum Foo { ... };` registers a tag whose constants diff --git a/tests/fixtures/c/dead_local_load_frame_elide.c b/tests/fixtures/c/dead_local_load_frame_elide.c new file mode 100644 index 000000000..2f66b7420 --- /dev/null +++ b/tests/fixtures/c/dead_local_load_frame_elide.c @@ -0,0 +1,29 @@ +// A slot load with no consumers emits no machine code, so it must not +// force a frame: an object that is never observed needs no storage +// (C99 6.2.4p2), and the loop leaf below compiles without a prologue. +// A volatile slot access is itself observable behaviour (5.1.2.3p2 / +// 6.7.3p6), is always emitted, and keeps the frame. + +typedef unsigned char u8; +typedef unsigned long long u64; + +u64 fold(const u8 *x) { + u64 i, u = 0; + for (i = 0; i < 8; i++) u = (u << 8) | x[i]; + return u; +} + +long vol_keep(const u8 *x) { + volatile long u = x[0]; + u; + return 9; +} + +int main(void) { + u8 buf[8]; + u64 i; + for (i = 0; i < 8; i++) buf[i] = (u8)(i + 1); + if (fold(buf) != 0x0102030405060708ULL) return 1; + if (vol_keep(buf) != 9) return 2; + return 0; +} diff --git a/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm b/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm index 30bce799a..35f74dcd4 100644 --- a/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm +++ b/tests/snapshots/asm/aapcs64_variadic_host_abi.aarch64.asm @@ -534,7 +534,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x80 + sub sp, sp, #0x10 str x20, [sp] mov x20, #0x0 // =0 mov x0, #0x5 // =5 @@ -675,7 +675,7 @@ Disassembly of section .text: orr x20, x20, x17 sxtw x0, w20 ldr x20, [sp] - add sp, sp, #0x80 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm b/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm index 51d48992c..c68936ef3 100644 --- a/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm +++ b/tests/snapshots/asm/aapcs64_variadic_host_abi.x64.asm @@ -389,7 +389,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0xb0, %rsp + subq $0x40, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) movq %r13, 0x10(%rsp) @@ -562,7 +562,7 @@ Disassembly of section .text: movq 0x10(%rsp), %r13 movq 0x18(%rsp), %r14 movq 0x20(%rsp), %r15 - addq $0xb0, %rsp + addq $0x40, %rsp popq %rbp retq jmp diff --git a/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm b/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm index cb1b3934c..9625e958a 100644 --- a/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm +++ b/tests/snapshots/asm/addr_of_libc_strcmp.aarch64.asm @@ -12,7 +12,7 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x40 + sub sp, sp, #0x20 str x20, [sp] str x21, [sp, #0x8] str x19, [sp, #0x10] @@ -36,7 +36,7 @@ Disassembly of section .text: ldr x20, [sp] ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] - add sp, sp, #0x40 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -57,7 +57,7 @@ Disassembly of section .text: ldr x20, [sp] ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] - add sp, sp, #0x40 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -78,7 +78,7 @@ Disassembly of section .text: ldr x20, [sp] ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] - add sp, sp, #0x40 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -106,13 +106,13 @@ Disassembly of section .text: ldr x20, [sp] ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] - add sp, sp, #0x40 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 ldr x20, [sp] ldr x21, [sp, #0x8] ldr x19, [sp, #0x10] - add sp, sp, #0x40 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm b/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm index c771849c9..309bf34a5 100644 --- a/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm +++ b/tests/snapshots/asm/addr_of_libc_strcmp.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) leaq , %rbx # @@ -27,7 +27,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -40,7 +40,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -53,7 +53,7 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -72,13 +72,13 @@ Disassembly of section .text: movl $0x4, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/adjacent_strings.aarch64.asm b/tests/snapshots/asm/adjacent_strings.aarch64.asm index 87df0b531..4251a03a1 100644 --- a/tests/snapshots/asm/adjacent_strings.aarch64.asm +++ b/tests/snapshots/asm/adjacent_strings.aarch64.asm @@ -10,12 +10,7 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldrb w0, [x0, #0x5] - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/adjacent_strings.x64.asm b/tests/snapshots/asm/adjacent_strings.x64.asm index 20941618a..6d70fb491 100644 --- a/tests/snapshots/asm/adjacent_strings.x64.asm +++ b/tests/snapshots/asm/adjacent_strings.x64.asm @@ -11,11 +11,8 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movsbq 0x5(%rax), %rax - addq $0x10, %rsp - popq %rbp retq + addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/anon_union_init.aarch64.asm b/tests/snapshots/asm/anon_union_init.aarch64.asm index c6c30f7ae..7eebe97a9 100644 --- a/tests/snapshots/asm/anon_union_init.aarch64.asm +++ b/tests/snapshots/asm/anon_union_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 adrp x0, add x0, x0, ldrsw x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x3 @@ -36,8 +31,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0xc] cmp x1, #0x4 @@ -48,8 +41,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -82,12 +73,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/anon_union_init.x64.asm b/tests/snapshots/asm/anon_union_init.x64.asm index cd9fba5f5..108c5f71b 100644 --- a/tests/snapshots/asm/anon_union_init.x64.asm +++ b/tests/snapshots/asm/anon_union_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x1, %rcx @@ -28,8 +25,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx cmpq $0x3, %rcx @@ -44,8 +39,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movslq 0xc(%rax), %rcx cmpq $0x4, %rcx @@ -60,8 +53,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -100,12 +91,8 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq jmp jmp @@ -114,4 +101,3 @@ Disassembly of section .text: jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_2d_struct_init.aarch64.asm b/tests/snapshots/asm/array_2d_struct_init.aarch64.asm index 015cb4dde..0a3a26061 100644 --- a/tests/snapshots/asm/array_2d_struct_init.aarch64.asm +++ b/tests/snapshots/asm/array_2d_struct_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldr d0, [x0] @@ -45,8 +42,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -75,8 +70,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -106,12 +99,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_2d_struct_init.x64.asm b/tests/snapshots/asm/array_2d_struct_init.x64.asm index 8f6592cee..cd4e915ca 100644 --- a/tests/snapshots/asm/array_2d_struct_init.x64.asm +++ b/tests/snapshots/asm/array_2d_struct_init.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movsd (%rax,%riz), %xmm0 movl $0x1, %esi @@ -67,8 +64,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -110,8 +105,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movsd (%rax,%riz), %xmm0 @@ -154,12 +147,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -168,4 +157,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm b/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm index f88acfae7..fc71ab228 100644 --- a/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm +++ b/tests/snapshots/asm/array_compound_literal_static_init.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, ldr x1, [x0] @@ -20,8 +17,6 @@ Disassembly of section .text: cmp x1, #0x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0] ldr x1, [x1] @@ -32,16 +27,12 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x8] cmp x1, #0x2aa b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1] @@ -62,16 +53,12 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x18] cmp x1, #0x28b b.eq mov x0, #0x5 // =5 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1, #0x10] @@ -82,8 +69,6 @@ Disassembly of section .text: cmp x1, #0x0 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldrsw x1, [x1, #0x28] @@ -94,24 +79,18 @@ Disassembly of section .text: cmp x1, x17 b.eq mov x0, #0x7 // =7 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x8] ldr x1, [x1, #0x20] cmp x1, #0x0 b.eq mov x0, #0x8 // =8 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x10] ldrsw x1, [x1, #0x8] cmp x1, #0x7 b.eq mov x0, #0x9 // =9 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x1, [x0, #0x10] ldrsw x1, [x1, #0x18] @@ -124,20 +103,14 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0xa // =10 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldr x0, [x0, #0x10] ldrsw x0, [x0, #0x28] cmp x0, #0x0 b.eq mov x0, #0xb // =11 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_compound_literal_static_init.x64.asm b/tests/snapshots/asm/array_compound_literal_static_init.x64.asm index 60455cade..69ab257a1 100644 --- a/tests/snapshots/asm/array_compound_literal_static_init.x64.asm +++ b/tests/snapshots/asm/array_compound_literal_static_init.x64.asm @@ -11,17 +11,12 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax movq (%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movq (%rax), %rcx movq (%rcx), %rcx @@ -29,16 +24,12 @@ Disassembly of section .text: cmpq $0x61, %rcx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x2aa, %rcx # imm = 0x2AA je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq (%rcx), %rcx @@ -57,16 +48,12 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x18(%rcx), %rcx cmpq $0x28b, %rcx # imm = 0x28B je movl $0x5, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq 0x10(%rcx), %rcx @@ -74,32 +61,24 @@ Disassembly of section .text: cmpq $0x6e, %rcx je movl $0x6, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movslq 0x28(%rcx), %rcx cmpq $-0x1, %rcx je movl $0x7, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x8(%rax), %rcx movq 0x20(%rcx), %rcx testq %rcx, %rcx je movl $0x8, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rcx movslq 0x8(%rcx), %rcx cmpq $0x7, %rcx je movl $0x9, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rcx movslq 0x18(%rcx), %rcx @@ -116,22 +95,15 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0xa, %eax - addq $0x10, %rsp - popq %rbp retq movq 0x10(%rax), %rax movslq 0x28(%rax), %rax testq %rax, %rax je movl $0xb, %eax - addq $0x10, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp - popq %rbp retq jmp jmp addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm b/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm index 73c59c3fe..26ba82fc4 100644 --- a/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm +++ b/tests/snapshots/asm/array_of_struct_brace_elision.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x40 adrp x0, add x0, x0, ldr x1, [x0] @@ -24,8 +21,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x1 // =1 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -58,8 +53,6 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x2 // =2 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -92,12 +85,8 @@ Disassembly of section .text: cset x1, ne cbz x1, mov x0, #0x3 // =3 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x40 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm b/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm index 97bad7a6a..ee0e0b1bf 100644 --- a/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm +++ b/tests/snapshots/asm/array_of_struct_brace_elision.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x40, %rsp leaq , %rax movq (%rax), %rcx cmpq $0x1, %rcx @@ -28,8 +25,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x1, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -68,8 +63,6 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x2, %eax - addq $0x40, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax @@ -108,12 +101,8 @@ Disassembly of section .text: testq %rcx, %rcx je movl $0x3, %eax - addq $0x40, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x40, %rsp - popq %rbp retq jmp jmp @@ -122,4 +111,3 @@ Disassembly of section .text: jmp jmp jmp - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/array_range_designator.aarch64.asm b/tests/snapshots/asm/array_range_designator.aarch64.asm index fbd50faaf..af78027e3 100644 --- a/tests/snapshots/asm/array_range_designator.aarch64.asm +++ b/tests/snapshots/asm/array_range_designator.aarch64.asm @@ -10,31 +10,22 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 adrp x0, add x0, x0, ldrsw x1, [x0] cmp x1, #0x1 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x4] cmp x1, #0x2 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x8] cmp x1, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x10] cmp x1, #0x7 @@ -45,8 +36,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0xc] cmp x1, #0x0 @@ -57,8 +46,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0, #0x30] cmp x1, #0x9 @@ -69,12 +56,8 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret b b diff --git a/tests/snapshots/asm/array_range_designator.x64.asm b/tests/snapshots/asm/array_range_designator.x64.asm index f65c82e32..6747e1bc8 100644 --- a/tests/snapshots/asm/array_range_designator.x64.asm +++ b/tests/snapshots/asm/array_range_designator.x64.asm @@ -11,30 +11,21 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp leaq , %rax movslq (%rax), %rcx cmpq $0x1, %rcx je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x4(%rax), %rcx cmpq $0x2, %rcx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x8(%rax), %rcx testq %rcx, %rcx je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x10(%rax), %rcx cmpq $0x7, %rcx @@ -49,8 +40,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0xc(%rax), %rcx testq %rcx, %rcx @@ -65,8 +54,6 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq movslq 0x30(%rax), %rcx cmpq $0x9, %rcx @@ -81,12 +68,8 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq jmp jmp @@ -187,3 +170,4 @@ Disassembly of section .text: xorq %rax, %rax popq %rbp retq + addb %al, (%rax) diff --git a/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm b/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm index cdaf0b437..869d65a6b 100644 --- a/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm +++ b/tests/snapshots/asm/assign_expr_value_narrowed.aarch64.asm @@ -10,15 +10,10 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 mov x0, #0x3 // =3 cmp x0, #0x3 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xabcd // =43981 movk x0, #0xffff, lsl #16 @@ -30,15 +25,11 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xfd // =253 cmp x0, #0xfd b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x7788 // =30600 movk x0, #0x5566, lsl #16 @@ -51,10 +42,6 @@ Disassembly of section .text: cmp x0, #0x88 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm b/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm index f80411e61..50721490a 100644 --- a/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm +++ b/tests/snapshots/asm/assign_expr_value_narrowed.x64.asm @@ -11,15 +11,10 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movl $0x3, %eax cmpq $0x3, %rax je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movabsq $-0x5433, %rax # imm = 0xABCD movl %eax, %eax @@ -27,15 +22,11 @@ Disassembly of section .text: cmpq %r11, %rax je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movl $0xfd, %eax cmpq $0xfd, %rax je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movabsq $0x1122334455667788, %rax # imm = 0x1122334455667788 movswq %ax, %rax @@ -44,11 +35,7 @@ Disassembly of section .text: cmpq $0x88, %rax je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm b/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm index c1ab8d686..79f083a61 100644 --- a/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm +++ b/tests/snapshots/asm/atomic_operand_in_working_regs.aarch64.asm @@ -92,7 +92,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x50 mov x0, #0x1 // =1 mov x1, #0x2 // =2 mov x2, #0x3 // =3 @@ -108,6 +107,5 @@ Disassembly of section .text: b sxtw x1, w0 mov x0, x1 - add sp, sp, #0x50 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm b/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm index 2c8e49c7d..fdfd2ebb8 100644 --- a/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm +++ b/tests/snapshots/asm/atomic_operand_in_working_regs.x64.asm @@ -129,7 +129,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x60, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x1, %edi movl $0x2, %esi @@ -151,7 +151,7 @@ Disassembly of section .text: movslq %eax, %rcx movq (%rsp), %rbx movq %rcx, %rax - addq $0x60, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm b/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm index 58e9a3735..785470358 100644 --- a/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm +++ b/tests/snapshots/asm/auto_include_undeclared_libc.aarch64.asm @@ -12,7 +12,7 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x20 + sub sp, sp, #0x10 str x19, [sp] adrp x0, add x0, x0, @@ -25,6 +25,6 @@ Disassembly of section .text: mov x1, #0x1 // =1 mov x0, x1 ldr x19, [sp] - add sp, sp, #0x20 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm b/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm index 033c45d92..6eeb56d5e 100644 --- a/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm +++ b/tests/snapshots/asm/auto_include_undeclared_libc.x64.asm @@ -13,7 +13,6 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp leaq , %rdi movb $0x0, %al callq @@ -24,7 +23,7 @@ Disassembly of section .text: jmp movl $0x1, %ecx movq %rcx, %rax - addq $0x10, %rsp popq %rbp retq + addb %al, (%rax) addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/binary_integer_literal.aarch64.asm b/tests/snapshots/asm/binary_integer_literal.aarch64.asm index 6f600ebb2..c00258a47 100644 --- a/tests/snapshots/asm/binary_integer_literal.aarch64.asm +++ b/tests/snapshots/asm/binary_integer_literal.aarch64.asm @@ -10,22 +10,15 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x30 mov x0, #0xa // =10 cmp x0, #0xa b.eq mov x0, #0x1 // =1 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 cmp x0, #0x3 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xc0 // =192 mov x17, #0xc0 // =192 @@ -34,8 +27,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x3f // =63 mov x17, #0x3f // =63 @@ -44,8 +35,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0xffff // =65535 movk x0, #0xffff, lsl #16 @@ -58,8 +47,6 @@ Disassembly of section .text: cmp x0, x17 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 mov x17, #0x1 // =1 @@ -68,10 +55,6 @@ Disassembly of section .text: cmp x0, #0x0 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x30 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/binary_integer_literal.x64.asm b/tests/snapshots/asm/binary_integer_literal.x64.asm index 2dcd43714..bae5cb5fe 100644 --- a/tests/snapshots/asm/binary_integer_literal.x64.asm +++ b/tests/snapshots/asm/binary_integer_literal.x64.asm @@ -11,22 +11,15 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x30, %rsp movl $0xa, %eax cmpq $0xa, %rax je movl $0x1, %eax - addq $0x30, %rsp - popq %rbp retq movl $0x3, %eax cmpq $0x3, %rax je movl $0x2, %eax - addq $0x30, %rsp - popq %rbp retq movl $0xc0, %eax xorq $0xc0, %rax @@ -34,8 +27,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x3, %eax - addq $0x30, %rsp - popq %rbp retq movl $0x3f, %eax xorq $0x3f, %rax @@ -43,15 +34,11 @@ Disassembly of section .text: testq %rax, %rax je movl $0x4, %eax - addq $0x30, %rsp - popq %rbp retq movabsq $-0x1, %rax cmpq $-0x1, %rax je movl $0x5, %eax - addq $0x30, %rsp - popq %rbp retq movl $0x1, %eax xorq $0x1, %rax @@ -59,11 +46,6 @@ Disassembly of section .text: testq %rax, %rax je movl $0x6, %eax - addq $0x30, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x30, %rsp - popq %rbp retq - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/binary_search_tree.aarch64.asm b/tests/snapshots/asm/binary_search_tree.aarch64.asm index 77ffe5d12..a16fc6952 100644 --- a/tests/snapshots/asm/binary_search_tree.aarch64.asm +++ b/tests/snapshots/asm/binary_search_tree.aarch64.asm @@ -100,7 +100,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x30 + sub sp, sp, #0x10 str x20, [sp] str x21, [sp, #0x8] mov x0, #0x0 // =0 @@ -128,7 +128,7 @@ Disassembly of section .text: mov x0, #0x1 // =1 ldr x20, [sp] ldr x21, [sp, #0x8] - add sp, sp, #0x30 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x1, #0x28 // =40 @@ -139,7 +139,7 @@ Disassembly of section .text: mov x0, #0x2 // =2 ldr x20, [sp] ldr x21, [sp, #0x8] - add sp, sp, #0x30 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x1, #0x63 // =99 @@ -150,12 +150,12 @@ Disassembly of section .text: mov x0, #0x3 // =3 ldr x20, [sp] ldr x21, [sp, #0x8] - add sp, sp, #0x30 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 ldr x20, [sp] ldr x21, [sp, #0x8] - add sp, sp, #0x30 + add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/binary_search_tree.x64.asm b/tests/snapshots/asm/binary_search_tree.x64.asm index 7855a5c3f..2de0deb6f 100644 --- a/tests/snapshots/asm/binary_search_tree.x64.asm +++ b/tests/snapshots/asm/binary_search_tree.x64.asm @@ -97,7 +97,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x30, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movq %r12, 0x8(%rsp) xorq %rdi, %rdi @@ -125,7 +125,7 @@ Disassembly of section .text: movl $0x1, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x28, %esi @@ -136,7 +136,7 @@ Disassembly of section .text: movl $0x2, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x63, %esi @@ -147,13 +147,13 @@ Disassembly of section .text: movl $0x3, %eax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx movq 0x8(%rsp), %r12 - addq $0x30, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, (%rax) diff --git a/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm b/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm index 62ee42cff..5305bd1b1 100644 --- a/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm +++ b/tests/snapshots/asm/binop_imm_chain_fold.aarch64.asm @@ -12,7 +12,7 @@ Disassembly of section .text: brk #: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x80 + sub sp, sp, #0x20 str x20, [sp] str x19, [sp, #0x10] mov x0, #0xa // =10 @@ -50,6 +50,6 @@ Disassembly of section .text: mov x0, x1 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x80 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/binop_imm_chain_fold.x64.asm b/tests/snapshots/asm/binop_imm_chain_fold.x64.asm index f81ebfec4..6c110481b 100644 --- a/tests/snapshots/asm/binop_imm_chain_fold.x64.asm +++ b/tests/snapshots/asm/binop_imm_chain_fold.x64.asm @@ -13,7 +13,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x70, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0xa, %eax leaq 0x3(%rax), %rcx @@ -48,7 +48,7 @@ Disassembly of section .text: movl $0x1, %ecx movq (%rsp), %rbx movq %rcx, %rax - addq $0x70, %rsp + addq $0x10, %rsp popq %rbp retq addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitop_common_type.aarch64.asm b/tests/snapshots/asm/bitop_common_type.aarch64.asm index c13c33227..d8699ddf6 100644 --- a/tests/snapshots/asm/bitop_common_type.aarch64.asm +++ b/tests/snapshots/asm/bitop_common_type.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x0, #0xf000 // =61440 movk x0, #0x4006, lsl #16 movk x0, #0x1, lsl #32 @@ -25,8 +22,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mvn x2, x1 and x2, x0, x2 @@ -37,8 +32,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret eor x2, x0, x1 add x2, x2, #0x1 @@ -48,8 +41,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x2, #0xf001 // =61441 movk x2, #0x4006, lsl #16 @@ -64,8 +55,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret orr x2, x0, x1 mov x17, #0xf000 // =61440 @@ -74,8 +63,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret orr x2, x0, x1 mov x17, #0xf000 // =61440 @@ -84,8 +71,6 @@ Disassembly of section .text: cmp x2, x17 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret orr x0, x0, x1 mov x17, #0x100000000 // =4294967296 @@ -94,10 +79,6 @@ Disassembly of section .text: cmp x0, #0x0 b.ne mov x0, #0x7 // =7 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/bitop_common_type.x64.asm b/tests/snapshots/asm/bitop_common_type.x64.asm index ca37fb999..28a036672 100644 --- a/tests/snapshots/asm/bitop_common_type.x64.asm +++ b/tests/snapshots/asm/bitop_common_type.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movabsq $0x14006f000, %rax # imm = 0x14006F000 xorq %rcx, %rcx movq %rax, %rdx @@ -23,8 +20,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movq %rcx, %rdx xorq $-0x1, %rdx @@ -34,8 +29,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq movq %rax, %rdx xorq %rcx, %rdx @@ -44,8 +37,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq movabsq $0x14006f001, %rdx # imm = 0x14006F001 decq %rdx @@ -55,8 +46,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq movq %rax, %rdx orq %rcx, %rdx @@ -64,8 +53,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq movq %rax, %rdx orq %rcx, %rdx @@ -73,8 +60,6 @@ Disassembly of section .text: cmpq %r11, %rdx je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq orq %rcx, %rax movabsq $0x100000000, %r11 # imm = 0x100000000 @@ -84,11 +69,7 @@ Disassembly of section .text: testq %rax, %rax jne movl $0x7, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) + addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm b/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm index 514d31e53..183f5f418 100644 --- a/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm +++ b/tests/snapshots/asm/bitop_common_type_sign_extend.aarch64.asm @@ -34,9 +34,6 @@ Disassembly of section .text: ret : - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 ldrb w2, [x0] lsl x2, x2, #24 mov w2, w2 @@ -51,8 +48,6 @@ Disassembly of section .text: sxtw x0, w0 add x0, x1, x0 sub x0, x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret
: diff --git a/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm b/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm index 1d8abec55..f0f28501a 100644 --- a/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm +++ b/tests/snapshots/asm/bitop_common_type_sign_extend.x64.asm @@ -35,9 +35,6 @@ Disassembly of section .text: retq : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movzbq (%rdi), %rax shlq $0x18, %rax movl %eax, %eax @@ -52,8 +49,6 @@ Disassembly of section .text: movslq %eax, %rax addq %rsi, %rax subq %rsi, %rax - addq $0x10, %rsp - popq %rbp retq
: @@ -144,4 +139,3 @@ Disassembly of section .text: popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm b/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm index aaef702e5..ef46cf3d4 100644 --- a/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm +++ b/tests/snapshots/asm/block_extern_shadows_local.aarch64.asm @@ -10,17 +10,12 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x0, #0x9 // =9 adrp x1, add x1, x1, ldrsw x1, [x1] add x0, x1, x0 sxtw x0, w0 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret : @@ -32,15 +27,10 @@ Disassembly of section .text: ret
: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x20 mov x0, #0x5 // =5 cmp x0, #0x5 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x5 // =5 mov x1, #0x0 // =0 @@ -55,14 +45,10 @@ Disassembly of section .text: cmp x1, #0x69 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret cmp x0, #0x5 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -70,8 +56,6 @@ Disassembly of section .text: cmp x0, #0x7 b.eq mov x0, #0x4 // =4 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x9 // =9 adrp x1, @@ -82,8 +66,6 @@ Disassembly of section .text: cmp x0, #0x40 b.eq mov x0, #0x5 // =5 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x3 // =3 adrp x1, @@ -94,10 +76,6 @@ Disassembly of section .text: cmp x0, #0x50 b.eq mov x0, #0x6 // =6 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x20 - ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/block_extern_shadows_local.x64.asm b/tests/snapshots/asm/block_extern_shadows_local.x64.asm index 6a9271b49..c33b9c0a6 100644 --- a/tests/snapshots/asm/block_extern_shadows_local.x64.asm +++ b/tests/snapshots/asm/block_extern_shadows_local.x64.asm @@ -11,16 +11,11 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movl $0x9, %eax leaq , %rcx movslq (%rcx), %rcx addq %rcx, %rax movslq %eax, %rax - addq $0x10, %rsp - popq %rbp retq : @@ -31,15 +26,10 @@ Disassembly of section .text: retq
: - pushq %rbp - movq %rsp, %rbp - subq $0x20, %rsp movl $0x5, %eax cmpq $0x5, %rax je movl $0x1, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x5, %eax xorq %rcx, %rcx @@ -53,22 +43,16 @@ Disassembly of section .text: cmpq $0x69, %rcx je movl $0x2, %eax - addq $0x20, %rsp - popq %rbp retq cmpq $0x5, %rax je movl $0x3, %eax - addq $0x20, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x7, %rax je movl $0x4, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x9, %eax leaq , %rcx @@ -78,8 +62,6 @@ Disassembly of section .text: cmpq $0x40, %rax je movl $0x5, %eax - addq $0x20, %rsp - popq %rbp retq movl $0x3, %eax leaq , %rcx @@ -89,11 +71,6 @@ Disassembly of section .text: cmpq $0x50, %rax je movl $0x6, %eax - addq $0x20, %rsp - popq %rbp retq xorq %rax, %rax - addq $0x20, %rsp - popq %rbp retq - addb %al, (%rax) diff --git a/tests/snapshots/asm/block_scope_extern.aarch64.asm b/tests/snapshots/asm/block_scope_extern.aarch64.asm index 929015418..711ed7551 100644 --- a/tests/snapshots/asm/block_scope_extern.aarch64.asm +++ b/tests/snapshots/asm/block_scope_extern.aarch64.asm @@ -10,16 +10,11 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 adrp x0, add x0, x0, cmp x0, #0x0 b.ne mov x0, #0x1 // =1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0] cmp x1, #0x3 @@ -30,8 +25,6 @@ Disassembly of section .text: cset x2, ne cbz x2, mov x0, #0x2 // =2 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -39,8 +32,6 @@ Disassembly of section .text: cmp x0, #0x5 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -53,8 +44,6 @@ Disassembly of section .text: cmp x0, #0x3c b.eq mov x0, #0x4 // =4 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret adrp x0, add x0, x0, @@ -67,7 +56,5 @@ Disassembly of section .text: b mov x1, #0x5 // =5 mov x0, x1 - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/block_scope_extern.x64.asm b/tests/snapshots/asm/block_scope_extern.x64.asm index 8bfd7dfad..d252e3027 100644 --- a/tests/snapshots/asm/block_scope_extern.x64.asm +++ b/tests/snapshots/asm/block_scope_extern.x64.asm @@ -11,15 +11,10 @@ Disassembly of section .text: ud2
: - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp leaq , %rax testq %rax, %rax jne movl $0x1, %eax - addq $0x10, %rsp - popq %rbp retq movslq (%rax), %rcx cmpq $0x3, %rcx @@ -34,16 +29,12 @@ Disassembly of section .text: testq %rdx, %rdx je movl $0x2, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rax cmpq $0x5, %rax je movl $0x3, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movslq (%rax), %rcx @@ -55,8 +46,6 @@ Disassembly of section .text: cmpq $0x3c, %rax je movl $0x4, %eax - addq $0x10, %rsp - popq %rbp retq leaq , %rax movl $0x9, %ecx @@ -68,8 +57,5 @@ Disassembly of section .text: jmp movl $0x5, %ecx movq %rcx, %rax - addq $0x10, %rsp - popq %rbp retq jmp - addb %al, (%rax) diff --git a/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm b/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm index 44cdcacc9..85f4329ec 100644 --- a/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm +++ b/tests/snapshots/asm/block_scope_extern_forward_ref.aarch64.asm @@ -24,7 +24,6 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x10 bl adrp x0, add x0, x0, @@ -32,23 +31,19 @@ Disassembly of section .text: cmp x1, #0x5 b.eq mov x0, #0x1 // =1 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret ldrsw x1, [x0] cmp x1, #0x5 b.eq mov x0, #0x2 // =2 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret cmp x0, x0 b.eq mov x0, #0x3 // =3 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 - add sp, sp, #0x10 ldp x29, x30, [sp], #0x10 ret diff --git a/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm b/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm index c6ced4395..a7192074a 100644 --- a/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm +++ b/tests/snapshots/asm/block_scope_extern_forward_ref.x64.asm @@ -24,32 +24,26 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x10, %rsp callq leaq , %rax movslq (%rax), %rcx cmpq $0x5, %rcx je movl $0x1, %eax - addq $0x10, %rsp popq %rbp retq movslq (%rax), %rcx cmpq $0x5, %rcx je movl $0x2, %eax - addq $0x10, %rsp popq %rbp retq cmpq %rax, %rax je movl $0x3, %eax - addq $0x10, %rsp popq %rbp retq xorq %rax, %rax - addq $0x10, %rsp popq %rbp retq addb %al, (%rax) - addb %al, 0x41(%rdx) diff --git a/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm b/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm index 3195cdf18..2dd5644fe 100644 --- a/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm +++ b/tests/snapshots/asm/block_scope_function_declaration.aarch64.asm @@ -10,9 +10,6 @@ Disassembly of section .text: movk x1, #0x0, lsl #16 b brk #: - stp x29, x30, [sp, #-0x10]! - mov x29, sp - sub sp, sp, #0x10 mov x2, x0 ldrb w3, [x2] cbz x3, @@ -24,8 +21,6 @@ Disassembly of section .text: ldrb w1, [x1] cmp x0, x1 cset x0, eq - add sp, sp, #0x10 - ldp x29, x30, [sp], #0x10 ret ldrb w0, [x2] ldrb w3, [x1] @@ -38,7 +33,7 @@ Disassembly of section .text:
: stp x29, x30, [sp, #-0x10]! mov x29, sp - sub sp, sp, #0x50 + sub sp, sp, #0x20 str x20, [sp] str x19, [sp, #0x10] mov x0, #0x28 // =40 @@ -50,7 +45,7 @@ Disassembly of section .text: mov x0, #0x1 // =1 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -63,7 +58,7 @@ Disassembly of section .text: mov x0, #0x2 // =2 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x1 // =1 @@ -84,7 +79,7 @@ Disassembly of section .text: mov x0, #0x3 // =3 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret adrp x0, @@ -96,7 +91,7 @@ Disassembly of section .text: mov x0, #0x4 // =4 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x5 // =5 @@ -115,7 +110,7 @@ Disassembly of section .text: mov x0, #0x5 // =5 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x7 // =7 @@ -124,13 +119,13 @@ Disassembly of section .text: mov x0, #0x6 // =6 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret mov x0, #0x0 // =0 ldr x20, [sp] ldr x19, [sp, #0x10] - add sp, sp, #0x50 + add sp, sp, #0x20 ldp x29, x30, [sp], #0x10 ret b diff --git a/tests/snapshots/asm/block_scope_function_declaration.x64.asm b/tests/snapshots/asm/block_scope_function_declaration.x64.asm index 3c34a5e30..8056f0944 100644 --- a/tests/snapshots/asm/block_scope_function_declaration.x64.asm +++ b/tests/snapshots/asm/block_scope_function_declaration.x64.asm @@ -11,9 +11,6 @@ Disassembly of section .text: ud2 : - pushq %rbp - movq %rsp, %rbp - subq $0x10, %rsp movsbq (%rdi), %rcx testq %rcx, %rcx je @@ -26,8 +23,6 @@ Disassembly of section .text: cmpq %rcx, %rax sete %al movzbq %al, %rax - addq $0x10, %rsp - popq %rbp retq movsbq (%rdi), %rax movsbq (%rsi), %rcx @@ -42,7 +37,7 @@ Disassembly of section .text:
: pushq %rbp movq %rsp, %rbp - subq $0x40, %rsp + subq $0x10, %rsp movq %rbx, (%rsp) movl $0x28, %eax movl $0x2, %ecx @@ -52,7 +47,7 @@ Disassembly of section .text: je movl $0x1, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -62,7 +57,7 @@ Disassembly of section .text: jne movl $0x2, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x1, %eax @@ -84,7 +79,7 @@ Disassembly of section .text: je movl $0x3, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq leaq , %rdi @@ -95,7 +90,7 @@ Disassembly of section .text: je movl $0x4, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x5, %eax @@ -117,7 +112,7 @@ Disassembly of section .text: je movl $0x5, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq movl $0x7, %eax @@ -125,12 +120,12 @@ Disassembly of section .text: je movl $0x6, %eax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq xorq %rax, %rax movq (%rsp), %rbx - addq $0x40, %rsp + addq $0x10, %rsp popq %rbp retq jmp @@ -150,3 +145,5 @@ Disassembly of section .text: