From e713aec906edb8431851393069c7a29f97e23963 Mon Sep 17 00:00:00 2001 From: GitHub Actions Date: Sun, 17 Aug 2025 01:20:39 +0000 Subject: [PATCH] Auto PR: Differences detected --- catalog/list.json | 97 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/catalog/list.json b/catalog/list.json index e4247b6..c5de56a 100644 --- a/catalog/list.json +++ b/catalog/list.json @@ -1,5 +1,5 @@ { - "num": 173, + "num": 178, "designs": [ { "id": "763954", @@ -4811,6 +4811,101 @@ "Q_GITHUB_RELEASE": "24.3-1", "Q_VALIDATED": true }, + { + "id": "-", + "title": "a5ed065es-premium-devkit-oobe-legacy-baseline", + "source": "GitHub", + "family": "Agilex 5 E-Series", + "quartus_version": "25.1.1", + "patch_number": "Unknown", + "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1", + "device_part": "A5ED013BB32AE5S", + "description": "This is the baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.", + "rich_description": "

Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the Agilex 5 E-Series Premium Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n- Hard Processor System (HPS) enablement and configuration\n - Enable dual core Arm Cortex-A76 processor\n - Enable dual core Arm Cortex-A55 processor\n - HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n - HPS Clock and Reset\n - HPS FPGA Bridge and Interrupt\n- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n- System integration with FPGA IPs\n - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n - 256KB of FPGA On-Chip Memory

USB modes

This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.

The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".

| dr_mode value | Equivalent USB mode |\n| :-- | :-- |\n| host | Host |\n| peripheral | Device |

", + "category": "Golden Hardware Reference Design (GHRD)", + "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd", + "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-baseline.zip", + "documentations": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/281369322", + "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR", + "Q_VALIDATED": true + }, + { + "id": "-", + "title": "a5ed065es-premium-devkit-oobe-legacy-tsn-cfg2", + "source": "GitHub", + "family": "Agilex 5 E-Series", + "quartus_version": "25.1.1", + "patch_number": "Unknown", + "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1", + "device_part": "A5ED065BB32AE6SR0", + "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.", + "rich_description": "

Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the Agilex 5 E-Series Premium Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n- Hard Processor System (HPS) enablement and configuration\n - Enable dual core Arm Cortex-A76 processor\n - Enable dual core Arm Cortex-A55 processor\n - HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)\n - HPS Clock and Reset\n - HPS FPGA Bridge and Interrupt\n- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n- System integration with FPGA IPs\n - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n - 256KB of FPGA On-Chip Memory

USB modes

This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.

The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".

| dr_mode value | Equivalent USB mode |\n| :-- | :-- |\n| host | Host |\n| peripheral | Device |

Advanced feature

", + "category": "Golden Hardware Reference Design (GHRD)", + "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd", + "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-tsn-cfg2.zip", + "documentations": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/281369330", + "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR", + "Q_VALIDATED": true + }, + { + "id": "-", + "title": "a5ed065es-modular-devkit-som-legacy-baseline", + "source": "GitHub", + "family": "Agilex 5 E-Series", + "quartus_version": "25.1.1", + "patch_number": "Unknown", + "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1", + "device_part": "A5ED065BB32AE6SR0", + "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Modular Development Kit.", + "rich_description": "

Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the Agilex 5 E-Series Modular Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n- Hard Processor System (HPS) enablement and configuration\n - Enable dual core Arm Cortex-A76 processor\n - Enable dual core Arm Cortex-A55 processor\n - HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO) - HPS Clock and Reset\n - HPS FPGA Bridge and Interrupt\n- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n- System integration with FPGA IPs\n - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n - 256KB of FPGA On-Chip Memory

", + "category": "Golden Hardware Reference Design (GHRD)", + "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd", + "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip", + "documentations": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/281369271", + "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR", + "Q_VALIDATED": true + }, + { + "id": "-", + "title": "a5ed065es-premium-devkit-debug2-legacy-baseline", + "source": "GitHub", + "family": "Agilex 5 E-Series", + "quartus_version": "25.1.1", + "patch_number": "Unknown", + "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1", + "device_part": "A5ED065BB32AE6SR0", + "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.", + "rich_description": "

Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the Agilex 5 E-Series Premium Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n- Hard Processor System (HPS) enablement and configuration\n - Enable dual core Arm Cortex-A76 processor\n - Enable dual core Arm Cortex-A55 processor\n - HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)\n - HPS Clock and Reset\n - HPS FPGA Bridge and Interrupt\n- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n- System integration with FPGA IPs\n - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n - 256KB of FPGA On-Chip Memory

", + "category": "Golden Hardware Reference Design (GHRD)", + "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd", + "downloadUrl": "a5ed065es-premium-devkit-debug2-legacy-baseline.zip", + "documentations": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/281369312", + "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR", + "Q_VALIDATED": true + }, + { + "id": "-", + "title": "a5ed065es-premium-devkit-emmc-legacy-baseline", + "source": "GitHub", + "family": "Agilex 5 E-Series", + "quartus_version": "25.1.1", + "patch_number": "Unknown", + "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1", + "device_part": "A5ED065BB32AE6SR0", + "description": "Baseline Golden Hardware Reference Design (GHRD) for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.", + "rich_description": "

Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.

The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the Agilex 5 E-Series Premium Development Kit GSRD for information about GSRD.

The design uses HPS First configuration mode.

Baseline feature

This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:\n- Hard Processor System (HPS) enablement and configuration\n - Enable dual core Arm Cortex-A76 processor\n - Enable dual core Arm Cortex-A55 processor\n - Hard Processor System enablement and configuration\n - HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)\n - HPS Clock and Reset\n - HPS FPGA Bridge and Interrupt\n- HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)\n- System integration with FPGA IPs\n - Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs\n - Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG\n - 256KB of FPGA On-Chip Memory

", + "category": "Golden Hardware Reference Design (GHRD)", + "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd", + "downloadUrl": "a5ed065es-premium-devkit-emmc-legacy-baseline.zip", + "documentations": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/281369316", + "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR", + "Q_VALIDATED": true + }, { "id": "-", "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",