diff --git a/catalog/list.json b/catalog/list.json
index e4247b6..812e153 100644
--- a/catalog/list.json
+++ b/catalog/list.json
@@ -1,5 +1,5 @@
 {
-    "num": 173,
+    "num": 184,
     "designs": [
         {
             "id": "763954",
@@ -4522,6 +4522,120 @@
             "Q_GITHUB_RELEASE": "24.3.0-v1.0",
             "Q_VALIDATED": true
         },
+        {
+            "id": "-",
+            "title": "Nios® V/c Helloworld OCM Memory Test Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "rich_description": "<p>Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md",
+            "downloadUrl": "agilex5_niosv_c_helloworld_ocm_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/290020590",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 5 FPGA - Hello World on Nios® V/g Processor Design Example",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "Nios® V/g Processor-based Helloworld example design on the Agilex® 5 FPGA.",
+            "rich_description": "<p>Nios® V/g Processor-based Helloworld example design on the Agilex® 5 FPGA E-Series 065B Premium Development Kit (ES1) DKA5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_g/niosv_g_helloworld/img/hello_world.png\"/></p>",
+            "category": "Helloworld",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_g/niosv_g_helloworld/img/block_diagram.png",
+            "downloadUrl": "agilex5_niosv_g_helloworld.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/289537233",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/g Processor-based OCM test example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "Agilex 5 FPGA - OCM Memory test example design on Nios® V/g Processor",
+            "rich_description": "<p>Nios® V/g Processor-based OCM test example design on the Agilex® 5 FPGA E-Series 065B Premium Development Kit (ES1) DKA5E065BB32AES1</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_g/niosv_g_ocm_mem_test/img/hello_world_ocm.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_g/niosv_g_ocm_mem_test/docs/Nios_Vg_Processor_OCM_Mem_Test_Design_on_Agilex_5_FPGA.md",
+            "downloadUrl": "agilex5_niosv_g_ocm_mem_test.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/289537677",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m DMA OCM Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design demonstrates the transaction between the Nios® V processor with DMA and OCM core for the AgilexTM 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1.",
+            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_m/niosv_m_dma_ocm/img/dma_ocm.png\"/></p>",
+            "category": "Memory",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_dma_ocm/docs/NiosV_m_Processor_DMA_OCM_Design_on_Agilex_5_FPGA.md",
+            "downloadUrl": "agilex5_niosv_m_dma_ocm.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/289538652",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex 5 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA ESeries 065B Premium Development Kit DKA5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 5 FPGA.",
+            "rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
+            "category": "Machine Learning",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_g/tinyml_liteRT",
+            "downloadUrl": "agilex5_niosv_g_tinyml_liteRT.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/289537999",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Nios® V/m Baseline Golden Hardware Reference Design (GHRD)",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios® V/m processor with basic bare minimum peripherals required for any application execution for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.",
+            "rich_description": "<p>This example design includes a Nios® V/m processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5e-nios-ed/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd/img/baseling_ghrd_block_design.png\"/></p>",
+            "category": "GHRD",
+            "url": "https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_baseline_ghrd",
+            "downloadUrl": "agilex5_niosv_m_baseline_ghrd.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-nios-ed/releases/assets/289538499",
+            "Q_GITHUB_RELEASE": "25.1.1-v1.0",
+            "Q_VALIDATED": true
+        },
         {
             "id": "-",
             "title": "Agilex 5 FPGA- Nios V/c Helloworld OCM Memory test Design",
@@ -4811,6 +4925,146 @@
             "Q_GITHUB_RELEASE": "24.3-1",
             "Q_VALIDATED": true
         },
+        {
+            "id": "-",
+            "title": "HPS Baseline System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
+            "source": "GitHub",
+            "family": "Agilex 5 E-Series",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
+            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\" ><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table>",
+            "category": "HPS",
+            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
+            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-baseline.zip",
+            "documentations": [
+                {
+                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
+                },
+                {
+                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-baseline/README.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/286681677",
+            "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
+            "source": "GitHub",
+            "family": "Agilex 5 E-Series",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with Out of Box Experience (OOBE) daughter card, which is also known as HPS Enablement Expansion Board.",
+            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I3C, JTAG, UART, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul><h3>USB modes</h3><p>This design supports USB 3.1 in both host and device mode.\nOnce power up, the USB mode will remain and cannot be changed during runtime.</p><p>The linux device tree (dts) needs to be configured.\nThe dts can be set with \"dr_mode\".</p><table border=\"1\" cellpadding=\"10\"><tr><th>dr_mode value</th><th>Equivalent USB mode</th></tr><tr><td>host</td><td>Host</td></tr><tr><td>peripheral</td><td>Device</td></tr></table><h2>Advanced feature</h2><p>FPGA RGMII subsystem that consists of GMII-to-RGMII conversion for HPS XGMAC into FPGA IO connection</p>",
+            "category": "HPS",
+            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
+            "downloadUrl": "a5ed065es-premium-devkit-oobe-legacy-tsn-cfg2.zip",
+            "documentations": [
+                {
+                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
+                },
+                {
+                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-oobe/legacy-tsn-cfg2/README.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/286681680",
+            "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "HPS Baseline System Example Design with eMMC Boot for Agilex 5 FPGA E-Series 065B Premium Development Kit",
+            "source": "GitHub",
+            "family": "Agilex 5 E-Series",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS NAND Board. This board also offers eMMC.",
+            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>Hard Processor System enablement and configuration</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I2C, I3C, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
+            "category": "HPS",
+            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
+            "downloadUrl": "a5ed065es-premium-devkit-emmc-legacy-baseline.zip",
+            "documentations": [
+                {
+                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
+                },
+                {
+                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-emmc/legacy-baseline/README.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/286681675",
+            "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "HPS Baseline System Example Design with HPS Test Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",
+            "source": "GitHub",
+            "family": "Agilex 5 E-Series",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Premium Development Kit with HPS Test Board.",
+            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/\">Agilex 5 E-Series Premium Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, SPI, MDIO, I3C, JTAG, UART, TRACE, and GPIO)</li><li>HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
+            "category": "HPS",
+            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
+            "downloadUrl": "a5ed065es-premium-devkit-debug2-legacy-baseline.zip",
+            "documentations": [
+                {
+                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/"
+                },
+                {
+                    "title": "GHRD README for the Agilex 5 E-Series Premium Development Kit",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-premium-devkit-debug2/legacy-baseline/README.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/286681657",
+            "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "HPS Baseline System Example Design for Modular Development Kit for Agilex 5 FPGA E-Series 065B Modular Development Kit",
+            "source": "GitHub",
+            "family": "Agilex 5 E-Series",
+            "quartus_version": "25.1.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "HPS Baseline System Example Design for Agilex 5 FPGA E-Series 065B Modular Development Kit.",
+            "rich_description": "<p>Agilex 5 GHRD is a reference design for Intel Agilex 5 System On Chip (SoC) FPGA.</p><p>The GHRD is part of the Golden System Reference Design (GSRD), which provides a complete solution, including exercising soft IP in the fabric, booting to U-Boot, then Linux, and running sample Linux applications.\nRefer to the <a href=\"https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/\">Agilex 5 E-Series Modular Development Kit GSRD</a> for information about GSRD.</p><p>The design uses HPS First configuration mode.</p><h2>Baseline feature</h2><p>This reference design demonstrates the following system integration between Hard Processor System (HPS) and FPGA IPs:</p><ul><li>Hard Processor System (HPS) enablement and configuration</li><li>Enable dual core Arm Cortex-A76 processor</li><li>Enable dual core Arm Cortex-A55 processor</li><li>HPS Peripheral and I/O (SD/MMC, EMAC, MDIO, USB, I2C, JTAG, UART, and GPIO)  - HPS Clock and Reset</li><li>HPS FPGA Bridge and Interrupt</li><li>HPS EMIF configuration (starting 25.1.1 ECC is enabled by default)</li><li>System integration with FPGA IPs</li><li>Peripheral subsystem that consists of System ID, Programmable I/O (PIO) IP for controlling DIPSW, PushButton, and LEDs</li><li>Debug subsystem that consists of JTAG-to-Avalon Master IP to allow System-Console debug activity and FPGA content access through JTAG</li><li>256KB of FPGA On-Chip Memory</li></ul>",
+            "category": "HPS",
+            "url": "https://www.github.com/altera-fpga/agilex5e-ed-gsrd",
+            "downloadUrl": "a5ed065es-modular-devkit-som-legacy-baseline.zip",
+            "documentations": [
+                {
+                    "title": "HPS GSRD User Guide for the Agilex 5 E-Series Modular Development Kit",
+                    "downloadUrl": "https://altera-fpga.github.io/latest/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/"
+                },
+                {
+                    "title": "GHRD README for the Agilex 5 E-Series Modular Development Kit",
+                    "downloadUrl": "https://github.com/altera-fpga/agilex5e-ed-gsrd/blob/main/a5ed065es-modular-devkit-som/legacy-baseline/README.md"
+                }
+            ],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5e-ed-gsrd/releases/assets/286681685",
+            "Q_GITHUB_RELEASE": "QPDS25.1.1_REL_GSRD_PR",
+            "Q_VALIDATED": true
+        },
         {
             "id": "-",
             "title": "HPS Time-Sensitive Network (RGMII from HVIO) System Example Design with HPS Expansion Board for Agilex 5 FPGA E-Series 065B Premium Development Kit",